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-rw-r--r--llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp6
-rw-r--r--llvm/utils/TableGen/Common/CodeGenRegisters.cpp21
-rw-r--r--llvm/utils/TableGen/Common/CodeGenRegisters.h2
-rw-r--r--llvm/utils/TableGen/Common/InfoByHwMode.cpp8
-rw-r--r--llvm/utils/TableGen/Common/PredicateExpander.cpp4
-rw-r--r--llvm/utils/TableGen/DXILEmitter.cpp22
-rw-r--r--llvm/utils/TableGen/DecoderEmitter.cpp4
-rw-r--r--llvm/utils/TableGen/ExegesisEmitter.cpp22
-rw-r--r--llvm/utils/TableGen/FastISelEmitter.cpp6
-rw-r--r--llvm/utils/TableGen/RegisterInfoEmitter.cpp3
-rw-r--r--llvm/utils/TableGen/SubtargetEmitter.cpp10
-rw-r--r--llvm/utils/TableGen/X86DisassemblerShared.h4
-rw-r--r--llvm/utils/TableGen/X86FoldTablesEmitter.cpp18
-rw-r--r--llvm/utils/TableGen/X86InstrMappingEmitter.cpp4
-rw-r--r--llvm/utils/TableGen/X86MnemonicTables.cpp3
-rw-r--r--llvm/utils/TableGen/X86ModRMFilters.h8
-rw-r--r--llvm/utils/TableGen/X86RecognizableInstr.h4
17 files changed, 68 insertions, 81 deletions
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index 75bea77..8076ce2 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -246,16 +246,14 @@ bool TypeSetByHwMode::operator==(const TypeSetByHwMode &VTS) const {
return true;
}
-namespace llvm {
-raw_ostream &operator<<(raw_ostream &OS, const MachineValueTypeSet &T) {
+raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineValueTypeSet &T) {
T.writeToStream(OS);
return OS;
}
-raw_ostream &operator<<(raw_ostream &OS, const TypeSetByHwMode &T) {
+raw_ostream &llvm::operator<<(raw_ostream &OS, const TypeSetByHwMode &T) {
T.writeToStream(OS);
return OS;
}
-} // namespace llvm
LLVM_DUMP_METHOD
void TypeSetByHwMode::dump() const { dbgs() << *this << '\n'; }
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index e873b3e..8d0ec9a 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -744,7 +744,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
RSI.insertRegSizeForMode(DefaultMode, RI);
}
- CopyCost = R->getValueAsInt("CopyCost");
+ int CopyCostParsed = R->getValueAsInt("CopyCost");
Allocatable = R->getValueAsBit("isAllocatable");
AltOrderSelect = R->getValueAsString("AltOrderSelect");
int AllocationPriority = R->getValueAsInt("AllocationPriority");
@@ -757,6 +757,14 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
const BitsInit *TSF = R->getValueAsBitsInit("TSFlags");
for (auto [Idx, Bit] : enumerate(TSF->getBits()))
TSFlags |= uint8_t(cast<BitInit>(Bit)->getValue()) << Idx;
+
+ // Saturate negative costs to the maximum
+ if (CopyCostParsed < 0)
+ CopyCost = std::numeric_limits<uint8_t>::max();
+ else if (!isUInt<8>(CopyCostParsed))
+ PrintFatalError(R->getLoc(), "'CopyCost' must be an 8-bit value");
+
+ CopyCost = CopyCostParsed;
}
// Create an inferred register class that was missing from the .td files.
@@ -849,17 +857,6 @@ unsigned CodeGenRegisterClass::getWeight(const CodeGenRegBank &RegBank) const {
return (*Members.begin())->getWeight(RegBank);
}
-namespace llvm {
-
-raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) {
- OS << "{ " << K.RSI;
- for (const auto R : *K.Members)
- OS << ", " << R->getName();
- return OS << " }";
-}
-
-} // end namespace llvm
-
// This is a simple lexicographical order that can be used to search for sets.
// It is not the same as the topological order provided by TopoOrderRC.
bool CodeGenRegisterClass::Key::operator<(
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h
index 81aa663..89dac12 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h
@@ -359,7 +359,7 @@ public:
StringRef Namespace;
SmallVector<ValueTypeByHwMode, 4> VTs;
RegSizeInfoByHwMode RSI;
- int CopyCost;
+ uint8_t CopyCost;
bool Allocatable;
StringRef AltOrderSelect;
uint8_t AllocationPriority;
diff --git a/llvm/utils/TableGen/Common/InfoByHwMode.cpp b/llvm/utils/TableGen/Common/InfoByHwMode.cpp
index a6e2fc4..4c8197d 100644
--- a/llvm/utils/TableGen/Common/InfoByHwMode.cpp
+++ b/llvm/utils/TableGen/Common/InfoByHwMode.cpp
@@ -227,19 +227,17 @@ EncodingInfoByHwMode::EncodingInfoByHwMode(const Record *R,
}
}
-namespace llvm {
-raw_ostream &operator<<(raw_ostream &OS, const ValueTypeByHwMode &T) {
+raw_ostream &llvm::operator<<(raw_ostream &OS, const ValueTypeByHwMode &T) {
T.writeToStream(OS);
return OS;
}
-raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfo &T) {
+raw_ostream &llvm::operator<<(raw_ostream &OS, const RegSizeInfo &T) {
T.writeToStream(OS);
return OS;
}
-raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfoByHwMode &T) {
+raw_ostream &llvm::operator<<(raw_ostream &OS, const RegSizeInfoByHwMode &T) {
T.writeToStream(OS);
return OS;
}
-} // namespace llvm
diff --git a/llvm/utils/TableGen/Common/PredicateExpander.cpp b/llvm/utils/TableGen/Common/PredicateExpander.cpp
index 09d9538..03252ed 100644
--- a/llvm/utils/TableGen/Common/PredicateExpander.cpp
+++ b/llvm/utils/TableGen/Common/PredicateExpander.cpp
@@ -14,7 +14,7 @@
#include "CodeGenSchedule.h" // Definition of STIPredicateFunction.
#include "llvm/TableGen/Record.h"
-namespace llvm {
+using namespace llvm;
void PredicateExpander::expandTrue(raw_ostream &OS) { OS << "true"; }
void PredicateExpander::expandFalse(raw_ostream &OS) { OS << "false"; }
@@ -553,5 +553,3 @@ void STIPredicateExpander::expandSTIPredicate(raw_ostream &OS,
expandEpilogue(OS, Fn);
}
}
-
-} // namespace llvm
diff --git a/llvm/utils/TableGen/DXILEmitter.cpp b/llvm/utils/TableGen/DXILEmitter.cpp
index 09ce9f3..9471959 100644
--- a/llvm/utils/TableGen/DXILEmitter.cpp
+++ b/llvm/utils/TableGen/DXILEmitter.cpp
@@ -37,15 +37,6 @@ struct DXILIntrinsicSelect {
SmallVector<const Record *> ArgSelectRecords;
};
-static StringRef StripIntrinArgSelectTypePrefix(StringRef Type) {
- StringRef Prefix = "IntrinArgSelect_";
- if (!Type.starts_with(Prefix)) {
- PrintFatalError("IntrinArgSelectType definintion must be prefixed with "
- "'IntrinArgSelect_'");
- }
- return Type.substr(Prefix.size());
-}
-
struct DXILOperationDesc {
std::string OpName; // name of DXIL operation
int OpCode; // ID of DXIL operation
@@ -66,6 +57,15 @@ struct DXILOperationDesc {
};
} // end anonymous namespace
+static StringRef stripIntrinArgSelectTypePrefix(StringRef Type) {
+ StringRef Prefix = "IntrinArgSelect_";
+ if (!Type.starts_with(Prefix)) {
+ PrintFatalError("IntrinArgSelectType definintion must be prefixed with "
+ "'IntrinArgSelect_'");
+ }
+ return Type.substr(Prefix.size());
+}
+
/// In-place sort TableGen records of class with a field
/// Version dxil_version
/// in the ascending version order.
@@ -449,7 +449,7 @@ static void emitDXILIntrinsicMap(ArrayRef<DXILOperationDesc> Ops,
ArgSelect->getValueAsDef("type")->getNameInitAsString();
int Value = ArgSelect->getValueAsInt("value");
OS << "(IntrinArgSelect{"
- << "IntrinArgSelect::Type::" << StripIntrinArgSelectTypePrefix(Type)
+ << "IntrinArgSelect::Type::" << stripIntrinArgSelectTypePrefix(Type)
<< "," << Value << "}), ";
}
OS << ")\n";
@@ -466,7 +466,7 @@ static void emitDXILIntrinsicArgSelectTypes(const RecordKeeper &Records,
OS << "#ifdef DXIL_OP_INTRINSIC_ARG_SELECT_TYPE\n";
for (const Record *Records :
Records.getAllDerivedDefinitions("IntrinArgSelectType")) {
- StringRef StrippedName = StripIntrinArgSelectTypePrefix(Records->getName());
+ StringRef StrippedName = stripIntrinArgSelectTypePrefix(Records->getName());
OS << "DXIL_OP_INTRINSIC_ARG_SELECT_TYPE(" << StrippedName << ")\n";
}
OS << "#undef DXIL_OP_INTRINSIC_ARG_SELECT_TYPE\n";
diff --git a/llvm/utils/TableGen/DecoderEmitter.cpp b/llvm/utils/TableGen/DecoderEmitter.cpp
index 961dc28..5d41b7d 100644
--- a/llvm/utils/TableGen/DecoderEmitter.cpp
+++ b/llvm/utils/TableGen/DecoderEmitter.cpp
@@ -194,10 +194,6 @@ private:
void parseInstructionEncodings();
};
-} // end anonymous namespace
-
-namespace {
-
struct EncodingIsland {
unsigned StartBit;
unsigned NumBits;
diff --git a/llvm/utils/TableGen/ExegesisEmitter.cpp b/llvm/utils/TableGen/ExegesisEmitter.cpp
index 1b4b072..bd69919 100644
--- a/llvm/utils/TableGen/ExegesisEmitter.cpp
+++ b/llvm/utils/TableGen/ExegesisEmitter.cpp
@@ -58,6 +58,14 @@ private:
const std::map<llvm::StringRef, unsigned> PfmCounterNameTable;
};
+struct ValidationCounterInfo {
+ int64_t EventNumber;
+ StringRef EventName;
+ unsigned PfmCounterID;
+};
+
+} // namespace
+
static std::map<llvm::StringRef, unsigned>
collectPfmCounters(const RecordKeeper &Records) {
std::map<llvm::StringRef, unsigned> PfmCounterNameTable;
@@ -106,14 +114,8 @@ ExegesisEmitter::ExegesisEmitter(const RecordKeeper &RK)
Target = Targets[0]->getName().str();
}
-struct ValidationCounterInfo {
- int64_t EventNumber;
- StringRef EventName;
- unsigned PfmCounterID;
-};
-
-bool EventNumberLess(const ValidationCounterInfo &LHS,
- const ValidationCounterInfo &RHS) {
+static bool EventNumberLess(const ValidationCounterInfo &LHS,
+ const ValidationCounterInfo &RHS) {
return LHS.EventNumber < RHS.EventNumber;
}
@@ -221,7 +223,7 @@ void ExegesisEmitter::emitPfmCounters(raw_ostream &OS) const {
emitPfmCountersInfo(*Def, IssueCountersTableOffset, OS);
OS << "\n";
-} // namespace
+}
void ExegesisEmitter::emitPfmCountersLookupTable(raw_ostream &OS) const {
std::vector<const Record *> Bindings =
@@ -249,7 +251,5 @@ void ExegesisEmitter::run(raw_ostream &OS) const {
emitPfmCountersLookupTable(OS);
}
-} // end anonymous namespace
-
static TableGen::Emitter::OptClass<ExegesisEmitter>
X("gen-exegesis", "Generate llvm-exegesis tables");
diff --git a/llvm/utils/TableGen/FastISelEmitter.cpp b/llvm/utils/TableGen/FastISelEmitter.cpp
index 694d89a..dba8bde 100644
--- a/llvm/utils/TableGen/FastISelEmitter.cpp
+++ b/llvm/utils/TableGen/FastISelEmitter.cpp
@@ -52,11 +52,9 @@ struct InstructionMemo {
InstructionMemo(const InstructionMemo &Other) = delete;
InstructionMemo(InstructionMemo &&Other) = default;
};
-} // End anonymous namespace
/// ImmPredicateSet - This uniques predicates (represented as a string) and
/// gives them unique (small) integer ID's that start at 0.
-namespace {
class ImmPredicateSet {
DenseMap<TreePattern *, unsigned> ImmIDs;
std::vector<TreePredicateFn> PredsByName;
@@ -77,12 +75,10 @@ public:
iterator begin() const { return PredsByName.begin(); }
iterator end() const { return PredsByName.end(); }
};
-} // End anonymous namespace
/// OperandsSignature - This class holds a description of a list of operand
/// types. It has utility methods for emitting text based on the operands.
///
-namespace {
struct OperandsSignature {
class OpKind {
enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 };
@@ -366,9 +362,7 @@ struct OperandsSignature {
Opnd.printManglingSuffix(OS, ImmPredicates, StripImmCodes);
}
};
-} // End anonymous namespace
-namespace {
class FastISelMap {
// A multimap is needed instead of a "plain" map because the key is
// the instruction's complexity (an int) and they are not unique.
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index c4b1c5f5..a67a5a9 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -1083,14 +1083,13 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS) {
std::string RCName = Order.empty() ? "nullptr" : RC.getName();
std::string RCBitsName = Order.empty() ? "nullptr" : RC.getName() + "Bits";
std::string RCBitsSize = Order.empty() ? "0" : "sizeof(" + RCBitsName + ")";
- assert(isInt<8>(RC.CopyCost) && "Copy cost too large.");
uint32_t RegSize = 0;
if (RC.RSI.isSimple())
RegSize = RC.RSI.getSimple().RegSize;
OS << " { " << RCName << ", " << RCBitsName << ", "
<< RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size()
<< ", " << RCBitsSize << ", " << RC.getQualifiedIdName() << ", "
- << RegSize << ", " << RC.CopyCost << ", "
+ << RegSize << ", " << static_cast<unsigned>(RC.CopyCost) << ", "
<< (RC.Allocatable ? "true" : "false") << ", "
<< (RC.getBaseClassOrder() ? "true" : "false") << " },\n";
}
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 0f42d49..b0a309c 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -1761,7 +1761,7 @@ void SubtargetEmitter::emitSchedModelHelpers(const std::string &ClassName,
<< "\n::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,"
<< " const MCInstrInfo *MCII, unsigned CPUID) const {\n"
<< " return " << Target << "_MC"
- << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);\n"
+ << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);\n"
<< "} // " << ClassName << "::resolveVariantSchedClass\n\n";
STIPredicateExpander PE(Target, /*Indent=*/0);
@@ -1923,7 +1923,8 @@ void SubtargetEmitter::parseFeaturesFunction(raw_ostream &OS) {
void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
OS << "namespace " << Target << "_MC {\n"
<< "unsigned resolveVariantSchedClassImpl(unsigned SchedClass,\n"
- << " const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {\n";
+ << " const MCInst *MI, const MCInstrInfo *MCII, "
+ << "const MCSubtargetInfo &STI, unsigned CPUID) {\n";
emitSchedModelHelpersImpl(OS, /* OnlyExpandMCPredicates */ true);
OS << "}\n";
OS << "} // end namespace " << Target << "_MC\n\n";
@@ -1945,7 +1946,7 @@ void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
<< " const MCInst *MI, const MCInstrInfo *MCII,\n"
<< " unsigned CPUID) const override {\n"
<< " return " << Target << "_MC"
- << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);\n";
+ << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);\n";
OS << " }\n";
if (TGT.getHwModes().getNumModeIds() > 1) {
OS << " unsigned getHwModeSet() const override;\n";
@@ -2073,7 +2074,8 @@ void SubtargetEmitter::run(raw_ostream &OS) {
OS << "class DFAPacketizer;\n";
OS << "namespace " << Target << "_MC {\n"
<< "unsigned resolveVariantSchedClassImpl(unsigned SchedClass,"
- << " const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);\n"
+ << " const MCInst *MI, const MCInstrInfo *MCII, "
+ << "const MCSubtargetInfo &STI, unsigned CPUID);\n"
<< "} // end namespace " << Target << "_MC\n\n";
OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
<< " explicit " << ClassName << "(const Triple &TT, StringRef CPU, "
diff --git a/llvm/utils/TableGen/X86DisassemblerShared.h b/llvm/utils/TableGen/X86DisassemblerShared.h
index f60fd47..d5f936d 100644
--- a/llvm/utils/TableGen/X86DisassemblerShared.h
+++ b/llvm/utils/TableGen/X86DisassemblerShared.h
@@ -14,6 +14,8 @@
#include "llvm/Support/X86DisassemblerDecoderCommon.h"
+namespace llvm::X86Disassembler {
+
struct InstructionSpecifier {
llvm::X86Disassembler::OperandSpecifier
operands[llvm::X86Disassembler::X86_MAX_OPERANDS];
@@ -52,4 +54,6 @@ struct ContextDecision {
ContextDecision() { memset(opcodeDecisions, 0, sizeof(opcodeDecisions)); }
};
+} // namespace llvm::X86Disassembler
+
#endif
diff --git a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
index 1e1e4ab..6f523b5 100644
--- a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
@@ -30,22 +30,23 @@ struct ManualMapEntry {
const char *MemInstStr;
uint16_t Strategy;
};
+} // namespace
// List of instructions requiring explicitly aligned memory.
-const char *ExplicitAlign[] = {"MOVDQA", "MOVAPS", "MOVAPD", "MOVNTPS",
- "MOVNTPD", "MOVNTDQ", "MOVNTDQA"};
+static constexpr const char *ExplicitAlign[] = {
+ "MOVDQA", "MOVAPS", "MOVAPD", "MOVNTPS", "MOVNTPD", "MOVNTDQ", "MOVNTDQA"};
// List of instructions NOT requiring explicit memory alignment.
-const char *ExplicitUnalign[] = {"MOVDQU", "MOVUPS", "MOVUPD",
- "PCMPESTRM", "PCMPESTRI", "PCMPISTRM",
- "PCMPISTRI"};
+static constexpr const char *ExplicitUnalign[] = {
+ "MOVDQU", "MOVUPS", "MOVUPD", "PCMPESTRM",
+ "PCMPESTRI", "PCMPISTRM", "PCMPISTRI"};
-const ManualMapEntry ManualMapSet[] = {
+static const ManualMapEntry ManualMapSet[] = {
#define ENTRY(REG, MEM, FLAGS) {#REG, #MEM, FLAGS},
#include "X86ManualFoldTables.def"
};
-const std::set<StringRef> NoFoldSet = {
+static const std::set<StringRef> NoFoldSet = {
#define NOFOLD(INSN) #INSN,
#include "X86ManualFoldTables.def"
};
@@ -62,6 +63,7 @@ static bool isExplicitUnalign(const CodeGenInstruction *Inst) {
});
}
+namespace {
class X86FoldTablesEmitter {
const RecordKeeper &Records;
const CodeGenTarget Target;
@@ -230,6 +232,7 @@ private:
OS << "};\n\n";
}
};
+} // namespace
// Return true if one of the instruction's operands is a RST register class
static bool hasRSTRegClass(const CodeGenInstruction *Inst) {
@@ -318,6 +321,7 @@ static bool isNOREXRegClass(const Record *Op) {
// Function object - Operator() returns true if the given Reg instruction
// matches the Mem instruction of this object.
+namespace {
class IsMatch {
const CodeGenInstruction *MemInst;
const X86Disassembler::RecognizableInstrBase MemRI;
diff --git a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
index be5e2a7..2745ba7 100644
--- a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
+++ b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
@@ -66,6 +66,7 @@ private:
void printTable(ArrayRef<Entry> Table, StringRef Name, StringRef Macro,
raw_ostream &OS);
};
+} // namespace
void X86InstrMappingEmitter::printClassDef(raw_ostream &OS) {
OS << "struct X86TableEntry {\n"
@@ -106,6 +107,7 @@ void X86InstrMappingEmitter::printTable(ArrayRef<Entry> Table, StringRef Name,
printMacroEnd(Macro, OS);
}
+namespace {
class IsMatch {
const CodeGenInstruction *OldInst;
@@ -146,6 +148,7 @@ public:
return true;
}
};
+} // namespace
static bool isInteresting(const Record *Rec) {
// _REV instruction should not appear before encoding optimization
@@ -368,7 +371,6 @@ void X86InstrMappingEmitter::run(raw_ostream &OS) {
emitND2NonNDTable(Insts, OS);
emitSSE2AVXTable(Insts, OS);
}
-} // namespace
static TableGen::Emitter::OptClass<X86InstrMappingEmitter>
X("gen-x86-instr-mapping", "Generate X86 instruction mapping");
diff --git a/llvm/utils/TableGen/X86MnemonicTables.cpp b/llvm/utils/TableGen/X86MnemonicTables.cpp
index 85bd4df..7851919 100644
--- a/llvm/utils/TableGen/X86MnemonicTables.cpp
+++ b/llvm/utils/TableGen/X86MnemonicTables.cpp
@@ -30,6 +30,7 @@ public:
// Output X86 mnemonic tables.
void run(raw_ostream &OS);
};
+} // namespace
void X86MnemonicTablesEmitter::run(raw_ostream &OS) {
emitSourceFileHeader("X86 Mnemonic tables", OS);
@@ -83,7 +84,5 @@ void X86MnemonicTablesEmitter::run(raw_ostream &OS) {
OS << "} // end namespace X86\n} // end namespace llvm";
}
-} // namespace
-
static TableGen::Emitter::OptClass<X86MnemonicTablesEmitter>
X("gen-x86-mnemonic-tables", "Generate X86 mnemonic tables");
diff --git a/llvm/utils/TableGen/X86ModRMFilters.h b/llvm/utils/TableGen/X86ModRMFilters.h
index b579f22..7bf111f 100644
--- a/llvm/utils/TableGen/X86ModRMFilters.h
+++ b/llvm/utils/TableGen/X86ModRMFilters.h
@@ -19,9 +19,7 @@
#include <cstdint>
-namespace llvm {
-
-namespace X86Disassembler {
+namespace llvm::X86Disassembler {
/// ModRMFilter - Abstract base class for clases that recognize patterns in
/// ModR/M bytes.
@@ -135,8 +133,6 @@ public:
bool accepts(uint8_t modRM) const override { return (ModRM == modRM); }
};
-} // namespace X86Disassembler
-
-} // namespace llvm
+} // namespace llvm::X86Disassembler
#endif
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.h b/llvm/utils/TableGen/X86RecognizableInstr.h
index b74e74d..52f9538 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.h
+++ b/llvm/utils/TableGen/X86RecognizableInstr.h
@@ -22,8 +22,6 @@
#include <string>
#include <vector>
-struct InstructionSpecifier;
-
namespace llvm {
class Record;
#define X86_INSTR_MRM_MAPPING \
@@ -179,6 +177,8 @@ enum { ExplicitREX2 = 1, ExplicitEVEX = 3 };
namespace X86Disassembler {
class DisassemblerTables;
+struct InstructionSpecifier;
+
/// Extract common fields of a single X86 instruction from a CodeGenInstruction
struct RecognizableInstrBase {
/// The OpPrefix field from the record
generated by cgit v1.1 at 2025-10-04 03:51:33 +0000