diff options
Diffstat (limited to 'llvm/utils/TableGen/Common')
19 files changed, 224 insertions, 217 deletions
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp index 8076ce2..364817f 100644 --- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp +++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp @@ -776,7 +776,7 @@ bool TypeInfer::EnforceSameSize(TypeSetByHwMode &A, TypeSetByHwMode &B) { if (B.empty()) Changed |= EnforceAny(B); - typedef SmallSet<TypeSize, 2, TypeSizeComparator> TypeSizeSet; + using TypeSizeSet = SmallSet<TypeSize, 2, TypeSizeComparator>; auto NoSize = [](const TypeSizeSet &Sizes, MVT T) -> bool { return !Sizes.contains(T.getSizeInBits()); @@ -1830,10 +1830,6 @@ bool TreePatternNode::UpdateNodeTypeFromInst(unsigned ResNo, return UpdateNodeType(ResNo, getValueTypeByHwMode(R, T.getHwModes()), TP); } - // PointerLikeRegClass has a type that is determined at runtime. - if (Operand->isSubClassOf("PointerLikeRegClass")) - return UpdateNodeType(ResNo, MVT::iPTR, TP); - // Both RegisterClass and RegisterOperand operands derive their types from a // register class def. const Record *RC = nullptr; @@ -1921,8 +1917,8 @@ SDNodeInfo::SDNodeInfo(const Record *R, const CodeGenHwModes &CGH) : Def(R) { /// getKnownType - If the type constraints on this node imply a fixed type /// (e.g. all stores return void, etc), then return it as an -/// MVT::SimpleValueType. Otherwise, return EEVT::Other. -MVT::SimpleValueType SDNodeInfo::getKnownType(unsigned ResNo) const { +/// MVT. Otherwise, return EEVT::Other. +MVT SDNodeInfo::getKnownType(unsigned ResNo) const { unsigned NumResults = getNumResults(); assert(NumResults <= 1 && "We only work with nodes with zero or one result so far!"); @@ -1990,7 +1986,8 @@ static unsigned GetNumNodeResults(const Record *Operator, } if (Operator->isSubClassOf("Instruction")) { - CodeGenInstruction &InstInfo = CDP.getTargetInfo().getInstruction(Operator); + const CodeGenInstruction &InstInfo = + CDP.getTargetInfo().getInstruction(Operator); unsigned NumDefsToAdd = InstInfo.Operands.NumDefs; @@ -2412,12 +2409,6 @@ static TypeSetByHwMode getImplicitType(const Record *R, unsigned ResNo, const CodeGenHwModes &CGH = CDP.getTargetInfo().getHwModes(); return TypeSetByHwMode(getValueTypeByHwMode(T, CGH)); } - if (R->isSubClassOf("PointerLikeRegClass")) { - assert(ResNo == 0 && "Regclass can only have one result!"); - TypeSetByHwMode VTS(MVT::iPTR); - TP.getInfer().expandOverloads(VTS); - return VTS; - } if (R->getName() == "node" || R->getName() == "srcvalue" || R->getName() == "zero_reg" || R->getName() == "immAllOnesV" || @@ -2585,14 +2576,14 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) { ValueTypeByHwMode VVT = TP.getInfer().getConcrete(Types[0], false); for (auto &P : VVT) { - MVT::SimpleValueType VT = P.second.SimpleTy; + MVT VT = P.second; // Can only check for types of a known size if (VT == MVT::iPTR) continue; // Check that the value doesn't use more bits than we have. It must // either be a sign- or zero-extended equivalent of the original. - unsigned Width = MVT(VT).getFixedSizeInBits(); + unsigned Width = VT.getFixedSizeInBits(); int64_t Val = II->getValue(); if (!isIntN(Width, Val) && !isUIntN(Width, Val)) { TP.error("Integer value '" + Twine(Val) + @@ -2629,8 +2620,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) { for (unsigned i = 0, e = getNumChildren() - 1; i != e; ++i) { MadeChange |= getChild(i + 1).ApplyTypeConstraints(TP, NotRegisters); - MVT::SimpleValueType OpVT = - getValueType(Int->IS.ParamTys[i]->getValueAsDef("VT")); + MVT OpVT = getValueType(Int->IS.ParamTys[i]->getValueAsDef("VT")); assert(getChild(i + 1).getNumTypes() == 1 && "Unhandled case"); MadeChange |= getChild(i + 1).UpdateNodeType(0, OpVT, TP); } @@ -2657,7 +2647,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) { if (getOperator()->isSubClassOf("Instruction")) { const DAGInstruction &Inst = CDP.getInstruction(getOperator()); - CodeGenInstruction &InstInfo = + const CodeGenInstruction &InstInfo = CDP.getTargetInfo().getInstruction(getOperator()); bool MadeChange = false; @@ -2676,8 +2666,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) { // FIXME: Generalize to multiple possible types and multiple possible // ImplicitDefs. - MVT::SimpleValueType VT = - InstInfo.HasOneImplicitDefWithKnownVT(CDP.getTargetInfo()); + MVT VT = InstInfo.HasOneImplicitDefWithKnownVT(CDP.getTargetInfo()); if (VT != MVT::Other) MadeChange |= UpdateNodeType(ResNo, VT, TP); @@ -2923,6 +2912,14 @@ TreePattern::TreePattern(const Record *TheRec, const DagInit *Pat, bool isInput, Trees.push_back(ParseTreePattern(Pat, "")); } +TreePattern::TreePattern(const Record *TheRec, ArrayRef<const Init *> Args, + ArrayRef<const StringInit *> ArgNames, bool isInput, + CodeGenDAGPatterns &cdp) + : TheRecord(TheRec), CDP(cdp), isInputPattern(isInput), HasError(false), + Infer(*this) { + Trees.push_back(ParseRootlessTreePattern(Args, ArgNames)); +} + TreePattern::TreePattern(const Record *TheRec, TreePatternNodePtr Pat, bool isInput, CodeGenDAGPatterns &cdp) : TheRecord(TheRec), CDP(cdp), isInputPattern(isInput), HasError(false), @@ -2951,6 +2948,19 @@ void TreePattern::ComputeNamedNodes(TreePatternNode &N) { ComputeNamedNodes(Child); } +TreePatternNodePtr +TreePattern::ParseRootlessTreePattern(ArrayRef<const Init *> Args, + ArrayRef<const StringInit *> ArgNames) { + std::vector<TreePatternNodePtr> Children; + + for (auto [Arg, ArgName] : llvm::zip_equal(Args, ArgNames)) { + StringRef NameStr = ArgName ? ArgName->getValue() : ""; + Children.push_back(ParseTreePattern(Arg, NameStr)); + } + + return makeIntrusiveRefCnt<TreePatternNode>(nullptr, std::move(Children), 1); +} + TreePatternNodePtr TreePattern::ParseTreePattern(const Init *TheInit, StringRef OpName) { RecordKeeper &RK = TheInit->getRecordKeeper(); @@ -3488,20 +3498,12 @@ void CodeGenDAGPatterns::ParseDefaultOperands() { ArrayRef<const Record *> DefaultOps = Records.getAllDerivedDefinitions("OperandWithDefaultOps"); - // Find some SDNode. - assert(!SDNodes.empty() && "No SDNodes parsed?"); - const Init *SomeSDNode = SDNodes.begin()->first->getDefInit(); - for (unsigned i = 0, e = DefaultOps.size(); i != e; ++i) { const DagInit *DefaultInfo = DefaultOps[i]->getValueAsDag("DefaultOps"); - // Clone the DefaultInfo dag node, changing the operator from 'ops' to - // SomeSDnode so that we can parse this. - const DagInit *DI = DagInit::get(SomeSDNode, DefaultInfo->getArgs(), - DefaultInfo->getArgNames()); - // Create a TreePattern to parse this. - TreePattern P(DefaultOps[i], DI, false, *this); + TreePattern P(DefaultOps[i], DefaultInfo->getArgs(), + DefaultInfo->getArgNames(), false, *this); assert(P.getNumTrees() == 1 && "This ctor can only produce one tree!"); // Copy the operands over into a DAGDefaultOperand. @@ -3649,8 +3651,7 @@ void CodeGenDAGPatterns::FindPatternInputsAndOutputs( if (Val->getDef()->isSubClassOf("RegisterClassLike") || Val->getDef()->isSubClassOf("ValueType") || - Val->getDef()->isSubClassOf("RegisterOperand") || - Val->getDef()->isSubClassOf("PointerLikeRegClass")) { + Val->getDef()->isSubClassOf("RegisterOperand")) { if (Dest->getName().empty()) I.error("set destination must have a name!"); if (!InstResults.insert_or_assign(Dest->getName(), Dest).second) @@ -3871,7 +3872,7 @@ static void getInstructionsInTree(TreePatternNode &Tree, /// Check the class of a pattern leaf node against the instruction operand it /// represents. -static bool checkOperandClass(CGIOperandList::OperandInfo &OI, +static bool checkOperandClass(const CGIOperandList::OperandInfo &OI, const Record *Leaf) { if (OI.Rec == Leaf) return true; @@ -3888,7 +3889,7 @@ static bool checkOperandClass(CGIOperandList::OperandInfo &OI, return false; } -void CodeGenDAGPatterns::parseInstructionPattern(CodeGenInstruction &CGI, +void CodeGenDAGPatterns::parseInstructionPattern(const CodeGenInstruction &CGI, const ListInit *Pat, DAGInstMap &DAGInsts) { @@ -3987,7 +3988,7 @@ void CodeGenDAGPatterns::parseInstructionPattern(CodeGenInstruction &CGI, std::vector<TreePatternNodePtr> ResultNodeOperands; std::vector<const Record *> Operands; for (unsigned i = NumResults, e = CGI.Operands.size(); i != e; ++i) { - CGIOperandList::OperandInfo &Op = CGI.Operands[i]; + const CGIOperandList::OperandInfo &Op = CGI.Operands[i]; StringRef OpName = Op.Name; if (OpName.empty()) { I.error("Operand #" + Twine(i) + " in operands list has no name!"); @@ -4093,7 +4094,7 @@ void CodeGenDAGPatterns::ParseInstructions() { std::vector<const Record *> Results; std::vector<const Record *> Operands; - CodeGenInstruction &InstInfo = Target.getInstruction(Instr); + const CodeGenInstruction &InstInfo = Target.getInstruction(Instr); if (InstInfo.Operands.size() != 0) { for (unsigned j = 0, e = InstInfo.Operands.NumDefs; j < e; ++j) @@ -4112,7 +4113,7 @@ void CodeGenDAGPatterns::ParseInstructions() { continue; // no pattern. } - CodeGenInstruction &CGI = Target.getInstruction(Instr); + const CodeGenInstruction &CGI = Target.getInstruction(Instr); parseInstructionPattern(CGI, LI, Instructions); } @@ -4129,7 +4130,7 @@ void CodeGenDAGPatterns::ParseInstructions() { } } -typedef std::pair<TreePatternNode *, unsigned> NameRecord; +using NameRecord = std::pair<TreePatternNode *, unsigned>; static void FindNames(TreePatternNode &P, std::map<StringRef, NameRecord> &Names, @@ -4590,7 +4591,7 @@ void CodeGenDAGPatterns::ExpandHwModeBasedTypes() { } /// Dependent variable map for CodeGenDAGPattern variant generation -typedef StringMap<int> DepVarMap; +using DepVarMap = StringMap<int>; static void FindDepVarsOf(TreePatternNode &N, DepVarMap &DepMap) { if (N.isLeaf()) { diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h index 2ed8d13..9a67933 100644 --- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h +++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h @@ -71,7 +71,7 @@ struct MachineValueTypeSet { return Count; } LLVM_ATTRIBUTE_ALWAYS_INLINE - void clear() { std::memset(Words.data(), 0, NumWords * sizeof(WordType)); } + void clear() { Words.fill(0); } LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const { for (WordType W : Words) @@ -86,7 +86,7 @@ struct MachineValueTypeSet { } std::pair<MachineValueTypeSet &, bool> insert(MVT T) { assert(T.SimpleTy < Capacity && "Capacity needs to be enlarged"); - bool V = count(T.SimpleTy); + bool V = count(T); Words[T.SimpleTy / WordWidth] |= WordType(1) << (T.SimpleTy % WordWidth); return {*this, V}; } @@ -138,25 +138,19 @@ struct MachineValueTypeSet { private: unsigned find_from_pos(unsigned P) const { unsigned SkipWords = P / WordWidth; - unsigned SkipBits = P % WordWidth; - unsigned Count = SkipWords * WordWidth; - - // If P is in the middle of a word, process it manually here, because - // the trailing bits need to be masked off to use findFirstSet. - if (SkipBits != 0) { - WordType W = Set->Words[SkipWords]; - W &= maskLeadingOnes<WordType>(WordWidth - SkipBits); - if (W != 0) - return Count + llvm::countr_zero(W); - Count += WordWidth; - SkipWords++; - } for (unsigned i = SkipWords; i != NumWords; ++i) { WordType W = Set->Words[i]; + + // If P is in the middle of a word, process it manually here, because + // the trailing bits need to be masked off to use countr_zero. + if (i == SkipWords) { + unsigned SkipBits = P % WordWidth; + W &= maskTrailingZeros<WordType>(SkipBits); + } + if (W != 0) - return Count + llvm::countr_zero(W); - Count += WordWidth; + return i * WordWidth + llvm::countr_zero(W); } return Capacity; } @@ -191,8 +185,7 @@ struct TypeSetByHwMode : public InfoByHwMode<MachineValueTypeSet> { TypeSetByHwMode() = default; TypeSetByHwMode(const TypeSetByHwMode &VTS) = default; TypeSetByHwMode &operator=(const TypeSetByHwMode &) = default; - TypeSetByHwMode(MVT::SimpleValueType VT) - : TypeSetByHwMode(ValueTypeByHwMode(VT)) {} + TypeSetByHwMode(MVT VT) : TypeSetByHwMode(ValueTypeByHwMode(VT)) {} TypeSetByHwMode(ArrayRef<ValueTypeByHwMode> VTList); SetType &getOrCreate(unsigned Mode) { return Map[Mode]; } @@ -259,7 +252,7 @@ struct TypeInfer { /// otherwise. bool MergeInTypeInfo(TypeSetByHwMode &Out, const TypeSetByHwMode &In) const; - bool MergeInTypeInfo(TypeSetByHwMode &Out, MVT::SimpleValueType InVT) const { + bool MergeInTypeInfo(TypeSetByHwMode &Out, MVT InVT) const { return MergeInTypeInfo(Out, TypeSetByHwMode(InVT)); } bool MergeInTypeInfo(TypeSetByHwMode &Out, @@ -349,7 +342,7 @@ private: }; /// Set type used to track multiply used variables in patterns -typedef StringSet<> MultipleUseVarSet; +using MultipleUseVarSet = StringSet<>; /// SDTypeConstraint - This is a discriminated union of constraints, /// corresponding to the SDTypeConstraint tablegen class in Target.td. @@ -451,8 +444,8 @@ public: /// getKnownType - If the type constraints on this node imply a fixed type /// (e.g. all stores return void, etc), then return it as an - /// MVT::SimpleValueType. Otherwise, return MVT::Other. - MVT::SimpleValueType getKnownType(unsigned ResNo) const; + /// MVT. Otherwise, return MVT::Other. + MVT getKnownType(unsigned ResNo) const; unsigned getProperties() const { return Properties; } @@ -698,8 +691,8 @@ public: } TypeSetByHwMode &getExtType(unsigned ResNo) { return Types[ResNo]; } void setType(unsigned ResNo, const TypeSetByHwMode &T) { Types[ResNo] = T; } - MVT::SimpleValueType getSimpleType(unsigned ResNo) const { - return Types[ResNo].getMachineValueType().SimpleTy; + MVT getSimpleType(unsigned ResNo) const { + return Types[ResNo].getMachineValueType(); } bool hasConcreteType(unsigned ResNo) const { @@ -850,8 +843,7 @@ public: // Higher level manipulation routines. /// bool UpdateNodeType(unsigned ResNo, const TypeSetByHwMode &InTy, TreePattern &TP); - bool UpdateNodeType(unsigned ResNo, MVT::SimpleValueType InTy, - TreePattern &TP); + bool UpdateNodeType(unsigned ResNo, MVT InTy, TreePattern &TP); bool UpdateNodeType(unsigned ResNo, const ValueTypeByHwMode &InTy, TreePattern &TP); @@ -925,6 +917,9 @@ public: CodeGenDAGPatterns &ise); TreePattern(const Record *TheRec, const DagInit *Pat, bool isInput, CodeGenDAGPatterns &ise); + TreePattern(const Record *TheRec, ArrayRef<const Init *> Args, + ArrayRef<const StringInit *> ArgNames, bool isInput, + CodeGenDAGPatterns &ise); TreePattern(const Record *TheRec, TreePatternNodePtr Pat, bool isInput, CodeGenDAGPatterns &ise); @@ -989,6 +984,9 @@ public: private: TreePatternNodePtr ParseTreePattern(const Init *DI, StringRef OpName); + TreePatternNodePtr + ParseRootlessTreePattern(ArrayRef<const Init *> Args, + ArrayRef<const StringInit *> ArgNames); void ComputeNamedNodes(); void ComputeNamedNodes(TreePatternNode &N); }; @@ -1001,8 +999,7 @@ inline bool TreePatternNode::UpdateNodeType(unsigned ResNo, return TP.getInfer().MergeInTypeInfo(Types[ResNo], VTS); } -inline bool TreePatternNode::UpdateNodeType(unsigned ResNo, - MVT::SimpleValueType InTy, +inline bool TreePatternNode::UpdateNodeType(unsigned ResNo, MVT InTy, TreePattern &TP) { TypeSetByHwMode VTS(InTy); TP.getInfer().expandOverloads(VTS); @@ -1217,15 +1214,15 @@ public: iterator_range<pf_iterator> ptfs() const { return PatternFragments; } // Patterns to match information. - typedef std::vector<PatternToMatch>::const_iterator ptm_iterator; + using ptm_iterator = std::vector<PatternToMatch>::const_iterator; ptm_iterator ptm_begin() const { return PatternsToMatch.begin(); } ptm_iterator ptm_end() const { return PatternsToMatch.end(); } iterator_range<ptm_iterator> ptms() const { return PatternsToMatch; } /// Parse the Pattern for an instruction, and insert the result in DAGInsts. - typedef std::map<const Record *, DAGInstruction, LessRecordByID> DAGInstMap; - void parseInstructionPattern(CodeGenInstruction &CGI, const ListInit *Pattern, - DAGInstMap &DAGInsts); + using DAGInstMap = std::map<const Record *, DAGInstruction, LessRecordByID>; + void parseInstructionPattern(const CodeGenInstruction &CGI, + const ListInit *Pattern, DAGInstMap &DAGInsts); const DAGInstruction &getInstruction(const Record *R) const { auto F = Instructions.find(R); diff --git a/llvm/utils/TableGen/Common/CodeGenHwModes.h b/llvm/utils/TableGen/Common/CodeGenHwModes.h index 5e1b31a..7e45f8e 100644 --- a/llvm/utils/TableGen/Common/CodeGenHwModes.h +++ b/llvm/utils/TableGen/Common/CodeGenHwModes.h @@ -15,7 +15,6 @@ #include "llvm/ADT/StringRef.h" #include <cassert> #include <map> -#include <string> #include <utility> #include <vector> @@ -36,7 +35,7 @@ struct HwMode { struct HwModeSelect { HwModeSelect(const Record *R, CodeGenHwModes &CGH); - typedef std::pair<unsigned, const Record *> PairType; + using PairType = std::pair<unsigned, const Record *>; std::vector<PairType> Items; void dump() const; }; diff --git a/llvm/utils/TableGen/Common/CodeGenInstAlias.cpp b/llvm/utils/TableGen/Common/CodeGenInstAlias.cpp index 6c1a3e9..d3050c0 100644 --- a/llvm/utils/TableGen/Common/CodeGenInstAlias.cpp +++ b/llvm/utils/TableGen/Common/CodeGenInstAlias.cpp @@ -40,24 +40,21 @@ unsigned CodeGenInstAlias::ResultOperand::getMINumOperands() const { using ResultOperand = CodeGenInstAlias::ResultOperand; -static Expected<ResultOperand> matchSimpleOperand(const Init *Arg, - const StringInit *ArgName, - const Record *Op, - const CodeGenTarget &T) { - if (Op->isSubClassOf("RegisterClass") || - Op->isSubClassOf("RegisterOperand")) { - const Record *OpRC = - Op->isSubClassOf("RegisterClass") ? Op : Op->getValueAsDef("RegClass"); - +static Expected<ResultOperand> +matchSimpleOperand(const Init *Arg, const StringInit *ArgName, const Record *Op, + const CodeGenTarget &T, ArrayRef<SMLoc> Loc) { + if (const Record *OpRC = T.getAsRegClassLike(Op)) { if (const auto *ArgDef = dyn_cast<DefInit>(Arg)) { const Record *ArgRec = ArgDef->getDef(); // Match 'RegClass:$name' or 'RegOp:$name'. if (const Record *ArgRC = T.getInitValueAsRegClassLike(Arg)) { if (ArgRC->isSubClassOf("RegisterClass")) { - if (!T.getRegisterClass(OpRC).hasSubClass(&T.getRegisterClass(ArgRC))) + if (!OpRC->isSubClassOf("RegisterClass") || + !T.getRegisterClass(OpRC, Loc).hasSubClass( + &T.getRegisterClass(ArgRC, Loc))) return createStringError( - "argument register class" + ArgRC->getName() + + "argument register class " + ArgRC->getName() + " is not a subclass of operand register class " + OpRC->getName()); if (!ArgName) @@ -73,7 +70,8 @@ static Expected<ResultOperand> matchSimpleOperand(const Init *Arg, // Match 'Reg'. if (ArgRec->isSubClassOf("Register")) { - if (!T.getRegisterClass(OpRC).contains(T.getRegBank().getReg(ArgRec))) + if (!T.getRegisterClass(OpRC, Loc).contains( + T.getRegBank().getReg(ArgRec))) return createStringError( "register argument " + ArgRec->getName() + " is not a member of operand register class " + OpRC->getName()); @@ -111,11 +109,9 @@ static Expected<ResultOperand> matchSimpleOperand(const Init *Arg, return ResultOperand::createRecord(ArgName->getAsUnquotedString(), ArgDef->getDef()); } - - return createStringError("argument must be a subclass of Operand"); } - - llvm_unreachable("Unknown operand kind"); + return createStringError("argument must be a subclass of 'Operand' but got " + + Op->getName() + " instead"); } static Expected<ResultOperand> matchComplexOperand(const Init *Arg, @@ -204,7 +200,8 @@ CodeGenInstAlias::CodeGenInstAlias(const Record *R, const CodeGenTarget &T) const Record *SubOp = cast<DefInit>(OpInfo.MIOperandInfo->getArg(SubOpIdx))->getDef(); Expected<ResultOperand> ResOpOrErr = matchSimpleOperand( - ArgDag->getArg(SubOpIdx), ArgDag->getArgName(SubOpIdx), SubOp, T); + ArgDag->getArg(SubOpIdx), ArgDag->getArgName(SubOpIdx), SubOp, T, + R->getLoc()); if (!ResOpOrErr) PrintFatalError(R, "in argument #" + Twine(ArgIdx) + "." + Twine(SubOpIdx) + ": " + @@ -225,8 +222,9 @@ CodeGenInstAlias::CodeGenInstAlias(const Record *R, const CodeGenTarget &T) } else { // Simple operand (RegisterClass, RegisterOperand or Operand with empty // MIOperandInfo). - Expected<ResultOperand> ResOpOrErr = matchSimpleOperand( - Result->getArg(ArgIdx), Result->getArgName(ArgIdx), Op, T); + Expected<ResultOperand> ResOpOrErr = + matchSimpleOperand(Result->getArg(ArgIdx), Result->getArgName(ArgIdx), + Op, T, R->getLoc()); if (!ResOpOrErr) PrintFatalError(R, "in argument #" + Twine(ArgIdx) + ": " + toString(ResOpOrErr.takeError())); diff --git a/llvm/utils/TableGen/Common/CodeGenInstAlias.h b/llvm/utils/TableGen/Common/CodeGenInstAlias.h index e9f6031..1cb68d6 100644 --- a/llvm/utils/TableGen/Common/CodeGenInstAlias.h +++ b/llvm/utils/TableGen/Common/CodeGenInstAlias.h @@ -41,7 +41,7 @@ public: /// ResultInst - The instruction generated by the alias (decoded from /// Result). - CodeGenInstruction *ResultInst; + const CodeGenInstruction *ResultInst; class ResultOperand { std::string Name; diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.cpp b/llvm/utils/TableGen/Common/CodeGenInstruction.cpp index 93d4f4b..62a7b54 100644 --- a/llvm/utils/TableGen/Common/CodeGenInstruction.cpp +++ b/llvm/utils/TableGen/Common/CodeGenInstruction.cpp @@ -499,7 +499,7 @@ CodeGenInstruction::CodeGenInstruction(const Record *R) /// HasOneImplicitDefWithKnownVT - If the instruction has at least one /// implicit def and it has a known VT, return the VT, otherwise return /// MVT::Other. -MVT::SimpleValueType CodeGenInstruction::HasOneImplicitDefWithKnownVT( +MVT CodeGenInstruction::HasOneImplicitDefWithKnownVT( const CodeGenTarget &TargetInfo) const { if (ImplicitDefs.empty()) return MVT::Other; @@ -510,7 +510,7 @@ MVT::SimpleValueType CodeGenInstruction::HasOneImplicitDefWithKnownVT( const std::vector<ValueTypeByHwMode> &RegVTs = TargetInfo.getRegisterVTs(FirstImplicitDef); if (RegVTs.size() == 1 && RegVTs[0].isSimple()) - return RegVTs[0].getSimple().SimpleTy; + return RegVTs[0].getSimple(); return MVT::Other; } diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.h b/llvm/utils/TableGen/Common/CodeGenInstruction.h index ed0bfa7..a50b190 100644 --- a/llvm/utils/TableGen/Common/CodeGenInstruction.h +++ b/llvm/utils/TableGen/Common/CodeGenInstruction.h @@ -158,8 +158,8 @@ public: OperandInfo &back() { return OperandList.back(); } const OperandInfo &back() const { return OperandList.back(); } - typedef std::vector<OperandInfo>::iterator iterator; - typedef std::vector<OperandInfo>::const_iterator const_iterator; + using iterator = std::vector<OperandInfo>::iterator; + using const_iterator = std::vector<OperandInfo>::const_iterator; iterator begin() { return OperandList.begin(); } const_iterator begin() const { return OperandList.begin(); } iterator end() { return OperandList.end(); } @@ -289,8 +289,7 @@ public: /// HasOneImplicitDefWithKnownVT - If the instruction has at least one /// implicit def and it has a known VT, return the VT, otherwise return /// MVT::Other. - MVT::SimpleValueType - HasOneImplicitDefWithKnownVT(const CodeGenTarget &TargetInfo) const; + MVT HasOneImplicitDefWithKnownVT(const CodeGenTarget &TargetInfo) const; /// FlattenAsmStringVariants - Flatten the specified AsmString to only /// include text from the specified variant, returning the new string. diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp index 8d0ec9a..65a2594 100644 --- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp +++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp @@ -734,8 +734,8 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, if (const Record *RV = R->getValueAsOptionalDef("RegInfos")) RSI = RegSizeInfoByHwMode(RV, RegBank.getHwModes()); unsigned Size = R->getValueAsInt("Size"); - assert((RSI.hasDefault() || Size != 0 || VTs[0].isSimple()) && - "Impossible to determine register size"); + if (!RSI.hasDefault() && Size == 0 && !VTs[0].isSimple()) + PrintFatalError(R->getLoc(), "Impossible to determine register size"); if (!RSI.hasDefault()) { RegSizeInfo RI; RI.RegSize = RI.SpillSize = @@ -1316,11 +1316,19 @@ CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC, return {&RegClasses.back(), true}; } -CodeGenRegisterClass *CodeGenRegBank::getRegClass(const Record *Def) const { +CodeGenRegisterClass *CodeGenRegBank::getRegClass(const Record *Def, + ArrayRef<SMLoc> Loc) const { + assert(Def->isSubClassOf("RegisterClassLike")); if (CodeGenRegisterClass *RC = Def2RC.lookup(Def)) return RC; - PrintFatalError(Def->getLoc(), "Not a known RegisterClass!"); + ArrayRef<SMLoc> DiagLoc = Loc.empty() ? Def->getLoc() : Loc; + // TODO: Ideally we should update the API to allow resolving HwMode. + if (Def->isSubClassOf("RegClassByHwMode")) + PrintError(DiagLoc, "cannot resolve HwMode for " + Def->getName()); + else + PrintError(DiagLoc, Def->getName() + " is not a known RegisterClass!"); + PrintFatalNote(Def->getLoc(), Def->getName() + " defined here"); } CodeGenSubRegIndex * @@ -1651,8 +1659,7 @@ template <> struct llvm::GraphTraits<SubRegIndexCompositionGraph> { struct ChildIteratorType : public iterator_adaptor_base< ChildIteratorType, CompMapIt, - typename std::iterator_traits<CompMapIt>::iterator_category, - NodeRef> { + std::iterator_traits<CompMapIt>::iterator_category, NodeRef> { ChildIteratorType(CompMapIt I) : ChildIteratorType::iterator_adaptor_base(I) {} @@ -2164,7 +2171,7 @@ void CodeGenRegBank::computeRegUnitLaneMasks() { CodeGenRegister::RegUnitLaneMaskList RegUnitLaneMasks( RegUnits.count(), LaneBitmask::getAll()); // Iterate through SubRegisters. - typedef CodeGenRegister::SubRegMap SubRegMap; + using SubRegMap = CodeGenRegister::SubRegMap; const SubRegMap &SubRegs = Register.getSubRegs(); for (auto [SubRegIndex, SubReg] : SubRegs) { // Ignore non-leaf subregisters, their lane masks are fully covered by @@ -2283,9 +2290,8 @@ void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) { // void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) { // Map SubRegIndex to set of registers in RC supporting that SubRegIndex. - typedef std::map<const CodeGenSubRegIndex *, CodeGenRegister::Vec, - deref<std::less<>>> - SubReg2SetMap; + using SubReg2SetMap = std::map<const CodeGenSubRegIndex *, + CodeGenRegister::Vec, deref<std::less<>>>; // Compute the set of registers supporting each SubRegIndex. SubReg2SetMap SRSets; diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h index 89dac12..a3ad0b7 100644 --- a/llvm/utils/TableGen/Common/CodeGenRegisters.h +++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h @@ -93,9 +93,8 @@ public: std::string getQualifiedName() const; // Map of composite subreg indices. - typedef std::map<CodeGenSubRegIndex *, CodeGenSubRegIndex *, - deref<std::less<>>> - CompMap; + using CompMap = + std::map<CodeGenSubRegIndex *, CodeGenSubRegIndex *, deref<std::less<>>>; // Returns the subreg index that results from composing this with Idx. // Returns NULL if this and Idx don't compose. @@ -180,8 +179,8 @@ public: bool Constant = false; // Map SubRegIndex -> Register. - typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *, deref<std::less<>>> - SubRegMap; + using SubRegMap = + std::map<CodeGenSubRegIndex *, CodeGenRegister *, deref<std::less<>>>; CodeGenRegister(const Record *R, unsigned Enum); @@ -220,7 +219,7 @@ public: return SubReg2Idx.lookup(Reg); } - typedef std::vector<const CodeGenRegister *> SuperRegList; + using SuperRegList = std::vector<const CodeGenRegister *>; // Get the list of super-registers in topological order, small to large. // This is valid after computeSubRegs visits all registers during RegBank @@ -248,8 +247,8 @@ public: } // List of register units in ascending order. - typedef SparseBitVector<> RegUnitList; - typedef SmallVector<LaneBitmask, 16> RegUnitLaneMaskList; + using RegUnitList = SparseBitVector<>; + using RegUnitLaneMaskList = SmallVector<LaneBitmask, 16>; // How many entries in RegUnitList are native? RegUnitList NativeRegUnits; @@ -281,7 +280,7 @@ public: unsigned getWeight(const CodeGenRegBank &RegBank) const; // Canonically ordered set. - typedef std::vector<const CodeGenRegister *> Vec; + using Vec = std::vector<const CodeGenRegister *>; private: bool SubRegsComplete; @@ -590,7 +589,7 @@ struct RegUnit { // Each RegUnitSet is a sorted vector with a name. struct RegUnitSet { - typedef std::vector<unsigned>::const_iterator iterator; + using iterator = std::vector<unsigned>::const_iterator; std::string Name; std::vector<unsigned> Units; @@ -602,7 +601,7 @@ struct RegUnitSet { // Base vector for identifying TopoSigs. The contents uniquely identify a // TopoSig, only computeSuperRegs needs to know how. -typedef SmallVector<unsigned, 16> TopoSigId; +using TopoSigId = SmallVector<unsigned, 16>; // CodeGenRegBank - Represent a target's registers and the relations between // them. @@ -621,8 +620,8 @@ class CodeGenRegBank { CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace); - typedef std::map<SmallVector<CodeGenSubRegIndex *, 8>, CodeGenSubRegIndex *> - ConcatIdxMap; + using ConcatIdxMap = + std::map<SmallVector<CodeGenSubRegIndex *, 8>, CodeGenSubRegIndex *>; ConcatIdxMap ConcatIdx; // Registers. @@ -639,7 +638,7 @@ class CodeGenRegBank { // Register classes. std::list<CodeGenRegisterClass> RegClasses; DenseMap<const Record *, CodeGenRegisterClass *> Def2RC; - typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass *> RCKeyMap; + using RCKeyMap = std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass *>; RCKeyMap Key2RC; // Register categories. @@ -816,7 +815,8 @@ public: } // Find a register class from its def. - CodeGenRegisterClass *getRegClass(const Record *) const; + CodeGenRegisterClass *getRegClass(const Record *, + ArrayRef<SMLoc> Loc = {}) const; /// getRegisterClassForRegister - Find the register class that contains the /// specified physical register. If the register is not in a register diff --git a/llvm/utils/TableGen/Common/CodeGenTarget.cpp b/llvm/utils/TableGen/Common/CodeGenTarget.cpp index 3db0d07..cca318a 100644 --- a/llvm/utils/TableGen/Common/CodeGenTarget.cpp +++ b/llvm/utils/TableGen/Common/CodeGenTarget.cpp @@ -18,12 +18,12 @@ #include "CodeGenRegisters.h" #include "CodeGenSchedule.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/StringSwitch.h" #include "llvm/ADT/Twine.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/TableGen/Error.h" #include "llvm/TableGen/Record.h" -#include <iterator> #include <tuple> using namespace llvm; @@ -40,18 +40,24 @@ static cl::opt<unsigned> cl::desc("Make -gen-asm-writer emit assembly writer #N"), cl::cat(AsmWriterCat)); -/// getValueType - Return the MVT::SimpleValueType that the specified TableGen +/// Returns the MVT that the specified TableGen /// record corresponds to. -MVT::SimpleValueType llvm::getValueType(const Record *Rec) { - return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); +MVT llvm::getValueType(const Record *Rec) { + return StringSwitch<MVT>(Rec->getValueAsString("LLVMName")) +#define GET_VT_ATTR(Ty, Sz, Any, Int, FP, Vec, Sc, Tup, NF, NElem, EltTy) \ + .Case(#Ty, MVT::Ty) +#include "llvm/CodeGen/GenVT.inc" +#undef GET_VT_ATTR + .Case("INVALID_SIMPLE_VALUE_TYPE", MVT::INVALID_SIMPLE_VALUE_TYPE); } -StringRef llvm::getEnumName(MVT::SimpleValueType T) { +StringRef llvm::getEnumName(MVT T) { // clang-format off - switch (T) { -#define GET_VT_ATTR(Ty, N, Sz, Any, Int, FP, Vec, Sc, Tup, NF, NElem, EltTy) \ + switch (T.SimpleTy) { +#define GET_VT_ATTR(Ty, Sz, Any, Int, FP, Vec, Sc, Tup, NF, NElem, EltTy) \ case MVT::Ty: return "MVT::" # Ty; #include "llvm/CodeGen/GenVT.inc" +#undef GET_VT_ATTR default: llvm_unreachable("ILLEGAL VALUE TYPE!"); } // clang-format on @@ -80,7 +86,7 @@ CodeGenTarget::CodeGenTarget(const RecordKeeper &records) MacroFusions = Records.getAllDerivedDefinitions("Fusion"); } -CodeGenTarget::~CodeGenTarget() {} +CodeGenTarget::~CodeGenTarget() = default; StringRef CodeGenTarget::getName() const { return TargetRec->getName(); } @@ -167,8 +173,8 @@ const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { } const CodeGenRegisterClass & -CodeGenTarget::getRegisterClass(const Record *R) const { - return *getRegBank().getRegClass(R); +CodeGenTarget::getRegisterClass(const Record *R, ArrayRef<SMLoc> Loc) const { + return *getRegBank().getRegClass(R, Loc); } std::vector<ValueTypeByHwMode> @@ -221,12 +227,14 @@ const Record *CodeGenTarget::getInitValueAsRegClassLike(const Init *V) const { const DefInit *VDefInit = dyn_cast<DefInit>(V); if (!VDefInit) return nullptr; + return getAsRegClassLike(VDefInit->getDef()); +} - const Record *RegClass = VDefInit->getDef(); - if (RegClass->isSubClassOf("RegisterOperand")) - return RegClass->getValueAsDef("RegClass"); +const Record *CodeGenTarget::getAsRegClassLike(const Record *Rec) const { + if (Rec->isSubClassOf("RegisterOperand")) + return Rec->getValueAsDef("RegClass"); - return RegClass->isSubClassOf("RegisterClassLike") ? RegClass : nullptr; + return Rec->isSubClassOf("RegisterClassLike") ? Rec : nullptr; } CodeGenSchedModels &CodeGenTarget::getSchedModels() const { @@ -284,15 +292,25 @@ void CodeGenTarget::ComputeInstrsByEnum() const { assert(EndOfPredefines == getNumFixedInstructions() && "Missing generic opcode"); + [[maybe_unused]] unsigned SkippedInsts = 0; + for (const auto &[_, CGIUp] : InstMap) { const CodeGenInstruction *CGI = CGIUp.get(); if (CGI->Namespace != "TargetOpcode") { + + if (CGI->TheDef->isSubClassOf( + "TargetSpecializedStandardPseudoInstruction")) { + ++SkippedInsts; + continue; + } + InstrsByEnum.push_back(CGI); NumPseudoInstructions += CGI->TheDef->getValueAsBit("isPseudo"); } } - assert(InstrsByEnum.size() == InstMap.size() && "Missing predefined instr"); + assert(InstrsByEnum.size() + SkippedInsts == InstMap.size() && + "Missing predefined instr"); // All of the instructions are now in random order based on the map iteration. llvm::sort( diff --git a/llvm/utils/TableGen/Common/CodeGenTarget.h b/llvm/utils/TableGen/Common/CodeGenTarget.h index b6f9d42..dc1740b 100644 --- a/llvm/utils/TableGen/Common/CodeGenTarget.h +++ b/llvm/utils/TableGen/Common/CodeGenTarget.h @@ -28,7 +28,6 @@ #include "llvm/CodeGenTypes/MachineValueType.h" #include <cassert> #include <memory> -#include <optional> #include <string> #include <vector> @@ -42,11 +41,11 @@ class CodeGenRegisterClass; class CodeGenSchedModels; class CodeGenSubRegIndex; -/// getValueType - Return the MVT::SimpleValueType that the specified TableGen +/// Returns the MVT that the specified TableGen /// record corresponds to. -MVT::SimpleValueType getValueType(const Record *Rec); +MVT getValueType(const Record *Rec); -StringRef getEnumName(MVT::SimpleValueType T); +StringRef getEnumName(MVT T); /// getQualifiedName - Return the name of the specified record, with a /// namespace qualifier if the record contains one. @@ -132,7 +131,8 @@ public: return RegAltNameIndices; } - const CodeGenRegisterClass &getRegisterClass(const Record *R) const; + const CodeGenRegisterClass &getRegisterClass(const Record *R, + ArrayRef<SMLoc> Loc = {}) const; /// Convenience wrapper to avoid hardcoding the name of RegClassByHwMode /// everywhere. This is here instead of CodeGenRegBank to avoid the fatal @@ -166,6 +166,7 @@ public: /// return the Record. This is used as a convenience function to handle direct /// RegisterClass references, or those wrapped in a RegisterOperand. const Record *getInitValueAsRegClassLike(const Init *V) const; + const Record *getAsRegClassLike(const Record *V) const; CodeGenSchedModels &getSchedModels() const; diff --git a/llvm/utils/TableGen/Common/DAGISelMatcher.cpp b/llvm/utils/TableGen/Common/DAGISelMatcher.cpp index 4fdb386..6f03989 100644 --- a/llvm/utils/TableGen/Common/DAGISelMatcher.cpp +++ b/llvm/utils/TableGen/Common/DAGISelMatcher.cpp @@ -286,7 +286,7 @@ void EmitNodeMatcherCommon::printImpl(raw_ostream &OS, indent Indent) const { OS << (isa<MorphNodeToMatcher>(this) ? "MorphNodeTo: " : "EmitNode: ") << CGI.Namespace << "::" << CGI.getName() << ": <todo flags> "; - for (MVT::SimpleValueType VT : VTs) + for (MVT VT : VTs) OS << ' ' << getEnumName(VT); OS << '('; for (unsigned Operand : Operands) @@ -321,8 +321,7 @@ void MorphNodeToMatcher::anchor() {} // isContradictoryImpl Implementations. -static bool TypesAreContradictory(MVT::SimpleValueType T1, - MVT::SimpleValueType T2) { +static bool TypesAreContradictory(MVT T1, MVT T2) { // If the two types are the same, then they are the same, so they don't // contradict. if (T1 == T2) @@ -339,16 +338,16 @@ static bool TypesAreContradictory(MVT::SimpleValueType T1, // If either type is about iPtr, then they don't conflict unless the other // one is not a scalar integer type. if (T1 == MVT::iPTR) - return !MVT(T2).isInteger() || MVT(T2).isVector(); + return !T2.isInteger() || T2.isVector(); if (T2 == MVT::iPTR) - return !MVT(T1).isInteger() || MVT(T1).isVector(); + return !T1.isInteger() || T1.isVector(); if (T1 == MVT::cPTR) - return !MVT(T2).isCheriCapability() || MVT(T2).isVector(); + return !T2.isCheriCapability() || T2.isVector(); if (T2 == MVT::cPTR) - return !MVT(T1).isCheriCapability() || MVT(T1).isVector(); + return !T1.isCheriCapability() || T1.isVector(); // Otherwise, they are two different non-iPTR/cPTR types, they conflict. return true; @@ -370,7 +369,7 @@ bool CheckOpcodeMatcher::isContradictoryImpl(const Matcher *M) const { if (CT->getResNo() >= getOpcode().getNumResults()) return true; - MVT::SimpleValueType NodeType = getOpcode().getKnownType(CT->getResNo()); + MVT NodeType = getOpcode().getKnownType(CT->getResNo()); if (NodeType != MVT::Other) return TypesAreContradictory(NodeType, CT->getType()); } diff --git a/llvm/utils/TableGen/Common/DAGISelMatcher.h b/llvm/utils/TableGen/Common/DAGISelMatcher.h index f87de75..e947dac 100644 --- a/llvm/utils/TableGen/Common/DAGISelMatcher.h +++ b/llvm/utils/TableGen/Common/DAGISelMatcher.h @@ -105,7 +105,7 @@ protected: Matcher(KindTy K) : Kind(K) {} public: - virtual ~Matcher() {} + virtual ~Matcher() = default; unsigned getSize() const { return Size; } void setSize(unsigned sz) { Size = sz; } @@ -517,14 +517,14 @@ private: /// CheckTypeMatcher - This checks to see if the current node has the /// specified type at the specified result, if not it fails to match. class CheckTypeMatcher : public Matcher { - MVT::SimpleValueType Type; + MVT Type; unsigned ResNo; public: - CheckTypeMatcher(MVT::SimpleValueType type, unsigned resno) + CheckTypeMatcher(MVT type, unsigned resno) : Matcher(CheckType), Type(type), ResNo(resno) {} - MVT::SimpleValueType getType() const { return Type; } + MVT getType() const { return Type; } unsigned getResNo() const { return ResNo; } static bool classof(const Matcher *N) { return N->getKind() == CheckType; } @@ -542,11 +542,10 @@ private: /// then the match fails. This is semantically equivalent to a Scope node where /// every child does a CheckType, but is much faster. class SwitchTypeMatcher : public Matcher { - SmallVector<std::pair<MVT::SimpleValueType, Matcher *>, 8> Cases; + SmallVector<std::pair<MVT, Matcher *>, 8> Cases; public: - SwitchTypeMatcher( - SmallVectorImpl<std::pair<MVT::SimpleValueType, Matcher *>> &&cases) + SwitchTypeMatcher(SmallVectorImpl<std::pair<MVT, Matcher *>> &&cases) : Matcher(SwitchType), Cases(std::move(cases)) {} ~SwitchTypeMatcher() override; @@ -554,7 +553,7 @@ public: unsigned getNumCases() const { return Cases.size(); } - MVT::SimpleValueType getCaseType(unsigned i) const { return Cases[i].first; } + MVT getCaseType(unsigned i) const { return Cases[i].first; } Matcher *getCaseMatcher(unsigned i) { return Cases[i].second; } const Matcher *getCaseMatcher(unsigned i) const { return Cases[i].second; } @@ -567,14 +566,14 @@ private: /// specified type, if not it fails to match. class CheckChildTypeMatcher : public Matcher { unsigned ChildNo; - MVT::SimpleValueType Type; + MVT Type; public: - CheckChildTypeMatcher(unsigned childno, MVT::SimpleValueType type) + CheckChildTypeMatcher(unsigned childno, MVT type) : Matcher(CheckChildType), ChildNo(childno), Type(type) {} unsigned getChildNo() const { return ChildNo; } - MVT::SimpleValueType getType() const { return Type; } + MVT getType() const { return Type; } static bool classof(const Matcher *N) { return N->getKind() == CheckChildType; @@ -684,13 +683,12 @@ private: /// CheckValueTypeMatcher - This checks to see if the current node is a /// VTSDNode with the specified type, if not it fails to match. class CheckValueTypeMatcher : public Matcher { - MVT::SimpleValueType VT; + MVT VT; public: - CheckValueTypeMatcher(MVT::SimpleValueType SimpleVT) - : Matcher(CheckValueType), VT(SimpleVT) {} + CheckValueTypeMatcher(MVT SimpleVT) : Matcher(CheckValueType), VT(SimpleVT) {} - MVT::SimpleValueType getVT() const { return VT; } + MVT getVT() const { return VT; } static bool classof(const Matcher *N) { return N->getKind() == CheckValueType; @@ -832,18 +830,18 @@ private: /// EmitIntegerMatcher - This creates a new TargetConstant. class EmitIntegerMatcher : public Matcher { int64_t Val; - MVT::SimpleValueType VT; + MVT VT; unsigned ResultNo; public: - EmitIntegerMatcher(int64_t val, MVT::SimpleValueType vt, unsigned resultNo) + EmitIntegerMatcher(int64_t val, MVT vt, unsigned resultNo) : Matcher(EmitInteger), Val(SignExtend64(val, MVT(vt).getFixedSizeInBits())), VT(vt), ResultNo(resultNo) {} int64_t getValue() const { return Val; } - MVT::SimpleValueType getVT() const { return VT; } + MVT getVT() const { return VT; } unsigned getResultNo() const { return ResultNo; } static bool classof(const Matcher *N) { return N->getKind() == EmitInteger; } @@ -860,17 +858,16 @@ private: /// by a string. class EmitStringIntegerMatcher : public Matcher { std::string Val; - MVT::SimpleValueType VT; + MVT VT; unsigned ResultNo; public: - EmitStringIntegerMatcher(const std::string &val, MVT::SimpleValueType vt, - unsigned resultNo) + EmitStringIntegerMatcher(const std::string &val, MVT vt, unsigned resultNo) : Matcher(EmitStringInteger), Val(val), VT(vt), ResultNo(resultNo) {} const std::string &getValue() const { return Val; } - MVT::SimpleValueType getVT() const { return VT; } + MVT getVT() const { return VT; } unsigned getResultNo() const { return ResultNo; } static bool classof(const Matcher *N) { @@ -890,17 +887,16 @@ class EmitRegisterMatcher : public Matcher { /// Reg - The def for the register that we're emitting. If this is null, then /// this is a reference to zero_reg. const CodeGenRegister *Reg; - MVT::SimpleValueType VT; + MVT VT; unsigned ResultNo; public: - EmitRegisterMatcher(const CodeGenRegister *reg, MVT::SimpleValueType vt, - unsigned resultNo) + EmitRegisterMatcher(const CodeGenRegister *reg, MVT vt, unsigned resultNo) : Matcher(EmitRegister), Reg(reg), VT(vt), ResultNo(resultNo) {} const CodeGenRegister *getReg() const { return Reg; } - MVT::SimpleValueType getVT() const { return VT; } + MVT getVT() const { return VT; } unsigned getResultNo() const { return ResultNo; } static bool classof(const Matcher *N) { return N->getKind() == EmitRegister; } @@ -1028,7 +1024,7 @@ private: /// MorphNodeTo. class EmitNodeMatcherCommon : public Matcher { const CodeGenInstruction &CGI; - const SmallVector<MVT::SimpleValueType, 3> VTs; + const SmallVector<MVT, 3> VTs; const SmallVector<unsigned, 6> Operands; bool HasChain, HasInGlue, HasOutGlue, HasMemRefs; @@ -1038,8 +1034,7 @@ class EmitNodeMatcherCommon : public Matcher { int NumFixedArityOperands; public: - EmitNodeMatcherCommon(const CodeGenInstruction &cgi, - ArrayRef<MVT::SimpleValueType> vts, + EmitNodeMatcherCommon(const CodeGenInstruction &cgi, ArrayRef<MVT> vts, ArrayRef<unsigned> operands, bool hasChain, bool hasInGlue, bool hasOutGlue, bool hasmemrefs, int numfixedarityoperands, bool isMorphNodeTo) @@ -1051,7 +1046,7 @@ public: const CodeGenInstruction &getInstruction() const { return CGI; } unsigned getNumVTs() const { return VTs.size(); } - MVT::SimpleValueType getVT(unsigned i) const { + MVT getVT(unsigned i) const { assert(i < VTs.size()); return VTs[i]; } @@ -1062,7 +1057,7 @@ public: return Operands[i]; } - const SmallVectorImpl<MVT::SimpleValueType> &getVTList() const { return VTs; } + const SmallVectorImpl<MVT> &getVTList() const { return VTs; } const SmallVectorImpl<unsigned> &getOperandList() const { return Operands; } bool hasChain() const { return HasChain; } @@ -1086,8 +1081,7 @@ class EmitNodeMatcher : public EmitNodeMatcherCommon { unsigned FirstResultSlot; public: - EmitNodeMatcher(const CodeGenInstruction &cgi, - ArrayRef<MVT::SimpleValueType> vts, + EmitNodeMatcher(const CodeGenInstruction &cgi, ArrayRef<MVT> vts, ArrayRef<unsigned> operands, bool hasChain, bool hasInGlue, bool hasOutGlue, bool hasmemrefs, int numfixedarityoperands, unsigned firstresultslot) @@ -1106,8 +1100,7 @@ class MorphNodeToMatcher : public EmitNodeMatcherCommon { const PatternToMatch &Pattern; public: - MorphNodeToMatcher(const CodeGenInstruction &cgi, - ArrayRef<MVT::SimpleValueType> vts, + MorphNodeToMatcher(const CodeGenInstruction &cgi, ArrayRef<MVT> vts, ArrayRef<unsigned> operands, bool hasChain, bool hasInGlue, bool hasOutGlue, bool hasmemrefs, int numfixedarityoperands, const PatternToMatch &pattern) diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp index 5d49715..8540fae 100644 --- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp +++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp @@ -440,9 +440,7 @@ bool LLTCodeGen::operator<(const LLTCodeGen &Other) const { //===- LLTCodeGen Helpers -------------------------------------------------===// -std::optional<LLTCodeGen> llvm::gi::MVTToLLT(MVT::SimpleValueType SVT) { - MVT VT(SVT); - +std::optional<LLTCodeGen> llvm::gi::MVTToLLT(MVT VT) { if (VT.isVector() && !VT.getVectorElementCount().isScalar()) return LLTCodeGen( LLT::vector(VT.getVectorElementCount(), VT.getScalarSizeInBits())); @@ -457,7 +455,7 @@ std::optional<LLTCodeGen> llvm::gi::MVTToLLT(MVT::SimpleValueType SVT) { void Matcher::optimize() {} -Matcher::~Matcher() {} +Matcher::~Matcher() = default; //===- GroupMatcher -------------------------------------------------------===// @@ -1150,11 +1148,11 @@ void RuleMatcher::insnmatchers_pop_front() { Matchers.erase(Matchers.begin()); } //===- PredicateMatcher ---------------------------------------------------===// -PredicateMatcher::~PredicateMatcher() {} +PredicateMatcher::~PredicateMatcher() = default; //===- OperandPredicateMatcher --------------------------------------------===// -OperandPredicateMatcher::~OperandPredicateMatcher() {} +OperandPredicateMatcher::~OperandPredicateMatcher() = default; bool OperandPredicateMatcher::isHigherPriorityThan( const OperandPredicateMatcher &B) const { @@ -1941,7 +1939,7 @@ bool InstructionOperandMatcher::isHigherPriorityThan( //===- OperandRenderer ----------------------------------------------------===// -OperandRenderer::~OperandRenderer() {} +OperandRenderer::~OperandRenderer() = default; //===- CopyRenderer -------------------------------------------------------===// diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h index 0f1241e..6a80178 100644 --- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h +++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h @@ -267,7 +267,7 @@ extern std::set<LLTCodeGen> KnownTypes; /// Convert an MVT to an equivalent LLT if possible, or the invalid LLT() for /// MVTs that don't map cleanly to an LLT (e.g., iPTR, *any, ...). -std::optional<LLTCodeGen> MVTToLLT(MVT::SimpleValueType SVT); +std::optional<LLTCodeGen> MVTToLLT(MVT VT); using TempTypeIdx = int64_t; class LLTCodeGenOrTempType { @@ -528,10 +528,10 @@ protected: ArrayRef<SMLoc> SrcLoc; - typedef std::tuple<const Record *, unsigned, unsigned> - DefinedComplexPatternSubOperand; - typedef StringMap<DefinedComplexPatternSubOperand> - DefinedComplexPatternSubOperandMap; + using DefinedComplexPatternSubOperand = + std::tuple<const Record *, unsigned, unsigned>; + using DefinedComplexPatternSubOperandMap = + StringMap<DefinedComplexPatternSubOperand>; /// A map of Symbolic Names to ComplexPattern sub-operands. DefinedComplexPatternSubOperandMap ComplexSubOperands; /// A map used to for multiple referenced error check of ComplexSubOperand. @@ -621,7 +621,7 @@ public: DefinedInsnVariablesMap::const_iterator defined_insn_vars_end() const { return InsnVariableIDs.end(); } - iterator_range<typename DefinedInsnVariablesMap::const_iterator> + iterator_range<DefinedInsnVariablesMap::const_iterator> defined_insn_vars() const { return make_range(defined_insn_vars_begin(), defined_insn_vars_end()); } @@ -632,8 +632,7 @@ public: MutatableInsnSet::const_iterator mutatable_insns_end() const { return MutatableInsns.end(); } - iterator_range<typename MutatableInsnSet::const_iterator> - mutatable_insns() const { + iterator_range<MutatableInsnSet::const_iterator> mutatable_insns() const { return make_range(mutatable_insns_begin(), mutatable_insns_end()); } void reserveInsnMatcherForMutation(InstructionMatcher *InsnMatcher) { @@ -1375,7 +1374,7 @@ class InstructionPredicateMatcher : public PredicateMatcher { public: InstructionPredicateMatcher(PredicateKind Kind, unsigned InsnVarID) : PredicateMatcher(Kind, InsnVarID) {} - ~InstructionPredicateMatcher() override {} + ~InstructionPredicateMatcher() override = default; /// Compare the priority of this object and B. /// @@ -1776,7 +1775,7 @@ public: /// * Has an nsw/nuw flag or doesn't. class InstructionMatcher final : public PredicateListMatcher<PredicateMatcher> { protected: - typedef std::vector<std::unique_ptr<OperandMatcher>> OperandVec; + using OperandVec = std::vector<std::unique_ptr<OperandMatcher>>; RuleMatcher &Rule; @@ -2319,7 +2318,7 @@ public: ActionKind getKind() const { return Kind; } - virtual ~MatchAction() {} + virtual ~MatchAction() = default; // Some actions may need to add extra predicates to ensure they can run. virtual void emitAdditionalPredicates(MatchTable &Table, diff --git a/llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp b/llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp index ad5089d..8e4a850 100644 --- a/llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp +++ b/llvm/utils/TableGen/Common/GlobalISel/PatternParser.cpp @@ -113,7 +113,8 @@ PatternParser::parseInstructionPattern(const Init &Arg, StringRef Name) { std::unique_ptr<InstructionPattern> Pat; if (const DagInit *IP = getDagWithOperatorOfSubClass(Arg, "Instruction")) { - auto &Instr = CGT.getInstruction(IP->getOperatorAsDef(DiagLoc)); + const CodeGenInstruction &Instr = + CGT.getInstruction(IP->getOperatorAsDef(DiagLoc)); Pat = std::make_unique<CodeGenInstructionPattern>(Instr, insertStrRef(Name)); } else if (const DagInit *IP = diff --git a/llvm/utils/TableGen/Common/InfoByHwMode.cpp b/llvm/utils/TableGen/Common/InfoByHwMode.cpp index 4c8197d..a16fdbb 100644 --- a/llvm/utils/TableGen/Common/InfoByHwMode.cpp +++ b/llvm/utils/TableGen/Common/InfoByHwMode.cpp @@ -174,7 +174,7 @@ bool RegSizeInfoByHwMode::hasStricterSpillThan( } void RegSizeInfoByHwMode::writeToStream(raw_ostream &OS) const { - typedef typename decltype(Map)::value_type PairType; + using PairType = decltype(Map)::value_type; std::vector<const PairType *> Pairs; for (const auto &P : Map) Pairs.push_back(&P); diff --git a/llvm/utils/TableGen/Common/InfoByHwMode.h b/llvm/utils/TableGen/Common/InfoByHwMode.h index c730b73..bd24fb8 100644 --- a/llvm/utils/TableGen/Common/InfoByHwMode.h +++ b/llvm/utils/TableGen/Common/InfoByHwMode.h @@ -24,7 +24,6 @@ #include <map> #include <string> #include <tuple> -#include <utility> namespace llvm { @@ -87,10 +86,10 @@ void union_modes(const InfoByHwMode<InfoT> &A, const InfoByHwMode<InfoT> &B, } template <typename InfoT> struct InfoByHwMode { - typedef std::map<unsigned, InfoT> MapType; - typedef typename MapType::value_type PairType; - typedef typename MapType::iterator iterator; - typedef typename MapType::const_iterator const_iterator; + using MapType = std::map<unsigned, InfoT>; + using PairType = typename MapType::value_type; + using iterator = typename MapType::iterator; + using const_iterator = typename MapType::const_iterator; InfoByHwMode() = default; InfoByHwMode(const MapType &M) : Map(M) {} @@ -104,6 +103,8 @@ template <typename InfoT> struct InfoByHwMode { LLVM_ATTRIBUTE_ALWAYS_INLINE const_iterator end() const { return Map.end(); } LLVM_ATTRIBUTE_ALWAYS_INLINE + size_t size() const { return Map.size(); } + LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const { return Map.empty(); } LLVM_ATTRIBUTE_ALWAYS_INLINE diff --git a/llvm/utils/TableGen/Common/InstructionEncoding.cpp b/llvm/utils/TableGen/Common/InstructionEncoding.cpp index 30bbac4..e9c2d93 100644 --- a/llvm/utils/TableGen/Common/InstructionEncoding.cpp +++ b/llvm/utils/TableGen/Common/InstructionEncoding.cpp @@ -35,9 +35,6 @@ InstructionEncoding::findOperandDecoderMethod(const Record *Record) { Decoder = "Decode" + Record->getName().str() + "RegisterClass"; } else if (Record->isSubClassOf("RegClassByHwMode")) { Decoder = "Decode" + Record->getName().str() + "RegClassByHwMode"; - } else if (Record->isSubClassOf("PointerLikeRegClass")) { - Decoder = "DecodePointerLikeRegClass" + - utostr(Record->getValueAsInt("RegClassKind")); } return {Decoder, true}; |