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-rw-r--r--llvm/unittests/CodeGen/AsmPrinterDwarfTest.cpp2
-rw-r--r--llvm/unittests/CodeGen/CMakeLists.txt2
-rw-r--r--llvm/unittests/CodeGen/GlobalISel/InstructionSelectTest.cpp2
-rw-r--r--llvm/unittests/CodeGen/InstrRefLDVTest.cpp36
-rw-r--r--llvm/unittests/CodeGen/MFCommon.inc17
-rw-r--r--llvm/unittests/CodeGen/MLRegAllocDevelopmentFeatures.cpp293
-rw-r--r--llvm/unittests/CodeGen/MachineOperandTest.cpp37
-rw-r--r--llvm/unittests/CodeGen/RegisterTest.cpp38
-rw-r--r--llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp74
9 files changed, 179 insertions, 322 deletions
diff --git a/llvm/unittests/CodeGen/AsmPrinterDwarfTest.cpp b/llvm/unittests/CodeGen/AsmPrinterDwarfTest.cpp
index af2d56d..d0991e6 100644
--- a/llvm/unittests/CodeGen/AsmPrinterDwarfTest.cpp
+++ b/llvm/unittests/CodeGen/AsmPrinterDwarfTest.cpp
@@ -383,7 +383,7 @@ class AsmPrinterHandlerTest : public AsmPrinterFixtureBase {
public:
TestHandler(AsmPrinterHandlerTest &Test) : Test(Test) {}
- ~TestHandler() override {}
+ ~TestHandler() override = default;
void setSymbolSize(const MCSymbol *Sym, uint64_t Size) override {}
void beginModule(Module *M) override { Test.BeginCount++; }
void endModule() override { Test.EndCount++; }
diff --git a/llvm/unittests/CodeGen/CMakeLists.txt b/llvm/unittests/CodeGen/CMakeLists.txt
index 18332d2..80d1013 100644
--- a/llvm/unittests/CodeGen/CMakeLists.txt
+++ b/llvm/unittests/CodeGen/CMakeLists.txt
@@ -39,6 +39,7 @@ add_llvm_unittest(CodeGenTests
MachineOperandTest.cpp
MIR2VecTest.cpp
RegAllocScoreTest.cpp
+ RegisterTest.cpp
PassManagerTest.cpp
ScalableVectorMVTsTest.cpp
SchedBoundary.cpp
@@ -48,7 +49,6 @@ add_llvm_unittest(CodeGenTests
TypeTraitsTest.cpp
TargetOptionsTest.cpp
TestAsmPrinter.cpp
- MLRegAllocDevelopmentFeatures.cpp
X86MCInstLowerTest.cpp
)
diff --git a/llvm/unittests/CodeGen/GlobalISel/InstructionSelectTest.cpp b/llvm/unittests/CodeGen/GlobalISel/InstructionSelectTest.cpp
index 7fbccf7..2237983 100644
--- a/llvm/unittests/CodeGen/GlobalISel/InstructionSelectTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/InstructionSelectTest.cpp
@@ -59,10 +59,8 @@ TEST_F(AArch64GISelMITest, TestInstructionSelectErase) {
GTEST_SKIP();
legacy::PassManager PM;
- std::unique_ptr<TargetPassConfig> TPC(TM->createPassConfig(PM));
EraseMockInstructionSelector ISel;
- ISel.TPC = TPC.get();
for (auto &MI : *EntryMBB) {
ISel.MIs.push_back(&MI);
}
diff --git a/llvm/unittests/CodeGen/InstrRefLDVTest.cpp b/llvm/unittests/CodeGen/InstrRefLDVTest.cpp
index ff87e7b..5211a6c 100644
--- a/llvm/unittests/CodeGen/InstrRefLDVTest.cpp
+++ b/llvm/unittests/CodeGen/InstrRefLDVTest.cpp
@@ -955,7 +955,7 @@ TEST_F(InstrRefLDVTest, MLocSingleBlock) {
// Add a new register to be tracked, and insert it into the transfer function
// as a copy. The output of $rax should be the live-in value of $rsp.
Register RAX = getRegByName("RAX");
- LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX);
+ LocIdx RaxLoc = MTracker->lookupOrTrackRegister(MTracker->getLocID(RAX));
TransferFunc[0].insert({RspLoc, ValueIDNum(0, 1, RspLoc)});
TransferFunc[0].insert({RaxLoc, ValueIDNum(0, 0, RspLoc)});
initValueArray(MInLocs, 1, 2);
@@ -980,7 +980,7 @@ TEST_F(InstrRefLDVTest, MLocDiamondBlocks) {
ASSERT_TRUE(MTracker->getNumLocs() == 1);
LocIdx RspLoc(0);
Register RAX = getRegByName("RAX");
- LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX);
+ LocIdx RaxLoc = MTracker->lookupOrTrackRegister(MTracker->getLocID(RAX));
auto [MInLocs, MOutLocs] = allocValueTables(4, 2);
@@ -1113,7 +1113,7 @@ TEST_F(InstrRefLDVTest, MLocDiamondSpills) {
// Create a stack location and ensure it's tracked.
SpillLoc SL = {getRegByName("RSP"), StackOffset::getFixed(-8)};
SpillLocationNo SpillNo = *MTracker->getOrTrackSpillLoc(SL);
- ASSERT_EQ(MTracker->getNumLocs(), 13u); // Tracks all possible stack locs.
+ ASSERT_EQ(MTracker->getNumLocs(), 11u); // Tracks all possible stack locs.
// Locations are: RSP, stack slots from 2^3 bits wide up to 2^9 for zmm regs,
// then slots for sub_8bit_hi and sub_16bit_hi ({8, 8} and {16, 16}).
// Finally, one for spilt fp80 registers.
@@ -1194,7 +1194,7 @@ TEST_F(InstrRefLDVTest, MLocSimpleLoop) {
ASSERT_TRUE(MTracker->getNumLocs() == 1);
LocIdx RspLoc(0);
Register RAX = getRegByName("RAX");
- LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX);
+ LocIdx RaxLoc = MTracker->lookupOrTrackRegister(MTracker->getLocID(RAX));
auto [MInLocs, MOutLocs] = allocValueTables(3, 2);
@@ -1292,7 +1292,7 @@ TEST_F(InstrRefLDVTest, MLocNestedLoop) {
ASSERT_TRUE(MTracker->getNumLocs() == 1);
LocIdx RspLoc(0);
Register RAX = getRegByName("RAX");
- LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX);
+ LocIdx RaxLoc = MTracker->lookupOrTrackRegister(MTracker->getLocID(RAX));
auto [MInLocs, MOutLocs] = allocValueTables(5, 2);
@@ -1493,7 +1493,7 @@ TEST_F(InstrRefLDVTest, MLocNoDominatingLoop) {
ASSERT_TRUE(MTracker->getNumLocs() == 1);
LocIdx RspLoc(0);
Register RAX = getRegByName("RAX");
- LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX);
+ LocIdx RaxLoc = MTracker->lookupOrTrackRegister(MTracker->getLocID(RAX));
auto [MInLocs, MOutLocs] = allocValueTables(5, 2);
@@ -1648,7 +1648,7 @@ TEST_F(InstrRefLDVTest, MLocBadlyNestedLoops) {
ASSERT_TRUE(MTracker->getNumLocs() == 1);
LocIdx RspLoc(0);
Register RAX = getRegByName("RAX");
- LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX);
+ LocIdx RaxLoc = MTracker->lookupOrTrackRegister(MTracker->getLocID(RAX));
auto [MInLocs, MOutLocs] = allocValueTables(5, 2);
@@ -1780,7 +1780,7 @@ TEST_F(InstrRefLDVTest, pickVPHILocDiamond) {
ASSERT_TRUE(MTracker->getNumLocs() == 1);
LocIdx RspLoc(0);
Register RAX = getRegByName("RAX");
- LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX);
+ LocIdx RaxLoc = MTracker->lookupOrTrackRegister(MTracker->getLocID(RAX));
auto [MInLocs, MOutLocs] = allocValueTables(4, 2);
@@ -1976,7 +1976,7 @@ TEST_F(InstrRefLDVTest, pickVPHILocLoops) {
ASSERT_TRUE(MTracker->getNumLocs() == 1);
LocIdx RspLoc(0);
Register RAX = getRegByName("RAX");
- LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX);
+ LocIdx RaxLoc = MTracker->lookupOrTrackRegister(MTracker->getLocID(RAX));
auto [MInLocs, MOutLocs] = allocValueTables(3, 2);
@@ -2104,9 +2104,9 @@ TEST_F(InstrRefLDVTest, pickVPHILocBadlyNestedLoops) {
ASSERT_TRUE(MTracker->getNumLocs() == 1);
LocIdx RspLoc(0);
Register RAX = getRegByName("RAX");
- LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX);
+ LocIdx RaxLoc = MTracker->lookupOrTrackRegister(MTracker->getLocID(RAX));
Register RBX = getRegByName("RBX");
- LocIdx RbxLoc = MTracker->lookupOrTrackRegister(RBX);
+ LocIdx RbxLoc = MTracker->lookupOrTrackRegister(MTracker->getLocID(RBX));
auto [MInLocs, MOutLocs] = allocValueTables(5, 3);
@@ -2256,7 +2256,7 @@ TEST_F(InstrRefLDVTest, vlocJoinDiamond) {
ASSERT_TRUE(MTracker->getNumLocs() == 1);
LocIdx RspLoc(0);
Register RAX = getRegByName("RAX");
- MTracker->lookupOrTrackRegister(RAX);
+ MTracker->lookupOrTrackRegister(MTracker->getLocID(RAX));
DbgOpID LiveInRspID = DbgOpID(false, 0);
DbgOpID LiveInRaxID = DbgOpID(false, 1);
@@ -2440,7 +2440,7 @@ TEST_F(InstrRefLDVTest, vlocJoinLoops) {
ASSERT_TRUE(MTracker->getNumLocs() == 1);
LocIdx RspLoc(0);
Register RAX = getRegByName("RAX");
- MTracker->lookupOrTrackRegister(RAX);
+ MTracker->lookupOrTrackRegister(MTracker->getLocID(RAX));
DbgOpID LiveInRspID = DbgOpID(false, 0);
DbgOpID LiveInRaxID = DbgOpID(false, 1);
@@ -2538,9 +2538,9 @@ TEST_F(InstrRefLDVTest, vlocJoinBadlyNestedLoops) {
ASSERT_TRUE(MTracker->getNumLocs() == 1);
LocIdx RspLoc(0);
Register RAX = getRegByName("RAX");
- MTracker->lookupOrTrackRegister(RAX);
+ MTracker->lookupOrTrackRegister(MTracker->getLocID(RAX));
Register RBX = getRegByName("RBX");
- MTracker->lookupOrTrackRegister(RBX);
+ MTracker->lookupOrTrackRegister(MTracker->getLocID(RBX));
DbgOpID LiveInRspID = DbgOpID(false, 0);
DbgOpID LiveInRaxID = DbgOpID(false, 1);
@@ -2678,7 +2678,7 @@ TEST_F(InstrRefLDVTest, VLocDiamondBlocks) {
ASSERT_TRUE(MTracker->getNumLocs() == 1);
LocIdx RspLoc(0);
Register RAX = getRegByName("RAX");
- LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX);
+ LocIdx RaxLoc = MTracker->lookupOrTrackRegister(MTracker->getLocID(RAX));
unsigned EntryBlk = 0, RetBlk = 3;
@@ -2896,7 +2896,7 @@ TEST_F(InstrRefLDVTest, VLocSimpleLoop) {
ASSERT_TRUE(MTracker->getNumLocs() == 1);
LocIdx RspLoc(0);
Register RAX = getRegByName("RAX");
- LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX);
+ LocIdx RaxLoc = MTracker->lookupOrTrackRegister(MTracker->getLocID(RAX));
unsigned EntryBlk = 0, LoopBlk = 1;
@@ -3175,7 +3175,7 @@ TEST_F(InstrRefLDVTest, VLocNestedLoop) {
ASSERT_TRUE(MTracker->getNumLocs() == 1);
LocIdx RspLoc(0);
Register RAX = getRegByName("RAX");
- LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX);
+ LocIdx RaxLoc = MTracker->lookupOrTrackRegister(MTracker->getLocID(RAX));
unsigned EntryBlk = 0, Loop1Blk = 1, Loop2Blk = 2;
diff --git a/llvm/unittests/CodeGen/MFCommon.inc b/llvm/unittests/CodeGen/MFCommon.inc
index a86a68c..c5e1c74 100644
--- a/llvm/unittests/CodeGen/MFCommon.inc
+++ b/llvm/unittests/CodeGen/MFCommon.inc
@@ -2,7 +2,8 @@
// depending on a real target.
class BogusTargetLowering : public TargetLowering {
public:
- BogusTargetLowering(TargetMachine &TM) : TargetLowering(TM) {}
+ BogusTargetLowering(const TargetMachine &TM, const TargetSubtargetInfo &STI)
+ : TargetLowering(TM, STI) {}
};
class BogusFrameLowering : public TargetFrameLowering {
@@ -45,7 +46,7 @@ public:
static RegClassWeight Bogus{1, 16};
return Bogus;
}
- unsigned getRegUnitWeight(unsigned RegUnit) const override { return 1; }
+ unsigned getRegUnitWeight(MCRegUnit RegUnit) const override { return 1; }
unsigned getNumRegPressureSets() const override { return 0; }
const char *getRegPressureSetName(unsigned Idx) const override {
return "bogus";
@@ -59,7 +60,7 @@ public:
static const int Bogus[] = {0, -1};
return &Bogus[0];
}
- const int *getRegUnitPressureSets(unsigned RegUnit) const override {
+ const int *getRegUnitPressureSets(MCRegUnit RegUnit) const override {
static const int Bogus[] = {0, -1};
return &Bogus[0];
}
@@ -76,8 +77,10 @@ public:
};
class BogusTargetInstrInfo : public TargetInstrInfo {
+ BogusRegisterInfo RegInfo;
+
public:
- BogusTargetInstrInfo() : TargetInstrInfo() {}
+ BogusTargetInstrInfo() : TargetInstrInfo(RegInfo) {}
};
class BogusSubtarget : public TargetSubtargetInfo {
@@ -85,8 +88,8 @@ public:
BogusSubtarget(TargetMachine &TM)
: TargetSubtargetInfo(Triple(""), "", "", "", {}, {}, {}, nullptr,
nullptr, nullptr, nullptr, nullptr, nullptr),
- FL(), TL(TM) {}
- ~BogusSubtarget() override {}
+ FL(), TL(TM, *this) {}
+ ~BogusSubtarget() override = default;
const TargetFrameLowering *getFrameLowering() const override { return &FL; }
@@ -117,7 +120,7 @@ public:
Reloc::Static, CodeModel::Small, CodeGenOptLevel::Default),
ST(*this) {}
- ~BogusTargetMachine() override {}
+ ~BogusTargetMachine() override = default;
const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override {
return &ST;
diff --git a/llvm/unittests/CodeGen/MLRegAllocDevelopmentFeatures.cpp b/llvm/unittests/CodeGen/MLRegAllocDevelopmentFeatures.cpp
deleted file mode 100644
index 00c2c3a..0000000
--- a/llvm/unittests/CodeGen/MLRegAllocDevelopmentFeatures.cpp
+++ /dev/null
@@ -1,293 +0,0 @@
-//===- MLRegAllocDevelopmentFeatures.cpp - test dev MLRegAlloc features ---===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#include "../../lib/CodeGen/MLRegAllocEvictAdvisor.h"
-#include "llvm/Analysis/NoInferenceModelRunner.h"
-#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineModuleInfo.h"
-#include "llvm/CodeGen/SlotIndexes.h"
-#include "llvm/CodeGen/TargetFrameLowering.h"
-#include "llvm/CodeGen/TargetInstrInfo.h"
-#include "llvm/CodeGen/TargetLowering.h"
-#include "llvm/IR/LLVMContext.h"
-#include "llvm/IR/Module.h"
-#include "llvm/MC/TargetRegistry.h"
-#include "llvm/Support/Allocator.h"
-#include "llvm/Support/CodeGen.h"
-#include "llvm/Support/TargetSelect.h"
-#include "llvm/Target/TargetOptions.h"
-#include "llvm/TargetParser/Triple.h"
-#include "gmock/gmock.h"
-#include "gtest/gtest.h"
-
-#include <string>
-#include <vector>
-
-using namespace llvm;
-using testing::ContainerEq;
-using testing::Test;
-
-namespace {
-
-#include "MFCommon.inc"
-
-struct LRPosInfoIndexes {
- size_t StartIndex;
- size_t EndIndex;
- size_t PhysReg;
-};
-
-class RegAllocDevelopmentFeaturesTest : public ::Test {
-protected:
- SmallVector<LRStartEndInfo>
- setupOverlapProblem(const SmallVectorImpl<LRPosInfoIndexes> &Segments,
- simple_ilist<IndexListEntry> &IndexList) {
- SmallVector<LRStartEndInfo> PositionsToReturn;
- PositionsToReturn.reserve(Segments.size());
- for (auto CurrentPosIndexInfo : Segments) {
- LRStartEndInfo CurrentPosInfo = {};
- CurrentPosInfo.Pos = CurrentPosIndexInfo.PhysReg;
- PositionsToReturn.push_back(CurrentPosInfo);
- }
- size_t CurrentSegmentIndex = 0;
- size_t CurrentIndex = 0;
- while (CurrentSegmentIndex < Segments.size()) {
- auto *CurrentLEMem = static_cast<IndexListEntry *>(
- Allocator.Allocate(sizeof(IndexListEntry), alignof(IndexListEntry)));
- auto *CurrentListEntry =
- new (CurrentLEMem) IndexListEntry(nullptr, CurrentIndex);
- IndexList.push_back(*CurrentListEntry);
- for (size_t CurrentPosInfoIndex = 0;
- CurrentPosInfoIndex < Segments.size(); ++CurrentPosInfoIndex) {
- if ((CurrentIndex / SlotIndex::InstrDist) ==
- Segments[CurrentPosInfoIndex].StartIndex) {
- PositionsToReturn[CurrentPosInfoIndex].Begin =
- SlotIndex(CurrentListEntry, 0);
- } else if ((CurrentIndex / SlotIndex::InstrDist) ==
- Segments[CurrentPosInfoIndex].EndIndex) {
- PositionsToReturn[CurrentPosInfoIndex].End =
- SlotIndex(CurrentListEntry, 0);
- ++CurrentSegmentIndex;
- }
- }
- CurrentIndex += SlotIndex::InstrDist;
- }
- return PositionsToReturn;
- }
-
- NoInferenceModelRunner setupModelRunner() {
- const std::vector<TensorSpec> Inputs{
- TensorSpec::createSpec<int64_t>("instructions", InstructionsShape),
- TensorSpec::createSpec<int64_t>("instructions_mapping",
- InstructionsMappingShape),
- TensorSpec::createSpec<float>("mbb_frequencies", MBBFrequencyShape),
- TensorSpec::createSpec<int64_t>("mbb_mapping", InstructionsShape)};
- LLVMContext Ctx;
- return NoInferenceModelRunner(Ctx, Inputs);
- }
-
- std::vector<int64_t>
- getExpectedMappingMatrix(SmallVectorImpl<LRPosInfoIndexes> &OverlapSetup) {
- std::vector<int64_t> ExpectedMappingMatrix(
- NumberOfInterferences * ModelMaxSupportedInstructionCount, 0);
- for (auto NewSegment : OverlapSetup) {
- for (size_t CurrentIndex = NewSegment.StartIndex;
- CurrentIndex <= NewSegment.EndIndex; ++CurrentIndex) {
- ExpectedMappingMatrix[NewSegment.PhysReg *
- ModelMaxSupportedInstructionCount +
- CurrentIndex] = 1;
- }
- }
- return ExpectedMappingMatrix;
- }
-
- void runOverlapTest(SmallVectorImpl<LRPosInfoIndexes> &OverlapSetup) {
- simple_ilist<IndexListEntry> IndexList;
- auto OverlapProblem = setupOverlapProblem(OverlapSetup, IndexList);
- NoInferenceModelRunner ModelRunner = setupModelRunner();
- size_t MaxIndex = 0;
- for (size_t CurrentOverlap = 0; CurrentOverlap < OverlapSetup.size();
- ++CurrentOverlap) {
- if (OverlapSetup[CurrentOverlap].EndIndex >
- OverlapSetup[MaxIndex].EndIndex) {
- MaxIndex = CurrentOverlap;
- }
- }
- SlotIndex LastIndex = OverlapProblem[MaxIndex].End;
- extractInstructionFeatures(
- OverlapProblem, &ModelRunner,
- [](SlotIndex InputSlot) -> int { return 0; },
- [](SlotIndex InputSlot) -> float { return 0.0f; },
- [](SlotIndex InputSlot) -> MachineBasicBlock * { return nullptr; }, 0,
- 1, 2, 3, LastIndex);
- std::vector<int64_t> MappingMatrix(
- ModelRunner.getTensor<int64_t>(1),
- ModelRunner.getTensor<int64_t>(1) +
- NumberOfInterferences * ModelMaxSupportedInstructionCount);
- ASSERT_THAT(MappingMatrix,
- ContainerEq(getExpectedMappingMatrix(OverlapSetup)));
- IndexList.clear();
- }
-
- BumpPtrAllocator Allocator;
-};
-
-// meta tests to ensure that test setup works correctly
-
-TEST_F(RegAllocDevelopmentFeaturesTest,
- MetaOverlapInstructionDistancesAreCorrect) {
- SmallVector<LRPosInfoIndexes, 2> OverlapSetup;
- OverlapSetup.push_back({0, 5, 0});
- OverlapSetup.push_back({5, 10, 0});
- simple_ilist<IndexListEntry> IndexList;
- auto OverlapProblem = setupOverlapProblem(OverlapSetup, IndexList);
- ASSERT_EQ(OverlapProblem[0].End.distance(OverlapProblem[1].End),
- 5 * SlotIndex::InstrDist);
- ASSERT_EQ(OverlapProblem[0].End.distance(OverlapProblem[1].Begin), 0);
-}
-
-TEST_F(RegAllocDevelopmentFeaturesTest, MetaSlotIndicesAreValid) {
- SmallVector<LRPosInfoIndexes, 1> OverlapSetup;
- OverlapSetup.push_back({0, 10, 0});
- simple_ilist<IndexListEntry> IndexList;
- auto OverlapProblem = setupOverlapProblem(OverlapSetup, IndexList);
- ASSERT_TRUE(OverlapProblem[0].Begin.isValid());
- ASSERT_TRUE(OverlapProblem[0].End.isValid());
-}
-
-// Testing of feature extraction for per-instruction features
-
-TEST_F(RegAllocDevelopmentFeaturesTest, InstructionOpcodesAreCorrect) {
- SmallVector<LRPosInfoIndexes, 1> OverlapSetup;
- OverlapSetup.push_back({0, ModelMaxSupportedInstructionCount - 1, 0});
- simple_ilist<IndexListEntry> IndexList;
- auto OverlapProblem = setupOverlapProblem(OverlapSetup, IndexList);
- NoInferenceModelRunner ModelRunner = setupModelRunner();
- SlotIndex LastIndex = OverlapProblem[0].End;
- SlotIndex FirstIndex = OverlapProblem[0].Begin;
- extractInstructionFeatures(
- OverlapProblem, &ModelRunner,
- [FirstIndex](SlotIndex InputSlot) -> int {
- return FirstIndex.distance(InputSlot) / SlotIndex::InstrDist;
- },
- [](SlotIndex InputSlot) -> float { return 0.0f; },
- [](SlotIndex InputSlot) -> MachineBasicBlock * { return nullptr; }, 0, 1,
- 2, 3, LastIndex);
- for (size_t CurrentInstructionIndex = 0;
- CurrentInstructionIndex < ModelMaxSupportedInstructionCount;
- ++CurrentInstructionIndex) {
- ASSERT_EQ(
- (size_t)ModelRunner.getTensor<int64_t>(0)[CurrentInstructionIndex],
- CurrentInstructionIndex);
- }
-}
-
-TEST_F(RegAllocDevelopmentFeaturesTest, FullOverlap) {
- SmallVector<LRPosInfoIndexes, 2> OverlapSetup;
- OverlapSetup.push_back({0, ModelMaxSupportedInstructionCount - 1, 0});
- OverlapSetup.push_back({0, ModelMaxSupportedInstructionCount - 1, 1});
- runOverlapTest(OverlapSetup);
-}
-
-TEST_F(RegAllocDevelopmentFeaturesTest, PartialOverlap) {
- SmallVector<LRPosInfoIndexes, 2> OverlapSetup;
- OverlapSetup.push_back({0, 20, 0});
- OverlapSetup.push_back({15, 30, 1});
- runOverlapTest(OverlapSetup);
-}
-
-TEST_F(RegAllocDevelopmentFeaturesTest, PartialOverlapOpposite) {
- SmallVector<LRPosInfoIndexes, 2> OverlapSetup;
- OverlapSetup.push_back({15, 30, 1});
- OverlapSetup.push_back({0, 20, 0});
- runOverlapTest(OverlapSetup);
-}
-
-TEST_F(RegAllocDevelopmentFeaturesTest, InternalOverlap) {
- SmallVector<LRPosInfoIndexes, 2> OverlapSetup;
- OverlapSetup.push_back({0, 30, 0});
- OverlapSetup.push_back({10, 20, 1});
- runOverlapTest(OverlapSetup);
-}
-
-TEST_F(RegAllocDevelopmentFeaturesTest, TripleInternalOverlap) {
- SmallVector<LRPosInfoIndexes, 3> OverlapSetup;
- OverlapSetup.push_back({0, 30, 0});
- OverlapSetup.push_back({10, 25, 1});
- OverlapSetup.push_back({15, 20, 2});
- runOverlapTest(OverlapSetup);
-}
-
-TEST_F(RegAllocDevelopmentFeaturesTest, InternalMultiOverlap) {
- SmallVector<LRPosInfoIndexes, 3> OverlapSetup;
- OverlapSetup.push_back({0, 45, 0});
- OverlapSetup.push_back({30, 40, 1});
- OverlapSetup.push_back({35, 60, 2});
- runOverlapTest(OverlapSetup);
-}
-
-TEST_F(RegAllocDevelopmentFeaturesTest, SingleMBBTest) {
- NoInferenceModelRunner ModelRunner = setupModelRunner();
- SlotIndex CurrentIndex;
- // set index to 1 so we can ensure that the mapping actually get set
- std::map<MachineBasicBlock *, size_t> VisitedMBBs = {{nullptr, 1}};
- extractMBBFrequency(
- CurrentIndex, 0, VisitedMBBs,
- [](SlotIndex InputSlot) -> float { return 1.0f; }, nullptr, &ModelRunner,
- 2, 3);
- ASSERT_FLOAT_EQ(ModelRunner.getTensor<float>(2)[1], 1.0f);
- ASSERT_EQ(ModelRunner.getTensor<int64_t>(3)[0], 1);
-}
-
-TEST_F(RegAllocDevelopmentFeaturesTest, MBBFullTruncated) {
- SmallVector<LRPosInfoIndexes, 1> OverlapSetup;
- OverlapSetup.push_back({0, ModelMaxSupportedInstructionCount - 1, 0});
- simple_ilist<IndexListEntry> IndexList;
- auto OverlapProblem = setupOverlapProblem(OverlapSetup, IndexList);
- NoInferenceModelRunner ModelRunner = setupModelRunner();
- SlotIndex LastIndex = OverlapProblem[0].End;
- SlotIndex FirstIndex = OverlapProblem[0].Begin;
-
- LLVMContext Ctx;
- Module Mod("Module", Ctx);
- auto MF = createMachineFunction(Ctx, Mod);
- std::array<MachineBasicBlock *, ModelMaxSupportedInstructionCount>
- MBBsForTest;
- for (size_t I = 0; I < ModelMaxSupportedInstructionCount; ++I) {
- MBBsForTest[I] = MF->CreateMachineBasicBlock();
- }
-
- extractInstructionFeatures(
- OverlapProblem, &ModelRunner,
- [](SlotIndex InputSlot) -> int { return 0; },
- [FirstIndex](SlotIndex InputSlot) -> float {
- return static_cast<float>(FirstIndex.distance(InputSlot) /
- SlotIndex::InstrDist);
- },
- [FirstIndex, MBBsForTest](SlotIndex InputSlot) -> MachineBasicBlock * {
- return MBBsForTest[FirstIndex.distance(InputSlot) /
- SlotIndex::InstrDist];
- },
- 0, 1, 2, 3, LastIndex);
- for (size_t MBBIndex = 0; MBBIndex < ModelMaxSupportedMBBCount; ++MBBIndex) {
- ASSERT_FLOAT_EQ(ModelRunner.getTensor<float>(2)[MBBIndex],
- static_cast<float>(MBBIndex));
- ASSERT_EQ(ModelRunner.getTensor<int64_t>(3)[MBBIndex],
- static_cast<int64_t>(MBBIndex));
- }
- // the rest of the mapping values should be zero (truncated to 100 MBBs)
- for (size_t MBBIndex = ModelMaxSupportedMBBCount;
- MBBIndex < ModelMaxSupportedInstructionCount; ++MBBIndex) {
- ASSERT_EQ(ModelRunner.getTensor<int64_t>(3)[MBBIndex],
- static_cast<int64_t>(0));
- }
-}
-
-} // end namespace
diff --git a/llvm/unittests/CodeGen/MachineOperandTest.cpp b/llvm/unittests/CodeGen/MachineOperandTest.cpp
index 3f3f48f..c0b2b18 100644
--- a/llvm/unittests/CodeGen/MachineOperandTest.cpp
+++ b/llvm/unittests/CodeGen/MachineOperandTest.cpp
@@ -288,6 +288,23 @@ TEST(MachineOperandTest, PrintGlobalAddress) {
}
}
+TEST(MachineOperandTest, PrintLaneMask) {
+ // Create a MachineOperand with a lanemask and print it.
+ LaneBitmask LaneMask = LaneBitmask(12);
+ MachineOperand MO = MachineOperand::CreateLaneMask(LaneMask);
+
+ // Checking some preconditions on the newly created
+ // MachineOperand.
+ ASSERT_TRUE(MO.isLaneMask());
+ ASSERT_EQ(MO.getLaneMask(), LaneMask);
+
+ std::string str;
+ // Print a MachineOperand that is lanemask as in HEX representation.
+ raw_string_ostream OS(str);
+ MO.print(OS, /*TRI=*/nullptr);
+ ASSERT_EQ(str, "lanemask(0x000000000000000C)");
+}
+
TEST(MachineOperandTest, PrintRegisterLiveOut) {
// Create a MachineOperand with a register live out list and print it.
uint32_t Mask = 0;
@@ -424,4 +441,24 @@ TEST(MachineOperandTest, HashValue) {
ASSERT_TRUE(MO1.isIdenticalTo(MO2));
}
+TEST(MachineOperandTest, RegisterLiveOutHashValue) {
+ LLVMContext Ctx;
+ Module Mod("Module", Ctx);
+ auto MF = createMachineFunction(Ctx, Mod);
+ MachineBasicBlock *MBB = MF->CreateMachineBasicBlock();
+ MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+ auto *MI1 = MF->CreateMachineInstr(MCID, DebugLoc());
+ auto *MI2 = MF->CreateMachineInstr(MCID, DebugLoc());
+ MBB->insert(MBB->begin(), MI1);
+ MBB->insert(MBB->begin(), MI2);
+ uint32_t Mask1 = 0;
+ uint32_t Mask2 = 0;
+ MI1->addOperand(*MF, MachineOperand::CreateRegLiveOut(&Mask1));
+ MI2->addOperand(*MF, MachineOperand::CreateRegLiveOut(&Mask2));
+ auto MO1 = MI1->getOperand(0);
+ auto MO2 = MI2->getOperand(0);
+ EXPECT_EQ(hash_value(MO1), hash_value(MO2));
+ EXPECT_TRUE(MO1.isIdenticalTo(MO2));
+}
+
} // end namespace
diff --git a/llvm/unittests/CodeGen/RegisterTest.cpp b/llvm/unittests/CodeGen/RegisterTest.cpp
new file mode 100644
index 0000000..db2747c
--- /dev/null
+++ b/llvm/unittests/CodeGen/RegisterTest.cpp
@@ -0,0 +1,38 @@
+//===- RegisterTest.cpp -----------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/Register.h"
+#include "gtest/gtest.h"
+
+using namespace llvm;
+
+namespace {
+TEST(RegisterTest, Idx2StackSlot) {
+ EXPECT_EQ(Register::index2StackSlot(0), Register::StackSlotZero);
+ EXPECT_EQ(Register::index2StackSlot(1), Register::StackSlotZero | 1);
+ EXPECT_EQ(Register::index2StackSlot(-1),
+ Register::StackSlotZero | Register::StackSlotMask);
+ int MaxPowOf2 = 1 << (Register::MaxFrameIndexBitwidth - 1);
+ // Check the highest possible value of frame index
+ EXPECT_EQ(Register::index2StackSlot(MaxPowOf2 - 1),
+ Register::StackSlotZero | (MaxPowOf2 - 1));
+ // Check the lowest possible value of frame index
+ EXPECT_EQ(Register::index2StackSlot(-MaxPowOf2),
+ Register::StackSlotZero | (-MaxPowOf2 & Register::StackSlotMask));
+}
+
+TEST(RegisterTest, StackSlotIndex) {
+ int MaxPowOf2 = 1 << (Register::MaxFrameIndexBitwidth - 1);
+ std::vector<int> FIs = {0, 1 - 1, MaxPowOf2 - 1, -MaxPowOf2};
+
+ for (int FI : FIs) {
+ Register Reg = Register::index2StackSlot(FI);
+ EXPECT_EQ(Reg.stackSlotIndex(), FI);
+ }
+}
+} // end namespace
diff --git a/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp b/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
index ceaee52..4fcd3fc 100644
--- a/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
+++ b/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
@@ -354,6 +354,46 @@ TEST_F(SelectionDAGPatternMatchTest, matchBinaryOp) {
sd_match(InsertELT, m_InsertElt(m_Value(), m_Value(), m_SpecificInt(1))));
}
+TEST_F(SelectionDAGPatternMatchTest, matchSpecificFpOp) {
+ SDLoc DL;
+ APFloat Value(1.5f);
+ auto Float32VT = EVT::getFloatingPointVT(32);
+ SDValue Op0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, Float32VT);
+ SDValue Op1 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 2, Float32VT);
+ SDValue Op2 = DAG->getConstantFP(Value, DL, Float32VT);
+ SDValue FAdd0 = DAG->getNode(ISD::FADD, DL, Float32VT, Op0, Op1);
+ SDValue FAdd1 = DAG->getNode(ISD::FADD, DL, Float32VT, Op1, Op2);
+
+ using namespace SDPatternMatch;
+
+ EXPECT_FALSE(sd_match(Op1, m_SpecificFP(Value)));
+ EXPECT_TRUE(sd_match(Op2, m_SpecificFP(Value)));
+
+ EXPECT_FALSE(sd_match(
+ FAdd0, m_BinOp(ISD::FADD, m_Specific(Op0), m_SpecificFP(Value))));
+ EXPECT_TRUE(sd_match(
+ FAdd1, m_BinOp(ISD::FADD, m_Specific(Op1), m_SpecificFP(Value))));
+ EXPECT_TRUE(sd_match(
+ FAdd1, m_c_BinOp(ISD::FADD, m_SpecificFP(Value), m_Specific(Op1))));
+
+ auto VFloat32VT = EVT::getVectorVT(Context, Float32VT, 2);
+ SDValue VOp0 = DAG->getSplat(VFloat32VT, DL, Op0);
+ SDValue VOp1 = DAG->getSplat(VFloat32VT, DL, Op1);
+ SDValue VOp2 = DAG->getSplat(VFloat32VT, DL, Op2);
+
+ EXPECT_FALSE(sd_match(VOp0, m_SpecificFP(Value)));
+ EXPECT_TRUE(sd_match(VOp2, m_SpecificFP(Value)));
+
+ SDValue VFAdd0 = DAG->getNode(ISD::FADD, DL, VFloat32VT, VOp0, VOp1);
+ SDValue VFAdd1 = DAG->getNode(ISD::FADD, DL, VFloat32VT, VOp1, VOp2);
+ EXPECT_FALSE(sd_match(
+ VFAdd0, m_BinOp(ISD::FADD, m_Specific(VOp0), m_SpecificFP(Value))));
+ EXPECT_TRUE(sd_match(
+ VFAdd1, m_BinOp(ISD::FADD, m_Specific(VOp1), m_SpecificFP(Value))));
+ EXPECT_TRUE(sd_match(
+ VFAdd1, m_c_BinOp(ISD::FADD, m_SpecificFP(Value), m_Specific(VOp1))));
+}
+
TEST_F(SelectionDAGPatternMatchTest, matchGenericTernaryOp) {
SDLoc DL;
auto Float32VT = EVT::getFloatingPointVT(32);
@@ -551,6 +591,8 @@ TEST_F(SelectionDAGPatternMatchTest, matchConstants) {
SDValue PoisonVInt32VT = DAG->getPOISON(VInt32VT);
EXPECT_TRUE(sd_match(PoisonInt32VT, m_Poison()));
EXPECT_TRUE(sd_match(PoisonVInt32VT, m_Poison()));
+ EXPECT_TRUE(sd_match(PoisonInt32VT, m_Undef()));
+ EXPECT_TRUE(sd_match(PoisonVInt32VT, m_Undef()));
}
TEST_F(SelectionDAGPatternMatchTest, patternCombinators) {
@@ -790,6 +832,38 @@ TEST_F(SelectionDAGPatternMatchTest, matchReassociatableOp) {
EXPECT_FALSE(sd_match(ADDS0123, m_ReassociatableAdd(m_Value(), m_Value(),
m_Value(), m_Value())));
+ // (Op0 + Op1) + Op0 binds correctly, allowing commutation on leaf nodes
+ SDValue ADD010 = DAG->getNode(ISD::ADD, DL, Int32VT, ADD01, Op0);
+ SDValue A, B;
+ EXPECT_TRUE(sd_match(
+ ADD010, m_ReassociatableAdd(m_Value(A), m_Value(B), m_Deferred(A))));
+ EXPECT_EQ(Op0, A);
+ EXPECT_EQ(Op1, B);
+
+ A.setNode(nullptr);
+ B.setNode(nullptr);
+ EXPECT_TRUE(sd_match(
+ ADD010, m_ReassociatableAdd(m_Value(A), m_Value(B), m_Deferred(B))));
+ EXPECT_EQ(Op0, B);
+ EXPECT_EQ(Op1, A);
+
+ A.setNode(nullptr);
+ B.setNode(nullptr);
+ EXPECT_TRUE(sd_match(
+ ADD010, m_ReassociatableAdd(m_Value(A), m_Deferred(A), m_Value(B))));
+ EXPECT_EQ(Op0, A);
+ EXPECT_EQ(Op1, B);
+
+ A.setNode(nullptr);
+ B.setNode(nullptr);
+ EXPECT_FALSE(sd_match(
+ ADD010, m_ReassociatableAdd(m_Value(A), m_Deferred(A), m_Deferred(A))));
+
+ A.setNode(nullptr);
+ B.setNode(nullptr);
+ EXPECT_FALSE(sd_match(
+ ADD010, m_ReassociatableAdd(m_Value(A), m_Deferred(B), m_Value(B))));
+
// (Op0 * Op1) * (Op2 * Op3)
SDValue MUL01 = DAG->getNode(ISD::MUL, DL, Int32VT, Op0, Op1);
SDValue MUL23 = DAG->getNode(ISD::MUL, DL, Int32VT, Op2, Op3);
generated by cgit v1.1 at 2026-01-06 06:28:51 +0000