1 files changed, 83 insertions, 0 deletions
diff --git a/llvm/unittests/CodeGen/MachineInstrTest.cpp b/llvm/unittests/CodeGen/MachineInstrTest.cpp
index be409a5..0841cd3 100644
--- a/llvm/unittests/CodeGen/MachineInstrTest.cpp
+++ b/llvm/unittests/CodeGen/MachineInstrTest.cpp
@@ -478,4 +478,87 @@ TEST(MachineInstrBuilder, BuildMI) {
 
 static_assert(std::is_trivially_copyable_v<MCOperand>, "trivially copyable");
 
+TEST(MachineInstrTest, SpliceOperands) {
+  LLVMContext Ctx;
+  Module Mod("Module", Ctx);
+  std::unique_ptr<MachineFunction> MF = createMachineFunction(Ctx, Mod);
+  MachineBasicBlock *MBB = MF->CreateMachineBasicBlock();
+  MCInstrDesc MCID = {TargetOpcode::INLINEASM,
+                      0,
+                      0,
+                      0,
+                      0,
+                      0,
+                      0,
+                      0,
+                      0,
+                      (1ULL << MCID::Pseudo) | (1ULL << MCID::Variadic),
+                      0};
+  MachineInstr *MI = MF->CreateMachineInstr(MCID, DebugLoc());
+  MBB->insert(MBB->begin(), MI);
+  MI->addOperand(MachineOperand::CreateImm(0));
+  MI->addOperand(MachineOperand::CreateImm(1));
+  MI->addOperand(MachineOperand::CreateImm(2));
+  MI->addOperand(MachineOperand::CreateImm(3));
+  MI->addOperand(MachineOperand::CreateImm(4));
+
+  MI->removeOperand(1);
+  EXPECT_EQ(MI->getOperand(1).getImm(), MachineOperand::CreateImm(2).getImm());
+  EXPECT_EQ(MI->getNumOperands(), 4U);
+
+  MachineOperand Ops[] = {
+      MachineOperand::CreateImm(42),   MachineOperand::CreateImm(1024),
+      MachineOperand::CreateImm(2048), MachineOperand::CreateImm(4096),
+      MachineOperand::CreateImm(8192),
+  };
+  auto *It = MI->operands_begin();
+  ++It;
+  MI->insert(It, Ops);
+
+  EXPECT_EQ(MI->getNumOperands(), 9U);
+  EXPECT_EQ(MI->getOperand(0).getImm(), MachineOperand::CreateImm(0).getImm());
+  EXPECT_EQ(MI->getOperand(1).getImm(), MachineOperand::CreateImm(42).getImm());
+  EXPECT_EQ(MI->getOperand(2).getImm(),
+            MachineOperand::CreateImm(1024).getImm());
+  EXPECT_EQ(MI->getOperand(3).getImm(),
+            MachineOperand::CreateImm(2048).getImm());
+  EXPECT_EQ(MI->getOperand(4).getImm(),
+            MachineOperand::CreateImm(4096).getImm());
+  EXPECT_EQ(MI->getOperand(5).getImm(),
+            MachineOperand::CreateImm(8192).getImm());
+  EXPECT_EQ(MI->getOperand(6).getImm(), MachineOperand::CreateImm(2).getImm());
+  EXPECT_EQ(MI->getOperand(7).getImm(), MachineOperand::CreateImm(3).getImm());
+  EXPECT_EQ(MI->getOperand(8).getImm(), MachineOperand::CreateImm(4).getImm());
+
+  // test tied operands
+  MCRegisterClass MRC{0, 0, 0, 0, 0, 0, 0, 0, /*Allocatable=*/true};
+  TargetRegisterClass RC{&MRC, 0, 0, {}, 0, 0, 0, 0, 0, 0, 0};
+  // MachineRegisterInfo will be very upset if these registers aren't
+  // allocatable.
+  assert(RC.isAllocatable() && "unusable TargetRegisterClass");
+  MachineRegisterInfo &MRI = MF->getRegInfo();
+  Register A = MRI.createVirtualRegister(&RC);
+  Register B = MRI.createVirtualRegister(&RC);
+  MI->getOperand(0).ChangeToRegister(A, /*isDef=*/true);
+  MI->getOperand(1).ChangeToRegister(B, /*isDef=*/false);
+  MI->tieOperands(0, 1);
+  EXPECT_TRUE(MI->getOperand(0).isTied());
+  EXPECT_TRUE(MI->getOperand(1).isTied());
+  EXPECT_EQ(MI->findTiedOperandIdx(0), 1U);
+  EXPECT_EQ(MI->findTiedOperandIdx(1), 0U);
+  MI->insert(&MI->getOperand(1), {MachineOperand::CreateImm(7)});
+  EXPECT_TRUE(MI->getOperand(0).isTied());
+  EXPECT_TRUE(MI->getOperand(1).isImm());
+  EXPECT_TRUE(MI->getOperand(2).isTied());
+  EXPECT_EQ(MI->findTiedOperandIdx(0), 2U);
+  EXPECT_EQ(MI->findTiedOperandIdx(2), 0U);
+  EXPECT_EQ(MI->getOperand(0).getReg(), A);
+  EXPECT_EQ(MI->getOperand(2).getReg(), B);
+
+  // bad inputs
+  EXPECT_EQ(MI->getNumOperands(), 10U);
+  MI->insert(MI->operands_begin(), {});
+  EXPECT_EQ(MI->getNumOperands(), 10U);
+}
+
 } // end namespace