diff options
Diffstat (limited to 'llvm/test/Transforms/InstCombine')
7 files changed, 396 insertions, 19 deletions
diff --git a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-to-svbool-binops.ll b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-to-svbool-binops.ll index ecedbdb..abe1ed0 100644 --- a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-to-svbool-binops.ll +++ b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-to-svbool-binops.ll @@ -124,6 +124,39 @@ define <vscale x 8 x i1> @try_combine_svbool_binop_orr(<vscale x 8 x i1> %a, <vs ret <vscale x 8 x i1> %t3 } +; Verify predicate cast does not hinder "isAllActive" knowledge. +define <vscale x 8 x half> @try_combine_svbool_binop_fadd(<vscale x 8 x half> %a, <vscale x 8 x half> %b) { +; CHECK-LABEL: @try_combine_svbool_binop_fadd( +; CHECK-NEXT: [[T2:%.*]] = fadd <vscale x 8 x half> [[A:%.*]], [[B:%.*]] +; CHECK-NEXT: ret <vscale x 8 x half> [[T2]] +; + %t1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> splat (i1 true)) + %t2 = tail call <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> %t1, <vscale x 8 x half> %a, <vscale x 8 x half> %b) + ret <vscale x 8 x half> %t2 +} + +; Verify predicate cast does not hinder "isAllActive" knowledge. +define <vscale x 4 x float> @try_combine_svbool_binop_fmul(<vscale x 4 x float> %a, <vscale x 4 x float> %b) { +; CHECK-LABEL: @try_combine_svbool_binop_fmul( +; CHECK-NEXT: [[T2:%.*]] = fmul <vscale x 4 x float> [[A:%.*]], [[B:%.*]] +; CHECK-NEXT: ret <vscale x 4 x float> [[T2]] +; + %t1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> splat (i1 true)) + %t2 = tail call <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32(<vscale x 4 x i1> %t1, <vscale x 4 x float> %a, <vscale x 4 x float> %b) + ret <vscale x 4 x float> %t2 +} + +; Verify predicate cast does not hinder "isAllActive" knowledge. +define <vscale x 2 x double> @try_combine_svbool_binop_fsub(<vscale x 2 x double> %a, <vscale x 2 x double> %b) { +; CHECK-LABEL: @try_combine_svbool_binop_fsub( +; CHECK-NEXT: [[T2:%.*]] = fsub <vscale x 2 x double> [[A:%.*]], [[B:%.*]] +; CHECK-NEXT: ret <vscale x 2 x double> [[T2]] +; + %t1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> splat (i1 true)) + %t2 = tail call <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1> %t1, <vscale x 2 x double> %a, <vscale x 2 x double> %b) + ret <vscale x 2 x double> %t2 +} + declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>) declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>) declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>) diff --git a/llvm/test/Transforms/InstCombine/bitreverse-hang.ll b/llvm/test/Transforms/InstCombine/bitreverse-hang.ll index bb01299..3f29509 100644 --- a/llvm/test/Transforms/InstCombine/bitreverse-hang.ll +++ b/llvm/test/Transforms/InstCombine/bitreverse-hang.ll @@ -21,7 +21,7 @@ @b = common global i32 0, align 4 ; CHECK: define i32 @fn1 -define i32 @fn1() #0 { +define i32 @fn1() { entry: %b.promoted = load i32, ptr @b, align 4, !tbaa !2 br label %for.body @@ -40,8 +40,6 @@ for.end: ; preds = %for.body ret i32 undef } -attributes #0 = { norecurse nounwind ssp uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="core2" "target-features"="+cx16,+fxsr,+mmx,+sse,+sse2,+sse3,+ssse3" "unsafe-fp-math"="false" "use-soft-float"="false" } - !llvm.module.flags = !{!0} !llvm.ident = !{!1} diff --git a/llvm/test/Transforms/InstCombine/constant-vector-insert.ll b/llvm/test/Transforms/InstCombine/constant-vector-insert.ll new file mode 100644 index 0000000..2688540 --- /dev/null +++ b/llvm/test/Transforms/InstCombine/constant-vector-insert.ll @@ -0,0 +1,156 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -S -passes=instcombine %s | FileCheck %s +; RUN: opt -S -passes=instcombine %s \ +; RUN: -use-constant-int-for-fixed-length-splat \ +; RUN -use-constant-fp-for-fixed-length-splat \ +; RUN: -use-constant-int-for-scalable-splat \ +; RUN: -use-constant-fp-for-scalable-splat | FileCheck %s + +define <vscale x 4 x i32> @insert_div() { +; CHECK-LABEL: @insert_div( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DIV:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> poison, <4 x i32> splat (i32 3), i64 0) +; CHECK-NEXT: ret <vscale x 4 x i32> [[DIV]] +; +entry: + %0 = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> poison, <4 x i32> splat (i32 9), i64 0) + %div = udiv <vscale x 4 x i32> %0, splat (i32 3) + ret <vscale x 4 x i32> %div +} + +define <vscale x 4 x i32> @insert_div_splat_lhs() { +; CHECK-LABEL: @insert_div_splat_lhs( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DIV:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> splat (i32 5), <4 x i32> splat (i32 2), i64 0) +; CHECK-NEXT: ret <vscale x 4 x i32> [[DIV]] +; +entry: + %0 = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> splat(i32 2), <4 x i32> splat (i32 5), i64 0) + %div = udiv <vscale x 4 x i32> splat (i32 10), %0 + ret <vscale x 4 x i32> %div +} + +define <vscale x 4 x i32> @insert_div_mixed_splat() { +; CHECK-LABEL: @insert_div_mixed_splat( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DIV:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> splat (i32 6), <4 x i32> splat (i32 3), i64 0) +; CHECK-NEXT: ret <vscale x 4 x i32> [[DIV]] +; +entry: + %0 = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> splat (i32 18), <4 x i32> splat (i32 9), i64 0) + %div = udiv <vscale x 4 x i32> %0, splat (i32 3) + ret <vscale x 4 x i32> %div +} + +define <vscale x 4 x i32> @insert_mul() { +; CHECK-LABEL: @insert_mul( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[MUL:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> poison, <4 x i32> splat (i32 7), i64 4) +; CHECK-NEXT: ret <vscale x 4 x i32> [[MUL]] +; +entry: + %0 = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> poison, <4 x i32> splat (i32 1), i64 4) + %mul = mul <vscale x 4 x i32> %0, splat (i32 7) + ret <vscale x 4 x i32> %mul +} + +define <vscale x 4 x i32> @insert_add() { +; CHECK-LABEL: @insert_add( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[ADD:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> poison, <4 x i32> splat (i32 16), i64 0) +; CHECK-NEXT: ret <vscale x 4 x i32> [[ADD]] +; +entry: + %0 = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> poison, <4 x i32> splat (i32 5), i64 0) + %add = add <vscale x 4 x i32> %0, splat (i32 11) + ret <vscale x 4 x i32> %add +} + +define <vscale x 4 x i32> @insert_add_non_splat_subvector() { +; CHECK-LABEL: @insert_add_non_splat_subvector( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[ADD:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> poison, <4 x i32> <i32 101, i32 102, i32 103, i32 104>, i64 0) +; CHECK-NEXT: ret <vscale x 4 x i32> [[ADD]] +; +entry: + %0 = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> poison, <4 x i32> <i32 1, i32 2, i32 3, i32 4>, i64 0) + %add = add <vscale x 4 x i32> %0, splat (i32 100) + ret <vscale x 4 x i32> %add +} + +define <vscale x 4 x float> @insert_add_fp() { +; CHECK-LABEL: @insert_add_fp( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[ADD:%.*]] = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> splat (float 6.250000e+00), <4 x float> splat (float 5.500000e+00), i64 0) +; CHECK-NEXT: ret <vscale x 4 x float> [[ADD]] +; +entry: + %0 = call <vscale x 4 x float> @llvm.vector.insert.nxv4f32.v4f32(<vscale x 4 x float> splat(float 1.25), <4 x float> splat (float 0.5), i64 0) + %add = fadd <vscale x 4 x float> %0, splat (float 5.0) + ret <vscale x 4 x float> %add +} + +define <vscale x 8 x i32> @insert_add_scalable_subvector() { +; CHECK-LABEL: @insert_add_scalable_subvector( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[ADD:%.*]] = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> splat (i32 20), <vscale x 4 x i32> splat (i32 -4), i64 0) +; CHECK-NEXT: ret <vscale x 8 x i32> [[ADD]] +; +entry: + %0 = call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> splat(i32 16), <vscale x 4 x i32> splat (i32 -8), i64 0) + %add = add <vscale x 8 x i32> %0, splat (i32 4) + ret <vscale x 8 x i32> %add +} + +define <vscale x 4 x i32> @insert_sub() { +; CHECK-LABEL: @insert_sub( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[SUB:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> poison, <4 x i32> zeroinitializer, i64 8) +; CHECK-NEXT: ret <vscale x 4 x i32> [[SUB]] +; +entry: + %0 = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> poison, <4 x i32> splat (i32 11), i64 8) + %sub = add <vscale x 4 x i32> %0, splat (i32 -11) + ret <vscale x 4 x i32> %sub +} + +define <vscale x 4 x i32> @insert_and_partially_undef() { +; CHECK-LABEL: @insert_and_partially_undef( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[AND:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> zeroinitializer, <4 x i32> splat (i32 4), i64 0) +; CHECK-NEXT: ret <vscale x 4 x i32> [[AND]] +; +entry: + %0 = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> undef, <4 x i32> splat (i32 6), i64 0) + %and = and <vscale x 4 x i32> %0, splat (i32 4) + ret <vscale x 4 x i32> %and +} + +define <vscale x 4 x i32> @insert_fold_chain() { +; CHECK-LABEL: @insert_fold_chain( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[ADD:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> splat (i32 11), <4 x i32> splat (i32 8), i64 0) +; CHECK-NEXT: ret <vscale x 4 x i32> [[ADD]] +; +entry: + %0 = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> splat (i32 21), <4 x i32> splat (i32 12), i64 0) + %div = udiv <vscale x 4 x i32> %0, splat (i32 3) + %add = add <vscale x 4 x i32> %div, splat (i32 4) + ret <vscale x 4 x i32> %add +} + +; TODO: This could be folded more. +define <vscale x 4 x i32> @insert_add_both_insert_vector() { +; CHECK-LABEL: @insert_add_both_insert_vector( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> splat (i32 10), <4 x i32> splat (i32 5), i64 0) +; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> splat (i32 -1), <4 x i32> splat (i32 2), i64 0) +; CHECK-NEXT: [[ADD:%.*]] = add <vscale x 4 x i32> [[TMP0]], [[TMP1]] +; CHECK-NEXT: ret <vscale x 4 x i32> [[ADD]] +; +entry: + %0 = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> splat(i32 10), <4 x i32> splat (i32 5), i64 0) + %1 = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v4i32(<vscale x 4 x i32> splat(i32 -1), <4 x i32> splat (i32 2), i64 0) + %add = add <vscale x 4 x i32> %0, %1 + ret <vscale x 4 x i32> %add +} diff --git a/llvm/test/Transforms/InstCombine/ctlz-cttz.ll b/llvm/test/Transforms/InstCombine/ctlz-cttz.ll new file mode 100644 index 0000000..871fb34 --- /dev/null +++ b/llvm/test/Transforms/InstCombine/ctlz-cttz.ll @@ -0,0 +1,145 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt < %s -S -passes=instcombine | FileCheck %s + +; ctpop(~i & (i - 1)) -> bitwidth - cttz(i, false) +define i8 @ctlz_to_sub_bw_cttz(i8 %a0) { +; CHECK-LABEL: define i8 @ctlz_to_sub_bw_cttz( +; CHECK-SAME: i8 [[A0:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) i8 @llvm.cttz.i8(i8 [[A0]], i1 false) +; CHECK-NEXT: [[CLZ:%.*]] = sub nuw nsw i8 8, [[TMP1]] +; CHECK-NEXT: ret i8 [[CLZ]] +; + %dec = add i8 %a0, -1 + %not = xor i8 %a0, -1 + %and = and i8 %dec, %not + %clz = tail call i8 @llvm.ctlz.i8(i8 %and, i1 false) + ret i8 %clz +} + +define i8 @ctlz_to_sub_bw_cttz_poison(i8 %a0) { +; CHECK-LABEL: define i8 @ctlz_to_sub_bw_cttz_poison( +; CHECK-SAME: i8 [[A0:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) i8 @llvm.cttz.i8(i8 [[A0]], i1 false) +; CHECK-NEXT: [[CLZ:%.*]] = sub nuw nsw i8 8, [[TMP1]] +; CHECK-NEXT: ret i8 [[CLZ]] +; + %dec = add i8 %a0, -1 + %not = xor i8 %a0, -1 + %and = and i8 %dec, %not + %clz = tail call i8 @llvm.ctlz.i8(i8 %and, i1 true) + ret i8 %clz +} + +define i8 @ctlz_to_sub_bw_cttz_different_add(i8 %a0) { +; CHECK-LABEL: define i8 @ctlz_to_sub_bw_cttz_different_add( +; CHECK-SAME: i8 [[A0:%.*]]) { +; CHECK-NEXT: [[DEC:%.*]] = add i8 [[A0]], 1 +; CHECK-NEXT: [[NOT:%.*]] = xor i8 [[A0]], -1 +; CHECK-NEXT: [[AND:%.*]] = and i8 [[DEC]], [[NOT]] +; CHECK-NEXT: [[CLZ:%.*]] = tail call range(i8 0, 9) i8 @llvm.ctlz.i8(i8 [[AND]], i1 false) +; CHECK-NEXT: ret i8 [[CLZ]] +; + %dec = add i8 %a0, 1 + %not = xor i8 %a0, -1 + %and = and i8 %dec, %not + %clz = tail call i8 @llvm.ctlz.i8(i8 %and, i1 false) + ret i8 %clz +} + +define i8 @ctlz_to_sub_bw_cttz_different_xor(i8 %a0) { +; CHECK-LABEL: define i8 @ctlz_to_sub_bw_cttz_different_xor( +; CHECK-SAME: i8 [[A0:%.*]]) { +; CHECK-NEXT: [[DEC:%.*]] = add i8 [[A0]], -1 +; CHECK-NEXT: [[NOT:%.*]] = xor i8 [[A0]], 1 +; CHECK-NEXT: [[AND:%.*]] = and i8 [[DEC]], [[NOT]] +; CHECK-NEXT: [[CLZ:%.*]] = tail call range(i8 0, 9) i8 @llvm.ctlz.i8(i8 [[AND]], i1 false) +; CHECK-NEXT: ret i8 [[CLZ]] +; + %dec = add i8 %a0, -1 + %not = xor i8 %a0, 1 + %and = and i8 %dec, %not + %clz = tail call i8 @llvm.ctlz.i8(i8 %and, i1 false) + ret i8 %clz +} + +declare void @use(i8) + +define i8 @ctlz_to_sub_bw_cttz_multi_use_dec(i8 %a0) { +; CHECK-LABEL: define i8 @ctlz_to_sub_bw_cttz_multi_use_dec( +; CHECK-SAME: i8 [[A0:%.*]]) { +; CHECK-NEXT: [[DEC:%.*]] = add i8 [[A0]], -1 +; CHECK-NEXT: call void @use(i8 [[DEC]]) +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) i8 @llvm.cttz.i8(i8 [[A0]], i1 false) +; CHECK-NEXT: [[CLZ:%.*]] = sub nuw nsw i8 8, [[TMP1]] +; CHECK-NEXT: ret i8 [[CLZ]] +; + %dec = add i8 %a0, -1 + call void @use(i8 %dec) + %not = xor i8 %a0, -1 + %and = and i8 %dec, %not + %clz = tail call i8 @llvm.ctlz.i8(i8 %and, i1 false) + ret i8 %clz +} + +define i8 @ctlz_to_sub_bw_cttz_multi_use_not(i8 %a0) { +; CHECK-LABEL: define i8 @ctlz_to_sub_bw_cttz_multi_use_not( +; CHECK-SAME: i8 [[A0:%.*]]) { +; CHECK-NEXT: [[NOT:%.*]] = xor i8 [[A0]], -1 +; CHECK-NEXT: call void @use(i8 [[NOT]]) +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) i8 @llvm.cttz.i8(i8 [[A0]], i1 false) +; CHECK-NEXT: [[CLZ:%.*]] = sub nuw nsw i8 8, [[TMP1]] +; CHECK-NEXT: ret i8 [[CLZ]] +; + %dec = add i8 %a0, -1 + %not = xor i8 %a0, -1 + call void @use(i8 %not) + %and = and i8 %dec, %not + %clz = tail call i8 @llvm.ctlz.i8(i8 %and, i1 false) + ret i8 %clz +} + +define i8 @ctlz_to_sub_bw_cttz_multi_use_and(i8 %a0) { +; CHECK-LABEL: define i8 @ctlz_to_sub_bw_cttz_multi_use_and( +; CHECK-SAME: i8 [[A0:%.*]]) { +; CHECK-NEXT: [[DEC:%.*]] = add i8 [[A0]], -1 +; CHECK-NEXT: [[NOT:%.*]] = xor i8 [[A0]], -1 +; CHECK-NEXT: [[AND:%.*]] = and i8 [[DEC]], [[NOT]] +; CHECK-NEXT: call void @use(i8 [[AND]]) +; CHECK-NEXT: [[CLZ:%.*]] = tail call range(i8 0, 9) i8 @llvm.ctlz.i8(i8 [[AND]], i1 false) +; CHECK-NEXT: ret i8 [[CLZ]] +; + %dec = add i8 %a0, -1 + %not = xor i8 %a0, -1 + %and = and i8 %dec, %not + call void @use(i8 %and) + %clz = tail call i8 @llvm.ctlz.i8(i8 %and, i1 false) + ret i8 %clz +} + +define i8 @ctlz_to_sub_bw_cttz_commute_and(i8 %a0) { +; CHECK-LABEL: define i8 @ctlz_to_sub_bw_cttz_commute_and( +; CHECK-SAME: i8 [[A0:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) i8 @llvm.cttz.i8(i8 [[A0]], i1 false) +; CHECK-NEXT: [[CLZ:%.*]] = sub nuw nsw i8 8, [[TMP1]] +; CHECK-NEXT: ret i8 [[CLZ]] +; + %dec = add i8 %a0, -1 + %not = xor i8 %a0, -1 + %and = and i8 %not, %dec + %clz = tail call i8 @llvm.ctlz.i8(i8 %and, i1 false) + ret i8 %clz +} + +define <2 x i8> @ctlz_to_sub_bw_cttz_vec_splat(<2 x i8> %a0) { +; CHECK-LABEL: define <2 x i8> @ctlz_to_sub_bw_cttz_vec_splat( +; CHECK-SAME: <2 x i8> [[A0:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) <2 x i8> @llvm.cttz.v2i8(<2 x i8> [[A0]], i1 false) +; CHECK-NEXT: [[CLZ:%.*]] = sub nuw nsw <2 x i8> splat (i8 8), [[TMP1]] +; CHECK-NEXT: ret <2 x i8> [[CLZ]] +; + %dec = add <2 x i8> %a0, <i8 -1, i8 -1> + %not = xor <2 x i8> %a0, <i8 -1, i8 -1> + %and = and <2 x i8> %dec, %not + %clz = tail call <2 x i8>@llvm.ctlz.v2i8(<2 x i8> %and, i1 false) + ret <2 x i8> %clz +} diff --git a/llvm/test/Transforms/InstCombine/scmp.ll b/llvm/test/Transforms/InstCombine/scmp.ll index c0be5b9..2ae062cd 100644 --- a/llvm/test/Transforms/InstCombine/scmp.ll +++ b/llvm/test/Transforms/InstCombine/scmp.ll @@ -519,9 +519,7 @@ define <3 x i2> @scmp_unary_shuffle_ops(<3 x i8> %x, <3 x i8> %y) { define i32 @scmp_sgt_slt(i32 %a) { ; CHECK-LABEL: define i32 @scmp_sgt_slt( ; CHECK-SAME: i32 [[A:%.*]]) { -; CHECK-NEXT: [[A_LOBIT:%.*]] = ashr i32 [[A]], 31 -; CHECK-NEXT: [[CMP_INV:%.*]] = icmp slt i32 [[A]], 1 -; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[CMP_INV]], i32 [[A_LOBIT]], i32 1 +; CHECK-NEXT: [[RETVAL_0:%.*]] = call i32 @llvm.scmp.i32.i32(i32 [[A]], i32 0) ; CHECK-NEXT: ret i32 [[RETVAL_0]] ; %cmp = icmp sgt i32 %a, 0 @@ -747,3 +745,55 @@ define i8 @scmp_from_select_eq_and_gt_neg3(i32 %x, i32 %y) { %r = select i1 %eq, i8 0, i8 %sel1 ret i8 %r } + +define i32 @scmp_ashr(i32 %a) { +; CHECK-LABEL: define i32 @scmp_ashr( +; CHECK-SAME: i32 [[A:%.*]]) { +; CHECK-NEXT: [[RETVAL_0:%.*]] = call i32 @llvm.scmp.i32.i32(i32 [[A]], i32 0) +; CHECK-NEXT: ret i32 [[RETVAL_0]] +; + %a.lobit = ashr i32 %a, 31 + %cmp.inv = icmp slt i32 %a, 1 + %retval.0 = select i1 %cmp.inv, i32 %a.lobit, i32 1 + ret i32 %retval.0 +} + +; select (icmp sgt X, 0), 1, ashr X, bitwidth-1 -> scmp(X, 0) +define i8 @scmp_ashr_sgt_pattern(i8 %a) { +; CHECK-LABEL: define i8 @scmp_ashr_sgt_pattern( +; CHECK-SAME: i8 [[A:%.*]]) { +; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.scmp.i8.i8(i8 [[A]], i8 0) +; CHECK-NEXT: ret i8 [[R]] +; + %a.lobit = ashr i8 %a, 7 + %cmp = icmp sgt i8 %a, 0 + %retval = select i1 %cmp, i8 1, i8 %a.lobit + ret i8 %retval +} + +; select (icmp slt X, 1), ashr X, bitwidth-1, 1 -> scmp(X, 0) +define i8 @scmp_ashr_slt_pattern(i8 %a) { +; CHECK-LABEL: define i8 @scmp_ashr_slt_pattern( +; CHECK-SAME: i8 [[A:%.*]]) { +; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.scmp.i8.i8(i8 [[A]], i8 0) +; CHECK-NEXT: ret i8 [[R]] +; + %a.lobit = ashr i8 %a, 7 + %cmp = icmp slt i8 %a, 1 + %retval = select i1 %cmp, i8 %a.lobit, i8 1 + ret i8 %retval +} + +define i8 @scmp_ashr_slt_pattern_neg(i8 %a) { +; CHECK-LABEL: define i8 @scmp_ashr_slt_pattern_neg( +; CHECK-SAME: i8 [[A:%.*]]) { +; CHECK-NEXT: [[A_LOBIT:%.*]] = ashr i8 [[A]], 4 +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[A]], 1 +; CHECK-NEXT: [[RETVAL:%.*]] = select i1 [[CMP]], i8 [[A_LOBIT]], i8 1 +; CHECK-NEXT: ret i8 [[RETVAL]] +; + %a.lobit = ashr i8 %a, 4 + %cmp = icmp slt i8 %a, 1 + %retval = select i1 %cmp, i8 %a.lobit, i8 1 + ret i8 %retval +} diff --git a/llvm/test/Transforms/InstCombine/select-extractelement-inseltpoison.ll b/llvm/test/Transforms/InstCombine/select-extractelement-inseltpoison.ll index 2348490..2d06f42 100644 --- a/llvm/test/Transforms/InstCombine/select-extractelement-inseltpoison.ll +++ b/llvm/test/Transforms/InstCombine/select-extractelement-inseltpoison.ll @@ -208,6 +208,3 @@ define <4 x i32> @extract_cond_type_mismatch(<4 x i32> %x, <4 x i32> %y, <5 x i1 %r = select i1 %cond, <4 x i32> %x, <4 x i32> %y ret <4 x i32> %r } - - -attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/Transforms/InstCombine/select-extractelement.ll b/llvm/test/Transforms/InstCombine/select-extractelement.ll index 621d278..6f80b7d 100644 --- a/llvm/test/Transforms/InstCombine/select-extractelement.ll +++ b/llvm/test/Transforms/InstCombine/select-extractelement.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -S -passes=instcombine < %s | FileCheck %s -declare void @v4float_user(<4 x float>) #0 +declare void @v4float_user(<4 x float>) -define float @extract_one_select(<4 x float> %a, <4 x float> %b, i32 %c) #0 { +define float @extract_one_select(<4 x float> %a, <4 x float> %b, i32 %c) { ; CHECK-LABEL: @extract_one_select( ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[C:%.*]], 0 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]] @@ -17,7 +17,7 @@ define float @extract_one_select(<4 x float> %a, <4 x float> %b, i32 %c) #0 { } ; Multiple extractelements -define <2 x float> @extract_two_select(<4 x float> %a, <4 x float> %b, i32 %c) #0 { +define <2 x float> @extract_two_select(<4 x float> %a, <4 x float> %b, i32 %c) { ; CHECK-LABEL: @extract_two_select( ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[C:%.*]], 0 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]] @@ -34,7 +34,7 @@ define <2 x float> @extract_two_select(<4 x float> %a, <4 x float> %b, i32 %c) # } ; Select has an extra non-extractelement user, don't change it -define float @extract_one_select_user(<4 x float> %a, <4 x float> %b, i32 %c) #0 { +define float @extract_one_select_user(<4 x float> %a, <4 x float> %b, i32 %c) { ; CHECK-LABEL: @extract_one_select_user( ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[C:%.*]], 0 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]] @@ -49,7 +49,7 @@ define float @extract_one_select_user(<4 x float> %a, <4 x float> %b, i32 %c) #0 ret float %extract } -define float @extract_one_vselect_user(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 { +define float @extract_one_vselect_user(<4 x float> %a, <4 x float> %b, <4 x i32> %c) { ; CHECK-LABEL: @extract_one_vselect_user( ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq <4 x i32> [[C:%.*]], zeroinitializer ; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> [[CMP_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]] @@ -67,7 +67,7 @@ define float @extract_one_vselect_user(<4 x float> %a, <4 x float> %b, <4 x i32> ; Do not convert the vector select into a scalar select. That would increase ; the instruction count and potentially obfuscate a vector min/max idiom. -define float @extract_one_vselect(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 { +define float @extract_one_vselect(<4 x float> %a, <4 x float> %b, <4 x i32> %c) { ; CHECK-LABEL: @extract_one_vselect( ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq <4 x i32> [[C:%.*]], zeroinitializer ; CHECK-NEXT: [[SELECT:%.*]] = select <4 x i1> [[CMP_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]] @@ -81,7 +81,7 @@ define float @extract_one_vselect(<4 x float> %a, <4 x float> %b, <4 x i32> %c) } ; Multiple extractelements from a vector select -define <2 x float> @extract_two_vselect(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 { +define <2 x float> @extract_two_vselect(<4 x float> %a, <4 x float> %b, <4 x i32> %c) { ; CHECK-LABEL: @extract_two_vselect( ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq <4 x i32> [[C:%.*]], zeroinitializer ; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> [[CMP_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]] @@ -100,7 +100,7 @@ define <2 x float> @extract_two_vselect(<4 x float> %a, <4 x float> %b, <4 x i32 ; The vector selects are not decomposed into scalar selects because that would increase ; the instruction count. Extract+insert is converted to non-lane-crossing shuffles. ; Test multiple extractelements -define <4 x float> @simple_vector_select(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 { +define <4 x float> @simple_vector_select(<4 x float> %a, <4 x float> %b, <4 x i32> %c) { ; CHECK-LABEL: @simple_vector_select( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x i32> [[C:%.*]], i64 0 @@ -232,5 +232,3 @@ define i32 @inf_loop_partial_undef(<2 x i1> %a, <2 x i1> %b, <2 x i32> %x, <2 x %t11 = extractelement <2 x i32> %p, i32 0 ret i32 %t11 } - -attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } |