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-rw-r--r--llvm/test/CodeGen/X86/call-graph-section-addrtaken.ll38
-rw-r--r--llvm/test/CodeGen/X86/call-graph-section-assembly.ll43
-rw-r--r--llvm/test/CodeGen/X86/call-graph-section-tailcall.ll13
-rw-r--r--llvm/test/CodeGen/X86/call-graph-section.ll13
-rw-r--r--llvm/test/CodeGen/X86/fast-isel-fneg.ll101
-rw-r--r--llvm/test/CodeGen/X86/fp-int-fp-cvt.ll240
-rw-r--r--llvm/test/CodeGen/X86/global-variable-partition-with-dap.ll43
-rw-r--r--llvm/test/CodeGen/X86/isel-fneg.ll208
-rw-r--r--llvm/test/CodeGen/X86/pr162812.ll98
-rw-r--r--llvm/test/CodeGen/X86/stack-protector-target.ll12
10 files changed, 663 insertions, 146 deletions
diff --git a/llvm/test/CodeGen/X86/call-graph-section-addrtaken.ll b/llvm/test/CodeGen/X86/call-graph-section-addrtaken.ll
new file mode 100644
index 0000000..2aea9c1
--- /dev/null
+++ b/llvm/test/CodeGen/X86/call-graph-section-addrtaken.ll
@@ -0,0 +1,38 @@
+;; Test if a potential indirect call target function which has internal linkage and
+;; address taken has its type ID emitted to callgraph section.
+;; This test also makes sure that callback functions which meet the above constraint
+;; are handled correctly.
+
+; RUN: llc -mtriple=x86_64-unknown-linux --call-graph-section -o - < %s | FileCheck %s
+
+declare !type !0 void @_Z6doWorkPFviE(ptr)
+
+define i32 @_Z4testv() !type !1 {
+entry:
+ call void @_Z6doWorkPFviE(ptr nonnull @_ZL10myCallbacki)
+ ret i32 0
+}
+
+; CHECK: _ZL10myCallbacki:
+; CHECK-NEXT: [[LABEL_FUNC:\.Lfunc_begin[0-9]+]]:
+define internal void @_ZL10myCallbacki(i32 %value) !type !2 {
+entry:
+ %sink = alloca i32, align 4
+ store volatile i32 %value, ptr %sink, align 4
+ %i1 = load volatile i32, ptr %sink, align 4
+ ret void
+}
+
+!0 = !{i64 0, !"_ZTSFvPFviEE.generalized"}
+!1 = !{i64 0, !"_ZTSFivE.generalized"}
+!2 = !{i64 0, !"_ZTSFviE.generalized"}
+
+; CHECK: .section .callgraph,"o",@progbits,.text
+;; Version
+; CHECK-NEXT: .byte 0
+;; Flags -- Potential indirect target so LSB is set to 1. Other bits are 0.
+; CHECK-NEXT: .byte 1
+;; Function Entry PC
+; CHECK-NEXT: .quad [[LABEL_FUNC]]
+;; Function type ID
+; CHECK-NEXT: .quad -5212364466660467813
diff --git a/llvm/test/CodeGen/X86/call-graph-section-assembly.ll b/llvm/test/CodeGen/X86/call-graph-section-assembly.ll
index f0dbc31..1aabf66 100644
--- a/llvm/test/CodeGen/X86/call-graph-section-assembly.ll
+++ b/llvm/test/CodeGen/X86/call-graph-section-assembly.ll
@@ -15,16 +15,13 @@ declare !type !2 ptr @direct_baz(ptr)
define ptr @ball() {
entry:
call void @direct_foo()
- %fp_foo_val = load ptr, ptr null, align 8
- ; CHECK: [[LABEL_TMP0:\.L.*]]:
+ %fp_foo_val = load ptr, ptr null, align 8
call void (...) %fp_foo_val(), !callee_type !0
call void @direct_foo()
- %fp_bar_val = load ptr, ptr null, align 8
- ; CHECK: [[LABEL_TMP1:\.L.*]]:
+ %fp_bar_val = load ptr, ptr null, align 8
%call_fp_bar = call i32 %fp_bar_val(i8 0), !callee_type !2
%call_fp_bar_direct = call i32 @direct_bar(i8 1)
%fp_baz_val = load ptr, ptr null, align 8
- ; CHECK: [[LABEL_TMP2:\.L.*]]:
%call_fp_baz = call ptr %fp_baz_val(ptr null), !callee_type !4
call void @direct_foo()
%call_fp_baz_direct = call ptr @direct_baz(ptr null)
@@ -32,29 +29,31 @@ entry:
ret ptr %call_fp_baz
}
-; CHECK: .section .callgraph,"o",@progbits,.text
-
-; CHECK-NEXT: .quad 0
-; CHECK-NEXT: .quad [[LABEL_FUNC]]
-; CHECK-NEXT: .quad 1
-; CHECK-NEXT: .quad 3
!0 = !{!1}
!1 = !{i64 0, !"_ZTSFvE.generalized"}
-;; Test for MD5 hash of _ZTSFvE.generalized and the generated temporary callsite label.
-; CHECK-NEXT: .quad 4524972987496481828
-; CHECK-NEXT: .quad [[LABEL_TMP0]]
!2 = !{!3}
!3 = !{i64 0, !"_ZTSFicE.generalized"}
-;; Test for MD5 hash of _ZTSFicE.generalized and the generated temporary callsite label.
-; CHECK-NEXT: .quad 3498816979441845844
-; CHECK-NEXT: .quad [[LABEL_TMP1]]
!4 = !{!5}
!5 = !{i64 0, !"_ZTSFPvS_E.generalized"}
-;; Test for MD5 hash of _ZTSFPvS_E.generalized and the generated temporary callsite label.
-; CHECK-NEXT: .quad 8646233951371320954
-; CHECK-NEXT: .quad [[LABEL_TMP2]]
-;; Test for number of direct calls and {callsite_label, callee} pairs.
-; CHECK-NEXT: .quad 3
+
+; CHECK: .section .callgraph,"o",@progbits,.text
+;; Version
+; CHECK-NEXT: .byte 0
+;; Flags
+; CHECK-NEXT: .byte 7
+;; Function Entry PC
+; CHECK-NEXT: .quad [[LABEL_FUNC]]
+;; Function type ID -- set to 0 as no type metadata attached to function.
+; CHECK-NEXT: .quad 0
+;; Number of unique direct callees.
+; CHECK-NEXT: .byte 3
+;; Direct callees.
; CHECK-NEXT: .quad direct_foo
; CHECK-NEXT: .quad direct_bar
; CHECK-NEXT: .quad direct_baz
+;; Number of unique indirect target type IDs.
+; CHECK-NEXT: .byte 3
+;; Indirect type IDs.
+; CHECK-NEXT: .quad 4524972987496481828
+; CHECK-NEXT: .quad 3498816979441845844
+; CHECK-NEXT: .quad 8646233951371320954
diff --git a/llvm/test/CodeGen/X86/call-graph-section-tailcall.ll b/llvm/test/CodeGen/X86/call-graph-section-tailcall.ll
index fa14a98..34dc5b8 100644
--- a/llvm/test/CodeGen/X86/call-graph-section-tailcall.ll
+++ b/llvm/test/CodeGen/X86/call-graph-section-tailcall.ll
@@ -22,13 +22,14 @@ declare !type !2 i32 @foo(i8 signext)
declare !type !2 i32 @bar(i8 signext)
-;; Check that the numeric type id (md5 hash) for the below type ids are emitted
-;; to the callgraph section.
-
-; CHECK: Hex dump of section '.callgraph':
-
!0 = !{i64 0, !"_ZTSFiPvcE.generalized"}
!1 = !{!2}
-; CHECK-DAG: 5486bc59 814b8e30
!2 = !{i64 0, !"_ZTSFicE.generalized"}
!3 = !{i64 0, !"_ZTSFiiE.generalized"}
+
+; CHECK: Hex dump of section '.callgraph':
+; CHECK-NEXT: 0x00000000 00050000 00000000 00008e19 0b7f3326
+; CHECK-NEXT: 0x00000010 e3000154 86bc5981 4b8e3000 05000000
+;; Verify that the type id 0x308e4b8159bc8654 is in section.
+; CHECK-NEXT: 0x00000020 00000000 00a150b8 3e0cfe3c b2015486
+; CHECK-NEXT: 0x00000030 bc59814b 8e30
diff --git a/llvm/test/CodeGen/X86/call-graph-section.ll b/llvm/test/CodeGen/X86/call-graph-section.ll
index 66d009c..c144a24 100644
--- a/llvm/test/CodeGen/X86/call-graph-section.ll
+++ b/llvm/test/CodeGen/X86/call-graph-section.ll
@@ -22,15 +22,16 @@ entry:
;; Check that the numeric type id (md5 hash) for the below type ids are emitted
;; to the callgraph section.
-
-; CHECK: Hex dump of section '.callgraph':
-
-; CHECK-DAG: 2444f731 f5eecb3e
!0 = !{i64 0, !"_ZTSFvE.generalized"}
!1 = !{!0}
-; CHECK-DAG: 5486bc59 814b8e30
!2 = !{i64 0, !"_ZTSFicE.generalized"}
!3 = !{!2}
-; CHECK-DAG: 7ade6814 f897fd77
!4 = !{!5}
!5 = !{i64 0, !"_ZTSFPvS_E.generalized"}
+
+;; Make sure following type IDs are in call graph section
+;; 0x5eecb3e2444f731f, 0x814b8e305486bc59, 0xf897fd777ade6814
+; CHECK: Hex dump of section '.callgraph':
+; CHECK-NEXT: 0x00000000 00050000 00000000 00000000 00000000
+; CHECK-NEXT: 0x00000010 00000324 44f731f5 eecb3e54 86bc5981
+; CHECK-NEXT: 0x00000020 4b8e307a de6814f8 97fd77
diff --git a/llvm/test/CodeGen/X86/fast-isel-fneg.ll b/llvm/test/CodeGen/X86/fast-isel-fneg.ll
deleted file mode 100644
index 128f5ee..0000000
--- a/llvm/test/CodeGen/X86/fast-isel-fneg.ll
+++ /dev/null
@@ -1,101 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64-apple-darwin10 | FileCheck %s
-; RUN: llc < %s -fast-isel -mtriple=i686-- -mattr=+sse2 | FileCheck --check-prefix=SSE2 %s
-
-define double @fneg_f64(double %x) nounwind {
-; CHECK-LABEL: fneg_f64:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: movq %xmm0, %rax
-; CHECK-NEXT: movabsq $-9223372036854775808, %rcx ## imm = 0x8000000000000000
-; CHECK-NEXT: xorq %rax, %rcx
-; CHECK-NEXT: movq %rcx, %xmm0
-; CHECK-NEXT: retq
-;
-; SSE2-LABEL: fneg_f64:
-; SSE2: # %bb.0:
-; SSE2-NEXT: pushl %ebp
-; SSE2-NEXT: movl %esp, %ebp
-; SSE2-NEXT: andl $-8, %esp
-; SSE2-NEXT: subl $8, %esp
-; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE2-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
-; SSE2-NEXT: movlps %xmm0, (%esp)
-; SSE2-NEXT: fldl (%esp)
-; SSE2-NEXT: movl %ebp, %esp
-; SSE2-NEXT: popl %ebp
-; SSE2-NEXT: retl
- %y = fneg double %x
- ret double %y
-}
-
-define float @fneg_f32(float %x) nounwind {
-; CHECK-LABEL: fneg_f32:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: movd %xmm0, %eax
-; CHECK-NEXT: xorl $2147483648, %eax ## imm = 0x80000000
-; CHECK-NEXT: movd %eax, %xmm0
-; CHECK-NEXT: retq
-;
-; SSE2-LABEL: fneg_f32:
-; SSE2: # %bb.0:
-; SSE2-NEXT: pushl %eax
-; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE2-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
-; SSE2-NEXT: movss %xmm0, (%esp)
-; SSE2-NEXT: flds (%esp)
-; SSE2-NEXT: popl %eax
-; SSE2-NEXT: retl
- %y = fneg float %x
- ret float %y
-}
-
-define void @fneg_f64_mem(ptr %x, ptr %y) nounwind {
-; CHECK-LABEL: fneg_f64_mem:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
-; CHECK-NEXT: movq %xmm0, %rax
-; CHECK-NEXT: movabsq $-9223372036854775808, %rcx ## imm = 0x8000000000000000
-; CHECK-NEXT: xorq %rax, %rcx
-; CHECK-NEXT: movq %rcx, %xmm0
-; CHECK-NEXT: movq %xmm0, (%rsi)
-; CHECK-NEXT: retq
-;
-; SSE2-LABEL: fneg_f64_mem:
-; SSE2: # %bb.0:
-; SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
-; SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE2-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
-; SSE2-NEXT: movsd %xmm0, (%eax)
-; SSE2-NEXT: retl
- %a = load double, ptr %x
- %b = fneg double %a
- store double %b, ptr %y
- ret void
-}
-
-define void @fneg_f32_mem(ptr %x, ptr %y) nounwind {
-; CHECK-LABEL: fneg_f32_mem:
-; CHECK: ## %bb.0:
-; CHECK-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-NEXT: movd %xmm0, %eax
-; CHECK-NEXT: xorl $2147483648, %eax ## imm = 0x80000000
-; CHECK-NEXT: movd %eax, %xmm0
-; CHECK-NEXT: movd %xmm0, (%rsi)
-; CHECK-NEXT: retq
-;
-; SSE2-LABEL: fneg_f32_mem:
-; SSE2: # %bb.0:
-; SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
-; SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; SSE2-NEXT: movd %xmm0, %ecx
-; SSE2-NEXT: xorl $2147483648, %ecx # imm = 0x80000000
-; SSE2-NEXT: movd %ecx, %xmm0
-; SSE2-NEXT: movd %xmm0, (%eax)
-; SSE2-NEXT: retl
- %a = load float, ptr %x
- %b = fneg float %a
- store float %b, ptr %y
- ret void
-}
diff --git a/llvm/test/CodeGen/X86/fp-int-fp-cvt.ll b/llvm/test/CodeGen/X86/fp-int-fp-cvt.ll
new file mode 100644
index 0000000..b6c17ce
--- /dev/null
+++ b/llvm/test/CodeGen/X86/fp-int-fp-cvt.ll
@@ -0,0 +1,240 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=x86-64 | FileCheck %s --check-prefixes=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX,AVX2
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX,AVX512,AVX512-VL
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=x86-64-v4 -mattr=-avx512vl | FileCheck %s --check-prefixes=AVX,AVX512,AVX512-NOVL
+
+;
+; fptosi -> sitofp
+;
+
+define double @scvtf64_i32(double %a0) {
+; SSE-LABEL: scvtf64_i32:
+; SSE: # %bb.0:
+; SSE-NEXT: cvttpd2dq %xmm0, %xmm0
+; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: scvtf64_i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vcvttpd2dq %xmm0, %xmm0
+; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0
+; AVX-NEXT: retq
+ %ii = fptosi double %a0 to i32
+ %ff = sitofp i32 %ii to double
+ ret double %ff
+}
+
+define double @scvtf64_i64(double %a0) {
+; SSE-LABEL: scvtf64_i64:
+; SSE: # %bb.0:
+; SSE-NEXT: cvttsd2si %xmm0, %rax
+; SSE-NEXT: xorps %xmm0, %xmm0
+; SSE-NEXT: cvtsi2sd %rax, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: scvtf64_i64:
+; AVX: # %bb.0:
+; AVX-NEXT: vcvttsd2si %xmm0, %rax
+; AVX-NEXT: vcvtsi2sd %rax, %xmm15, %xmm0
+; AVX-NEXT: retq
+ %ii = fptosi double %a0 to i64
+ %ff = sitofp i64 %ii to double
+ ret double %ff
+}
+
+define float @scvtf32_i32(float %a0) {
+; SSE-LABEL: scvtf32_i32:
+; SSE: # %bb.0:
+; SSE-NEXT: cvttps2dq %xmm0, %xmm0
+; SSE-NEXT: cvtdq2ps %xmm0, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: scvtf32_i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vcvttps2dq %xmm0, %xmm0
+; AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
+; AVX-NEXT: retq
+ %ii = fptosi float %a0 to i32
+ %ff = sitofp i32 %ii to float
+ ret float %ff
+}
+
+define float @scvtf32_i64(float %a0) {
+; SSE-LABEL: scvtf32_i64:
+; SSE: # %bb.0:
+; SSE-NEXT: cvttss2si %xmm0, %rax
+; SSE-NEXT: xorps %xmm0, %xmm0
+; SSE-NEXT: cvtsi2ss %rax, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: scvtf32_i64:
+; AVX: # %bb.0:
+; AVX-NEXT: vcvttss2si %xmm0, %rax
+; AVX-NEXT: vcvtsi2ss %rax, %xmm15, %xmm0
+; AVX-NEXT: retq
+ %ii = fptosi float %a0 to i64
+ %ff = sitofp i64 %ii to float
+ ret float %ff
+}
+
+;
+; fptoui -> uitofp
+;
+
+define double @ucvtf64_i32(double %a0) {
+; SSE-LABEL: ucvtf64_i32:
+; SSE: # %bb.0:
+; SSE-NEXT: cvttsd2si %xmm0, %rax
+; SSE-NEXT: movl %eax, %eax
+; SSE-NEXT: xorps %xmm0, %xmm0
+; SSE-NEXT: cvtsi2sd %rax, %xmm0
+; SSE-NEXT: retq
+;
+; AVX2-LABEL: ucvtf64_i32:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vcvttsd2si %xmm0, %rax
+; AVX2-NEXT: movl %eax, %eax
+; AVX2-NEXT: vcvtsi2sd %rax, %xmm15, %xmm0
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: ucvtf64_i32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vcvttsd2usi %xmm0, %eax
+; AVX512-NEXT: vcvtusi2sd %eax, %xmm15, %xmm0
+; AVX512-NEXT: retq
+ %ii = fptoui double %a0 to i32
+ %ff = uitofp i32 %ii to double
+ ret double %ff
+}
+
+define double @ucvtf64_i64(double %a0) {
+; SSE-LABEL: ucvtf64_i64:
+; SSE: # %bb.0:
+; SSE-NEXT: cvttsd2si %xmm0, %rax
+; SSE-NEXT: movq %rax, %rcx
+; SSE-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: cvttsd2si %xmm0, %rdx
+; SSE-NEXT: sarq $63, %rcx
+; SSE-NEXT: andq %rcx, %rdx
+; SSE-NEXT: orq %rax, %rdx
+; SSE-NEXT: movq %rdx, %xmm1
+; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
+; SSE-NEXT: subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT: movapd %xmm1, %xmm0
+; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
+; SSE-NEXT: addsd %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX2-LABEL: ucvtf64_i64:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vcvttsd2si %xmm0, %rax
+; AVX2-NEXT: movq %rax, %rcx
+; AVX2-NEXT: vsubsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: sarq $63, %rcx
+; AVX2-NEXT: vcvttsd2si %xmm0, %rdx
+; AVX2-NEXT: andq %rcx, %rdx
+; AVX2-NEXT: orq %rax, %rdx
+; AVX2-NEXT: vmovq %rdx, %xmm0
+; AVX2-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
+; AVX2-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
+; AVX2-NEXT: vaddsd %xmm0, %xmm1, %xmm0
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: ucvtf64_i64:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vcvttsd2usi %xmm0, %rax
+; AVX512-NEXT: vcvtusi2sd %rax, %xmm15, %xmm0
+; AVX512-NEXT: retq
+ %ii = fptoui double %a0 to i64
+ %ff = uitofp i64 %ii to double
+ ret double %ff
+}
+
+define float @ucvtf32_i32(float %a0) {
+; SSE-LABEL: ucvtf32_i32:
+; SSE: # %bb.0:
+; SSE-NEXT: cvttss2si %xmm0, %rax
+; SSE-NEXT: movl %eax, %eax
+; SSE-NEXT: xorps %xmm0, %xmm0
+; SSE-NEXT: cvtsi2ss %rax, %xmm0
+; SSE-NEXT: retq
+;
+; AVX2-LABEL: ucvtf32_i32:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vcvttss2si %xmm0, %rax
+; AVX2-NEXT: movl %eax, %eax
+; AVX2-NEXT: vcvtsi2ss %rax, %xmm15, %xmm0
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: ucvtf32_i32:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vcvttss2usi %xmm0, %eax
+; AVX512-NEXT: vcvtusi2ss %eax, %xmm15, %xmm0
+; AVX512-NEXT: retq
+ %ii = fptoui float %a0 to i32
+ %ff = uitofp i32 %ii to float
+ ret float %ff
+}
+
+define float @ucvtf32_i64(float %a0) {
+; SSE-LABEL: ucvtf32_i64:
+; SSE: # %bb.0:
+; SSE-NEXT: cvttss2si %xmm0, %rcx
+; SSE-NEXT: movq %rcx, %rdx
+; SSE-NEXT: sarq $63, %rdx
+; SSE-NEXT: subss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: cvttss2si %xmm0, %rax
+; SSE-NEXT: andq %rdx, %rax
+; SSE-NEXT: orq %rcx, %rax
+; SSE-NEXT: js .LBB7_1
+; SSE-NEXT: # %bb.2:
+; SSE-NEXT: xorps %xmm0, %xmm0
+; SSE-NEXT: cvtsi2ss %rax, %xmm0
+; SSE-NEXT: retq
+; SSE-NEXT: .LBB7_1:
+; SSE-NEXT: movq %rax, %rcx
+; SSE-NEXT: shrq %rcx
+; SSE-NEXT: andl $1, %eax
+; SSE-NEXT: orq %rcx, %rax
+; SSE-NEXT: xorps %xmm0, %xmm0
+; SSE-NEXT: cvtsi2ss %rax, %xmm0
+; SSE-NEXT: addss %xmm0, %xmm0
+; SSE-NEXT: retq
+;
+; AVX2-LABEL: ucvtf32_i64:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vcvttss2si %xmm0, %rcx
+; AVX2-NEXT: movq %rcx, %rdx
+; AVX2-NEXT: sarq $63, %rdx
+; AVX2-NEXT: vsubss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vcvttss2si %xmm0, %rax
+; AVX2-NEXT: andq %rdx, %rax
+; AVX2-NEXT: orq %rcx, %rax
+; AVX2-NEXT: js .LBB7_1
+; AVX2-NEXT: # %bb.2:
+; AVX2-NEXT: vcvtsi2ss %rax, %xmm15, %xmm0
+; AVX2-NEXT: retq
+; AVX2-NEXT: .LBB7_1:
+; AVX2-NEXT: movq %rax, %rcx
+; AVX2-NEXT: shrq %rcx
+; AVX2-NEXT: andl $1, %eax
+; AVX2-NEXT: orq %rcx, %rax
+; AVX2-NEXT: vcvtsi2ss %rax, %xmm15, %xmm0
+; AVX2-NEXT: vaddss %xmm0, %xmm0, %xmm0
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: ucvtf32_i64:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vcvttss2usi %xmm0, %rax
+; AVX512-NEXT: vcvtusi2ss %rax, %xmm15, %xmm0
+; AVX512-NEXT: retq
+ %ii = fptoui float %a0 to i64
+ %ff = uitofp i64 %ii to float
+ ret float %ff
+}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX512-NOVL: {{.*}}
+; AVX512-VL: {{.*}}
diff --git a/llvm/test/CodeGen/X86/global-variable-partition-with-dap.ll b/llvm/test/CodeGen/X86/global-variable-partition-with-dap.ll
new file mode 100644
index 0000000..a0c243b
--- /dev/null
+++ b/llvm/test/CodeGen/X86/global-variable-partition-with-dap.ll
@@ -0,0 +1,43 @@
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+;; A minimal test case. llc will crash if global variables already has a section
+;; prefix. Subsequent PRs will expand on this test case to test the hotness
+;; reconciliation implementation.
+
+; RUN: not llc -mtriple=x86_64-unknown-linux-gnu -relocation-model=pic \
+; RUN: -partition-static-data-sections=true \
+; RUN: -data-sections=true -unique-section-names=false \
+; RUN: %s -o - 2>&1 | FileCheck %s --check-prefix=ERR
+
+; ERR: Global variable hot_bss already has a section prefix hot
+
+@hot_bss = internal global i32 0, !section_prefix !17
+
+define void @hot_func() !prof !14 {
+ %9 = load i32, ptr @hot_bss
+ %11 = call i32 (...) @func_taking_arbitrary_param(i32 %9)
+ ret void
+}
+
+declare i32 @func_taking_arbitrary_param(...)
+
+!llvm.module.flags = !{!1}
+
+!1 = !{i32 1, !"ProfileSummary", !2}
+!2 = !{!3, !4, !5, !6, !7, !8, !9, !10}
+!3 = !{!"ProfileFormat", !"InstrProf"}
+!4 = !{!"TotalCount", i64 1460183}
+!5 = !{!"MaxCount", i64 849024}
+!6 = !{!"MaxInternalCount", i64 32769}
+!7 = !{!"MaxFunctionCount", i64 849024}
+!8 = !{!"NumCounts", i64 23627}
+!9 = !{!"NumFunctions", i64 3271}
+!10 = !{!"DetailedSummary", !11}
+!11 = !{!12, !13}
+!12 = !{i32 990000, i64 166, i32 73}
+!13 = !{i32 999999, i64 3, i32 1443}
+!14 = !{!"function_entry_count", i64 100000}
+!15 = !{!"function_entry_count", i64 1}
+!16 = !{!"branch_weights", i32 1, i32 99999}
+!17 = !{!"section_prefix", !"hot"}
diff --git a/llvm/test/CodeGen/X86/isel-fneg.ll b/llvm/test/CodeGen/X86/isel-fneg.ll
new file mode 100644
index 0000000..77b3f26
--- /dev/null
+++ b/llvm/test/CodeGen/X86/isel-fneg.ll
@@ -0,0 +1,208 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=i686-linux-gnu -fast-isel | FileCheck %s --check-prefixes=X86,FASTISEL-X86
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel=0 -fast-isel=0 | FileCheck %s --check-prefixes=X86,SDAG-X86
+; DISABLED: llc < %s -mtriple=i686-linux-gnu -global-isel=1 -global-isel-abort=2 | FileCheck %s --check-prefixes=X86,GISEL-X86
+; RUN: llc < %s -mtriple=i686-linux-gnu -fast-isel -mattr=+sse | FileCheck %s --check-prefixes=X86,SSE-X86,FASTISEL-SSE-X86
+; RUN: llc < %s -mtriple=i686-linux-gnu -global-isel=0 -fast-isel=0 -mattr=+sse | FileCheck %s --check-prefixes=X86,SSE-X86,SDAG-SSE-X86
+; DISABLED: llc < %s -mtriple=i686-linux-gnu -global-isel=1 -global-isel-abort=2 -mattr=+sse | FileCheck %s --check-prefixes=X86,SSE-X86,GISEL-SSE-X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnu -fast-isel -mattr=+sse | FileCheck %s --check-prefixes=X64,SSE-X64,FASTISEL-SSE-X64
+; RUN: llc < %s -mtriple=x86_64-linux-gnu -global-isel=0 -fast-isel=0 -mattr=+sse | FileCheck %s --check-prefixes=X64,SSE-X64,SDAG-SSE-X64
+; RUN: llc < %s -mtriple=x86_64-linux-gnu -global-isel=1 -global-isel-abort=2 -mattr=+sse | FileCheck %s --check-prefixes=X64,SSE-X64,GISEL-SSE-X64
+
+define double @fneg_f64(double %x) nounwind {
+; X86-LABEL: fneg_f64:
+; X86: # %bb.0:
+; X86-NEXT: fldl {{[0-9]+}}(%esp)
+; X86-NEXT: fchs
+; X86-NEXT: retl
+;
+; FASTISEL-SSE-X64-LABEL: fneg_f64:
+; FASTISEL-SSE-X64: # %bb.0:
+; FASTISEL-SSE-X64-NEXT: movq %xmm0, %rax
+; FASTISEL-SSE-X64-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; FASTISEL-SSE-X64-NEXT: xorq %rax, %rcx
+; FASTISEL-SSE-X64-NEXT: movq %rcx, %xmm0
+; FASTISEL-SSE-X64-NEXT: retq
+;
+; SDAG-SSE-X64-LABEL: fneg_f64:
+; SDAG-SSE-X64: # %bb.0:
+; SDAG-SSE-X64-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SDAG-SSE-X64-NEXT: retq
+;
+; GISEL-SSE-X64-LABEL: fneg_f64:
+; GISEL-SSE-X64: # %bb.0:
+; GISEL-SSE-X64-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
+; GISEL-SSE-X64-NEXT: movq %xmm0, %rcx
+; GISEL-SSE-X64-NEXT: xorq %rax, %rcx
+; GISEL-SSE-X64-NEXT: movq %rcx, %xmm0
+; GISEL-SSE-X64-NEXT: retq
+ %y = fneg double %x
+ ret double %y
+}
+
+define float @fneg_f32(float %x) nounwind {
+; FASTISEL-X86-LABEL: fneg_f32:
+; FASTISEL-X86: # %bb.0:
+; FASTISEL-X86-NEXT: flds {{[0-9]+}}(%esp)
+; FASTISEL-X86-NEXT: fchs
+; FASTISEL-X86-NEXT: retl
+;
+; SDAG-X86-LABEL: fneg_f32:
+; SDAG-X86: # %bb.0:
+; SDAG-X86-NEXT: flds {{[0-9]+}}(%esp)
+; SDAG-X86-NEXT: fchs
+; SDAG-X86-NEXT: retl
+;
+; SSE-X86-LABEL: fneg_f32:
+; SSE-X86: # %bb.0:
+; SSE-X86-NEXT: pushl %eax
+; SSE-X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE-X86-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; SSE-X86-NEXT: movss %xmm0, (%esp)
+; SSE-X86-NEXT: flds (%esp)
+; SSE-X86-NEXT: popl %eax
+; SSE-X86-NEXT: retl
+;
+; FASTISEL-SSE-X64-LABEL: fneg_f32:
+; FASTISEL-SSE-X64: # %bb.0:
+; FASTISEL-SSE-X64-NEXT: movd %xmm0, %eax
+; FASTISEL-SSE-X64-NEXT: xorl $2147483648, %eax # imm = 0x80000000
+; FASTISEL-SSE-X64-NEXT: movd %eax, %xmm0
+; FASTISEL-SSE-X64-NEXT: retq
+;
+; SDAG-SSE-X64-LABEL: fneg_f32:
+; SDAG-SSE-X64: # %bb.0:
+; SDAG-SSE-X64-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SDAG-SSE-X64-NEXT: retq
+;
+; GISEL-SSE-X64-LABEL: fneg_f32:
+; GISEL-SSE-X64: # %bb.0:
+; GISEL-SSE-X64-NEXT: movd %xmm0, %eax
+; GISEL-SSE-X64-NEXT: addl $-2147483648, %eax # imm = 0x80000000
+; GISEL-SSE-X64-NEXT: movd %eax, %xmm0
+; GISEL-SSE-X64-NEXT: retq
+ %y = fneg float %x
+ ret float %y
+}
+
+define void @fneg_f64_mem(ptr %x, ptr %y) nounwind {
+; X86-LABEL: fneg_f64_mem:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: fldl (%ecx)
+; X86-NEXT: fchs
+; X86-NEXT: fstpl (%eax)
+; X86-NEXT: retl
+;
+; FASTISEL-SSE-X64-LABEL: fneg_f64_mem:
+; FASTISEL-SSE-X64: # %bb.0:
+; FASTISEL-SSE-X64-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
+; FASTISEL-SSE-X64-NEXT: movq %xmm0, %rax
+; FASTISEL-SSE-X64-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; FASTISEL-SSE-X64-NEXT: xorq %rax, %rcx
+; FASTISEL-SSE-X64-NEXT: movq %rcx, %xmm0
+; FASTISEL-SSE-X64-NEXT: movq %xmm0, (%rsi)
+; FASTISEL-SSE-X64-NEXT: retq
+;
+; SDAG-SSE-X64-LABEL: fneg_f64_mem:
+; SDAG-SSE-X64: # %bb.0:
+; SDAG-SSE-X64-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
+; SDAG-SSE-X64-NEXT: xorq (%rdi), %rax
+; SDAG-SSE-X64-NEXT: movq %rax, (%rsi)
+; SDAG-SSE-X64-NEXT: retq
+;
+; GISEL-SSE-X64-LABEL: fneg_f64_mem:
+; GISEL-SSE-X64: # %bb.0:
+; GISEL-SSE-X64-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
+; GISEL-SSE-X64-NEXT: xorq (%rdi), %rax
+; GISEL-SSE-X64-NEXT: movq %rax, (%rsi)
+; GISEL-SSE-X64-NEXT: retq
+ %a = load double, ptr %x
+ %b = fneg double %a
+ store double %b, ptr %y
+ ret void
+}
+
+define void @fneg_f32_mem(ptr %x, ptr %y) nounwind {
+; FASTISEL-X86-LABEL: fneg_f32_mem:
+; FASTISEL-X86: # %bb.0:
+; FASTISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; FASTISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; FASTISEL-X86-NEXT: movl $-2147483648, %edx # imm = 0x80000000
+; FASTISEL-X86-NEXT: xorl (%ecx), %edx
+; FASTISEL-X86-NEXT: movl %edx, (%eax)
+; FASTISEL-X86-NEXT: retl
+;
+; SDAG-X86-LABEL: fneg_f32_mem:
+; SDAG-X86: # %bb.0:
+; SDAG-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; SDAG-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; SDAG-X86-NEXT: movl $-2147483648, %edx # imm = 0x80000000
+; SDAG-X86-NEXT: xorl (%ecx), %edx
+; SDAG-X86-NEXT: movl %edx, (%eax)
+; SDAG-X86-NEXT: retl
+;
+; FASTISEL-SSE-X86-LABEL: fneg_f32_mem:
+; FASTISEL-SSE-X86: # %bb.0:
+; FASTISEL-SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; FASTISEL-SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; FASTISEL-SSE-X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; FASTISEL-SSE-X86-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; FASTISEL-SSE-X86-NEXT: movss %xmm0, (%eax)
+; FASTISEL-SSE-X86-NEXT: retl
+;
+; SDAG-SSE-X86-LABEL: fneg_f32_mem:
+; SDAG-SSE-X86: # %bb.0:
+; SDAG-SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; SDAG-SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; SDAG-SSE-X86-NEXT: movl $-2147483648, %edx # imm = 0x80000000
+; SDAG-SSE-X86-NEXT: xorl (%ecx), %edx
+; SDAG-SSE-X86-NEXT: movl %edx, (%eax)
+; SDAG-SSE-X86-NEXT: retl
+;
+; FASTISEL-SSE-X64-LABEL: fneg_f32_mem:
+; FASTISEL-SSE-X64: # %bb.0:
+; FASTISEL-SSE-X64-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; FASTISEL-SSE-X64-NEXT: movd %xmm0, %eax
+; FASTISEL-SSE-X64-NEXT: xorl $2147483648, %eax # imm = 0x80000000
+; FASTISEL-SSE-X64-NEXT: movd %eax, %xmm0
+; FASTISEL-SSE-X64-NEXT: movd %xmm0, (%rsi)
+; FASTISEL-SSE-X64-NEXT: retq
+;
+; SDAG-SSE-X64-LABEL: fneg_f32_mem:
+; SDAG-SSE-X64: # %bb.0:
+; SDAG-SSE-X64-NEXT: movl $-2147483648, %eax # imm = 0x80000000
+; SDAG-SSE-X64-NEXT: xorl (%rdi), %eax
+; SDAG-SSE-X64-NEXT: movl %eax, (%rsi)
+; SDAG-SSE-X64-NEXT: retq
+;
+; GISEL-SSE-X64-LABEL: fneg_f32_mem:
+; GISEL-SSE-X64: # %bb.0:
+; GISEL-SSE-X64-NEXT: movl $-2147483648, %eax # imm = 0x80000000
+; GISEL-SSE-X64-NEXT: xorl (%rdi), %eax
+; GISEL-SSE-X64-NEXT: movl %eax, (%rsi)
+; GISEL-SSE-X64-NEXT: retq
+ %a = load float, ptr %x
+ %b = fneg float %a
+ store float %b, ptr %y
+ ret void
+}
+
+define x86_fp80 @test_fp80(x86_fp80 %a) nounwind {
+; X86-LABEL: test_fp80:
+; X86: # %bb.0:
+; X86-NEXT: fldt {{[0-9]+}}(%esp)
+; X86-NEXT: fchs
+; X86-NEXT: retl
+;
+; X64-LABEL: test_fp80:
+; X64: # %bb.0:
+; X64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X64-NEXT: fchs
+; X64-NEXT: retq
+ %1 = fneg x86_fp80 %a
+ ret x86_fp80 %1
+}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; SSE-X64: {{.*}}
diff --git a/llvm/test/CodeGen/X86/pr162812.ll b/llvm/test/CodeGen/X86/pr162812.ll
new file mode 100644
index 0000000..4ea3101
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr162812.ll
@@ -0,0 +1,98 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=SSE2
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE42
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX2
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX512
+
+define <32 x i8> @PR162812(<32 x i8> %a, <32 x i8> %mask) {
+; SSE2-LABEL: PR162812:
+; SSE2: # %bb.0:
+; SSE2-NEXT: psrlw $2, %xmm2
+; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [8224,8224,8224,8224,8224,8224,8224,8224]
+; SSE2-NEXT: pand %xmm4, %xmm2
+; SSE2-NEXT: paddb %xmm2, %xmm2
+; SSE2-NEXT: paddb %xmm2, %xmm2
+; SSE2-NEXT: pxor %xmm5, %xmm5
+; SSE2-NEXT: pxor %xmm6, %xmm6
+; SSE2-NEXT: pcmpgtb %xmm2, %xmm6
+; SSE2-NEXT: movdqa %xmm6, %xmm2
+; SSE2-NEXT: pandn %xmm0, %xmm2
+; SSE2-NEXT: paddb %xmm0, %xmm0
+; SSE2-NEXT: pand %xmm6, %xmm0
+; SSE2-NEXT: por %xmm2, %xmm0
+; SSE2-NEXT: psrlw $2, %xmm3
+; SSE2-NEXT: pand %xmm4, %xmm3
+; SSE2-NEXT: paddb %xmm3, %xmm3
+; SSE2-NEXT: paddb %xmm3, %xmm3
+; SSE2-NEXT: pcmpgtb %xmm3, %xmm5
+; SSE2-NEXT: movdqa %xmm5, %xmm2
+; SSE2-NEXT: pandn %xmm1, %xmm2
+; SSE2-NEXT: paddb %xmm1, %xmm1
+; SSE2-NEXT: pand %xmm5, %xmm1
+; SSE2-NEXT: por %xmm2, %xmm1
+; SSE2-NEXT: retq
+;
+; SSE42-LABEL: PR162812:
+; SSE42: # %bb.0:
+; SSE42-NEXT: movdqa %xmm2, %xmm5
+; SSE42-NEXT: movdqa %xmm0, %xmm2
+; SSE42-NEXT: movdqa %xmm0, %xmm6
+; SSE42-NEXT: psllw $2, %xmm6
+; SSE42-NEXT: movdqa {{.*#+}} xmm7 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
+; SSE42-NEXT: pand %xmm7, %xmm6
+; SSE42-NEXT: psrlw $2, %xmm5
+; SSE42-NEXT: movdqa {{.*#+}} xmm4 = [8224,8224,8224,8224,8224,8224,8224,8224]
+; SSE42-NEXT: pand %xmm4, %xmm5
+; SSE42-NEXT: paddb %xmm5, %xmm5
+; SSE42-NEXT: movdqa %xmm5, %xmm0
+; SSE42-NEXT: pblendvb %xmm0, %xmm6, %xmm2
+; SSE42-NEXT: movdqa %xmm2, %xmm6
+; SSE42-NEXT: paddb %xmm2, %xmm6
+; SSE42-NEXT: paddb %xmm5, %xmm5
+; SSE42-NEXT: movdqa %xmm5, %xmm0
+; SSE42-NEXT: pblendvb %xmm0, %xmm6, %xmm2
+; SSE42-NEXT: movdqa %xmm1, %xmm5
+; SSE42-NEXT: psllw $2, %xmm5
+; SSE42-NEXT: pand %xmm7, %xmm5
+; SSE42-NEXT: psrlw $2, %xmm3
+; SSE42-NEXT: pand %xmm3, %xmm4
+; SSE42-NEXT: paddb %xmm4, %xmm4
+; SSE42-NEXT: movdqa %xmm4, %xmm0
+; SSE42-NEXT: pblendvb %xmm0, %xmm5, %xmm1
+; SSE42-NEXT: movdqa %xmm1, %xmm3
+; SSE42-NEXT: paddb %xmm1, %xmm3
+; SSE42-NEXT: paddb %xmm4, %xmm4
+; SSE42-NEXT: movdqa %xmm4, %xmm0
+; SSE42-NEXT: pblendvb %xmm0, %xmm3, %xmm1
+; SSE42-NEXT: movdqa %xmm2, %xmm0
+; SSE42-NEXT: retq
+;
+; AVX2-LABEL: PR162812:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpsllw $2, %ymm0, %ymm2
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
+; AVX2-NEXT: vpsrlw $2, %ymm1, %ymm1
+; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1
+; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm2
+; AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1
+; AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: PR162812:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpsllw $2, %ymm0, %ymm2
+; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm2
+; AVX512-NEXT: vpsrlw $2, %ymm1, %ymm1
+; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm1
+; AVX512-NEXT: vpaddb %ymm1, %ymm1, %ymm1
+; AVX512-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
+; AVX512-NEXT: vpaddb %ymm0, %ymm0, %ymm2
+; AVX512-NEXT: vpaddb %ymm1, %ymm1, %ymm1
+; AVX512-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
+; AVX512-NEXT: retq
+ %1 = lshr <32 x i8> %mask, splat (i8 7)
+ %ret = shl <32 x i8> %a, %1
+ ret <32 x i8> %ret
+}
diff --git a/llvm/test/CodeGen/X86/stack-protector-target.ll b/llvm/test/CodeGen/X86/stack-protector-target.ll
index f7c5680..4ba0302 100644
--- a/llvm/test/CodeGen/X86/stack-protector-target.ll
+++ b/llvm/test/CodeGen/X86/stack-protector-target.ll
@@ -2,13 +2,8 @@
; RUN: llc -mtriple=i386-linux < %s -o - | FileCheck --check-prefix=I386-TLS %s
; RUN: llc -mtriple=x86_64-linux < %s -o - | FileCheck --check-prefix=X64-TLS %s
-; RUN: llc -mtriple=i386-linux-android < %s -o - | FileCheck --check-prefix=I386 %s
-; RUN: llc -mtriple=i386-linux-android16 < %s -o - | FileCheck --check-prefix=I386 %s
-; RUN: llc -mtriple=i386-linux-android17 < %s -o - | FileCheck --check-prefix=I386-TLS %s
-; RUN: llc -mtriple=i386-linux-android24 < %s -o - | FileCheck --check-prefix=I386-TLS %s
+; RUN: llc -mtriple=i386-linux-android < %s -o - | FileCheck --check-prefix=I386-TLS %s
; RUN: llc -mtriple=x86_64-linux-android < %s -o - | FileCheck --check-prefix=X64-TLS %s
-; RUN: llc -mtriple=x86_64-linux-android17 < %s -o - | FileCheck --check-prefix=X64-TLS %s
-; RUN: llc -mtriple=x86_64-linux-android24 < %s -o - | FileCheck --check-prefix=X64-TLS %s
; RUN: llc -mtriple=i386-kfreebsd < %s -o - | FileCheck --check-prefix=I386-TLS %s
; RUN: llc -mtriple=x86_64-kfreebsd < %s -o - | FileCheck --check-prefix=X64-TLS %s
@@ -27,11 +22,6 @@ declare void @_Z7CapturePi(ptr)
; X64-TLS: movq %fs:40, %[[C:.*]]
; X64-TLS: cmpq 16(%rsp), %[[C]]
-; I386: movl __stack_chk_guard, %[[B:.*]]
-; I386: movl %[[B]], 8(%esp)
-; I386: movl __stack_chk_guard, %[[C:.*]]
-; I386: cmpl 8(%esp), %[[C]]
-
; I386-TLS: movl %gs:20, %[[B:.*]]
; I386-TLS: movl %[[B]], 8(%esp)
; I386-TLS: movl %gs:20, %[[C:.*]]
generated by cgit v1.1 at 2025-10-11 04:34:06 +0000