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Diffstat (limited to 'llvm/test/CodeGen/RISCV/select.ll')
-rw-r--r--llvm/test/CodeGen/RISCV/select.ll322
1 files changed, 195 insertions, 127 deletions
diff --git a/llvm/test/CodeGen/RISCV/select.ll b/llvm/test/CodeGen/RISCV/select.ll
index 8273c65..1eb47e4c 100644
--- a/llvm/test/CodeGen/RISCV/select.ll
+++ b/llvm/test/CodeGen/RISCV/select.ll
@@ -4,7 +4,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+m,+xventanacondops -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64IMXVTCONDOPS %s
; RUN: llc -mtriple=riscv32 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV32IMZICOND %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV64IMZICOND %s
-; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-opt,+conditional-cmv-fusion -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IXQCI
define i16 @select_xor_1(i16 %A, i8 %cond) {
@@ -44,10 +44,11 @@ define i16 @select_xor_1(i16 %A, i8 %cond) {
;
; RV32IXQCI-LABEL: select_xor_1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: slli a1, a1, 31
-; RV32IXQCI-NEXT: srai a1, a1, 31
-; RV32IXQCI-NEXT: andi a1, a1, 43
-; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: andi a1, a1, 1
+; RV32IXQCI-NEXT: beqz a1, .LBB0_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
+; RV32IXQCI-NEXT: xori a0, a0, 43
+; RV32IXQCI-NEXT: .LBB0_2: # %entry
; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
@@ -102,10 +103,11 @@ define i16 @select_xor_1b(i16 %A, i8 %cond) {
;
; RV32IXQCI-LABEL: select_xor_1b:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: slli a1, a1, 31
-; RV32IXQCI-NEXT: srai a1, a1, 31
-; RV32IXQCI-NEXT: andi a1, a1, 43
-; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: andi a1, a1, 1
+; RV32IXQCI-NEXT: beqz a1, .LBB1_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
+; RV32IXQCI-NEXT: xori a0, a0, 43
+; RV32IXQCI-NEXT: .LBB1_2: # %entry
; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
@@ -148,10 +150,11 @@ define i32 @select_xor_2(i32 %A, i32 %B, i8 %cond) {
;
; RV32IXQCI-LABEL: select_xor_2:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: slli a2, a2, 31
-; RV32IXQCI-NEXT: srai a2, a2, 31
-; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: andi a2, a2, 1
+; RV32IXQCI-NEXT: beqz a2, .LBB2_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: .LBB2_2: # %entry
; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
@@ -196,10 +199,11 @@ define i32 @select_xor_2b(i32 %A, i32 %B, i8 %cond) {
;
; RV32IXQCI-LABEL: select_xor_2b:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: slli a2, a2, 31
-; RV32IXQCI-NEXT: srai a2, a2, 31
-; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: andi a2, a2, 1
+; RV32IXQCI-NEXT: beqz a2, .LBB3_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: .LBB3_2: # %entry
; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
@@ -221,9 +225,10 @@ define i16 @select_xor_3(i16 %A, i8 %cond) {
; RV32IXQCI-LABEL: select_xor_3:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: andi a1, a1, 1
-; RV32IXQCI-NEXT: addi a1, a1, -1
-; RV32IXQCI-NEXT: andi a1, a1, 43
-; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: bnez a1, .LBB4_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
+; RV32IXQCI-NEXT: xori a0, a0, 43
+; RV32IXQCI-NEXT: .LBB4_2: # %entry
; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
@@ -247,9 +252,10 @@ define i16 @select_xor_3b(i16 %A, i8 %cond) {
; RV32IXQCI-LABEL: select_xor_3b:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: andi a1, a1, 1
-; RV32IXQCI-NEXT: addi a1, a1, -1
-; RV32IXQCI-NEXT: andi a1, a1, 43
-; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: bnez a1, .LBB5_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
+; RV32IXQCI-NEXT: xori a0, a0, 43
+; RV32IXQCI-NEXT: .LBB5_2: # %entry
; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
@@ -293,9 +299,10 @@ define i32 @select_xor_4(i32 %A, i32 %B, i8 %cond) {
; RV32IXQCI-LABEL: select_xor_4:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: andi a2, a2, 1
-; RV32IXQCI-NEXT: addi a2, a2, -1
-; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: bnez a2, .LBB6_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: .LBB6_2: # %entry
; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
@@ -341,9 +348,10 @@ define i32 @select_xor_4b(i32 %A, i32 %B, i8 %cond) {
; RV32IXQCI-LABEL: select_xor_4b:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: andi a2, a2, 1
-; RV32IXQCI-NEXT: addi a2, a2, -1
-; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: bnez a2, .LBB7_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
; RV32IXQCI-NEXT: xor a0, a0, a1
+; RV32IXQCI-NEXT: .LBB7_2: # %entry
; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
@@ -382,9 +390,12 @@ define i32 @select_xor_5(i1 zeroext %cond, i32 %x) {
;
; RV32IXQCI-LABEL: select_xor_5:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: addi a0, a0, -1
-; RV32IXQCI-NEXT: and a0, a0, a1
-; RV32IXQCI-NEXT: xori a0, a0, 128
+; RV32IXQCI-NEXT: li a2, 128
+; RV32IXQCI-NEXT: bnez a0, .LBB8_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: xori a2, a1, 128
+; RV32IXQCI-NEXT: .LBB8_2:
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
%add = xor i32 %x, 128
%sel = select i1 %cond, i32 128, i32 %add
@@ -424,10 +435,11 @@ define i32 @select_or(i32 %A, i32 %B, i8 %cond) {
;
; RV32IXQCI-LABEL: select_or:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: slli a2, a2, 31
-; RV32IXQCI-NEXT: srai a2, a2, 31
-; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: andi a2, a2, 1
+; RV32IXQCI-NEXT: beqz a2, .LBB9_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: .LBB9_2: # %entry
; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
@@ -472,10 +484,11 @@ define i32 @select_or_b(i32 %A, i32 %B, i8 %cond) {
;
; RV32IXQCI-LABEL: select_or_b:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: slli a2, a2, 31
-; RV32IXQCI-NEXT: srai a2, a2, 31
-; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: andi a2, a2, 1
+; RV32IXQCI-NEXT: beqz a2, .LBB10_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: .LBB10_2: # %entry
; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
@@ -518,10 +531,11 @@ define i32 @select_or_1(i32 %A, i32 %B, i32 %cond) {
;
; RV32IXQCI-LABEL: select_or_1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: slli a2, a2, 31
-; RV32IXQCI-NEXT: srai a2, a2, 31
-; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: andi a2, a2, 1
+; RV32IXQCI-NEXT: beqz a2, .LBB11_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: .LBB11_2: # %entry
; RV32IXQCI-NEXT: ret
entry:
%and = and i32 %cond, 1
@@ -566,10 +580,11 @@ define i32 @select_or_1b(i32 %A, i32 %B, i32 %cond) {
;
; RV32IXQCI-LABEL: select_or_1b:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: slli a2, a2, 31
-; RV32IXQCI-NEXT: srai a2, a2, 31
-; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: andi a2, a2, 1
+; RV32IXQCI-NEXT: beqz a2, .LBB12_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: .LBB12_2: # %entry
; RV32IXQCI-NEXT: ret
entry:
%and = and i32 %cond, 1
@@ -613,9 +628,10 @@ define i32 @select_or_2(i32 %A, i32 %B, i8 %cond) {
; RV32IXQCI-LABEL: select_or_2:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: andi a2, a2, 1
-; RV32IXQCI-NEXT: addi a2, a2, -1
-; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: bnez a2, .LBB13_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: .LBB13_2: # %entry
; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
@@ -661,9 +677,10 @@ define i32 @select_or_2b(i32 %A, i32 %B, i8 %cond) {
; RV32IXQCI-LABEL: select_or_2b:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: andi a2, a2, 1
-; RV32IXQCI-NEXT: addi a2, a2, -1
-; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: bnez a2, .LBB14_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: .LBB14_2: # %entry
; RV32IXQCI-NEXT: ret
entry:
%and = and i8 %cond, 1
@@ -707,9 +724,10 @@ define i32 @select_or_3(i32 %A, i32 %B, i32 %cond) {
; RV32IXQCI-LABEL: select_or_3:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: andi a2, a2, 1
-; RV32IXQCI-NEXT: addi a2, a2, -1
-; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: bnez a2, .LBB15_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: .LBB15_2: # %entry
; RV32IXQCI-NEXT: ret
entry:
%and = and i32 %cond, 1
@@ -755,9 +773,10 @@ define i32 @select_or_3b(i32 %A, i32 %B, i32 %cond) {
; RV32IXQCI-LABEL: select_or_3b:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: andi a2, a2, 1
-; RV32IXQCI-NEXT: addi a2, a2, -1
-; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: bnez a2, .LBB16_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
; RV32IXQCI-NEXT: or a0, a0, a1
+; RV32IXQCI-NEXT: .LBB16_2: # %entry
; RV32IXQCI-NEXT: ret
entry:
%and = and i32 %cond, 1
@@ -796,9 +815,12 @@ define i32 @select_or_4(i1 zeroext %cond, i32 %x) {
;
; RV32IXQCI-LABEL: select_or_4:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: addi a0, a0, -1
-; RV32IXQCI-NEXT: and a0, a0, a1
-; RV32IXQCI-NEXT: ori a0, a0, 128
+; RV32IXQCI-NEXT: li a2, 128
+; RV32IXQCI-NEXT: bnez a0, .LBB17_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: ori a2, a1, 128
+; RV32IXQCI-NEXT: .LBB17_2:
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
%add = or i32 %x, 128
%sel = select i1 %cond, i32 128, i32 %add
@@ -840,9 +862,11 @@ define i32 @select_add_1(i1 zeroext %cond, i32 %a, i32 %b) {
;
; RV32IXQCI-LABEL: select_add_1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: neg a0, a0
-; RV32IXQCI-NEXT: and a0, a0, a1
-; RV32IXQCI-NEXT: add a0, a0, a2
+; RV32IXQCI-NEXT: beqz a0, .LBB18_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
+; RV32IXQCI-NEXT: add a2, a2, a1
+; RV32IXQCI-NEXT: .LBB18_2: # %entry
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%c = add i32 %a, %b
@@ -885,9 +909,11 @@ define i32 @select_add_2(i1 zeroext %cond, i32 %a, i32 %b) {
;
; RV32IXQCI-LABEL: select_add_2:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: addi a0, a0, -1
-; RV32IXQCI-NEXT: and a0, a0, a2
-; RV32IXQCI-NEXT: add a0, a0, a1
+; RV32IXQCI-NEXT: bnez a0, .LBB19_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
+; RV32IXQCI-NEXT: add a1, a1, a2
+; RV32IXQCI-NEXT: .LBB19_2: # %entry
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
entry:
%c = add i32 %a, %b
@@ -933,9 +959,11 @@ define i32 @select_add_3(i1 zeroext %cond, i32 %a) {
;
; RV32IXQCI-LABEL: select_add_3:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: addi a0, a0, -1
-; RV32IXQCI-NEXT: andi a0, a0, 42
-; RV32IXQCI-NEXT: add a0, a0, a1
+; RV32IXQCI-NEXT: bnez a0, .LBB20_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
+; RV32IXQCI-NEXT: addi a1, a1, 42
+; RV32IXQCI-NEXT: .LBB20_2: # %entry
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
entry:
%c = add i32 %a, 42
@@ -978,9 +1006,12 @@ define i32 @select_add_4(i1 zeroext %cond, i32 %x) {
;
; RV32IXQCI-LABEL: select_add_4:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: addi a0, a0, -1
-; RV32IXQCI-NEXT: and a0, a0, a1
-; RV32IXQCI-NEXT: addi a0, a0, 128
+; RV32IXQCI-NEXT: li a2, 128
+; RV32IXQCI-NEXT: bnez a0, .LBB21_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: addi a2, a1, 128
+; RV32IXQCI-NEXT: .LBB21_2:
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
%add = add i32 %x, 128
%sel = select i1 %cond, i32 128, i32 %add
@@ -1029,12 +1060,14 @@ define i64 @select_add_5(i1 zeroext %cond, i64 %x) {
;
; RV32IXQCI-LABEL: select_add_5:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: addi a3, a0, -1
-; RV32IXQCI-NEXT: and a1, a1, a3
-; RV32IXQCI-NEXT: addi a0, a1, 128
-; RV32IXQCI-NEXT: sltu a1, a0, a1
-; RV32IXQCI-NEXT: and a2, a2, a3
-; RV32IXQCI-NEXT: add a1, a1, a2
+; RV32IXQCI-NEXT: mv a3, a0
+; RV32IXQCI-NEXT: addi a4, a1, 128
+; RV32IXQCI-NEXT: sltu a0, a4, a1
+; RV32IXQCI-NEXT: add a2, a2, a0
+; RV32IXQCI-NEXT: li a0, 128
+; RV32IXQCI-NEXT: qc.mveqi a0, a3, 0, a4
+; RV32IXQCI-NEXT: qc.selectieqi a3, 0, a2, 0
+; RV32IXQCI-NEXT: mv a1, a3
; RV32IXQCI-NEXT: ret
%add = add i64 %x, 128
%sel = select i1 %cond, i64 128, i64 %add
@@ -1093,14 +1126,15 @@ define i64 @select_add_6(i1 zeroext %cond, i64 %x) {
;
; RV32IXQCI-LABEL: select_add_6:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: addi a3, a0, -1
+; RV32IXQCI-NEXT: mv a3, a0
; RV32IXQCI-NEXT: lui a0, 14
-; RV32IXQCI-NEXT: and a1, a1, a3
-; RV32IXQCI-NEXT: addi a0, a0, 1005
-; RV32IXQCI-NEXT: add a0, a0, a1
+; RV32IXQCI-NEXT: addi a4, a0, 1005
+; RV32IXQCI-NEXT: add a0, a1, a4
; RV32IXQCI-NEXT: sltu a1, a0, a1
-; RV32IXQCI-NEXT: and a2, a2, a3
; RV32IXQCI-NEXT: add a1, a1, a2
+; RV32IXQCI-NEXT: qc.mvnei a0, a3, 0, a4
+; RV32IXQCI-NEXT: qc.selectieqi a3, 0, a1, 0
+; RV32IXQCI-NEXT: mv a1, a3
; RV32IXQCI-NEXT: ret
%add = add i64 %x, 58349
%sel = select i1 %cond, i64 58349, i64 %add
@@ -1152,9 +1186,11 @@ define i32 @select_sub_1(i1 zeroext %cond, i32 %a, i32 %b) {
;
; RV32IXQCI-LABEL: select_sub_1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: sub a1, a1, a2
-; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
-; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: beqz a0, .LBB24_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
+; RV32IXQCI-NEXT: sub a2, a1, a2
+; RV32IXQCI-NEXT: .LBB24_2: # %entry
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%c = sub i32 %a, %b
@@ -1197,9 +1233,11 @@ define i32 @select_sub_2(i1 zeroext %cond, i32 %a, i32 %b) {
;
; RV32IXQCI-LABEL: select_sub_2:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: addi a0, a0, -1
-; RV32IXQCI-NEXT: and a0, a0, a2
-; RV32IXQCI-NEXT: sub a0, a1, a0
+; RV32IXQCI-NEXT: bnez a0, .LBB25_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
+; RV32IXQCI-NEXT: sub a1, a1, a2
+; RV32IXQCI-NEXT: .LBB25_2: # %entry
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
entry:
%c = sub i32 %a, %b
@@ -1245,9 +1283,11 @@ define i32 @select_sub_3(i1 zeroext %cond, i32 %a) {
;
; RV32IXQCI-LABEL: select_sub_3:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: addi a0, a0, -1
-; RV32IXQCI-NEXT: andi a0, a0, 42
-; RV32IXQCI-NEXT: sub a0, a1, a0
+; RV32IXQCI-NEXT: bnez a0, .LBB26_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
+; RV32IXQCI-NEXT: addi a1, a1, -42
+; RV32IXQCI-NEXT: .LBB26_2: # %entry
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
entry:
%c = sub i32 %a, 42
@@ -1301,10 +1341,12 @@ define i32 @select_sub_4(i1 zeroext %cond, i32 %x) {
;
; RV32IXQCI-LABEL: select_sub_4:
; RV32IXQCI: # %bb.0:
+; RV32IXQCI-NEXT: li a2, 128
+; RV32IXQCI-NEXT: bnez a0, .LBB27_2
+; RV32IXQCI-NEXT: # %bb.1:
; RV32IXQCI-NEXT: addi a2, a1, -128
-; RV32IXQCI-NEXT: li a1, 128
-; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
-; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: .LBB27_2:
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
%add = sub i32 %x, 128
%sel = select i1 %cond, i32 128, i32 %add
@@ -1347,9 +1389,11 @@ define i32 @select_and_1(i1 zeroext %cond, i32 %a, i32 %b) {
;
; RV32IXQCI-LABEL: select_and_1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: and a1, a1, a2
-; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
-; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: beqz a0, .LBB28_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
+; RV32IXQCI-NEXT: and a2, a2, a1
+; RV32IXQCI-NEXT: .LBB28_2: # %entry
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%c = and i32 %a, %b
@@ -1392,9 +1436,11 @@ define i32 @select_and_2(i1 zeroext %cond, i32 %a, i32 %b) {
;
; RV32IXQCI-LABEL: select_and_2:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: and a2, a2, a1
-; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: bnez a0, .LBB29_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
+; RV32IXQCI-NEXT: and a1, a1, a2
+; RV32IXQCI-NEXT: .LBB29_2: # %entry
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
entry:
%c = and i32 %a, %b
@@ -1437,9 +1483,11 @@ define i32 @select_and_3(i1 zeroext %cond, i32 %a) {
;
; RV32IXQCI-LABEL: select_and_3:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: andi a2, a1, 42
-; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: bnez a0, .LBB30_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
+; RV32IXQCI-NEXT: andi a1, a1, 42
+; RV32IXQCI-NEXT: .LBB30_2: # %entry
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
entry:
%c = and i32 %a, 42
@@ -1626,9 +1674,11 @@ define i32 @select_udiv_3(i1 zeroext %cond, i32 %a) {
; RV32IXQCI-NEXT: lui a3, 199729
; RV32IXQCI-NEXT: addi a3, a3, -975
; RV32IXQCI-NEXT: mulhu a2, a2, a3
-; RV32IXQCI-NEXT: srli a2, a2, 2
-; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: bnez a0, .LBB33_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
+; RV32IXQCI-NEXT: srli a1, a2, 2
+; RV32IXQCI-NEXT: .LBB33_2: # %entry
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
entry:
%c = udiv i32 %a, 42
@@ -1681,9 +1731,11 @@ define i32 @select_shl_1(i1 zeroext %cond, i32 %a, i32 %b) {
;
; RV32IXQCI-LABEL: select_shl_1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: sll a1, a1, a2
-; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
-; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: beqz a0, .LBB34_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
+; RV32IXQCI-NEXT: sll a2, a1, a2
+; RV32IXQCI-NEXT: .LBB34_2: # %entry
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%c = shl i32 %a, %b
@@ -1726,9 +1778,11 @@ define i32 @select_shl_2(i1 zeroext %cond, i32 %a, i32 %b) {
;
; RV32IXQCI-LABEL: select_shl_2:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: addi a0, a0, -1
-; RV32IXQCI-NEXT: and a0, a0, a2
-; RV32IXQCI-NEXT: sll a0, a1, a0
+; RV32IXQCI-NEXT: bnez a0, .LBB35_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
+; RV32IXQCI-NEXT: sll a1, a1, a2
+; RV32IXQCI-NEXT: .LBB35_2: # %entry
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
entry:
%c = shl i32 %a, %b
@@ -1797,9 +1851,11 @@ define i32 @select_ashr_1(i1 zeroext %cond, i32 %a, i32 %b) {
;
; RV32IXQCI-LABEL: select_ashr_1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: sra a1, a1, a2
-; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
-; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: beqz a0, .LBB37_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
+; RV32IXQCI-NEXT: sra a2, a1, a2
+; RV32IXQCI-NEXT: .LBB37_2: # %entry
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%c = ashr i32 %a, %b
@@ -1842,9 +1898,11 @@ define i32 @select_ashr_2(i1 zeroext %cond, i32 %a, i32 %b) {
;
; RV32IXQCI-LABEL: select_ashr_2:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: addi a0, a0, -1
-; RV32IXQCI-NEXT: and a0, a0, a2
-; RV32IXQCI-NEXT: sra a0, a1, a0
+; RV32IXQCI-NEXT: bnez a0, .LBB38_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
+; RV32IXQCI-NEXT: sra a1, a1, a2
+; RV32IXQCI-NEXT: .LBB38_2: # %entry
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
entry:
%c = ashr i32 %a, %b
@@ -1913,9 +1971,11 @@ define i32 @select_lshr_1(i1 zeroext %cond, i32 %a, i32 %b) {
;
; RV32IXQCI-LABEL: select_lshr_1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: srl a1, a1, a2
-; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
-; RV32IXQCI-NEXT: mv a0, a1
+; RV32IXQCI-NEXT: beqz a0, .LBB40_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
+; RV32IXQCI-NEXT: srl a2, a1, a2
+; RV32IXQCI-NEXT: .LBB40_2: # %entry
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%c = lshr i32 %a, %b
@@ -1958,9 +2018,11 @@ define i32 @select_lshr_2(i1 zeroext %cond, i32 %a, i32 %b) {
;
; RV32IXQCI-LABEL: select_lshr_2:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: addi a0, a0, -1
-; RV32IXQCI-NEXT: and a0, a0, a2
-; RV32IXQCI-NEXT: srl a0, a1, a0
+; RV32IXQCI-NEXT: bnez a0, .LBB41_2
+; RV32IXQCI-NEXT: # %bb.1: # %entry
+; RV32IXQCI-NEXT: srl a1, a1, a2
+; RV32IXQCI-NEXT: .LBB41_2: # %entry
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
entry:
%c = lshr i32 %a, %b
@@ -2304,11 +2366,13 @@ define i32 @select_cst3(i1 zeroext %cond) {
;
; RV32IXQCI-LABEL: select_cst3:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: lui a1, 7
-; RV32IXQCI-NEXT: lui a2, 5
-; RV32IXQCI-NEXT: addi a3, a1, 1328
-; RV32IXQCI-NEXT: addi a1, a2, -480
-; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a3
+; RV32IXQCI-NEXT: lui a2, 7
+; RV32IXQCI-NEXT: lui a1, 5
+; RV32IXQCI-NEXT: addi a1, a1, -480
+; RV32IXQCI-NEXT: beqz a0, .LBB51_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: addi a1, a2, 1328
+; RV32IXQCI-NEXT: .LBB51_2:
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 30000, i32 20000
@@ -2370,10 +2434,12 @@ define i32 @select_cst5(i1 zeroext %cond) {
;
; RV32IXQCI-LABEL: select_cst5:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: lui a1, 1
-; RV32IXQCI-NEXT: addi a2, a1, -2047
+; RV32IXQCI-NEXT: lui a2, 1
; RV32IXQCI-NEXT: li a1, 2047
-; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32IXQCI-NEXT: bnez a0, .LBB53_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: addi a1, a2, -2047
+; RV32IXQCI-NEXT: .LBB53_2:
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 2047, i32 2049
@@ -2417,10 +2483,12 @@ define i32 @select_cst5_invert(i1 zeroext %cond) {
;
; RV32IXQCI-LABEL: select_cst5_invert:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: lui a1, 1
-; RV32IXQCI-NEXT: addi a2, a1, -2047
+; RV32IXQCI-NEXT: lui a2, 1
; RV32IXQCI-NEXT: li a1, 2047
-; RV32IXQCI-NEXT: qc.mvnei a1, a0, 0, a2
+; RV32IXQCI-NEXT: beqz a0, .LBB54_2
+; RV32IXQCI-NEXT: # %bb.1:
+; RV32IXQCI-NEXT: addi a1, a2, -2047
+; RV32IXQCI-NEXT: .LBB54_2:
; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
%ret = select i1 %cond, i32 2049, i32 2047
generated by cgit v1.1 at 2025-10-03 20:28:16 +0000