diff options
Diffstat (limited to 'llvm/test/CodeGen/RISCV/select-cc.ll')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/select-cc.ll | 59 |
1 files changed, 29 insertions, 30 deletions
diff --git a/llvm/test/CodeGen/RISCV/select-cc.ll b/llvm/test/CodeGen/RISCV/select-cc.ll index b57f625..95f5a9d 100644 --- a/llvm/test/CodeGen/RISCV/select-cc.ll +++ b/llvm/test/CodeGen/RISCV/select-cc.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -disable-block-placement -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-opt,+conditional-cmv-fusion -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCI ; RUN: llc -mtriple=riscv64 -disable-block-placement -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64I %s @@ -88,39 +88,38 @@ define signext i32 @foo(i32 signext %a, ptr %b) nounwind { ; RV32IXQCI-LABEL: foo: ; RV32IXQCI: # %bb.0: ; RV32IXQCI-NEXT: lw a2, 0(a1) -; RV32IXQCI-NEXT: lw a4, 0(a1) -; RV32IXQCI-NEXT: lw t5, 0(a1) -; RV32IXQCI-NEXT: lw t4, 0(a1) -; RV32IXQCI-NEXT: lw t3, 0(a1) -; RV32IXQCI-NEXT: lw t2, 0(a1) -; RV32IXQCI-NEXT: lw t0, 0(a1) -; RV32IXQCI-NEXT: lw a7, 0(a1) -; RV32IXQCI-NEXT: lw a6, 0(a1) ; RV32IXQCI-NEXT: lw a3, 0(a1) -; RV32IXQCI-NEXT: lw t1, 0(a1) +; RV32IXQCI-NEXT: lw a4, 0(a1) ; RV32IXQCI-NEXT: lw a5, 0(a1) -; RV32IXQCI-NEXT: bltz t1, .LBB0_2 +; RV32IXQCI-NEXT: qc.mvne a0, a0, a2, a2 +; RV32IXQCI-NEXT: qc.mveq a0, a0, a3, a3 +; RV32IXQCI-NEXT: lw a2, 0(a1) +; RV32IXQCI-NEXT: qc.mvgeu a0, a4, a0, a4 +; RV32IXQCI-NEXT: lw a3, 0(a1) +; RV32IXQCI-NEXT: qc.mvltu a0, a0, a5, a5 +; RV32IXQCI-NEXT: lw a4, 0(a1) +; RV32IXQCI-NEXT: qc.mvgeu a0, a0, a2, a2 +; RV32IXQCI-NEXT: lw a2, 0(a1) +; RV32IXQCI-NEXT: qc.mvltu a0, a3, a0, a3 +; RV32IXQCI-NEXT: lw a3, 0(a1) +; RV32IXQCI-NEXT: qc.mvge a0, a4, a0, a4 +; RV32IXQCI-NEXT: lw a4, 0(a1) +; RV32IXQCI-NEXT: qc.mvlt a0, a0, a2, a2 +; RV32IXQCI-NEXT: lw a2, 0(a1) +; RV32IXQCI-NEXT: qc.mvge a0, a0, a3, a3 +; RV32IXQCI-NEXT: lw a3, 0(a1) +; RV32IXQCI-NEXT: qc.mvlt a0, a4, a0, a4 +; RV32IXQCI-NEXT: lw a4, 0(a1) +; RV32IXQCI-NEXT: lw a1, 0(a1) +; RV32IXQCI-NEXT: blez a2, .LBB0_2 ; RV32IXQCI-NEXT: # %bb.1: -; RV32IXQCI-NEXT: li a5, 0 -; RV32IXQCI-NEXT: qc.mveq a2, a0, a2, a0 -; RV32IXQCI-NEXT: qc.mvne a4, a2, a4, a2 -; RV32IXQCI-NEXT: qc.mvltu t5, t5, a4, a4 -; RV32IXQCI-NEXT: qc.mvgeu t4, t5, t4, t5 -; RV32IXQCI-NEXT: qc.mvltu t3, t4, t3, t4 -; RV32IXQCI-NEXT: qc.mvgeu t2, t2, t3, t3 -; RV32IXQCI-NEXT: qc.mvlt t0, t0, t2, t2 -; RV32IXQCI-NEXT: qc.mvge a7, t0, a7, t0 -; RV32IXQCI-NEXT: qc.mvlt a6, a7, a6, a7 -; RV32IXQCI-NEXT: qc.mvge a3, a3, a6, a6 -; RV32IXQCI-NEXT: qc.mvlt a3, a5, t1, t1 -; RV32IXQCI-NEXT: mv a5, a3 +; RV32IXQCI-NEXT: mv a0, a2 ; RV32IXQCI-NEXT: .LBB0_2: -; RV32IXQCI-NEXT: lw a2, 0(a1) -; RV32IXQCI-NEXT: lw a0, 0(a1) -; RV32IXQCI-NEXT: li a1, 1024 -; RV32IXQCI-NEXT: qc.mvlt a2, a1, a2, a5 -; RV32IXQCI-NEXT: li a1, 2046 -; RV32IXQCI-NEXT: qc.mvltu a0, a1, t1, a2 +; RV32IXQCI-NEXT: qc.mvlti a0, a2, 0, a3 +; RV32IXQCI-NEXT: li a3, 1024 +; RV32IXQCI-NEXT: qc.mvge a0, a3, a4, a4 +; RV32IXQCI-NEXT: li a3, 2046 +; RV32IXQCI-NEXT: qc.mvgeu a0, a3, a2, a1 ; RV32IXQCI-NEXT: ret ; ; RV64I-LABEL: foo: |