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-rw-r--r--llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir67
1 files changed, 50 insertions, 17 deletions
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
index fdd30c9..6e6b708 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
@@ -27,8 +27,6 @@
ret <vscale x 1 x i64> %b
}
- declare i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64>) #1
-
define i64 @vmv_x_s(<vscale x 1 x i64> %0) #0 {
entry:
%a = call i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64> %0)
@@ -43,16 +41,12 @@
ret void
}
- declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>) #2
-
define i64 @vreduce_add_v2i64(ptr %x) #0 {
%v = load <2 x i64>, ptr %x, align 16
%red = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %v)
ret i64 %red
}
- declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #3
-
define <vscale x 1 x i64> @vsetvli_add(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %avl) #0 {
entry:
%a = call i64 @llvm.riscv.vsetvli.i64(i64 %avl, i64 3, i64 0)
@@ -100,23 +94,19 @@
ret void
}
- define void @vsetvli_vleff() {
+ define void @coalesce_vl_clobber() {
ret void
}
- declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
-
- declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>, ptr nocapture, i64) #4
-
- declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32>, ptr nocapture, i64) #4
+ define void @vsetvli_vleff() {
+ ret void
+ }
- declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
+ define void @non_li_addi() {
+ ret void
+ }
attributes #0 = { "target-features"="+v" }
- attributes #1 = { nounwind readnone }
- attributes #2 = { nofree nosync nounwind readnone willreturn }
- attributes #3 = { nounwind }
- attributes #4 = { nounwind readonly }
...
---
@@ -620,10 +610,33 @@ body: |
; CHECK: liveins: $x8, $v8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:gprnox0 = COPY $x8
+ ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: dead %v:vr = COPY $v8, implicit $vtype
; CHECK-NEXT: dead %x:gprnox0 = PseudoVSETVLI %x, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
+ %x:gprnox0 = COPY $x8
+ dead $x0 = PseudoVSETIVLI 1, 208, implicit-def $vl, implicit-def $vtype
+ %v:vr = COPY $v8, implicit $vtype
+ %x = PseudoVSETVLI %x, 208, implicit-def $vl, implicit-def $vtype
+...
+---
+# Because of the %y:gprnox0 = COPY %x, we can't extend the live range of %x from
+# the second vsetvli to the first vsetvli when coalescing.
+name: coalesce_vl_clobber
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x8, $v8
+ ; CHECK-LABEL: name: coalesce_vl_clobber
+ ; CHECK: liveins: $x8, $v8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %x:gprnox0 = COPY $x8
+ ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: dead %y:gprnox0 = COPY %x
; CHECK-NEXT: dead %v:vr = COPY $v8, implicit $vtype
+ ; CHECK-NEXT: dead %x:gprnox0 = PseudoVSETVLI %x, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
%x:gprnox0 = COPY $x8
dead $x0 = PseudoVSETIVLI 1, 208, implicit-def $vl, implicit-def $vtype
+ %y:gprnox0 = COPY %x
%v:vr = COPY $v8, implicit $vtype
%x = PseudoVSETVLI %x, 208, implicit-def $vl, implicit-def $vtype
...
@@ -664,3 +677,23 @@ body: |
bb.2:
$x10 = COPY %vl
PseudoRET implicit killed $x10
+...
+---
+# The two vsetvlis will be coalesced so the ADDI will be made dead and removed.
+# Make sure we shrink the live interval of %0.
+name: non_li_addi
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x10
+ ; CHECK-LABEL: name: non_li_addi
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: dead [[PseudoVSETIVLI:%[0-9]+]]:gprnox0 = PseudoVSETIVLI 1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: PseudoRET
+ %0:gpr = COPY $x10
+ %1:gprnox0 = ADDI %0, 1
+ %2:gprnox0 = PseudoVSETVLI %1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
+ %3:gprnox0 = PseudoVSETIVLI 1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
+ PseudoRET