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-rw-r--r--llvm/test/CodeGen/RISCV/atomic-load-store.ll406
1 files changed, 406 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/atomic-load-store.ll b/llvm/test/CodeGen/RISCV/atomic-load-store.ll
index 7e3abc7..c6234de 100644
--- a/llvm/test/CodeGen/RISCV/atomic-load-store.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-load-store.ll
@@ -1,12 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv32 -mattr=+zalrsc -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I-ZALRSC %s
; RUN: llc -mtriple=riscv32 -mattr=+a,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-WMO %s
; RUN: llc -mtriple=riscv32 -mattr=+a,+ztso,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-TSO %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
+; RUN: llc -mtriple=riscv64 -mattr=+zalrsc -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I-ZALRSC %s
; RUN: llc -mtriple=riscv64 -mattr=+a,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO %s
; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \
@@ -44,6 +48,11 @@ define i8 @atomic_load_i8_unordered(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i8_unordered:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lb a0, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_load_i8_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lb a0, 0(a0)
@@ -59,6 +68,11 @@ define i8 @atomic_load_i8_unordered(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i8_unordered:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lb a0, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_load_i8_unordered:
; RV64IA: # %bb.0:
; RV64IA-NEXT: lb a0, 0(a0)
@@ -78,6 +92,11 @@ define i8 @atomic_load_i8_monotonic(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lb a0, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_load_i8_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lb a0, 0(a0)
@@ -93,6 +112,11 @@ define i8 @atomic_load_i8_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lb a0, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_load_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: lb a0, 0(a0)
@@ -112,6 +136,12 @@ define i8 @atomic_load_i8_acquire(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i8_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lb a0, 0(a0)
+; RV32I-ZALRSC-NEXT: fence r, rw
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_load_i8_acquire:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: lb a0, 0(a0)
@@ -133,6 +163,12 @@ define i8 @atomic_load_i8_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i8_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lb a0, 0(a0)
+; RV64I-ZALRSC-NEXT: fence r, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_load_i8_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: lb a0, 0(a0)
@@ -200,6 +236,13 @@ define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i8_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: fence rw, rw
+; RV32I-ZALRSC-NEXT: lb a0, 0(a0)
+; RV32I-ZALRSC-NEXT: fence r, rw
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_load_i8_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: fence rw, rw
@@ -223,6 +266,13 @@ define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i8_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, rw
+; RV64I-ZALRSC-NEXT: lb a0, 0(a0)
+; RV64I-ZALRSC-NEXT: fence r, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_load_i8_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, rw
@@ -286,6 +336,11 @@ define i16 @atomic_load_i16_unordered(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i16_unordered:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lh a0, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_load_i16_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lh a0, 0(a0)
@@ -301,6 +356,11 @@ define i16 @atomic_load_i16_unordered(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i16_unordered:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lh a0, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_load_i16_unordered:
; RV64IA: # %bb.0:
; RV64IA-NEXT: lh a0, 0(a0)
@@ -320,6 +380,11 @@ define i16 @atomic_load_i16_monotonic(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lh a0, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_load_i16_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lh a0, 0(a0)
@@ -335,6 +400,11 @@ define i16 @atomic_load_i16_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lh a0, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_load_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: lh a0, 0(a0)
@@ -354,6 +424,12 @@ define i16 @atomic_load_i16_acquire(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i16_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lh a0, 0(a0)
+; RV32I-ZALRSC-NEXT: fence r, rw
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_load_i16_acquire:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: lh a0, 0(a0)
@@ -375,6 +451,12 @@ define i16 @atomic_load_i16_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i16_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lh a0, 0(a0)
+; RV64I-ZALRSC-NEXT: fence r, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_load_i16_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: lh a0, 0(a0)
@@ -442,6 +524,13 @@ define i16 @atomic_load_i16_seq_cst(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i16_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: fence rw, rw
+; RV32I-ZALRSC-NEXT: lh a0, 0(a0)
+; RV32I-ZALRSC-NEXT: fence r, rw
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_load_i16_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: fence rw, rw
@@ -465,6 +554,13 @@ define i16 @atomic_load_i16_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i16_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, rw
+; RV64I-ZALRSC-NEXT: lh a0, 0(a0)
+; RV64I-ZALRSC-NEXT: fence r, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_load_i16_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, rw
@@ -528,6 +624,11 @@ define i32 @atomic_load_i32_unordered(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i32_unordered:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lw a0, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_load_i32_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lw a0, 0(a0)
@@ -543,6 +644,11 @@ define i32 @atomic_load_i32_unordered(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i32_unordered:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lw a0, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_load_i32_unordered:
; RV64IA: # %bb.0:
; RV64IA-NEXT: lw a0, 0(a0)
@@ -562,6 +668,11 @@ define i32 @atomic_load_i32_monotonic(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lw a0, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_load_i32_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: lw a0, 0(a0)
@@ -577,6 +688,11 @@ define i32 @atomic_load_i32_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lw a0, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_load_i32_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: lw a0, 0(a0)
@@ -596,6 +712,12 @@ define i32 @atomic_load_i32_acquire(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i32_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: lw a0, 0(a0)
+; RV32I-ZALRSC-NEXT: fence r, rw
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_load_i32_acquire:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: lw a0, 0(a0)
@@ -617,6 +739,12 @@ define i32 @atomic_load_i32_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i32_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: lw a0, 0(a0)
+; RV64I-ZALRSC-NEXT: fence r, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_load_i32_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: lw a0, 0(a0)
@@ -684,6 +812,13 @@ define i32 @atomic_load_i32_seq_cst(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i32_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: fence rw, rw
+; RV32I-ZALRSC-NEXT: lw a0, 0(a0)
+; RV32I-ZALRSC-NEXT: fence r, rw
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_load_i32_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: fence rw, rw
@@ -707,6 +842,13 @@ define i32 @atomic_load_i32_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i32_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, rw
+; RV64I-ZALRSC-NEXT: lw a0, 0(a0)
+; RV64I-ZALRSC-NEXT: fence r, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_load_i32_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, rw
@@ -770,6 +912,16 @@ define i64 @atomic_load_i64_unordered(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i64_unordered:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a1, 0
+; RV32I-ZALRSC-NEXT: call __atomic_load_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_load_i64_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -790,6 +942,11 @@ define i64 @atomic_load_i64_unordered(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i64_unordered:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: ld a0, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_load_i64_unordered:
; RV64IA: # %bb.0:
; RV64IA-NEXT: ld a0, 0(a0)
@@ -809,6 +966,16 @@ define i64 @atomic_load_i64_monotonic(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a1, 0
+; RV32I-ZALRSC-NEXT: call __atomic_load_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_load_i64_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -829,6 +996,11 @@ define i64 @atomic_load_i64_monotonic(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: ld a0, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_load_i64_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: ld a0, 0(a0)
@@ -848,6 +1020,16 @@ define i64 @atomic_load_i64_acquire(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i64_acquire:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a1, 2
+; RV32I-ZALRSC-NEXT: call __atomic_load_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_load_i64_acquire:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -868,6 +1050,12 @@ define i64 @atomic_load_i64_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i64_acquire:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: ld a0, 0(a0)
+; RV64I-ZALRSC-NEXT: fence r, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_load_i64_acquire:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: ld a0, 0(a0)
@@ -914,6 +1102,16 @@ define i64 @atomic_load_i64_seq_cst(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_load_i64_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a1, 5
+; RV32I-ZALRSC-NEXT: call __atomic_load_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_load_i64_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -934,6 +1132,13 @@ define i64 @atomic_load_i64_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_load_i64_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, rw
+; RV64I-ZALRSC-NEXT: ld a0, 0(a0)
+; RV64I-ZALRSC-NEXT: fence r, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_load_i64_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, rw
@@ -979,6 +1184,11 @@ define void @atomic_store_i8_unordered(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i8_unordered:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: sb a1, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_store_i8_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sb a1, 0(a0)
@@ -994,6 +1204,11 @@ define void @atomic_store_i8_unordered(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i8_unordered:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sb a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_store_i8_unordered:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sb a1, 0(a0)
@@ -1013,6 +1228,11 @@ define void @atomic_store_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i8_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: sb a1, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_store_i8_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sb a1, 0(a0)
@@ -1028,6 +1248,11 @@ define void @atomic_store_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i8_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sb a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_store_i8_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sb a1, 0(a0)
@@ -1047,6 +1272,12 @@ define void @atomic_store_i8_release(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i8_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: fence rw, w
+; RV32I-ZALRSC-NEXT: sb a1, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_store_i8_release:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: fence rw, w
@@ -1068,6 +1299,12 @@ define void @atomic_store_i8_release(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i8_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, w
+; RV64I-ZALRSC-NEXT: sb a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_store_i8_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, w
@@ -1135,6 +1372,13 @@ define void @atomic_store_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i8_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: fence rw, w
+; RV32I-ZALRSC-NEXT: sb a1, 0(a0)
+; RV32I-ZALRSC-NEXT: fence rw, rw
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_store_i8_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: fence rw, w
@@ -1157,6 +1401,13 @@ define void @atomic_store_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i8_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, w
+; RV64I-ZALRSC-NEXT: sb a1, 0(a0)
+; RV64I-ZALRSC-NEXT: fence rw, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_store_i8_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, w
@@ -1219,6 +1470,11 @@ define void @atomic_store_i16_unordered(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i16_unordered:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: sh a1, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_store_i16_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sh a1, 0(a0)
@@ -1234,6 +1490,11 @@ define void @atomic_store_i16_unordered(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i16_unordered:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sh a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_store_i16_unordered:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sh a1, 0(a0)
@@ -1253,6 +1514,11 @@ define void @atomic_store_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i16_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: sh a1, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_store_i16_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sh a1, 0(a0)
@@ -1268,6 +1534,11 @@ define void @atomic_store_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i16_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sh a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_store_i16_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sh a1, 0(a0)
@@ -1287,6 +1558,12 @@ define void @atomic_store_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i16_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: fence rw, w
+; RV32I-ZALRSC-NEXT: sh a1, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_store_i16_release:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: fence rw, w
@@ -1308,6 +1585,12 @@ define void @atomic_store_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i16_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, w
+; RV64I-ZALRSC-NEXT: sh a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_store_i16_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, w
@@ -1375,6 +1658,13 @@ define void @atomic_store_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i16_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: fence rw, w
+; RV32I-ZALRSC-NEXT: sh a1, 0(a0)
+; RV32I-ZALRSC-NEXT: fence rw, rw
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_store_i16_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: fence rw, w
@@ -1397,6 +1687,13 @@ define void @atomic_store_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i16_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, w
+; RV64I-ZALRSC-NEXT: sh a1, 0(a0)
+; RV64I-ZALRSC-NEXT: fence rw, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_store_i16_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, w
@@ -1459,6 +1756,11 @@ define void @atomic_store_i32_unordered(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i32_unordered:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: sw a1, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_store_i32_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sw a1, 0(a0)
@@ -1474,6 +1776,11 @@ define void @atomic_store_i32_unordered(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i32_unordered:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sw a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_store_i32_unordered:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sw a1, 0(a0)
@@ -1493,6 +1800,11 @@ define void @atomic_store_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i32_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: sw a1, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_store_i32_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: sw a1, 0(a0)
@@ -1508,6 +1820,11 @@ define void @atomic_store_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i32_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sw a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_store_i32_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sw a1, 0(a0)
@@ -1527,6 +1844,12 @@ define void @atomic_store_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i32_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: fence rw, w
+; RV32I-ZALRSC-NEXT: sw a1, 0(a0)
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_store_i32_release:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: fence rw, w
@@ -1548,6 +1871,12 @@ define void @atomic_store_i32_release(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i32_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, w
+; RV64I-ZALRSC-NEXT: sw a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_store_i32_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, w
@@ -1615,6 +1944,13 @@ define void @atomic_store_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i32_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: fence rw, w
+; RV32I-ZALRSC-NEXT: sw a1, 0(a0)
+; RV32I-ZALRSC-NEXT: fence rw, rw
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-WMO-LABEL: atomic_store_i32_seq_cst:
; RV32IA-WMO: # %bb.0:
; RV32IA-WMO-NEXT: fence rw, w
@@ -1637,6 +1973,13 @@ define void @atomic_store_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i32_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, w
+; RV64I-ZALRSC-NEXT: sw a1, 0(a0)
+; RV64I-ZALRSC-NEXT: fence rw, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_store_i32_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, w
@@ -1699,6 +2042,16 @@ define void @atomic_store_i64_unordered(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i64_unordered:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 0
+; RV32I-ZALRSC-NEXT: call __atomic_store_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_store_i64_unordered:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -1719,6 +2072,11 @@ define void @atomic_store_i64_unordered(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i64_unordered:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sd a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_store_i64_unordered:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sd a1, 0(a0)
@@ -1738,6 +2096,16 @@ define void @atomic_store_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i64_monotonic:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 0
+; RV32I-ZALRSC-NEXT: call __atomic_store_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_store_i64_monotonic:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -1758,6 +2126,11 @@ define void @atomic_store_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i64_monotonic:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: sd a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-LABEL: atomic_store_i64_monotonic:
; RV64IA: # %bb.0:
; RV64IA-NEXT: sd a1, 0(a0)
@@ -1777,6 +2150,16 @@ define void @atomic_store_i64_release(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i64_release:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 3
+; RV32I-ZALRSC-NEXT: call __atomic_store_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_store_i64_release:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -1797,6 +2180,12 @@ define void @atomic_store_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i64_release:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, w
+; RV64I-ZALRSC-NEXT: sd a1, 0(a0)
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_store_i64_release:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, w
@@ -1843,6 +2232,16 @@ define void @atomic_store_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
+; RV32I-ZALRSC-LABEL: atomic_store_i64_seq_cst:
+; RV32I-ZALRSC: # %bb.0:
+; RV32I-ZALRSC-NEXT: addi sp, sp, -16
+; RV32I-ZALRSC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-ZALRSC-NEXT: li a3, 5
+; RV32I-ZALRSC-NEXT: call __atomic_store_8
+; RV32I-ZALRSC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-ZALRSC-NEXT: addi sp, sp, 16
+; RV32I-ZALRSC-NEXT: ret
+;
; RV32IA-LABEL: atomic_store_i64_seq_cst:
; RV32IA: # %bb.0:
; RV32IA-NEXT: addi sp, sp, -16
@@ -1863,6 +2262,13 @@ define void @atomic_store_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
+; RV64I-ZALRSC-LABEL: atomic_store_i64_seq_cst:
+; RV64I-ZALRSC: # %bb.0:
+; RV64I-ZALRSC-NEXT: fence rw, w
+; RV64I-ZALRSC-NEXT: sd a1, 0(a0)
+; RV64I-ZALRSC-NEXT: fence rw, rw
+; RV64I-ZALRSC-NEXT: ret
+;
; RV64IA-WMO-LABEL: atomic_store_i64_seq_cst:
; RV64IA-WMO: # %bb.0:
; RV64IA-WMO-NEXT: fence rw, w
generated by cgit v1.1 at 2025-10-22 13:15:44 +0000