5 files changed, 220 insertions, 152 deletions
diff --git a/llvm/test/CodeGen/ARM/combine-movc-sub.ll b/llvm/test/CodeGen/ARM/combine-movc-sub.ll
index ca5d089..8ca4c43 100644
--- a/llvm/test/CodeGen/ARM/combine-movc-sub.ll
+++ b/llvm/test/CodeGen/ARM/combine-movc-sub.ll
@@ -27,11 +27,11 @@ define hidden fastcc ptr @test(ptr %Search, ptr %ClauseList, i32 %Level, ptr noc
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    push.w {r4, r5, r6, r7, r8, r9, lr}
 ; CHECK-NEXT:    sub sp, #4
-; CHECK-NEXT:    sub.w r7, r2, #32
-; CHECK-NEXT:    mov r8, r0
+; CHECK-NEXT:    sub.w r8, r2, #32
+; CHECK-NEXT:    mov r6, r0
 ; CHECK-NEXT:    movs r0, #1
 ; CHECK-NEXT:    mov r4, r2
-; CHECK-NEXT:    add.w r6, r0, r7, lsr #5
+; CHECK-NEXT:    add.w r7, r0, r8, lsr #5
 ; CHECK-NEXT:    mov r5, r1
 ; CHECK-NEXT:    mov.w r9, #0
 ; CHECK-NEXT:    b .LBB0_2
@@ -44,16 +44,16 @@ define hidden fastcc ptr @test(ptr %Search, ptr %ClauseList, i32 %Level, ptr noc
 ; CHECK-NEXT:    mov r2, r4
 ; CHECK-NEXT:    cmp r4, #31
 ; CHECK-NEXT:    ldr r0, [r1, #16]
-; CHECK-NEXT:    add.w r0, r0, r6, lsl #2
+; CHECK-NEXT:    add.w r0, r0, r7, lsl #2
 ; CHECK-NEXT:    ldr r0, [r0, #40]
 ; CHECK-NEXT:    it hi
-; CHECK-NEXT:    andhi r2, r7, #31
+; CHECK-NEXT:    andhi r2, r8, #31
 ; CHECK-NEXT:    lsrs r0, r2
 ; CHECK-NEXT:    lsls r0, r0, #31
 ; CHECK-NEXT:    beq .LBB0_1
 ; CHECK-NEXT:  @ %bb.3: @ %if.then
 ; CHECK-NEXT:    @ in Loop: Header=BB0_2 Depth=1
-; CHECK-NEXT:    mov r0, r8
+; CHECK-NEXT:    mov r0, r6
 ; CHECK-NEXT:    bl foo
 ; CHECK-NEXT:    str.w r9, [r5, #4]
 ; CHECK-NEXT:    b .LBB0_1
diff --git a/llvm/test/CodeGen/ARM/extract-bits.ll b/llvm/test/CodeGen/ARM/extract-bits.ll
index 77deaa5..d717806 100644
--- a/llvm/test/CodeGen/ARM/extract-bits.ll
+++ b/llvm/test/CodeGen/ARM/extract-bits.ll
@@ -316,28 +316,28 @@ define i64 @bextr64_a0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind {
 ;
 ; V7A-LABEL: bextr64_a0:
 ; V7A:       @ %bb.0:
-; V7A-NEXT:    .save {r4, lr}
-; V7A-NEXT:    push {r4, lr}
-; V7A-NEXT:    ldr r12, [sp, #8]
-; V7A-NEXT:    mov lr, #1
+; V7A-NEXT:    .save {r4, r5, r11, lr}
+; V7A-NEXT:    push {r4, r5, r11, lr}
+; V7A-NEXT:    ldr lr, [sp, #16]
+; V7A-NEXT:    mov r5, #1
 ; V7A-NEXT:    lsr r0, r0, r2
-; V7A-NEXT:    rsb r3, r12, #32
-; V7A-NEXT:    subs r4, r12, #32
-; V7A-NEXT:    lsr r3, lr, r3
-; V7A-NEXT:    lslpl r3, lr, r4
-; V7A-NEXT:    lsl r4, lr, r12
-; V7A-NEXT:    movwpl r4, #0
-; V7A-NEXT:    subs r4, r4, #1
-; V7A-NEXT:    sbc r12, r3, #0
-; V7A-NEXT:    rsb r3, r2, #32
-; V7A-NEXT:    orr r0, r0, r1, lsl r3
-; V7A-NEXT:    subs r3, r2, #32
-; V7A-NEXT:    lsrpl r0, r1, r3
+; V7A-NEXT:    rsb r12, lr, #32
+; V7A-NEXT:    subs r4, lr, #32
+; V7A-NEXT:    lsr r3, r5, r12
+; V7A-NEXT:    lslpl r3, r5, r4
+; V7A-NEXT:    lsl r5, r5, lr
+; V7A-NEXT:    movwpl r5, #0
+; V7A-NEXT:    rsb r4, r2, #32
+; V7A-NEXT:    subs r5, r5, #1
+; V7A-NEXT:    sbc r3, r3, #0
+; V7A-NEXT:    orr r0, r0, r1, lsl r4
+; V7A-NEXT:    subs r4, r2, #32
+; V7A-NEXT:    lsrpl r0, r1, r4
 ; V7A-NEXT:    lsr r1, r1, r2
 ; V7A-NEXT:    movwpl r1, #0
-; V7A-NEXT:    and r0, r4, r0
-; V7A-NEXT:    and r1, r12, r1
-; V7A-NEXT:    pop {r4, pc}
+; V7A-NEXT:    and r0, r5, r0
+; V7A-NEXT:    and r1, r3, r1
+; V7A-NEXT:    pop {r4, r5, r11, pc}
 ;
 ; V7A-T-LABEL: bextr64_a0:
 ; V7A-T:       @ %bb.0:
@@ -434,28 +434,28 @@ define i64 @bextr64_a0_arithmetic(i64 %val, i64 %numskipbits, i64 %numlowbits) n
 ;
 ; V7A-LABEL: bextr64_a0_arithmetic:
 ; V7A:       @ %bb.0:
-; V7A-NEXT:    .save {r4, lr}
-; V7A-NEXT:    push {r4, lr}
-; V7A-NEXT:    ldr r12, [sp, #8]
-; V7A-NEXT:    mov lr, #1
+; V7A-NEXT:    .save {r4, r5, r11, lr}
+; V7A-NEXT:    push {r4, r5, r11, lr}
+; V7A-NEXT:    ldr lr, [sp, #16]
+; V7A-NEXT:    mov r5, #1
 ; V7A-NEXT:    lsr r0, r0, r2
-; V7A-NEXT:    rsb r3, r12, #32
-; V7A-NEXT:    subs r4, r12, #32
-; V7A-NEXT:    lsr r3, lr, r3
-; V7A-NEXT:    lslpl r3, lr, r4
-; V7A-NEXT:    lsl r4, lr, r12
-; V7A-NEXT:    movwpl r4, #0
-; V7A-NEXT:    subs r4, r4, #1
-; V7A-NEXT:    sbc r12, r3, #0
-; V7A-NEXT:    rsb r3, r2, #32
-; V7A-NEXT:    orr r0, r0, r1, lsl r3
-; V7A-NEXT:    subs r3, r2, #32
+; V7A-NEXT:    rsb r12, lr, #32
+; V7A-NEXT:    subs r4, lr, #32
+; V7A-NEXT:    lsr r3, r5, r12
+; V7A-NEXT:    lslpl r3, r5, r4
+; V7A-NEXT:    lsl r5, r5, lr
+; V7A-NEXT:    movwpl r5, #0
+; V7A-NEXT:    rsb r4, r2, #32
+; V7A-NEXT:    subs r5, r5, #1
+; V7A-NEXT:    sbc r3, r3, #0
+; V7A-NEXT:    orr r0, r0, r1, lsl r4
+; V7A-NEXT:    subs r4, r2, #32
 ; V7A-NEXT:    asr r2, r1, r2
-; V7A-NEXT:    asrpl r0, r1, r3
 ; V7A-NEXT:    asrpl r2, r1, #31
-; V7A-NEXT:    and r0, r4, r0
-; V7A-NEXT:    and r1, r12, r2
-; V7A-NEXT:    pop {r4, pc}
+; V7A-NEXT:    asrpl r0, r1, r4
+; V7A-NEXT:    and r1, r3, r2
+; V7A-NEXT:    and r0, r5, r0
+; V7A-NEXT:    pop {r4, r5, r11, pc}
 ;
 ; V7A-T-LABEL: bextr64_a0_arithmetic:
 ; V7A-T:       @ %bb.0:
@@ -911,28 +911,28 @@ define i64 @bextr64_a4_commutative(i64 %val, i64 %numskipbits, i64 %numlowbits)
 ;
 ; V7A-LABEL: bextr64_a4_commutative:
 ; V7A:       @ %bb.0:
-; V7A-NEXT:    .save {r4, lr}
-; V7A-NEXT:    push {r4, lr}
-; V7A-NEXT:    ldr r12, [sp, #8]
-; V7A-NEXT:    mov lr, #1
+; V7A-NEXT:    .save {r4, r5, r11, lr}
+; V7A-NEXT:    push {r4, r5, r11, lr}
+; V7A-NEXT:    ldr lr, [sp, #16]
+; V7A-NEXT:    mov r5, #1
 ; V7A-NEXT:    lsr r0, r0, r2
-; V7A-NEXT:    rsb r3, r12, #32
-; V7A-NEXT:    subs r4, r12, #32
-; V7A-NEXT:    lsr r3, lr, r3
-; V7A-NEXT:    lslpl r3, lr, r4
-; V7A-NEXT:    lsl r4, lr, r12
-; V7A-NEXT:    movwpl r4, #0
-; V7A-NEXT:    subs r4, r4, #1
-; V7A-NEXT:    sbc r12, r3, #0
-; V7A-NEXT:    rsb r3, r2, #32
-; V7A-NEXT:    orr r0, r0, r1, lsl r3
-; V7A-NEXT:    subs r3, r2, #32
-; V7A-NEXT:    lsrpl r0, r1, r3
+; V7A-NEXT:    rsb r12, lr, #32
+; V7A-NEXT:    subs r4, lr, #32
+; V7A-NEXT:    lsr r3, r5, r12
+; V7A-NEXT:    lslpl r3, r5, r4
+; V7A-NEXT:    lsl r5, r5, lr
+; V7A-NEXT:    movwpl r5, #0
+; V7A-NEXT:    rsb r4, r2, #32
+; V7A-NEXT:    subs r5, r5, #1
+; V7A-NEXT:    sbc r3, r3, #0
+; V7A-NEXT:    orr r0, r0, r1, lsl r4
+; V7A-NEXT:    subs r4, r2, #32
+; V7A-NEXT:    lsrpl r0, r1, r4
 ; V7A-NEXT:    lsr r1, r1, r2
 ; V7A-NEXT:    movwpl r1, #0
-; V7A-NEXT:    and r0, r0, r4
-; V7A-NEXT:    and r1, r1, r12
-; V7A-NEXT:    pop {r4, pc}
+; V7A-NEXT:    and r0, r0, r5
+; V7A-NEXT:    and r1, r1, r3
+; V7A-NEXT:    pop {r4, r5, r11, pc}
 ;
 ; V7A-T-LABEL: bextr64_a4_commutative:
 ; V7A-T:       @ %bb.0:
@@ -3456,22 +3456,22 @@ define i64 @bextr64_d1_indexzext(i64 %val, i8 %numskipbits, i8 %numlowbits) noun
 ; V7M-NEXT:    uxtb r2, r2
 ; V7M-NEXT:    it pl
 ; V7M-NEXT:    movpl r1, #0
-; V7M-NEXT:    rsb.w r12, r2, #32
+; V7M-NEXT:    rsb.w r3, r2, #32
 ; V7M-NEXT:    lsls r1, r2
-; V7M-NEXT:    sub.w r3, r2, #32
-; V7M-NEXT:    lsr.w r4, r0, r12
+; V7M-NEXT:    sub.w r12, r2, #32
+; V7M-NEXT:    lsr.w r4, r0, r3
 ; V7M-NEXT:    orrs r1, r4
-; V7M-NEXT:    cmp r3, #0
+; V7M-NEXT:    cmp.w r12, #0
 ; V7M-NEXT:    it pl
-; V7M-NEXT:    lslpl.w r1, r0, r3
+; V7M-NEXT:    lslpl.w r1, r0, r12
 ; V7M-NEXT:    lsl.w r0, r0, r2
-; V7M-NEXT:    lsl.w r4, r1, r12
+; V7M-NEXT:    lsl.w r3, r1, r3
 ; V7M-NEXT:    it pl
 ; V7M-NEXT:    movpl r0, #0
 ; V7M-NEXT:    lsr.w r0, r0, r2
-; V7M-NEXT:    orr.w r0, r0, r4
+; V7M-NEXT:    orr.w r0, r0, r3
 ; V7M-NEXT:    it pl
-; V7M-NEXT:    lsrpl.w r0, r1, r3
+; V7M-NEXT:    lsrpl.w r0, r1, r12
 ; V7M-NEXT:    lsr.w r1, r1, r2
 ; V7M-NEXT:    it pl
 ; V7M-NEXT:    movpl r1, #0
@@ -3715,26 +3715,26 @@ define i64 @bextr64_d3_load_indexzext(ptr %w, i8 %numskipbits, i8 %numlowbits) n
 ; V7M-NEXT:    uxtb r2, r2
 ; V7M-NEXT:    lsl.w r0, lr, r0
 ; V7M-NEXT:    orr.w r0, r0, r12
-; V7M-NEXT:    rsb.w r12, r2, #32
+; V7M-NEXT:    sub.w r12, r2, #32
 ; V7M-NEXT:    it pl
 ; V7M-NEXT:    lsrpl.w r0, lr, r3
 ; V7M-NEXT:    it pl
 ; V7M-NEXT:    movpl r1, #0
+; V7M-NEXT:    rsb.w r3, r2, #32
 ; V7M-NEXT:    lsls r1, r2
-; V7M-NEXT:    sub.w r3, r2, #32
-; V7M-NEXT:    lsr.w r4, r0, r12
-; V7M-NEXT:    orrs r1, r4
-; V7M-NEXT:    cmp r3, #0
+; V7M-NEXT:    cmp.w r12, #0
+; V7M-NEXT:    lsr.w r4, r0, r3
+; V7M-NEXT:    orr.w r1, r1, r4
 ; V7M-NEXT:    it pl
-; V7M-NEXT:    lslpl.w r1, r0, r3
+; V7M-NEXT:    lslpl.w r1, r0, r12
 ; V7M-NEXT:    lsl.w r0, r0, r2
-; V7M-NEXT:    lsl.w r4, r1, r12
 ; V7M-NEXT:    it pl
 ; V7M-NEXT:    movpl r0, #0
+; V7M-NEXT:    lsl.w r3, r1, r3
 ; V7M-NEXT:    lsr.w r0, r0, r2
-; V7M-NEXT:    orr.w r0, r0, r4
+; V7M-NEXT:    orr.w r0, r0, r3
 ; V7M-NEXT:    it pl
-; V7M-NEXT:    lsrpl.w r0, r1, r3
+; V7M-NEXT:    lsrpl.w r0, r1, r12
 ; V7M-NEXT:    lsr.w r1, r1, r2
 ; V7M-NEXT:    it pl
 ; V7M-NEXT:    movpl r1, #0
diff --git a/llvm/test/CodeGen/ARM/extract-lowbits.ll b/llvm/test/CodeGen/ARM/extract-lowbits.ll
index b483793..373d998 100644
--- a/llvm/test/CodeGen/ARM/extract-lowbits.ll
+++ b/llvm/test/CodeGen/ARM/extract-lowbits.ll
@@ -243,15 +243,15 @@ define i64 @bzhi64_a0(i64 %val, i64 %numlowbits) nounwind {
 ; V7A:       @ %bb.0:
 ; V7A-NEXT:    .save {r11, lr}
 ; V7A-NEXT:    push {r11, lr}
-; V7A-NEXT:    rsb r3, r2, #32
-; V7A-NEXT:    mov r12, #1
-; V7A-NEXT:    lsr lr, r12, r3
+; V7A-NEXT:    rsb r12, r2, #32
+; V7A-NEXT:    mov lr, #1
 ; V7A-NEXT:    subs r3, r2, #32
-; V7A-NEXT:    lsl r2, r12, r2
+; V7A-NEXT:    lsl r2, lr, r2
+; V7A-NEXT:    lsr r12, lr, r12
 ; V7A-NEXT:    movwpl r2, #0
-; V7A-NEXT:    lslpl lr, r12, r3
+; V7A-NEXT:    lslpl r12, lr, r3
 ; V7A-NEXT:    subs r2, r2, #1
-; V7A-NEXT:    sbc r3, lr, #0
+; V7A-NEXT:    sbc r3, r12, #0
 ; V7A-NEXT:    and r0, r2, r0
 ; V7A-NEXT:    and r1, r3, r1
 ; V7A-NEXT:    pop {r11, pc}
@@ -323,15 +323,15 @@ define i64 @bzhi64_a0_masked(i64 %val, i64 %numlowbits) nounwind {
 ; V7A-NEXT:    .save {r11, lr}
 ; V7A-NEXT:    push {r11, lr}
 ; V7A-NEXT:    and r2, r2, #63
-; V7A-NEXT:    mov r12, #1
-; V7A-NEXT:    rsb r3, r2, #32
-; V7A-NEXT:    lsr lr, r12, r3
+; V7A-NEXT:    mov lr, #1
+; V7A-NEXT:    rsb r12, r2, #32
 ; V7A-NEXT:    subs r3, r2, #32
-; V7A-NEXT:    lsl r2, r12, r2
+; V7A-NEXT:    lsl r2, lr, r2
+; V7A-NEXT:    lsr r12, lr, r12
 ; V7A-NEXT:    movwpl r2, #0
-; V7A-NEXT:    lslpl lr, r12, r3
+; V7A-NEXT:    lslpl r12, lr, r3
 ; V7A-NEXT:    subs r2, r2, #1
-; V7A-NEXT:    sbc r3, lr, #0
+; V7A-NEXT:    sbc r3, r12, #0
 ; V7A-NEXT:    and r0, r2, r0
 ; V7A-NEXT:    and r1, r3, r1
 ; V7A-NEXT:    pop {r11, pc}
@@ -404,15 +404,15 @@ define i64 @bzhi64_a1_indexzext(i64 %val, i8 zeroext %numlowbits) nounwind {
 ; V7A:       @ %bb.0:
 ; V7A-NEXT:    .save {r11, lr}
 ; V7A-NEXT:    push {r11, lr}
-; V7A-NEXT:    rsb r3, r2, #32
-; V7A-NEXT:    mov r12, #1
-; V7A-NEXT:    lsr lr, r12, r3
+; V7A-NEXT:    rsb r12, r2, #32
+; V7A-NEXT:    mov lr, #1
 ; V7A-NEXT:    subs r3, r2, #32
-; V7A-NEXT:    lsl r2, r12, r2
+; V7A-NEXT:    lsl r2, lr, r2
+; V7A-NEXT:    lsr r12, lr, r12
 ; V7A-NEXT:    movwpl r2, #0
-; V7A-NEXT:    lslpl lr, r12, r3
+; V7A-NEXT:    lslpl r12, lr, r3
 ; V7A-NEXT:    subs r2, r2, #1
-; V7A-NEXT:    sbc r3, lr, #0
+; V7A-NEXT:    sbc r3, r12, #0
 ; V7A-NEXT:    and r0, r2, r0
 ; V7A-NEXT:    and r1, r3, r1
 ; V7A-NEXT:    pop {r11, pc}
@@ -644,15 +644,15 @@ define i64 @bzhi64_a4_commutative(i64 %val, i64 %numlowbits) nounwind {
 ; V7A:       @ %bb.0:
 ; V7A-NEXT:    .save {r11, lr}
 ; V7A-NEXT:    push {r11, lr}
-; V7A-NEXT:    rsb r3, r2, #32
-; V7A-NEXT:    mov r12, #1
-; V7A-NEXT:    lsr lr, r12, r3
+; V7A-NEXT:    rsb r12, r2, #32
+; V7A-NEXT:    mov lr, #1
 ; V7A-NEXT:    subs r3, r2, #32
-; V7A-NEXT:    lsl r2, r12, r2
+; V7A-NEXT:    lsl r2, lr, r2
+; V7A-NEXT:    lsr r12, lr, r12
 ; V7A-NEXT:    movwpl r2, #0
-; V7A-NEXT:    lslpl lr, r12, r3
+; V7A-NEXT:    lslpl r12, lr, r3
 ; V7A-NEXT:    subs r2, r2, #1
-; V7A-NEXT:    sbc r3, lr, #0
+; V7A-NEXT:    sbc r3, r12, #0
 ; V7A-NEXT:    and r0, r0, r2
 ; V7A-NEXT:    and r1, r1, r3
 ; V7A-NEXT:    pop {r11, pc}
@@ -2144,23 +2144,23 @@ define i64 @bzhi64_d2_load(ptr %w, i64 %numlowbits) nounwind {
 ;
 ; V7A-LABEL: bzhi64_d2_load:
 ; V7A:       @ %bb.0:
-; V7A-NEXT:    .save {r5, r7, r11, lr}
-; V7A-NEXT:    push {r5, r7, r11, lr}
+; V7A-NEXT:    .save {r5, lr}
+; V7A-NEXT:    push {r5, lr}
 ; V7A-NEXT:    rsb r3, r2, #64
-; V7A-NEXT:    ldm r0, {r0, r7}
-; V7A-NEXT:    rsb r1, r3, #32
+; V7A-NEXT:    ldm r0, {r0, r5}
+; V7A-NEXT:    rsb r12, r3, #32
 ; V7A-NEXT:    rsbs r2, r2, #32
-; V7A-NEXT:    lsr r5, r0, r1
-; V7A-NEXT:    orr r7, r5, r7, lsl r3
-; V7A-NEXT:    lslpl r7, r0, r2
+; V7A-NEXT:    lsr r1, r0, r12
+; V7A-NEXT:    orr r1, r1, r5, lsl r3
+; V7A-NEXT:    lslpl r1, r0, r2
 ; V7A-NEXT:    lsl r0, r0, r3
 ; V7A-NEXT:    movwpl r0, #0
 ; V7A-NEXT:    lsr r0, r0, r3
-; V7A-NEXT:    orr r0, r0, r7, lsl r1
-; V7A-NEXT:    lsr r1, r7, r3
-; V7A-NEXT:    lsrpl r0, r7, r2
+; V7A-NEXT:    orr r0, r0, r1, lsl r12
+; V7A-NEXT:    lsrpl r0, r1, r2
+; V7A-NEXT:    lsr r1, r1, r3
 ; V7A-NEXT:    movwpl r1, #0
-; V7A-NEXT:    pop {r5, r7, r11, pc}
+; V7A-NEXT:    pop {r5, pc}
 ;
 ; V7A-T-LABEL: bzhi64_d2_load:
 ; V7A-T:       @ %bb.0:
@@ -2237,26 +2237,26 @@ define i64 @bzhi64_d3_load_indexzext(ptr %w, i8 %numlowbits) nounwind {
 ;
 ; V7A-LABEL: bzhi64_d3_load_indexzext:
 ; V7A:       @ %bb.0:
-; V7A-NEXT:    .save {r5, r7, r11, lr}
-; V7A-NEXT:    push {r5, r7, r11, lr}
+; V7A-NEXT:    .save {r5, lr}
+; V7A-NEXT:    push {r5, lr}
 ; V7A-NEXT:    rsb r1, r1, #64
-; V7A-NEXT:    ldm r0, {r0, r7}
+; V7A-NEXT:    ldm r0, {r0, r5}
 ; V7A-NEXT:    uxtb r2, r1
-; V7A-NEXT:    rsb r3, r2, #32
-; V7A-NEXT:    lsr r5, r0, r3
-; V7A-NEXT:    orr r7, r5, r7, lsl r2
+; V7A-NEXT:    rsb r12, r2, #32
+; V7A-NEXT:    lsr r3, r0, r12
+; V7A-NEXT:    orr r3, r3, r5, lsl r2
 ; V7A-NEXT:    mvn r5, #31
 ; V7A-NEXT:    uxtab r1, r5, r1
 ; V7A-NEXT:    cmp r1, #0
-; V7A-NEXT:    lslpl r7, r0, r1
+; V7A-NEXT:    lslpl r3, r0, r1
 ; V7A-NEXT:    lsl r0, r0, r2
 ; V7A-NEXT:    movwpl r0, #0
 ; V7A-NEXT:    lsr r0, r0, r2
-; V7A-NEXT:    orr r0, r0, r7, lsl r3
-; V7A-NEXT:    lsrpl r0, r7, r1
-; V7A-NEXT:    lsr r1, r7, r2
+; V7A-NEXT:    orr r0, r0, r3, lsl r12
+; V7A-NEXT:    lsrpl r0, r3, r1
+; V7A-NEXT:    lsr r1, r3, r2
 ; V7A-NEXT:    movwpl r1, #0
-; V7A-NEXT:    pop {r5, r7, r11, pc}
+; V7A-NEXT:    pop {r5, pc}
 ;
 ; V7A-T-LABEL: bzhi64_d3_load_indexzext:
 ; V7A-T:       @ %bb.0:
diff --git a/llvm/test/CodeGen/ARM/llround-conv.ll b/llvm/test/CodeGen/ARM/llround-conv.ll
index 0f57e4a..f734db8 100644
--- a/llvm/test/CodeGen/ARM/llround-conv.ll
+++ b/llvm/test/CodeGen/ARM/llround-conv.ll
@@ -1,25 +1,71 @@
-; RUN: llc < %s -mtriple=arm-eabi -float-abi=soft | FileCheck %s --check-prefix=SOFTFP
-; RUN: llc < %s -mtriple=arm-eabi -float-abi=hard | FileCheck %s --check-prefix=HARDFP
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=armv7-none-eabi -float-abi=soft | FileCheck %s --check-prefixes=CHECK,CHECK-SOFT
+; RUN: llc < %s -mtriple=armv7-none-eabihf -mattr=+vfp2 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16
+; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8,+fullfp16 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
+
+define i64 @testmsxh_builtin(half %x) {
+; CHECK-SOFT-LABEL: testmsxh_builtin:
+; CHECK-SOFT:       @ %bb.0: @ %entry
+; CHECK-SOFT-NEXT:    .save {r11, lr}
+; CHECK-SOFT-NEXT:    push {r11, lr}
+; CHECK-SOFT-NEXT:    bl __aeabi_h2f
+; CHECK-SOFT-NEXT:    bl llroundf
+; CHECK-SOFT-NEXT:    pop {r11, pc}
+;
+; CHECK-NOFP16-LABEL: testmsxh_builtin:
+; CHECK-NOFP16:       @ %bb.0: @ %entry
+; CHECK-NOFP16-NEXT:    .save {r11, lr}
+; CHECK-NOFP16-NEXT:    push {r11, lr}
+; CHECK-NOFP16-NEXT:    vmov r0, s0
+; CHECK-NOFP16-NEXT:    bl __aeabi_h2f
+; CHECK-NOFP16-NEXT:    vmov s0, r0
+; CHECK-NOFP16-NEXT:    bl llroundf
+; CHECK-NOFP16-NEXT:    pop {r11, pc}
+;
+; CHECK-FP16-LABEL: testmsxh_builtin:
+; CHECK-FP16:       @ %bb.0: @ %entry
+; CHECK-FP16-NEXT:    .save {r11, lr}
+; CHECK-FP16-NEXT:    push {r11, lr}
+; CHECK-FP16-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-FP16-NEXT:    bl llroundf
+; CHECK-FP16-NEXT:    pop {r11, pc}
+entry:
+  %0 = tail call i64 @llvm.llround.i64.f16(half %x)
+  ret i64 %0
+}
 
-; SOFTFP-LABEL: testmsxs_builtin:
-; SOFTFP:       bl      llroundf
-; HARDFP-LABEL: testmsxs_builtin:
-; HARDFP:       bl      llroundf
 define i64 @testmsxs_builtin(float %x) {
+; CHECK-LABEL: testmsxs_builtin:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r11, lr}
+; CHECK-NEXT:    push {r11, lr}
+; CHECK-NEXT:    bl llroundf
+; CHECK-NEXT:    pop {r11, pc}
 entry:
-  %0 = tail call i64 @llvm.llround.f32(float %x)
+  %0 = tail call i64 @llvm.llround.i64.f32(float %x)
   ret i64 %0
 }
 
-; SOFTFP-LABEL: testmsxd_builtin:
-; SOFTFP:       bl      llround
-; HARDFP-LABEL: testmsxd_builtin:
-; HARDFP:       bl      llround
 define i64 @testmsxd_builtin(double %x) {
+; CHECK-LABEL: testmsxd_builtin:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r11, lr}
+; CHECK-NEXT:    push {r11, lr}
+; CHECK-NEXT:    bl llround
+; CHECK-NEXT:    pop {r11, pc}
 entry:
-  %0 = tail call i64 @llvm.llround.f64(double %x)
+  %0 = tail call i64 @llvm.llround.i64.f64(double %x)
   ret i64 %0
 }
 
-declare i64 @llvm.llround.f32(float) nounwind readnone
-declare i64 @llvm.llround.f64(double) nounwind readnone
+define i64 @testmsxq_builtin(fp128 %x) {
+; CHECK-LABEL: testmsxq_builtin:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r11, lr}
+; CHECK-NEXT:    push {r11, lr}
+; CHECK-NEXT:    bl llroundl
+; CHECK-NEXT:    pop {r11, pc}
+entry:
+  %0 = tail call i64 @llvm.llround.i64.f128(fp128 %x)
+  ret i64 %0
+}
diff --git a/llvm/test/CodeGen/ARM/lround-conv.ll b/llvm/test/CodeGen/ARM/lround-conv.ll
index 3aaed74..03f7a0d 100644
--- a/llvm/test/CodeGen/ARM/lround-conv.ll
+++ b/llvm/test/CodeGen/ARM/lround-conv.ll
@@ -1,25 +1,47 @@
-; RUN: llc < %s -mtriple=arm-eabi -float-abi=soft | FileCheck %s --check-prefix=SOFTFP
-; RUN: llc < %s -mtriple=arm-eabi -float-abi=hard | FileCheck %s --check-prefix=HARDFP
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=armv7-none-eabi -float-abi=soft | FileCheck %s --check-prefixes=CHECK,CHECK-SOFT
+; RUN: llc < %s -mtriple=armv7-none-eabihf -mattr=+vfp2 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16
+; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FPv8
+; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8,+fullfp16 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
+
+;define i32 @testmswh_builtin(half %x) {
+;entry:
+;  %0 = tail call i32 @llvm.lround.i32.f16(half %x)
+;  ret i32 %0
+;}
 
-; SOFTFP-LABEL: testmsws_builtin:
-; SOFTFP:       bl      lroundf
-; HARDFP-LABEL: testmsws_builtin:
-; HARDFP:       bl      lroundf
 define i32 @testmsws_builtin(float %x) {
+; CHECK-LABEL: testmsws_builtin:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    b lroundf
 entry:
   %0 = tail call i32 @llvm.lround.i32.f32(float %x)
   ret i32 %0
 }
 
-; SOFTFP-LABEL: testmswd_builtin:
-; SOFTFP:       bl      lround
-; HARDFP-LABEL: testmswd_builtin:
-; HARDFP:       bl      lround
 define i32 @testmswd_builtin(double %x) {
+; CHECK-LABEL: testmswd_builtin:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    b lround
 entry:
   %0 = tail call i32 @llvm.lround.i32.f64(double %x)
   ret i32 %0
 }
 
-declare i32 @llvm.lround.i32.f32(float) nounwind readnone
-declare i32 @llvm.lround.i32.f64(double) nounwind readnone
+define i32 @testmswq_builtin(fp128 %x) {
+; CHECK-LABEL: testmswq_builtin:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r11, lr}
+; CHECK-NEXT:    push {r11, lr}
+; CHECK-NEXT:    bl lroundl
+; CHECK-NEXT:    pop {r11, pc}
+entry:
+  %0 = tail call i32 @llvm.lround.i32.f128(fp128 %x)
+  ret i32 %0
+}
+
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-FP16: {{.*}}
+; CHECK-FPv8: {{.*}}
+; CHECK-NOFP16: {{.*}}
+; CHECK-SOFT: {{.*}}