diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/fmaximum.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/fmaximum.ll | 921 |
1 files changed, 790 insertions, 131 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum.ll b/llvm/test/CodeGen/AMDGPU/fmaximum.ll index e59fbad..62ec010 100644 --- a/llvm/test/CodeGen/AMDGPU/fmaximum.ll +++ b/llvm/test/CodeGen/AMDGPU/fmaximum.ll @@ -1,117 +1,296 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-SDAG,GFX12-SDAG-TRUE16 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-SDAG,GFX12-SDAG-FAKE16 %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-GISEL,GFX12-GISEL-TRUE16 %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-GISEL,GFX12-GISEL-FAKE16 %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-SDAG %s +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s define amdgpu_ps float @test_fmaximum_f32_vv(float %a, float %b) { -; GCN-LABEL: test_fmaximum_f32_vv: -; GCN: ; %bb.0: -; GCN-NEXT: v_maximum_f32 v0, v0, v1 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: test_fmaximum_f32_vv: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_max_f32_e32 v2, v0, v1 +; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc +; GFX9-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_f32_vv: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maximum_f32 v0, v0, v1 +; GFX12-NEXT: ; return to shader part epilog %val = call float @llvm.maximum.f32(float %a, float %b) ret float %val } define amdgpu_ps float @test_fmaximum_f32_ss(float inreg %a, float inreg %b) { -; GCN-LABEL: test_fmaximum_f32_ss: -; GCN: ; %bb.0: -; GCN-NEXT: s_maximum_f32 s0, s0, s1 -; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_3) -; GCN-NEXT: v_mov_b32_e32 v0, s0 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: test_fmaximum_f32_ss: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_max_f32_e32 v1, s0, v0 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, s0, v0 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc +; GFX9-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_f32_ss: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_maximum_f32 s0, s0, s1 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) +; GFX12-NEXT: v_mov_b32_e32 v0, s0 +; GFX12-NEXT: ; return to shader part epilog %val = call float @llvm.maximum.f32(float %a, float %b) ret float %val } define amdgpu_ps float @test_fmaximum_f32_vs(float %a, float inreg %b) { -; GCN-LABEL: test_fmaximum_f32_vs: -; GCN: ; %bb.0: -; GCN-NEXT: v_maximum_f32 v0, v0, s0 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: test_fmaximum_f32_vs: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_max_f32_e32 v1, s0, v0 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, s0, v0 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc +; GFX9-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_f32_vs: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maximum_f32 v0, v0, s0 +; GFX12-NEXT: ; return to shader part epilog %val = call float @llvm.maximum.f32(float %a, float %b) ret float %val } define amdgpu_ps float @test_fmaximum_nnan_f32(float %a, float %b) { -; GCN-LABEL: test_fmaximum_nnan_f32: -; GCN: ; %bb.0: -; GCN-NEXT: v_maximum_f32 v0, v0, v1 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: test_fmaximum_nnan_f32: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_max_f32_e32 v0, v0, v1 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_nnan_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maximum_f32 v0, v0, v1 +; GFX12-NEXT: ; return to shader part epilog %val = call nnan float @llvm.maximum.f32(float %a, float %b) ret float %val } +define amdgpu_ps float @test_fmaximum_nsz_f32(float %a, float %b) { +; GFX9-LABEL: test_fmaximum_nsz_f32: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_max_f32_e32 v2, v0, v1 +; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc +; GFX9-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_nsz_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maximum_f32 v0, v0, v1 +; GFX12-NEXT: ; return to shader part epilog + %val = call nsz float @llvm.maximum.f32(float %a, float %b) + ret float %val +} + +define amdgpu_ps float @test_fmaximum_signed_zero_f32() { +; GFX9-LABEL: test_fmaximum_signed_zero_f32: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_signed_zero_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_mov_b32_e32 v0, 0 +; GFX12-NEXT: ; return to shader part epilog + %val = call float @llvm.maximum.f32(float -0.0, float 0.0) + ret float %val +} + define amdgpu_ps <2 x float> @test_fmaximum_v2f32(<2 x float> %a, <2 x float> %b) { -; GCN-LABEL: test_fmaximum_v2f32: -; GCN: ; %bb.0: -; GCN-NEXT: v_maximum_f32 v0, v0, v2 -; GCN-NEXT: v_maximum_f32 v1, v1, v3 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: test_fmaximum_v2f32: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_max_f32_e32 v4, v0, v2 +; GFX9-NEXT: v_mov_b32_e32 v5, 0x7fc00000 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v4, vcc +; GFX9-NEXT: v_max_f32_e32 v2, v1, v3 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc +; GFX9-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_v2f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maximum_f32 v0, v0, v2 +; GFX12-NEXT: v_maximum_f32 v1, v1, v3 +; GFX12-NEXT: ; return to shader part epilog %val = call <2 x float> @llvm.maximum.v2f32(<2 x float> %a, <2 x float> %b) ret <2 x float> %val } define amdgpu_ps <2 x float> @test_fmaximum_v2f32_ss(<2 x float> inreg %a, <2 x float> inreg %b) { -; GCN-LABEL: test_fmaximum_v2f32_ss: -; GCN: ; %bb.0: -; GCN-NEXT: s_maximum_f32 s0, s0, s2 -; GCN-NEXT: s_maximum_f32 s1, s1, s3 -; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_3) -; GCN-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: test_fmaximum_v2f32_ss: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_max_f32_e32 v1, s0, v0 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fc00000 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, s0, v0 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: v_max_f32_e32 v3, s1, v1 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, s1, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc +; GFX9-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_v2f32_ss: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_maximum_f32 s0, s0, s2 +; GFX12-NEXT: s_maximum_f32 s1, s1, s3 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) +; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX12-NEXT: ; return to shader part epilog %val = call <2 x float> @llvm.maximum.v2f32(<2 x float> %a, <2 x float> %b) ret <2 x float> %val } define amdgpu_ps <3 x float> @test_fmaximum_v3f32(<3 x float> %a, <3 x float> %b) { -; GCN-LABEL: test_fmaximum_v3f32: -; GCN: ; %bb.0: -; GCN-NEXT: v_maximum_f32 v0, v0, v3 -; GCN-NEXT: v_maximum_f32 v1, v1, v4 -; GCN-NEXT: v_maximum_f32 v2, v2, v5 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: test_fmaximum_v3f32: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_max_f32_e32 v6, v0, v3 +; GFX9-NEXT: v_mov_b32_e32 v7, 0x7fc00000 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v7, v6, vcc +; GFX9-NEXT: v_max_f32_e32 v3, v1, v4 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v4 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v3, vcc +; GFX9-NEXT: v_max_f32_e32 v3, v2, v5 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v2, v5 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v3, vcc +; GFX9-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_v3f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maximum_f32 v0, v0, v3 +; GFX12-NEXT: v_maximum_f32 v1, v1, v4 +; GFX12-NEXT: v_maximum_f32 v2, v2, v5 +; GFX12-NEXT: ; return to shader part epilog %val = call <3 x float> @llvm.maximum.v3f32(<3 x float> %a, <3 x float> %b) ret <3 x float> %val } define amdgpu_ps <4 x float> @test_fmaximum_v4f32(<4 x float> %a, <4 x float> %b) { -; GCN-LABEL: test_fmaximum_v4f32: -; GCN: ; %bb.0: -; GCN-NEXT: v_maximum_f32 v0, v0, v4 -; GCN-NEXT: v_maximum_f32 v1, v1, v5 -; GCN-NEXT: v_maximum_f32 v2, v2, v6 -; GCN-NEXT: v_maximum_f32 v3, v3, v7 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: test_fmaximum_v4f32: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_max_f32_e32 v8, v0, v4 +; GFX9-NEXT: v_mov_b32_e32 v9, 0x7fc00000 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v4 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v8, vcc +; GFX9-NEXT: v_max_f32_e32 v4, v1, v5 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v5 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc +; GFX9-NEXT: v_max_f32_e32 v4, v2, v6 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v2, v6 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v9, v4, vcc +; GFX9-NEXT: v_max_f32_e32 v4, v3, v7 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v3, v7 +; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v4, vcc +; GFX9-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_v4f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maximum_f32 v0, v0, v4 +; GFX12-NEXT: v_maximum_f32 v1, v1, v5 +; GFX12-NEXT: v_maximum_f32 v2, v2, v6 +; GFX12-NEXT: v_maximum_f32 v3, v3, v7 +; GFX12-NEXT: ; return to shader part epilog %val = call <4 x float> @llvm.maximum.v4f32(<4 x float> %a, <4 x float> %b) ret <4 x float> %val } define amdgpu_ps <16 x float> @test_fmaximum_v16f32(<16 x float> %a, <16 x float> %b) { -; GCN-LABEL: test_fmaximum_v16f32: -; GCN: ; %bb.0: -; GCN-NEXT: v_maximum_f32 v0, v0, v16 -; GCN-NEXT: v_maximum_f32 v1, v1, v17 -; GCN-NEXT: v_maximum_f32 v2, v2, v18 -; GCN-NEXT: v_maximum_f32 v3, v3, v19 -; GCN-NEXT: v_maximum_f32 v4, v4, v20 -; GCN-NEXT: v_maximum_f32 v5, v5, v21 -; GCN-NEXT: v_maximum_f32 v6, v6, v22 -; GCN-NEXT: v_maximum_f32 v7, v7, v23 -; GCN-NEXT: v_maximum_f32 v8, v8, v24 -; GCN-NEXT: v_maximum_f32 v9, v9, v25 -; GCN-NEXT: v_maximum_f32 v10, v10, v26 -; GCN-NEXT: v_maximum_f32 v11, v11, v27 -; GCN-NEXT: v_maximum_f32 v12, v12, v28 -; GCN-NEXT: v_maximum_f32 v13, v13, v29 -; GCN-NEXT: v_maximum_f32 v14, v14, v30 -; GCN-NEXT: v_maximum_f32 v15, v15, v31 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: test_fmaximum_v16f32: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_max_f32_e32 v32, v1, v17 +; GFX9-NEXT: v_mov_b32_e32 v33, 0x7fc00000 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v17 +; GFX9-NEXT: v_max_f32_e32 v1, v0, v16 +; GFX9-NEXT: v_cmp_o_f32_e64 s[12:13], v0, v16 +; GFX9-NEXT: v_max_f32_e32 v17, v2, v18 +; GFX9-NEXT: v_cmp_o_f32_e64 s[0:1], v2, v18 +; GFX9-NEXT: v_max_f32_e32 v18, v3, v19 +; GFX9-NEXT: v_cmp_o_f32_e64 s[2:3], v3, v19 +; GFX9-NEXT: v_max_f32_e32 v19, v4, v20 +; GFX9-NEXT: v_cmp_o_f32_e64 s[4:5], v4, v20 +; GFX9-NEXT: v_max_f32_e32 v20, v5, v21 +; GFX9-NEXT: v_cmp_o_f32_e64 s[6:7], v5, v21 +; GFX9-NEXT: v_max_f32_e32 v21, v6, v22 +; GFX9-NEXT: v_cmp_o_f32_e64 s[8:9], v6, v22 +; GFX9-NEXT: v_max_f32_e32 v22, v7, v23 +; GFX9-NEXT: v_cmp_o_f32_e64 s[10:11], v7, v23 +; GFX9-NEXT: v_max_f32_e32 v23, v8, v24 +; GFX9-NEXT: v_cndmask_b32_e64 v0, v33, v1, s[12:13] +; GFX9-NEXT: v_cndmask_b32_e32 v1, v33, v32, vcc +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v8, v24 +; GFX9-NEXT: v_max_f32_e32 v34, v9, v25 +; GFX9-NEXT: v_cndmask_b32_e32 v8, v33, v23, vcc +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v9, v25 +; GFX9-NEXT: v_max_f32_e32 v35, v10, v26 +; GFX9-NEXT: v_cndmask_b32_e32 v9, v33, v34, vcc +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v10, v26 +; GFX9-NEXT: v_max_f32_e32 v36, v11, v27 +; GFX9-NEXT: v_cndmask_b32_e32 v10, v33, v35, vcc +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v11, v27 +; GFX9-NEXT: v_max_f32_e32 v37, v12, v28 +; GFX9-NEXT: v_cndmask_b32_e32 v11, v33, v36, vcc +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v12, v28 +; GFX9-NEXT: v_max_f32_e32 v16, v13, v29 +; GFX9-NEXT: v_cndmask_b32_e32 v12, v33, v37, vcc +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v13, v29 +; GFX9-NEXT: v_cndmask_b32_e32 v13, v33, v16, vcc +; GFX9-NEXT: v_max_f32_e32 v16, v14, v30 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v14, v30 +; GFX9-NEXT: v_cndmask_b32_e32 v14, v33, v16, vcc +; GFX9-NEXT: v_max_f32_e32 v16, v15, v31 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v15, v31 +; GFX9-NEXT: v_cndmask_b32_e64 v2, v33, v17, s[0:1] +; GFX9-NEXT: v_cndmask_b32_e64 v3, v33, v18, s[2:3] +; GFX9-NEXT: v_cndmask_b32_e64 v4, v33, v19, s[4:5] +; GFX9-NEXT: v_cndmask_b32_e64 v5, v33, v20, s[6:7] +; GFX9-NEXT: v_cndmask_b32_e64 v6, v33, v21, s[8:9] +; GFX9-NEXT: v_cndmask_b32_e64 v7, v33, v22, s[10:11] +; GFX9-NEXT: v_cndmask_b32_e32 v15, v33, v16, vcc +; GFX9-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_v16f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maximum_f32 v0, v0, v16 +; GFX12-NEXT: v_maximum_f32 v1, v1, v17 +; GFX12-NEXT: v_maximum_f32 v2, v2, v18 +; GFX12-NEXT: v_maximum_f32 v3, v3, v19 +; GFX12-NEXT: v_maximum_f32 v4, v4, v20 +; GFX12-NEXT: v_maximum_f32 v5, v5, v21 +; GFX12-NEXT: v_maximum_f32 v6, v6, v22 +; GFX12-NEXT: v_maximum_f32 v7, v7, v23 +; GFX12-NEXT: v_maximum_f32 v8, v8, v24 +; GFX12-NEXT: v_maximum_f32 v9, v9, v25 +; GFX12-NEXT: v_maximum_f32 v10, v10, v26 +; GFX12-NEXT: v_maximum_f32 v11, v11, v27 +; GFX12-NEXT: v_maximum_f32 v12, v12, v28 +; GFX12-NEXT: v_maximum_f32 v13, v13, v29 +; GFX12-NEXT: v_maximum_f32 v14, v14, v30 +; GFX12-NEXT: v_maximum_f32 v15, v15, v31 +; GFX12-NEXT: ; return to shader part epilog %val = call <16 x float> @llvm.maximum.v16f32(<16 x float> %a, <16 x float> %b) ret <16 x float> %val } define amdgpu_ps half @test_fmaximum_f16_vv(half %a, half %b) { +; GFX9-LABEL: test_fmaximum_f16_vv: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_max_f16_e32 v2, v0, v1 +; GFX9-NEXT: v_mov_b32_e32 v3, 0x7e00 +; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc +; GFX9-NEXT: ; return to shader part epilog +; ; GFX12-SDAG-TRUE16-LABEL: test_fmaximum_f16_vv: ; GFX12-SDAG-TRUE16: ; %bb.0: ; GFX12-SDAG-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v1.l @@ -136,35 +315,131 @@ define amdgpu_ps half @test_fmaximum_f16_vv(half %a, half %b) { } define amdgpu_ps half @test_fmaximum_f16_ss(half inreg %a, half inreg %b) { -; GCN-LABEL: test_fmaximum_f16_ss: -; GCN: ; %bb.0: -; GCN-NEXT: s_maximum_f16 s0, s0, s1 -; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_3) -; GCN-NEXT: v_mov_b32_e32 v0, s0 -; GCN-NEXT: ; return to shader part epilog +; GFX9-LABEL: test_fmaximum_f16_ss: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-NEXT: v_max_f16_e32 v1, s0, v0 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x7e00 +; GFX9-NEXT: v_cmp_o_f16_e32 vcc, s0, v0 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc +; GFX9-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_f16_ss: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_maximum_f16 s0, s0, s1 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) +; GFX12-NEXT: v_mov_b32_e32 v0, s0 +; GFX12-NEXT: ; return to shader part epilog %val = call half @llvm.maximum.f16(half %a, half %b) ret half %val } define amdgpu_ps <2 x half> @test_fmaximum_v2f16_vv(<2 x half> %a, <2 x half> %b) { -; GCN-LABEL: test_fmaximum_v2f16_vv: -; GCN: ; %bb.0: -; GCN-NEXT: v_pk_maximum_f16 v0, v0, v1 -; GCN-NEXT: ; return to shader part epilog +; GFX9-SDAG-LABEL: test_fmaximum_v2f16_vv: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: v_pk_max_f16 v2, v0, v1 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x7e00 +; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, v0, v1 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v3, v2, vcc +; GFX9-SDAG-NEXT: v_cmp_o_f16_sdwa vcc, v0, v1 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-SDAG-NEXT: v_cndmask_b32_sdwa v0, v3, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-SDAG-NEXT: s_mov_b32 s0, 0x5040100 +; GFX9-SDAG-NEXT: v_perm_b32 v0, v0, v4, s0 +; GFX9-SDAG-NEXT: ; return to shader part epilog +; +; GFX9-GISEL-LABEL: test_fmaximum_v2f16_vv: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: v_pk_max_f16 v2, v0, v1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7e00 +; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], v0, v1 +; GFX9-GISEL-NEXT: v_cmp_o_f16_sdwa vcc, v0, v1 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v3, v2, s[0:1] +; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v1, v3, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 +; GFX9-GISEL-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_v2f16_vv: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_pk_maximum_f16 v0, v0, v1 +; GFX12-NEXT: ; return to shader part epilog %val = call <2 x half> @llvm.maximum.v2f16(<2 x half> %a, <2 x half> %b) ret <2 x half> %val } define amdgpu_ps <2 x half> @test_fmaximum_v2f16_ss(<2 x half> inreg %a, <2 x half> inreg %b) { -; GCN-LABEL: test_fmaximum_v2f16_ss: -; GCN: ; %bb.0: -; GCN-NEXT: v_pk_maximum_f16 v0, s0, s1 -; GCN-NEXT: ; return to shader part epilog +; GFX9-SDAG-LABEL: test_fmaximum_v2f16_ss: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-SDAG-NEXT: s_lshr_b32 s1, s1, 16 +; GFX9-SDAG-NEXT: v_pk_max_f16 v1, s0, v1 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7e00 +; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, s0, v0 +; GFX9-SDAG-NEXT: s_lshr_b32 s0, s0, 16 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc +; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, s0, v3 +; GFX9-SDAG-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-SDAG-NEXT: v_lshl_or_b32 v0, v1, 16, v0 +; GFX9-SDAG-NEXT: ; return to shader part epilog +; +; GFX9-GISEL-LABEL: test_fmaximum_v2f16_ss: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s1 +; GFX9-GISEL-NEXT: s_lshr_b32 s1, s1, 16 +; GFX9-GISEL-NEXT: s_lshr_b32 s2, s0, 16 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-GISEL-NEXT: v_pk_max_f16 v1, s0, v0 +; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s2, v2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x7e00 +; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], s0, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[0:1] +; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 +; GFX9-GISEL-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_v2f16_ss: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_pk_maximum_f16 v0, s0, s1 +; GFX12-NEXT: ; return to shader part epilog %val = call <2 x half> @llvm.maximum.v2f16(<2 x half> %a, <2 x half> %b) ret <2 x half> %val } define amdgpu_ps <3 x half> @test_fmaximum_v3f16_vv(<3 x half> %a, <3 x half> %b) { +; GFX9-SDAG-LABEL: test_fmaximum_v3f16_vv: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: v_pk_max_f16 v4, v1, v3 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v5, 0x7e00 +; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, v1, v3 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc +; GFX9-SDAG-NEXT: v_pk_max_f16 v3, v0, v2 +; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v5, v3, vcc +; GFX9-SDAG-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-SDAG-NEXT: v_cndmask_b32_sdwa v0, v5, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-SDAG-NEXT: s_mov_b32 s0, 0x5040100 +; GFX9-SDAG-NEXT: v_perm_b32 v0, v0, v4, s0 +; GFX9-SDAG-NEXT: ; return to shader part epilog +; +; GFX9-GISEL-LABEL: test_fmaximum_v3f16_vv: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: v_pk_max_f16 v4, v0, v2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x7e00 +; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], v0, v2 +; GFX9-GISEL-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, v5, v4, s[0:1] +; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v2, v5, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-GISEL-NEXT: v_pk_max_f16 v4, v1, v3 +; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, v1, v3 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc +; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v2, 16, v0 +; GFX9-GISEL-NEXT: ; return to shader part epilog +; ; GFX12-SDAG-LABEL: test_fmaximum_v3f16_vv: ; GFX12-SDAG: ; %bb.0: ; GFX12-SDAG-NEXT: v_pk_maximum_f16 v0, v0, v2 @@ -187,6 +462,49 @@ define amdgpu_ps <3 x half> @test_fmaximum_v3f16_vv(<3 x half> %a, <3 x half> %b } define amdgpu_ps <3 x half> @test_fmaximum_v3f16_ss(<3 x half> inreg %a, <3 x half> inreg %b) { +; GFX9-SDAG-LABEL: test_fmaximum_v3f16_ss: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s3 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-SDAG-NEXT: v_pk_max_f16 v1, s1, v1 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7e00 +; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, s1, v0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, s2 +; GFX9-SDAG-NEXT: s_lshr_b32 s1, s2, 16 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX9-SDAG-NEXT: v_pk_max_f16 v3, s0, v3 +; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, s0, v0 +; GFX9-SDAG-NEXT: s_lshr_b32 s0, s0, 16 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, s1 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc +; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, s0, v4 +; GFX9-SDAG-NEXT: v_cndmask_b32_sdwa v2, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-SDAG-NEXT: v_lshl_or_b32 v0, v2, 16, v0 +; GFX9-SDAG-NEXT: ; return to shader part epilog +; +; GFX9-GISEL-LABEL: test_fmaximum_v3f16_ss: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_lshr_b32 s5, s2, 16 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-GISEL-NEXT: s_lshr_b32 s4, s0, 16 +; GFX9-GISEL-NEXT: v_pk_max_f16 v1, s0, v0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s5 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7e00 +; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v0 +; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v1 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc +; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s4, v2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc +; GFX9-GISEL-NEXT: v_pk_max_f16 v3, s1, v1 +; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s1, v1 +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc +; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v2, 16, v0 +; GFX9-GISEL-NEXT: ; return to shader part epilog +; ; GFX12-SDAG-LABEL: test_fmaximum_v3f16_ss: ; GFX12-SDAG: ; %bb.0: ; GFX12-SDAG-NEXT: v_pk_maximum_f16 v0, s0, s2 @@ -206,97 +524,384 @@ define amdgpu_ps <3 x half> @test_fmaximum_v3f16_ss(<3 x half> inreg %a, <3 x ha } define amdgpu_ps <4 x half> @test_fmaximum_v4f16(<4 x half> %a, <4 x half> %b) { -; GCN-LABEL: test_fmaximum_v4f16: -; GCN: ; %bb.0: -; GCN-NEXT: v_pk_maximum_f16 v0, v0, v2 -; GCN-NEXT: v_pk_maximum_f16 v1, v1, v3 -; GCN-NEXT: ; return to shader part epilog +; GFX9-SDAG-LABEL: test_fmaximum_v4f16: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: v_pk_max_f16 v4, v1, v3 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v5, 0x7e00 +; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, v1, v3 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc +; GFX9-SDAG-NEXT: v_cmp_o_f16_sdwa vcc, v1, v3 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-SDAG-NEXT: v_cndmask_b32_sdwa v1, v5, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-SDAG-NEXT: v_pk_max_f16 v3, v0, v2 +; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v4, v5, v3, vcc +; GFX9-SDAG-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-SDAG-NEXT: v_cndmask_b32_sdwa v0, v5, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-SDAG-NEXT: s_mov_b32 s0, 0x5040100 +; GFX9-SDAG-NEXT: v_perm_b32 v0, v0, v4, s0 +; GFX9-SDAG-NEXT: v_perm_b32 v1, v1, v6, s0 +; GFX9-SDAG-NEXT: ; return to shader part epilog +; +; GFX9-GISEL-LABEL: test_fmaximum_v4f16: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: v_pk_max_f16 v4, v0, v2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x7e00 +; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, v0, v2 +; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v5, 16, v4 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc +; GFX9-GISEL-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v6, v5, vcc +; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v4 +; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v2 +; GFX9-GISEL-NEXT: v_pk_max_f16 v2, v1, v3 +; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], v1, v3 +; GFX9-GISEL-NEXT: v_cmp_o_f16_sdwa vcc, v1, v3 src0_sel:WORD_1 src1_sel:WORD_1 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, v6, v2, s[0:1] +; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v2, v6, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, v2, 16, v1 +; GFX9-GISEL-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_v4f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_pk_maximum_f16 v0, v0, v2 +; GFX12-NEXT: v_pk_maximum_f16 v1, v1, v3 +; GFX12-NEXT: ; return to shader part epilog %val = call <4 x half> @llvm.maximum.v4f16(<4 x half> %a, <4 x half> %b) ret <4 x half> %val } define amdgpu_ps <4 x half> @test_fmaximum_v4f16_ss(<4 x half> inreg %a, <4 x half> inreg %b) { -; GCN-LABEL: test_fmaximum_v4f16_ss: -; GCN: ; %bb.0: -; GCN-NEXT: v_pk_maximum_f16 v0, s0, s2 -; GCN-NEXT: v_pk_maximum_f16 v1, s1, s3 -; GCN-NEXT: ; return to shader part epilog +; GFX9-SDAG-LABEL: test_fmaximum_v4f16_ss: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s3 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-SDAG-NEXT: s_lshr_b32 s3, s3, 16 +; GFX9-SDAG-NEXT: v_pk_max_f16 v1, s1, v1 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7e00 +; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, s1, v0 +; GFX9-SDAG-NEXT: s_lshr_b32 s1, s1, 16 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s3 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v3, v2, v1, vcc +; GFX9-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, s1, v0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, s2 +; GFX9-SDAG-NEXT: s_lshr_b32 s1, s2, 16 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GFX9-SDAG-NEXT: v_pk_max_f16 v4, s0, v4 +; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, s0, v0 +; GFX9-SDAG-NEXT: s_lshr_b32 s0, s0, 16 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v5, s1 +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc +; GFX9-SDAG-NEXT: v_cmp_o_f16_e32 vcc, s0, v5 +; GFX9-SDAG-NEXT: v_cndmask_b32_sdwa v2, v2, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-SDAG-NEXT: v_lshl_or_b32 v0, v2, 16, v0 +; GFX9-SDAG-NEXT: v_and_b32_e32 v2, 0xffff, v3 +; GFX9-SDAG-NEXT: v_lshl_or_b32 v1, v1, 16, v2 +; GFX9-SDAG-NEXT: ; return to shader part epilog +; +; GFX9-GISEL-LABEL: test_fmaximum_v4f16_ss: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-GISEL-NEXT: s_lshr_b32 s2, s2, 16 +; GFX9-GISEL-NEXT: v_pk_max_f16 v1, s0, v0 +; GFX9-GISEL-NEXT: s_lshr_b32 s4, s0, 16 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7e00 +; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v0 +; GFX9-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v1 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc +; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s4, v2 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc +; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX9-GISEL-NEXT: s_lshr_b32 s2, s3, 16 +; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-GISEL-NEXT: s_lshr_b32 s0, s1, 16 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s2 +; GFX9-GISEL-NEXT: v_pk_max_f16 v2, s1, v1 +; GFX9-GISEL-NEXT: v_cmp_o_f16_e32 vcc, s0, v3 +; GFX9-GISEL-NEXT: v_cmp_o_f16_e64 s[0:1], s1, v1 +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, v4, v2, s[0:1] +; GFX9-GISEL-NEXT: v_cndmask_b32_sdwa v2, v4, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, v2, 16, v1 +; GFX9-GISEL-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_v4f16_ss: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_pk_maximum_f16 v0, s0, s2 +; GFX12-NEXT: v_pk_maximum_f16 v1, s1, s3 +; GFX12-NEXT: ; return to shader part epilog %val = call <4 x half> @llvm.maximum.v4f16(<4 x half> %a, <4 x half> %b) ret <4 x half> %val } define amdgpu_ps <2 x float> @test_fmaximum_f64_vv(double %a, double %b) { -; GCN-LABEL: test_fmaximum_f64_vv: -; GCN: ; %bb.0: -; GCN-NEXT: v_maximum_f64 v[0:1], v[0:1], v[2:3] -; GCN-NEXT: ; return to shader part epilog +; GFX9-SDAG-LABEL: test_fmaximum_f64_vv: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] +; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3] +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v4, 0, vcc +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GFX9-SDAG-NEXT: ; return to shader part epilog +; +; GFX9-GISEL-LABEL: test_fmaximum_f64_vv: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: v_max_f64 v[4:5], v[0:1], v[2:3] +; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[2:3] +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX9-GISEL-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_f64_vv: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[2:3] +; GFX12-NEXT: ; return to shader part epilog %val = call double @llvm.maximum.f64(double %a, double %b) %ret = bitcast double %val to <2 x float> ret <2 x float> %ret } define amdgpu_ps <2 x float> @test_fmaximum_f64_ss(double inreg %a, double inreg %b) { -; GCN-LABEL: test_fmaximum_f64_ss: -; GCN: ; %bb.0: -; GCN-NEXT: v_maximum_f64 v[0:1], s[0:1], s[2:3] -; GCN-NEXT: ; return to shader part epilog +; GFX9-SDAG-LABEL: test_fmaximum_f64_ss: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-SDAG-NEXT: v_max_f64 v[2:3], s[0:1], v[0:1] +; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, s[0:1], v[0:1] +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; GFX9-SDAG-NEXT: ; return to shader part epilog +; +; GFX9-GISEL-LABEL: test_fmaximum_f64_ss: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[0:1], v[0:1] +; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[0:1], v[0:1] +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x7ff80000 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX9-GISEL-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_f64_ss: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maximum_f64 v[0:1], s[0:1], s[2:3] +; GFX12-NEXT: ; return to shader part epilog %val = call double @llvm.maximum.f64(double %a, double %b) %ret = bitcast double %val to <2 x float> ret <2 x float> %ret } define amdgpu_ps <4 x float> @test_fmaximum_v2f64_ss(<2 x double> inreg %a, <2 x double> inreg %b) { -; GCN-LABEL: test_fmaximum_v2f64_ss: -; GCN: ; %bb.0: -; GCN-NEXT: v_maximum_f64 v[0:1], s[0:1], s[4:5] -; GCN-NEXT: v_maximum_f64 v[2:3], s[2:3], s[6:7] -; GCN-NEXT: ; return to shader part epilog +; GFX9-SDAG-LABEL: test_fmaximum_v2f64_ss: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-SDAG-NEXT: v_max_f64 v[2:3], s[0:1], v[0:1] +; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, s[0:1], v[0:1] +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s6 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s7 +; GFX9-SDAG-NEXT: v_max_f64 v[4:5], s[2:3], v[0:1] +; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[0:1], s[2:3], v[0:1] +; GFX9-SDAG-NEXT: v_mov_b32_e32 v6, 0x7ff80000 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v6, vcc +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[0:1] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, v5, v6, s[0:1] +; GFX9-SDAG-NEXT: ; return to shader part epilog +; +; GFX9-GISEL-LABEL: test_fmaximum_v2f64_ss: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[0:1], v[0:1] +; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[0:1], v[0:1] +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s6 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s7 +; GFX9-GISEL-NEXT: v_max_f64 v[4:5], s[2:3], v[0:1] +; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[0:1], s[2:3], v[0:1] +; GFX9-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff80000 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[0:1] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v6, v5, s[0:1] +; GFX9-GISEL-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_v2f64_ss: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maximum_f64 v[0:1], s[0:1], s[4:5] +; GFX12-NEXT: v_maximum_f64 v[2:3], s[2:3], s[6:7] +; GFX12-NEXT: ; return to shader part epilog %val = call <2 x double> @llvm.maximum.v2f64(<2 x double> %a, <2 x double> %b) %ret = bitcast <2 x double> %val to <4 x float> ret <4 x float> %ret } define amdgpu_ps <8 x float> @test_fmaximum_v4f64(<4 x double> %a, <4 x double> %b) { -; GCN-LABEL: test_fmaximum_v4f64: -; GCN: ; %bb.0: -; GCN-NEXT: v_maximum_f64 v[0:1], v[0:1], v[8:9] -; GCN-NEXT: v_maximum_f64 v[2:3], v[2:3], v[10:11] -; GCN-NEXT: v_maximum_f64 v[4:5], v[4:5], v[12:13] -; GCN-NEXT: v_maximum_f64 v[6:7], v[6:7], v[14:15] -; GCN-NEXT: ; return to shader part epilog +; GFX9-SDAG-LABEL: test_fmaximum_v4f64: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9] +; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[8:9] +; GFX9-SDAG-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11] +; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[0:1], v[2:3], v[10:11] +; GFX9-SDAG-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13] +; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[2:3], v[4:5], v[12:13] +; GFX9-SDAG-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15] +; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[4:5], v[6:7], v[14:15] +; GFX9-SDAG-NEXT: v_mov_b32_e32 v7, 0x7ff80000 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v16, 0, vcc +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v17, v7, vcc +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v8, 0, s[0:1] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[0:1] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v4, v10, 0, s[2:3] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v5, v11, v7, s[2:3] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v6, v12, 0, s[4:5] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v7, v13, v7, s[4:5] +; GFX9-SDAG-NEXT: ; return to shader part epilog +; +; GFX9-GISEL-LABEL: test_fmaximum_v4f64: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: v_max_f64 v[16:17], v[0:1], v[8:9] +; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, v[0:1], v[8:9] +; GFX9-GISEL-NEXT: v_max_f64 v[8:9], v[2:3], v[10:11] +; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[0:1], v[2:3], v[10:11] +; GFX9-GISEL-NEXT: v_max_f64 v[10:11], v[4:5], v[12:13] +; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[2:3], v[4:5], v[12:13] +; GFX9-GISEL-NEXT: v_max_f64 v[12:13], v[6:7], v[14:15] +; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[4:5], v[6:7], v[14:15] +; GFX9-GISEL-NEXT: v_mov_b32_e32 v18, 0x7ff80000 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v16, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v18, v17, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v8, s[0:1] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v18, v9, s[0:1] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v10, s[2:3] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v18, v11, s[2:3] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v12, s[4:5] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v7, v18, v13, s[4:5] +; GFX9-GISEL-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_v4f64: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maximum_f64 v[0:1], v[0:1], v[8:9] +; GFX12-NEXT: v_maximum_f64 v[2:3], v[2:3], v[10:11] +; GFX12-NEXT: v_maximum_f64 v[4:5], v[4:5], v[12:13] +; GFX12-NEXT: v_maximum_f64 v[6:7], v[6:7], v[14:15] +; GFX12-NEXT: ; return to shader part epilog %val = call <4 x double> @llvm.maximum.v4f64(<4 x double> %a, <4 x double> %b) %ret = bitcast <4 x double> %val to <8 x float> ret <8 x float> %ret } define amdgpu_ps <8 x float> @test_fmaximum_v4f64_ss(<4 x double> inreg %a, <4 x double> inreg %b) { -; GCN-LABEL: test_fmaximum_v4f64_ss: -; GCN: ; %bb.0: -; GCN-NEXT: v_maximum_f64 v[0:1], s[0:1], s[8:9] -; GCN-NEXT: v_maximum_f64 v[2:3], s[2:3], s[10:11] -; GCN-NEXT: v_maximum_f64 v[4:5], s[4:5], s[12:13] -; GCN-NEXT: v_maximum_f64 v[6:7], s[6:7], s[14:15] -; GCN-NEXT: ; return to shader part epilog +; GFX9-SDAG-LABEL: test_fmaximum_v4f64_ss: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s8 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s9 +; GFX9-SDAG-NEXT: v_max_f64 v[2:3], s[0:1], v[0:1] +; GFX9-SDAG-NEXT: v_cmp_u_f64_e32 vcc, s[0:1], v[0:1] +; GFX9-SDAG-NEXT: v_mov_b32_e32 v10, 0x7ff80000 +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s10 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s11 +; GFX9-SDAG-NEXT: v_max_f64 v[4:5], s[2:3], v[1:2] +; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[0:1], s[2:3], v[1:2] +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s12 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s13 +; GFX9-SDAG-NEXT: v_max_f64 v[6:7], s[4:5], v[1:2] +; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[2:3], s[4:5], v[1:2] +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s14 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s15 +; GFX9-SDAG-NEXT: v_max_f64 v[8:9], s[6:7], v[1:2] +; GFX9-SDAG-NEXT: v_cmp_u_f64_e64 s[4:5], s[6:7], v[1:2] +; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v10, vcc +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v2, v4, 0, s[0:1] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v3, v5, v10, s[0:1] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v4, v6, 0, s[2:3] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v5, v7, v10, s[2:3] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v6, v8, 0, s[4:5] +; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v7, v9, v10, s[4:5] +; GFX9-SDAG-NEXT: ; return to shader part epilog +; +; GFX9-GISEL-LABEL: test_fmaximum_v4f64_ss: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s8 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s9 +; GFX9-GISEL-NEXT: v_max_f64 v[2:3], s[0:1], v[0:1] +; GFX9-GISEL-NEXT: v_cmp_o_f64_e32 vcc, s[0:1], v[0:1] +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s10 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s11 +; GFX9-GISEL-NEXT: v_max_f64 v[4:5], s[2:3], v[0:1] +; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[0:1], s[2:3], v[0:1] +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s12 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s13 +; GFX9-GISEL-NEXT: v_max_f64 v[6:7], s[4:5], v[0:1] +; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[2:3], s[4:5], v[0:1] +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s14 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s15 +; GFX9-GISEL-NEXT: v_max_f64 v[8:9], s[6:7], v[0:1] +; GFX9-GISEL-NEXT: v_cmp_o_f64_e64 s[4:5], s[6:7], v[0:1] +; GFX9-GISEL-NEXT: v_mov_b32_e32 v10, 0x7ff80000 +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v1, v10, v3, vcc +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[0:1] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v3, v10, v5, s[0:1] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, v6, s[2:3] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v5, v10, v7, s[2:3] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, v8, s[4:5] +; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v7, v10, v9, s[4:5] +; GFX9-GISEL-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_v4f64_ss: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maximum_f64 v[0:1], s[0:1], s[8:9] +; GFX12-NEXT: v_maximum_f64 v[2:3], s[2:3], s[10:11] +; GFX12-NEXT: v_maximum_f64 v[4:5], s[4:5], s[12:13] +; GFX12-NEXT: v_maximum_f64 v[6:7], s[6:7], s[14:15] +; GFX12-NEXT: ; return to shader part epilog %val = call <4 x double> @llvm.maximum.v4f64(<4 x double> %a, <4 x double> %b) %ret = bitcast <4 x double> %val to <8 x float> ret <8 x float> %ret } define amdgpu_kernel void @fmaximumi_f32_move_to_valu(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) { -; GCN-LABEL: fmaximumi_f32_move_to_valu: -; GCN: ; %bb.0: -; GCN-NEXT: s_clause 0x1 -; GCN-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GCN-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 -; GCN-NEXT: v_mov_b32_e32 v0, 0 -; GCN-NEXT: s_wait_kmcnt 0x0 -; GCN-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS -; GCN-NEXT: s_wait_loadcnt 0x0 -; GCN-NEXT: global_load_b32 v2, v0, s[4:5] scope:SCOPE_SYS -; GCN-NEXT: s_wait_loadcnt 0x0 -; GCN-NEXT: v_maximum_f32 v1, v1, v2 -; GCN-NEXT: global_store_b32 v0, v1, s[0:1] -; GCN-NEXT: s_endpgm +; GFX9-LABEL: fmaximumi_f32_move_to_valu: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_dword v1, v0, s[2:3] glc +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: global_load_dword v2, v0, s[6:7] glc +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_max_f32_e32 v4, v1, v2 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v1, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX9-NEXT: global_store_dword v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; +; GFX12-LABEL: fmaximumi_f32_move_to_valu: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_clause 0x1 +; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 +; GFX12-NEXT: v_mov_b32_e32 v0, 0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: global_load_b32 v2, v0, s[4:5] scope:SCOPE_SYS +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: v_maximum_f32 v1, v1, v2 +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_endpgm %a = load volatile float, ptr addrspace(1) %aptr, align 4 %b = load volatile float, ptr addrspace(1) %bptr, align 4 %v = call float @llvm.maximum.f32(float %a, float %b) @@ -305,6 +910,23 @@ define amdgpu_kernel void @fmaximumi_f32_move_to_valu(ptr addrspace(1) %out, ptr } define amdgpu_kernel void @fmaximum_f16_move_to_valu(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) { +; GFX9-LABEL: fmaximum_f16_move_to_valu: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: v_mov_b32_e32 v3, 0x7e00 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] glc +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: global_load_ushort v2, v0, s[6:7] glc +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_max_f16_e32 v4, v1, v2 +; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc +; GFX9-NEXT: global_store_short v0, v1, s[0:1] +; GFX9-NEXT: s_endpgm +; ; GFX12-SDAG-TRUE16-LABEL: fmaximum_f16_move_to_valu: ; GFX12-SDAG-TRUE16: ; %bb.0: ; GFX12-SDAG-TRUE16-NEXT: s_clause 0x1 @@ -371,6 +993,40 @@ define amdgpu_kernel void @fmaximum_f16_move_to_valu(ptr addrspace(1) %out, ptr ret void } +define amdgpu_ps float @test_fmaximum_f32_ieee_on(float %a, float %b) #0 { +; GFX9-LABEL: test_fmaximum_f32_ieee_on: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_max_f32_e32 v2, v0, v1 +; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc +; GFX9-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_f32_ieee_on: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maximum_f32 v0, v0, v1 +; GFX12-NEXT: ; return to shader part epilog + %val = call float @llvm.maximum.f32(float %a, float %b) + ret float %val +} + +define amdgpu_ps float @test_fmaximum_f32_ieee_off(float %a, float %b) #1 { +; GFX9-LABEL: test_fmaximum_f32_ieee_off: +; GFX9: ; %bb.0: +; GFX9-NEXT: v_max_f32_e32 v2, v0, v1 +; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fc00000 +; GFX9-NEXT: v_cmp_o_f32_e32 vcc, v0, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc +; GFX9-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_fmaximum_f32_ieee_off: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maximum_f32 v0, v0, v1 +; GFX12-NEXT: ; return to shader part epilog + %val = call float @llvm.maximum.f32(float %a, float %b) + ret float %val +} + declare float @llvm.maximum.f32(float, float) declare <2 x float> @llvm.maximum.v2f32(<2 x float>, <2 x float>) declare <3 x float> @llvm.maximum.v3f32(<3 x float>, <3 x float>) @@ -383,3 +1039,6 @@ declare <4 x half> @llvm.maximum.v4f16(<4 x half>, <4 x half>) declare double @llvm.maximum.f64(double, double) declare <2 x double> @llvm.maximum.v2f64(<2 x double>, <2 x double>) declare <4 x double> @llvm.maximum.v4f64(<4 x double>, <4 x double>) + +attributes #0 = { nounwind "amdgpu-ieee"="true" } +attributes #1 = { nounwind "amdgpu-ieee"="false" } |