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-rw-r--r--llvm/test/CodeGen/AMDGPU/call-constexpr.ll343
1 files changed, 307 insertions, 36 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/call-constexpr.ll b/llvm/test/CodeGen/AMDGPU/call-constexpr.ll
index 5f324df..fe0b018 100644
--- a/llvm/test/CodeGen/AMDGPU/call-constexpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-constexpr.ll
@@ -1,84 +1,341 @@
-; RUN: llc -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefix=GCN %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefixes=GCN,GISEL %s
-; GCN-LABEL: {{^}}test_bitcast_return_type_noinline:
-; GCN: s_getpc_b64
-; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, ret_i32_noinline@rel32@lo+4
-; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ret_i32_noinline@rel32@hi+12
-; GCN: s_swappc_b64
define amdgpu_kernel void @test_bitcast_return_type_noinline() #0 {
+; SDAG-LABEL: test_bitcast_return_type_noinline:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: s_mov_b32 s32, 0
+; SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
+; SDAG-NEXT: s_add_i32 s12, s12, s17
+; SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; SDAG-NEXT: s_add_u32 s0, s0, s17
+; SDAG-NEXT: s_addc_u32 s1, s1, 0
+; SDAG-NEXT: s_mov_b32 s13, s15
+; SDAG-NEXT: s_mov_b32 s12, s14
+; SDAG-NEXT: s_getpc_b64 s[18:19]
+; SDAG-NEXT: s_add_u32 s18, s18, ret_i32_noinline@rel32@lo+4
+; SDAG-NEXT: s_addc_u32 s19, s19, ret_i32_noinline@rel32@hi+12
+; SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-NEXT: v_or_b32_e32 v31, v0, v2
+; SDAG-NEXT: s_mov_b32 s14, s16
+; SDAG-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; SDAG-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SDAG-NEXT: flat_store_dword v[0:1], v0
+; SDAG-NEXT: s_waitcnt vmcnt(0)
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: test_bitcast_return_type_noinline:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_mov_b32 s32, 0
+; GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GISEL-NEXT: s_add_i32 s12, s12, s17
+; GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GISEL-NEXT: s_add_u32 s0, s0, s17
+; GISEL-NEXT: s_addc_u32 s1, s1, 0
+; GISEL-NEXT: s_mov_b32 s13, s15
+; GISEL-NEXT: s_mov_b32 s12, s14
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GISEL-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-NEXT: v_or_b32_e32 v31, v0, v2
+; GISEL-NEXT: s_getpc_b64 s[18:19]
+; GISEL-NEXT: s_add_u32 s18, s18, ret_i32_noinline@rel32@lo+4
+; GISEL-NEXT: s_addc_u32 s19, s19, ret_i32_noinline@rel32@hi+12
+; GISEL-NEXT: s_mov_b32 s14, s16
+; GISEL-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; GISEL-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GISEL-NEXT: flat_store_dword v[0:1], v0
+; GISEL-NEXT: s_waitcnt vmcnt(0)
+; GISEL-NEXT: s_endpgm
%val = call float @ret_i32_noinline()
%op = fadd float %val, 1.0
store volatile float %op, ptr addrspace(1) poison
ret void
}
-; GCN-LABEL: {{^}}test_bitcast_return_type_alwaysinline:
-; GCN: s_swappc_b64
define amdgpu_kernel void @test_bitcast_return_type_alwaysinline() #0 {
+; SDAG-LABEL: test_bitcast_return_type_alwaysinline:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: s_mov_b32 s32, 0
+; SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
+; SDAG-NEXT: s_add_i32 s12, s12, s17
+; SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; SDAG-NEXT: s_add_u32 s0, s0, s17
+; SDAG-NEXT: s_addc_u32 s1, s1, 0
+; SDAG-NEXT: s_mov_b32 s13, s15
+; SDAG-NEXT: s_mov_b32 s12, s14
+; SDAG-NEXT: s_getpc_b64 s[18:19]
+; SDAG-NEXT: s_add_u32 s18, s18, ret_i32_alwaysinline@rel32@lo+4
+; SDAG-NEXT: s_addc_u32 s19, s19, ret_i32_alwaysinline@rel32@hi+12
+; SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-NEXT: v_or_b32_e32 v31, v0, v2
+; SDAG-NEXT: s_mov_b32 s14, s16
+; SDAG-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; SDAG-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SDAG-NEXT: flat_store_dword v[0:1], v0
+; SDAG-NEXT: s_waitcnt vmcnt(0)
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: test_bitcast_return_type_alwaysinline:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_mov_b32 s32, 0
+; GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GISEL-NEXT: s_add_i32 s12, s12, s17
+; GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GISEL-NEXT: s_add_u32 s0, s0, s17
+; GISEL-NEXT: s_addc_u32 s1, s1, 0
+; GISEL-NEXT: s_mov_b32 s13, s15
+; GISEL-NEXT: s_mov_b32 s12, s14
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GISEL-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-NEXT: v_or_b32_e32 v31, v0, v2
+; GISEL-NEXT: s_getpc_b64 s[18:19]
+; GISEL-NEXT: s_add_u32 s18, s18, ret_i32_alwaysinline@rel32@lo+4
+; GISEL-NEXT: s_addc_u32 s19, s19, ret_i32_alwaysinline@rel32@hi+12
+; GISEL-NEXT: s_mov_b32 s14, s16
+; GISEL-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; GISEL-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GISEL-NEXT: flat_store_dword v[0:1], v0
+; GISEL-NEXT: s_waitcnt vmcnt(0)
+; GISEL-NEXT: s_endpgm
%val = call float @ret_i32_alwaysinline()
%op = fadd float %val, 1.0
store volatile float %op, ptr addrspace(1) poison
ret void
}
-; GCN-LABEL: {{^}}test_bitcast_argument_type:
-; GCN: s_getpc_b64
-; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32@rel32@lo+4
-; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32@rel32@hi+12
-; GCN: s_swappc_b64
define amdgpu_kernel void @test_bitcast_argument_type() #0 {
+; SDAG-LABEL: test_bitcast_argument_type:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: s_mov_b32 s32, 0
+; SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
+; SDAG-NEXT: s_add_i32 s12, s12, s17
+; SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; SDAG-NEXT: s_add_u32 s0, s0, s17
+; SDAG-NEXT: s_addc_u32 s1, s1, 0
+; SDAG-NEXT: s_mov_b32 s13, s15
+; SDAG-NEXT: s_mov_b32 s12, s14
+; SDAG-NEXT: s_getpc_b64 s[18:19]
+; SDAG-NEXT: s_add_u32 s18, s18, ident_i32@rel32@lo+4
+; SDAG-NEXT: s_addc_u32 s19, s19, ident_i32@rel32@hi+12
+; SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-NEXT: v_or_b32_e32 v31, v0, v2
+; SDAG-NEXT: v_mov_b32_e32 v0, 2.0
+; SDAG-NEXT: s_mov_b32 s14, s16
+; SDAG-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; SDAG-NEXT: v_add_i32_e32 v0, vcc, 1, v0
+; SDAG-NEXT: flat_store_dword v[0:1], v0
+; SDAG-NEXT: s_waitcnt vmcnt(0)
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: test_bitcast_argument_type:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_mov_b32 s32, 0
+; GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GISEL-NEXT: s_add_i32 s12, s12, s17
+; GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GISEL-NEXT: s_add_u32 s0, s0, s17
+; GISEL-NEXT: s_addc_u32 s1, s1, 0
+; GISEL-NEXT: s_mov_b32 s13, s15
+; GISEL-NEXT: s_mov_b32 s12, s14
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GISEL-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; GISEL-NEXT: s_getpc_b64 s[18:19]
+; GISEL-NEXT: s_add_u32 s18, s18, ident_i32@rel32@lo+4
+; GISEL-NEXT: s_addc_u32 s19, s19, ident_i32@rel32@hi+12
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-NEXT: v_or_b32_e32 v31, v0, v2
+; GISEL-NEXT: v_mov_b32_e32 v0, 2.0
+; GISEL-NEXT: s_mov_b32 s14, s16
+; GISEL-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; GISEL-NEXT: v_add_i32_e32 v0, vcc, 1, v0
+; GISEL-NEXT: flat_store_dword v[0:1], v0
+; GISEL-NEXT: s_waitcnt vmcnt(0)
+; GISEL-NEXT: s_endpgm
%val = call i32 @ident_i32(float 2.0)
%op = add i32 %val, 1
store volatile i32 %op, ptr addrspace(1) poison
ret void
}
-; GCN-LABEL: {{^}}test_bitcast_argument_and_return_types:
-; GCN: s_getpc_b64
-; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32@rel32@lo+4
-; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32@rel32@hi+12
-; GCN: s_swappc_b64
define amdgpu_kernel void @test_bitcast_argument_and_return_types() #0 {
+; SDAG-LABEL: test_bitcast_argument_and_return_types:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: s_mov_b32 s32, 0
+; SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
+; SDAG-NEXT: s_add_i32 s12, s12, s17
+; SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; SDAG-NEXT: s_add_u32 s0, s0, s17
+; SDAG-NEXT: s_addc_u32 s1, s1, 0
+; SDAG-NEXT: s_mov_b32 s13, s15
+; SDAG-NEXT: s_mov_b32 s12, s14
+; SDAG-NEXT: s_getpc_b64 s[18:19]
+; SDAG-NEXT: s_add_u32 s18, s18, ident_i32@rel32@lo+4
+; SDAG-NEXT: s_addc_u32 s19, s19, ident_i32@rel32@hi+12
+; SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-NEXT: v_or_b32_e32 v31, v0, v2
+; SDAG-NEXT: v_mov_b32_e32 v0, 2.0
+; SDAG-NEXT: s_mov_b32 s14, s16
+; SDAG-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; SDAG-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SDAG-NEXT: flat_store_dword v[0:1], v0
+; SDAG-NEXT: s_waitcnt vmcnt(0)
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: test_bitcast_argument_and_return_types:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_mov_b32 s32, 0
+; GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GISEL-NEXT: s_add_i32 s12, s12, s17
+; GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GISEL-NEXT: s_add_u32 s0, s0, s17
+; GISEL-NEXT: s_addc_u32 s1, s1, 0
+; GISEL-NEXT: s_mov_b32 s13, s15
+; GISEL-NEXT: s_mov_b32 s12, s14
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GISEL-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; GISEL-NEXT: s_getpc_b64 s[18:19]
+; GISEL-NEXT: s_add_u32 s18, s18, ident_i32@rel32@lo+4
+; GISEL-NEXT: s_addc_u32 s19, s19, ident_i32@rel32@hi+12
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-NEXT: v_or_b32_e32 v31, v0, v2
+; GISEL-NEXT: v_mov_b32_e32 v0, 2.0
+; GISEL-NEXT: s_mov_b32 s14, s16
+; GISEL-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; GISEL-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GISEL-NEXT: flat_store_dword v[0:1], v0
+; GISEL-NEXT: s_waitcnt vmcnt(0)
+; GISEL-NEXT: s_endpgm
%val = call float @ident_i32(float 2.0)
%op = fadd float %val, 1.0
store volatile float %op, ptr addrspace(1) poison
ret void
}
-; GCN-LABEL: {{^}}use_workitem_id_x:
-; GCN: s_waitcnt
-; GCN-NEXT: v_and_b32_e32 [[TMP:v[0-9]+]], 0x3ff, v31
-; GCN-NEXT: v_add_i32_e32 v0, vcc, [[TMP]], v0
-; GCN-NEXT: s_setpc_b64
define hidden i32 @use_workitem_id_x(i32 %arg0) #3 {
+; GCN-LABEL: use_workitem_id_x:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_and_b32_e32 v1, 0x3ff, v31
+; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
%id = call i32 @llvm.amdgcn.workitem.id.x()
%op = add i32 %id, %arg0
ret i32 %op
}
-; GCN-LABEL: {{^}}test_bitcast_use_workitem_id_x:
-; GCN: v_mov_b32_e32 v31, v0
-; GCN: s_getpc_b64
-; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, use_workitem_id_x@rel32@lo+4
-; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, use_workitem_id_x@rel32@hi+12
-; GCN: v_mov_b32_e32 v0, 9
-; GCN: s_swappc_b64
-; GCN: v_add_f32_e32
define amdgpu_kernel void @test_bitcast_use_workitem_id_x() #3 {
+; SDAG-LABEL: test_bitcast_use_workitem_id_x:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: s_mov_b32 s32, 0
+; SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
+; SDAG-NEXT: s_add_i32 s12, s12, s17
+; SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; SDAG-NEXT: s_add_u32 s0, s0, s17
+; SDAG-NEXT: s_addc_u32 s1, s1, 0
+; SDAG-NEXT: s_mov_b32 s13, s15
+; SDAG-NEXT: s_mov_b32 s12, s14
+; SDAG-NEXT: v_mov_b32_e32 v31, v0
+; SDAG-NEXT: s_getpc_b64 s[18:19]
+; SDAG-NEXT: s_add_u32 s18, s18, use_workitem_id_x@rel32@lo+4
+; SDAG-NEXT: s_addc_u32 s19, s19, use_workitem_id_x@rel32@hi+12
+; SDAG-NEXT: v_mov_b32_e32 v0, 9
+; SDAG-NEXT: s_mov_b32 s14, s16
+; SDAG-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; SDAG-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SDAG-NEXT: flat_store_dword v[0:1], v0
+; SDAG-NEXT: s_waitcnt vmcnt(0)
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: test_bitcast_use_workitem_id_x:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_mov_b32 s32, 0
+; GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GISEL-NEXT: s_add_i32 s12, s12, s17
+; GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GISEL-NEXT: s_add_u32 s0, s0, s17
+; GISEL-NEXT: s_addc_u32 s1, s1, 0
+; GISEL-NEXT: v_mov_b32_e32 v31, v0
+; GISEL-NEXT: s_mov_b32 s13, s15
+; GISEL-NEXT: s_mov_b32 s12, s14
+; GISEL-NEXT: s_getpc_b64 s[18:19]
+; GISEL-NEXT: s_add_u32 s18, s18, use_workitem_id_x@rel32@lo+4
+; GISEL-NEXT: s_addc_u32 s19, s19, use_workitem_id_x@rel32@hi+12
+; GISEL-NEXT: v_mov_b32_e32 v0, 9
+; GISEL-NEXT: s_mov_b32 s14, s16
+; GISEL-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; GISEL-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GISEL-NEXT: flat_store_dword v[0:1], v0
+; GISEL-NEXT: s_waitcnt vmcnt(0)
+; GISEL-NEXT: s_endpgm
%val = call float @use_workitem_id_x(i32 9)
%op = fadd float %val, 1.0
store volatile float %op, ptr addrspace(1) poison
ret void
}
-; GCN-LABEL: {{^}}test_invoke:
-; GCN: s_getpc_b64
-; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32@rel32@lo+4
-; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32@rel32@hi+12
-; GCN: s_swappc_b64
@_ZTIi = external global ptr
declare i32 @__gxx_personality_v0(...)
define amdgpu_kernel void @test_invoke() #0 personality ptr @__gxx_personality_v0 {
+; SDAG-LABEL: test_invoke:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: s_mov_b32 s32, 0
+; SDAG-NEXT: s_mov_b32 flat_scratch_lo, s13
+; SDAG-NEXT: s_add_i32 s12, s12, s17
+; SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; SDAG-NEXT: s_add_u32 s0, s0, s17
+; SDAG-NEXT: s_addc_u32 s1, s1, 0
+; SDAG-NEXT: s_mov_b32 s13, s15
+; SDAG-NEXT: s_mov_b32 s12, s14
+; SDAG-NEXT: s_getpc_b64 s[18:19]
+; SDAG-NEXT: s_add_u32 s18, s18, ident_i32@rel32@lo+4
+; SDAG-NEXT: s_addc_u32 s19, s19, ident_i32@rel32@hi+12
+; SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; SDAG-NEXT: v_or_b32_e32 v31, v0, v2
+; SDAG-NEXT: v_mov_b32_e32 v0, 2.0
+; SDAG-NEXT: s_mov_b32 s14, s16
+; SDAG-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; SDAG-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SDAG-NEXT: flat_store_dword v[0:1], v0
+; SDAG-NEXT: s_waitcnt vmcnt(0)
+; SDAG-NEXT: s_endpgm
+;
+; GISEL-LABEL: test_invoke:
+; GISEL: ; %bb.0:
+; GISEL-NEXT: s_mov_b32 s32, 0
+; GISEL-NEXT: s_mov_b32 flat_scratch_lo, s13
+; GISEL-NEXT: s_add_i32 s12, s12, s17
+; GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
+; GISEL-NEXT: s_add_u32 s0, s0, s17
+; GISEL-NEXT: s_addc_u32 s1, s1, 0
+; GISEL-NEXT: s_mov_b32 s13, s15
+; GISEL-NEXT: s_mov_b32 s12, s14
+; GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GISEL-NEXT: v_lshlrev_b32_e32 v2, 20, v2
+; GISEL-NEXT: s_getpc_b64 s[18:19]
+; GISEL-NEXT: s_add_u32 s18, s18, ident_i32@rel32@lo+4
+; GISEL-NEXT: s_addc_u32 s19, s19, ident_i32@rel32@hi+12
+; GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GISEL-NEXT: v_or_b32_e32 v31, v0, v2
+; GISEL-NEXT: v_mov_b32_e32 v0, 2.0
+; GISEL-NEXT: s_mov_b32 s14, s16
+; GISEL-NEXT: s_swappc_b64 s[30:31], s[18:19]
+; GISEL-NEXT: v_add_f32_e32 v0, 1.0, v0
+; GISEL-NEXT: flat_store_dword v[0:1], v0
+; GISEL-NEXT: s_waitcnt vmcnt(0)
+; GISEL-NEXT: s_endpgm
%val = invoke float @ident_i32(float 2.0)
to label %continue unwind label %broken
@@ -96,14 +353,28 @@ continue:
; arguments before we lower any calls to them.
define hidden i32 @ret_i32_noinline() #0 {
+; GCN-LABEL: ret_i32_noinline:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, 4
+; GCN-NEXT: s_setpc_b64 s[30:31]
ret i32 4
}
define hidden i32 @ret_i32_alwaysinline() #1 {
+; GCN-LABEL: ret_i32_alwaysinline:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, 4
+; GCN-NEXT: s_setpc_b64 s[30:31]
ret i32 4
}
define hidden i32 @ident_i32(i32 %i) #0 {
+; GCN-LABEL: ident_i32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
ret i32 %i
}
generated by cgit v1.1 at 2025-11-08 09:42:46 +0000