diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll | 10634 |
1 files changed, 4910 insertions, 5724 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll index 93c11f1..4372f11 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll @@ -3848,30 +3848,58 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v18, s30, 0 -; SI-NEXT: v_writelane_b32 v18, s31, 1 -; SI-NEXT: v_writelane_b32 v18, s34, 2 -; SI-NEXT: v_writelane_b32 v18, s35, 3 -; SI-NEXT: v_writelane_b32 v18, s36, 4 -; SI-NEXT: v_writelane_b32 v18, s37, 5 -; SI-NEXT: v_writelane_b32 v18, s38, 6 -; SI-NEXT: v_writelane_b32 v18, s39, 7 -; SI-NEXT: v_writelane_b32 v18, s48, 8 -; SI-NEXT: v_writelane_b32 v18, s49, 9 -; SI-NEXT: v_writelane_b32 v18, s50, 10 -; SI-NEXT: v_writelane_b32 v18, s51, 11 -; SI-NEXT: v_writelane_b32 v18, s52, 12 -; SI-NEXT: v_writelane_b32 v18, s53, 13 -; SI-NEXT: v_writelane_b32 v18, s54, 14 +; SI-NEXT: v_writelane_b32 v20, s30, 0 +; SI-NEXT: v_writelane_b32 v20, s31, 1 +; SI-NEXT: v_writelane_b32 v20, s34, 2 +; SI-NEXT: v_writelane_b32 v20, s35, 3 +; SI-NEXT: v_writelane_b32 v20, s36, 4 +; SI-NEXT: v_writelane_b32 v20, s37, 5 +; SI-NEXT: v_writelane_b32 v20, s38, 6 +; SI-NEXT: v_writelane_b32 v20, s39, 7 +; SI-NEXT: v_writelane_b32 v20, s48, 8 +; SI-NEXT: v_mov_b32_e32 v18, s16 +; SI-NEXT: v_mov_b32_e32 v19, s17 +; SI-NEXT: v_writelane_b32 v20, s49, 9 +; SI-NEXT: v_readfirstlane_b32 s46, v18 +; SI-NEXT: v_mov_b32_e32 v18, s18 +; SI-NEXT: v_readfirstlane_b32 s47, v19 +; SI-NEXT: v_mov_b32_e32 v19, s19 +; SI-NEXT: v_writelane_b32 v20, s50, 10 +; SI-NEXT: v_readfirstlane_b32 s44, v18 +; SI-NEXT: v_mov_b32_e32 v18, s20 +; SI-NEXT: v_readfirstlane_b32 s45, v19 +; SI-NEXT: v_mov_b32_e32 v19, s21 +; SI-NEXT: v_writelane_b32 v20, s51, 11 +; SI-NEXT: v_readfirstlane_b32 s42, v18 +; SI-NEXT: v_mov_b32_e32 v18, s22 +; SI-NEXT: v_readfirstlane_b32 s43, v19 +; SI-NEXT: v_mov_b32_e32 v19, s23 +; SI-NEXT: v_writelane_b32 v20, s52, 12 +; SI-NEXT: v_readfirstlane_b32 s40, v18 +; SI-NEXT: v_mov_b32_e32 v18, s24 +; SI-NEXT: v_readfirstlane_b32 s41, v19 +; SI-NEXT: v_mov_b32_e32 v19, s25 +; SI-NEXT: v_writelane_b32 v20, s53, 13 +; SI-NEXT: v_readfirstlane_b32 s24, v18 +; SI-NEXT: v_mov_b32_e32 v18, s26 +; SI-NEXT: v_readfirstlane_b32 s25, v19 +; SI-NEXT: v_mov_b32_e32 v19, s27 +; SI-NEXT: v_writelane_b32 v20, s54, 14 +; SI-NEXT: v_readfirstlane_b32 s22, v18 +; SI-NEXT: v_mov_b32_e32 v18, s28 +; SI-NEXT: v_readfirstlane_b32 s23, v19 +; SI-NEXT: v_mov_b32_e32 v19, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; SI-NEXT: v_writelane_b32 v18, s55, 15 -; SI-NEXT: v_readfirstlane_b32 s42, v1 -; SI-NEXT: v_readfirstlane_b32 s43, v2 -; SI-NEXT: v_readfirstlane_b32 s40, v3 -; SI-NEXT: v_readfirstlane_b32 s41, v4 +; SI-NEXT: v_writelane_b32 v20, s55, 15 +; SI-NEXT: v_readfirstlane_b32 s20, v18 +; SI-NEXT: v_readfirstlane_b32 s21, v19 +; SI-NEXT: v_readfirstlane_b32 s18, v1 +; SI-NEXT: v_readfirstlane_b32 s19, v2 +; SI-NEXT: v_readfirstlane_b32 s16, v3 +; SI-NEXT: v_readfirstlane_b32 s17, v4 ; SI-NEXT: v_readfirstlane_b32 s14, v5 ; SI-NEXT: v_readfirstlane_b32 s15, v6 ; SI-NEXT: v_readfirstlane_b32 s12, v7 @@ -3883,9 +3911,9 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s6, v13 ; SI-NEXT: v_readfirstlane_b32 s7, v14 ; SI-NEXT: v_readfirstlane_b32 s4, v15 -; SI-NEXT: s_and_b64 s[44:45], vcc, exec +; SI-NEXT: s_and_b64 s[26:27], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v16 -; SI-NEXT: v_writelane_b32 v18, s64, 16 +; SI-NEXT: v_writelane_b32 v20, s64, 16 ; SI-NEXT: s_cbranch_scc0 .LBB13_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s34, s5, 16 @@ -3894,50 +3922,50 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; SI-NEXT: s_lshr_b32 s37, s11, 16 ; SI-NEXT: s_lshr_b32 s38, s13, 16 ; SI-NEXT: s_lshr_b32 s39, s15, 16 -; SI-NEXT: s_lshr_b32 s48, s41, 16 -; SI-NEXT: s_lshr_b32 s49, s43, 16 -; SI-NEXT: s_lshr_b32 s50, s29, 16 -; SI-NEXT: s_lshr_b32 s51, s27, 16 +; SI-NEXT: s_lshr_b32 s48, s17, 16 +; SI-NEXT: s_lshr_b32 s49, s19, 16 +; SI-NEXT: s_lshr_b32 s50, s21, 16 +; SI-NEXT: s_lshr_b32 s51, s23, 16 ; SI-NEXT: s_lshr_b32 s52, s25, 16 -; SI-NEXT: s_lshr_b32 s53, s23, 16 -; SI-NEXT: s_lshr_b32 s54, s21, 16 -; SI-NEXT: s_lshr_b32 s55, s19, 16 -; SI-NEXT: s_lshr_b32 s64, s17, 16 -; SI-NEXT: s_lshr_b64 s[44:45], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 16 +; SI-NEXT: s_lshr_b32 s53, s41, 16 +; SI-NEXT: s_lshr_b32 s54, s43, 16 +; SI-NEXT: s_lshr_b32 s55, s45, 16 +; SI-NEXT: s_lshr_b32 s64, s47, 16 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[6:7], 16 ; SI-NEXT: s_lshr_b64 s[56:57], s[8:9], 16 ; SI-NEXT: s_lshr_b64 s[58:59], s[10:11], 16 ; SI-NEXT: s_lshr_b64 s[60:61], s[12:13], 16 ; SI-NEXT: s_lshr_b64 s[62:63], s[14:15], 16 -; SI-NEXT: s_lshr_b64 s[72:73], s[40:41], 16 -; SI-NEXT: s_lshr_b64 s[74:75], s[42:43], 16 -; SI-NEXT: s_lshr_b64 s[76:77], s[28:29], 16 -; SI-NEXT: s_lshr_b64 s[78:79], s[26:27], 16 +; SI-NEXT: s_lshr_b64 s[72:73], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[74:75], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[76:77], s[20:21], 16 +; SI-NEXT: s_lshr_b64 s[78:79], s[22:23], 16 ; SI-NEXT: s_lshr_b64 s[88:89], s[24:25], 16 -; SI-NEXT: s_lshr_b64 s[90:91], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[92:93], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[94:95], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[30:31], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[90:91], s[40:41], 16 +; SI-NEXT: s_lshr_b64 s[92:93], s[42:43], 16 +; SI-NEXT: s_lshr_b64 s[94:95], s[44:45], 16 +; SI-NEXT: s_lshr_b64 s[30:31], s[46:47], 16 ; SI-NEXT: s_cbranch_execnz .LBB13_3 ; SI-NEXT: .LBB13_2: ; %cmp.true -; SI-NEXT: s_add_i32 s17, s17, 3 -; SI-NEXT: s_add_i32 s16, s16, 3 -; SI-NEXT: s_add_i32 s19, s19, 3 -; SI-NEXT: s_add_i32 s18, s18, 3 -; SI-NEXT: s_add_i32 s21, s21, 3 -; SI-NEXT: s_add_i32 s20, s20, 3 -; SI-NEXT: s_add_i32 s23, s23, 3 -; SI-NEXT: s_add_i32 s22, s22, 3 -; SI-NEXT: s_add_i32 s25, s25, 3 -; SI-NEXT: s_add_i32 s24, s24, 3 -; SI-NEXT: s_add_i32 s27, s27, 3 -; SI-NEXT: s_add_i32 s26, s26, 3 -; SI-NEXT: s_add_i32 s29, s29, 3 -; SI-NEXT: s_add_i32 s28, s28, 3 +; SI-NEXT: s_add_i32 s47, s47, 3 +; SI-NEXT: s_add_i32 s46, s46, 3 +; SI-NEXT: s_add_i32 s45, s45, 3 +; SI-NEXT: s_add_i32 s44, s44, 3 ; SI-NEXT: s_add_i32 s43, s43, 3 ; SI-NEXT: s_add_i32 s42, s42, 3 ; SI-NEXT: s_add_i32 s41, s41, 3 ; SI-NEXT: s_add_i32 s40, s40, 3 +; SI-NEXT: s_add_i32 s25, s25, 3 +; SI-NEXT: s_add_i32 s24, s24, 3 +; SI-NEXT: s_add_i32 s23, s23, 3 +; SI-NEXT: s_add_i32 s22, s22, 3 +; SI-NEXT: s_add_i32 s21, s21, 3 +; SI-NEXT: s_add_i32 s20, s20, 3 +; SI-NEXT: s_add_i32 s19, s19, 3 +; SI-NEXT: s_add_i32 s18, s18, 3 +; SI-NEXT: s_add_i32 s17, s17, 3 +; SI-NEXT: s_add_i32 s16, s16, 3 ; SI-NEXT: s_add_i32 s15, s15, 3 ; SI-NEXT: s_add_i32 s14, s14, 3 ; SI-NEXT: s_add_i32 s13, s13, 3 @@ -3950,149 +3978,149 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; SI-NEXT: s_add_i32 s6, s6, 3 ; SI-NEXT: s_add_i32 s5, s5, 3 ; SI-NEXT: s_add_i32 s4, s4, 3 -; SI-NEXT: s_lshr_b64 s[44:45], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 16 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[6:7], 16 ; SI-NEXT: s_lshr_b64 s[56:57], s[8:9], 16 ; SI-NEXT: s_lshr_b64 s[58:59], s[10:11], 16 ; SI-NEXT: s_lshr_b64 s[60:61], s[12:13], 16 ; SI-NEXT: s_lshr_b64 s[62:63], s[14:15], 16 -; SI-NEXT: s_lshr_b64 s[72:73], s[40:41], 16 -; SI-NEXT: s_lshr_b64 s[74:75], s[42:43], 16 +; SI-NEXT: s_lshr_b64 s[72:73], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[74:75], s[18:19], 16 ; SI-NEXT: s_lshr_b32 s34, s5, 16 ; SI-NEXT: s_lshr_b32 s35, s7, 16 ; SI-NEXT: s_lshr_b32 s36, s9, 16 ; SI-NEXT: s_lshr_b32 s37, s11, 16 ; SI-NEXT: s_lshr_b32 s38, s13, 16 ; SI-NEXT: s_lshr_b32 s39, s15, 16 -; SI-NEXT: s_lshr_b32 s48, s41, 16 -; SI-NEXT: s_lshr_b32 s49, s43, 16 -; SI-NEXT: s_lshr_b32 s50, s29, 16 -; SI-NEXT: s_lshr_b32 s51, s27, 16 +; SI-NEXT: s_lshr_b32 s48, s17, 16 +; SI-NEXT: s_lshr_b32 s49, s19, 16 +; SI-NEXT: s_lshr_b32 s50, s21, 16 +; SI-NEXT: s_lshr_b32 s51, s23, 16 ; SI-NEXT: s_lshr_b32 s52, s25, 16 -; SI-NEXT: s_lshr_b32 s53, s23, 16 -; SI-NEXT: s_lshr_b32 s54, s21, 16 -; SI-NEXT: s_lshr_b32 s55, s19, 16 -; SI-NEXT: s_lshr_b32 s64, s17, 16 -; SI-NEXT: s_lshr_b64 s[76:77], s[28:29], 16 -; SI-NEXT: s_lshr_b64 s[78:79], s[26:27], 16 +; SI-NEXT: s_lshr_b32 s53, s41, 16 +; SI-NEXT: s_lshr_b32 s54, s43, 16 +; SI-NEXT: s_lshr_b32 s55, s45, 16 +; SI-NEXT: s_lshr_b32 s64, s47, 16 +; SI-NEXT: s_lshr_b64 s[76:77], s[20:21], 16 +; SI-NEXT: s_lshr_b64 s[78:79], s[22:23], 16 ; SI-NEXT: s_lshr_b64 s[88:89], s[24:25], 16 -; SI-NEXT: s_lshr_b64 s[90:91], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[92:93], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[94:95], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[30:31], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[90:91], s[40:41], 16 +; SI-NEXT: s_lshr_b64 s[92:93], s[42:43], 16 +; SI-NEXT: s_lshr_b64 s[94:95], s[44:45], 16 +; SI-NEXT: s_lshr_b64 s[30:31], s[46:47], 16 ; SI-NEXT: .LBB13_3: ; %end -; SI-NEXT: s_lshl_b32 s45, s30, 16 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s45 -; SI-NEXT: v_mov_b32_e32 v1, s16 -; SI-NEXT: s_and_b32 s16, s17, 0xffff -; SI-NEXT: s_lshl_b32 s17, s64, 16 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_lshl_b32 s16, s94, 16 -; SI-NEXT: s_and_b32 s17, s18, 0xffff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: v_mov_b32_e32 v3, s16 -; SI-NEXT: s_and_b32 s16, s19, 0xffff -; SI-NEXT: s_lshl_b32 s17, s55, 16 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v4, s16 -; SI-NEXT: s_lshl_b32 s16, s92, 16 -; SI-NEXT: s_and_b32 s17, s20, 0xffff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: v_mov_b32_e32 v5, s16 -; SI-NEXT: s_and_b32 s16, s21, 0xffff -; SI-NEXT: s_lshl_b32 s17, s54, 16 +; SI-NEXT: s_lshl_b32 s27, s30, 16 +; SI-NEXT: s_and_b32 s29, s46, 0xffff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: v_mov_b32_e32 v1, s27 +; SI-NEXT: s_and_b32 s27, s47, 0xffff +; SI-NEXT: s_lshl_b32 s29, s64, 16 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_lshl_b32 s27, s94, 16 +; SI-NEXT: s_and_b32 s29, s44, 0xffff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: v_mov_b32_e32 v3, s27 +; SI-NEXT: s_and_b32 s27, s45, 0xffff +; SI-NEXT: s_lshl_b32 s29, s55, 16 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v4, s27 +; SI-NEXT: s_lshl_b32 s27, s92, 16 +; SI-NEXT: s_and_b32 s29, s42, 0xffff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: v_mov_b32_e32 v5, s27 +; SI-NEXT: s_and_b32 s27, s43, 0xffff +; SI-NEXT: s_lshl_b32 s29, s54, 16 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s27, s27, s29 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0 -; SI-NEXT: v_mov_b32_e32 v6, s16 +; SI-NEXT: v_mov_b32_e32 v6, s27 ; SI-NEXT: buffer_store_dword v3, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 12, v0 -; SI-NEXT: s_lshl_b32 s16, s90, 16 -; SI-NEXT: s_and_b32 s17, s22, 0xffff +; SI-NEXT: s_lshl_b32 s27, s90, 16 +; SI-NEXT: s_and_b32 s29, s40, 0xffff ; SI-NEXT: buffer_store_dword v4, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0 -; SI-NEXT: s_or_b32 s16, s17, s16 +; SI-NEXT: s_or_b32 s27, s29, s27 ; SI-NEXT: buffer_store_dword v5, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 20, v0 ; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s23, 0xffff -; SI-NEXT: s_lshl_b32 s17, s53, 16 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_and_b32 s27, s41, 0xffff +; SI-NEXT: s_lshl_b32 s29, s53, 16 ; SI-NEXT: buffer_store_dword v6, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s27, s27, s29 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s24, 0xffff -; SI-NEXT: s_lshl_b32 s17, s88, 16 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_and_b32 s24, s24, 0xffff +; SI-NEXT: s_lshl_b32 s27, s88, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 28, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s24, s24, s27 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s25, 0xffff -; SI-NEXT: s_lshl_b32 s17, s52, 16 +; SI-NEXT: v_mov_b32_e32 v2, s24 +; SI-NEXT: s_and_b32 s24, s25, 0xffff +; SI-NEXT: s_lshl_b32 s25, s52, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s24, s24, s25 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s26, 0xffff -; SI-NEXT: s_lshl_b32 s17, s78, 16 +; SI-NEXT: v_mov_b32_e32 v2, s24 +; SI-NEXT: s_and_b32 s22, s22, 0xffff +; SI-NEXT: s_lshl_b32 s24, s78, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 36, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s22, s22, s24 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s27, 0xffff -; SI-NEXT: s_lshl_b32 s17, s51, 16 +; SI-NEXT: v_mov_b32_e32 v2, s22 +; SI-NEXT: s_and_b32 s22, s23, 0xffff +; SI-NEXT: s_lshl_b32 s23, s51, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s22, s22, s23 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s28, 0xffff -; SI-NEXT: s_lshl_b32 s17, s76, 16 +; SI-NEXT: v_mov_b32_e32 v2, s22 +; SI-NEXT: s_and_b32 s20, s20, 0xffff +; SI-NEXT: s_lshl_b32 s22, s76, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 44, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s20, s20, s22 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s29, 0xffff -; SI-NEXT: s_lshl_b32 s17, s50, 16 +; SI-NEXT: v_mov_b32_e32 v2, s20 +; SI-NEXT: s_and_b32 s20, s21, 0xffff +; SI-NEXT: s_lshl_b32 s21, s50, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s20, s20, s21 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s42, 0xffff -; SI-NEXT: s_lshl_b32 s17, s74, 16 +; SI-NEXT: v_mov_b32_e32 v2, s20 +; SI-NEXT: s_and_b32 s18, s18, 0xffff +; SI-NEXT: s_lshl_b32 s20, s74, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 52, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s18, s18, s20 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s43, 0xffff -; SI-NEXT: s_lshl_b32 s17, s49, 16 +; SI-NEXT: v_mov_b32_e32 v2, s18 +; SI-NEXT: s_and_b32 s18, s19, 0xffff +; SI-NEXT: s_lshl_b32 s19, s49, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 56, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s18, s18, s19 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s40, 0xffff -; SI-NEXT: s_lshl_b32 s17, s72, 16 +; SI-NEXT: v_mov_b32_e32 v2, s18 +; SI-NEXT: s_and_b32 s16, s16, 0xffff +; SI-NEXT: s_lshl_b32 s18, s72, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 60, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s16, s16, s18 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s41, 0xffff +; SI-NEXT: s_and_b32 s16, s17, 0xffff ; SI-NEXT: s_lshl_b32 s17, s48, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 64, v0 ; SI-NEXT: s_or_b32 s16, s16, s17 @@ -4156,7 +4184,7 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s8 ; SI-NEXT: s_and_b32 s6, s6, 0xffff -; SI-NEXT: s_lshl_b32 s8, s46, 16 +; SI-NEXT: s_lshl_b32 s8, s28, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x64, v0 ; SI-NEXT: s_or_b32 s6, s6, s8 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen @@ -4170,7 +4198,7 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s6 ; SI-NEXT: s_and_b32 s4, s4, 0xffff -; SI-NEXT: s_lshl_b32 s6, s44, 16 +; SI-NEXT: s_lshl_b32 s6, s26, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x6c, v0 ; SI-NEXT: s_or_b32 s4, s4, s6 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen @@ -4184,25 +4212,25 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x74, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s64, v18, 16 -; SI-NEXT: v_readlane_b32 s55, v18, 15 -; SI-NEXT: v_readlane_b32 s54, v18, 14 -; SI-NEXT: v_readlane_b32 s53, v18, 13 -; SI-NEXT: v_readlane_b32 s52, v18, 12 -; SI-NEXT: v_readlane_b32 s51, v18, 11 -; SI-NEXT: v_readlane_b32 s50, v18, 10 -; SI-NEXT: v_readlane_b32 s49, v18, 9 -; SI-NEXT: v_readlane_b32 s48, v18, 8 -; SI-NEXT: v_readlane_b32 s39, v18, 7 -; SI-NEXT: v_readlane_b32 s38, v18, 6 -; SI-NEXT: v_readlane_b32 s37, v18, 5 -; SI-NEXT: v_readlane_b32 s36, v18, 4 -; SI-NEXT: v_readlane_b32 s35, v18, 3 -; SI-NEXT: v_readlane_b32 s34, v18, 2 -; SI-NEXT: v_readlane_b32 s31, v18, 1 -; SI-NEXT: v_readlane_b32 s30, v18, 0 +; SI-NEXT: v_readlane_b32 s64, v20, 16 +; SI-NEXT: v_readlane_b32 s55, v20, 15 +; SI-NEXT: v_readlane_b32 s54, v20, 14 +; SI-NEXT: v_readlane_b32 s53, v20, 13 +; SI-NEXT: v_readlane_b32 s52, v20, 12 +; SI-NEXT: v_readlane_b32 s51, v20, 11 +; SI-NEXT: v_readlane_b32 s50, v20, 10 +; SI-NEXT: v_readlane_b32 s49, v20, 9 +; SI-NEXT: v_readlane_b32 s48, v20, 8 +; SI-NEXT: v_readlane_b32 s39, v20, 7 +; SI-NEXT: v_readlane_b32 s38, v20, 6 +; SI-NEXT: v_readlane_b32 s37, v20, 5 +; SI-NEXT: v_readlane_b32 s36, v20, 4 +; SI-NEXT: v_readlane_b32 s35, v20, 3 +; SI-NEXT: v_readlane_b32 s34, v20, 2 +; SI-NEXT: v_readlane_b32 s31, v20, 1 +; SI-NEXT: v_readlane_b32 s30, v20, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] @@ -4233,10 +4261,10 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; SI-NEXT: ; implicit-def: $sgpr37 ; SI-NEXT: ; implicit-def: $sgpr56 ; SI-NEXT: ; implicit-def: $sgpr36 -; SI-NEXT: ; implicit-def: $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr28 ; SI-NEXT: ; implicit-def: $sgpr35 ; SI-NEXT: ; implicit-def: $sgpr34 -; SI-NEXT: ; implicit-def: $sgpr44 +; SI-NEXT: ; implicit-def: $sgpr26 ; SI-NEXT: s_branch .LBB13_2 ; ; VI-LABEL: bitcast_v30i32_to_v60i16_scalar: @@ -4247,18 +4275,46 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; VI-NEXT: s_mov_b64 exec, s[4:5] ; VI-NEXT: v_writelane_b32 v30, s30, 0 ; VI-NEXT: v_writelane_b32 v30, s31, 1 +; VI-NEXT: v_mov_b32_e32 v17, s16 +; VI-NEXT: v_mov_b32_e32 v18, s17 ; VI-NEXT: v_writelane_b32 v30, s34, 2 +; VI-NEXT: v_mov_b32_e32 v19, s18 +; VI-NEXT: v_readfirstlane_b32 s56, v17 +; VI-NEXT: v_mov_b32_e32 v17, s19 +; VI-NEXT: v_readfirstlane_b32 s47, v18 +; VI-NEXT: v_mov_b32_e32 v18, s20 ; VI-NEXT: v_writelane_b32 v30, s35, 3 +; VI-NEXT: v_readfirstlane_b32 s46, v19 +; VI-NEXT: v_mov_b32_e32 v19, s21 +; VI-NEXT: v_readfirstlane_b32 s45, v17 +; VI-NEXT: v_mov_b32_e32 v17, s22 +; VI-NEXT: v_readfirstlane_b32 s44, v18 +; VI-NEXT: v_mov_b32_e32 v18, s23 ; VI-NEXT: v_writelane_b32 v30, s36, 4 +; VI-NEXT: v_readfirstlane_b32 s43, v19 +; VI-NEXT: v_mov_b32_e32 v19, s24 +; VI-NEXT: v_readfirstlane_b32 s42, v17 +; VI-NEXT: v_mov_b32_e32 v17, s25 +; VI-NEXT: v_readfirstlane_b32 s41, v18 +; VI-NEXT: v_mov_b32_e32 v18, s26 ; VI-NEXT: v_writelane_b32 v30, s37, 5 +; VI-NEXT: v_readfirstlane_b32 s40, v19 +; VI-NEXT: v_mov_b32_e32 v19, s27 +; VI-NEXT: v_readfirstlane_b32 s26, v17 +; VI-NEXT: v_mov_b32_e32 v17, s28 +; VI-NEXT: v_readfirstlane_b32 s25, v18 +; VI-NEXT: v_mov_b32_e32 v18, s29 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 ; VI-NEXT: v_writelane_b32 v30, s38, 6 -; VI-NEXT: v_readfirstlane_b32 s45, v0 -; VI-NEXT: v_readfirstlane_b32 s44, v1 -; VI-NEXT: v_readfirstlane_b32 s43, v2 -; VI-NEXT: v_readfirstlane_b32 s42, v3 -; VI-NEXT: v_readfirstlane_b32 s41, v4 -; VI-NEXT: v_readfirstlane_b32 s40, v5 +; VI-NEXT: v_readfirstlane_b32 s24, v19 +; VI-NEXT: v_readfirstlane_b32 s23, v17 +; VI-NEXT: v_readfirstlane_b32 s22, v18 +; VI-NEXT: v_readfirstlane_b32 s21, v0 +; VI-NEXT: v_readfirstlane_b32 s20, v1 +; VI-NEXT: v_readfirstlane_b32 s19, v2 +; VI-NEXT: v_readfirstlane_b32 s18, v3 +; VI-NEXT: v_readfirstlane_b32 s17, v4 +; VI-NEXT: v_readfirstlane_b32 s16, v5 ; VI-NEXT: v_readfirstlane_b32 s15, v6 ; VI-NEXT: v_readfirstlane_b32 s14, v7 ; VI-NEXT: v_readfirstlane_b32 s13, v8 @@ -4273,9 +4329,9 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; VI-NEXT: v_writelane_b32 v30, s39, 7 ; VI-NEXT: s_cbranch_scc0 .LBB13_4 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_lshr_b32 s46, s7, 16 -; VI-NEXT: s_lshr_b32 s47, s6, 16 -; VI-NEXT: s_lshr_b32 s56, s8, 16 +; VI-NEXT: s_lshr_b32 s27, s7, 16 +; VI-NEXT: s_lshr_b32 s28, s6, 16 +; VI-NEXT: s_lshr_b32 s29, s8, 16 ; VI-NEXT: s_lshr_b32 s57, s9, 16 ; VI-NEXT: s_lshr_b32 s58, s10, 16 ; VI-NEXT: s_lshr_b32 s59, s11, 16 @@ -4283,26 +4339,26 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; VI-NEXT: s_lshr_b32 s61, s13, 16 ; VI-NEXT: s_lshr_b32 s62, s14, 16 ; VI-NEXT: s_lshr_b32 s63, s15, 16 -; VI-NEXT: s_lshr_b32 s72, s40, 16 -; VI-NEXT: s_lshr_b32 s73, s41, 16 -; VI-NEXT: s_lshr_b32 s74, s42, 16 -; VI-NEXT: s_lshr_b32 s75, s43, 16 -; VI-NEXT: s_lshr_b32 s76, s44, 16 -; VI-NEXT: s_lshr_b32 s77, s45, 16 -; VI-NEXT: s_lshr_b32 s78, s29, 16 -; VI-NEXT: s_lshr_b32 s79, s28, 16 -; VI-NEXT: s_lshr_b32 s88, s27, 16 -; VI-NEXT: s_lshr_b32 s89, s26, 16 -; VI-NEXT: s_lshr_b32 s90, s25, 16 -; VI-NEXT: s_lshr_b32 s91, s24, 16 -; VI-NEXT: s_lshr_b32 s30, s23, 16 -; VI-NEXT: s_lshr_b32 s31, s22, 16 -; VI-NEXT: s_lshr_b32 s34, s21, 16 -; VI-NEXT: s_lshr_b32 s35, s20, 16 -; VI-NEXT: s_lshr_b32 s36, s19, 16 -; VI-NEXT: s_lshr_b32 s37, s18, 16 -; VI-NEXT: s_lshr_b32 s38, s17, 16 -; VI-NEXT: s_lshr_b32 s39, s16, 16 +; VI-NEXT: s_lshr_b32 s72, s16, 16 +; VI-NEXT: s_lshr_b32 s73, s17, 16 +; VI-NEXT: s_lshr_b32 s74, s18, 16 +; VI-NEXT: s_lshr_b32 s75, s19, 16 +; VI-NEXT: s_lshr_b32 s76, s20, 16 +; VI-NEXT: s_lshr_b32 s77, s21, 16 +; VI-NEXT: s_lshr_b32 s78, s22, 16 +; VI-NEXT: s_lshr_b32 s79, s23, 16 +; VI-NEXT: s_lshr_b32 s88, s24, 16 +; VI-NEXT: s_lshr_b32 s89, s25, 16 +; VI-NEXT: s_lshr_b32 s90, s26, 16 +; VI-NEXT: s_lshr_b32 s91, s40, 16 +; VI-NEXT: s_lshr_b32 s30, s41, 16 +; VI-NEXT: s_lshr_b32 s31, s42, 16 +; VI-NEXT: s_lshr_b32 s34, s43, 16 +; VI-NEXT: s_lshr_b32 s35, s44, 16 +; VI-NEXT: s_lshr_b32 s36, s45, 16 +; VI-NEXT: s_lshr_b32 s37, s46, 16 +; VI-NEXT: s_lshr_b32 s38, s47, 16 +; VI-NEXT: s_lshr_b32 s39, s56, 16 ; VI-NEXT: s_cbranch_execnz .LBB13_3 ; VI-NEXT: .LBB13_2: ; %cmp.true ; VI-NEXT: s_add_i32 s7, s7, 3 @@ -4315,29 +4371,29 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; VI-NEXT: s_add_i32 s13, s13, 3 ; VI-NEXT: s_add_i32 s14, s14, 3 ; VI-NEXT: s_add_i32 s15, s15, 3 +; VI-NEXT: s_add_i32 s16, s16, 3 +; VI-NEXT: s_add_i32 s17, s17, 3 +; VI-NEXT: s_add_i32 s18, s18, 3 +; VI-NEXT: s_add_i32 s19, s19, 3 +; VI-NEXT: s_add_i32 s20, s20, 3 +; VI-NEXT: s_add_i32 s21, s21, 3 +; VI-NEXT: s_add_i32 s22, s22, 3 +; VI-NEXT: s_add_i32 s23, s23, 3 +; VI-NEXT: s_add_i32 s24, s24, 3 +; VI-NEXT: s_add_i32 s25, s25, 3 +; VI-NEXT: s_add_i32 s26, s26, 3 ; VI-NEXT: s_add_i32 s40, s40, 3 ; VI-NEXT: s_add_i32 s41, s41, 3 ; VI-NEXT: s_add_i32 s42, s42, 3 ; VI-NEXT: s_add_i32 s43, s43, 3 ; VI-NEXT: s_add_i32 s44, s44, 3 ; VI-NEXT: s_add_i32 s45, s45, 3 -; VI-NEXT: s_add_i32 s29, s29, 3 -; VI-NEXT: s_add_i32 s28, s28, 3 -; VI-NEXT: s_add_i32 s27, s27, 3 -; VI-NEXT: s_add_i32 s26, s26, 3 -; VI-NEXT: s_add_i32 s25, s25, 3 -; VI-NEXT: s_add_i32 s24, s24, 3 -; VI-NEXT: s_add_i32 s23, s23, 3 -; VI-NEXT: s_add_i32 s22, s22, 3 -; VI-NEXT: s_add_i32 s21, s21, 3 -; VI-NEXT: s_add_i32 s20, s20, 3 -; VI-NEXT: s_add_i32 s19, s19, 3 -; VI-NEXT: s_add_i32 s18, s18, 3 -; VI-NEXT: s_add_i32 s17, s17, 3 -; VI-NEXT: s_add_i32 s16, s16, 3 -; VI-NEXT: s_lshr_b32 s46, s7, 16 -; VI-NEXT: s_lshr_b32 s47, s6, 16 -; VI-NEXT: s_lshr_b32 s56, s8, 16 +; VI-NEXT: s_add_i32 s46, s46, 3 +; VI-NEXT: s_add_i32 s47, s47, 3 +; VI-NEXT: s_add_i32 s56, s56, 3 +; VI-NEXT: s_lshr_b32 s27, s7, 16 +; VI-NEXT: s_lshr_b32 s28, s6, 16 +; VI-NEXT: s_lshr_b32 s29, s8, 16 ; VI-NEXT: s_lshr_b32 s57, s9, 16 ; VI-NEXT: s_lshr_b32 s58, s10, 16 ; VI-NEXT: s_lshr_b32 s59, s11, 16 @@ -4345,137 +4401,137 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; VI-NEXT: s_lshr_b32 s61, s13, 16 ; VI-NEXT: s_lshr_b32 s62, s14, 16 ; VI-NEXT: s_lshr_b32 s63, s15, 16 -; VI-NEXT: s_lshr_b32 s72, s40, 16 -; VI-NEXT: s_lshr_b32 s73, s41, 16 -; VI-NEXT: s_lshr_b32 s74, s42, 16 -; VI-NEXT: s_lshr_b32 s75, s43, 16 -; VI-NEXT: s_lshr_b32 s76, s44, 16 -; VI-NEXT: s_lshr_b32 s77, s45, 16 -; VI-NEXT: s_lshr_b32 s78, s29, 16 -; VI-NEXT: s_lshr_b32 s79, s28, 16 -; VI-NEXT: s_lshr_b32 s88, s27, 16 -; VI-NEXT: s_lshr_b32 s89, s26, 16 -; VI-NEXT: s_lshr_b32 s90, s25, 16 -; VI-NEXT: s_lshr_b32 s91, s24, 16 -; VI-NEXT: s_lshr_b32 s30, s23, 16 -; VI-NEXT: s_lshr_b32 s31, s22, 16 -; VI-NEXT: s_lshr_b32 s34, s21, 16 -; VI-NEXT: s_lshr_b32 s35, s20, 16 -; VI-NEXT: s_lshr_b32 s36, s19, 16 -; VI-NEXT: s_lshr_b32 s37, s18, 16 -; VI-NEXT: s_lshr_b32 s38, s17, 16 -; VI-NEXT: s_lshr_b32 s39, s16, 16 +; VI-NEXT: s_lshr_b32 s72, s16, 16 +; VI-NEXT: s_lshr_b32 s73, s17, 16 +; VI-NEXT: s_lshr_b32 s74, s18, 16 +; VI-NEXT: s_lshr_b32 s75, s19, 16 +; VI-NEXT: s_lshr_b32 s76, s20, 16 +; VI-NEXT: s_lshr_b32 s77, s21, 16 +; VI-NEXT: s_lshr_b32 s78, s22, 16 +; VI-NEXT: s_lshr_b32 s79, s23, 16 +; VI-NEXT: s_lshr_b32 s88, s24, 16 +; VI-NEXT: s_lshr_b32 s89, s25, 16 +; VI-NEXT: s_lshr_b32 s90, s26, 16 +; VI-NEXT: s_lshr_b32 s91, s40, 16 +; VI-NEXT: s_lshr_b32 s30, s41, 16 +; VI-NEXT: s_lshr_b32 s31, s42, 16 +; VI-NEXT: s_lshr_b32 s34, s43, 16 +; VI-NEXT: s_lshr_b32 s35, s44, 16 +; VI-NEXT: s_lshr_b32 s36, s45, 16 +; VI-NEXT: s_lshr_b32 s37, s46, 16 +; VI-NEXT: s_lshr_b32 s38, s47, 16 +; VI-NEXT: s_lshr_b32 s39, s56, 16 ; VI-NEXT: .LBB13_3: ; %end -; VI-NEXT: s_and_b32 s4, 0xffff, s16 +; VI-NEXT: s_and_b32 s4, 0xffff, s56 ; VI-NEXT: s_lshl_b32 s5, s39, 16 ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_and_b32 s5, 0xffff, s17 -; VI-NEXT: s_lshl_b32 s16, s38, 16 -; VI-NEXT: s_or_b32 s5, s5, s16 -; VI-NEXT: s_and_b32 s16, 0xffff, s18 -; VI-NEXT: s_lshl_b32 s17, s37, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, 0xffff, s19 -; VI-NEXT: s_lshl_b32 s18, s36, 16 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s18, 0xffff, s20 -; VI-NEXT: s_lshl_b32 s19, s35, 16 -; VI-NEXT: s_or_b32 s18, s18, s19 -; VI-NEXT: s_and_b32 s19, 0xffff, s21 -; VI-NEXT: s_lshl_b32 s20, s34, 16 -; VI-NEXT: s_or_b32 s19, s19, s20 -; VI-NEXT: s_and_b32 s20, 0xffff, s22 -; VI-NEXT: s_lshl_b32 s21, s31, 16 -; VI-NEXT: s_or_b32 s20, s20, s21 -; VI-NEXT: s_and_b32 s21, 0xffff, s23 -; VI-NEXT: s_lshl_b32 s22, s30, 16 -; VI-NEXT: s_or_b32 s21, s21, s22 -; VI-NEXT: s_and_b32 s22, 0xffff, s24 -; VI-NEXT: s_lshl_b32 s23, s91, 16 -; VI-NEXT: s_or_b32 s22, s22, s23 -; VI-NEXT: s_and_b32 s23, 0xffff, s25 -; VI-NEXT: s_lshl_b32 s24, s90, 16 -; VI-NEXT: s_or_b32 s23, s23, s24 -; VI-NEXT: s_and_b32 s24, 0xffff, s26 -; VI-NEXT: s_lshl_b32 s25, s89, 16 -; VI-NEXT: s_or_b32 s24, s24, s25 -; VI-NEXT: s_and_b32 s25, 0xffff, s27 -; VI-NEXT: s_lshl_b32 s26, s88, 16 -; VI-NEXT: s_or_b32 s25, s25, s26 -; VI-NEXT: s_and_b32 s26, 0xffff, s28 -; VI-NEXT: s_lshl_b32 s27, s79, 16 -; VI-NEXT: s_or_b32 s26, s26, s27 -; VI-NEXT: s_and_b32 s27, 0xffff, s29 -; VI-NEXT: s_lshl_b32 s28, s78, 16 -; VI-NEXT: s_or_b32 s27, s27, s28 -; VI-NEXT: s_and_b32 s28, 0xffff, s45 -; VI-NEXT: s_lshl_b32 s29, s77, 16 -; VI-NEXT: s_or_b32 s28, s28, s29 -; VI-NEXT: s_and_b32 s29, 0xffff, s44 -; VI-NEXT: s_lshl_b32 s44, s76, 16 -; VI-NEXT: s_or_b32 s29, s29, s44 +; VI-NEXT: s_and_b32 s5, 0xffff, s47 +; VI-NEXT: s_lshl_b32 s47, s38, 16 +; VI-NEXT: s_or_b32 s5, s5, s47 +; VI-NEXT: s_and_b32 s46, 0xffff, s46 +; VI-NEXT: s_lshl_b32 s47, s37, 16 +; VI-NEXT: s_or_b32 s46, s46, s47 +; VI-NEXT: s_and_b32 s45, 0xffff, s45 +; VI-NEXT: s_lshl_b32 s47, s36, 16 +; VI-NEXT: s_or_b32 s45, s45, s47 +; VI-NEXT: s_and_b32 s44, 0xffff, s44 +; VI-NEXT: s_lshl_b32 s47, s35, 16 +; VI-NEXT: s_or_b32 s44, s44, s47 ; VI-NEXT: s_and_b32 s43, 0xffff, s43 -; VI-NEXT: s_lshl_b32 s44, s75, 16 -; VI-NEXT: s_or_b32 s43, s43, s44 +; VI-NEXT: s_lshl_b32 s47, s34, 16 +; VI-NEXT: s_or_b32 s43, s43, s47 ; VI-NEXT: s_and_b32 s42, 0xffff, s42 -; VI-NEXT: s_lshl_b32 s44, s74, 16 -; VI-NEXT: s_or_b32 s42, s42, s44 +; VI-NEXT: s_lshl_b32 s47, s31, 16 +; VI-NEXT: s_or_b32 s42, s42, s47 ; VI-NEXT: s_and_b32 s41, 0xffff, s41 -; VI-NEXT: s_lshl_b32 s44, s73, 16 -; VI-NEXT: s_or_b32 s41, s41, s44 +; VI-NEXT: s_lshl_b32 s47, s30, 16 +; VI-NEXT: s_or_b32 s41, s41, s47 ; VI-NEXT: s_and_b32 s40, 0xffff, s40 -; VI-NEXT: s_lshl_b32 s44, s72, 16 -; VI-NEXT: s_or_b32 s40, s40, s44 +; VI-NEXT: s_lshl_b32 s47, s91, 16 +; VI-NEXT: s_or_b32 s40, s40, s47 +; VI-NEXT: s_and_b32 s26, 0xffff, s26 +; VI-NEXT: s_lshl_b32 s47, s90, 16 +; VI-NEXT: s_or_b32 s26, s26, s47 +; VI-NEXT: s_and_b32 s25, 0xffff, s25 +; VI-NEXT: s_lshl_b32 s47, s89, 16 +; VI-NEXT: s_or_b32 s25, s25, s47 +; VI-NEXT: s_and_b32 s24, 0xffff, s24 +; VI-NEXT: s_lshl_b32 s47, s88, 16 +; VI-NEXT: s_or_b32 s24, s24, s47 +; VI-NEXT: s_and_b32 s23, 0xffff, s23 +; VI-NEXT: s_lshl_b32 s47, s79, 16 +; VI-NEXT: s_or_b32 s23, s23, s47 +; VI-NEXT: s_and_b32 s22, 0xffff, s22 +; VI-NEXT: s_lshl_b32 s47, s78, 16 +; VI-NEXT: s_or_b32 s22, s22, s47 +; VI-NEXT: s_and_b32 s21, 0xffff, s21 +; VI-NEXT: s_lshl_b32 s47, s77, 16 +; VI-NEXT: s_or_b32 s21, s21, s47 +; VI-NEXT: s_and_b32 s20, 0xffff, s20 +; VI-NEXT: s_lshl_b32 s47, s76, 16 +; VI-NEXT: s_or_b32 s20, s20, s47 +; VI-NEXT: s_and_b32 s19, 0xffff, s19 +; VI-NEXT: s_lshl_b32 s47, s75, 16 +; VI-NEXT: s_or_b32 s19, s19, s47 +; VI-NEXT: s_and_b32 s18, 0xffff, s18 +; VI-NEXT: s_lshl_b32 s47, s74, 16 +; VI-NEXT: s_or_b32 s18, s18, s47 +; VI-NEXT: s_and_b32 s17, 0xffff, s17 +; VI-NEXT: s_lshl_b32 s47, s73, 16 +; VI-NEXT: s_or_b32 s17, s17, s47 +; VI-NEXT: s_and_b32 s16, 0xffff, s16 +; VI-NEXT: s_lshl_b32 s47, s72, 16 +; VI-NEXT: s_or_b32 s16, s16, s47 ; VI-NEXT: s_and_b32 s15, 0xffff, s15 -; VI-NEXT: s_lshl_b32 s44, s63, 16 -; VI-NEXT: s_or_b32 s15, s15, s44 +; VI-NEXT: s_lshl_b32 s47, s63, 16 +; VI-NEXT: s_or_b32 s15, s15, s47 ; VI-NEXT: s_and_b32 s14, 0xffff, s14 -; VI-NEXT: s_lshl_b32 s44, s62, 16 -; VI-NEXT: s_or_b32 s14, s14, s44 +; VI-NEXT: s_lshl_b32 s47, s62, 16 +; VI-NEXT: s_or_b32 s14, s14, s47 ; VI-NEXT: s_and_b32 s13, 0xffff, s13 -; VI-NEXT: s_lshl_b32 s44, s61, 16 -; VI-NEXT: s_or_b32 s13, s13, s44 +; VI-NEXT: s_lshl_b32 s47, s61, 16 +; VI-NEXT: s_or_b32 s13, s13, s47 ; VI-NEXT: s_and_b32 s12, 0xffff, s12 -; VI-NEXT: s_lshl_b32 s44, s60, 16 -; VI-NEXT: s_or_b32 s12, s12, s44 +; VI-NEXT: s_lshl_b32 s47, s60, 16 +; VI-NEXT: s_or_b32 s12, s12, s47 ; VI-NEXT: s_and_b32 s11, 0xffff, s11 -; VI-NEXT: s_lshl_b32 s44, s59, 16 -; VI-NEXT: s_or_b32 s11, s11, s44 +; VI-NEXT: s_lshl_b32 s47, s59, 16 +; VI-NEXT: s_or_b32 s11, s11, s47 ; VI-NEXT: s_and_b32 s10, 0xffff, s10 -; VI-NEXT: s_lshl_b32 s44, s58, 16 -; VI-NEXT: s_or_b32 s10, s10, s44 +; VI-NEXT: s_lshl_b32 s47, s58, 16 +; VI-NEXT: s_or_b32 s10, s10, s47 ; VI-NEXT: s_and_b32 s9, 0xffff, s9 -; VI-NEXT: s_lshl_b32 s44, s57, 16 -; VI-NEXT: s_or_b32 s9, s9, s44 +; VI-NEXT: s_lshl_b32 s47, s57, 16 ; VI-NEXT: s_and_b32 s8, 0xffff, s8 -; VI-NEXT: s_lshl_b32 s44, s56, 16 -; VI-NEXT: s_or_b32 s8, s8, s44 +; VI-NEXT: s_lshl_b32 s29, s29, 16 ; VI-NEXT: s_and_b32 s6, 0xffff, s6 -; VI-NEXT: s_lshl_b32 s44, s47, 16 -; VI-NEXT: s_or_b32 s6, s6, s44 +; VI-NEXT: s_lshl_b32 s28, s28, 16 ; VI-NEXT: s_and_b32 s7, 0xffff, s7 -; VI-NEXT: s_lshl_b32 s44, s46, 16 -; VI-NEXT: s_or_b32 s7, s7, s44 +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s9, s9, s47 +; VI-NEXT: s_or_b32 s8, s8, s29 +; VI-NEXT: s_or_b32 s6, s6, s28 +; VI-NEXT: s_or_b32 s7, s7, s27 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s5 -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: v_mov_b32_e32 v3, s17 -; VI-NEXT: v_mov_b32_e32 v4, s18 -; VI-NEXT: v_mov_b32_e32 v5, s19 -; VI-NEXT: v_mov_b32_e32 v6, s20 -; VI-NEXT: v_mov_b32_e32 v7, s21 -; VI-NEXT: v_mov_b32_e32 v8, s22 -; VI-NEXT: v_mov_b32_e32 v9, s23 -; VI-NEXT: v_mov_b32_e32 v10, s24 -; VI-NEXT: v_mov_b32_e32 v11, s25 -; VI-NEXT: v_mov_b32_e32 v12, s26 -; VI-NEXT: v_mov_b32_e32 v13, s27 -; VI-NEXT: v_mov_b32_e32 v14, s28 -; VI-NEXT: v_mov_b32_e32 v15, s29 -; VI-NEXT: v_mov_b32_e32 v16, s43 -; VI-NEXT: v_mov_b32_e32 v17, s42 -; VI-NEXT: v_mov_b32_e32 v18, s41 -; VI-NEXT: v_mov_b32_e32 v19, s40 +; VI-NEXT: v_mov_b32_e32 v2, s46 +; VI-NEXT: v_mov_b32_e32 v3, s45 +; VI-NEXT: v_mov_b32_e32 v4, s44 +; VI-NEXT: v_mov_b32_e32 v5, s43 +; VI-NEXT: v_mov_b32_e32 v6, s42 +; VI-NEXT: v_mov_b32_e32 v7, s41 +; VI-NEXT: v_mov_b32_e32 v8, s40 +; VI-NEXT: v_mov_b32_e32 v9, s26 +; VI-NEXT: v_mov_b32_e32 v10, s25 +; VI-NEXT: v_mov_b32_e32 v11, s24 +; VI-NEXT: v_mov_b32_e32 v12, s23 +; VI-NEXT: v_mov_b32_e32 v13, s22 +; VI-NEXT: v_mov_b32_e32 v14, s21 +; VI-NEXT: v_mov_b32_e32 v15, s20 +; VI-NEXT: v_mov_b32_e32 v16, s19 +; VI-NEXT: v_mov_b32_e32 v17, s18 +; VI-NEXT: v_mov_b32_e32 v18, s17 +; VI-NEXT: v_mov_b32_e32 v19, s16 ; VI-NEXT: v_mov_b32_e32 v20, s15 ; VI-NEXT: v_mov_b32_e32 v21, s14 ; VI-NEXT: v_mov_b32_e32 v22, s13 @@ -4527,9 +4583,9 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; VI-NEXT: ; implicit-def: $sgpr59 ; VI-NEXT: ; implicit-def: $sgpr58 ; VI-NEXT: ; implicit-def: $sgpr57 -; VI-NEXT: ; implicit-def: $sgpr56 -; VI-NEXT: ; implicit-def: $sgpr47 -; VI-NEXT: ; implicit-def: $sgpr46 +; VI-NEXT: ; implicit-def: $sgpr29 +; VI-NEXT: ; implicit-def: $sgpr28 +; VI-NEXT: ; implicit-def: $sgpr27 ; VI-NEXT: s_branch .LBB13_2 ; ; GFX9-LABEL: bitcast_v30i32_to_v60i16_scalar: @@ -4538,20 +4594,48 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] +; GFX9-NEXT: v_mov_b32_e32 v17, s16 +; GFX9-NEXT: v_mov_b32_e32 v18, s17 +; GFX9-NEXT: v_mov_b32_e32 v19, s18 +; GFX9-NEXT: v_readfirstlane_b32 s6, v17 +; GFX9-NEXT: v_mov_b32_e32 v17, s19 +; GFX9-NEXT: v_readfirstlane_b32 s7, v18 +; GFX9-NEXT: v_mov_b32_e32 v18, s20 +; GFX9-NEXT: v_readfirstlane_b32 s8, v19 +; GFX9-NEXT: v_mov_b32_e32 v19, s21 +; GFX9-NEXT: v_readfirstlane_b32 s9, v17 +; GFX9-NEXT: v_mov_b32_e32 v17, s22 +; GFX9-NEXT: v_readfirstlane_b32 s10, v18 +; GFX9-NEXT: v_mov_b32_e32 v18, s23 ; GFX9-NEXT: v_writelane_b32 v30, s30, 0 +; GFX9-NEXT: v_readfirstlane_b32 s11, v19 +; GFX9-NEXT: v_mov_b32_e32 v19, s24 +; GFX9-NEXT: v_readfirstlane_b32 s12, v17 +; GFX9-NEXT: v_mov_b32_e32 v17, s25 +; GFX9-NEXT: v_readfirstlane_b32 s13, v18 +; GFX9-NEXT: v_mov_b32_e32 v18, s26 ; GFX9-NEXT: v_writelane_b32 v30, s31, 1 +; GFX9-NEXT: v_readfirstlane_b32 s14, v19 +; GFX9-NEXT: v_mov_b32_e32 v19, s27 +; GFX9-NEXT: v_readfirstlane_b32 s15, v17 +; GFX9-NEXT: v_mov_b32_e32 v17, s28 +; GFX9-NEXT: v_readfirstlane_b32 s16, v18 +; GFX9-NEXT: v_mov_b32_e32 v18, s29 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 ; GFX9-NEXT: v_writelane_b32 v30, s34, 2 -; GFX9-NEXT: v_readfirstlane_b32 s6, v0 -; GFX9-NEXT: v_readfirstlane_b32 s7, v1 -; GFX9-NEXT: v_readfirstlane_b32 s8, v2 -; GFX9-NEXT: v_readfirstlane_b32 s9, v3 -; GFX9-NEXT: v_readfirstlane_b32 s10, v4 -; GFX9-NEXT: v_readfirstlane_b32 s11, v5 -; GFX9-NEXT: v_readfirstlane_b32 s12, v6 -; GFX9-NEXT: v_readfirstlane_b32 s13, v7 -; GFX9-NEXT: v_readfirstlane_b32 s14, v8 -; GFX9-NEXT: v_readfirstlane_b32 s15, v9 +; GFX9-NEXT: v_readfirstlane_b32 s17, v19 +; GFX9-NEXT: v_readfirstlane_b32 s18, v17 +; GFX9-NEXT: v_readfirstlane_b32 s19, v18 +; GFX9-NEXT: v_readfirstlane_b32 s20, v0 +; GFX9-NEXT: v_readfirstlane_b32 s21, v1 +; GFX9-NEXT: v_readfirstlane_b32 s22, v2 +; GFX9-NEXT: v_readfirstlane_b32 s23, v3 +; GFX9-NEXT: v_readfirstlane_b32 s24, v4 +; GFX9-NEXT: v_readfirstlane_b32 s25, v5 +; GFX9-NEXT: v_readfirstlane_b32 s26, v6 +; GFX9-NEXT: v_readfirstlane_b32 s27, v7 +; GFX9-NEXT: v_readfirstlane_b32 s28, v8 +; GFX9-NEXT: v_readfirstlane_b32 s29, v9 ; GFX9-NEXT: v_readfirstlane_b32 s40, v10 ; GFX9-NEXT: v_readfirstlane_b32 s41, v11 ; GFX9-NEXT: v_readfirstlane_b32 s42, v12 @@ -4568,30 +4652,30 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; GFX9-NEXT: s_lshr_b32 s57, s42, 16 ; GFX9-NEXT: s_lshr_b32 s58, s41, 16 ; GFX9-NEXT: s_lshr_b32 s59, s40, 16 -; GFX9-NEXT: s_lshr_b32 s60, s15, 16 -; GFX9-NEXT: s_lshr_b32 s61, s14, 16 -; GFX9-NEXT: s_lshr_b32 s62, s13, 16 -; GFX9-NEXT: s_lshr_b32 s63, s12, 16 -; GFX9-NEXT: s_lshr_b32 s72, s11, 16 -; GFX9-NEXT: s_lshr_b32 s73, s10, 16 -; GFX9-NEXT: s_lshr_b32 s74, s9, 16 -; GFX9-NEXT: s_lshr_b32 s75, s8, 16 -; GFX9-NEXT: s_lshr_b32 s76, s7, 16 -; GFX9-NEXT: s_lshr_b32 s77, s6, 16 -; GFX9-NEXT: s_lshr_b32 s78, s29, 16 -; GFX9-NEXT: s_lshr_b32 s79, s28, 16 -; GFX9-NEXT: s_lshr_b32 s88, s27, 16 -; GFX9-NEXT: s_lshr_b32 s89, s26, 16 -; GFX9-NEXT: s_lshr_b32 s90, s25, 16 -; GFX9-NEXT: s_lshr_b32 s91, s24, 16 -; GFX9-NEXT: s_lshr_b32 s92, s23, 16 -; GFX9-NEXT: s_lshr_b32 s93, s22, 16 -; GFX9-NEXT: s_lshr_b32 s94, s21, 16 -; GFX9-NEXT: s_lshr_b32 s95, s20, 16 -; GFX9-NEXT: s_lshr_b32 s30, s19, 16 -; GFX9-NEXT: s_lshr_b32 s31, s18, 16 -; GFX9-NEXT: s_lshr_b32 s34, s17, 16 -; GFX9-NEXT: s_lshr_b32 s35, s16, 16 +; GFX9-NEXT: s_lshr_b32 s60, s29, 16 +; GFX9-NEXT: s_lshr_b32 s61, s28, 16 +; GFX9-NEXT: s_lshr_b32 s62, s27, 16 +; GFX9-NEXT: s_lshr_b32 s63, s26, 16 +; GFX9-NEXT: s_lshr_b32 s72, s25, 16 +; GFX9-NEXT: s_lshr_b32 s73, s24, 16 +; GFX9-NEXT: s_lshr_b32 s74, s23, 16 +; GFX9-NEXT: s_lshr_b32 s75, s22, 16 +; GFX9-NEXT: s_lshr_b32 s76, s21, 16 +; GFX9-NEXT: s_lshr_b32 s77, s20, 16 +; GFX9-NEXT: s_lshr_b32 s78, s19, 16 +; GFX9-NEXT: s_lshr_b32 s79, s18, 16 +; GFX9-NEXT: s_lshr_b32 s88, s17, 16 +; GFX9-NEXT: s_lshr_b32 s89, s16, 16 +; GFX9-NEXT: s_lshr_b32 s90, s15, 16 +; GFX9-NEXT: s_lshr_b32 s91, s14, 16 +; GFX9-NEXT: s_lshr_b32 s92, s13, 16 +; GFX9-NEXT: s_lshr_b32 s93, s12, 16 +; GFX9-NEXT: s_lshr_b32 s94, s11, 16 +; GFX9-NEXT: s_lshr_b32 s95, s10, 16 +; GFX9-NEXT: s_lshr_b32 s30, s9, 16 +; GFX9-NEXT: s_lshr_b32 s31, s8, 16 +; GFX9-NEXT: s_lshr_b32 s34, s7, 16 +; GFX9-NEXT: s_lshr_b32 s35, s6, 16 ; GFX9-NEXT: s_cbranch_execnz .LBB13_3 ; GFX9-NEXT: .LBB13_2: ; %cmp.true ; GFX9-NEXT: s_add_i32 s45, s45, 3 @@ -4600,16 +4684,6 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; GFX9-NEXT: s_add_i32 s42, s42, 3 ; GFX9-NEXT: s_add_i32 s41, s41, 3 ; GFX9-NEXT: s_add_i32 s40, s40, 3 -; GFX9-NEXT: s_add_i32 s15, s15, 3 -; GFX9-NEXT: s_add_i32 s14, s14, 3 -; GFX9-NEXT: s_add_i32 s13, s13, 3 -; GFX9-NEXT: s_add_i32 s12, s12, 3 -; GFX9-NEXT: s_add_i32 s11, s11, 3 -; GFX9-NEXT: s_add_i32 s10, s10, 3 -; GFX9-NEXT: s_add_i32 s9, s9, 3 -; GFX9-NEXT: s_add_i32 s8, s8, 3 -; GFX9-NEXT: s_add_i32 s7, s7, 3 -; GFX9-NEXT: s_add_i32 s6, s6, 3 ; GFX9-NEXT: s_add_i32 s29, s29, 3 ; GFX9-NEXT: s_add_i32 s28, s28, 3 ; GFX9-NEXT: s_add_i32 s27, s27, 3 @@ -4624,61 +4698,71 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; GFX9-NEXT: s_add_i32 s18, s18, 3 ; GFX9-NEXT: s_add_i32 s17, s17, 3 ; GFX9-NEXT: s_add_i32 s16, s16, 3 +; GFX9-NEXT: s_add_i32 s15, s15, 3 +; GFX9-NEXT: s_add_i32 s14, s14, 3 +; GFX9-NEXT: s_add_i32 s13, s13, 3 +; GFX9-NEXT: s_add_i32 s12, s12, 3 +; GFX9-NEXT: s_add_i32 s11, s11, 3 +; GFX9-NEXT: s_add_i32 s10, s10, 3 +; GFX9-NEXT: s_add_i32 s9, s9, 3 +; GFX9-NEXT: s_add_i32 s8, s8, 3 +; GFX9-NEXT: s_add_i32 s7, s7, 3 +; GFX9-NEXT: s_add_i32 s6, s6, 3 ; GFX9-NEXT: s_lshr_b32 s46, s45, 16 ; GFX9-NEXT: s_lshr_b32 s47, s44, 16 ; GFX9-NEXT: s_lshr_b32 s56, s43, 16 ; GFX9-NEXT: s_lshr_b32 s57, s42, 16 ; GFX9-NEXT: s_lshr_b32 s58, s41, 16 ; GFX9-NEXT: s_lshr_b32 s59, s40, 16 -; GFX9-NEXT: s_lshr_b32 s60, s15, 16 -; GFX9-NEXT: s_lshr_b32 s61, s14, 16 -; GFX9-NEXT: s_lshr_b32 s62, s13, 16 -; GFX9-NEXT: s_lshr_b32 s63, s12, 16 -; GFX9-NEXT: s_lshr_b32 s72, s11, 16 -; GFX9-NEXT: s_lshr_b32 s73, s10, 16 -; GFX9-NEXT: s_lshr_b32 s74, s9, 16 -; GFX9-NEXT: s_lshr_b32 s75, s8, 16 -; GFX9-NEXT: s_lshr_b32 s76, s7, 16 -; GFX9-NEXT: s_lshr_b32 s77, s6, 16 -; GFX9-NEXT: s_lshr_b32 s78, s29, 16 -; GFX9-NEXT: s_lshr_b32 s79, s28, 16 -; GFX9-NEXT: s_lshr_b32 s88, s27, 16 -; GFX9-NEXT: s_lshr_b32 s89, s26, 16 -; GFX9-NEXT: s_lshr_b32 s90, s25, 16 -; GFX9-NEXT: s_lshr_b32 s91, s24, 16 -; GFX9-NEXT: s_lshr_b32 s92, s23, 16 -; GFX9-NEXT: s_lshr_b32 s93, s22, 16 -; GFX9-NEXT: s_lshr_b32 s94, s21, 16 -; GFX9-NEXT: s_lshr_b32 s95, s20, 16 -; GFX9-NEXT: s_lshr_b32 s30, s19, 16 -; GFX9-NEXT: s_lshr_b32 s31, s18, 16 -; GFX9-NEXT: s_lshr_b32 s34, s17, 16 -; GFX9-NEXT: s_lshr_b32 s35, s16, 16 +; GFX9-NEXT: s_lshr_b32 s60, s29, 16 +; GFX9-NEXT: s_lshr_b32 s61, s28, 16 +; GFX9-NEXT: s_lshr_b32 s62, s27, 16 +; GFX9-NEXT: s_lshr_b32 s63, s26, 16 +; GFX9-NEXT: s_lshr_b32 s72, s25, 16 +; GFX9-NEXT: s_lshr_b32 s73, s24, 16 +; GFX9-NEXT: s_lshr_b32 s74, s23, 16 +; GFX9-NEXT: s_lshr_b32 s75, s22, 16 +; GFX9-NEXT: s_lshr_b32 s76, s21, 16 +; GFX9-NEXT: s_lshr_b32 s77, s20, 16 +; GFX9-NEXT: s_lshr_b32 s78, s19, 16 +; GFX9-NEXT: s_lshr_b32 s79, s18, 16 +; GFX9-NEXT: s_lshr_b32 s88, s17, 16 +; GFX9-NEXT: s_lshr_b32 s89, s16, 16 +; GFX9-NEXT: s_lshr_b32 s90, s15, 16 +; GFX9-NEXT: s_lshr_b32 s91, s14, 16 +; GFX9-NEXT: s_lshr_b32 s92, s13, 16 +; GFX9-NEXT: s_lshr_b32 s93, s12, 16 +; GFX9-NEXT: s_lshr_b32 s94, s11, 16 +; GFX9-NEXT: s_lshr_b32 s95, s10, 16 +; GFX9-NEXT: s_lshr_b32 s30, s9, 16 +; GFX9-NEXT: s_lshr_b32 s31, s8, 16 +; GFX9-NEXT: s_lshr_b32 s34, s7, 16 +; GFX9-NEXT: s_lshr_b32 s35, s6, 16 ; GFX9-NEXT: .LBB13_3: ; %end -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s16, s35 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s17, s34 -; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s31 -; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s30 -; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s95 -; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s94 -; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s93 -; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s92 -; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s91 -; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s90 -; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s89 -; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s88 -; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s79 -; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s78 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s77 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s76 -; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s75 -; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s74 -; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s73 -; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s72 -; GFX9-NEXT: s_pack_ll_b32_b16 s12, s12, s63 -; GFX9-NEXT: s_pack_ll_b32_b16 s13, s13, s62 -; GFX9-NEXT: s_pack_ll_b32_b16 s14, s14, s61 -; GFX9-NEXT: s_pack_ll_b32_b16 s15, s15, s60 +; GFX9-NEXT: s_pack_ll_b32_b16 s4, s6, s35 +; GFX9-NEXT: s_pack_ll_b32_b16 s5, s7, s34 +; GFX9-NEXT: s_pack_ll_b32_b16 s6, s8, s31 +; GFX9-NEXT: s_pack_ll_b32_b16 s7, s9, s30 +; GFX9-NEXT: s_pack_ll_b32_b16 s8, s10, s95 +; GFX9-NEXT: s_pack_ll_b32_b16 s9, s11, s94 +; GFX9-NEXT: s_pack_ll_b32_b16 s10, s12, s93 +; GFX9-NEXT: s_pack_ll_b32_b16 s11, s13, s92 +; GFX9-NEXT: s_pack_ll_b32_b16 s12, s14, s91 +; GFX9-NEXT: s_pack_ll_b32_b16 s13, s15, s90 +; GFX9-NEXT: s_pack_ll_b32_b16 s14, s16, s89 +; GFX9-NEXT: s_pack_ll_b32_b16 s15, s17, s88 +; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s79 +; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s78 +; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s77 +; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s76 +; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s75 +; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s74 +; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s73 +; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s72 +; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s63 +; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s62 +; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s61 +; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s60 ; GFX9-NEXT: s_pack_ll_b32_b16 s28, s40, s59 ; GFX9-NEXT: s_pack_ll_b32_b16 s29, s41, s58 ; GFX9-NEXT: s_pack_ll_b32_b16 s40, s42, s57 @@ -4687,28 +4771,28 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; GFX9-NEXT: s_pack_ll_b32_b16 s43, s45, s46 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 -; GFX9-NEXT: v_mov_b32_e32 v2, s16 -; GFX9-NEXT: v_mov_b32_e32 v3, s17 -; GFX9-NEXT: v_mov_b32_e32 v4, s18 -; GFX9-NEXT: v_mov_b32_e32 v5, s19 -; GFX9-NEXT: v_mov_b32_e32 v6, s20 -; GFX9-NEXT: v_mov_b32_e32 v7, s21 -; GFX9-NEXT: v_mov_b32_e32 v8, s22 -; GFX9-NEXT: v_mov_b32_e32 v9, s23 -; GFX9-NEXT: v_mov_b32_e32 v10, s24 -; GFX9-NEXT: v_mov_b32_e32 v11, s25 -; GFX9-NEXT: v_mov_b32_e32 v12, s26 -; GFX9-NEXT: v_mov_b32_e32 v13, s27 -; GFX9-NEXT: v_mov_b32_e32 v14, s6 -; GFX9-NEXT: v_mov_b32_e32 v15, s7 -; GFX9-NEXT: v_mov_b32_e32 v16, s8 -; GFX9-NEXT: v_mov_b32_e32 v17, s9 -; GFX9-NEXT: v_mov_b32_e32 v18, s10 -; GFX9-NEXT: v_mov_b32_e32 v19, s11 -; GFX9-NEXT: v_mov_b32_e32 v20, s12 -; GFX9-NEXT: v_mov_b32_e32 v21, s13 -; GFX9-NEXT: v_mov_b32_e32 v22, s14 -; GFX9-NEXT: v_mov_b32_e32 v23, s15 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: v_mov_b32_e32 v4, s8 +; GFX9-NEXT: v_mov_b32_e32 v5, s9 +; GFX9-NEXT: v_mov_b32_e32 v6, s10 +; GFX9-NEXT: v_mov_b32_e32 v7, s11 +; GFX9-NEXT: v_mov_b32_e32 v8, s12 +; GFX9-NEXT: v_mov_b32_e32 v9, s13 +; GFX9-NEXT: v_mov_b32_e32 v10, s14 +; GFX9-NEXT: v_mov_b32_e32 v11, s15 +; GFX9-NEXT: v_mov_b32_e32 v12, s16 +; GFX9-NEXT: v_mov_b32_e32 v13, s17 +; GFX9-NEXT: v_mov_b32_e32 v14, s18 +; GFX9-NEXT: v_mov_b32_e32 v15, s19 +; GFX9-NEXT: v_mov_b32_e32 v16, s20 +; GFX9-NEXT: v_mov_b32_e32 v17, s21 +; GFX9-NEXT: v_mov_b32_e32 v18, s22 +; GFX9-NEXT: v_mov_b32_e32 v19, s23 +; GFX9-NEXT: v_mov_b32_e32 v20, s24 +; GFX9-NEXT: v_mov_b32_e32 v21, s25 +; GFX9-NEXT: v_mov_b32_e32 v22, s26 +; GFX9-NEXT: v_mov_b32_e32 v23, s27 ; GFX9-NEXT: v_mov_b32_e32 v24, s28 ; GFX9-NEXT: v_mov_b32_e32 v25, s29 ; GFX9-NEXT: v_mov_b32_e32 v26, s40 @@ -4760,49 +4844,76 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; GFX11-LABEL: bitcast_v30i32_to_v60i16_scalar: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v13, s0 :: v_dual_mov_b32 v14, s1 +; GFX11-NEXT: v_dual_mov_b32 v15, s2 :: v_dual_mov_b32 v16, s3 +; GFX11-NEXT: v_dual_mov_b32 v17, s16 :: v_dual_mov_b32 v18, s17 +; GFX11-NEXT: v_dual_mov_b32 v19, s18 :: v_dual_mov_b32 v20, s19 +; GFX11-NEXT: v_dual_mov_b32 v21, s20 :: v_dual_mov_b32 v22, s21 +; GFX11-NEXT: v_dual_mov_b32 v23, s22 :: v_dual_mov_b32 v24, s23 +; GFX11-NEXT: v_dual_mov_b32 v25, s24 :: v_dual_mov_b32 v26, s25 +; GFX11-NEXT: v_dual_mov_b32 v27, s26 :: v_dual_mov_b32 v28, s27 +; GFX11-NEXT: v_dual_mov_b32 v29, s28 :: v_dual_mov_b32 v30, s29 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 -; GFX11-NEXT: v_readfirstlane_b32 s4, v0 -; GFX11-NEXT: v_readfirstlane_b32 s5, v1 -; GFX11-NEXT: v_readfirstlane_b32 s6, v2 -; GFX11-NEXT: v_readfirstlane_b32 s7, v3 -; GFX11-NEXT: v_readfirstlane_b32 s8, v4 -; GFX11-NEXT: v_readfirstlane_b32 s9, v5 -; GFX11-NEXT: v_readfirstlane_b32 s10, v6 -; GFX11-NEXT: v_readfirstlane_b32 s11, v7 -; GFX11-NEXT: v_readfirstlane_b32 s12, v8 -; GFX11-NEXT: v_readfirstlane_b32 s13, v9 -; GFX11-NEXT: v_readfirstlane_b32 s15, v10 -; GFX11-NEXT: v_readfirstlane_b32 s14, v11 +; GFX11-NEXT: v_readfirstlane_b32 s0, v13 +; GFX11-NEXT: v_readfirstlane_b32 s1, v14 +; GFX11-NEXT: v_readfirstlane_b32 s2, v15 +; GFX11-NEXT: v_readfirstlane_b32 s3, v16 +; GFX11-NEXT: v_readfirstlane_b32 s4, v17 +; GFX11-NEXT: v_readfirstlane_b32 s5, v18 +; GFX11-NEXT: v_readfirstlane_b32 s6, v19 +; GFX11-NEXT: v_readfirstlane_b32 s7, v20 +; GFX11-NEXT: v_readfirstlane_b32 s8, v21 +; GFX11-NEXT: v_readfirstlane_b32 s9, v22 +; GFX11-NEXT: v_readfirstlane_b32 s10, v23 +; GFX11-NEXT: v_readfirstlane_b32 s11, v24 +; GFX11-NEXT: v_readfirstlane_b32 s12, v25 +; GFX11-NEXT: v_readfirstlane_b32 s13, v26 +; GFX11-NEXT: v_readfirstlane_b32 s14, v27 +; GFX11-NEXT: v_readfirstlane_b32 s15, v28 +; GFX11-NEXT: v_readfirstlane_b32 s16, v29 +; GFX11-NEXT: v_readfirstlane_b32 s17, v30 +; GFX11-NEXT: v_readfirstlane_b32 s18, v0 +; GFX11-NEXT: v_readfirstlane_b32 s19, v1 +; GFX11-NEXT: v_readfirstlane_b32 s20, v2 +; GFX11-NEXT: v_readfirstlane_b32 s21, v3 +; GFX11-NEXT: v_readfirstlane_b32 s22, v4 +; GFX11-NEXT: v_readfirstlane_b32 s23, v5 +; GFX11-NEXT: v_readfirstlane_b32 s24, v6 +; GFX11-NEXT: v_readfirstlane_b32 s25, v7 +; GFX11-NEXT: v_readfirstlane_b32 s26, v8 +; GFX11-NEXT: v_readfirstlane_b32 s27, v9 +; GFX11-NEXT: v_readfirstlane_b32 s29, v10 +; GFX11-NEXT: v_readfirstlane_b32 s28, v11 ; GFX11-NEXT: s_mov_b32 s94, 0 ; GFX11-NEXT: s_and_b32 s40, vcc_lo, exec_lo ; GFX11-NEXT: s_cbranch_scc0 .LBB13_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: s_lshr_b32 s40, s14, 16 -; GFX11-NEXT: s_lshr_b32 s41, s15, 16 -; GFX11-NEXT: s_lshr_b32 s42, s13, 16 -; GFX11-NEXT: s_lshr_b32 s43, s12, 16 -; GFX11-NEXT: s_lshr_b32 s44, s11, 16 -; GFX11-NEXT: s_lshr_b32 s45, s10, 16 -; GFX11-NEXT: s_lshr_b32 s46, s9, 16 -; GFX11-NEXT: s_lshr_b32 s47, s8, 16 -; GFX11-NEXT: s_lshr_b32 s56, s7, 16 -; GFX11-NEXT: s_lshr_b32 s57, s6, 16 -; GFX11-NEXT: s_lshr_b32 s58, s5, 16 -; GFX11-NEXT: s_lshr_b32 s59, s4, 16 -; GFX11-NEXT: s_lshr_b32 s60, s29, 16 -; GFX11-NEXT: s_lshr_b32 s61, s28, 16 -; GFX11-NEXT: s_lshr_b32 s62, s27, 16 -; GFX11-NEXT: s_lshr_b32 s63, s26, 16 -; GFX11-NEXT: s_lshr_b32 s72, s25, 16 -; GFX11-NEXT: s_lshr_b32 s73, s24, 16 -; GFX11-NEXT: s_lshr_b32 s74, s23, 16 -; GFX11-NEXT: s_lshr_b32 s75, s22, 16 -; GFX11-NEXT: s_lshr_b32 s76, s21, 16 -; GFX11-NEXT: s_lshr_b32 s77, s20, 16 -; GFX11-NEXT: s_lshr_b32 s78, s19, 16 -; GFX11-NEXT: s_lshr_b32 s79, s18, 16 -; GFX11-NEXT: s_lshr_b32 s88, s17, 16 -; GFX11-NEXT: s_lshr_b32 s89, s16, 16 +; GFX11-NEXT: s_lshr_b32 s40, s28, 16 +; GFX11-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-NEXT: s_lshr_b32 s42, s27, 16 +; GFX11-NEXT: s_lshr_b32 s43, s26, 16 +; GFX11-NEXT: s_lshr_b32 s44, s25, 16 +; GFX11-NEXT: s_lshr_b32 s45, s24, 16 +; GFX11-NEXT: s_lshr_b32 s46, s23, 16 +; GFX11-NEXT: s_lshr_b32 s47, s22, 16 +; GFX11-NEXT: s_lshr_b32 s56, s21, 16 +; GFX11-NEXT: s_lshr_b32 s57, s20, 16 +; GFX11-NEXT: s_lshr_b32 s58, s19, 16 +; GFX11-NEXT: s_lshr_b32 s59, s18, 16 +; GFX11-NEXT: s_lshr_b32 s60, s17, 16 +; GFX11-NEXT: s_lshr_b32 s61, s16, 16 +; GFX11-NEXT: s_lshr_b32 s62, s15, 16 +; GFX11-NEXT: s_lshr_b32 s63, s14, 16 +; GFX11-NEXT: s_lshr_b32 s72, s13, 16 +; GFX11-NEXT: s_lshr_b32 s73, s12, 16 +; GFX11-NEXT: s_lshr_b32 s74, s11, 16 +; GFX11-NEXT: s_lshr_b32 s75, s10, 16 +; GFX11-NEXT: s_lshr_b32 s76, s9, 16 +; GFX11-NEXT: s_lshr_b32 s77, s8, 16 +; GFX11-NEXT: s_lshr_b32 s78, s7, 16 +; GFX11-NEXT: s_lshr_b32 s79, s6, 16 +; GFX11-NEXT: s_lshr_b32 s88, s5, 16 +; GFX11-NEXT: s_lshr_b32 s89, s4, 16 ; GFX11-NEXT: s_lshr_b32 s90, s3, 16 ; GFX11-NEXT: s_lshr_b32 s91, s2, 16 ; GFX11-NEXT: s_lshr_b32 s92, s1, 16 @@ -4810,20 +4921,8 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s94 ; GFX11-NEXT: s_cbranch_vccnz .LBB13_3 ; GFX11-NEXT: .LBB13_2: ; %cmp.true -; GFX11-NEXT: s_add_i32 s14, s14, 3 -; GFX11-NEXT: s_add_i32 s15, s15, 3 -; GFX11-NEXT: s_add_i32 s13, s13, 3 -; GFX11-NEXT: s_add_i32 s12, s12, 3 -; GFX11-NEXT: s_add_i32 s11, s11, 3 -; GFX11-NEXT: s_add_i32 s10, s10, 3 -; GFX11-NEXT: s_add_i32 s9, s9, 3 -; GFX11-NEXT: s_add_i32 s8, s8, 3 -; GFX11-NEXT: s_add_i32 s7, s7, 3 -; GFX11-NEXT: s_add_i32 s6, s6, 3 -; GFX11-NEXT: s_add_i32 s5, s5, 3 -; GFX11-NEXT: s_add_i32 s4, s4, 3 -; GFX11-NEXT: s_add_i32 s29, s29, 3 ; GFX11-NEXT: s_add_i32 s28, s28, 3 +; GFX11-NEXT: s_add_i32 s29, s29, 3 ; GFX11-NEXT: s_add_i32 s27, s27, 3 ; GFX11-NEXT: s_add_i32 s26, s26, 3 ; GFX11-NEXT: s_add_i32 s25, s25, 3 @@ -4836,36 +4935,48 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; GFX11-NEXT: s_add_i32 s18, s18, 3 ; GFX11-NEXT: s_add_i32 s17, s17, 3 ; GFX11-NEXT: s_add_i32 s16, s16, 3 +; GFX11-NEXT: s_add_i32 s15, s15, 3 +; GFX11-NEXT: s_add_i32 s14, s14, 3 +; GFX11-NEXT: s_add_i32 s13, s13, 3 +; GFX11-NEXT: s_add_i32 s12, s12, 3 +; GFX11-NEXT: s_add_i32 s11, s11, 3 +; GFX11-NEXT: s_add_i32 s10, s10, 3 +; GFX11-NEXT: s_add_i32 s9, s9, 3 +; GFX11-NEXT: s_add_i32 s8, s8, 3 +; GFX11-NEXT: s_add_i32 s7, s7, 3 +; GFX11-NEXT: s_add_i32 s6, s6, 3 +; GFX11-NEXT: s_add_i32 s5, s5, 3 +; GFX11-NEXT: s_add_i32 s4, s4, 3 ; GFX11-NEXT: s_add_i32 s3, s3, 3 ; GFX11-NEXT: s_add_i32 s2, s2, 3 ; GFX11-NEXT: s_add_i32 s1, s1, 3 ; GFX11-NEXT: s_add_i32 s0, s0, 3 -; GFX11-NEXT: s_lshr_b32 s40, s14, 16 -; GFX11-NEXT: s_lshr_b32 s41, s15, 16 -; GFX11-NEXT: s_lshr_b32 s42, s13, 16 -; GFX11-NEXT: s_lshr_b32 s43, s12, 16 -; GFX11-NEXT: s_lshr_b32 s44, s11, 16 -; GFX11-NEXT: s_lshr_b32 s45, s10, 16 -; GFX11-NEXT: s_lshr_b32 s46, s9, 16 -; GFX11-NEXT: s_lshr_b32 s47, s8, 16 -; GFX11-NEXT: s_lshr_b32 s56, s7, 16 -; GFX11-NEXT: s_lshr_b32 s57, s6, 16 -; GFX11-NEXT: s_lshr_b32 s58, s5, 16 -; GFX11-NEXT: s_lshr_b32 s59, s4, 16 -; GFX11-NEXT: s_lshr_b32 s60, s29, 16 -; GFX11-NEXT: s_lshr_b32 s61, s28, 16 -; GFX11-NEXT: s_lshr_b32 s62, s27, 16 -; GFX11-NEXT: s_lshr_b32 s63, s26, 16 -; GFX11-NEXT: s_lshr_b32 s72, s25, 16 -; GFX11-NEXT: s_lshr_b32 s73, s24, 16 -; GFX11-NEXT: s_lshr_b32 s74, s23, 16 -; GFX11-NEXT: s_lshr_b32 s75, s22, 16 -; GFX11-NEXT: s_lshr_b32 s76, s21, 16 -; GFX11-NEXT: s_lshr_b32 s77, s20, 16 -; GFX11-NEXT: s_lshr_b32 s78, s19, 16 -; GFX11-NEXT: s_lshr_b32 s79, s18, 16 -; GFX11-NEXT: s_lshr_b32 s88, s17, 16 -; GFX11-NEXT: s_lshr_b32 s89, s16, 16 +; GFX11-NEXT: s_lshr_b32 s40, s28, 16 +; GFX11-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-NEXT: s_lshr_b32 s42, s27, 16 +; GFX11-NEXT: s_lshr_b32 s43, s26, 16 +; GFX11-NEXT: s_lshr_b32 s44, s25, 16 +; GFX11-NEXT: s_lshr_b32 s45, s24, 16 +; GFX11-NEXT: s_lshr_b32 s46, s23, 16 +; GFX11-NEXT: s_lshr_b32 s47, s22, 16 +; GFX11-NEXT: s_lshr_b32 s56, s21, 16 +; GFX11-NEXT: s_lshr_b32 s57, s20, 16 +; GFX11-NEXT: s_lshr_b32 s58, s19, 16 +; GFX11-NEXT: s_lshr_b32 s59, s18, 16 +; GFX11-NEXT: s_lshr_b32 s60, s17, 16 +; GFX11-NEXT: s_lshr_b32 s61, s16, 16 +; GFX11-NEXT: s_lshr_b32 s62, s15, 16 +; GFX11-NEXT: s_lshr_b32 s63, s14, 16 +; GFX11-NEXT: s_lshr_b32 s72, s13, 16 +; GFX11-NEXT: s_lshr_b32 s73, s12, 16 +; GFX11-NEXT: s_lshr_b32 s74, s11, 16 +; GFX11-NEXT: s_lshr_b32 s75, s10, 16 +; GFX11-NEXT: s_lshr_b32 s76, s9, 16 +; GFX11-NEXT: s_lshr_b32 s77, s8, 16 +; GFX11-NEXT: s_lshr_b32 s78, s7, 16 +; GFX11-NEXT: s_lshr_b32 s79, s6, 16 +; GFX11-NEXT: s_lshr_b32 s88, s5, 16 +; GFX11-NEXT: s_lshr_b32 s89, s4, 16 ; GFX11-NEXT: s_lshr_b32 s90, s3, 16 ; GFX11-NEXT: s_lshr_b32 s91, s2, 16 ; GFX11-NEXT: s_lshr_b32 s92, s1, 16 @@ -4876,47 +4987,47 @@ define inreg <60 x i16> @bitcast_v30i32_to_v60i16_scalar(<30 x i32> inreg %a, i3 ; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s92 ; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s91 ; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s90 -; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s89 -; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s88 -; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s79 -; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s78 -; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s77 -; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s76 -; GFX11-NEXT: s_pack_ll_b32_b16 s22, s22, s75 -; GFX11-NEXT: s_pack_ll_b32_b16 s23, s23, s74 -; GFX11-NEXT: s_pack_ll_b32_b16 s24, s24, s73 -; GFX11-NEXT: s_pack_ll_b32_b16 s25, s25, s72 -; GFX11-NEXT: s_pack_ll_b32_b16 s26, s26, s63 -; GFX11-NEXT: s_pack_ll_b32_b16 s27, s27, s62 -; GFX11-NEXT: s_pack_ll_b32_b16 s28, s28, s61 -; GFX11-NEXT: s_pack_ll_b32_b16 s29, s29, s60 -; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s59 -; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s58 -; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s57 -; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s56 -; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s47 -; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s46 -; GFX11-NEXT: s_pack_ll_b32_b16 s10, s10, s45 -; GFX11-NEXT: s_pack_ll_b32_b16 s11, s11, s44 -; GFX11-NEXT: s_pack_ll_b32_b16 s12, s12, s43 -; GFX11-NEXT: s_pack_ll_b32_b16 s13, s13, s42 -; GFX11-NEXT: s_pack_ll_b32_b16 s15, s15, s41 -; GFX11-NEXT: s_pack_ll_b32_b16 s14, s14, s40 +; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s89 +; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s88 +; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s79 +; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s78 +; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s77 +; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s76 +; GFX11-NEXT: s_pack_ll_b32_b16 s10, s10, s75 +; GFX11-NEXT: s_pack_ll_b32_b16 s11, s11, s74 +; GFX11-NEXT: s_pack_ll_b32_b16 s12, s12, s73 +; GFX11-NEXT: s_pack_ll_b32_b16 s13, s13, s72 +; GFX11-NEXT: s_pack_ll_b32_b16 s14, s14, s63 +; GFX11-NEXT: s_pack_ll_b32_b16 s15, s15, s62 +; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s61 +; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s60 +; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s59 +; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s58 +; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s57 +; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s56 +; GFX11-NEXT: s_pack_ll_b32_b16 s22, s22, s47 +; GFX11-NEXT: s_pack_ll_b32_b16 s23, s23, s46 +; GFX11-NEXT: s_pack_ll_b32_b16 s24, s24, s45 +; GFX11-NEXT: s_pack_ll_b32_b16 s25, s25, s44 +; GFX11-NEXT: s_pack_ll_b32_b16 s26, s26, s43 +; GFX11-NEXT: s_pack_ll_b32_b16 s27, s27, s42 +; GFX11-NEXT: s_pack_ll_b32_b16 s29, s29, s41 +; GFX11-NEXT: s_pack_ll_b32_b16 s28, s28, s40 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 -; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 -; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 -; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 -; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 -; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 -; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 -; GFX11-NEXT: v_dual_mov_b32 v18, s4 :: v_dual_mov_b32 v19, s5 -; GFX11-NEXT: v_dual_mov_b32 v20, s6 :: v_dual_mov_b32 v21, s7 -; GFX11-NEXT: v_dual_mov_b32 v22, s8 :: v_dual_mov_b32 v23, s9 -; GFX11-NEXT: v_dual_mov_b32 v24, s10 :: v_dual_mov_b32 v25, s11 -; GFX11-NEXT: v_dual_mov_b32 v26, s12 :: v_dual_mov_b32 v27, s13 -; GFX11-NEXT: v_dual_mov_b32 v28, s15 :: v_dual_mov_b32 v29, s14 +; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19 +; GFX11-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v21, s21 +; GFX11-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v23, s23 +; GFX11-NEXT: v_dual_mov_b32 v24, s24 :: v_dual_mov_b32 v25, s25 +; GFX11-NEXT: v_dual_mov_b32 v26, s26 :: v_dual_mov_b32 v27, s27 +; GFX11-NEXT: v_dual_mov_b32 v28, s29 :: v_dual_mov_b32 v29, s28 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: .LBB13_4: ; GFX11-NEXT: ; implicit-def: $sgpr93 @@ -5032,40 +5143,53 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) { ; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:8 ; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:4 ; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v2 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v4 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:52 +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:112 ; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:108 +; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v4 +; SI-NEXT: s_waitcnt vmcnt(4) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:44 ; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v6 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v8 -; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:104 ; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:100 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v10 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v6 +; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v8 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:36 +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:96 ; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:92 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v12 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v10 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:28 +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:88 ; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:84 -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v12 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v14 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:48 @@ -5096,27 +5220,10 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) { ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:56 ; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:64 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:52 -; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v28 -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v30 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:44 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:36 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:28 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v30 ; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] @@ -5201,7 +5308,6 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr30 ; SI-NEXT: ; kill: killed $vgpr30 ; SI-NEXT: ; implicit-def: $vgpr30 -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_and_b32_e32 v0, 0xffff, v55 ; SI-NEXT: v_and_b32_e32 v18, 0xffff, v61 ; SI-NEXT: ; kill: killed $vgpr30 @@ -5346,7 +5452,6 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) { ; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v55 ; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v61 ; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0 @@ -5473,7 +5578,7 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) { ; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24 ; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25 ; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26 -; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v27 +; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v27 ; SI-NEXT: v_add_i32_e32 v28, vcc, 0x30000, v28 ; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v29 ; SI-NEXT: .LBB14_4: ; %end @@ -5494,7 +5599,7 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) { ; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] ; ; VI-LABEL: bitcast_v60i16_to_v30i32: @@ -5776,7 +5881,6 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v61, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v29 -; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v28 @@ -5855,6 +5959,7 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v60 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v61 +; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -6019,6 +6124,9 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] ; GFX9-NEXT: s_cbranch_execz .LBB14_4 ; GFX9-NEXT: ; %bb.3: ; %cmp.true +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload @@ -6033,9 +6141,6 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload -; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v38, v61, s6 ; GFX9-NEXT: v_perm_b32 v1, v37, v60, s6 ; GFX9-NEXT: v_perm_b32 v2, v62, v59, s6 @@ -6054,6 +6159,10 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] +; GFX9-NEXT: s_waitcnt vmcnt(14) +; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; GFX9-NEXT: s_waitcnt vmcnt(15) ; GFX9-NEXT: v_perm_b32 v9, v9, v44, s6 ; GFX9-NEXT: s_waitcnt vmcnt(14) @@ -6082,10 +6191,6 @@ define <30 x i32> @bitcast_v60i16_to_v30i32(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: v_perm_b32 v21, v21, v48, s6 ; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: v_perm_b32 v22, v22, v39, s6 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] @@ -7241,304 +7346,115 @@ define inreg <30 x i32> @bitcast_v60i16_to_v30i32_scalar(<60 x i16> inreg %a, i3 ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v190, v6 :: v_dual_mov_b32 v185, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v186, v3 :: v_dual_mov_b32 v187, v2 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v1 :: v_dual_mov_b32 v189, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB15_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB15_3 ; GFX11-TRUE16-NEXT: .LBB15_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s40, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s41, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v189, v189, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v188, v188, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v187, v187, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v186, v186, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v185, v185, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v191, v191, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v190, v190, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, s6, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, s7, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, s8, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s9, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, s10, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, s11, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, s12, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, s13, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s14, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, s15, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, s16, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v30, v30, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s0, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s1, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s2, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, s3, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, s4, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v35, s5, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v44, s6, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v54, s7, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v65, s8, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v77, s9, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v90, s10, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v104, s11, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v119, s12, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v135, s13, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v152, s14, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v170, s15, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: .LBB15_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v170 :: v_dual_mov_b32 v18, v189 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v188 :: v_dual_mov_b32 v20, v187 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v186 :: v_dual_mov_b32 v22, v185 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v191 :: v_dual_mov_b32 v24, v190 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v191, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v190, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v189, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v188, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v187, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:316 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v119 :: v_dual_mov_b32 v27, v30 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB15_4: -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v64, v29 :: v_dual_mov_b32 v65, v28 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v66, v30 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v53, v26 :: v_dual_mov_b32 v54, v25 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v54 :: v_dual_mov_b32 v26, v53 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v65 :: v_dual_mov_b32 v29, v64 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v30, v66 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB15_2 ; ; GFX11-FAKE16-LABEL: bitcast_v60i16_to_v30i32_scalar: @@ -9056,13 +8972,41 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; SI-LABEL: bitcast_v30i32_to_v60f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v18, s16 +; SI-NEXT: v_mov_b32_e32 v19, s17 +; SI-NEXT: v_readfirstlane_b32 s40, v18 +; SI-NEXT: v_mov_b32_e32 v18, s18 +; SI-NEXT: v_readfirstlane_b32 s41, v19 +; SI-NEXT: v_mov_b32_e32 v19, s19 +; SI-NEXT: v_readfirstlane_b32 s42, v18 +; SI-NEXT: v_mov_b32_e32 v18, s20 +; SI-NEXT: v_readfirstlane_b32 s43, v19 +; SI-NEXT: v_mov_b32_e32 v19, s21 +; SI-NEXT: v_readfirstlane_b32 s44, v18 +; SI-NEXT: v_mov_b32_e32 v18, s22 +; SI-NEXT: v_readfirstlane_b32 s45, v19 +; SI-NEXT: v_mov_b32_e32 v19, s23 +; SI-NEXT: v_readfirstlane_b32 s23, v18 +; SI-NEXT: v_mov_b32_e32 v18, s24 +; SI-NEXT: v_readfirstlane_b32 s24, v19 +; SI-NEXT: v_mov_b32_e32 v19, s25 +; SI-NEXT: v_readfirstlane_b32 s25, v18 +; SI-NEXT: v_mov_b32_e32 v18, s26 +; SI-NEXT: v_readfirstlane_b32 s26, v19 +; SI-NEXT: v_mov_b32_e32 v19, s27 +; SI-NEXT: v_readfirstlane_b32 s27, v18 +; SI-NEXT: v_mov_b32_e32 v18, s28 +; SI-NEXT: v_readfirstlane_b32 s28, v19 +; SI-NEXT: v_mov_b32_e32 v19, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; SI-NEXT: v_readfirstlane_b32 s45, v1 -; SI-NEXT: v_readfirstlane_b32 s44, v2 -; SI-NEXT: v_readfirstlane_b32 s43, v3 -; SI-NEXT: v_readfirstlane_b32 s42, v4 -; SI-NEXT: v_readfirstlane_b32 s41, v5 -; SI-NEXT: v_readfirstlane_b32 s40, v6 +; SI-NEXT: v_readfirstlane_b32 s29, v18 +; SI-NEXT: v_readfirstlane_b32 s22, v19 +; SI-NEXT: v_readfirstlane_b32 s21, v1 +; SI-NEXT: v_readfirstlane_b32 s20, v2 +; SI-NEXT: v_readfirstlane_b32 s19, v3 +; SI-NEXT: v_readfirstlane_b32 s18, v4 +; SI-NEXT: v_readfirstlane_b32 s17, v5 +; SI-NEXT: v_readfirstlane_b32 s16, v6 ; SI-NEXT: v_readfirstlane_b32 s15, v7 ; SI-NEXT: v_readfirstlane_b32 s14, v8 ; SI-NEXT: v_readfirstlane_b32 s13, v9 @@ -9109,48 +9053,48 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v15, s4 ; SI-NEXT: s_lshr_b32 s4, s15, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v17, s4 -; SI-NEXT: s_lshr_b32 s4, s40, 16 +; SI-NEXT: s_lshr_b32 s4, s16, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v19, s4 -; SI-NEXT: s_lshr_b32 s4, s41, 16 +; SI-NEXT: s_lshr_b32 s4, s17, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v22, s4 -; SI-NEXT: s_lshr_b32 s4, s42, 16 +; SI-NEXT: s_lshr_b32 s4, s18, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v24, s4 -; SI-NEXT: s_lshr_b32 s4, s43, 16 +; SI-NEXT: s_lshr_b32 s4, s19, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v26, s4 -; SI-NEXT: s_lshr_b32 s4, s44, 16 +; SI-NEXT: s_lshr_b32 s4, s20, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v28, s4 -; SI-NEXT: s_lshr_b32 s4, s45, 16 +; SI-NEXT: s_lshr_b32 s4, s21, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v30, s4 -; SI-NEXT: s_lshr_b32 s4, s29, 16 +; SI-NEXT: s_lshr_b32 s4, s22, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v32, s4 -; SI-NEXT: s_lshr_b32 s4, s28, 16 +; SI-NEXT: s_lshr_b32 s4, s29, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v34, s4 -; SI-NEXT: s_lshr_b32 s4, s27, 16 +; SI-NEXT: s_lshr_b32 s4, s28, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v36, s4 -; SI-NEXT: s_lshr_b32 s4, s26, 16 +; SI-NEXT: s_lshr_b32 s4, s27, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v39, s4 -; SI-NEXT: s_lshr_b32 s4, s25, 16 +; SI-NEXT: s_lshr_b32 s4, s26, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v49, s4 -; SI-NEXT: s_lshr_b32 s4, s24, 16 +; SI-NEXT: s_lshr_b32 s4, s25, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v51, s4 -; SI-NEXT: s_lshr_b32 s4, s23, 16 +; SI-NEXT: s_lshr_b32 s4, s24, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v53, s4 -; SI-NEXT: s_lshr_b32 s4, s22, 16 +; SI-NEXT: s_lshr_b32 s4, s23, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v55, s4 -; SI-NEXT: s_lshr_b32 s4, s21, 16 +; SI-NEXT: s_lshr_b32 s4, s45, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v41, s4 -; SI-NEXT: s_lshr_b32 s4, s20, 16 +; SI-NEXT: s_lshr_b32 s4, s44, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v43, s4 -; SI-NEXT: s_lshr_b32 s4, s19, 16 +; SI-NEXT: s_lshr_b32 s4, s43, 16 ; SI-NEXT: s_waitcnt expcnt(6) ; SI-NEXT: v_cvt_f32_f16_e32 v46, s4 -; SI-NEXT: s_lshr_b32 s4, s18, 16 +; SI-NEXT: s_lshr_b32 s4, s42, 16 ; SI-NEXT: s_waitcnt expcnt(4) ; SI-NEXT: v_cvt_f32_f16_e32 v56, s4 -; SI-NEXT: s_lshr_b32 s4, s17, 16 +; SI-NEXT: s_lshr_b32 s4, s41, 16 ; SI-NEXT: s_waitcnt expcnt(2) ; SI-NEXT: v_cvt_f32_f16_e32 v58, s4 -; SI-NEXT: s_lshr_b32 s4, s16, 16 +; SI-NEXT: s_lshr_b32 s4, s40, 16 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f32_f16_e32 v60, s4 ; SI-NEXT: v_cvt_f32_f16_e32 v4, s9 @@ -9163,35 +9107,34 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v18, s13 ; SI-NEXT: v_cvt_f32_f16_e32 v20, s14 ; SI-NEXT: v_cvt_f32_f16_e32 v21, s15 -; SI-NEXT: v_cvt_f32_f16_e32 v23, s40 -; SI-NEXT: v_cvt_f32_f16_e32 v25, s41 -; SI-NEXT: v_cvt_f32_f16_e32 v27, s42 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s43 -; SI-NEXT: v_cvt_f32_f16_e32 v31, s44 -; SI-NEXT: v_cvt_f32_f16_e32 v33, s45 -; SI-NEXT: v_cvt_f32_f16_e32 v35, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v37, s28 -; SI-NEXT: v_cvt_f32_f16_e32 v38, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v48, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v50, s25 -; SI-NEXT: v_cvt_f32_f16_e32 v52, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v54, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v40, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v42, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v44, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v45, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v47, s18 -; SI-NEXT: v_cvt_f32_f16_e32 v57, s17 -; SI-NEXT: v_cvt_f32_f16_e32 v59, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v23, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v25, s17 +; SI-NEXT: v_cvt_f32_f16_e32 v27, s18 +; SI-NEXT: v_cvt_f32_f16_e32 v29, s19 +; SI-NEXT: v_cvt_f32_f16_e32 v31, s20 +; SI-NEXT: v_cvt_f32_f16_e32 v33, s21 +; SI-NEXT: v_cvt_f32_f16_e32 v35, s22 +; SI-NEXT: v_cvt_f32_f16_e32 v37, s29 +; SI-NEXT: v_cvt_f32_f16_e32 v38, s28 +; SI-NEXT: v_cvt_f32_f16_e32 v48, s27 +; SI-NEXT: v_cvt_f32_f16_e32 v50, s26 +; SI-NEXT: v_cvt_f32_f16_e32 v52, s25 +; SI-NEXT: v_cvt_f32_f16_e32 v54, s24 +; SI-NEXT: v_cvt_f32_f16_e32 v40, s23 +; SI-NEXT: v_cvt_f32_f16_e32 v42, s45 +; SI-NEXT: v_cvt_f32_f16_e32 v44, s44 +; SI-NEXT: v_cvt_f32_f16_e32 v45, s43 +; SI-NEXT: v_cvt_f32_f16_e32 v47, s42 +; SI-NEXT: v_cvt_f32_f16_e32 v57, s41 +; SI-NEXT: v_cvt_f32_f16_e32 v59, s40 ; SI-NEXT: s_cbranch_execnz .LBB17_3 ; SI-NEXT: .LBB17_2: ; %cmp.true -; SI-NEXT: s_add_i32 s16, s16, 3 -; SI-NEXT: s_add_i32 s17, s17, 3 -; SI-NEXT: s_add_i32 s18, s18, 3 -; SI-NEXT: s_add_i32 s19, s19, 3 -; SI-NEXT: s_add_i32 s20, s20, 3 -; SI-NEXT: s_add_i32 s21, s21, 3 -; SI-NEXT: s_add_i32 s22, s22, 3 +; SI-NEXT: s_add_i32 s40, s40, 3 +; SI-NEXT: s_add_i32 s41, s41, 3 +; SI-NEXT: s_add_i32 s42, s42, 3 +; SI-NEXT: s_add_i32 s43, s43, 3 +; SI-NEXT: s_add_i32 s44, s44, 3 +; SI-NEXT: s_add_i32 s45, s45, 3 ; SI-NEXT: s_add_i32 s23, s23, 3 ; SI-NEXT: s_add_i32 s24, s24, 3 ; SI-NEXT: s_add_i32 s25, s25, 3 @@ -9199,12 +9142,13 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; SI-NEXT: s_add_i32 s27, s27, 3 ; SI-NEXT: s_add_i32 s28, s28, 3 ; SI-NEXT: s_add_i32 s29, s29, 3 -; SI-NEXT: s_add_i32 s45, s45, 3 -; SI-NEXT: s_add_i32 s44, s44, 3 -; SI-NEXT: s_add_i32 s43, s43, 3 -; SI-NEXT: s_add_i32 s42, s42, 3 -; SI-NEXT: s_add_i32 s41, s41, 3 -; SI-NEXT: s_add_i32 s40, s40, 3 +; SI-NEXT: s_add_i32 s22, s22, 3 +; SI-NEXT: s_add_i32 s21, s21, 3 +; SI-NEXT: s_add_i32 s20, s20, 3 +; SI-NEXT: s_add_i32 s19, s19, 3 +; SI-NEXT: s_add_i32 s18, s18, 3 +; SI-NEXT: s_add_i32 s17, s17, 3 +; SI-NEXT: s_add_i32 s16, s16, 3 ; SI-NEXT: s_add_i32 s15, s15, 3 ; SI-NEXT: s_add_i32 s14, s14, 3 ; SI-NEXT: s_add_i32 s13, s13, 3 @@ -9215,26 +9159,26 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; SI-NEXT: s_add_i32 s7, s7, 3 ; SI-NEXT: s_add_i32 s6, s6, 3 ; SI-NEXT: s_add_i32 s9, s9, 3 -; SI-NEXT: s_lshr_b32 s4, s16, 16 -; SI-NEXT: s_lshr_b32 s5, s17, 16 -; SI-NEXT: s_lshr_b32 s46, s18, 16 -; SI-NEXT: s_lshr_b32 s47, s19, 16 -; SI-NEXT: s_lshr_b32 s56, s20, 16 -; SI-NEXT: s_lshr_b32 s57, s21, 16 -; SI-NEXT: s_lshr_b32 s58, s22, 16 -; SI-NEXT: s_lshr_b32 s59, s23, 16 -; SI-NEXT: s_lshr_b32 s60, s24, 16 -; SI-NEXT: s_lshr_b32 s61, s25, 16 -; SI-NEXT: s_lshr_b32 s62, s26, 16 -; SI-NEXT: s_lshr_b32 s63, s27, 16 -; SI-NEXT: s_lshr_b32 s72, s28, 16 -; SI-NEXT: s_lshr_b32 s73, s29, 16 -; SI-NEXT: s_lshr_b32 s74, s45, 16 -; SI-NEXT: s_lshr_b32 s75, s44, 16 -; SI-NEXT: s_lshr_b32 s76, s43, 16 -; SI-NEXT: s_lshr_b32 s77, s42, 16 -; SI-NEXT: s_lshr_b32 s78, s41, 16 -; SI-NEXT: s_lshr_b32 s79, s40, 16 +; SI-NEXT: s_lshr_b32 s4, s40, 16 +; SI-NEXT: s_lshr_b32 s5, s41, 16 +; SI-NEXT: s_lshr_b32 s46, s42, 16 +; SI-NEXT: s_lshr_b32 s47, s43, 16 +; SI-NEXT: s_lshr_b32 s56, s44, 16 +; SI-NEXT: s_lshr_b32 s57, s45, 16 +; SI-NEXT: s_lshr_b32 s58, s23, 16 +; SI-NEXT: s_lshr_b32 s59, s24, 16 +; SI-NEXT: s_lshr_b32 s60, s25, 16 +; SI-NEXT: s_lshr_b32 s61, s26, 16 +; SI-NEXT: s_lshr_b32 s62, s27, 16 +; SI-NEXT: s_lshr_b32 s63, s28, 16 +; SI-NEXT: s_lshr_b32 s72, s29, 16 +; SI-NEXT: s_lshr_b32 s73, s22, 16 +; SI-NEXT: s_lshr_b32 s74, s21, 16 +; SI-NEXT: s_lshr_b32 s75, s20, 16 +; SI-NEXT: s_lshr_b32 s76, s19, 16 +; SI-NEXT: s_lshr_b32 s77, s18, 16 +; SI-NEXT: s_lshr_b32 s78, s17, 16 +; SI-NEXT: s_lshr_b32 s79, s16, 16 ; SI-NEXT: s_lshr_b32 s88, s15, 16 ; SI-NEXT: s_lshr_b32 s89, s14, 16 ; SI-NEXT: s_lshr_b32 s90, s13, 16 @@ -9255,29 +9199,29 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v18, s13 ; SI-NEXT: v_cvt_f32_f16_e32 v20, s14 ; SI-NEXT: v_cvt_f32_f16_e32 v21, s15 -; SI-NEXT: v_cvt_f32_f16_e32 v23, s40 -; SI-NEXT: v_cvt_f32_f16_e32 v25, s41 -; SI-NEXT: v_cvt_f32_f16_e32 v27, s42 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s43 -; SI-NEXT: v_cvt_f32_f16_e32 v31, s44 -; SI-NEXT: v_cvt_f32_f16_e32 v33, s45 -; SI-NEXT: v_cvt_f32_f16_e32 v35, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v37, s28 -; SI-NEXT: v_cvt_f32_f16_e32 v38, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v48, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v50, s25 -; SI-NEXT: v_cvt_f32_f16_e32 v52, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v54, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v40, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v42, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v44, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v45, s19 +; SI-NEXT: v_cvt_f32_f16_e32 v23, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v25, s17 +; SI-NEXT: v_cvt_f32_f16_e32 v27, s18 +; SI-NEXT: v_cvt_f32_f16_e32 v29, s19 +; SI-NEXT: v_cvt_f32_f16_e32 v31, s20 +; SI-NEXT: v_cvt_f32_f16_e32 v33, s21 +; SI-NEXT: v_cvt_f32_f16_e32 v35, s22 +; SI-NEXT: v_cvt_f32_f16_e32 v37, s29 +; SI-NEXT: v_cvt_f32_f16_e32 v38, s28 +; SI-NEXT: v_cvt_f32_f16_e32 v48, s27 +; SI-NEXT: v_cvt_f32_f16_e32 v50, s26 +; SI-NEXT: v_cvt_f32_f16_e32 v52, s25 +; SI-NEXT: v_cvt_f32_f16_e32 v54, s24 +; SI-NEXT: v_cvt_f32_f16_e32 v40, s23 +; SI-NEXT: v_cvt_f32_f16_e32 v42, s45 +; SI-NEXT: v_cvt_f32_f16_e32 v44, s44 +; SI-NEXT: v_cvt_f32_f16_e32 v45, s43 ; SI-NEXT: s_waitcnt expcnt(5) -; SI-NEXT: v_cvt_f32_f16_e32 v47, s18 +; SI-NEXT: v_cvt_f32_f16_e32 v47, s42 ; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_cvt_f32_f16_e32 v57, s17 +; SI-NEXT: v_cvt_f32_f16_e32 v57, s41 ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_cvt_f32_f16_e32 v59, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v59, s40 ; SI-NEXT: v_cvt_f32_f16_e32 v1, vcc_hi ; SI-NEXT: v_cvt_f32_f16_e32 v2, vcc_lo ; SI-NEXT: v_cvt_f32_f16_e32 v3, s95 @@ -9605,18 +9549,46 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; VI-NEXT: s_mov_b64 exec, s[4:5] ; VI-NEXT: v_writelane_b32 v30, s30, 0 ; VI-NEXT: v_writelane_b32 v30, s31, 1 +; VI-NEXT: v_mov_b32_e32 v17, s16 +; VI-NEXT: v_mov_b32_e32 v18, s17 ; VI-NEXT: v_writelane_b32 v30, s34, 2 +; VI-NEXT: v_mov_b32_e32 v19, s18 +; VI-NEXT: v_readfirstlane_b32 s56, v17 +; VI-NEXT: v_mov_b32_e32 v17, s19 +; VI-NEXT: v_readfirstlane_b32 s47, v18 +; VI-NEXT: v_mov_b32_e32 v18, s20 ; VI-NEXT: v_writelane_b32 v30, s35, 3 +; VI-NEXT: v_readfirstlane_b32 s46, v19 +; VI-NEXT: v_mov_b32_e32 v19, s21 +; VI-NEXT: v_readfirstlane_b32 s45, v17 +; VI-NEXT: v_mov_b32_e32 v17, s22 +; VI-NEXT: v_readfirstlane_b32 s44, v18 +; VI-NEXT: v_mov_b32_e32 v18, s23 ; VI-NEXT: v_writelane_b32 v30, s36, 4 +; VI-NEXT: v_readfirstlane_b32 s43, v19 +; VI-NEXT: v_mov_b32_e32 v19, s24 +; VI-NEXT: v_readfirstlane_b32 s42, v17 +; VI-NEXT: v_mov_b32_e32 v17, s25 +; VI-NEXT: v_readfirstlane_b32 s41, v18 +; VI-NEXT: v_mov_b32_e32 v18, s26 ; VI-NEXT: v_writelane_b32 v30, s37, 5 +; VI-NEXT: v_readfirstlane_b32 s40, v19 +; VI-NEXT: v_mov_b32_e32 v19, s27 +; VI-NEXT: v_readfirstlane_b32 s26, v17 +; VI-NEXT: v_mov_b32_e32 v17, s28 +; VI-NEXT: v_readfirstlane_b32 s25, v18 +; VI-NEXT: v_mov_b32_e32 v18, s29 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 ; VI-NEXT: v_writelane_b32 v30, s38, 6 -; VI-NEXT: v_readfirstlane_b32 s45, v0 -; VI-NEXT: v_readfirstlane_b32 s44, v1 -; VI-NEXT: v_readfirstlane_b32 s43, v2 -; VI-NEXT: v_readfirstlane_b32 s42, v3 -; VI-NEXT: v_readfirstlane_b32 s41, v4 -; VI-NEXT: v_readfirstlane_b32 s40, v5 +; VI-NEXT: v_readfirstlane_b32 s24, v19 +; VI-NEXT: v_readfirstlane_b32 s23, v17 +; VI-NEXT: v_readfirstlane_b32 s22, v18 +; VI-NEXT: v_readfirstlane_b32 s21, v0 +; VI-NEXT: v_readfirstlane_b32 s20, v1 +; VI-NEXT: v_readfirstlane_b32 s19, v2 +; VI-NEXT: v_readfirstlane_b32 s18, v3 +; VI-NEXT: v_readfirstlane_b32 s17, v4 +; VI-NEXT: v_readfirstlane_b32 s16, v5 ; VI-NEXT: v_readfirstlane_b32 s15, v6 ; VI-NEXT: v_readfirstlane_b32 s14, v7 ; VI-NEXT: v_readfirstlane_b32 s13, v8 @@ -9631,9 +9603,9 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; VI-NEXT: v_writelane_b32 v30, s39, 7 ; VI-NEXT: s_cbranch_scc0 .LBB17_4 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_lshr_b32 s46, s7, 16 -; VI-NEXT: s_lshr_b32 s47, s6, 16 -; VI-NEXT: s_lshr_b32 s56, s8, 16 +; VI-NEXT: s_lshr_b32 s27, s7, 16 +; VI-NEXT: s_lshr_b32 s28, s6, 16 +; VI-NEXT: s_lshr_b32 s29, s8, 16 ; VI-NEXT: s_lshr_b32 s57, s9, 16 ; VI-NEXT: s_lshr_b32 s58, s10, 16 ; VI-NEXT: s_lshr_b32 s59, s11, 16 @@ -9641,26 +9613,26 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; VI-NEXT: s_lshr_b32 s61, s13, 16 ; VI-NEXT: s_lshr_b32 s62, s14, 16 ; VI-NEXT: s_lshr_b32 s63, s15, 16 -; VI-NEXT: s_lshr_b32 s72, s40, 16 -; VI-NEXT: s_lshr_b32 s73, s41, 16 -; VI-NEXT: s_lshr_b32 s74, s42, 16 -; VI-NEXT: s_lshr_b32 s75, s43, 16 -; VI-NEXT: s_lshr_b32 s76, s44, 16 -; VI-NEXT: s_lshr_b32 s77, s45, 16 -; VI-NEXT: s_lshr_b32 s78, s29, 16 -; VI-NEXT: s_lshr_b32 s79, s28, 16 -; VI-NEXT: s_lshr_b32 s88, s27, 16 -; VI-NEXT: s_lshr_b32 s89, s26, 16 -; VI-NEXT: s_lshr_b32 s90, s25, 16 -; VI-NEXT: s_lshr_b32 s91, s24, 16 -; VI-NEXT: s_lshr_b32 s30, s23, 16 -; VI-NEXT: s_lshr_b32 s31, s22, 16 -; VI-NEXT: s_lshr_b32 s34, s21, 16 -; VI-NEXT: s_lshr_b32 s35, s20, 16 -; VI-NEXT: s_lshr_b32 s36, s19, 16 -; VI-NEXT: s_lshr_b32 s37, s18, 16 -; VI-NEXT: s_lshr_b32 s38, s17, 16 -; VI-NEXT: s_lshr_b32 s39, s16, 16 +; VI-NEXT: s_lshr_b32 s72, s16, 16 +; VI-NEXT: s_lshr_b32 s73, s17, 16 +; VI-NEXT: s_lshr_b32 s74, s18, 16 +; VI-NEXT: s_lshr_b32 s75, s19, 16 +; VI-NEXT: s_lshr_b32 s76, s20, 16 +; VI-NEXT: s_lshr_b32 s77, s21, 16 +; VI-NEXT: s_lshr_b32 s78, s22, 16 +; VI-NEXT: s_lshr_b32 s79, s23, 16 +; VI-NEXT: s_lshr_b32 s88, s24, 16 +; VI-NEXT: s_lshr_b32 s89, s25, 16 +; VI-NEXT: s_lshr_b32 s90, s26, 16 +; VI-NEXT: s_lshr_b32 s91, s40, 16 +; VI-NEXT: s_lshr_b32 s30, s41, 16 +; VI-NEXT: s_lshr_b32 s31, s42, 16 +; VI-NEXT: s_lshr_b32 s34, s43, 16 +; VI-NEXT: s_lshr_b32 s35, s44, 16 +; VI-NEXT: s_lshr_b32 s36, s45, 16 +; VI-NEXT: s_lshr_b32 s37, s46, 16 +; VI-NEXT: s_lshr_b32 s38, s47, 16 +; VI-NEXT: s_lshr_b32 s39, s56, 16 ; VI-NEXT: s_cbranch_execnz .LBB17_3 ; VI-NEXT: .LBB17_2: ; %cmp.true ; VI-NEXT: s_add_i32 s7, s7, 3 @@ -9673,29 +9645,29 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; VI-NEXT: s_add_i32 s13, s13, 3 ; VI-NEXT: s_add_i32 s14, s14, 3 ; VI-NEXT: s_add_i32 s15, s15, 3 +; VI-NEXT: s_add_i32 s16, s16, 3 +; VI-NEXT: s_add_i32 s17, s17, 3 +; VI-NEXT: s_add_i32 s18, s18, 3 +; VI-NEXT: s_add_i32 s19, s19, 3 +; VI-NEXT: s_add_i32 s20, s20, 3 +; VI-NEXT: s_add_i32 s21, s21, 3 +; VI-NEXT: s_add_i32 s22, s22, 3 +; VI-NEXT: s_add_i32 s23, s23, 3 +; VI-NEXT: s_add_i32 s24, s24, 3 +; VI-NEXT: s_add_i32 s25, s25, 3 +; VI-NEXT: s_add_i32 s26, s26, 3 ; VI-NEXT: s_add_i32 s40, s40, 3 ; VI-NEXT: s_add_i32 s41, s41, 3 ; VI-NEXT: s_add_i32 s42, s42, 3 ; VI-NEXT: s_add_i32 s43, s43, 3 ; VI-NEXT: s_add_i32 s44, s44, 3 ; VI-NEXT: s_add_i32 s45, s45, 3 -; VI-NEXT: s_add_i32 s29, s29, 3 -; VI-NEXT: s_add_i32 s28, s28, 3 -; VI-NEXT: s_add_i32 s27, s27, 3 -; VI-NEXT: s_add_i32 s26, s26, 3 -; VI-NEXT: s_add_i32 s25, s25, 3 -; VI-NEXT: s_add_i32 s24, s24, 3 -; VI-NEXT: s_add_i32 s23, s23, 3 -; VI-NEXT: s_add_i32 s22, s22, 3 -; VI-NEXT: s_add_i32 s21, s21, 3 -; VI-NEXT: s_add_i32 s20, s20, 3 -; VI-NEXT: s_add_i32 s19, s19, 3 -; VI-NEXT: s_add_i32 s18, s18, 3 -; VI-NEXT: s_add_i32 s17, s17, 3 -; VI-NEXT: s_add_i32 s16, s16, 3 -; VI-NEXT: s_lshr_b32 s46, s7, 16 -; VI-NEXT: s_lshr_b32 s47, s6, 16 -; VI-NEXT: s_lshr_b32 s56, s8, 16 +; VI-NEXT: s_add_i32 s46, s46, 3 +; VI-NEXT: s_add_i32 s47, s47, 3 +; VI-NEXT: s_add_i32 s56, s56, 3 +; VI-NEXT: s_lshr_b32 s27, s7, 16 +; VI-NEXT: s_lshr_b32 s28, s6, 16 +; VI-NEXT: s_lshr_b32 s29, s8, 16 ; VI-NEXT: s_lshr_b32 s57, s9, 16 ; VI-NEXT: s_lshr_b32 s58, s10, 16 ; VI-NEXT: s_lshr_b32 s59, s11, 16 @@ -9703,137 +9675,137 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; VI-NEXT: s_lshr_b32 s61, s13, 16 ; VI-NEXT: s_lshr_b32 s62, s14, 16 ; VI-NEXT: s_lshr_b32 s63, s15, 16 -; VI-NEXT: s_lshr_b32 s72, s40, 16 -; VI-NEXT: s_lshr_b32 s73, s41, 16 -; VI-NEXT: s_lshr_b32 s74, s42, 16 -; VI-NEXT: s_lshr_b32 s75, s43, 16 -; VI-NEXT: s_lshr_b32 s76, s44, 16 -; VI-NEXT: s_lshr_b32 s77, s45, 16 -; VI-NEXT: s_lshr_b32 s78, s29, 16 -; VI-NEXT: s_lshr_b32 s79, s28, 16 -; VI-NEXT: s_lshr_b32 s88, s27, 16 -; VI-NEXT: s_lshr_b32 s89, s26, 16 -; VI-NEXT: s_lshr_b32 s90, s25, 16 -; VI-NEXT: s_lshr_b32 s91, s24, 16 -; VI-NEXT: s_lshr_b32 s30, s23, 16 -; VI-NEXT: s_lshr_b32 s31, s22, 16 -; VI-NEXT: s_lshr_b32 s34, s21, 16 -; VI-NEXT: s_lshr_b32 s35, s20, 16 -; VI-NEXT: s_lshr_b32 s36, s19, 16 -; VI-NEXT: s_lshr_b32 s37, s18, 16 -; VI-NEXT: s_lshr_b32 s38, s17, 16 -; VI-NEXT: s_lshr_b32 s39, s16, 16 +; VI-NEXT: s_lshr_b32 s72, s16, 16 +; VI-NEXT: s_lshr_b32 s73, s17, 16 +; VI-NEXT: s_lshr_b32 s74, s18, 16 +; VI-NEXT: s_lshr_b32 s75, s19, 16 +; VI-NEXT: s_lshr_b32 s76, s20, 16 +; VI-NEXT: s_lshr_b32 s77, s21, 16 +; VI-NEXT: s_lshr_b32 s78, s22, 16 +; VI-NEXT: s_lshr_b32 s79, s23, 16 +; VI-NEXT: s_lshr_b32 s88, s24, 16 +; VI-NEXT: s_lshr_b32 s89, s25, 16 +; VI-NEXT: s_lshr_b32 s90, s26, 16 +; VI-NEXT: s_lshr_b32 s91, s40, 16 +; VI-NEXT: s_lshr_b32 s30, s41, 16 +; VI-NEXT: s_lshr_b32 s31, s42, 16 +; VI-NEXT: s_lshr_b32 s34, s43, 16 +; VI-NEXT: s_lshr_b32 s35, s44, 16 +; VI-NEXT: s_lshr_b32 s36, s45, 16 +; VI-NEXT: s_lshr_b32 s37, s46, 16 +; VI-NEXT: s_lshr_b32 s38, s47, 16 +; VI-NEXT: s_lshr_b32 s39, s56, 16 ; VI-NEXT: .LBB17_3: ; %end -; VI-NEXT: s_and_b32 s4, 0xffff, s16 +; VI-NEXT: s_and_b32 s4, 0xffff, s56 ; VI-NEXT: s_lshl_b32 s5, s39, 16 ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_and_b32 s5, 0xffff, s17 -; VI-NEXT: s_lshl_b32 s16, s38, 16 -; VI-NEXT: s_or_b32 s5, s5, s16 -; VI-NEXT: s_and_b32 s16, 0xffff, s18 -; VI-NEXT: s_lshl_b32 s17, s37, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, 0xffff, s19 -; VI-NEXT: s_lshl_b32 s18, s36, 16 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s18, 0xffff, s20 -; VI-NEXT: s_lshl_b32 s19, s35, 16 -; VI-NEXT: s_or_b32 s18, s18, s19 -; VI-NEXT: s_and_b32 s19, 0xffff, s21 -; VI-NEXT: s_lshl_b32 s20, s34, 16 -; VI-NEXT: s_or_b32 s19, s19, s20 -; VI-NEXT: s_and_b32 s20, 0xffff, s22 -; VI-NEXT: s_lshl_b32 s21, s31, 16 -; VI-NEXT: s_or_b32 s20, s20, s21 -; VI-NEXT: s_and_b32 s21, 0xffff, s23 -; VI-NEXT: s_lshl_b32 s22, s30, 16 -; VI-NEXT: s_or_b32 s21, s21, s22 -; VI-NEXT: s_and_b32 s22, 0xffff, s24 -; VI-NEXT: s_lshl_b32 s23, s91, 16 -; VI-NEXT: s_or_b32 s22, s22, s23 -; VI-NEXT: s_and_b32 s23, 0xffff, s25 -; VI-NEXT: s_lshl_b32 s24, s90, 16 -; VI-NEXT: s_or_b32 s23, s23, s24 -; VI-NEXT: s_and_b32 s24, 0xffff, s26 -; VI-NEXT: s_lshl_b32 s25, s89, 16 -; VI-NEXT: s_or_b32 s24, s24, s25 -; VI-NEXT: s_and_b32 s25, 0xffff, s27 -; VI-NEXT: s_lshl_b32 s26, s88, 16 -; VI-NEXT: s_or_b32 s25, s25, s26 -; VI-NEXT: s_and_b32 s26, 0xffff, s28 -; VI-NEXT: s_lshl_b32 s27, s79, 16 -; VI-NEXT: s_or_b32 s26, s26, s27 -; VI-NEXT: s_and_b32 s27, 0xffff, s29 -; VI-NEXT: s_lshl_b32 s28, s78, 16 -; VI-NEXT: s_or_b32 s27, s27, s28 -; VI-NEXT: s_and_b32 s28, 0xffff, s45 -; VI-NEXT: s_lshl_b32 s29, s77, 16 -; VI-NEXT: s_or_b32 s28, s28, s29 -; VI-NEXT: s_and_b32 s29, 0xffff, s44 -; VI-NEXT: s_lshl_b32 s44, s76, 16 -; VI-NEXT: s_or_b32 s29, s29, s44 +; VI-NEXT: s_and_b32 s5, 0xffff, s47 +; VI-NEXT: s_lshl_b32 s47, s38, 16 +; VI-NEXT: s_or_b32 s5, s5, s47 +; VI-NEXT: s_and_b32 s46, 0xffff, s46 +; VI-NEXT: s_lshl_b32 s47, s37, 16 +; VI-NEXT: s_or_b32 s46, s46, s47 +; VI-NEXT: s_and_b32 s45, 0xffff, s45 +; VI-NEXT: s_lshl_b32 s47, s36, 16 +; VI-NEXT: s_or_b32 s45, s45, s47 +; VI-NEXT: s_and_b32 s44, 0xffff, s44 +; VI-NEXT: s_lshl_b32 s47, s35, 16 +; VI-NEXT: s_or_b32 s44, s44, s47 ; VI-NEXT: s_and_b32 s43, 0xffff, s43 -; VI-NEXT: s_lshl_b32 s44, s75, 16 -; VI-NEXT: s_or_b32 s43, s43, s44 +; VI-NEXT: s_lshl_b32 s47, s34, 16 +; VI-NEXT: s_or_b32 s43, s43, s47 ; VI-NEXT: s_and_b32 s42, 0xffff, s42 -; VI-NEXT: s_lshl_b32 s44, s74, 16 -; VI-NEXT: s_or_b32 s42, s42, s44 +; VI-NEXT: s_lshl_b32 s47, s31, 16 +; VI-NEXT: s_or_b32 s42, s42, s47 ; VI-NEXT: s_and_b32 s41, 0xffff, s41 -; VI-NEXT: s_lshl_b32 s44, s73, 16 -; VI-NEXT: s_or_b32 s41, s41, s44 +; VI-NEXT: s_lshl_b32 s47, s30, 16 +; VI-NEXT: s_or_b32 s41, s41, s47 ; VI-NEXT: s_and_b32 s40, 0xffff, s40 -; VI-NEXT: s_lshl_b32 s44, s72, 16 -; VI-NEXT: s_or_b32 s40, s40, s44 +; VI-NEXT: s_lshl_b32 s47, s91, 16 +; VI-NEXT: s_or_b32 s40, s40, s47 +; VI-NEXT: s_and_b32 s26, 0xffff, s26 +; VI-NEXT: s_lshl_b32 s47, s90, 16 +; VI-NEXT: s_or_b32 s26, s26, s47 +; VI-NEXT: s_and_b32 s25, 0xffff, s25 +; VI-NEXT: s_lshl_b32 s47, s89, 16 +; VI-NEXT: s_or_b32 s25, s25, s47 +; VI-NEXT: s_and_b32 s24, 0xffff, s24 +; VI-NEXT: s_lshl_b32 s47, s88, 16 +; VI-NEXT: s_or_b32 s24, s24, s47 +; VI-NEXT: s_and_b32 s23, 0xffff, s23 +; VI-NEXT: s_lshl_b32 s47, s79, 16 +; VI-NEXT: s_or_b32 s23, s23, s47 +; VI-NEXT: s_and_b32 s22, 0xffff, s22 +; VI-NEXT: s_lshl_b32 s47, s78, 16 +; VI-NEXT: s_or_b32 s22, s22, s47 +; VI-NEXT: s_and_b32 s21, 0xffff, s21 +; VI-NEXT: s_lshl_b32 s47, s77, 16 +; VI-NEXT: s_or_b32 s21, s21, s47 +; VI-NEXT: s_and_b32 s20, 0xffff, s20 +; VI-NEXT: s_lshl_b32 s47, s76, 16 +; VI-NEXT: s_or_b32 s20, s20, s47 +; VI-NEXT: s_and_b32 s19, 0xffff, s19 +; VI-NEXT: s_lshl_b32 s47, s75, 16 +; VI-NEXT: s_or_b32 s19, s19, s47 +; VI-NEXT: s_and_b32 s18, 0xffff, s18 +; VI-NEXT: s_lshl_b32 s47, s74, 16 +; VI-NEXT: s_or_b32 s18, s18, s47 +; VI-NEXT: s_and_b32 s17, 0xffff, s17 +; VI-NEXT: s_lshl_b32 s47, s73, 16 +; VI-NEXT: s_or_b32 s17, s17, s47 +; VI-NEXT: s_and_b32 s16, 0xffff, s16 +; VI-NEXT: s_lshl_b32 s47, s72, 16 +; VI-NEXT: s_or_b32 s16, s16, s47 ; VI-NEXT: s_and_b32 s15, 0xffff, s15 -; VI-NEXT: s_lshl_b32 s44, s63, 16 -; VI-NEXT: s_or_b32 s15, s15, s44 +; VI-NEXT: s_lshl_b32 s47, s63, 16 +; VI-NEXT: s_or_b32 s15, s15, s47 ; VI-NEXT: s_and_b32 s14, 0xffff, s14 -; VI-NEXT: s_lshl_b32 s44, s62, 16 -; VI-NEXT: s_or_b32 s14, s14, s44 +; VI-NEXT: s_lshl_b32 s47, s62, 16 +; VI-NEXT: s_or_b32 s14, s14, s47 ; VI-NEXT: s_and_b32 s13, 0xffff, s13 -; VI-NEXT: s_lshl_b32 s44, s61, 16 -; VI-NEXT: s_or_b32 s13, s13, s44 +; VI-NEXT: s_lshl_b32 s47, s61, 16 +; VI-NEXT: s_or_b32 s13, s13, s47 ; VI-NEXT: s_and_b32 s12, 0xffff, s12 -; VI-NEXT: s_lshl_b32 s44, s60, 16 -; VI-NEXT: s_or_b32 s12, s12, s44 +; VI-NEXT: s_lshl_b32 s47, s60, 16 +; VI-NEXT: s_or_b32 s12, s12, s47 ; VI-NEXT: s_and_b32 s11, 0xffff, s11 -; VI-NEXT: s_lshl_b32 s44, s59, 16 -; VI-NEXT: s_or_b32 s11, s11, s44 +; VI-NEXT: s_lshl_b32 s47, s59, 16 +; VI-NEXT: s_or_b32 s11, s11, s47 ; VI-NEXT: s_and_b32 s10, 0xffff, s10 -; VI-NEXT: s_lshl_b32 s44, s58, 16 -; VI-NEXT: s_or_b32 s10, s10, s44 +; VI-NEXT: s_lshl_b32 s47, s58, 16 +; VI-NEXT: s_or_b32 s10, s10, s47 ; VI-NEXT: s_and_b32 s9, 0xffff, s9 -; VI-NEXT: s_lshl_b32 s44, s57, 16 -; VI-NEXT: s_or_b32 s9, s9, s44 +; VI-NEXT: s_lshl_b32 s47, s57, 16 ; VI-NEXT: s_and_b32 s8, 0xffff, s8 -; VI-NEXT: s_lshl_b32 s44, s56, 16 -; VI-NEXT: s_or_b32 s8, s8, s44 +; VI-NEXT: s_lshl_b32 s29, s29, 16 ; VI-NEXT: s_and_b32 s6, 0xffff, s6 -; VI-NEXT: s_lshl_b32 s44, s47, 16 -; VI-NEXT: s_or_b32 s6, s6, s44 +; VI-NEXT: s_lshl_b32 s28, s28, 16 ; VI-NEXT: s_and_b32 s7, 0xffff, s7 -; VI-NEXT: s_lshl_b32 s44, s46, 16 -; VI-NEXT: s_or_b32 s7, s7, s44 +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s9, s9, s47 +; VI-NEXT: s_or_b32 s8, s8, s29 +; VI-NEXT: s_or_b32 s6, s6, s28 +; VI-NEXT: s_or_b32 s7, s7, s27 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s5 -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: v_mov_b32_e32 v3, s17 -; VI-NEXT: v_mov_b32_e32 v4, s18 -; VI-NEXT: v_mov_b32_e32 v5, s19 -; VI-NEXT: v_mov_b32_e32 v6, s20 -; VI-NEXT: v_mov_b32_e32 v7, s21 -; VI-NEXT: v_mov_b32_e32 v8, s22 -; VI-NEXT: v_mov_b32_e32 v9, s23 -; VI-NEXT: v_mov_b32_e32 v10, s24 -; VI-NEXT: v_mov_b32_e32 v11, s25 -; VI-NEXT: v_mov_b32_e32 v12, s26 -; VI-NEXT: v_mov_b32_e32 v13, s27 -; VI-NEXT: v_mov_b32_e32 v14, s28 -; VI-NEXT: v_mov_b32_e32 v15, s29 -; VI-NEXT: v_mov_b32_e32 v16, s43 -; VI-NEXT: v_mov_b32_e32 v17, s42 -; VI-NEXT: v_mov_b32_e32 v18, s41 -; VI-NEXT: v_mov_b32_e32 v19, s40 +; VI-NEXT: v_mov_b32_e32 v2, s46 +; VI-NEXT: v_mov_b32_e32 v3, s45 +; VI-NEXT: v_mov_b32_e32 v4, s44 +; VI-NEXT: v_mov_b32_e32 v5, s43 +; VI-NEXT: v_mov_b32_e32 v6, s42 +; VI-NEXT: v_mov_b32_e32 v7, s41 +; VI-NEXT: v_mov_b32_e32 v8, s40 +; VI-NEXT: v_mov_b32_e32 v9, s26 +; VI-NEXT: v_mov_b32_e32 v10, s25 +; VI-NEXT: v_mov_b32_e32 v11, s24 +; VI-NEXT: v_mov_b32_e32 v12, s23 +; VI-NEXT: v_mov_b32_e32 v13, s22 +; VI-NEXT: v_mov_b32_e32 v14, s21 +; VI-NEXT: v_mov_b32_e32 v15, s20 +; VI-NEXT: v_mov_b32_e32 v16, s19 +; VI-NEXT: v_mov_b32_e32 v17, s18 +; VI-NEXT: v_mov_b32_e32 v18, s17 +; VI-NEXT: v_mov_b32_e32 v19, s16 ; VI-NEXT: v_mov_b32_e32 v20, s15 ; VI-NEXT: v_mov_b32_e32 v21, s14 ; VI-NEXT: v_mov_b32_e32 v22, s13 @@ -9885,9 +9857,9 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; VI-NEXT: ; implicit-def: $sgpr59 ; VI-NEXT: ; implicit-def: $sgpr58 ; VI-NEXT: ; implicit-def: $sgpr57 -; VI-NEXT: ; implicit-def: $sgpr56 -; VI-NEXT: ; implicit-def: $sgpr47 -; VI-NEXT: ; implicit-def: $sgpr46 +; VI-NEXT: ; implicit-def: $sgpr29 +; VI-NEXT: ; implicit-def: $sgpr28 +; VI-NEXT: ; implicit-def: $sgpr27 ; VI-NEXT: s_branch .LBB17_2 ; ; GFX9-LABEL: bitcast_v30i32_to_v60f16_scalar: @@ -9896,20 +9868,48 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] +; GFX9-NEXT: v_mov_b32_e32 v17, s16 +; GFX9-NEXT: v_mov_b32_e32 v18, s17 +; GFX9-NEXT: v_mov_b32_e32 v19, s18 +; GFX9-NEXT: v_readfirstlane_b32 s6, v17 +; GFX9-NEXT: v_mov_b32_e32 v17, s19 +; GFX9-NEXT: v_readfirstlane_b32 s7, v18 +; GFX9-NEXT: v_mov_b32_e32 v18, s20 +; GFX9-NEXT: v_readfirstlane_b32 s8, v19 +; GFX9-NEXT: v_mov_b32_e32 v19, s21 +; GFX9-NEXT: v_readfirstlane_b32 s9, v17 +; GFX9-NEXT: v_mov_b32_e32 v17, s22 +; GFX9-NEXT: v_readfirstlane_b32 s10, v18 +; GFX9-NEXT: v_mov_b32_e32 v18, s23 ; GFX9-NEXT: v_writelane_b32 v30, s30, 0 +; GFX9-NEXT: v_readfirstlane_b32 s11, v19 +; GFX9-NEXT: v_mov_b32_e32 v19, s24 +; GFX9-NEXT: v_readfirstlane_b32 s12, v17 +; GFX9-NEXT: v_mov_b32_e32 v17, s25 +; GFX9-NEXT: v_readfirstlane_b32 s13, v18 +; GFX9-NEXT: v_mov_b32_e32 v18, s26 ; GFX9-NEXT: v_writelane_b32 v30, s31, 1 +; GFX9-NEXT: v_readfirstlane_b32 s14, v19 +; GFX9-NEXT: v_mov_b32_e32 v19, s27 +; GFX9-NEXT: v_readfirstlane_b32 s15, v17 +; GFX9-NEXT: v_mov_b32_e32 v17, s28 +; GFX9-NEXT: v_readfirstlane_b32 s16, v18 +; GFX9-NEXT: v_mov_b32_e32 v18, s29 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 ; GFX9-NEXT: v_writelane_b32 v30, s34, 2 -; GFX9-NEXT: v_readfirstlane_b32 s6, v0 -; GFX9-NEXT: v_readfirstlane_b32 s7, v1 -; GFX9-NEXT: v_readfirstlane_b32 s8, v2 -; GFX9-NEXT: v_readfirstlane_b32 s9, v3 -; GFX9-NEXT: v_readfirstlane_b32 s10, v4 -; GFX9-NEXT: v_readfirstlane_b32 s11, v5 -; GFX9-NEXT: v_readfirstlane_b32 s12, v6 -; GFX9-NEXT: v_readfirstlane_b32 s13, v7 -; GFX9-NEXT: v_readfirstlane_b32 s14, v8 -; GFX9-NEXT: v_readfirstlane_b32 s15, v9 +; GFX9-NEXT: v_readfirstlane_b32 s17, v19 +; GFX9-NEXT: v_readfirstlane_b32 s18, v17 +; GFX9-NEXT: v_readfirstlane_b32 s19, v18 +; GFX9-NEXT: v_readfirstlane_b32 s20, v0 +; GFX9-NEXT: v_readfirstlane_b32 s21, v1 +; GFX9-NEXT: v_readfirstlane_b32 s22, v2 +; GFX9-NEXT: v_readfirstlane_b32 s23, v3 +; GFX9-NEXT: v_readfirstlane_b32 s24, v4 +; GFX9-NEXT: v_readfirstlane_b32 s25, v5 +; GFX9-NEXT: v_readfirstlane_b32 s26, v6 +; GFX9-NEXT: v_readfirstlane_b32 s27, v7 +; GFX9-NEXT: v_readfirstlane_b32 s28, v8 +; GFX9-NEXT: v_readfirstlane_b32 s29, v9 ; GFX9-NEXT: v_readfirstlane_b32 s40, v10 ; GFX9-NEXT: v_readfirstlane_b32 s41, v11 ; GFX9-NEXT: v_readfirstlane_b32 s42, v12 @@ -9926,30 +9926,30 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; GFX9-NEXT: s_lshr_b32 s57, s42, 16 ; GFX9-NEXT: s_lshr_b32 s58, s41, 16 ; GFX9-NEXT: s_lshr_b32 s59, s40, 16 -; GFX9-NEXT: s_lshr_b32 s60, s15, 16 -; GFX9-NEXT: s_lshr_b32 s61, s14, 16 -; GFX9-NEXT: s_lshr_b32 s62, s13, 16 -; GFX9-NEXT: s_lshr_b32 s63, s12, 16 -; GFX9-NEXT: s_lshr_b32 s72, s11, 16 -; GFX9-NEXT: s_lshr_b32 s73, s10, 16 -; GFX9-NEXT: s_lshr_b32 s74, s9, 16 -; GFX9-NEXT: s_lshr_b32 s75, s8, 16 -; GFX9-NEXT: s_lshr_b32 s76, s7, 16 -; GFX9-NEXT: s_lshr_b32 s77, s6, 16 -; GFX9-NEXT: s_lshr_b32 s78, s29, 16 -; GFX9-NEXT: s_lshr_b32 s79, s28, 16 -; GFX9-NEXT: s_lshr_b32 s88, s27, 16 -; GFX9-NEXT: s_lshr_b32 s89, s26, 16 -; GFX9-NEXT: s_lshr_b32 s90, s25, 16 -; GFX9-NEXT: s_lshr_b32 s91, s24, 16 -; GFX9-NEXT: s_lshr_b32 s92, s23, 16 -; GFX9-NEXT: s_lshr_b32 s93, s22, 16 -; GFX9-NEXT: s_lshr_b32 s94, s21, 16 -; GFX9-NEXT: s_lshr_b32 s95, s20, 16 -; GFX9-NEXT: s_lshr_b32 s30, s19, 16 -; GFX9-NEXT: s_lshr_b32 s31, s18, 16 -; GFX9-NEXT: s_lshr_b32 s34, s17, 16 -; GFX9-NEXT: s_lshr_b32 s35, s16, 16 +; GFX9-NEXT: s_lshr_b32 s60, s29, 16 +; GFX9-NEXT: s_lshr_b32 s61, s28, 16 +; GFX9-NEXT: s_lshr_b32 s62, s27, 16 +; GFX9-NEXT: s_lshr_b32 s63, s26, 16 +; GFX9-NEXT: s_lshr_b32 s72, s25, 16 +; GFX9-NEXT: s_lshr_b32 s73, s24, 16 +; GFX9-NEXT: s_lshr_b32 s74, s23, 16 +; GFX9-NEXT: s_lshr_b32 s75, s22, 16 +; GFX9-NEXT: s_lshr_b32 s76, s21, 16 +; GFX9-NEXT: s_lshr_b32 s77, s20, 16 +; GFX9-NEXT: s_lshr_b32 s78, s19, 16 +; GFX9-NEXT: s_lshr_b32 s79, s18, 16 +; GFX9-NEXT: s_lshr_b32 s88, s17, 16 +; GFX9-NEXT: s_lshr_b32 s89, s16, 16 +; GFX9-NEXT: s_lshr_b32 s90, s15, 16 +; GFX9-NEXT: s_lshr_b32 s91, s14, 16 +; GFX9-NEXT: s_lshr_b32 s92, s13, 16 +; GFX9-NEXT: s_lshr_b32 s93, s12, 16 +; GFX9-NEXT: s_lshr_b32 s94, s11, 16 +; GFX9-NEXT: s_lshr_b32 s95, s10, 16 +; GFX9-NEXT: s_lshr_b32 s30, s9, 16 +; GFX9-NEXT: s_lshr_b32 s31, s8, 16 +; GFX9-NEXT: s_lshr_b32 s34, s7, 16 +; GFX9-NEXT: s_lshr_b32 s35, s6, 16 ; GFX9-NEXT: s_cbranch_execnz .LBB17_3 ; GFX9-NEXT: .LBB17_2: ; %cmp.true ; GFX9-NEXT: s_add_i32 s45, s45, 3 @@ -9958,16 +9958,6 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; GFX9-NEXT: s_add_i32 s42, s42, 3 ; GFX9-NEXT: s_add_i32 s41, s41, 3 ; GFX9-NEXT: s_add_i32 s40, s40, 3 -; GFX9-NEXT: s_add_i32 s15, s15, 3 -; GFX9-NEXT: s_add_i32 s14, s14, 3 -; GFX9-NEXT: s_add_i32 s13, s13, 3 -; GFX9-NEXT: s_add_i32 s12, s12, 3 -; GFX9-NEXT: s_add_i32 s11, s11, 3 -; GFX9-NEXT: s_add_i32 s10, s10, 3 -; GFX9-NEXT: s_add_i32 s9, s9, 3 -; GFX9-NEXT: s_add_i32 s8, s8, 3 -; GFX9-NEXT: s_add_i32 s7, s7, 3 -; GFX9-NEXT: s_add_i32 s6, s6, 3 ; GFX9-NEXT: s_add_i32 s29, s29, 3 ; GFX9-NEXT: s_add_i32 s28, s28, 3 ; GFX9-NEXT: s_add_i32 s27, s27, 3 @@ -9982,61 +9972,71 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; GFX9-NEXT: s_add_i32 s18, s18, 3 ; GFX9-NEXT: s_add_i32 s17, s17, 3 ; GFX9-NEXT: s_add_i32 s16, s16, 3 +; GFX9-NEXT: s_add_i32 s15, s15, 3 +; GFX9-NEXT: s_add_i32 s14, s14, 3 +; GFX9-NEXT: s_add_i32 s13, s13, 3 +; GFX9-NEXT: s_add_i32 s12, s12, 3 +; GFX9-NEXT: s_add_i32 s11, s11, 3 +; GFX9-NEXT: s_add_i32 s10, s10, 3 +; GFX9-NEXT: s_add_i32 s9, s9, 3 +; GFX9-NEXT: s_add_i32 s8, s8, 3 +; GFX9-NEXT: s_add_i32 s7, s7, 3 +; GFX9-NEXT: s_add_i32 s6, s6, 3 ; GFX9-NEXT: s_lshr_b32 s46, s45, 16 ; GFX9-NEXT: s_lshr_b32 s47, s44, 16 ; GFX9-NEXT: s_lshr_b32 s56, s43, 16 ; GFX9-NEXT: s_lshr_b32 s57, s42, 16 ; GFX9-NEXT: s_lshr_b32 s58, s41, 16 ; GFX9-NEXT: s_lshr_b32 s59, s40, 16 -; GFX9-NEXT: s_lshr_b32 s60, s15, 16 -; GFX9-NEXT: s_lshr_b32 s61, s14, 16 -; GFX9-NEXT: s_lshr_b32 s62, s13, 16 -; GFX9-NEXT: s_lshr_b32 s63, s12, 16 -; GFX9-NEXT: s_lshr_b32 s72, s11, 16 -; GFX9-NEXT: s_lshr_b32 s73, s10, 16 -; GFX9-NEXT: s_lshr_b32 s74, s9, 16 -; GFX9-NEXT: s_lshr_b32 s75, s8, 16 -; GFX9-NEXT: s_lshr_b32 s76, s7, 16 -; GFX9-NEXT: s_lshr_b32 s77, s6, 16 -; GFX9-NEXT: s_lshr_b32 s78, s29, 16 -; GFX9-NEXT: s_lshr_b32 s79, s28, 16 -; GFX9-NEXT: s_lshr_b32 s88, s27, 16 -; GFX9-NEXT: s_lshr_b32 s89, s26, 16 -; GFX9-NEXT: s_lshr_b32 s90, s25, 16 -; GFX9-NEXT: s_lshr_b32 s91, s24, 16 -; GFX9-NEXT: s_lshr_b32 s92, s23, 16 -; GFX9-NEXT: s_lshr_b32 s93, s22, 16 -; GFX9-NEXT: s_lshr_b32 s94, s21, 16 -; GFX9-NEXT: s_lshr_b32 s95, s20, 16 -; GFX9-NEXT: s_lshr_b32 s30, s19, 16 -; GFX9-NEXT: s_lshr_b32 s31, s18, 16 -; GFX9-NEXT: s_lshr_b32 s34, s17, 16 -; GFX9-NEXT: s_lshr_b32 s35, s16, 16 +; GFX9-NEXT: s_lshr_b32 s60, s29, 16 +; GFX9-NEXT: s_lshr_b32 s61, s28, 16 +; GFX9-NEXT: s_lshr_b32 s62, s27, 16 +; GFX9-NEXT: s_lshr_b32 s63, s26, 16 +; GFX9-NEXT: s_lshr_b32 s72, s25, 16 +; GFX9-NEXT: s_lshr_b32 s73, s24, 16 +; GFX9-NEXT: s_lshr_b32 s74, s23, 16 +; GFX9-NEXT: s_lshr_b32 s75, s22, 16 +; GFX9-NEXT: s_lshr_b32 s76, s21, 16 +; GFX9-NEXT: s_lshr_b32 s77, s20, 16 +; GFX9-NEXT: s_lshr_b32 s78, s19, 16 +; GFX9-NEXT: s_lshr_b32 s79, s18, 16 +; GFX9-NEXT: s_lshr_b32 s88, s17, 16 +; GFX9-NEXT: s_lshr_b32 s89, s16, 16 +; GFX9-NEXT: s_lshr_b32 s90, s15, 16 +; GFX9-NEXT: s_lshr_b32 s91, s14, 16 +; GFX9-NEXT: s_lshr_b32 s92, s13, 16 +; GFX9-NEXT: s_lshr_b32 s93, s12, 16 +; GFX9-NEXT: s_lshr_b32 s94, s11, 16 +; GFX9-NEXT: s_lshr_b32 s95, s10, 16 +; GFX9-NEXT: s_lshr_b32 s30, s9, 16 +; GFX9-NEXT: s_lshr_b32 s31, s8, 16 +; GFX9-NEXT: s_lshr_b32 s34, s7, 16 +; GFX9-NEXT: s_lshr_b32 s35, s6, 16 ; GFX9-NEXT: .LBB17_3: ; %end -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s16, s35 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s17, s34 -; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s31 -; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s30 -; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s95 -; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s94 -; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s93 -; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s92 -; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s91 -; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s90 -; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s89 -; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s88 -; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s79 -; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s78 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s77 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s76 -; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s75 -; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s74 -; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s73 -; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s72 -; GFX9-NEXT: s_pack_ll_b32_b16 s12, s12, s63 -; GFX9-NEXT: s_pack_ll_b32_b16 s13, s13, s62 -; GFX9-NEXT: s_pack_ll_b32_b16 s14, s14, s61 -; GFX9-NEXT: s_pack_ll_b32_b16 s15, s15, s60 +; GFX9-NEXT: s_pack_ll_b32_b16 s4, s6, s35 +; GFX9-NEXT: s_pack_ll_b32_b16 s5, s7, s34 +; GFX9-NEXT: s_pack_ll_b32_b16 s6, s8, s31 +; GFX9-NEXT: s_pack_ll_b32_b16 s7, s9, s30 +; GFX9-NEXT: s_pack_ll_b32_b16 s8, s10, s95 +; GFX9-NEXT: s_pack_ll_b32_b16 s9, s11, s94 +; GFX9-NEXT: s_pack_ll_b32_b16 s10, s12, s93 +; GFX9-NEXT: s_pack_ll_b32_b16 s11, s13, s92 +; GFX9-NEXT: s_pack_ll_b32_b16 s12, s14, s91 +; GFX9-NEXT: s_pack_ll_b32_b16 s13, s15, s90 +; GFX9-NEXT: s_pack_ll_b32_b16 s14, s16, s89 +; GFX9-NEXT: s_pack_ll_b32_b16 s15, s17, s88 +; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s79 +; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s78 +; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s77 +; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s76 +; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s75 +; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s74 +; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s73 +; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s72 +; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s63 +; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s62 +; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s61 +; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s60 ; GFX9-NEXT: s_pack_ll_b32_b16 s28, s40, s59 ; GFX9-NEXT: s_pack_ll_b32_b16 s29, s41, s58 ; GFX9-NEXT: s_pack_ll_b32_b16 s40, s42, s57 @@ -10045,28 +10045,28 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; GFX9-NEXT: s_pack_ll_b32_b16 s43, s45, s46 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 -; GFX9-NEXT: v_mov_b32_e32 v2, s16 -; GFX9-NEXT: v_mov_b32_e32 v3, s17 -; GFX9-NEXT: v_mov_b32_e32 v4, s18 -; GFX9-NEXT: v_mov_b32_e32 v5, s19 -; GFX9-NEXT: v_mov_b32_e32 v6, s20 -; GFX9-NEXT: v_mov_b32_e32 v7, s21 -; GFX9-NEXT: v_mov_b32_e32 v8, s22 -; GFX9-NEXT: v_mov_b32_e32 v9, s23 -; GFX9-NEXT: v_mov_b32_e32 v10, s24 -; GFX9-NEXT: v_mov_b32_e32 v11, s25 -; GFX9-NEXT: v_mov_b32_e32 v12, s26 -; GFX9-NEXT: v_mov_b32_e32 v13, s27 -; GFX9-NEXT: v_mov_b32_e32 v14, s6 -; GFX9-NEXT: v_mov_b32_e32 v15, s7 -; GFX9-NEXT: v_mov_b32_e32 v16, s8 -; GFX9-NEXT: v_mov_b32_e32 v17, s9 -; GFX9-NEXT: v_mov_b32_e32 v18, s10 -; GFX9-NEXT: v_mov_b32_e32 v19, s11 -; GFX9-NEXT: v_mov_b32_e32 v20, s12 -; GFX9-NEXT: v_mov_b32_e32 v21, s13 -; GFX9-NEXT: v_mov_b32_e32 v22, s14 -; GFX9-NEXT: v_mov_b32_e32 v23, s15 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: v_mov_b32_e32 v4, s8 +; GFX9-NEXT: v_mov_b32_e32 v5, s9 +; GFX9-NEXT: v_mov_b32_e32 v6, s10 +; GFX9-NEXT: v_mov_b32_e32 v7, s11 +; GFX9-NEXT: v_mov_b32_e32 v8, s12 +; GFX9-NEXT: v_mov_b32_e32 v9, s13 +; GFX9-NEXT: v_mov_b32_e32 v10, s14 +; GFX9-NEXT: v_mov_b32_e32 v11, s15 +; GFX9-NEXT: v_mov_b32_e32 v12, s16 +; GFX9-NEXT: v_mov_b32_e32 v13, s17 +; GFX9-NEXT: v_mov_b32_e32 v14, s18 +; GFX9-NEXT: v_mov_b32_e32 v15, s19 +; GFX9-NEXT: v_mov_b32_e32 v16, s20 +; GFX9-NEXT: v_mov_b32_e32 v17, s21 +; GFX9-NEXT: v_mov_b32_e32 v18, s22 +; GFX9-NEXT: v_mov_b32_e32 v19, s23 +; GFX9-NEXT: v_mov_b32_e32 v20, s24 +; GFX9-NEXT: v_mov_b32_e32 v21, s25 +; GFX9-NEXT: v_mov_b32_e32 v22, s26 +; GFX9-NEXT: v_mov_b32_e32 v23, s27 ; GFX9-NEXT: v_mov_b32_e32 v24, s28 ; GFX9-NEXT: v_mov_b32_e32 v25, s29 ; GFX9-NEXT: v_mov_b32_e32 v26, s40 @@ -10118,49 +10118,76 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; GFX11-LABEL: bitcast_v30i32_to_v60f16_scalar: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v13, s0 :: v_dual_mov_b32 v14, s1 +; GFX11-NEXT: v_dual_mov_b32 v15, s2 :: v_dual_mov_b32 v16, s3 +; GFX11-NEXT: v_dual_mov_b32 v17, s16 :: v_dual_mov_b32 v18, s17 +; GFX11-NEXT: v_dual_mov_b32 v19, s18 :: v_dual_mov_b32 v20, s19 +; GFX11-NEXT: v_dual_mov_b32 v21, s20 :: v_dual_mov_b32 v22, s21 +; GFX11-NEXT: v_dual_mov_b32 v23, s22 :: v_dual_mov_b32 v24, s23 +; GFX11-NEXT: v_dual_mov_b32 v25, s24 :: v_dual_mov_b32 v26, s25 +; GFX11-NEXT: v_dual_mov_b32 v27, s26 :: v_dual_mov_b32 v28, s27 +; GFX11-NEXT: v_dual_mov_b32 v29, s28 :: v_dual_mov_b32 v30, s29 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 -; GFX11-NEXT: v_readfirstlane_b32 s4, v0 -; GFX11-NEXT: v_readfirstlane_b32 s5, v1 -; GFX11-NEXT: v_readfirstlane_b32 s6, v2 -; GFX11-NEXT: v_readfirstlane_b32 s7, v3 -; GFX11-NEXT: v_readfirstlane_b32 s8, v4 -; GFX11-NEXT: v_readfirstlane_b32 s9, v5 -; GFX11-NEXT: v_readfirstlane_b32 s10, v6 -; GFX11-NEXT: v_readfirstlane_b32 s11, v7 -; GFX11-NEXT: v_readfirstlane_b32 s12, v8 -; GFX11-NEXT: v_readfirstlane_b32 s13, v9 -; GFX11-NEXT: v_readfirstlane_b32 s15, v10 -; GFX11-NEXT: v_readfirstlane_b32 s14, v11 +; GFX11-NEXT: v_readfirstlane_b32 s0, v13 +; GFX11-NEXT: v_readfirstlane_b32 s1, v14 +; GFX11-NEXT: v_readfirstlane_b32 s2, v15 +; GFX11-NEXT: v_readfirstlane_b32 s3, v16 +; GFX11-NEXT: v_readfirstlane_b32 s4, v17 +; GFX11-NEXT: v_readfirstlane_b32 s5, v18 +; GFX11-NEXT: v_readfirstlane_b32 s6, v19 +; GFX11-NEXT: v_readfirstlane_b32 s7, v20 +; GFX11-NEXT: v_readfirstlane_b32 s8, v21 +; GFX11-NEXT: v_readfirstlane_b32 s9, v22 +; GFX11-NEXT: v_readfirstlane_b32 s10, v23 +; GFX11-NEXT: v_readfirstlane_b32 s11, v24 +; GFX11-NEXT: v_readfirstlane_b32 s12, v25 +; GFX11-NEXT: v_readfirstlane_b32 s13, v26 +; GFX11-NEXT: v_readfirstlane_b32 s14, v27 +; GFX11-NEXT: v_readfirstlane_b32 s15, v28 +; GFX11-NEXT: v_readfirstlane_b32 s16, v29 +; GFX11-NEXT: v_readfirstlane_b32 s17, v30 +; GFX11-NEXT: v_readfirstlane_b32 s18, v0 +; GFX11-NEXT: v_readfirstlane_b32 s19, v1 +; GFX11-NEXT: v_readfirstlane_b32 s20, v2 +; GFX11-NEXT: v_readfirstlane_b32 s21, v3 +; GFX11-NEXT: v_readfirstlane_b32 s22, v4 +; GFX11-NEXT: v_readfirstlane_b32 s23, v5 +; GFX11-NEXT: v_readfirstlane_b32 s24, v6 +; GFX11-NEXT: v_readfirstlane_b32 s25, v7 +; GFX11-NEXT: v_readfirstlane_b32 s26, v8 +; GFX11-NEXT: v_readfirstlane_b32 s27, v9 +; GFX11-NEXT: v_readfirstlane_b32 s29, v10 +; GFX11-NEXT: v_readfirstlane_b32 s28, v11 ; GFX11-NEXT: s_mov_b32 s94, 0 ; GFX11-NEXT: s_and_b32 s40, vcc_lo, exec_lo ; GFX11-NEXT: s_cbranch_scc0 .LBB17_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: s_lshr_b32 s40, s14, 16 -; GFX11-NEXT: s_lshr_b32 s41, s15, 16 -; GFX11-NEXT: s_lshr_b32 s42, s13, 16 -; GFX11-NEXT: s_lshr_b32 s43, s12, 16 -; GFX11-NEXT: s_lshr_b32 s44, s11, 16 -; GFX11-NEXT: s_lshr_b32 s45, s10, 16 -; GFX11-NEXT: s_lshr_b32 s46, s9, 16 -; GFX11-NEXT: s_lshr_b32 s47, s8, 16 -; GFX11-NEXT: s_lshr_b32 s56, s7, 16 -; GFX11-NEXT: s_lshr_b32 s57, s6, 16 -; GFX11-NEXT: s_lshr_b32 s58, s5, 16 -; GFX11-NEXT: s_lshr_b32 s59, s4, 16 -; GFX11-NEXT: s_lshr_b32 s60, s29, 16 -; GFX11-NEXT: s_lshr_b32 s61, s28, 16 -; GFX11-NEXT: s_lshr_b32 s62, s27, 16 -; GFX11-NEXT: s_lshr_b32 s63, s26, 16 -; GFX11-NEXT: s_lshr_b32 s72, s25, 16 -; GFX11-NEXT: s_lshr_b32 s73, s24, 16 -; GFX11-NEXT: s_lshr_b32 s74, s23, 16 -; GFX11-NEXT: s_lshr_b32 s75, s22, 16 -; GFX11-NEXT: s_lshr_b32 s76, s21, 16 -; GFX11-NEXT: s_lshr_b32 s77, s20, 16 -; GFX11-NEXT: s_lshr_b32 s78, s19, 16 -; GFX11-NEXT: s_lshr_b32 s79, s18, 16 -; GFX11-NEXT: s_lshr_b32 s88, s17, 16 -; GFX11-NEXT: s_lshr_b32 s89, s16, 16 +; GFX11-NEXT: s_lshr_b32 s40, s28, 16 +; GFX11-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-NEXT: s_lshr_b32 s42, s27, 16 +; GFX11-NEXT: s_lshr_b32 s43, s26, 16 +; GFX11-NEXT: s_lshr_b32 s44, s25, 16 +; GFX11-NEXT: s_lshr_b32 s45, s24, 16 +; GFX11-NEXT: s_lshr_b32 s46, s23, 16 +; GFX11-NEXT: s_lshr_b32 s47, s22, 16 +; GFX11-NEXT: s_lshr_b32 s56, s21, 16 +; GFX11-NEXT: s_lshr_b32 s57, s20, 16 +; GFX11-NEXT: s_lshr_b32 s58, s19, 16 +; GFX11-NEXT: s_lshr_b32 s59, s18, 16 +; GFX11-NEXT: s_lshr_b32 s60, s17, 16 +; GFX11-NEXT: s_lshr_b32 s61, s16, 16 +; GFX11-NEXT: s_lshr_b32 s62, s15, 16 +; GFX11-NEXT: s_lshr_b32 s63, s14, 16 +; GFX11-NEXT: s_lshr_b32 s72, s13, 16 +; GFX11-NEXT: s_lshr_b32 s73, s12, 16 +; GFX11-NEXT: s_lshr_b32 s74, s11, 16 +; GFX11-NEXT: s_lshr_b32 s75, s10, 16 +; GFX11-NEXT: s_lshr_b32 s76, s9, 16 +; GFX11-NEXT: s_lshr_b32 s77, s8, 16 +; GFX11-NEXT: s_lshr_b32 s78, s7, 16 +; GFX11-NEXT: s_lshr_b32 s79, s6, 16 +; GFX11-NEXT: s_lshr_b32 s88, s5, 16 +; GFX11-NEXT: s_lshr_b32 s89, s4, 16 ; GFX11-NEXT: s_lshr_b32 s90, s3, 16 ; GFX11-NEXT: s_lshr_b32 s91, s2, 16 ; GFX11-NEXT: s_lshr_b32 s92, s1, 16 @@ -10168,20 +10195,8 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s94 ; GFX11-NEXT: s_cbranch_vccnz .LBB17_3 ; GFX11-NEXT: .LBB17_2: ; %cmp.true -; GFX11-NEXT: s_add_i32 s14, s14, 3 -; GFX11-NEXT: s_add_i32 s15, s15, 3 -; GFX11-NEXT: s_add_i32 s13, s13, 3 -; GFX11-NEXT: s_add_i32 s12, s12, 3 -; GFX11-NEXT: s_add_i32 s11, s11, 3 -; GFX11-NEXT: s_add_i32 s10, s10, 3 -; GFX11-NEXT: s_add_i32 s9, s9, 3 -; GFX11-NEXT: s_add_i32 s8, s8, 3 -; GFX11-NEXT: s_add_i32 s7, s7, 3 -; GFX11-NEXT: s_add_i32 s6, s6, 3 -; GFX11-NEXT: s_add_i32 s5, s5, 3 -; GFX11-NEXT: s_add_i32 s4, s4, 3 -; GFX11-NEXT: s_add_i32 s29, s29, 3 ; GFX11-NEXT: s_add_i32 s28, s28, 3 +; GFX11-NEXT: s_add_i32 s29, s29, 3 ; GFX11-NEXT: s_add_i32 s27, s27, 3 ; GFX11-NEXT: s_add_i32 s26, s26, 3 ; GFX11-NEXT: s_add_i32 s25, s25, 3 @@ -10194,36 +10209,48 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; GFX11-NEXT: s_add_i32 s18, s18, 3 ; GFX11-NEXT: s_add_i32 s17, s17, 3 ; GFX11-NEXT: s_add_i32 s16, s16, 3 +; GFX11-NEXT: s_add_i32 s15, s15, 3 +; GFX11-NEXT: s_add_i32 s14, s14, 3 +; GFX11-NEXT: s_add_i32 s13, s13, 3 +; GFX11-NEXT: s_add_i32 s12, s12, 3 +; GFX11-NEXT: s_add_i32 s11, s11, 3 +; GFX11-NEXT: s_add_i32 s10, s10, 3 +; GFX11-NEXT: s_add_i32 s9, s9, 3 +; GFX11-NEXT: s_add_i32 s8, s8, 3 +; GFX11-NEXT: s_add_i32 s7, s7, 3 +; GFX11-NEXT: s_add_i32 s6, s6, 3 +; GFX11-NEXT: s_add_i32 s5, s5, 3 +; GFX11-NEXT: s_add_i32 s4, s4, 3 ; GFX11-NEXT: s_add_i32 s3, s3, 3 ; GFX11-NEXT: s_add_i32 s2, s2, 3 ; GFX11-NEXT: s_add_i32 s1, s1, 3 ; GFX11-NEXT: s_add_i32 s0, s0, 3 -; GFX11-NEXT: s_lshr_b32 s40, s14, 16 -; GFX11-NEXT: s_lshr_b32 s41, s15, 16 -; GFX11-NEXT: s_lshr_b32 s42, s13, 16 -; GFX11-NEXT: s_lshr_b32 s43, s12, 16 -; GFX11-NEXT: s_lshr_b32 s44, s11, 16 -; GFX11-NEXT: s_lshr_b32 s45, s10, 16 -; GFX11-NEXT: s_lshr_b32 s46, s9, 16 -; GFX11-NEXT: s_lshr_b32 s47, s8, 16 -; GFX11-NEXT: s_lshr_b32 s56, s7, 16 -; GFX11-NEXT: s_lshr_b32 s57, s6, 16 -; GFX11-NEXT: s_lshr_b32 s58, s5, 16 -; GFX11-NEXT: s_lshr_b32 s59, s4, 16 -; GFX11-NEXT: s_lshr_b32 s60, s29, 16 -; GFX11-NEXT: s_lshr_b32 s61, s28, 16 -; GFX11-NEXT: s_lshr_b32 s62, s27, 16 -; GFX11-NEXT: s_lshr_b32 s63, s26, 16 -; GFX11-NEXT: s_lshr_b32 s72, s25, 16 -; GFX11-NEXT: s_lshr_b32 s73, s24, 16 -; GFX11-NEXT: s_lshr_b32 s74, s23, 16 -; GFX11-NEXT: s_lshr_b32 s75, s22, 16 -; GFX11-NEXT: s_lshr_b32 s76, s21, 16 -; GFX11-NEXT: s_lshr_b32 s77, s20, 16 -; GFX11-NEXT: s_lshr_b32 s78, s19, 16 -; GFX11-NEXT: s_lshr_b32 s79, s18, 16 -; GFX11-NEXT: s_lshr_b32 s88, s17, 16 -; GFX11-NEXT: s_lshr_b32 s89, s16, 16 +; GFX11-NEXT: s_lshr_b32 s40, s28, 16 +; GFX11-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-NEXT: s_lshr_b32 s42, s27, 16 +; GFX11-NEXT: s_lshr_b32 s43, s26, 16 +; GFX11-NEXT: s_lshr_b32 s44, s25, 16 +; GFX11-NEXT: s_lshr_b32 s45, s24, 16 +; GFX11-NEXT: s_lshr_b32 s46, s23, 16 +; GFX11-NEXT: s_lshr_b32 s47, s22, 16 +; GFX11-NEXT: s_lshr_b32 s56, s21, 16 +; GFX11-NEXT: s_lshr_b32 s57, s20, 16 +; GFX11-NEXT: s_lshr_b32 s58, s19, 16 +; GFX11-NEXT: s_lshr_b32 s59, s18, 16 +; GFX11-NEXT: s_lshr_b32 s60, s17, 16 +; GFX11-NEXT: s_lshr_b32 s61, s16, 16 +; GFX11-NEXT: s_lshr_b32 s62, s15, 16 +; GFX11-NEXT: s_lshr_b32 s63, s14, 16 +; GFX11-NEXT: s_lshr_b32 s72, s13, 16 +; GFX11-NEXT: s_lshr_b32 s73, s12, 16 +; GFX11-NEXT: s_lshr_b32 s74, s11, 16 +; GFX11-NEXT: s_lshr_b32 s75, s10, 16 +; GFX11-NEXT: s_lshr_b32 s76, s9, 16 +; GFX11-NEXT: s_lshr_b32 s77, s8, 16 +; GFX11-NEXT: s_lshr_b32 s78, s7, 16 +; GFX11-NEXT: s_lshr_b32 s79, s6, 16 +; GFX11-NEXT: s_lshr_b32 s88, s5, 16 +; GFX11-NEXT: s_lshr_b32 s89, s4, 16 ; GFX11-NEXT: s_lshr_b32 s90, s3, 16 ; GFX11-NEXT: s_lshr_b32 s91, s2, 16 ; GFX11-NEXT: s_lshr_b32 s92, s1, 16 @@ -10234,47 +10261,47 @@ define inreg <60 x half> @bitcast_v30i32_to_v60f16_scalar(<30 x i32> inreg %a, i ; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s92 ; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s91 ; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s90 -; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s89 -; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s88 -; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s79 -; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s78 -; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s77 -; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s76 -; GFX11-NEXT: s_pack_ll_b32_b16 s22, s22, s75 -; GFX11-NEXT: s_pack_ll_b32_b16 s23, s23, s74 -; GFX11-NEXT: s_pack_ll_b32_b16 s24, s24, s73 -; GFX11-NEXT: s_pack_ll_b32_b16 s25, s25, s72 -; GFX11-NEXT: s_pack_ll_b32_b16 s26, s26, s63 -; GFX11-NEXT: s_pack_ll_b32_b16 s27, s27, s62 -; GFX11-NEXT: s_pack_ll_b32_b16 s28, s28, s61 -; GFX11-NEXT: s_pack_ll_b32_b16 s29, s29, s60 -; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s59 -; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s58 -; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s57 -; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s56 -; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s47 -; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s46 -; GFX11-NEXT: s_pack_ll_b32_b16 s10, s10, s45 -; GFX11-NEXT: s_pack_ll_b32_b16 s11, s11, s44 -; GFX11-NEXT: s_pack_ll_b32_b16 s12, s12, s43 -; GFX11-NEXT: s_pack_ll_b32_b16 s13, s13, s42 -; GFX11-NEXT: s_pack_ll_b32_b16 s15, s15, s41 -; GFX11-NEXT: s_pack_ll_b32_b16 s14, s14, s40 +; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s89 +; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s88 +; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s79 +; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s78 +; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s77 +; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s76 +; GFX11-NEXT: s_pack_ll_b32_b16 s10, s10, s75 +; GFX11-NEXT: s_pack_ll_b32_b16 s11, s11, s74 +; GFX11-NEXT: s_pack_ll_b32_b16 s12, s12, s73 +; GFX11-NEXT: s_pack_ll_b32_b16 s13, s13, s72 +; GFX11-NEXT: s_pack_ll_b32_b16 s14, s14, s63 +; GFX11-NEXT: s_pack_ll_b32_b16 s15, s15, s62 +; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s61 +; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s60 +; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s59 +; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s58 +; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s57 +; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s56 +; GFX11-NEXT: s_pack_ll_b32_b16 s22, s22, s47 +; GFX11-NEXT: s_pack_ll_b32_b16 s23, s23, s46 +; GFX11-NEXT: s_pack_ll_b32_b16 s24, s24, s45 +; GFX11-NEXT: s_pack_ll_b32_b16 s25, s25, s44 +; GFX11-NEXT: s_pack_ll_b32_b16 s26, s26, s43 +; GFX11-NEXT: s_pack_ll_b32_b16 s27, s27, s42 +; GFX11-NEXT: s_pack_ll_b32_b16 s29, s29, s41 +; GFX11-NEXT: s_pack_ll_b32_b16 s28, s28, s40 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 -; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 -; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 -; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 -; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 -; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 -; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 -; GFX11-NEXT: v_dual_mov_b32 v18, s4 :: v_dual_mov_b32 v19, s5 -; GFX11-NEXT: v_dual_mov_b32 v20, s6 :: v_dual_mov_b32 v21, s7 -; GFX11-NEXT: v_dual_mov_b32 v22, s8 :: v_dual_mov_b32 v23, s9 -; GFX11-NEXT: v_dual_mov_b32 v24, s10 :: v_dual_mov_b32 v25, s11 -; GFX11-NEXT: v_dual_mov_b32 v26, s12 :: v_dual_mov_b32 v27, s13 -; GFX11-NEXT: v_dual_mov_b32 v28, s15 :: v_dual_mov_b32 v29, s14 +; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19 +; GFX11-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v21, s21 +; GFX11-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v23, s23 +; GFX11-NEXT: v_dual_mov_b32 v24, s24 :: v_dual_mov_b32 v25, s25 +; GFX11-NEXT: v_dual_mov_b32 v26, s26 :: v_dual_mov_b32 v27, s27 +; GFX11-NEXT: v_dual_mov_b32 v28, s29 :: v_dual_mov_b32 v29, s28 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: .LBB17_4: ; GFX11-NEXT: ; implicit-def: $sgpr93 @@ -10345,6 +10372,9 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(5) +; SI-NEXT: v_cvt_f16_f32_e32 v58, v0 +; SI-NEXT: v_cvt_f16_f32_e32 v0, v5 ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116 ; SI-NEXT: s_waitcnt expcnt(3) ; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 @@ -10373,23 +10403,12 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:76 ; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:88 ; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:84 -; SI-NEXT: v_cvt_f16_f32_e32 v58, v0 -; SI-NEXT: v_cvt_f16_f32_e32 v0, v5 ; SI-NEXT: v_cvt_f16_f32_e32 v59, v1 ; SI-NEXT: v_cvt_f16_f32_e32 v57, v3 -; SI-NEXT: v_cvt_f16_f32_e32 v56, v2 -; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:96 -; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:92 -; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:104 -; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:100 -; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:112 -; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:108 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v60, v60 +; SI-NEXT: v_cvt_f16_f32_e32 v56, v2 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v7 @@ -10399,8 +10418,6 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v9 -; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_cvt_f16_f32_e32 v52, v52 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v8 @@ -10422,9 +10439,18 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v14 +; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v17 +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:96 +; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:92 +; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:104 +; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:100 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:112 +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:108 +; SI-NEXT: v_cvt_f16_f32_e32 v60, v60 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v16 @@ -10434,6 +10460,7 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v18 +; SI-NEXT: v_cvt_f16_f32_e32 v52, v52 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v21 @@ -10471,7 +10498,6 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) { ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v61 ; SI-NEXT: v_cvt_f16_f32_e32 v61, v49 -; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cvt_f16_f32_e32 v49, v55 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -10486,6 +10512,7 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v32 +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cvt_f16_f32_e32 v32, v47 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -11357,7 +11384,6 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v61, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v29 -; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v28 @@ -11436,6 +11462,7 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) { ; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v60 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v61 +; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -11600,6 +11627,9 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) { ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] ; GFX9-NEXT: s_cbranch_execz .LBB18_4 ; GFX9-NEXT: ; %bb.3: ; %cmp.true +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload @@ -11614,9 +11644,6 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload -; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v38, v61, s6 ; GFX9-NEXT: s_movk_i32 s7, 0x200 ; GFX9-NEXT: v_perm_b32 v1, v37, v60, s6 @@ -11636,6 +11663,10 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) { ; GFX9-NEXT: v_pk_add_f16 v6, v6, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v7, v7, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v8, v8, s7 op_sel_hi:[1,0] +; GFX9-NEXT: s_waitcnt vmcnt(14) +; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; GFX9-NEXT: s_waitcnt vmcnt(15) ; GFX9-NEXT: v_perm_b32 v9, v9, v44, s6 ; GFX9-NEXT: s_waitcnt vmcnt(14) @@ -11664,10 +11695,6 @@ define <30 x i32> @bitcast_v60f16_to_v30i32(<60 x half> %a, i32 %b) { ; GFX9-NEXT: v_perm_b32 v21, v21, v48, s6 ; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: v_perm_b32 v22, v22, v39, s6 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v10, v10, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0] @@ -11988,12 +12015,35 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i ; SI-NEXT: v_cvt_f16_f32_e32 v8, s26 ; SI-NEXT: v_cvt_f16_f32_e32 v6, s29 ; SI-NEXT: v_cvt_f16_f32_e32 v7, s28 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: v_cvt_f16_f32_e32 v50, v54 ; SI-NEXT: v_cvt_f16_f32_e32 v48, v48 ; SI-NEXT: v_cvt_f16_f32_e32 v31, v40 -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v33 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill @@ -12003,7 +12053,7 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v38 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0) +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v44 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -12012,7 +12062,7 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v46 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0) +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v47 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -12021,7 +12071,7 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v57 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0) +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v58 ; SI-NEXT: v_cvt_f16_f32_e32 v58, s16 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill @@ -12032,38 +12082,12 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v60 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB19_2 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(4) ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; SI-NEXT: v_or_b32_e32 v3, v10, v3 -; SI-NEXT: s_waitcnt expcnt(3) ; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34 ; SI-NEXT: v_mov_b32_e32 v33, v32 ; SI-NEXT: v_or_b32_e32 v10, v32, v10 @@ -12088,12 +12112,12 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i ; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18 ; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v59 ; SI-NEXT: v_or_b32_e32 v1, v12, v1 ; SI-NEXT: v_or_b32_e32 v2, v11, v2 @@ -12202,12 +12226,10 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i ; SI-NEXT: v_mov_b32_e32 v40, v44 ; SI-NEXT: s_cbranch_vccnz .LBB19_5 ; SI-NEXT: ; %bb.4: ; %cmp.true -; SI-NEXT: s_waitcnt expcnt(5) ; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(4) ; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; SI-NEXT: v_cvt_f32_f16_e32 v0, v59 ; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v0, v59 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v58 ; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_cvt_f32_f16_e32 v8, v33 @@ -12993,304 +13015,115 @@ define inreg <30 x i32> @bitcast_v60f16_to_v30i32_scalar(<60 x half> inreg %a, i ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v190, v6 :: v_dual_mov_b32 v185, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v186, v3 :: v_dual_mov_b32 v187, v2 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v1 :: v_dual_mov_b32 v189, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB19_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB19_3 ; GFX11-TRUE16-NEXT: .LBB19_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s40 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s41 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v189, 0x200, v189 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v188, 0x200, v188 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v187, 0x200, v187 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v186, 0x200, v186 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v185, 0x200, v185 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v191, 0x200, v191 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v190, 0x200, v190 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, s6 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, s7 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, s8 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s9 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, s10 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, s11 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, s12 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, s13 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s14 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, s15 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, s16 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v30, 0x200, v30 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s0 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s1 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s2 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, s3 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, s4 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v35, 0x200, s5 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v44, 0x200, s6 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v54, 0x200, s7 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v65, 0x200, s8 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v77, 0x200, s9 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v90, 0x200, s10 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v104, 0x200, s11 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v119, 0x200, s12 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v135, 0x200, s13 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v152, 0x200, s14 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v170, 0x200, s15 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: .LBB19_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v170 :: v_dual_mov_b32 v18, v189 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v188 :: v_dual_mov_b32 v20, v187 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v186 :: v_dual_mov_b32 v22, v185 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v191 :: v_dual_mov_b32 v24, v190 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v191, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v190, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v189, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v188, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v187, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:316 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v119 :: v_dual_mov_b32 v27, v30 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB19_4: -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v64, v29 :: v_dual_mov_b32 v65, v28 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v66, v30 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v53, v26 :: v_dual_mov_b32 v54, v25 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v54 :: v_dual_mov_b32 v26, v53 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v65 :: v_dual_mov_b32 v29, v64 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v30, v66 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB19_2 ; ; GFX11-FAKE16-LABEL: bitcast_v60f16_to_v30i32_scalar: @@ -17570,40 +17403,53 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) { ; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:8 ; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:4 ; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v2 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v4 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:52 +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:112 ; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:108 +; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v4 +; SI-NEXT: s_waitcnt vmcnt(4) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:44 ; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v6 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v8 -; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:104 ; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:100 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v10 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v6 +; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v8 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:36 +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:96 ; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:92 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v12 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v10 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:28 +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:88 ; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:84 -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v12 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v14 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:48 @@ -17634,27 +17480,10 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) { ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:56 ; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:64 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:52 -; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v28 -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v30 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:44 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:36 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:28 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v30 ; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] @@ -17739,7 +17568,6 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr30 ; SI-NEXT: ; kill: killed $vgpr30 ; SI-NEXT: ; implicit-def: $vgpr30 -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_and_b32_e32 v0, 0xffff, v55 ; SI-NEXT: v_and_b32_e32 v18, 0xffff, v61 ; SI-NEXT: ; kill: killed $vgpr30 @@ -17884,7 +17712,6 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) { ; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v55 ; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v61 ; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0 @@ -18011,7 +17838,7 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) { ; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24 ; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25 ; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26 -; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v27 +; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v27 ; SI-NEXT: v_add_i32_e32 v28, vcc, 0x30000, v28 ; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v29 ; SI-NEXT: .LBB30_4: ; %end @@ -18032,7 +17859,7 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) { ; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] ; ; VI-LABEL: bitcast_v60i16_to_v30f32: @@ -18314,7 +18141,6 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v61, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v29 -; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v28 @@ -18393,6 +18219,7 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v60 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v61 +; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -18557,6 +18384,9 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] ; GFX9-NEXT: s_cbranch_execz .LBB30_4 ; GFX9-NEXT: ; %bb.3: ; %cmp.true +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload @@ -18571,9 +18401,6 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload -; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v38, v61, s6 ; GFX9-NEXT: v_perm_b32 v1, v37, v60, s6 ; GFX9-NEXT: v_perm_b32 v2, v62, v59, s6 @@ -18592,6 +18419,10 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] +; GFX9-NEXT: s_waitcnt vmcnt(14) +; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; GFX9-NEXT: s_waitcnt vmcnt(15) ; GFX9-NEXT: v_perm_b32 v9, v9, v44, s6 ; GFX9-NEXT: s_waitcnt vmcnt(14) @@ -18620,10 +18451,6 @@ define <30 x float> @bitcast_v60i16_to_v30f32(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: v_perm_b32 v21, v21, v48, s6 ; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: v_perm_b32 v22, v22, v39, s6 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] @@ -19779,304 +19606,115 @@ define inreg <30 x float> @bitcast_v60i16_to_v30f32_scalar(<60 x i16> inreg %a, ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v190, v6 :: v_dual_mov_b32 v185, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v186, v3 :: v_dual_mov_b32 v187, v2 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v1 :: v_dual_mov_b32 v189, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB31_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB31_3 ; GFX11-TRUE16-NEXT: .LBB31_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s40, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s41, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v189, v189, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v188, v188, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v187, v187, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v186, v186, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v185, v185, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v191, v191, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v190, v190, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, s6, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, s7, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, s8, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s9, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, s10, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, s11, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, s12, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, s13, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s14, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, s15, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, s16, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v30, v30, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s0, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s1, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s2, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, s3, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, s4, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v35, s5, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v44, s6, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v54, s7, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v65, s8, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v77, s9, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v90, s10, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v104, s11, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v119, s12, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v135, s13, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v152, s14, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v170, s15, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: .LBB31_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v170 :: v_dual_mov_b32 v18, v189 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v188 :: v_dual_mov_b32 v20, v187 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v186 :: v_dual_mov_b32 v22, v185 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v191 :: v_dual_mov_b32 v24, v190 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v191, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v190, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v189, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v188, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v187, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:316 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v119 :: v_dual_mov_b32 v27, v30 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB31_4: -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v64, v29 :: v_dual_mov_b32 v65, v28 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v66, v30 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v53, v26 :: v_dual_mov_b32 v54, v25 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v54 :: v_dual_mov_b32 v26, v53 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v65 :: v_dual_mov_b32 v29, v64 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v30, v66 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB31_2 ; ; GFX11-FAKE16-LABEL: bitcast_v60i16_to_v30f32_scalar: @@ -21565,23 +21203,21 @@ define inreg <60 x half> @bitcast_v30f32_to_v60f16_scalar(<30 x float> inreg %a, ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; SI-NEXT: v_readfirstlane_b32 s45, v1 -; SI-NEXT: v_readfirstlane_b32 s44, v2 -; SI-NEXT: v_readfirstlane_b32 s43, v3 -; SI-NEXT: v_readfirstlane_b32 s42, v4 -; SI-NEXT: v_readfirstlane_b32 s41, v5 -; SI-NEXT: v_readfirstlane_b32 s40, v6 -; SI-NEXT: v_readfirstlane_b32 s15, v7 -; SI-NEXT: v_readfirstlane_b32 s14, v8 -; SI-NEXT: v_readfirstlane_b32 s13, v9 -; SI-NEXT: v_readfirstlane_b32 s12, v10 -; SI-NEXT: v_readfirstlane_b32 s11, v11 -; SI-NEXT: v_readfirstlane_b32 s10, v12 -; SI-NEXT: v_readfirstlane_b32 s8, v13 -; SI-NEXT: v_readfirstlane_b32 s7, v14 -; SI-NEXT: v_readfirstlane_b32 s6, v15 +; SI-NEXT: v_mov_b32_e32 v31, s16 +; SI-NEXT: v_mov_b32_e32 v29, s17 +; SI-NEXT: v_mov_b32_e32 v50, s18 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec -; SI-NEXT: v_readfirstlane_b32 s9, v16 +; SI-NEXT: v_mov_b32_e32 v51, s19 +; SI-NEXT: v_mov_b32_e32 v49, s20 +; SI-NEXT: v_mov_b32_e32 v48, s21 +; SI-NEXT: v_mov_b32_e32 v39, s22 +; SI-NEXT: v_mov_b32_e32 v38, s23 +; SI-NEXT: v_mov_b32_e32 v37, s24 +; SI-NEXT: v_mov_b32_e32 v36, s25 +; SI-NEXT: v_mov_b32_e32 v35, s26 +; SI-NEXT: v_mov_b32_e32 v34, s27 +; SI-NEXT: v_mov_b32_e32 v33, s28 +; SI-NEXT: v_mov_b32_e32 v32, s29 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -21600,450 +21236,574 @@ define inreg <60 x half> @bitcast_v30f32_to_v60f16_scalar(<30 x float> inreg %a, ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB33_4 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: s_lshr_b32 s4, s9, 16 -; SI-NEXT: s_waitcnt expcnt(4) -; SI-NEXT: v_cvt_f32_f16_e32 v59, s4 -; SI-NEXT: s_lshr_b32 s4, s6, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v42, s4 -; SI-NEXT: s_lshr_b32 s4, s7, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v54, s4 -; SI-NEXT: s_lshr_b32 s4, s8, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v50, s4 -; SI-NEXT: s_lshr_b32 s4, s10, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v57, s4 -; SI-NEXT: s_lshr_b32 s4, s11, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v35, s4 -; SI-NEXT: s_lshr_b32 s4, s12, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v11, s4 -; SI-NEXT: s_lshr_b32 s4, s13, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v12, s4 -; SI-NEXT: s_lshr_b32 s4, s14, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v15, s4 -; SI-NEXT: s_lshr_b32 s4, s15, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v8, s4 -; SI-NEXT: s_lshr_b32 s4, s40, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v19, s4 -; SI-NEXT: s_lshr_b32 s4, s41, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v22, s4 -; SI-NEXT: s_lshr_b32 s4, s42, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v24, s4 -; SI-NEXT: s_lshr_b32 s4, s43, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v26, s4 -; SI-NEXT: s_lshr_b32 s4, s44, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v28, s4 -; SI-NEXT: s_lshr_b32 s4, s45, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v30, s4 -; SI-NEXT: s_lshr_b32 s4, s29, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v32, s4 -; SI-NEXT: s_lshr_b32 s4, s28, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v34, s4 -; SI-NEXT: s_lshr_b32 s4, s27, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v36, s4 -; SI-NEXT: s_lshr_b32 s4, s26, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v39, s4 -; SI-NEXT: s_lshr_b32 s4, s25, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v49, s4 -; SI-NEXT: s_lshr_b32 s4, s24, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v51, s4 -; SI-NEXT: s_lshr_b32 s4, s23, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v53, s4 -; SI-NEXT: s_lshr_b32 s4, s22, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v55, s4 -; SI-NEXT: s_lshr_b32 s4, s21, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v41, s4 -; SI-NEXT: s_lshr_b32 s4, s20, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v43, s4 -; SI-NEXT: s_lshr_b32 s4, s19, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v46, s4 -; SI-NEXT: s_lshr_b32 s4, s18, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v56, s4 -; SI-NEXT: s_lshr_b32 s4, s17, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v58, s4 -; SI-NEXT: s_lshr_b32 s4, s16, 16 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v16 +; SI-NEXT: v_cvt_f32_f16_e32 v56, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v15 +; SI-NEXT: v_cvt_f32_f16_e32 v46, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v14 +; SI-NEXT: v_cvt_f32_f16_e32 v44, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v13 +; SI-NEXT: v_cvt_f32_f16_e32 v42, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v12 +; SI-NEXT: v_cvt_f32_f16_e32 v40, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v11 +; SI-NEXT: v_cvt_f32_f16_e32 v55, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v10 +; SI-NEXT: v_cvt_f32_f16_e32 v53, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v9 +; SI-NEXT: v_cvt_f32_f16_e32 v17, v17 +; SI-NEXT: s_waitcnt expcnt(5) +; SI-NEXT: v_cvt_f32_f16_e32 v58, v34 ; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_cvt_f32_f16_e32 v60, s4 -; SI-NEXT: v_cvt_f32_f16_e32 v14, s9 -; SI-NEXT: v_cvt_f32_f16_e32 v38, s6 -; SI-NEXT: v_cvt_f32_f16_e32 v45, s7 -; SI-NEXT: v_cvt_f32_f16_e32 v47, s8 -; SI-NEXT: v_cvt_f32_f16_e32 v1, s10 -; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_cvt_f32_f16_e32 v61, s11 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_cvt_f32_f16_e32 v62, s12 +; SI-NEXT: v_cvt_f32_f16_e32 v60, v35 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v63, s13 -; SI-NEXT: v_cvt_f32_f16_e32 v20, s14 -; SI-NEXT: v_cvt_f32_f16_e32 v21, s15 -; SI-NEXT: v_cvt_f32_f16_e32 v23, s40 -; SI-NEXT: v_cvt_f32_f16_e32 v25, s41 -; SI-NEXT: v_cvt_f32_f16_e32 v27, s42 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s43 -; SI-NEXT: v_cvt_f32_f16_e32 v31, s44 -; SI-NEXT: v_cvt_f32_f16_e32 v33, s45 -; SI-NEXT: v_cvt_f32_f16_e32 v16, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v37, s28 -; SI-NEXT: v_cvt_f32_f16_e32 v18, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v48, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v17, s25 -; SI-NEXT: v_cvt_f32_f16_e32 v52, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v13, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v40, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v9, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v44, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v5, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v3, s18 -; SI-NEXT: v_cvt_f32_f16_e32 v2, s17 -; SI-NEXT: v_cvt_f32_f16_e32 v7, s16 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v8 +; SI-NEXT: v_cvt_f32_f16_e32 v17, v17 +; SI-NEXT: v_cvt_f32_f16_e32 v62, v36 +; SI-NEXT: v_cvt_f32_f16_e32 v18, v38 +; SI-NEXT: v_cvt_f32_f16_e32 v20, v39 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v7 +; SI-NEXT: v_cvt_f32_f16_e32 v17, v17 +; SI-NEXT: v_cvt_f32_f16_e32 v22, v48 +; SI-NEXT: v_cvt_f32_f16_e32 v24, v49 +; SI-NEXT: v_cvt_f32_f16_e32 v26, v51 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v6 +; SI-NEXT: v_cvt_f32_f16_e32 v17, v17 +; SI-NEXT: v_cvt_f32_f16_e32 v27, v50 +; SI-NEXT: v_cvt_f32_f16_e32 v28, v29 +; SI-NEXT: v_cvt_f32_f16_e32 v30, v31 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v17, v17 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v17, v17 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v17, v17 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v17, v17 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v17, v17 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v32 +; SI-NEXT: v_cvt_f32_f16_e32 v52, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v33 +; SI-NEXT: v_cvt_f32_f16_e32 v54, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v34 +; SI-NEXT: v_cvt_f32_f16_e32 v41, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v35 +; SI-NEXT: v_cvt_f32_f16_e32 v43, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v36 +; SI-NEXT: v_cvt_f32_f16_e32 v45, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v37 +; SI-NEXT: v_cvt_f32_f16_e32 v47, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v38 +; SI-NEXT: v_cvt_f32_f16_e32 v57, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v39 +; SI-NEXT: v_cvt_f32_f16_e32 v59, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v48 +; SI-NEXT: v_cvt_f32_f16_e32 v61, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v49 +; SI-NEXT: v_cvt_f32_f16_e32 v63, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v51 +; SI-NEXT: v_cvt_f32_f16_e32 v19, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v50 +; SI-NEXT: v_cvt_f32_f16_e32 v21, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v29 +; SI-NEXT: v_cvt_f32_f16_e32 v23, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v31 +; SI-NEXT: v_cvt_f32_f16_e32 v25, v17 +; SI-NEXT: v_cvt_f32_f16_e32 v17, v16 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v17, v15 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v17, v14 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v17, v13 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v17, v12 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v17, v11 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v17, v10 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v17, v9 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v17, v8 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v17, v7 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v17, v6 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v17, v5 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v17, v4 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v17, v3 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v17, v2 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v17, v1 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v17, v32 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v17, v33 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v17, v37 ; SI-NEXT: s_cbranch_execnz .LBB33_3 ; SI-NEXT: .LBB33_2: ; %cmp.true -; SI-NEXT: v_add_f32_e64 v6, s16, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v6 -; SI-NEXT: v_add_f32_e64 v2, s17, 1.0 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; SI-NEXT: v_add_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SI-NEXT: v_add_f32_e32 v32, 1.0, v32 +; SI-NEXT: v_add_f32_e32 v33, 1.0, v33 +; SI-NEXT: v_add_f32_e32 v9, 1.0, v9 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2 -; SI-NEXT: v_add_f32_e64 v3, s18, 1.0 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f32_f16_e32 v1, v32 +; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v9 +; SI-NEXT: v_add_f32_e32 v8, 1.0, v8 +; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v8 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v33 +; SI-NEXT: v_add_f32_e32 v7, 1.0, v7 +; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v7 +; SI-NEXT: v_add_f32_e32 v6, 1.0, v6 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v3 -; SI-NEXT: v_add_f32_e64 v5, s19, 1.0 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f32_f16_e32 v1, v63 +; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v6 +; SI-NEXT: v_add_f32_e32 v5, 1.0, v5 +; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v5 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v5 -; SI-NEXT: v_add_f32_e64 v7, s20, 1.0 +; SI-NEXT: v_cvt_f32_f16_e32 v1, v61 +; SI-NEXT: v_add_f32_e32 v4, 1.0, v4 +; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v4 +; SI-NEXT: v_add_f32_e32 v3, 1.0, v3 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v7 -; SI-NEXT: v_add_f32_e64 v16, s12, 1.0 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; SI-NEXT: v_add_f32_e64 v11, s22, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v16 -; SI-NEXT: v_add_f32_e64 v40, s6, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v11 -; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v40 -; SI-NEXT: v_cvt_f32_f16_e32 v38, v40 -; SI-NEXT: v_cvt_f32_f16_e32 v40, v11 -; SI-NEXT: v_cvt_f32_f16_e32 v11, v4 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e64 v17, s25, 1.0 -; SI-NEXT: v_add_f32_e64 v28, s45, 1.0 -; SI-NEXT: v_add_f32_e64 v23, s40, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v17 -; SI-NEXT: v_add_f32_e64 v19, s26, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v28 -; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v23 -; SI-NEXT: v_add_f32_e64 v48, s8, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v19 -; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v48 -; SI-NEXT: v_cvt_f32_f16_e32 v47, v48 -; SI-NEXT: v_cvt_f32_f16_e32 v48, v19 -; SI-NEXT: v_cvt_f32_f16_e32 v19, v30 -; SI-NEXT: v_cvt_f32_f16_e32 v30, v49 -; SI-NEXT: v_cvt_f32_f16_e32 v49, v43 -; SI-NEXT: v_add_f32_e64 v15, s24, 1.0 -; SI-NEXT: v_add_f32_e64 v26, s29, 1.0 -; SI-NEXT: v_add_f32_e64 v25, s41, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v15 -; SI-NEXT: v_add_f32_e64 v22, s27, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v26 -; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v25 -; SI-NEXT: v_add_f32_e64 v18, s13, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v22 -; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v18 -; SI-NEXT: v_cvt_f32_f16_e32 v63, v18 -; SI-NEXT: v_cvt_f32_f16_e32 v18, v22 -; SI-NEXT: v_cvt_f32_f16_e32 v22, v32 -; SI-NEXT: v_cvt_f32_f16_e32 v32, v51 -; SI-NEXT: v_cvt_f32_f16_e32 v51, v46 -; SI-NEXT: v_add_f32_e64 v13, s23, 1.0 -; SI-NEXT: v_add_f32_e64 v24, s28, 1.0 -; SI-NEXT: v_add_f32_e64 v27, s42, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v13 -; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v24 -; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v27 -; SI-NEXT: v_add_f32_e64 v37, s10, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v37 +; SI-NEXT: v_cvt_f32_f16_e32 v1, v59 +; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v3 +; SI-NEXT: v_add_f32_e32 v2, 1.0, v2 +; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v2 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v1, v37 -; SI-NEXT: v_cvt_f32_f16_e32 v37, v24 -; SI-NEXT: v_cvt_f32_f16_e32 v24, v34 -; SI-NEXT: v_cvt_f32_f16_e32 v34, v53 -; SI-NEXT: v_cvt_f32_f16_e32 v53, v56 -; SI-NEXT: v_add_f32_e64 v29, s43, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v29 -; SI-NEXT: v_cvt_f32_f16_e32 v62, v16 -; SI-NEXT: v_cvt_f32_f16_e32 v16, v26 -; SI-NEXT: v_cvt_f32_f16_e32 v26, v36 -; SI-NEXT: v_cvt_f32_f16_e32 v36, v55 -; SI-NEXT: v_cvt_f32_f16_e32 v55, v58 -; SI-NEXT: v_add_f32_e64 v9, s21, 1.0 -; SI-NEXT: v_add_f32_e64 v31, s44, 1.0 -; SI-NEXT: v_add_f32_e64 v21, s15, 1.0 -; SI-NEXT: v_add_f32_e64 v20, s14, 1.0 -; SI-NEXT: v_add_f32_e64 v33, s11, 1.0 -; SI-NEXT: v_add_f32_e64 v52, s7, 1.0 -; SI-NEXT: v_add_f32_e64 v44, s9, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v9 -; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v31 -; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v21 -; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v20 -; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v33 -; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v52 -; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v44 -; SI-NEXT: v_cvt_f32_f16_e32 v14, v44 -; SI-NEXT: v_cvt_f32_f16_e32 v45, v52 -; SI-NEXT: v_cvt_f32_f16_e32 v61, v33 -; SI-NEXT: v_cvt_f32_f16_e32 v20, v20 -; SI-NEXT: v_cvt_f32_f16_e32 v21, v21 -; SI-NEXT: v_cvt_f32_f16_e32 v23, v23 -; SI-NEXT: v_cvt_f32_f16_e32 v25, v25 -; SI-NEXT: v_cvt_f32_f16_e32 v27, v27 -; SI-NEXT: v_cvt_f32_f16_e32 v29, v29 -; SI-NEXT: v_cvt_f32_f16_e32 v31, v31 -; SI-NEXT: v_cvt_f32_f16_e32 v33, v28 -; SI-NEXT: v_cvt_f32_f16_e32 v17, v17 -; SI-NEXT: v_cvt_f32_f16_e32 v52, v15 +; SI-NEXT: v_cvt_f32_f16_e32 v1, v57 +; SI-NEXT: v_add_f32_e32 v19, 1.0, v31 +; SI-NEXT: v_add_f32_e32 v21, 1.0, v29 +; SI-NEXT: v_add_f32_e32 v27, 1.0, v50 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v47 +; SI-NEXT: v_add_f32_e32 v26, 1.0, v51 +; SI-NEXT: v_add_f32_e32 v24, 1.0, v49 +; SI-NEXT: v_add_f32_e32 v22, 1.0, v48 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v45 +; SI-NEXT: v_add_f32_e32 v20, 1.0, v39 +; SI-NEXT: v_add_f32_e32 v18, 1.0, v38 +; SI-NEXT: v_add_f32_e32 v17, 1.0, v37 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v43 +; SI-NEXT: v_add_f32_e32 v28, 1.0, v36 +; SI-NEXT: v_add_f32_e32 v30, 1.0, v35 +; SI-NEXT: v_add_f32_e32 v34, 1.0, v34 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v41 +; SI-NEXT: v_add_f32_e32 v10, 1.0, v10 +; SI-NEXT: v_add_f32_e32 v11, 1.0, v11 +; SI-NEXT: v_add_f32_e32 v12, 1.0, v12 +; SI-NEXT: v_add_f32_e32 v13, 1.0, v13 +; SI-NEXT: v_add_f32_e32 v14, 1.0, v14 +; SI-NEXT: v_add_f32_e32 v15, 1.0, v15 +; SI-NEXT: v_add_f32_e32 v16, 1.0, v16 +; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v19 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v21 +; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v27 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v26 +; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v24 +; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v22 +; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v20 +; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v18 +; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v17 +; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v28 +; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v30 +; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v34 +; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v33 +; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v32 +; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v10 +; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v11 +; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v12 +; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v13 +; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v14 +; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v15 +; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v16 +; SI-NEXT: v_cvt_f32_f16_e32 v16, v16 +; SI-NEXT: v_cvt_f32_f16_e32 v15, v15 +; SI-NEXT: v_cvt_f32_f16_e32 v14, v14 ; SI-NEXT: v_cvt_f32_f16_e32 v13, v13 +; SI-NEXT: v_cvt_f32_f16_e32 v12, v12 +; SI-NEXT: v_cvt_f32_f16_e32 v11, v11 +; SI-NEXT: v_cvt_f32_f16_e32 v10, v10 ; SI-NEXT: v_cvt_f32_f16_e32 v9, v9 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v43, v4 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload -; SI-NEXT: v_cvt_f32_f16_e32 v44, v7 +; SI-NEXT: v_cvt_f32_f16_e32 v8, v8 +; SI-NEXT: v_cvt_f32_f16_e32 v7, v7 +; SI-NEXT: v_cvt_f32_f16_e32 v6, v6 ; SI-NEXT: v_cvt_f32_f16_e32 v5, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v4, v4 ; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v7, v6 -; SI-NEXT: v_cvt_f32_f16_e32 v59, v59 +; SI-NEXT: v_cvt_f32_f16_e32 v58, v34 +; SI-NEXT: v_cvt_f32_f16_e32 v60, v30 +; SI-NEXT: v_cvt_f32_f16_e32 v62, v28 +; SI-NEXT: v_cvt_f32_f16_e32 v17, v17 +; SI-NEXT: v_cvt_f32_f16_e32 v18, v18 +; SI-NEXT: v_cvt_f32_f16_e32 v20, v20 +; SI-NEXT: v_cvt_f32_f16_e32 v22, v22 +; SI-NEXT: v_cvt_f32_f16_e32 v24, v24 +; SI-NEXT: v_cvt_f32_f16_e32 v26, v26 +; SI-NEXT: v_cvt_f32_f16_e32 v27, v27 +; SI-NEXT: v_cvt_f32_f16_e32 v28, v21 +; SI-NEXT: v_cvt_f32_f16_e32 v30, v19 +; SI-NEXT: v_cvt_f32_f16_e32 v56, v56 +; SI-NEXT: v_cvt_f32_f16_e32 v46, v46 +; SI-NEXT: v_cvt_f32_f16_e32 v44, v44 ; SI-NEXT: v_cvt_f32_f16_e32 v42, v42 -; SI-NEXT: v_cvt_f32_f16_e32 v54, v54 -; SI-NEXT: v_cvt_f32_f16_e32 v50, v50 -; SI-NEXT: v_cvt_f32_f16_e32 v57, v57 -; SI-NEXT: v_cvt_f32_f16_e32 v35, v35 -; SI-NEXT: v_cvt_f32_f16_e32 v12, v12 -; SI-NEXT: v_cvt_f32_f16_e32 v15, v10 -; SI-NEXT: v_cvt_f32_f16_e32 v8, v8 -; SI-NEXT: v_cvt_f32_f16_e32 v28, v39 -; SI-NEXT: v_cvt_f32_f16_e32 v39, v41 -; SI-NEXT: v_cvt_f32_f16_e32 v41, v60 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v46, v4 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v56, v4 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v58, v4 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v60, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v40, v40 +; SI-NEXT: v_cvt_f32_f16_e32 v55, v55 +; SI-NEXT: v_cvt_f32_f16_e32 v53, v53 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v54 +; SI-NEXT: v_cvt_f32_f16_e32 v52, v52 +; SI-NEXT: v_cvt_f32_f16_e32 v54, v51 +; SI-NEXT: v_cvt_f32_f16_e32 v41, v50 +; SI-NEXT: v_cvt_f32_f16_e32 v43, v35 +; SI-NEXT: v_cvt_f32_f16_e32 v45, v36 +; SI-NEXT: v_cvt_f32_f16_e32 v47, v37 +; SI-NEXT: v_cvt_f32_f16_e32 v57, v38 +; SI-NEXT: v_cvt_f32_f16_e32 v59, v39 +; SI-NEXT: v_cvt_f32_f16_e32 v61, v48 +; SI-NEXT: v_cvt_f32_f16_e32 v63, v49 +; SI-NEXT: v_cvt_f32_f16_e32 v19, v31 +; SI-NEXT: v_cvt_f32_f16_e32 v21, v29 +; SI-NEXT: v_cvt_f32_f16_e32 v23, v23 +; SI-NEXT: v_cvt_f32_f16_e32 v25, v25 +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill ; SI-NEXT: .LBB33_3: ; %end -; SI-NEXT: v_cvt_f16_f32_e32 v4, v60 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v7 -; SI-NEXT: v_cvt_f16_f32_e32 v10, v2 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v5 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v6, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v58 -; SI-NEXT: buffer_store_dword v4, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v4, vcc, 4, v0 -; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; SI-NEXT: v_or_b32_e32 v6, v10, v6 -; SI-NEXT: buffer_store_dword v6, v4, s[0:3], 0 offen -; SI-NEXT: v_cvt_f16_f32_e32 v4, v56 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v25 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v30 +; SI-NEXT: v_cvt_f16_f32_e32 v3, v28 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v23 +; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v6, v3 -; SI-NEXT: v_add_i32_e32 v10, vcc, 8, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v6, v4 -; SI-NEXT: buffer_store_dword v4, v10, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0 +; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; SI-NEXT: v_or_b32_e32 v2, v3, v2 +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v21 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v46 -; SI-NEXT: v_add_i32_e32 v6, vcc, 12, v0 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v54 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v2, v27 +; SI-NEXT: v_add_i32_e32 v3, vcc, 8, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v43 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v44 -; SI-NEXT: v_add_i32_e32 v6, vcc, 16, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v19 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v26 +; SI-NEXT: v_add_i32_e32 v3, vcc, 12, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v41 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v9 -; SI-NEXT: v_add_i32_e32 v6, vcc, 20, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v63 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v24 +; SI-NEXT: v_add_i32_e32 v3, vcc, 16, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v55 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v40 -; SI-NEXT: v_add_i32_e32 v6, vcc, 24, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v61 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v22 +; SI-NEXT: v_add_i32_e32 v3, vcc, 20, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v53 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v13 -; SI-NEXT: v_add_i32_e32 v6, vcc, 28, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v59 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v20 +; SI-NEXT: v_add_i32_e32 v3, vcc, 24, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v51 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v52 -; SI-NEXT: v_add_i32_e32 v6, vcc, 32, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v57 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v18 +; SI-NEXT: v_add_i32_e32 v3, vcc, 28, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v49 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v17 -; SI-NEXT: v_add_i32_e32 v6, vcc, 36, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v47 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v17 +; SI-NEXT: v_add_i32_e32 v3, vcc, 32, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v39 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v48 -; SI-NEXT: v_add_i32_e32 v6, vcc, 40, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v45 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v62 +; SI-NEXT: v_add_i32_e32 v3, vcc, 36, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v36 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v18 -; SI-NEXT: v_add_i32_e32 v6, vcc, 44, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v43 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v60 +; SI-NEXT: v_add_i32_e32 v3, vcc, 40, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v34 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v37 -; SI-NEXT: v_add_i32_e32 v6, vcc, 48, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v41 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v58 +; SI-NEXT: v_add_i32_e32 v3, vcc, 44, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v32 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v16 -; SI-NEXT: v_add_i32_e32 v6, vcc, 52, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v54 +; SI-NEXT: v_add_i32_e32 v3, vcc, 48, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v30 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v33 -; SI-NEXT: v_add_i32_e32 v6, vcc, 56, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v52 +; SI-NEXT: v_add_i32_e32 v3, vcc, 52, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v28 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v31 -; SI-NEXT: v_add_i32_e32 v6, vcc, 60, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 56, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v26 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v29 -; SI-NEXT: v_add_i32_e32 v6, vcc, 64, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 60, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v24 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v27 -; SI-NEXT: v_add_i32_e32 v6, vcc, 0x44, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 64, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v22 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v25 -; SI-NEXT: v_add_i32_e32 v6, vcc, 0x48, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x44, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v19 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v23 -; SI-NEXT: v_add_i32_e32 v6, vcc, 0x4c, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x48, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v8 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v21 -; SI-NEXT: v_add_i32_e32 v6, vcc, 0x50, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x4c, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v15 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v20 -; SI-NEXT: v_add_i32_e32 v6, vcc, 0x54, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x50, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v12 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v63 -; SI-NEXT: v_add_i32_e32 v6, vcc, 0x58, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x54, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v11 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v62 -; SI-NEXT: v_add_i32_e32 v6, vcc, 0x5c, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x58, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v35 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v61 -; SI-NEXT: v_add_i32_e32 v6, vcc, 0x60, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v53 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x5c, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v57 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v1 -; SI-NEXT: v_add_i32_e32 v6, vcc, 0x64, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v55 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x60, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v50 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v47 -; SI-NEXT: v_add_i32_e32 v6, vcc, 0x68, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v40 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x64, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v45 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_add_i32_e32 v5, vcc, 0x6c, v0 -; SI-NEXT: v_or_b32_e32 v3, v4, v3 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v42 -; SI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v42 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x68, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v38 -; SI-NEXT: v_add_i32_e32 v4, vcc, 0x70, v0 -; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; SI-NEXT: v_or_b32_e32 v2, v3, v2 -; SI-NEXT: v_cvt_f16_f32_e32 v1, v59 -; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v44 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x6c, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v2, v14 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v46 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x70, v0 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x74, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v56 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload @@ -22065,66 +21825,93 @@ define inreg <60 x half> @bitcast_v30f32_to_v60f16_scalar(<30 x float> inreg %a, ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] ; SI-NEXT: .LBB33_4: -; SI-NEXT: ; implicit-def: $vgpr7 -; SI-NEXT: ; implicit-def: $vgpr60 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr58 -; SI-NEXT: ; implicit-def: $vgpr3 -; SI-NEXT: ; implicit-def: $vgpr56 -; SI-NEXT: ; implicit-def: $vgpr5 -; SI-NEXT: ; implicit-def: $vgpr46 -; SI-NEXT: ; implicit-def: $vgpr44 -; SI-NEXT: ; implicit-def: $vgpr43 -; SI-NEXT: ; implicit-def: $vgpr9 -; SI-NEXT: ; implicit-def: $vgpr41 -; SI-NEXT: ; implicit-def: $vgpr40 -; SI-NEXT: ; implicit-def: $vgpr55 -; SI-NEXT: ; implicit-def: $vgpr13 ; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; kill: killed $vgpr53 ; SI-NEXT: ; implicit-def: $vgpr52 -; SI-NEXT: ; implicit-def: $vgpr51 -; SI-NEXT: ; implicit-def: $vgpr17 -; SI-NEXT: ; implicit-def: $vgpr49 -; SI-NEXT: ; implicit-def: $vgpr48 -; SI-NEXT: ; implicit-def: $vgpr39 -; SI-NEXT: ; implicit-def: $vgpr18 -; SI-NEXT: ; implicit-def: $vgpr36 -; SI-NEXT: ; implicit-def: $vgpr37 -; SI-NEXT: ; implicit-def: $vgpr34 -; SI-NEXT: ; implicit-def: $vgpr16 -; SI-NEXT: ; implicit-def: $vgpr32 -; SI-NEXT: ; implicit-def: $vgpr33 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; kill: killed $vgpr53 +; SI-NEXT: ; kill: killed $vgpr52 +; SI-NEXT: ; implicit-def: $vgpr52 +; SI-NEXT: ; implicit-def: $vgpr55 +; SI-NEXT: ; implicit-def: $vgpr40 +; SI-NEXT: ; implicit-def: $vgpr42 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr46 +; SI-NEXT: ; implicit-def: $vgpr56 ; SI-NEXT: ; implicit-def: $vgpr30 -; SI-NEXT: ; implicit-def: $vgpr31 -; SI-NEXT: ; implicit-def: $vgpr28 -; SI-NEXT: ; implicit-def: $vgpr29 -; SI-NEXT: ; implicit-def: $vgpr26 -; SI-NEXT: ; implicit-def: $vgpr27 -; SI-NEXT: ; implicit-def: $vgpr24 ; SI-NEXT: ; implicit-def: $vgpr25 -; SI-NEXT: ; implicit-def: $vgpr22 +; SI-NEXT: ; implicit-def: $vgpr28 ; SI-NEXT: ; implicit-def: $vgpr23 -; SI-NEXT: ; implicit-def: $vgpr19 +; SI-NEXT: ; implicit-def: $vgpr27 ; SI-NEXT: ; implicit-def: $vgpr21 -; SI-NEXT: ; implicit-def: $vgpr8 -; SI-NEXT: ; implicit-def: $vgpr20 -; SI-NEXT: ; implicit-def: $vgpr15 +; SI-NEXT: ; implicit-def: $vgpr26 +; SI-NEXT: ; implicit-def: $vgpr19 +; SI-NEXT: ; implicit-def: $vgpr24 ; SI-NEXT: ; implicit-def: $vgpr63 -; SI-NEXT: ; implicit-def: $vgpr12 -; SI-NEXT: ; implicit-def: $vgpr62 -; SI-NEXT: ; implicit-def: $vgpr11 +; SI-NEXT: ; implicit-def: $vgpr22 ; SI-NEXT: ; implicit-def: $vgpr61 -; SI-NEXT: ; implicit-def: $vgpr35 -; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: ; implicit-def: $vgpr20 +; SI-NEXT: ; implicit-def: $vgpr59 +; SI-NEXT: ; implicit-def: $vgpr18 ; SI-NEXT: ; implicit-def: $vgpr57 +; SI-NEXT: ; implicit-def: $vgpr17 ; SI-NEXT: ; implicit-def: $vgpr47 -; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; implicit-def: $vgpr62 ; SI-NEXT: ; implicit-def: $vgpr45 +; SI-NEXT: ; implicit-def: $vgpr60 +; SI-NEXT: ; implicit-def: $vgpr43 +; SI-NEXT: ; implicit-def: $vgpr58 +; SI-NEXT: ; implicit-def: $vgpr41 ; SI-NEXT: ; implicit-def: $vgpr54 -; SI-NEXT: ; implicit-def: $vgpr38 +; SI-NEXT: ; kill: killed $vgpr52 +; SI-NEXT: ; kill: killed $vgpr55 +; SI-NEXT: ; implicit-def: $vgpr55 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; kill: killed $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr52 +; SI-NEXT: ; kill: killed $vgpr40 +; SI-NEXT: ; implicit-def: $vgpr40 +; SI-NEXT: ; kill: killed $vgpr42 ; SI-NEXT: ; implicit-def: $vgpr42 -; SI-NEXT: ; implicit-def: $vgpr14 -; SI-NEXT: ; implicit-def: $vgpr59 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr46 +; SI-NEXT: ; implicit-def: $vgpr46 +; SI-NEXT: ; kill: killed $vgpr56 +; SI-NEXT: ; implicit-def: $vgpr56 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; kill: killed $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; kill: killed $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; kill: killed $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; kill: killed $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; kill: killed $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; kill: killed $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; kill: killed $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; kill: killed $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; kill: killed $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; kill: killed $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; kill: killed $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; kill: killed $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; kill: killed $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; kill: killed $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; kill: killed $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; kill: killed $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr53 ; SI-NEXT: s_branch .LBB33_2 ; ; VI-LABEL: bitcast_v30f32_to_v60f16_scalar: @@ -23044,6 +22831,9 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(5) +; SI-NEXT: v_cvt_f16_f32_e32 v58, v0 +; SI-NEXT: v_cvt_f16_f32_e32 v0, v5 ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116 ; SI-NEXT: s_waitcnt expcnt(3) ; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 @@ -23072,23 +22862,12 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:76 ; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:88 ; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:84 -; SI-NEXT: v_cvt_f16_f32_e32 v58, v0 -; SI-NEXT: v_cvt_f16_f32_e32 v0, v5 ; SI-NEXT: v_cvt_f16_f32_e32 v59, v1 ; SI-NEXT: v_cvt_f16_f32_e32 v57, v3 -; SI-NEXT: v_cvt_f16_f32_e32 v56, v2 -; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:96 -; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:92 -; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:104 -; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:100 -; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:112 -; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:108 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v60, v60 +; SI-NEXT: v_cvt_f16_f32_e32 v56, v2 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v7 @@ -23098,8 +22877,6 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v9 -; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_cvt_f16_f32_e32 v52, v52 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v8 @@ -23121,9 +22898,18 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v14 +; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v17 +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:96 +; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:92 +; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:104 +; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:100 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:112 +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:108 +; SI-NEXT: v_cvt_f16_f32_e32 v60, v60 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v16 @@ -23133,6 +22919,7 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v18 +; SI-NEXT: v_cvt_f16_f32_e32 v52, v52 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v21 @@ -23170,7 +22957,6 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) { ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v61 ; SI-NEXT: v_cvt_f16_f32_e32 v61, v49 -; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cvt_f16_f32_e32 v49, v55 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -23185,6 +22971,7 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v32 +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cvt_f16_f32_e32 v32, v47 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -24056,7 +23843,6 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v61, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v29 -; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v28 @@ -24135,6 +23921,7 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) { ; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v60 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v61 +; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -24299,6 +24086,9 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) { ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] ; GFX9-NEXT: s_cbranch_execz .LBB34_4 ; GFX9-NEXT: ; %bb.3: ; %cmp.true +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload @@ -24313,9 +24103,6 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload -; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v38, v61, s6 ; GFX9-NEXT: s_movk_i32 s7, 0x200 ; GFX9-NEXT: v_perm_b32 v1, v37, v60, s6 @@ -24335,6 +24122,10 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) { ; GFX9-NEXT: v_pk_add_f16 v6, v6, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v7, v7, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v8, v8, s7 op_sel_hi:[1,0] +; GFX9-NEXT: s_waitcnt vmcnt(14) +; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; GFX9-NEXT: s_waitcnt vmcnt(15) ; GFX9-NEXT: v_perm_b32 v9, v9, v44, s6 ; GFX9-NEXT: s_waitcnt vmcnt(14) @@ -24363,10 +24154,6 @@ define <30 x float> @bitcast_v60f16_to_v30f32(<60 x half> %a, i32 %b) { ; GFX9-NEXT: v_perm_b32 v21, v21, v48, s6 ; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: v_perm_b32 v22, v22, v39, s6 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v10, v10, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0] @@ -24687,12 +24474,35 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a, ; SI-NEXT: v_cvt_f16_f32_e32 v8, s26 ; SI-NEXT: v_cvt_f16_f32_e32 v6, s29 ; SI-NEXT: v_cvt_f16_f32_e32 v7, s28 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: v_cvt_f16_f32_e32 v50, v54 ; SI-NEXT: v_cvt_f16_f32_e32 v48, v48 ; SI-NEXT: v_cvt_f16_f32_e32 v31, v40 -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v33 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill @@ -24702,7 +24512,7 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a, ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v38 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0) +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v44 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -24711,7 +24521,7 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a, ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v46 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0) +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v47 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -24720,7 +24530,7 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a, ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v57 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0) +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v58 ; SI-NEXT: v_cvt_f16_f32_e32 v58, s16 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill @@ -24731,38 +24541,12 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a, ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v60 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB35_2 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(4) ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; SI-NEXT: v_or_b32_e32 v3, v10, v3 -; SI-NEXT: s_waitcnt expcnt(3) ; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34 ; SI-NEXT: v_mov_b32_e32 v33, v32 ; SI-NEXT: v_or_b32_e32 v10, v32, v10 @@ -24787,12 +24571,12 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a, ; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18 ; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v59 ; SI-NEXT: v_or_b32_e32 v1, v12, v1 ; SI-NEXT: v_or_b32_e32 v2, v11, v2 @@ -24901,12 +24685,10 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a, ; SI-NEXT: v_mov_b32_e32 v40, v44 ; SI-NEXT: s_cbranch_vccnz .LBB35_5 ; SI-NEXT: ; %bb.4: ; %cmp.true -; SI-NEXT: s_waitcnt expcnt(5) ; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(4) ; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; SI-NEXT: v_cvt_f32_f16_e32 v0, v59 ; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v0, v59 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v58 ; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_cvt_f32_f16_e32 v8, v33 @@ -25692,304 +25474,115 @@ define inreg <30 x float> @bitcast_v60f16_to_v30f32_scalar(<60 x half> inreg %a, ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v190, v6 :: v_dual_mov_b32 v185, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v186, v3 :: v_dual_mov_b32 v187, v2 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v1 :: v_dual_mov_b32 v189, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB35_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB35_3 ; GFX11-TRUE16-NEXT: .LBB35_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s40 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s41 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v189, 0x200, v189 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v188, 0x200, v188 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v187, 0x200, v187 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v186, 0x200, v186 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v185, 0x200, v185 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v191, 0x200, v191 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v190, 0x200, v190 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, s6 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, s7 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, s8 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s9 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, s10 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, s11 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, s12 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, s13 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s14 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, s15 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, s16 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v30, 0x200, v30 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s0 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s1 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s2 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, s3 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, s4 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v35, 0x200, s5 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v44, 0x200, s6 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v54, 0x200, s7 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v65, 0x200, s8 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v77, 0x200, s9 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v90, 0x200, s10 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v104, 0x200, s11 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v119, 0x200, s12 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v135, 0x200, s13 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v152, 0x200, s14 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v170, 0x200, s15 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: .LBB35_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v170 :: v_dual_mov_b32 v18, v189 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v188 :: v_dual_mov_b32 v20, v187 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v186 :: v_dual_mov_b32 v22, v185 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v191 :: v_dual_mov_b32 v24, v190 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v191, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v190, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v189, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v188, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v187, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:316 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v119 :: v_dual_mov_b32 v27, v30 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB35_4: -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v64, v29 :: v_dual_mov_b32 v65, v28 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v66, v30 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v53, v26 :: v_dual_mov_b32 v54, v25 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v54 :: v_dual_mov_b32 v26, v53 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v65 :: v_dual_mov_b32 v29, v64 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v30, v66 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB35_2 ; ; GFX11-FAKE16-LABEL: bitcast_v60f16_to_v30f32_scalar: @@ -28056,30 +27649,58 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v18, s30, 0 -; SI-NEXT: v_writelane_b32 v18, s31, 1 -; SI-NEXT: v_writelane_b32 v18, s34, 2 -; SI-NEXT: v_writelane_b32 v18, s35, 3 -; SI-NEXT: v_writelane_b32 v18, s36, 4 -; SI-NEXT: v_writelane_b32 v18, s37, 5 -; SI-NEXT: v_writelane_b32 v18, s38, 6 -; SI-NEXT: v_writelane_b32 v18, s39, 7 -; SI-NEXT: v_writelane_b32 v18, s48, 8 -; SI-NEXT: v_writelane_b32 v18, s49, 9 -; SI-NEXT: v_writelane_b32 v18, s50, 10 -; SI-NEXT: v_writelane_b32 v18, s51, 11 -; SI-NEXT: v_writelane_b32 v18, s52, 12 -; SI-NEXT: v_writelane_b32 v18, s53, 13 -; SI-NEXT: v_writelane_b32 v18, s54, 14 +; SI-NEXT: v_writelane_b32 v20, s30, 0 +; SI-NEXT: v_writelane_b32 v20, s31, 1 +; SI-NEXT: v_writelane_b32 v20, s34, 2 +; SI-NEXT: v_writelane_b32 v20, s35, 3 +; SI-NEXT: v_writelane_b32 v20, s36, 4 +; SI-NEXT: v_writelane_b32 v20, s37, 5 +; SI-NEXT: v_writelane_b32 v20, s38, 6 +; SI-NEXT: v_writelane_b32 v20, s39, 7 +; SI-NEXT: v_writelane_b32 v20, s48, 8 +; SI-NEXT: v_mov_b32_e32 v18, s16 +; SI-NEXT: v_mov_b32_e32 v19, s17 +; SI-NEXT: v_writelane_b32 v20, s49, 9 +; SI-NEXT: v_readfirstlane_b32 s46, v18 +; SI-NEXT: v_mov_b32_e32 v18, s18 +; SI-NEXT: v_readfirstlane_b32 s47, v19 +; SI-NEXT: v_mov_b32_e32 v19, s19 +; SI-NEXT: v_writelane_b32 v20, s50, 10 +; SI-NEXT: v_readfirstlane_b32 s44, v18 +; SI-NEXT: v_mov_b32_e32 v18, s20 +; SI-NEXT: v_readfirstlane_b32 s45, v19 +; SI-NEXT: v_mov_b32_e32 v19, s21 +; SI-NEXT: v_writelane_b32 v20, s51, 11 +; SI-NEXT: v_readfirstlane_b32 s42, v18 +; SI-NEXT: v_mov_b32_e32 v18, s22 +; SI-NEXT: v_readfirstlane_b32 s43, v19 +; SI-NEXT: v_mov_b32_e32 v19, s23 +; SI-NEXT: v_writelane_b32 v20, s52, 12 +; SI-NEXT: v_readfirstlane_b32 s40, v18 +; SI-NEXT: v_mov_b32_e32 v18, s24 +; SI-NEXT: v_readfirstlane_b32 s41, v19 +; SI-NEXT: v_mov_b32_e32 v19, s25 +; SI-NEXT: v_writelane_b32 v20, s53, 13 +; SI-NEXT: v_readfirstlane_b32 s24, v18 +; SI-NEXT: v_mov_b32_e32 v18, s26 +; SI-NEXT: v_readfirstlane_b32 s25, v19 +; SI-NEXT: v_mov_b32_e32 v19, s27 +; SI-NEXT: v_writelane_b32 v20, s54, 14 +; SI-NEXT: v_readfirstlane_b32 s22, v18 +; SI-NEXT: v_mov_b32_e32 v18, s28 +; SI-NEXT: v_readfirstlane_b32 s23, v19 +; SI-NEXT: v_mov_b32_e32 v19, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; SI-NEXT: v_writelane_b32 v18, s55, 15 -; SI-NEXT: v_readfirstlane_b32 s42, v1 -; SI-NEXT: v_readfirstlane_b32 s43, v2 -; SI-NEXT: v_readfirstlane_b32 s40, v3 -; SI-NEXT: v_readfirstlane_b32 s41, v4 +; SI-NEXT: v_writelane_b32 v20, s55, 15 +; SI-NEXT: v_readfirstlane_b32 s20, v18 +; SI-NEXT: v_readfirstlane_b32 s21, v19 +; SI-NEXT: v_readfirstlane_b32 s18, v1 +; SI-NEXT: v_readfirstlane_b32 s19, v2 +; SI-NEXT: v_readfirstlane_b32 s16, v3 +; SI-NEXT: v_readfirstlane_b32 s17, v4 ; SI-NEXT: v_readfirstlane_b32 s14, v5 ; SI-NEXT: v_readfirstlane_b32 s15, v6 ; SI-NEXT: v_readfirstlane_b32 s12, v7 @@ -28091,9 +27712,9 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s6, v13 ; SI-NEXT: v_readfirstlane_b32 s7, v14 ; SI-NEXT: v_readfirstlane_b32 s4, v15 -; SI-NEXT: s_and_b64 s[44:45], vcc, exec +; SI-NEXT: s_and_b64 s[26:27], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v16 -; SI-NEXT: v_writelane_b32 v18, s64, 16 +; SI-NEXT: v_writelane_b32 v20, s64, 16 ; SI-NEXT: s_cbranch_scc0 .LBB41_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s34, s5, 16 @@ -28102,30 +27723,30 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; SI-NEXT: s_lshr_b32 s37, s11, 16 ; SI-NEXT: s_lshr_b32 s38, s13, 16 ; SI-NEXT: s_lshr_b32 s39, s15, 16 -; SI-NEXT: s_lshr_b32 s48, s41, 16 -; SI-NEXT: s_lshr_b32 s49, s43, 16 -; SI-NEXT: s_lshr_b32 s50, s29, 16 -; SI-NEXT: s_lshr_b32 s51, s27, 16 +; SI-NEXT: s_lshr_b32 s48, s17, 16 +; SI-NEXT: s_lshr_b32 s49, s19, 16 +; SI-NEXT: s_lshr_b32 s50, s21, 16 +; SI-NEXT: s_lshr_b32 s51, s23, 16 ; SI-NEXT: s_lshr_b32 s52, s25, 16 -; SI-NEXT: s_lshr_b32 s53, s23, 16 -; SI-NEXT: s_lshr_b32 s54, s21, 16 -; SI-NEXT: s_lshr_b32 s55, s19, 16 -; SI-NEXT: s_lshr_b32 s64, s17, 16 -; SI-NEXT: s_lshr_b64 s[44:45], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 16 +; SI-NEXT: s_lshr_b32 s53, s41, 16 +; SI-NEXT: s_lshr_b32 s54, s43, 16 +; SI-NEXT: s_lshr_b32 s55, s45, 16 +; SI-NEXT: s_lshr_b32 s64, s47, 16 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[6:7], 16 ; SI-NEXT: s_lshr_b64 s[56:57], s[8:9], 16 ; SI-NEXT: s_lshr_b64 s[58:59], s[10:11], 16 ; SI-NEXT: s_lshr_b64 s[60:61], s[12:13], 16 ; SI-NEXT: s_lshr_b64 s[62:63], s[14:15], 16 -; SI-NEXT: s_lshr_b64 s[72:73], s[40:41], 16 -; SI-NEXT: s_lshr_b64 s[74:75], s[42:43], 16 -; SI-NEXT: s_lshr_b64 s[76:77], s[28:29], 16 -; SI-NEXT: s_lshr_b64 s[78:79], s[26:27], 16 +; SI-NEXT: s_lshr_b64 s[72:73], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[74:75], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[76:77], s[20:21], 16 +; SI-NEXT: s_lshr_b64 s[78:79], s[22:23], 16 ; SI-NEXT: s_lshr_b64 s[88:89], s[24:25], 16 -; SI-NEXT: s_lshr_b64 s[90:91], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[92:93], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[94:95], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[30:31], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[90:91], s[40:41], 16 +; SI-NEXT: s_lshr_b64 s[92:93], s[42:43], 16 +; SI-NEXT: s_lshr_b64 s[94:95], s[44:45], 16 +; SI-NEXT: s_lshr_b64 s[30:31], s[46:47], 16 ; SI-NEXT: s_cbranch_execnz .LBB41_3 ; SI-NEXT: .LBB41_2: ; %cmp.true ; SI-NEXT: s_add_u32 s4, s4, 3 @@ -28140,167 +27761,167 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; SI-NEXT: s_addc_u32 s13, s13, 0 ; SI-NEXT: s_add_u32 s14, s14, 3 ; SI-NEXT: s_addc_u32 s15, s15, 0 +; SI-NEXT: s_add_u32 s16, s16, 3 +; SI-NEXT: s_addc_u32 s17, s17, 0 +; SI-NEXT: s_add_u32 s18, s18, 3 +; SI-NEXT: s_addc_u32 s19, s19, 0 +; SI-NEXT: s_add_u32 s20, s20, 3 +; SI-NEXT: s_addc_u32 s21, s21, 0 +; SI-NEXT: s_add_u32 s22, s22, 3 +; SI-NEXT: s_addc_u32 s23, s23, 0 +; SI-NEXT: s_add_u32 s24, s24, 3 +; SI-NEXT: s_addc_u32 s25, s25, 0 ; SI-NEXT: s_add_u32 s40, s40, 3 ; SI-NEXT: s_addc_u32 s41, s41, 0 ; SI-NEXT: s_add_u32 s42, s42, 3 ; SI-NEXT: s_addc_u32 s43, s43, 0 -; SI-NEXT: s_add_u32 s28, s28, 3 -; SI-NEXT: s_addc_u32 s29, s29, 0 -; SI-NEXT: s_add_u32 s26, s26, 3 -; SI-NEXT: s_addc_u32 s27, s27, 0 -; SI-NEXT: s_add_u32 s24, s24, 3 -; SI-NEXT: s_addc_u32 s25, s25, 0 -; SI-NEXT: s_add_u32 s22, s22, 3 -; SI-NEXT: s_addc_u32 s23, s23, 0 -; SI-NEXT: s_add_u32 s20, s20, 3 -; SI-NEXT: s_addc_u32 s21, s21, 0 -; SI-NEXT: s_add_u32 s18, s18, 3 -; SI-NEXT: s_addc_u32 s19, s19, 0 -; SI-NEXT: s_add_u32 s16, s16, 3 -; SI-NEXT: s_addc_u32 s17, s17, 0 +; SI-NEXT: s_add_u32 s44, s44, 3 +; SI-NEXT: s_addc_u32 s45, s45, 0 +; SI-NEXT: s_add_u32 s46, s46, 3 +; SI-NEXT: s_addc_u32 s47, s47, 0 ; SI-NEXT: s_lshr_b32 s34, s5, 16 ; SI-NEXT: s_lshr_b32 s35, s7, 16 ; SI-NEXT: s_lshr_b32 s36, s9, 16 ; SI-NEXT: s_lshr_b32 s37, s11, 16 ; SI-NEXT: s_lshr_b32 s38, s13, 16 ; SI-NEXT: s_lshr_b32 s39, s15, 16 -; SI-NEXT: s_lshr_b32 s48, s41, 16 -; SI-NEXT: s_lshr_b32 s49, s43, 16 -; SI-NEXT: s_lshr_b32 s50, s29, 16 -; SI-NEXT: s_lshr_b32 s51, s27, 16 +; SI-NEXT: s_lshr_b32 s48, s17, 16 +; SI-NEXT: s_lshr_b32 s49, s19, 16 +; SI-NEXT: s_lshr_b32 s50, s21, 16 +; SI-NEXT: s_lshr_b32 s51, s23, 16 ; SI-NEXT: s_lshr_b32 s52, s25, 16 -; SI-NEXT: s_lshr_b32 s53, s23, 16 -; SI-NEXT: s_lshr_b32 s54, s21, 16 -; SI-NEXT: s_lshr_b32 s55, s19, 16 -; SI-NEXT: s_lshr_b32 s64, s17, 16 -; SI-NEXT: s_lshr_b64 s[44:45], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 16 +; SI-NEXT: s_lshr_b32 s53, s41, 16 +; SI-NEXT: s_lshr_b32 s54, s43, 16 +; SI-NEXT: s_lshr_b32 s55, s45, 16 +; SI-NEXT: s_lshr_b32 s64, s47, 16 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[6:7], 16 ; SI-NEXT: s_lshr_b64 s[56:57], s[8:9], 16 ; SI-NEXT: s_lshr_b64 s[58:59], s[10:11], 16 ; SI-NEXT: s_lshr_b64 s[60:61], s[12:13], 16 ; SI-NEXT: s_lshr_b64 s[62:63], s[14:15], 16 -; SI-NEXT: s_lshr_b64 s[72:73], s[40:41], 16 -; SI-NEXT: s_lshr_b64 s[74:75], s[42:43], 16 -; SI-NEXT: s_lshr_b64 s[76:77], s[28:29], 16 -; SI-NEXT: s_lshr_b64 s[78:79], s[26:27], 16 +; SI-NEXT: s_lshr_b64 s[72:73], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[74:75], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[76:77], s[20:21], 16 +; SI-NEXT: s_lshr_b64 s[78:79], s[22:23], 16 ; SI-NEXT: s_lshr_b64 s[88:89], s[24:25], 16 -; SI-NEXT: s_lshr_b64 s[90:91], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[92:93], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[94:95], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[30:31], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[90:91], s[40:41], 16 +; SI-NEXT: s_lshr_b64 s[92:93], s[42:43], 16 +; SI-NEXT: s_lshr_b64 s[94:95], s[44:45], 16 +; SI-NEXT: s_lshr_b64 s[30:31], s[46:47], 16 ; SI-NEXT: .LBB41_3: ; %end -; SI-NEXT: s_lshl_b32 s45, s30, 16 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s45 -; SI-NEXT: v_mov_b32_e32 v1, s16 -; SI-NEXT: s_and_b32 s16, s17, 0xffff -; SI-NEXT: s_lshl_b32 s17, s64, 16 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_lshl_b32 s16, s94, 16 -; SI-NEXT: s_and_b32 s17, s18, 0xffff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: v_mov_b32_e32 v3, s16 -; SI-NEXT: s_and_b32 s16, s19, 0xffff -; SI-NEXT: s_lshl_b32 s17, s55, 16 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v4, s16 -; SI-NEXT: s_lshl_b32 s16, s92, 16 -; SI-NEXT: s_and_b32 s17, s20, 0xffff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: v_mov_b32_e32 v5, s16 -; SI-NEXT: s_and_b32 s16, s21, 0xffff -; SI-NEXT: s_lshl_b32 s17, s54, 16 +; SI-NEXT: s_lshl_b32 s27, s30, 16 +; SI-NEXT: s_and_b32 s29, s46, 0xffff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: v_mov_b32_e32 v1, s27 +; SI-NEXT: s_and_b32 s27, s47, 0xffff +; SI-NEXT: s_lshl_b32 s29, s64, 16 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_lshl_b32 s27, s94, 16 +; SI-NEXT: s_and_b32 s29, s44, 0xffff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: v_mov_b32_e32 v3, s27 +; SI-NEXT: s_and_b32 s27, s45, 0xffff +; SI-NEXT: s_lshl_b32 s29, s55, 16 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v4, s27 +; SI-NEXT: s_lshl_b32 s27, s92, 16 +; SI-NEXT: s_and_b32 s29, s42, 0xffff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: v_mov_b32_e32 v5, s27 +; SI-NEXT: s_and_b32 s27, s43, 0xffff +; SI-NEXT: s_lshl_b32 s29, s54, 16 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s27, s27, s29 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0 -; SI-NEXT: v_mov_b32_e32 v6, s16 +; SI-NEXT: v_mov_b32_e32 v6, s27 ; SI-NEXT: buffer_store_dword v3, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 12, v0 -; SI-NEXT: s_lshl_b32 s16, s90, 16 -; SI-NEXT: s_and_b32 s17, s22, 0xffff +; SI-NEXT: s_lshl_b32 s27, s90, 16 +; SI-NEXT: s_and_b32 s29, s40, 0xffff ; SI-NEXT: buffer_store_dword v4, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0 -; SI-NEXT: s_or_b32 s16, s17, s16 +; SI-NEXT: s_or_b32 s27, s29, s27 ; SI-NEXT: buffer_store_dword v5, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 20, v0 ; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s23, 0xffff -; SI-NEXT: s_lshl_b32 s17, s53, 16 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_and_b32 s27, s41, 0xffff +; SI-NEXT: s_lshl_b32 s29, s53, 16 ; SI-NEXT: buffer_store_dword v6, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s27, s27, s29 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s24, 0xffff -; SI-NEXT: s_lshl_b32 s17, s88, 16 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_and_b32 s24, s24, 0xffff +; SI-NEXT: s_lshl_b32 s27, s88, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 28, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s24, s24, s27 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s25, 0xffff -; SI-NEXT: s_lshl_b32 s17, s52, 16 +; SI-NEXT: v_mov_b32_e32 v2, s24 +; SI-NEXT: s_and_b32 s24, s25, 0xffff +; SI-NEXT: s_lshl_b32 s25, s52, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s24, s24, s25 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s26, 0xffff -; SI-NEXT: s_lshl_b32 s17, s78, 16 +; SI-NEXT: v_mov_b32_e32 v2, s24 +; SI-NEXT: s_and_b32 s22, s22, 0xffff +; SI-NEXT: s_lshl_b32 s24, s78, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 36, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s22, s22, s24 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s27, 0xffff -; SI-NEXT: s_lshl_b32 s17, s51, 16 +; SI-NEXT: v_mov_b32_e32 v2, s22 +; SI-NEXT: s_and_b32 s22, s23, 0xffff +; SI-NEXT: s_lshl_b32 s23, s51, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s22, s22, s23 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s28, 0xffff -; SI-NEXT: s_lshl_b32 s17, s76, 16 +; SI-NEXT: v_mov_b32_e32 v2, s22 +; SI-NEXT: s_and_b32 s20, s20, 0xffff +; SI-NEXT: s_lshl_b32 s22, s76, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 44, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s20, s20, s22 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s29, 0xffff -; SI-NEXT: s_lshl_b32 s17, s50, 16 +; SI-NEXT: v_mov_b32_e32 v2, s20 +; SI-NEXT: s_and_b32 s20, s21, 0xffff +; SI-NEXT: s_lshl_b32 s21, s50, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s20, s20, s21 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s42, 0xffff -; SI-NEXT: s_lshl_b32 s17, s74, 16 +; SI-NEXT: v_mov_b32_e32 v2, s20 +; SI-NEXT: s_and_b32 s18, s18, 0xffff +; SI-NEXT: s_lshl_b32 s20, s74, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 52, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s18, s18, s20 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s43, 0xffff -; SI-NEXT: s_lshl_b32 s17, s49, 16 +; SI-NEXT: v_mov_b32_e32 v2, s18 +; SI-NEXT: s_and_b32 s18, s19, 0xffff +; SI-NEXT: s_lshl_b32 s19, s49, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 56, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s18, s18, s19 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s40, 0xffff -; SI-NEXT: s_lshl_b32 s17, s72, 16 +; SI-NEXT: v_mov_b32_e32 v2, s18 +; SI-NEXT: s_and_b32 s16, s16, 0xffff +; SI-NEXT: s_lshl_b32 s18, s72, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 60, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s16, s16, s18 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s41, 0xffff +; SI-NEXT: s_and_b32 s16, s17, 0xffff ; SI-NEXT: s_lshl_b32 s17, s48, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 64, v0 ; SI-NEXT: s_or_b32 s16, s16, s17 @@ -28364,7 +27985,7 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s8 ; SI-NEXT: s_and_b32 s6, s6, 0xffff -; SI-NEXT: s_lshl_b32 s8, s46, 16 +; SI-NEXT: s_lshl_b32 s8, s28, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x64, v0 ; SI-NEXT: s_or_b32 s6, s6, s8 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen @@ -28378,7 +27999,7 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s6 ; SI-NEXT: s_and_b32 s4, s4, 0xffff -; SI-NEXT: s_lshl_b32 s6, s44, 16 +; SI-NEXT: s_lshl_b32 s6, s26, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x6c, v0 ; SI-NEXT: s_or_b32 s4, s4, s6 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen @@ -28392,25 +28013,25 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x74, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s64, v18, 16 -; SI-NEXT: v_readlane_b32 s55, v18, 15 -; SI-NEXT: v_readlane_b32 s54, v18, 14 -; SI-NEXT: v_readlane_b32 s53, v18, 13 -; SI-NEXT: v_readlane_b32 s52, v18, 12 -; SI-NEXT: v_readlane_b32 s51, v18, 11 -; SI-NEXT: v_readlane_b32 s50, v18, 10 -; SI-NEXT: v_readlane_b32 s49, v18, 9 -; SI-NEXT: v_readlane_b32 s48, v18, 8 -; SI-NEXT: v_readlane_b32 s39, v18, 7 -; SI-NEXT: v_readlane_b32 s38, v18, 6 -; SI-NEXT: v_readlane_b32 s37, v18, 5 -; SI-NEXT: v_readlane_b32 s36, v18, 4 -; SI-NEXT: v_readlane_b32 s35, v18, 3 -; SI-NEXT: v_readlane_b32 s34, v18, 2 -; SI-NEXT: v_readlane_b32 s31, v18, 1 -; SI-NEXT: v_readlane_b32 s30, v18, 0 +; SI-NEXT: v_readlane_b32 s64, v20, 16 +; SI-NEXT: v_readlane_b32 s55, v20, 15 +; SI-NEXT: v_readlane_b32 s54, v20, 14 +; SI-NEXT: v_readlane_b32 s53, v20, 13 +; SI-NEXT: v_readlane_b32 s52, v20, 12 +; SI-NEXT: v_readlane_b32 s51, v20, 11 +; SI-NEXT: v_readlane_b32 s50, v20, 10 +; SI-NEXT: v_readlane_b32 s49, v20, 9 +; SI-NEXT: v_readlane_b32 s48, v20, 8 +; SI-NEXT: v_readlane_b32 s39, v20, 7 +; SI-NEXT: v_readlane_b32 s38, v20, 6 +; SI-NEXT: v_readlane_b32 s37, v20, 5 +; SI-NEXT: v_readlane_b32 s36, v20, 4 +; SI-NEXT: v_readlane_b32 s35, v20, 3 +; SI-NEXT: v_readlane_b32 s34, v20, 2 +; SI-NEXT: v_readlane_b32 s31, v20, 1 +; SI-NEXT: v_readlane_b32 s30, v20, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] @@ -28441,10 +28062,10 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; SI-NEXT: ; implicit-def: $sgpr37 ; SI-NEXT: ; implicit-def: $sgpr56 ; SI-NEXT: ; implicit-def: $sgpr36 -; SI-NEXT: ; implicit-def: $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr28 ; SI-NEXT: ; implicit-def: $sgpr35 ; SI-NEXT: ; implicit-def: $sgpr34 -; SI-NEXT: ; implicit-def: $sgpr44 +; SI-NEXT: ; implicit-def: $sgpr26 ; SI-NEXT: s_branch .LBB41_2 ; ; VI-LABEL: bitcast_v15i64_to_v60i16_scalar: @@ -28455,18 +28076,46 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; VI-NEXT: s_mov_b64 exec, s[4:5] ; VI-NEXT: v_writelane_b32 v30, s30, 0 ; VI-NEXT: v_writelane_b32 v30, s31, 1 +; VI-NEXT: v_mov_b32_e32 v17, s16 +; VI-NEXT: v_mov_b32_e32 v18, s17 ; VI-NEXT: v_writelane_b32 v30, s34, 2 +; VI-NEXT: v_mov_b32_e32 v19, s18 +; VI-NEXT: v_readfirstlane_b32 s56, v17 +; VI-NEXT: v_mov_b32_e32 v17, s19 +; VI-NEXT: v_readfirstlane_b32 s47, v18 +; VI-NEXT: v_mov_b32_e32 v18, s20 ; VI-NEXT: v_writelane_b32 v30, s35, 3 +; VI-NEXT: v_readfirstlane_b32 s46, v19 +; VI-NEXT: v_mov_b32_e32 v19, s21 +; VI-NEXT: v_readfirstlane_b32 s45, v17 +; VI-NEXT: v_mov_b32_e32 v17, s22 +; VI-NEXT: v_readfirstlane_b32 s44, v18 +; VI-NEXT: v_mov_b32_e32 v18, s23 ; VI-NEXT: v_writelane_b32 v30, s36, 4 +; VI-NEXT: v_readfirstlane_b32 s43, v19 +; VI-NEXT: v_mov_b32_e32 v19, s24 +; VI-NEXT: v_readfirstlane_b32 s42, v17 +; VI-NEXT: v_mov_b32_e32 v17, s25 +; VI-NEXT: v_readfirstlane_b32 s41, v18 +; VI-NEXT: v_mov_b32_e32 v18, s26 ; VI-NEXT: v_writelane_b32 v30, s37, 5 +; VI-NEXT: v_readfirstlane_b32 s40, v19 +; VI-NEXT: v_mov_b32_e32 v19, s27 +; VI-NEXT: v_readfirstlane_b32 s26, v17 +; VI-NEXT: v_mov_b32_e32 v17, s28 +; VI-NEXT: v_readfirstlane_b32 s25, v18 +; VI-NEXT: v_mov_b32_e32 v18, s29 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 ; VI-NEXT: v_writelane_b32 v30, s38, 6 -; VI-NEXT: v_readfirstlane_b32 s45, v0 -; VI-NEXT: v_readfirstlane_b32 s44, v1 -; VI-NEXT: v_readfirstlane_b32 s43, v2 -; VI-NEXT: v_readfirstlane_b32 s42, v3 -; VI-NEXT: v_readfirstlane_b32 s41, v4 -; VI-NEXT: v_readfirstlane_b32 s40, v5 +; VI-NEXT: v_readfirstlane_b32 s24, v19 +; VI-NEXT: v_readfirstlane_b32 s23, v17 +; VI-NEXT: v_readfirstlane_b32 s22, v18 +; VI-NEXT: v_readfirstlane_b32 s21, v0 +; VI-NEXT: v_readfirstlane_b32 s20, v1 +; VI-NEXT: v_readfirstlane_b32 s19, v2 +; VI-NEXT: v_readfirstlane_b32 s18, v3 +; VI-NEXT: v_readfirstlane_b32 s17, v4 +; VI-NEXT: v_readfirstlane_b32 s16, v5 ; VI-NEXT: v_readfirstlane_b32 s15, v6 ; VI-NEXT: v_readfirstlane_b32 s14, v7 ; VI-NEXT: v_readfirstlane_b32 s13, v8 @@ -28481,9 +28130,9 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; VI-NEXT: v_writelane_b32 v30, s39, 7 ; VI-NEXT: s_cbranch_scc0 .LBB41_4 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_lshr_b32 s46, s7, 16 -; VI-NEXT: s_lshr_b32 s47, s6, 16 -; VI-NEXT: s_lshr_b32 s56, s8, 16 +; VI-NEXT: s_lshr_b32 s27, s7, 16 +; VI-NEXT: s_lshr_b32 s28, s6, 16 +; VI-NEXT: s_lshr_b32 s29, s8, 16 ; VI-NEXT: s_lshr_b32 s57, s9, 16 ; VI-NEXT: s_lshr_b32 s58, s10, 16 ; VI-NEXT: s_lshr_b32 s59, s11, 16 @@ -28491,26 +28140,26 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; VI-NEXT: s_lshr_b32 s61, s13, 16 ; VI-NEXT: s_lshr_b32 s62, s14, 16 ; VI-NEXT: s_lshr_b32 s63, s15, 16 -; VI-NEXT: s_lshr_b32 s72, s40, 16 -; VI-NEXT: s_lshr_b32 s73, s41, 16 -; VI-NEXT: s_lshr_b32 s74, s42, 16 -; VI-NEXT: s_lshr_b32 s75, s43, 16 -; VI-NEXT: s_lshr_b32 s76, s44, 16 -; VI-NEXT: s_lshr_b32 s77, s45, 16 -; VI-NEXT: s_lshr_b32 s78, s29, 16 -; VI-NEXT: s_lshr_b32 s79, s28, 16 -; VI-NEXT: s_lshr_b32 s88, s27, 16 -; VI-NEXT: s_lshr_b32 s89, s26, 16 -; VI-NEXT: s_lshr_b32 s90, s25, 16 -; VI-NEXT: s_lshr_b32 s91, s24, 16 -; VI-NEXT: s_lshr_b32 s30, s23, 16 -; VI-NEXT: s_lshr_b32 s31, s22, 16 -; VI-NEXT: s_lshr_b32 s34, s21, 16 -; VI-NEXT: s_lshr_b32 s35, s20, 16 -; VI-NEXT: s_lshr_b32 s36, s19, 16 -; VI-NEXT: s_lshr_b32 s37, s18, 16 -; VI-NEXT: s_lshr_b32 s38, s17, 16 -; VI-NEXT: s_lshr_b32 s39, s16, 16 +; VI-NEXT: s_lshr_b32 s72, s16, 16 +; VI-NEXT: s_lshr_b32 s73, s17, 16 +; VI-NEXT: s_lshr_b32 s74, s18, 16 +; VI-NEXT: s_lshr_b32 s75, s19, 16 +; VI-NEXT: s_lshr_b32 s76, s20, 16 +; VI-NEXT: s_lshr_b32 s77, s21, 16 +; VI-NEXT: s_lshr_b32 s78, s22, 16 +; VI-NEXT: s_lshr_b32 s79, s23, 16 +; VI-NEXT: s_lshr_b32 s88, s24, 16 +; VI-NEXT: s_lshr_b32 s89, s25, 16 +; VI-NEXT: s_lshr_b32 s90, s26, 16 +; VI-NEXT: s_lshr_b32 s91, s40, 16 +; VI-NEXT: s_lshr_b32 s30, s41, 16 +; VI-NEXT: s_lshr_b32 s31, s42, 16 +; VI-NEXT: s_lshr_b32 s34, s43, 16 +; VI-NEXT: s_lshr_b32 s35, s44, 16 +; VI-NEXT: s_lshr_b32 s36, s45, 16 +; VI-NEXT: s_lshr_b32 s37, s46, 16 +; VI-NEXT: s_lshr_b32 s38, s47, 16 +; VI-NEXT: s_lshr_b32 s39, s56, 16 ; VI-NEXT: s_cbranch_execnz .LBB41_3 ; VI-NEXT: .LBB41_2: ; %cmp.true ; VI-NEXT: s_add_u32 s6, s6, 3 @@ -28523,29 +28172,29 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; VI-NEXT: s_addc_u32 s12, s12, 0 ; VI-NEXT: s_add_u32 s15, s15, 3 ; VI-NEXT: s_addc_u32 s14, s14, 0 -; VI-NEXT: s_add_u32 s41, s41, 3 -; VI-NEXT: s_addc_u32 s40, s40, 0 -; VI-NEXT: s_add_u32 s43, s43, 3 -; VI-NEXT: s_addc_u32 s42, s42, 0 -; VI-NEXT: s_add_u32 s45, s45, 3 -; VI-NEXT: s_addc_u32 s44, s44, 0 -; VI-NEXT: s_add_u32 s28, s28, 3 -; VI-NEXT: s_addc_u32 s29, s29, 0 -; VI-NEXT: s_add_u32 s26, s26, 3 -; VI-NEXT: s_addc_u32 s27, s27, 0 -; VI-NEXT: s_add_u32 s24, s24, 3 -; VI-NEXT: s_addc_u32 s25, s25, 0 -; VI-NEXT: s_add_u32 s22, s22, 3 -; VI-NEXT: s_addc_u32 s23, s23, 0 -; VI-NEXT: s_add_u32 s20, s20, 3 -; VI-NEXT: s_addc_u32 s21, s21, 0 -; VI-NEXT: s_add_u32 s18, s18, 3 -; VI-NEXT: s_addc_u32 s19, s19, 0 -; VI-NEXT: s_add_u32 s16, s16, 3 -; VI-NEXT: s_addc_u32 s17, s17, 0 -; VI-NEXT: s_lshr_b32 s46, s7, 16 -; VI-NEXT: s_lshr_b32 s47, s6, 16 -; VI-NEXT: s_lshr_b32 s56, s8, 16 +; VI-NEXT: s_add_u32 s17, s17, 3 +; VI-NEXT: s_addc_u32 s16, s16, 0 +; VI-NEXT: s_add_u32 s19, s19, 3 +; VI-NEXT: s_addc_u32 s18, s18, 0 +; VI-NEXT: s_add_u32 s21, s21, 3 +; VI-NEXT: s_addc_u32 s20, s20, 0 +; VI-NEXT: s_add_u32 s23, s23, 3 +; VI-NEXT: s_addc_u32 s22, s22, 0 +; VI-NEXT: s_add_u32 s25, s25, 3 +; VI-NEXT: s_addc_u32 s24, s24, 0 +; VI-NEXT: s_add_u32 s40, s40, 3 +; VI-NEXT: s_addc_u32 s26, s26, 0 +; VI-NEXT: s_add_u32 s42, s42, 3 +; VI-NEXT: s_addc_u32 s41, s41, 0 +; VI-NEXT: s_add_u32 s44, s44, 3 +; VI-NEXT: s_addc_u32 s43, s43, 0 +; VI-NEXT: s_add_u32 s46, s46, 3 +; VI-NEXT: s_addc_u32 s45, s45, 0 +; VI-NEXT: s_add_u32 s56, s56, 3 +; VI-NEXT: s_addc_u32 s47, s47, 0 +; VI-NEXT: s_lshr_b32 s27, s7, 16 +; VI-NEXT: s_lshr_b32 s28, s6, 16 +; VI-NEXT: s_lshr_b32 s29, s8, 16 ; VI-NEXT: s_lshr_b32 s57, s9, 16 ; VI-NEXT: s_lshr_b32 s58, s10, 16 ; VI-NEXT: s_lshr_b32 s59, s11, 16 @@ -28553,137 +28202,137 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; VI-NEXT: s_lshr_b32 s61, s13, 16 ; VI-NEXT: s_lshr_b32 s62, s14, 16 ; VI-NEXT: s_lshr_b32 s63, s15, 16 -; VI-NEXT: s_lshr_b32 s72, s40, 16 -; VI-NEXT: s_lshr_b32 s73, s41, 16 -; VI-NEXT: s_lshr_b32 s74, s42, 16 -; VI-NEXT: s_lshr_b32 s75, s43, 16 -; VI-NEXT: s_lshr_b32 s76, s44, 16 -; VI-NEXT: s_lshr_b32 s77, s45, 16 -; VI-NEXT: s_lshr_b32 s78, s29, 16 -; VI-NEXT: s_lshr_b32 s79, s28, 16 -; VI-NEXT: s_lshr_b32 s88, s27, 16 -; VI-NEXT: s_lshr_b32 s89, s26, 16 -; VI-NEXT: s_lshr_b32 s90, s25, 16 -; VI-NEXT: s_lshr_b32 s91, s24, 16 -; VI-NEXT: s_lshr_b32 s30, s23, 16 -; VI-NEXT: s_lshr_b32 s31, s22, 16 -; VI-NEXT: s_lshr_b32 s34, s21, 16 -; VI-NEXT: s_lshr_b32 s35, s20, 16 -; VI-NEXT: s_lshr_b32 s36, s19, 16 -; VI-NEXT: s_lshr_b32 s37, s18, 16 -; VI-NEXT: s_lshr_b32 s38, s17, 16 -; VI-NEXT: s_lshr_b32 s39, s16, 16 +; VI-NEXT: s_lshr_b32 s72, s16, 16 +; VI-NEXT: s_lshr_b32 s73, s17, 16 +; VI-NEXT: s_lshr_b32 s74, s18, 16 +; VI-NEXT: s_lshr_b32 s75, s19, 16 +; VI-NEXT: s_lshr_b32 s76, s20, 16 +; VI-NEXT: s_lshr_b32 s77, s21, 16 +; VI-NEXT: s_lshr_b32 s78, s22, 16 +; VI-NEXT: s_lshr_b32 s79, s23, 16 +; VI-NEXT: s_lshr_b32 s88, s24, 16 +; VI-NEXT: s_lshr_b32 s89, s25, 16 +; VI-NEXT: s_lshr_b32 s90, s26, 16 +; VI-NEXT: s_lshr_b32 s91, s40, 16 +; VI-NEXT: s_lshr_b32 s30, s41, 16 +; VI-NEXT: s_lshr_b32 s31, s42, 16 +; VI-NEXT: s_lshr_b32 s34, s43, 16 +; VI-NEXT: s_lshr_b32 s35, s44, 16 +; VI-NEXT: s_lshr_b32 s36, s45, 16 +; VI-NEXT: s_lshr_b32 s37, s46, 16 +; VI-NEXT: s_lshr_b32 s38, s47, 16 +; VI-NEXT: s_lshr_b32 s39, s56, 16 ; VI-NEXT: .LBB41_3: ; %end -; VI-NEXT: s_and_b32 s4, 0xffff, s16 +; VI-NEXT: s_and_b32 s4, 0xffff, s56 ; VI-NEXT: s_lshl_b32 s5, s39, 16 ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_and_b32 s5, 0xffff, s17 -; VI-NEXT: s_lshl_b32 s16, s38, 16 -; VI-NEXT: s_or_b32 s5, s5, s16 -; VI-NEXT: s_and_b32 s16, 0xffff, s18 -; VI-NEXT: s_lshl_b32 s17, s37, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, 0xffff, s19 -; VI-NEXT: s_lshl_b32 s18, s36, 16 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s18, 0xffff, s20 -; VI-NEXT: s_lshl_b32 s19, s35, 16 -; VI-NEXT: s_or_b32 s18, s18, s19 -; VI-NEXT: s_and_b32 s19, 0xffff, s21 -; VI-NEXT: s_lshl_b32 s20, s34, 16 -; VI-NEXT: s_or_b32 s19, s19, s20 -; VI-NEXT: s_and_b32 s20, 0xffff, s22 -; VI-NEXT: s_lshl_b32 s21, s31, 16 -; VI-NEXT: s_or_b32 s20, s20, s21 -; VI-NEXT: s_and_b32 s21, 0xffff, s23 -; VI-NEXT: s_lshl_b32 s22, s30, 16 -; VI-NEXT: s_or_b32 s21, s21, s22 -; VI-NEXT: s_and_b32 s22, 0xffff, s24 -; VI-NEXT: s_lshl_b32 s23, s91, 16 -; VI-NEXT: s_or_b32 s22, s22, s23 -; VI-NEXT: s_and_b32 s23, 0xffff, s25 -; VI-NEXT: s_lshl_b32 s24, s90, 16 -; VI-NEXT: s_or_b32 s23, s23, s24 -; VI-NEXT: s_and_b32 s24, 0xffff, s26 -; VI-NEXT: s_lshl_b32 s25, s89, 16 -; VI-NEXT: s_or_b32 s24, s24, s25 -; VI-NEXT: s_and_b32 s25, 0xffff, s27 -; VI-NEXT: s_lshl_b32 s26, s88, 16 -; VI-NEXT: s_or_b32 s25, s25, s26 -; VI-NEXT: s_and_b32 s26, 0xffff, s28 -; VI-NEXT: s_lshl_b32 s27, s79, 16 -; VI-NEXT: s_or_b32 s26, s26, s27 -; VI-NEXT: s_and_b32 s27, 0xffff, s29 -; VI-NEXT: s_lshl_b32 s28, s78, 16 -; VI-NEXT: s_or_b32 s27, s27, s28 -; VI-NEXT: s_and_b32 s28, 0xffff, s45 -; VI-NEXT: s_lshl_b32 s29, s77, 16 -; VI-NEXT: s_or_b32 s28, s28, s29 -; VI-NEXT: s_and_b32 s29, 0xffff, s44 -; VI-NEXT: s_lshl_b32 s44, s76, 16 -; VI-NEXT: s_or_b32 s29, s29, s44 +; VI-NEXT: s_and_b32 s5, 0xffff, s47 +; VI-NEXT: s_lshl_b32 s47, s38, 16 +; VI-NEXT: s_or_b32 s5, s5, s47 +; VI-NEXT: s_and_b32 s46, 0xffff, s46 +; VI-NEXT: s_lshl_b32 s47, s37, 16 +; VI-NEXT: s_or_b32 s46, s46, s47 +; VI-NEXT: s_and_b32 s45, 0xffff, s45 +; VI-NEXT: s_lshl_b32 s47, s36, 16 +; VI-NEXT: s_or_b32 s45, s45, s47 +; VI-NEXT: s_and_b32 s44, 0xffff, s44 +; VI-NEXT: s_lshl_b32 s47, s35, 16 +; VI-NEXT: s_or_b32 s44, s44, s47 ; VI-NEXT: s_and_b32 s43, 0xffff, s43 -; VI-NEXT: s_lshl_b32 s44, s75, 16 -; VI-NEXT: s_or_b32 s43, s43, s44 +; VI-NEXT: s_lshl_b32 s47, s34, 16 +; VI-NEXT: s_or_b32 s43, s43, s47 ; VI-NEXT: s_and_b32 s42, 0xffff, s42 -; VI-NEXT: s_lshl_b32 s44, s74, 16 -; VI-NEXT: s_or_b32 s42, s42, s44 +; VI-NEXT: s_lshl_b32 s47, s31, 16 +; VI-NEXT: s_or_b32 s42, s42, s47 ; VI-NEXT: s_and_b32 s41, 0xffff, s41 -; VI-NEXT: s_lshl_b32 s44, s73, 16 -; VI-NEXT: s_or_b32 s41, s41, s44 +; VI-NEXT: s_lshl_b32 s47, s30, 16 +; VI-NEXT: s_or_b32 s41, s41, s47 ; VI-NEXT: s_and_b32 s40, 0xffff, s40 -; VI-NEXT: s_lshl_b32 s44, s72, 16 -; VI-NEXT: s_or_b32 s40, s40, s44 +; VI-NEXT: s_lshl_b32 s47, s91, 16 +; VI-NEXT: s_or_b32 s40, s40, s47 +; VI-NEXT: s_and_b32 s26, 0xffff, s26 +; VI-NEXT: s_lshl_b32 s47, s90, 16 +; VI-NEXT: s_or_b32 s26, s26, s47 +; VI-NEXT: s_and_b32 s25, 0xffff, s25 +; VI-NEXT: s_lshl_b32 s47, s89, 16 +; VI-NEXT: s_or_b32 s25, s25, s47 +; VI-NEXT: s_and_b32 s24, 0xffff, s24 +; VI-NEXT: s_lshl_b32 s47, s88, 16 +; VI-NEXT: s_or_b32 s24, s24, s47 +; VI-NEXT: s_and_b32 s23, 0xffff, s23 +; VI-NEXT: s_lshl_b32 s47, s79, 16 +; VI-NEXT: s_or_b32 s23, s23, s47 +; VI-NEXT: s_and_b32 s22, 0xffff, s22 +; VI-NEXT: s_lshl_b32 s47, s78, 16 +; VI-NEXT: s_or_b32 s22, s22, s47 +; VI-NEXT: s_and_b32 s21, 0xffff, s21 +; VI-NEXT: s_lshl_b32 s47, s77, 16 +; VI-NEXT: s_or_b32 s21, s21, s47 +; VI-NEXT: s_and_b32 s20, 0xffff, s20 +; VI-NEXT: s_lshl_b32 s47, s76, 16 +; VI-NEXT: s_or_b32 s20, s20, s47 +; VI-NEXT: s_and_b32 s19, 0xffff, s19 +; VI-NEXT: s_lshl_b32 s47, s75, 16 +; VI-NEXT: s_or_b32 s19, s19, s47 +; VI-NEXT: s_and_b32 s18, 0xffff, s18 +; VI-NEXT: s_lshl_b32 s47, s74, 16 +; VI-NEXT: s_or_b32 s18, s18, s47 +; VI-NEXT: s_and_b32 s17, 0xffff, s17 +; VI-NEXT: s_lshl_b32 s47, s73, 16 +; VI-NEXT: s_or_b32 s17, s17, s47 +; VI-NEXT: s_and_b32 s16, 0xffff, s16 +; VI-NEXT: s_lshl_b32 s47, s72, 16 +; VI-NEXT: s_or_b32 s16, s16, s47 ; VI-NEXT: s_and_b32 s15, 0xffff, s15 -; VI-NEXT: s_lshl_b32 s44, s63, 16 -; VI-NEXT: s_or_b32 s15, s15, s44 +; VI-NEXT: s_lshl_b32 s47, s63, 16 +; VI-NEXT: s_or_b32 s15, s15, s47 ; VI-NEXT: s_and_b32 s14, 0xffff, s14 -; VI-NEXT: s_lshl_b32 s44, s62, 16 -; VI-NEXT: s_or_b32 s14, s14, s44 +; VI-NEXT: s_lshl_b32 s47, s62, 16 +; VI-NEXT: s_or_b32 s14, s14, s47 ; VI-NEXT: s_and_b32 s13, 0xffff, s13 -; VI-NEXT: s_lshl_b32 s44, s61, 16 -; VI-NEXT: s_or_b32 s13, s13, s44 +; VI-NEXT: s_lshl_b32 s47, s61, 16 +; VI-NEXT: s_or_b32 s13, s13, s47 ; VI-NEXT: s_and_b32 s12, 0xffff, s12 -; VI-NEXT: s_lshl_b32 s44, s60, 16 -; VI-NEXT: s_or_b32 s12, s12, s44 +; VI-NEXT: s_lshl_b32 s47, s60, 16 +; VI-NEXT: s_or_b32 s12, s12, s47 ; VI-NEXT: s_and_b32 s11, 0xffff, s11 -; VI-NEXT: s_lshl_b32 s44, s59, 16 -; VI-NEXT: s_or_b32 s11, s11, s44 +; VI-NEXT: s_lshl_b32 s47, s59, 16 +; VI-NEXT: s_or_b32 s11, s11, s47 ; VI-NEXT: s_and_b32 s10, 0xffff, s10 -; VI-NEXT: s_lshl_b32 s44, s58, 16 -; VI-NEXT: s_or_b32 s10, s10, s44 +; VI-NEXT: s_lshl_b32 s47, s58, 16 +; VI-NEXT: s_or_b32 s10, s10, s47 ; VI-NEXT: s_and_b32 s9, 0xffff, s9 -; VI-NEXT: s_lshl_b32 s44, s57, 16 -; VI-NEXT: s_or_b32 s9, s9, s44 +; VI-NEXT: s_lshl_b32 s47, s57, 16 ; VI-NEXT: s_and_b32 s8, 0xffff, s8 -; VI-NEXT: s_lshl_b32 s44, s56, 16 -; VI-NEXT: s_or_b32 s8, s8, s44 +; VI-NEXT: s_lshl_b32 s29, s29, 16 ; VI-NEXT: s_and_b32 s6, 0xffff, s6 -; VI-NEXT: s_lshl_b32 s44, s47, 16 -; VI-NEXT: s_or_b32 s6, s6, s44 +; VI-NEXT: s_lshl_b32 s28, s28, 16 ; VI-NEXT: s_and_b32 s7, 0xffff, s7 -; VI-NEXT: s_lshl_b32 s44, s46, 16 -; VI-NEXT: s_or_b32 s7, s7, s44 +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s9, s9, s47 +; VI-NEXT: s_or_b32 s8, s8, s29 +; VI-NEXT: s_or_b32 s6, s6, s28 +; VI-NEXT: s_or_b32 s7, s7, s27 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s5 -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: v_mov_b32_e32 v3, s17 -; VI-NEXT: v_mov_b32_e32 v4, s18 -; VI-NEXT: v_mov_b32_e32 v5, s19 -; VI-NEXT: v_mov_b32_e32 v6, s20 -; VI-NEXT: v_mov_b32_e32 v7, s21 -; VI-NEXT: v_mov_b32_e32 v8, s22 -; VI-NEXT: v_mov_b32_e32 v9, s23 -; VI-NEXT: v_mov_b32_e32 v10, s24 -; VI-NEXT: v_mov_b32_e32 v11, s25 -; VI-NEXT: v_mov_b32_e32 v12, s26 -; VI-NEXT: v_mov_b32_e32 v13, s27 -; VI-NEXT: v_mov_b32_e32 v14, s28 -; VI-NEXT: v_mov_b32_e32 v15, s29 -; VI-NEXT: v_mov_b32_e32 v16, s43 -; VI-NEXT: v_mov_b32_e32 v17, s42 -; VI-NEXT: v_mov_b32_e32 v18, s41 -; VI-NEXT: v_mov_b32_e32 v19, s40 +; VI-NEXT: v_mov_b32_e32 v2, s46 +; VI-NEXT: v_mov_b32_e32 v3, s45 +; VI-NEXT: v_mov_b32_e32 v4, s44 +; VI-NEXT: v_mov_b32_e32 v5, s43 +; VI-NEXT: v_mov_b32_e32 v6, s42 +; VI-NEXT: v_mov_b32_e32 v7, s41 +; VI-NEXT: v_mov_b32_e32 v8, s40 +; VI-NEXT: v_mov_b32_e32 v9, s26 +; VI-NEXT: v_mov_b32_e32 v10, s25 +; VI-NEXT: v_mov_b32_e32 v11, s24 +; VI-NEXT: v_mov_b32_e32 v12, s23 +; VI-NEXT: v_mov_b32_e32 v13, s22 +; VI-NEXT: v_mov_b32_e32 v14, s21 +; VI-NEXT: v_mov_b32_e32 v15, s20 +; VI-NEXT: v_mov_b32_e32 v16, s19 +; VI-NEXT: v_mov_b32_e32 v17, s18 +; VI-NEXT: v_mov_b32_e32 v18, s17 +; VI-NEXT: v_mov_b32_e32 v19, s16 ; VI-NEXT: v_mov_b32_e32 v20, s15 ; VI-NEXT: v_mov_b32_e32 v21, s14 ; VI-NEXT: v_mov_b32_e32 v22, s13 @@ -28735,9 +28384,9 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; VI-NEXT: ; implicit-def: $sgpr59 ; VI-NEXT: ; implicit-def: $sgpr58 ; VI-NEXT: ; implicit-def: $sgpr57 -; VI-NEXT: ; implicit-def: $sgpr56 -; VI-NEXT: ; implicit-def: $sgpr47 -; VI-NEXT: ; implicit-def: $sgpr46 +; VI-NEXT: ; implicit-def: $sgpr29 +; VI-NEXT: ; implicit-def: $sgpr28 +; VI-NEXT: ; implicit-def: $sgpr27 ; VI-NEXT: s_branch .LBB41_2 ; ; GFX9-LABEL: bitcast_v15i64_to_v60i16_scalar: @@ -28746,20 +28395,48 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] +; GFX9-NEXT: v_mov_b32_e32 v17, s16 +; GFX9-NEXT: v_mov_b32_e32 v18, s17 +; GFX9-NEXT: v_mov_b32_e32 v19, s18 +; GFX9-NEXT: v_readfirstlane_b32 s6, v17 +; GFX9-NEXT: v_mov_b32_e32 v17, s19 +; GFX9-NEXT: v_readfirstlane_b32 s7, v18 +; GFX9-NEXT: v_mov_b32_e32 v18, s20 +; GFX9-NEXT: v_readfirstlane_b32 s8, v19 +; GFX9-NEXT: v_mov_b32_e32 v19, s21 +; GFX9-NEXT: v_readfirstlane_b32 s9, v17 +; GFX9-NEXT: v_mov_b32_e32 v17, s22 +; GFX9-NEXT: v_readfirstlane_b32 s10, v18 +; GFX9-NEXT: v_mov_b32_e32 v18, s23 ; GFX9-NEXT: v_writelane_b32 v30, s30, 0 +; GFX9-NEXT: v_readfirstlane_b32 s11, v19 +; GFX9-NEXT: v_mov_b32_e32 v19, s24 +; GFX9-NEXT: v_readfirstlane_b32 s12, v17 +; GFX9-NEXT: v_mov_b32_e32 v17, s25 +; GFX9-NEXT: v_readfirstlane_b32 s13, v18 +; GFX9-NEXT: v_mov_b32_e32 v18, s26 ; GFX9-NEXT: v_writelane_b32 v30, s31, 1 +; GFX9-NEXT: v_readfirstlane_b32 s14, v19 +; GFX9-NEXT: v_mov_b32_e32 v19, s27 +; GFX9-NEXT: v_readfirstlane_b32 s15, v17 +; GFX9-NEXT: v_mov_b32_e32 v17, s28 +; GFX9-NEXT: v_readfirstlane_b32 s16, v18 +; GFX9-NEXT: v_mov_b32_e32 v18, s29 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 ; GFX9-NEXT: v_writelane_b32 v30, s34, 2 -; GFX9-NEXT: v_readfirstlane_b32 s6, v0 -; GFX9-NEXT: v_readfirstlane_b32 s7, v1 -; GFX9-NEXT: v_readfirstlane_b32 s8, v2 -; GFX9-NEXT: v_readfirstlane_b32 s9, v3 -; GFX9-NEXT: v_readfirstlane_b32 s10, v4 -; GFX9-NEXT: v_readfirstlane_b32 s11, v5 -; GFX9-NEXT: v_readfirstlane_b32 s12, v6 -; GFX9-NEXT: v_readfirstlane_b32 s13, v7 -; GFX9-NEXT: v_readfirstlane_b32 s14, v8 -; GFX9-NEXT: v_readfirstlane_b32 s15, v9 +; GFX9-NEXT: v_readfirstlane_b32 s17, v19 +; GFX9-NEXT: v_readfirstlane_b32 s18, v17 +; GFX9-NEXT: v_readfirstlane_b32 s19, v18 +; GFX9-NEXT: v_readfirstlane_b32 s20, v0 +; GFX9-NEXT: v_readfirstlane_b32 s21, v1 +; GFX9-NEXT: v_readfirstlane_b32 s22, v2 +; GFX9-NEXT: v_readfirstlane_b32 s23, v3 +; GFX9-NEXT: v_readfirstlane_b32 s24, v4 +; GFX9-NEXT: v_readfirstlane_b32 s25, v5 +; GFX9-NEXT: v_readfirstlane_b32 s26, v6 +; GFX9-NEXT: v_readfirstlane_b32 s27, v7 +; GFX9-NEXT: v_readfirstlane_b32 s28, v8 +; GFX9-NEXT: v_readfirstlane_b32 s29, v9 ; GFX9-NEXT: v_readfirstlane_b32 s40, v10 ; GFX9-NEXT: v_readfirstlane_b32 s41, v11 ; GFX9-NEXT: v_readfirstlane_b32 s42, v12 @@ -28776,30 +28453,30 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; GFX9-NEXT: s_lshr_b32 s57, s42, 16 ; GFX9-NEXT: s_lshr_b32 s58, s41, 16 ; GFX9-NEXT: s_lshr_b32 s59, s40, 16 -; GFX9-NEXT: s_lshr_b32 s60, s15, 16 -; GFX9-NEXT: s_lshr_b32 s61, s14, 16 -; GFX9-NEXT: s_lshr_b32 s62, s13, 16 -; GFX9-NEXT: s_lshr_b32 s63, s12, 16 -; GFX9-NEXT: s_lshr_b32 s72, s11, 16 -; GFX9-NEXT: s_lshr_b32 s73, s10, 16 -; GFX9-NEXT: s_lshr_b32 s74, s9, 16 -; GFX9-NEXT: s_lshr_b32 s75, s8, 16 -; GFX9-NEXT: s_lshr_b32 s76, s7, 16 -; GFX9-NEXT: s_lshr_b32 s77, s6, 16 -; GFX9-NEXT: s_lshr_b32 s78, s29, 16 -; GFX9-NEXT: s_lshr_b32 s79, s28, 16 -; GFX9-NEXT: s_lshr_b32 s88, s27, 16 -; GFX9-NEXT: s_lshr_b32 s89, s26, 16 -; GFX9-NEXT: s_lshr_b32 s90, s25, 16 -; GFX9-NEXT: s_lshr_b32 s91, s24, 16 -; GFX9-NEXT: s_lshr_b32 s92, s23, 16 -; GFX9-NEXT: s_lshr_b32 s93, s22, 16 -; GFX9-NEXT: s_lshr_b32 s94, s21, 16 -; GFX9-NEXT: s_lshr_b32 s95, s20, 16 -; GFX9-NEXT: s_lshr_b32 s30, s19, 16 -; GFX9-NEXT: s_lshr_b32 s31, s18, 16 -; GFX9-NEXT: s_lshr_b32 s34, s17, 16 -; GFX9-NEXT: s_lshr_b32 s35, s16, 16 +; GFX9-NEXT: s_lshr_b32 s60, s29, 16 +; GFX9-NEXT: s_lshr_b32 s61, s28, 16 +; GFX9-NEXT: s_lshr_b32 s62, s27, 16 +; GFX9-NEXT: s_lshr_b32 s63, s26, 16 +; GFX9-NEXT: s_lshr_b32 s72, s25, 16 +; GFX9-NEXT: s_lshr_b32 s73, s24, 16 +; GFX9-NEXT: s_lshr_b32 s74, s23, 16 +; GFX9-NEXT: s_lshr_b32 s75, s22, 16 +; GFX9-NEXT: s_lshr_b32 s76, s21, 16 +; GFX9-NEXT: s_lshr_b32 s77, s20, 16 +; GFX9-NEXT: s_lshr_b32 s78, s19, 16 +; GFX9-NEXT: s_lshr_b32 s79, s18, 16 +; GFX9-NEXT: s_lshr_b32 s88, s17, 16 +; GFX9-NEXT: s_lshr_b32 s89, s16, 16 +; GFX9-NEXT: s_lshr_b32 s90, s15, 16 +; GFX9-NEXT: s_lshr_b32 s91, s14, 16 +; GFX9-NEXT: s_lshr_b32 s92, s13, 16 +; GFX9-NEXT: s_lshr_b32 s93, s12, 16 +; GFX9-NEXT: s_lshr_b32 s94, s11, 16 +; GFX9-NEXT: s_lshr_b32 s95, s10, 16 +; GFX9-NEXT: s_lshr_b32 s30, s9, 16 +; GFX9-NEXT: s_lshr_b32 s31, s8, 16 +; GFX9-NEXT: s_lshr_b32 s34, s7, 16 +; GFX9-NEXT: s_lshr_b32 s35, s6, 16 ; GFX9-NEXT: s_cbranch_execnz .LBB41_3 ; GFX9-NEXT: .LBB41_2: ; %cmp.true ; GFX9-NEXT: s_add_u32 s44, s44, 3 @@ -28808,16 +28485,6 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; GFX9-NEXT: s_addc_u32 s43, s43, 0 ; GFX9-NEXT: s_add_u32 s40, s40, 3 ; GFX9-NEXT: s_addc_u32 s41, s41, 0 -; GFX9-NEXT: s_add_u32 s14, s14, 3 -; GFX9-NEXT: s_addc_u32 s15, s15, 0 -; GFX9-NEXT: s_add_u32 s12, s12, 3 -; GFX9-NEXT: s_addc_u32 s13, s13, 0 -; GFX9-NEXT: s_add_u32 s10, s10, 3 -; GFX9-NEXT: s_addc_u32 s11, s11, 0 -; GFX9-NEXT: s_add_u32 s8, s8, 3 -; GFX9-NEXT: s_addc_u32 s9, s9, 0 -; GFX9-NEXT: s_add_u32 s6, s6, 3 -; GFX9-NEXT: s_addc_u32 s7, s7, 0 ; GFX9-NEXT: s_add_u32 s28, s28, 3 ; GFX9-NEXT: s_addc_u32 s29, s29, 0 ; GFX9-NEXT: s_add_u32 s26, s26, 3 @@ -28832,61 +28499,71 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; GFX9-NEXT: s_addc_u32 s19, s19, 0 ; GFX9-NEXT: s_add_u32 s16, s16, 3 ; GFX9-NEXT: s_addc_u32 s17, s17, 0 +; GFX9-NEXT: s_add_u32 s14, s14, 3 +; GFX9-NEXT: s_addc_u32 s15, s15, 0 +; GFX9-NEXT: s_add_u32 s12, s12, 3 +; GFX9-NEXT: s_addc_u32 s13, s13, 0 +; GFX9-NEXT: s_add_u32 s10, s10, 3 +; GFX9-NEXT: s_addc_u32 s11, s11, 0 +; GFX9-NEXT: s_add_u32 s8, s8, 3 +; GFX9-NEXT: s_addc_u32 s9, s9, 0 +; GFX9-NEXT: s_add_u32 s6, s6, 3 +; GFX9-NEXT: s_addc_u32 s7, s7, 0 ; GFX9-NEXT: s_lshr_b32 s46, s45, 16 ; GFX9-NEXT: s_lshr_b32 s47, s44, 16 ; GFX9-NEXT: s_lshr_b32 s56, s43, 16 ; GFX9-NEXT: s_lshr_b32 s57, s42, 16 ; GFX9-NEXT: s_lshr_b32 s58, s41, 16 ; GFX9-NEXT: s_lshr_b32 s59, s40, 16 -; GFX9-NEXT: s_lshr_b32 s60, s15, 16 -; GFX9-NEXT: s_lshr_b32 s61, s14, 16 -; GFX9-NEXT: s_lshr_b32 s62, s13, 16 -; GFX9-NEXT: s_lshr_b32 s63, s12, 16 -; GFX9-NEXT: s_lshr_b32 s72, s11, 16 -; GFX9-NEXT: s_lshr_b32 s73, s10, 16 -; GFX9-NEXT: s_lshr_b32 s74, s9, 16 -; GFX9-NEXT: s_lshr_b32 s75, s8, 16 -; GFX9-NEXT: s_lshr_b32 s76, s7, 16 -; GFX9-NEXT: s_lshr_b32 s77, s6, 16 -; GFX9-NEXT: s_lshr_b32 s78, s29, 16 -; GFX9-NEXT: s_lshr_b32 s79, s28, 16 -; GFX9-NEXT: s_lshr_b32 s88, s27, 16 -; GFX9-NEXT: s_lshr_b32 s89, s26, 16 -; GFX9-NEXT: s_lshr_b32 s90, s25, 16 -; GFX9-NEXT: s_lshr_b32 s91, s24, 16 -; GFX9-NEXT: s_lshr_b32 s92, s23, 16 -; GFX9-NEXT: s_lshr_b32 s93, s22, 16 -; GFX9-NEXT: s_lshr_b32 s94, s21, 16 -; GFX9-NEXT: s_lshr_b32 s95, s20, 16 -; GFX9-NEXT: s_lshr_b32 s30, s19, 16 -; GFX9-NEXT: s_lshr_b32 s31, s18, 16 -; GFX9-NEXT: s_lshr_b32 s34, s17, 16 -; GFX9-NEXT: s_lshr_b32 s35, s16, 16 +; GFX9-NEXT: s_lshr_b32 s60, s29, 16 +; GFX9-NEXT: s_lshr_b32 s61, s28, 16 +; GFX9-NEXT: s_lshr_b32 s62, s27, 16 +; GFX9-NEXT: s_lshr_b32 s63, s26, 16 +; GFX9-NEXT: s_lshr_b32 s72, s25, 16 +; GFX9-NEXT: s_lshr_b32 s73, s24, 16 +; GFX9-NEXT: s_lshr_b32 s74, s23, 16 +; GFX9-NEXT: s_lshr_b32 s75, s22, 16 +; GFX9-NEXT: s_lshr_b32 s76, s21, 16 +; GFX9-NEXT: s_lshr_b32 s77, s20, 16 +; GFX9-NEXT: s_lshr_b32 s78, s19, 16 +; GFX9-NEXT: s_lshr_b32 s79, s18, 16 +; GFX9-NEXT: s_lshr_b32 s88, s17, 16 +; GFX9-NEXT: s_lshr_b32 s89, s16, 16 +; GFX9-NEXT: s_lshr_b32 s90, s15, 16 +; GFX9-NEXT: s_lshr_b32 s91, s14, 16 +; GFX9-NEXT: s_lshr_b32 s92, s13, 16 +; GFX9-NEXT: s_lshr_b32 s93, s12, 16 +; GFX9-NEXT: s_lshr_b32 s94, s11, 16 +; GFX9-NEXT: s_lshr_b32 s95, s10, 16 +; GFX9-NEXT: s_lshr_b32 s30, s9, 16 +; GFX9-NEXT: s_lshr_b32 s31, s8, 16 +; GFX9-NEXT: s_lshr_b32 s34, s7, 16 +; GFX9-NEXT: s_lshr_b32 s35, s6, 16 ; GFX9-NEXT: .LBB41_3: ; %end -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s16, s35 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s17, s34 -; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s31 -; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s30 -; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s95 -; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s94 -; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s93 -; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s92 -; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s91 -; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s90 -; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s89 -; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s88 -; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s79 -; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s78 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s77 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s76 -; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s75 -; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s74 -; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s73 -; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s72 -; GFX9-NEXT: s_pack_ll_b32_b16 s12, s12, s63 -; GFX9-NEXT: s_pack_ll_b32_b16 s13, s13, s62 -; GFX9-NEXT: s_pack_ll_b32_b16 s14, s14, s61 -; GFX9-NEXT: s_pack_ll_b32_b16 s15, s15, s60 +; GFX9-NEXT: s_pack_ll_b32_b16 s4, s6, s35 +; GFX9-NEXT: s_pack_ll_b32_b16 s5, s7, s34 +; GFX9-NEXT: s_pack_ll_b32_b16 s6, s8, s31 +; GFX9-NEXT: s_pack_ll_b32_b16 s7, s9, s30 +; GFX9-NEXT: s_pack_ll_b32_b16 s8, s10, s95 +; GFX9-NEXT: s_pack_ll_b32_b16 s9, s11, s94 +; GFX9-NEXT: s_pack_ll_b32_b16 s10, s12, s93 +; GFX9-NEXT: s_pack_ll_b32_b16 s11, s13, s92 +; GFX9-NEXT: s_pack_ll_b32_b16 s12, s14, s91 +; GFX9-NEXT: s_pack_ll_b32_b16 s13, s15, s90 +; GFX9-NEXT: s_pack_ll_b32_b16 s14, s16, s89 +; GFX9-NEXT: s_pack_ll_b32_b16 s15, s17, s88 +; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s79 +; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s78 +; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s77 +; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s76 +; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s75 +; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s74 +; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s73 +; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s72 +; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s63 +; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s62 +; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s61 +; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s60 ; GFX9-NEXT: s_pack_ll_b32_b16 s28, s40, s59 ; GFX9-NEXT: s_pack_ll_b32_b16 s29, s41, s58 ; GFX9-NEXT: s_pack_ll_b32_b16 s40, s42, s57 @@ -28895,28 +28572,28 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; GFX9-NEXT: s_pack_ll_b32_b16 s43, s45, s46 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 -; GFX9-NEXT: v_mov_b32_e32 v2, s16 -; GFX9-NEXT: v_mov_b32_e32 v3, s17 -; GFX9-NEXT: v_mov_b32_e32 v4, s18 -; GFX9-NEXT: v_mov_b32_e32 v5, s19 -; GFX9-NEXT: v_mov_b32_e32 v6, s20 -; GFX9-NEXT: v_mov_b32_e32 v7, s21 -; GFX9-NEXT: v_mov_b32_e32 v8, s22 -; GFX9-NEXT: v_mov_b32_e32 v9, s23 -; GFX9-NEXT: v_mov_b32_e32 v10, s24 -; GFX9-NEXT: v_mov_b32_e32 v11, s25 -; GFX9-NEXT: v_mov_b32_e32 v12, s26 -; GFX9-NEXT: v_mov_b32_e32 v13, s27 -; GFX9-NEXT: v_mov_b32_e32 v14, s6 -; GFX9-NEXT: v_mov_b32_e32 v15, s7 -; GFX9-NEXT: v_mov_b32_e32 v16, s8 -; GFX9-NEXT: v_mov_b32_e32 v17, s9 -; GFX9-NEXT: v_mov_b32_e32 v18, s10 -; GFX9-NEXT: v_mov_b32_e32 v19, s11 -; GFX9-NEXT: v_mov_b32_e32 v20, s12 -; GFX9-NEXT: v_mov_b32_e32 v21, s13 -; GFX9-NEXT: v_mov_b32_e32 v22, s14 -; GFX9-NEXT: v_mov_b32_e32 v23, s15 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: v_mov_b32_e32 v4, s8 +; GFX9-NEXT: v_mov_b32_e32 v5, s9 +; GFX9-NEXT: v_mov_b32_e32 v6, s10 +; GFX9-NEXT: v_mov_b32_e32 v7, s11 +; GFX9-NEXT: v_mov_b32_e32 v8, s12 +; GFX9-NEXT: v_mov_b32_e32 v9, s13 +; GFX9-NEXT: v_mov_b32_e32 v10, s14 +; GFX9-NEXT: v_mov_b32_e32 v11, s15 +; GFX9-NEXT: v_mov_b32_e32 v12, s16 +; GFX9-NEXT: v_mov_b32_e32 v13, s17 +; GFX9-NEXT: v_mov_b32_e32 v14, s18 +; GFX9-NEXT: v_mov_b32_e32 v15, s19 +; GFX9-NEXT: v_mov_b32_e32 v16, s20 +; GFX9-NEXT: v_mov_b32_e32 v17, s21 +; GFX9-NEXT: v_mov_b32_e32 v18, s22 +; GFX9-NEXT: v_mov_b32_e32 v19, s23 +; GFX9-NEXT: v_mov_b32_e32 v20, s24 +; GFX9-NEXT: v_mov_b32_e32 v21, s25 +; GFX9-NEXT: v_mov_b32_e32 v22, s26 +; GFX9-NEXT: v_mov_b32_e32 v23, s27 ; GFX9-NEXT: v_mov_b32_e32 v24, s28 ; GFX9-NEXT: v_mov_b32_e32 v25, s29 ; GFX9-NEXT: v_mov_b32_e32 v26, s40 @@ -28968,49 +28645,76 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; GFX11-LABEL: bitcast_v15i64_to_v60i16_scalar: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v13, s0 :: v_dual_mov_b32 v14, s1 +; GFX11-NEXT: v_dual_mov_b32 v15, s2 :: v_dual_mov_b32 v16, s3 +; GFX11-NEXT: v_dual_mov_b32 v17, s16 :: v_dual_mov_b32 v18, s17 +; GFX11-NEXT: v_dual_mov_b32 v19, s18 :: v_dual_mov_b32 v20, s19 +; GFX11-NEXT: v_dual_mov_b32 v21, s20 :: v_dual_mov_b32 v22, s21 +; GFX11-NEXT: v_dual_mov_b32 v23, s22 :: v_dual_mov_b32 v24, s23 +; GFX11-NEXT: v_dual_mov_b32 v25, s24 :: v_dual_mov_b32 v26, s25 +; GFX11-NEXT: v_dual_mov_b32 v27, s26 :: v_dual_mov_b32 v28, s27 +; GFX11-NEXT: v_dual_mov_b32 v29, s28 :: v_dual_mov_b32 v30, s29 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 -; GFX11-NEXT: v_readfirstlane_b32 s4, v0 -; GFX11-NEXT: v_readfirstlane_b32 s5, v1 -; GFX11-NEXT: v_readfirstlane_b32 s6, v2 -; GFX11-NEXT: v_readfirstlane_b32 s7, v3 -; GFX11-NEXT: v_readfirstlane_b32 s8, v4 -; GFX11-NEXT: v_readfirstlane_b32 s9, v5 -; GFX11-NEXT: v_readfirstlane_b32 s10, v6 -; GFX11-NEXT: v_readfirstlane_b32 s11, v7 -; GFX11-NEXT: v_readfirstlane_b32 s12, v8 -; GFX11-NEXT: v_readfirstlane_b32 s13, v9 -; GFX11-NEXT: v_readfirstlane_b32 s15, v10 -; GFX11-NEXT: v_readfirstlane_b32 s14, v11 +; GFX11-NEXT: v_readfirstlane_b32 s0, v13 +; GFX11-NEXT: v_readfirstlane_b32 s1, v14 +; GFX11-NEXT: v_readfirstlane_b32 s2, v15 +; GFX11-NEXT: v_readfirstlane_b32 s3, v16 +; GFX11-NEXT: v_readfirstlane_b32 s4, v17 +; GFX11-NEXT: v_readfirstlane_b32 s5, v18 +; GFX11-NEXT: v_readfirstlane_b32 s6, v19 +; GFX11-NEXT: v_readfirstlane_b32 s7, v20 +; GFX11-NEXT: v_readfirstlane_b32 s8, v21 +; GFX11-NEXT: v_readfirstlane_b32 s9, v22 +; GFX11-NEXT: v_readfirstlane_b32 s10, v23 +; GFX11-NEXT: v_readfirstlane_b32 s11, v24 +; GFX11-NEXT: v_readfirstlane_b32 s12, v25 +; GFX11-NEXT: v_readfirstlane_b32 s13, v26 +; GFX11-NEXT: v_readfirstlane_b32 s14, v27 +; GFX11-NEXT: v_readfirstlane_b32 s15, v28 +; GFX11-NEXT: v_readfirstlane_b32 s16, v29 +; GFX11-NEXT: v_readfirstlane_b32 s17, v30 +; GFX11-NEXT: v_readfirstlane_b32 s18, v0 +; GFX11-NEXT: v_readfirstlane_b32 s19, v1 +; GFX11-NEXT: v_readfirstlane_b32 s20, v2 +; GFX11-NEXT: v_readfirstlane_b32 s21, v3 +; GFX11-NEXT: v_readfirstlane_b32 s22, v4 +; GFX11-NEXT: v_readfirstlane_b32 s23, v5 +; GFX11-NEXT: v_readfirstlane_b32 s24, v6 +; GFX11-NEXT: v_readfirstlane_b32 s25, v7 +; GFX11-NEXT: v_readfirstlane_b32 s26, v8 +; GFX11-NEXT: v_readfirstlane_b32 s27, v9 +; GFX11-NEXT: v_readfirstlane_b32 s29, v10 +; GFX11-NEXT: v_readfirstlane_b32 s28, v11 ; GFX11-NEXT: s_mov_b32 s94, 0 ; GFX11-NEXT: s_and_b32 s40, vcc_lo, exec_lo ; GFX11-NEXT: s_cbranch_scc0 .LBB41_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: s_lshr_b32 s40, s14, 16 -; GFX11-NEXT: s_lshr_b32 s41, s15, 16 -; GFX11-NEXT: s_lshr_b32 s42, s13, 16 -; GFX11-NEXT: s_lshr_b32 s43, s12, 16 -; GFX11-NEXT: s_lshr_b32 s44, s11, 16 -; GFX11-NEXT: s_lshr_b32 s45, s10, 16 -; GFX11-NEXT: s_lshr_b32 s46, s9, 16 -; GFX11-NEXT: s_lshr_b32 s47, s8, 16 -; GFX11-NEXT: s_lshr_b32 s56, s7, 16 -; GFX11-NEXT: s_lshr_b32 s57, s6, 16 -; GFX11-NEXT: s_lshr_b32 s58, s5, 16 -; GFX11-NEXT: s_lshr_b32 s59, s4, 16 -; GFX11-NEXT: s_lshr_b32 s60, s29, 16 -; GFX11-NEXT: s_lshr_b32 s61, s28, 16 -; GFX11-NEXT: s_lshr_b32 s62, s27, 16 -; GFX11-NEXT: s_lshr_b32 s63, s26, 16 -; GFX11-NEXT: s_lshr_b32 s72, s25, 16 -; GFX11-NEXT: s_lshr_b32 s73, s24, 16 -; GFX11-NEXT: s_lshr_b32 s74, s23, 16 -; GFX11-NEXT: s_lshr_b32 s75, s22, 16 -; GFX11-NEXT: s_lshr_b32 s76, s21, 16 -; GFX11-NEXT: s_lshr_b32 s77, s20, 16 -; GFX11-NEXT: s_lshr_b32 s78, s19, 16 -; GFX11-NEXT: s_lshr_b32 s79, s18, 16 -; GFX11-NEXT: s_lshr_b32 s88, s17, 16 -; GFX11-NEXT: s_lshr_b32 s89, s16, 16 +; GFX11-NEXT: s_lshr_b32 s40, s28, 16 +; GFX11-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-NEXT: s_lshr_b32 s42, s27, 16 +; GFX11-NEXT: s_lshr_b32 s43, s26, 16 +; GFX11-NEXT: s_lshr_b32 s44, s25, 16 +; GFX11-NEXT: s_lshr_b32 s45, s24, 16 +; GFX11-NEXT: s_lshr_b32 s46, s23, 16 +; GFX11-NEXT: s_lshr_b32 s47, s22, 16 +; GFX11-NEXT: s_lshr_b32 s56, s21, 16 +; GFX11-NEXT: s_lshr_b32 s57, s20, 16 +; GFX11-NEXT: s_lshr_b32 s58, s19, 16 +; GFX11-NEXT: s_lshr_b32 s59, s18, 16 +; GFX11-NEXT: s_lshr_b32 s60, s17, 16 +; GFX11-NEXT: s_lshr_b32 s61, s16, 16 +; GFX11-NEXT: s_lshr_b32 s62, s15, 16 +; GFX11-NEXT: s_lshr_b32 s63, s14, 16 +; GFX11-NEXT: s_lshr_b32 s72, s13, 16 +; GFX11-NEXT: s_lshr_b32 s73, s12, 16 +; GFX11-NEXT: s_lshr_b32 s74, s11, 16 +; GFX11-NEXT: s_lshr_b32 s75, s10, 16 +; GFX11-NEXT: s_lshr_b32 s76, s9, 16 +; GFX11-NEXT: s_lshr_b32 s77, s8, 16 +; GFX11-NEXT: s_lshr_b32 s78, s7, 16 +; GFX11-NEXT: s_lshr_b32 s79, s6, 16 +; GFX11-NEXT: s_lshr_b32 s88, s5, 16 +; GFX11-NEXT: s_lshr_b32 s89, s4, 16 ; GFX11-NEXT: s_lshr_b32 s90, s3, 16 ; GFX11-NEXT: s_lshr_b32 s91, s2, 16 ; GFX11-NEXT: s_lshr_b32 s92, s1, 16 @@ -29018,20 +28722,8 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s94 ; GFX11-NEXT: s_cbranch_vccnz .LBB41_3 ; GFX11-NEXT: .LBB41_2: ; %cmp.true -; GFX11-NEXT: s_add_u32 s15, s15, 3 -; GFX11-NEXT: s_addc_u32 s14, s14, 0 -; GFX11-NEXT: s_add_u32 s12, s12, 3 -; GFX11-NEXT: s_addc_u32 s13, s13, 0 -; GFX11-NEXT: s_add_u32 s10, s10, 3 -; GFX11-NEXT: s_addc_u32 s11, s11, 0 -; GFX11-NEXT: s_add_u32 s8, s8, 3 -; GFX11-NEXT: s_addc_u32 s9, s9, 0 -; GFX11-NEXT: s_add_u32 s6, s6, 3 -; GFX11-NEXT: s_addc_u32 s7, s7, 0 -; GFX11-NEXT: s_add_u32 s4, s4, 3 -; GFX11-NEXT: s_addc_u32 s5, s5, 0 -; GFX11-NEXT: s_add_u32 s28, s28, 3 -; GFX11-NEXT: s_addc_u32 s29, s29, 0 +; GFX11-NEXT: s_add_u32 s29, s29, 3 +; GFX11-NEXT: s_addc_u32 s28, s28, 0 ; GFX11-NEXT: s_add_u32 s26, s26, 3 ; GFX11-NEXT: s_addc_u32 s27, s27, 0 ; GFX11-NEXT: s_add_u32 s24, s24, 3 @@ -29044,36 +28736,48 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; GFX11-NEXT: s_addc_u32 s19, s19, 0 ; GFX11-NEXT: s_add_u32 s16, s16, 3 ; GFX11-NEXT: s_addc_u32 s17, s17, 0 +; GFX11-NEXT: s_add_u32 s14, s14, 3 +; GFX11-NEXT: s_addc_u32 s15, s15, 0 +; GFX11-NEXT: s_add_u32 s12, s12, 3 +; GFX11-NEXT: s_addc_u32 s13, s13, 0 +; GFX11-NEXT: s_add_u32 s10, s10, 3 +; GFX11-NEXT: s_addc_u32 s11, s11, 0 +; GFX11-NEXT: s_add_u32 s8, s8, 3 +; GFX11-NEXT: s_addc_u32 s9, s9, 0 +; GFX11-NEXT: s_add_u32 s6, s6, 3 +; GFX11-NEXT: s_addc_u32 s7, s7, 0 +; GFX11-NEXT: s_add_u32 s4, s4, 3 +; GFX11-NEXT: s_addc_u32 s5, s5, 0 ; GFX11-NEXT: s_add_u32 s2, s2, 3 ; GFX11-NEXT: s_addc_u32 s3, s3, 0 ; GFX11-NEXT: s_add_u32 s0, s0, 3 ; GFX11-NEXT: s_addc_u32 s1, s1, 0 -; GFX11-NEXT: s_lshr_b32 s40, s14, 16 -; GFX11-NEXT: s_lshr_b32 s41, s15, 16 -; GFX11-NEXT: s_lshr_b32 s42, s13, 16 -; GFX11-NEXT: s_lshr_b32 s43, s12, 16 -; GFX11-NEXT: s_lshr_b32 s44, s11, 16 -; GFX11-NEXT: s_lshr_b32 s45, s10, 16 -; GFX11-NEXT: s_lshr_b32 s46, s9, 16 -; GFX11-NEXT: s_lshr_b32 s47, s8, 16 -; GFX11-NEXT: s_lshr_b32 s56, s7, 16 -; GFX11-NEXT: s_lshr_b32 s57, s6, 16 -; GFX11-NEXT: s_lshr_b32 s58, s5, 16 -; GFX11-NEXT: s_lshr_b32 s59, s4, 16 -; GFX11-NEXT: s_lshr_b32 s60, s29, 16 -; GFX11-NEXT: s_lshr_b32 s61, s28, 16 -; GFX11-NEXT: s_lshr_b32 s62, s27, 16 -; GFX11-NEXT: s_lshr_b32 s63, s26, 16 -; GFX11-NEXT: s_lshr_b32 s72, s25, 16 -; GFX11-NEXT: s_lshr_b32 s73, s24, 16 -; GFX11-NEXT: s_lshr_b32 s74, s23, 16 -; GFX11-NEXT: s_lshr_b32 s75, s22, 16 -; GFX11-NEXT: s_lshr_b32 s76, s21, 16 -; GFX11-NEXT: s_lshr_b32 s77, s20, 16 -; GFX11-NEXT: s_lshr_b32 s78, s19, 16 -; GFX11-NEXT: s_lshr_b32 s79, s18, 16 -; GFX11-NEXT: s_lshr_b32 s88, s17, 16 -; GFX11-NEXT: s_lshr_b32 s89, s16, 16 +; GFX11-NEXT: s_lshr_b32 s40, s28, 16 +; GFX11-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-NEXT: s_lshr_b32 s42, s27, 16 +; GFX11-NEXT: s_lshr_b32 s43, s26, 16 +; GFX11-NEXT: s_lshr_b32 s44, s25, 16 +; GFX11-NEXT: s_lshr_b32 s45, s24, 16 +; GFX11-NEXT: s_lshr_b32 s46, s23, 16 +; GFX11-NEXT: s_lshr_b32 s47, s22, 16 +; GFX11-NEXT: s_lshr_b32 s56, s21, 16 +; GFX11-NEXT: s_lshr_b32 s57, s20, 16 +; GFX11-NEXT: s_lshr_b32 s58, s19, 16 +; GFX11-NEXT: s_lshr_b32 s59, s18, 16 +; GFX11-NEXT: s_lshr_b32 s60, s17, 16 +; GFX11-NEXT: s_lshr_b32 s61, s16, 16 +; GFX11-NEXT: s_lshr_b32 s62, s15, 16 +; GFX11-NEXT: s_lshr_b32 s63, s14, 16 +; GFX11-NEXT: s_lshr_b32 s72, s13, 16 +; GFX11-NEXT: s_lshr_b32 s73, s12, 16 +; GFX11-NEXT: s_lshr_b32 s74, s11, 16 +; GFX11-NEXT: s_lshr_b32 s75, s10, 16 +; GFX11-NEXT: s_lshr_b32 s76, s9, 16 +; GFX11-NEXT: s_lshr_b32 s77, s8, 16 +; GFX11-NEXT: s_lshr_b32 s78, s7, 16 +; GFX11-NEXT: s_lshr_b32 s79, s6, 16 +; GFX11-NEXT: s_lshr_b32 s88, s5, 16 +; GFX11-NEXT: s_lshr_b32 s89, s4, 16 ; GFX11-NEXT: s_lshr_b32 s90, s3, 16 ; GFX11-NEXT: s_lshr_b32 s91, s2, 16 ; GFX11-NEXT: s_lshr_b32 s92, s1, 16 @@ -29084,47 +28788,47 @@ define inreg <60 x i16> @bitcast_v15i64_to_v60i16_scalar(<15 x i64> inreg %a, i3 ; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s92 ; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s91 ; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s90 -; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s89 -; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s88 -; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s79 -; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s78 -; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s77 -; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s76 -; GFX11-NEXT: s_pack_ll_b32_b16 s22, s22, s75 -; GFX11-NEXT: s_pack_ll_b32_b16 s23, s23, s74 -; GFX11-NEXT: s_pack_ll_b32_b16 s24, s24, s73 -; GFX11-NEXT: s_pack_ll_b32_b16 s25, s25, s72 -; GFX11-NEXT: s_pack_ll_b32_b16 s26, s26, s63 -; GFX11-NEXT: s_pack_ll_b32_b16 s27, s27, s62 -; GFX11-NEXT: s_pack_ll_b32_b16 s28, s28, s61 -; GFX11-NEXT: s_pack_ll_b32_b16 s29, s29, s60 -; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s59 -; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s58 -; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s57 -; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s56 -; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s47 -; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s46 -; GFX11-NEXT: s_pack_ll_b32_b16 s10, s10, s45 -; GFX11-NEXT: s_pack_ll_b32_b16 s11, s11, s44 -; GFX11-NEXT: s_pack_ll_b32_b16 s12, s12, s43 -; GFX11-NEXT: s_pack_ll_b32_b16 s13, s13, s42 -; GFX11-NEXT: s_pack_ll_b32_b16 s15, s15, s41 -; GFX11-NEXT: s_pack_ll_b32_b16 s14, s14, s40 +; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s89 +; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s88 +; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s79 +; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s78 +; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s77 +; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s76 +; GFX11-NEXT: s_pack_ll_b32_b16 s10, s10, s75 +; GFX11-NEXT: s_pack_ll_b32_b16 s11, s11, s74 +; GFX11-NEXT: s_pack_ll_b32_b16 s12, s12, s73 +; GFX11-NEXT: s_pack_ll_b32_b16 s13, s13, s72 +; GFX11-NEXT: s_pack_ll_b32_b16 s14, s14, s63 +; GFX11-NEXT: s_pack_ll_b32_b16 s15, s15, s62 +; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s61 +; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s60 +; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s59 +; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s58 +; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s57 +; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s56 +; GFX11-NEXT: s_pack_ll_b32_b16 s22, s22, s47 +; GFX11-NEXT: s_pack_ll_b32_b16 s23, s23, s46 +; GFX11-NEXT: s_pack_ll_b32_b16 s24, s24, s45 +; GFX11-NEXT: s_pack_ll_b32_b16 s25, s25, s44 +; GFX11-NEXT: s_pack_ll_b32_b16 s26, s26, s43 +; GFX11-NEXT: s_pack_ll_b32_b16 s27, s27, s42 +; GFX11-NEXT: s_pack_ll_b32_b16 s29, s29, s41 +; GFX11-NEXT: s_pack_ll_b32_b16 s28, s28, s40 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 -; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 -; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 -; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 -; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 -; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 -; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 -; GFX11-NEXT: v_dual_mov_b32 v18, s4 :: v_dual_mov_b32 v19, s5 -; GFX11-NEXT: v_dual_mov_b32 v20, s6 :: v_dual_mov_b32 v21, s7 -; GFX11-NEXT: v_dual_mov_b32 v22, s8 :: v_dual_mov_b32 v23, s9 -; GFX11-NEXT: v_dual_mov_b32 v24, s10 :: v_dual_mov_b32 v25, s11 -; GFX11-NEXT: v_dual_mov_b32 v26, s12 :: v_dual_mov_b32 v27, s13 -; GFX11-NEXT: v_dual_mov_b32 v28, s15 :: v_dual_mov_b32 v29, s14 +; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19 +; GFX11-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v21, s21 +; GFX11-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v23, s23 +; GFX11-NEXT: v_dual_mov_b32 v24, s24 :: v_dual_mov_b32 v25, s25 +; GFX11-NEXT: v_dual_mov_b32 v26, s26 :: v_dual_mov_b32 v27, s27 +; GFX11-NEXT: v_dual_mov_b32 v28, s29 :: v_dual_mov_b32 v29, s28 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: .LBB41_4: ; GFX11-NEXT: ; implicit-def: $sgpr93 @@ -29240,40 +28944,53 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) { ; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:8 ; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:4 ; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v2 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v4 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:52 +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:112 ; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:108 +; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v4 +; SI-NEXT: s_waitcnt vmcnt(4) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:44 ; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v6 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v8 -; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:104 ; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:100 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v10 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v6 +; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v8 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:36 +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:96 ; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:92 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v12 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v10 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:28 +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:88 ; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:84 -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v12 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v14 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:48 @@ -29304,27 +29021,10 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) { ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:56 ; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:64 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:52 -; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v28 -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v30 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:44 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:36 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:28 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v30 ; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] @@ -29409,7 +29109,6 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr30 ; SI-NEXT: ; kill: killed $vgpr30 ; SI-NEXT: ; implicit-def: $vgpr30 -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_and_b32_e32 v0, 0xffff, v55 ; SI-NEXT: v_and_b32_e32 v18, 0xffff, v61 ; SI-NEXT: ; kill: killed $vgpr30 @@ -29554,7 +29253,6 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) { ; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v55 ; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v61 ; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0 @@ -29681,7 +29379,7 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) { ; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24 ; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25 ; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26 -; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v27 +; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v27 ; SI-NEXT: v_add_i32_e32 v28, vcc, 0x30000, v28 ; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v29 ; SI-NEXT: .LBB42_4: ; %end @@ -29702,7 +29400,7 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) { ; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] ; ; VI-LABEL: bitcast_v60i16_to_v15i64: @@ -29984,7 +29682,6 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v61, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v29 -; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v28 @@ -30063,6 +29760,7 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v60 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v61 +; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -30227,6 +29925,9 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] ; GFX9-NEXT: s_cbranch_execz .LBB42_4 ; GFX9-NEXT: ; %bb.3: ; %cmp.true +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload @@ -30241,9 +29942,6 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload -; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v38, v61, s6 ; GFX9-NEXT: v_perm_b32 v1, v37, v60, s6 ; GFX9-NEXT: v_perm_b32 v2, v62, v59, s6 @@ -30262,6 +29960,10 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] +; GFX9-NEXT: s_waitcnt vmcnt(14) +; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; GFX9-NEXT: s_waitcnt vmcnt(15) ; GFX9-NEXT: v_perm_b32 v9, v9, v44, s6 ; GFX9-NEXT: s_waitcnt vmcnt(14) @@ -30290,10 +29992,6 @@ define <15 x i64> @bitcast_v60i16_to_v15i64(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: v_perm_b32 v21, v21, v48, s6 ; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: v_perm_b32 v22, v22, v39, s6 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] @@ -31449,304 +31147,115 @@ define inreg <15 x i64> @bitcast_v60i16_to_v15i64_scalar(<60 x i16> inreg %a, i3 ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v190, v6 :: v_dual_mov_b32 v185, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v186, v3 :: v_dual_mov_b32 v187, v2 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v1 :: v_dual_mov_b32 v189, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB43_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB43_3 ; GFX11-TRUE16-NEXT: .LBB43_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s40, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s41, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v189, v189, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v188, v188, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v187, v187, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v186, v186, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v185, v185, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v191, v191, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v190, v190, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, s6, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, s7, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, s8, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s9, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, s10, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, s11, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, s12, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, s13, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s14, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, s15, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, s16, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v30, v30, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s0, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s1, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s2, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, s3, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, s4, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v35, s5, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v44, s6, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v54, s7, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v65, s8, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v77, s9, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v90, s10, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v104, s11, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v119, s12, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v135, s13, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v152, s14, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v170, s15, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: .LBB43_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v170 :: v_dual_mov_b32 v18, v189 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v188 :: v_dual_mov_b32 v20, v187 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v186 :: v_dual_mov_b32 v22, v185 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v191 :: v_dual_mov_b32 v24, v190 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v191, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v190, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v189, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v188, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v187, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:316 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v119 :: v_dual_mov_b32 v27, v30 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB43_4: -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v64, v29 :: v_dual_mov_b32 v65, v28 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v66, v30 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v53, v26 :: v_dual_mov_b32 v54, v25 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v54 :: v_dual_mov_b32 v26, v53 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v65 :: v_dual_mov_b32 v29, v64 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v30, v66 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB43_2 ; ; GFX11-FAKE16-LABEL: bitcast_v60i16_to_v15i64_scalar: @@ -33281,13 +32790,41 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; SI-LABEL: bitcast_v15i64_to_v60f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v18, s16 +; SI-NEXT: v_mov_b32_e32 v19, s17 +; SI-NEXT: v_readfirstlane_b32 s40, v18 +; SI-NEXT: v_mov_b32_e32 v18, s18 +; SI-NEXT: v_readfirstlane_b32 s43, v19 +; SI-NEXT: v_mov_b32_e32 v19, s19 +; SI-NEXT: v_readfirstlane_b32 s41, v18 +; SI-NEXT: v_mov_b32_e32 v18, s20 +; SI-NEXT: v_readfirstlane_b32 s44, v19 +; SI-NEXT: v_mov_b32_e32 v19, s21 +; SI-NEXT: v_readfirstlane_b32 s42, v18 +; SI-NEXT: v_mov_b32_e32 v18, s22 +; SI-NEXT: v_readfirstlane_b32 s45, v19 +; SI-NEXT: v_mov_b32_e32 v19, s23 +; SI-NEXT: v_readfirstlane_b32 s22, v18 +; SI-NEXT: v_mov_b32_e32 v18, s24 +; SI-NEXT: v_readfirstlane_b32 s46, v19 +; SI-NEXT: v_mov_b32_e32 v19, s25 +; SI-NEXT: v_readfirstlane_b32 s23, v18 +; SI-NEXT: v_mov_b32_e32 v18, s26 +; SI-NEXT: v_readfirstlane_b32 s47, v19 +; SI-NEXT: v_mov_b32_e32 v19, s27 +; SI-NEXT: v_readfirstlane_b32 s24, v18 +; SI-NEXT: v_mov_b32_e32 v18, s28 +; SI-NEXT: v_readfirstlane_b32 s27, v19 +; SI-NEXT: v_mov_b32_e32 v19, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; SI-NEXT: v_readfirstlane_b32 s44, v1 -; SI-NEXT: v_readfirstlane_b32 s45, v2 -; SI-NEXT: v_readfirstlane_b32 s42, v3 -; SI-NEXT: v_readfirstlane_b32 s43, v4 -; SI-NEXT: v_readfirstlane_b32 s40, v5 -; SI-NEXT: v_readfirstlane_b32 s41, v6 +; SI-NEXT: v_readfirstlane_b32 s25, v18 +; SI-NEXT: v_readfirstlane_b32 s26, v19 +; SI-NEXT: v_readfirstlane_b32 s20, v1 +; SI-NEXT: v_readfirstlane_b32 s21, v2 +; SI-NEXT: v_readfirstlane_b32 s18, v3 +; SI-NEXT: v_readfirstlane_b32 s19, v4 +; SI-NEXT: v_readfirstlane_b32 s16, v5 +; SI-NEXT: v_readfirstlane_b32 s17, v6 ; SI-NEXT: v_readfirstlane_b32 s14, v7 ; SI-NEXT: v_readfirstlane_b32 s15, v8 ; SI-NEXT: v_readfirstlane_b32 s12, v9 @@ -33334,48 +32871,48 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v15, s4 ; SI-NEXT: s_lshr_b32 s4, s14, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v17, s4 -; SI-NEXT: s_lshr_b32 s4, s41, 16 +; SI-NEXT: s_lshr_b32 s4, s17, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v19, s4 -; SI-NEXT: s_lshr_b32 s4, s40, 16 +; SI-NEXT: s_lshr_b32 s4, s16, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v22, s4 -; SI-NEXT: s_lshr_b32 s4, s43, 16 +; SI-NEXT: s_lshr_b32 s4, s19, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v24, s4 -; SI-NEXT: s_lshr_b32 s4, s42, 16 +; SI-NEXT: s_lshr_b32 s4, s18, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v26, s4 -; SI-NEXT: s_lshr_b32 s4, s45, 16 +; SI-NEXT: s_lshr_b32 s4, s21, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v28, s4 -; SI-NEXT: s_lshr_b32 s4, s44, 16 +; SI-NEXT: s_lshr_b32 s4, s20, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v30, s4 -; SI-NEXT: s_lshr_b32 s4, s29, 16 +; SI-NEXT: s_lshr_b32 s4, s26, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v32, s4 -; SI-NEXT: s_lshr_b32 s4, s28, 16 +; SI-NEXT: s_lshr_b32 s4, s25, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v34, s4 ; SI-NEXT: s_lshr_b32 s4, s27, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v36, s4 -; SI-NEXT: s_lshr_b32 s4, s26, 16 +; SI-NEXT: s_lshr_b32 s4, s24, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v39, s4 -; SI-NEXT: s_lshr_b32 s4, s25, 16 +; SI-NEXT: s_lshr_b32 s4, s47, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v49, s4 -; SI-NEXT: s_lshr_b32 s4, s24, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v51, s4 ; SI-NEXT: s_lshr_b32 s4, s23, 16 +; SI-NEXT: v_cvt_f32_f16_e32 v51, s4 +; SI-NEXT: s_lshr_b32 s4, s46, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v53, s4 ; SI-NEXT: s_lshr_b32 s4, s22, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v55, s4 -; SI-NEXT: s_lshr_b32 s4, s21, 16 +; SI-NEXT: s_lshr_b32 s4, s45, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v41, s4 -; SI-NEXT: s_lshr_b32 s4, s20, 16 +; SI-NEXT: s_lshr_b32 s4, s42, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v43, s4 -; SI-NEXT: s_lshr_b32 s4, s19, 16 +; SI-NEXT: s_lshr_b32 s4, s44, 16 ; SI-NEXT: s_waitcnt expcnt(6) ; SI-NEXT: v_cvt_f32_f16_e32 v46, s4 -; SI-NEXT: s_lshr_b32 s4, s18, 16 +; SI-NEXT: s_lshr_b32 s4, s41, 16 ; SI-NEXT: s_waitcnt expcnt(4) ; SI-NEXT: v_cvt_f32_f16_e32 v56, s4 -; SI-NEXT: s_lshr_b32 s4, s17, 16 +; SI-NEXT: s_lshr_b32 s4, s43, 16 ; SI-NEXT: s_waitcnt expcnt(2) ; SI-NEXT: v_cvt_f32_f16_e32 v58, s4 -; SI-NEXT: s_lshr_b32 s4, s16, 16 +; SI-NEXT: s_lshr_b32 s4, s40, 16 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f32_f16_e32 v60, s4 ; SI-NEXT: v_cvt_f32_f16_e32 v4, s9 @@ -33388,68 +32925,68 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v18, s12 ; SI-NEXT: v_cvt_f32_f16_e32 v20, s15 ; SI-NEXT: v_cvt_f32_f16_e32 v21, s14 -; SI-NEXT: v_cvt_f32_f16_e32 v23, s41 -; SI-NEXT: v_cvt_f32_f16_e32 v25, s40 -; SI-NEXT: v_cvt_f32_f16_e32 v27, s43 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s42 -; SI-NEXT: v_cvt_f32_f16_e32 v31, s45 -; SI-NEXT: v_cvt_f32_f16_e32 v33, s44 -; SI-NEXT: v_cvt_f32_f16_e32 v35, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v37, s28 +; SI-NEXT: v_cvt_f32_f16_e32 v23, s17 +; SI-NEXT: v_cvt_f32_f16_e32 v25, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v27, s19 +; SI-NEXT: v_cvt_f32_f16_e32 v29, s18 +; SI-NEXT: v_cvt_f32_f16_e32 v31, s21 +; SI-NEXT: v_cvt_f32_f16_e32 v33, s20 +; SI-NEXT: v_cvt_f32_f16_e32 v35, s26 +; SI-NEXT: v_cvt_f32_f16_e32 v37, s25 ; SI-NEXT: v_cvt_f32_f16_e32 v38, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v48, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v50, s25 -; SI-NEXT: v_cvt_f32_f16_e32 v52, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v54, s23 +; SI-NEXT: v_cvt_f32_f16_e32 v48, s24 +; SI-NEXT: v_cvt_f32_f16_e32 v50, s47 +; SI-NEXT: v_cvt_f32_f16_e32 v52, s23 +; SI-NEXT: v_cvt_f32_f16_e32 v54, s46 ; SI-NEXT: v_cvt_f32_f16_e32 v40, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v42, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v44, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v45, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v47, s18 -; SI-NEXT: v_cvt_f32_f16_e32 v57, s17 -; SI-NEXT: v_cvt_f32_f16_e32 v59, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v42, s45 +; SI-NEXT: v_cvt_f32_f16_e32 v44, s42 +; SI-NEXT: v_cvt_f32_f16_e32 v45, s44 +; SI-NEXT: v_cvt_f32_f16_e32 v47, s41 +; SI-NEXT: v_cvt_f32_f16_e32 v57, s43 +; SI-NEXT: v_cvt_f32_f16_e32 v59, s40 ; SI-NEXT: s_cbranch_execnz .LBB45_3 ; SI-NEXT: .LBB45_2: ; %cmp.true -; SI-NEXT: s_add_u32 s4, s16, 3 -; SI-NEXT: s_addc_u32 s5, s17, 0 -; SI-NEXT: s_lshr_b32 s16, s4, 16 -; SI-NEXT: s_lshr_b32 s17, s5, 16 -; SI-NEXT: s_add_u32 s18, s18, 3 -; SI-NEXT: s_addc_u32 s19, s19, 0 -; SI-NEXT: s_lshr_b32 s46, s18, 16 -; SI-NEXT: s_lshr_b32 s47, s19, 16 -; SI-NEXT: s_add_u32 s20, s20, 3 -; SI-NEXT: s_addc_u32 s21, s21, 0 -; SI-NEXT: s_lshr_b32 s56, s20, 16 -; SI-NEXT: s_lshr_b32 s57, s21, 16 +; SI-NEXT: s_add_u32 s4, s40, 3 +; SI-NEXT: s_addc_u32 s5, s43, 0 +; SI-NEXT: s_lshr_b32 s28, s4, 16 +; SI-NEXT: s_lshr_b32 s29, s5, 16 +; SI-NEXT: s_add_u32 s40, s41, 3 +; SI-NEXT: s_addc_u32 s41, s44, 0 +; SI-NEXT: s_lshr_b32 s43, s40, 16 +; SI-NEXT: s_lshr_b32 s44, s41, 16 +; SI-NEXT: s_add_u32 s42, s42, 3 +; SI-NEXT: s_addc_u32 s45, s45, 0 +; SI-NEXT: s_lshr_b32 s56, s42, 16 +; SI-NEXT: s_lshr_b32 s57, s45, 16 ; SI-NEXT: s_add_u32 s22, s22, 3 -; SI-NEXT: s_addc_u32 s23, s23, 0 +; SI-NEXT: s_addc_u32 s46, s46, 0 ; SI-NEXT: s_lshr_b32 s58, s22, 16 -; SI-NEXT: s_lshr_b32 s59, s23, 16 +; SI-NEXT: s_lshr_b32 s59, s46, 16 +; SI-NEXT: s_add_u32 s23, s23, 3 +; SI-NEXT: s_addc_u32 s47, s47, 0 +; SI-NEXT: s_lshr_b32 s60, s23, 16 +; SI-NEXT: s_lshr_b32 s61, s47, 16 ; SI-NEXT: s_add_u32 s24, s24, 3 -; SI-NEXT: s_addc_u32 s25, s25, 0 -; SI-NEXT: s_lshr_b32 s60, s24, 16 -; SI-NEXT: s_lshr_b32 s61, s25, 16 -; SI-NEXT: s_add_u32 s26, s26, 3 ; SI-NEXT: s_addc_u32 s27, s27, 0 -; SI-NEXT: s_lshr_b32 s62, s26, 16 +; SI-NEXT: s_lshr_b32 s62, s24, 16 ; SI-NEXT: s_lshr_b32 s63, s27, 16 -; SI-NEXT: s_add_u32 s28, s28, 3 -; SI-NEXT: s_addc_u32 s29, s29, 0 -; SI-NEXT: s_lshr_b32 s72, s28, 16 -; SI-NEXT: s_lshr_b32 s73, s29, 16 -; SI-NEXT: s_add_u32 s44, s44, 3 -; SI-NEXT: s_addc_u32 s45, s45, 0 -; SI-NEXT: s_lshr_b32 s74, s44, 16 -; SI-NEXT: s_lshr_b32 s75, s45, 16 -; SI-NEXT: s_add_u32 s42, s42, 3 -; SI-NEXT: s_addc_u32 s43, s43, 0 -; SI-NEXT: s_lshr_b32 s76, s42, 16 -; SI-NEXT: s_lshr_b32 s77, s43, 16 -; SI-NEXT: s_add_u32 s40, s40, 3 -; SI-NEXT: s_addc_u32 s41, s41, 0 -; SI-NEXT: s_lshr_b32 s78, s40, 16 -; SI-NEXT: s_lshr_b32 s79, s41, 16 +; SI-NEXT: s_add_u32 s25, s25, 3 +; SI-NEXT: s_addc_u32 s26, s26, 0 +; SI-NEXT: s_lshr_b32 s72, s25, 16 +; SI-NEXT: s_lshr_b32 s73, s26, 16 +; SI-NEXT: s_add_u32 s20, s20, 3 +; SI-NEXT: s_addc_u32 s21, s21, 0 +; SI-NEXT: s_lshr_b32 s74, s20, 16 +; SI-NEXT: s_lshr_b32 s75, s21, 16 +; SI-NEXT: s_add_u32 s18, s18, 3 +; SI-NEXT: s_addc_u32 s19, s19, 0 +; SI-NEXT: s_lshr_b32 s76, s18, 16 +; SI-NEXT: s_lshr_b32 s77, s19, 16 +; SI-NEXT: s_add_u32 s16, s16, 3 +; SI-NEXT: s_addc_u32 s17, s17, 0 +; SI-NEXT: s_lshr_b32 s78, s16, 16 +; SI-NEXT: s_lshr_b32 s79, s17, 16 ; SI-NEXT: s_add_u32 s14, s14, 3 ; SI-NEXT: s_addc_u32 s15, s15, 0 ; SI-NEXT: s_lshr_b32 s88, s14, 16 @@ -33480,25 +33017,25 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v18, s12 ; SI-NEXT: v_cvt_f32_f16_e32 v20, s15 ; SI-NEXT: v_cvt_f32_f16_e32 v21, s14 -; SI-NEXT: v_cvt_f32_f16_e32 v23, s41 -; SI-NEXT: v_cvt_f32_f16_e32 v25, s40 -; SI-NEXT: v_cvt_f32_f16_e32 v27, s43 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s42 -; SI-NEXT: v_cvt_f32_f16_e32 v31, s45 -; SI-NEXT: v_cvt_f32_f16_e32 v33, s44 -; SI-NEXT: v_cvt_f32_f16_e32 v35, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v37, s28 +; SI-NEXT: v_cvt_f32_f16_e32 v23, s17 +; SI-NEXT: v_cvt_f32_f16_e32 v25, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v27, s19 +; SI-NEXT: v_cvt_f32_f16_e32 v29, s18 +; SI-NEXT: v_cvt_f32_f16_e32 v31, s21 +; SI-NEXT: v_cvt_f32_f16_e32 v33, s20 +; SI-NEXT: v_cvt_f32_f16_e32 v35, s26 +; SI-NEXT: v_cvt_f32_f16_e32 v37, s25 ; SI-NEXT: v_cvt_f32_f16_e32 v38, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v48, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v50, s25 -; SI-NEXT: v_cvt_f32_f16_e32 v52, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v54, s23 +; SI-NEXT: v_cvt_f32_f16_e32 v48, s24 +; SI-NEXT: v_cvt_f32_f16_e32 v50, s47 +; SI-NEXT: v_cvt_f32_f16_e32 v52, s23 +; SI-NEXT: v_cvt_f32_f16_e32 v54, s46 ; SI-NEXT: v_cvt_f32_f16_e32 v40, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v42, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v44, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v45, s19 +; SI-NEXT: v_cvt_f32_f16_e32 v42, s45 +; SI-NEXT: v_cvt_f32_f16_e32 v44, s42 +; SI-NEXT: v_cvt_f32_f16_e32 v45, s41 ; SI-NEXT: s_waitcnt expcnt(5) -; SI-NEXT: v_cvt_f32_f16_e32 v47, s18 +; SI-NEXT: v_cvt_f32_f16_e32 v47, s40 ; SI-NEXT: s_waitcnt expcnt(3) ; SI-NEXT: v_cvt_f32_f16_e32 v57, s5 ; SI-NEXT: s_waitcnt expcnt(1) @@ -33529,11 +33066,11 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v55, s58 ; SI-NEXT: v_cvt_f32_f16_e32 v41, s57 ; SI-NEXT: v_cvt_f32_f16_e32 v43, s56 -; SI-NEXT: v_cvt_f32_f16_e32 v46, s47 -; SI-NEXT: v_cvt_f32_f16_e32 v56, s46 -; SI-NEXT: v_cvt_f32_f16_e32 v58, s17 +; SI-NEXT: v_cvt_f32_f16_e32 v46, s44 +; SI-NEXT: v_cvt_f32_f16_e32 v56, s43 +; SI-NEXT: v_cvt_f32_f16_e32 v58, s29 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v60, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v60, s28 ; SI-NEXT: .LBB45_3: ; %end ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v60, v60 @@ -33830,18 +33367,46 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; VI-NEXT: s_mov_b64 exec, s[4:5] ; VI-NEXT: v_writelane_b32 v30, s30, 0 ; VI-NEXT: v_writelane_b32 v30, s31, 1 +; VI-NEXT: v_mov_b32_e32 v17, s16 +; VI-NEXT: v_mov_b32_e32 v18, s17 ; VI-NEXT: v_writelane_b32 v30, s34, 2 +; VI-NEXT: v_mov_b32_e32 v19, s18 +; VI-NEXT: v_readfirstlane_b32 s56, v17 +; VI-NEXT: v_mov_b32_e32 v17, s19 +; VI-NEXT: v_readfirstlane_b32 s47, v18 +; VI-NEXT: v_mov_b32_e32 v18, s20 ; VI-NEXT: v_writelane_b32 v30, s35, 3 +; VI-NEXT: v_readfirstlane_b32 s46, v19 +; VI-NEXT: v_mov_b32_e32 v19, s21 +; VI-NEXT: v_readfirstlane_b32 s45, v17 +; VI-NEXT: v_mov_b32_e32 v17, s22 +; VI-NEXT: v_readfirstlane_b32 s44, v18 +; VI-NEXT: v_mov_b32_e32 v18, s23 ; VI-NEXT: v_writelane_b32 v30, s36, 4 +; VI-NEXT: v_readfirstlane_b32 s43, v19 +; VI-NEXT: v_mov_b32_e32 v19, s24 +; VI-NEXT: v_readfirstlane_b32 s42, v17 +; VI-NEXT: v_mov_b32_e32 v17, s25 +; VI-NEXT: v_readfirstlane_b32 s41, v18 +; VI-NEXT: v_mov_b32_e32 v18, s26 ; VI-NEXT: v_writelane_b32 v30, s37, 5 +; VI-NEXT: v_readfirstlane_b32 s40, v19 +; VI-NEXT: v_mov_b32_e32 v19, s27 +; VI-NEXT: v_readfirstlane_b32 s26, v17 +; VI-NEXT: v_mov_b32_e32 v17, s28 +; VI-NEXT: v_readfirstlane_b32 s25, v18 +; VI-NEXT: v_mov_b32_e32 v18, s29 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 ; VI-NEXT: v_writelane_b32 v30, s38, 6 -; VI-NEXT: v_readfirstlane_b32 s45, v0 -; VI-NEXT: v_readfirstlane_b32 s44, v1 -; VI-NEXT: v_readfirstlane_b32 s43, v2 -; VI-NEXT: v_readfirstlane_b32 s42, v3 -; VI-NEXT: v_readfirstlane_b32 s41, v4 -; VI-NEXT: v_readfirstlane_b32 s40, v5 +; VI-NEXT: v_readfirstlane_b32 s24, v19 +; VI-NEXT: v_readfirstlane_b32 s23, v17 +; VI-NEXT: v_readfirstlane_b32 s22, v18 +; VI-NEXT: v_readfirstlane_b32 s21, v0 +; VI-NEXT: v_readfirstlane_b32 s20, v1 +; VI-NEXT: v_readfirstlane_b32 s19, v2 +; VI-NEXT: v_readfirstlane_b32 s18, v3 +; VI-NEXT: v_readfirstlane_b32 s17, v4 +; VI-NEXT: v_readfirstlane_b32 s16, v5 ; VI-NEXT: v_readfirstlane_b32 s15, v6 ; VI-NEXT: v_readfirstlane_b32 s14, v7 ; VI-NEXT: v_readfirstlane_b32 s13, v8 @@ -33856,9 +33421,9 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; VI-NEXT: v_writelane_b32 v30, s39, 7 ; VI-NEXT: s_cbranch_scc0 .LBB45_4 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_lshr_b32 s46, s7, 16 -; VI-NEXT: s_lshr_b32 s47, s6, 16 -; VI-NEXT: s_lshr_b32 s56, s8, 16 +; VI-NEXT: s_lshr_b32 s27, s7, 16 +; VI-NEXT: s_lshr_b32 s28, s6, 16 +; VI-NEXT: s_lshr_b32 s29, s8, 16 ; VI-NEXT: s_lshr_b32 s57, s9, 16 ; VI-NEXT: s_lshr_b32 s58, s10, 16 ; VI-NEXT: s_lshr_b32 s59, s11, 16 @@ -33866,26 +33431,26 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; VI-NEXT: s_lshr_b32 s61, s13, 16 ; VI-NEXT: s_lshr_b32 s62, s14, 16 ; VI-NEXT: s_lshr_b32 s63, s15, 16 -; VI-NEXT: s_lshr_b32 s72, s40, 16 -; VI-NEXT: s_lshr_b32 s73, s41, 16 -; VI-NEXT: s_lshr_b32 s74, s42, 16 -; VI-NEXT: s_lshr_b32 s75, s43, 16 -; VI-NEXT: s_lshr_b32 s76, s44, 16 -; VI-NEXT: s_lshr_b32 s77, s45, 16 -; VI-NEXT: s_lshr_b32 s78, s29, 16 -; VI-NEXT: s_lshr_b32 s79, s28, 16 -; VI-NEXT: s_lshr_b32 s88, s27, 16 -; VI-NEXT: s_lshr_b32 s89, s26, 16 -; VI-NEXT: s_lshr_b32 s90, s25, 16 -; VI-NEXT: s_lshr_b32 s91, s24, 16 -; VI-NEXT: s_lshr_b32 s30, s23, 16 -; VI-NEXT: s_lshr_b32 s31, s22, 16 -; VI-NEXT: s_lshr_b32 s34, s21, 16 -; VI-NEXT: s_lshr_b32 s35, s20, 16 -; VI-NEXT: s_lshr_b32 s36, s19, 16 -; VI-NEXT: s_lshr_b32 s37, s18, 16 -; VI-NEXT: s_lshr_b32 s38, s17, 16 -; VI-NEXT: s_lshr_b32 s39, s16, 16 +; VI-NEXT: s_lshr_b32 s72, s16, 16 +; VI-NEXT: s_lshr_b32 s73, s17, 16 +; VI-NEXT: s_lshr_b32 s74, s18, 16 +; VI-NEXT: s_lshr_b32 s75, s19, 16 +; VI-NEXT: s_lshr_b32 s76, s20, 16 +; VI-NEXT: s_lshr_b32 s77, s21, 16 +; VI-NEXT: s_lshr_b32 s78, s22, 16 +; VI-NEXT: s_lshr_b32 s79, s23, 16 +; VI-NEXT: s_lshr_b32 s88, s24, 16 +; VI-NEXT: s_lshr_b32 s89, s25, 16 +; VI-NEXT: s_lshr_b32 s90, s26, 16 +; VI-NEXT: s_lshr_b32 s91, s40, 16 +; VI-NEXT: s_lshr_b32 s30, s41, 16 +; VI-NEXT: s_lshr_b32 s31, s42, 16 +; VI-NEXT: s_lshr_b32 s34, s43, 16 +; VI-NEXT: s_lshr_b32 s35, s44, 16 +; VI-NEXT: s_lshr_b32 s36, s45, 16 +; VI-NEXT: s_lshr_b32 s37, s46, 16 +; VI-NEXT: s_lshr_b32 s38, s47, 16 +; VI-NEXT: s_lshr_b32 s39, s56, 16 ; VI-NEXT: s_cbranch_execnz .LBB45_3 ; VI-NEXT: .LBB45_2: ; %cmp.true ; VI-NEXT: s_add_u32 s6, s6, 3 @@ -33898,29 +33463,29 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; VI-NEXT: s_addc_u32 s12, s12, 0 ; VI-NEXT: s_add_u32 s15, s15, 3 ; VI-NEXT: s_addc_u32 s14, s14, 0 -; VI-NEXT: s_add_u32 s41, s41, 3 -; VI-NEXT: s_addc_u32 s40, s40, 0 -; VI-NEXT: s_add_u32 s43, s43, 3 -; VI-NEXT: s_addc_u32 s42, s42, 0 -; VI-NEXT: s_add_u32 s45, s45, 3 -; VI-NEXT: s_addc_u32 s44, s44, 0 -; VI-NEXT: s_add_u32 s28, s28, 3 -; VI-NEXT: s_addc_u32 s29, s29, 0 -; VI-NEXT: s_add_u32 s26, s26, 3 -; VI-NEXT: s_addc_u32 s27, s27, 0 -; VI-NEXT: s_add_u32 s24, s24, 3 -; VI-NEXT: s_addc_u32 s25, s25, 0 -; VI-NEXT: s_add_u32 s22, s22, 3 -; VI-NEXT: s_addc_u32 s23, s23, 0 -; VI-NEXT: s_add_u32 s20, s20, 3 -; VI-NEXT: s_addc_u32 s21, s21, 0 -; VI-NEXT: s_add_u32 s18, s18, 3 -; VI-NEXT: s_addc_u32 s19, s19, 0 -; VI-NEXT: s_add_u32 s16, s16, 3 -; VI-NEXT: s_addc_u32 s17, s17, 0 -; VI-NEXT: s_lshr_b32 s46, s7, 16 -; VI-NEXT: s_lshr_b32 s47, s6, 16 -; VI-NEXT: s_lshr_b32 s56, s8, 16 +; VI-NEXT: s_add_u32 s17, s17, 3 +; VI-NEXT: s_addc_u32 s16, s16, 0 +; VI-NEXT: s_add_u32 s19, s19, 3 +; VI-NEXT: s_addc_u32 s18, s18, 0 +; VI-NEXT: s_add_u32 s21, s21, 3 +; VI-NEXT: s_addc_u32 s20, s20, 0 +; VI-NEXT: s_add_u32 s23, s23, 3 +; VI-NEXT: s_addc_u32 s22, s22, 0 +; VI-NEXT: s_add_u32 s25, s25, 3 +; VI-NEXT: s_addc_u32 s24, s24, 0 +; VI-NEXT: s_add_u32 s40, s40, 3 +; VI-NEXT: s_addc_u32 s26, s26, 0 +; VI-NEXT: s_add_u32 s42, s42, 3 +; VI-NEXT: s_addc_u32 s41, s41, 0 +; VI-NEXT: s_add_u32 s44, s44, 3 +; VI-NEXT: s_addc_u32 s43, s43, 0 +; VI-NEXT: s_add_u32 s46, s46, 3 +; VI-NEXT: s_addc_u32 s45, s45, 0 +; VI-NEXT: s_add_u32 s56, s56, 3 +; VI-NEXT: s_addc_u32 s47, s47, 0 +; VI-NEXT: s_lshr_b32 s27, s7, 16 +; VI-NEXT: s_lshr_b32 s28, s6, 16 +; VI-NEXT: s_lshr_b32 s29, s8, 16 ; VI-NEXT: s_lshr_b32 s57, s9, 16 ; VI-NEXT: s_lshr_b32 s58, s10, 16 ; VI-NEXT: s_lshr_b32 s59, s11, 16 @@ -33928,137 +33493,137 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; VI-NEXT: s_lshr_b32 s61, s13, 16 ; VI-NEXT: s_lshr_b32 s62, s14, 16 ; VI-NEXT: s_lshr_b32 s63, s15, 16 -; VI-NEXT: s_lshr_b32 s72, s40, 16 -; VI-NEXT: s_lshr_b32 s73, s41, 16 -; VI-NEXT: s_lshr_b32 s74, s42, 16 -; VI-NEXT: s_lshr_b32 s75, s43, 16 -; VI-NEXT: s_lshr_b32 s76, s44, 16 -; VI-NEXT: s_lshr_b32 s77, s45, 16 -; VI-NEXT: s_lshr_b32 s78, s29, 16 -; VI-NEXT: s_lshr_b32 s79, s28, 16 -; VI-NEXT: s_lshr_b32 s88, s27, 16 -; VI-NEXT: s_lshr_b32 s89, s26, 16 -; VI-NEXT: s_lshr_b32 s90, s25, 16 -; VI-NEXT: s_lshr_b32 s91, s24, 16 -; VI-NEXT: s_lshr_b32 s30, s23, 16 -; VI-NEXT: s_lshr_b32 s31, s22, 16 -; VI-NEXT: s_lshr_b32 s34, s21, 16 -; VI-NEXT: s_lshr_b32 s35, s20, 16 -; VI-NEXT: s_lshr_b32 s36, s19, 16 -; VI-NEXT: s_lshr_b32 s37, s18, 16 -; VI-NEXT: s_lshr_b32 s38, s17, 16 -; VI-NEXT: s_lshr_b32 s39, s16, 16 +; VI-NEXT: s_lshr_b32 s72, s16, 16 +; VI-NEXT: s_lshr_b32 s73, s17, 16 +; VI-NEXT: s_lshr_b32 s74, s18, 16 +; VI-NEXT: s_lshr_b32 s75, s19, 16 +; VI-NEXT: s_lshr_b32 s76, s20, 16 +; VI-NEXT: s_lshr_b32 s77, s21, 16 +; VI-NEXT: s_lshr_b32 s78, s22, 16 +; VI-NEXT: s_lshr_b32 s79, s23, 16 +; VI-NEXT: s_lshr_b32 s88, s24, 16 +; VI-NEXT: s_lshr_b32 s89, s25, 16 +; VI-NEXT: s_lshr_b32 s90, s26, 16 +; VI-NEXT: s_lshr_b32 s91, s40, 16 +; VI-NEXT: s_lshr_b32 s30, s41, 16 +; VI-NEXT: s_lshr_b32 s31, s42, 16 +; VI-NEXT: s_lshr_b32 s34, s43, 16 +; VI-NEXT: s_lshr_b32 s35, s44, 16 +; VI-NEXT: s_lshr_b32 s36, s45, 16 +; VI-NEXT: s_lshr_b32 s37, s46, 16 +; VI-NEXT: s_lshr_b32 s38, s47, 16 +; VI-NEXT: s_lshr_b32 s39, s56, 16 ; VI-NEXT: .LBB45_3: ; %end -; VI-NEXT: s_and_b32 s4, 0xffff, s16 +; VI-NEXT: s_and_b32 s4, 0xffff, s56 ; VI-NEXT: s_lshl_b32 s5, s39, 16 ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_and_b32 s5, 0xffff, s17 -; VI-NEXT: s_lshl_b32 s16, s38, 16 -; VI-NEXT: s_or_b32 s5, s5, s16 -; VI-NEXT: s_and_b32 s16, 0xffff, s18 -; VI-NEXT: s_lshl_b32 s17, s37, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, 0xffff, s19 -; VI-NEXT: s_lshl_b32 s18, s36, 16 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s18, 0xffff, s20 -; VI-NEXT: s_lshl_b32 s19, s35, 16 -; VI-NEXT: s_or_b32 s18, s18, s19 -; VI-NEXT: s_and_b32 s19, 0xffff, s21 -; VI-NEXT: s_lshl_b32 s20, s34, 16 -; VI-NEXT: s_or_b32 s19, s19, s20 -; VI-NEXT: s_and_b32 s20, 0xffff, s22 -; VI-NEXT: s_lshl_b32 s21, s31, 16 -; VI-NEXT: s_or_b32 s20, s20, s21 -; VI-NEXT: s_and_b32 s21, 0xffff, s23 -; VI-NEXT: s_lshl_b32 s22, s30, 16 -; VI-NEXT: s_or_b32 s21, s21, s22 -; VI-NEXT: s_and_b32 s22, 0xffff, s24 -; VI-NEXT: s_lshl_b32 s23, s91, 16 -; VI-NEXT: s_or_b32 s22, s22, s23 -; VI-NEXT: s_and_b32 s23, 0xffff, s25 -; VI-NEXT: s_lshl_b32 s24, s90, 16 -; VI-NEXT: s_or_b32 s23, s23, s24 -; VI-NEXT: s_and_b32 s24, 0xffff, s26 -; VI-NEXT: s_lshl_b32 s25, s89, 16 -; VI-NEXT: s_or_b32 s24, s24, s25 -; VI-NEXT: s_and_b32 s25, 0xffff, s27 -; VI-NEXT: s_lshl_b32 s26, s88, 16 -; VI-NEXT: s_or_b32 s25, s25, s26 -; VI-NEXT: s_and_b32 s26, 0xffff, s28 -; VI-NEXT: s_lshl_b32 s27, s79, 16 -; VI-NEXT: s_or_b32 s26, s26, s27 -; VI-NEXT: s_and_b32 s27, 0xffff, s29 -; VI-NEXT: s_lshl_b32 s28, s78, 16 -; VI-NEXT: s_or_b32 s27, s27, s28 -; VI-NEXT: s_and_b32 s28, 0xffff, s45 -; VI-NEXT: s_lshl_b32 s29, s77, 16 -; VI-NEXT: s_or_b32 s28, s28, s29 -; VI-NEXT: s_and_b32 s29, 0xffff, s44 -; VI-NEXT: s_lshl_b32 s44, s76, 16 -; VI-NEXT: s_or_b32 s29, s29, s44 +; VI-NEXT: s_and_b32 s5, 0xffff, s47 +; VI-NEXT: s_lshl_b32 s47, s38, 16 +; VI-NEXT: s_or_b32 s5, s5, s47 +; VI-NEXT: s_and_b32 s46, 0xffff, s46 +; VI-NEXT: s_lshl_b32 s47, s37, 16 +; VI-NEXT: s_or_b32 s46, s46, s47 +; VI-NEXT: s_and_b32 s45, 0xffff, s45 +; VI-NEXT: s_lshl_b32 s47, s36, 16 +; VI-NEXT: s_or_b32 s45, s45, s47 +; VI-NEXT: s_and_b32 s44, 0xffff, s44 +; VI-NEXT: s_lshl_b32 s47, s35, 16 +; VI-NEXT: s_or_b32 s44, s44, s47 ; VI-NEXT: s_and_b32 s43, 0xffff, s43 -; VI-NEXT: s_lshl_b32 s44, s75, 16 -; VI-NEXT: s_or_b32 s43, s43, s44 +; VI-NEXT: s_lshl_b32 s47, s34, 16 +; VI-NEXT: s_or_b32 s43, s43, s47 ; VI-NEXT: s_and_b32 s42, 0xffff, s42 -; VI-NEXT: s_lshl_b32 s44, s74, 16 -; VI-NEXT: s_or_b32 s42, s42, s44 +; VI-NEXT: s_lshl_b32 s47, s31, 16 +; VI-NEXT: s_or_b32 s42, s42, s47 ; VI-NEXT: s_and_b32 s41, 0xffff, s41 -; VI-NEXT: s_lshl_b32 s44, s73, 16 -; VI-NEXT: s_or_b32 s41, s41, s44 +; VI-NEXT: s_lshl_b32 s47, s30, 16 +; VI-NEXT: s_or_b32 s41, s41, s47 ; VI-NEXT: s_and_b32 s40, 0xffff, s40 -; VI-NEXT: s_lshl_b32 s44, s72, 16 -; VI-NEXT: s_or_b32 s40, s40, s44 +; VI-NEXT: s_lshl_b32 s47, s91, 16 +; VI-NEXT: s_or_b32 s40, s40, s47 +; VI-NEXT: s_and_b32 s26, 0xffff, s26 +; VI-NEXT: s_lshl_b32 s47, s90, 16 +; VI-NEXT: s_or_b32 s26, s26, s47 +; VI-NEXT: s_and_b32 s25, 0xffff, s25 +; VI-NEXT: s_lshl_b32 s47, s89, 16 +; VI-NEXT: s_or_b32 s25, s25, s47 +; VI-NEXT: s_and_b32 s24, 0xffff, s24 +; VI-NEXT: s_lshl_b32 s47, s88, 16 +; VI-NEXT: s_or_b32 s24, s24, s47 +; VI-NEXT: s_and_b32 s23, 0xffff, s23 +; VI-NEXT: s_lshl_b32 s47, s79, 16 +; VI-NEXT: s_or_b32 s23, s23, s47 +; VI-NEXT: s_and_b32 s22, 0xffff, s22 +; VI-NEXT: s_lshl_b32 s47, s78, 16 +; VI-NEXT: s_or_b32 s22, s22, s47 +; VI-NEXT: s_and_b32 s21, 0xffff, s21 +; VI-NEXT: s_lshl_b32 s47, s77, 16 +; VI-NEXT: s_or_b32 s21, s21, s47 +; VI-NEXT: s_and_b32 s20, 0xffff, s20 +; VI-NEXT: s_lshl_b32 s47, s76, 16 +; VI-NEXT: s_or_b32 s20, s20, s47 +; VI-NEXT: s_and_b32 s19, 0xffff, s19 +; VI-NEXT: s_lshl_b32 s47, s75, 16 +; VI-NEXT: s_or_b32 s19, s19, s47 +; VI-NEXT: s_and_b32 s18, 0xffff, s18 +; VI-NEXT: s_lshl_b32 s47, s74, 16 +; VI-NEXT: s_or_b32 s18, s18, s47 +; VI-NEXT: s_and_b32 s17, 0xffff, s17 +; VI-NEXT: s_lshl_b32 s47, s73, 16 +; VI-NEXT: s_or_b32 s17, s17, s47 +; VI-NEXT: s_and_b32 s16, 0xffff, s16 +; VI-NEXT: s_lshl_b32 s47, s72, 16 +; VI-NEXT: s_or_b32 s16, s16, s47 ; VI-NEXT: s_and_b32 s15, 0xffff, s15 -; VI-NEXT: s_lshl_b32 s44, s63, 16 -; VI-NEXT: s_or_b32 s15, s15, s44 +; VI-NEXT: s_lshl_b32 s47, s63, 16 +; VI-NEXT: s_or_b32 s15, s15, s47 ; VI-NEXT: s_and_b32 s14, 0xffff, s14 -; VI-NEXT: s_lshl_b32 s44, s62, 16 -; VI-NEXT: s_or_b32 s14, s14, s44 +; VI-NEXT: s_lshl_b32 s47, s62, 16 +; VI-NEXT: s_or_b32 s14, s14, s47 ; VI-NEXT: s_and_b32 s13, 0xffff, s13 -; VI-NEXT: s_lshl_b32 s44, s61, 16 -; VI-NEXT: s_or_b32 s13, s13, s44 +; VI-NEXT: s_lshl_b32 s47, s61, 16 +; VI-NEXT: s_or_b32 s13, s13, s47 ; VI-NEXT: s_and_b32 s12, 0xffff, s12 -; VI-NEXT: s_lshl_b32 s44, s60, 16 -; VI-NEXT: s_or_b32 s12, s12, s44 +; VI-NEXT: s_lshl_b32 s47, s60, 16 +; VI-NEXT: s_or_b32 s12, s12, s47 ; VI-NEXT: s_and_b32 s11, 0xffff, s11 -; VI-NEXT: s_lshl_b32 s44, s59, 16 -; VI-NEXT: s_or_b32 s11, s11, s44 +; VI-NEXT: s_lshl_b32 s47, s59, 16 +; VI-NEXT: s_or_b32 s11, s11, s47 ; VI-NEXT: s_and_b32 s10, 0xffff, s10 -; VI-NEXT: s_lshl_b32 s44, s58, 16 -; VI-NEXT: s_or_b32 s10, s10, s44 +; VI-NEXT: s_lshl_b32 s47, s58, 16 +; VI-NEXT: s_or_b32 s10, s10, s47 ; VI-NEXT: s_and_b32 s9, 0xffff, s9 -; VI-NEXT: s_lshl_b32 s44, s57, 16 -; VI-NEXT: s_or_b32 s9, s9, s44 +; VI-NEXT: s_lshl_b32 s47, s57, 16 ; VI-NEXT: s_and_b32 s8, 0xffff, s8 -; VI-NEXT: s_lshl_b32 s44, s56, 16 -; VI-NEXT: s_or_b32 s8, s8, s44 +; VI-NEXT: s_lshl_b32 s29, s29, 16 ; VI-NEXT: s_and_b32 s6, 0xffff, s6 -; VI-NEXT: s_lshl_b32 s44, s47, 16 -; VI-NEXT: s_or_b32 s6, s6, s44 +; VI-NEXT: s_lshl_b32 s28, s28, 16 ; VI-NEXT: s_and_b32 s7, 0xffff, s7 -; VI-NEXT: s_lshl_b32 s44, s46, 16 -; VI-NEXT: s_or_b32 s7, s7, s44 +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s9, s9, s47 +; VI-NEXT: s_or_b32 s8, s8, s29 +; VI-NEXT: s_or_b32 s6, s6, s28 +; VI-NEXT: s_or_b32 s7, s7, s27 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s5 -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: v_mov_b32_e32 v3, s17 -; VI-NEXT: v_mov_b32_e32 v4, s18 -; VI-NEXT: v_mov_b32_e32 v5, s19 -; VI-NEXT: v_mov_b32_e32 v6, s20 -; VI-NEXT: v_mov_b32_e32 v7, s21 -; VI-NEXT: v_mov_b32_e32 v8, s22 -; VI-NEXT: v_mov_b32_e32 v9, s23 -; VI-NEXT: v_mov_b32_e32 v10, s24 -; VI-NEXT: v_mov_b32_e32 v11, s25 -; VI-NEXT: v_mov_b32_e32 v12, s26 -; VI-NEXT: v_mov_b32_e32 v13, s27 -; VI-NEXT: v_mov_b32_e32 v14, s28 -; VI-NEXT: v_mov_b32_e32 v15, s29 -; VI-NEXT: v_mov_b32_e32 v16, s43 -; VI-NEXT: v_mov_b32_e32 v17, s42 -; VI-NEXT: v_mov_b32_e32 v18, s41 -; VI-NEXT: v_mov_b32_e32 v19, s40 +; VI-NEXT: v_mov_b32_e32 v2, s46 +; VI-NEXT: v_mov_b32_e32 v3, s45 +; VI-NEXT: v_mov_b32_e32 v4, s44 +; VI-NEXT: v_mov_b32_e32 v5, s43 +; VI-NEXT: v_mov_b32_e32 v6, s42 +; VI-NEXT: v_mov_b32_e32 v7, s41 +; VI-NEXT: v_mov_b32_e32 v8, s40 +; VI-NEXT: v_mov_b32_e32 v9, s26 +; VI-NEXT: v_mov_b32_e32 v10, s25 +; VI-NEXT: v_mov_b32_e32 v11, s24 +; VI-NEXT: v_mov_b32_e32 v12, s23 +; VI-NEXT: v_mov_b32_e32 v13, s22 +; VI-NEXT: v_mov_b32_e32 v14, s21 +; VI-NEXT: v_mov_b32_e32 v15, s20 +; VI-NEXT: v_mov_b32_e32 v16, s19 +; VI-NEXT: v_mov_b32_e32 v17, s18 +; VI-NEXT: v_mov_b32_e32 v18, s17 +; VI-NEXT: v_mov_b32_e32 v19, s16 ; VI-NEXT: v_mov_b32_e32 v20, s15 ; VI-NEXT: v_mov_b32_e32 v21, s14 ; VI-NEXT: v_mov_b32_e32 v22, s13 @@ -34110,9 +33675,9 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; VI-NEXT: ; implicit-def: $sgpr59 ; VI-NEXT: ; implicit-def: $sgpr58 ; VI-NEXT: ; implicit-def: $sgpr57 -; VI-NEXT: ; implicit-def: $sgpr56 -; VI-NEXT: ; implicit-def: $sgpr47 -; VI-NEXT: ; implicit-def: $sgpr46 +; VI-NEXT: ; implicit-def: $sgpr29 +; VI-NEXT: ; implicit-def: $sgpr28 +; VI-NEXT: ; implicit-def: $sgpr27 ; VI-NEXT: s_branch .LBB45_2 ; ; GFX9-LABEL: bitcast_v15i64_to_v60f16_scalar: @@ -34121,20 +33686,48 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] +; GFX9-NEXT: v_mov_b32_e32 v17, s16 +; GFX9-NEXT: v_mov_b32_e32 v18, s17 +; GFX9-NEXT: v_mov_b32_e32 v19, s18 +; GFX9-NEXT: v_readfirstlane_b32 s6, v17 +; GFX9-NEXT: v_mov_b32_e32 v17, s19 +; GFX9-NEXT: v_readfirstlane_b32 s7, v18 +; GFX9-NEXT: v_mov_b32_e32 v18, s20 +; GFX9-NEXT: v_readfirstlane_b32 s8, v19 +; GFX9-NEXT: v_mov_b32_e32 v19, s21 +; GFX9-NEXT: v_readfirstlane_b32 s9, v17 +; GFX9-NEXT: v_mov_b32_e32 v17, s22 +; GFX9-NEXT: v_readfirstlane_b32 s10, v18 +; GFX9-NEXT: v_mov_b32_e32 v18, s23 ; GFX9-NEXT: v_writelane_b32 v30, s30, 0 +; GFX9-NEXT: v_readfirstlane_b32 s11, v19 +; GFX9-NEXT: v_mov_b32_e32 v19, s24 +; GFX9-NEXT: v_readfirstlane_b32 s12, v17 +; GFX9-NEXT: v_mov_b32_e32 v17, s25 +; GFX9-NEXT: v_readfirstlane_b32 s13, v18 +; GFX9-NEXT: v_mov_b32_e32 v18, s26 ; GFX9-NEXT: v_writelane_b32 v30, s31, 1 +; GFX9-NEXT: v_readfirstlane_b32 s14, v19 +; GFX9-NEXT: v_mov_b32_e32 v19, s27 +; GFX9-NEXT: v_readfirstlane_b32 s15, v17 +; GFX9-NEXT: v_mov_b32_e32 v17, s28 +; GFX9-NEXT: v_readfirstlane_b32 s16, v18 +; GFX9-NEXT: v_mov_b32_e32 v18, s29 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16 ; GFX9-NEXT: v_writelane_b32 v30, s34, 2 -; GFX9-NEXT: v_readfirstlane_b32 s6, v0 -; GFX9-NEXT: v_readfirstlane_b32 s7, v1 -; GFX9-NEXT: v_readfirstlane_b32 s8, v2 -; GFX9-NEXT: v_readfirstlane_b32 s9, v3 -; GFX9-NEXT: v_readfirstlane_b32 s10, v4 -; GFX9-NEXT: v_readfirstlane_b32 s11, v5 -; GFX9-NEXT: v_readfirstlane_b32 s12, v6 -; GFX9-NEXT: v_readfirstlane_b32 s13, v7 -; GFX9-NEXT: v_readfirstlane_b32 s14, v8 -; GFX9-NEXT: v_readfirstlane_b32 s15, v9 +; GFX9-NEXT: v_readfirstlane_b32 s17, v19 +; GFX9-NEXT: v_readfirstlane_b32 s18, v17 +; GFX9-NEXT: v_readfirstlane_b32 s19, v18 +; GFX9-NEXT: v_readfirstlane_b32 s20, v0 +; GFX9-NEXT: v_readfirstlane_b32 s21, v1 +; GFX9-NEXT: v_readfirstlane_b32 s22, v2 +; GFX9-NEXT: v_readfirstlane_b32 s23, v3 +; GFX9-NEXT: v_readfirstlane_b32 s24, v4 +; GFX9-NEXT: v_readfirstlane_b32 s25, v5 +; GFX9-NEXT: v_readfirstlane_b32 s26, v6 +; GFX9-NEXT: v_readfirstlane_b32 s27, v7 +; GFX9-NEXT: v_readfirstlane_b32 s28, v8 +; GFX9-NEXT: v_readfirstlane_b32 s29, v9 ; GFX9-NEXT: v_readfirstlane_b32 s40, v10 ; GFX9-NEXT: v_readfirstlane_b32 s41, v11 ; GFX9-NEXT: v_readfirstlane_b32 s42, v12 @@ -34151,30 +33744,30 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; GFX9-NEXT: s_lshr_b32 s57, s42, 16 ; GFX9-NEXT: s_lshr_b32 s58, s41, 16 ; GFX9-NEXT: s_lshr_b32 s59, s40, 16 -; GFX9-NEXT: s_lshr_b32 s60, s15, 16 -; GFX9-NEXT: s_lshr_b32 s61, s14, 16 -; GFX9-NEXT: s_lshr_b32 s62, s13, 16 -; GFX9-NEXT: s_lshr_b32 s63, s12, 16 -; GFX9-NEXT: s_lshr_b32 s72, s11, 16 -; GFX9-NEXT: s_lshr_b32 s73, s10, 16 -; GFX9-NEXT: s_lshr_b32 s74, s9, 16 -; GFX9-NEXT: s_lshr_b32 s75, s8, 16 -; GFX9-NEXT: s_lshr_b32 s76, s7, 16 -; GFX9-NEXT: s_lshr_b32 s77, s6, 16 -; GFX9-NEXT: s_lshr_b32 s78, s29, 16 -; GFX9-NEXT: s_lshr_b32 s79, s28, 16 -; GFX9-NEXT: s_lshr_b32 s88, s27, 16 -; GFX9-NEXT: s_lshr_b32 s89, s26, 16 -; GFX9-NEXT: s_lshr_b32 s90, s25, 16 -; GFX9-NEXT: s_lshr_b32 s91, s24, 16 -; GFX9-NEXT: s_lshr_b32 s92, s23, 16 -; GFX9-NEXT: s_lshr_b32 s93, s22, 16 -; GFX9-NEXT: s_lshr_b32 s94, s21, 16 -; GFX9-NEXT: s_lshr_b32 s95, s20, 16 -; GFX9-NEXT: s_lshr_b32 s30, s19, 16 -; GFX9-NEXT: s_lshr_b32 s31, s18, 16 -; GFX9-NEXT: s_lshr_b32 s34, s17, 16 -; GFX9-NEXT: s_lshr_b32 s35, s16, 16 +; GFX9-NEXT: s_lshr_b32 s60, s29, 16 +; GFX9-NEXT: s_lshr_b32 s61, s28, 16 +; GFX9-NEXT: s_lshr_b32 s62, s27, 16 +; GFX9-NEXT: s_lshr_b32 s63, s26, 16 +; GFX9-NEXT: s_lshr_b32 s72, s25, 16 +; GFX9-NEXT: s_lshr_b32 s73, s24, 16 +; GFX9-NEXT: s_lshr_b32 s74, s23, 16 +; GFX9-NEXT: s_lshr_b32 s75, s22, 16 +; GFX9-NEXT: s_lshr_b32 s76, s21, 16 +; GFX9-NEXT: s_lshr_b32 s77, s20, 16 +; GFX9-NEXT: s_lshr_b32 s78, s19, 16 +; GFX9-NEXT: s_lshr_b32 s79, s18, 16 +; GFX9-NEXT: s_lshr_b32 s88, s17, 16 +; GFX9-NEXT: s_lshr_b32 s89, s16, 16 +; GFX9-NEXT: s_lshr_b32 s90, s15, 16 +; GFX9-NEXT: s_lshr_b32 s91, s14, 16 +; GFX9-NEXT: s_lshr_b32 s92, s13, 16 +; GFX9-NEXT: s_lshr_b32 s93, s12, 16 +; GFX9-NEXT: s_lshr_b32 s94, s11, 16 +; GFX9-NEXT: s_lshr_b32 s95, s10, 16 +; GFX9-NEXT: s_lshr_b32 s30, s9, 16 +; GFX9-NEXT: s_lshr_b32 s31, s8, 16 +; GFX9-NEXT: s_lshr_b32 s34, s7, 16 +; GFX9-NEXT: s_lshr_b32 s35, s6, 16 ; GFX9-NEXT: s_cbranch_execnz .LBB45_3 ; GFX9-NEXT: .LBB45_2: ; %cmp.true ; GFX9-NEXT: s_add_u32 s44, s44, 3 @@ -34183,16 +33776,6 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; GFX9-NEXT: s_addc_u32 s43, s43, 0 ; GFX9-NEXT: s_add_u32 s40, s40, 3 ; GFX9-NEXT: s_addc_u32 s41, s41, 0 -; GFX9-NEXT: s_add_u32 s14, s14, 3 -; GFX9-NEXT: s_addc_u32 s15, s15, 0 -; GFX9-NEXT: s_add_u32 s12, s12, 3 -; GFX9-NEXT: s_addc_u32 s13, s13, 0 -; GFX9-NEXT: s_add_u32 s10, s10, 3 -; GFX9-NEXT: s_addc_u32 s11, s11, 0 -; GFX9-NEXT: s_add_u32 s8, s8, 3 -; GFX9-NEXT: s_addc_u32 s9, s9, 0 -; GFX9-NEXT: s_add_u32 s6, s6, 3 -; GFX9-NEXT: s_addc_u32 s7, s7, 0 ; GFX9-NEXT: s_add_u32 s28, s28, 3 ; GFX9-NEXT: s_addc_u32 s29, s29, 0 ; GFX9-NEXT: s_add_u32 s26, s26, 3 @@ -34207,61 +33790,71 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; GFX9-NEXT: s_addc_u32 s19, s19, 0 ; GFX9-NEXT: s_add_u32 s16, s16, 3 ; GFX9-NEXT: s_addc_u32 s17, s17, 0 +; GFX9-NEXT: s_add_u32 s14, s14, 3 +; GFX9-NEXT: s_addc_u32 s15, s15, 0 +; GFX9-NEXT: s_add_u32 s12, s12, 3 +; GFX9-NEXT: s_addc_u32 s13, s13, 0 +; GFX9-NEXT: s_add_u32 s10, s10, 3 +; GFX9-NEXT: s_addc_u32 s11, s11, 0 +; GFX9-NEXT: s_add_u32 s8, s8, 3 +; GFX9-NEXT: s_addc_u32 s9, s9, 0 +; GFX9-NEXT: s_add_u32 s6, s6, 3 +; GFX9-NEXT: s_addc_u32 s7, s7, 0 ; GFX9-NEXT: s_lshr_b32 s46, s45, 16 ; GFX9-NEXT: s_lshr_b32 s47, s44, 16 ; GFX9-NEXT: s_lshr_b32 s56, s43, 16 ; GFX9-NEXT: s_lshr_b32 s57, s42, 16 ; GFX9-NEXT: s_lshr_b32 s58, s41, 16 ; GFX9-NEXT: s_lshr_b32 s59, s40, 16 -; GFX9-NEXT: s_lshr_b32 s60, s15, 16 -; GFX9-NEXT: s_lshr_b32 s61, s14, 16 -; GFX9-NEXT: s_lshr_b32 s62, s13, 16 -; GFX9-NEXT: s_lshr_b32 s63, s12, 16 -; GFX9-NEXT: s_lshr_b32 s72, s11, 16 -; GFX9-NEXT: s_lshr_b32 s73, s10, 16 -; GFX9-NEXT: s_lshr_b32 s74, s9, 16 -; GFX9-NEXT: s_lshr_b32 s75, s8, 16 -; GFX9-NEXT: s_lshr_b32 s76, s7, 16 -; GFX9-NEXT: s_lshr_b32 s77, s6, 16 -; GFX9-NEXT: s_lshr_b32 s78, s29, 16 -; GFX9-NEXT: s_lshr_b32 s79, s28, 16 -; GFX9-NEXT: s_lshr_b32 s88, s27, 16 -; GFX9-NEXT: s_lshr_b32 s89, s26, 16 -; GFX9-NEXT: s_lshr_b32 s90, s25, 16 -; GFX9-NEXT: s_lshr_b32 s91, s24, 16 -; GFX9-NEXT: s_lshr_b32 s92, s23, 16 -; GFX9-NEXT: s_lshr_b32 s93, s22, 16 -; GFX9-NEXT: s_lshr_b32 s94, s21, 16 -; GFX9-NEXT: s_lshr_b32 s95, s20, 16 -; GFX9-NEXT: s_lshr_b32 s30, s19, 16 -; GFX9-NEXT: s_lshr_b32 s31, s18, 16 -; GFX9-NEXT: s_lshr_b32 s34, s17, 16 -; GFX9-NEXT: s_lshr_b32 s35, s16, 16 +; GFX9-NEXT: s_lshr_b32 s60, s29, 16 +; GFX9-NEXT: s_lshr_b32 s61, s28, 16 +; GFX9-NEXT: s_lshr_b32 s62, s27, 16 +; GFX9-NEXT: s_lshr_b32 s63, s26, 16 +; GFX9-NEXT: s_lshr_b32 s72, s25, 16 +; GFX9-NEXT: s_lshr_b32 s73, s24, 16 +; GFX9-NEXT: s_lshr_b32 s74, s23, 16 +; GFX9-NEXT: s_lshr_b32 s75, s22, 16 +; GFX9-NEXT: s_lshr_b32 s76, s21, 16 +; GFX9-NEXT: s_lshr_b32 s77, s20, 16 +; GFX9-NEXT: s_lshr_b32 s78, s19, 16 +; GFX9-NEXT: s_lshr_b32 s79, s18, 16 +; GFX9-NEXT: s_lshr_b32 s88, s17, 16 +; GFX9-NEXT: s_lshr_b32 s89, s16, 16 +; GFX9-NEXT: s_lshr_b32 s90, s15, 16 +; GFX9-NEXT: s_lshr_b32 s91, s14, 16 +; GFX9-NEXT: s_lshr_b32 s92, s13, 16 +; GFX9-NEXT: s_lshr_b32 s93, s12, 16 +; GFX9-NEXT: s_lshr_b32 s94, s11, 16 +; GFX9-NEXT: s_lshr_b32 s95, s10, 16 +; GFX9-NEXT: s_lshr_b32 s30, s9, 16 +; GFX9-NEXT: s_lshr_b32 s31, s8, 16 +; GFX9-NEXT: s_lshr_b32 s34, s7, 16 +; GFX9-NEXT: s_lshr_b32 s35, s6, 16 ; GFX9-NEXT: .LBB45_3: ; %end -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s16, s35 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s17, s34 -; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s31 -; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s30 -; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s95 -; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s94 -; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s93 -; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s92 -; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s91 -; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s90 -; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s89 -; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s88 -; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s79 -; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s78 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s77 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s76 -; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s75 -; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s74 -; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s73 -; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s72 -; GFX9-NEXT: s_pack_ll_b32_b16 s12, s12, s63 -; GFX9-NEXT: s_pack_ll_b32_b16 s13, s13, s62 -; GFX9-NEXT: s_pack_ll_b32_b16 s14, s14, s61 -; GFX9-NEXT: s_pack_ll_b32_b16 s15, s15, s60 +; GFX9-NEXT: s_pack_ll_b32_b16 s4, s6, s35 +; GFX9-NEXT: s_pack_ll_b32_b16 s5, s7, s34 +; GFX9-NEXT: s_pack_ll_b32_b16 s6, s8, s31 +; GFX9-NEXT: s_pack_ll_b32_b16 s7, s9, s30 +; GFX9-NEXT: s_pack_ll_b32_b16 s8, s10, s95 +; GFX9-NEXT: s_pack_ll_b32_b16 s9, s11, s94 +; GFX9-NEXT: s_pack_ll_b32_b16 s10, s12, s93 +; GFX9-NEXT: s_pack_ll_b32_b16 s11, s13, s92 +; GFX9-NEXT: s_pack_ll_b32_b16 s12, s14, s91 +; GFX9-NEXT: s_pack_ll_b32_b16 s13, s15, s90 +; GFX9-NEXT: s_pack_ll_b32_b16 s14, s16, s89 +; GFX9-NEXT: s_pack_ll_b32_b16 s15, s17, s88 +; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s79 +; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s78 +; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s77 +; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s76 +; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s75 +; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s74 +; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s73 +; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s72 +; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s63 +; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s62 +; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s61 +; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s60 ; GFX9-NEXT: s_pack_ll_b32_b16 s28, s40, s59 ; GFX9-NEXT: s_pack_ll_b32_b16 s29, s41, s58 ; GFX9-NEXT: s_pack_ll_b32_b16 s40, s42, s57 @@ -34270,28 +33863,28 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; GFX9-NEXT: s_pack_ll_b32_b16 s43, s45, s46 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 -; GFX9-NEXT: v_mov_b32_e32 v2, s16 -; GFX9-NEXT: v_mov_b32_e32 v3, s17 -; GFX9-NEXT: v_mov_b32_e32 v4, s18 -; GFX9-NEXT: v_mov_b32_e32 v5, s19 -; GFX9-NEXT: v_mov_b32_e32 v6, s20 -; GFX9-NEXT: v_mov_b32_e32 v7, s21 -; GFX9-NEXT: v_mov_b32_e32 v8, s22 -; GFX9-NEXT: v_mov_b32_e32 v9, s23 -; GFX9-NEXT: v_mov_b32_e32 v10, s24 -; GFX9-NEXT: v_mov_b32_e32 v11, s25 -; GFX9-NEXT: v_mov_b32_e32 v12, s26 -; GFX9-NEXT: v_mov_b32_e32 v13, s27 -; GFX9-NEXT: v_mov_b32_e32 v14, s6 -; GFX9-NEXT: v_mov_b32_e32 v15, s7 -; GFX9-NEXT: v_mov_b32_e32 v16, s8 -; GFX9-NEXT: v_mov_b32_e32 v17, s9 -; GFX9-NEXT: v_mov_b32_e32 v18, s10 -; GFX9-NEXT: v_mov_b32_e32 v19, s11 -; GFX9-NEXT: v_mov_b32_e32 v20, s12 -; GFX9-NEXT: v_mov_b32_e32 v21, s13 -; GFX9-NEXT: v_mov_b32_e32 v22, s14 -; GFX9-NEXT: v_mov_b32_e32 v23, s15 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: v_mov_b32_e32 v4, s8 +; GFX9-NEXT: v_mov_b32_e32 v5, s9 +; GFX9-NEXT: v_mov_b32_e32 v6, s10 +; GFX9-NEXT: v_mov_b32_e32 v7, s11 +; GFX9-NEXT: v_mov_b32_e32 v8, s12 +; GFX9-NEXT: v_mov_b32_e32 v9, s13 +; GFX9-NEXT: v_mov_b32_e32 v10, s14 +; GFX9-NEXT: v_mov_b32_e32 v11, s15 +; GFX9-NEXT: v_mov_b32_e32 v12, s16 +; GFX9-NEXT: v_mov_b32_e32 v13, s17 +; GFX9-NEXT: v_mov_b32_e32 v14, s18 +; GFX9-NEXT: v_mov_b32_e32 v15, s19 +; GFX9-NEXT: v_mov_b32_e32 v16, s20 +; GFX9-NEXT: v_mov_b32_e32 v17, s21 +; GFX9-NEXT: v_mov_b32_e32 v18, s22 +; GFX9-NEXT: v_mov_b32_e32 v19, s23 +; GFX9-NEXT: v_mov_b32_e32 v20, s24 +; GFX9-NEXT: v_mov_b32_e32 v21, s25 +; GFX9-NEXT: v_mov_b32_e32 v22, s26 +; GFX9-NEXT: v_mov_b32_e32 v23, s27 ; GFX9-NEXT: v_mov_b32_e32 v24, s28 ; GFX9-NEXT: v_mov_b32_e32 v25, s29 ; GFX9-NEXT: v_mov_b32_e32 v26, s40 @@ -34343,49 +33936,76 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; GFX11-LABEL: bitcast_v15i64_to_v60f16_scalar: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v13, s0 :: v_dual_mov_b32 v14, s1 +; GFX11-NEXT: v_dual_mov_b32 v15, s2 :: v_dual_mov_b32 v16, s3 +; GFX11-NEXT: v_dual_mov_b32 v17, s16 :: v_dual_mov_b32 v18, s17 +; GFX11-NEXT: v_dual_mov_b32 v19, s18 :: v_dual_mov_b32 v20, s19 +; GFX11-NEXT: v_dual_mov_b32 v21, s20 :: v_dual_mov_b32 v22, s21 +; GFX11-NEXT: v_dual_mov_b32 v23, s22 :: v_dual_mov_b32 v24, s23 +; GFX11-NEXT: v_dual_mov_b32 v25, s24 :: v_dual_mov_b32 v26, s25 +; GFX11-NEXT: v_dual_mov_b32 v27, s26 :: v_dual_mov_b32 v28, s27 +; GFX11-NEXT: v_dual_mov_b32 v29, s28 :: v_dual_mov_b32 v30, s29 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 -; GFX11-NEXT: v_readfirstlane_b32 s4, v0 -; GFX11-NEXT: v_readfirstlane_b32 s5, v1 -; GFX11-NEXT: v_readfirstlane_b32 s6, v2 -; GFX11-NEXT: v_readfirstlane_b32 s7, v3 -; GFX11-NEXT: v_readfirstlane_b32 s8, v4 -; GFX11-NEXT: v_readfirstlane_b32 s9, v5 -; GFX11-NEXT: v_readfirstlane_b32 s10, v6 -; GFX11-NEXT: v_readfirstlane_b32 s11, v7 -; GFX11-NEXT: v_readfirstlane_b32 s12, v8 -; GFX11-NEXT: v_readfirstlane_b32 s13, v9 -; GFX11-NEXT: v_readfirstlane_b32 s15, v10 -; GFX11-NEXT: v_readfirstlane_b32 s14, v11 +; GFX11-NEXT: v_readfirstlane_b32 s0, v13 +; GFX11-NEXT: v_readfirstlane_b32 s1, v14 +; GFX11-NEXT: v_readfirstlane_b32 s2, v15 +; GFX11-NEXT: v_readfirstlane_b32 s3, v16 +; GFX11-NEXT: v_readfirstlane_b32 s4, v17 +; GFX11-NEXT: v_readfirstlane_b32 s5, v18 +; GFX11-NEXT: v_readfirstlane_b32 s6, v19 +; GFX11-NEXT: v_readfirstlane_b32 s7, v20 +; GFX11-NEXT: v_readfirstlane_b32 s8, v21 +; GFX11-NEXT: v_readfirstlane_b32 s9, v22 +; GFX11-NEXT: v_readfirstlane_b32 s10, v23 +; GFX11-NEXT: v_readfirstlane_b32 s11, v24 +; GFX11-NEXT: v_readfirstlane_b32 s12, v25 +; GFX11-NEXT: v_readfirstlane_b32 s13, v26 +; GFX11-NEXT: v_readfirstlane_b32 s14, v27 +; GFX11-NEXT: v_readfirstlane_b32 s15, v28 +; GFX11-NEXT: v_readfirstlane_b32 s16, v29 +; GFX11-NEXT: v_readfirstlane_b32 s17, v30 +; GFX11-NEXT: v_readfirstlane_b32 s18, v0 +; GFX11-NEXT: v_readfirstlane_b32 s19, v1 +; GFX11-NEXT: v_readfirstlane_b32 s20, v2 +; GFX11-NEXT: v_readfirstlane_b32 s21, v3 +; GFX11-NEXT: v_readfirstlane_b32 s22, v4 +; GFX11-NEXT: v_readfirstlane_b32 s23, v5 +; GFX11-NEXT: v_readfirstlane_b32 s24, v6 +; GFX11-NEXT: v_readfirstlane_b32 s25, v7 +; GFX11-NEXT: v_readfirstlane_b32 s26, v8 +; GFX11-NEXT: v_readfirstlane_b32 s27, v9 +; GFX11-NEXT: v_readfirstlane_b32 s29, v10 +; GFX11-NEXT: v_readfirstlane_b32 s28, v11 ; GFX11-NEXT: s_mov_b32 s94, 0 ; GFX11-NEXT: s_and_b32 s40, vcc_lo, exec_lo ; GFX11-NEXT: s_cbranch_scc0 .LBB45_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: s_lshr_b32 s40, s14, 16 -; GFX11-NEXT: s_lshr_b32 s41, s15, 16 -; GFX11-NEXT: s_lshr_b32 s42, s13, 16 -; GFX11-NEXT: s_lshr_b32 s43, s12, 16 -; GFX11-NEXT: s_lshr_b32 s44, s11, 16 -; GFX11-NEXT: s_lshr_b32 s45, s10, 16 -; GFX11-NEXT: s_lshr_b32 s46, s9, 16 -; GFX11-NEXT: s_lshr_b32 s47, s8, 16 -; GFX11-NEXT: s_lshr_b32 s56, s7, 16 -; GFX11-NEXT: s_lshr_b32 s57, s6, 16 -; GFX11-NEXT: s_lshr_b32 s58, s5, 16 -; GFX11-NEXT: s_lshr_b32 s59, s4, 16 -; GFX11-NEXT: s_lshr_b32 s60, s29, 16 -; GFX11-NEXT: s_lshr_b32 s61, s28, 16 -; GFX11-NEXT: s_lshr_b32 s62, s27, 16 -; GFX11-NEXT: s_lshr_b32 s63, s26, 16 -; GFX11-NEXT: s_lshr_b32 s72, s25, 16 -; GFX11-NEXT: s_lshr_b32 s73, s24, 16 -; GFX11-NEXT: s_lshr_b32 s74, s23, 16 -; GFX11-NEXT: s_lshr_b32 s75, s22, 16 -; GFX11-NEXT: s_lshr_b32 s76, s21, 16 -; GFX11-NEXT: s_lshr_b32 s77, s20, 16 -; GFX11-NEXT: s_lshr_b32 s78, s19, 16 -; GFX11-NEXT: s_lshr_b32 s79, s18, 16 -; GFX11-NEXT: s_lshr_b32 s88, s17, 16 -; GFX11-NEXT: s_lshr_b32 s89, s16, 16 +; GFX11-NEXT: s_lshr_b32 s40, s28, 16 +; GFX11-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-NEXT: s_lshr_b32 s42, s27, 16 +; GFX11-NEXT: s_lshr_b32 s43, s26, 16 +; GFX11-NEXT: s_lshr_b32 s44, s25, 16 +; GFX11-NEXT: s_lshr_b32 s45, s24, 16 +; GFX11-NEXT: s_lshr_b32 s46, s23, 16 +; GFX11-NEXT: s_lshr_b32 s47, s22, 16 +; GFX11-NEXT: s_lshr_b32 s56, s21, 16 +; GFX11-NEXT: s_lshr_b32 s57, s20, 16 +; GFX11-NEXT: s_lshr_b32 s58, s19, 16 +; GFX11-NEXT: s_lshr_b32 s59, s18, 16 +; GFX11-NEXT: s_lshr_b32 s60, s17, 16 +; GFX11-NEXT: s_lshr_b32 s61, s16, 16 +; GFX11-NEXT: s_lshr_b32 s62, s15, 16 +; GFX11-NEXT: s_lshr_b32 s63, s14, 16 +; GFX11-NEXT: s_lshr_b32 s72, s13, 16 +; GFX11-NEXT: s_lshr_b32 s73, s12, 16 +; GFX11-NEXT: s_lshr_b32 s74, s11, 16 +; GFX11-NEXT: s_lshr_b32 s75, s10, 16 +; GFX11-NEXT: s_lshr_b32 s76, s9, 16 +; GFX11-NEXT: s_lshr_b32 s77, s8, 16 +; GFX11-NEXT: s_lshr_b32 s78, s7, 16 +; GFX11-NEXT: s_lshr_b32 s79, s6, 16 +; GFX11-NEXT: s_lshr_b32 s88, s5, 16 +; GFX11-NEXT: s_lshr_b32 s89, s4, 16 ; GFX11-NEXT: s_lshr_b32 s90, s3, 16 ; GFX11-NEXT: s_lshr_b32 s91, s2, 16 ; GFX11-NEXT: s_lshr_b32 s92, s1, 16 @@ -34393,20 +34013,8 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s94 ; GFX11-NEXT: s_cbranch_vccnz .LBB45_3 ; GFX11-NEXT: .LBB45_2: ; %cmp.true -; GFX11-NEXT: s_add_u32 s15, s15, 3 -; GFX11-NEXT: s_addc_u32 s14, s14, 0 -; GFX11-NEXT: s_add_u32 s12, s12, 3 -; GFX11-NEXT: s_addc_u32 s13, s13, 0 -; GFX11-NEXT: s_add_u32 s10, s10, 3 -; GFX11-NEXT: s_addc_u32 s11, s11, 0 -; GFX11-NEXT: s_add_u32 s8, s8, 3 -; GFX11-NEXT: s_addc_u32 s9, s9, 0 -; GFX11-NEXT: s_add_u32 s6, s6, 3 -; GFX11-NEXT: s_addc_u32 s7, s7, 0 -; GFX11-NEXT: s_add_u32 s4, s4, 3 -; GFX11-NEXT: s_addc_u32 s5, s5, 0 -; GFX11-NEXT: s_add_u32 s28, s28, 3 -; GFX11-NEXT: s_addc_u32 s29, s29, 0 +; GFX11-NEXT: s_add_u32 s29, s29, 3 +; GFX11-NEXT: s_addc_u32 s28, s28, 0 ; GFX11-NEXT: s_add_u32 s26, s26, 3 ; GFX11-NEXT: s_addc_u32 s27, s27, 0 ; GFX11-NEXT: s_add_u32 s24, s24, 3 @@ -34419,36 +34027,48 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; GFX11-NEXT: s_addc_u32 s19, s19, 0 ; GFX11-NEXT: s_add_u32 s16, s16, 3 ; GFX11-NEXT: s_addc_u32 s17, s17, 0 +; GFX11-NEXT: s_add_u32 s14, s14, 3 +; GFX11-NEXT: s_addc_u32 s15, s15, 0 +; GFX11-NEXT: s_add_u32 s12, s12, 3 +; GFX11-NEXT: s_addc_u32 s13, s13, 0 +; GFX11-NEXT: s_add_u32 s10, s10, 3 +; GFX11-NEXT: s_addc_u32 s11, s11, 0 +; GFX11-NEXT: s_add_u32 s8, s8, 3 +; GFX11-NEXT: s_addc_u32 s9, s9, 0 +; GFX11-NEXT: s_add_u32 s6, s6, 3 +; GFX11-NEXT: s_addc_u32 s7, s7, 0 +; GFX11-NEXT: s_add_u32 s4, s4, 3 +; GFX11-NEXT: s_addc_u32 s5, s5, 0 ; GFX11-NEXT: s_add_u32 s2, s2, 3 ; GFX11-NEXT: s_addc_u32 s3, s3, 0 ; GFX11-NEXT: s_add_u32 s0, s0, 3 ; GFX11-NEXT: s_addc_u32 s1, s1, 0 -; GFX11-NEXT: s_lshr_b32 s40, s14, 16 -; GFX11-NEXT: s_lshr_b32 s41, s15, 16 -; GFX11-NEXT: s_lshr_b32 s42, s13, 16 -; GFX11-NEXT: s_lshr_b32 s43, s12, 16 -; GFX11-NEXT: s_lshr_b32 s44, s11, 16 -; GFX11-NEXT: s_lshr_b32 s45, s10, 16 -; GFX11-NEXT: s_lshr_b32 s46, s9, 16 -; GFX11-NEXT: s_lshr_b32 s47, s8, 16 -; GFX11-NEXT: s_lshr_b32 s56, s7, 16 -; GFX11-NEXT: s_lshr_b32 s57, s6, 16 -; GFX11-NEXT: s_lshr_b32 s58, s5, 16 -; GFX11-NEXT: s_lshr_b32 s59, s4, 16 -; GFX11-NEXT: s_lshr_b32 s60, s29, 16 -; GFX11-NEXT: s_lshr_b32 s61, s28, 16 -; GFX11-NEXT: s_lshr_b32 s62, s27, 16 -; GFX11-NEXT: s_lshr_b32 s63, s26, 16 -; GFX11-NEXT: s_lshr_b32 s72, s25, 16 -; GFX11-NEXT: s_lshr_b32 s73, s24, 16 -; GFX11-NEXT: s_lshr_b32 s74, s23, 16 -; GFX11-NEXT: s_lshr_b32 s75, s22, 16 -; GFX11-NEXT: s_lshr_b32 s76, s21, 16 -; GFX11-NEXT: s_lshr_b32 s77, s20, 16 -; GFX11-NEXT: s_lshr_b32 s78, s19, 16 -; GFX11-NEXT: s_lshr_b32 s79, s18, 16 -; GFX11-NEXT: s_lshr_b32 s88, s17, 16 -; GFX11-NEXT: s_lshr_b32 s89, s16, 16 +; GFX11-NEXT: s_lshr_b32 s40, s28, 16 +; GFX11-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-NEXT: s_lshr_b32 s42, s27, 16 +; GFX11-NEXT: s_lshr_b32 s43, s26, 16 +; GFX11-NEXT: s_lshr_b32 s44, s25, 16 +; GFX11-NEXT: s_lshr_b32 s45, s24, 16 +; GFX11-NEXT: s_lshr_b32 s46, s23, 16 +; GFX11-NEXT: s_lshr_b32 s47, s22, 16 +; GFX11-NEXT: s_lshr_b32 s56, s21, 16 +; GFX11-NEXT: s_lshr_b32 s57, s20, 16 +; GFX11-NEXT: s_lshr_b32 s58, s19, 16 +; GFX11-NEXT: s_lshr_b32 s59, s18, 16 +; GFX11-NEXT: s_lshr_b32 s60, s17, 16 +; GFX11-NEXT: s_lshr_b32 s61, s16, 16 +; GFX11-NEXT: s_lshr_b32 s62, s15, 16 +; GFX11-NEXT: s_lshr_b32 s63, s14, 16 +; GFX11-NEXT: s_lshr_b32 s72, s13, 16 +; GFX11-NEXT: s_lshr_b32 s73, s12, 16 +; GFX11-NEXT: s_lshr_b32 s74, s11, 16 +; GFX11-NEXT: s_lshr_b32 s75, s10, 16 +; GFX11-NEXT: s_lshr_b32 s76, s9, 16 +; GFX11-NEXT: s_lshr_b32 s77, s8, 16 +; GFX11-NEXT: s_lshr_b32 s78, s7, 16 +; GFX11-NEXT: s_lshr_b32 s79, s6, 16 +; GFX11-NEXT: s_lshr_b32 s88, s5, 16 +; GFX11-NEXT: s_lshr_b32 s89, s4, 16 ; GFX11-NEXT: s_lshr_b32 s90, s3, 16 ; GFX11-NEXT: s_lshr_b32 s91, s2, 16 ; GFX11-NEXT: s_lshr_b32 s92, s1, 16 @@ -34459,47 +34079,47 @@ define inreg <60 x half> @bitcast_v15i64_to_v60f16_scalar(<15 x i64> inreg %a, i ; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s92 ; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s91 ; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s90 -; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s89 -; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s88 -; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s79 -; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s78 -; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s77 -; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s76 -; GFX11-NEXT: s_pack_ll_b32_b16 s22, s22, s75 -; GFX11-NEXT: s_pack_ll_b32_b16 s23, s23, s74 -; GFX11-NEXT: s_pack_ll_b32_b16 s24, s24, s73 -; GFX11-NEXT: s_pack_ll_b32_b16 s25, s25, s72 -; GFX11-NEXT: s_pack_ll_b32_b16 s26, s26, s63 -; GFX11-NEXT: s_pack_ll_b32_b16 s27, s27, s62 -; GFX11-NEXT: s_pack_ll_b32_b16 s28, s28, s61 -; GFX11-NEXT: s_pack_ll_b32_b16 s29, s29, s60 -; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s59 -; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s58 -; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s57 -; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s56 -; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s47 -; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s46 -; GFX11-NEXT: s_pack_ll_b32_b16 s10, s10, s45 -; GFX11-NEXT: s_pack_ll_b32_b16 s11, s11, s44 -; GFX11-NEXT: s_pack_ll_b32_b16 s12, s12, s43 -; GFX11-NEXT: s_pack_ll_b32_b16 s13, s13, s42 -; GFX11-NEXT: s_pack_ll_b32_b16 s15, s15, s41 -; GFX11-NEXT: s_pack_ll_b32_b16 s14, s14, s40 +; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s89 +; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s88 +; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s79 +; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s78 +; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s77 +; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s76 +; GFX11-NEXT: s_pack_ll_b32_b16 s10, s10, s75 +; GFX11-NEXT: s_pack_ll_b32_b16 s11, s11, s74 +; GFX11-NEXT: s_pack_ll_b32_b16 s12, s12, s73 +; GFX11-NEXT: s_pack_ll_b32_b16 s13, s13, s72 +; GFX11-NEXT: s_pack_ll_b32_b16 s14, s14, s63 +; GFX11-NEXT: s_pack_ll_b32_b16 s15, s15, s62 +; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s61 +; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s60 +; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s59 +; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s58 +; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s57 +; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s56 +; GFX11-NEXT: s_pack_ll_b32_b16 s22, s22, s47 +; GFX11-NEXT: s_pack_ll_b32_b16 s23, s23, s46 +; GFX11-NEXT: s_pack_ll_b32_b16 s24, s24, s45 +; GFX11-NEXT: s_pack_ll_b32_b16 s25, s25, s44 +; GFX11-NEXT: s_pack_ll_b32_b16 s26, s26, s43 +; GFX11-NEXT: s_pack_ll_b32_b16 s27, s27, s42 +; GFX11-NEXT: s_pack_ll_b32_b16 s29, s29, s41 +; GFX11-NEXT: s_pack_ll_b32_b16 s28, s28, s40 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 -; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 -; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 -; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 -; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 -; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 -; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 -; GFX11-NEXT: v_dual_mov_b32 v18, s4 :: v_dual_mov_b32 v19, s5 -; GFX11-NEXT: v_dual_mov_b32 v20, s6 :: v_dual_mov_b32 v21, s7 -; GFX11-NEXT: v_dual_mov_b32 v22, s8 :: v_dual_mov_b32 v23, s9 -; GFX11-NEXT: v_dual_mov_b32 v24, s10 :: v_dual_mov_b32 v25, s11 -; GFX11-NEXT: v_dual_mov_b32 v26, s12 :: v_dual_mov_b32 v27, s13 -; GFX11-NEXT: v_dual_mov_b32 v28, s15 :: v_dual_mov_b32 v29, s14 +; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19 +; GFX11-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v21, s21 +; GFX11-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v23, s23 +; GFX11-NEXT: v_dual_mov_b32 v24, s24 :: v_dual_mov_b32 v25, s25 +; GFX11-NEXT: v_dual_mov_b32 v26, s26 :: v_dual_mov_b32 v27, s27 +; GFX11-NEXT: v_dual_mov_b32 v28, s29 :: v_dual_mov_b32 v29, s28 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: .LBB45_4: ; GFX11-NEXT: ; implicit-def: $sgpr93 @@ -34570,6 +34190,9 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(5) +; SI-NEXT: v_cvt_f16_f32_e32 v58, v0 +; SI-NEXT: v_cvt_f16_f32_e32 v0, v5 ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116 ; SI-NEXT: s_waitcnt expcnt(3) ; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 @@ -34598,23 +34221,12 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:76 ; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:88 ; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:84 -; SI-NEXT: v_cvt_f16_f32_e32 v58, v0 -; SI-NEXT: v_cvt_f16_f32_e32 v0, v5 ; SI-NEXT: v_cvt_f16_f32_e32 v59, v1 ; SI-NEXT: v_cvt_f16_f32_e32 v57, v3 -; SI-NEXT: v_cvt_f16_f32_e32 v56, v2 -; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:96 -; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:92 -; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:104 -; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:100 -; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:112 -; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:108 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v60, v60 +; SI-NEXT: v_cvt_f16_f32_e32 v56, v2 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v7 @@ -34624,8 +34236,6 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v9 -; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_cvt_f16_f32_e32 v52, v52 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v8 @@ -34647,9 +34257,18 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v14 +; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v17 +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:96 +; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:92 +; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:104 +; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:100 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:112 +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:108 +; SI-NEXT: v_cvt_f16_f32_e32 v60, v60 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v16 @@ -34659,6 +34278,7 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v18 +; SI-NEXT: v_cvt_f16_f32_e32 v52, v52 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v21 @@ -34696,7 +34316,6 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) { ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v61 ; SI-NEXT: v_cvt_f16_f32_e32 v61, v49 -; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cvt_f16_f32_e32 v49, v55 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -34711,6 +34330,7 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v32 +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cvt_f16_f32_e32 v32, v47 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -35582,7 +35202,6 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v61, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v29 -; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v28 @@ -35661,6 +35280,7 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) { ; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v60 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v61 +; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -35825,6 +35445,9 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) { ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] ; GFX9-NEXT: s_cbranch_execz .LBB46_4 ; GFX9-NEXT: ; %bb.3: ; %cmp.true +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload @@ -35839,9 +35462,6 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload -; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v38, v61, s6 ; GFX9-NEXT: s_movk_i32 s7, 0x200 ; GFX9-NEXT: v_perm_b32 v1, v37, v60, s6 @@ -35861,6 +35481,10 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) { ; GFX9-NEXT: v_pk_add_f16 v6, v6, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v7, v7, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v8, v8, s7 op_sel_hi:[1,0] +; GFX9-NEXT: s_waitcnt vmcnt(14) +; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; GFX9-NEXT: s_waitcnt vmcnt(15) ; GFX9-NEXT: v_perm_b32 v9, v9, v44, s6 ; GFX9-NEXT: s_waitcnt vmcnt(14) @@ -35889,10 +35513,6 @@ define <15 x i64> @bitcast_v60f16_to_v15i64(<60 x half> %a, i32 %b) { ; GFX9-NEXT: v_perm_b32 v21, v21, v48, s6 ; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: v_perm_b32 v22, v22, v39, s6 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v10, v10, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0] @@ -36213,12 +35833,35 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i ; SI-NEXT: v_cvt_f16_f32_e32 v8, s26 ; SI-NEXT: v_cvt_f16_f32_e32 v6, s29 ; SI-NEXT: v_cvt_f16_f32_e32 v7, s28 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: v_cvt_f16_f32_e32 v50, v54 ; SI-NEXT: v_cvt_f16_f32_e32 v48, v48 ; SI-NEXT: v_cvt_f16_f32_e32 v31, v40 -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v33 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill @@ -36228,7 +35871,7 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v38 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0) +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v44 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -36237,7 +35880,7 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v46 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0) +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v47 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -36246,7 +35889,7 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v57 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0) +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v58 ; SI-NEXT: v_cvt_f16_f32_e32 v58, s16 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill @@ -36257,38 +35900,12 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v60 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB47_2 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(4) ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; SI-NEXT: v_or_b32_e32 v3, v10, v3 -; SI-NEXT: s_waitcnt expcnt(3) ; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34 ; SI-NEXT: v_mov_b32_e32 v33, v32 ; SI-NEXT: v_or_b32_e32 v10, v32, v10 @@ -36313,12 +35930,12 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i ; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18 ; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v59 ; SI-NEXT: v_or_b32_e32 v1, v12, v1 ; SI-NEXT: v_or_b32_e32 v2, v11, v2 @@ -36427,12 +36044,10 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i ; SI-NEXT: v_mov_b32_e32 v40, v44 ; SI-NEXT: s_cbranch_vccnz .LBB47_5 ; SI-NEXT: ; %bb.4: ; %cmp.true -; SI-NEXT: s_waitcnt expcnt(5) ; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(4) ; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; SI-NEXT: v_cvt_f32_f16_e32 v0, v59 ; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v0, v59 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v58 ; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_cvt_f32_f16_e32 v8, v33 @@ -37218,304 +36833,115 @@ define inreg <15 x i64> @bitcast_v60f16_to_v15i64_scalar(<60 x half> inreg %a, i ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v190, v6 :: v_dual_mov_b32 v185, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v186, v3 :: v_dual_mov_b32 v187, v2 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v1 :: v_dual_mov_b32 v189, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB47_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB47_3 ; GFX11-TRUE16-NEXT: .LBB47_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s40 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s41 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v189, 0x200, v189 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v188, 0x200, v188 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v187, 0x200, v187 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v186, 0x200, v186 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v185, 0x200, v185 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v191, 0x200, v191 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v190, 0x200, v190 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, s6 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, s7 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, s8 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s9 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, s10 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, s11 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, s12 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, s13 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s14 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, s15 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, s16 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v30, 0x200, v30 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s0 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s1 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s2 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, s3 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, s4 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v35, 0x200, s5 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v44, 0x200, s6 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v54, 0x200, s7 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v65, 0x200, s8 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v77, 0x200, s9 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v90, 0x200, s10 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v104, 0x200, s11 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v119, 0x200, s12 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v135, 0x200, s13 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v152, 0x200, s14 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v170, 0x200, s15 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: .LBB47_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v170 :: v_dual_mov_b32 v18, v189 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v188 :: v_dual_mov_b32 v20, v187 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v186 :: v_dual_mov_b32 v22, v185 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v191 :: v_dual_mov_b32 v24, v190 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v191, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v190, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v189, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v188, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v187, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:316 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v119 :: v_dual_mov_b32 v27, v30 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB47_4: -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v64, v29 :: v_dual_mov_b32 v65, v28 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v66, v30 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v53, v26 :: v_dual_mov_b32 v54, v25 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v54 :: v_dual_mov_b32 v26, v53 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v65 :: v_dual_mov_b32 v29, v64 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v30, v66 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB47_2 ; ; GFX11-FAKE16-LABEL: bitcast_v60f16_to_v15i64_scalar: @@ -39888,40 +39314,53 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) { ; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:8 ; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:4 ; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v2 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v4 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:52 +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:112 ; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:108 +; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v4 +; SI-NEXT: s_waitcnt vmcnt(4) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:44 ; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v6 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v8 -; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:104 ; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:100 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v10 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v6 +; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v8 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:36 +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:96 ; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:92 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v12 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v10 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:28 +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:88 ; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:84 -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v12 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v14 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:48 @@ -39952,27 +39391,10 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) { ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:56 ; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:64 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:52 -; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v28 -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v30 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:44 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:36 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:28 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v30 ; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc ; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5] @@ -40057,7 +39479,6 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr30 ; SI-NEXT: ; kill: killed $vgpr30 ; SI-NEXT: ; implicit-def: $vgpr30 -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_and_b32_e32 v0, 0xffff, v55 ; SI-NEXT: v_and_b32_e32 v18, 0xffff, v61 ; SI-NEXT: ; kill: killed $vgpr30 @@ -40202,7 +39623,6 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) { ; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v55 ; SI-NEXT: v_add_i32_e32 v18, vcc, 3, v61 ; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0 @@ -40329,7 +39749,7 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) { ; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24 ; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v25 ; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v26 -; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v27 +; SI-NEXT: v_add_i32_e32 v27, vcc, 0x30000, v27 ; SI-NEXT: v_add_i32_e32 v28, vcc, 0x30000, v28 ; SI-NEXT: v_add_i32_e32 v29, vcc, 0x30000, v29 ; SI-NEXT: .LBB50_4: ; %end @@ -40350,7 +39770,7 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) { ; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] ; ; VI-LABEL: bitcast_v60i16_to_v15f64: @@ -40632,7 +40052,6 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v61, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v29 -; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v28 @@ -40711,6 +40130,7 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v60 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v61 +; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -40875,6 +40295,9 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] ; GFX9-NEXT: s_cbranch_execz .LBB50_4 ; GFX9-NEXT: ; %bb.3: ; %cmp.true +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload @@ -40889,9 +40312,6 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload -; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v38, v61, s6 ; GFX9-NEXT: v_perm_b32 v1, v37, v60, s6 ; GFX9-NEXT: v_perm_b32 v2, v62, v59, s6 @@ -40910,6 +40330,10 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] +; GFX9-NEXT: s_waitcnt vmcnt(14) +; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; GFX9-NEXT: s_waitcnt vmcnt(15) ; GFX9-NEXT: v_perm_b32 v9, v9, v44, s6 ; GFX9-NEXT: s_waitcnt vmcnt(14) @@ -40938,10 +40362,6 @@ define <15 x double> @bitcast_v60i16_to_v15f64(<60 x i16> %a, i32 %b) { ; GFX9-NEXT: v_perm_b32 v21, v21, v48, s6 ; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: v_perm_b32 v22, v22, v39, s6 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] @@ -42097,304 +41517,115 @@ define inreg <15 x double> @bitcast_v60i16_to_v15f64_scalar(<60 x i16> inreg %a, ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v190, v6 :: v_dual_mov_b32 v185, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v186, v3 :: v_dual_mov_b32 v187, v2 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v1 :: v_dual_mov_b32 v189, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB51_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB51_3 ; GFX11-TRUE16-NEXT: .LBB51_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s40, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s41, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v189, v189, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v188, v188, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v187, v187, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v186, v186, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v185, v185, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v191, v191, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v190, v190, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, s6, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, s7, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, s8, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s9, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, s10, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, s11, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, s12, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, s13, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s14, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, s15, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, s16, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v30, v30, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s0, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s1, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s2, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, s3, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, s4, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v35, s5, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v44, s6, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v54, s7, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v65, s8, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v77, s9, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v90, s10, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v104, s11, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v119, s12, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v135, s13, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v152, s14, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v170, s15, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: .LBB51_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v170 :: v_dual_mov_b32 v18, v189 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v188 :: v_dual_mov_b32 v20, v187 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v186 :: v_dual_mov_b32 v22, v185 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v191 :: v_dual_mov_b32 v24, v190 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v191, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v190, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v189, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v188, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v187, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:316 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v119 :: v_dual_mov_b32 v27, v30 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB51_4: -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v64, v29 :: v_dual_mov_b32 v65, v28 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v66, v30 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v53, v26 :: v_dual_mov_b32 v54, v25 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v54 :: v_dual_mov_b32 v26, v53 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v65 :: v_dual_mov_b32 v29, v64 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v30, v66 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB51_2 ; ; GFX11-FAKE16-LABEL: bitcast_v60i16_to_v15f64_scalar: @@ -43823,23 +43054,21 @@ define inreg <60 x half> @bitcast_v15f64_to_v60f16_scalar(<15 x double> inreg %a ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17 -; SI-NEXT: v_readfirstlane_b32 s42, v1 -; SI-NEXT: v_readfirstlane_b32 s43, v2 -; SI-NEXT: v_readfirstlane_b32 s40, v3 -; SI-NEXT: v_readfirstlane_b32 s41, v4 -; SI-NEXT: v_readfirstlane_b32 s14, v5 -; SI-NEXT: v_readfirstlane_b32 s15, v6 -; SI-NEXT: v_readfirstlane_b32 s12, v7 -; SI-NEXT: v_readfirstlane_b32 s13, v8 -; SI-NEXT: v_readfirstlane_b32 s10, v9 -; SI-NEXT: v_readfirstlane_b32 s11, v10 -; SI-NEXT: v_readfirstlane_b32 s8, v11 -; SI-NEXT: v_readfirstlane_b32 s9, v12 -; SI-NEXT: v_readfirstlane_b32 s6, v13 -; SI-NEXT: v_readfirstlane_b32 s7, v14 -; SI-NEXT: v_readfirstlane_b32 s4, v15 -; SI-NEXT: s_and_b64 s[44:45], vcc, exec -; SI-NEXT: v_readfirstlane_b32 s5, v16 +; SI-NEXT: v_mov_b32_e32 v23, s16 +; SI-NEXT: v_mov_b32_e32 v24, s17 +; SI-NEXT: v_mov_b32_e32 v29, s18 +; SI-NEXT: v_mov_b32_e32 v30, s19 +; SI-NEXT: v_mov_b32_e32 v27, s20 +; SI-NEXT: v_mov_b32_e32 v28, s21 +; SI-NEXT: v_mov_b32_e32 v25, s22 +; SI-NEXT: v_mov_b32_e32 v26, s23 +; SI-NEXT: v_mov_b32_e32 v21, s24 +; SI-NEXT: v_mov_b32_e32 v22, s25 +; SI-NEXT: v_mov_b32_e32 v19, s26 +; SI-NEXT: v_mov_b32_e32 v20, s27 +; SI-NEXT: s_and_b64 s[4:5], vcc, exec +; SI-NEXT: v_mov_b32_e32 v17, s28 +; SI-NEXT: v_mov_b32_e32 v18, s29 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -43858,438 +43087,565 @@ define inreg <60 x half> @bitcast_v15f64_to_v60f16_scalar(<15 x double> inreg %a ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB53_4 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: s_lshr_b32 s44, s5, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v40, s44 -; SI-NEXT: s_lshr_b32 s44, s4, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v52, s44 -; SI-NEXT: s_lshr_b32 s44, s7, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v48, s44 -; SI-NEXT: s_lshr_b32 s44, s6, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v36, s44 -; SI-NEXT: s_lshr_b32 s44, s9, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v33, s44 -; SI-NEXT: s_lshr_b32 s44, s8, 16 -; SI-NEXT: s_waitcnt expcnt(4) -; SI-NEXT: v_cvt_f32_f16_e32 v59, s44 -; SI-NEXT: s_lshr_b32 s44, s11, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v25, s44 -; SI-NEXT: s_lshr_b32 s44, s10, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v1, s44 -; SI-NEXT: s_lshr_b32 s44, s13, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v18, s44 -; SI-NEXT: s_lshr_b32 s44, s12, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v17, s44 -; SI-NEXT: s_lshr_b32 s44, s15, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v14, s44 -; SI-NEXT: s_lshr_b32 s44, s14, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v22, s44 -; SI-NEXT: s_lshr_b32 s44, s41, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v24, s44 -; SI-NEXT: s_lshr_b32 s44, s40, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v26, s44 -; SI-NEXT: s_lshr_b32 s44, s43, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v28, s44 -; SI-NEXT: s_lshr_b32 s44, s42, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v30, s44 -; SI-NEXT: s_lshr_b32 s44, s29, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v32, s44 -; SI-NEXT: s_lshr_b32 s44, s28, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v34, s44 -; SI-NEXT: s_lshr_b32 s44, s27, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v37, s44 -; SI-NEXT: s_lshr_b32 s44, s26, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v39, s44 -; SI-NEXT: s_lshr_b32 s44, s25, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v49, s44 -; SI-NEXT: s_lshr_b32 s44, s24, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v51, s44 -; SI-NEXT: s_lshr_b32 s44, s23, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v53, s44 -; SI-NEXT: s_lshr_b32 s44, s22, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v55, s44 -; SI-NEXT: s_lshr_b32 s44, s21, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v41, s44 -; SI-NEXT: s_lshr_b32 s44, s20, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v44, s44 -; SI-NEXT: s_lshr_b32 s44, s19, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v46, s44 -; SI-NEXT: s_lshr_b32 s44, s18, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v56, s44 -; SI-NEXT: s_lshr_b32 s44, s17, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v58, s44 -; SI-NEXT: s_lshr_b32 s44, s16, 16 -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_cvt_f32_f16_e32 v60, s44 -; SI-NEXT: v_cvt_f32_f16_e32 v10, s5 -; SI-NEXT: v_cvt_f32_f16_e32 v13, s4 -; SI-NEXT: v_cvt_f32_f16_e32 v19, s7 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s6 -; SI-NEXT: v_cvt_f32_f16_e32 v43, s9 -; SI-NEXT: v_cvt_f32_f16_e32 v45, s8 -; SI-NEXT: v_cvt_f32_f16_e32 v47, s11 -; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_cvt_f32_f16_e32 v61, s10 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_cvt_f32_f16_e32 v62, s13 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v63, s12 -; SI-NEXT: v_cvt_f32_f16_e32 v23, s15 -; SI-NEXT: v_cvt_f32_f16_e32 v4, s14 -; SI-NEXT: v_cvt_f32_f16_e32 v27, s41 -; SI-NEXT: v_cvt_f32_f16_e32 v11, s40 -; SI-NEXT: v_cvt_f32_f16_e32 v31, s43 -; SI-NEXT: v_cvt_f32_f16_e32 v12, s42 -; SI-NEXT: v_cvt_f32_f16_e32 v35, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v3, s28 -; SI-NEXT: v_cvt_f32_f16_e32 v38, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v15, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v50, s25 -; SI-NEXT: v_cvt_f32_f16_e32 v16, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v54, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v7, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v42, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v8, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v20, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v21, s18 -; SI-NEXT: v_cvt_f32_f16_e32 v57, s17 -; SI-NEXT: v_cvt_f32_f16_e32 v2, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v42, v12 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v16 +; SI-NEXT: v_cvt_f32_f16_e32 v40, v31 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v15 +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v42, v11 +; SI-NEXT: v_cvt_f32_f16_e32 v54, v31 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v14 +; SI-NEXT: v_cvt_f32_f16_e32 v52, v31 +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v42, v10 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v13 +; SI-NEXT: v_cvt_f32_f16_e32 v51, v31 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v12 +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v42, v9 +; SI-NEXT: v_cvt_f32_f16_e32 v49, v31 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v11 +; SI-NEXT: v_cvt_f32_f16_e32 v39, v31 +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v42, v8 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v10 +; SI-NEXT: v_cvt_f32_f16_e32 v37, v31 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v9 +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v42, v7 +; SI-NEXT: v_cvt_f32_f16_e32 v35, v31 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v8 +; SI-NEXT: v_cvt_f32_f16_e32 v59, v31 +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v42, v6 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v7 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v31 +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v42, v5 +; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v6 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v31 +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v42, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v15 +; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v5 +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v42, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v31 +; SI-NEXT: v_cvt_f32_f16_e32 v60, v14 +; SI-NEXT: v_cvt_f32_f16_e32 v62, v13 +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v42, v2 +; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v31 +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v42, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v44, v27 +; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v3 +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v42, v18 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v31 +; SI-NEXT: v_cvt_f32_f16_e32 v46, v30 +; SI-NEXT: v_cvt_f32_f16_e32 v47, v29 +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v42, v17 +; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v31 +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v42, v20 +; SI-NEXT: v_cvt_f32_f16_e32 v56, v24 +; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1 +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v42, v19 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v31 +; SI-NEXT: v_cvt_f32_f16_e32 v57, v23 +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v42, v22 +; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v18 +; SI-NEXT: v_cvt_f32_f16_e32 v58, v31 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v17 +; SI-NEXT: v_cvt_f32_f16_e32 v61, v31 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v20 +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v42, v21 +; SI-NEXT: v_cvt_f32_f16_e32 v63, v31 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v19 +; SI-NEXT: v_cvt_f32_f16_e32 v32, v31 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v22 +; SI-NEXT: v_cvt_f32_f16_e32 v34, v31 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v21 +; SI-NEXT: v_cvt_f32_f16_e32 v36, v31 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v26 +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v42, v26 +; SI-NEXT: v_cvt_f32_f16_e32 v38, v31 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v25 +; SI-NEXT: v_cvt_f32_f16_e32 v48, v31 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v28 +; SI-NEXT: v_cvt_f32_f16_e32 v50, v31 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v27 +; SI-NEXT: v_cvt_f32_f16_e32 v53, v31 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v30 +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v42, v25 +; SI-NEXT: v_cvt_f32_f16_e32 v55, v31 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v29 +; SI-NEXT: v_cvt_f32_f16_e32 v41, v31 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v24 +; SI-NEXT: v_cvt_f32_f16_e32 v43, v31 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v23 +; SI-NEXT: v_cvt_f32_f16_e32 v45, v31 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v16 +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v42, v28 ; SI-NEXT: s_cbranch_execnz .LBB53_3 ; SI-NEXT: .LBB53_2: ; %cmp.true -; SI-NEXT: v_add_f64 v[1:2], s[16:17], 1.0 +; SI-NEXT: v_add_f64 v[1:2], v[1:2], 1.0 +; SI-NEXT: v_add_f64 v[17:18], v[17:18], 1.0 ; SI-NEXT: s_waitcnt expcnt(5) -; SI-NEXT: v_add_f64 v[57:58], s[18:19], 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1 +; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SI-NEXT: v_add_f64 v[19:20], v[19:20], 1.0 +; SI-NEXT: v_add_f64 v[3:4], v[3:4], 1.0 +; SI-NEXT: v_add_f64 v[7:8], v[7:8], 1.0 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v18 +; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v7 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v17 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v3, v31 +; SI-NEXT: v_add_f64 v[21:22], v[21:22], 1.0 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v20 +; SI-NEXT: v_add_f64 v[5:6], v[5:6], 1.0 +; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v2 +; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v6 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v19 +; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 ; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v57 -; SI-NEXT: v_add_f64 v[41:42], s[20:21], 1.0 -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f32_f16_e32 v3, v62 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v22 +; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v5 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v8 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v58 +; SI-NEXT: v_cvt_f32_f16_e32 v1, v21 +; SI-NEXT: v_cvt_f32_f16_e32 v2, v33 ; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v41 -; SI-NEXT: v_add_f64 v[53:54], s[22:23], 1.0 -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f32_f16_e32 v3, v60 +; SI-NEXT: v_add_f64 v[25:26], v[25:26], 1.0 +; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v4 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v42 -; SI-NEXT: v_add_f64 v[15:16], s[10:11], 1.0 +; SI-NEXT: v_cvt_f32_f16_e32 v1, v26 ; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v53 -; SI-NEXT: v_add_f64 v[20:21], s[12:13], 1.0 -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill -; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v15 -; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v20 -; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v21 -; SI-NEXT: v_cvt_f32_f16_e32 v62, v21 -; SI-NEXT: v_cvt_f32_f16_e32 v63, v20 -; SI-NEXT: v_cvt_f32_f16_e32 v20, v58 -; SI-NEXT: v_cvt_f32_f16_e32 v21, v57 -; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v57, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v1 -; SI-NEXT: v_cvt_f32_f16_e32 v1, v5 -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; SI-NEXT: v_add_f64 v[37:38], s[26:27], 1.0 -; SI-NEXT: v_cvt_f32_f16_e32 v61, v15 -; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v38 -; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v37 -; SI-NEXT: v_cvt_f32_f16_e32 v15, v37 -; SI-NEXT: v_cvt_f32_f16_e32 v37, v55 -; SI-NEXT: v_add_f64 v[7:8], s[6:7], 1.0 -; SI-NEXT: v_add_f64 v[34:35], s[28:29], 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v8 -; SI-NEXT: v_cvt_f32_f16_e32 v19, v8 -; SI-NEXT: v_cvt_f32_f16_e32 v8, v41 -; SI-NEXT: v_add_f64 v[30:31], s[42:43], 1.0 -; SI-NEXT: v_add_f64 v[11:12], s[8:9], 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v35 -; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v30 -; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v12 -; SI-NEXT: v_cvt_f32_f16_e32 v43, v12 -; SI-NEXT: v_cvt_f32_f16_e32 v12, v30 -; SI-NEXT: v_cvt_f32_f16_e32 v30, v32 -; SI-NEXT: v_cvt_f32_f16_e32 v32, v39 -; SI-NEXT: v_cvt_f32_f16_e32 v39, v44 -; SI-NEXT: v_add_f64 v[49:50], s[24:25], 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v16 -; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v50 -; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v49 -; SI-NEXT: v_cvt_f32_f16_e32 v47, v16 -; SI-NEXT: v_cvt_f32_f16_e32 v16, v49 -; SI-NEXT: v_cvt_f32_f16_e32 v49, v46 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_f64 v[3:4], s[4:5], 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v34 -; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v13, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v34 -; SI-NEXT: v_cvt_f32_f16_e32 v34, v51 -; SI-NEXT: v_cvt_f32_f16_e32 v51, v56 -; SI-NEXT: v_add_f64 v[26:27], s[40:41], 1.0 -; SI-NEXT: v_add_f64 v[22:23], s[14:15], 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v54 -; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v31 -; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v26 -; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v27 -; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22 -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v23 -; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v11 -; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v7 -; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v4 -; SI-NEXT: v_cvt_f32_f16_e32 v10, v4 -; SI-NEXT: v_cvt_f32_f16_e32 v29, v7 -; SI-NEXT: v_cvt_f32_f16_e32 v45, v11 -; SI-NEXT: v_cvt_f32_f16_e32 v23, v23 -; SI-NEXT: v_cvt_f32_f16_e32 v4, v22 -; SI-NEXT: v_cvt_f32_f16_e32 v27, v27 -; SI-NEXT: v_cvt_f32_f16_e32 v11, v26 -; SI-NEXT: v_cvt_f32_f16_e32 v31, v31 -; SI-NEXT: v_cvt_f32_f16_e32 v35, v35 -; SI-NEXT: v_cvt_f32_f16_e32 v38, v38 -; SI-NEXT: v_cvt_f32_f16_e32 v50, v50 -; SI-NEXT: v_cvt_f32_f16_e32 v54, v54 -; SI-NEXT: v_cvt_f32_f16_e32 v7, v53 +; SI-NEXT: v_cvt_f32_f16_e32 v3, v59 +; SI-NEXT: v_mov_b32_e32 v59, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v2, v63 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v25 +; SI-NEXT: v_add_f64 v[55:56], v[23:24], 1.0 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v2, v61 +; SI-NEXT: v_add_f64 v[29:30], v[29:30], 1.0 +; SI-NEXT: v_add_f64 v[41:42], v[27:28], 1.0 +; SI-NEXT: v_add_f64 v[9:10], v[9:10], 1.0 +; SI-NEXT: v_add_f64 v[11:12], v[11:12], 1.0 +; SI-NEXT: v_add_f64 v[13:14], v[13:14], 1.0 +; SI-NEXT: v_add_f64 v[15:16], v[15:16], 1.0 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v55 +; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v29 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v30 +; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v41 +; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v42 +; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v25 +; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v26 +; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v21 +; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v22 +; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v19 +; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v20 +; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v17 +; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v18 +; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v9 +; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v10 +; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v11 +; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v12 +; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v13 +; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v14 +; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v15 +; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v16 +; SI-NEXT: v_cvt_f32_f16_e32 v16, v16 +; SI-NEXT: v_cvt_f32_f16_e32 v15, v15 +; SI-NEXT: v_cvt_f32_f16_e32 v14, v14 +; SI-NEXT: v_cvt_f32_f16_e32 v13, v13 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v56 +; SI-NEXT: v_cvt_f32_f16_e32 v12, v12 +; SI-NEXT: v_cvt_f32_f16_e32 v11, v11 +; SI-NEXT: v_cvt_f32_f16_e32 v10, v10 +; SI-NEXT: v_cvt_f32_f16_e32 v9, v9 +; SI-NEXT: v_cvt_f32_f16_e32 v8, v8 +; SI-NEXT: v_cvt_f32_f16_e32 v7, v7 +; SI-NEXT: v_cvt_f32_f16_e32 v6, v6 +; SI-NEXT: v_cvt_f32_f16_e32 v5, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v4, v4 ; SI-NEXT: v_cvt_f32_f16_e32 v42, v42 +; SI-NEXT: v_cvt_f32_f16_e32 v44, v41 +; SI-NEXT: v_cvt_f32_f16_e32 v46, v30 +; SI-NEXT: v_cvt_f32_f16_e32 v47, v29 +; SI-NEXT: v_cvt_f32_f16_e32 v56, v56 +; SI-NEXT: v_cvt_f32_f16_e32 v57, v55 ; SI-NEXT: v_cvt_f32_f16_e32 v40, v40 +; SI-NEXT: v_cvt_f32_f16_e32 v54, v54 ; SI-NEXT: v_cvt_f32_f16_e32 v52, v52 -; SI-NEXT: v_cvt_f32_f16_e32 v48, v48 +; SI-NEXT: v_cvt_f32_f16_e32 v51, v51 +; SI-NEXT: v_cvt_f32_f16_e32 v49, v49 +; SI-NEXT: v_cvt_f32_f16_e32 v39, v39 +; SI-NEXT: v_cvt_f32_f16_e32 v37, v37 +; SI-NEXT: v_cvt_f32_f16_e32 v35, v35 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v2, v58 +; SI-NEXT: v_cvt_f32_f16_e32 v58, v45 +; SI-NEXT: v_cvt_f32_f16_e32 v61, v43 +; SI-NEXT: v_cvt_f32_f16_e32 v63, v53 +; SI-NEXT: v_cvt_f32_f16_e32 v32, v32 +; SI-NEXT: v_cvt_f32_f16_e32 v34, v34 ; SI-NEXT: v_cvt_f32_f16_e32 v36, v36 -; SI-NEXT: v_cvt_f32_f16_e32 v33, v33 -; SI-NEXT: v_cvt_f32_f16_e32 v59, v59 -; SI-NEXT: v_cvt_f32_f16_e32 v25, v25 -; SI-NEXT: v_cvt_f32_f16_e32 v18, v18 -; SI-NEXT: v_cvt_f32_f16_e32 v17, v17 -; SI-NEXT: v_cvt_f32_f16_e32 v14, v14 -; SI-NEXT: v_cvt_f32_f16_e32 v22, v6 -; SI-NEXT: v_cvt_f32_f16_e32 v24, v24 -; SI-NEXT: v_cvt_f32_f16_e32 v26, v9 -; SI-NEXT: v_cvt_f32_f16_e32 v28, v28 -; SI-NEXT: v_cvt_f32_f16_e32 v53, v60 -; SI-NEXT: v_cvt_f32_f16_e32 v58, v58 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v55, v5 -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v41, v5 -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v44, v5 -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v46, v5 -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v56, v5 -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v60, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v38, v38 +; SI-NEXT: v_cvt_f32_f16_e32 v48, v48 +; SI-NEXT: v_cvt_f32_f16_e32 v50, v50 +; SI-NEXT: v_cvt_f32_f16_e32 v53, v28 +; SI-NEXT: v_cvt_f32_f16_e32 v55, v27 +; SI-NEXT: v_cvt_f32_f16_e32 v41, v24 +; SI-NEXT: v_cvt_f32_f16_e32 v43, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v45, v23 +; SI-NEXT: v_mov_b32_e32 v33, v15 +; SI-NEXT: v_mov_b32_e32 v31, v16 +; SI-NEXT: v_mov_b32_e32 v62, v13 +; SI-NEXT: v_mov_b32_e32 v60, v14 +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill ; SI-NEXT: .LBB53_3: ; %end -; SI-NEXT: v_cvt_f16_f32_e32 v5, v60 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v2 -; SI-NEXT: v_cvt_f16_f32_e32 v9, v57 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_or_b32_e32 v5, v6, v5 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v58 -; SI-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v45 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v5, vcc, 4, v0 -; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; SI-NEXT: v_or_b32_e32 v6, v9, v6 -; SI-NEXT: buffer_store_dword v6, v5, s[0:3], 0 offen -; SI-NEXT: v_cvt_f16_f32_e32 v5, v56 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v57 +; SI-NEXT: v_cvt_f16_f32_e32 v3, v56 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v43 +; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v6, v21 -; SI-NEXT: v_add_i32_e32 v9, vcc, 8, v0 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_or_b32_e32 v5, v6, v5 -; SI-NEXT: buffer_store_dword v5, v9, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0 +; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; SI-NEXT: v_or_b32_e32 v2, v3, v2 +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v41 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v5, v46 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v20 -; SI-NEXT: v_add_i32_e32 v9, vcc, 12, v0 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_or_b32_e32 v5, v6, v5 -; SI-NEXT: buffer_store_dword v5, v9, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v2, v47 +; SI-NEXT: v_add_i32_e32 v3, vcc, 8, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v5, v44 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v8 -; SI-NEXT: v_add_i32_e32 v9, vcc, 16, v0 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_or_b32_e32 v5, v6, v5 -; SI-NEXT: buffer_store_dword v5, v9, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v55 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v46 +; SI-NEXT: v_add_i32_e32 v3, vcc, 12, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v5, v41 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v42 -; SI-NEXT: v_add_i32_e32 v9, vcc, 20, v0 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_or_b32_e32 v5, v6, v5 -; SI-NEXT: buffer_store_dword v5, v9, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v53 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v44 +; SI-NEXT: v_add_i32_e32 v3, vcc, 16, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v5, v55 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v7 -; SI-NEXT: v_add_i32_e32 v7, vcc, 24, v0 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_or_b32_e32 v5, v6, v5 -; SI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v50 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v42 +; SI-NEXT: v_add_i32_e32 v3, vcc, 20, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v5, v53 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v54 -; SI-NEXT: v_add_i32_e32 v7, vcc, 28, v0 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_or_b32_e32 v5, v6, v5 -; SI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v48 +; SI-NEXT: v_add_i32_e32 v3, vcc, 24, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v5, v51 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v16 -; SI-NEXT: v_add_i32_e32 v7, vcc, 32, v0 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_or_b32_e32 v5, v6, v5 -; SI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v38 +; SI-NEXT: v_add_i32_e32 v3, vcc, 28, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v5, v49 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v50 -; SI-NEXT: v_add_i32_e32 v7, vcc, 36, v0 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_or_b32_e32 v5, v6, v5 -; SI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v36 +; SI-NEXT: v_add_i32_e32 v3, vcc, 32, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v5, v39 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v15 -; SI-NEXT: v_add_i32_e32 v7, vcc, 40, v0 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_or_b32_e32 v5, v6, v5 -; SI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v34 +; SI-NEXT: v_add_i32_e32 v3, vcc, 36, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v5, v37 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v38 -; SI-NEXT: v_add_i32_e32 v7, vcc, 44, v0 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_or_b32_e32 v5, v6, v5 -; SI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v32 +; SI-NEXT: v_add_i32_e32 v3, vcc, 40, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v5, v34 -; SI-NEXT: v_add_i32_e32 v6, vcc, 48, v0 -; SI-NEXT: v_cvt_f16_f32_e32 v4, v4 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_or_b32_e32 v3, v3, v5 -; SI-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v63 +; SI-NEXT: v_add_i32_e32 v3, vcc, 44, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v32 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v35 -; SI-NEXT: v_add_i32_e32 v6, vcc, 52, v0 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_or_b32_e32 v3, v5, v3 -; SI-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v61 +; SI-NEXT: v_add_i32_e32 v3, vcc, 48, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v30 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v12 -; SI-NEXT: v_add_i32_e32 v6, vcc, 56, v0 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_or_b32_e32 v3, v5, v3 -; SI-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v58 +; SI-NEXT: v_add_i32_e32 v3, vcc, 52, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v28 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v31 -; SI-NEXT: v_add_i32_e32 v6, vcc, 60, v0 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_or_b32_e32 v3, v5, v3 -; SI-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 56, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v26 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v11 -; SI-NEXT: v_add_i32_e32 v6, vcc, 64, v0 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_or_b32_e32 v3, v5, v3 -; SI-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 60, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v24 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v27 -; SI-NEXT: v_add_i32_e32 v6, vcc, 0x44, v0 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_or_b32_e32 v3, v5, v3 -; SI-NEXT: buffer_store_dword v3, v6, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 64, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v22 -; SI-NEXT: v_add_i32_e32 v5, vcc, 0x48, v0 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x44, v0 +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_or_b32_e32 v3, v4, v3 -; SI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v14 -; SI-NEXT: v_cvt_f16_f32_e32 v4, v23 -; SI-NEXT: v_add_i32_e32 v5, vcc, 0x4c, v0 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_or_b32_e32 v3, v4, v3 -; SI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x48, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v17 -; SI-NEXT: v_cvt_f16_f32_e32 v4, v63 -; SI-NEXT: v_add_i32_e32 v5, vcc, 0x50, v0 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_or_b32_e32 v3, v4, v3 -; SI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x4c, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v18 -; SI-NEXT: v_cvt_f16_f32_e32 v4, v62 -; SI-NEXT: v_add_i32_e32 v5, vcc, 0x54, v0 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_or_b32_e32 v3, v4, v3 -; SI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x50, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v61 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v59 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x54, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_add_i32_e32 v4, vcc, 0x58, v0 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v25 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v47 -; SI-NEXT: v_add_i32_e32 v4, vcc, 0x5c, v0 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v35 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x58, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v59 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v45 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v37 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x5c, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v39 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x60, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v33 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v43 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v49 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x64, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v36 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v29 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v51 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v62 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x68, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v48 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v19 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v52 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v60 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x6c, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v52 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v13 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v54 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v33 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x70, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v1, v40 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v10 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v31 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x74, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 @@ -44313,66 +43669,93 @@ define inreg <60 x half> @bitcast_v15f64_to_v60f16_scalar(<15 x double> inreg %a ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] ; SI-NEXT: .LBB53_4: -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr60 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 ; SI-NEXT: ; implicit-def: $vgpr57 -; SI-NEXT: ; implicit-def: $vgpr58 -; SI-NEXT: ; implicit-def: $vgpr21 +; SI-NEXT: ; implicit-def: $vgpr45 ; SI-NEXT: ; implicit-def: $vgpr56 -; SI-NEXT: ; implicit-def: $vgpr20 -; SI-NEXT: ; implicit-def: $vgpr46 -; SI-NEXT: ; implicit-def: $vgpr8 -; SI-NEXT: ; implicit-def: $vgpr44 -; SI-NEXT: ; implicit-def: $vgpr42 +; SI-NEXT: ; implicit-def: $vgpr43 +; SI-NEXT: ; implicit-def: $vgpr47 ; SI-NEXT: ; implicit-def: $vgpr41 -; SI-NEXT: ; implicit-def: $vgpr7 +; SI-NEXT: ; implicit-def: $vgpr46 ; SI-NEXT: ; implicit-def: $vgpr55 -; SI-NEXT: ; implicit-def: $vgpr54 +; SI-NEXT: ; implicit-def: $vgpr44 ; SI-NEXT: ; implicit-def: $vgpr53 -; SI-NEXT: ; implicit-def: $vgpr16 -; SI-NEXT: ; implicit-def: $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr42 ; SI-NEXT: ; implicit-def: $vgpr50 -; SI-NEXT: ; implicit-def: $vgpr49 -; SI-NEXT: ; implicit-def: $vgpr15 -; SI-NEXT: ; implicit-def: $vgpr39 +; SI-NEXT: ; implicit-def: $vgpr48 ; SI-NEXT: ; implicit-def: $vgpr38 -; SI-NEXT: ; implicit-def: $vgpr37 -; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr36 ; SI-NEXT: ; implicit-def: $vgpr34 -; SI-NEXT: ; implicit-def: $vgpr35 ; SI-NEXT: ; implicit-def: $vgpr32 -; SI-NEXT: ; implicit-def: $vgpr12 -; SI-NEXT: ; implicit-def: $vgpr30 -; SI-NEXT: ; implicit-def: $vgpr31 -; SI-NEXT: ; implicit-def: $vgpr28 -; SI-NEXT: ; implicit-def: $vgpr11 -; SI-NEXT: ; implicit-def: $vgpr26 -; SI-NEXT: ; implicit-def: $vgpr27 -; SI-NEXT: ; implicit-def: $vgpr24 -; SI-NEXT: ; implicit-def: $vgpr4 -; SI-NEXT: ; implicit-def: $vgpr22 -; SI-NEXT: ; implicit-def: $vgpr23 -; SI-NEXT: ; implicit-def: $vgpr14 ; SI-NEXT: ; implicit-def: $vgpr63 -; SI-NEXT: ; implicit-def: $vgpr17 -; SI-NEXT: ; implicit-def: $vgpr62 -; SI-NEXT: ; implicit-def: $vgpr18 ; SI-NEXT: ; implicit-def: $vgpr61 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr47 -; SI-NEXT: ; implicit-def: $vgpr25 -; SI-NEXT: ; implicit-def: $vgpr45 +; SI-NEXT: ; implicit-def: $vgpr58 ; SI-NEXT: ; implicit-def: $vgpr59 -; SI-NEXT: ; implicit-def: $vgpr43 -; SI-NEXT: ; implicit-def: $vgpr33 -; SI-NEXT: ; implicit-def: $vgpr29 -; SI-NEXT: ; implicit-def: $vgpr36 -; SI-NEXT: ; implicit-def: $vgpr19 -; SI-NEXT: ; implicit-def: $vgpr48 -; SI-NEXT: ; implicit-def: $vgpr13 +; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr37 +; SI-NEXT: ; implicit-def: $vgpr39 +; SI-NEXT: ; implicit-def: $vgpr49 +; SI-NEXT: ; implicit-def: $vgpr62 +; SI-NEXT: ; implicit-def: $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr60 ; SI-NEXT: ; implicit-def: $vgpr52 -; SI-NEXT: ; implicit-def: $vgpr10 +; SI-NEXT: ; implicit-def: $vgpr33 +; SI-NEXT: ; implicit-def: $vgpr54 ; SI-NEXT: ; implicit-def: $vgpr40 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; kill: killed $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr31 ; SI-NEXT: s_branch .LBB53_2 ; ; VI-LABEL: bitcast_v15f64_to_v60f16_scalar: @@ -45262,6 +44645,9 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(5) +; SI-NEXT: v_cvt_f16_f32_e32 v58, v0 +; SI-NEXT: v_cvt_f16_f32_e32 v0, v5 ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116 ; SI-NEXT: s_waitcnt expcnt(3) ; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 @@ -45290,23 +44676,12 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:76 ; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:88 ; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:84 -; SI-NEXT: v_cvt_f16_f32_e32 v58, v0 -; SI-NEXT: v_cvt_f16_f32_e32 v0, v5 ; SI-NEXT: v_cvt_f16_f32_e32 v59, v1 ; SI-NEXT: v_cvt_f16_f32_e32 v57, v3 -; SI-NEXT: v_cvt_f16_f32_e32 v56, v2 -; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:96 -; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:92 -; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:104 -; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:100 -; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:112 -; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:108 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v60, v60 +; SI-NEXT: v_cvt_f16_f32_e32 v56, v2 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v7 @@ -45316,8 +44691,6 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v9 -; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_cvt_f16_f32_e32 v52, v52 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v8 @@ -45339,9 +44712,18 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v14 +; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v17 +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:96 +; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:92 +; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:104 +; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:100 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:112 +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:108 +; SI-NEXT: v_cvt_f16_f32_e32 v60, v60 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v16 @@ -45351,6 +44733,7 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v18 +; SI-NEXT: v_cvt_f16_f32_e32 v52, v52 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v21 @@ -45388,7 +44771,6 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) { ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v61 ; SI-NEXT: v_cvt_f16_f32_e32 v61, v49 -; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cvt_f16_f32_e32 v49, v55 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -45403,6 +44785,7 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v32 +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cvt_f16_f32_e32 v32, v47 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -46274,7 +45657,6 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v61, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v29 -; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v28 @@ -46353,6 +45735,7 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) { ; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v60 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v30 ; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v61 +; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -46517,6 +45900,9 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) { ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] ; GFX9-NEXT: s_cbranch_execz .LBB54_4 ; GFX9-NEXT: ; %bb.3: ; %cmp.true +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload @@ -46531,9 +45917,6 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload -; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v38, v61, s6 ; GFX9-NEXT: s_movk_i32 s7, 0x200 ; GFX9-NEXT: v_perm_b32 v1, v37, v60, s6 @@ -46553,6 +45936,10 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) { ; GFX9-NEXT: v_pk_add_f16 v6, v6, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v7, v7, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v8, v8, s7 op_sel_hi:[1,0] +; GFX9-NEXT: s_waitcnt vmcnt(14) +; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; GFX9-NEXT: s_waitcnt vmcnt(15) ; GFX9-NEXT: v_perm_b32 v9, v9, v44, s6 ; GFX9-NEXT: s_waitcnt vmcnt(14) @@ -46581,10 +45968,6 @@ define <15 x double> @bitcast_v60f16_to_v15f64(<60 x half> %a, i32 %b) { ; GFX9-NEXT: v_perm_b32 v21, v21, v48, s6 ; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: v_perm_b32 v22, v22, v39, s6 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v10, v10, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0] @@ -46905,12 +46288,35 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a ; SI-NEXT: v_cvt_f16_f32_e32 v8, s26 ; SI-NEXT: v_cvt_f16_f32_e32 v6, s29 ; SI-NEXT: v_cvt_f16_f32_e32 v7, s28 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: v_cvt_f16_f32_e32 v50, v54 ; SI-NEXT: v_cvt_f16_f32_e32 v48, v48 ; SI-NEXT: v_cvt_f16_f32_e32 v31, v40 -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v33 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill @@ -46920,7 +46326,7 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v38 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0) +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v44 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -46929,7 +46335,7 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v46 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0) +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v47 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -46938,7 +46344,7 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v57 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0) +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v58 ; SI-NEXT: v_cvt_f16_f32_e32 v58, s16 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill @@ -46949,38 +46355,12 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v60 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB55_2 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(4) ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; SI-NEXT: v_or_b32_e32 v3, v10, v3 -; SI-NEXT: s_waitcnt expcnt(3) ; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34 ; SI-NEXT: v_mov_b32_e32 v33, v32 ; SI-NEXT: v_or_b32_e32 v10, v32, v10 @@ -47005,12 +46385,12 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a ; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 ; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18 ; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v59 ; SI-NEXT: v_or_b32_e32 v1, v12, v1 ; SI-NEXT: v_or_b32_e32 v2, v11, v2 @@ -47119,12 +46499,10 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a ; SI-NEXT: v_mov_b32_e32 v40, v44 ; SI-NEXT: s_cbranch_vccnz .LBB55_5 ; SI-NEXT: ; %bb.4: ; %cmp.true -; SI-NEXT: s_waitcnt expcnt(5) ; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(4) ; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; SI-NEXT: v_cvt_f32_f16_e32 v0, v59 ; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v0, v59 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v58 ; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_cvt_f32_f16_e32 v8, v33 @@ -47910,304 +47288,115 @@ define inreg <15 x double> @bitcast_v60f16_to_v15f64_scalar(<60 x half> inreg %a ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v12 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v9 :: v_dual_mov_b32 v25, v7 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v8 :: v_dual_mov_b32 v191, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v190, v6 :: v_dual_mov_b32 v185, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v186, v3 :: v_dual_mov_b32 v187, v2 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v188, v1 :: v_dual_mov_b32 v189, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB55_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB55_3 ; GFX11-TRUE16-NEXT: .LBB55_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s40 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s41 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v189, 0x200, v189 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v188, 0x200, v188 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v187, 0x200, v187 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v186, 0x200, v186 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v185, 0x200, v185 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v191, 0x200, v191 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v190, 0x200, v190 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, s6 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, s7 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, s8 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s9 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, s10 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, s11 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, s12 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, s13 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s14 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, s15 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, s16 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v30, 0x200, v30 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s0 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s1 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s2 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, s3 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, s4 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v35, 0x200, s5 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v44, 0x200, s6 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v54, 0x200, s7 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v65, 0x200, s8 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v77, 0x200, s9 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v90, 0x200, s10 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v104, 0x200, s11 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v119, 0x200, s12 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v135, 0x200, s13 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v152, 0x200, s14 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v170, 0x200, s15 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: .LBB55_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v170 :: v_dual_mov_b32 v18, v189 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v188 :: v_dual_mov_b32 v20, v187 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v186 :: v_dual_mov_b32 v22, v185 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v191 :: v_dual_mov_b32 v24, v190 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v191, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v190, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v189, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v188, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v187, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:316 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v119 :: v_dual_mov_b32 v27, v30 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB55_4: -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v64, v29 :: v_dual_mov_b32 v65, v28 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v66, v30 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v53, v26 :: v_dual_mov_b32 v54, v25 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v54 :: v_dual_mov_b32 v26, v53 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v65 :: v_dual_mov_b32 v29, v64 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v30, v66 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB55_2 ; ; GFX11-FAKE16-LABEL: bitcast_v60f16_to_v15f64_scalar: @@ -51893,27 +51082,27 @@ define <60 x i16> @bitcast_v60f16_to_v60i16(<60 x half> %a, i32 %b) { ; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 ; SI-NEXT: v_cvt_f16_f32_e32 v55, v3 ; SI-NEXT: v_cvt_f16_f32_e32 v3, v22 -; SI-NEXT: v_cvt_f16_f32_e32 v60, v2 +; SI-NEXT: v_cvt_f16_f32_e32 v40, v4 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v1, v5 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v18 ; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; SI-NEXT: v_cvt_f16_f32_e32 v40, v4 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v6 ; SI-NEXT: v_cvt_f16_f32_e32 v53, v8 ; SI-NEXT: v_cvt_f16_f32_e32 v8, v10 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v6 ; SI-NEXT: v_cvt_f16_f32_e32 v49, v12 ; SI-NEXT: v_cvt_f16_f32_e32 v6, v13 ; SI-NEXT: v_cvt_f16_f32_e32 v37, v15 +; SI-NEXT: v_cvt_f16_f32_e32 v60, v2 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v18 ; SI-NEXT: v_cvt_f16_f32_e32 v52, v7 ; SI-NEXT: v_cvt_f16_f32_e32 v7, v9 ; SI-NEXT: v_cvt_f16_f32_e32 v48, v11 ; SI-NEXT: v_cvt_f16_f32_e32 v14, v14 ; SI-NEXT: v_cvt_f16_f32_e32 v38, v16 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v2, v19 ; SI-NEXT: v_cvt_f16_f32_e32 v20, v20 @@ -53259,6 +52448,8 @@ define inreg <60 x i16> @bitcast_v60f16_to_v60i16_scalar(<60 x half> inreg %a, i ; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 ; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v1 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v44 +; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 ; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1 ; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 @@ -53285,10 +52476,13 @@ define inreg <60 x i16> @bitcast_v60f16_to_v60i16_scalar(<60 x half> inreg %a, i ; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 ; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v1 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v50 +; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mov_b32_e32 v51, v11 ; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1 ; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 ; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v1 -; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_cvt_f32_f16_e32 v5, v5 ; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5 ; SI-NEXT: v_cvt_f16_f32_e32 v5, v5 @@ -53300,8 +52494,26 @@ define inreg <60 x i16> @bitcast_v60f16_to_v60i16_scalar(<60 x half> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v3, v26 ; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3 ; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v1, v50 +; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v1, v8 +; SI-NEXT: v_mov_b32_e32 v8, v48 +; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v1, v44 +; SI-NEXT: v_lshr_b64 v[44:45], v[29:30], 16 +; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v1, v38 +; SI-NEXT: v_cvt_f32_f16_e32 v38, v43 ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_cvt_f32_f16_e32 v5, v5 +; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 ; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5 ; SI-NEXT: v_cvt_f16_f32_e32 v5, v5 ; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill @@ -53329,17 +52541,11 @@ define inreg <60 x i16> @bitcast_v60f16_to_v60i16_scalar(<60 x half> inreg %a, i ; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5 ; SI-NEXT: v_cvt_f16_f32_e32 v5, v5 ; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 ; SI-NEXT: v_or_b32_e32 v18, v3, v5 ; SI-NEXT: v_cvt_f32_f16_e32 v5, v37 ; SI-NEXT: v_cvt_f32_f16_e32 v3, v16 -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_mov_b32_e32 v51, v11 ; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5 ; SI-NEXT: v_cvt_f16_f32_e32 v55, v5 ; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3 @@ -53382,52 +52588,32 @@ define inreg <60 x i16> @bitcast_v60f16_to_v60i16_scalar(<60 x half> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v3, v6 ; SI-NEXT: v_lshr_b64 v[58:59], v[34:35], 16 ; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5 -; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v1, v50 -; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1 -; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 -; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v1 -; SI-NEXT: v_cvt_f32_f16_e32 v1, v8 -; SI-NEXT: v_mov_b32_e32 v8, v48 ; SI-NEXT: v_cvt_f16_f32_e32 v48, v5 -; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1 -; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v48 -; SI-NEXT: v_or_b32_e32 v6, v3, v5 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v4 -; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v1 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_cvt_f32_f16_e32 v1, v44 -; SI-NEXT: v_cvt_f32_f16_e32 v4, v31 ; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3 ; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 -; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1 -; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 -; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v60, v4 +; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v48 ; SI-NEXT: v_mov_b32_e32 v59, v48 -; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v1 -; SI-NEXT: v_cvt_f32_f16_e32 v1, v38 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v60 -; SI-NEXT: v_or_b32_e32 v4, v3, v4 -; SI-NEXT: v_cvt_f32_f16_e32 v38, v43 -; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1 -; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 -; SI-NEXT: v_lshr_b64 v[47:48], v[17:18], 16 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshr_b64 v[44:45], v[29:30], 16 +; SI-NEXT: v_or_b32_e32 v6, v3, v5 ; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v1 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v24 ; SI-NEXT: v_cvt_f32_f16_e32 v24, v8 ; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; SI-NEXT: v_cvt_f32_f16_e32 v3, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v4, v31 ; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1 ; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3 +; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4 +; SI-NEXT: v_cvt_f16_f32_e32 v60, v4 +; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 ; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v24 ; SI-NEXT: v_cvt_f16_f32_e32 v24, v24 +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v60 +; SI-NEXT: v_or_b32_e32 v4, v3, v4 ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v1 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v20 ; SI-NEXT: v_cvt_f32_f16_e32 v20, v39 +; SI-NEXT: v_lshr_b64 v[47:48], v[17:18], 16 ; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1 ; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20 ; SI-NEXT: v_cvt_f16_f32_e32 v31, v20 @@ -53524,14 +52710,15 @@ define inreg <60 x i16> @bitcast_v60f16_to_v60i16_scalar(<60 x half> inreg %a, i ; SI-NEXT: v_mov_b32_e32 v32, v41 ; SI-NEXT: v_lshr_b64 v[40:41], v[21:22], 16 ; SI-NEXT: v_lshr_b64 v[20:21], v[11:12], 16 -; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshr_b64 v[20:21], v[56:57], 16 ; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill ; SI-NEXT: v_mov_b32_e32 v11, v24 +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshr_b64 v[8:9], v[9:10], 16 ; SI-NEXT: v_mov_b32_e32 v39, v31 ; SI-NEXT: v_mov_b32_e32 v31, v60 @@ -53541,7 +52728,6 @@ define inreg <60 x i16> @bitcast_v60f16_to_v60i16_scalar(<60 x half> inreg %a, i ; SI-NEXT: v_mov_b32_e32 v37, v55 ; SI-NEXT: v_lshr_b64 v[55:56], v[5:6], 16 ; SI-NEXT: v_lshr_b64 v[24:25], v[3:4], 16 -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshr_b64 v[20:21], v[1:2], 16 ; SI-NEXT: .LBB59_3: ; %end ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v58 |