diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll | 9449 |
1 files changed, 4275 insertions, 5174 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll index 07cdbef..63b61f6 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll @@ -3409,18 +3409,46 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v14, s30, 0 -; SI-NEXT: v_writelane_b32 v14, s31, 1 -; SI-NEXT: v_writelane_b32 v14, s34, 2 -; SI-NEXT: v_writelane_b32 v14, s35, 3 -; SI-NEXT: v_writelane_b32 v14, s36, 4 -; SI-NEXT: v_writelane_b32 v14, s37, 5 -; SI-NEXT: v_writelane_b32 v14, s38, 6 +; SI-NEXT: v_writelane_b32 v20, s30, 0 +; SI-NEXT: v_writelane_b32 v20, s31, 1 +; SI-NEXT: v_writelane_b32 v20, s34, 2 +; SI-NEXT: v_writelane_b32 v20, s35, 3 +; SI-NEXT: v_writelane_b32 v20, s36, 4 +; SI-NEXT: v_mov_b32_e32 v14, s16 +; SI-NEXT: v_mov_b32_e32 v15, s17 +; SI-NEXT: v_writelane_b32 v20, s37, 5 +; SI-NEXT: v_mov_b32_e32 v16, s18 +; SI-NEXT: v_mov_b32_e32 v17, s19 +; SI-NEXT: v_mov_b32_e32 v18, s20 +; SI-NEXT: v_mov_b32_e32 v19, s21 +; SI-NEXT: v_readfirstlane_b32 s42, v14 +; SI-NEXT: v_mov_b32_e32 v14, s22 +; SI-NEXT: v_readfirstlane_b32 s43, v15 +; SI-NEXT: v_mov_b32_e32 v15, s23 +; SI-NEXT: v_writelane_b32 v20, s38, 6 +; SI-NEXT: v_readfirstlane_b32 s40, v16 +; SI-NEXT: v_mov_b32_e32 v16, s24 +; SI-NEXT: v_readfirstlane_b32 s41, v17 +; SI-NEXT: v_mov_b32_e32 v17, s25 +; SI-NEXT: v_readfirstlane_b32 s24, v18 +; SI-NEXT: v_mov_b32_e32 v18, s26 +; SI-NEXT: v_readfirstlane_b32 s25, v19 +; SI-NEXT: v_mov_b32_e32 v19, s27 +; SI-NEXT: v_readfirstlane_b32 s22, v14 +; SI-NEXT: v_mov_b32_e32 v14, s28 +; SI-NEXT: v_readfirstlane_b32 s23, v15 +; SI-NEXT: v_mov_b32_e32 v15, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 -; SI-NEXT: v_writelane_b32 v14, s39, 7 +; SI-NEXT: v_writelane_b32 v20, s39, 7 +; SI-NEXT: v_readfirstlane_b32 s20, v16 +; SI-NEXT: v_readfirstlane_b32 s21, v17 +; SI-NEXT: v_readfirstlane_b32 s18, v18 +; SI-NEXT: v_readfirstlane_b32 s19, v19 +; SI-NEXT: v_readfirstlane_b32 s16, v14 +; SI-NEXT: v_readfirstlane_b32 s17, v15 ; SI-NEXT: v_readfirstlane_b32 s14, v1 ; SI-NEXT: v_readfirstlane_b32 s15, v2 ; SI-NEXT: v_readfirstlane_b32 s12, v3 @@ -3432,9 +3460,9 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s6, v9 ; SI-NEXT: v_readfirstlane_b32 s7, v10 ; SI-NEXT: v_readfirstlane_b32 s4, v11 -; SI-NEXT: s_and_b64 s[40:41], vcc, exec +; SI-NEXT: s_and_b64 s[26:27], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v12 -; SI-NEXT: v_writelane_b32 v14, s48, 8 +; SI-NEXT: v_writelane_b32 v20, s48, 8 ; SI-NEXT: s_cbranch_scc0 .LBB13_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s92, s5, 16 @@ -3443,42 +3471,42 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; SI-NEXT: s_lshr_b32 s95, s11, 16 ; SI-NEXT: s_lshr_b32 s30, s13, 16 ; SI-NEXT: s_lshr_b32 s31, s15, 16 -; SI-NEXT: s_lshr_b32 s34, s29, 16 -; SI-NEXT: s_lshr_b32 s35, s27, 16 -; SI-NEXT: s_lshr_b32 s36, s25, 16 +; SI-NEXT: s_lshr_b32 s34, s17, 16 +; SI-NEXT: s_lshr_b32 s35, s19, 16 +; SI-NEXT: s_lshr_b32 s36, s21, 16 ; SI-NEXT: s_lshr_b32 s37, s23, 16 -; SI-NEXT: s_lshr_b32 s38, s21, 16 -; SI-NEXT: s_lshr_b32 s39, s19, 16 -; SI-NEXT: s_lshr_b32 s48, s17, 16 -; SI-NEXT: s_lshr_b64 s[40:41], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[42:43], s[6:7], 16 +; SI-NEXT: s_lshr_b32 s38, s25, 16 +; SI-NEXT: s_lshr_b32 s39, s41, 16 +; SI-NEXT: s_lshr_b32 s48, s43, 16 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[6:7], 16 ; SI-NEXT: s_lshr_b64 s[44:45], s[8:9], 16 ; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 16 ; SI-NEXT: s_lshr_b64 s[56:57], s[12:13], 16 ; SI-NEXT: s_lshr_b64 s[58:59], s[14:15], 16 -; SI-NEXT: s_lshr_b64 s[60:61], s[28:29], 16 -; SI-NEXT: s_lshr_b64 s[62:63], s[26:27], 16 -; SI-NEXT: s_lshr_b64 s[72:73], s[24:25], 16 +; SI-NEXT: s_lshr_b64 s[60:61], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[62:63], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[72:73], s[20:21], 16 ; SI-NEXT: s_lshr_b64 s[74:75], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[76:77], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[78:79], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[88:89], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[76:77], s[24:25], 16 +; SI-NEXT: s_lshr_b64 s[78:79], s[40:41], 16 +; SI-NEXT: s_lshr_b64 s[88:89], s[42:43], 16 ; SI-NEXT: s_cbranch_execnz .LBB13_3 ; SI-NEXT: .LBB13_2: ; %cmp.true -; SI-NEXT: s_add_i32 s17, s17, 3 -; SI-NEXT: s_add_i32 s16, s16, 3 -; SI-NEXT: s_add_i32 s19, s19, 3 -; SI-NEXT: s_add_i32 s18, s18, 3 -; SI-NEXT: s_add_i32 s21, s21, 3 -; SI-NEXT: s_add_i32 s20, s20, 3 -; SI-NEXT: s_add_i32 s23, s23, 3 -; SI-NEXT: s_add_i32 s22, s22, 3 +; SI-NEXT: s_add_i32 s43, s43, 3 +; SI-NEXT: s_add_i32 s42, s42, 3 +; SI-NEXT: s_add_i32 s41, s41, 3 +; SI-NEXT: s_add_i32 s40, s40, 3 ; SI-NEXT: s_add_i32 s25, s25, 3 ; SI-NEXT: s_add_i32 s24, s24, 3 -; SI-NEXT: s_add_i32 s27, s27, 3 -; SI-NEXT: s_add_i32 s26, s26, 3 -; SI-NEXT: s_add_i32 s29, s29, 3 -; SI-NEXT: s_add_i32 s28, s28, 3 +; SI-NEXT: s_add_i32 s23, s23, 3 +; SI-NEXT: s_add_i32 s22, s22, 3 +; SI-NEXT: s_add_i32 s21, s21, 3 +; SI-NEXT: s_add_i32 s20, s20, 3 +; SI-NEXT: s_add_i32 s19, s19, 3 +; SI-NEXT: s_add_i32 s18, s18, 3 +; SI-NEXT: s_add_i32 s17, s17, 3 +; SI-NEXT: s_add_i32 s16, s16, 3 ; SI-NEXT: s_add_i32 s15, s15, 3 ; SI-NEXT: s_add_i32 s14, s14, 3 ; SI-NEXT: s_add_i32 s13, s13, 3 @@ -3491,118 +3519,118 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; SI-NEXT: s_add_i32 s6, s6, 3 ; SI-NEXT: s_add_i32 s5, s5, 3 ; SI-NEXT: s_add_i32 s4, s4, 3 -; SI-NEXT: s_lshr_b64 s[40:41], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[42:43], s[6:7], 16 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[6:7], 16 ; SI-NEXT: s_lshr_b64 s[44:45], s[8:9], 16 ; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 16 ; SI-NEXT: s_lshr_b64 s[56:57], s[12:13], 16 ; SI-NEXT: s_lshr_b64 s[58:59], s[14:15], 16 -; SI-NEXT: s_lshr_b64 s[60:61], s[28:29], 16 +; SI-NEXT: s_lshr_b64 s[60:61], s[16:17], 16 ; SI-NEXT: s_lshr_b32 s92, s5, 16 ; SI-NEXT: s_lshr_b32 s93, s7, 16 ; SI-NEXT: s_lshr_b32 s94, s9, 16 ; SI-NEXT: s_lshr_b32 s95, s11, 16 ; SI-NEXT: s_lshr_b32 s30, s13, 16 ; SI-NEXT: s_lshr_b32 s31, s15, 16 -; SI-NEXT: s_lshr_b32 s34, s29, 16 -; SI-NEXT: s_lshr_b32 s35, s27, 16 -; SI-NEXT: s_lshr_b32 s36, s25, 16 +; SI-NEXT: s_lshr_b32 s34, s17, 16 +; SI-NEXT: s_lshr_b32 s35, s19, 16 +; SI-NEXT: s_lshr_b32 s36, s21, 16 ; SI-NEXT: s_lshr_b32 s37, s23, 16 -; SI-NEXT: s_lshr_b32 s38, s21, 16 -; SI-NEXT: s_lshr_b32 s39, s19, 16 -; SI-NEXT: s_lshr_b32 s48, s17, 16 -; SI-NEXT: s_lshr_b64 s[62:63], s[26:27], 16 -; SI-NEXT: s_lshr_b64 s[72:73], s[24:25], 16 +; SI-NEXT: s_lshr_b32 s38, s25, 16 +; SI-NEXT: s_lshr_b32 s39, s41, 16 +; SI-NEXT: s_lshr_b32 s48, s43, 16 +; SI-NEXT: s_lshr_b64 s[62:63], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[72:73], s[20:21], 16 ; SI-NEXT: s_lshr_b64 s[74:75], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[76:77], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[78:79], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[88:89], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[76:77], s[24:25], 16 +; SI-NEXT: s_lshr_b64 s[78:79], s[40:41], 16 +; SI-NEXT: s_lshr_b64 s[88:89], s[42:43], 16 ; SI-NEXT: .LBB13_3: ; %end -; SI-NEXT: s_lshl_b32 s41, s88, 16 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s41 -; SI-NEXT: v_mov_b32_e32 v1, s16 -; SI-NEXT: s_and_b32 s16, s17, 0xffff -; SI-NEXT: s_lshl_b32 s17, s48, 16 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_lshl_b32 s16, s78, 16 -; SI-NEXT: s_and_b32 s17, s18, 0xffff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: v_mov_b32_e32 v3, s16 -; SI-NEXT: s_and_b32 s16, s19, 0xffff -; SI-NEXT: s_lshl_b32 s17, s39, 16 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v4, s16 -; SI-NEXT: s_lshl_b32 s16, s76, 16 -; SI-NEXT: s_and_b32 s17, s20, 0xffff -; SI-NEXT: s_or_b32 s16, s17, s16 +; SI-NEXT: s_lshl_b32 s27, s88, 16 +; SI-NEXT: s_and_b32 s29, s42, 0xffff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: v_mov_b32_e32 v1, s27 +; SI-NEXT: s_and_b32 s27, s43, 0xffff +; SI-NEXT: s_lshl_b32 s29, s48, 16 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_lshl_b32 s27, s78, 16 +; SI-NEXT: s_and_b32 s29, s40, 0xffff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: v_mov_b32_e32 v3, s27 +; SI-NEXT: s_and_b32 s27, s41, 0xffff +; SI-NEXT: s_lshl_b32 s29, s39, 16 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v4, s27 +; SI-NEXT: s_lshl_b32 s27, s76, 16 +; SI-NEXT: s_and_b32 s24, s24, 0xffff +; SI-NEXT: s_or_b32 s24, s24, s27 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0 -; SI-NEXT: v_mov_b32_e32 v5, s16 -; SI-NEXT: s_and_b32 s16, s21, 0xffff +; SI-NEXT: v_mov_b32_e32 v5, s24 +; SI-NEXT: s_and_b32 s24, s25, 0xffff ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0 -; SI-NEXT: s_lshl_b32 s17, s38, 16 +; SI-NEXT: s_lshl_b32 s25, s38, 16 ; SI-NEXT: buffer_store_dword v3, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 12, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s24, s24, s25 ; SI-NEXT: buffer_store_dword v4, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0 ; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s22, 0xffff -; SI-NEXT: s_lshl_b32 s17, s74, 16 +; SI-NEXT: v_mov_b32_e32 v2, s24 +; SI-NEXT: s_and_b32 s22, s22, 0xffff +; SI-NEXT: s_lshl_b32 s24, s74, 16 ; SI-NEXT: buffer_store_dword v5, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 20, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s22, s22, s24 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s23, 0xffff -; SI-NEXT: s_lshl_b32 s17, s37, 16 +; SI-NEXT: v_mov_b32_e32 v2, s22 +; SI-NEXT: s_and_b32 s22, s23, 0xffff +; SI-NEXT: s_lshl_b32 s23, s37, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s22, s22, s23 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s24, 0xffff -; SI-NEXT: s_lshl_b32 s17, s72, 16 +; SI-NEXT: v_mov_b32_e32 v2, s22 +; SI-NEXT: s_and_b32 s20, s20, 0xffff +; SI-NEXT: s_lshl_b32 s22, s72, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 28, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s20, s20, s22 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s25, 0xffff -; SI-NEXT: s_lshl_b32 s17, s36, 16 +; SI-NEXT: v_mov_b32_e32 v2, s20 +; SI-NEXT: s_and_b32 s20, s21, 0xffff +; SI-NEXT: s_lshl_b32 s21, s36, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s20, s20, s21 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s26, 0xffff -; SI-NEXT: s_lshl_b32 s17, s62, 16 +; SI-NEXT: v_mov_b32_e32 v2, s20 +; SI-NEXT: s_and_b32 s18, s18, 0xffff +; SI-NEXT: s_lshl_b32 s20, s62, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 36, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s18, s18, s20 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s27, 0xffff -; SI-NEXT: s_lshl_b32 s17, s35, 16 +; SI-NEXT: v_mov_b32_e32 v2, s18 +; SI-NEXT: s_and_b32 s18, s19, 0xffff +; SI-NEXT: s_lshl_b32 s19, s35, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s18, s18, s19 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s28, 0xffff -; SI-NEXT: s_lshl_b32 s17, s60, 16 +; SI-NEXT: v_mov_b32_e32 v2, s18 +; SI-NEXT: s_and_b32 s16, s16, 0xffff +; SI-NEXT: s_lshl_b32 s18, s60, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 44, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s16, s16, s18 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s29, 0xffff +; SI-NEXT: s_and_b32 s16, s17, 0xffff ; SI-NEXT: s_lshl_b32 s17, s34, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0 ; SI-NEXT: s_or_b32 s16, s16, s17 @@ -3666,7 +3694,7 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s8 ; SI-NEXT: s_and_b32 s6, s6, 0xffff -; SI-NEXT: s_lshl_b32 s8, s42, 16 +; SI-NEXT: s_lshl_b32 s8, s28, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x54, v0 ; SI-NEXT: s_or_b32 s6, s6, s8 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen @@ -3680,7 +3708,7 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s6 ; SI-NEXT: s_and_b32 s4, s4, 0xffff -; SI-NEXT: s_lshl_b32 s6, s40, 16 +; SI-NEXT: s_lshl_b32 s6, s26, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x5c, v0 ; SI-NEXT: s_or_b32 s4, s4, s6 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen @@ -3694,17 +3722,17 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x64, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s48, v14, 8 -; SI-NEXT: v_readlane_b32 s39, v14, 7 -; SI-NEXT: v_readlane_b32 s38, v14, 6 -; SI-NEXT: v_readlane_b32 s37, v14, 5 -; SI-NEXT: v_readlane_b32 s36, v14, 4 -; SI-NEXT: v_readlane_b32 s35, v14, 3 -; SI-NEXT: v_readlane_b32 s34, v14, 2 -; SI-NEXT: v_readlane_b32 s31, v14, 1 -; SI-NEXT: v_readlane_b32 s30, v14, 0 +; SI-NEXT: v_readlane_b32 s48, v20, 8 +; SI-NEXT: v_readlane_b32 s39, v20, 7 +; SI-NEXT: v_readlane_b32 s38, v20, 6 +; SI-NEXT: v_readlane_b32 s37, v20, 5 +; SI-NEXT: v_readlane_b32 s36, v20, 4 +; SI-NEXT: v_readlane_b32 s35, v20, 3 +; SI-NEXT: v_readlane_b32 s34, v20, 2 +; SI-NEXT: v_readlane_b32 s31, v20, 1 +; SI-NEXT: v_readlane_b32 s30, v20, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] @@ -3733,16 +3761,44 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; SI-NEXT: ; implicit-def: $sgpr94 ; SI-NEXT: ; implicit-def: $sgpr93 ; SI-NEXT: ; implicit-def: $sgpr92 -; SI-NEXT: ; implicit-def: $sgpr42 -; SI-NEXT: ; implicit-def: $sgpr40 +; SI-NEXT: ; implicit-def: $sgpr28 +; SI-NEXT: ; implicit-def: $sgpr26 ; SI-NEXT: s_branch .LBB13_2 ; ; VI-LABEL: bitcast_v26i32_to_v52i16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v13, s16 +; VI-NEXT: v_mov_b32_e32 v14, s17 +; VI-NEXT: v_mov_b32_e32 v15, s18 +; VI-NEXT: v_mov_b32_e32 v16, s19 +; VI-NEXT: v_mov_b32_e32 v17, s20 +; VI-NEXT: v_mov_b32_e32 v18, s21 +; VI-NEXT: v_mov_b32_e32 v19, s22 +; VI-NEXT: v_readfirstlane_b32 s44, v13 +; VI-NEXT: v_mov_b32_e32 v13, s23 +; VI-NEXT: v_readfirstlane_b32 s43, v14 +; VI-NEXT: v_mov_b32_e32 v14, s24 +; VI-NEXT: v_readfirstlane_b32 s42, v15 +; VI-NEXT: v_mov_b32_e32 v15, s25 +; VI-NEXT: v_readfirstlane_b32 s41, v16 +; VI-NEXT: v_mov_b32_e32 v16, s26 +; VI-NEXT: v_readfirstlane_b32 s40, v17 +; VI-NEXT: v_mov_b32_e32 v17, s27 +; VI-NEXT: v_readfirstlane_b32 s26, v18 +; VI-NEXT: v_mov_b32_e32 v18, s28 +; VI-NEXT: v_readfirstlane_b32 s25, v19 +; VI-NEXT: v_mov_b32_e32 v19, s29 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 -; VI-NEXT: v_readfirstlane_b32 s41, v0 -; VI-NEXT: v_readfirstlane_b32 s40, v1 +; VI-NEXT: v_readfirstlane_b32 s24, v13 +; VI-NEXT: v_readfirstlane_b32 s23, v14 +; VI-NEXT: v_readfirstlane_b32 s22, v15 +; VI-NEXT: v_readfirstlane_b32 s21, v16 +; VI-NEXT: v_readfirstlane_b32 s20, v17 +; VI-NEXT: v_readfirstlane_b32 s19, v18 +; VI-NEXT: v_readfirstlane_b32 s18, v19 +; VI-NEXT: v_readfirstlane_b32 s17, v0 +; VI-NEXT: v_readfirstlane_b32 s16, v1 ; VI-NEXT: v_readfirstlane_b32 s15, v2 ; VI-NEXT: v_readfirstlane_b32 s14, v3 ; VI-NEXT: v_readfirstlane_b32 s13, v4 @@ -3756,9 +3812,9 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; VI-NEXT: v_readfirstlane_b32 s7, v11 ; VI-NEXT: s_cbranch_scc0 .LBB13_4 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_lshr_b32 s42, s7, 16 -; VI-NEXT: s_lshr_b32 s43, s6, 16 -; VI-NEXT: s_lshr_b32 s44, s8, 16 +; VI-NEXT: s_lshr_b32 s27, s7, 16 +; VI-NEXT: s_lshr_b32 s28, s6, 16 +; VI-NEXT: s_lshr_b32 s29, s8, 16 ; VI-NEXT: s_lshr_b32 s45, s9, 16 ; VI-NEXT: s_lshr_b32 s46, s10, 16 ; VI-NEXT: s_lshr_b32 s47, s11, 16 @@ -3766,22 +3822,22 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; VI-NEXT: s_lshr_b32 s57, s13, 16 ; VI-NEXT: s_lshr_b32 s58, s14, 16 ; VI-NEXT: s_lshr_b32 s59, s15, 16 -; VI-NEXT: s_lshr_b32 s60, s40, 16 -; VI-NEXT: s_lshr_b32 s61, s41, 16 -; VI-NEXT: s_lshr_b32 s62, s29, 16 -; VI-NEXT: s_lshr_b32 s63, s28, 16 -; VI-NEXT: s_lshr_b32 s72, s27, 16 -; VI-NEXT: s_lshr_b32 s73, s26, 16 -; VI-NEXT: s_lshr_b32 s74, s25, 16 -; VI-NEXT: s_lshr_b32 s75, s24, 16 -; VI-NEXT: s_lshr_b32 s76, s23, 16 -; VI-NEXT: s_lshr_b32 s77, s22, 16 -; VI-NEXT: s_lshr_b32 s78, s21, 16 -; VI-NEXT: s_lshr_b32 s79, s20, 16 -; VI-NEXT: s_lshr_b32 s88, s19, 16 -; VI-NEXT: s_lshr_b32 s89, s18, 16 -; VI-NEXT: s_lshr_b32 s90, s17, 16 -; VI-NEXT: s_lshr_b32 s91, s16, 16 +; VI-NEXT: s_lshr_b32 s60, s16, 16 +; VI-NEXT: s_lshr_b32 s61, s17, 16 +; VI-NEXT: s_lshr_b32 s62, s18, 16 +; VI-NEXT: s_lshr_b32 s63, s19, 16 +; VI-NEXT: s_lshr_b32 s72, s20, 16 +; VI-NEXT: s_lshr_b32 s73, s21, 16 +; VI-NEXT: s_lshr_b32 s74, s22, 16 +; VI-NEXT: s_lshr_b32 s75, s23, 16 +; VI-NEXT: s_lshr_b32 s76, s24, 16 +; VI-NEXT: s_lshr_b32 s77, s25, 16 +; VI-NEXT: s_lshr_b32 s78, s26, 16 +; VI-NEXT: s_lshr_b32 s79, s40, 16 +; VI-NEXT: s_lshr_b32 s88, s41, 16 +; VI-NEXT: s_lshr_b32 s89, s42, 16 +; VI-NEXT: s_lshr_b32 s90, s43, 16 +; VI-NEXT: s_lshr_b32 s91, s44, 16 ; VI-NEXT: s_cbranch_execnz .LBB13_3 ; VI-NEXT: .LBB13_2: ; %cmp.true ; VI-NEXT: s_add_i32 s7, s7, 3 @@ -3794,25 +3850,25 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; VI-NEXT: s_add_i32 s13, s13, 3 ; VI-NEXT: s_add_i32 s14, s14, 3 ; VI-NEXT: s_add_i32 s15, s15, 3 +; VI-NEXT: s_add_i32 s16, s16, 3 +; VI-NEXT: s_add_i32 s17, s17, 3 +; VI-NEXT: s_add_i32 s18, s18, 3 +; VI-NEXT: s_add_i32 s19, s19, 3 +; VI-NEXT: s_add_i32 s20, s20, 3 +; VI-NEXT: s_add_i32 s21, s21, 3 +; VI-NEXT: s_add_i32 s22, s22, 3 +; VI-NEXT: s_add_i32 s23, s23, 3 +; VI-NEXT: s_add_i32 s24, s24, 3 +; VI-NEXT: s_add_i32 s25, s25, 3 +; VI-NEXT: s_add_i32 s26, s26, 3 ; VI-NEXT: s_add_i32 s40, s40, 3 ; VI-NEXT: s_add_i32 s41, s41, 3 -; VI-NEXT: s_add_i32 s29, s29, 3 -; VI-NEXT: s_add_i32 s28, s28, 3 -; VI-NEXT: s_add_i32 s27, s27, 3 -; VI-NEXT: s_add_i32 s26, s26, 3 -; VI-NEXT: s_add_i32 s25, s25, 3 -; VI-NEXT: s_add_i32 s24, s24, 3 -; VI-NEXT: s_add_i32 s23, s23, 3 -; VI-NEXT: s_add_i32 s22, s22, 3 -; VI-NEXT: s_add_i32 s21, s21, 3 -; VI-NEXT: s_add_i32 s20, s20, 3 -; VI-NEXT: s_add_i32 s19, s19, 3 -; VI-NEXT: s_add_i32 s18, s18, 3 -; VI-NEXT: s_add_i32 s17, s17, 3 -; VI-NEXT: s_add_i32 s16, s16, 3 -; VI-NEXT: s_lshr_b32 s42, s7, 16 -; VI-NEXT: s_lshr_b32 s43, s6, 16 -; VI-NEXT: s_lshr_b32 s44, s8, 16 +; VI-NEXT: s_add_i32 s42, s42, 3 +; VI-NEXT: s_add_i32 s43, s43, 3 +; VI-NEXT: s_add_i32 s44, s44, 3 +; VI-NEXT: s_lshr_b32 s27, s7, 16 +; VI-NEXT: s_lshr_b32 s28, s6, 16 +; VI-NEXT: s_lshr_b32 s29, s8, 16 ; VI-NEXT: s_lshr_b32 s45, s9, 16 ; VI-NEXT: s_lshr_b32 s46, s10, 16 ; VI-NEXT: s_lshr_b32 s47, s11, 16 @@ -3820,117 +3876,117 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; VI-NEXT: s_lshr_b32 s57, s13, 16 ; VI-NEXT: s_lshr_b32 s58, s14, 16 ; VI-NEXT: s_lshr_b32 s59, s15, 16 -; VI-NEXT: s_lshr_b32 s60, s40, 16 -; VI-NEXT: s_lshr_b32 s61, s41, 16 -; VI-NEXT: s_lshr_b32 s62, s29, 16 -; VI-NEXT: s_lshr_b32 s63, s28, 16 -; VI-NEXT: s_lshr_b32 s72, s27, 16 -; VI-NEXT: s_lshr_b32 s73, s26, 16 -; VI-NEXT: s_lshr_b32 s74, s25, 16 -; VI-NEXT: s_lshr_b32 s75, s24, 16 -; VI-NEXT: s_lshr_b32 s76, s23, 16 -; VI-NEXT: s_lshr_b32 s77, s22, 16 -; VI-NEXT: s_lshr_b32 s78, s21, 16 -; VI-NEXT: s_lshr_b32 s79, s20, 16 -; VI-NEXT: s_lshr_b32 s88, s19, 16 -; VI-NEXT: s_lshr_b32 s89, s18, 16 -; VI-NEXT: s_lshr_b32 s90, s17, 16 -; VI-NEXT: s_lshr_b32 s91, s16, 16 +; VI-NEXT: s_lshr_b32 s60, s16, 16 +; VI-NEXT: s_lshr_b32 s61, s17, 16 +; VI-NEXT: s_lshr_b32 s62, s18, 16 +; VI-NEXT: s_lshr_b32 s63, s19, 16 +; VI-NEXT: s_lshr_b32 s72, s20, 16 +; VI-NEXT: s_lshr_b32 s73, s21, 16 +; VI-NEXT: s_lshr_b32 s74, s22, 16 +; VI-NEXT: s_lshr_b32 s75, s23, 16 +; VI-NEXT: s_lshr_b32 s76, s24, 16 +; VI-NEXT: s_lshr_b32 s77, s25, 16 +; VI-NEXT: s_lshr_b32 s78, s26, 16 +; VI-NEXT: s_lshr_b32 s79, s40, 16 +; VI-NEXT: s_lshr_b32 s88, s41, 16 +; VI-NEXT: s_lshr_b32 s89, s42, 16 +; VI-NEXT: s_lshr_b32 s90, s43, 16 +; VI-NEXT: s_lshr_b32 s91, s44, 16 ; VI-NEXT: .LBB13_3: ; %end -; VI-NEXT: s_and_b32 s4, 0xffff, s16 +; VI-NEXT: s_and_b32 s4, 0xffff, s44 ; VI-NEXT: s_lshl_b32 s5, s91, 16 ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_and_b32 s5, 0xffff, s17 -; VI-NEXT: s_lshl_b32 s16, s90, 16 -; VI-NEXT: s_or_b32 s5, s5, s16 -; VI-NEXT: s_and_b32 s16, 0xffff, s18 -; VI-NEXT: s_lshl_b32 s17, s89, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, 0xffff, s19 -; VI-NEXT: s_lshl_b32 s18, s88, 16 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s18, 0xffff, s20 -; VI-NEXT: s_lshl_b32 s19, s79, 16 -; VI-NEXT: s_or_b32 s18, s18, s19 -; VI-NEXT: s_and_b32 s19, 0xffff, s21 -; VI-NEXT: s_lshl_b32 s20, s78, 16 -; VI-NEXT: s_or_b32 s19, s19, s20 -; VI-NEXT: s_and_b32 s20, 0xffff, s22 -; VI-NEXT: s_lshl_b32 s21, s77, 16 -; VI-NEXT: s_or_b32 s20, s20, s21 -; VI-NEXT: s_and_b32 s21, 0xffff, s23 -; VI-NEXT: s_lshl_b32 s22, s76, 16 -; VI-NEXT: s_or_b32 s21, s21, s22 -; VI-NEXT: s_and_b32 s22, 0xffff, s24 -; VI-NEXT: s_lshl_b32 s23, s75, 16 -; VI-NEXT: s_or_b32 s22, s22, s23 -; VI-NEXT: s_and_b32 s23, 0xffff, s25 -; VI-NEXT: s_lshl_b32 s24, s74, 16 -; VI-NEXT: s_or_b32 s23, s23, s24 -; VI-NEXT: s_and_b32 s24, 0xffff, s26 -; VI-NEXT: s_lshl_b32 s25, s73, 16 -; VI-NEXT: s_or_b32 s24, s24, s25 -; VI-NEXT: s_and_b32 s25, 0xffff, s27 -; VI-NEXT: s_lshl_b32 s26, s72, 16 -; VI-NEXT: s_or_b32 s25, s25, s26 -; VI-NEXT: s_and_b32 s26, 0xffff, s28 -; VI-NEXT: s_lshl_b32 s27, s63, 16 -; VI-NEXT: s_or_b32 s26, s26, s27 -; VI-NEXT: s_and_b32 s27, 0xffff, s29 -; VI-NEXT: s_lshl_b32 s28, s62, 16 -; VI-NEXT: s_or_b32 s27, s27, s28 -; VI-NEXT: s_and_b32 s28, 0xffff, s41 -; VI-NEXT: s_lshl_b32 s29, s61, 16 -; VI-NEXT: s_or_b32 s28, s28, s29 -; VI-NEXT: s_and_b32 s29, 0xffff, s40 -; VI-NEXT: s_lshl_b32 s40, s60, 16 -; VI-NEXT: s_or_b32 s29, s29, s40 +; VI-NEXT: s_and_b32 s5, 0xffff, s43 +; VI-NEXT: s_lshl_b32 s43, s90, 16 +; VI-NEXT: s_or_b32 s5, s5, s43 +; VI-NEXT: s_and_b32 s42, 0xffff, s42 +; VI-NEXT: s_lshl_b32 s43, s89, 16 +; VI-NEXT: s_or_b32 s42, s42, s43 +; VI-NEXT: s_and_b32 s41, 0xffff, s41 +; VI-NEXT: s_lshl_b32 s43, s88, 16 +; VI-NEXT: s_or_b32 s41, s41, s43 +; VI-NEXT: s_and_b32 s40, 0xffff, s40 +; VI-NEXT: s_lshl_b32 s43, s79, 16 +; VI-NEXT: s_or_b32 s40, s40, s43 +; VI-NEXT: s_and_b32 s26, 0xffff, s26 +; VI-NEXT: s_lshl_b32 s43, s78, 16 +; VI-NEXT: s_or_b32 s26, s26, s43 +; VI-NEXT: s_and_b32 s25, 0xffff, s25 +; VI-NEXT: s_lshl_b32 s43, s77, 16 +; VI-NEXT: s_or_b32 s25, s25, s43 +; VI-NEXT: s_and_b32 s24, 0xffff, s24 +; VI-NEXT: s_lshl_b32 s43, s76, 16 +; VI-NEXT: s_or_b32 s24, s24, s43 +; VI-NEXT: s_and_b32 s23, 0xffff, s23 +; VI-NEXT: s_lshl_b32 s43, s75, 16 +; VI-NEXT: s_or_b32 s23, s23, s43 +; VI-NEXT: s_and_b32 s22, 0xffff, s22 +; VI-NEXT: s_lshl_b32 s43, s74, 16 +; VI-NEXT: s_or_b32 s22, s22, s43 +; VI-NEXT: s_and_b32 s21, 0xffff, s21 +; VI-NEXT: s_lshl_b32 s43, s73, 16 +; VI-NEXT: s_or_b32 s21, s21, s43 +; VI-NEXT: s_and_b32 s20, 0xffff, s20 +; VI-NEXT: s_lshl_b32 s43, s72, 16 +; VI-NEXT: s_or_b32 s20, s20, s43 +; VI-NEXT: s_and_b32 s19, 0xffff, s19 +; VI-NEXT: s_lshl_b32 s43, s63, 16 +; VI-NEXT: s_or_b32 s19, s19, s43 +; VI-NEXT: s_and_b32 s18, 0xffff, s18 +; VI-NEXT: s_lshl_b32 s43, s62, 16 +; VI-NEXT: s_or_b32 s18, s18, s43 +; VI-NEXT: s_and_b32 s17, 0xffff, s17 +; VI-NEXT: s_lshl_b32 s43, s61, 16 +; VI-NEXT: s_or_b32 s17, s17, s43 +; VI-NEXT: s_and_b32 s16, 0xffff, s16 +; VI-NEXT: s_lshl_b32 s43, s60, 16 +; VI-NEXT: s_or_b32 s16, s16, s43 ; VI-NEXT: s_and_b32 s15, 0xffff, s15 -; VI-NEXT: s_lshl_b32 s40, s59, 16 -; VI-NEXT: s_or_b32 s15, s15, s40 +; VI-NEXT: s_lshl_b32 s43, s59, 16 +; VI-NEXT: s_or_b32 s15, s15, s43 ; VI-NEXT: s_and_b32 s14, 0xffff, s14 -; VI-NEXT: s_lshl_b32 s40, s58, 16 -; VI-NEXT: s_or_b32 s14, s14, s40 +; VI-NEXT: s_lshl_b32 s43, s58, 16 +; VI-NEXT: s_or_b32 s14, s14, s43 ; VI-NEXT: s_and_b32 s13, 0xffff, s13 -; VI-NEXT: s_lshl_b32 s40, s57, 16 -; VI-NEXT: s_or_b32 s13, s13, s40 +; VI-NEXT: s_lshl_b32 s43, s57, 16 +; VI-NEXT: s_or_b32 s13, s13, s43 ; VI-NEXT: s_and_b32 s12, 0xffff, s12 -; VI-NEXT: s_lshl_b32 s40, s56, 16 -; VI-NEXT: s_or_b32 s12, s12, s40 +; VI-NEXT: s_lshl_b32 s43, s56, 16 +; VI-NEXT: s_or_b32 s12, s12, s43 ; VI-NEXT: s_and_b32 s11, 0xffff, s11 -; VI-NEXT: s_lshl_b32 s40, s47, 16 -; VI-NEXT: s_or_b32 s11, s11, s40 +; VI-NEXT: s_lshl_b32 s43, s47, 16 +; VI-NEXT: s_or_b32 s11, s11, s43 ; VI-NEXT: s_and_b32 s10, 0xffff, s10 -; VI-NEXT: s_lshl_b32 s40, s46, 16 -; VI-NEXT: s_or_b32 s10, s10, s40 +; VI-NEXT: s_lshl_b32 s43, s46, 16 +; VI-NEXT: s_or_b32 s10, s10, s43 ; VI-NEXT: s_and_b32 s9, 0xffff, s9 -; VI-NEXT: s_lshl_b32 s40, s45, 16 -; VI-NEXT: s_or_b32 s9, s9, s40 +; VI-NEXT: s_lshl_b32 s43, s45, 16 ; VI-NEXT: s_and_b32 s8, 0xffff, s8 -; VI-NEXT: s_lshl_b32 s40, s44, 16 -; VI-NEXT: s_or_b32 s8, s8, s40 +; VI-NEXT: s_lshl_b32 s29, s29, 16 ; VI-NEXT: s_and_b32 s6, 0xffff, s6 -; VI-NEXT: s_lshl_b32 s40, s43, 16 -; VI-NEXT: s_or_b32 s6, s6, s40 +; VI-NEXT: s_lshl_b32 s28, s28, 16 ; VI-NEXT: s_and_b32 s7, 0xffff, s7 -; VI-NEXT: s_lshl_b32 s40, s42, 16 -; VI-NEXT: s_or_b32 s7, s7, s40 +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s9, s9, s43 +; VI-NEXT: s_or_b32 s8, s8, s29 +; VI-NEXT: s_or_b32 s6, s6, s28 +; VI-NEXT: s_or_b32 s7, s7, s27 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s5 -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: v_mov_b32_e32 v3, s17 -; VI-NEXT: v_mov_b32_e32 v4, s18 -; VI-NEXT: v_mov_b32_e32 v5, s19 -; VI-NEXT: v_mov_b32_e32 v6, s20 -; VI-NEXT: v_mov_b32_e32 v7, s21 -; VI-NEXT: v_mov_b32_e32 v8, s22 -; VI-NEXT: v_mov_b32_e32 v9, s23 -; VI-NEXT: v_mov_b32_e32 v10, s24 -; VI-NEXT: v_mov_b32_e32 v11, s25 -; VI-NEXT: v_mov_b32_e32 v12, s26 -; VI-NEXT: v_mov_b32_e32 v13, s27 -; VI-NEXT: v_mov_b32_e32 v14, s28 -; VI-NEXT: v_mov_b32_e32 v15, s29 +; VI-NEXT: v_mov_b32_e32 v2, s42 +; VI-NEXT: v_mov_b32_e32 v3, s41 +; VI-NEXT: v_mov_b32_e32 v4, s40 +; VI-NEXT: v_mov_b32_e32 v5, s26 +; VI-NEXT: v_mov_b32_e32 v6, s25 +; VI-NEXT: v_mov_b32_e32 v7, s24 +; VI-NEXT: v_mov_b32_e32 v8, s23 +; VI-NEXT: v_mov_b32_e32 v9, s22 +; VI-NEXT: v_mov_b32_e32 v10, s21 +; VI-NEXT: v_mov_b32_e32 v11, s20 +; VI-NEXT: v_mov_b32_e32 v12, s19 +; VI-NEXT: v_mov_b32_e32 v13, s18 +; VI-NEXT: v_mov_b32_e32 v14, s17 +; VI-NEXT: v_mov_b32_e32 v15, s16 ; VI-NEXT: v_mov_b32_e32 v16, s15 ; VI-NEXT: v_mov_b32_e32 v17, s14 ; VI-NEXT: v_mov_b32_e32 v18, s13 @@ -3966,25 +4022,53 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; VI-NEXT: ; implicit-def: $sgpr47 ; VI-NEXT: ; implicit-def: $sgpr46 ; VI-NEXT: ; implicit-def: $sgpr45 -; VI-NEXT: ; implicit-def: $sgpr44 -; VI-NEXT: ; implicit-def: $sgpr43 -; VI-NEXT: ; implicit-def: $sgpr42 +; VI-NEXT: ; implicit-def: $sgpr29 +; VI-NEXT: ; implicit-def: $sgpr28 +; VI-NEXT: ; implicit-def: $sgpr27 ; VI-NEXT: s_branch .LBB13_2 ; ; GFX9-LABEL: bitcast_v26i32_to_v52i16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v13, s16 +; GFX9-NEXT: v_mov_b32_e32 v14, s17 +; GFX9-NEXT: v_mov_b32_e32 v15, s18 +; GFX9-NEXT: v_mov_b32_e32 v16, s19 +; GFX9-NEXT: v_mov_b32_e32 v17, s20 +; GFX9-NEXT: v_mov_b32_e32 v18, s21 +; GFX9-NEXT: v_mov_b32_e32 v19, s22 +; GFX9-NEXT: v_readfirstlane_b32 s6, v13 +; GFX9-NEXT: v_mov_b32_e32 v13, s23 +; GFX9-NEXT: v_readfirstlane_b32 s7, v14 +; GFX9-NEXT: v_mov_b32_e32 v14, s24 +; GFX9-NEXT: v_readfirstlane_b32 s8, v15 +; GFX9-NEXT: v_mov_b32_e32 v15, s25 +; GFX9-NEXT: v_readfirstlane_b32 s9, v16 +; GFX9-NEXT: v_mov_b32_e32 v16, s26 +; GFX9-NEXT: v_readfirstlane_b32 s10, v17 +; GFX9-NEXT: v_mov_b32_e32 v17, s27 +; GFX9-NEXT: v_readfirstlane_b32 s11, v18 +; GFX9-NEXT: v_mov_b32_e32 v18, s28 +; GFX9-NEXT: v_readfirstlane_b32 s12, v19 +; GFX9-NEXT: v_mov_b32_e32 v19, s29 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 -; GFX9-NEXT: v_readfirstlane_b32 s6, v0 -; GFX9-NEXT: v_readfirstlane_b32 s7, v1 -; GFX9-NEXT: v_readfirstlane_b32 s8, v2 -; GFX9-NEXT: v_readfirstlane_b32 s9, v3 -; GFX9-NEXT: v_readfirstlane_b32 s10, v4 -; GFX9-NEXT: v_readfirstlane_b32 s11, v5 -; GFX9-NEXT: v_readfirstlane_b32 s12, v6 -; GFX9-NEXT: v_readfirstlane_b32 s13, v7 -; GFX9-NEXT: v_readfirstlane_b32 s14, v8 -; GFX9-NEXT: v_readfirstlane_b32 s15, v9 +; GFX9-NEXT: v_readfirstlane_b32 s13, v13 +; GFX9-NEXT: v_readfirstlane_b32 s14, v14 +; GFX9-NEXT: v_readfirstlane_b32 s15, v15 +; GFX9-NEXT: v_readfirstlane_b32 s16, v16 +; GFX9-NEXT: v_readfirstlane_b32 s17, v17 +; GFX9-NEXT: v_readfirstlane_b32 s18, v18 +; GFX9-NEXT: v_readfirstlane_b32 s19, v19 +; GFX9-NEXT: v_readfirstlane_b32 s20, v0 +; GFX9-NEXT: v_readfirstlane_b32 s21, v1 +; GFX9-NEXT: v_readfirstlane_b32 s22, v2 +; GFX9-NEXT: v_readfirstlane_b32 s23, v3 +; GFX9-NEXT: v_readfirstlane_b32 s24, v4 +; GFX9-NEXT: v_readfirstlane_b32 s25, v5 +; GFX9-NEXT: v_readfirstlane_b32 s26, v6 +; GFX9-NEXT: v_readfirstlane_b32 s27, v7 +; GFX9-NEXT: v_readfirstlane_b32 s28, v8 +; GFX9-NEXT: v_readfirstlane_b32 s29, v9 ; GFX9-NEXT: v_readfirstlane_b32 s40, v10 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s41, v11 @@ -3992,44 +4076,34 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_lshr_b32 s42, s41, 16 ; GFX9-NEXT: s_lshr_b32 s43, s40, 16 -; GFX9-NEXT: s_lshr_b32 s44, s15, 16 -; GFX9-NEXT: s_lshr_b32 s45, s14, 16 -; GFX9-NEXT: s_lshr_b32 s46, s13, 16 -; GFX9-NEXT: s_lshr_b32 s47, s12, 16 -; GFX9-NEXT: s_lshr_b32 s56, s11, 16 -; GFX9-NEXT: s_lshr_b32 s57, s10, 16 -; GFX9-NEXT: s_lshr_b32 s58, s9, 16 -; GFX9-NEXT: s_lshr_b32 s59, s8, 16 -; GFX9-NEXT: s_lshr_b32 s60, s7, 16 -; GFX9-NEXT: s_lshr_b32 s61, s6, 16 -; GFX9-NEXT: s_lshr_b32 s62, s29, 16 -; GFX9-NEXT: s_lshr_b32 s63, s28, 16 -; GFX9-NEXT: s_lshr_b32 s72, s27, 16 -; GFX9-NEXT: s_lshr_b32 s73, s26, 16 -; GFX9-NEXT: s_lshr_b32 s74, s25, 16 -; GFX9-NEXT: s_lshr_b32 s75, s24, 16 -; GFX9-NEXT: s_lshr_b32 s76, s23, 16 -; GFX9-NEXT: s_lshr_b32 s77, s22, 16 -; GFX9-NEXT: s_lshr_b32 s78, s21, 16 -; GFX9-NEXT: s_lshr_b32 s79, s20, 16 -; GFX9-NEXT: s_lshr_b32 s88, s19, 16 -; GFX9-NEXT: s_lshr_b32 s89, s18, 16 -; GFX9-NEXT: s_lshr_b32 s90, s17, 16 -; GFX9-NEXT: s_lshr_b32 s91, s16, 16 +; GFX9-NEXT: s_lshr_b32 s44, s29, 16 +; GFX9-NEXT: s_lshr_b32 s45, s28, 16 +; GFX9-NEXT: s_lshr_b32 s46, s27, 16 +; GFX9-NEXT: s_lshr_b32 s47, s26, 16 +; GFX9-NEXT: s_lshr_b32 s56, s25, 16 +; GFX9-NEXT: s_lshr_b32 s57, s24, 16 +; GFX9-NEXT: s_lshr_b32 s58, s23, 16 +; GFX9-NEXT: s_lshr_b32 s59, s22, 16 +; GFX9-NEXT: s_lshr_b32 s60, s21, 16 +; GFX9-NEXT: s_lshr_b32 s61, s20, 16 +; GFX9-NEXT: s_lshr_b32 s62, s19, 16 +; GFX9-NEXT: s_lshr_b32 s63, s18, 16 +; GFX9-NEXT: s_lshr_b32 s72, s17, 16 +; GFX9-NEXT: s_lshr_b32 s73, s16, 16 +; GFX9-NEXT: s_lshr_b32 s74, s15, 16 +; GFX9-NEXT: s_lshr_b32 s75, s14, 16 +; GFX9-NEXT: s_lshr_b32 s76, s13, 16 +; GFX9-NEXT: s_lshr_b32 s77, s12, 16 +; GFX9-NEXT: s_lshr_b32 s78, s11, 16 +; GFX9-NEXT: s_lshr_b32 s79, s10, 16 +; GFX9-NEXT: s_lshr_b32 s88, s9, 16 +; GFX9-NEXT: s_lshr_b32 s89, s8, 16 +; GFX9-NEXT: s_lshr_b32 s90, s7, 16 +; GFX9-NEXT: s_lshr_b32 s91, s6, 16 ; GFX9-NEXT: s_cbranch_execnz .LBB13_3 ; GFX9-NEXT: .LBB13_2: ; %cmp.true ; GFX9-NEXT: s_add_i32 s41, s41, 3 ; GFX9-NEXT: s_add_i32 s40, s40, 3 -; GFX9-NEXT: s_add_i32 s15, s15, 3 -; GFX9-NEXT: s_add_i32 s14, s14, 3 -; GFX9-NEXT: s_add_i32 s13, s13, 3 -; GFX9-NEXT: s_add_i32 s12, s12, 3 -; GFX9-NEXT: s_add_i32 s11, s11, 3 -; GFX9-NEXT: s_add_i32 s10, s10, 3 -; GFX9-NEXT: s_add_i32 s9, s9, 3 -; GFX9-NEXT: s_add_i32 s8, s8, 3 -; GFX9-NEXT: s_add_i32 s7, s7, 3 -; GFX9-NEXT: s_add_i32 s6, s6, 3 ; GFX9-NEXT: s_add_i32 s29, s29, 3 ; GFX9-NEXT: s_add_i32 s28, s28, 3 ; GFX9-NEXT: s_add_i32 s27, s27, 3 @@ -4044,83 +4118,93 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; GFX9-NEXT: s_add_i32 s18, s18, 3 ; GFX9-NEXT: s_add_i32 s17, s17, 3 ; GFX9-NEXT: s_add_i32 s16, s16, 3 +; GFX9-NEXT: s_add_i32 s15, s15, 3 +; GFX9-NEXT: s_add_i32 s14, s14, 3 +; GFX9-NEXT: s_add_i32 s13, s13, 3 +; GFX9-NEXT: s_add_i32 s12, s12, 3 +; GFX9-NEXT: s_add_i32 s11, s11, 3 +; GFX9-NEXT: s_add_i32 s10, s10, 3 +; GFX9-NEXT: s_add_i32 s9, s9, 3 +; GFX9-NEXT: s_add_i32 s8, s8, 3 +; GFX9-NEXT: s_add_i32 s7, s7, 3 +; GFX9-NEXT: s_add_i32 s6, s6, 3 ; GFX9-NEXT: s_lshr_b32 s42, s41, 16 ; GFX9-NEXT: s_lshr_b32 s43, s40, 16 -; GFX9-NEXT: s_lshr_b32 s44, s15, 16 -; GFX9-NEXT: s_lshr_b32 s45, s14, 16 -; GFX9-NEXT: s_lshr_b32 s46, s13, 16 -; GFX9-NEXT: s_lshr_b32 s47, s12, 16 -; GFX9-NEXT: s_lshr_b32 s56, s11, 16 -; GFX9-NEXT: s_lshr_b32 s57, s10, 16 -; GFX9-NEXT: s_lshr_b32 s58, s9, 16 -; GFX9-NEXT: s_lshr_b32 s59, s8, 16 -; GFX9-NEXT: s_lshr_b32 s60, s7, 16 -; GFX9-NEXT: s_lshr_b32 s61, s6, 16 -; GFX9-NEXT: s_lshr_b32 s62, s29, 16 -; GFX9-NEXT: s_lshr_b32 s63, s28, 16 -; GFX9-NEXT: s_lshr_b32 s72, s27, 16 -; GFX9-NEXT: s_lshr_b32 s73, s26, 16 -; GFX9-NEXT: s_lshr_b32 s74, s25, 16 -; GFX9-NEXT: s_lshr_b32 s75, s24, 16 -; GFX9-NEXT: s_lshr_b32 s76, s23, 16 -; GFX9-NEXT: s_lshr_b32 s77, s22, 16 -; GFX9-NEXT: s_lshr_b32 s78, s21, 16 -; GFX9-NEXT: s_lshr_b32 s79, s20, 16 -; GFX9-NEXT: s_lshr_b32 s88, s19, 16 -; GFX9-NEXT: s_lshr_b32 s89, s18, 16 -; GFX9-NEXT: s_lshr_b32 s90, s17, 16 -; GFX9-NEXT: s_lshr_b32 s91, s16, 16 +; GFX9-NEXT: s_lshr_b32 s44, s29, 16 +; GFX9-NEXT: s_lshr_b32 s45, s28, 16 +; GFX9-NEXT: s_lshr_b32 s46, s27, 16 +; GFX9-NEXT: s_lshr_b32 s47, s26, 16 +; GFX9-NEXT: s_lshr_b32 s56, s25, 16 +; GFX9-NEXT: s_lshr_b32 s57, s24, 16 +; GFX9-NEXT: s_lshr_b32 s58, s23, 16 +; GFX9-NEXT: s_lshr_b32 s59, s22, 16 +; GFX9-NEXT: s_lshr_b32 s60, s21, 16 +; GFX9-NEXT: s_lshr_b32 s61, s20, 16 +; GFX9-NEXT: s_lshr_b32 s62, s19, 16 +; GFX9-NEXT: s_lshr_b32 s63, s18, 16 +; GFX9-NEXT: s_lshr_b32 s72, s17, 16 +; GFX9-NEXT: s_lshr_b32 s73, s16, 16 +; GFX9-NEXT: s_lshr_b32 s74, s15, 16 +; GFX9-NEXT: s_lshr_b32 s75, s14, 16 +; GFX9-NEXT: s_lshr_b32 s76, s13, 16 +; GFX9-NEXT: s_lshr_b32 s77, s12, 16 +; GFX9-NEXT: s_lshr_b32 s78, s11, 16 +; GFX9-NEXT: s_lshr_b32 s79, s10, 16 +; GFX9-NEXT: s_lshr_b32 s88, s9, 16 +; GFX9-NEXT: s_lshr_b32 s89, s8, 16 +; GFX9-NEXT: s_lshr_b32 s90, s7, 16 +; GFX9-NEXT: s_lshr_b32 s91, s6, 16 ; GFX9-NEXT: .LBB13_3: ; %end -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s16, s91 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s17, s90 -; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s89 -; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s88 -; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s79 -; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s78 -; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s77 -; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s76 -; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s75 -; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s74 -; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s73 -; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s72 -; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s63 -; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s62 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s61 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s60 -; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s59 -; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s58 -; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s57 -; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s56 -; GFX9-NEXT: s_pack_ll_b32_b16 s12, s12, s47 -; GFX9-NEXT: s_pack_ll_b32_b16 s13, s13, s46 -; GFX9-NEXT: s_pack_ll_b32_b16 s14, s14, s45 -; GFX9-NEXT: s_pack_ll_b32_b16 s15, s15, s44 +; GFX9-NEXT: s_pack_ll_b32_b16 s4, s6, s91 +; GFX9-NEXT: s_pack_ll_b32_b16 s5, s7, s90 +; GFX9-NEXT: s_pack_ll_b32_b16 s6, s8, s89 +; GFX9-NEXT: s_pack_ll_b32_b16 s7, s9, s88 +; GFX9-NEXT: s_pack_ll_b32_b16 s8, s10, s79 +; GFX9-NEXT: s_pack_ll_b32_b16 s9, s11, s78 +; GFX9-NEXT: s_pack_ll_b32_b16 s10, s12, s77 +; GFX9-NEXT: s_pack_ll_b32_b16 s11, s13, s76 +; GFX9-NEXT: s_pack_ll_b32_b16 s12, s14, s75 +; GFX9-NEXT: s_pack_ll_b32_b16 s13, s15, s74 +; GFX9-NEXT: s_pack_ll_b32_b16 s14, s16, s73 +; GFX9-NEXT: s_pack_ll_b32_b16 s15, s17, s72 +; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s63 +; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s62 +; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s61 +; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s60 +; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s59 +; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s58 +; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s57 +; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s56 +; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s47 +; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s46 +; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s45 +; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s44 ; GFX9-NEXT: s_pack_ll_b32_b16 s28, s40, s43 ; GFX9-NEXT: s_pack_ll_b32_b16 s29, s41, s42 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 -; GFX9-NEXT: v_mov_b32_e32 v2, s16 -; GFX9-NEXT: v_mov_b32_e32 v3, s17 -; GFX9-NEXT: v_mov_b32_e32 v4, s18 -; GFX9-NEXT: v_mov_b32_e32 v5, s19 -; GFX9-NEXT: v_mov_b32_e32 v6, s20 -; GFX9-NEXT: v_mov_b32_e32 v7, s21 -; GFX9-NEXT: v_mov_b32_e32 v8, s22 -; GFX9-NEXT: v_mov_b32_e32 v9, s23 -; GFX9-NEXT: v_mov_b32_e32 v10, s24 -; GFX9-NEXT: v_mov_b32_e32 v11, s25 -; GFX9-NEXT: v_mov_b32_e32 v12, s26 -; GFX9-NEXT: v_mov_b32_e32 v13, s27 -; GFX9-NEXT: v_mov_b32_e32 v14, s6 -; GFX9-NEXT: v_mov_b32_e32 v15, s7 -; GFX9-NEXT: v_mov_b32_e32 v16, s8 -; GFX9-NEXT: v_mov_b32_e32 v17, s9 -; GFX9-NEXT: v_mov_b32_e32 v18, s10 -; GFX9-NEXT: v_mov_b32_e32 v19, s11 -; GFX9-NEXT: v_mov_b32_e32 v20, s12 -; GFX9-NEXT: v_mov_b32_e32 v21, s13 -; GFX9-NEXT: v_mov_b32_e32 v22, s14 -; GFX9-NEXT: v_mov_b32_e32 v23, s15 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: v_mov_b32_e32 v4, s8 +; GFX9-NEXT: v_mov_b32_e32 v5, s9 +; GFX9-NEXT: v_mov_b32_e32 v6, s10 +; GFX9-NEXT: v_mov_b32_e32 v7, s11 +; GFX9-NEXT: v_mov_b32_e32 v8, s12 +; GFX9-NEXT: v_mov_b32_e32 v9, s13 +; GFX9-NEXT: v_mov_b32_e32 v10, s14 +; GFX9-NEXT: v_mov_b32_e32 v11, s15 +; GFX9-NEXT: v_mov_b32_e32 v12, s16 +; GFX9-NEXT: v_mov_b32_e32 v13, s17 +; GFX9-NEXT: v_mov_b32_e32 v14, s18 +; GFX9-NEXT: v_mov_b32_e32 v15, s19 +; GFX9-NEXT: v_mov_b32_e32 v16, s20 +; GFX9-NEXT: v_mov_b32_e32 v17, s21 +; GFX9-NEXT: v_mov_b32_e32 v18, s22 +; GFX9-NEXT: v_mov_b32_e32 v19, s23 +; GFX9-NEXT: v_mov_b32_e32 v20, s24 +; GFX9-NEXT: v_mov_b32_e32 v21, s25 +; GFX9-NEXT: v_mov_b32_e32 v22, s26 +; GFX9-NEXT: v_mov_b32_e32 v23, s27 ; GFX9-NEXT: v_mov_b32_e32 v24, s28 ; GFX9-NEXT: v_mov_b32_e32 v25, s29 ; GFX9-NEXT: s_setpc_b64 s[30:31] @@ -4156,41 +4240,68 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; GFX11-LABEL: bitcast_v26i32_to_v52i16_scalar: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v9, s0 :: v_dual_mov_b32 v10, s1 +; GFX11-NEXT: v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v12, s3 +; GFX11-NEXT: v_dual_mov_b32 v13, s16 :: v_dual_mov_b32 v14, s17 +; GFX11-NEXT: v_dual_mov_b32 v15, s18 :: v_dual_mov_b32 v16, s19 +; GFX11-NEXT: v_dual_mov_b32 v17, s20 :: v_dual_mov_b32 v18, s21 +; GFX11-NEXT: v_dual_mov_b32 v19, s22 :: v_dual_mov_b32 v20, s23 +; GFX11-NEXT: v_dual_mov_b32 v21, s24 :: v_dual_mov_b32 v22, s25 +; GFX11-NEXT: v_dual_mov_b32 v23, s26 :: v_dual_mov_b32 v24, s27 +; GFX11-NEXT: v_dual_mov_b32 v25, s28 :: v_dual_mov_b32 v26, s29 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 -; GFX11-NEXT: v_readfirstlane_b32 s4, v0 -; GFX11-NEXT: v_readfirstlane_b32 s5, v1 -; GFX11-NEXT: v_readfirstlane_b32 s6, v2 -; GFX11-NEXT: v_readfirstlane_b32 s7, v3 -; GFX11-NEXT: v_readfirstlane_b32 s8, v4 -; GFX11-NEXT: v_readfirstlane_b32 s9, v5 -; GFX11-NEXT: v_readfirstlane_b32 s11, v6 -; GFX11-NEXT: v_readfirstlane_b32 s10, v7 +; GFX11-NEXT: v_readfirstlane_b32 s0, v9 +; GFX11-NEXT: v_readfirstlane_b32 s1, v10 +; GFX11-NEXT: v_readfirstlane_b32 s2, v11 +; GFX11-NEXT: v_readfirstlane_b32 s3, v12 +; GFX11-NEXT: v_readfirstlane_b32 s4, v13 +; GFX11-NEXT: v_readfirstlane_b32 s5, v14 +; GFX11-NEXT: v_readfirstlane_b32 s6, v15 +; GFX11-NEXT: v_readfirstlane_b32 s7, v16 +; GFX11-NEXT: v_readfirstlane_b32 s8, v17 +; GFX11-NEXT: v_readfirstlane_b32 s9, v18 +; GFX11-NEXT: v_readfirstlane_b32 s10, v19 +; GFX11-NEXT: v_readfirstlane_b32 s11, v20 +; GFX11-NEXT: v_readfirstlane_b32 s12, v21 +; GFX11-NEXT: v_readfirstlane_b32 s13, v22 +; GFX11-NEXT: v_readfirstlane_b32 s14, v23 +; GFX11-NEXT: v_readfirstlane_b32 s15, v24 +; GFX11-NEXT: v_readfirstlane_b32 s16, v25 +; GFX11-NEXT: v_readfirstlane_b32 s17, v26 +; GFX11-NEXT: v_readfirstlane_b32 s18, v0 +; GFX11-NEXT: v_readfirstlane_b32 s19, v1 +; GFX11-NEXT: v_readfirstlane_b32 s20, v2 +; GFX11-NEXT: v_readfirstlane_b32 s21, v3 +; GFX11-NEXT: v_readfirstlane_b32 s22, v4 +; GFX11-NEXT: v_readfirstlane_b32 s23, v5 +; GFX11-NEXT: v_readfirstlane_b32 s25, v6 +; GFX11-NEXT: v_readfirstlane_b32 s24, v7 ; GFX11-NEXT: s_mov_b32 s78, 0 -; GFX11-NEXT: s_and_b32 s12, vcc_lo, exec_lo +; GFX11-NEXT: s_and_b32 s26, vcc_lo, exec_lo ; GFX11-NEXT: s_cbranch_scc0 .LBB13_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: s_lshr_b32 s12, s10, 16 -; GFX11-NEXT: s_lshr_b32 s13, s11, 16 -; GFX11-NEXT: s_lshr_b32 s14, s9, 16 -; GFX11-NEXT: s_lshr_b32 s15, s8, 16 -; GFX11-NEXT: s_lshr_b32 s40, s7, 16 -; GFX11-NEXT: s_lshr_b32 s41, s6, 16 -; GFX11-NEXT: s_lshr_b32 s42, s5, 16 -; GFX11-NEXT: s_lshr_b32 s43, s4, 16 -; GFX11-NEXT: s_lshr_b32 s44, s29, 16 -; GFX11-NEXT: s_lshr_b32 s45, s28, 16 -; GFX11-NEXT: s_lshr_b32 s46, s27, 16 -; GFX11-NEXT: s_lshr_b32 s47, s26, 16 -; GFX11-NEXT: s_lshr_b32 s56, s25, 16 -; GFX11-NEXT: s_lshr_b32 s57, s24, 16 -; GFX11-NEXT: s_lshr_b32 s58, s23, 16 -; GFX11-NEXT: s_lshr_b32 s59, s22, 16 -; GFX11-NEXT: s_lshr_b32 s60, s21, 16 -; GFX11-NEXT: s_lshr_b32 s61, s20, 16 -; GFX11-NEXT: s_lshr_b32 s62, s19, 16 -; GFX11-NEXT: s_lshr_b32 s63, s18, 16 -; GFX11-NEXT: s_lshr_b32 s72, s17, 16 -; GFX11-NEXT: s_lshr_b32 s73, s16, 16 +; GFX11-NEXT: s_lshr_b32 s26, s24, 16 +; GFX11-NEXT: s_lshr_b32 s27, s25, 16 +; GFX11-NEXT: s_lshr_b32 s28, s23, 16 +; GFX11-NEXT: s_lshr_b32 s29, s22, 16 +; GFX11-NEXT: s_lshr_b32 s40, s21, 16 +; GFX11-NEXT: s_lshr_b32 s41, s20, 16 +; GFX11-NEXT: s_lshr_b32 s42, s19, 16 +; GFX11-NEXT: s_lshr_b32 s43, s18, 16 +; GFX11-NEXT: s_lshr_b32 s44, s17, 16 +; GFX11-NEXT: s_lshr_b32 s45, s16, 16 +; GFX11-NEXT: s_lshr_b32 s46, s15, 16 +; GFX11-NEXT: s_lshr_b32 s47, s14, 16 +; GFX11-NEXT: s_lshr_b32 s56, s13, 16 +; GFX11-NEXT: s_lshr_b32 s57, s12, 16 +; GFX11-NEXT: s_lshr_b32 s58, s11, 16 +; GFX11-NEXT: s_lshr_b32 s59, s10, 16 +; GFX11-NEXT: s_lshr_b32 s60, s9, 16 +; GFX11-NEXT: s_lshr_b32 s61, s8, 16 +; GFX11-NEXT: s_lshr_b32 s62, s7, 16 +; GFX11-NEXT: s_lshr_b32 s63, s6, 16 +; GFX11-NEXT: s_lshr_b32 s72, s5, 16 +; GFX11-NEXT: s_lshr_b32 s73, s4, 16 ; GFX11-NEXT: s_lshr_b32 s74, s3, 16 ; GFX11-NEXT: s_lshr_b32 s75, s2, 16 ; GFX11-NEXT: s_lshr_b32 s76, s1, 16 @@ -4198,20 +4309,8 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s78 ; GFX11-NEXT: s_cbranch_vccnz .LBB13_3 ; GFX11-NEXT: .LBB13_2: ; %cmp.true -; GFX11-NEXT: s_add_i32 s10, s10, 3 -; GFX11-NEXT: s_add_i32 s11, s11, 3 -; GFX11-NEXT: s_add_i32 s9, s9, 3 -; GFX11-NEXT: s_add_i32 s8, s8, 3 -; GFX11-NEXT: s_add_i32 s7, s7, 3 -; GFX11-NEXT: s_add_i32 s6, s6, 3 -; GFX11-NEXT: s_add_i32 s5, s5, 3 -; GFX11-NEXT: s_add_i32 s4, s4, 3 -; GFX11-NEXT: s_add_i32 s29, s29, 3 -; GFX11-NEXT: s_add_i32 s28, s28, 3 -; GFX11-NEXT: s_add_i32 s27, s27, 3 -; GFX11-NEXT: s_add_i32 s26, s26, 3 -; GFX11-NEXT: s_add_i32 s25, s25, 3 ; GFX11-NEXT: s_add_i32 s24, s24, 3 +; GFX11-NEXT: s_add_i32 s25, s25, 3 ; GFX11-NEXT: s_add_i32 s23, s23, 3 ; GFX11-NEXT: s_add_i32 s22, s22, 3 ; GFX11-NEXT: s_add_i32 s21, s21, 3 @@ -4220,32 +4319,44 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; GFX11-NEXT: s_add_i32 s18, s18, 3 ; GFX11-NEXT: s_add_i32 s17, s17, 3 ; GFX11-NEXT: s_add_i32 s16, s16, 3 +; GFX11-NEXT: s_add_i32 s15, s15, 3 +; GFX11-NEXT: s_add_i32 s14, s14, 3 +; GFX11-NEXT: s_add_i32 s13, s13, 3 +; GFX11-NEXT: s_add_i32 s12, s12, 3 +; GFX11-NEXT: s_add_i32 s11, s11, 3 +; GFX11-NEXT: s_add_i32 s10, s10, 3 +; GFX11-NEXT: s_add_i32 s9, s9, 3 +; GFX11-NEXT: s_add_i32 s8, s8, 3 +; GFX11-NEXT: s_add_i32 s7, s7, 3 +; GFX11-NEXT: s_add_i32 s6, s6, 3 +; GFX11-NEXT: s_add_i32 s5, s5, 3 +; GFX11-NEXT: s_add_i32 s4, s4, 3 ; GFX11-NEXT: s_add_i32 s3, s3, 3 ; GFX11-NEXT: s_add_i32 s2, s2, 3 ; GFX11-NEXT: s_add_i32 s1, s1, 3 ; GFX11-NEXT: s_add_i32 s0, s0, 3 -; GFX11-NEXT: s_lshr_b32 s12, s10, 16 -; GFX11-NEXT: s_lshr_b32 s13, s11, 16 -; GFX11-NEXT: s_lshr_b32 s14, s9, 16 -; GFX11-NEXT: s_lshr_b32 s15, s8, 16 -; GFX11-NEXT: s_lshr_b32 s40, s7, 16 -; GFX11-NEXT: s_lshr_b32 s41, s6, 16 -; GFX11-NEXT: s_lshr_b32 s42, s5, 16 -; GFX11-NEXT: s_lshr_b32 s43, s4, 16 -; GFX11-NEXT: s_lshr_b32 s44, s29, 16 -; GFX11-NEXT: s_lshr_b32 s45, s28, 16 -; GFX11-NEXT: s_lshr_b32 s46, s27, 16 -; GFX11-NEXT: s_lshr_b32 s47, s26, 16 -; GFX11-NEXT: s_lshr_b32 s56, s25, 16 -; GFX11-NEXT: s_lshr_b32 s57, s24, 16 -; GFX11-NEXT: s_lshr_b32 s58, s23, 16 -; GFX11-NEXT: s_lshr_b32 s59, s22, 16 -; GFX11-NEXT: s_lshr_b32 s60, s21, 16 -; GFX11-NEXT: s_lshr_b32 s61, s20, 16 -; GFX11-NEXT: s_lshr_b32 s62, s19, 16 -; GFX11-NEXT: s_lshr_b32 s63, s18, 16 -; GFX11-NEXT: s_lshr_b32 s72, s17, 16 -; GFX11-NEXT: s_lshr_b32 s73, s16, 16 +; GFX11-NEXT: s_lshr_b32 s26, s24, 16 +; GFX11-NEXT: s_lshr_b32 s27, s25, 16 +; GFX11-NEXT: s_lshr_b32 s28, s23, 16 +; GFX11-NEXT: s_lshr_b32 s29, s22, 16 +; GFX11-NEXT: s_lshr_b32 s40, s21, 16 +; GFX11-NEXT: s_lshr_b32 s41, s20, 16 +; GFX11-NEXT: s_lshr_b32 s42, s19, 16 +; GFX11-NEXT: s_lshr_b32 s43, s18, 16 +; GFX11-NEXT: s_lshr_b32 s44, s17, 16 +; GFX11-NEXT: s_lshr_b32 s45, s16, 16 +; GFX11-NEXT: s_lshr_b32 s46, s15, 16 +; GFX11-NEXT: s_lshr_b32 s47, s14, 16 +; GFX11-NEXT: s_lshr_b32 s56, s13, 16 +; GFX11-NEXT: s_lshr_b32 s57, s12, 16 +; GFX11-NEXT: s_lshr_b32 s58, s11, 16 +; GFX11-NEXT: s_lshr_b32 s59, s10, 16 +; GFX11-NEXT: s_lshr_b32 s60, s9, 16 +; GFX11-NEXT: s_lshr_b32 s61, s8, 16 +; GFX11-NEXT: s_lshr_b32 s62, s7, 16 +; GFX11-NEXT: s_lshr_b32 s63, s6, 16 +; GFX11-NEXT: s_lshr_b32 s72, s5, 16 +; GFX11-NEXT: s_lshr_b32 s73, s4, 16 ; GFX11-NEXT: s_lshr_b32 s74, s3, 16 ; GFX11-NEXT: s_lshr_b32 s75, s2, 16 ; GFX11-NEXT: s_lshr_b32 s76, s1, 16 @@ -4256,41 +4367,41 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s76 ; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s75 ; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s74 -; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s73 -; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s72 -; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s63 -; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s62 -; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s61 -; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s60 -; GFX11-NEXT: s_pack_ll_b32_b16 s22, s22, s59 -; GFX11-NEXT: s_pack_ll_b32_b16 s23, s23, s58 -; GFX11-NEXT: s_pack_ll_b32_b16 s24, s24, s57 -; GFX11-NEXT: s_pack_ll_b32_b16 s25, s25, s56 -; GFX11-NEXT: s_pack_ll_b32_b16 s26, s26, s47 -; GFX11-NEXT: s_pack_ll_b32_b16 s27, s27, s46 -; GFX11-NEXT: s_pack_ll_b32_b16 s28, s28, s45 -; GFX11-NEXT: s_pack_ll_b32_b16 s29, s29, s44 -; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s43 -; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s42 -; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s41 -; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s40 -; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s15 -; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s14 -; GFX11-NEXT: s_pack_ll_b32_b16 s11, s11, s13 -; GFX11-NEXT: s_pack_ll_b32_b16 s10, s10, s12 +; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s73 +; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s72 +; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s63 +; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s62 +; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s61 +; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s60 +; GFX11-NEXT: s_pack_ll_b32_b16 s10, s10, s59 +; GFX11-NEXT: s_pack_ll_b32_b16 s11, s11, s58 +; GFX11-NEXT: s_pack_ll_b32_b16 s12, s12, s57 +; GFX11-NEXT: s_pack_ll_b32_b16 s13, s13, s56 +; GFX11-NEXT: s_pack_ll_b32_b16 s14, s14, s47 +; GFX11-NEXT: s_pack_ll_b32_b16 s15, s15, s46 +; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s45 +; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s44 +; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s43 +; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s42 +; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s41 +; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s40 +; GFX11-NEXT: s_pack_ll_b32_b16 s22, s22, s29 +; GFX11-NEXT: s_pack_ll_b32_b16 s23, s23, s28 +; GFX11-NEXT: s_pack_ll_b32_b16 s25, s25, s27 +; GFX11-NEXT: s_pack_ll_b32_b16 s24, s24, s26 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 -; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 -; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 -; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 -; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 -; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 -; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 -; GFX11-NEXT: v_dual_mov_b32 v18, s4 :: v_dual_mov_b32 v19, s5 -; GFX11-NEXT: v_dual_mov_b32 v20, s6 :: v_dual_mov_b32 v21, s7 -; GFX11-NEXT: v_dual_mov_b32 v22, s8 :: v_dual_mov_b32 v23, s9 -; GFX11-NEXT: v_dual_mov_b32 v24, s11 :: v_dual_mov_b32 v25, s10 +; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19 +; GFX11-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v21, s21 +; GFX11-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v23, s23 +; GFX11-NEXT: v_dual_mov_b32 v24, s25 :: v_dual_mov_b32 v25, s24 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: .LBB13_4: ; GFX11-NEXT: ; implicit-def: $sgpr77 @@ -4315,10 +4426,10 @@ define inreg <52 x i16> @bitcast_v26i32_to_v52i16_scalar(<26 x i32> inreg %a, i3 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr41 ; GFX11-NEXT: ; implicit-def: $sgpr40 -; GFX11-NEXT: ; implicit-def: $sgpr15 -; GFX11-NEXT: ; implicit-def: $sgpr14 -; GFX11-NEXT: ; implicit-def: $sgpr13 -; GFX11-NEXT: ; implicit-def: $sgpr12 +; GFX11-NEXT: ; implicit-def: $sgpr29 +; GFX11-NEXT: ; implicit-def: $sgpr28 +; GFX11-NEXT: ; implicit-def: $sgpr27 +; GFX11-NEXT: ; implicit-def: $sgpr26 ; GFX11-NEXT: s_branch .LBB13_2 %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -4341,6 +4452,19 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) { ; SI-LABEL: bitcast_v52i16_to_v26i32: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v50, v10 +; SI-NEXT: v_mov_b32_e32 v51, v8 +; SI-NEXT: v_mov_b32_e32 v52, v6 +; SI-NEXT: v_mov_b32_e32 v53, v4 +; SI-NEXT: v_mov_b32_e32 v54, v2 +; SI-NEXT: v_mov_b32_e32 v55, v0 +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:48 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:40 +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24 +; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:16 +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:12 +; SI-NEXT: v_mov_b32_e32 v49, v12 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill @@ -4366,19 +4490,6 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v50, v10 -; SI-NEXT: v_mov_b32_e32 v51, v8 -; SI-NEXT: v_mov_b32_e32 v52, v6 -; SI-NEXT: v_mov_b32_e32 v53, v4 -; SI-NEXT: v_mov_b32_e32 v54, v2 -; SI-NEXT: v_mov_b32_e32 v55, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:48 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:40 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32 -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24 -; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:16 -; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:12 -; SI-NEXT: v_mov_b32_e32 v49, v12 ; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v1 ; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v3 ; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v5 @@ -4394,17 +4505,12 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) { ; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v25 ; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v27 ; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v29 -; SI-NEXT: s_waitcnt vmcnt(5) +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v0 -; SI-NEXT: s_waitcnt vmcnt(4) ; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v2 -; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v4 -; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v6 -; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v8 -; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:8 @@ -4429,9 +4535,10 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) { ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72 ; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:68 -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v18 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 @@ -4443,10 +4550,9 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) { ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:56 ; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:52 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v22 ; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v22 +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:44 @@ -4766,7 +4872,7 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) { ; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21 ; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22 ; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23 -; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24 +; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v24 ; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25 ; SI-NEXT: .LBB14_4: ; %end ; SI-NEXT: s_or_b64 exec, exec, s[4:5] @@ -5032,7 +5138,6 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v57, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v25 -; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v24 @@ -5099,6 +5204,7 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v56 ; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v57 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 +; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -5231,6 +5337,9 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] ; GFX9-NEXT: s_cbranch_execz .LBB14_4 ; GFX9-NEXT: ; %bb.3: ; %cmp.true +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload @@ -5245,9 +5354,6 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v34, v57, s6 ; GFX9-NEXT: v_perm_b32 v1, v62, v56, s6 ; GFX9-NEXT: v_perm_b32 v2, v33, v47, s6 @@ -5266,6 +5372,10 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] +; GFX9-NEXT: s_waitcnt vmcnt(14) +; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; GFX9-NEXT: s_waitcnt vmcnt(15) ; GFX9-NEXT: v_perm_b32 v9, v9, v40, s6 ; GFX9-NEXT: s_waitcnt vmcnt(14) @@ -5294,10 +5404,6 @@ define <26 x i32> @bitcast_v52i16_to_v26i32(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: v_perm_b32 v21, v21, v36, s6 ; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: v_perm_b32 v22, v22, v35, s6 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] @@ -6287,294 +6393,109 @@ define inreg <26 x i32> @bitcast_v52i16_to_v26i32_scalar(<52 x i16> inreg %a, i3 ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v191, v1 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v185, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB15_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB15_3 ; GFX11-TRUE16-NEXT: .LBB15_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s40, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s41, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v185, v185, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v191, v191, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v190, v190, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v189, v189, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v188, v188, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v187, v187, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v186, v186, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, s6, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, s7, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, s8, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s9, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, s10, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, s11, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, s12, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, s13, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s14, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, s15, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, s16, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s0, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s1, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s2, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, s3, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, s4, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v35, s5, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v44, s6, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v54, s7, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v65, s8, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v77, s9, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v90, s10, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v104, s11, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v119, s12, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v135, s13, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v152, s14, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v170, s15, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: .LBB15_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v170 :: v_dual_mov_b32 v18, v185 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v191 :: v_dual_mov_b32 v20, v190 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v189 :: v_dual_mov_b32 v22, v188 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v187 :: v_dual_mov_b32 v24, v186 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v191, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v190, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v189, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v188, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v187, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:316 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v14, v119 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB15_4: -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v53, v25 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v25, v53 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB15_2 ; ; GFX11-FAKE16-LABEL: bitcast_v52i16_to_v26i32_scalar: @@ -7832,9 +7753,37 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; SI-LABEL: bitcast_v26i32_to_v52f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v14, s16 +; SI-NEXT: v_mov_b32_e32 v15, s17 +; SI-NEXT: v_mov_b32_e32 v16, s18 +; SI-NEXT: v_mov_b32_e32 v17, s19 +; SI-NEXT: v_mov_b32_e32 v18, s20 +; SI-NEXT: v_mov_b32_e32 v19, s21 +; SI-NEXT: v_readfirstlane_b32 s40, v14 +; SI-NEXT: v_mov_b32_e32 v14, s22 +; SI-NEXT: v_readfirstlane_b32 s41, v15 +; SI-NEXT: v_mov_b32_e32 v15, s23 +; SI-NEXT: v_readfirstlane_b32 s23, v16 +; SI-NEXT: v_mov_b32_e32 v16, s24 +; SI-NEXT: v_readfirstlane_b32 s24, v17 +; SI-NEXT: v_mov_b32_e32 v17, s25 +; SI-NEXT: v_readfirstlane_b32 s25, v18 +; SI-NEXT: v_mov_b32_e32 v18, s26 +; SI-NEXT: v_readfirstlane_b32 s26, v19 +; SI-NEXT: v_mov_b32_e32 v19, s27 +; SI-NEXT: v_readfirstlane_b32 s27, v14 +; SI-NEXT: v_mov_b32_e32 v14, s28 +; SI-NEXT: v_readfirstlane_b32 s28, v15 +; SI-NEXT: v_mov_b32_e32 v15, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 -; SI-NEXT: v_readfirstlane_b32 s41, v1 -; SI-NEXT: v_readfirstlane_b32 s40, v2 +; SI-NEXT: v_readfirstlane_b32 s29, v16 +; SI-NEXT: v_readfirstlane_b32 s22, v17 +; SI-NEXT: v_readfirstlane_b32 s21, v18 +; SI-NEXT: v_readfirstlane_b32 s20, v19 +; SI-NEXT: v_readfirstlane_b32 s19, v14 +; SI-NEXT: v_readfirstlane_b32 s18, v15 +; SI-NEXT: v_readfirstlane_b32 s17, v1 +; SI-NEXT: v_readfirstlane_b32 s16, v2 ; SI-NEXT: v_readfirstlane_b32 s15, v3 ; SI-NEXT: v_readfirstlane_b32 s14, v4 ; SI-NEXT: v_readfirstlane_b32 s13, v5 @@ -7873,39 +7822,39 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v16, s4 ; SI-NEXT: s_lshr_b32 s4, s15, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v18, s4 -; SI-NEXT: s_lshr_b32 s4, s40, 16 +; SI-NEXT: s_lshr_b32 s4, s16, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v20, s4 -; SI-NEXT: s_lshr_b32 s4, s41, 16 +; SI-NEXT: s_lshr_b32 s4, s17, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v22, s4 -; SI-NEXT: s_lshr_b32 s4, s29, 16 +; SI-NEXT: s_lshr_b32 s4, s18, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v24, s4 -; SI-NEXT: s_lshr_b32 s4, s28, 16 +; SI-NEXT: s_lshr_b32 s4, s19, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v26, s4 -; SI-NEXT: s_lshr_b32 s4, s27, 16 +; SI-NEXT: s_lshr_b32 s4, s20, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v28, s4 -; SI-NEXT: s_lshr_b32 s4, s26, 16 +; SI-NEXT: s_lshr_b32 s4, s21, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v31, s4 -; SI-NEXT: s_lshr_b32 s4, s25, 16 +; SI-NEXT: s_lshr_b32 s4, s22, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v33, s4 -; SI-NEXT: s_lshr_b32 s4, s24, 16 +; SI-NEXT: s_lshr_b32 s4, s29, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v35, s4 -; SI-NEXT: s_lshr_b32 s4, s23, 16 +; SI-NEXT: s_lshr_b32 s4, s28, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v37, s4 -; SI-NEXT: s_lshr_b32 s4, s22, 16 +; SI-NEXT: s_lshr_b32 s4, s27, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v39, s4 -; SI-NEXT: s_lshr_b32 s4, s21, 16 +; SI-NEXT: s_lshr_b32 s4, s26, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v49, s4 -; SI-NEXT: s_lshr_b32 s4, s20, 16 +; SI-NEXT: s_lshr_b32 s4, s25, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v51, s4 -; SI-NEXT: s_lshr_b32 s4, s19, 16 +; SI-NEXT: s_lshr_b32 s4, s24, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v54, s4 -; SI-NEXT: s_lshr_b32 s4, s18, 16 +; SI-NEXT: s_lshr_b32 s4, s23, 16 ; SI-NEXT: s_waitcnt expcnt(4) ; SI-NEXT: v_cvt_f32_f16_e32 v40, s4 -; SI-NEXT: s_lshr_b32 s4, s17, 16 +; SI-NEXT: s_lshr_b32 s4, s41, 16 ; SI-NEXT: s_waitcnt expcnt(2) ; SI-NEXT: v_cvt_f32_f16_e32 v42, s4 -; SI-NEXT: s_lshr_b32 s4, s16, 16 +; SI-NEXT: s_lshr_b32 s4, s40, 16 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f32_f16_e32 v44, s4 ; SI-NEXT: v_cvt_f32_f16_e32 v4, s9 @@ -7918,31 +7867,26 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v17, s13 ; SI-NEXT: v_cvt_f32_f16_e32 v19, s14 ; SI-NEXT: v_cvt_f32_f16_e32 v21, s15 -; SI-NEXT: v_cvt_f32_f16_e32 v23, s40 -; SI-NEXT: v_cvt_f32_f16_e32 v25, s41 -; SI-NEXT: v_cvt_f32_f16_e32 v27, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s28 -; SI-NEXT: v_cvt_f32_f16_e32 v30, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v32, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v34, s25 -; SI-NEXT: v_cvt_f32_f16_e32 v36, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v38, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v48, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v50, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v52, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v53, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v55, s18 -; SI-NEXT: v_cvt_f32_f16_e32 v41, s17 -; SI-NEXT: v_cvt_f32_f16_e32 v43, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v23, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v25, s17 +; SI-NEXT: v_cvt_f32_f16_e32 v27, s18 +; SI-NEXT: v_cvt_f32_f16_e32 v29, s19 +; SI-NEXT: v_cvt_f32_f16_e32 v30, s20 +; SI-NEXT: v_cvt_f32_f16_e32 v32, s21 +; SI-NEXT: v_cvt_f32_f16_e32 v34, s22 +; SI-NEXT: v_cvt_f32_f16_e32 v36, s29 +; SI-NEXT: v_cvt_f32_f16_e32 v38, s28 +; SI-NEXT: v_cvt_f32_f16_e32 v48, s27 +; SI-NEXT: v_cvt_f32_f16_e32 v50, s26 +; SI-NEXT: v_cvt_f32_f16_e32 v52, s25 +; SI-NEXT: v_cvt_f32_f16_e32 v53, s24 +; SI-NEXT: v_cvt_f32_f16_e32 v55, s23 +; SI-NEXT: v_cvt_f32_f16_e32 v41, s41 +; SI-NEXT: v_cvt_f32_f16_e32 v43, s40 ; SI-NEXT: s_cbranch_execnz .LBB17_3 ; SI-NEXT: .LBB17_2: ; %cmp.true -; SI-NEXT: s_add_i32 s16, s16, 3 -; SI-NEXT: s_add_i32 s17, s17, 3 -; SI-NEXT: s_add_i32 s18, s18, 3 -; SI-NEXT: s_add_i32 s19, s19, 3 -; SI-NEXT: s_add_i32 s20, s20, 3 -; SI-NEXT: s_add_i32 s21, s21, 3 -; SI-NEXT: s_add_i32 s22, s22, 3 +; SI-NEXT: s_add_i32 s40, s40, 3 +; SI-NEXT: s_add_i32 s41, s41, 3 ; SI-NEXT: s_add_i32 s23, s23, 3 ; SI-NEXT: s_add_i32 s24, s24, 3 ; SI-NEXT: s_add_i32 s25, s25, 3 @@ -7950,8 +7894,13 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; SI-NEXT: s_add_i32 s27, s27, 3 ; SI-NEXT: s_add_i32 s28, s28, 3 ; SI-NEXT: s_add_i32 s29, s29, 3 -; SI-NEXT: s_add_i32 s41, s41, 3 -; SI-NEXT: s_add_i32 s40, s40, 3 +; SI-NEXT: s_add_i32 s22, s22, 3 +; SI-NEXT: s_add_i32 s21, s21, 3 +; SI-NEXT: s_add_i32 s20, s20, 3 +; SI-NEXT: s_add_i32 s19, s19, 3 +; SI-NEXT: s_add_i32 s18, s18, 3 +; SI-NEXT: s_add_i32 s17, s17, 3 +; SI-NEXT: s_add_i32 s16, s16, 3 ; SI-NEXT: s_add_i32 s15, s15, 3 ; SI-NEXT: s_add_i32 s14, s14, 3 ; SI-NEXT: s_add_i32 s13, s13, 3 @@ -7962,22 +7911,22 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; SI-NEXT: s_add_i32 s7, s7, 3 ; SI-NEXT: s_add_i32 s6, s6, 3 ; SI-NEXT: s_add_i32 s9, s9, 3 -; SI-NEXT: s_lshr_b32 s4, s16, 16 -; SI-NEXT: s_lshr_b32 s5, s17, 16 -; SI-NEXT: s_lshr_b32 s42, s18, 16 -; SI-NEXT: s_lshr_b32 s43, s19, 16 -; SI-NEXT: s_lshr_b32 s44, s20, 16 -; SI-NEXT: s_lshr_b32 s45, s21, 16 -; SI-NEXT: s_lshr_b32 s46, s22, 16 -; SI-NEXT: s_lshr_b32 s47, s23, 16 -; SI-NEXT: s_lshr_b32 s56, s24, 16 -; SI-NEXT: s_lshr_b32 s57, s25, 16 -; SI-NEXT: s_lshr_b32 s58, s26, 16 -; SI-NEXT: s_lshr_b32 s59, s27, 16 -; SI-NEXT: s_lshr_b32 s60, s28, 16 -; SI-NEXT: s_lshr_b32 s61, s29, 16 -; SI-NEXT: s_lshr_b32 s62, s41, 16 -; SI-NEXT: s_lshr_b32 s63, s40, 16 +; SI-NEXT: s_lshr_b32 s4, s40, 16 +; SI-NEXT: s_lshr_b32 s5, s41, 16 +; SI-NEXT: s_lshr_b32 s42, s23, 16 +; SI-NEXT: s_lshr_b32 s43, s24, 16 +; SI-NEXT: s_lshr_b32 s44, s25, 16 +; SI-NEXT: s_lshr_b32 s45, s26, 16 +; SI-NEXT: s_lshr_b32 s46, s27, 16 +; SI-NEXT: s_lshr_b32 s47, s28, 16 +; SI-NEXT: s_lshr_b32 s56, s29, 16 +; SI-NEXT: s_lshr_b32 s57, s22, 16 +; SI-NEXT: s_lshr_b32 s58, s21, 16 +; SI-NEXT: s_lshr_b32 s59, s20, 16 +; SI-NEXT: s_lshr_b32 s60, s19, 16 +; SI-NEXT: s_lshr_b32 s61, s18, 16 +; SI-NEXT: s_lshr_b32 s62, s17, 16 +; SI-NEXT: s_lshr_b32 s63, s16, 16 ; SI-NEXT: s_lshr_b32 s72, s15, 16 ; SI-NEXT: s_lshr_b32 s73, s14, 16 ; SI-NEXT: s_lshr_b32 s74, s13, 16 @@ -7998,24 +7947,24 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v17, s13 ; SI-NEXT: v_cvt_f32_f16_e32 v19, s14 ; SI-NEXT: v_cvt_f32_f16_e32 v21, s15 -; SI-NEXT: v_cvt_f32_f16_e32 v23, s40 -; SI-NEXT: v_cvt_f32_f16_e32 v25, s41 -; SI-NEXT: v_cvt_f32_f16_e32 v27, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s28 -; SI-NEXT: v_cvt_f32_f16_e32 v30, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v32, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v34, s25 -; SI-NEXT: v_cvt_f32_f16_e32 v36, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v38, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v48, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v50, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v52, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v53, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v55, s18 +; SI-NEXT: v_cvt_f32_f16_e32 v23, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v25, s17 +; SI-NEXT: v_cvt_f32_f16_e32 v27, s18 +; SI-NEXT: v_cvt_f32_f16_e32 v29, s19 +; SI-NEXT: v_cvt_f32_f16_e32 v30, s20 +; SI-NEXT: v_cvt_f32_f16_e32 v32, s21 +; SI-NEXT: v_cvt_f32_f16_e32 v34, s22 +; SI-NEXT: v_cvt_f32_f16_e32 v36, s29 +; SI-NEXT: v_cvt_f32_f16_e32 v38, s28 +; SI-NEXT: v_cvt_f32_f16_e32 v48, s27 +; SI-NEXT: v_cvt_f32_f16_e32 v50, s26 +; SI-NEXT: v_cvt_f32_f16_e32 v52, s25 +; SI-NEXT: v_cvt_f32_f16_e32 v53, s24 +; SI-NEXT: v_cvt_f32_f16_e32 v55, s23 ; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_cvt_f32_f16_e32 v41, s17 +; SI-NEXT: v_cvt_f32_f16_e32 v41, s41 ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_cvt_f32_f16_e32 v43, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v43, s40 ; SI-NEXT: v_cvt_f32_f16_e32 v1, s89 ; SI-NEXT: v_cvt_f32_f16_e32 v2, s88 ; SI-NEXT: v_cvt_f32_f16_e32 v3, s79 @@ -8290,9 +8239,37 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; VI-LABEL: bitcast_v26i32_to_v52f16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v13, s16 +; VI-NEXT: v_mov_b32_e32 v14, s17 +; VI-NEXT: v_mov_b32_e32 v15, s18 +; VI-NEXT: v_mov_b32_e32 v16, s19 +; VI-NEXT: v_mov_b32_e32 v17, s20 +; VI-NEXT: v_mov_b32_e32 v18, s21 +; VI-NEXT: v_mov_b32_e32 v19, s22 +; VI-NEXT: v_readfirstlane_b32 s44, v13 +; VI-NEXT: v_mov_b32_e32 v13, s23 +; VI-NEXT: v_readfirstlane_b32 s43, v14 +; VI-NEXT: v_mov_b32_e32 v14, s24 +; VI-NEXT: v_readfirstlane_b32 s42, v15 +; VI-NEXT: v_mov_b32_e32 v15, s25 +; VI-NEXT: v_readfirstlane_b32 s41, v16 +; VI-NEXT: v_mov_b32_e32 v16, s26 +; VI-NEXT: v_readfirstlane_b32 s40, v17 +; VI-NEXT: v_mov_b32_e32 v17, s27 +; VI-NEXT: v_readfirstlane_b32 s26, v18 +; VI-NEXT: v_mov_b32_e32 v18, s28 +; VI-NEXT: v_readfirstlane_b32 s25, v19 +; VI-NEXT: v_mov_b32_e32 v19, s29 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 -; VI-NEXT: v_readfirstlane_b32 s41, v0 -; VI-NEXT: v_readfirstlane_b32 s40, v1 +; VI-NEXT: v_readfirstlane_b32 s24, v13 +; VI-NEXT: v_readfirstlane_b32 s23, v14 +; VI-NEXT: v_readfirstlane_b32 s22, v15 +; VI-NEXT: v_readfirstlane_b32 s21, v16 +; VI-NEXT: v_readfirstlane_b32 s20, v17 +; VI-NEXT: v_readfirstlane_b32 s19, v18 +; VI-NEXT: v_readfirstlane_b32 s18, v19 +; VI-NEXT: v_readfirstlane_b32 s17, v0 +; VI-NEXT: v_readfirstlane_b32 s16, v1 ; VI-NEXT: v_readfirstlane_b32 s15, v2 ; VI-NEXT: v_readfirstlane_b32 s14, v3 ; VI-NEXT: v_readfirstlane_b32 s13, v4 @@ -8306,9 +8283,9 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; VI-NEXT: v_readfirstlane_b32 s7, v11 ; VI-NEXT: s_cbranch_scc0 .LBB17_4 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_lshr_b32 s42, s7, 16 -; VI-NEXT: s_lshr_b32 s43, s6, 16 -; VI-NEXT: s_lshr_b32 s44, s8, 16 +; VI-NEXT: s_lshr_b32 s27, s7, 16 +; VI-NEXT: s_lshr_b32 s28, s6, 16 +; VI-NEXT: s_lshr_b32 s29, s8, 16 ; VI-NEXT: s_lshr_b32 s45, s9, 16 ; VI-NEXT: s_lshr_b32 s46, s10, 16 ; VI-NEXT: s_lshr_b32 s47, s11, 16 @@ -8316,22 +8293,22 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; VI-NEXT: s_lshr_b32 s57, s13, 16 ; VI-NEXT: s_lshr_b32 s58, s14, 16 ; VI-NEXT: s_lshr_b32 s59, s15, 16 -; VI-NEXT: s_lshr_b32 s60, s40, 16 -; VI-NEXT: s_lshr_b32 s61, s41, 16 -; VI-NEXT: s_lshr_b32 s62, s29, 16 -; VI-NEXT: s_lshr_b32 s63, s28, 16 -; VI-NEXT: s_lshr_b32 s72, s27, 16 -; VI-NEXT: s_lshr_b32 s73, s26, 16 -; VI-NEXT: s_lshr_b32 s74, s25, 16 -; VI-NEXT: s_lshr_b32 s75, s24, 16 -; VI-NEXT: s_lshr_b32 s76, s23, 16 -; VI-NEXT: s_lshr_b32 s77, s22, 16 -; VI-NEXT: s_lshr_b32 s78, s21, 16 -; VI-NEXT: s_lshr_b32 s79, s20, 16 -; VI-NEXT: s_lshr_b32 s88, s19, 16 -; VI-NEXT: s_lshr_b32 s89, s18, 16 -; VI-NEXT: s_lshr_b32 s90, s17, 16 -; VI-NEXT: s_lshr_b32 s91, s16, 16 +; VI-NEXT: s_lshr_b32 s60, s16, 16 +; VI-NEXT: s_lshr_b32 s61, s17, 16 +; VI-NEXT: s_lshr_b32 s62, s18, 16 +; VI-NEXT: s_lshr_b32 s63, s19, 16 +; VI-NEXT: s_lshr_b32 s72, s20, 16 +; VI-NEXT: s_lshr_b32 s73, s21, 16 +; VI-NEXT: s_lshr_b32 s74, s22, 16 +; VI-NEXT: s_lshr_b32 s75, s23, 16 +; VI-NEXT: s_lshr_b32 s76, s24, 16 +; VI-NEXT: s_lshr_b32 s77, s25, 16 +; VI-NEXT: s_lshr_b32 s78, s26, 16 +; VI-NEXT: s_lshr_b32 s79, s40, 16 +; VI-NEXT: s_lshr_b32 s88, s41, 16 +; VI-NEXT: s_lshr_b32 s89, s42, 16 +; VI-NEXT: s_lshr_b32 s90, s43, 16 +; VI-NEXT: s_lshr_b32 s91, s44, 16 ; VI-NEXT: s_cbranch_execnz .LBB17_3 ; VI-NEXT: .LBB17_2: ; %cmp.true ; VI-NEXT: s_add_i32 s7, s7, 3 @@ -8344,25 +8321,25 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; VI-NEXT: s_add_i32 s13, s13, 3 ; VI-NEXT: s_add_i32 s14, s14, 3 ; VI-NEXT: s_add_i32 s15, s15, 3 +; VI-NEXT: s_add_i32 s16, s16, 3 +; VI-NEXT: s_add_i32 s17, s17, 3 +; VI-NEXT: s_add_i32 s18, s18, 3 +; VI-NEXT: s_add_i32 s19, s19, 3 +; VI-NEXT: s_add_i32 s20, s20, 3 +; VI-NEXT: s_add_i32 s21, s21, 3 +; VI-NEXT: s_add_i32 s22, s22, 3 +; VI-NEXT: s_add_i32 s23, s23, 3 +; VI-NEXT: s_add_i32 s24, s24, 3 +; VI-NEXT: s_add_i32 s25, s25, 3 +; VI-NEXT: s_add_i32 s26, s26, 3 ; VI-NEXT: s_add_i32 s40, s40, 3 ; VI-NEXT: s_add_i32 s41, s41, 3 -; VI-NEXT: s_add_i32 s29, s29, 3 -; VI-NEXT: s_add_i32 s28, s28, 3 -; VI-NEXT: s_add_i32 s27, s27, 3 -; VI-NEXT: s_add_i32 s26, s26, 3 -; VI-NEXT: s_add_i32 s25, s25, 3 -; VI-NEXT: s_add_i32 s24, s24, 3 -; VI-NEXT: s_add_i32 s23, s23, 3 -; VI-NEXT: s_add_i32 s22, s22, 3 -; VI-NEXT: s_add_i32 s21, s21, 3 -; VI-NEXT: s_add_i32 s20, s20, 3 -; VI-NEXT: s_add_i32 s19, s19, 3 -; VI-NEXT: s_add_i32 s18, s18, 3 -; VI-NEXT: s_add_i32 s17, s17, 3 -; VI-NEXT: s_add_i32 s16, s16, 3 -; VI-NEXT: s_lshr_b32 s42, s7, 16 -; VI-NEXT: s_lshr_b32 s43, s6, 16 -; VI-NEXT: s_lshr_b32 s44, s8, 16 +; VI-NEXT: s_add_i32 s42, s42, 3 +; VI-NEXT: s_add_i32 s43, s43, 3 +; VI-NEXT: s_add_i32 s44, s44, 3 +; VI-NEXT: s_lshr_b32 s27, s7, 16 +; VI-NEXT: s_lshr_b32 s28, s6, 16 +; VI-NEXT: s_lshr_b32 s29, s8, 16 ; VI-NEXT: s_lshr_b32 s45, s9, 16 ; VI-NEXT: s_lshr_b32 s46, s10, 16 ; VI-NEXT: s_lshr_b32 s47, s11, 16 @@ -8370,117 +8347,117 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; VI-NEXT: s_lshr_b32 s57, s13, 16 ; VI-NEXT: s_lshr_b32 s58, s14, 16 ; VI-NEXT: s_lshr_b32 s59, s15, 16 -; VI-NEXT: s_lshr_b32 s60, s40, 16 -; VI-NEXT: s_lshr_b32 s61, s41, 16 -; VI-NEXT: s_lshr_b32 s62, s29, 16 -; VI-NEXT: s_lshr_b32 s63, s28, 16 -; VI-NEXT: s_lshr_b32 s72, s27, 16 -; VI-NEXT: s_lshr_b32 s73, s26, 16 -; VI-NEXT: s_lshr_b32 s74, s25, 16 -; VI-NEXT: s_lshr_b32 s75, s24, 16 -; VI-NEXT: s_lshr_b32 s76, s23, 16 -; VI-NEXT: s_lshr_b32 s77, s22, 16 -; VI-NEXT: s_lshr_b32 s78, s21, 16 -; VI-NEXT: s_lshr_b32 s79, s20, 16 -; VI-NEXT: s_lshr_b32 s88, s19, 16 -; VI-NEXT: s_lshr_b32 s89, s18, 16 -; VI-NEXT: s_lshr_b32 s90, s17, 16 -; VI-NEXT: s_lshr_b32 s91, s16, 16 +; VI-NEXT: s_lshr_b32 s60, s16, 16 +; VI-NEXT: s_lshr_b32 s61, s17, 16 +; VI-NEXT: s_lshr_b32 s62, s18, 16 +; VI-NEXT: s_lshr_b32 s63, s19, 16 +; VI-NEXT: s_lshr_b32 s72, s20, 16 +; VI-NEXT: s_lshr_b32 s73, s21, 16 +; VI-NEXT: s_lshr_b32 s74, s22, 16 +; VI-NEXT: s_lshr_b32 s75, s23, 16 +; VI-NEXT: s_lshr_b32 s76, s24, 16 +; VI-NEXT: s_lshr_b32 s77, s25, 16 +; VI-NEXT: s_lshr_b32 s78, s26, 16 +; VI-NEXT: s_lshr_b32 s79, s40, 16 +; VI-NEXT: s_lshr_b32 s88, s41, 16 +; VI-NEXT: s_lshr_b32 s89, s42, 16 +; VI-NEXT: s_lshr_b32 s90, s43, 16 +; VI-NEXT: s_lshr_b32 s91, s44, 16 ; VI-NEXT: .LBB17_3: ; %end -; VI-NEXT: s_and_b32 s4, 0xffff, s16 +; VI-NEXT: s_and_b32 s4, 0xffff, s44 ; VI-NEXT: s_lshl_b32 s5, s91, 16 ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_and_b32 s5, 0xffff, s17 -; VI-NEXT: s_lshl_b32 s16, s90, 16 -; VI-NEXT: s_or_b32 s5, s5, s16 -; VI-NEXT: s_and_b32 s16, 0xffff, s18 -; VI-NEXT: s_lshl_b32 s17, s89, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, 0xffff, s19 -; VI-NEXT: s_lshl_b32 s18, s88, 16 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s18, 0xffff, s20 -; VI-NEXT: s_lshl_b32 s19, s79, 16 -; VI-NEXT: s_or_b32 s18, s18, s19 -; VI-NEXT: s_and_b32 s19, 0xffff, s21 -; VI-NEXT: s_lshl_b32 s20, s78, 16 -; VI-NEXT: s_or_b32 s19, s19, s20 -; VI-NEXT: s_and_b32 s20, 0xffff, s22 -; VI-NEXT: s_lshl_b32 s21, s77, 16 -; VI-NEXT: s_or_b32 s20, s20, s21 -; VI-NEXT: s_and_b32 s21, 0xffff, s23 -; VI-NEXT: s_lshl_b32 s22, s76, 16 -; VI-NEXT: s_or_b32 s21, s21, s22 -; VI-NEXT: s_and_b32 s22, 0xffff, s24 -; VI-NEXT: s_lshl_b32 s23, s75, 16 -; VI-NEXT: s_or_b32 s22, s22, s23 -; VI-NEXT: s_and_b32 s23, 0xffff, s25 -; VI-NEXT: s_lshl_b32 s24, s74, 16 -; VI-NEXT: s_or_b32 s23, s23, s24 -; VI-NEXT: s_and_b32 s24, 0xffff, s26 -; VI-NEXT: s_lshl_b32 s25, s73, 16 -; VI-NEXT: s_or_b32 s24, s24, s25 -; VI-NEXT: s_and_b32 s25, 0xffff, s27 -; VI-NEXT: s_lshl_b32 s26, s72, 16 -; VI-NEXT: s_or_b32 s25, s25, s26 -; VI-NEXT: s_and_b32 s26, 0xffff, s28 -; VI-NEXT: s_lshl_b32 s27, s63, 16 -; VI-NEXT: s_or_b32 s26, s26, s27 -; VI-NEXT: s_and_b32 s27, 0xffff, s29 -; VI-NEXT: s_lshl_b32 s28, s62, 16 -; VI-NEXT: s_or_b32 s27, s27, s28 -; VI-NEXT: s_and_b32 s28, 0xffff, s41 -; VI-NEXT: s_lshl_b32 s29, s61, 16 -; VI-NEXT: s_or_b32 s28, s28, s29 -; VI-NEXT: s_and_b32 s29, 0xffff, s40 -; VI-NEXT: s_lshl_b32 s40, s60, 16 -; VI-NEXT: s_or_b32 s29, s29, s40 +; VI-NEXT: s_and_b32 s5, 0xffff, s43 +; VI-NEXT: s_lshl_b32 s43, s90, 16 +; VI-NEXT: s_or_b32 s5, s5, s43 +; VI-NEXT: s_and_b32 s42, 0xffff, s42 +; VI-NEXT: s_lshl_b32 s43, s89, 16 +; VI-NEXT: s_or_b32 s42, s42, s43 +; VI-NEXT: s_and_b32 s41, 0xffff, s41 +; VI-NEXT: s_lshl_b32 s43, s88, 16 +; VI-NEXT: s_or_b32 s41, s41, s43 +; VI-NEXT: s_and_b32 s40, 0xffff, s40 +; VI-NEXT: s_lshl_b32 s43, s79, 16 +; VI-NEXT: s_or_b32 s40, s40, s43 +; VI-NEXT: s_and_b32 s26, 0xffff, s26 +; VI-NEXT: s_lshl_b32 s43, s78, 16 +; VI-NEXT: s_or_b32 s26, s26, s43 +; VI-NEXT: s_and_b32 s25, 0xffff, s25 +; VI-NEXT: s_lshl_b32 s43, s77, 16 +; VI-NEXT: s_or_b32 s25, s25, s43 +; VI-NEXT: s_and_b32 s24, 0xffff, s24 +; VI-NEXT: s_lshl_b32 s43, s76, 16 +; VI-NEXT: s_or_b32 s24, s24, s43 +; VI-NEXT: s_and_b32 s23, 0xffff, s23 +; VI-NEXT: s_lshl_b32 s43, s75, 16 +; VI-NEXT: s_or_b32 s23, s23, s43 +; VI-NEXT: s_and_b32 s22, 0xffff, s22 +; VI-NEXT: s_lshl_b32 s43, s74, 16 +; VI-NEXT: s_or_b32 s22, s22, s43 +; VI-NEXT: s_and_b32 s21, 0xffff, s21 +; VI-NEXT: s_lshl_b32 s43, s73, 16 +; VI-NEXT: s_or_b32 s21, s21, s43 +; VI-NEXT: s_and_b32 s20, 0xffff, s20 +; VI-NEXT: s_lshl_b32 s43, s72, 16 +; VI-NEXT: s_or_b32 s20, s20, s43 +; VI-NEXT: s_and_b32 s19, 0xffff, s19 +; VI-NEXT: s_lshl_b32 s43, s63, 16 +; VI-NEXT: s_or_b32 s19, s19, s43 +; VI-NEXT: s_and_b32 s18, 0xffff, s18 +; VI-NEXT: s_lshl_b32 s43, s62, 16 +; VI-NEXT: s_or_b32 s18, s18, s43 +; VI-NEXT: s_and_b32 s17, 0xffff, s17 +; VI-NEXT: s_lshl_b32 s43, s61, 16 +; VI-NEXT: s_or_b32 s17, s17, s43 +; VI-NEXT: s_and_b32 s16, 0xffff, s16 +; VI-NEXT: s_lshl_b32 s43, s60, 16 +; VI-NEXT: s_or_b32 s16, s16, s43 ; VI-NEXT: s_and_b32 s15, 0xffff, s15 -; VI-NEXT: s_lshl_b32 s40, s59, 16 -; VI-NEXT: s_or_b32 s15, s15, s40 +; VI-NEXT: s_lshl_b32 s43, s59, 16 +; VI-NEXT: s_or_b32 s15, s15, s43 ; VI-NEXT: s_and_b32 s14, 0xffff, s14 -; VI-NEXT: s_lshl_b32 s40, s58, 16 -; VI-NEXT: s_or_b32 s14, s14, s40 +; VI-NEXT: s_lshl_b32 s43, s58, 16 +; VI-NEXT: s_or_b32 s14, s14, s43 ; VI-NEXT: s_and_b32 s13, 0xffff, s13 -; VI-NEXT: s_lshl_b32 s40, s57, 16 -; VI-NEXT: s_or_b32 s13, s13, s40 +; VI-NEXT: s_lshl_b32 s43, s57, 16 +; VI-NEXT: s_or_b32 s13, s13, s43 ; VI-NEXT: s_and_b32 s12, 0xffff, s12 -; VI-NEXT: s_lshl_b32 s40, s56, 16 -; VI-NEXT: s_or_b32 s12, s12, s40 +; VI-NEXT: s_lshl_b32 s43, s56, 16 +; VI-NEXT: s_or_b32 s12, s12, s43 ; VI-NEXT: s_and_b32 s11, 0xffff, s11 -; VI-NEXT: s_lshl_b32 s40, s47, 16 -; VI-NEXT: s_or_b32 s11, s11, s40 +; VI-NEXT: s_lshl_b32 s43, s47, 16 +; VI-NEXT: s_or_b32 s11, s11, s43 ; VI-NEXT: s_and_b32 s10, 0xffff, s10 -; VI-NEXT: s_lshl_b32 s40, s46, 16 -; VI-NEXT: s_or_b32 s10, s10, s40 +; VI-NEXT: s_lshl_b32 s43, s46, 16 +; VI-NEXT: s_or_b32 s10, s10, s43 ; VI-NEXT: s_and_b32 s9, 0xffff, s9 -; VI-NEXT: s_lshl_b32 s40, s45, 16 -; VI-NEXT: s_or_b32 s9, s9, s40 +; VI-NEXT: s_lshl_b32 s43, s45, 16 ; VI-NEXT: s_and_b32 s8, 0xffff, s8 -; VI-NEXT: s_lshl_b32 s40, s44, 16 -; VI-NEXT: s_or_b32 s8, s8, s40 +; VI-NEXT: s_lshl_b32 s29, s29, 16 ; VI-NEXT: s_and_b32 s6, 0xffff, s6 -; VI-NEXT: s_lshl_b32 s40, s43, 16 -; VI-NEXT: s_or_b32 s6, s6, s40 +; VI-NEXT: s_lshl_b32 s28, s28, 16 ; VI-NEXT: s_and_b32 s7, 0xffff, s7 -; VI-NEXT: s_lshl_b32 s40, s42, 16 -; VI-NEXT: s_or_b32 s7, s7, s40 +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s9, s9, s43 +; VI-NEXT: s_or_b32 s8, s8, s29 +; VI-NEXT: s_or_b32 s6, s6, s28 +; VI-NEXT: s_or_b32 s7, s7, s27 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s5 -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: v_mov_b32_e32 v3, s17 -; VI-NEXT: v_mov_b32_e32 v4, s18 -; VI-NEXT: v_mov_b32_e32 v5, s19 -; VI-NEXT: v_mov_b32_e32 v6, s20 -; VI-NEXT: v_mov_b32_e32 v7, s21 -; VI-NEXT: v_mov_b32_e32 v8, s22 -; VI-NEXT: v_mov_b32_e32 v9, s23 -; VI-NEXT: v_mov_b32_e32 v10, s24 -; VI-NEXT: v_mov_b32_e32 v11, s25 -; VI-NEXT: v_mov_b32_e32 v12, s26 -; VI-NEXT: v_mov_b32_e32 v13, s27 -; VI-NEXT: v_mov_b32_e32 v14, s28 -; VI-NEXT: v_mov_b32_e32 v15, s29 +; VI-NEXT: v_mov_b32_e32 v2, s42 +; VI-NEXT: v_mov_b32_e32 v3, s41 +; VI-NEXT: v_mov_b32_e32 v4, s40 +; VI-NEXT: v_mov_b32_e32 v5, s26 +; VI-NEXT: v_mov_b32_e32 v6, s25 +; VI-NEXT: v_mov_b32_e32 v7, s24 +; VI-NEXT: v_mov_b32_e32 v8, s23 +; VI-NEXT: v_mov_b32_e32 v9, s22 +; VI-NEXT: v_mov_b32_e32 v10, s21 +; VI-NEXT: v_mov_b32_e32 v11, s20 +; VI-NEXT: v_mov_b32_e32 v12, s19 +; VI-NEXT: v_mov_b32_e32 v13, s18 +; VI-NEXT: v_mov_b32_e32 v14, s17 +; VI-NEXT: v_mov_b32_e32 v15, s16 ; VI-NEXT: v_mov_b32_e32 v16, s15 ; VI-NEXT: v_mov_b32_e32 v17, s14 ; VI-NEXT: v_mov_b32_e32 v18, s13 @@ -8516,25 +8493,53 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; VI-NEXT: ; implicit-def: $sgpr47 ; VI-NEXT: ; implicit-def: $sgpr46 ; VI-NEXT: ; implicit-def: $sgpr45 -; VI-NEXT: ; implicit-def: $sgpr44 -; VI-NEXT: ; implicit-def: $sgpr43 -; VI-NEXT: ; implicit-def: $sgpr42 +; VI-NEXT: ; implicit-def: $sgpr29 +; VI-NEXT: ; implicit-def: $sgpr28 +; VI-NEXT: ; implicit-def: $sgpr27 ; VI-NEXT: s_branch .LBB17_2 ; ; GFX9-LABEL: bitcast_v26i32_to_v52f16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v13, s16 +; GFX9-NEXT: v_mov_b32_e32 v14, s17 +; GFX9-NEXT: v_mov_b32_e32 v15, s18 +; GFX9-NEXT: v_mov_b32_e32 v16, s19 +; GFX9-NEXT: v_mov_b32_e32 v17, s20 +; GFX9-NEXT: v_mov_b32_e32 v18, s21 +; GFX9-NEXT: v_mov_b32_e32 v19, s22 +; GFX9-NEXT: v_readfirstlane_b32 s6, v13 +; GFX9-NEXT: v_mov_b32_e32 v13, s23 +; GFX9-NEXT: v_readfirstlane_b32 s7, v14 +; GFX9-NEXT: v_mov_b32_e32 v14, s24 +; GFX9-NEXT: v_readfirstlane_b32 s8, v15 +; GFX9-NEXT: v_mov_b32_e32 v15, s25 +; GFX9-NEXT: v_readfirstlane_b32 s9, v16 +; GFX9-NEXT: v_mov_b32_e32 v16, s26 +; GFX9-NEXT: v_readfirstlane_b32 s10, v17 +; GFX9-NEXT: v_mov_b32_e32 v17, s27 +; GFX9-NEXT: v_readfirstlane_b32 s11, v18 +; GFX9-NEXT: v_mov_b32_e32 v18, s28 +; GFX9-NEXT: v_readfirstlane_b32 s12, v19 +; GFX9-NEXT: v_mov_b32_e32 v19, s29 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 -; GFX9-NEXT: v_readfirstlane_b32 s6, v0 -; GFX9-NEXT: v_readfirstlane_b32 s7, v1 -; GFX9-NEXT: v_readfirstlane_b32 s8, v2 -; GFX9-NEXT: v_readfirstlane_b32 s9, v3 -; GFX9-NEXT: v_readfirstlane_b32 s10, v4 -; GFX9-NEXT: v_readfirstlane_b32 s11, v5 -; GFX9-NEXT: v_readfirstlane_b32 s12, v6 -; GFX9-NEXT: v_readfirstlane_b32 s13, v7 -; GFX9-NEXT: v_readfirstlane_b32 s14, v8 -; GFX9-NEXT: v_readfirstlane_b32 s15, v9 +; GFX9-NEXT: v_readfirstlane_b32 s13, v13 +; GFX9-NEXT: v_readfirstlane_b32 s14, v14 +; GFX9-NEXT: v_readfirstlane_b32 s15, v15 +; GFX9-NEXT: v_readfirstlane_b32 s16, v16 +; GFX9-NEXT: v_readfirstlane_b32 s17, v17 +; GFX9-NEXT: v_readfirstlane_b32 s18, v18 +; GFX9-NEXT: v_readfirstlane_b32 s19, v19 +; GFX9-NEXT: v_readfirstlane_b32 s20, v0 +; GFX9-NEXT: v_readfirstlane_b32 s21, v1 +; GFX9-NEXT: v_readfirstlane_b32 s22, v2 +; GFX9-NEXT: v_readfirstlane_b32 s23, v3 +; GFX9-NEXT: v_readfirstlane_b32 s24, v4 +; GFX9-NEXT: v_readfirstlane_b32 s25, v5 +; GFX9-NEXT: v_readfirstlane_b32 s26, v6 +; GFX9-NEXT: v_readfirstlane_b32 s27, v7 +; GFX9-NEXT: v_readfirstlane_b32 s28, v8 +; GFX9-NEXT: v_readfirstlane_b32 s29, v9 ; GFX9-NEXT: v_readfirstlane_b32 s40, v10 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s41, v11 @@ -8542,44 +8547,34 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_lshr_b32 s42, s41, 16 ; GFX9-NEXT: s_lshr_b32 s43, s40, 16 -; GFX9-NEXT: s_lshr_b32 s44, s15, 16 -; GFX9-NEXT: s_lshr_b32 s45, s14, 16 -; GFX9-NEXT: s_lshr_b32 s46, s13, 16 -; GFX9-NEXT: s_lshr_b32 s47, s12, 16 -; GFX9-NEXT: s_lshr_b32 s56, s11, 16 -; GFX9-NEXT: s_lshr_b32 s57, s10, 16 -; GFX9-NEXT: s_lshr_b32 s58, s9, 16 -; GFX9-NEXT: s_lshr_b32 s59, s8, 16 -; GFX9-NEXT: s_lshr_b32 s60, s7, 16 -; GFX9-NEXT: s_lshr_b32 s61, s6, 16 -; GFX9-NEXT: s_lshr_b32 s62, s29, 16 -; GFX9-NEXT: s_lshr_b32 s63, s28, 16 -; GFX9-NEXT: s_lshr_b32 s72, s27, 16 -; GFX9-NEXT: s_lshr_b32 s73, s26, 16 -; GFX9-NEXT: s_lshr_b32 s74, s25, 16 -; GFX9-NEXT: s_lshr_b32 s75, s24, 16 -; GFX9-NEXT: s_lshr_b32 s76, s23, 16 -; GFX9-NEXT: s_lshr_b32 s77, s22, 16 -; GFX9-NEXT: s_lshr_b32 s78, s21, 16 -; GFX9-NEXT: s_lshr_b32 s79, s20, 16 -; GFX9-NEXT: s_lshr_b32 s88, s19, 16 -; GFX9-NEXT: s_lshr_b32 s89, s18, 16 -; GFX9-NEXT: s_lshr_b32 s90, s17, 16 -; GFX9-NEXT: s_lshr_b32 s91, s16, 16 +; GFX9-NEXT: s_lshr_b32 s44, s29, 16 +; GFX9-NEXT: s_lshr_b32 s45, s28, 16 +; GFX9-NEXT: s_lshr_b32 s46, s27, 16 +; GFX9-NEXT: s_lshr_b32 s47, s26, 16 +; GFX9-NEXT: s_lshr_b32 s56, s25, 16 +; GFX9-NEXT: s_lshr_b32 s57, s24, 16 +; GFX9-NEXT: s_lshr_b32 s58, s23, 16 +; GFX9-NEXT: s_lshr_b32 s59, s22, 16 +; GFX9-NEXT: s_lshr_b32 s60, s21, 16 +; GFX9-NEXT: s_lshr_b32 s61, s20, 16 +; GFX9-NEXT: s_lshr_b32 s62, s19, 16 +; GFX9-NEXT: s_lshr_b32 s63, s18, 16 +; GFX9-NEXT: s_lshr_b32 s72, s17, 16 +; GFX9-NEXT: s_lshr_b32 s73, s16, 16 +; GFX9-NEXT: s_lshr_b32 s74, s15, 16 +; GFX9-NEXT: s_lshr_b32 s75, s14, 16 +; GFX9-NEXT: s_lshr_b32 s76, s13, 16 +; GFX9-NEXT: s_lshr_b32 s77, s12, 16 +; GFX9-NEXT: s_lshr_b32 s78, s11, 16 +; GFX9-NEXT: s_lshr_b32 s79, s10, 16 +; GFX9-NEXT: s_lshr_b32 s88, s9, 16 +; GFX9-NEXT: s_lshr_b32 s89, s8, 16 +; GFX9-NEXT: s_lshr_b32 s90, s7, 16 +; GFX9-NEXT: s_lshr_b32 s91, s6, 16 ; GFX9-NEXT: s_cbranch_execnz .LBB17_3 ; GFX9-NEXT: .LBB17_2: ; %cmp.true ; GFX9-NEXT: s_add_i32 s41, s41, 3 ; GFX9-NEXT: s_add_i32 s40, s40, 3 -; GFX9-NEXT: s_add_i32 s15, s15, 3 -; GFX9-NEXT: s_add_i32 s14, s14, 3 -; GFX9-NEXT: s_add_i32 s13, s13, 3 -; GFX9-NEXT: s_add_i32 s12, s12, 3 -; GFX9-NEXT: s_add_i32 s11, s11, 3 -; GFX9-NEXT: s_add_i32 s10, s10, 3 -; GFX9-NEXT: s_add_i32 s9, s9, 3 -; GFX9-NEXT: s_add_i32 s8, s8, 3 -; GFX9-NEXT: s_add_i32 s7, s7, 3 -; GFX9-NEXT: s_add_i32 s6, s6, 3 ; GFX9-NEXT: s_add_i32 s29, s29, 3 ; GFX9-NEXT: s_add_i32 s28, s28, 3 ; GFX9-NEXT: s_add_i32 s27, s27, 3 @@ -8594,83 +8589,93 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; GFX9-NEXT: s_add_i32 s18, s18, 3 ; GFX9-NEXT: s_add_i32 s17, s17, 3 ; GFX9-NEXT: s_add_i32 s16, s16, 3 +; GFX9-NEXT: s_add_i32 s15, s15, 3 +; GFX9-NEXT: s_add_i32 s14, s14, 3 +; GFX9-NEXT: s_add_i32 s13, s13, 3 +; GFX9-NEXT: s_add_i32 s12, s12, 3 +; GFX9-NEXT: s_add_i32 s11, s11, 3 +; GFX9-NEXT: s_add_i32 s10, s10, 3 +; GFX9-NEXT: s_add_i32 s9, s9, 3 +; GFX9-NEXT: s_add_i32 s8, s8, 3 +; GFX9-NEXT: s_add_i32 s7, s7, 3 +; GFX9-NEXT: s_add_i32 s6, s6, 3 ; GFX9-NEXT: s_lshr_b32 s42, s41, 16 ; GFX9-NEXT: s_lshr_b32 s43, s40, 16 -; GFX9-NEXT: s_lshr_b32 s44, s15, 16 -; GFX9-NEXT: s_lshr_b32 s45, s14, 16 -; GFX9-NEXT: s_lshr_b32 s46, s13, 16 -; GFX9-NEXT: s_lshr_b32 s47, s12, 16 -; GFX9-NEXT: s_lshr_b32 s56, s11, 16 -; GFX9-NEXT: s_lshr_b32 s57, s10, 16 -; GFX9-NEXT: s_lshr_b32 s58, s9, 16 -; GFX9-NEXT: s_lshr_b32 s59, s8, 16 -; GFX9-NEXT: s_lshr_b32 s60, s7, 16 -; GFX9-NEXT: s_lshr_b32 s61, s6, 16 -; GFX9-NEXT: s_lshr_b32 s62, s29, 16 -; GFX9-NEXT: s_lshr_b32 s63, s28, 16 -; GFX9-NEXT: s_lshr_b32 s72, s27, 16 -; GFX9-NEXT: s_lshr_b32 s73, s26, 16 -; GFX9-NEXT: s_lshr_b32 s74, s25, 16 -; GFX9-NEXT: s_lshr_b32 s75, s24, 16 -; GFX9-NEXT: s_lshr_b32 s76, s23, 16 -; GFX9-NEXT: s_lshr_b32 s77, s22, 16 -; GFX9-NEXT: s_lshr_b32 s78, s21, 16 -; GFX9-NEXT: s_lshr_b32 s79, s20, 16 -; GFX9-NEXT: s_lshr_b32 s88, s19, 16 -; GFX9-NEXT: s_lshr_b32 s89, s18, 16 -; GFX9-NEXT: s_lshr_b32 s90, s17, 16 -; GFX9-NEXT: s_lshr_b32 s91, s16, 16 +; GFX9-NEXT: s_lshr_b32 s44, s29, 16 +; GFX9-NEXT: s_lshr_b32 s45, s28, 16 +; GFX9-NEXT: s_lshr_b32 s46, s27, 16 +; GFX9-NEXT: s_lshr_b32 s47, s26, 16 +; GFX9-NEXT: s_lshr_b32 s56, s25, 16 +; GFX9-NEXT: s_lshr_b32 s57, s24, 16 +; GFX9-NEXT: s_lshr_b32 s58, s23, 16 +; GFX9-NEXT: s_lshr_b32 s59, s22, 16 +; GFX9-NEXT: s_lshr_b32 s60, s21, 16 +; GFX9-NEXT: s_lshr_b32 s61, s20, 16 +; GFX9-NEXT: s_lshr_b32 s62, s19, 16 +; GFX9-NEXT: s_lshr_b32 s63, s18, 16 +; GFX9-NEXT: s_lshr_b32 s72, s17, 16 +; GFX9-NEXT: s_lshr_b32 s73, s16, 16 +; GFX9-NEXT: s_lshr_b32 s74, s15, 16 +; GFX9-NEXT: s_lshr_b32 s75, s14, 16 +; GFX9-NEXT: s_lshr_b32 s76, s13, 16 +; GFX9-NEXT: s_lshr_b32 s77, s12, 16 +; GFX9-NEXT: s_lshr_b32 s78, s11, 16 +; GFX9-NEXT: s_lshr_b32 s79, s10, 16 +; GFX9-NEXT: s_lshr_b32 s88, s9, 16 +; GFX9-NEXT: s_lshr_b32 s89, s8, 16 +; GFX9-NEXT: s_lshr_b32 s90, s7, 16 +; GFX9-NEXT: s_lshr_b32 s91, s6, 16 ; GFX9-NEXT: .LBB17_3: ; %end -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s16, s91 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s17, s90 -; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s89 -; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s88 -; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s79 -; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s78 -; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s77 -; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s76 -; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s75 -; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s74 -; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s73 -; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s72 -; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s63 -; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s62 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s61 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s60 -; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s59 -; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s58 -; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s57 -; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s56 -; GFX9-NEXT: s_pack_ll_b32_b16 s12, s12, s47 -; GFX9-NEXT: s_pack_ll_b32_b16 s13, s13, s46 -; GFX9-NEXT: s_pack_ll_b32_b16 s14, s14, s45 -; GFX9-NEXT: s_pack_ll_b32_b16 s15, s15, s44 +; GFX9-NEXT: s_pack_ll_b32_b16 s4, s6, s91 +; GFX9-NEXT: s_pack_ll_b32_b16 s5, s7, s90 +; GFX9-NEXT: s_pack_ll_b32_b16 s6, s8, s89 +; GFX9-NEXT: s_pack_ll_b32_b16 s7, s9, s88 +; GFX9-NEXT: s_pack_ll_b32_b16 s8, s10, s79 +; GFX9-NEXT: s_pack_ll_b32_b16 s9, s11, s78 +; GFX9-NEXT: s_pack_ll_b32_b16 s10, s12, s77 +; GFX9-NEXT: s_pack_ll_b32_b16 s11, s13, s76 +; GFX9-NEXT: s_pack_ll_b32_b16 s12, s14, s75 +; GFX9-NEXT: s_pack_ll_b32_b16 s13, s15, s74 +; GFX9-NEXT: s_pack_ll_b32_b16 s14, s16, s73 +; GFX9-NEXT: s_pack_ll_b32_b16 s15, s17, s72 +; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s63 +; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s62 +; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s61 +; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s60 +; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s59 +; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s58 +; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s57 +; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s56 +; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s47 +; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s46 +; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s45 +; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s44 ; GFX9-NEXT: s_pack_ll_b32_b16 s28, s40, s43 ; GFX9-NEXT: s_pack_ll_b32_b16 s29, s41, s42 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 -; GFX9-NEXT: v_mov_b32_e32 v2, s16 -; GFX9-NEXT: v_mov_b32_e32 v3, s17 -; GFX9-NEXT: v_mov_b32_e32 v4, s18 -; GFX9-NEXT: v_mov_b32_e32 v5, s19 -; GFX9-NEXT: v_mov_b32_e32 v6, s20 -; GFX9-NEXT: v_mov_b32_e32 v7, s21 -; GFX9-NEXT: v_mov_b32_e32 v8, s22 -; GFX9-NEXT: v_mov_b32_e32 v9, s23 -; GFX9-NEXT: v_mov_b32_e32 v10, s24 -; GFX9-NEXT: v_mov_b32_e32 v11, s25 -; GFX9-NEXT: v_mov_b32_e32 v12, s26 -; GFX9-NEXT: v_mov_b32_e32 v13, s27 -; GFX9-NEXT: v_mov_b32_e32 v14, s6 -; GFX9-NEXT: v_mov_b32_e32 v15, s7 -; GFX9-NEXT: v_mov_b32_e32 v16, s8 -; GFX9-NEXT: v_mov_b32_e32 v17, s9 -; GFX9-NEXT: v_mov_b32_e32 v18, s10 -; GFX9-NEXT: v_mov_b32_e32 v19, s11 -; GFX9-NEXT: v_mov_b32_e32 v20, s12 -; GFX9-NEXT: v_mov_b32_e32 v21, s13 -; GFX9-NEXT: v_mov_b32_e32 v22, s14 -; GFX9-NEXT: v_mov_b32_e32 v23, s15 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: v_mov_b32_e32 v4, s8 +; GFX9-NEXT: v_mov_b32_e32 v5, s9 +; GFX9-NEXT: v_mov_b32_e32 v6, s10 +; GFX9-NEXT: v_mov_b32_e32 v7, s11 +; GFX9-NEXT: v_mov_b32_e32 v8, s12 +; GFX9-NEXT: v_mov_b32_e32 v9, s13 +; GFX9-NEXT: v_mov_b32_e32 v10, s14 +; GFX9-NEXT: v_mov_b32_e32 v11, s15 +; GFX9-NEXT: v_mov_b32_e32 v12, s16 +; GFX9-NEXT: v_mov_b32_e32 v13, s17 +; GFX9-NEXT: v_mov_b32_e32 v14, s18 +; GFX9-NEXT: v_mov_b32_e32 v15, s19 +; GFX9-NEXT: v_mov_b32_e32 v16, s20 +; GFX9-NEXT: v_mov_b32_e32 v17, s21 +; GFX9-NEXT: v_mov_b32_e32 v18, s22 +; GFX9-NEXT: v_mov_b32_e32 v19, s23 +; GFX9-NEXT: v_mov_b32_e32 v20, s24 +; GFX9-NEXT: v_mov_b32_e32 v21, s25 +; GFX9-NEXT: v_mov_b32_e32 v22, s26 +; GFX9-NEXT: v_mov_b32_e32 v23, s27 ; GFX9-NEXT: v_mov_b32_e32 v24, s28 ; GFX9-NEXT: v_mov_b32_e32 v25, s29 ; GFX9-NEXT: s_setpc_b64 s[30:31] @@ -8706,41 +8711,68 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; GFX11-LABEL: bitcast_v26i32_to_v52f16_scalar: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v9, s0 :: v_dual_mov_b32 v10, s1 +; GFX11-NEXT: v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v12, s3 +; GFX11-NEXT: v_dual_mov_b32 v13, s16 :: v_dual_mov_b32 v14, s17 +; GFX11-NEXT: v_dual_mov_b32 v15, s18 :: v_dual_mov_b32 v16, s19 +; GFX11-NEXT: v_dual_mov_b32 v17, s20 :: v_dual_mov_b32 v18, s21 +; GFX11-NEXT: v_dual_mov_b32 v19, s22 :: v_dual_mov_b32 v20, s23 +; GFX11-NEXT: v_dual_mov_b32 v21, s24 :: v_dual_mov_b32 v22, s25 +; GFX11-NEXT: v_dual_mov_b32 v23, s26 :: v_dual_mov_b32 v24, s27 +; GFX11-NEXT: v_dual_mov_b32 v25, s28 :: v_dual_mov_b32 v26, s29 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 -; GFX11-NEXT: v_readfirstlane_b32 s4, v0 -; GFX11-NEXT: v_readfirstlane_b32 s5, v1 -; GFX11-NEXT: v_readfirstlane_b32 s6, v2 -; GFX11-NEXT: v_readfirstlane_b32 s7, v3 -; GFX11-NEXT: v_readfirstlane_b32 s8, v4 -; GFX11-NEXT: v_readfirstlane_b32 s9, v5 -; GFX11-NEXT: v_readfirstlane_b32 s11, v6 -; GFX11-NEXT: v_readfirstlane_b32 s10, v7 +; GFX11-NEXT: v_readfirstlane_b32 s0, v9 +; GFX11-NEXT: v_readfirstlane_b32 s1, v10 +; GFX11-NEXT: v_readfirstlane_b32 s2, v11 +; GFX11-NEXT: v_readfirstlane_b32 s3, v12 +; GFX11-NEXT: v_readfirstlane_b32 s4, v13 +; GFX11-NEXT: v_readfirstlane_b32 s5, v14 +; GFX11-NEXT: v_readfirstlane_b32 s6, v15 +; GFX11-NEXT: v_readfirstlane_b32 s7, v16 +; GFX11-NEXT: v_readfirstlane_b32 s8, v17 +; GFX11-NEXT: v_readfirstlane_b32 s9, v18 +; GFX11-NEXT: v_readfirstlane_b32 s10, v19 +; GFX11-NEXT: v_readfirstlane_b32 s11, v20 +; GFX11-NEXT: v_readfirstlane_b32 s12, v21 +; GFX11-NEXT: v_readfirstlane_b32 s13, v22 +; GFX11-NEXT: v_readfirstlane_b32 s14, v23 +; GFX11-NEXT: v_readfirstlane_b32 s15, v24 +; GFX11-NEXT: v_readfirstlane_b32 s16, v25 +; GFX11-NEXT: v_readfirstlane_b32 s17, v26 +; GFX11-NEXT: v_readfirstlane_b32 s18, v0 +; GFX11-NEXT: v_readfirstlane_b32 s19, v1 +; GFX11-NEXT: v_readfirstlane_b32 s20, v2 +; GFX11-NEXT: v_readfirstlane_b32 s21, v3 +; GFX11-NEXT: v_readfirstlane_b32 s22, v4 +; GFX11-NEXT: v_readfirstlane_b32 s23, v5 +; GFX11-NEXT: v_readfirstlane_b32 s25, v6 +; GFX11-NEXT: v_readfirstlane_b32 s24, v7 ; GFX11-NEXT: s_mov_b32 s78, 0 -; GFX11-NEXT: s_and_b32 s12, vcc_lo, exec_lo +; GFX11-NEXT: s_and_b32 s26, vcc_lo, exec_lo ; GFX11-NEXT: s_cbranch_scc0 .LBB17_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: s_lshr_b32 s12, s10, 16 -; GFX11-NEXT: s_lshr_b32 s13, s11, 16 -; GFX11-NEXT: s_lshr_b32 s14, s9, 16 -; GFX11-NEXT: s_lshr_b32 s15, s8, 16 -; GFX11-NEXT: s_lshr_b32 s40, s7, 16 -; GFX11-NEXT: s_lshr_b32 s41, s6, 16 -; GFX11-NEXT: s_lshr_b32 s42, s5, 16 -; GFX11-NEXT: s_lshr_b32 s43, s4, 16 -; GFX11-NEXT: s_lshr_b32 s44, s29, 16 -; GFX11-NEXT: s_lshr_b32 s45, s28, 16 -; GFX11-NEXT: s_lshr_b32 s46, s27, 16 -; GFX11-NEXT: s_lshr_b32 s47, s26, 16 -; GFX11-NEXT: s_lshr_b32 s56, s25, 16 -; GFX11-NEXT: s_lshr_b32 s57, s24, 16 -; GFX11-NEXT: s_lshr_b32 s58, s23, 16 -; GFX11-NEXT: s_lshr_b32 s59, s22, 16 -; GFX11-NEXT: s_lshr_b32 s60, s21, 16 -; GFX11-NEXT: s_lshr_b32 s61, s20, 16 -; GFX11-NEXT: s_lshr_b32 s62, s19, 16 -; GFX11-NEXT: s_lshr_b32 s63, s18, 16 -; GFX11-NEXT: s_lshr_b32 s72, s17, 16 -; GFX11-NEXT: s_lshr_b32 s73, s16, 16 +; GFX11-NEXT: s_lshr_b32 s26, s24, 16 +; GFX11-NEXT: s_lshr_b32 s27, s25, 16 +; GFX11-NEXT: s_lshr_b32 s28, s23, 16 +; GFX11-NEXT: s_lshr_b32 s29, s22, 16 +; GFX11-NEXT: s_lshr_b32 s40, s21, 16 +; GFX11-NEXT: s_lshr_b32 s41, s20, 16 +; GFX11-NEXT: s_lshr_b32 s42, s19, 16 +; GFX11-NEXT: s_lshr_b32 s43, s18, 16 +; GFX11-NEXT: s_lshr_b32 s44, s17, 16 +; GFX11-NEXT: s_lshr_b32 s45, s16, 16 +; GFX11-NEXT: s_lshr_b32 s46, s15, 16 +; GFX11-NEXT: s_lshr_b32 s47, s14, 16 +; GFX11-NEXT: s_lshr_b32 s56, s13, 16 +; GFX11-NEXT: s_lshr_b32 s57, s12, 16 +; GFX11-NEXT: s_lshr_b32 s58, s11, 16 +; GFX11-NEXT: s_lshr_b32 s59, s10, 16 +; GFX11-NEXT: s_lshr_b32 s60, s9, 16 +; GFX11-NEXT: s_lshr_b32 s61, s8, 16 +; GFX11-NEXT: s_lshr_b32 s62, s7, 16 +; GFX11-NEXT: s_lshr_b32 s63, s6, 16 +; GFX11-NEXT: s_lshr_b32 s72, s5, 16 +; GFX11-NEXT: s_lshr_b32 s73, s4, 16 ; GFX11-NEXT: s_lshr_b32 s74, s3, 16 ; GFX11-NEXT: s_lshr_b32 s75, s2, 16 ; GFX11-NEXT: s_lshr_b32 s76, s1, 16 @@ -8748,20 +8780,8 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s78 ; GFX11-NEXT: s_cbranch_vccnz .LBB17_3 ; GFX11-NEXT: .LBB17_2: ; %cmp.true -; GFX11-NEXT: s_add_i32 s10, s10, 3 -; GFX11-NEXT: s_add_i32 s11, s11, 3 -; GFX11-NEXT: s_add_i32 s9, s9, 3 -; GFX11-NEXT: s_add_i32 s8, s8, 3 -; GFX11-NEXT: s_add_i32 s7, s7, 3 -; GFX11-NEXT: s_add_i32 s6, s6, 3 -; GFX11-NEXT: s_add_i32 s5, s5, 3 -; GFX11-NEXT: s_add_i32 s4, s4, 3 -; GFX11-NEXT: s_add_i32 s29, s29, 3 -; GFX11-NEXT: s_add_i32 s28, s28, 3 -; GFX11-NEXT: s_add_i32 s27, s27, 3 -; GFX11-NEXT: s_add_i32 s26, s26, 3 -; GFX11-NEXT: s_add_i32 s25, s25, 3 ; GFX11-NEXT: s_add_i32 s24, s24, 3 +; GFX11-NEXT: s_add_i32 s25, s25, 3 ; GFX11-NEXT: s_add_i32 s23, s23, 3 ; GFX11-NEXT: s_add_i32 s22, s22, 3 ; GFX11-NEXT: s_add_i32 s21, s21, 3 @@ -8770,32 +8790,44 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; GFX11-NEXT: s_add_i32 s18, s18, 3 ; GFX11-NEXT: s_add_i32 s17, s17, 3 ; GFX11-NEXT: s_add_i32 s16, s16, 3 +; GFX11-NEXT: s_add_i32 s15, s15, 3 +; GFX11-NEXT: s_add_i32 s14, s14, 3 +; GFX11-NEXT: s_add_i32 s13, s13, 3 +; GFX11-NEXT: s_add_i32 s12, s12, 3 +; GFX11-NEXT: s_add_i32 s11, s11, 3 +; GFX11-NEXT: s_add_i32 s10, s10, 3 +; GFX11-NEXT: s_add_i32 s9, s9, 3 +; GFX11-NEXT: s_add_i32 s8, s8, 3 +; GFX11-NEXT: s_add_i32 s7, s7, 3 +; GFX11-NEXT: s_add_i32 s6, s6, 3 +; GFX11-NEXT: s_add_i32 s5, s5, 3 +; GFX11-NEXT: s_add_i32 s4, s4, 3 ; GFX11-NEXT: s_add_i32 s3, s3, 3 ; GFX11-NEXT: s_add_i32 s2, s2, 3 ; GFX11-NEXT: s_add_i32 s1, s1, 3 ; GFX11-NEXT: s_add_i32 s0, s0, 3 -; GFX11-NEXT: s_lshr_b32 s12, s10, 16 -; GFX11-NEXT: s_lshr_b32 s13, s11, 16 -; GFX11-NEXT: s_lshr_b32 s14, s9, 16 -; GFX11-NEXT: s_lshr_b32 s15, s8, 16 -; GFX11-NEXT: s_lshr_b32 s40, s7, 16 -; GFX11-NEXT: s_lshr_b32 s41, s6, 16 -; GFX11-NEXT: s_lshr_b32 s42, s5, 16 -; GFX11-NEXT: s_lshr_b32 s43, s4, 16 -; GFX11-NEXT: s_lshr_b32 s44, s29, 16 -; GFX11-NEXT: s_lshr_b32 s45, s28, 16 -; GFX11-NEXT: s_lshr_b32 s46, s27, 16 -; GFX11-NEXT: s_lshr_b32 s47, s26, 16 -; GFX11-NEXT: s_lshr_b32 s56, s25, 16 -; GFX11-NEXT: s_lshr_b32 s57, s24, 16 -; GFX11-NEXT: s_lshr_b32 s58, s23, 16 -; GFX11-NEXT: s_lshr_b32 s59, s22, 16 -; GFX11-NEXT: s_lshr_b32 s60, s21, 16 -; GFX11-NEXT: s_lshr_b32 s61, s20, 16 -; GFX11-NEXT: s_lshr_b32 s62, s19, 16 -; GFX11-NEXT: s_lshr_b32 s63, s18, 16 -; GFX11-NEXT: s_lshr_b32 s72, s17, 16 -; GFX11-NEXT: s_lshr_b32 s73, s16, 16 +; GFX11-NEXT: s_lshr_b32 s26, s24, 16 +; GFX11-NEXT: s_lshr_b32 s27, s25, 16 +; GFX11-NEXT: s_lshr_b32 s28, s23, 16 +; GFX11-NEXT: s_lshr_b32 s29, s22, 16 +; GFX11-NEXT: s_lshr_b32 s40, s21, 16 +; GFX11-NEXT: s_lshr_b32 s41, s20, 16 +; GFX11-NEXT: s_lshr_b32 s42, s19, 16 +; GFX11-NEXT: s_lshr_b32 s43, s18, 16 +; GFX11-NEXT: s_lshr_b32 s44, s17, 16 +; GFX11-NEXT: s_lshr_b32 s45, s16, 16 +; GFX11-NEXT: s_lshr_b32 s46, s15, 16 +; GFX11-NEXT: s_lshr_b32 s47, s14, 16 +; GFX11-NEXT: s_lshr_b32 s56, s13, 16 +; GFX11-NEXT: s_lshr_b32 s57, s12, 16 +; GFX11-NEXT: s_lshr_b32 s58, s11, 16 +; GFX11-NEXT: s_lshr_b32 s59, s10, 16 +; GFX11-NEXT: s_lshr_b32 s60, s9, 16 +; GFX11-NEXT: s_lshr_b32 s61, s8, 16 +; GFX11-NEXT: s_lshr_b32 s62, s7, 16 +; GFX11-NEXT: s_lshr_b32 s63, s6, 16 +; GFX11-NEXT: s_lshr_b32 s72, s5, 16 +; GFX11-NEXT: s_lshr_b32 s73, s4, 16 ; GFX11-NEXT: s_lshr_b32 s74, s3, 16 ; GFX11-NEXT: s_lshr_b32 s75, s2, 16 ; GFX11-NEXT: s_lshr_b32 s76, s1, 16 @@ -8806,41 +8838,41 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s76 ; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s75 ; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s74 -; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s73 -; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s72 -; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s63 -; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s62 -; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s61 -; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s60 -; GFX11-NEXT: s_pack_ll_b32_b16 s22, s22, s59 -; GFX11-NEXT: s_pack_ll_b32_b16 s23, s23, s58 -; GFX11-NEXT: s_pack_ll_b32_b16 s24, s24, s57 -; GFX11-NEXT: s_pack_ll_b32_b16 s25, s25, s56 -; GFX11-NEXT: s_pack_ll_b32_b16 s26, s26, s47 -; GFX11-NEXT: s_pack_ll_b32_b16 s27, s27, s46 -; GFX11-NEXT: s_pack_ll_b32_b16 s28, s28, s45 -; GFX11-NEXT: s_pack_ll_b32_b16 s29, s29, s44 -; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s43 -; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s42 -; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s41 -; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s40 -; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s15 -; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s14 -; GFX11-NEXT: s_pack_ll_b32_b16 s11, s11, s13 -; GFX11-NEXT: s_pack_ll_b32_b16 s10, s10, s12 +; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s73 +; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s72 +; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s63 +; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s62 +; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s61 +; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s60 +; GFX11-NEXT: s_pack_ll_b32_b16 s10, s10, s59 +; GFX11-NEXT: s_pack_ll_b32_b16 s11, s11, s58 +; GFX11-NEXT: s_pack_ll_b32_b16 s12, s12, s57 +; GFX11-NEXT: s_pack_ll_b32_b16 s13, s13, s56 +; GFX11-NEXT: s_pack_ll_b32_b16 s14, s14, s47 +; GFX11-NEXT: s_pack_ll_b32_b16 s15, s15, s46 +; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s45 +; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s44 +; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s43 +; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s42 +; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s41 +; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s40 +; GFX11-NEXT: s_pack_ll_b32_b16 s22, s22, s29 +; GFX11-NEXT: s_pack_ll_b32_b16 s23, s23, s28 +; GFX11-NEXT: s_pack_ll_b32_b16 s25, s25, s27 +; GFX11-NEXT: s_pack_ll_b32_b16 s24, s24, s26 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 -; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 -; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 -; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 -; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 -; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 -; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 -; GFX11-NEXT: v_dual_mov_b32 v18, s4 :: v_dual_mov_b32 v19, s5 -; GFX11-NEXT: v_dual_mov_b32 v20, s6 :: v_dual_mov_b32 v21, s7 -; GFX11-NEXT: v_dual_mov_b32 v22, s8 :: v_dual_mov_b32 v23, s9 -; GFX11-NEXT: v_dual_mov_b32 v24, s11 :: v_dual_mov_b32 v25, s10 +; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19 +; GFX11-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v21, s21 +; GFX11-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v23, s23 +; GFX11-NEXT: v_dual_mov_b32 v24, s25 :: v_dual_mov_b32 v25, s24 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: .LBB17_4: ; GFX11-NEXT: ; implicit-def: $sgpr77 @@ -8865,10 +8897,10 @@ define inreg <52 x half> @bitcast_v26i32_to_v52f16_scalar(<26 x i32> inreg %a, i ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr41 ; GFX11-NEXT: ; implicit-def: $sgpr40 -; GFX11-NEXT: ; implicit-def: $sgpr15 -; GFX11-NEXT: ; implicit-def: $sgpr14 -; GFX11-NEXT: ; implicit-def: $sgpr13 -; GFX11-NEXT: ; implicit-def: $sgpr12 +; GFX11-NEXT: ; implicit-def: $sgpr29 +; GFX11-NEXT: ; implicit-def: $sgpr28 +; GFX11-NEXT: ; implicit-def: $sgpr27 +; GFX11-NEXT: ; implicit-def: $sgpr26 ; GFX11-NEXT: s_branch .LBB17_2 %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -9760,7 +9792,6 @@ define <26 x i32> @bitcast_v52f16_to_v26i32(<52 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v57, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v25 -; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v24 @@ -9827,6 +9858,7 @@ define <26 x i32> @bitcast_v52f16_to_v26i32(<52 x half> %a, i32 %b) { ; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v56 ; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v57 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 +; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -9959,6 +9991,9 @@ define <26 x i32> @bitcast_v52f16_to_v26i32(<52 x half> %a, i32 %b) { ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] ; GFX9-NEXT: s_cbranch_execz .LBB18_4 ; GFX9-NEXT: ; %bb.3: ; %cmp.true +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload @@ -9973,9 +10008,6 @@ define <26 x i32> @bitcast_v52f16_to_v26i32(<52 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v34, v57, s6 ; GFX9-NEXT: s_movk_i32 s7, 0x200 ; GFX9-NEXT: v_perm_b32 v1, v62, v56, s6 @@ -9995,6 +10027,10 @@ define <26 x i32> @bitcast_v52f16_to_v26i32(<52 x half> %a, i32 %b) { ; GFX9-NEXT: v_pk_add_f16 v6, v6, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v7, v7, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v8, v8, s7 op_sel_hi:[1,0] +; GFX9-NEXT: s_waitcnt vmcnt(14) +; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; GFX9-NEXT: s_waitcnt vmcnt(15) ; GFX9-NEXT: v_perm_b32 v9, v9, v40, s6 ; GFX9-NEXT: s_waitcnt vmcnt(14) @@ -10023,10 +10059,6 @@ define <26 x i32> @bitcast_v52f16_to_v26i32(<52 x half> %a, i32 %b) { ; GFX9-NEXT: v_perm_b32 v21, v21, v36, s6 ; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: v_perm_b32 v22, v22, v35, s6 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v10, v10, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0] @@ -10295,14 +10327,28 @@ define inreg <26 x i32> @bitcast_v52f16_to_v26i32_scalar(<52 x half> inreg %a, i ; SI-NEXT: v_cvt_f16_f32_e32 v8, s26 ; SI-NEXT: v_cvt_f16_f32_e32 v6, s29 ; SI-NEXT: v_cvt_f16_f32_e32 v7, s28 -; SI-NEXT: s_waitcnt vmcnt(9) +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cvt_f16_f32_e32 v31, v31 -; SI-NEXT: s_waitcnt vmcnt(8) expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v38 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(8) expcnt(0) +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v39 -; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v44 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill @@ -10318,22 +10364,6 @@ define inreg <26 x i32> @bitcast_v52f16_to_v26i32_scalar(<52 x half> inreg %a, i ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v51 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB19_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload @@ -10342,8 +10372,8 @@ define inreg <26 x i32> @bitcast_v52f16_to_v26i32_scalar(<52 x half> inreg %a, i ; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(2) ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v53 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v12 @@ -10363,10 +10393,8 @@ define inreg <26 x i32> @bitcast_v52f16_to_v26i32_scalar(<52 x half> inreg %a, i ; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v42 ; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v56 ; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v43 -; SI-NEXT: s_waitcnt expcnt(1) ; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v57 ; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v15 ; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v62 ; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v36 @@ -10407,11 +10435,11 @@ define inreg <26 x i32> @bitcast_v52f16_to_v26i32_scalar(<52 x half> inreg %a, i ; SI-NEXT: v_or_b32_e32 v25, v38, v25 ; SI-NEXT: s_cbranch_execnz .LBB19_3 ; SI-NEXT: .LBB19_2: ; %cmp.true -; SI-NEXT: s_waitcnt expcnt(2) ; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f32_f16_e32 v0, v53 ; SI-NEXT: v_cvt_f32_f16_e32 v9, v40 ; SI-NEXT: v_cvt_f32_f16_e32 v10, v55 @@ -10425,7 +10453,6 @@ define inreg <26 x i32> @bitcast_v52f16_to_v26i32_scalar(<52 x half> inreg %a, i ; SI-NEXT: v_cvt_f16_f32_e32 v10, v10 ; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11 ; SI-NEXT: v_cvt_f16_f32_e32 v11, v11 -; SI-NEXT: s_waitcnt expcnt(1) ; SI-NEXT: v_cvt_f32_f16_e32 v12, v47 ; SI-NEXT: v_cvt_f32_f16_e32 v13, v60 ; SI-NEXT: v_cvt_f32_f16_e32 v15, v52 @@ -10463,7 +10490,6 @@ define inreg <26 x i32> @bitcast_v52f16_to_v26i32_scalar(<52 x half> inreg %a, i ; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload @@ -11113,294 +11139,109 @@ define inreg <26 x i32> @bitcast_v52f16_to_v26i32_scalar(<52 x half> inreg %a, i ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v191, v1 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v185, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB19_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB19_3 ; GFX11-TRUE16-NEXT: .LBB19_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s40 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s41 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v185, 0x200, v185 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v191, 0x200, v191 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v190, 0x200, v190 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v189, 0x200, v189 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v188, 0x200, v188 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v187, 0x200, v187 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v186, 0x200, v186 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, s6 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, s7 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, s8 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s9 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, s10 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, s11 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, s12 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, s13 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s14 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, s15 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, s16 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s0 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s1 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s2 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, s3 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, s4 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v35, 0x200, s5 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v44, 0x200, s6 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v54, 0x200, s7 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v65, 0x200, s8 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v77, 0x200, s9 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v90, 0x200, s10 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v104, 0x200, s11 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v119, 0x200, s12 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v135, 0x200, s13 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v152, 0x200, s14 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v170, 0x200, s15 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: .LBB19_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v170 :: v_dual_mov_b32 v18, v185 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v191 :: v_dual_mov_b32 v20, v190 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v189 :: v_dual_mov_b32 v22, v188 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v187 :: v_dual_mov_b32 v24, v186 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v191, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v190, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v189, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v188, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v187, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:316 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v14, v119 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB19_4: -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v53, v25 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v25, v53 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB19_2 ; ; GFX11-FAKE16-LABEL: bitcast_v52f16_to_v26i32_scalar: @@ -15076,6 +14917,19 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) { ; SI-LABEL: bitcast_v52i16_to_v26f32: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v50, v10 +; SI-NEXT: v_mov_b32_e32 v51, v8 +; SI-NEXT: v_mov_b32_e32 v52, v6 +; SI-NEXT: v_mov_b32_e32 v53, v4 +; SI-NEXT: v_mov_b32_e32 v54, v2 +; SI-NEXT: v_mov_b32_e32 v55, v0 +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:48 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:40 +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24 +; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:16 +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:12 +; SI-NEXT: v_mov_b32_e32 v49, v12 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill @@ -15101,19 +14955,6 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v50, v10 -; SI-NEXT: v_mov_b32_e32 v51, v8 -; SI-NEXT: v_mov_b32_e32 v52, v6 -; SI-NEXT: v_mov_b32_e32 v53, v4 -; SI-NEXT: v_mov_b32_e32 v54, v2 -; SI-NEXT: v_mov_b32_e32 v55, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:48 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:40 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32 -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24 -; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:16 -; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:12 -; SI-NEXT: v_mov_b32_e32 v49, v12 ; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v1 ; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v3 ; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v5 @@ -15129,17 +14970,12 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) { ; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v25 ; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v27 ; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v29 -; SI-NEXT: s_waitcnt vmcnt(5) +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v0 -; SI-NEXT: s_waitcnt vmcnt(4) ; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v2 -; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v4 -; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v6 -; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v8 -; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:8 @@ -15164,9 +15000,10 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) { ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72 ; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:68 -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v18 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 @@ -15178,10 +15015,9 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) { ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:56 ; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:52 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v22 ; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v22 +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:44 @@ -15501,7 +15337,7 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) { ; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21 ; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22 ; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23 -; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24 +; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v24 ; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25 ; SI-NEXT: .LBB30_4: ; %end ; SI-NEXT: s_or_b64 exec, exec, s[4:5] @@ -15767,7 +15603,6 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v57, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v25 -; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v24 @@ -15834,6 +15669,7 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v56 ; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v57 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 +; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -15966,6 +15802,9 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] ; GFX9-NEXT: s_cbranch_execz .LBB30_4 ; GFX9-NEXT: ; %bb.3: ; %cmp.true +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload @@ -15980,9 +15819,6 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v34, v57, s6 ; GFX9-NEXT: v_perm_b32 v1, v62, v56, s6 ; GFX9-NEXT: v_perm_b32 v2, v33, v47, s6 @@ -16001,6 +15837,10 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] +; GFX9-NEXT: s_waitcnt vmcnt(14) +; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; GFX9-NEXT: s_waitcnt vmcnt(15) ; GFX9-NEXT: v_perm_b32 v9, v9, v40, s6 ; GFX9-NEXT: s_waitcnt vmcnt(14) @@ -16029,10 +15869,6 @@ define <26 x float> @bitcast_v52i16_to_v26f32(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: v_perm_b32 v21, v21, v36, s6 ; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: v_perm_b32 v22, v22, v35, s6 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] @@ -17022,294 +16858,109 @@ define inreg <26 x float> @bitcast_v52i16_to_v26f32_scalar(<52 x i16> inreg %a, ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v191, v1 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v185, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB31_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB31_3 ; GFX11-TRUE16-NEXT: .LBB31_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s40, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s41, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v185, v185, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v191, v191, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v190, v190, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v189, v189, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v188, v188, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v187, v187, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v186, v186, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, s6, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, s7, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, s8, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s9, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, s10, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, s11, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, s12, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, s13, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s14, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, s15, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, s16, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s0, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s1, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s2, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, s3, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, s4, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v35, s5, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v44, s6, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v54, s7, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v65, s8, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v77, s9, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v90, s10, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v104, s11, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v119, s12, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v135, s13, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v152, s14, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v170, s15, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: .LBB31_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v170 :: v_dual_mov_b32 v18, v185 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v191 :: v_dual_mov_b32 v20, v190 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v189 :: v_dual_mov_b32 v22, v188 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v187 :: v_dual_mov_b32 v24, v186 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v191, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v190, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v189, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v188, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v187, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:316 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v14, v119 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB31_4: -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v53, v25 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v25, v53 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB31_2 ; ; GFX11-FAKE16-LABEL: bitcast_v52i16_to_v26f32_scalar: @@ -18542,19 +18193,6 @@ define inreg <52 x half> @bitcast_v26f32_to_v52f16_scalar(<26 x float> inreg %a, ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 -; SI-NEXT: v_readfirstlane_b32 s41, v1 -; SI-NEXT: v_readfirstlane_b32 s40, v2 -; SI-NEXT: v_readfirstlane_b32 s15, v3 -; SI-NEXT: v_readfirstlane_b32 s14, v4 -; SI-NEXT: v_readfirstlane_b32 s13, v5 -; SI-NEXT: v_readfirstlane_b32 s12, v6 -; SI-NEXT: v_readfirstlane_b32 s11, v7 -; SI-NEXT: v_readfirstlane_b32 s10, v8 -; SI-NEXT: v_readfirstlane_b32 s8, v9 -; SI-NEXT: v_readfirstlane_b32 s7, v10 -; SI-NEXT: v_readfirstlane_b32 s6, v11 -; SI-NEXT: s_and_b64 s[4:5], vcc, exec -; SI-NEXT: v_readfirstlane_b32 s9, v12 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -18571,377 +18209,468 @@ define inreg <52 x half> @bitcast_v26f32_to_v52f16_scalar(<26 x float> inreg %a, ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v21, s16 +; SI-NEXT: v_mov_b32_e32 v18, s17 +; SI-NEXT: v_mov_b32_e32 v16, s18 +; SI-NEXT: v_mov_b32_e32 v15, s19 +; SI-NEXT: v_mov_b32_e32 v14, s20 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v63, s21 +; SI-NEXT: v_mov_b32_e32 v25, s22 +; SI-NEXT: s_and_b64 s[4:5], vcc, exec +; SI-NEXT: v_mov_b32_e32 v26, s23 +; SI-NEXT: v_mov_b32_e32 v24, s24 +; SI-NEXT: v_mov_b32_e32 v23, s25 +; SI-NEXT: v_mov_b32_e32 v22, s26 +; SI-NEXT: v_mov_b32_e32 v19, s27 +; SI-NEXT: v_mov_b32_e32 v17, s28 +; SI-NEXT: v_mov_b32_e32 v13, s29 ; SI-NEXT: s_cbranch_scc0 .LBB33_4 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: s_lshr_b32 s4, s9, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v1, s4 -; SI-NEXT: s_lshr_b32 s4, s6, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v2, s4 -; SI-NEXT: s_lshr_b32 s4, s7, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v3, s4 -; SI-NEXT: s_lshr_b32 s4, s8, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v5, s4 -; SI-NEXT: s_lshr_b32 s4, s10, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v7, s4 -; SI-NEXT: s_lshr_b32 s4, s11, 16 -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_cvt_f32_f16_e32 v60, s4 -; SI-NEXT: s_lshr_b32 s4, s12, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v59, s4 -; SI-NEXT: s_lshr_b32 s4, s13, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v14, s4 -; SI-NEXT: s_lshr_b32 s4, s14, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v16, s4 -; SI-NEXT: s_lshr_b32 s4, s15, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v18, s4 -; SI-NEXT: s_lshr_b32 s4, s40, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v20, s4 -; SI-NEXT: s_lshr_b32 s4, s41, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v22, s4 -; SI-NEXT: s_lshr_b32 s4, s29, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v24, s4 -; SI-NEXT: s_lshr_b32 s4, s28, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v26, s4 -; SI-NEXT: s_lshr_b32 s4, s27, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v28, s4 -; SI-NEXT: s_lshr_b32 s4, s26, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v31, s4 -; SI-NEXT: s_lshr_b32 s4, s25, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v33, s4 -; SI-NEXT: s_lshr_b32 s4, s24, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v35, s4 -; SI-NEXT: s_lshr_b32 s4, s23, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v37, s4 -; SI-NEXT: s_lshr_b32 s4, s22, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v39, s4 -; SI-NEXT: s_lshr_b32 s4, s21, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v49, s4 -; SI-NEXT: s_lshr_b32 s4, s20, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v51, s4 -; SI-NEXT: s_lshr_b32 s4, s19, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v54, s4 -; SI-NEXT: s_lshr_b32 s4, s18, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v40, s4 -; SI-NEXT: s_lshr_b32 s4, s17, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v42, s4 -; SI-NEXT: s_lshr_b32 s4, s16, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v44, s4 -; SI-NEXT: v_cvt_f32_f16_e32 v45, s9 -; SI-NEXT: v_cvt_f32_f16_e32 v32, s6 -; SI-NEXT: v_cvt_f32_f16_e32 v34, s7 -; SI-NEXT: v_cvt_f32_f16_e32 v36, s8 -; SI-NEXT: v_cvt_f32_f16_e32 v38, s10 -; SI-NEXT: v_cvt_f32_f16_e32 v48, s11 -; SI-NEXT: v_cvt_f32_f16_e32 v15, s12 -; SI-NEXT: v_cvt_f32_f16_e32 v17, s13 -; SI-NEXT: v_cvt_f32_f16_e32 v19, s14 -; SI-NEXT: v_cvt_f32_f16_e32 v21, s15 -; SI-NEXT: v_cvt_f32_f16_e32 v23, s40 -; SI-NEXT: v_cvt_f32_f16_e32 v25, s41 -; SI-NEXT: v_cvt_f32_f16_e32 v27, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s28 -; SI-NEXT: v_cvt_f32_f16_e32 v6, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v8, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v10, s25 -; SI-NEXT: v_cvt_f32_f16_e32 v12, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v13, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v11, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v9, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v52, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v53, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v55, s18 -; SI-NEXT: v_cvt_f32_f16_e32 v41, s17 -; SI-NEXT: v_cvt_f32_f16_e32 v43, s16 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v12 +; SI-NEXT: v_cvt_f32_f16_e32 v52, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v11 +; SI-NEXT: v_cvt_f32_f16_e32 v50, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v10 +; SI-NEXT: v_cvt_f32_f16_e32 v48, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v9 +; SI-NEXT: v_cvt_f32_f16_e32 v39, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v8 +; SI-NEXT: v_cvt_f32_f16_e32 v37, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v7 +; SI-NEXT: v_cvt_f32_f16_e32 v20, v20 +; SI-NEXT: v_cvt_f32_f16_e32 v29, v12 +; SI-NEXT: v_cvt_f32_f16_e32 v35, v11 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v6 +; SI-NEXT: v_cvt_f32_f16_e32 v20, v20 +; SI-NEXT: v_cvt_f32_f16_e32 v54, v19 +; SI-NEXT: v_cvt_f32_f16_e32 v40, v22 +; SI-NEXT: v_cvt_f32_f16_e32 v42, v23 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v20, v20 +; SI-NEXT: v_cvt_f32_f16_e32 v44, v24 +; SI-NEXT: v_cvt_f32_f16_e32 v46, v26 +; SI-NEXT: v_cvt_f32_f16_e32 v56, v25 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v28, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v30, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v32, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v13 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v17 +; SI-NEXT: v_cvt_f32_f16_e32 v34, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v19 +; SI-NEXT: v_cvt_f32_f16_e32 v36, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v22 +; SI-NEXT: v_cvt_f32_f16_e32 v38, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v23 +; SI-NEXT: v_cvt_f32_f16_e32 v49, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v24 +; SI-NEXT: v_cvt_f32_f16_e32 v51, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v26 +; SI-NEXT: v_cvt_f32_f16_e32 v53, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v25 +; SI-NEXT: v_cvt_f32_f16_e32 v55, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v63 +; SI-NEXT: v_cvt_f32_f16_e32 v41, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v14 +; SI-NEXT: v_cvt_f32_f16_e32 v43, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v15 +; SI-NEXT: v_cvt_f32_f16_e32 v45, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v16 +; SI-NEXT: v_cvt_f32_f16_e32 v47, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v18 +; SI-NEXT: v_cvt_f32_f16_e32 v58, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v21 +; SI-NEXT: v_cvt_f32_f16_e32 v60, v20 +; SI-NEXT: v_cvt_f32_f16_e32 v20, v10 +; SI-NEXT: v_cvt_f32_f16_e32 v57, v63 +; SI-NEXT: v_cvt_f32_f16_e32 v59, v14 +; SI-NEXT: v_cvt_f32_f16_e32 v61, v15 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v9 +; SI-NEXT: v_cvt_f32_f16_e32 v62, v16 +; SI-NEXT: v_cvt_f32_f16_e32 v27, v21 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v8 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v7 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v6 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v5 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v4 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v3 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v2 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v1 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v13 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v17 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v18 ; SI-NEXT: s_cbranch_execnz .LBB33_3 ; SI-NEXT: .LBB33_2: ; %cmp.true -; SI-NEXT: v_add_f32_e64 v1, s16, 1.0 -; SI-NEXT: v_add_f32_e64 v2, s17, 1.0 -; SI-NEXT: v_add_f32_e64 v3, s18, 1.0 -; SI-NEXT: v_add_f32_e64 v5, s19, 1.0 -; SI-NEXT: v_add_f32_e64 v7, s20, 1.0 -; SI-NEXT: v_add_f32_e64 v9, s21, 1.0 -; SI-NEXT: v_add_f32_e64 v11, s22, 1.0 -; SI-NEXT: v_add_f32_e64 v14, s23, 1.0 -; SI-NEXT: v_add_f32_e64 v16, s24, 1.0 -; SI-NEXT: v_add_f32_e64 v18, s25, 1.0 -; SI-NEXT: v_add_f32_e64 v20, s26, 1.0 -; SI-NEXT: v_add_f32_e64 v22, s27, 1.0 -; SI-NEXT: v_add_f32_e64 v24, s28, 1.0 -; SI-NEXT: v_add_f32_e64 v27, s29, 1.0 -; SI-NEXT: v_add_f32_e64 v25, s41, 1.0 -; SI-NEXT: v_add_f32_e64 v23, s40, 1.0 -; SI-NEXT: v_add_f32_e64 v21, s15, 1.0 -; SI-NEXT: v_add_f32_e64 v19, s14, 1.0 -; SI-NEXT: v_add_f32_e64 v17, s13, 1.0 -; SI-NEXT: v_add_f32_e64 v15, s12, 1.0 -; SI-NEXT: v_add_f32_e64 v13, s11, 1.0 -; SI-NEXT: v_add_f32_e64 v12, s10, 1.0 -; SI-NEXT: v_add_f32_e64 v10, s8, 1.0 -; SI-NEXT: v_add_f32_e64 v8, s7, 1.0 -; SI-NEXT: v_add_f32_e64 v6, s6, 1.0 -; SI-NEXT: v_add_f32_e64 v29, s9, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v1 -; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v2 -; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v3 -; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v5 -; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v7 -; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v9 -; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v11 -; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v14 -; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v16 -; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v18 -; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v20 -; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v22 -; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v24 -; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v27 -; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v25 -; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v23 -; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v21 -; SI-NEXT: s_waitcnt expcnt(6) -; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v19 -; SI-NEXT: s_waitcnt expcnt(5) -; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v17 -; SI-NEXT: s_waitcnt expcnt(4) -; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v15 -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v13 -; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v12 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v10 +; SI-NEXT: v_add_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SI-NEXT: v_add_f32_e32 v13, 1.0, v13 +; SI-NEXT: v_add_f32_e32 v17, 1.0, v17 +; SI-NEXT: v_add_f32_e32 v7, 1.0, v7 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v8 -; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v6 -; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v29 -; SI-NEXT: v_cvt_f32_f16_e32 v45, v29 -; SI-NEXT: v_cvt_f32_f16_e32 v32, v6 -; SI-NEXT: v_cvt_f32_f16_e32 v34, v8 -; SI-NEXT: v_cvt_f32_f16_e32 v36, v10 -; SI-NEXT: v_cvt_f32_f16_e32 v38, v12 -; SI-NEXT: v_cvt_f32_f16_e32 v48, v13 -; SI-NEXT: v_cvt_f32_f16_e32 v15, v15 -; SI-NEXT: v_cvt_f32_f16_e32 v17, v17 -; SI-NEXT: v_cvt_f32_f16_e32 v19, v19 -; SI-NEXT: v_cvt_f32_f16_e32 v21, v21 -; SI-NEXT: v_cvt_f32_f16_e32 v23, v23 -; SI-NEXT: v_cvt_f32_f16_e32 v25, v25 -; SI-NEXT: v_cvt_f32_f16_e32 v27, v27 -; SI-NEXT: v_cvt_f32_f16_e32 v29, v24 -; SI-NEXT: v_cvt_f32_f16_e32 v6, v22 -; SI-NEXT: v_cvt_f32_f16_e32 v8, v20 -; SI-NEXT: v_cvt_f32_f16_e32 v10, v18 -; SI-NEXT: v_cvt_f32_f16_e32 v12, v16 -; SI-NEXT: v_cvt_f32_f16_e32 v13, v14 +; SI-NEXT: v_cvt_f32_f16_e32 v1, v13 +; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v7 +; SI-NEXT: v_add_f32_e32 v6, 1.0, v6 +; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v6 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v17 +; SI-NEXT: v_add_f32_e32 v21, 1.0, v21 +; SI-NEXT: v_add_f32_e32 v18, 1.0, v18 +; SI-NEXT: v_add_f32_e32 v16, 1.0, v16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v35 +; SI-NEXT: v_add_f32_e32 v15, 1.0, v15 +; SI-NEXT: v_add_f32_e32 v14, 1.0, v14 +; SI-NEXT: v_add_f32_e32 v20, 1.0, v63 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v29 +; SI-NEXT: v_add_f32_e32 v25, 1.0, v25 +; SI-NEXT: v_add_f32_e32 v26, 1.0, v26 +; SI-NEXT: v_add_f32_e32 v24, 1.0, v24 +; SI-NEXT: v_add_f32_e32 v23, 1.0, v23 +; SI-NEXT: v_add_f32_e32 v22, 1.0, v22 +; SI-NEXT: v_add_f32_e32 v19, 1.0, v19 +; SI-NEXT: v_add_f32_e32 v2, 1.0, v2 +; SI-NEXT: v_add_f32_e32 v3, 1.0, v3 +; SI-NEXT: v_add_f32_e32 v4, 1.0, v4 +; SI-NEXT: v_add_f32_e32 v5, 1.0, v5 +; SI-NEXT: v_add_f32_e32 v8, 1.0, v8 +; SI-NEXT: v_add_f32_e32 v9, 1.0, v9 +; SI-NEXT: v_add_f32_e32 v10, 1.0, v10 +; SI-NEXT: v_add_f32_e32 v11, 1.0, v11 +; SI-NEXT: v_add_f32_e32 v12, 1.0, v12 +; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v21 +; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v18 +; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v16 +; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v15 +; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v14 +; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v20 +; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v25 +; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v26 +; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v24 +; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v23 +; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v22 +; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v19 +; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v17 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v13 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v2 +; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v3 +; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v4 +; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v5 +; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v8 +; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v9 +; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v10 +; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v11 +; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v12 +; SI-NEXT: v_cvt_f32_f16_e32 v12, v12 ; SI-NEXT: v_cvt_f32_f16_e32 v11, v11 +; SI-NEXT: v_cvt_f32_f16_e32 v10, v10 ; SI-NEXT: v_cvt_f32_f16_e32 v9, v9 -; SI-NEXT: v_cvt_f32_f16_e32 v52, v7 -; SI-NEXT: v_cvt_f32_f16_e32 v53, v5 -; SI-NEXT: v_cvt_f32_f16_e32 v55, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v41, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v43, v1 -; SI-NEXT: v_cvt_f32_f16_e32 v1, v30 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v4 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v63 -; SI-NEXT: v_cvt_f32_f16_e32 v5, v62 -; SI-NEXT: v_cvt_f32_f16_e32 v7, v61 -; SI-NEXT: v_cvt_f32_f16_e32 v60, v60 -; SI-NEXT: v_cvt_f32_f16_e32 v59, v59 -; SI-NEXT: v_cvt_f32_f16_e32 v14, v58 -; SI-NEXT: v_cvt_f32_f16_e32 v16, v57 -; SI-NEXT: v_cvt_f32_f16_e32 v18, v56 -; SI-NEXT: v_cvt_f32_f16_e32 v20, v47 -; SI-NEXT: v_cvt_f32_f16_e32 v22, v46 -; SI-NEXT: v_cvt_f32_f16_e32 v24, v50 -; SI-NEXT: v_cvt_f32_f16_e32 v26, v26 +; SI-NEXT: v_cvt_f32_f16_e32 v8, v8 +; SI-NEXT: v_cvt_f32_f16_e32 v7, v7 +; SI-NEXT: v_cvt_f32_f16_e32 v6, v6 +; SI-NEXT: v_cvt_f32_f16_e32 v5, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v4, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v54, v19 +; SI-NEXT: v_cvt_f32_f16_e32 v40, v22 +; SI-NEXT: v_cvt_f32_f16_e32 v42, v23 +; SI-NEXT: v_cvt_f32_f16_e32 v44, v24 +; SI-NEXT: v_cvt_f32_f16_e32 v46, v26 +; SI-NEXT: v_cvt_f32_f16_e32 v56, v25 +; SI-NEXT: v_cvt_f32_f16_e32 v57, v20 +; SI-NEXT: v_cvt_f32_f16_e32 v59, v14 +; SI-NEXT: v_cvt_f32_f16_e32 v61, v15 +; SI-NEXT: v_cvt_f32_f16_e32 v62, v16 +; SI-NEXT: v_cvt_f32_f16_e32 v20, v18 +; SI-NEXT: v_cvt_f32_f16_e32 v27, v21 +; SI-NEXT: v_cvt_f32_f16_e32 v52, v52 +; SI-NEXT: v_cvt_f32_f16_e32 v50, v50 +; SI-NEXT: v_cvt_f32_f16_e32 v48, v48 +; SI-NEXT: v_cvt_f32_f16_e32 v39, v39 +; SI-NEXT: v_cvt_f32_f16_e32 v37, v37 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v63 ; SI-NEXT: v_cvt_f32_f16_e32 v28, v28 +; SI-NEXT: v_cvt_f32_f16_e32 v30, v30 ; SI-NEXT: v_cvt_f32_f16_e32 v31, v31 +; SI-NEXT: v_cvt_f32_f16_e32 v32, v32 ; SI-NEXT: v_cvt_f32_f16_e32 v33, v33 -; SI-NEXT: v_cvt_f32_f16_e32 v35, v35 -; SI-NEXT: v_cvt_f32_f16_e32 v37, v37 -; SI-NEXT: v_cvt_f32_f16_e32 v39, v39 +; SI-NEXT: v_cvt_f32_f16_e32 v34, v34 +; SI-NEXT: v_cvt_f32_f16_e32 v36, v36 +; SI-NEXT: v_cvt_f32_f16_e32 v38, v38 ; SI-NEXT: v_cvt_f32_f16_e32 v49, v49 ; SI-NEXT: v_cvt_f32_f16_e32 v51, v51 -; SI-NEXT: v_cvt_f32_f16_e32 v54, v54 -; SI-NEXT: v_cvt_f32_f16_e32 v40, v40 -; SI-NEXT: v_cvt_f32_f16_e32 v42, v42 -; SI-NEXT: v_cvt_f32_f16_e32 v44, v44 +; SI-NEXT: v_cvt_f32_f16_e32 v53, v53 +; SI-NEXT: v_cvt_f32_f16_e32 v55, v55 +; SI-NEXT: v_cvt_f32_f16_e32 v41, v41 +; SI-NEXT: v_cvt_f32_f16_e32 v43, v43 +; SI-NEXT: v_cvt_f32_f16_e32 v45, v45 +; SI-NEXT: v_cvt_f32_f16_e32 v47, v47 +; SI-NEXT: v_cvt_f32_f16_e32 v58, v58 +; SI-NEXT: v_cvt_f32_f16_e32 v60, v60 +; SI-NEXT: v_mov_b32_e32 v35, v11 +; SI-NEXT: v_mov_b32_e32 v29, v12 +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill ; SI-NEXT: .LBB33_3: ; %end -; SI-NEXT: v_cvt_f16_f32_e32 v4, v44 -; SI-NEXT: v_cvt_f16_f32_e32 v30, v43 -; SI-NEXT: v_cvt_f16_f32_e32 v42, v42 -; SI-NEXT: v_cvt_f16_f32_e32 v41, v41 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v30, v4 -; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v42 -; SI-NEXT: buffer_store_dword v4, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v4, vcc, 4, v0 -; SI-NEXT: v_or_b32_e32 v30, v41, v30 -; SI-NEXT: buffer_store_dword v30, v4, s[0:3], 0 offen -; SI-NEXT: v_cvt_f16_f32_e32 v4, v40 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v60 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v27 +; SI-NEXT: v_cvt_f16_f32_e32 v3, v58 +; SI-NEXT: v_cvt_f16_f32_e32 v4, v20 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3 +; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v30, v55 -; SI-NEXT: v_add_i32_e32 v55, vcc, 8, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v30, v4 -; SI-NEXT: buffer_store_dword v4, v55, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0 +; SI-NEXT: v_or_b32_e32 v2, v4, v2 +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v47 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v54 -; SI-NEXT: v_cvt_f16_f32_e32 v30, v53 -; SI-NEXT: v_add_i32_e32 v53, vcc, 12, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v30, v4 -; SI-NEXT: buffer_store_dword v4, v53, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v2, v62 +; SI-NEXT: v_add_i32_e32 v3, vcc, 8, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v51 -; SI-NEXT: v_cvt_f16_f32_e32 v30, v52 -; SI-NEXT: v_add_i32_e32 v51, vcc, 16, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v30, v4 -; SI-NEXT: buffer_store_dword v4, v51, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v45 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v61 +; SI-NEXT: v_add_i32_e32 v3, vcc, 12, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v49 -; SI-NEXT: v_cvt_f16_f32_e32 v30, v9 -; SI-NEXT: v_add_i32_e32 v49, vcc, 20, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v30, v4 -; SI-NEXT: buffer_store_dword v4, v49, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v43 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v59 +; SI-NEXT: v_add_i32_e32 v3, vcc, 16, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v39 -; SI-NEXT: v_cvt_f16_f32_e32 v30, v11 -; SI-NEXT: v_add_i32_e32 v39, vcc, 24, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v30, v4 -; SI-NEXT: buffer_store_dword v4, v39, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v41 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v57 +; SI-NEXT: v_add_i32_e32 v3, vcc, 20, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v37 -; SI-NEXT: v_cvt_f16_f32_e32 v30, v13 -; SI-NEXT: v_add_i32_e32 v37, vcc, 28, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v30, v4 -; SI-NEXT: buffer_store_dword v4, v37, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v55 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v56 +; SI-NEXT: v_add_i32_e32 v3, vcc, 24, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v35 -; SI-NEXT: v_cvt_f16_f32_e32 v30, v12 -; SI-NEXT: v_add_i32_e32 v35, vcc, 32, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v30, v4 -; SI-NEXT: buffer_store_dword v4, v35, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v53 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v46 +; SI-NEXT: v_add_i32_e32 v3, vcc, 28, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v33 -; SI-NEXT: v_cvt_f16_f32_e32 v30, v10 -; SI-NEXT: v_add_i32_e32 v33, vcc, 36, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v30, v4 -; SI-NEXT: buffer_store_dword v4, v33, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v51 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v44 +; SI-NEXT: v_add_i32_e32 v3, vcc, 32, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v31 -; SI-NEXT: v_cvt_f16_f32_e32 v30, v8 -; SI-NEXT: v_add_i32_e32 v31, vcc, 40, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v30, v4 -; SI-NEXT: buffer_store_dword v4, v31, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v49 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v42 +; SI-NEXT: v_add_i32_e32 v3, vcc, 36, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v28 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v6 -; SI-NEXT: v_add_i32_e32 v28, vcc, 44, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v6, v4 -; SI-NEXT: buffer_store_dword v4, v28, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v38 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v40 +; SI-NEXT: v_add_i32_e32 v3, vcc, 40, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v26 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v29 -; SI-NEXT: v_add_i32_e32 v26, vcc, 48, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v6, v4 -; SI-NEXT: buffer_store_dword v4, v26, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v36 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v54 +; SI-NEXT: v_add_i32_e32 v3, vcc, 44, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v24 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v27 -; SI-NEXT: v_add_i32_e32 v24, vcc, 52, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v6, v4 -; SI-NEXT: buffer_store_dword v4, v24, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v34 +; SI-NEXT: v_add_i32_e32 v3, vcc, 48, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v22 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v25 -; SI-NEXT: v_add_i32_e32 v22, vcc, 56, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v6, v4 -; SI-NEXT: buffer_store_dword v4, v22, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v33 +; SI-NEXT: v_add_i32_e32 v3, vcc, 52, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v20 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v23 -; SI-NEXT: v_add_i32_e32 v20, vcc, 60, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v6, v4 -; SI-NEXT: buffer_store_dword v4, v20, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v32 +; SI-NEXT: v_add_i32_e32 v3, vcc, 56, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v18 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v21 -; SI-NEXT: v_add_i32_e32 v18, vcc, 64, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v6, v4 -; SI-NEXT: buffer_store_dword v4, v18, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v31 +; SI-NEXT: v_add_i32_e32 v3, vcc, 60, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v16 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v19 -; SI-NEXT: v_add_i32_e32 v16, vcc, 0x44, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v6, v4 -; SI-NEXT: buffer_store_dword v4, v16, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v30 +; SI-NEXT: v_add_i32_e32 v3, vcc, 64, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v14 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v17 -; SI-NEXT: v_add_i32_e32 v14, vcc, 0x48, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v6, v4 -; SI-NEXT: buffer_store_dword v4, v14, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v28 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x44, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v59 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v15 -; SI-NEXT: v_add_i32_e32 v11, vcc, 0x4c, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v6, v4 -; SI-NEXT: buffer_store_dword v4, v11, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x48, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v60 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v48 -; SI-NEXT: v_add_i32_e32 v9, vcc, 0x50, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v6, v4 -; SI-NEXT: buffer_store_dword v4, v9, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x4c, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v7 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v38 -; SI-NEXT: v_add_i32_e32 v7, vcc, 0x54, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v6, v4 -; SI-NEXT: buffer_store_dword v4, v7, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x50, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v5 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v36 -; SI-NEXT: v_add_i32_e32 v6, vcc, 0x58, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 -; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v37 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x54, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v34 -; SI-NEXT: v_add_i32_e32 v5, vcc, 0x5c, v0 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_or_b32_e32 v3, v4, v3 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v39 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x58, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v32 -; SI-NEXT: v_add_i32_e32 v4, vcc, 0x60, v0 -; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; SI-NEXT: v_or_b32_e32 v2, v3, v2 -; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 -; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v48 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x5c, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v50 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v35 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x60, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v2, v45 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v52 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v29 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x64, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 @@ -18965,58 +18694,73 @@ define inreg <52 x half> @bitcast_v26f32_to_v52f16_scalar(<26 x float> inreg %a, ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] ; SI-NEXT: .LBB33_4: +; SI-NEXT: ; implicit-def: $vgpr29 +; SI-NEXT: ; kill: killed $vgpr29 +; SI-NEXT: ; implicit-def: $vgpr28 +; SI-NEXT: ; kill: killed $vgpr28 +; SI-NEXT: ; implicit-def: $vgpr29 +; SI-NEXT: ; kill: killed $vgpr29 +; SI-NEXT: ; implicit-def: $vgpr28 +; SI-NEXT: ; kill: killed $vgpr28 +; SI-NEXT: ; implicit-def: $vgpr27 +; SI-NEXT: ; implicit-def: $vgpr60 +; SI-NEXT: ; implicit-def: $vgpr20 +; SI-NEXT: ; implicit-def: $vgpr58 +; SI-NEXT: ; implicit-def: $vgpr62 +; SI-NEXT: ; implicit-def: $vgpr47 +; SI-NEXT: ; implicit-def: $vgpr61 +; SI-NEXT: ; implicit-def: $vgpr45 +; SI-NEXT: ; implicit-def: $vgpr59 ; SI-NEXT: ; implicit-def: $vgpr43 -; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr57 ; SI-NEXT: ; implicit-def: $vgpr41 -; SI-NEXT: ; implicit-def: $vgpr42 +; SI-NEXT: ; implicit-def: $vgpr56 ; SI-NEXT: ; implicit-def: $vgpr55 -; SI-NEXT: ; implicit-def: $vgpr40 +; SI-NEXT: ; implicit-def: $vgpr46 ; SI-NEXT: ; implicit-def: $vgpr53 -; SI-NEXT: ; implicit-def: $vgpr54 -; SI-NEXT: ; implicit-def: $vgpr52 +; SI-NEXT: ; implicit-def: $vgpr44 ; SI-NEXT: ; implicit-def: $vgpr51 -; SI-NEXT: ; implicit-def: $vgpr9 +; SI-NEXT: ; implicit-def: $vgpr42 ; SI-NEXT: ; implicit-def: $vgpr49 -; SI-NEXT: ; implicit-def: $vgpr11 -; SI-NEXT: ; implicit-def: $vgpr39 -; SI-NEXT: ; implicit-def: $vgpr13 -; SI-NEXT: ; implicit-def: $vgpr37 -; SI-NEXT: ; implicit-def: $vgpr12 -; SI-NEXT: ; implicit-def: $vgpr35 -; SI-NEXT: ; implicit-def: $vgpr10 -; SI-NEXT: ; implicit-def: $vgpr33 -; SI-NEXT: ; implicit-def: $vgpr8 -; SI-NEXT: ; implicit-def: $vgpr31 -; SI-NEXT: ; implicit-def: $vgpr6 -; SI-NEXT: ; implicit-def: $vgpr28 -; SI-NEXT: ; implicit-def: $vgpr29 -; SI-NEXT: ; implicit-def: $vgpr26 -; SI-NEXT: ; implicit-def: $vgpr27 -; SI-NEXT: ; implicit-def: $vgpr24 -; SI-NEXT: ; implicit-def: $vgpr25 -; SI-NEXT: ; implicit-def: $vgpr22 -; SI-NEXT: ; implicit-def: $vgpr23 -; SI-NEXT: ; implicit-def: $vgpr20 -; SI-NEXT: ; implicit-def: $vgpr21 -; SI-NEXT: ; implicit-def: $vgpr18 -; SI-NEXT: ; implicit-def: $vgpr19 -; SI-NEXT: ; implicit-def: $vgpr16 -; SI-NEXT: ; implicit-def: $vgpr17 -; SI-NEXT: ; implicit-def: $vgpr14 -; SI-NEXT: ; implicit-def: $vgpr15 -; SI-NEXT: ; implicit-def: $vgpr59 -; SI-NEXT: ; implicit-def: $vgpr48 -; SI-NEXT: ; implicit-def: $vgpr60 +; SI-NEXT: ; implicit-def: $vgpr40 ; SI-NEXT: ; implicit-def: $vgpr38 -; SI-NEXT: ; implicit-def: $vgpr7 +; SI-NEXT: ; implicit-def: $vgpr54 ; SI-NEXT: ; implicit-def: $vgpr36 -; SI-NEXT: ; implicit-def: $vgpr5 ; SI-NEXT: ; implicit-def: $vgpr34 -; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr33 ; SI-NEXT: ; implicit-def: $vgpr32 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr45 -; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr30 +; SI-NEXT: ; implicit-def: $vgpr37 +; SI-NEXT: ; implicit-def: $vgpr39 +; SI-NEXT: ; implicit-def: $vgpr48 +; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; implicit-def: $vgpr52 +; SI-NEXT: ; implicit-def: $vgpr29 +; SI-NEXT: ; kill: killed $vgpr29 +; SI-NEXT: ; implicit-def: $vgpr28 +; SI-NEXT: ; kill: killed $vgpr28 +; SI-NEXT: ; implicit-def: $vgpr29 +; SI-NEXT: ; kill: killed $vgpr29 +; SI-NEXT: ; implicit-def: $vgpr28 +; SI-NEXT: ; kill: killed $vgpr28 +; SI-NEXT: ; implicit-def: $vgpr29 +; SI-NEXT: ; kill: killed $vgpr29 +; SI-NEXT: ; implicit-def: $vgpr28 +; SI-NEXT: ; kill: killed $vgpr28 +; SI-NEXT: ; implicit-def: $vgpr29 +; SI-NEXT: ; kill: killed $vgpr29 +; SI-NEXT: ; implicit-def: $vgpr28 +; SI-NEXT: ; kill: killed $vgpr28 +; SI-NEXT: ; implicit-def: $vgpr29 +; SI-NEXT: ; kill: killed $vgpr29 +; SI-NEXT: ; implicit-def: $vgpr28 +; SI-NEXT: ; implicit-def: $vgpr29 +; SI-NEXT: ; kill: killed $vgpr29 +; SI-NEXT: ; implicit-def: $vgpr29 +; SI-NEXT: ; kill: killed $vgpr29 +; SI-NEXT: ; implicit-def: $vgpr29 ; SI-NEXT: s_branch .LBB33_2 ; ; VI-LABEL: bitcast_v26f32_to_v52f16_scalar: @@ -20653,7 +20397,6 @@ define <26 x float> @bitcast_v52f16_to_v26f32(<52 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v57, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v25 -; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v24 @@ -20720,6 +20463,7 @@ define <26 x float> @bitcast_v52f16_to_v26f32(<52 x half> %a, i32 %b) { ; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v56 ; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v57 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 +; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -20852,6 +20596,9 @@ define <26 x float> @bitcast_v52f16_to_v26f32(<52 x half> %a, i32 %b) { ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] ; GFX9-NEXT: s_cbranch_execz .LBB34_4 ; GFX9-NEXT: ; %bb.3: ; %cmp.true +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload @@ -20866,9 +20613,6 @@ define <26 x float> @bitcast_v52f16_to_v26f32(<52 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v34, v57, s6 ; GFX9-NEXT: s_movk_i32 s7, 0x200 ; GFX9-NEXT: v_perm_b32 v1, v62, v56, s6 @@ -20888,6 +20632,10 @@ define <26 x float> @bitcast_v52f16_to_v26f32(<52 x half> %a, i32 %b) { ; GFX9-NEXT: v_pk_add_f16 v6, v6, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v7, v7, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v8, v8, s7 op_sel_hi:[1,0] +; GFX9-NEXT: s_waitcnt vmcnt(14) +; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; GFX9-NEXT: s_waitcnt vmcnt(15) ; GFX9-NEXT: v_perm_b32 v9, v9, v40, s6 ; GFX9-NEXT: s_waitcnt vmcnt(14) @@ -20916,10 +20664,6 @@ define <26 x float> @bitcast_v52f16_to_v26f32(<52 x half> %a, i32 %b) { ; GFX9-NEXT: v_perm_b32 v21, v21, v36, s6 ; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: v_perm_b32 v22, v22, v35, s6 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v10, v10, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0] @@ -21188,14 +20932,28 @@ define inreg <26 x float> @bitcast_v52f16_to_v26f32_scalar(<52 x half> inreg %a, ; SI-NEXT: v_cvt_f16_f32_e32 v8, s26 ; SI-NEXT: v_cvt_f16_f32_e32 v6, s29 ; SI-NEXT: v_cvt_f16_f32_e32 v7, s28 -; SI-NEXT: s_waitcnt vmcnt(9) +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cvt_f16_f32_e32 v31, v31 -; SI-NEXT: s_waitcnt vmcnt(8) expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v38 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(8) expcnt(0) +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v39 -; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v44 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill @@ -21211,22 +20969,6 @@ define inreg <26 x float> @bitcast_v52f16_to_v26f32_scalar(<52 x half> inreg %a, ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v51 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB35_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload @@ -21235,8 +20977,8 @@ define inreg <26 x float> @bitcast_v52f16_to_v26f32_scalar(<52 x half> inreg %a, ; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(2) ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v53 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v12 @@ -21256,10 +20998,8 @@ define inreg <26 x float> @bitcast_v52f16_to_v26f32_scalar(<52 x half> inreg %a, ; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v42 ; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v56 ; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v43 -; SI-NEXT: s_waitcnt expcnt(1) ; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v57 ; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v15 ; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v62 ; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v36 @@ -21300,11 +21040,11 @@ define inreg <26 x float> @bitcast_v52f16_to_v26f32_scalar(<52 x half> inreg %a, ; SI-NEXT: v_or_b32_e32 v25, v38, v25 ; SI-NEXT: s_cbranch_execnz .LBB35_3 ; SI-NEXT: .LBB35_2: ; %cmp.true -; SI-NEXT: s_waitcnt expcnt(2) ; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f32_f16_e32 v0, v53 ; SI-NEXT: v_cvt_f32_f16_e32 v9, v40 ; SI-NEXT: v_cvt_f32_f16_e32 v10, v55 @@ -21318,7 +21058,6 @@ define inreg <26 x float> @bitcast_v52f16_to_v26f32_scalar(<52 x half> inreg %a, ; SI-NEXT: v_cvt_f16_f32_e32 v10, v10 ; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11 ; SI-NEXT: v_cvt_f16_f32_e32 v11, v11 -; SI-NEXT: s_waitcnt expcnt(1) ; SI-NEXT: v_cvt_f32_f16_e32 v12, v47 ; SI-NEXT: v_cvt_f32_f16_e32 v13, v60 ; SI-NEXT: v_cvt_f32_f16_e32 v15, v52 @@ -21356,7 +21095,6 @@ define inreg <26 x float> @bitcast_v52f16_to_v26f32_scalar(<52 x half> inreg %a, ; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload @@ -22006,294 +21744,109 @@ define inreg <26 x float> @bitcast_v52f16_to_v26f32_scalar(<52 x half> inreg %a, ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v191, v1 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v185, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB35_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB35_3 ; GFX11-TRUE16-NEXT: .LBB35_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s40 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s41 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v185, 0x200, v185 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v191, 0x200, v191 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v190, 0x200, v190 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v189, 0x200, v189 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v188, 0x200, v188 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v187, 0x200, v187 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v186, 0x200, v186 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, s6 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, s7 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, s8 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s9 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, s10 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, s11 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, s12 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, s13 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s14 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, s15 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, s16 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s0 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s1 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s2 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, s3 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, s4 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v35, 0x200, s5 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v44, 0x200, s6 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v54, 0x200, s7 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v65, 0x200, s8 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v77, 0x200, s9 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v90, 0x200, s10 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v104, 0x200, s11 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v119, 0x200, s12 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v135, 0x200, s13 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v152, 0x200, s14 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v170, 0x200, s15 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: .LBB35_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v170 :: v_dual_mov_b32 v18, v185 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v191 :: v_dual_mov_b32 v20, v190 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v189 :: v_dual_mov_b32 v22, v188 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v187 :: v_dual_mov_b32 v24, v186 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v191, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v190, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v189, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v188, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v187, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:316 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v14, v119 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB35_4: -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v53, v25 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v25, v53 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB35_2 ; ; GFX11-FAKE16-LABEL: bitcast_v52f16_to_v26f32_scalar: @@ -24091,18 +23644,46 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v14, s30, 0 -; SI-NEXT: v_writelane_b32 v14, s31, 1 -; SI-NEXT: v_writelane_b32 v14, s34, 2 -; SI-NEXT: v_writelane_b32 v14, s35, 3 -; SI-NEXT: v_writelane_b32 v14, s36, 4 -; SI-NEXT: v_writelane_b32 v14, s37, 5 -; SI-NEXT: v_writelane_b32 v14, s38, 6 +; SI-NEXT: v_writelane_b32 v20, s30, 0 +; SI-NEXT: v_writelane_b32 v20, s31, 1 +; SI-NEXT: v_writelane_b32 v20, s34, 2 +; SI-NEXT: v_writelane_b32 v20, s35, 3 +; SI-NEXT: v_writelane_b32 v20, s36, 4 +; SI-NEXT: v_mov_b32_e32 v14, s16 +; SI-NEXT: v_mov_b32_e32 v15, s17 +; SI-NEXT: v_writelane_b32 v20, s37, 5 +; SI-NEXT: v_mov_b32_e32 v16, s18 +; SI-NEXT: v_mov_b32_e32 v17, s19 +; SI-NEXT: v_mov_b32_e32 v18, s20 +; SI-NEXT: v_mov_b32_e32 v19, s21 +; SI-NEXT: v_readfirstlane_b32 s42, v14 +; SI-NEXT: v_mov_b32_e32 v14, s22 +; SI-NEXT: v_readfirstlane_b32 s43, v15 +; SI-NEXT: v_mov_b32_e32 v15, s23 +; SI-NEXT: v_writelane_b32 v20, s38, 6 +; SI-NEXT: v_readfirstlane_b32 s40, v16 +; SI-NEXT: v_mov_b32_e32 v16, s24 +; SI-NEXT: v_readfirstlane_b32 s41, v17 +; SI-NEXT: v_mov_b32_e32 v17, s25 +; SI-NEXT: v_readfirstlane_b32 s24, v18 +; SI-NEXT: v_mov_b32_e32 v18, s26 +; SI-NEXT: v_readfirstlane_b32 s25, v19 +; SI-NEXT: v_mov_b32_e32 v19, s27 +; SI-NEXT: v_readfirstlane_b32 s22, v14 +; SI-NEXT: v_mov_b32_e32 v14, s28 +; SI-NEXT: v_readfirstlane_b32 s23, v15 +; SI-NEXT: v_mov_b32_e32 v15, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 -; SI-NEXT: v_writelane_b32 v14, s39, 7 +; SI-NEXT: v_writelane_b32 v20, s39, 7 +; SI-NEXT: v_readfirstlane_b32 s20, v16 +; SI-NEXT: v_readfirstlane_b32 s21, v17 +; SI-NEXT: v_readfirstlane_b32 s18, v18 +; SI-NEXT: v_readfirstlane_b32 s19, v19 +; SI-NEXT: v_readfirstlane_b32 s16, v14 +; SI-NEXT: v_readfirstlane_b32 s17, v15 ; SI-NEXT: v_readfirstlane_b32 s14, v1 ; SI-NEXT: v_readfirstlane_b32 s15, v2 ; SI-NEXT: v_readfirstlane_b32 s12, v3 @@ -24114,9 +23695,9 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s6, v9 ; SI-NEXT: v_readfirstlane_b32 s7, v10 ; SI-NEXT: v_readfirstlane_b32 s4, v11 -; SI-NEXT: s_and_b64 s[40:41], vcc, exec +; SI-NEXT: s_and_b64 s[26:27], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v12 -; SI-NEXT: v_writelane_b32 v14, s48, 8 +; SI-NEXT: v_writelane_b32 v20, s48, 8 ; SI-NEXT: s_cbranch_scc0 .LBB41_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s92, s5, 16 @@ -24125,26 +23706,26 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; SI-NEXT: s_lshr_b32 s95, s11, 16 ; SI-NEXT: s_lshr_b32 s30, s13, 16 ; SI-NEXT: s_lshr_b32 s31, s15, 16 -; SI-NEXT: s_lshr_b32 s34, s29, 16 -; SI-NEXT: s_lshr_b32 s35, s27, 16 -; SI-NEXT: s_lshr_b32 s36, s25, 16 +; SI-NEXT: s_lshr_b32 s34, s17, 16 +; SI-NEXT: s_lshr_b32 s35, s19, 16 +; SI-NEXT: s_lshr_b32 s36, s21, 16 ; SI-NEXT: s_lshr_b32 s37, s23, 16 -; SI-NEXT: s_lshr_b32 s38, s21, 16 -; SI-NEXT: s_lshr_b32 s39, s19, 16 -; SI-NEXT: s_lshr_b32 s48, s17, 16 -; SI-NEXT: s_lshr_b64 s[40:41], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[42:43], s[6:7], 16 +; SI-NEXT: s_lshr_b32 s38, s25, 16 +; SI-NEXT: s_lshr_b32 s39, s41, 16 +; SI-NEXT: s_lshr_b32 s48, s43, 16 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[6:7], 16 ; SI-NEXT: s_lshr_b64 s[44:45], s[8:9], 16 ; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 16 ; SI-NEXT: s_lshr_b64 s[56:57], s[12:13], 16 ; SI-NEXT: s_lshr_b64 s[58:59], s[14:15], 16 -; SI-NEXT: s_lshr_b64 s[60:61], s[28:29], 16 -; SI-NEXT: s_lshr_b64 s[62:63], s[26:27], 16 -; SI-NEXT: s_lshr_b64 s[72:73], s[24:25], 16 +; SI-NEXT: s_lshr_b64 s[60:61], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[62:63], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[72:73], s[20:21], 16 ; SI-NEXT: s_lshr_b64 s[74:75], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[76:77], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[78:79], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[88:89], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[76:77], s[24:25], 16 +; SI-NEXT: s_lshr_b64 s[78:79], s[40:41], 16 +; SI-NEXT: s_lshr_b64 s[88:89], s[42:43], 16 ; SI-NEXT: s_cbranch_execnz .LBB41_3 ; SI-NEXT: .LBB41_2: ; %cmp.true ; SI-NEXT: s_add_u32 s4, s4, 3 @@ -24159,132 +23740,132 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; SI-NEXT: s_addc_u32 s13, s13, 0 ; SI-NEXT: s_add_u32 s14, s14, 3 ; SI-NEXT: s_addc_u32 s15, s15, 0 -; SI-NEXT: s_add_u32 s28, s28, 3 -; SI-NEXT: s_addc_u32 s29, s29, 0 -; SI-NEXT: s_add_u32 s26, s26, 3 -; SI-NEXT: s_addc_u32 s27, s27, 0 -; SI-NEXT: s_add_u32 s24, s24, 3 -; SI-NEXT: s_addc_u32 s25, s25, 0 -; SI-NEXT: s_add_u32 s22, s22, 3 -; SI-NEXT: s_addc_u32 s23, s23, 0 -; SI-NEXT: s_add_u32 s20, s20, 3 -; SI-NEXT: s_addc_u32 s21, s21, 0 -; SI-NEXT: s_add_u32 s18, s18, 3 -; SI-NEXT: s_addc_u32 s19, s19, 0 ; SI-NEXT: s_add_u32 s16, s16, 3 ; SI-NEXT: s_addc_u32 s17, s17, 0 +; SI-NEXT: s_add_u32 s18, s18, 3 +; SI-NEXT: s_addc_u32 s19, s19, 0 +; SI-NEXT: s_add_u32 s20, s20, 3 +; SI-NEXT: s_addc_u32 s21, s21, 0 +; SI-NEXT: s_add_u32 s22, s22, 3 +; SI-NEXT: s_addc_u32 s23, s23, 0 +; SI-NEXT: s_add_u32 s24, s24, 3 +; SI-NEXT: s_addc_u32 s25, s25, 0 +; SI-NEXT: s_add_u32 s40, s40, 3 +; SI-NEXT: s_addc_u32 s41, s41, 0 +; SI-NEXT: s_add_u32 s42, s42, 3 +; SI-NEXT: s_addc_u32 s43, s43, 0 ; SI-NEXT: s_lshr_b32 s92, s5, 16 ; SI-NEXT: s_lshr_b32 s93, s7, 16 ; SI-NEXT: s_lshr_b32 s94, s9, 16 ; SI-NEXT: s_lshr_b32 s95, s11, 16 ; SI-NEXT: s_lshr_b32 s30, s13, 16 ; SI-NEXT: s_lshr_b32 s31, s15, 16 -; SI-NEXT: s_lshr_b32 s34, s29, 16 -; SI-NEXT: s_lshr_b32 s35, s27, 16 -; SI-NEXT: s_lshr_b32 s36, s25, 16 +; SI-NEXT: s_lshr_b32 s34, s17, 16 +; SI-NEXT: s_lshr_b32 s35, s19, 16 +; SI-NEXT: s_lshr_b32 s36, s21, 16 ; SI-NEXT: s_lshr_b32 s37, s23, 16 -; SI-NEXT: s_lshr_b32 s38, s21, 16 -; SI-NEXT: s_lshr_b32 s39, s19, 16 -; SI-NEXT: s_lshr_b32 s48, s17, 16 -; SI-NEXT: s_lshr_b64 s[40:41], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[42:43], s[6:7], 16 +; SI-NEXT: s_lshr_b32 s38, s25, 16 +; SI-NEXT: s_lshr_b32 s39, s41, 16 +; SI-NEXT: s_lshr_b32 s48, s43, 16 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[6:7], 16 ; SI-NEXT: s_lshr_b64 s[44:45], s[8:9], 16 ; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 16 ; SI-NEXT: s_lshr_b64 s[56:57], s[12:13], 16 ; SI-NEXT: s_lshr_b64 s[58:59], s[14:15], 16 -; SI-NEXT: s_lshr_b64 s[60:61], s[28:29], 16 -; SI-NEXT: s_lshr_b64 s[62:63], s[26:27], 16 -; SI-NEXT: s_lshr_b64 s[72:73], s[24:25], 16 +; SI-NEXT: s_lshr_b64 s[60:61], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[62:63], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[72:73], s[20:21], 16 ; SI-NEXT: s_lshr_b64 s[74:75], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[76:77], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[78:79], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[88:89], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[76:77], s[24:25], 16 +; SI-NEXT: s_lshr_b64 s[78:79], s[40:41], 16 +; SI-NEXT: s_lshr_b64 s[88:89], s[42:43], 16 ; SI-NEXT: .LBB41_3: ; %end -; SI-NEXT: s_lshl_b32 s41, s88, 16 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s41 -; SI-NEXT: v_mov_b32_e32 v1, s16 -; SI-NEXT: s_and_b32 s16, s17, 0xffff -; SI-NEXT: s_lshl_b32 s17, s48, 16 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_lshl_b32 s16, s78, 16 -; SI-NEXT: s_and_b32 s17, s18, 0xffff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: v_mov_b32_e32 v3, s16 -; SI-NEXT: s_and_b32 s16, s19, 0xffff -; SI-NEXT: s_lshl_b32 s17, s39, 16 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v4, s16 -; SI-NEXT: s_lshl_b32 s16, s76, 16 -; SI-NEXT: s_and_b32 s17, s20, 0xffff -; SI-NEXT: s_or_b32 s16, s17, s16 +; SI-NEXT: s_lshl_b32 s27, s88, 16 +; SI-NEXT: s_and_b32 s29, s42, 0xffff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: v_mov_b32_e32 v1, s27 +; SI-NEXT: s_and_b32 s27, s43, 0xffff +; SI-NEXT: s_lshl_b32 s29, s48, 16 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_lshl_b32 s27, s78, 16 +; SI-NEXT: s_and_b32 s29, s40, 0xffff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: v_mov_b32_e32 v3, s27 +; SI-NEXT: s_and_b32 s27, s41, 0xffff +; SI-NEXT: s_lshl_b32 s29, s39, 16 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v4, s27 +; SI-NEXT: s_lshl_b32 s27, s76, 16 +; SI-NEXT: s_and_b32 s24, s24, 0xffff +; SI-NEXT: s_or_b32 s24, s24, s27 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0 -; SI-NEXT: v_mov_b32_e32 v5, s16 -; SI-NEXT: s_and_b32 s16, s21, 0xffff +; SI-NEXT: v_mov_b32_e32 v5, s24 +; SI-NEXT: s_and_b32 s24, s25, 0xffff ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0 -; SI-NEXT: s_lshl_b32 s17, s38, 16 +; SI-NEXT: s_lshl_b32 s25, s38, 16 ; SI-NEXT: buffer_store_dword v3, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 12, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s24, s24, s25 ; SI-NEXT: buffer_store_dword v4, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0 ; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s22, 0xffff -; SI-NEXT: s_lshl_b32 s17, s74, 16 +; SI-NEXT: v_mov_b32_e32 v2, s24 +; SI-NEXT: s_and_b32 s22, s22, 0xffff +; SI-NEXT: s_lshl_b32 s24, s74, 16 ; SI-NEXT: buffer_store_dword v5, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 20, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s22, s22, s24 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s23, 0xffff -; SI-NEXT: s_lshl_b32 s17, s37, 16 +; SI-NEXT: v_mov_b32_e32 v2, s22 +; SI-NEXT: s_and_b32 s22, s23, 0xffff +; SI-NEXT: s_lshl_b32 s23, s37, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s22, s22, s23 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s24, 0xffff -; SI-NEXT: s_lshl_b32 s17, s72, 16 +; SI-NEXT: v_mov_b32_e32 v2, s22 +; SI-NEXT: s_and_b32 s20, s20, 0xffff +; SI-NEXT: s_lshl_b32 s22, s72, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 28, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s20, s20, s22 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s25, 0xffff -; SI-NEXT: s_lshl_b32 s17, s36, 16 +; SI-NEXT: v_mov_b32_e32 v2, s20 +; SI-NEXT: s_and_b32 s20, s21, 0xffff +; SI-NEXT: s_lshl_b32 s21, s36, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s20, s20, s21 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s26, 0xffff -; SI-NEXT: s_lshl_b32 s17, s62, 16 +; SI-NEXT: v_mov_b32_e32 v2, s20 +; SI-NEXT: s_and_b32 s18, s18, 0xffff +; SI-NEXT: s_lshl_b32 s20, s62, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 36, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s18, s18, s20 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s27, 0xffff -; SI-NEXT: s_lshl_b32 s17, s35, 16 +; SI-NEXT: v_mov_b32_e32 v2, s18 +; SI-NEXT: s_and_b32 s18, s19, 0xffff +; SI-NEXT: s_lshl_b32 s19, s35, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s18, s18, s19 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s28, 0xffff -; SI-NEXT: s_lshl_b32 s17, s60, 16 +; SI-NEXT: v_mov_b32_e32 v2, s18 +; SI-NEXT: s_and_b32 s16, s16, 0xffff +; SI-NEXT: s_lshl_b32 s18, s60, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 44, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s16, s16, s18 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s29, 0xffff +; SI-NEXT: s_and_b32 s16, s17, 0xffff ; SI-NEXT: s_lshl_b32 s17, s34, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0 ; SI-NEXT: s_or_b32 s16, s16, s17 @@ -24348,7 +23929,7 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s8 ; SI-NEXT: s_and_b32 s6, s6, 0xffff -; SI-NEXT: s_lshl_b32 s8, s42, 16 +; SI-NEXT: s_lshl_b32 s8, s28, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x54, v0 ; SI-NEXT: s_or_b32 s6, s6, s8 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen @@ -24362,7 +23943,7 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s6 ; SI-NEXT: s_and_b32 s4, s4, 0xffff -; SI-NEXT: s_lshl_b32 s6, s40, 16 +; SI-NEXT: s_lshl_b32 s6, s26, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x5c, v0 ; SI-NEXT: s_or_b32 s4, s4, s6 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen @@ -24376,17 +23957,17 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x64, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s48, v14, 8 -; SI-NEXT: v_readlane_b32 s39, v14, 7 -; SI-NEXT: v_readlane_b32 s38, v14, 6 -; SI-NEXT: v_readlane_b32 s37, v14, 5 -; SI-NEXT: v_readlane_b32 s36, v14, 4 -; SI-NEXT: v_readlane_b32 s35, v14, 3 -; SI-NEXT: v_readlane_b32 s34, v14, 2 -; SI-NEXT: v_readlane_b32 s31, v14, 1 -; SI-NEXT: v_readlane_b32 s30, v14, 0 +; SI-NEXT: v_readlane_b32 s48, v20, 8 +; SI-NEXT: v_readlane_b32 s39, v20, 7 +; SI-NEXT: v_readlane_b32 s38, v20, 6 +; SI-NEXT: v_readlane_b32 s37, v20, 5 +; SI-NEXT: v_readlane_b32 s36, v20, 4 +; SI-NEXT: v_readlane_b32 s35, v20, 3 +; SI-NEXT: v_readlane_b32 s34, v20, 2 +; SI-NEXT: v_readlane_b32 s31, v20, 1 +; SI-NEXT: v_readlane_b32 s30, v20, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] @@ -24415,16 +23996,44 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; SI-NEXT: ; implicit-def: $sgpr94 ; SI-NEXT: ; implicit-def: $sgpr93 ; SI-NEXT: ; implicit-def: $sgpr92 -; SI-NEXT: ; implicit-def: $sgpr42 -; SI-NEXT: ; implicit-def: $sgpr40 +; SI-NEXT: ; implicit-def: $sgpr28 +; SI-NEXT: ; implicit-def: $sgpr26 ; SI-NEXT: s_branch .LBB41_2 ; ; VI-LABEL: bitcast_v13i64_to_v52i16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v13, s16 +; VI-NEXT: v_mov_b32_e32 v14, s17 +; VI-NEXT: v_mov_b32_e32 v15, s18 +; VI-NEXT: v_mov_b32_e32 v16, s19 +; VI-NEXT: v_mov_b32_e32 v17, s20 +; VI-NEXT: v_mov_b32_e32 v18, s21 +; VI-NEXT: v_mov_b32_e32 v19, s22 +; VI-NEXT: v_readfirstlane_b32 s44, v13 +; VI-NEXT: v_mov_b32_e32 v13, s23 +; VI-NEXT: v_readfirstlane_b32 s43, v14 +; VI-NEXT: v_mov_b32_e32 v14, s24 +; VI-NEXT: v_readfirstlane_b32 s42, v15 +; VI-NEXT: v_mov_b32_e32 v15, s25 +; VI-NEXT: v_readfirstlane_b32 s41, v16 +; VI-NEXT: v_mov_b32_e32 v16, s26 +; VI-NEXT: v_readfirstlane_b32 s40, v17 +; VI-NEXT: v_mov_b32_e32 v17, s27 +; VI-NEXT: v_readfirstlane_b32 s26, v18 +; VI-NEXT: v_mov_b32_e32 v18, s28 +; VI-NEXT: v_readfirstlane_b32 s25, v19 +; VI-NEXT: v_mov_b32_e32 v19, s29 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 -; VI-NEXT: v_readfirstlane_b32 s41, v0 -; VI-NEXT: v_readfirstlane_b32 s40, v1 +; VI-NEXT: v_readfirstlane_b32 s24, v13 +; VI-NEXT: v_readfirstlane_b32 s23, v14 +; VI-NEXT: v_readfirstlane_b32 s22, v15 +; VI-NEXT: v_readfirstlane_b32 s21, v16 +; VI-NEXT: v_readfirstlane_b32 s20, v17 +; VI-NEXT: v_readfirstlane_b32 s19, v18 +; VI-NEXT: v_readfirstlane_b32 s18, v19 +; VI-NEXT: v_readfirstlane_b32 s17, v0 +; VI-NEXT: v_readfirstlane_b32 s16, v1 ; VI-NEXT: v_readfirstlane_b32 s15, v2 ; VI-NEXT: v_readfirstlane_b32 s14, v3 ; VI-NEXT: v_readfirstlane_b32 s13, v4 @@ -24438,9 +24047,9 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; VI-NEXT: v_readfirstlane_b32 s7, v11 ; VI-NEXT: s_cbranch_scc0 .LBB41_4 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_lshr_b32 s42, s7, 16 -; VI-NEXT: s_lshr_b32 s43, s6, 16 -; VI-NEXT: s_lshr_b32 s44, s8, 16 +; VI-NEXT: s_lshr_b32 s27, s7, 16 +; VI-NEXT: s_lshr_b32 s28, s6, 16 +; VI-NEXT: s_lshr_b32 s29, s8, 16 ; VI-NEXT: s_lshr_b32 s45, s9, 16 ; VI-NEXT: s_lshr_b32 s46, s10, 16 ; VI-NEXT: s_lshr_b32 s47, s11, 16 @@ -24448,22 +24057,22 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; VI-NEXT: s_lshr_b32 s57, s13, 16 ; VI-NEXT: s_lshr_b32 s58, s14, 16 ; VI-NEXT: s_lshr_b32 s59, s15, 16 -; VI-NEXT: s_lshr_b32 s60, s40, 16 -; VI-NEXT: s_lshr_b32 s61, s41, 16 -; VI-NEXT: s_lshr_b32 s62, s29, 16 -; VI-NEXT: s_lshr_b32 s63, s28, 16 -; VI-NEXT: s_lshr_b32 s72, s27, 16 -; VI-NEXT: s_lshr_b32 s73, s26, 16 -; VI-NEXT: s_lshr_b32 s74, s25, 16 -; VI-NEXT: s_lshr_b32 s75, s24, 16 -; VI-NEXT: s_lshr_b32 s76, s23, 16 -; VI-NEXT: s_lshr_b32 s77, s22, 16 -; VI-NEXT: s_lshr_b32 s78, s21, 16 -; VI-NEXT: s_lshr_b32 s79, s20, 16 -; VI-NEXT: s_lshr_b32 s88, s19, 16 -; VI-NEXT: s_lshr_b32 s89, s18, 16 -; VI-NEXT: s_lshr_b32 s90, s17, 16 -; VI-NEXT: s_lshr_b32 s91, s16, 16 +; VI-NEXT: s_lshr_b32 s60, s16, 16 +; VI-NEXT: s_lshr_b32 s61, s17, 16 +; VI-NEXT: s_lshr_b32 s62, s18, 16 +; VI-NEXT: s_lshr_b32 s63, s19, 16 +; VI-NEXT: s_lshr_b32 s72, s20, 16 +; VI-NEXT: s_lshr_b32 s73, s21, 16 +; VI-NEXT: s_lshr_b32 s74, s22, 16 +; VI-NEXT: s_lshr_b32 s75, s23, 16 +; VI-NEXT: s_lshr_b32 s76, s24, 16 +; VI-NEXT: s_lshr_b32 s77, s25, 16 +; VI-NEXT: s_lshr_b32 s78, s26, 16 +; VI-NEXT: s_lshr_b32 s79, s40, 16 +; VI-NEXT: s_lshr_b32 s88, s41, 16 +; VI-NEXT: s_lshr_b32 s89, s42, 16 +; VI-NEXT: s_lshr_b32 s90, s43, 16 +; VI-NEXT: s_lshr_b32 s91, s44, 16 ; VI-NEXT: s_cbranch_execnz .LBB41_3 ; VI-NEXT: .LBB41_2: ; %cmp.true ; VI-NEXT: s_add_u32 s6, s6, 3 @@ -24476,25 +24085,25 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; VI-NEXT: s_addc_u32 s12, s12, 0 ; VI-NEXT: s_add_u32 s15, s15, 3 ; VI-NEXT: s_addc_u32 s14, s14, 0 -; VI-NEXT: s_add_u32 s41, s41, 3 -; VI-NEXT: s_addc_u32 s40, s40, 0 -; VI-NEXT: s_add_u32 s28, s28, 3 -; VI-NEXT: s_addc_u32 s29, s29, 0 -; VI-NEXT: s_add_u32 s26, s26, 3 -; VI-NEXT: s_addc_u32 s27, s27, 0 -; VI-NEXT: s_add_u32 s24, s24, 3 -; VI-NEXT: s_addc_u32 s25, s25, 0 -; VI-NEXT: s_add_u32 s22, s22, 3 -; VI-NEXT: s_addc_u32 s23, s23, 0 -; VI-NEXT: s_add_u32 s20, s20, 3 -; VI-NEXT: s_addc_u32 s21, s21, 0 -; VI-NEXT: s_add_u32 s18, s18, 3 -; VI-NEXT: s_addc_u32 s19, s19, 0 -; VI-NEXT: s_add_u32 s16, s16, 3 -; VI-NEXT: s_addc_u32 s17, s17, 0 -; VI-NEXT: s_lshr_b32 s42, s7, 16 -; VI-NEXT: s_lshr_b32 s43, s6, 16 -; VI-NEXT: s_lshr_b32 s44, s8, 16 +; VI-NEXT: s_add_u32 s17, s17, 3 +; VI-NEXT: s_addc_u32 s16, s16, 0 +; VI-NEXT: s_add_u32 s19, s19, 3 +; VI-NEXT: s_addc_u32 s18, s18, 0 +; VI-NEXT: s_add_u32 s21, s21, 3 +; VI-NEXT: s_addc_u32 s20, s20, 0 +; VI-NEXT: s_add_u32 s23, s23, 3 +; VI-NEXT: s_addc_u32 s22, s22, 0 +; VI-NEXT: s_add_u32 s25, s25, 3 +; VI-NEXT: s_addc_u32 s24, s24, 0 +; VI-NEXT: s_add_u32 s40, s40, 3 +; VI-NEXT: s_addc_u32 s26, s26, 0 +; VI-NEXT: s_add_u32 s42, s42, 3 +; VI-NEXT: s_addc_u32 s41, s41, 0 +; VI-NEXT: s_add_u32 s44, s44, 3 +; VI-NEXT: s_addc_u32 s43, s43, 0 +; VI-NEXT: s_lshr_b32 s27, s7, 16 +; VI-NEXT: s_lshr_b32 s28, s6, 16 +; VI-NEXT: s_lshr_b32 s29, s8, 16 ; VI-NEXT: s_lshr_b32 s45, s9, 16 ; VI-NEXT: s_lshr_b32 s46, s10, 16 ; VI-NEXT: s_lshr_b32 s47, s11, 16 @@ -24502,117 +24111,117 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; VI-NEXT: s_lshr_b32 s57, s13, 16 ; VI-NEXT: s_lshr_b32 s58, s14, 16 ; VI-NEXT: s_lshr_b32 s59, s15, 16 -; VI-NEXT: s_lshr_b32 s60, s40, 16 -; VI-NEXT: s_lshr_b32 s61, s41, 16 -; VI-NEXT: s_lshr_b32 s62, s29, 16 -; VI-NEXT: s_lshr_b32 s63, s28, 16 -; VI-NEXT: s_lshr_b32 s72, s27, 16 -; VI-NEXT: s_lshr_b32 s73, s26, 16 -; VI-NEXT: s_lshr_b32 s74, s25, 16 -; VI-NEXT: s_lshr_b32 s75, s24, 16 -; VI-NEXT: s_lshr_b32 s76, s23, 16 -; VI-NEXT: s_lshr_b32 s77, s22, 16 -; VI-NEXT: s_lshr_b32 s78, s21, 16 -; VI-NEXT: s_lshr_b32 s79, s20, 16 -; VI-NEXT: s_lshr_b32 s88, s19, 16 -; VI-NEXT: s_lshr_b32 s89, s18, 16 -; VI-NEXT: s_lshr_b32 s90, s17, 16 -; VI-NEXT: s_lshr_b32 s91, s16, 16 +; VI-NEXT: s_lshr_b32 s60, s16, 16 +; VI-NEXT: s_lshr_b32 s61, s17, 16 +; VI-NEXT: s_lshr_b32 s62, s18, 16 +; VI-NEXT: s_lshr_b32 s63, s19, 16 +; VI-NEXT: s_lshr_b32 s72, s20, 16 +; VI-NEXT: s_lshr_b32 s73, s21, 16 +; VI-NEXT: s_lshr_b32 s74, s22, 16 +; VI-NEXT: s_lshr_b32 s75, s23, 16 +; VI-NEXT: s_lshr_b32 s76, s24, 16 +; VI-NEXT: s_lshr_b32 s77, s25, 16 +; VI-NEXT: s_lshr_b32 s78, s26, 16 +; VI-NEXT: s_lshr_b32 s79, s40, 16 +; VI-NEXT: s_lshr_b32 s88, s41, 16 +; VI-NEXT: s_lshr_b32 s89, s42, 16 +; VI-NEXT: s_lshr_b32 s90, s43, 16 +; VI-NEXT: s_lshr_b32 s91, s44, 16 ; VI-NEXT: .LBB41_3: ; %end -; VI-NEXT: s_and_b32 s4, 0xffff, s16 +; VI-NEXT: s_and_b32 s4, 0xffff, s44 ; VI-NEXT: s_lshl_b32 s5, s91, 16 ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_and_b32 s5, 0xffff, s17 -; VI-NEXT: s_lshl_b32 s16, s90, 16 -; VI-NEXT: s_or_b32 s5, s5, s16 -; VI-NEXT: s_and_b32 s16, 0xffff, s18 -; VI-NEXT: s_lshl_b32 s17, s89, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, 0xffff, s19 -; VI-NEXT: s_lshl_b32 s18, s88, 16 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s18, 0xffff, s20 -; VI-NEXT: s_lshl_b32 s19, s79, 16 -; VI-NEXT: s_or_b32 s18, s18, s19 -; VI-NEXT: s_and_b32 s19, 0xffff, s21 -; VI-NEXT: s_lshl_b32 s20, s78, 16 -; VI-NEXT: s_or_b32 s19, s19, s20 -; VI-NEXT: s_and_b32 s20, 0xffff, s22 -; VI-NEXT: s_lshl_b32 s21, s77, 16 -; VI-NEXT: s_or_b32 s20, s20, s21 -; VI-NEXT: s_and_b32 s21, 0xffff, s23 -; VI-NEXT: s_lshl_b32 s22, s76, 16 -; VI-NEXT: s_or_b32 s21, s21, s22 -; VI-NEXT: s_and_b32 s22, 0xffff, s24 -; VI-NEXT: s_lshl_b32 s23, s75, 16 -; VI-NEXT: s_or_b32 s22, s22, s23 -; VI-NEXT: s_and_b32 s23, 0xffff, s25 -; VI-NEXT: s_lshl_b32 s24, s74, 16 -; VI-NEXT: s_or_b32 s23, s23, s24 -; VI-NEXT: s_and_b32 s24, 0xffff, s26 -; VI-NEXT: s_lshl_b32 s25, s73, 16 -; VI-NEXT: s_or_b32 s24, s24, s25 -; VI-NEXT: s_and_b32 s25, 0xffff, s27 -; VI-NEXT: s_lshl_b32 s26, s72, 16 -; VI-NEXT: s_or_b32 s25, s25, s26 -; VI-NEXT: s_and_b32 s26, 0xffff, s28 -; VI-NEXT: s_lshl_b32 s27, s63, 16 -; VI-NEXT: s_or_b32 s26, s26, s27 -; VI-NEXT: s_and_b32 s27, 0xffff, s29 -; VI-NEXT: s_lshl_b32 s28, s62, 16 -; VI-NEXT: s_or_b32 s27, s27, s28 -; VI-NEXT: s_and_b32 s28, 0xffff, s41 -; VI-NEXT: s_lshl_b32 s29, s61, 16 -; VI-NEXT: s_or_b32 s28, s28, s29 -; VI-NEXT: s_and_b32 s29, 0xffff, s40 -; VI-NEXT: s_lshl_b32 s40, s60, 16 -; VI-NEXT: s_or_b32 s29, s29, s40 +; VI-NEXT: s_and_b32 s5, 0xffff, s43 +; VI-NEXT: s_lshl_b32 s43, s90, 16 +; VI-NEXT: s_or_b32 s5, s5, s43 +; VI-NEXT: s_and_b32 s42, 0xffff, s42 +; VI-NEXT: s_lshl_b32 s43, s89, 16 +; VI-NEXT: s_or_b32 s42, s42, s43 +; VI-NEXT: s_and_b32 s41, 0xffff, s41 +; VI-NEXT: s_lshl_b32 s43, s88, 16 +; VI-NEXT: s_or_b32 s41, s41, s43 +; VI-NEXT: s_and_b32 s40, 0xffff, s40 +; VI-NEXT: s_lshl_b32 s43, s79, 16 +; VI-NEXT: s_or_b32 s40, s40, s43 +; VI-NEXT: s_and_b32 s26, 0xffff, s26 +; VI-NEXT: s_lshl_b32 s43, s78, 16 +; VI-NEXT: s_or_b32 s26, s26, s43 +; VI-NEXT: s_and_b32 s25, 0xffff, s25 +; VI-NEXT: s_lshl_b32 s43, s77, 16 +; VI-NEXT: s_or_b32 s25, s25, s43 +; VI-NEXT: s_and_b32 s24, 0xffff, s24 +; VI-NEXT: s_lshl_b32 s43, s76, 16 +; VI-NEXT: s_or_b32 s24, s24, s43 +; VI-NEXT: s_and_b32 s23, 0xffff, s23 +; VI-NEXT: s_lshl_b32 s43, s75, 16 +; VI-NEXT: s_or_b32 s23, s23, s43 +; VI-NEXT: s_and_b32 s22, 0xffff, s22 +; VI-NEXT: s_lshl_b32 s43, s74, 16 +; VI-NEXT: s_or_b32 s22, s22, s43 +; VI-NEXT: s_and_b32 s21, 0xffff, s21 +; VI-NEXT: s_lshl_b32 s43, s73, 16 +; VI-NEXT: s_or_b32 s21, s21, s43 +; VI-NEXT: s_and_b32 s20, 0xffff, s20 +; VI-NEXT: s_lshl_b32 s43, s72, 16 +; VI-NEXT: s_or_b32 s20, s20, s43 +; VI-NEXT: s_and_b32 s19, 0xffff, s19 +; VI-NEXT: s_lshl_b32 s43, s63, 16 +; VI-NEXT: s_or_b32 s19, s19, s43 +; VI-NEXT: s_and_b32 s18, 0xffff, s18 +; VI-NEXT: s_lshl_b32 s43, s62, 16 +; VI-NEXT: s_or_b32 s18, s18, s43 +; VI-NEXT: s_and_b32 s17, 0xffff, s17 +; VI-NEXT: s_lshl_b32 s43, s61, 16 +; VI-NEXT: s_or_b32 s17, s17, s43 +; VI-NEXT: s_and_b32 s16, 0xffff, s16 +; VI-NEXT: s_lshl_b32 s43, s60, 16 +; VI-NEXT: s_or_b32 s16, s16, s43 ; VI-NEXT: s_and_b32 s15, 0xffff, s15 -; VI-NEXT: s_lshl_b32 s40, s59, 16 -; VI-NEXT: s_or_b32 s15, s15, s40 +; VI-NEXT: s_lshl_b32 s43, s59, 16 +; VI-NEXT: s_or_b32 s15, s15, s43 ; VI-NEXT: s_and_b32 s14, 0xffff, s14 -; VI-NEXT: s_lshl_b32 s40, s58, 16 -; VI-NEXT: s_or_b32 s14, s14, s40 +; VI-NEXT: s_lshl_b32 s43, s58, 16 +; VI-NEXT: s_or_b32 s14, s14, s43 ; VI-NEXT: s_and_b32 s13, 0xffff, s13 -; VI-NEXT: s_lshl_b32 s40, s57, 16 -; VI-NEXT: s_or_b32 s13, s13, s40 +; VI-NEXT: s_lshl_b32 s43, s57, 16 +; VI-NEXT: s_or_b32 s13, s13, s43 ; VI-NEXT: s_and_b32 s12, 0xffff, s12 -; VI-NEXT: s_lshl_b32 s40, s56, 16 -; VI-NEXT: s_or_b32 s12, s12, s40 +; VI-NEXT: s_lshl_b32 s43, s56, 16 +; VI-NEXT: s_or_b32 s12, s12, s43 ; VI-NEXT: s_and_b32 s11, 0xffff, s11 -; VI-NEXT: s_lshl_b32 s40, s47, 16 -; VI-NEXT: s_or_b32 s11, s11, s40 +; VI-NEXT: s_lshl_b32 s43, s47, 16 +; VI-NEXT: s_or_b32 s11, s11, s43 ; VI-NEXT: s_and_b32 s10, 0xffff, s10 -; VI-NEXT: s_lshl_b32 s40, s46, 16 -; VI-NEXT: s_or_b32 s10, s10, s40 +; VI-NEXT: s_lshl_b32 s43, s46, 16 +; VI-NEXT: s_or_b32 s10, s10, s43 ; VI-NEXT: s_and_b32 s9, 0xffff, s9 -; VI-NEXT: s_lshl_b32 s40, s45, 16 -; VI-NEXT: s_or_b32 s9, s9, s40 +; VI-NEXT: s_lshl_b32 s43, s45, 16 ; VI-NEXT: s_and_b32 s8, 0xffff, s8 -; VI-NEXT: s_lshl_b32 s40, s44, 16 -; VI-NEXT: s_or_b32 s8, s8, s40 +; VI-NEXT: s_lshl_b32 s29, s29, 16 ; VI-NEXT: s_and_b32 s6, 0xffff, s6 -; VI-NEXT: s_lshl_b32 s40, s43, 16 -; VI-NEXT: s_or_b32 s6, s6, s40 +; VI-NEXT: s_lshl_b32 s28, s28, 16 ; VI-NEXT: s_and_b32 s7, 0xffff, s7 -; VI-NEXT: s_lshl_b32 s40, s42, 16 -; VI-NEXT: s_or_b32 s7, s7, s40 +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s9, s9, s43 +; VI-NEXT: s_or_b32 s8, s8, s29 +; VI-NEXT: s_or_b32 s6, s6, s28 +; VI-NEXT: s_or_b32 s7, s7, s27 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s5 -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: v_mov_b32_e32 v3, s17 -; VI-NEXT: v_mov_b32_e32 v4, s18 -; VI-NEXT: v_mov_b32_e32 v5, s19 -; VI-NEXT: v_mov_b32_e32 v6, s20 -; VI-NEXT: v_mov_b32_e32 v7, s21 -; VI-NEXT: v_mov_b32_e32 v8, s22 -; VI-NEXT: v_mov_b32_e32 v9, s23 -; VI-NEXT: v_mov_b32_e32 v10, s24 -; VI-NEXT: v_mov_b32_e32 v11, s25 -; VI-NEXT: v_mov_b32_e32 v12, s26 -; VI-NEXT: v_mov_b32_e32 v13, s27 -; VI-NEXT: v_mov_b32_e32 v14, s28 -; VI-NEXT: v_mov_b32_e32 v15, s29 +; VI-NEXT: v_mov_b32_e32 v2, s42 +; VI-NEXT: v_mov_b32_e32 v3, s41 +; VI-NEXT: v_mov_b32_e32 v4, s40 +; VI-NEXT: v_mov_b32_e32 v5, s26 +; VI-NEXT: v_mov_b32_e32 v6, s25 +; VI-NEXT: v_mov_b32_e32 v7, s24 +; VI-NEXT: v_mov_b32_e32 v8, s23 +; VI-NEXT: v_mov_b32_e32 v9, s22 +; VI-NEXT: v_mov_b32_e32 v10, s21 +; VI-NEXT: v_mov_b32_e32 v11, s20 +; VI-NEXT: v_mov_b32_e32 v12, s19 +; VI-NEXT: v_mov_b32_e32 v13, s18 +; VI-NEXT: v_mov_b32_e32 v14, s17 +; VI-NEXT: v_mov_b32_e32 v15, s16 ; VI-NEXT: v_mov_b32_e32 v16, s15 ; VI-NEXT: v_mov_b32_e32 v17, s14 ; VI-NEXT: v_mov_b32_e32 v18, s13 @@ -24648,25 +24257,53 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; VI-NEXT: ; implicit-def: $sgpr47 ; VI-NEXT: ; implicit-def: $sgpr46 ; VI-NEXT: ; implicit-def: $sgpr45 -; VI-NEXT: ; implicit-def: $sgpr44 -; VI-NEXT: ; implicit-def: $sgpr43 -; VI-NEXT: ; implicit-def: $sgpr42 +; VI-NEXT: ; implicit-def: $sgpr29 +; VI-NEXT: ; implicit-def: $sgpr28 +; VI-NEXT: ; implicit-def: $sgpr27 ; VI-NEXT: s_branch .LBB41_2 ; ; GFX9-LABEL: bitcast_v13i64_to_v52i16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v13, s16 +; GFX9-NEXT: v_mov_b32_e32 v14, s17 +; GFX9-NEXT: v_mov_b32_e32 v15, s18 +; GFX9-NEXT: v_mov_b32_e32 v16, s19 +; GFX9-NEXT: v_mov_b32_e32 v17, s20 +; GFX9-NEXT: v_mov_b32_e32 v18, s21 +; GFX9-NEXT: v_mov_b32_e32 v19, s22 +; GFX9-NEXT: v_readfirstlane_b32 s6, v13 +; GFX9-NEXT: v_mov_b32_e32 v13, s23 +; GFX9-NEXT: v_readfirstlane_b32 s7, v14 +; GFX9-NEXT: v_mov_b32_e32 v14, s24 +; GFX9-NEXT: v_readfirstlane_b32 s8, v15 +; GFX9-NEXT: v_mov_b32_e32 v15, s25 +; GFX9-NEXT: v_readfirstlane_b32 s9, v16 +; GFX9-NEXT: v_mov_b32_e32 v16, s26 +; GFX9-NEXT: v_readfirstlane_b32 s10, v17 +; GFX9-NEXT: v_mov_b32_e32 v17, s27 +; GFX9-NEXT: v_readfirstlane_b32 s11, v18 +; GFX9-NEXT: v_mov_b32_e32 v18, s28 +; GFX9-NEXT: v_readfirstlane_b32 s12, v19 +; GFX9-NEXT: v_mov_b32_e32 v19, s29 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 -; GFX9-NEXT: v_readfirstlane_b32 s6, v0 -; GFX9-NEXT: v_readfirstlane_b32 s7, v1 -; GFX9-NEXT: v_readfirstlane_b32 s8, v2 -; GFX9-NEXT: v_readfirstlane_b32 s9, v3 -; GFX9-NEXT: v_readfirstlane_b32 s10, v4 -; GFX9-NEXT: v_readfirstlane_b32 s11, v5 -; GFX9-NEXT: v_readfirstlane_b32 s12, v6 -; GFX9-NEXT: v_readfirstlane_b32 s13, v7 -; GFX9-NEXT: v_readfirstlane_b32 s14, v8 -; GFX9-NEXT: v_readfirstlane_b32 s15, v9 +; GFX9-NEXT: v_readfirstlane_b32 s13, v13 +; GFX9-NEXT: v_readfirstlane_b32 s14, v14 +; GFX9-NEXT: v_readfirstlane_b32 s15, v15 +; GFX9-NEXT: v_readfirstlane_b32 s16, v16 +; GFX9-NEXT: v_readfirstlane_b32 s17, v17 +; GFX9-NEXT: v_readfirstlane_b32 s18, v18 +; GFX9-NEXT: v_readfirstlane_b32 s19, v19 +; GFX9-NEXT: v_readfirstlane_b32 s20, v0 +; GFX9-NEXT: v_readfirstlane_b32 s21, v1 +; GFX9-NEXT: v_readfirstlane_b32 s22, v2 +; GFX9-NEXT: v_readfirstlane_b32 s23, v3 +; GFX9-NEXT: v_readfirstlane_b32 s24, v4 +; GFX9-NEXT: v_readfirstlane_b32 s25, v5 +; GFX9-NEXT: v_readfirstlane_b32 s26, v6 +; GFX9-NEXT: v_readfirstlane_b32 s27, v7 +; GFX9-NEXT: v_readfirstlane_b32 s28, v8 +; GFX9-NEXT: v_readfirstlane_b32 s29, v9 ; GFX9-NEXT: v_readfirstlane_b32 s40, v10 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s41, v11 @@ -24674,44 +24311,34 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_lshr_b32 s42, s41, 16 ; GFX9-NEXT: s_lshr_b32 s43, s40, 16 -; GFX9-NEXT: s_lshr_b32 s44, s15, 16 -; GFX9-NEXT: s_lshr_b32 s45, s14, 16 -; GFX9-NEXT: s_lshr_b32 s46, s13, 16 -; GFX9-NEXT: s_lshr_b32 s47, s12, 16 -; GFX9-NEXT: s_lshr_b32 s56, s11, 16 -; GFX9-NEXT: s_lshr_b32 s57, s10, 16 -; GFX9-NEXT: s_lshr_b32 s58, s9, 16 -; GFX9-NEXT: s_lshr_b32 s59, s8, 16 -; GFX9-NEXT: s_lshr_b32 s60, s7, 16 -; GFX9-NEXT: s_lshr_b32 s61, s6, 16 -; GFX9-NEXT: s_lshr_b32 s62, s29, 16 -; GFX9-NEXT: s_lshr_b32 s63, s28, 16 -; GFX9-NEXT: s_lshr_b32 s72, s27, 16 -; GFX9-NEXT: s_lshr_b32 s73, s26, 16 -; GFX9-NEXT: s_lshr_b32 s74, s25, 16 -; GFX9-NEXT: s_lshr_b32 s75, s24, 16 -; GFX9-NEXT: s_lshr_b32 s76, s23, 16 -; GFX9-NEXT: s_lshr_b32 s77, s22, 16 -; GFX9-NEXT: s_lshr_b32 s78, s21, 16 -; GFX9-NEXT: s_lshr_b32 s79, s20, 16 -; GFX9-NEXT: s_lshr_b32 s88, s19, 16 -; GFX9-NEXT: s_lshr_b32 s89, s18, 16 -; GFX9-NEXT: s_lshr_b32 s90, s17, 16 -; GFX9-NEXT: s_lshr_b32 s91, s16, 16 +; GFX9-NEXT: s_lshr_b32 s44, s29, 16 +; GFX9-NEXT: s_lshr_b32 s45, s28, 16 +; GFX9-NEXT: s_lshr_b32 s46, s27, 16 +; GFX9-NEXT: s_lshr_b32 s47, s26, 16 +; GFX9-NEXT: s_lshr_b32 s56, s25, 16 +; GFX9-NEXT: s_lshr_b32 s57, s24, 16 +; GFX9-NEXT: s_lshr_b32 s58, s23, 16 +; GFX9-NEXT: s_lshr_b32 s59, s22, 16 +; GFX9-NEXT: s_lshr_b32 s60, s21, 16 +; GFX9-NEXT: s_lshr_b32 s61, s20, 16 +; GFX9-NEXT: s_lshr_b32 s62, s19, 16 +; GFX9-NEXT: s_lshr_b32 s63, s18, 16 +; GFX9-NEXT: s_lshr_b32 s72, s17, 16 +; GFX9-NEXT: s_lshr_b32 s73, s16, 16 +; GFX9-NEXT: s_lshr_b32 s74, s15, 16 +; GFX9-NEXT: s_lshr_b32 s75, s14, 16 +; GFX9-NEXT: s_lshr_b32 s76, s13, 16 +; GFX9-NEXT: s_lshr_b32 s77, s12, 16 +; GFX9-NEXT: s_lshr_b32 s78, s11, 16 +; GFX9-NEXT: s_lshr_b32 s79, s10, 16 +; GFX9-NEXT: s_lshr_b32 s88, s9, 16 +; GFX9-NEXT: s_lshr_b32 s89, s8, 16 +; GFX9-NEXT: s_lshr_b32 s90, s7, 16 +; GFX9-NEXT: s_lshr_b32 s91, s6, 16 ; GFX9-NEXT: s_cbranch_execnz .LBB41_3 ; GFX9-NEXT: .LBB41_2: ; %cmp.true ; GFX9-NEXT: s_add_u32 s40, s40, 3 ; GFX9-NEXT: s_addc_u32 s41, s41, 0 -; GFX9-NEXT: s_add_u32 s14, s14, 3 -; GFX9-NEXT: s_addc_u32 s15, s15, 0 -; GFX9-NEXT: s_add_u32 s12, s12, 3 -; GFX9-NEXT: s_addc_u32 s13, s13, 0 -; GFX9-NEXT: s_add_u32 s10, s10, 3 -; GFX9-NEXT: s_addc_u32 s11, s11, 0 -; GFX9-NEXT: s_add_u32 s8, s8, 3 -; GFX9-NEXT: s_addc_u32 s9, s9, 0 -; GFX9-NEXT: s_add_u32 s6, s6, 3 -; GFX9-NEXT: s_addc_u32 s7, s7, 0 ; GFX9-NEXT: s_add_u32 s28, s28, 3 ; GFX9-NEXT: s_addc_u32 s29, s29, 0 ; GFX9-NEXT: s_add_u32 s26, s26, 3 @@ -24726,83 +24353,93 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; GFX9-NEXT: s_addc_u32 s19, s19, 0 ; GFX9-NEXT: s_add_u32 s16, s16, 3 ; GFX9-NEXT: s_addc_u32 s17, s17, 0 +; GFX9-NEXT: s_add_u32 s14, s14, 3 +; GFX9-NEXT: s_addc_u32 s15, s15, 0 +; GFX9-NEXT: s_add_u32 s12, s12, 3 +; GFX9-NEXT: s_addc_u32 s13, s13, 0 +; GFX9-NEXT: s_add_u32 s10, s10, 3 +; GFX9-NEXT: s_addc_u32 s11, s11, 0 +; GFX9-NEXT: s_add_u32 s8, s8, 3 +; GFX9-NEXT: s_addc_u32 s9, s9, 0 +; GFX9-NEXT: s_add_u32 s6, s6, 3 +; GFX9-NEXT: s_addc_u32 s7, s7, 0 ; GFX9-NEXT: s_lshr_b32 s42, s41, 16 ; GFX9-NEXT: s_lshr_b32 s43, s40, 16 -; GFX9-NEXT: s_lshr_b32 s44, s15, 16 -; GFX9-NEXT: s_lshr_b32 s45, s14, 16 -; GFX9-NEXT: s_lshr_b32 s46, s13, 16 -; GFX9-NEXT: s_lshr_b32 s47, s12, 16 -; GFX9-NEXT: s_lshr_b32 s56, s11, 16 -; GFX9-NEXT: s_lshr_b32 s57, s10, 16 -; GFX9-NEXT: s_lshr_b32 s58, s9, 16 -; GFX9-NEXT: s_lshr_b32 s59, s8, 16 -; GFX9-NEXT: s_lshr_b32 s60, s7, 16 -; GFX9-NEXT: s_lshr_b32 s61, s6, 16 -; GFX9-NEXT: s_lshr_b32 s62, s29, 16 -; GFX9-NEXT: s_lshr_b32 s63, s28, 16 -; GFX9-NEXT: s_lshr_b32 s72, s27, 16 -; GFX9-NEXT: s_lshr_b32 s73, s26, 16 -; GFX9-NEXT: s_lshr_b32 s74, s25, 16 -; GFX9-NEXT: s_lshr_b32 s75, s24, 16 -; GFX9-NEXT: s_lshr_b32 s76, s23, 16 -; GFX9-NEXT: s_lshr_b32 s77, s22, 16 -; GFX9-NEXT: s_lshr_b32 s78, s21, 16 -; GFX9-NEXT: s_lshr_b32 s79, s20, 16 -; GFX9-NEXT: s_lshr_b32 s88, s19, 16 -; GFX9-NEXT: s_lshr_b32 s89, s18, 16 -; GFX9-NEXT: s_lshr_b32 s90, s17, 16 -; GFX9-NEXT: s_lshr_b32 s91, s16, 16 +; GFX9-NEXT: s_lshr_b32 s44, s29, 16 +; GFX9-NEXT: s_lshr_b32 s45, s28, 16 +; GFX9-NEXT: s_lshr_b32 s46, s27, 16 +; GFX9-NEXT: s_lshr_b32 s47, s26, 16 +; GFX9-NEXT: s_lshr_b32 s56, s25, 16 +; GFX9-NEXT: s_lshr_b32 s57, s24, 16 +; GFX9-NEXT: s_lshr_b32 s58, s23, 16 +; GFX9-NEXT: s_lshr_b32 s59, s22, 16 +; GFX9-NEXT: s_lshr_b32 s60, s21, 16 +; GFX9-NEXT: s_lshr_b32 s61, s20, 16 +; GFX9-NEXT: s_lshr_b32 s62, s19, 16 +; GFX9-NEXT: s_lshr_b32 s63, s18, 16 +; GFX9-NEXT: s_lshr_b32 s72, s17, 16 +; GFX9-NEXT: s_lshr_b32 s73, s16, 16 +; GFX9-NEXT: s_lshr_b32 s74, s15, 16 +; GFX9-NEXT: s_lshr_b32 s75, s14, 16 +; GFX9-NEXT: s_lshr_b32 s76, s13, 16 +; GFX9-NEXT: s_lshr_b32 s77, s12, 16 +; GFX9-NEXT: s_lshr_b32 s78, s11, 16 +; GFX9-NEXT: s_lshr_b32 s79, s10, 16 +; GFX9-NEXT: s_lshr_b32 s88, s9, 16 +; GFX9-NEXT: s_lshr_b32 s89, s8, 16 +; GFX9-NEXT: s_lshr_b32 s90, s7, 16 +; GFX9-NEXT: s_lshr_b32 s91, s6, 16 ; GFX9-NEXT: .LBB41_3: ; %end -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s16, s91 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s17, s90 -; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s89 -; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s88 -; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s79 -; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s78 -; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s77 -; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s76 -; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s75 -; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s74 -; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s73 -; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s72 -; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s63 -; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s62 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s61 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s60 -; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s59 -; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s58 -; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s57 -; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s56 -; GFX9-NEXT: s_pack_ll_b32_b16 s12, s12, s47 -; GFX9-NEXT: s_pack_ll_b32_b16 s13, s13, s46 -; GFX9-NEXT: s_pack_ll_b32_b16 s14, s14, s45 -; GFX9-NEXT: s_pack_ll_b32_b16 s15, s15, s44 +; GFX9-NEXT: s_pack_ll_b32_b16 s4, s6, s91 +; GFX9-NEXT: s_pack_ll_b32_b16 s5, s7, s90 +; GFX9-NEXT: s_pack_ll_b32_b16 s6, s8, s89 +; GFX9-NEXT: s_pack_ll_b32_b16 s7, s9, s88 +; GFX9-NEXT: s_pack_ll_b32_b16 s8, s10, s79 +; GFX9-NEXT: s_pack_ll_b32_b16 s9, s11, s78 +; GFX9-NEXT: s_pack_ll_b32_b16 s10, s12, s77 +; GFX9-NEXT: s_pack_ll_b32_b16 s11, s13, s76 +; GFX9-NEXT: s_pack_ll_b32_b16 s12, s14, s75 +; GFX9-NEXT: s_pack_ll_b32_b16 s13, s15, s74 +; GFX9-NEXT: s_pack_ll_b32_b16 s14, s16, s73 +; GFX9-NEXT: s_pack_ll_b32_b16 s15, s17, s72 +; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s63 +; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s62 +; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s61 +; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s60 +; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s59 +; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s58 +; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s57 +; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s56 +; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s47 +; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s46 +; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s45 +; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s44 ; GFX9-NEXT: s_pack_ll_b32_b16 s28, s40, s43 ; GFX9-NEXT: s_pack_ll_b32_b16 s29, s41, s42 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 -; GFX9-NEXT: v_mov_b32_e32 v2, s16 -; GFX9-NEXT: v_mov_b32_e32 v3, s17 -; GFX9-NEXT: v_mov_b32_e32 v4, s18 -; GFX9-NEXT: v_mov_b32_e32 v5, s19 -; GFX9-NEXT: v_mov_b32_e32 v6, s20 -; GFX9-NEXT: v_mov_b32_e32 v7, s21 -; GFX9-NEXT: v_mov_b32_e32 v8, s22 -; GFX9-NEXT: v_mov_b32_e32 v9, s23 -; GFX9-NEXT: v_mov_b32_e32 v10, s24 -; GFX9-NEXT: v_mov_b32_e32 v11, s25 -; GFX9-NEXT: v_mov_b32_e32 v12, s26 -; GFX9-NEXT: v_mov_b32_e32 v13, s27 -; GFX9-NEXT: v_mov_b32_e32 v14, s6 -; GFX9-NEXT: v_mov_b32_e32 v15, s7 -; GFX9-NEXT: v_mov_b32_e32 v16, s8 -; GFX9-NEXT: v_mov_b32_e32 v17, s9 -; GFX9-NEXT: v_mov_b32_e32 v18, s10 -; GFX9-NEXT: v_mov_b32_e32 v19, s11 -; GFX9-NEXT: v_mov_b32_e32 v20, s12 -; GFX9-NEXT: v_mov_b32_e32 v21, s13 -; GFX9-NEXT: v_mov_b32_e32 v22, s14 -; GFX9-NEXT: v_mov_b32_e32 v23, s15 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: v_mov_b32_e32 v4, s8 +; GFX9-NEXT: v_mov_b32_e32 v5, s9 +; GFX9-NEXT: v_mov_b32_e32 v6, s10 +; GFX9-NEXT: v_mov_b32_e32 v7, s11 +; GFX9-NEXT: v_mov_b32_e32 v8, s12 +; GFX9-NEXT: v_mov_b32_e32 v9, s13 +; GFX9-NEXT: v_mov_b32_e32 v10, s14 +; GFX9-NEXT: v_mov_b32_e32 v11, s15 +; GFX9-NEXT: v_mov_b32_e32 v12, s16 +; GFX9-NEXT: v_mov_b32_e32 v13, s17 +; GFX9-NEXT: v_mov_b32_e32 v14, s18 +; GFX9-NEXT: v_mov_b32_e32 v15, s19 +; GFX9-NEXT: v_mov_b32_e32 v16, s20 +; GFX9-NEXT: v_mov_b32_e32 v17, s21 +; GFX9-NEXT: v_mov_b32_e32 v18, s22 +; GFX9-NEXT: v_mov_b32_e32 v19, s23 +; GFX9-NEXT: v_mov_b32_e32 v20, s24 +; GFX9-NEXT: v_mov_b32_e32 v21, s25 +; GFX9-NEXT: v_mov_b32_e32 v22, s26 +; GFX9-NEXT: v_mov_b32_e32 v23, s27 ; GFX9-NEXT: v_mov_b32_e32 v24, s28 ; GFX9-NEXT: v_mov_b32_e32 v25, s29 ; GFX9-NEXT: s_setpc_b64 s[30:31] @@ -24838,41 +24475,68 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; GFX11-LABEL: bitcast_v13i64_to_v52i16_scalar: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v9, s0 :: v_dual_mov_b32 v10, s1 +; GFX11-NEXT: v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v12, s3 +; GFX11-NEXT: v_dual_mov_b32 v13, s16 :: v_dual_mov_b32 v14, s17 +; GFX11-NEXT: v_dual_mov_b32 v15, s18 :: v_dual_mov_b32 v16, s19 +; GFX11-NEXT: v_dual_mov_b32 v17, s20 :: v_dual_mov_b32 v18, s21 +; GFX11-NEXT: v_dual_mov_b32 v19, s22 :: v_dual_mov_b32 v20, s23 +; GFX11-NEXT: v_dual_mov_b32 v21, s24 :: v_dual_mov_b32 v22, s25 +; GFX11-NEXT: v_dual_mov_b32 v23, s26 :: v_dual_mov_b32 v24, s27 +; GFX11-NEXT: v_dual_mov_b32 v25, s28 :: v_dual_mov_b32 v26, s29 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 -; GFX11-NEXT: v_readfirstlane_b32 s4, v0 -; GFX11-NEXT: v_readfirstlane_b32 s5, v1 -; GFX11-NEXT: v_readfirstlane_b32 s6, v2 -; GFX11-NEXT: v_readfirstlane_b32 s7, v3 -; GFX11-NEXT: v_readfirstlane_b32 s8, v4 -; GFX11-NEXT: v_readfirstlane_b32 s9, v5 -; GFX11-NEXT: v_readfirstlane_b32 s11, v6 -; GFX11-NEXT: v_readfirstlane_b32 s10, v7 +; GFX11-NEXT: v_readfirstlane_b32 s0, v9 +; GFX11-NEXT: v_readfirstlane_b32 s1, v10 +; GFX11-NEXT: v_readfirstlane_b32 s2, v11 +; GFX11-NEXT: v_readfirstlane_b32 s3, v12 +; GFX11-NEXT: v_readfirstlane_b32 s4, v13 +; GFX11-NEXT: v_readfirstlane_b32 s5, v14 +; GFX11-NEXT: v_readfirstlane_b32 s6, v15 +; GFX11-NEXT: v_readfirstlane_b32 s7, v16 +; GFX11-NEXT: v_readfirstlane_b32 s8, v17 +; GFX11-NEXT: v_readfirstlane_b32 s9, v18 +; GFX11-NEXT: v_readfirstlane_b32 s10, v19 +; GFX11-NEXT: v_readfirstlane_b32 s11, v20 +; GFX11-NEXT: v_readfirstlane_b32 s12, v21 +; GFX11-NEXT: v_readfirstlane_b32 s13, v22 +; GFX11-NEXT: v_readfirstlane_b32 s14, v23 +; GFX11-NEXT: v_readfirstlane_b32 s15, v24 +; GFX11-NEXT: v_readfirstlane_b32 s16, v25 +; GFX11-NEXT: v_readfirstlane_b32 s17, v26 +; GFX11-NEXT: v_readfirstlane_b32 s18, v0 +; GFX11-NEXT: v_readfirstlane_b32 s19, v1 +; GFX11-NEXT: v_readfirstlane_b32 s20, v2 +; GFX11-NEXT: v_readfirstlane_b32 s21, v3 +; GFX11-NEXT: v_readfirstlane_b32 s22, v4 +; GFX11-NEXT: v_readfirstlane_b32 s23, v5 +; GFX11-NEXT: v_readfirstlane_b32 s25, v6 +; GFX11-NEXT: v_readfirstlane_b32 s24, v7 ; GFX11-NEXT: s_mov_b32 s78, 0 -; GFX11-NEXT: s_and_b32 s12, vcc_lo, exec_lo +; GFX11-NEXT: s_and_b32 s26, vcc_lo, exec_lo ; GFX11-NEXT: s_cbranch_scc0 .LBB41_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: s_lshr_b32 s12, s10, 16 -; GFX11-NEXT: s_lshr_b32 s13, s11, 16 -; GFX11-NEXT: s_lshr_b32 s14, s9, 16 -; GFX11-NEXT: s_lshr_b32 s15, s8, 16 -; GFX11-NEXT: s_lshr_b32 s40, s7, 16 -; GFX11-NEXT: s_lshr_b32 s41, s6, 16 -; GFX11-NEXT: s_lshr_b32 s42, s5, 16 -; GFX11-NEXT: s_lshr_b32 s43, s4, 16 -; GFX11-NEXT: s_lshr_b32 s44, s29, 16 -; GFX11-NEXT: s_lshr_b32 s45, s28, 16 -; GFX11-NEXT: s_lshr_b32 s46, s27, 16 -; GFX11-NEXT: s_lshr_b32 s47, s26, 16 -; GFX11-NEXT: s_lshr_b32 s56, s25, 16 -; GFX11-NEXT: s_lshr_b32 s57, s24, 16 -; GFX11-NEXT: s_lshr_b32 s58, s23, 16 -; GFX11-NEXT: s_lshr_b32 s59, s22, 16 -; GFX11-NEXT: s_lshr_b32 s60, s21, 16 -; GFX11-NEXT: s_lshr_b32 s61, s20, 16 -; GFX11-NEXT: s_lshr_b32 s62, s19, 16 -; GFX11-NEXT: s_lshr_b32 s63, s18, 16 -; GFX11-NEXT: s_lshr_b32 s72, s17, 16 -; GFX11-NEXT: s_lshr_b32 s73, s16, 16 +; GFX11-NEXT: s_lshr_b32 s26, s24, 16 +; GFX11-NEXT: s_lshr_b32 s27, s25, 16 +; GFX11-NEXT: s_lshr_b32 s28, s23, 16 +; GFX11-NEXT: s_lshr_b32 s29, s22, 16 +; GFX11-NEXT: s_lshr_b32 s40, s21, 16 +; GFX11-NEXT: s_lshr_b32 s41, s20, 16 +; GFX11-NEXT: s_lshr_b32 s42, s19, 16 +; GFX11-NEXT: s_lshr_b32 s43, s18, 16 +; GFX11-NEXT: s_lshr_b32 s44, s17, 16 +; GFX11-NEXT: s_lshr_b32 s45, s16, 16 +; GFX11-NEXT: s_lshr_b32 s46, s15, 16 +; GFX11-NEXT: s_lshr_b32 s47, s14, 16 +; GFX11-NEXT: s_lshr_b32 s56, s13, 16 +; GFX11-NEXT: s_lshr_b32 s57, s12, 16 +; GFX11-NEXT: s_lshr_b32 s58, s11, 16 +; GFX11-NEXT: s_lshr_b32 s59, s10, 16 +; GFX11-NEXT: s_lshr_b32 s60, s9, 16 +; GFX11-NEXT: s_lshr_b32 s61, s8, 16 +; GFX11-NEXT: s_lshr_b32 s62, s7, 16 +; GFX11-NEXT: s_lshr_b32 s63, s6, 16 +; GFX11-NEXT: s_lshr_b32 s72, s5, 16 +; GFX11-NEXT: s_lshr_b32 s73, s4, 16 ; GFX11-NEXT: s_lshr_b32 s74, s3, 16 ; GFX11-NEXT: s_lshr_b32 s75, s2, 16 ; GFX11-NEXT: s_lshr_b32 s76, s1, 16 @@ -24880,20 +24544,8 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s78 ; GFX11-NEXT: s_cbranch_vccnz .LBB41_3 ; GFX11-NEXT: .LBB41_2: ; %cmp.true -; GFX11-NEXT: s_add_u32 s11, s11, 3 -; GFX11-NEXT: s_addc_u32 s10, s10, 0 -; GFX11-NEXT: s_add_u32 s8, s8, 3 -; GFX11-NEXT: s_addc_u32 s9, s9, 0 -; GFX11-NEXT: s_add_u32 s6, s6, 3 -; GFX11-NEXT: s_addc_u32 s7, s7, 0 -; GFX11-NEXT: s_add_u32 s4, s4, 3 -; GFX11-NEXT: s_addc_u32 s5, s5, 0 -; GFX11-NEXT: s_add_u32 s28, s28, 3 -; GFX11-NEXT: s_addc_u32 s29, s29, 0 -; GFX11-NEXT: s_add_u32 s26, s26, 3 -; GFX11-NEXT: s_addc_u32 s27, s27, 0 -; GFX11-NEXT: s_add_u32 s24, s24, 3 -; GFX11-NEXT: s_addc_u32 s25, s25, 0 +; GFX11-NEXT: s_add_u32 s25, s25, 3 +; GFX11-NEXT: s_addc_u32 s24, s24, 0 ; GFX11-NEXT: s_add_u32 s22, s22, 3 ; GFX11-NEXT: s_addc_u32 s23, s23, 0 ; GFX11-NEXT: s_add_u32 s20, s20, 3 @@ -24902,32 +24554,44 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; GFX11-NEXT: s_addc_u32 s19, s19, 0 ; GFX11-NEXT: s_add_u32 s16, s16, 3 ; GFX11-NEXT: s_addc_u32 s17, s17, 0 +; GFX11-NEXT: s_add_u32 s14, s14, 3 +; GFX11-NEXT: s_addc_u32 s15, s15, 0 +; GFX11-NEXT: s_add_u32 s12, s12, 3 +; GFX11-NEXT: s_addc_u32 s13, s13, 0 +; GFX11-NEXT: s_add_u32 s10, s10, 3 +; GFX11-NEXT: s_addc_u32 s11, s11, 0 +; GFX11-NEXT: s_add_u32 s8, s8, 3 +; GFX11-NEXT: s_addc_u32 s9, s9, 0 +; GFX11-NEXT: s_add_u32 s6, s6, 3 +; GFX11-NEXT: s_addc_u32 s7, s7, 0 +; GFX11-NEXT: s_add_u32 s4, s4, 3 +; GFX11-NEXT: s_addc_u32 s5, s5, 0 ; GFX11-NEXT: s_add_u32 s2, s2, 3 ; GFX11-NEXT: s_addc_u32 s3, s3, 0 ; GFX11-NEXT: s_add_u32 s0, s0, 3 ; GFX11-NEXT: s_addc_u32 s1, s1, 0 -; GFX11-NEXT: s_lshr_b32 s12, s10, 16 -; GFX11-NEXT: s_lshr_b32 s13, s11, 16 -; GFX11-NEXT: s_lshr_b32 s14, s9, 16 -; GFX11-NEXT: s_lshr_b32 s15, s8, 16 -; GFX11-NEXT: s_lshr_b32 s40, s7, 16 -; GFX11-NEXT: s_lshr_b32 s41, s6, 16 -; GFX11-NEXT: s_lshr_b32 s42, s5, 16 -; GFX11-NEXT: s_lshr_b32 s43, s4, 16 -; GFX11-NEXT: s_lshr_b32 s44, s29, 16 -; GFX11-NEXT: s_lshr_b32 s45, s28, 16 -; GFX11-NEXT: s_lshr_b32 s46, s27, 16 -; GFX11-NEXT: s_lshr_b32 s47, s26, 16 -; GFX11-NEXT: s_lshr_b32 s56, s25, 16 -; GFX11-NEXT: s_lshr_b32 s57, s24, 16 -; GFX11-NEXT: s_lshr_b32 s58, s23, 16 -; GFX11-NEXT: s_lshr_b32 s59, s22, 16 -; GFX11-NEXT: s_lshr_b32 s60, s21, 16 -; GFX11-NEXT: s_lshr_b32 s61, s20, 16 -; GFX11-NEXT: s_lshr_b32 s62, s19, 16 -; GFX11-NEXT: s_lshr_b32 s63, s18, 16 -; GFX11-NEXT: s_lshr_b32 s72, s17, 16 -; GFX11-NEXT: s_lshr_b32 s73, s16, 16 +; GFX11-NEXT: s_lshr_b32 s26, s24, 16 +; GFX11-NEXT: s_lshr_b32 s27, s25, 16 +; GFX11-NEXT: s_lshr_b32 s28, s23, 16 +; GFX11-NEXT: s_lshr_b32 s29, s22, 16 +; GFX11-NEXT: s_lshr_b32 s40, s21, 16 +; GFX11-NEXT: s_lshr_b32 s41, s20, 16 +; GFX11-NEXT: s_lshr_b32 s42, s19, 16 +; GFX11-NEXT: s_lshr_b32 s43, s18, 16 +; GFX11-NEXT: s_lshr_b32 s44, s17, 16 +; GFX11-NEXT: s_lshr_b32 s45, s16, 16 +; GFX11-NEXT: s_lshr_b32 s46, s15, 16 +; GFX11-NEXT: s_lshr_b32 s47, s14, 16 +; GFX11-NEXT: s_lshr_b32 s56, s13, 16 +; GFX11-NEXT: s_lshr_b32 s57, s12, 16 +; GFX11-NEXT: s_lshr_b32 s58, s11, 16 +; GFX11-NEXT: s_lshr_b32 s59, s10, 16 +; GFX11-NEXT: s_lshr_b32 s60, s9, 16 +; GFX11-NEXT: s_lshr_b32 s61, s8, 16 +; GFX11-NEXT: s_lshr_b32 s62, s7, 16 +; GFX11-NEXT: s_lshr_b32 s63, s6, 16 +; GFX11-NEXT: s_lshr_b32 s72, s5, 16 +; GFX11-NEXT: s_lshr_b32 s73, s4, 16 ; GFX11-NEXT: s_lshr_b32 s74, s3, 16 ; GFX11-NEXT: s_lshr_b32 s75, s2, 16 ; GFX11-NEXT: s_lshr_b32 s76, s1, 16 @@ -24938,41 +24602,41 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s76 ; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s75 ; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s74 -; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s73 -; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s72 -; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s63 -; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s62 -; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s61 -; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s60 -; GFX11-NEXT: s_pack_ll_b32_b16 s22, s22, s59 -; GFX11-NEXT: s_pack_ll_b32_b16 s23, s23, s58 -; GFX11-NEXT: s_pack_ll_b32_b16 s24, s24, s57 -; GFX11-NEXT: s_pack_ll_b32_b16 s25, s25, s56 -; GFX11-NEXT: s_pack_ll_b32_b16 s26, s26, s47 -; GFX11-NEXT: s_pack_ll_b32_b16 s27, s27, s46 -; GFX11-NEXT: s_pack_ll_b32_b16 s28, s28, s45 -; GFX11-NEXT: s_pack_ll_b32_b16 s29, s29, s44 -; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s43 -; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s42 -; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s41 -; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s40 -; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s15 -; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s14 -; GFX11-NEXT: s_pack_ll_b32_b16 s11, s11, s13 -; GFX11-NEXT: s_pack_ll_b32_b16 s10, s10, s12 +; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s73 +; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s72 +; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s63 +; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s62 +; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s61 +; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s60 +; GFX11-NEXT: s_pack_ll_b32_b16 s10, s10, s59 +; GFX11-NEXT: s_pack_ll_b32_b16 s11, s11, s58 +; GFX11-NEXT: s_pack_ll_b32_b16 s12, s12, s57 +; GFX11-NEXT: s_pack_ll_b32_b16 s13, s13, s56 +; GFX11-NEXT: s_pack_ll_b32_b16 s14, s14, s47 +; GFX11-NEXT: s_pack_ll_b32_b16 s15, s15, s46 +; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s45 +; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s44 +; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s43 +; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s42 +; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s41 +; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s40 +; GFX11-NEXT: s_pack_ll_b32_b16 s22, s22, s29 +; GFX11-NEXT: s_pack_ll_b32_b16 s23, s23, s28 +; GFX11-NEXT: s_pack_ll_b32_b16 s25, s25, s27 +; GFX11-NEXT: s_pack_ll_b32_b16 s24, s24, s26 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 -; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 -; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 -; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 -; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 -; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 -; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 -; GFX11-NEXT: v_dual_mov_b32 v18, s4 :: v_dual_mov_b32 v19, s5 -; GFX11-NEXT: v_dual_mov_b32 v20, s6 :: v_dual_mov_b32 v21, s7 -; GFX11-NEXT: v_dual_mov_b32 v22, s8 :: v_dual_mov_b32 v23, s9 -; GFX11-NEXT: v_dual_mov_b32 v24, s11 :: v_dual_mov_b32 v25, s10 +; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19 +; GFX11-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v21, s21 +; GFX11-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v23, s23 +; GFX11-NEXT: v_dual_mov_b32 v24, s25 :: v_dual_mov_b32 v25, s24 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: .LBB41_4: ; GFX11-NEXT: ; implicit-def: $sgpr77 @@ -24997,10 +24661,10 @@ define inreg <52 x i16> @bitcast_v13i64_to_v52i16_scalar(<13 x i64> inreg %a, i3 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr41 ; GFX11-NEXT: ; implicit-def: $sgpr40 -; GFX11-NEXT: ; implicit-def: $sgpr15 -; GFX11-NEXT: ; implicit-def: $sgpr14 -; GFX11-NEXT: ; implicit-def: $sgpr13 -; GFX11-NEXT: ; implicit-def: $sgpr12 +; GFX11-NEXT: ; implicit-def: $sgpr29 +; GFX11-NEXT: ; implicit-def: $sgpr28 +; GFX11-NEXT: ; implicit-def: $sgpr27 +; GFX11-NEXT: ; implicit-def: $sgpr26 ; GFX11-NEXT: s_branch .LBB41_2 %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -25023,6 +24687,19 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) { ; SI-LABEL: bitcast_v52i16_to_v13i64: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v50, v10 +; SI-NEXT: v_mov_b32_e32 v51, v8 +; SI-NEXT: v_mov_b32_e32 v52, v6 +; SI-NEXT: v_mov_b32_e32 v53, v4 +; SI-NEXT: v_mov_b32_e32 v54, v2 +; SI-NEXT: v_mov_b32_e32 v55, v0 +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:48 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:40 +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24 +; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:16 +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:12 +; SI-NEXT: v_mov_b32_e32 v49, v12 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill @@ -25048,19 +24725,6 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v50, v10 -; SI-NEXT: v_mov_b32_e32 v51, v8 -; SI-NEXT: v_mov_b32_e32 v52, v6 -; SI-NEXT: v_mov_b32_e32 v53, v4 -; SI-NEXT: v_mov_b32_e32 v54, v2 -; SI-NEXT: v_mov_b32_e32 v55, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:48 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:40 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32 -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24 -; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:16 -; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:12 -; SI-NEXT: v_mov_b32_e32 v49, v12 ; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v1 ; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v3 ; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v5 @@ -25076,17 +24740,12 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) { ; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v25 ; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v27 ; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v29 -; SI-NEXT: s_waitcnt vmcnt(5) +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v0 -; SI-NEXT: s_waitcnt vmcnt(4) ; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v2 -; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v4 -; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v6 -; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v8 -; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:8 @@ -25111,9 +24770,10 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) { ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72 ; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:68 -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v18 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 @@ -25125,10 +24785,9 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) { ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:56 ; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:52 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v22 ; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v22 +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:44 @@ -25448,7 +25107,7 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) { ; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21 ; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22 ; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23 -; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24 +; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v24 ; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25 ; SI-NEXT: .LBB42_4: ; %end ; SI-NEXT: s_or_b64 exec, exec, s[4:5] @@ -25714,7 +25373,6 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v57, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v25 -; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v24 @@ -25781,6 +25439,7 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v56 ; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v57 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 +; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -25913,6 +25572,9 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] ; GFX9-NEXT: s_cbranch_execz .LBB42_4 ; GFX9-NEXT: ; %bb.3: ; %cmp.true +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload @@ -25927,9 +25589,6 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v34, v57, s6 ; GFX9-NEXT: v_perm_b32 v1, v62, v56, s6 ; GFX9-NEXT: v_perm_b32 v2, v33, v47, s6 @@ -25948,6 +25607,10 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] +; GFX9-NEXT: s_waitcnt vmcnt(14) +; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; GFX9-NEXT: s_waitcnt vmcnt(15) ; GFX9-NEXT: v_perm_b32 v9, v9, v40, s6 ; GFX9-NEXT: s_waitcnt vmcnt(14) @@ -25976,10 +25639,6 @@ define <13 x i64> @bitcast_v52i16_to_v13i64(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: v_perm_b32 v21, v21, v36, s6 ; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: v_perm_b32 v22, v22, v35, s6 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] @@ -26969,294 +26628,109 @@ define inreg <13 x i64> @bitcast_v52i16_to_v13i64_scalar(<52 x i16> inreg %a, i3 ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v191, v1 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v185, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB43_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB43_3 ; GFX11-TRUE16-NEXT: .LBB43_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s40, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s41, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v185, v185, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v191, v191, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v190, v190, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v189, v189, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v188, v188, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v187, v187, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v186, v186, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, s6, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, s7, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, s8, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s9, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, s10, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, s11, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, s12, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, s13, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s14, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, s15, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, s16, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s0, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s1, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s2, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, s3, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, s4, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v35, s5, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v44, s6, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v54, s7, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v65, s8, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v77, s9, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v90, s10, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v104, s11, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v119, s12, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v135, s13, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v152, s14, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v170, s15, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: .LBB43_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v170 :: v_dual_mov_b32 v18, v185 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v191 :: v_dual_mov_b32 v20, v190 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v189 :: v_dual_mov_b32 v22, v188 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v187 :: v_dual_mov_b32 v24, v186 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v191, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v190, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v189, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v188, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v187, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:316 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v14, v119 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB43_4: -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v53, v25 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v25, v53 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB43_2 ; ; GFX11-FAKE16-LABEL: bitcast_v52i16_to_v13i64_scalar: @@ -28529,9 +28003,37 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i ; SI-LABEL: bitcast_v13i64_to_v52f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v14, s16 +; SI-NEXT: v_mov_b32_e32 v15, s17 +; SI-NEXT: v_mov_b32_e32 v16, s18 +; SI-NEXT: v_mov_b32_e32 v17, s19 +; SI-NEXT: v_mov_b32_e32 v18, s20 +; SI-NEXT: v_mov_b32_e32 v19, s21 +; SI-NEXT: v_readfirstlane_b32 s40, v14 +; SI-NEXT: v_mov_b32_e32 v14, s22 +; SI-NEXT: v_readfirstlane_b32 s41, v15 +; SI-NEXT: v_mov_b32_e32 v15, s23 +; SI-NEXT: v_readfirstlane_b32 s22, v16 +; SI-NEXT: v_mov_b32_e32 v16, s24 +; SI-NEXT: v_readfirstlane_b32 s42, v17 +; SI-NEXT: v_mov_b32_e32 v17, s25 +; SI-NEXT: v_readfirstlane_b32 s23, v18 +; SI-NEXT: v_mov_b32_e32 v18, s26 +; SI-NEXT: v_readfirstlane_b32 s43, v19 +; SI-NEXT: v_mov_b32_e32 v19, s27 +; SI-NEXT: v_readfirstlane_b32 s24, v14 +; SI-NEXT: v_mov_b32_e32 v14, s28 +; SI-NEXT: v_readfirstlane_b32 s27, v15 +; SI-NEXT: v_mov_b32_e32 v15, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 -; SI-NEXT: v_readfirstlane_b32 s40, v1 -; SI-NEXT: v_readfirstlane_b32 s41, v2 +; SI-NEXT: v_readfirstlane_b32 s25, v16 +; SI-NEXT: v_readfirstlane_b32 s26, v17 +; SI-NEXT: v_readfirstlane_b32 s20, v18 +; SI-NEXT: v_readfirstlane_b32 s21, v19 +; SI-NEXT: v_readfirstlane_b32 s18, v14 +; SI-NEXT: v_readfirstlane_b32 s19, v15 +; SI-NEXT: v_readfirstlane_b32 s16, v1 +; SI-NEXT: v_readfirstlane_b32 s17, v2 ; SI-NEXT: v_readfirstlane_b32 s14, v3 ; SI-NEXT: v_readfirstlane_b32 s15, v4 ; SI-NEXT: v_readfirstlane_b32 s12, v5 @@ -28570,39 +28072,39 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v16, s4 ; SI-NEXT: s_lshr_b32 s4, s14, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v18, s4 -; SI-NEXT: s_lshr_b32 s4, s41, 16 +; SI-NEXT: s_lshr_b32 s4, s17, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v20, s4 -; SI-NEXT: s_lshr_b32 s4, s40, 16 +; SI-NEXT: s_lshr_b32 s4, s16, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v22, s4 -; SI-NEXT: s_lshr_b32 s4, s29, 16 +; SI-NEXT: s_lshr_b32 s4, s19, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v24, s4 -; SI-NEXT: s_lshr_b32 s4, s28, 16 +; SI-NEXT: s_lshr_b32 s4, s18, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v26, s4 -; SI-NEXT: s_lshr_b32 s4, s27, 16 +; SI-NEXT: s_lshr_b32 s4, s21, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v28, s4 -; SI-NEXT: s_lshr_b32 s4, s26, 16 +; SI-NEXT: s_lshr_b32 s4, s20, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v31, s4 -; SI-NEXT: s_lshr_b32 s4, s25, 16 +; SI-NEXT: s_lshr_b32 s4, s26, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v33, s4 -; SI-NEXT: s_lshr_b32 s4, s24, 16 +; SI-NEXT: s_lshr_b32 s4, s25, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v35, s4 -; SI-NEXT: s_lshr_b32 s4, s23, 16 +; SI-NEXT: s_lshr_b32 s4, s27, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v37, s4 -; SI-NEXT: s_lshr_b32 s4, s22, 16 +; SI-NEXT: s_lshr_b32 s4, s24, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v39, s4 -; SI-NEXT: s_lshr_b32 s4, s21, 16 +; SI-NEXT: s_lshr_b32 s4, s43, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v49, s4 -; SI-NEXT: s_lshr_b32 s4, s20, 16 +; SI-NEXT: s_lshr_b32 s4, s23, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v51, s4 -; SI-NEXT: s_lshr_b32 s4, s19, 16 +; SI-NEXT: s_lshr_b32 s4, s42, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v54, s4 -; SI-NEXT: s_lshr_b32 s4, s18, 16 +; SI-NEXT: s_lshr_b32 s4, s22, 16 ; SI-NEXT: s_waitcnt expcnt(4) ; SI-NEXT: v_cvt_f32_f16_e32 v40, s4 -; SI-NEXT: s_lshr_b32 s4, s17, 16 +; SI-NEXT: s_lshr_b32 s4, s41, 16 ; SI-NEXT: s_waitcnt expcnt(2) ; SI-NEXT: v_cvt_f32_f16_e32 v42, s4 -; SI-NEXT: s_lshr_b32 s4, s16, 16 +; SI-NEXT: s_lshr_b32 s4, s40, 16 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f32_f16_e32 v44, s4 ; SI-NEXT: v_cvt_f32_f16_e32 v4, s9 @@ -28615,56 +28117,56 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v17, s12 ; SI-NEXT: v_cvt_f32_f16_e32 v19, s15 ; SI-NEXT: v_cvt_f32_f16_e32 v21, s14 -; SI-NEXT: v_cvt_f32_f16_e32 v23, s41 -; SI-NEXT: v_cvt_f32_f16_e32 v25, s40 -; SI-NEXT: v_cvt_f32_f16_e32 v27, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s28 -; SI-NEXT: v_cvt_f32_f16_e32 v30, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v32, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v34, s25 -; SI-NEXT: v_cvt_f32_f16_e32 v36, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v38, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v48, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v50, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v52, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v53, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v55, s18 -; SI-NEXT: v_cvt_f32_f16_e32 v41, s17 -; SI-NEXT: v_cvt_f32_f16_e32 v43, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v23, s17 +; SI-NEXT: v_cvt_f32_f16_e32 v25, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v27, s19 +; SI-NEXT: v_cvt_f32_f16_e32 v29, s18 +; SI-NEXT: v_cvt_f32_f16_e32 v30, s21 +; SI-NEXT: v_cvt_f32_f16_e32 v32, s20 +; SI-NEXT: v_cvt_f32_f16_e32 v34, s26 +; SI-NEXT: v_cvt_f32_f16_e32 v36, s25 +; SI-NEXT: v_cvt_f32_f16_e32 v38, s27 +; SI-NEXT: v_cvt_f32_f16_e32 v48, s24 +; SI-NEXT: v_cvt_f32_f16_e32 v50, s43 +; SI-NEXT: v_cvt_f32_f16_e32 v52, s23 +; SI-NEXT: v_cvt_f32_f16_e32 v53, s42 +; SI-NEXT: v_cvt_f32_f16_e32 v55, s22 +; SI-NEXT: v_cvt_f32_f16_e32 v41, s41 +; SI-NEXT: v_cvt_f32_f16_e32 v43, s40 ; SI-NEXT: s_cbranch_execnz .LBB45_3 ; SI-NEXT: .LBB45_2: ; %cmp.true -; SI-NEXT: s_add_u32 s4, s16, 3 -; SI-NEXT: s_addc_u32 s5, s17, 0 -; SI-NEXT: s_lshr_b32 s16, s4, 16 -; SI-NEXT: s_lshr_b32 s17, s5, 16 -; SI-NEXT: s_add_u32 s18, s18, 3 -; SI-NEXT: s_addc_u32 s19, s19, 0 -; SI-NEXT: s_lshr_b32 s42, s18, 16 -; SI-NEXT: s_lshr_b32 s43, s19, 16 -; SI-NEXT: s_add_u32 s20, s20, 3 -; SI-NEXT: s_addc_u32 s21, s21, 0 -; SI-NEXT: s_lshr_b32 s44, s20, 16 -; SI-NEXT: s_lshr_b32 s45, s21, 16 +; SI-NEXT: s_add_u32 s4, s40, 3 +; SI-NEXT: s_addc_u32 s5, s41, 0 +; SI-NEXT: s_lshr_b32 s28, s4, 16 +; SI-NEXT: s_lshr_b32 s29, s5, 16 ; SI-NEXT: s_add_u32 s22, s22, 3 -; SI-NEXT: s_addc_u32 s23, s23, 0 -; SI-NEXT: s_lshr_b32 s46, s22, 16 -; SI-NEXT: s_lshr_b32 s47, s23, 16 +; SI-NEXT: s_addc_u32 s40, s42, 0 +; SI-NEXT: s_lshr_b32 s41, s22, 16 +; SI-NEXT: s_lshr_b32 s42, s40, 16 +; SI-NEXT: s_add_u32 s23, s23, 3 +; SI-NEXT: s_addc_u32 s43, s43, 0 +; SI-NEXT: s_lshr_b32 s44, s23, 16 +; SI-NEXT: s_lshr_b32 s45, s43, 16 ; SI-NEXT: s_add_u32 s24, s24, 3 -; SI-NEXT: s_addc_u32 s25, s25, 0 -; SI-NEXT: s_lshr_b32 s56, s24, 16 -; SI-NEXT: s_lshr_b32 s57, s25, 16 -; SI-NEXT: s_add_u32 s26, s26, 3 ; SI-NEXT: s_addc_u32 s27, s27, 0 -; SI-NEXT: s_lshr_b32 s58, s26, 16 -; SI-NEXT: s_lshr_b32 s59, s27, 16 -; SI-NEXT: s_add_u32 s28, s28, 3 -; SI-NEXT: s_addc_u32 s29, s29, 0 -; SI-NEXT: s_lshr_b32 s60, s28, 16 -; SI-NEXT: s_lshr_b32 s61, s29, 16 -; SI-NEXT: s_add_u32 s40, s40, 3 -; SI-NEXT: s_addc_u32 s41, s41, 0 -; SI-NEXT: s_lshr_b32 s62, s40, 16 -; SI-NEXT: s_lshr_b32 s63, s41, 16 +; SI-NEXT: s_lshr_b32 s46, s24, 16 +; SI-NEXT: s_lshr_b32 s47, s27, 16 +; SI-NEXT: s_add_u32 s25, s25, 3 +; SI-NEXT: s_addc_u32 s26, s26, 0 +; SI-NEXT: s_lshr_b32 s56, s25, 16 +; SI-NEXT: s_lshr_b32 s57, s26, 16 +; SI-NEXT: s_add_u32 s20, s20, 3 +; SI-NEXT: s_addc_u32 s21, s21, 0 +; SI-NEXT: s_lshr_b32 s58, s20, 16 +; SI-NEXT: s_lshr_b32 s59, s21, 16 +; SI-NEXT: s_add_u32 s18, s18, 3 +; SI-NEXT: s_addc_u32 s19, s19, 0 +; SI-NEXT: s_lshr_b32 s60, s18, 16 +; SI-NEXT: s_lshr_b32 s61, s19, 16 +; SI-NEXT: s_add_u32 s16, s16, 3 +; SI-NEXT: s_addc_u32 s17, s17, 0 +; SI-NEXT: s_lshr_b32 s62, s16, 16 +; SI-NEXT: s_lshr_b32 s63, s17, 16 ; SI-NEXT: s_add_u32 s14, s14, 3 ; SI-NEXT: s_addc_u32 s15, s15, 0 ; SI-NEXT: s_lshr_b32 s72, s14, 16 @@ -28695,20 +28197,20 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v17, s12 ; SI-NEXT: v_cvt_f32_f16_e32 v19, s15 ; SI-NEXT: v_cvt_f32_f16_e32 v21, s14 -; SI-NEXT: v_cvt_f32_f16_e32 v23, s41 -; SI-NEXT: v_cvt_f32_f16_e32 v25, s40 -; SI-NEXT: v_cvt_f32_f16_e32 v27, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s28 -; SI-NEXT: v_cvt_f32_f16_e32 v30, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v32, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v34, s25 -; SI-NEXT: v_cvt_f32_f16_e32 v36, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v38, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v48, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v50, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v52, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v53, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v55, s18 +; SI-NEXT: v_cvt_f32_f16_e32 v23, s17 +; SI-NEXT: v_cvt_f32_f16_e32 v25, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v27, s19 +; SI-NEXT: v_cvt_f32_f16_e32 v29, s18 +; SI-NEXT: v_cvt_f32_f16_e32 v30, s21 +; SI-NEXT: v_cvt_f32_f16_e32 v32, s20 +; SI-NEXT: v_cvt_f32_f16_e32 v34, s26 +; SI-NEXT: v_cvt_f32_f16_e32 v36, s25 +; SI-NEXT: v_cvt_f32_f16_e32 v38, s27 +; SI-NEXT: v_cvt_f32_f16_e32 v48, s24 +; SI-NEXT: v_cvt_f32_f16_e32 v50, s43 +; SI-NEXT: v_cvt_f32_f16_e32 v52, s23 +; SI-NEXT: v_cvt_f32_f16_e32 v53, s40 +; SI-NEXT: v_cvt_f32_f16_e32 v55, s22 ; SI-NEXT: s_waitcnt expcnt(3) ; SI-NEXT: v_cvt_f32_f16_e32 v41, s5 ; SI-NEXT: s_waitcnt expcnt(1) @@ -28735,11 +28237,11 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v39, s46 ; SI-NEXT: v_cvt_f32_f16_e32 v49, s45 ; SI-NEXT: v_cvt_f32_f16_e32 v51, s44 -; SI-NEXT: v_cvt_f32_f16_e32 v54, s43 -; SI-NEXT: v_cvt_f32_f16_e32 v40, s42 -; SI-NEXT: v_cvt_f32_f16_e32 v42, s17 +; SI-NEXT: v_cvt_f32_f16_e32 v54, s42 +; SI-NEXT: v_cvt_f32_f16_e32 v40, s41 +; SI-NEXT: v_cvt_f32_f16_e32 v42, s29 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v44, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v44, s28 ; SI-NEXT: .LBB45_3: ; %end ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v44, v44 @@ -28987,9 +28489,37 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i ; VI-LABEL: bitcast_v13i64_to_v52f16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v13, s16 +; VI-NEXT: v_mov_b32_e32 v14, s17 +; VI-NEXT: v_mov_b32_e32 v15, s18 +; VI-NEXT: v_mov_b32_e32 v16, s19 +; VI-NEXT: v_mov_b32_e32 v17, s20 +; VI-NEXT: v_mov_b32_e32 v18, s21 +; VI-NEXT: v_mov_b32_e32 v19, s22 +; VI-NEXT: v_readfirstlane_b32 s44, v13 +; VI-NEXT: v_mov_b32_e32 v13, s23 +; VI-NEXT: v_readfirstlane_b32 s43, v14 +; VI-NEXT: v_mov_b32_e32 v14, s24 +; VI-NEXT: v_readfirstlane_b32 s42, v15 +; VI-NEXT: v_mov_b32_e32 v15, s25 +; VI-NEXT: v_readfirstlane_b32 s41, v16 +; VI-NEXT: v_mov_b32_e32 v16, s26 +; VI-NEXT: v_readfirstlane_b32 s40, v17 +; VI-NEXT: v_mov_b32_e32 v17, s27 +; VI-NEXT: v_readfirstlane_b32 s26, v18 +; VI-NEXT: v_mov_b32_e32 v18, s28 +; VI-NEXT: v_readfirstlane_b32 s25, v19 +; VI-NEXT: v_mov_b32_e32 v19, s29 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 -; VI-NEXT: v_readfirstlane_b32 s41, v0 -; VI-NEXT: v_readfirstlane_b32 s40, v1 +; VI-NEXT: v_readfirstlane_b32 s24, v13 +; VI-NEXT: v_readfirstlane_b32 s23, v14 +; VI-NEXT: v_readfirstlane_b32 s22, v15 +; VI-NEXT: v_readfirstlane_b32 s21, v16 +; VI-NEXT: v_readfirstlane_b32 s20, v17 +; VI-NEXT: v_readfirstlane_b32 s19, v18 +; VI-NEXT: v_readfirstlane_b32 s18, v19 +; VI-NEXT: v_readfirstlane_b32 s17, v0 +; VI-NEXT: v_readfirstlane_b32 s16, v1 ; VI-NEXT: v_readfirstlane_b32 s15, v2 ; VI-NEXT: v_readfirstlane_b32 s14, v3 ; VI-NEXT: v_readfirstlane_b32 s13, v4 @@ -29003,9 +28533,9 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i ; VI-NEXT: v_readfirstlane_b32 s7, v11 ; VI-NEXT: s_cbranch_scc0 .LBB45_4 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_lshr_b32 s42, s7, 16 -; VI-NEXT: s_lshr_b32 s43, s6, 16 -; VI-NEXT: s_lshr_b32 s44, s8, 16 +; VI-NEXT: s_lshr_b32 s27, s7, 16 +; VI-NEXT: s_lshr_b32 s28, s6, 16 +; VI-NEXT: s_lshr_b32 s29, s8, 16 ; VI-NEXT: s_lshr_b32 s45, s9, 16 ; VI-NEXT: s_lshr_b32 s46, s10, 16 ; VI-NEXT: s_lshr_b32 s47, s11, 16 @@ -29013,22 +28543,22 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i ; VI-NEXT: s_lshr_b32 s57, s13, 16 ; VI-NEXT: s_lshr_b32 s58, s14, 16 ; VI-NEXT: s_lshr_b32 s59, s15, 16 -; VI-NEXT: s_lshr_b32 s60, s40, 16 -; VI-NEXT: s_lshr_b32 s61, s41, 16 -; VI-NEXT: s_lshr_b32 s62, s29, 16 -; VI-NEXT: s_lshr_b32 s63, s28, 16 -; VI-NEXT: s_lshr_b32 s72, s27, 16 -; VI-NEXT: s_lshr_b32 s73, s26, 16 -; VI-NEXT: s_lshr_b32 s74, s25, 16 -; VI-NEXT: s_lshr_b32 s75, s24, 16 -; VI-NEXT: s_lshr_b32 s76, s23, 16 -; VI-NEXT: s_lshr_b32 s77, s22, 16 -; VI-NEXT: s_lshr_b32 s78, s21, 16 -; VI-NEXT: s_lshr_b32 s79, s20, 16 -; VI-NEXT: s_lshr_b32 s88, s19, 16 -; VI-NEXT: s_lshr_b32 s89, s18, 16 -; VI-NEXT: s_lshr_b32 s90, s17, 16 -; VI-NEXT: s_lshr_b32 s91, s16, 16 +; VI-NEXT: s_lshr_b32 s60, s16, 16 +; VI-NEXT: s_lshr_b32 s61, s17, 16 +; VI-NEXT: s_lshr_b32 s62, s18, 16 +; VI-NEXT: s_lshr_b32 s63, s19, 16 +; VI-NEXT: s_lshr_b32 s72, s20, 16 +; VI-NEXT: s_lshr_b32 s73, s21, 16 +; VI-NEXT: s_lshr_b32 s74, s22, 16 +; VI-NEXT: s_lshr_b32 s75, s23, 16 +; VI-NEXT: s_lshr_b32 s76, s24, 16 +; VI-NEXT: s_lshr_b32 s77, s25, 16 +; VI-NEXT: s_lshr_b32 s78, s26, 16 +; VI-NEXT: s_lshr_b32 s79, s40, 16 +; VI-NEXT: s_lshr_b32 s88, s41, 16 +; VI-NEXT: s_lshr_b32 s89, s42, 16 +; VI-NEXT: s_lshr_b32 s90, s43, 16 +; VI-NEXT: s_lshr_b32 s91, s44, 16 ; VI-NEXT: s_cbranch_execnz .LBB45_3 ; VI-NEXT: .LBB45_2: ; %cmp.true ; VI-NEXT: s_add_u32 s6, s6, 3 @@ -29041,25 +28571,25 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i ; VI-NEXT: s_addc_u32 s12, s12, 0 ; VI-NEXT: s_add_u32 s15, s15, 3 ; VI-NEXT: s_addc_u32 s14, s14, 0 -; VI-NEXT: s_add_u32 s41, s41, 3 -; VI-NEXT: s_addc_u32 s40, s40, 0 -; VI-NEXT: s_add_u32 s28, s28, 3 -; VI-NEXT: s_addc_u32 s29, s29, 0 -; VI-NEXT: s_add_u32 s26, s26, 3 -; VI-NEXT: s_addc_u32 s27, s27, 0 -; VI-NEXT: s_add_u32 s24, s24, 3 -; VI-NEXT: s_addc_u32 s25, s25, 0 -; VI-NEXT: s_add_u32 s22, s22, 3 -; VI-NEXT: s_addc_u32 s23, s23, 0 -; VI-NEXT: s_add_u32 s20, s20, 3 -; VI-NEXT: s_addc_u32 s21, s21, 0 -; VI-NEXT: s_add_u32 s18, s18, 3 -; VI-NEXT: s_addc_u32 s19, s19, 0 -; VI-NEXT: s_add_u32 s16, s16, 3 -; VI-NEXT: s_addc_u32 s17, s17, 0 -; VI-NEXT: s_lshr_b32 s42, s7, 16 -; VI-NEXT: s_lshr_b32 s43, s6, 16 -; VI-NEXT: s_lshr_b32 s44, s8, 16 +; VI-NEXT: s_add_u32 s17, s17, 3 +; VI-NEXT: s_addc_u32 s16, s16, 0 +; VI-NEXT: s_add_u32 s19, s19, 3 +; VI-NEXT: s_addc_u32 s18, s18, 0 +; VI-NEXT: s_add_u32 s21, s21, 3 +; VI-NEXT: s_addc_u32 s20, s20, 0 +; VI-NEXT: s_add_u32 s23, s23, 3 +; VI-NEXT: s_addc_u32 s22, s22, 0 +; VI-NEXT: s_add_u32 s25, s25, 3 +; VI-NEXT: s_addc_u32 s24, s24, 0 +; VI-NEXT: s_add_u32 s40, s40, 3 +; VI-NEXT: s_addc_u32 s26, s26, 0 +; VI-NEXT: s_add_u32 s42, s42, 3 +; VI-NEXT: s_addc_u32 s41, s41, 0 +; VI-NEXT: s_add_u32 s44, s44, 3 +; VI-NEXT: s_addc_u32 s43, s43, 0 +; VI-NEXT: s_lshr_b32 s27, s7, 16 +; VI-NEXT: s_lshr_b32 s28, s6, 16 +; VI-NEXT: s_lshr_b32 s29, s8, 16 ; VI-NEXT: s_lshr_b32 s45, s9, 16 ; VI-NEXT: s_lshr_b32 s46, s10, 16 ; VI-NEXT: s_lshr_b32 s47, s11, 16 @@ -29067,117 +28597,117 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i ; VI-NEXT: s_lshr_b32 s57, s13, 16 ; VI-NEXT: s_lshr_b32 s58, s14, 16 ; VI-NEXT: s_lshr_b32 s59, s15, 16 -; VI-NEXT: s_lshr_b32 s60, s40, 16 -; VI-NEXT: s_lshr_b32 s61, s41, 16 -; VI-NEXT: s_lshr_b32 s62, s29, 16 -; VI-NEXT: s_lshr_b32 s63, s28, 16 -; VI-NEXT: s_lshr_b32 s72, s27, 16 -; VI-NEXT: s_lshr_b32 s73, s26, 16 -; VI-NEXT: s_lshr_b32 s74, s25, 16 -; VI-NEXT: s_lshr_b32 s75, s24, 16 -; VI-NEXT: s_lshr_b32 s76, s23, 16 -; VI-NEXT: s_lshr_b32 s77, s22, 16 -; VI-NEXT: s_lshr_b32 s78, s21, 16 -; VI-NEXT: s_lshr_b32 s79, s20, 16 -; VI-NEXT: s_lshr_b32 s88, s19, 16 -; VI-NEXT: s_lshr_b32 s89, s18, 16 -; VI-NEXT: s_lshr_b32 s90, s17, 16 -; VI-NEXT: s_lshr_b32 s91, s16, 16 +; VI-NEXT: s_lshr_b32 s60, s16, 16 +; VI-NEXT: s_lshr_b32 s61, s17, 16 +; VI-NEXT: s_lshr_b32 s62, s18, 16 +; VI-NEXT: s_lshr_b32 s63, s19, 16 +; VI-NEXT: s_lshr_b32 s72, s20, 16 +; VI-NEXT: s_lshr_b32 s73, s21, 16 +; VI-NEXT: s_lshr_b32 s74, s22, 16 +; VI-NEXT: s_lshr_b32 s75, s23, 16 +; VI-NEXT: s_lshr_b32 s76, s24, 16 +; VI-NEXT: s_lshr_b32 s77, s25, 16 +; VI-NEXT: s_lshr_b32 s78, s26, 16 +; VI-NEXT: s_lshr_b32 s79, s40, 16 +; VI-NEXT: s_lshr_b32 s88, s41, 16 +; VI-NEXT: s_lshr_b32 s89, s42, 16 +; VI-NEXT: s_lshr_b32 s90, s43, 16 +; VI-NEXT: s_lshr_b32 s91, s44, 16 ; VI-NEXT: .LBB45_3: ; %end -; VI-NEXT: s_and_b32 s4, 0xffff, s16 +; VI-NEXT: s_and_b32 s4, 0xffff, s44 ; VI-NEXT: s_lshl_b32 s5, s91, 16 ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_and_b32 s5, 0xffff, s17 -; VI-NEXT: s_lshl_b32 s16, s90, 16 -; VI-NEXT: s_or_b32 s5, s5, s16 -; VI-NEXT: s_and_b32 s16, 0xffff, s18 -; VI-NEXT: s_lshl_b32 s17, s89, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, 0xffff, s19 -; VI-NEXT: s_lshl_b32 s18, s88, 16 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s18, 0xffff, s20 -; VI-NEXT: s_lshl_b32 s19, s79, 16 -; VI-NEXT: s_or_b32 s18, s18, s19 -; VI-NEXT: s_and_b32 s19, 0xffff, s21 -; VI-NEXT: s_lshl_b32 s20, s78, 16 -; VI-NEXT: s_or_b32 s19, s19, s20 -; VI-NEXT: s_and_b32 s20, 0xffff, s22 -; VI-NEXT: s_lshl_b32 s21, s77, 16 -; VI-NEXT: s_or_b32 s20, s20, s21 -; VI-NEXT: s_and_b32 s21, 0xffff, s23 -; VI-NEXT: s_lshl_b32 s22, s76, 16 -; VI-NEXT: s_or_b32 s21, s21, s22 -; VI-NEXT: s_and_b32 s22, 0xffff, s24 -; VI-NEXT: s_lshl_b32 s23, s75, 16 -; VI-NEXT: s_or_b32 s22, s22, s23 -; VI-NEXT: s_and_b32 s23, 0xffff, s25 -; VI-NEXT: s_lshl_b32 s24, s74, 16 -; VI-NEXT: s_or_b32 s23, s23, s24 -; VI-NEXT: s_and_b32 s24, 0xffff, s26 -; VI-NEXT: s_lshl_b32 s25, s73, 16 -; VI-NEXT: s_or_b32 s24, s24, s25 -; VI-NEXT: s_and_b32 s25, 0xffff, s27 -; VI-NEXT: s_lshl_b32 s26, s72, 16 -; VI-NEXT: s_or_b32 s25, s25, s26 -; VI-NEXT: s_and_b32 s26, 0xffff, s28 -; VI-NEXT: s_lshl_b32 s27, s63, 16 -; VI-NEXT: s_or_b32 s26, s26, s27 -; VI-NEXT: s_and_b32 s27, 0xffff, s29 -; VI-NEXT: s_lshl_b32 s28, s62, 16 -; VI-NEXT: s_or_b32 s27, s27, s28 -; VI-NEXT: s_and_b32 s28, 0xffff, s41 -; VI-NEXT: s_lshl_b32 s29, s61, 16 -; VI-NEXT: s_or_b32 s28, s28, s29 -; VI-NEXT: s_and_b32 s29, 0xffff, s40 -; VI-NEXT: s_lshl_b32 s40, s60, 16 -; VI-NEXT: s_or_b32 s29, s29, s40 +; VI-NEXT: s_and_b32 s5, 0xffff, s43 +; VI-NEXT: s_lshl_b32 s43, s90, 16 +; VI-NEXT: s_or_b32 s5, s5, s43 +; VI-NEXT: s_and_b32 s42, 0xffff, s42 +; VI-NEXT: s_lshl_b32 s43, s89, 16 +; VI-NEXT: s_or_b32 s42, s42, s43 +; VI-NEXT: s_and_b32 s41, 0xffff, s41 +; VI-NEXT: s_lshl_b32 s43, s88, 16 +; VI-NEXT: s_or_b32 s41, s41, s43 +; VI-NEXT: s_and_b32 s40, 0xffff, s40 +; VI-NEXT: s_lshl_b32 s43, s79, 16 +; VI-NEXT: s_or_b32 s40, s40, s43 +; VI-NEXT: s_and_b32 s26, 0xffff, s26 +; VI-NEXT: s_lshl_b32 s43, s78, 16 +; VI-NEXT: s_or_b32 s26, s26, s43 +; VI-NEXT: s_and_b32 s25, 0xffff, s25 +; VI-NEXT: s_lshl_b32 s43, s77, 16 +; VI-NEXT: s_or_b32 s25, s25, s43 +; VI-NEXT: s_and_b32 s24, 0xffff, s24 +; VI-NEXT: s_lshl_b32 s43, s76, 16 +; VI-NEXT: s_or_b32 s24, s24, s43 +; VI-NEXT: s_and_b32 s23, 0xffff, s23 +; VI-NEXT: s_lshl_b32 s43, s75, 16 +; VI-NEXT: s_or_b32 s23, s23, s43 +; VI-NEXT: s_and_b32 s22, 0xffff, s22 +; VI-NEXT: s_lshl_b32 s43, s74, 16 +; VI-NEXT: s_or_b32 s22, s22, s43 +; VI-NEXT: s_and_b32 s21, 0xffff, s21 +; VI-NEXT: s_lshl_b32 s43, s73, 16 +; VI-NEXT: s_or_b32 s21, s21, s43 +; VI-NEXT: s_and_b32 s20, 0xffff, s20 +; VI-NEXT: s_lshl_b32 s43, s72, 16 +; VI-NEXT: s_or_b32 s20, s20, s43 +; VI-NEXT: s_and_b32 s19, 0xffff, s19 +; VI-NEXT: s_lshl_b32 s43, s63, 16 +; VI-NEXT: s_or_b32 s19, s19, s43 +; VI-NEXT: s_and_b32 s18, 0xffff, s18 +; VI-NEXT: s_lshl_b32 s43, s62, 16 +; VI-NEXT: s_or_b32 s18, s18, s43 +; VI-NEXT: s_and_b32 s17, 0xffff, s17 +; VI-NEXT: s_lshl_b32 s43, s61, 16 +; VI-NEXT: s_or_b32 s17, s17, s43 +; VI-NEXT: s_and_b32 s16, 0xffff, s16 +; VI-NEXT: s_lshl_b32 s43, s60, 16 +; VI-NEXT: s_or_b32 s16, s16, s43 ; VI-NEXT: s_and_b32 s15, 0xffff, s15 -; VI-NEXT: s_lshl_b32 s40, s59, 16 -; VI-NEXT: s_or_b32 s15, s15, s40 +; VI-NEXT: s_lshl_b32 s43, s59, 16 +; VI-NEXT: s_or_b32 s15, s15, s43 ; VI-NEXT: s_and_b32 s14, 0xffff, s14 -; VI-NEXT: s_lshl_b32 s40, s58, 16 -; VI-NEXT: s_or_b32 s14, s14, s40 +; VI-NEXT: s_lshl_b32 s43, s58, 16 +; VI-NEXT: s_or_b32 s14, s14, s43 ; VI-NEXT: s_and_b32 s13, 0xffff, s13 -; VI-NEXT: s_lshl_b32 s40, s57, 16 -; VI-NEXT: s_or_b32 s13, s13, s40 +; VI-NEXT: s_lshl_b32 s43, s57, 16 +; VI-NEXT: s_or_b32 s13, s13, s43 ; VI-NEXT: s_and_b32 s12, 0xffff, s12 -; VI-NEXT: s_lshl_b32 s40, s56, 16 -; VI-NEXT: s_or_b32 s12, s12, s40 +; VI-NEXT: s_lshl_b32 s43, s56, 16 +; VI-NEXT: s_or_b32 s12, s12, s43 ; VI-NEXT: s_and_b32 s11, 0xffff, s11 -; VI-NEXT: s_lshl_b32 s40, s47, 16 -; VI-NEXT: s_or_b32 s11, s11, s40 +; VI-NEXT: s_lshl_b32 s43, s47, 16 +; VI-NEXT: s_or_b32 s11, s11, s43 ; VI-NEXT: s_and_b32 s10, 0xffff, s10 -; VI-NEXT: s_lshl_b32 s40, s46, 16 -; VI-NEXT: s_or_b32 s10, s10, s40 +; VI-NEXT: s_lshl_b32 s43, s46, 16 +; VI-NEXT: s_or_b32 s10, s10, s43 ; VI-NEXT: s_and_b32 s9, 0xffff, s9 -; VI-NEXT: s_lshl_b32 s40, s45, 16 -; VI-NEXT: s_or_b32 s9, s9, s40 +; VI-NEXT: s_lshl_b32 s43, s45, 16 ; VI-NEXT: s_and_b32 s8, 0xffff, s8 -; VI-NEXT: s_lshl_b32 s40, s44, 16 -; VI-NEXT: s_or_b32 s8, s8, s40 +; VI-NEXT: s_lshl_b32 s29, s29, 16 ; VI-NEXT: s_and_b32 s6, 0xffff, s6 -; VI-NEXT: s_lshl_b32 s40, s43, 16 -; VI-NEXT: s_or_b32 s6, s6, s40 +; VI-NEXT: s_lshl_b32 s28, s28, 16 ; VI-NEXT: s_and_b32 s7, 0xffff, s7 -; VI-NEXT: s_lshl_b32 s40, s42, 16 -; VI-NEXT: s_or_b32 s7, s7, s40 +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s9, s9, s43 +; VI-NEXT: s_or_b32 s8, s8, s29 +; VI-NEXT: s_or_b32 s6, s6, s28 +; VI-NEXT: s_or_b32 s7, s7, s27 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s5 -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: v_mov_b32_e32 v3, s17 -; VI-NEXT: v_mov_b32_e32 v4, s18 -; VI-NEXT: v_mov_b32_e32 v5, s19 -; VI-NEXT: v_mov_b32_e32 v6, s20 -; VI-NEXT: v_mov_b32_e32 v7, s21 -; VI-NEXT: v_mov_b32_e32 v8, s22 -; VI-NEXT: v_mov_b32_e32 v9, s23 -; VI-NEXT: v_mov_b32_e32 v10, s24 -; VI-NEXT: v_mov_b32_e32 v11, s25 -; VI-NEXT: v_mov_b32_e32 v12, s26 -; VI-NEXT: v_mov_b32_e32 v13, s27 -; VI-NEXT: v_mov_b32_e32 v14, s28 -; VI-NEXT: v_mov_b32_e32 v15, s29 +; VI-NEXT: v_mov_b32_e32 v2, s42 +; VI-NEXT: v_mov_b32_e32 v3, s41 +; VI-NEXT: v_mov_b32_e32 v4, s40 +; VI-NEXT: v_mov_b32_e32 v5, s26 +; VI-NEXT: v_mov_b32_e32 v6, s25 +; VI-NEXT: v_mov_b32_e32 v7, s24 +; VI-NEXT: v_mov_b32_e32 v8, s23 +; VI-NEXT: v_mov_b32_e32 v9, s22 +; VI-NEXT: v_mov_b32_e32 v10, s21 +; VI-NEXT: v_mov_b32_e32 v11, s20 +; VI-NEXT: v_mov_b32_e32 v12, s19 +; VI-NEXT: v_mov_b32_e32 v13, s18 +; VI-NEXT: v_mov_b32_e32 v14, s17 +; VI-NEXT: v_mov_b32_e32 v15, s16 ; VI-NEXT: v_mov_b32_e32 v16, s15 ; VI-NEXT: v_mov_b32_e32 v17, s14 ; VI-NEXT: v_mov_b32_e32 v18, s13 @@ -29213,25 +28743,53 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i ; VI-NEXT: ; implicit-def: $sgpr47 ; VI-NEXT: ; implicit-def: $sgpr46 ; VI-NEXT: ; implicit-def: $sgpr45 -; VI-NEXT: ; implicit-def: $sgpr44 -; VI-NEXT: ; implicit-def: $sgpr43 -; VI-NEXT: ; implicit-def: $sgpr42 +; VI-NEXT: ; implicit-def: $sgpr29 +; VI-NEXT: ; implicit-def: $sgpr28 +; VI-NEXT: ; implicit-def: $sgpr27 ; VI-NEXT: s_branch .LBB45_2 ; ; GFX9-LABEL: bitcast_v13i64_to_v52f16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v13, s16 +; GFX9-NEXT: v_mov_b32_e32 v14, s17 +; GFX9-NEXT: v_mov_b32_e32 v15, s18 +; GFX9-NEXT: v_mov_b32_e32 v16, s19 +; GFX9-NEXT: v_mov_b32_e32 v17, s20 +; GFX9-NEXT: v_mov_b32_e32 v18, s21 +; GFX9-NEXT: v_mov_b32_e32 v19, s22 +; GFX9-NEXT: v_readfirstlane_b32 s6, v13 +; GFX9-NEXT: v_mov_b32_e32 v13, s23 +; GFX9-NEXT: v_readfirstlane_b32 s7, v14 +; GFX9-NEXT: v_mov_b32_e32 v14, s24 +; GFX9-NEXT: v_readfirstlane_b32 s8, v15 +; GFX9-NEXT: v_mov_b32_e32 v15, s25 +; GFX9-NEXT: v_readfirstlane_b32 s9, v16 +; GFX9-NEXT: v_mov_b32_e32 v16, s26 +; GFX9-NEXT: v_readfirstlane_b32 s10, v17 +; GFX9-NEXT: v_mov_b32_e32 v17, s27 +; GFX9-NEXT: v_readfirstlane_b32 s11, v18 +; GFX9-NEXT: v_mov_b32_e32 v18, s28 +; GFX9-NEXT: v_readfirstlane_b32 s12, v19 +; GFX9-NEXT: v_mov_b32_e32 v19, s29 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 -; GFX9-NEXT: v_readfirstlane_b32 s6, v0 -; GFX9-NEXT: v_readfirstlane_b32 s7, v1 -; GFX9-NEXT: v_readfirstlane_b32 s8, v2 -; GFX9-NEXT: v_readfirstlane_b32 s9, v3 -; GFX9-NEXT: v_readfirstlane_b32 s10, v4 -; GFX9-NEXT: v_readfirstlane_b32 s11, v5 -; GFX9-NEXT: v_readfirstlane_b32 s12, v6 -; GFX9-NEXT: v_readfirstlane_b32 s13, v7 -; GFX9-NEXT: v_readfirstlane_b32 s14, v8 -; GFX9-NEXT: v_readfirstlane_b32 s15, v9 +; GFX9-NEXT: v_readfirstlane_b32 s13, v13 +; GFX9-NEXT: v_readfirstlane_b32 s14, v14 +; GFX9-NEXT: v_readfirstlane_b32 s15, v15 +; GFX9-NEXT: v_readfirstlane_b32 s16, v16 +; GFX9-NEXT: v_readfirstlane_b32 s17, v17 +; GFX9-NEXT: v_readfirstlane_b32 s18, v18 +; GFX9-NEXT: v_readfirstlane_b32 s19, v19 +; GFX9-NEXT: v_readfirstlane_b32 s20, v0 +; GFX9-NEXT: v_readfirstlane_b32 s21, v1 +; GFX9-NEXT: v_readfirstlane_b32 s22, v2 +; GFX9-NEXT: v_readfirstlane_b32 s23, v3 +; GFX9-NEXT: v_readfirstlane_b32 s24, v4 +; GFX9-NEXT: v_readfirstlane_b32 s25, v5 +; GFX9-NEXT: v_readfirstlane_b32 s26, v6 +; GFX9-NEXT: v_readfirstlane_b32 s27, v7 +; GFX9-NEXT: v_readfirstlane_b32 s28, v8 +; GFX9-NEXT: v_readfirstlane_b32 s29, v9 ; GFX9-NEXT: v_readfirstlane_b32 s40, v10 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s41, v11 @@ -29239,44 +28797,34 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i ; GFX9-NEXT: ; %bb.1: ; %cmp.false ; GFX9-NEXT: s_lshr_b32 s42, s41, 16 ; GFX9-NEXT: s_lshr_b32 s43, s40, 16 -; GFX9-NEXT: s_lshr_b32 s44, s15, 16 -; GFX9-NEXT: s_lshr_b32 s45, s14, 16 -; GFX9-NEXT: s_lshr_b32 s46, s13, 16 -; GFX9-NEXT: s_lshr_b32 s47, s12, 16 -; GFX9-NEXT: s_lshr_b32 s56, s11, 16 -; GFX9-NEXT: s_lshr_b32 s57, s10, 16 -; GFX9-NEXT: s_lshr_b32 s58, s9, 16 -; GFX9-NEXT: s_lshr_b32 s59, s8, 16 -; GFX9-NEXT: s_lshr_b32 s60, s7, 16 -; GFX9-NEXT: s_lshr_b32 s61, s6, 16 -; GFX9-NEXT: s_lshr_b32 s62, s29, 16 -; GFX9-NEXT: s_lshr_b32 s63, s28, 16 -; GFX9-NEXT: s_lshr_b32 s72, s27, 16 -; GFX9-NEXT: s_lshr_b32 s73, s26, 16 -; GFX9-NEXT: s_lshr_b32 s74, s25, 16 -; GFX9-NEXT: s_lshr_b32 s75, s24, 16 -; GFX9-NEXT: s_lshr_b32 s76, s23, 16 -; GFX9-NEXT: s_lshr_b32 s77, s22, 16 -; GFX9-NEXT: s_lshr_b32 s78, s21, 16 -; GFX9-NEXT: s_lshr_b32 s79, s20, 16 -; GFX9-NEXT: s_lshr_b32 s88, s19, 16 -; GFX9-NEXT: s_lshr_b32 s89, s18, 16 -; GFX9-NEXT: s_lshr_b32 s90, s17, 16 -; GFX9-NEXT: s_lshr_b32 s91, s16, 16 +; GFX9-NEXT: s_lshr_b32 s44, s29, 16 +; GFX9-NEXT: s_lshr_b32 s45, s28, 16 +; GFX9-NEXT: s_lshr_b32 s46, s27, 16 +; GFX9-NEXT: s_lshr_b32 s47, s26, 16 +; GFX9-NEXT: s_lshr_b32 s56, s25, 16 +; GFX9-NEXT: s_lshr_b32 s57, s24, 16 +; GFX9-NEXT: s_lshr_b32 s58, s23, 16 +; GFX9-NEXT: s_lshr_b32 s59, s22, 16 +; GFX9-NEXT: s_lshr_b32 s60, s21, 16 +; GFX9-NEXT: s_lshr_b32 s61, s20, 16 +; GFX9-NEXT: s_lshr_b32 s62, s19, 16 +; GFX9-NEXT: s_lshr_b32 s63, s18, 16 +; GFX9-NEXT: s_lshr_b32 s72, s17, 16 +; GFX9-NEXT: s_lshr_b32 s73, s16, 16 +; GFX9-NEXT: s_lshr_b32 s74, s15, 16 +; GFX9-NEXT: s_lshr_b32 s75, s14, 16 +; GFX9-NEXT: s_lshr_b32 s76, s13, 16 +; GFX9-NEXT: s_lshr_b32 s77, s12, 16 +; GFX9-NEXT: s_lshr_b32 s78, s11, 16 +; GFX9-NEXT: s_lshr_b32 s79, s10, 16 +; GFX9-NEXT: s_lshr_b32 s88, s9, 16 +; GFX9-NEXT: s_lshr_b32 s89, s8, 16 +; GFX9-NEXT: s_lshr_b32 s90, s7, 16 +; GFX9-NEXT: s_lshr_b32 s91, s6, 16 ; GFX9-NEXT: s_cbranch_execnz .LBB45_3 ; GFX9-NEXT: .LBB45_2: ; %cmp.true ; GFX9-NEXT: s_add_u32 s40, s40, 3 ; GFX9-NEXT: s_addc_u32 s41, s41, 0 -; GFX9-NEXT: s_add_u32 s14, s14, 3 -; GFX9-NEXT: s_addc_u32 s15, s15, 0 -; GFX9-NEXT: s_add_u32 s12, s12, 3 -; GFX9-NEXT: s_addc_u32 s13, s13, 0 -; GFX9-NEXT: s_add_u32 s10, s10, 3 -; GFX9-NEXT: s_addc_u32 s11, s11, 0 -; GFX9-NEXT: s_add_u32 s8, s8, 3 -; GFX9-NEXT: s_addc_u32 s9, s9, 0 -; GFX9-NEXT: s_add_u32 s6, s6, 3 -; GFX9-NEXT: s_addc_u32 s7, s7, 0 ; GFX9-NEXT: s_add_u32 s28, s28, 3 ; GFX9-NEXT: s_addc_u32 s29, s29, 0 ; GFX9-NEXT: s_add_u32 s26, s26, 3 @@ -29291,83 +28839,93 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i ; GFX9-NEXT: s_addc_u32 s19, s19, 0 ; GFX9-NEXT: s_add_u32 s16, s16, 3 ; GFX9-NEXT: s_addc_u32 s17, s17, 0 +; GFX9-NEXT: s_add_u32 s14, s14, 3 +; GFX9-NEXT: s_addc_u32 s15, s15, 0 +; GFX9-NEXT: s_add_u32 s12, s12, 3 +; GFX9-NEXT: s_addc_u32 s13, s13, 0 +; GFX9-NEXT: s_add_u32 s10, s10, 3 +; GFX9-NEXT: s_addc_u32 s11, s11, 0 +; GFX9-NEXT: s_add_u32 s8, s8, 3 +; GFX9-NEXT: s_addc_u32 s9, s9, 0 +; GFX9-NEXT: s_add_u32 s6, s6, 3 +; GFX9-NEXT: s_addc_u32 s7, s7, 0 ; GFX9-NEXT: s_lshr_b32 s42, s41, 16 ; GFX9-NEXT: s_lshr_b32 s43, s40, 16 -; GFX9-NEXT: s_lshr_b32 s44, s15, 16 -; GFX9-NEXT: s_lshr_b32 s45, s14, 16 -; GFX9-NEXT: s_lshr_b32 s46, s13, 16 -; GFX9-NEXT: s_lshr_b32 s47, s12, 16 -; GFX9-NEXT: s_lshr_b32 s56, s11, 16 -; GFX9-NEXT: s_lshr_b32 s57, s10, 16 -; GFX9-NEXT: s_lshr_b32 s58, s9, 16 -; GFX9-NEXT: s_lshr_b32 s59, s8, 16 -; GFX9-NEXT: s_lshr_b32 s60, s7, 16 -; GFX9-NEXT: s_lshr_b32 s61, s6, 16 -; GFX9-NEXT: s_lshr_b32 s62, s29, 16 -; GFX9-NEXT: s_lshr_b32 s63, s28, 16 -; GFX9-NEXT: s_lshr_b32 s72, s27, 16 -; GFX9-NEXT: s_lshr_b32 s73, s26, 16 -; GFX9-NEXT: s_lshr_b32 s74, s25, 16 -; GFX9-NEXT: s_lshr_b32 s75, s24, 16 -; GFX9-NEXT: s_lshr_b32 s76, s23, 16 -; GFX9-NEXT: s_lshr_b32 s77, s22, 16 -; GFX9-NEXT: s_lshr_b32 s78, s21, 16 -; GFX9-NEXT: s_lshr_b32 s79, s20, 16 -; GFX9-NEXT: s_lshr_b32 s88, s19, 16 -; GFX9-NEXT: s_lshr_b32 s89, s18, 16 -; GFX9-NEXT: s_lshr_b32 s90, s17, 16 -; GFX9-NEXT: s_lshr_b32 s91, s16, 16 +; GFX9-NEXT: s_lshr_b32 s44, s29, 16 +; GFX9-NEXT: s_lshr_b32 s45, s28, 16 +; GFX9-NEXT: s_lshr_b32 s46, s27, 16 +; GFX9-NEXT: s_lshr_b32 s47, s26, 16 +; GFX9-NEXT: s_lshr_b32 s56, s25, 16 +; GFX9-NEXT: s_lshr_b32 s57, s24, 16 +; GFX9-NEXT: s_lshr_b32 s58, s23, 16 +; GFX9-NEXT: s_lshr_b32 s59, s22, 16 +; GFX9-NEXT: s_lshr_b32 s60, s21, 16 +; GFX9-NEXT: s_lshr_b32 s61, s20, 16 +; GFX9-NEXT: s_lshr_b32 s62, s19, 16 +; GFX9-NEXT: s_lshr_b32 s63, s18, 16 +; GFX9-NEXT: s_lshr_b32 s72, s17, 16 +; GFX9-NEXT: s_lshr_b32 s73, s16, 16 +; GFX9-NEXT: s_lshr_b32 s74, s15, 16 +; GFX9-NEXT: s_lshr_b32 s75, s14, 16 +; GFX9-NEXT: s_lshr_b32 s76, s13, 16 +; GFX9-NEXT: s_lshr_b32 s77, s12, 16 +; GFX9-NEXT: s_lshr_b32 s78, s11, 16 +; GFX9-NEXT: s_lshr_b32 s79, s10, 16 +; GFX9-NEXT: s_lshr_b32 s88, s9, 16 +; GFX9-NEXT: s_lshr_b32 s89, s8, 16 +; GFX9-NEXT: s_lshr_b32 s90, s7, 16 +; GFX9-NEXT: s_lshr_b32 s91, s6, 16 ; GFX9-NEXT: .LBB45_3: ; %end -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s16, s91 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s17, s90 -; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s89 -; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s88 -; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s79 -; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s78 -; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s77 -; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s76 -; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s75 -; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s74 -; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s73 -; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s72 -; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s63 -; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s62 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s61 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s60 -; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s59 -; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s58 -; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s57 -; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s56 -; GFX9-NEXT: s_pack_ll_b32_b16 s12, s12, s47 -; GFX9-NEXT: s_pack_ll_b32_b16 s13, s13, s46 -; GFX9-NEXT: s_pack_ll_b32_b16 s14, s14, s45 -; GFX9-NEXT: s_pack_ll_b32_b16 s15, s15, s44 +; GFX9-NEXT: s_pack_ll_b32_b16 s4, s6, s91 +; GFX9-NEXT: s_pack_ll_b32_b16 s5, s7, s90 +; GFX9-NEXT: s_pack_ll_b32_b16 s6, s8, s89 +; GFX9-NEXT: s_pack_ll_b32_b16 s7, s9, s88 +; GFX9-NEXT: s_pack_ll_b32_b16 s8, s10, s79 +; GFX9-NEXT: s_pack_ll_b32_b16 s9, s11, s78 +; GFX9-NEXT: s_pack_ll_b32_b16 s10, s12, s77 +; GFX9-NEXT: s_pack_ll_b32_b16 s11, s13, s76 +; GFX9-NEXT: s_pack_ll_b32_b16 s12, s14, s75 +; GFX9-NEXT: s_pack_ll_b32_b16 s13, s15, s74 +; GFX9-NEXT: s_pack_ll_b32_b16 s14, s16, s73 +; GFX9-NEXT: s_pack_ll_b32_b16 s15, s17, s72 +; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s63 +; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s62 +; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s61 +; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s60 +; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s59 +; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s58 +; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s57 +; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s56 +; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s47 +; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s46 +; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s45 +; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s44 ; GFX9-NEXT: s_pack_ll_b32_b16 s28, s40, s43 ; GFX9-NEXT: s_pack_ll_b32_b16 s29, s41, s42 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 -; GFX9-NEXT: v_mov_b32_e32 v2, s16 -; GFX9-NEXT: v_mov_b32_e32 v3, s17 -; GFX9-NEXT: v_mov_b32_e32 v4, s18 -; GFX9-NEXT: v_mov_b32_e32 v5, s19 -; GFX9-NEXT: v_mov_b32_e32 v6, s20 -; GFX9-NEXT: v_mov_b32_e32 v7, s21 -; GFX9-NEXT: v_mov_b32_e32 v8, s22 -; GFX9-NEXT: v_mov_b32_e32 v9, s23 -; GFX9-NEXT: v_mov_b32_e32 v10, s24 -; GFX9-NEXT: v_mov_b32_e32 v11, s25 -; GFX9-NEXT: v_mov_b32_e32 v12, s26 -; GFX9-NEXT: v_mov_b32_e32 v13, s27 -; GFX9-NEXT: v_mov_b32_e32 v14, s6 -; GFX9-NEXT: v_mov_b32_e32 v15, s7 -; GFX9-NEXT: v_mov_b32_e32 v16, s8 -; GFX9-NEXT: v_mov_b32_e32 v17, s9 -; GFX9-NEXT: v_mov_b32_e32 v18, s10 -; GFX9-NEXT: v_mov_b32_e32 v19, s11 -; GFX9-NEXT: v_mov_b32_e32 v20, s12 -; GFX9-NEXT: v_mov_b32_e32 v21, s13 -; GFX9-NEXT: v_mov_b32_e32 v22, s14 -; GFX9-NEXT: v_mov_b32_e32 v23, s15 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: v_mov_b32_e32 v4, s8 +; GFX9-NEXT: v_mov_b32_e32 v5, s9 +; GFX9-NEXT: v_mov_b32_e32 v6, s10 +; GFX9-NEXT: v_mov_b32_e32 v7, s11 +; GFX9-NEXT: v_mov_b32_e32 v8, s12 +; GFX9-NEXT: v_mov_b32_e32 v9, s13 +; GFX9-NEXT: v_mov_b32_e32 v10, s14 +; GFX9-NEXT: v_mov_b32_e32 v11, s15 +; GFX9-NEXT: v_mov_b32_e32 v12, s16 +; GFX9-NEXT: v_mov_b32_e32 v13, s17 +; GFX9-NEXT: v_mov_b32_e32 v14, s18 +; GFX9-NEXT: v_mov_b32_e32 v15, s19 +; GFX9-NEXT: v_mov_b32_e32 v16, s20 +; GFX9-NEXT: v_mov_b32_e32 v17, s21 +; GFX9-NEXT: v_mov_b32_e32 v18, s22 +; GFX9-NEXT: v_mov_b32_e32 v19, s23 +; GFX9-NEXT: v_mov_b32_e32 v20, s24 +; GFX9-NEXT: v_mov_b32_e32 v21, s25 +; GFX9-NEXT: v_mov_b32_e32 v22, s26 +; GFX9-NEXT: v_mov_b32_e32 v23, s27 ; GFX9-NEXT: v_mov_b32_e32 v24, s28 ; GFX9-NEXT: v_mov_b32_e32 v25, s29 ; GFX9-NEXT: s_setpc_b64 s[30:31] @@ -29403,41 +28961,68 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i ; GFX11-LABEL: bitcast_v13i64_to_v52f16_scalar: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v9, s0 :: v_dual_mov_b32 v10, s1 +; GFX11-NEXT: v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v12, s3 +; GFX11-NEXT: v_dual_mov_b32 v13, s16 :: v_dual_mov_b32 v14, s17 +; GFX11-NEXT: v_dual_mov_b32 v15, s18 :: v_dual_mov_b32 v16, s19 +; GFX11-NEXT: v_dual_mov_b32 v17, s20 :: v_dual_mov_b32 v18, s21 +; GFX11-NEXT: v_dual_mov_b32 v19, s22 :: v_dual_mov_b32 v20, s23 +; GFX11-NEXT: v_dual_mov_b32 v21, s24 :: v_dual_mov_b32 v22, s25 +; GFX11-NEXT: v_dual_mov_b32 v23, s26 :: v_dual_mov_b32 v24, s27 +; GFX11-NEXT: v_dual_mov_b32 v25, s28 :: v_dual_mov_b32 v26, s29 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 -; GFX11-NEXT: v_readfirstlane_b32 s4, v0 -; GFX11-NEXT: v_readfirstlane_b32 s5, v1 -; GFX11-NEXT: v_readfirstlane_b32 s6, v2 -; GFX11-NEXT: v_readfirstlane_b32 s7, v3 -; GFX11-NEXT: v_readfirstlane_b32 s8, v4 -; GFX11-NEXT: v_readfirstlane_b32 s9, v5 -; GFX11-NEXT: v_readfirstlane_b32 s11, v6 -; GFX11-NEXT: v_readfirstlane_b32 s10, v7 +; GFX11-NEXT: v_readfirstlane_b32 s0, v9 +; GFX11-NEXT: v_readfirstlane_b32 s1, v10 +; GFX11-NEXT: v_readfirstlane_b32 s2, v11 +; GFX11-NEXT: v_readfirstlane_b32 s3, v12 +; GFX11-NEXT: v_readfirstlane_b32 s4, v13 +; GFX11-NEXT: v_readfirstlane_b32 s5, v14 +; GFX11-NEXT: v_readfirstlane_b32 s6, v15 +; GFX11-NEXT: v_readfirstlane_b32 s7, v16 +; GFX11-NEXT: v_readfirstlane_b32 s8, v17 +; GFX11-NEXT: v_readfirstlane_b32 s9, v18 +; GFX11-NEXT: v_readfirstlane_b32 s10, v19 +; GFX11-NEXT: v_readfirstlane_b32 s11, v20 +; GFX11-NEXT: v_readfirstlane_b32 s12, v21 +; GFX11-NEXT: v_readfirstlane_b32 s13, v22 +; GFX11-NEXT: v_readfirstlane_b32 s14, v23 +; GFX11-NEXT: v_readfirstlane_b32 s15, v24 +; GFX11-NEXT: v_readfirstlane_b32 s16, v25 +; GFX11-NEXT: v_readfirstlane_b32 s17, v26 +; GFX11-NEXT: v_readfirstlane_b32 s18, v0 +; GFX11-NEXT: v_readfirstlane_b32 s19, v1 +; GFX11-NEXT: v_readfirstlane_b32 s20, v2 +; GFX11-NEXT: v_readfirstlane_b32 s21, v3 +; GFX11-NEXT: v_readfirstlane_b32 s22, v4 +; GFX11-NEXT: v_readfirstlane_b32 s23, v5 +; GFX11-NEXT: v_readfirstlane_b32 s25, v6 +; GFX11-NEXT: v_readfirstlane_b32 s24, v7 ; GFX11-NEXT: s_mov_b32 s78, 0 -; GFX11-NEXT: s_and_b32 s12, vcc_lo, exec_lo +; GFX11-NEXT: s_and_b32 s26, vcc_lo, exec_lo ; GFX11-NEXT: s_cbranch_scc0 .LBB45_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: s_lshr_b32 s12, s10, 16 -; GFX11-NEXT: s_lshr_b32 s13, s11, 16 -; GFX11-NEXT: s_lshr_b32 s14, s9, 16 -; GFX11-NEXT: s_lshr_b32 s15, s8, 16 -; GFX11-NEXT: s_lshr_b32 s40, s7, 16 -; GFX11-NEXT: s_lshr_b32 s41, s6, 16 -; GFX11-NEXT: s_lshr_b32 s42, s5, 16 -; GFX11-NEXT: s_lshr_b32 s43, s4, 16 -; GFX11-NEXT: s_lshr_b32 s44, s29, 16 -; GFX11-NEXT: s_lshr_b32 s45, s28, 16 -; GFX11-NEXT: s_lshr_b32 s46, s27, 16 -; GFX11-NEXT: s_lshr_b32 s47, s26, 16 -; GFX11-NEXT: s_lshr_b32 s56, s25, 16 -; GFX11-NEXT: s_lshr_b32 s57, s24, 16 -; GFX11-NEXT: s_lshr_b32 s58, s23, 16 -; GFX11-NEXT: s_lshr_b32 s59, s22, 16 -; GFX11-NEXT: s_lshr_b32 s60, s21, 16 -; GFX11-NEXT: s_lshr_b32 s61, s20, 16 -; GFX11-NEXT: s_lshr_b32 s62, s19, 16 -; GFX11-NEXT: s_lshr_b32 s63, s18, 16 -; GFX11-NEXT: s_lshr_b32 s72, s17, 16 -; GFX11-NEXT: s_lshr_b32 s73, s16, 16 +; GFX11-NEXT: s_lshr_b32 s26, s24, 16 +; GFX11-NEXT: s_lshr_b32 s27, s25, 16 +; GFX11-NEXT: s_lshr_b32 s28, s23, 16 +; GFX11-NEXT: s_lshr_b32 s29, s22, 16 +; GFX11-NEXT: s_lshr_b32 s40, s21, 16 +; GFX11-NEXT: s_lshr_b32 s41, s20, 16 +; GFX11-NEXT: s_lshr_b32 s42, s19, 16 +; GFX11-NEXT: s_lshr_b32 s43, s18, 16 +; GFX11-NEXT: s_lshr_b32 s44, s17, 16 +; GFX11-NEXT: s_lshr_b32 s45, s16, 16 +; GFX11-NEXT: s_lshr_b32 s46, s15, 16 +; GFX11-NEXT: s_lshr_b32 s47, s14, 16 +; GFX11-NEXT: s_lshr_b32 s56, s13, 16 +; GFX11-NEXT: s_lshr_b32 s57, s12, 16 +; GFX11-NEXT: s_lshr_b32 s58, s11, 16 +; GFX11-NEXT: s_lshr_b32 s59, s10, 16 +; GFX11-NEXT: s_lshr_b32 s60, s9, 16 +; GFX11-NEXT: s_lshr_b32 s61, s8, 16 +; GFX11-NEXT: s_lshr_b32 s62, s7, 16 +; GFX11-NEXT: s_lshr_b32 s63, s6, 16 +; GFX11-NEXT: s_lshr_b32 s72, s5, 16 +; GFX11-NEXT: s_lshr_b32 s73, s4, 16 ; GFX11-NEXT: s_lshr_b32 s74, s3, 16 ; GFX11-NEXT: s_lshr_b32 s75, s2, 16 ; GFX11-NEXT: s_lshr_b32 s76, s1, 16 @@ -29445,20 +29030,8 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s78 ; GFX11-NEXT: s_cbranch_vccnz .LBB45_3 ; GFX11-NEXT: .LBB45_2: ; %cmp.true -; GFX11-NEXT: s_add_u32 s11, s11, 3 -; GFX11-NEXT: s_addc_u32 s10, s10, 0 -; GFX11-NEXT: s_add_u32 s8, s8, 3 -; GFX11-NEXT: s_addc_u32 s9, s9, 0 -; GFX11-NEXT: s_add_u32 s6, s6, 3 -; GFX11-NEXT: s_addc_u32 s7, s7, 0 -; GFX11-NEXT: s_add_u32 s4, s4, 3 -; GFX11-NEXT: s_addc_u32 s5, s5, 0 -; GFX11-NEXT: s_add_u32 s28, s28, 3 -; GFX11-NEXT: s_addc_u32 s29, s29, 0 -; GFX11-NEXT: s_add_u32 s26, s26, 3 -; GFX11-NEXT: s_addc_u32 s27, s27, 0 -; GFX11-NEXT: s_add_u32 s24, s24, 3 -; GFX11-NEXT: s_addc_u32 s25, s25, 0 +; GFX11-NEXT: s_add_u32 s25, s25, 3 +; GFX11-NEXT: s_addc_u32 s24, s24, 0 ; GFX11-NEXT: s_add_u32 s22, s22, 3 ; GFX11-NEXT: s_addc_u32 s23, s23, 0 ; GFX11-NEXT: s_add_u32 s20, s20, 3 @@ -29467,32 +29040,44 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i ; GFX11-NEXT: s_addc_u32 s19, s19, 0 ; GFX11-NEXT: s_add_u32 s16, s16, 3 ; GFX11-NEXT: s_addc_u32 s17, s17, 0 +; GFX11-NEXT: s_add_u32 s14, s14, 3 +; GFX11-NEXT: s_addc_u32 s15, s15, 0 +; GFX11-NEXT: s_add_u32 s12, s12, 3 +; GFX11-NEXT: s_addc_u32 s13, s13, 0 +; GFX11-NEXT: s_add_u32 s10, s10, 3 +; GFX11-NEXT: s_addc_u32 s11, s11, 0 +; GFX11-NEXT: s_add_u32 s8, s8, 3 +; GFX11-NEXT: s_addc_u32 s9, s9, 0 +; GFX11-NEXT: s_add_u32 s6, s6, 3 +; GFX11-NEXT: s_addc_u32 s7, s7, 0 +; GFX11-NEXT: s_add_u32 s4, s4, 3 +; GFX11-NEXT: s_addc_u32 s5, s5, 0 ; GFX11-NEXT: s_add_u32 s2, s2, 3 ; GFX11-NEXT: s_addc_u32 s3, s3, 0 ; GFX11-NEXT: s_add_u32 s0, s0, 3 ; GFX11-NEXT: s_addc_u32 s1, s1, 0 -; GFX11-NEXT: s_lshr_b32 s12, s10, 16 -; GFX11-NEXT: s_lshr_b32 s13, s11, 16 -; GFX11-NEXT: s_lshr_b32 s14, s9, 16 -; GFX11-NEXT: s_lshr_b32 s15, s8, 16 -; GFX11-NEXT: s_lshr_b32 s40, s7, 16 -; GFX11-NEXT: s_lshr_b32 s41, s6, 16 -; GFX11-NEXT: s_lshr_b32 s42, s5, 16 -; GFX11-NEXT: s_lshr_b32 s43, s4, 16 -; GFX11-NEXT: s_lshr_b32 s44, s29, 16 -; GFX11-NEXT: s_lshr_b32 s45, s28, 16 -; GFX11-NEXT: s_lshr_b32 s46, s27, 16 -; GFX11-NEXT: s_lshr_b32 s47, s26, 16 -; GFX11-NEXT: s_lshr_b32 s56, s25, 16 -; GFX11-NEXT: s_lshr_b32 s57, s24, 16 -; GFX11-NEXT: s_lshr_b32 s58, s23, 16 -; GFX11-NEXT: s_lshr_b32 s59, s22, 16 -; GFX11-NEXT: s_lshr_b32 s60, s21, 16 -; GFX11-NEXT: s_lshr_b32 s61, s20, 16 -; GFX11-NEXT: s_lshr_b32 s62, s19, 16 -; GFX11-NEXT: s_lshr_b32 s63, s18, 16 -; GFX11-NEXT: s_lshr_b32 s72, s17, 16 -; GFX11-NEXT: s_lshr_b32 s73, s16, 16 +; GFX11-NEXT: s_lshr_b32 s26, s24, 16 +; GFX11-NEXT: s_lshr_b32 s27, s25, 16 +; GFX11-NEXT: s_lshr_b32 s28, s23, 16 +; GFX11-NEXT: s_lshr_b32 s29, s22, 16 +; GFX11-NEXT: s_lshr_b32 s40, s21, 16 +; GFX11-NEXT: s_lshr_b32 s41, s20, 16 +; GFX11-NEXT: s_lshr_b32 s42, s19, 16 +; GFX11-NEXT: s_lshr_b32 s43, s18, 16 +; GFX11-NEXT: s_lshr_b32 s44, s17, 16 +; GFX11-NEXT: s_lshr_b32 s45, s16, 16 +; GFX11-NEXT: s_lshr_b32 s46, s15, 16 +; GFX11-NEXT: s_lshr_b32 s47, s14, 16 +; GFX11-NEXT: s_lshr_b32 s56, s13, 16 +; GFX11-NEXT: s_lshr_b32 s57, s12, 16 +; GFX11-NEXT: s_lshr_b32 s58, s11, 16 +; GFX11-NEXT: s_lshr_b32 s59, s10, 16 +; GFX11-NEXT: s_lshr_b32 s60, s9, 16 +; GFX11-NEXT: s_lshr_b32 s61, s8, 16 +; GFX11-NEXT: s_lshr_b32 s62, s7, 16 +; GFX11-NEXT: s_lshr_b32 s63, s6, 16 +; GFX11-NEXT: s_lshr_b32 s72, s5, 16 +; GFX11-NEXT: s_lshr_b32 s73, s4, 16 ; GFX11-NEXT: s_lshr_b32 s74, s3, 16 ; GFX11-NEXT: s_lshr_b32 s75, s2, 16 ; GFX11-NEXT: s_lshr_b32 s76, s1, 16 @@ -29503,41 +29088,41 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i ; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s76 ; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s75 ; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s74 -; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s73 -; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s72 -; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s63 -; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s62 -; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s61 -; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s60 -; GFX11-NEXT: s_pack_ll_b32_b16 s22, s22, s59 -; GFX11-NEXT: s_pack_ll_b32_b16 s23, s23, s58 -; GFX11-NEXT: s_pack_ll_b32_b16 s24, s24, s57 -; GFX11-NEXT: s_pack_ll_b32_b16 s25, s25, s56 -; GFX11-NEXT: s_pack_ll_b32_b16 s26, s26, s47 -; GFX11-NEXT: s_pack_ll_b32_b16 s27, s27, s46 -; GFX11-NEXT: s_pack_ll_b32_b16 s28, s28, s45 -; GFX11-NEXT: s_pack_ll_b32_b16 s29, s29, s44 -; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s43 -; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s42 -; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s41 -; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s40 -; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s15 -; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s14 -; GFX11-NEXT: s_pack_ll_b32_b16 s11, s11, s13 -; GFX11-NEXT: s_pack_ll_b32_b16 s10, s10, s12 +; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s73 +; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s72 +; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s63 +; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s62 +; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s61 +; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s60 +; GFX11-NEXT: s_pack_ll_b32_b16 s10, s10, s59 +; GFX11-NEXT: s_pack_ll_b32_b16 s11, s11, s58 +; GFX11-NEXT: s_pack_ll_b32_b16 s12, s12, s57 +; GFX11-NEXT: s_pack_ll_b32_b16 s13, s13, s56 +; GFX11-NEXT: s_pack_ll_b32_b16 s14, s14, s47 +; GFX11-NEXT: s_pack_ll_b32_b16 s15, s15, s46 +; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s45 +; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s44 +; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s43 +; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s42 +; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s41 +; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s40 +; GFX11-NEXT: s_pack_ll_b32_b16 s22, s22, s29 +; GFX11-NEXT: s_pack_ll_b32_b16 s23, s23, s28 +; GFX11-NEXT: s_pack_ll_b32_b16 s25, s25, s27 +; GFX11-NEXT: s_pack_ll_b32_b16 s24, s24, s26 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 -; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 -; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 -; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 -; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 -; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 -; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 -; GFX11-NEXT: v_dual_mov_b32 v18, s4 :: v_dual_mov_b32 v19, s5 -; GFX11-NEXT: v_dual_mov_b32 v20, s6 :: v_dual_mov_b32 v21, s7 -; GFX11-NEXT: v_dual_mov_b32 v22, s8 :: v_dual_mov_b32 v23, s9 -; GFX11-NEXT: v_dual_mov_b32 v24, s11 :: v_dual_mov_b32 v25, s10 +; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19 +; GFX11-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v21, s21 +; GFX11-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v23, s23 +; GFX11-NEXT: v_dual_mov_b32 v24, s25 :: v_dual_mov_b32 v25, s24 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: .LBB45_4: ; GFX11-NEXT: ; implicit-def: $sgpr77 @@ -29562,10 +29147,10 @@ define inreg <52 x half> @bitcast_v13i64_to_v52f16_scalar(<13 x i64> inreg %a, i ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr41 ; GFX11-NEXT: ; implicit-def: $sgpr40 -; GFX11-NEXT: ; implicit-def: $sgpr15 -; GFX11-NEXT: ; implicit-def: $sgpr14 -; GFX11-NEXT: ; implicit-def: $sgpr13 -; GFX11-NEXT: ; implicit-def: $sgpr12 +; GFX11-NEXT: ; implicit-def: $sgpr29 +; GFX11-NEXT: ; implicit-def: $sgpr28 +; GFX11-NEXT: ; implicit-def: $sgpr27 +; GFX11-NEXT: ; implicit-def: $sgpr26 ; GFX11-NEXT: s_branch .LBB45_2 %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -30457,7 +30042,6 @@ define <13 x i64> @bitcast_v52f16_to_v13i64(<52 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v57, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v25 -; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v24 @@ -30524,6 +30108,7 @@ define <13 x i64> @bitcast_v52f16_to_v13i64(<52 x half> %a, i32 %b) { ; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v56 ; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v57 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 +; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -30656,6 +30241,9 @@ define <13 x i64> @bitcast_v52f16_to_v13i64(<52 x half> %a, i32 %b) { ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] ; GFX9-NEXT: s_cbranch_execz .LBB46_4 ; GFX9-NEXT: ; %bb.3: ; %cmp.true +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload @@ -30670,9 +30258,6 @@ define <13 x i64> @bitcast_v52f16_to_v13i64(<52 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v34, v57, s6 ; GFX9-NEXT: s_movk_i32 s7, 0x200 ; GFX9-NEXT: v_perm_b32 v1, v62, v56, s6 @@ -30692,6 +30277,10 @@ define <13 x i64> @bitcast_v52f16_to_v13i64(<52 x half> %a, i32 %b) { ; GFX9-NEXT: v_pk_add_f16 v6, v6, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v7, v7, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v8, v8, s7 op_sel_hi:[1,0] +; GFX9-NEXT: s_waitcnt vmcnt(14) +; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; GFX9-NEXT: s_waitcnt vmcnt(15) ; GFX9-NEXT: v_perm_b32 v9, v9, v40, s6 ; GFX9-NEXT: s_waitcnt vmcnt(14) @@ -30720,10 +30309,6 @@ define <13 x i64> @bitcast_v52f16_to_v13i64(<52 x half> %a, i32 %b) { ; GFX9-NEXT: v_perm_b32 v21, v21, v36, s6 ; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: v_perm_b32 v22, v22, v35, s6 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v10, v10, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0] @@ -30992,14 +30577,28 @@ define inreg <13 x i64> @bitcast_v52f16_to_v13i64_scalar(<52 x half> inreg %a, i ; SI-NEXT: v_cvt_f16_f32_e32 v8, s26 ; SI-NEXT: v_cvt_f16_f32_e32 v6, s29 ; SI-NEXT: v_cvt_f16_f32_e32 v7, s28 -; SI-NEXT: s_waitcnt vmcnt(9) +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cvt_f16_f32_e32 v31, v31 -; SI-NEXT: s_waitcnt vmcnt(8) expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v38 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(8) expcnt(0) +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v39 -; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v44 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill @@ -31015,22 +30614,6 @@ define inreg <13 x i64> @bitcast_v52f16_to_v13i64_scalar(<52 x half> inreg %a, i ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v51 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB47_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload @@ -31039,8 +30622,8 @@ define inreg <13 x i64> @bitcast_v52f16_to_v13i64_scalar(<52 x half> inreg %a, i ; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(2) ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v53 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v12 @@ -31060,10 +30643,8 @@ define inreg <13 x i64> @bitcast_v52f16_to_v13i64_scalar(<52 x half> inreg %a, i ; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v42 ; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v56 ; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v43 -; SI-NEXT: s_waitcnt expcnt(1) ; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v57 ; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v15 ; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v62 ; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v36 @@ -31104,11 +30685,11 @@ define inreg <13 x i64> @bitcast_v52f16_to_v13i64_scalar(<52 x half> inreg %a, i ; SI-NEXT: v_or_b32_e32 v25, v38, v25 ; SI-NEXT: s_cbranch_execnz .LBB47_3 ; SI-NEXT: .LBB47_2: ; %cmp.true -; SI-NEXT: s_waitcnt expcnt(2) ; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f32_f16_e32 v0, v53 ; SI-NEXT: v_cvt_f32_f16_e32 v9, v40 ; SI-NEXT: v_cvt_f32_f16_e32 v10, v55 @@ -31122,7 +30703,6 @@ define inreg <13 x i64> @bitcast_v52f16_to_v13i64_scalar(<52 x half> inreg %a, i ; SI-NEXT: v_cvt_f16_f32_e32 v10, v10 ; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11 ; SI-NEXT: v_cvt_f16_f32_e32 v11, v11 -; SI-NEXT: s_waitcnt expcnt(1) ; SI-NEXT: v_cvt_f32_f16_e32 v12, v47 ; SI-NEXT: v_cvt_f32_f16_e32 v13, v60 ; SI-NEXT: v_cvt_f32_f16_e32 v15, v52 @@ -31160,7 +30740,6 @@ define inreg <13 x i64> @bitcast_v52f16_to_v13i64_scalar(<52 x half> inreg %a, i ; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload @@ -31810,294 +31389,109 @@ define inreg <13 x i64> @bitcast_v52f16_to_v13i64_scalar(<52 x half> inreg %a, i ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v191, v1 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v185, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB47_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB47_3 ; GFX11-TRUE16-NEXT: .LBB47_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s40 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s41 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v185, 0x200, v185 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v191, 0x200, v191 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v190, 0x200, v190 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v189, 0x200, v189 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v188, 0x200, v188 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v187, 0x200, v187 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v186, 0x200, v186 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, s6 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, s7 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, s8 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s9 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, s10 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, s11 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, s12 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, s13 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s14 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, s15 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, s16 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s0 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s1 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s2 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, s3 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, s4 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v35, 0x200, s5 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v44, 0x200, s6 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v54, 0x200, s7 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v65, 0x200, s8 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v77, 0x200, s9 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v90, 0x200, s10 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v104, 0x200, s11 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v119, 0x200, s12 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v135, 0x200, s13 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v152, 0x200, s14 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v170, 0x200, s15 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: .LBB47_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v170 :: v_dual_mov_b32 v18, v185 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v191 :: v_dual_mov_b32 v20, v190 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v189 :: v_dual_mov_b32 v22, v188 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v187 :: v_dual_mov_b32 v24, v186 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v191, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v190, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v189, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v188, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v187, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:316 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v14, v119 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB47_4: -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v53, v25 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v25, v53 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB47_2 ; ; GFX11-FAKE16-LABEL: bitcast_v52f16_to_v13i64_scalar: @@ -33320,8 +32714,8 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; VI-NEXT: v_mov_b32_e32 v21, s16 ; VI-NEXT: v_mov_b32_e32 v22, s17 -; VI-NEXT: v_mov_b32_e32 v17, s18 -; VI-NEXT: v_mov_b32_e32 v18, s19 +; VI-NEXT: v_mov_b32_e32 v15, s18 +; VI-NEXT: v_mov_b32_e32 v16, s19 ; VI-NEXT: v_mov_b32_e32 v13, s20 ; VI-NEXT: v_mov_b32_e32 v14, s21 ; VI-NEXT: v_mov_b32_e32 v30, s22 @@ -33331,8 +32725,8 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; VI-NEXT: v_mov_b32_e32 v19, s26 ; VI-NEXT: v_mov_b32_e32 v20, s27 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec -; VI-NEXT: v_mov_b32_e32 v15, s28 -; VI-NEXT: v_mov_b32_e32 v16, s29 +; VI-NEXT: v_mov_b32_e32 v17, s28 +; VI-NEXT: v_mov_b32_e32 v18, s29 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill @@ -33351,8 +32745,8 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v2 ; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1 ; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v0 -; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v16 -; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v15 +; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v18 +; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v17 ; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v20 ; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v19 ; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v24 @@ -33361,8 +32755,8 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v30 ; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v14 ; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v13 -; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v18 -; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v17 +; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v16 +; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v15 ; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v22 ; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v21 ; VI-NEXT: s_cbranch_execnz .LBB49_3 @@ -33373,12 +32767,12 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 ; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 ; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 -; VI-NEXT: v_add_f64 v[15:16], v[15:16], 1.0 +; VI-NEXT: v_add_f64 v[17:18], v[17:18], 1.0 ; VI-NEXT: v_add_f64 v[19:20], v[19:20], 1.0 ; VI-NEXT: v_add_f64 v[23:24], v[23:24], 1.0 ; VI-NEXT: v_add_f64 v[30:31], v[30:31], 1.0 ; VI-NEXT: v_add_f64 v[13:14], v[13:14], 1.0 -; VI-NEXT: v_add_f64 v[17:18], v[17:18], 1.0 +; VI-NEXT: v_add_f64 v[15:16], v[15:16], 1.0 ; VI-NEXT: v_add_f64 v[21:22], v[21:22], 1.0 ; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v11 ; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v10 @@ -33392,8 +32786,8 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v2 ; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1 ; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v0 -; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v16 -; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v15 +; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v18 +; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v17 ; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v20 ; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v19 ; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v24 @@ -33402,8 +32796,8 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v30 ; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v14 ; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v13 -; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v18 -; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v17 +; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v16 +; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v15 ; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v22 ; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v21 ; VI-NEXT: .LBB49_3: ; %end @@ -33412,11 +32806,11 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v37 ; VI-NEXT: v_or_b32_sdwa v37, v22, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v26 -; VI-NEXT: v_or_b32_sdwa v26, v17, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v27 -; VI-NEXT: v_or_b32_sdwa v27, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v28 -; VI-NEXT: v_or_b32_sdwa v28, v13, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v26, v15, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v27 +; VI-NEXT: v_or_b32_sdwa v27, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v28 +; VI-NEXT: v_or_b32_sdwa v28, v13, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v29 ; VI-NEXT: v_or_b32_sdwa v29, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v43 @@ -33437,17 +32831,17 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12 ; VI-NEXT: v_or_b32_sdwa v14, v0, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v55 -; VI-NEXT: v_or_b32_sdwa v12, v15, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v15, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v54 -; VI-NEXT: v_or_b32_sdwa v13, v16, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12 ; VI-NEXT: v_or_b32_sdwa v16, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v53 +; VI-NEXT: v_or_b32_sdwa v12, v17, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v17, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v52 +; VI-NEXT: v_or_b32_sdwa v13, v18, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v18, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v51 ; VI-NEXT: v_or_b32_sdwa v19, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD @@ -33512,8 +32906,8 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX9-NEXT: v_mov_b32_e32 v21, s16 ; GFX9-NEXT: v_mov_b32_e32 v22, s17 -; GFX9-NEXT: v_mov_b32_e32 v17, s18 -; GFX9-NEXT: v_mov_b32_e32 v18, s19 +; GFX9-NEXT: v_mov_b32_e32 v15, s18 +; GFX9-NEXT: v_mov_b32_e32 v16, s19 ; GFX9-NEXT: v_mov_b32_e32 v13, s20 ; GFX9-NEXT: v_mov_b32_e32 v14, s21 ; GFX9-NEXT: v_mov_b32_e32 v30, s22 @@ -33523,8 +32917,8 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; GFX9-NEXT: v_mov_b32_e32 v19, s26 ; GFX9-NEXT: v_mov_b32_e32 v20, s27 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec -; GFX9-NEXT: v_mov_b32_e32 v15, s28 -; GFX9-NEXT: v_mov_b32_e32 v16, s29 +; GFX9-NEXT: v_mov_b32_e32 v17, s28 +; GFX9-NEXT: v_mov_b32_e32 v18, s29 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill @@ -33543,8 +32937,8 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v2 ; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v0 -; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v16 -; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v15 +; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v18 +; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v17 ; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v20 ; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v19 ; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v24 @@ -33553,8 +32947,8 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v30 ; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v14 ; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v13 -; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v18 -; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v17 +; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v16 +; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v15 ; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v22 ; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v21 ; GFX9-NEXT: s_cbranch_execnz .LBB49_3 @@ -33565,12 +32959,12 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 ; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 ; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 -; GFX9-NEXT: v_add_f64 v[15:16], v[15:16], 1.0 +; GFX9-NEXT: v_add_f64 v[17:18], v[17:18], 1.0 ; GFX9-NEXT: v_add_f64 v[19:20], v[19:20], 1.0 ; GFX9-NEXT: v_add_f64 v[23:24], v[23:24], 1.0 ; GFX9-NEXT: v_add_f64 v[30:31], v[30:31], 1.0 ; GFX9-NEXT: v_add_f64 v[13:14], v[13:14], 1.0 -; GFX9-NEXT: v_add_f64 v[17:18], v[17:18], 1.0 +; GFX9-NEXT: v_add_f64 v[15:16], v[15:16], 1.0 ; GFX9-NEXT: v_add_f64 v[21:22], v[21:22], 1.0 ; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v11 ; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v10 @@ -33584,8 +32978,8 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v2 ; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v0 -; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v16 -; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v15 +; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v18 +; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v17 ; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v20 ; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v19 ; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v24 @@ -33594,8 +32988,8 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v30 ; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v14 ; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v13 -; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v18 -; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v17 +; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v16 +; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v15 ; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v22 ; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v21 ; GFX9-NEXT: .LBB49_3: ; %end @@ -33615,9 +33009,9 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; GFX9-NEXT: v_lshl_or_b32 v34, v34, 16, v13 ; GFX9-NEXT: v_and_b32_e32 v13, 0xffff, v20 ; GFX9-NEXT: v_lshl_or_b32 v35, v35, 16, v13 -; GFX9-NEXT: v_and_b32_e32 v13, 0xffff, v15 +; GFX9-NEXT: v_and_b32_e32 v13, 0xffff, v17 ; GFX9-NEXT: v_lshl_or_b32 v12, v12, 16, v13 -; GFX9-NEXT: v_and_b32_e32 v13, 0xffff, v16 +; GFX9-NEXT: v_and_b32_e32 v13, 0xffff, v18 ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX9-NEXT: v_lshl_or_b32 v13, v41, 16, v13 ; GFX9-NEXT: v_lshl_or_b32 v14, v40, 16, v0 @@ -33625,15 +33019,15 @@ define inreg <52 x i16> @bitcast_v13f64_to_v52i16_scalar(<13 x double> inreg %a, ; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload +; GFX9-NEXT: v_and_b32_e32 v15, 0xffff, v15 +; GFX9-NEXT: v_lshl_or_b32 v26, v26, 16, v15 +; GFX9-NEXT: v_and_b32_e32 v15, 0xffff, v16 ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v1 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff, v17 +; GFX9-NEXT: v_lshl_or_b32 v27, v27, 16, v15 ; GFX9-NEXT: v_lshl_or_b32 v15, v55, 16, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v2 -; GFX9-NEXT: v_lshl_or_b32 v26, v26, 16, v17 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff, v18 ; GFX9-NEXT: v_lshl_or_b32 v16, v54, 16, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v3 -; GFX9-NEXT: v_lshl_or_b32 v27, v27, 16, v17 ; GFX9-NEXT: v_lshl_or_b32 v17, v53, 16, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v4 ; GFX9-NEXT: v_lshl_or_b32 v18, v52, 16, v0 @@ -34053,6 +33447,19 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) { ; SI-LABEL: bitcast_v52i16_to_v13f64: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v50, v10 +; SI-NEXT: v_mov_b32_e32 v51, v8 +; SI-NEXT: v_mov_b32_e32 v52, v6 +; SI-NEXT: v_mov_b32_e32 v53, v4 +; SI-NEXT: v_mov_b32_e32 v54, v2 +; SI-NEXT: v_mov_b32_e32 v55, v0 +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:48 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:40 +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24 +; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:16 +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:12 +; SI-NEXT: v_mov_b32_e32 v49, v12 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill @@ -34078,19 +33485,6 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v50, v10 -; SI-NEXT: v_mov_b32_e32 v51, v8 -; SI-NEXT: v_mov_b32_e32 v52, v6 -; SI-NEXT: v_mov_b32_e32 v53, v4 -; SI-NEXT: v_mov_b32_e32 v54, v2 -; SI-NEXT: v_mov_b32_e32 v55, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:48 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:40 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32 -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24 -; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:16 -; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:12 -; SI-NEXT: v_mov_b32_e32 v49, v12 ; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v1 ; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v3 ; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v5 @@ -34106,17 +33500,12 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) { ; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v25 ; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v27 ; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v29 -; SI-NEXT: s_waitcnt vmcnt(5) +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v0 -; SI-NEXT: s_waitcnt vmcnt(4) ; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v2 -; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v4 -; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v6 -; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v8 -; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:8 @@ -34141,9 +33530,10 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) { ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72 ; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:68 -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v18 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 @@ -34155,10 +33545,9 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) { ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:56 ; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:52 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v22 ; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v22 +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:44 @@ -34478,7 +33867,7 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) { ; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v21 ; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v22 ; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v23 -; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v24 +; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v24 ; SI-NEXT: v_add_i32_e32 v25, vcc, 0x30000, v25 ; SI-NEXT: .LBB50_4: ; %end ; SI-NEXT: s_or_b64 exec, exec, s[4:5] @@ -34744,7 +34133,6 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v57, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v25 -; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v24 @@ -34811,6 +34199,7 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v56 ; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v57 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 +; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -34943,6 +34332,9 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] ; GFX9-NEXT: s_cbranch_execz .LBB50_4 ; GFX9-NEXT: ; %bb.3: ; %cmp.true +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload @@ -34957,9 +34349,6 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v34, v57, s6 ; GFX9-NEXT: v_perm_b32 v1, v62, v56, s6 ; GFX9-NEXT: v_perm_b32 v2, v33, v47, s6 @@ -34978,6 +34367,10 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0] +; GFX9-NEXT: s_waitcnt vmcnt(14) +; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; GFX9-NEXT: s_waitcnt vmcnt(15) ; GFX9-NEXT: v_perm_b32 v9, v9, v40, s6 ; GFX9-NEXT: s_waitcnt vmcnt(14) @@ -35006,10 +34399,6 @@ define <13 x double> @bitcast_v52i16_to_v13f64(<52 x i16> %a, i32 %b) { ; GFX9-NEXT: v_perm_b32 v21, v21, v36, s6 ; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: v_perm_b32 v22, v22, v35, s6 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0] @@ -35999,294 +35388,109 @@ define inreg <13 x double> @bitcast_v52i16_to_v13f64_scalar(<52 x i16> inreg %a, ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v191, v1 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v185, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB51_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB51_3 ; GFX11-TRUE16-NEXT: .LBB51_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s40, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s41, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v185, v185, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v191, v191, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v190, v190, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v189, v189, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v188, v188, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v187, v187, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v186, v186, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, s6, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, s7, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, s8, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s9, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, s10, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, s11, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, s12, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, s13, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s14, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, s15, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, s16, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s0, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s1, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s2, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, s3, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, s4, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v35, s5, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v44, s6, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v54, s7, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v65, s8, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v77, s9, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v90, s10, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v104, s11, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v119, s12, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v135, s13, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v152, s14, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v170, s15, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: .LBB51_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v170 :: v_dual_mov_b32 v18, v185 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v191 :: v_dual_mov_b32 v20, v190 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v189 :: v_dual_mov_b32 v22, v188 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v187 :: v_dual_mov_b32 v24, v186 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v191, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v190, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v189, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v188, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v187, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:316 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v14, v119 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB51_4: -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v53, v25 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v25, v53 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB51_2 ; ; GFX11-FAKE16-LABEL: bitcast_v52i16_to_v13f64_scalar: @@ -37467,19 +36671,21 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v13 -; SI-NEXT: v_readfirstlane_b32 s14, v1 -; SI-NEXT: v_readfirstlane_b32 s15, v2 -; SI-NEXT: v_readfirstlane_b32 s12, v3 -; SI-NEXT: v_readfirstlane_b32 s13, v4 -; SI-NEXT: v_readfirstlane_b32 s10, v5 -; SI-NEXT: v_readfirstlane_b32 s11, v6 -; SI-NEXT: v_readfirstlane_b32 s8, v7 -; SI-NEXT: v_readfirstlane_b32 s9, v8 -; SI-NEXT: v_readfirstlane_b32 s6, v9 -; SI-NEXT: v_readfirstlane_b32 s7, v10 -; SI-NEXT: v_readfirstlane_b32 s4, v11 -; SI-NEXT: s_and_b64 s[40:41], vcc, exec -; SI-NEXT: v_readfirstlane_b32 s5, v12 +; SI-NEXT: v_mov_b32_e32 v25, s16 +; SI-NEXT: v_mov_b32_e32 v26, s17 +; SI-NEXT: v_mov_b32_e32 v21, s18 +; SI-NEXT: v_mov_b32_e32 v22, s19 +; SI-NEXT: v_mov_b32_e32 v17, s20 +; SI-NEXT: v_mov_b32_e32 v18, s21 +; SI-NEXT: v_mov_b32_e32 v23, s22 +; SI-NEXT: v_mov_b32_e32 v24, s23 +; SI-NEXT: v_mov_b32_e32 v19, s24 +; SI-NEXT: v_mov_b32_e32 v20, s25 +; SI-NEXT: v_mov_b32_e32 v15, s26 +; SI-NEXT: v_mov_b32_e32 v16, s27 +; SI-NEXT: s_and_b64 s[4:5], vcc, exec +; SI-NEXT: v_mov_b32_e32 v13, s28 +; SI-NEXT: v_mov_b32_e32 v14, s29 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -37498,362 +36704,440 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB53_4 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: s_lshr_b32 s40, s5, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v1, s40 -; SI-NEXT: s_lshr_b32 s40, s4, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v2, s40 -; SI-NEXT: s_lshr_b32 s40, s7, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v6, s40 -; SI-NEXT: s_lshr_b32 s40, s6, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v5, s40 -; SI-NEXT: s_lshr_b32 s40, s9, 16 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v63, s40 -; SI-NEXT: s_lshr_b32 s40, s8, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v9, s40 -; SI-NEXT: s_lshr_b32 s40, s11, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v62, s40 -; SI-NEXT: s_lshr_b32 s40, s10, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v14, s40 -; SI-NEXT: s_lshr_b32 s40, s13, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v16, s40 -; SI-NEXT: s_lshr_b32 s40, s12, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v18, s40 -; SI-NEXT: s_lshr_b32 s40, s15, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v20, s40 -; SI-NEXT: s_lshr_b32 s40, s14, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v22, s40 -; SI-NEXT: s_lshr_b32 s40, s29, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v24, s40 -; SI-NEXT: s_lshr_b32 s40, s28, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v26, s40 -; SI-NEXT: s_lshr_b32 s40, s27, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v28, s40 -; SI-NEXT: s_lshr_b32 s40, s26, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v31, s40 -; SI-NEXT: s_lshr_b32 s40, s25, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v33, s40 -; SI-NEXT: s_lshr_b32 s40, s24, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v35, s40 -; SI-NEXT: s_lshr_b32 s40, s23, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v37, s40 -; SI-NEXT: s_lshr_b32 s40, s22, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v39, s40 -; SI-NEXT: s_lshr_b32 s40, s21, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v49, s40 -; SI-NEXT: s_lshr_b32 s40, s20, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v51, s40 -; SI-NEXT: s_lshr_b32 s40, s19, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v54, s40 -; SI-NEXT: s_lshr_b32 s40, s18, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v40, s40 -; SI-NEXT: s_lshr_b32 s40, s17, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v42, s40 -; SI-NEXT: s_lshr_b32 s40, s16, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v44, s40 -; SI-NEXT: v_cvt_f32_f16_e32 v45, s5 -; SI-NEXT: v_cvt_f32_f16_e32 v17, s4 -; SI-NEXT: v_cvt_f32_f16_e32 v21, s7 -; SI-NEXT: v_cvt_f32_f16_e32 v25, s6 -; SI-NEXT: v_cvt_f32_f16_e32 v12, s9 -; SI-NEXT: v_cvt_f32_f16_e32 v3, s8 -; SI-NEXT: v_cvt_f32_f16_e32 v15, s11 -; SI-NEXT: v_cvt_f32_f16_e32 v7, s10 -; SI-NEXT: v_cvt_f32_f16_e32 v19, s13 -; SI-NEXT: v_cvt_f32_f16_e32 v8, s12 -; SI-NEXT: v_cvt_f32_f16_e32 v23, s15 -; SI-NEXT: v_cvt_f32_f16_e32 v4, s14 -; SI-NEXT: v_cvt_f32_f16_e32 v27, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v11, s28 -; SI-NEXT: v_cvt_f32_f16_e32 v30, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v32, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v34, s25 -; SI-NEXT: v_cvt_f32_f16_e32 v36, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v38, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v48, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v50, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v52, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v53, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v55, s18 -; SI-NEXT: v_cvt_f32_f16_e32 v41, s17 -; SI-NEXT: v_cvt_f32_f16_e32 v43, s16 -; SI-NEXT: s_cbranch_execnz .LBB53_3 -; SI-NEXT: .LBB53_2: ; %cmp.true -; SI-NEXT: v_add_f64 v[1:2], s[16:17], 1.0 -; SI-NEXT: v_add_f64 v[54:55], s[18:19], 1.0 -; SI-NEXT: v_add_f64 v[49:50], s[20:21], 1.0 -; SI-NEXT: v_add_f64 v[37:38], s[22:23], 1.0 -; SI-NEXT: v_add_f64 v[33:34], s[24:25], 1.0 -; SI-NEXT: v_add_f64 v[31:32], s[26:27], 1.0 -; SI-NEXT: v_add_f64 v[26:27], s[28:29], 1.0 -; SI-NEXT: v_add_f64 v[22:23], s[14:15], 1.0 -; SI-NEXT: v_add_f64 v[18:19], s[12:13], 1.0 -; SI-NEXT: v_add_f64 v[14:15], s[10:11], 1.0 -; SI-NEXT: v_add_f64 v[11:12], s[8:9], 1.0 -; SI-NEXT: v_add_f64 v[7:8], s[6:7], 1.0 -; SI-NEXT: v_add_f64 v[3:4], s[4:5], 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v1 -; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v2 -; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v54 -; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v55 -; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v49 -; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v50 -; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v37 -; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v38 -; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v33 -; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v34 -; SI-NEXT: s_waitcnt expcnt(6) -; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v31 -; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v32 -; SI-NEXT: s_waitcnt expcnt(5) -; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v26 -; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v27 -; SI-NEXT: s_waitcnt expcnt(4) -; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v22 -; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v23 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v12 ; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v18 -; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v19 -; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v14 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v15 -; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v11 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v12 -; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v7 -; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v8 -; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v3 -; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v4 -; SI-NEXT: v_cvt_f32_f16_e32 v45, v4 -; SI-NEXT: v_cvt_f32_f16_e32 v17, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v21, v8 -; SI-NEXT: v_cvt_f32_f16_e32 v25, v7 -; SI-NEXT: v_cvt_f32_f16_e32 v12, v12 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v11 -; SI-NEXT: v_cvt_f32_f16_e32 v15, v15 -; SI-NEXT: v_cvt_f32_f16_e32 v7, v14 -; SI-NEXT: v_cvt_f32_f16_e32 v19, v19 -; SI-NEXT: v_cvt_f32_f16_e32 v8, v18 -; SI-NEXT: v_cvt_f32_f16_e32 v23, v23 -; SI-NEXT: v_cvt_f32_f16_e32 v4, v22 +; SI-NEXT: v_cvt_f32_f16_e32 v60, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v11 +; SI-NEXT: v_cvt_f32_f16_e32 v58, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v10 +; SI-NEXT: v_cvt_f32_f16_e32 v56, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v9 +; SI-NEXT: v_cvt_f32_f16_e32 v46, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v8 +; SI-NEXT: v_cvt_f32_f16_e32 v45, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v7 ; SI-NEXT: v_cvt_f32_f16_e32 v27, v27 -; SI-NEXT: v_cvt_f32_f16_e32 v11, v26 -; SI-NEXT: v_cvt_f32_f16_e32 v30, v32 -; SI-NEXT: v_cvt_f32_f16_e32 v32, v31 -; SI-NEXT: v_cvt_f32_f16_e32 v34, v34 -; SI-NEXT: v_cvt_f32_f16_e32 v36, v33 -; SI-NEXT: v_cvt_f32_f16_e32 v38, v38 -; SI-NEXT: v_cvt_f32_f16_e32 v48, v37 -; SI-NEXT: v_cvt_f32_f16_e32 v50, v50 -; SI-NEXT: v_cvt_f32_f16_e32 v52, v49 -; SI-NEXT: v_cvt_f32_f16_e32 v53, v55 -; SI-NEXT: v_cvt_f32_f16_e32 v55, v54 -; SI-NEXT: v_cvt_f32_f16_e32 v41, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v43, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v51, v12 +; SI-NEXT: v_cvt_f32_f16_e32 v41, v11 +; SI-NEXT: v_cvt_f32_f16_e32 v43, v10 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v6 +; SI-NEXT: v_cvt_f32_f16_e32 v27, v27 +; SI-NEXT: v_cvt_f32_f16_e32 v62, v15 +; SI-NEXT: v_cvt_f32_f16_e32 v29, v19 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v27, v27 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v24 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v23 +; SI-NEXT: v_cvt_f32_f16_e32 v34, v18 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v50, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v52, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v53, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v54, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v14 +; SI-NEXT: v_cvt_f32_f16_e32 v55, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v13 +; SI-NEXT: v_cvt_f32_f16_e32 v40, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v16 +; SI-NEXT: v_cvt_f32_f16_e32 v42, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v15 +; SI-NEXT: v_cvt_f32_f16_e32 v44, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v20 +; SI-NEXT: v_cvt_f32_f16_e32 v47, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v19 +; SI-NEXT: v_cvt_f32_f16_e32 v57, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v24 +; SI-NEXT: v_cvt_f32_f16_e32 v59, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v23 +; SI-NEXT: v_cvt_f32_f16_e32 v61, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v18 +; SI-NEXT: v_cvt_f32_f16_e32 v63, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v17 +; SI-NEXT: v_cvt_f32_f16_e32 v28, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v22 +; SI-NEXT: v_cvt_f32_f16_e32 v30, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v21 +; SI-NEXT: v_cvt_f32_f16_e32 v32, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v26 +; SI-NEXT: v_cvt_f32_f16_e32 v35, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v25 +; SI-NEXT: v_cvt_f32_f16_e32 v37, v27 +; SI-NEXT: v_cvt_f32_f16_e32 v27, v9 +; SI-NEXT: v_cvt_f32_f16_e32 v36, v17 +; SI-NEXT: v_cvt_f32_f16_e32 v38, v22 +; SI-NEXT: v_cvt_f32_f16_e32 v39, v21 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v27, v8 +; SI-NEXT: v_cvt_f32_f16_e32 v48, v26 +; SI-NEXT: v_cvt_f32_f16_e32 v49, v25 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v27, v7 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v27, v6 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v27, v5 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v27, v4 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v27, v3 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v27, v2 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v27, v1 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v27, v14 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v27, v13 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v27, v16 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v27, v20 +; SI-NEXT: s_cbranch_execnz .LBB53_3 +; SI-NEXT: .LBB53_2: ; %cmp.true +; SI-NEXT: v_add_f64 v[1:2], v[1:2], 1.0 +; SI-NEXT: v_add_f64 v[13:14], v[13:14], 1.0 +; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 +; SI-NEXT: v_add_f64 v[15:16], v[15:16], 1.0 +; SI-NEXT: v_add_f64 v[7:8], v[7:8], 1.0 +; SI-NEXT: v_add_f64 v[5:6], v[5:6], 1.0 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v14 +; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v7 +; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v6 +; SI-NEXT: v_add_f64 v[25:26], v[25:26], 1.0 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f32_f16_e32 v1, v13 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v10 +; SI-NEXT: v_add_f64 v[21:22], v[21:22], 1.0 +; SI-NEXT: v_add_f64 v[17:18], v[17:18], 1.0 +; SI-NEXT: v_add_f64 v[23:24], v[23:24], 1.0 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v16 +; SI-NEXT: v_add_f64 v[19:20], v[19:20], 1.0 +; SI-NEXT: v_add_f64 v[3:4], v[3:4], 1.0 +; SI-NEXT: v_add_f64 v[9:10], v[9:10], 1.0 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v43 +; SI-NEXT: v_add_f64 v[11:12], v[11:12], 1.0 +; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v25 +; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v26 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v41 +; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v21 +; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v22 +; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v17 +; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v18 +; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v23 +; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v24 +; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v19 +; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v20 +; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v15 +; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v16 +; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v13 +; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v14 +; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v2 +; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v3 +; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v4 +; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v5 +; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v8 +; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v9 +; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v10 +; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v11 +; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v12 +; SI-NEXT: v_cvt_f32_f16_e32 v12, v12 +; SI-NEXT: v_cvt_f32_f16_e32 v11, v11 +; SI-NEXT: v_cvt_f32_f16_e32 v10, v10 +; SI-NEXT: v_cvt_f32_f16_e32 v9, v9 +; SI-NEXT: v_cvt_f32_f16_e32 v8, v8 +; SI-NEXT: v_cvt_f32_f16_e32 v7, v7 ; SI-NEXT: v_cvt_f32_f16_e32 v6, v6 ; SI-NEXT: v_cvt_f32_f16_e32 v5, v5 -; SI-NEXT: v_cvt_f32_f16_e32 v63, v63 -; SI-NEXT: v_cvt_f32_f16_e32 v9, v9 -; SI-NEXT: v_cvt_f32_f16_e32 v62, v62 -; SI-NEXT: v_cvt_f32_f16_e32 v14, v61 -; SI-NEXT: v_cvt_f32_f16_e32 v16, v16 -; SI-NEXT: v_cvt_f32_f16_e32 v18, v60 -; SI-NEXT: v_cvt_f32_f16_e32 v20, v20 -; SI-NEXT: v_cvt_f32_f16_e32 v22, v59 -; SI-NEXT: v_cvt_f32_f16_e32 v24, v24 -; SI-NEXT: v_cvt_f32_f16_e32 v26, v58 -; SI-NEXT: v_cvt_f32_f16_e32 v28, v28 -; SI-NEXT: v_cvt_f32_f16_e32 v31, v57 -; SI-NEXT: v_cvt_f32_f16_e32 v33, v56 -; SI-NEXT: v_cvt_f32_f16_e32 v35, v35 -; SI-NEXT: v_cvt_f32_f16_e32 v37, v47 -; SI-NEXT: v_cvt_f32_f16_e32 v39, v39 -; SI-NEXT: v_cvt_f32_f16_e32 v49, v46 -; SI-NEXT: v_cvt_f32_f16_e32 v51, v51 -; SI-NEXT: v_cvt_f32_f16_e32 v54, v29 +; SI-NEXT: v_cvt_f32_f16_e32 v4, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v62, v15 +; SI-NEXT: v_cvt_f32_f16_e32 v27, v20 +; SI-NEXT: v_cvt_f32_f16_e32 v29, v19 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v24 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v23 +; SI-NEXT: v_cvt_f32_f16_e32 v34, v18 +; SI-NEXT: v_cvt_f32_f16_e32 v36, v17 +; SI-NEXT: v_cvt_f32_f16_e32 v38, v22 +; SI-NEXT: v_cvt_f32_f16_e32 v39, v21 +; SI-NEXT: v_cvt_f32_f16_e32 v48, v26 +; SI-NEXT: v_cvt_f32_f16_e32 v49, v25 +; SI-NEXT: v_cvt_f32_f16_e32 v60, v60 +; SI-NEXT: v_cvt_f32_f16_e32 v58, v58 +; SI-NEXT: v_cvt_f32_f16_e32 v56, v56 +; SI-NEXT: v_cvt_f32_f16_e32 v46, v46 +; SI-NEXT: v_cvt_f32_f16_e32 v45, v45 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v51 +; SI-NEXT: v_cvt_f32_f16_e32 v50, v50 +; SI-NEXT: v_cvt_f32_f16_e32 v52, v52 +; SI-NEXT: v_cvt_f32_f16_e32 v53, v53 +; SI-NEXT: v_cvt_f32_f16_e32 v54, v54 +; SI-NEXT: v_cvt_f32_f16_e32 v55, v55 ; SI-NEXT: v_cvt_f32_f16_e32 v40, v40 ; SI-NEXT: v_cvt_f32_f16_e32 v42, v42 ; SI-NEXT: v_cvt_f32_f16_e32 v44, v44 +; SI-NEXT: v_cvt_f32_f16_e32 v47, v47 +; SI-NEXT: v_cvt_f32_f16_e32 v57, v57 +; SI-NEXT: v_cvt_f32_f16_e32 v59, v59 +; SI-NEXT: v_cvt_f32_f16_e32 v61, v61 +; SI-NEXT: v_cvt_f32_f16_e32 v63, v63 +; SI-NEXT: v_cvt_f32_f16_e32 v28, v28 +; SI-NEXT: v_cvt_f32_f16_e32 v30, v30 +; SI-NEXT: v_cvt_f32_f16_e32 v32, v32 +; SI-NEXT: v_cvt_f32_f16_e32 v35, v35 +; SI-NEXT: v_cvt_f32_f16_e32 v37, v37 +; SI-NEXT: v_mov_b32_e32 v43, v10 +; SI-NEXT: v_mov_b32_e32 v41, v11 +; SI-NEXT: v_mov_b32_e32 v51, v12 +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill ; SI-NEXT: .LBB53_3: ; %end -; SI-NEXT: v_cvt_f16_f32_e32 v10, v44 -; SI-NEXT: v_cvt_f16_f32_e32 v13, v43 -; SI-NEXT: v_cvt_f16_f32_e32 v42, v42 -; SI-NEXT: v_cvt_f16_f32_e32 v41, v41 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v13, v10 -; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v42 -; SI-NEXT: buffer_store_dword v10, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v10, vcc, 4, v0 -; SI-NEXT: v_or_b32_e32 v13, v41, v13 -; SI-NEXT: buffer_store_dword v13, v10, s[0:3], 0 offen -; SI-NEXT: v_cvt_f16_f32_e32 v10, v40 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v37 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v49 +; SI-NEXT: v_cvt_f16_f32_e32 v3, v35 +; SI-NEXT: v_cvt_f16_f32_e32 v4, v48 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3 +; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v13, v55 -; SI-NEXT: v_add_i32_e32 v55, vcc, 8, v0 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v13, v10 -; SI-NEXT: buffer_store_dword v10, v55, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0 +; SI-NEXT: v_or_b32_e32 v2, v4, v2 +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v32 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v10, v54 -; SI-NEXT: v_cvt_f16_f32_e32 v13, v53 -; SI-NEXT: v_add_i32_e32 v53, vcc, 12, v0 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v13, v10 -; SI-NEXT: buffer_store_dword v10, v53, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v2, v39 +; SI-NEXT: v_add_i32_e32 v3, vcc, 8, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v10, v51 -; SI-NEXT: v_cvt_f16_f32_e32 v13, v52 -; SI-NEXT: v_add_i32_e32 v51, vcc, 16, v0 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v13, v10 -; SI-NEXT: buffer_store_dword v10, v51, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v30 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v38 +; SI-NEXT: v_add_i32_e32 v3, vcc, 12, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v10, v49 -; SI-NEXT: v_cvt_f16_f32_e32 v13, v50 -; SI-NEXT: v_add_i32_e32 v49, vcc, 20, v0 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v13, v10 -; SI-NEXT: buffer_store_dword v10, v49, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v28 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v36 +; SI-NEXT: v_add_i32_e32 v3, vcc, 16, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v10, v39 -; SI-NEXT: v_cvt_f16_f32_e32 v13, v48 -; SI-NEXT: v_add_i32_e32 v39, vcc, 24, v0 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v13, v10 -; SI-NEXT: buffer_store_dword v10, v39, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v63 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v34 +; SI-NEXT: v_add_i32_e32 v3, vcc, 20, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v10, v37 -; SI-NEXT: v_cvt_f16_f32_e32 v13, v38 -; SI-NEXT: v_add_i32_e32 v37, vcc, 28, v0 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v13, v10 -; SI-NEXT: buffer_store_dword v10, v37, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v61 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v33 +; SI-NEXT: v_add_i32_e32 v3, vcc, 24, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v10, v35 -; SI-NEXT: v_cvt_f16_f32_e32 v13, v36 -; SI-NEXT: v_add_i32_e32 v35, vcc, 32, v0 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v13, v10 -; SI-NEXT: buffer_store_dword v10, v35, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v59 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v31 +; SI-NEXT: v_add_i32_e32 v3, vcc, 28, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v10, v33 -; SI-NEXT: v_cvt_f16_f32_e32 v13, v34 -; SI-NEXT: v_add_i32_e32 v33, vcc, 36, v0 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v13, v10 -; SI-NEXT: buffer_store_dword v10, v33, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v57 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v29 +; SI-NEXT: v_add_i32_e32 v3, vcc, 32, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v10, v31 -; SI-NEXT: v_cvt_f16_f32_e32 v13, v32 -; SI-NEXT: v_add_i32_e32 v31, vcc, 40, v0 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v13, v10 -; SI-NEXT: buffer_store_dword v10, v31, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v47 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v27 +; SI-NEXT: v_add_i32_e32 v3, vcc, 36, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v10, v28 -; SI-NEXT: v_cvt_f16_f32_e32 v13, v30 -; SI-NEXT: v_add_i32_e32 v28, vcc, 44, v0 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v13, v10 -; SI-NEXT: buffer_store_dword v10, v28, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v44 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v62 +; SI-NEXT: v_add_i32_e32 v3, vcc, 40, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v10, v26 -; SI-NEXT: v_cvt_f16_f32_e32 v13, v11 -; SI-NEXT: v_add_i32_e32 v26, vcc, 48, v0 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v13, v10 -; SI-NEXT: buffer_store_dword v10, v26, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v42 +; SI-NEXT: v_add_i32_e32 v3, vcc, 44, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v10, v24 -; SI-NEXT: v_cvt_f16_f32_e32 v13, v27 -; SI-NEXT: v_add_i32_e32 v24, vcc, 52, v0 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v13, v10 -; SI-NEXT: buffer_store_dword v10, v24, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v40 +; SI-NEXT: v_add_i32_e32 v3, vcc, 48, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v10, v22 -; SI-NEXT: v_cvt_f16_f32_e32 v13, v4 -; SI-NEXT: v_add_i32_e32 v22, vcc, 56, v0 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v13, v10 -; SI-NEXT: buffer_store_dword v10, v22, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v55 +; SI-NEXT: v_add_i32_e32 v3, vcc, 52, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v10, v20 -; SI-NEXT: v_cvt_f16_f32_e32 v13, v23 -; SI-NEXT: v_add_i32_e32 v20, vcc, 60, v0 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v13, v10 -; SI-NEXT: buffer_store_dword v10, v20, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v54 +; SI-NEXT: v_add_i32_e32 v3, vcc, 56, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v10, v18 -; SI-NEXT: v_cvt_f16_f32_e32 v13, v8 -; SI-NEXT: v_add_i32_e32 v18, vcc, 64, v0 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v13, v10 -; SI-NEXT: buffer_store_dword v10, v18, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v53 +; SI-NEXT: v_add_i32_e32 v3, vcc, 60, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v10, v16 -; SI-NEXT: v_cvt_f16_f32_e32 v13, v19 -; SI-NEXT: v_add_i32_e32 v16, vcc, 0x44, v0 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v13, v10 -; SI-NEXT: buffer_store_dword v10, v16, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v52 +; SI-NEXT: v_add_i32_e32 v3, vcc, 64, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v10, v14 -; SI-NEXT: v_cvt_f16_f32_e32 v13, v7 -; SI-NEXT: v_add_i32_e32 v14, vcc, 0x48, v0 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v13, v10 -; SI-NEXT: buffer_store_dword v10, v14, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v50 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x44, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v10, v62 -; SI-NEXT: v_cvt_f16_f32_e32 v11, v15 -; SI-NEXT: v_cvt_f16_f32_e32 v9, v9 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_add_i32_e32 v13, vcc, 0x4c, v0 -; SI-NEXT: v_or_b32_e32 v10, v11, v10 -; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; SI-NEXT: buffer_store_dword v10, v13, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x48, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v10, vcc, 0x50, v0 -; SI-NEXT: v_or_b32_e32 v3, v3, v9 -; SI-NEXT: buffer_store_dword v3, v10, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x4c, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v63 -; SI-NEXT: v_cvt_f16_f32_e32 v7, v12 -; SI-NEXT: v_add_i32_e32 v9, vcc, 0x54, v0 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_or_b32_e32 v3, v7, v3 -; SI-NEXT: buffer_store_dword v3, v9, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x50, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v5 -; SI-NEXT: v_cvt_f16_f32_e32 v4, v25 -; SI-NEXT: v_add_i32_e32 v5, vcc, 0x58, v0 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_or_b32_e32 v3, v4, v3 -; SI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v45 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x54, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v6 -; SI-NEXT: v_cvt_f16_f32_e32 v4, v21 -; SI-NEXT: v_add_i32_e32 v5, vcc, 0x5c, v0 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_or_b32_e32 v3, v4, v3 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v46 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x58, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v17 -; SI-NEXT: v_add_i32_e32 v4, vcc, 0x60, v0 -; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; SI-NEXT: v_or_b32_e32 v2, v3, v2 -; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 -; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v56 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v43 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x5c, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v2, v45 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v58 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v41 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x60, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v60 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v51 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x64, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 @@ -37877,58 +37161,73 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] ; SI-NEXT: .LBB53_4: -; SI-NEXT: ; implicit-def: $vgpr43 -; SI-NEXT: ; implicit-def: $vgpr44 -; SI-NEXT: ; implicit-def: $vgpr41 -; SI-NEXT: ; implicit-def: $vgpr42 -; SI-NEXT: ; implicit-def: $vgpr55 -; SI-NEXT: ; implicit-def: $vgpr40 -; SI-NEXT: ; implicit-def: $vgpr53 -; SI-NEXT: ; implicit-def: $vgpr54 -; SI-NEXT: ; implicit-def: $vgpr52 ; SI-NEXT: ; implicit-def: $vgpr51 ; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; kill: killed $vgpr51 +; SI-NEXT: ; kill: killed $vgpr50 +; SI-NEXT: ; implicit-def: $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; kill: killed $vgpr51 +; SI-NEXT: ; kill: killed $vgpr50 ; SI-NEXT: ; implicit-def: $vgpr49 +; SI-NEXT: ; implicit-def: $vgpr37 ; SI-NEXT: ; implicit-def: $vgpr48 +; SI-NEXT: ; implicit-def: $vgpr35 ; SI-NEXT: ; implicit-def: $vgpr39 +; SI-NEXT: ; implicit-def: $vgpr32 ; SI-NEXT: ; implicit-def: $vgpr38 -; SI-NEXT: ; implicit-def: $vgpr37 +; SI-NEXT: ; implicit-def: $vgpr30 ; SI-NEXT: ; implicit-def: $vgpr36 -; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr28 ; SI-NEXT: ; implicit-def: $vgpr34 +; SI-NEXT: ; implicit-def: $vgpr63 ; SI-NEXT: ; implicit-def: $vgpr33 -; SI-NEXT: ; implicit-def: $vgpr32 +; SI-NEXT: ; implicit-def: $vgpr61 ; SI-NEXT: ; implicit-def: $vgpr31 -; SI-NEXT: ; implicit-def: $vgpr30 -; SI-NEXT: ; implicit-def: $vgpr28 -; SI-NEXT: ; implicit-def: $vgpr11 -; SI-NEXT: ; implicit-def: $vgpr26 +; SI-NEXT: ; implicit-def: $vgpr59 +; SI-NEXT: ; implicit-def: $vgpr29 +; SI-NEXT: ; implicit-def: $vgpr57 ; SI-NEXT: ; implicit-def: $vgpr27 -; SI-NEXT: ; implicit-def: $vgpr24 -; SI-NEXT: ; implicit-def: $vgpr4 -; SI-NEXT: ; implicit-def: $vgpr22 -; SI-NEXT: ; implicit-def: $vgpr23 -; SI-NEXT: ; implicit-def: $vgpr20 -; SI-NEXT: ; implicit-def: $vgpr8 -; SI-NEXT: ; implicit-def: $vgpr18 -; SI-NEXT: ; implicit-def: $vgpr19 -; SI-NEXT: ; implicit-def: $vgpr16 -; SI-NEXT: ; implicit-def: $vgpr7 -; SI-NEXT: ; implicit-def: $vgpr14 -; SI-NEXT: ; implicit-def: $vgpr15 +; SI-NEXT: ; implicit-def: $vgpr47 ; SI-NEXT: ; implicit-def: $vgpr62 -; SI-NEXT: ; implicit-def: $vgpr3 -; SI-NEXT: ; implicit-def: $vgpr9 -; SI-NEXT: ; implicit-def: $vgpr12 -; SI-NEXT: ; implicit-def: $vgpr63 -; SI-NEXT: ; implicit-def: $vgpr25 -; SI-NEXT: ; implicit-def: $vgpr5 -; SI-NEXT: ; implicit-def: $vgpr21 -; SI-NEXT: ; implicit-def: $vgpr6 -; SI-NEXT: ; implicit-def: $vgpr17 -; SI-NEXT: ; implicit-def: $vgpr2 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr42 +; SI-NEXT: ; implicit-def: $vgpr40 +; SI-NEXT: ; implicit-def: $vgpr55 +; SI-NEXT: ; implicit-def: $vgpr54 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr52 ; SI-NEXT: ; implicit-def: $vgpr45 -; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: ; implicit-def: $vgpr46 +; SI-NEXT: ; implicit-def: $vgpr43 +; SI-NEXT: ; implicit-def: $vgpr56 +; SI-NEXT: ; implicit-def: $vgpr41 +; SI-NEXT: ; implicit-def: $vgpr58 +; SI-NEXT: ; implicit-def: $vgpr60 +; SI-NEXT: ; implicit-def: $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; kill: killed $vgpr51 +; SI-NEXT: ; kill: killed $vgpr50 +; SI-NEXT: ; implicit-def: $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; kill: killed $vgpr51 +; SI-NEXT: ; kill: killed $vgpr50 +; SI-NEXT: ; implicit-def: $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; kill: killed $vgpr51 +; SI-NEXT: ; kill: killed $vgpr50 +; SI-NEXT: ; implicit-def: $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; kill: killed $vgpr51 +; SI-NEXT: ; kill: killed $vgpr50 +; SI-NEXT: ; implicit-def: $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; kill: killed $vgpr51 +; SI-NEXT: ; kill: killed $vgpr50 +; SI-NEXT: ; implicit-def: $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; kill: killed $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr51 ; SI-NEXT: s_branch .LBB53_2 ; ; VI-LABEL: bitcast_v13f64_to_v52f16_scalar: @@ -37937,8 +37236,8 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; VI-NEXT: v_mov_b32_e32 v21, s16 ; VI-NEXT: v_mov_b32_e32 v22, s17 -; VI-NEXT: v_mov_b32_e32 v17, s18 -; VI-NEXT: v_mov_b32_e32 v18, s19 +; VI-NEXT: v_mov_b32_e32 v15, s18 +; VI-NEXT: v_mov_b32_e32 v16, s19 ; VI-NEXT: v_mov_b32_e32 v13, s20 ; VI-NEXT: v_mov_b32_e32 v14, s21 ; VI-NEXT: v_mov_b32_e32 v30, s22 @@ -37948,8 +37247,8 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; VI-NEXT: v_mov_b32_e32 v19, s26 ; VI-NEXT: v_mov_b32_e32 v20, s27 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec -; VI-NEXT: v_mov_b32_e32 v15, s28 -; VI-NEXT: v_mov_b32_e32 v16, s29 +; VI-NEXT: v_mov_b32_e32 v17, s28 +; VI-NEXT: v_mov_b32_e32 v18, s29 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill @@ -37968,8 +37267,8 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v2 ; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1 ; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v0 -; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v16 -; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v15 +; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v18 +; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v17 ; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v20 ; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v19 ; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v24 @@ -37978,8 +37277,8 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v30 ; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v14 ; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v13 -; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v18 -; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v17 +; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v16 +; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v15 ; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v22 ; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v21 ; VI-NEXT: s_cbranch_execnz .LBB53_3 @@ -37990,12 +37289,12 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 ; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 ; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 -; VI-NEXT: v_add_f64 v[15:16], v[15:16], 1.0 +; VI-NEXT: v_add_f64 v[17:18], v[17:18], 1.0 ; VI-NEXT: v_add_f64 v[19:20], v[19:20], 1.0 ; VI-NEXT: v_add_f64 v[23:24], v[23:24], 1.0 ; VI-NEXT: v_add_f64 v[30:31], v[30:31], 1.0 ; VI-NEXT: v_add_f64 v[13:14], v[13:14], 1.0 -; VI-NEXT: v_add_f64 v[17:18], v[17:18], 1.0 +; VI-NEXT: v_add_f64 v[15:16], v[15:16], 1.0 ; VI-NEXT: v_add_f64 v[21:22], v[21:22], 1.0 ; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v11 ; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v10 @@ -38009,8 +37308,8 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v2 ; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1 ; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v0 -; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v16 -; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v15 +; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v18 +; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v17 ; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v20 ; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v19 ; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v24 @@ -38019,8 +37318,8 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v30 ; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v14 ; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v13 -; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v18 -; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v17 +; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v16 +; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v15 ; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v22 ; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v21 ; VI-NEXT: .LBB53_3: ; %end @@ -38029,11 +37328,11 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v37 ; VI-NEXT: v_or_b32_sdwa v37, v22, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v26 -; VI-NEXT: v_or_b32_sdwa v26, v17, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v27 -; VI-NEXT: v_or_b32_sdwa v27, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v28 -; VI-NEXT: v_or_b32_sdwa v28, v13, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v26, v15, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v27 +; VI-NEXT: v_or_b32_sdwa v27, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v28 +; VI-NEXT: v_or_b32_sdwa v28, v13, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v29 ; VI-NEXT: v_or_b32_sdwa v29, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v43 @@ -38054,17 +37353,17 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12 ; VI-NEXT: v_or_b32_sdwa v14, v0, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v55 -; VI-NEXT: v_or_b32_sdwa v12, v15, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v15, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v54 -; VI-NEXT: v_or_b32_sdwa v13, v16, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12 ; VI-NEXT: v_or_b32_sdwa v16, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v53 +; VI-NEXT: v_or_b32_sdwa v12, v17, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v17, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v52 +; VI-NEXT: v_or_b32_sdwa v13, v18, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v18, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v51 ; VI-NEXT: v_or_b32_sdwa v19, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD @@ -38129,8 +37428,8 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX9-NEXT: v_mov_b32_e32 v21, s16 ; GFX9-NEXT: v_mov_b32_e32 v22, s17 -; GFX9-NEXT: v_mov_b32_e32 v17, s18 -; GFX9-NEXT: v_mov_b32_e32 v18, s19 +; GFX9-NEXT: v_mov_b32_e32 v15, s18 +; GFX9-NEXT: v_mov_b32_e32 v16, s19 ; GFX9-NEXT: v_mov_b32_e32 v13, s20 ; GFX9-NEXT: v_mov_b32_e32 v14, s21 ; GFX9-NEXT: v_mov_b32_e32 v30, s22 @@ -38140,8 +37439,8 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; GFX9-NEXT: v_mov_b32_e32 v19, s26 ; GFX9-NEXT: v_mov_b32_e32 v20, s27 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec -; GFX9-NEXT: v_mov_b32_e32 v15, s28 -; GFX9-NEXT: v_mov_b32_e32 v16, s29 +; GFX9-NEXT: v_mov_b32_e32 v17, s28 +; GFX9-NEXT: v_mov_b32_e32 v18, s29 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill @@ -38160,8 +37459,8 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v2 ; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v0 -; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v16 -; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v15 +; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v18 +; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v17 ; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v20 ; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v19 ; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v24 @@ -38170,8 +37469,8 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v30 ; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v14 ; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v13 -; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v18 -; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v17 +; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v16 +; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v15 ; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v22 ; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v21 ; GFX9-NEXT: s_cbranch_execnz .LBB53_3 @@ -38182,12 +37481,12 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0 ; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0 ; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 -; GFX9-NEXT: v_add_f64 v[15:16], v[15:16], 1.0 +; GFX9-NEXT: v_add_f64 v[17:18], v[17:18], 1.0 ; GFX9-NEXT: v_add_f64 v[19:20], v[19:20], 1.0 ; GFX9-NEXT: v_add_f64 v[23:24], v[23:24], 1.0 ; GFX9-NEXT: v_add_f64 v[30:31], v[30:31], 1.0 ; GFX9-NEXT: v_add_f64 v[13:14], v[13:14], 1.0 -; GFX9-NEXT: v_add_f64 v[17:18], v[17:18], 1.0 +; GFX9-NEXT: v_add_f64 v[15:16], v[15:16], 1.0 ; GFX9-NEXT: v_add_f64 v[21:22], v[21:22], 1.0 ; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v11 ; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v10 @@ -38201,8 +37500,8 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v2 ; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v1 ; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v0 -; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v16 -; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v15 +; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v18 +; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v17 ; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v20 ; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v19 ; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v24 @@ -38211,8 +37510,8 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v30 ; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v14 ; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v13 -; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v18 -; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v17 +; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v16 +; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v15 ; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v22 ; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v21 ; GFX9-NEXT: .LBB53_3: ; %end @@ -38232,9 +37531,9 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; GFX9-NEXT: v_lshl_or_b32 v34, v34, 16, v13 ; GFX9-NEXT: v_and_b32_e32 v13, 0xffff, v20 ; GFX9-NEXT: v_lshl_or_b32 v35, v35, 16, v13 -; GFX9-NEXT: v_and_b32_e32 v13, 0xffff, v15 +; GFX9-NEXT: v_and_b32_e32 v13, 0xffff, v17 ; GFX9-NEXT: v_lshl_or_b32 v12, v12, 16, v13 -; GFX9-NEXT: v_and_b32_e32 v13, 0xffff, v16 +; GFX9-NEXT: v_and_b32_e32 v13, 0xffff, v18 ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX9-NEXT: v_lshl_or_b32 v13, v41, 16, v13 ; GFX9-NEXT: v_lshl_or_b32 v14, v40, 16, v0 @@ -38242,15 +37541,15 @@ define inreg <52 x half> @bitcast_v13f64_to_v52f16_scalar(<13 x double> inreg %a ; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload +; GFX9-NEXT: v_and_b32_e32 v15, 0xffff, v15 +; GFX9-NEXT: v_lshl_or_b32 v26, v26, 16, v15 +; GFX9-NEXT: v_and_b32_e32 v15, 0xffff, v16 ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v1 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff, v17 +; GFX9-NEXT: v_lshl_or_b32 v27, v27, 16, v15 ; GFX9-NEXT: v_lshl_or_b32 v15, v55, 16, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v2 -; GFX9-NEXT: v_lshl_or_b32 v26, v26, 16, v17 -; GFX9-NEXT: v_and_b32_e32 v17, 0xffff, v18 ; GFX9-NEXT: v_lshl_or_b32 v16, v54, 16, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v3 -; GFX9-NEXT: v_lshl_or_b32 v27, v27, 16, v17 ; GFX9-NEXT: v_lshl_or_b32 v17, v53, 16, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v4 ; GFX9-NEXT: v_lshl_or_b32 v18, v52, 16, v0 @@ -39539,7 +38838,6 @@ define <13 x double> @bitcast_v52f16_to_v13f64(<52 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v57, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v25 -; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v24 @@ -39606,6 +38904,7 @@ define <13 x double> @bitcast_v52f16_to_v13f64(<52 x half> %a, i32 %b) { ; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v56 ; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v57 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v26 +; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill ; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -39738,6 +39037,9 @@ define <13 x double> @bitcast_v52f16_to_v13f64(<52 x half> %a, i32 %b) { ; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5] ; GFX9-NEXT: s_cbranch_execz .LBB54_4 ; GFX9-NEXT: ; %bb.3: ; %cmp.true +; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload @@ -39752,9 +39054,6 @@ define <13 x double> @bitcast_v52f16_to_v13f64(<52 x half> %a, i32 %b) { ; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; GFX9-NEXT: s_mov_b32 s6, 0x5040100 ; GFX9-NEXT: v_perm_b32 v0, v34, v57, s6 ; GFX9-NEXT: s_movk_i32 s7, 0x200 ; GFX9-NEXT: v_perm_b32 v1, v62, v56, s6 @@ -39774,6 +39073,10 @@ define <13 x double> @bitcast_v52f16_to_v13f64(<52 x half> %a, i32 %b) { ; GFX9-NEXT: v_pk_add_f16 v6, v6, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v7, v7, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v8, v8, s7 op_sel_hi:[1,0] +; GFX9-NEXT: s_waitcnt vmcnt(14) +; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 +; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; GFX9-NEXT: s_waitcnt vmcnt(15) ; GFX9-NEXT: v_perm_b32 v9, v9, v40, s6 ; GFX9-NEXT: s_waitcnt vmcnt(14) @@ -39802,10 +39105,6 @@ define <13 x double> @bitcast_v52f16_to_v13f64(<52 x half> %a, i32 %b) { ; GFX9-NEXT: v_perm_b32 v21, v21, v36, s6 ; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: v_perm_b32 v22, v22, v35, s6 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_perm_b32 v23, v24, v23, s6 -; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; GFX9-NEXT: v_pk_add_f16 v9, v9, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v10, v10, s7 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v11, v11, s7 op_sel_hi:[1,0] @@ -40074,14 +39373,28 @@ define inreg <13 x double> @bitcast_v52f16_to_v13f64_scalar(<52 x half> inreg %a ; SI-NEXT: v_cvt_f16_f32_e32 v8, s26 ; SI-NEXT: v_cvt_f16_f32_e32 v6, s29 ; SI-NEXT: v_cvt_f16_f32_e32 v7, s28 -; SI-NEXT: s_waitcnt vmcnt(9) +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cvt_f16_f32_e32 v31, v31 -; SI-NEXT: s_waitcnt vmcnt(8) expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v38 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(8) expcnt(0) +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v39 -; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v44 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill @@ -40097,22 +39410,6 @@ define inreg <13 x double> @bitcast_v52f16_to_v13f64_scalar(<52 x half> inreg %a ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v0, v51 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB55_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload @@ -40121,8 +39418,8 @@ define inreg <13 x double> @bitcast_v52f16_to_v13f64_scalar(<52 x half> inreg %a ; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(2) ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v53 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v12 @@ -40142,10 +39439,8 @@ define inreg <13 x double> @bitcast_v52f16_to_v13f64_scalar(<52 x half> inreg %a ; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v42 ; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v56 ; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v43 -; SI-NEXT: s_waitcnt expcnt(1) ; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v57 ; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v15 ; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v62 ; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v36 @@ -40186,11 +39481,11 @@ define inreg <13 x double> @bitcast_v52f16_to_v13f64_scalar(<52 x half> inreg %a ; SI-NEXT: v_or_b32_e32 v25, v38, v25 ; SI-NEXT: s_cbranch_execnz .LBB55_3 ; SI-NEXT: .LBB55_2: ; %cmp.true -; SI-NEXT: s_waitcnt expcnt(2) ; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f32_f16_e32 v0, v53 ; SI-NEXT: v_cvt_f32_f16_e32 v9, v40 ; SI-NEXT: v_cvt_f32_f16_e32 v10, v55 @@ -40204,7 +39499,6 @@ define inreg <13 x double> @bitcast_v52f16_to_v13f64_scalar(<52 x half> inreg %a ; SI-NEXT: v_cvt_f16_f32_e32 v10, v10 ; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11 ; SI-NEXT: v_cvt_f16_f32_e32 v11, v11 -; SI-NEXT: s_waitcnt expcnt(1) ; SI-NEXT: v_cvt_f32_f16_e32 v12, v47 ; SI-NEXT: v_cvt_f32_f16_e32 v13, v60 ; SI-NEXT: v_cvt_f32_f16_e32 v15, v52 @@ -40242,7 +39536,6 @@ define inreg <13 x double> @bitcast_v52f16_to_v13f64_scalar(<52 x half> inreg %a ; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload @@ -40892,294 +40185,109 @@ define inreg <13 x double> @bitcast_v52f16_to_v13f64_scalar(<52 x half> inreg %a ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:316 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:192 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:64 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v187, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v188, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v189, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v190, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v191, s32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v186, v6 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v187, v5 :: v_dual_mov_b32 v188, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v189, v3 :: v_dual_mov_b32 v190, v2 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v191, v1 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v185, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB55_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB55_3 ; GFX11-TRUE16-NEXT: .LBB55_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s40 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s41 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v185, 0x200, v185 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v191, 0x200, v191 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v190, 0x200, v190 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v189, 0x200, v189 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v188, 0x200, v188 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v187, 0x200, v187 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v186, 0x200, v186 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, s6 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, s7 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, s8 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s9 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, s10 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, s11 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, s12 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, s13 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s14 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, s15 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, s16 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s0 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s1 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s2 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, s3 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, s4 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v35, 0x200, s5 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v44, 0x200, s6 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v54, 0x200, s7 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v65, 0x200, s8 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v77, 0x200, s9 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v90, 0x200, s10 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v104, 0x200, s11 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v119, 0x200, s12 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v135, 0x200, s13 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v152, 0x200, s14 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v170, 0x200, s15 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: .LBB55_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v170 :: v_dual_mov_b32 v18, v185 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v191 :: v_dual_mov_b32 v20, v190 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v189 :: v_dual_mov_b32 v22, v188 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v187 :: v_dual_mov_b32 v24, v186 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v191, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v190, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v189, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v188, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v187, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xf -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:300 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:304 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:308 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:312 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:316 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v14, v119 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB55_4: -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v53, v25 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v25, v53 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB55_2 ; ; GFX11-FAKE16-LABEL: bitcast_v52f16_to_v13f64_scalar: @@ -45248,6 +44356,15 @@ define inreg <52 x i16> @bitcast_v52f16_to_v52i16_scalar(<52 x half> inreg %a, i ; SI-LABEL: bitcast_v52f16_to_v52i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:32 +; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 +; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:12 +; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:16 +; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:28 +; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:4 +; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:8 +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:20 +; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:24 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill @@ -45264,15 +44381,6 @@ define inreg <52 x i16> @bitcast_v52f16_to_v52i16_scalar(<52 x half> inreg %a, i ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:32 -; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 -; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:12 -; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:16 -; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:28 -; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:4 -; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:8 -; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:20 -; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:24 ; SI-NEXT: s_waitcnt expcnt(5) ; SI-NEXT: v_cvt_f16_f32_e32 v58, v2 ; SI-NEXT: v_cvt_f16_f32_e32 v2, v3 @@ -45317,26 +44425,19 @@ define inreg <52 x i16> @bitcast_v52f16_to_v52i16_scalar(<52 x half> inreg %a, i ; SI-NEXT: v_cvt_f16_f32_e32 v41, s21 ; SI-NEXT: v_cvt_f16_f32_e32 v16, s26 ; SI-NEXT: v_cvt_f16_f32_e32 v54, s29 -; SI-NEXT: s_waitcnt vmcnt(10) +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 -; SI-NEXT: s_waitcnt vmcnt(9) ; SI-NEXT: v_cvt_f16_f32_e32 v53, v32 -; SI-NEXT: s_waitcnt vmcnt(8) ; SI-NEXT: v_cvt_f16_f32_e32 v32, v33 -; SI-NEXT: s_waitcnt vmcnt(7) ; SI-NEXT: v_cvt_f16_f32_e32 v34, v34 -; SI-NEXT: s_waitcnt vmcnt(6) ; SI-NEXT: v_cvt_f16_f32_e32 v30, v35 ; SI-NEXT: v_cvt_f16_f32_e32 v35, v20 ; SI-NEXT: v_cvt_f16_f32_e32 v33, v24 ; SI-NEXT: v_cvt_f16_f32_e32 v31, v28 -; SI-NEXT: s_waitcnt vmcnt(5) ; SI-NEXT: v_cvt_f16_f32_e32 v55, v36 -; SI-NEXT: s_waitcnt vmcnt(4) ; SI-NEXT: v_cvt_f16_f32_e32 v4, v38 -; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_cvt_f16_f32_e32 v27, v39 -; SI-NEXT: s_waitcnt vmcnt(2) expcnt(0) +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v2, v49 ; SI-NEXT: v_cvt_f16_f32_e32 v24, s18 ; SI-NEXT: v_cvt_f16_f32_e32 v20, s22 |