diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll | 7592 |
1 files changed, 3361 insertions, 4231 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll index 44cfd6c..51bffb7 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll @@ -2837,177 +2837,205 @@ define inreg <40 x i16> @bitcast_v20i32_to_v40i16_scalar(<20 x i32> inreg %a, i3 ; SI-LABEL: bitcast_v20i32_to_v40i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v8, s16 +; SI-NEXT: v_mov_b32_e32 v9, s17 +; SI-NEXT: v_mov_b32_e32 v10, s18 +; SI-NEXT: v_mov_b32_e32 v11, s19 +; SI-NEXT: v_mov_b32_e32 v12, s20 +; SI-NEXT: v_mov_b32_e32 v13, s21 +; SI-NEXT: v_mov_b32_e32 v14, s22 +; SI-NEXT: v_mov_b32_e32 v15, s23 +; SI-NEXT: v_mov_b32_e32 v16, s24 +; SI-NEXT: v_mov_b32_e32 v17, s25 +; SI-NEXT: v_mov_b32_e32 v18, s26 +; SI-NEXT: v_mov_b32_e32 v19, s27 +; SI-NEXT: v_readfirstlane_b32 s22, v8 +; SI-NEXT: v_mov_b32_e32 v8, s28 +; SI-NEXT: v_readfirstlane_b32 s23, v9 +; SI-NEXT: v_mov_b32_e32 v9, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 +; SI-NEXT: v_readfirstlane_b32 s20, v10 +; SI-NEXT: v_readfirstlane_b32 s21, v11 +; SI-NEXT: v_readfirstlane_b32 s18, v12 +; SI-NEXT: v_readfirstlane_b32 s19, v13 +; SI-NEXT: v_readfirstlane_b32 s16, v14 +; SI-NEXT: v_readfirstlane_b32 s17, v15 +; SI-NEXT: v_readfirstlane_b32 s14, v16 +; SI-NEXT: v_readfirstlane_b32 s15, v17 +; SI-NEXT: v_readfirstlane_b32 s12, v18 +; SI-NEXT: v_readfirstlane_b32 s13, v19 +; SI-NEXT: v_readfirstlane_b32 s10, v8 +; SI-NEXT: v_readfirstlane_b32 s11, v9 ; SI-NEXT: v_readfirstlane_b32 s8, v1 ; SI-NEXT: v_readfirstlane_b32 s9, v2 ; SI-NEXT: v_readfirstlane_b32 s6, v3 ; SI-NEXT: v_readfirstlane_b32 s7, v4 ; SI-NEXT: v_readfirstlane_b32 s4, v5 -; SI-NEXT: s_and_b64 s[10:11], vcc, exec +; SI-NEXT: s_and_b64 s[24:25], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v6 ; SI-NEXT: s_cbranch_scc0 .LBB13_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s72, s5, 16 ; SI-NEXT: s_lshr_b32 s73, s7, 16 ; SI-NEXT: s_lshr_b32 s74, s9, 16 -; SI-NEXT: s_lshr_b32 s75, s29, 16 -; SI-NEXT: s_lshr_b32 s76, s27, 16 -; SI-NEXT: s_lshr_b32 s77, s25, 16 -; SI-NEXT: s_lshr_b32 s78, s23, 16 -; SI-NEXT: s_lshr_b32 s79, s21, 16 -; SI-NEXT: s_lshr_b32 s88, s19, 16 -; SI-NEXT: s_lshr_b32 s89, s17, 16 -; SI-NEXT: s_lshr_b64 s[10:11], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[12:13], s[6:7], 16 -; SI-NEXT: s_lshr_b64 s[14:15], s[8:9], 16 -; SI-NEXT: s_lshr_b64 s[40:41], s[28:29], 16 -; SI-NEXT: s_lshr_b64 s[42:43], s[26:27], 16 -; SI-NEXT: s_lshr_b64 s[44:45], s[24:25], 16 -; SI-NEXT: s_lshr_b64 s[46:47], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[56:57], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[58:59], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[60:61], s[16:17], 16 +; SI-NEXT: s_lshr_b32 s75, s11, 16 +; SI-NEXT: s_lshr_b32 s76, s13, 16 +; SI-NEXT: s_lshr_b32 s77, s15, 16 +; SI-NEXT: s_lshr_b32 s78, s17, 16 +; SI-NEXT: s_lshr_b32 s79, s19, 16 +; SI-NEXT: s_lshr_b32 s88, s21, 16 +; SI-NEXT: s_lshr_b32 s89, s23, 16 +; SI-NEXT: s_lshr_b64 s[24:25], s[4:5], 16 +; SI-NEXT: s_lshr_b64 s[26:27], s[6:7], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[8:9], 16 +; SI-NEXT: s_lshr_b64 s[40:41], s[10:11], 16 +; SI-NEXT: s_lshr_b64 s[42:43], s[12:13], 16 +; SI-NEXT: s_lshr_b64 s[44:45], s[14:15], 16 +; SI-NEXT: s_lshr_b64 s[46:47], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[56:57], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[58:59], s[20:21], 16 +; SI-NEXT: s_lshr_b64 s[60:61], s[22:23], 16 ; SI-NEXT: s_cbranch_execnz .LBB13_3 ; SI-NEXT: .LBB13_2: ; %cmp.true -; SI-NEXT: s_add_i32 s17, s17, 3 -; SI-NEXT: s_add_i32 s16, s16, 3 -; SI-NEXT: s_add_i32 s19, s19, 3 -; SI-NEXT: s_add_i32 s18, s18, 3 -; SI-NEXT: s_add_i32 s21, s21, 3 -; SI-NEXT: s_add_i32 s20, s20, 3 ; SI-NEXT: s_add_i32 s23, s23, 3 ; SI-NEXT: s_add_i32 s22, s22, 3 -; SI-NEXT: s_add_i32 s25, s25, 3 -; SI-NEXT: s_add_i32 s24, s24, 3 -; SI-NEXT: s_add_i32 s27, s27, 3 -; SI-NEXT: s_add_i32 s26, s26, 3 -; SI-NEXT: s_add_i32 s29, s29, 3 -; SI-NEXT: s_add_i32 s28, s28, 3 +; SI-NEXT: s_add_i32 s21, s21, 3 +; SI-NEXT: s_add_i32 s20, s20, 3 +; SI-NEXT: s_add_i32 s19, s19, 3 +; SI-NEXT: s_add_i32 s18, s18, 3 +; SI-NEXT: s_add_i32 s17, s17, 3 +; SI-NEXT: s_add_i32 s16, s16, 3 +; SI-NEXT: s_add_i32 s15, s15, 3 +; SI-NEXT: s_add_i32 s14, s14, 3 +; SI-NEXT: s_add_i32 s13, s13, 3 +; SI-NEXT: s_add_i32 s12, s12, 3 +; SI-NEXT: s_add_i32 s11, s11, 3 +; SI-NEXT: s_add_i32 s10, s10, 3 ; SI-NEXT: s_add_i32 s9, s9, 3 ; SI-NEXT: s_add_i32 s8, s8, 3 ; SI-NEXT: s_add_i32 s7, s7, 3 ; SI-NEXT: s_add_i32 s6, s6, 3 ; SI-NEXT: s_add_i32 s5, s5, 3 ; SI-NEXT: s_add_i32 s4, s4, 3 -; SI-NEXT: s_lshr_b64 s[10:11], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[12:13], s[6:7], 16 -; SI-NEXT: s_lshr_b64 s[14:15], s[8:9], 16 -; SI-NEXT: s_lshr_b64 s[40:41], s[28:29], 16 -; SI-NEXT: s_lshr_b64 s[42:43], s[26:27], 16 -; SI-NEXT: s_lshr_b64 s[44:45], s[24:25], 16 -; SI-NEXT: s_lshr_b64 s[46:47], s[22:23], 16 +; SI-NEXT: s_lshr_b64 s[24:25], s[4:5], 16 +; SI-NEXT: s_lshr_b64 s[26:27], s[6:7], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[8:9], 16 +; SI-NEXT: s_lshr_b64 s[40:41], s[10:11], 16 +; SI-NEXT: s_lshr_b64 s[42:43], s[12:13], 16 +; SI-NEXT: s_lshr_b64 s[44:45], s[14:15], 16 +; SI-NEXT: s_lshr_b64 s[46:47], s[16:17], 16 ; SI-NEXT: s_lshr_b32 s72, s5, 16 ; SI-NEXT: s_lshr_b32 s73, s7, 16 ; SI-NEXT: s_lshr_b32 s74, s9, 16 -; SI-NEXT: s_lshr_b32 s75, s29, 16 -; SI-NEXT: s_lshr_b32 s76, s27, 16 -; SI-NEXT: s_lshr_b32 s77, s25, 16 -; SI-NEXT: s_lshr_b32 s78, s23, 16 -; SI-NEXT: s_lshr_b32 s79, s21, 16 -; SI-NEXT: s_lshr_b32 s88, s19, 16 -; SI-NEXT: s_lshr_b32 s89, s17, 16 -; SI-NEXT: s_lshr_b64 s[56:57], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[58:59], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[60:61], s[16:17], 16 +; SI-NEXT: s_lshr_b32 s75, s11, 16 +; SI-NEXT: s_lshr_b32 s76, s13, 16 +; SI-NEXT: s_lshr_b32 s77, s15, 16 +; SI-NEXT: s_lshr_b32 s78, s17, 16 +; SI-NEXT: s_lshr_b32 s79, s19, 16 +; SI-NEXT: s_lshr_b32 s88, s21, 16 +; SI-NEXT: s_lshr_b32 s89, s23, 16 +; SI-NEXT: s_lshr_b64 s[56:57], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[58:59], s[20:21], 16 +; SI-NEXT: s_lshr_b64 s[60:61], s[22:23], 16 ; SI-NEXT: .LBB13_3: ; %end -; SI-NEXT: s_lshl_b32 s11, s60, 16 -; SI-NEXT: s_and_b32 s13, s16, 0xffff -; SI-NEXT: s_or_b32 s11, s13, s11 -; SI-NEXT: v_mov_b32_e32 v1, s11 -; SI-NEXT: s_and_b32 s11, s17, 0xffff -; SI-NEXT: s_lshl_b32 s13, s89, 16 -; SI-NEXT: s_or_b32 s11, s11, s13 -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_lshl_b32 s11, s58, 16 -; SI-NEXT: s_and_b32 s13, s18, 0xffff -; SI-NEXT: s_or_b32 s11, s13, s11 +; SI-NEXT: s_lshl_b32 s25, s60, 16 +; SI-NEXT: s_and_b32 s22, s22, 0xffff +; SI-NEXT: s_or_b32 s22, s22, s25 +; SI-NEXT: v_mov_b32_e32 v1, s22 +; SI-NEXT: s_and_b32 s22, s23, 0xffff +; SI-NEXT: s_lshl_b32 s23, s89, 16 +; SI-NEXT: s_or_b32 s22, s22, s23 +; SI-NEXT: v_mov_b32_e32 v2, s22 +; SI-NEXT: s_lshl_b32 s22, s58, 16 +; SI-NEXT: s_and_b32 s20, s20, 0xffff +; SI-NEXT: s_or_b32 s20, s20, s22 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s19, 0xffff -; SI-NEXT: s_lshl_b32 s13, s88, 16 +; SI-NEXT: v_mov_b32_e32 v2, s20 +; SI-NEXT: s_and_b32 s20, s21, 0xffff +; SI-NEXT: s_lshl_b32 s21, s88, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s20, s20, s21 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s20, 0xffff -; SI-NEXT: s_lshl_b32 s13, s56, 16 +; SI-NEXT: v_mov_b32_e32 v2, s20 +; SI-NEXT: s_and_b32 s18, s18, 0xffff +; SI-NEXT: s_lshl_b32 s20, s56, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 12, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s18, s18, s20 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s21, 0xffff -; SI-NEXT: s_lshl_b32 s13, s79, 16 +; SI-NEXT: v_mov_b32_e32 v2, s18 +; SI-NEXT: s_and_b32 s18, s19, 0xffff +; SI-NEXT: s_lshl_b32 s19, s79, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s18, s18, s19 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s22, 0xffff -; SI-NEXT: s_lshl_b32 s13, s46, 16 +; SI-NEXT: v_mov_b32_e32 v2, s18 +; SI-NEXT: s_and_b32 s16, s16, 0xffff +; SI-NEXT: s_lshl_b32 s18, s46, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 20, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s16, s16, s18 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s23, 0xffff -; SI-NEXT: s_lshl_b32 s13, s78, 16 +; SI-NEXT: v_mov_b32_e32 v2, s16 +; SI-NEXT: s_and_b32 s16, s17, 0xffff +; SI-NEXT: s_lshl_b32 s17, s78, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s16, s16, s17 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s24, 0xffff -; SI-NEXT: s_lshl_b32 s13, s44, 16 +; SI-NEXT: v_mov_b32_e32 v2, s16 +; SI-NEXT: s_and_b32 s14, s14, 0xffff +; SI-NEXT: s_lshl_b32 s16, s44, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 28, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s14, s14, s16 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s25, 0xffff -; SI-NEXT: s_lshl_b32 s13, s77, 16 +; SI-NEXT: v_mov_b32_e32 v2, s14 +; SI-NEXT: s_and_b32 s14, s15, 0xffff +; SI-NEXT: s_lshl_b32 s15, s77, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s14, s14, s15 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s26, 0xffff -; SI-NEXT: s_lshl_b32 s13, s42, 16 +; SI-NEXT: v_mov_b32_e32 v2, s14 +; SI-NEXT: s_and_b32 s12, s12, 0xffff +; SI-NEXT: s_lshl_b32 s14, s42, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 36, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s12, s12, s14 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s27, 0xffff +; SI-NEXT: v_mov_b32_e32 v2, s12 +; SI-NEXT: s_and_b32 s12, s13, 0xffff ; SI-NEXT: s_lshl_b32 s13, s76, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s12, s12, s13 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s28, 0xffff -; SI-NEXT: s_lshl_b32 s13, s40, 16 +; SI-NEXT: v_mov_b32_e32 v2, s12 +; SI-NEXT: s_and_b32 s10, s10, 0xffff +; SI-NEXT: s_lshl_b32 s12, s40, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 44, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s10, s10, s12 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s29, 0xffff -; SI-NEXT: s_lshl_b32 s13, s75, 16 +; SI-NEXT: v_mov_b32_e32 v2, s10 +; SI-NEXT: s_and_b32 s10, s11, 0xffff +; SI-NEXT: s_lshl_b32 s11, s75, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s10, s10, s11 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 +; SI-NEXT: v_mov_b32_e32 v2, s10 ; SI-NEXT: s_and_b32 s8, s8, 0xffff -; SI-NEXT: s_lshl_b32 s11, s14, 16 +; SI-NEXT: s_lshl_b32 s10, s28, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 52, v0 -; SI-NEXT: s_or_b32 s8, s8, s11 +; SI-NEXT: s_or_b32 s8, s8, s10 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s8 @@ -3019,7 +3047,7 @@ define inreg <40 x i16> @bitcast_v20i32_to_v40i16_scalar(<20 x i32> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s8 ; SI-NEXT: s_and_b32 s6, s6, 0xffff -; SI-NEXT: s_lshl_b32 s8, s12, 16 +; SI-NEXT: s_lshl_b32 s8, s26, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 60, v0 ; SI-NEXT: s_or_b32 s6, s6, s8 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen @@ -3033,7 +3061,7 @@ define inreg <40 x i16> @bitcast_v20i32_to_v40i16_scalar(<20 x i32> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s6 ; SI-NEXT: s_and_b32 s4, s4, 0xffff -; SI-NEXT: s_lshl_b32 s6, s10, 16 +; SI-NEXT: s_lshl_b32 s6, s24, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x44, v0 ; SI-NEXT: s_or_b32 s4, s4, s6 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen @@ -3064,18 +3092,46 @@ define inreg <40 x i16> @bitcast_v20i32_to_v40i16_scalar(<20 x i32> inreg %a, i3 ; SI-NEXT: ; implicit-def: $sgpr76 ; SI-NEXT: ; implicit-def: $sgpr40 ; SI-NEXT: ; implicit-def: $sgpr75 -; SI-NEXT: ; implicit-def: $sgpr14 +; SI-NEXT: ; implicit-def: $sgpr28 ; SI-NEXT: ; implicit-def: $sgpr74 -; SI-NEXT: ; implicit-def: $sgpr12 +; SI-NEXT: ; implicit-def: $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr73 -; SI-NEXT: ; implicit-def: $sgpr10 +; SI-NEXT: ; implicit-def: $sgpr24 ; SI-NEXT: ; implicit-def: $sgpr72 ; SI-NEXT: s_branch .LBB13_2 ; ; VI-LABEL: bitcast_v20i32_to_v40i16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v7, s16 +; VI-NEXT: v_mov_b32_e32 v8, s17 +; VI-NEXT: v_mov_b32_e32 v9, s18 +; VI-NEXT: v_mov_b32_e32 v10, s19 +; VI-NEXT: v_mov_b32_e32 v11, s20 +; VI-NEXT: v_mov_b32_e32 v12, s21 +; VI-NEXT: v_mov_b32_e32 v13, s22 +; VI-NEXT: v_mov_b32_e32 v14, s23 +; VI-NEXT: v_mov_b32_e32 v15, s24 +; VI-NEXT: v_mov_b32_e32 v16, s25 +; VI-NEXT: v_mov_b32_e32 v17, s26 +; VI-NEXT: v_mov_b32_e32 v18, s27 +; VI-NEXT: v_mov_b32_e32 v19, s28 +; VI-NEXT: v_readfirstlane_b32 s25, v7 +; VI-NEXT: v_mov_b32_e32 v7, s29 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 +; VI-NEXT: v_readfirstlane_b32 s24, v8 +; VI-NEXT: v_readfirstlane_b32 s23, v9 +; VI-NEXT: v_readfirstlane_b32 s22, v10 +; VI-NEXT: v_readfirstlane_b32 s21, v11 +; VI-NEXT: v_readfirstlane_b32 s20, v12 +; VI-NEXT: v_readfirstlane_b32 s19, v13 +; VI-NEXT: v_readfirstlane_b32 s18, v14 +; VI-NEXT: v_readfirstlane_b32 s17, v15 +; VI-NEXT: v_readfirstlane_b32 s16, v16 +; VI-NEXT: v_readfirstlane_b32 s15, v17 +; VI-NEXT: v_readfirstlane_b32 s14, v18 +; VI-NEXT: v_readfirstlane_b32 s13, v19 +; VI-NEXT: v_readfirstlane_b32 s12, v7 ; VI-NEXT: v_readfirstlane_b32 s11, v0 ; VI-NEXT: v_readfirstlane_b32 s10, v1 ; VI-NEXT: v_readfirstlane_b32 s9, v2 @@ -3085,26 +3141,26 @@ define inreg <40 x i16> @bitcast_v20i32_to_v40i16_scalar(<20 x i32> inreg %a, i3 ; VI-NEXT: v_readfirstlane_b32 s7, v5 ; VI-NEXT: s_cbranch_scc0 .LBB13_4 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_lshr_b32 s12, s7, 16 -; VI-NEXT: s_lshr_b32 s13, s6, 16 -; VI-NEXT: s_lshr_b32 s14, s8, 16 -; VI-NEXT: s_lshr_b32 s15, s9, 16 +; VI-NEXT: s_lshr_b32 s26, s7, 16 +; VI-NEXT: s_lshr_b32 s27, s6, 16 +; VI-NEXT: s_lshr_b32 s28, s8, 16 +; VI-NEXT: s_lshr_b32 s29, s9, 16 ; VI-NEXT: s_lshr_b32 s40, s10, 16 ; VI-NEXT: s_lshr_b32 s41, s11, 16 -; VI-NEXT: s_lshr_b32 s42, s29, 16 -; VI-NEXT: s_lshr_b32 s43, s28, 16 -; VI-NEXT: s_lshr_b32 s44, s27, 16 -; VI-NEXT: s_lshr_b32 s45, s26, 16 -; VI-NEXT: s_lshr_b32 s46, s25, 16 -; VI-NEXT: s_lshr_b32 s47, s24, 16 -; VI-NEXT: s_lshr_b32 s56, s23, 16 -; VI-NEXT: s_lshr_b32 s57, s22, 16 -; VI-NEXT: s_lshr_b32 s58, s21, 16 -; VI-NEXT: s_lshr_b32 s59, s20, 16 -; VI-NEXT: s_lshr_b32 s60, s19, 16 -; VI-NEXT: s_lshr_b32 s61, s18, 16 -; VI-NEXT: s_lshr_b32 s62, s17, 16 -; VI-NEXT: s_lshr_b32 s63, s16, 16 +; VI-NEXT: s_lshr_b32 s42, s12, 16 +; VI-NEXT: s_lshr_b32 s43, s13, 16 +; VI-NEXT: s_lshr_b32 s44, s14, 16 +; VI-NEXT: s_lshr_b32 s45, s15, 16 +; VI-NEXT: s_lshr_b32 s46, s16, 16 +; VI-NEXT: s_lshr_b32 s47, s17, 16 +; VI-NEXT: s_lshr_b32 s56, s18, 16 +; VI-NEXT: s_lshr_b32 s57, s19, 16 +; VI-NEXT: s_lshr_b32 s58, s20, 16 +; VI-NEXT: s_lshr_b32 s59, s21, 16 +; VI-NEXT: s_lshr_b32 s60, s22, 16 +; VI-NEXT: s_lshr_b32 s61, s23, 16 +; VI-NEXT: s_lshr_b32 s62, s24, 16 +; VI-NEXT: s_lshr_b32 s63, s25, 16 ; VI-NEXT: s_cbranch_execnz .LBB13_3 ; VI-NEXT: .LBB13_2: ; %cmp.true ; VI-NEXT: s_add_i32 s7, s7, 3 @@ -3113,115 +3169,115 @@ define inreg <40 x i16> @bitcast_v20i32_to_v40i16_scalar(<20 x i32> inreg %a, i3 ; VI-NEXT: s_add_i32 s9, s9, 3 ; VI-NEXT: s_add_i32 s10, s10, 3 ; VI-NEXT: s_add_i32 s11, s11, 3 -; VI-NEXT: s_add_i32 s29, s29, 3 -; VI-NEXT: s_add_i32 s28, s28, 3 -; VI-NEXT: s_add_i32 s27, s27, 3 -; VI-NEXT: s_add_i32 s26, s26, 3 -; VI-NEXT: s_add_i32 s25, s25, 3 -; VI-NEXT: s_add_i32 s24, s24, 3 -; VI-NEXT: s_add_i32 s23, s23, 3 -; VI-NEXT: s_add_i32 s22, s22, 3 -; VI-NEXT: s_add_i32 s21, s21, 3 -; VI-NEXT: s_add_i32 s20, s20, 3 -; VI-NEXT: s_add_i32 s19, s19, 3 -; VI-NEXT: s_add_i32 s18, s18, 3 -; VI-NEXT: s_add_i32 s17, s17, 3 +; VI-NEXT: s_add_i32 s12, s12, 3 +; VI-NEXT: s_add_i32 s13, s13, 3 +; VI-NEXT: s_add_i32 s14, s14, 3 +; VI-NEXT: s_add_i32 s15, s15, 3 ; VI-NEXT: s_add_i32 s16, s16, 3 -; VI-NEXT: s_lshr_b32 s12, s7, 16 -; VI-NEXT: s_lshr_b32 s13, s6, 16 -; VI-NEXT: s_lshr_b32 s14, s8, 16 -; VI-NEXT: s_lshr_b32 s15, s9, 16 +; VI-NEXT: s_add_i32 s17, s17, 3 +; VI-NEXT: s_add_i32 s18, s18, 3 +; VI-NEXT: s_add_i32 s19, s19, 3 +; VI-NEXT: s_add_i32 s20, s20, 3 +; VI-NEXT: s_add_i32 s21, s21, 3 +; VI-NEXT: s_add_i32 s22, s22, 3 +; VI-NEXT: s_add_i32 s23, s23, 3 +; VI-NEXT: s_add_i32 s24, s24, 3 +; VI-NEXT: s_add_i32 s25, s25, 3 +; VI-NEXT: s_lshr_b32 s26, s7, 16 +; VI-NEXT: s_lshr_b32 s27, s6, 16 +; VI-NEXT: s_lshr_b32 s28, s8, 16 +; VI-NEXT: s_lshr_b32 s29, s9, 16 ; VI-NEXT: s_lshr_b32 s40, s10, 16 ; VI-NEXT: s_lshr_b32 s41, s11, 16 -; VI-NEXT: s_lshr_b32 s42, s29, 16 -; VI-NEXT: s_lshr_b32 s43, s28, 16 -; VI-NEXT: s_lshr_b32 s44, s27, 16 -; VI-NEXT: s_lshr_b32 s45, s26, 16 -; VI-NEXT: s_lshr_b32 s46, s25, 16 -; VI-NEXT: s_lshr_b32 s47, s24, 16 -; VI-NEXT: s_lshr_b32 s56, s23, 16 -; VI-NEXT: s_lshr_b32 s57, s22, 16 -; VI-NEXT: s_lshr_b32 s58, s21, 16 -; VI-NEXT: s_lshr_b32 s59, s20, 16 -; VI-NEXT: s_lshr_b32 s60, s19, 16 -; VI-NEXT: s_lshr_b32 s61, s18, 16 -; VI-NEXT: s_lshr_b32 s62, s17, 16 -; VI-NEXT: s_lshr_b32 s63, s16, 16 +; VI-NEXT: s_lshr_b32 s42, s12, 16 +; VI-NEXT: s_lshr_b32 s43, s13, 16 +; VI-NEXT: s_lshr_b32 s44, s14, 16 +; VI-NEXT: s_lshr_b32 s45, s15, 16 +; VI-NEXT: s_lshr_b32 s46, s16, 16 +; VI-NEXT: s_lshr_b32 s47, s17, 16 +; VI-NEXT: s_lshr_b32 s56, s18, 16 +; VI-NEXT: s_lshr_b32 s57, s19, 16 +; VI-NEXT: s_lshr_b32 s58, s20, 16 +; VI-NEXT: s_lshr_b32 s59, s21, 16 +; VI-NEXT: s_lshr_b32 s60, s22, 16 +; VI-NEXT: s_lshr_b32 s61, s23, 16 +; VI-NEXT: s_lshr_b32 s62, s24, 16 +; VI-NEXT: s_lshr_b32 s63, s25, 16 ; VI-NEXT: .LBB13_3: ; %end -; VI-NEXT: s_and_b32 s4, 0xffff, s16 +; VI-NEXT: s_and_b32 s4, 0xffff, s25 ; VI-NEXT: s_lshl_b32 s5, s63, 16 ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_and_b32 s5, 0xffff, s17 -; VI-NEXT: s_lshl_b32 s16, s62, 16 -; VI-NEXT: s_or_b32 s5, s5, s16 -; VI-NEXT: s_and_b32 s16, 0xffff, s18 -; VI-NEXT: s_lshl_b32 s17, s61, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, 0xffff, s19 -; VI-NEXT: s_lshl_b32 s18, s60, 16 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s18, 0xffff, s20 -; VI-NEXT: s_lshl_b32 s19, s59, 16 -; VI-NEXT: s_or_b32 s18, s18, s19 -; VI-NEXT: s_and_b32 s19, 0xffff, s21 -; VI-NEXT: s_lshl_b32 s20, s58, 16 -; VI-NEXT: s_or_b32 s19, s19, s20 -; VI-NEXT: s_and_b32 s20, 0xffff, s22 -; VI-NEXT: s_lshl_b32 s21, s57, 16 -; VI-NEXT: s_or_b32 s20, s20, s21 -; VI-NEXT: s_and_b32 s21, 0xffff, s23 -; VI-NEXT: s_lshl_b32 s22, s56, 16 -; VI-NEXT: s_or_b32 s21, s21, s22 -; VI-NEXT: s_and_b32 s22, 0xffff, s24 -; VI-NEXT: s_lshl_b32 s23, s47, 16 -; VI-NEXT: s_or_b32 s22, s22, s23 -; VI-NEXT: s_and_b32 s23, 0xffff, s25 -; VI-NEXT: s_lshl_b32 s24, s46, 16 +; VI-NEXT: s_and_b32 s5, 0xffff, s24 +; VI-NEXT: s_lshl_b32 s24, s62, 16 +; VI-NEXT: s_or_b32 s5, s5, s24 +; VI-NEXT: s_and_b32 s23, 0xffff, s23 +; VI-NEXT: s_lshl_b32 s24, s61, 16 ; VI-NEXT: s_or_b32 s23, s23, s24 -; VI-NEXT: s_and_b32 s24, 0xffff, s26 -; VI-NEXT: s_lshl_b32 s25, s45, 16 -; VI-NEXT: s_or_b32 s24, s24, s25 -; VI-NEXT: s_and_b32 s25, 0xffff, s27 -; VI-NEXT: s_lshl_b32 s26, s44, 16 -; VI-NEXT: s_or_b32 s25, s25, s26 -; VI-NEXT: s_and_b32 s26, 0xffff, s28 -; VI-NEXT: s_lshl_b32 s27, s43, 16 -; VI-NEXT: s_or_b32 s26, s26, s27 -; VI-NEXT: s_and_b32 s27, 0xffff, s29 -; VI-NEXT: s_lshl_b32 s28, s42, 16 -; VI-NEXT: s_or_b32 s27, s27, s28 +; VI-NEXT: s_and_b32 s22, 0xffff, s22 +; VI-NEXT: s_lshl_b32 s24, s60, 16 +; VI-NEXT: s_or_b32 s22, s22, s24 +; VI-NEXT: s_and_b32 s21, 0xffff, s21 +; VI-NEXT: s_lshl_b32 s24, s59, 16 +; VI-NEXT: s_or_b32 s21, s21, s24 +; VI-NEXT: s_and_b32 s20, 0xffff, s20 +; VI-NEXT: s_lshl_b32 s24, s58, 16 +; VI-NEXT: s_or_b32 s20, s20, s24 +; VI-NEXT: s_and_b32 s19, 0xffff, s19 +; VI-NEXT: s_lshl_b32 s24, s57, 16 +; VI-NEXT: s_or_b32 s19, s19, s24 +; VI-NEXT: s_and_b32 s18, 0xffff, s18 +; VI-NEXT: s_lshl_b32 s24, s56, 16 +; VI-NEXT: s_or_b32 s18, s18, s24 +; VI-NEXT: s_and_b32 s17, 0xffff, s17 +; VI-NEXT: s_lshl_b32 s24, s47, 16 +; VI-NEXT: s_or_b32 s17, s17, s24 +; VI-NEXT: s_and_b32 s16, 0xffff, s16 +; VI-NEXT: s_lshl_b32 s24, s46, 16 +; VI-NEXT: s_or_b32 s16, s16, s24 +; VI-NEXT: s_and_b32 s15, 0xffff, s15 +; VI-NEXT: s_lshl_b32 s24, s45, 16 +; VI-NEXT: s_or_b32 s15, s15, s24 +; VI-NEXT: s_and_b32 s14, 0xffff, s14 +; VI-NEXT: s_lshl_b32 s24, s44, 16 +; VI-NEXT: s_or_b32 s14, s14, s24 +; VI-NEXT: s_and_b32 s13, 0xffff, s13 +; VI-NEXT: s_lshl_b32 s24, s43, 16 +; VI-NEXT: s_or_b32 s13, s13, s24 +; VI-NEXT: s_and_b32 s12, 0xffff, s12 +; VI-NEXT: s_lshl_b32 s24, s42, 16 +; VI-NEXT: s_or_b32 s12, s12, s24 ; VI-NEXT: s_and_b32 s11, 0xffff, s11 -; VI-NEXT: s_lshl_b32 s28, s41, 16 -; VI-NEXT: s_or_b32 s11, s11, s28 +; VI-NEXT: s_lshl_b32 s24, s41, 16 +; VI-NEXT: s_or_b32 s11, s11, s24 ; VI-NEXT: s_and_b32 s10, 0xffff, s10 -; VI-NEXT: s_lshl_b32 s28, s40, 16 +; VI-NEXT: s_lshl_b32 s24, s40, 16 +; VI-NEXT: s_or_b32 s10, s10, s24 ; VI-NEXT: s_and_b32 s9, 0xffff, s9 -; VI-NEXT: s_lshl_b32 s15, s15, 16 +; VI-NEXT: s_lshl_b32 s24, s29, 16 +; VI-NEXT: s_or_b32 s9, s9, s24 ; VI-NEXT: s_and_b32 s8, 0xffff, s8 -; VI-NEXT: s_lshl_b32 s14, s14, 16 +; VI-NEXT: s_lshl_b32 s24, s28, 16 +; VI-NEXT: s_or_b32 s8, s8, s24 ; VI-NEXT: s_and_b32 s6, 0xffff, s6 -; VI-NEXT: s_lshl_b32 s13, s13, 16 +; VI-NEXT: s_lshl_b32 s24, s27, 16 +; VI-NEXT: s_or_b32 s6, s6, s24 ; VI-NEXT: s_and_b32 s7, 0xffff, s7 -; VI-NEXT: s_lshl_b32 s12, s12, 16 -; VI-NEXT: s_or_b32 s10, s10, s28 -; VI-NEXT: s_or_b32 s9, s9, s15 -; VI-NEXT: s_or_b32 s8, s8, s14 -; VI-NEXT: s_or_b32 s6, s6, s13 -; VI-NEXT: s_or_b32 s7, s7, s12 +; VI-NEXT: s_lshl_b32 s24, s26, 16 +; VI-NEXT: s_or_b32 s7, s7, s24 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s5 -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: v_mov_b32_e32 v3, s17 -; VI-NEXT: v_mov_b32_e32 v4, s18 -; VI-NEXT: v_mov_b32_e32 v5, s19 -; VI-NEXT: v_mov_b32_e32 v6, s20 -; VI-NEXT: v_mov_b32_e32 v7, s21 -; VI-NEXT: v_mov_b32_e32 v8, s22 -; VI-NEXT: v_mov_b32_e32 v9, s23 -; VI-NEXT: v_mov_b32_e32 v10, s24 -; VI-NEXT: v_mov_b32_e32 v11, s25 -; VI-NEXT: v_mov_b32_e32 v12, s26 -; VI-NEXT: v_mov_b32_e32 v13, s27 +; VI-NEXT: v_mov_b32_e32 v2, s23 +; VI-NEXT: v_mov_b32_e32 v3, s22 +; VI-NEXT: v_mov_b32_e32 v4, s21 +; VI-NEXT: v_mov_b32_e32 v5, s20 +; VI-NEXT: v_mov_b32_e32 v6, s19 +; VI-NEXT: v_mov_b32_e32 v7, s18 +; VI-NEXT: v_mov_b32_e32 v8, s17 +; VI-NEXT: v_mov_b32_e32 v9, s16 +; VI-NEXT: v_mov_b32_e32 v10, s15 +; VI-NEXT: v_mov_b32_e32 v11, s14 +; VI-NEXT: v_mov_b32_e32 v12, s13 +; VI-NEXT: v_mov_b32_e32 v13, s12 ; VI-NEXT: v_mov_b32_e32 v14, s11 ; VI-NEXT: v_mov_b32_e32 v15, s10 ; VI-NEXT: v_mov_b32_e32 v16, s9 @@ -3246,57 +3302,75 @@ define inreg <40 x i16> @bitcast_v20i32_to_v40i16_scalar(<20 x i32> inreg %a, i3 ; VI-NEXT: ; implicit-def: $sgpr42 ; VI-NEXT: ; implicit-def: $sgpr41 ; VI-NEXT: ; implicit-def: $sgpr40 -; VI-NEXT: ; implicit-def: $sgpr15 -; VI-NEXT: ; implicit-def: $sgpr14 -; VI-NEXT: ; implicit-def: $sgpr13 -; VI-NEXT: ; implicit-def: $sgpr12 +; VI-NEXT: ; implicit-def: $sgpr29 +; VI-NEXT: ; implicit-def: $sgpr28 +; VI-NEXT: ; implicit-def: $sgpr27 +; VI-NEXT: ; implicit-def: $sgpr26 ; VI-NEXT: s_branch .LBB13_2 ; ; GFX9-LABEL: bitcast_v20i32_to_v40i16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v7, s16 +; GFX9-NEXT: v_mov_b32_e32 v8, s17 +; GFX9-NEXT: v_mov_b32_e32 v9, s18 +; GFX9-NEXT: v_mov_b32_e32 v10, s19 +; GFX9-NEXT: v_mov_b32_e32 v11, s20 +; GFX9-NEXT: v_mov_b32_e32 v12, s21 +; GFX9-NEXT: v_mov_b32_e32 v13, s22 +; GFX9-NEXT: v_mov_b32_e32 v14, s23 +; GFX9-NEXT: v_mov_b32_e32 v15, s24 +; GFX9-NEXT: v_mov_b32_e32 v16, s25 +; GFX9-NEXT: v_mov_b32_e32 v17, s26 +; GFX9-NEXT: v_mov_b32_e32 v18, s27 +; GFX9-NEXT: v_mov_b32_e32 v19, s28 +; GFX9-NEXT: v_readfirstlane_b32 s6, v7 +; GFX9-NEXT: v_mov_b32_e32 v7, s29 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 -; GFX9-NEXT: v_readfirstlane_b32 s6, v0 -; GFX9-NEXT: v_readfirstlane_b32 s7, v1 -; GFX9-NEXT: v_readfirstlane_b32 s8, v2 -; GFX9-NEXT: v_readfirstlane_b32 s9, v3 -; GFX9-NEXT: v_readfirstlane_b32 s10, v4 +; GFX9-NEXT: v_readfirstlane_b32 s7, v8 +; GFX9-NEXT: v_readfirstlane_b32 s8, v9 +; GFX9-NEXT: v_readfirstlane_b32 s9, v10 +; GFX9-NEXT: v_readfirstlane_b32 s10, v11 +; GFX9-NEXT: v_readfirstlane_b32 s11, v12 +; GFX9-NEXT: v_readfirstlane_b32 s12, v13 +; GFX9-NEXT: v_readfirstlane_b32 s13, v14 +; GFX9-NEXT: v_readfirstlane_b32 s14, v15 +; GFX9-NEXT: v_readfirstlane_b32 s15, v16 +; GFX9-NEXT: v_readfirstlane_b32 s16, v17 +; GFX9-NEXT: v_readfirstlane_b32 s17, v18 +; GFX9-NEXT: v_readfirstlane_b32 s18, v19 +; GFX9-NEXT: v_readfirstlane_b32 s19, v7 +; GFX9-NEXT: v_readfirstlane_b32 s20, v0 +; GFX9-NEXT: v_readfirstlane_b32 s21, v1 +; GFX9-NEXT: v_readfirstlane_b32 s22, v2 +; GFX9-NEXT: v_readfirstlane_b32 s23, v3 +; GFX9-NEXT: v_readfirstlane_b32 s24, v4 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec -; GFX9-NEXT: v_readfirstlane_b32 s11, v5 +; GFX9-NEXT: v_readfirstlane_b32 s25, v5 ; GFX9-NEXT: s_cbranch_scc0 .LBB13_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false -; GFX9-NEXT: s_lshr_b32 s12, s11, 16 -; GFX9-NEXT: s_lshr_b32 s13, s10, 16 -; GFX9-NEXT: s_lshr_b32 s14, s9, 16 -; GFX9-NEXT: s_lshr_b32 s15, s8, 16 -; GFX9-NEXT: s_lshr_b32 s40, s7, 16 -; GFX9-NEXT: s_lshr_b32 s41, s6, 16 -; GFX9-NEXT: s_lshr_b32 s42, s29, 16 -; GFX9-NEXT: s_lshr_b32 s43, s28, 16 -; GFX9-NEXT: s_lshr_b32 s44, s27, 16 -; GFX9-NEXT: s_lshr_b32 s45, s26, 16 -; GFX9-NEXT: s_lshr_b32 s46, s25, 16 -; GFX9-NEXT: s_lshr_b32 s47, s24, 16 -; GFX9-NEXT: s_lshr_b32 s56, s23, 16 -; GFX9-NEXT: s_lshr_b32 s57, s22, 16 -; GFX9-NEXT: s_lshr_b32 s58, s21, 16 -; GFX9-NEXT: s_lshr_b32 s59, s20, 16 -; GFX9-NEXT: s_lshr_b32 s60, s19, 16 -; GFX9-NEXT: s_lshr_b32 s61, s18, 16 -; GFX9-NEXT: s_lshr_b32 s62, s17, 16 -; GFX9-NEXT: s_lshr_b32 s63, s16, 16 +; GFX9-NEXT: s_lshr_b32 s26, s25, 16 +; GFX9-NEXT: s_lshr_b32 s27, s24, 16 +; GFX9-NEXT: s_lshr_b32 s28, s23, 16 +; GFX9-NEXT: s_lshr_b32 s29, s22, 16 +; GFX9-NEXT: s_lshr_b32 s40, s21, 16 +; GFX9-NEXT: s_lshr_b32 s41, s20, 16 +; GFX9-NEXT: s_lshr_b32 s42, s19, 16 +; GFX9-NEXT: s_lshr_b32 s43, s18, 16 +; GFX9-NEXT: s_lshr_b32 s44, s17, 16 +; GFX9-NEXT: s_lshr_b32 s45, s16, 16 +; GFX9-NEXT: s_lshr_b32 s46, s15, 16 +; GFX9-NEXT: s_lshr_b32 s47, s14, 16 +; GFX9-NEXT: s_lshr_b32 s56, s13, 16 +; GFX9-NEXT: s_lshr_b32 s57, s12, 16 +; GFX9-NEXT: s_lshr_b32 s58, s11, 16 +; GFX9-NEXT: s_lshr_b32 s59, s10, 16 +; GFX9-NEXT: s_lshr_b32 s60, s9, 16 +; GFX9-NEXT: s_lshr_b32 s61, s8, 16 +; GFX9-NEXT: s_lshr_b32 s62, s7, 16 +; GFX9-NEXT: s_lshr_b32 s63, s6, 16 ; GFX9-NEXT: s_cbranch_execnz .LBB13_3 ; GFX9-NEXT: .LBB13_2: ; %cmp.true -; GFX9-NEXT: s_add_i32 s11, s11, 3 -; GFX9-NEXT: s_add_i32 s10, s10, 3 -; GFX9-NEXT: s_add_i32 s9, s9, 3 -; GFX9-NEXT: s_add_i32 s8, s8, 3 -; GFX9-NEXT: s_add_i32 s7, s7, 3 -; GFX9-NEXT: s_add_i32 s6, s6, 3 -; GFX9-NEXT: s_add_i32 s29, s29, 3 -; GFX9-NEXT: s_add_i32 s28, s28, 3 -; GFX9-NEXT: s_add_i32 s27, s27, 3 -; GFX9-NEXT: s_add_i32 s26, s26, 3 ; GFX9-NEXT: s_add_i32 s25, s25, 3 ; GFX9-NEXT: s_add_i32 s24, s24, 3 ; GFX9-NEXT: s_add_i32 s23, s23, 3 @@ -3307,67 +3381,77 @@ define inreg <40 x i16> @bitcast_v20i32_to_v40i16_scalar(<20 x i32> inreg %a, i3 ; GFX9-NEXT: s_add_i32 s18, s18, 3 ; GFX9-NEXT: s_add_i32 s17, s17, 3 ; GFX9-NEXT: s_add_i32 s16, s16, 3 -; GFX9-NEXT: s_lshr_b32 s12, s11, 16 -; GFX9-NEXT: s_lshr_b32 s13, s10, 16 -; GFX9-NEXT: s_lshr_b32 s14, s9, 16 -; GFX9-NEXT: s_lshr_b32 s15, s8, 16 -; GFX9-NEXT: s_lshr_b32 s40, s7, 16 -; GFX9-NEXT: s_lshr_b32 s41, s6, 16 -; GFX9-NEXT: s_lshr_b32 s42, s29, 16 -; GFX9-NEXT: s_lshr_b32 s43, s28, 16 -; GFX9-NEXT: s_lshr_b32 s44, s27, 16 -; GFX9-NEXT: s_lshr_b32 s45, s26, 16 -; GFX9-NEXT: s_lshr_b32 s46, s25, 16 -; GFX9-NEXT: s_lshr_b32 s47, s24, 16 -; GFX9-NEXT: s_lshr_b32 s56, s23, 16 -; GFX9-NEXT: s_lshr_b32 s57, s22, 16 -; GFX9-NEXT: s_lshr_b32 s58, s21, 16 -; GFX9-NEXT: s_lshr_b32 s59, s20, 16 -; GFX9-NEXT: s_lshr_b32 s60, s19, 16 -; GFX9-NEXT: s_lshr_b32 s61, s18, 16 -; GFX9-NEXT: s_lshr_b32 s62, s17, 16 -; GFX9-NEXT: s_lshr_b32 s63, s16, 16 +; GFX9-NEXT: s_add_i32 s15, s15, 3 +; GFX9-NEXT: s_add_i32 s14, s14, 3 +; GFX9-NEXT: s_add_i32 s13, s13, 3 +; GFX9-NEXT: s_add_i32 s12, s12, 3 +; GFX9-NEXT: s_add_i32 s11, s11, 3 +; GFX9-NEXT: s_add_i32 s10, s10, 3 +; GFX9-NEXT: s_add_i32 s9, s9, 3 +; GFX9-NEXT: s_add_i32 s8, s8, 3 +; GFX9-NEXT: s_add_i32 s7, s7, 3 +; GFX9-NEXT: s_add_i32 s6, s6, 3 +; GFX9-NEXT: s_lshr_b32 s26, s25, 16 +; GFX9-NEXT: s_lshr_b32 s27, s24, 16 +; GFX9-NEXT: s_lshr_b32 s28, s23, 16 +; GFX9-NEXT: s_lshr_b32 s29, s22, 16 +; GFX9-NEXT: s_lshr_b32 s40, s21, 16 +; GFX9-NEXT: s_lshr_b32 s41, s20, 16 +; GFX9-NEXT: s_lshr_b32 s42, s19, 16 +; GFX9-NEXT: s_lshr_b32 s43, s18, 16 +; GFX9-NEXT: s_lshr_b32 s44, s17, 16 +; GFX9-NEXT: s_lshr_b32 s45, s16, 16 +; GFX9-NEXT: s_lshr_b32 s46, s15, 16 +; GFX9-NEXT: s_lshr_b32 s47, s14, 16 +; GFX9-NEXT: s_lshr_b32 s56, s13, 16 +; GFX9-NEXT: s_lshr_b32 s57, s12, 16 +; GFX9-NEXT: s_lshr_b32 s58, s11, 16 +; GFX9-NEXT: s_lshr_b32 s59, s10, 16 +; GFX9-NEXT: s_lshr_b32 s60, s9, 16 +; GFX9-NEXT: s_lshr_b32 s61, s8, 16 +; GFX9-NEXT: s_lshr_b32 s62, s7, 16 +; GFX9-NEXT: s_lshr_b32 s63, s6, 16 ; GFX9-NEXT: .LBB13_3: ; %end -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s16, s63 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s17, s62 -; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s61 -; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s60 -; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s59 -; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s58 -; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s57 -; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s56 -; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s47 -; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s46 -; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s45 -; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s44 -; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s43 -; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s42 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s41 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s40 -; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s15 -; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s14 -; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s13 -; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s12 +; GFX9-NEXT: s_pack_ll_b32_b16 s4, s6, s63 +; GFX9-NEXT: s_pack_ll_b32_b16 s5, s7, s62 +; GFX9-NEXT: s_pack_ll_b32_b16 s6, s8, s61 +; GFX9-NEXT: s_pack_ll_b32_b16 s7, s9, s60 +; GFX9-NEXT: s_pack_ll_b32_b16 s8, s10, s59 +; GFX9-NEXT: s_pack_ll_b32_b16 s9, s11, s58 +; GFX9-NEXT: s_pack_ll_b32_b16 s10, s12, s57 +; GFX9-NEXT: s_pack_ll_b32_b16 s11, s13, s56 +; GFX9-NEXT: s_pack_ll_b32_b16 s12, s14, s47 +; GFX9-NEXT: s_pack_ll_b32_b16 s13, s15, s46 +; GFX9-NEXT: s_pack_ll_b32_b16 s14, s16, s45 +; GFX9-NEXT: s_pack_ll_b32_b16 s15, s17, s44 +; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s43 +; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s42 +; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s41 +; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s40 +; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s29 +; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s28 +; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s27 +; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s26 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 -; GFX9-NEXT: v_mov_b32_e32 v2, s16 -; GFX9-NEXT: v_mov_b32_e32 v3, s17 -; GFX9-NEXT: v_mov_b32_e32 v4, s18 -; GFX9-NEXT: v_mov_b32_e32 v5, s19 -; GFX9-NEXT: v_mov_b32_e32 v6, s20 -; GFX9-NEXT: v_mov_b32_e32 v7, s21 -; GFX9-NEXT: v_mov_b32_e32 v8, s22 -; GFX9-NEXT: v_mov_b32_e32 v9, s23 -; GFX9-NEXT: v_mov_b32_e32 v10, s24 -; GFX9-NEXT: v_mov_b32_e32 v11, s25 -; GFX9-NEXT: v_mov_b32_e32 v12, s26 -; GFX9-NEXT: v_mov_b32_e32 v13, s27 -; GFX9-NEXT: v_mov_b32_e32 v14, s6 -; GFX9-NEXT: v_mov_b32_e32 v15, s7 -; GFX9-NEXT: v_mov_b32_e32 v16, s8 -; GFX9-NEXT: v_mov_b32_e32 v17, s9 -; GFX9-NEXT: v_mov_b32_e32 v18, s10 -; GFX9-NEXT: v_mov_b32_e32 v19, s11 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: v_mov_b32_e32 v4, s8 +; GFX9-NEXT: v_mov_b32_e32 v5, s9 +; GFX9-NEXT: v_mov_b32_e32 v6, s10 +; GFX9-NEXT: v_mov_b32_e32 v7, s11 +; GFX9-NEXT: v_mov_b32_e32 v8, s12 +; GFX9-NEXT: v_mov_b32_e32 v9, s13 +; GFX9-NEXT: v_mov_b32_e32 v10, s14 +; GFX9-NEXT: v_mov_b32_e32 v11, s15 +; GFX9-NEXT: v_mov_b32_e32 v12, s16 +; GFX9-NEXT: v_mov_b32_e32 v13, s17 +; GFX9-NEXT: v_mov_b32_e32 v14, s18 +; GFX9-NEXT: v_mov_b32_e32 v15, s19 +; GFX9-NEXT: v_mov_b32_e32 v16, s20 +; GFX9-NEXT: v_mov_b32_e32 v17, s21 +; GFX9-NEXT: v_mov_b32_e32 v18, s22 +; GFX9-NEXT: v_mov_b32_e32 v19, s23 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: .LBB13_4: ; GFX9-NEXT: ; implicit-def: $sgpr63 @@ -3386,38 +3470,65 @@ define inreg <40 x i16> @bitcast_v20i32_to_v40i16_scalar(<20 x i32> inreg %a, i3 ; GFX9-NEXT: ; implicit-def: $sgpr42 ; GFX9-NEXT: ; implicit-def: $sgpr41 ; GFX9-NEXT: ; implicit-def: $sgpr40 -; GFX9-NEXT: ; implicit-def: $sgpr15 -; GFX9-NEXT: ; implicit-def: $sgpr14 -; GFX9-NEXT: ; implicit-def: $sgpr13 -; GFX9-NEXT: ; implicit-def: $sgpr12 +; GFX9-NEXT: ; implicit-def: $sgpr29 +; GFX9-NEXT: ; implicit-def: $sgpr28 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr26 ; GFX9-NEXT: s_branch .LBB13_2 ; ; GFX11-LABEL: bitcast_v20i32_to_v40i16_scalar: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v3, s0 :: v_dual_mov_b32 v4, s1 +; GFX11-NEXT: v_dual_mov_b32 v5, s2 :: v_dual_mov_b32 v6, s3 +; GFX11-NEXT: v_dual_mov_b32 v7, s16 :: v_dual_mov_b32 v8, s17 +; GFX11-NEXT: v_dual_mov_b32 v9, s18 :: v_dual_mov_b32 v10, s19 +; GFX11-NEXT: v_dual_mov_b32 v11, s20 :: v_dual_mov_b32 v12, s21 +; GFX11-NEXT: v_dual_mov_b32 v13, s22 :: v_dual_mov_b32 v14, s23 +; GFX11-NEXT: v_dual_mov_b32 v15, s24 :: v_dual_mov_b32 v16, s25 +; GFX11-NEXT: v_dual_mov_b32 v17, s26 :: v_dual_mov_b32 v18, s27 +; GFX11-NEXT: v_dual_mov_b32 v19, s28 :: v_dual_mov_b32 v20, s29 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 -; GFX11-NEXT: v_readfirstlane_b32 s5, v0 -; GFX11-NEXT: v_readfirstlane_b32 s4, v1 +; GFX11-NEXT: v_readfirstlane_b32 s0, v3 +; GFX11-NEXT: v_readfirstlane_b32 s1, v4 +; GFX11-NEXT: v_readfirstlane_b32 s2, v5 +; GFX11-NEXT: v_readfirstlane_b32 s3, v6 +; GFX11-NEXT: v_readfirstlane_b32 s4, v7 +; GFX11-NEXT: v_readfirstlane_b32 s5, v8 +; GFX11-NEXT: v_readfirstlane_b32 s6, v9 +; GFX11-NEXT: v_readfirstlane_b32 s7, v10 +; GFX11-NEXT: v_readfirstlane_b32 s8, v11 +; GFX11-NEXT: v_readfirstlane_b32 s9, v12 +; GFX11-NEXT: v_readfirstlane_b32 s10, v13 +; GFX11-NEXT: v_readfirstlane_b32 s11, v14 +; GFX11-NEXT: v_readfirstlane_b32 s12, v15 +; GFX11-NEXT: v_readfirstlane_b32 s13, v16 +; GFX11-NEXT: v_readfirstlane_b32 s14, v17 +; GFX11-NEXT: v_readfirstlane_b32 s15, v18 +; GFX11-NEXT: v_readfirstlane_b32 s16, v19 +; GFX11-NEXT: v_readfirstlane_b32 s17, v20 +; GFX11-NEXT: v_readfirstlane_b32 s19, v0 +; GFX11-NEXT: v_readfirstlane_b32 s18, v1 ; GFX11-NEXT: s_mov_b32 s58, 0 -; GFX11-NEXT: s_and_b32 s6, vcc_lo, exec_lo +; GFX11-NEXT: s_and_b32 s20, vcc_lo, exec_lo ; GFX11-NEXT: s_cbranch_scc0 .LBB13_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: s_lshr_b32 s6, s4, 16 -; GFX11-NEXT: s_lshr_b32 s7, s5, 16 -; GFX11-NEXT: s_lshr_b32 s8, s29, 16 -; GFX11-NEXT: s_lshr_b32 s9, s28, 16 -; GFX11-NEXT: s_lshr_b32 s10, s27, 16 -; GFX11-NEXT: s_lshr_b32 s11, s26, 16 -; GFX11-NEXT: s_lshr_b32 s12, s25, 16 -; GFX11-NEXT: s_lshr_b32 s13, s24, 16 -; GFX11-NEXT: s_lshr_b32 s14, s23, 16 -; GFX11-NEXT: s_lshr_b32 s15, s22, 16 -; GFX11-NEXT: s_lshr_b32 s40, s21, 16 -; GFX11-NEXT: s_lshr_b32 s41, s20, 16 -; GFX11-NEXT: s_lshr_b32 s42, s19, 16 -; GFX11-NEXT: s_lshr_b32 s43, s18, 16 -; GFX11-NEXT: s_lshr_b32 s44, s17, 16 -; GFX11-NEXT: s_lshr_b32 s45, s16, 16 +; GFX11-NEXT: s_lshr_b32 s20, s18, 16 +; GFX11-NEXT: s_lshr_b32 s21, s19, 16 +; GFX11-NEXT: s_lshr_b32 s22, s17, 16 +; GFX11-NEXT: s_lshr_b32 s23, s16, 16 +; GFX11-NEXT: s_lshr_b32 s24, s15, 16 +; GFX11-NEXT: s_lshr_b32 s25, s14, 16 +; GFX11-NEXT: s_lshr_b32 s26, s13, 16 +; GFX11-NEXT: s_lshr_b32 s27, s12, 16 +; GFX11-NEXT: s_lshr_b32 s28, s11, 16 +; GFX11-NEXT: s_lshr_b32 s29, s10, 16 +; GFX11-NEXT: s_lshr_b32 s40, s9, 16 +; GFX11-NEXT: s_lshr_b32 s41, s8, 16 +; GFX11-NEXT: s_lshr_b32 s42, s7, 16 +; GFX11-NEXT: s_lshr_b32 s43, s6, 16 +; GFX11-NEXT: s_lshr_b32 s44, s5, 16 +; GFX11-NEXT: s_lshr_b32 s45, s4, 16 ; GFX11-NEXT: s_lshr_b32 s46, s3, 16 ; GFX11-NEXT: s_lshr_b32 s47, s2, 16 ; GFX11-NEXT: s_lshr_b32 s56, s1, 16 @@ -3425,42 +3536,42 @@ define inreg <40 x i16> @bitcast_v20i32_to_v40i16_scalar(<20 x i32> inreg %a, i3 ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58 ; GFX11-NEXT: s_cbranch_vccnz .LBB13_3 ; GFX11-NEXT: .LBB13_2: ; %cmp.true -; GFX11-NEXT: s_add_i32 s4, s4, 3 -; GFX11-NEXT: s_add_i32 s5, s5, 3 -; GFX11-NEXT: s_add_i32 s29, s29, 3 -; GFX11-NEXT: s_add_i32 s28, s28, 3 -; GFX11-NEXT: s_add_i32 s27, s27, 3 -; GFX11-NEXT: s_add_i32 s26, s26, 3 -; GFX11-NEXT: s_add_i32 s25, s25, 3 -; GFX11-NEXT: s_add_i32 s24, s24, 3 -; GFX11-NEXT: s_add_i32 s23, s23, 3 -; GFX11-NEXT: s_add_i32 s22, s22, 3 -; GFX11-NEXT: s_add_i32 s21, s21, 3 -; GFX11-NEXT: s_add_i32 s20, s20, 3 -; GFX11-NEXT: s_add_i32 s19, s19, 3 ; GFX11-NEXT: s_add_i32 s18, s18, 3 +; GFX11-NEXT: s_add_i32 s19, s19, 3 ; GFX11-NEXT: s_add_i32 s17, s17, 3 ; GFX11-NEXT: s_add_i32 s16, s16, 3 +; GFX11-NEXT: s_add_i32 s15, s15, 3 +; GFX11-NEXT: s_add_i32 s14, s14, 3 +; GFX11-NEXT: s_add_i32 s13, s13, 3 +; GFX11-NEXT: s_add_i32 s12, s12, 3 +; GFX11-NEXT: s_add_i32 s11, s11, 3 +; GFX11-NEXT: s_add_i32 s10, s10, 3 +; GFX11-NEXT: s_add_i32 s9, s9, 3 +; GFX11-NEXT: s_add_i32 s8, s8, 3 +; GFX11-NEXT: s_add_i32 s7, s7, 3 +; GFX11-NEXT: s_add_i32 s6, s6, 3 +; GFX11-NEXT: s_add_i32 s5, s5, 3 +; GFX11-NEXT: s_add_i32 s4, s4, 3 ; GFX11-NEXT: s_add_i32 s3, s3, 3 ; GFX11-NEXT: s_add_i32 s2, s2, 3 ; GFX11-NEXT: s_add_i32 s1, s1, 3 ; GFX11-NEXT: s_add_i32 s0, s0, 3 -; GFX11-NEXT: s_lshr_b32 s6, s4, 16 -; GFX11-NEXT: s_lshr_b32 s7, s5, 16 -; GFX11-NEXT: s_lshr_b32 s8, s29, 16 -; GFX11-NEXT: s_lshr_b32 s9, s28, 16 -; GFX11-NEXT: s_lshr_b32 s10, s27, 16 -; GFX11-NEXT: s_lshr_b32 s11, s26, 16 -; GFX11-NEXT: s_lshr_b32 s12, s25, 16 -; GFX11-NEXT: s_lshr_b32 s13, s24, 16 -; GFX11-NEXT: s_lshr_b32 s14, s23, 16 -; GFX11-NEXT: s_lshr_b32 s15, s22, 16 -; GFX11-NEXT: s_lshr_b32 s40, s21, 16 -; GFX11-NEXT: s_lshr_b32 s41, s20, 16 -; GFX11-NEXT: s_lshr_b32 s42, s19, 16 -; GFX11-NEXT: s_lshr_b32 s43, s18, 16 -; GFX11-NEXT: s_lshr_b32 s44, s17, 16 -; GFX11-NEXT: s_lshr_b32 s45, s16, 16 +; GFX11-NEXT: s_lshr_b32 s20, s18, 16 +; GFX11-NEXT: s_lshr_b32 s21, s19, 16 +; GFX11-NEXT: s_lshr_b32 s22, s17, 16 +; GFX11-NEXT: s_lshr_b32 s23, s16, 16 +; GFX11-NEXT: s_lshr_b32 s24, s15, 16 +; GFX11-NEXT: s_lshr_b32 s25, s14, 16 +; GFX11-NEXT: s_lshr_b32 s26, s13, 16 +; GFX11-NEXT: s_lshr_b32 s27, s12, 16 +; GFX11-NEXT: s_lshr_b32 s28, s11, 16 +; GFX11-NEXT: s_lshr_b32 s29, s10, 16 +; GFX11-NEXT: s_lshr_b32 s40, s9, 16 +; GFX11-NEXT: s_lshr_b32 s41, s8, 16 +; GFX11-NEXT: s_lshr_b32 s42, s7, 16 +; GFX11-NEXT: s_lshr_b32 s43, s6, 16 +; GFX11-NEXT: s_lshr_b32 s44, s5, 16 +; GFX11-NEXT: s_lshr_b32 s45, s4, 16 ; GFX11-NEXT: s_lshr_b32 s46, s3, 16 ; GFX11-NEXT: s_lshr_b32 s47, s2, 16 ; GFX11-NEXT: s_lshr_b32 s56, s1, 16 @@ -3471,32 +3582,32 @@ define inreg <40 x i16> @bitcast_v20i32_to_v40i16_scalar(<20 x i32> inreg %a, i3 ; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s56 ; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s47 ; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s46 -; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s45 -; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s44 -; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s43 -; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s42 -; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s41 -; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s40 -; GFX11-NEXT: s_pack_ll_b32_b16 s15, s22, s15 -; GFX11-NEXT: s_pack_ll_b32_b16 s14, s23, s14 -; GFX11-NEXT: s_pack_ll_b32_b16 s13, s24, s13 -; GFX11-NEXT: s_pack_ll_b32_b16 s12, s25, s12 -; GFX11-NEXT: s_pack_ll_b32_b16 s11, s26, s11 -; GFX11-NEXT: s_pack_ll_b32_b16 s10, s27, s10 -; GFX11-NEXT: s_pack_ll_b32_b16 s9, s28, s9 -; GFX11-NEXT: s_pack_ll_b32_b16 s8, s29, s8 -; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s7 -; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s6 +; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s45 +; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s44 +; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s43 +; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s42 +; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s41 +; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s40 +; GFX11-NEXT: s_pack_ll_b32_b16 s10, s10, s29 +; GFX11-NEXT: s_pack_ll_b32_b16 s11, s11, s28 +; GFX11-NEXT: s_pack_ll_b32_b16 s12, s12, s27 +; GFX11-NEXT: s_pack_ll_b32_b16 s13, s13, s26 +; GFX11-NEXT: s_pack_ll_b32_b16 s14, s14, s25 +; GFX11-NEXT: s_pack_ll_b32_b16 s15, s15, s24 +; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s23 +; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s22 +; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s21 +; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s20 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 -; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 -; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 -; GFX11-NEXT: v_dual_mov_b32 v10, s15 :: v_dual_mov_b32 v11, s14 -; GFX11-NEXT: v_dual_mov_b32 v12, s13 :: v_dual_mov_b32 v13, s12 -; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v15, s10 -; GFX11-NEXT: v_dual_mov_b32 v16, s9 :: v_dual_mov_b32 v17, s8 -; GFX11-NEXT: v_dual_mov_b32 v18, s5 :: v_dual_mov_b32 v19, s4 +; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-NEXT: v_dual_mov_b32 v18, s19 :: v_dual_mov_b32 v19, s18 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: .LBB13_4: ; GFX11-NEXT: ; implicit-def: $sgpr57 @@ -3509,16 +3620,16 @@ define inreg <40 x i16> @bitcast_v20i32_to_v40i16_scalar(<20 x i32> inreg %a, i3 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr41 ; GFX11-NEXT: ; implicit-def: $sgpr40 -; GFX11-NEXT: ; implicit-def: $sgpr15 -; GFX11-NEXT: ; implicit-def: $sgpr14 -; GFX11-NEXT: ; implicit-def: $sgpr13 -; GFX11-NEXT: ; implicit-def: $sgpr12 -; GFX11-NEXT: ; implicit-def: $sgpr11 -; GFX11-NEXT: ; implicit-def: $sgpr10 -; GFX11-NEXT: ; implicit-def: $sgpr9 -; GFX11-NEXT: ; implicit-def: $sgpr8 -; GFX11-NEXT: ; implicit-def: $sgpr7 -; GFX11-NEXT: ; implicit-def: $sgpr6 +; GFX11-NEXT: ; implicit-def: $sgpr29 +; GFX11-NEXT: ; implicit-def: $sgpr28 +; GFX11-NEXT: ; implicit-def: $sgpr27 +; GFX11-NEXT: ; implicit-def: $sgpr26 +; GFX11-NEXT: ; implicit-def: $sgpr25 +; GFX11-NEXT: ; implicit-def: $sgpr24 +; GFX11-NEXT: ; implicit-def: $sgpr23 +; GFX11-NEXT: ; implicit-def: $sgpr22 +; GFX11-NEXT: ; implicit-def: $sgpr21 +; GFX11-NEXT: ; implicit-def: $sgpr20 ; GFX11-NEXT: s_branch .LBB13_2 %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -3541,6 +3652,17 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) { ; SI-LABEL: bitcast_v40i16_to_v20i32: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v52, v6 +; SI-NEXT: v_mov_b32_e32 v53, v4 +; SI-NEXT: v_mov_b32_e32 v54, v2 +; SI-NEXT: v_mov_b32_e32 v55, v0 +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:36 +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:28 +; SI-NEXT: v_mov_b32_e32 v49, v12 +; SI-NEXT: v_mov_b32_e32 v50, v10 +; SI-NEXT: v_mov_b32_e32 v51, v8 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill @@ -3562,17 +3684,6 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v52, v6 -; SI-NEXT: v_mov_b32_e32 v53, v4 -; SI-NEXT: v_mov_b32_e32 v54, v2 -; SI-NEXT: v_mov_b32_e32 v55, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:36 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32 -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:28 -; SI-NEXT: v_mov_b32_e32 v49, v12 -; SI-NEXT: v_mov_b32_e32 v50, v10 -; SI-NEXT: v_mov_b32_e32 v51, v8 ; SI-NEXT: v_mov_b32_e32 v37, v20 ; SI-NEXT: v_mov_b32_e32 v38, v18 ; SI-NEXT: v_mov_b32_e32 v39, v16 @@ -3594,13 +3705,10 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) { ; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v27 ; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v29 ; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:4 -; SI-NEXT: s_waitcnt vmcnt(4) +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v0 -; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v4 -; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24 @@ -3826,7 +3934,7 @@ define <20 x i32> @bitcast_v40i16_to_v20i32(<40 x i16> %a, i32 %b) { ; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15 ; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17 ; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18 -; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19 +; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19 ; SI-NEXT: .LBB14_4: ; %end ; SI-NEXT: s_or_b64 exec, exec, s[4:5] ; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload @@ -4914,269 +5022,100 @@ define inreg <20 x i32> @bitcast_v40i16_to_v20i32_scalar(<40 x i16> inreg %a, i3 ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44 -; GFX11-TRUE16-NEXT: s_clause 0xa -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB15_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB15_3 ; GFX11-TRUE16-NEXT: .LBB15_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s40, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s41, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v186, v186, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v185, v185, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s0, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s1, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s2, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, s3, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, s4, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v35, s5, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v44, s6, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v54, s7, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v65, s8, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v77, s9, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v90, s10, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v104, s11, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v119, s12, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v135, s13, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v152, s14, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v170, s15, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, s6, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, s7, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, s8, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s9, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, s10, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, s11, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, s12, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, s13, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s14, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, s15, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, s16, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: .LBB15_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v17, v170 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v186 :: v_dual_mov_b32 v19, v185 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xa -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:296 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v14, v119 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB15_4: -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB15_2 ; ; GFX11-FAKE16-LABEL: bitcast_v40i16_to_v20i32_scalar: @@ -6097,7 +6036,35 @@ define inreg <40 x half> @bitcast_v20i32_to_v40f16_scalar(<20 x i32> inreg %a, i ; SI-LABEL: bitcast_v20i32_to_v40f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v8, s16 +; SI-NEXT: v_mov_b32_e32 v9, s17 +; SI-NEXT: v_mov_b32_e32 v10, s18 +; SI-NEXT: v_mov_b32_e32 v11, s19 +; SI-NEXT: v_mov_b32_e32 v12, s20 +; SI-NEXT: v_mov_b32_e32 v13, s21 +; SI-NEXT: v_mov_b32_e32 v14, s22 +; SI-NEXT: v_mov_b32_e32 v15, s23 +; SI-NEXT: v_mov_b32_e32 v16, s24 +; SI-NEXT: v_mov_b32_e32 v17, s25 +; SI-NEXT: v_mov_b32_e32 v18, s26 +; SI-NEXT: v_mov_b32_e32 v19, s27 +; SI-NEXT: v_readfirstlane_b32 s23, v8 +; SI-NEXT: v_mov_b32_e32 v8, s28 +; SI-NEXT: v_readfirstlane_b32 s24, v9 +; SI-NEXT: v_mov_b32_e32 v9, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 +; SI-NEXT: v_readfirstlane_b32 s25, v10 +; SI-NEXT: v_readfirstlane_b32 s22, v11 +; SI-NEXT: v_readfirstlane_b32 s21, v12 +; SI-NEXT: v_readfirstlane_b32 s20, v13 +; SI-NEXT: v_readfirstlane_b32 s19, v14 +; SI-NEXT: v_readfirstlane_b32 s18, v15 +; SI-NEXT: v_readfirstlane_b32 s17, v16 +; SI-NEXT: v_readfirstlane_b32 s16, v17 +; SI-NEXT: v_readfirstlane_b32 s15, v18 +; SI-NEXT: v_readfirstlane_b32 s14, v19 +; SI-NEXT: v_readfirstlane_b32 s13, v8 +; SI-NEXT: v_readfirstlane_b32 s12, v9 ; SI-NEXT: v_readfirstlane_b32 s11, v1 ; SI-NEXT: v_readfirstlane_b32 s10, v2 ; SI-NEXT: v_readfirstlane_b32 s8, v3 @@ -6119,33 +6086,33 @@ define inreg <40 x half> @bitcast_v20i32_to_v40f16_scalar(<20 x i32> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v8, s4 ; SI-NEXT: s_lshr_b32 s4, s11, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v10, s4 -; SI-NEXT: s_lshr_b32 s4, s29, 16 +; SI-NEXT: s_lshr_b32 s4, s12, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v12, s4 -; SI-NEXT: s_lshr_b32 s4, s28, 16 +; SI-NEXT: s_lshr_b32 s4, s13, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v14, s4 -; SI-NEXT: s_lshr_b32 s4, s27, 16 +; SI-NEXT: s_lshr_b32 s4, s14, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v16, s4 -; SI-NEXT: s_lshr_b32 s4, s26, 16 +; SI-NEXT: s_lshr_b32 s4, s15, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v19, s4 -; SI-NEXT: s_lshr_b32 s4, s25, 16 +; SI-NEXT: s_lshr_b32 s4, s16, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v21, s4 -; SI-NEXT: s_lshr_b32 s4, s24, 16 +; SI-NEXT: s_lshr_b32 s4, s17, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v23, s4 -; SI-NEXT: s_lshr_b32 s4, s23, 16 +; SI-NEXT: s_lshr_b32 s4, s18, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v25, s4 -; SI-NEXT: s_lshr_b32 s4, s22, 16 +; SI-NEXT: s_lshr_b32 s4, s19, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v27, s4 -; SI-NEXT: s_lshr_b32 s4, s21, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s4 ; SI-NEXT: s_lshr_b32 s4, s20, 16 +; SI-NEXT: v_cvt_f32_f16_e32 v29, s4 +; SI-NEXT: s_lshr_b32 s4, s21, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v31, s4 -; SI-NEXT: s_lshr_b32 s4, s19, 16 +; SI-NEXT: s_lshr_b32 s4, s22, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v34, s4 -; SI-NEXT: s_lshr_b32 s4, s18, 16 +; SI-NEXT: s_lshr_b32 s4, s25, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v36, s4 -; SI-NEXT: s_lshr_b32 s4, s17, 16 +; SI-NEXT: s_lshr_b32 s4, s24, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v38, s4 -; SI-NEXT: s_lshr_b32 s4, s16, 16 +; SI-NEXT: s_lshr_b32 s4, s23, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v48, s4 ; SI-NEXT: v_cvt_f32_f16_e32 v3, s9 ; SI-NEXT: v_cvt_f32_f16_e32 v5, s6 @@ -6153,56 +6120,56 @@ define inreg <40 x half> @bitcast_v20i32_to_v40f16_scalar(<20 x i32> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v9, s8 ; SI-NEXT: v_cvt_f32_f16_e32 v11, s10 ; SI-NEXT: v_cvt_f32_f16_e32 v13, s11 -; SI-NEXT: v_cvt_f32_f16_e32 v15, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v17, s28 -; SI-NEXT: v_cvt_f32_f16_e32 v18, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v20, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v22, s25 -; SI-NEXT: v_cvt_f32_f16_e32 v24, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v26, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v28, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v30, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v32, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v33, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v35, s18 -; SI-NEXT: v_cvt_f32_f16_e32 v37, s17 -; SI-NEXT: v_cvt_f32_f16_e32 v39, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v15, s12 +; SI-NEXT: v_cvt_f32_f16_e32 v17, s13 +; SI-NEXT: v_cvt_f32_f16_e32 v18, s14 +; SI-NEXT: v_cvt_f32_f16_e32 v20, s15 +; SI-NEXT: v_cvt_f32_f16_e32 v22, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v24, s17 +; SI-NEXT: v_cvt_f32_f16_e32 v26, s18 +; SI-NEXT: v_cvt_f32_f16_e32 v28, s19 +; SI-NEXT: v_cvt_f32_f16_e32 v30, s20 +; SI-NEXT: v_cvt_f32_f16_e32 v32, s21 +; SI-NEXT: v_cvt_f32_f16_e32 v33, s22 +; SI-NEXT: v_cvt_f32_f16_e32 v35, s25 +; SI-NEXT: v_cvt_f32_f16_e32 v37, s24 +; SI-NEXT: v_cvt_f32_f16_e32 v39, s23 ; SI-NEXT: s_cbranch_execnz .LBB17_3 ; SI-NEXT: .LBB17_2: ; %cmp.true -; SI-NEXT: s_add_i32 s16, s16, 3 -; SI-NEXT: s_add_i32 s17, s17, 3 -; SI-NEXT: s_add_i32 s18, s18, 3 -; SI-NEXT: s_add_i32 s19, s19, 3 -; SI-NEXT: s_add_i32 s20, s20, 3 -; SI-NEXT: s_add_i32 s21, s21, 3 -; SI-NEXT: s_add_i32 s22, s22, 3 ; SI-NEXT: s_add_i32 s23, s23, 3 ; SI-NEXT: s_add_i32 s24, s24, 3 ; SI-NEXT: s_add_i32 s25, s25, 3 -; SI-NEXT: s_add_i32 s26, s26, 3 -; SI-NEXT: s_add_i32 s27, s27, 3 -; SI-NEXT: s_add_i32 s28, s28, 3 -; SI-NEXT: s_add_i32 s29, s29, 3 +; SI-NEXT: s_add_i32 s22, s22, 3 +; SI-NEXT: s_add_i32 s21, s21, 3 +; SI-NEXT: s_add_i32 s20, s20, 3 +; SI-NEXT: s_add_i32 s19, s19, 3 +; SI-NEXT: s_add_i32 s18, s18, 3 +; SI-NEXT: s_add_i32 s17, s17, 3 +; SI-NEXT: s_add_i32 s16, s16, 3 +; SI-NEXT: s_add_i32 s15, s15, 3 +; SI-NEXT: s_add_i32 s14, s14, 3 +; SI-NEXT: s_add_i32 s13, s13, 3 +; SI-NEXT: s_add_i32 s12, s12, 3 ; SI-NEXT: s_add_i32 s11, s11, 3 ; SI-NEXT: s_add_i32 s10, s10, 3 ; SI-NEXT: s_add_i32 s8, s8, 3 ; SI-NEXT: s_add_i32 s7, s7, 3 ; SI-NEXT: s_add_i32 s6, s6, 3 ; SI-NEXT: s_add_i32 s9, s9, 3 -; SI-NEXT: s_lshr_b32 s4, s16, 16 -; SI-NEXT: s_lshr_b32 s5, s17, 16 -; SI-NEXT: s_lshr_b32 s12, s18, 16 -; SI-NEXT: s_lshr_b32 s13, s19, 16 -; SI-NEXT: s_lshr_b32 s14, s20, 16 -; SI-NEXT: s_lshr_b32 s15, s21, 16 -; SI-NEXT: s_lshr_b32 s40, s22, 16 -; SI-NEXT: s_lshr_b32 s41, s23, 16 -; SI-NEXT: s_lshr_b32 s42, s24, 16 -; SI-NEXT: s_lshr_b32 s43, s25, 16 -; SI-NEXT: s_lshr_b32 s44, s26, 16 -; SI-NEXT: s_lshr_b32 s45, s27, 16 -; SI-NEXT: s_lshr_b32 s46, s28, 16 -; SI-NEXT: s_lshr_b32 s47, s29, 16 +; SI-NEXT: s_lshr_b32 s4, s23, 16 +; SI-NEXT: s_lshr_b32 s5, s24, 16 +; SI-NEXT: s_lshr_b32 s26, s25, 16 +; SI-NEXT: s_lshr_b32 s27, s22, 16 +; SI-NEXT: s_lshr_b32 s28, s21, 16 +; SI-NEXT: s_lshr_b32 s29, s20, 16 +; SI-NEXT: s_lshr_b32 s40, s19, 16 +; SI-NEXT: s_lshr_b32 s41, s18, 16 +; SI-NEXT: s_lshr_b32 s42, s17, 16 +; SI-NEXT: s_lshr_b32 s43, s16, 16 +; SI-NEXT: s_lshr_b32 s44, s15, 16 +; SI-NEXT: s_lshr_b32 s45, s14, 16 +; SI-NEXT: s_lshr_b32 s46, s13, 16 +; SI-NEXT: s_lshr_b32 s47, s12, 16 ; SI-NEXT: s_lshr_b32 s56, s11, 16 ; SI-NEXT: s_lshr_b32 s57, s10, 16 ; SI-NEXT: s_lshr_b32 s58, s8, 16 @@ -6215,20 +6182,20 @@ define inreg <40 x half> @bitcast_v20i32_to_v40f16_scalar(<20 x i32> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v9, s8 ; SI-NEXT: v_cvt_f32_f16_e32 v11, s10 ; SI-NEXT: v_cvt_f32_f16_e32 v13, s11 -; SI-NEXT: v_cvt_f32_f16_e32 v15, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v17, s28 -; SI-NEXT: v_cvt_f32_f16_e32 v18, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v20, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v22, s25 -; SI-NEXT: v_cvt_f32_f16_e32 v24, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v26, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v28, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v30, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v32, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v33, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v35, s18 -; SI-NEXT: v_cvt_f32_f16_e32 v37, s17 -; SI-NEXT: v_cvt_f32_f16_e32 v39, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v15, s12 +; SI-NEXT: v_cvt_f32_f16_e32 v17, s13 +; SI-NEXT: v_cvt_f32_f16_e32 v18, s14 +; SI-NEXT: v_cvt_f32_f16_e32 v20, s15 +; SI-NEXT: v_cvt_f32_f16_e32 v22, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v24, s17 +; SI-NEXT: v_cvt_f32_f16_e32 v26, s18 +; SI-NEXT: v_cvt_f32_f16_e32 v28, s19 +; SI-NEXT: v_cvt_f32_f16_e32 v30, s20 +; SI-NEXT: v_cvt_f32_f16_e32 v32, s21 +; SI-NEXT: v_cvt_f32_f16_e32 v33, s22 +; SI-NEXT: v_cvt_f32_f16_e32 v35, s25 +; SI-NEXT: v_cvt_f32_f16_e32 v37, s24 +; SI-NEXT: v_cvt_f32_f16_e32 v39, s23 ; SI-NEXT: v_cvt_f32_f16_e32 v1, s61 ; SI-NEXT: v_cvt_f32_f16_e32 v2, s60 ; SI-NEXT: v_cvt_f32_f16_e32 v4, s59 @@ -6243,10 +6210,10 @@ define inreg <40 x half> @bitcast_v20i32_to_v40f16_scalar(<20 x i32> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v23, s42 ; SI-NEXT: v_cvt_f32_f16_e32 v25, s41 ; SI-NEXT: v_cvt_f32_f16_e32 v27, s40 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s15 -; SI-NEXT: v_cvt_f32_f16_e32 v31, s14 -; SI-NEXT: v_cvt_f32_f16_e32 v34, s13 -; SI-NEXT: v_cvt_f32_f16_e32 v36, s12 +; SI-NEXT: v_cvt_f32_f16_e32 v29, s29 +; SI-NEXT: v_cvt_f32_f16_e32 v31, s28 +; SI-NEXT: v_cvt_f32_f16_e32 v34, s27 +; SI-NEXT: v_cvt_f32_f16_e32 v36, s26 ; SI-NEXT: v_cvt_f32_f16_e32 v38, s5 ; SI-NEXT: v_cvt_f32_f16_e32 v48, s4 ; SI-NEXT: .LBB17_3: ; %end @@ -6436,7 +6403,35 @@ define inreg <40 x half> @bitcast_v20i32_to_v40f16_scalar(<20 x i32> inreg %a, i ; VI-LABEL: bitcast_v20i32_to_v40f16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v7, s16 +; VI-NEXT: v_mov_b32_e32 v8, s17 +; VI-NEXT: v_mov_b32_e32 v9, s18 +; VI-NEXT: v_mov_b32_e32 v10, s19 +; VI-NEXT: v_mov_b32_e32 v11, s20 +; VI-NEXT: v_mov_b32_e32 v12, s21 +; VI-NEXT: v_mov_b32_e32 v13, s22 +; VI-NEXT: v_mov_b32_e32 v14, s23 +; VI-NEXT: v_mov_b32_e32 v15, s24 +; VI-NEXT: v_mov_b32_e32 v16, s25 +; VI-NEXT: v_mov_b32_e32 v17, s26 +; VI-NEXT: v_mov_b32_e32 v18, s27 +; VI-NEXT: v_mov_b32_e32 v19, s28 +; VI-NEXT: v_readfirstlane_b32 s25, v7 +; VI-NEXT: v_mov_b32_e32 v7, s29 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 +; VI-NEXT: v_readfirstlane_b32 s24, v8 +; VI-NEXT: v_readfirstlane_b32 s23, v9 +; VI-NEXT: v_readfirstlane_b32 s22, v10 +; VI-NEXT: v_readfirstlane_b32 s21, v11 +; VI-NEXT: v_readfirstlane_b32 s20, v12 +; VI-NEXT: v_readfirstlane_b32 s19, v13 +; VI-NEXT: v_readfirstlane_b32 s18, v14 +; VI-NEXT: v_readfirstlane_b32 s17, v15 +; VI-NEXT: v_readfirstlane_b32 s16, v16 +; VI-NEXT: v_readfirstlane_b32 s15, v17 +; VI-NEXT: v_readfirstlane_b32 s14, v18 +; VI-NEXT: v_readfirstlane_b32 s13, v19 +; VI-NEXT: v_readfirstlane_b32 s12, v7 ; VI-NEXT: v_readfirstlane_b32 s11, v0 ; VI-NEXT: v_readfirstlane_b32 s10, v1 ; VI-NEXT: v_readfirstlane_b32 s9, v2 @@ -6446,26 +6441,26 @@ define inreg <40 x half> @bitcast_v20i32_to_v40f16_scalar(<20 x i32> inreg %a, i ; VI-NEXT: v_readfirstlane_b32 s7, v5 ; VI-NEXT: s_cbranch_scc0 .LBB17_4 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_lshr_b32 s12, s7, 16 -; VI-NEXT: s_lshr_b32 s13, s6, 16 -; VI-NEXT: s_lshr_b32 s14, s8, 16 -; VI-NEXT: s_lshr_b32 s15, s9, 16 +; VI-NEXT: s_lshr_b32 s26, s7, 16 +; VI-NEXT: s_lshr_b32 s27, s6, 16 +; VI-NEXT: s_lshr_b32 s28, s8, 16 +; VI-NEXT: s_lshr_b32 s29, s9, 16 ; VI-NEXT: s_lshr_b32 s40, s10, 16 ; VI-NEXT: s_lshr_b32 s41, s11, 16 -; VI-NEXT: s_lshr_b32 s42, s29, 16 -; VI-NEXT: s_lshr_b32 s43, s28, 16 -; VI-NEXT: s_lshr_b32 s44, s27, 16 -; VI-NEXT: s_lshr_b32 s45, s26, 16 -; VI-NEXT: s_lshr_b32 s46, s25, 16 -; VI-NEXT: s_lshr_b32 s47, s24, 16 -; VI-NEXT: s_lshr_b32 s56, s23, 16 -; VI-NEXT: s_lshr_b32 s57, s22, 16 -; VI-NEXT: s_lshr_b32 s58, s21, 16 -; VI-NEXT: s_lshr_b32 s59, s20, 16 -; VI-NEXT: s_lshr_b32 s60, s19, 16 -; VI-NEXT: s_lshr_b32 s61, s18, 16 -; VI-NEXT: s_lshr_b32 s62, s17, 16 -; VI-NEXT: s_lshr_b32 s63, s16, 16 +; VI-NEXT: s_lshr_b32 s42, s12, 16 +; VI-NEXT: s_lshr_b32 s43, s13, 16 +; VI-NEXT: s_lshr_b32 s44, s14, 16 +; VI-NEXT: s_lshr_b32 s45, s15, 16 +; VI-NEXT: s_lshr_b32 s46, s16, 16 +; VI-NEXT: s_lshr_b32 s47, s17, 16 +; VI-NEXT: s_lshr_b32 s56, s18, 16 +; VI-NEXT: s_lshr_b32 s57, s19, 16 +; VI-NEXT: s_lshr_b32 s58, s20, 16 +; VI-NEXT: s_lshr_b32 s59, s21, 16 +; VI-NEXT: s_lshr_b32 s60, s22, 16 +; VI-NEXT: s_lshr_b32 s61, s23, 16 +; VI-NEXT: s_lshr_b32 s62, s24, 16 +; VI-NEXT: s_lshr_b32 s63, s25, 16 ; VI-NEXT: s_cbranch_execnz .LBB17_3 ; VI-NEXT: .LBB17_2: ; %cmp.true ; VI-NEXT: s_add_i32 s7, s7, 3 @@ -6474,115 +6469,115 @@ define inreg <40 x half> @bitcast_v20i32_to_v40f16_scalar(<20 x i32> inreg %a, i ; VI-NEXT: s_add_i32 s9, s9, 3 ; VI-NEXT: s_add_i32 s10, s10, 3 ; VI-NEXT: s_add_i32 s11, s11, 3 -; VI-NEXT: s_add_i32 s29, s29, 3 -; VI-NEXT: s_add_i32 s28, s28, 3 -; VI-NEXT: s_add_i32 s27, s27, 3 -; VI-NEXT: s_add_i32 s26, s26, 3 -; VI-NEXT: s_add_i32 s25, s25, 3 -; VI-NEXT: s_add_i32 s24, s24, 3 -; VI-NEXT: s_add_i32 s23, s23, 3 -; VI-NEXT: s_add_i32 s22, s22, 3 -; VI-NEXT: s_add_i32 s21, s21, 3 -; VI-NEXT: s_add_i32 s20, s20, 3 -; VI-NEXT: s_add_i32 s19, s19, 3 -; VI-NEXT: s_add_i32 s18, s18, 3 -; VI-NEXT: s_add_i32 s17, s17, 3 +; VI-NEXT: s_add_i32 s12, s12, 3 +; VI-NEXT: s_add_i32 s13, s13, 3 +; VI-NEXT: s_add_i32 s14, s14, 3 +; VI-NEXT: s_add_i32 s15, s15, 3 ; VI-NEXT: s_add_i32 s16, s16, 3 -; VI-NEXT: s_lshr_b32 s12, s7, 16 -; VI-NEXT: s_lshr_b32 s13, s6, 16 -; VI-NEXT: s_lshr_b32 s14, s8, 16 -; VI-NEXT: s_lshr_b32 s15, s9, 16 +; VI-NEXT: s_add_i32 s17, s17, 3 +; VI-NEXT: s_add_i32 s18, s18, 3 +; VI-NEXT: s_add_i32 s19, s19, 3 +; VI-NEXT: s_add_i32 s20, s20, 3 +; VI-NEXT: s_add_i32 s21, s21, 3 +; VI-NEXT: s_add_i32 s22, s22, 3 +; VI-NEXT: s_add_i32 s23, s23, 3 +; VI-NEXT: s_add_i32 s24, s24, 3 +; VI-NEXT: s_add_i32 s25, s25, 3 +; VI-NEXT: s_lshr_b32 s26, s7, 16 +; VI-NEXT: s_lshr_b32 s27, s6, 16 +; VI-NEXT: s_lshr_b32 s28, s8, 16 +; VI-NEXT: s_lshr_b32 s29, s9, 16 ; VI-NEXT: s_lshr_b32 s40, s10, 16 ; VI-NEXT: s_lshr_b32 s41, s11, 16 -; VI-NEXT: s_lshr_b32 s42, s29, 16 -; VI-NEXT: s_lshr_b32 s43, s28, 16 -; VI-NEXT: s_lshr_b32 s44, s27, 16 -; VI-NEXT: s_lshr_b32 s45, s26, 16 -; VI-NEXT: s_lshr_b32 s46, s25, 16 -; VI-NEXT: s_lshr_b32 s47, s24, 16 -; VI-NEXT: s_lshr_b32 s56, s23, 16 -; VI-NEXT: s_lshr_b32 s57, s22, 16 -; VI-NEXT: s_lshr_b32 s58, s21, 16 -; VI-NEXT: s_lshr_b32 s59, s20, 16 -; VI-NEXT: s_lshr_b32 s60, s19, 16 -; VI-NEXT: s_lshr_b32 s61, s18, 16 -; VI-NEXT: s_lshr_b32 s62, s17, 16 -; VI-NEXT: s_lshr_b32 s63, s16, 16 +; VI-NEXT: s_lshr_b32 s42, s12, 16 +; VI-NEXT: s_lshr_b32 s43, s13, 16 +; VI-NEXT: s_lshr_b32 s44, s14, 16 +; VI-NEXT: s_lshr_b32 s45, s15, 16 +; VI-NEXT: s_lshr_b32 s46, s16, 16 +; VI-NEXT: s_lshr_b32 s47, s17, 16 +; VI-NEXT: s_lshr_b32 s56, s18, 16 +; VI-NEXT: s_lshr_b32 s57, s19, 16 +; VI-NEXT: s_lshr_b32 s58, s20, 16 +; VI-NEXT: s_lshr_b32 s59, s21, 16 +; VI-NEXT: s_lshr_b32 s60, s22, 16 +; VI-NEXT: s_lshr_b32 s61, s23, 16 +; VI-NEXT: s_lshr_b32 s62, s24, 16 +; VI-NEXT: s_lshr_b32 s63, s25, 16 ; VI-NEXT: .LBB17_3: ; %end -; VI-NEXT: s_and_b32 s4, 0xffff, s16 +; VI-NEXT: s_and_b32 s4, 0xffff, s25 ; VI-NEXT: s_lshl_b32 s5, s63, 16 ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_and_b32 s5, 0xffff, s17 -; VI-NEXT: s_lshl_b32 s16, s62, 16 -; VI-NEXT: s_or_b32 s5, s5, s16 -; VI-NEXT: s_and_b32 s16, 0xffff, s18 -; VI-NEXT: s_lshl_b32 s17, s61, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, 0xffff, s19 -; VI-NEXT: s_lshl_b32 s18, s60, 16 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s18, 0xffff, s20 -; VI-NEXT: s_lshl_b32 s19, s59, 16 -; VI-NEXT: s_or_b32 s18, s18, s19 -; VI-NEXT: s_and_b32 s19, 0xffff, s21 -; VI-NEXT: s_lshl_b32 s20, s58, 16 -; VI-NEXT: s_or_b32 s19, s19, s20 -; VI-NEXT: s_and_b32 s20, 0xffff, s22 -; VI-NEXT: s_lshl_b32 s21, s57, 16 -; VI-NEXT: s_or_b32 s20, s20, s21 -; VI-NEXT: s_and_b32 s21, 0xffff, s23 -; VI-NEXT: s_lshl_b32 s22, s56, 16 -; VI-NEXT: s_or_b32 s21, s21, s22 -; VI-NEXT: s_and_b32 s22, 0xffff, s24 -; VI-NEXT: s_lshl_b32 s23, s47, 16 -; VI-NEXT: s_or_b32 s22, s22, s23 -; VI-NEXT: s_and_b32 s23, 0xffff, s25 -; VI-NEXT: s_lshl_b32 s24, s46, 16 +; VI-NEXT: s_and_b32 s5, 0xffff, s24 +; VI-NEXT: s_lshl_b32 s24, s62, 16 +; VI-NEXT: s_or_b32 s5, s5, s24 +; VI-NEXT: s_and_b32 s23, 0xffff, s23 +; VI-NEXT: s_lshl_b32 s24, s61, 16 ; VI-NEXT: s_or_b32 s23, s23, s24 -; VI-NEXT: s_and_b32 s24, 0xffff, s26 -; VI-NEXT: s_lshl_b32 s25, s45, 16 -; VI-NEXT: s_or_b32 s24, s24, s25 -; VI-NEXT: s_and_b32 s25, 0xffff, s27 -; VI-NEXT: s_lshl_b32 s26, s44, 16 -; VI-NEXT: s_or_b32 s25, s25, s26 -; VI-NEXT: s_and_b32 s26, 0xffff, s28 -; VI-NEXT: s_lshl_b32 s27, s43, 16 -; VI-NEXT: s_or_b32 s26, s26, s27 -; VI-NEXT: s_and_b32 s27, 0xffff, s29 -; VI-NEXT: s_lshl_b32 s28, s42, 16 -; VI-NEXT: s_or_b32 s27, s27, s28 +; VI-NEXT: s_and_b32 s22, 0xffff, s22 +; VI-NEXT: s_lshl_b32 s24, s60, 16 +; VI-NEXT: s_or_b32 s22, s22, s24 +; VI-NEXT: s_and_b32 s21, 0xffff, s21 +; VI-NEXT: s_lshl_b32 s24, s59, 16 +; VI-NEXT: s_or_b32 s21, s21, s24 +; VI-NEXT: s_and_b32 s20, 0xffff, s20 +; VI-NEXT: s_lshl_b32 s24, s58, 16 +; VI-NEXT: s_or_b32 s20, s20, s24 +; VI-NEXT: s_and_b32 s19, 0xffff, s19 +; VI-NEXT: s_lshl_b32 s24, s57, 16 +; VI-NEXT: s_or_b32 s19, s19, s24 +; VI-NEXT: s_and_b32 s18, 0xffff, s18 +; VI-NEXT: s_lshl_b32 s24, s56, 16 +; VI-NEXT: s_or_b32 s18, s18, s24 +; VI-NEXT: s_and_b32 s17, 0xffff, s17 +; VI-NEXT: s_lshl_b32 s24, s47, 16 +; VI-NEXT: s_or_b32 s17, s17, s24 +; VI-NEXT: s_and_b32 s16, 0xffff, s16 +; VI-NEXT: s_lshl_b32 s24, s46, 16 +; VI-NEXT: s_or_b32 s16, s16, s24 +; VI-NEXT: s_and_b32 s15, 0xffff, s15 +; VI-NEXT: s_lshl_b32 s24, s45, 16 +; VI-NEXT: s_or_b32 s15, s15, s24 +; VI-NEXT: s_and_b32 s14, 0xffff, s14 +; VI-NEXT: s_lshl_b32 s24, s44, 16 +; VI-NEXT: s_or_b32 s14, s14, s24 +; VI-NEXT: s_and_b32 s13, 0xffff, s13 +; VI-NEXT: s_lshl_b32 s24, s43, 16 +; VI-NEXT: s_or_b32 s13, s13, s24 +; VI-NEXT: s_and_b32 s12, 0xffff, s12 +; VI-NEXT: s_lshl_b32 s24, s42, 16 +; VI-NEXT: s_or_b32 s12, s12, s24 ; VI-NEXT: s_and_b32 s11, 0xffff, s11 -; VI-NEXT: s_lshl_b32 s28, s41, 16 -; VI-NEXT: s_or_b32 s11, s11, s28 +; VI-NEXT: s_lshl_b32 s24, s41, 16 +; VI-NEXT: s_or_b32 s11, s11, s24 ; VI-NEXT: s_and_b32 s10, 0xffff, s10 -; VI-NEXT: s_lshl_b32 s28, s40, 16 +; VI-NEXT: s_lshl_b32 s24, s40, 16 +; VI-NEXT: s_or_b32 s10, s10, s24 ; VI-NEXT: s_and_b32 s9, 0xffff, s9 -; VI-NEXT: s_lshl_b32 s15, s15, 16 +; VI-NEXT: s_lshl_b32 s24, s29, 16 +; VI-NEXT: s_or_b32 s9, s9, s24 ; VI-NEXT: s_and_b32 s8, 0xffff, s8 -; VI-NEXT: s_lshl_b32 s14, s14, 16 +; VI-NEXT: s_lshl_b32 s24, s28, 16 +; VI-NEXT: s_or_b32 s8, s8, s24 ; VI-NEXT: s_and_b32 s6, 0xffff, s6 -; VI-NEXT: s_lshl_b32 s13, s13, 16 +; VI-NEXT: s_lshl_b32 s24, s27, 16 +; VI-NEXT: s_or_b32 s6, s6, s24 ; VI-NEXT: s_and_b32 s7, 0xffff, s7 -; VI-NEXT: s_lshl_b32 s12, s12, 16 -; VI-NEXT: s_or_b32 s10, s10, s28 -; VI-NEXT: s_or_b32 s9, s9, s15 -; VI-NEXT: s_or_b32 s8, s8, s14 -; VI-NEXT: s_or_b32 s6, s6, s13 -; VI-NEXT: s_or_b32 s7, s7, s12 +; VI-NEXT: s_lshl_b32 s24, s26, 16 +; VI-NEXT: s_or_b32 s7, s7, s24 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s5 -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: v_mov_b32_e32 v3, s17 -; VI-NEXT: v_mov_b32_e32 v4, s18 -; VI-NEXT: v_mov_b32_e32 v5, s19 -; VI-NEXT: v_mov_b32_e32 v6, s20 -; VI-NEXT: v_mov_b32_e32 v7, s21 -; VI-NEXT: v_mov_b32_e32 v8, s22 -; VI-NEXT: v_mov_b32_e32 v9, s23 -; VI-NEXT: v_mov_b32_e32 v10, s24 -; VI-NEXT: v_mov_b32_e32 v11, s25 -; VI-NEXT: v_mov_b32_e32 v12, s26 -; VI-NEXT: v_mov_b32_e32 v13, s27 +; VI-NEXT: v_mov_b32_e32 v2, s23 +; VI-NEXT: v_mov_b32_e32 v3, s22 +; VI-NEXT: v_mov_b32_e32 v4, s21 +; VI-NEXT: v_mov_b32_e32 v5, s20 +; VI-NEXT: v_mov_b32_e32 v6, s19 +; VI-NEXT: v_mov_b32_e32 v7, s18 +; VI-NEXT: v_mov_b32_e32 v8, s17 +; VI-NEXT: v_mov_b32_e32 v9, s16 +; VI-NEXT: v_mov_b32_e32 v10, s15 +; VI-NEXT: v_mov_b32_e32 v11, s14 +; VI-NEXT: v_mov_b32_e32 v12, s13 +; VI-NEXT: v_mov_b32_e32 v13, s12 ; VI-NEXT: v_mov_b32_e32 v14, s11 ; VI-NEXT: v_mov_b32_e32 v15, s10 ; VI-NEXT: v_mov_b32_e32 v16, s9 @@ -6607,57 +6602,75 @@ define inreg <40 x half> @bitcast_v20i32_to_v40f16_scalar(<20 x i32> inreg %a, i ; VI-NEXT: ; implicit-def: $sgpr42 ; VI-NEXT: ; implicit-def: $sgpr41 ; VI-NEXT: ; implicit-def: $sgpr40 -; VI-NEXT: ; implicit-def: $sgpr15 -; VI-NEXT: ; implicit-def: $sgpr14 -; VI-NEXT: ; implicit-def: $sgpr13 -; VI-NEXT: ; implicit-def: $sgpr12 +; VI-NEXT: ; implicit-def: $sgpr29 +; VI-NEXT: ; implicit-def: $sgpr28 +; VI-NEXT: ; implicit-def: $sgpr27 +; VI-NEXT: ; implicit-def: $sgpr26 ; VI-NEXT: s_branch .LBB17_2 ; ; GFX9-LABEL: bitcast_v20i32_to_v40f16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v7, s16 +; GFX9-NEXT: v_mov_b32_e32 v8, s17 +; GFX9-NEXT: v_mov_b32_e32 v9, s18 +; GFX9-NEXT: v_mov_b32_e32 v10, s19 +; GFX9-NEXT: v_mov_b32_e32 v11, s20 +; GFX9-NEXT: v_mov_b32_e32 v12, s21 +; GFX9-NEXT: v_mov_b32_e32 v13, s22 +; GFX9-NEXT: v_mov_b32_e32 v14, s23 +; GFX9-NEXT: v_mov_b32_e32 v15, s24 +; GFX9-NEXT: v_mov_b32_e32 v16, s25 +; GFX9-NEXT: v_mov_b32_e32 v17, s26 +; GFX9-NEXT: v_mov_b32_e32 v18, s27 +; GFX9-NEXT: v_mov_b32_e32 v19, s28 +; GFX9-NEXT: v_readfirstlane_b32 s6, v7 +; GFX9-NEXT: v_mov_b32_e32 v7, s29 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 -; GFX9-NEXT: v_readfirstlane_b32 s6, v0 -; GFX9-NEXT: v_readfirstlane_b32 s7, v1 -; GFX9-NEXT: v_readfirstlane_b32 s8, v2 -; GFX9-NEXT: v_readfirstlane_b32 s9, v3 -; GFX9-NEXT: v_readfirstlane_b32 s10, v4 +; GFX9-NEXT: v_readfirstlane_b32 s7, v8 +; GFX9-NEXT: v_readfirstlane_b32 s8, v9 +; GFX9-NEXT: v_readfirstlane_b32 s9, v10 +; GFX9-NEXT: v_readfirstlane_b32 s10, v11 +; GFX9-NEXT: v_readfirstlane_b32 s11, v12 +; GFX9-NEXT: v_readfirstlane_b32 s12, v13 +; GFX9-NEXT: v_readfirstlane_b32 s13, v14 +; GFX9-NEXT: v_readfirstlane_b32 s14, v15 +; GFX9-NEXT: v_readfirstlane_b32 s15, v16 +; GFX9-NEXT: v_readfirstlane_b32 s16, v17 +; GFX9-NEXT: v_readfirstlane_b32 s17, v18 +; GFX9-NEXT: v_readfirstlane_b32 s18, v19 +; GFX9-NEXT: v_readfirstlane_b32 s19, v7 +; GFX9-NEXT: v_readfirstlane_b32 s20, v0 +; GFX9-NEXT: v_readfirstlane_b32 s21, v1 +; GFX9-NEXT: v_readfirstlane_b32 s22, v2 +; GFX9-NEXT: v_readfirstlane_b32 s23, v3 +; GFX9-NEXT: v_readfirstlane_b32 s24, v4 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec -; GFX9-NEXT: v_readfirstlane_b32 s11, v5 +; GFX9-NEXT: v_readfirstlane_b32 s25, v5 ; GFX9-NEXT: s_cbranch_scc0 .LBB17_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false -; GFX9-NEXT: s_lshr_b32 s12, s11, 16 -; GFX9-NEXT: s_lshr_b32 s13, s10, 16 -; GFX9-NEXT: s_lshr_b32 s14, s9, 16 -; GFX9-NEXT: s_lshr_b32 s15, s8, 16 -; GFX9-NEXT: s_lshr_b32 s40, s7, 16 -; GFX9-NEXT: s_lshr_b32 s41, s6, 16 -; GFX9-NEXT: s_lshr_b32 s42, s29, 16 -; GFX9-NEXT: s_lshr_b32 s43, s28, 16 -; GFX9-NEXT: s_lshr_b32 s44, s27, 16 -; GFX9-NEXT: s_lshr_b32 s45, s26, 16 -; GFX9-NEXT: s_lshr_b32 s46, s25, 16 -; GFX9-NEXT: s_lshr_b32 s47, s24, 16 -; GFX9-NEXT: s_lshr_b32 s56, s23, 16 -; GFX9-NEXT: s_lshr_b32 s57, s22, 16 -; GFX9-NEXT: s_lshr_b32 s58, s21, 16 -; GFX9-NEXT: s_lshr_b32 s59, s20, 16 -; GFX9-NEXT: s_lshr_b32 s60, s19, 16 -; GFX9-NEXT: s_lshr_b32 s61, s18, 16 -; GFX9-NEXT: s_lshr_b32 s62, s17, 16 -; GFX9-NEXT: s_lshr_b32 s63, s16, 16 +; GFX9-NEXT: s_lshr_b32 s26, s25, 16 +; GFX9-NEXT: s_lshr_b32 s27, s24, 16 +; GFX9-NEXT: s_lshr_b32 s28, s23, 16 +; GFX9-NEXT: s_lshr_b32 s29, s22, 16 +; GFX9-NEXT: s_lshr_b32 s40, s21, 16 +; GFX9-NEXT: s_lshr_b32 s41, s20, 16 +; GFX9-NEXT: s_lshr_b32 s42, s19, 16 +; GFX9-NEXT: s_lshr_b32 s43, s18, 16 +; GFX9-NEXT: s_lshr_b32 s44, s17, 16 +; GFX9-NEXT: s_lshr_b32 s45, s16, 16 +; GFX9-NEXT: s_lshr_b32 s46, s15, 16 +; GFX9-NEXT: s_lshr_b32 s47, s14, 16 +; GFX9-NEXT: s_lshr_b32 s56, s13, 16 +; GFX9-NEXT: s_lshr_b32 s57, s12, 16 +; GFX9-NEXT: s_lshr_b32 s58, s11, 16 +; GFX9-NEXT: s_lshr_b32 s59, s10, 16 +; GFX9-NEXT: s_lshr_b32 s60, s9, 16 +; GFX9-NEXT: s_lshr_b32 s61, s8, 16 +; GFX9-NEXT: s_lshr_b32 s62, s7, 16 +; GFX9-NEXT: s_lshr_b32 s63, s6, 16 ; GFX9-NEXT: s_cbranch_execnz .LBB17_3 ; GFX9-NEXT: .LBB17_2: ; %cmp.true -; GFX9-NEXT: s_add_i32 s11, s11, 3 -; GFX9-NEXT: s_add_i32 s10, s10, 3 -; GFX9-NEXT: s_add_i32 s9, s9, 3 -; GFX9-NEXT: s_add_i32 s8, s8, 3 -; GFX9-NEXT: s_add_i32 s7, s7, 3 -; GFX9-NEXT: s_add_i32 s6, s6, 3 -; GFX9-NEXT: s_add_i32 s29, s29, 3 -; GFX9-NEXT: s_add_i32 s28, s28, 3 -; GFX9-NEXT: s_add_i32 s27, s27, 3 -; GFX9-NEXT: s_add_i32 s26, s26, 3 ; GFX9-NEXT: s_add_i32 s25, s25, 3 ; GFX9-NEXT: s_add_i32 s24, s24, 3 ; GFX9-NEXT: s_add_i32 s23, s23, 3 @@ -6668,67 +6681,77 @@ define inreg <40 x half> @bitcast_v20i32_to_v40f16_scalar(<20 x i32> inreg %a, i ; GFX9-NEXT: s_add_i32 s18, s18, 3 ; GFX9-NEXT: s_add_i32 s17, s17, 3 ; GFX9-NEXT: s_add_i32 s16, s16, 3 -; GFX9-NEXT: s_lshr_b32 s12, s11, 16 -; GFX9-NEXT: s_lshr_b32 s13, s10, 16 -; GFX9-NEXT: s_lshr_b32 s14, s9, 16 -; GFX9-NEXT: s_lshr_b32 s15, s8, 16 -; GFX9-NEXT: s_lshr_b32 s40, s7, 16 -; GFX9-NEXT: s_lshr_b32 s41, s6, 16 -; GFX9-NEXT: s_lshr_b32 s42, s29, 16 -; GFX9-NEXT: s_lshr_b32 s43, s28, 16 -; GFX9-NEXT: s_lshr_b32 s44, s27, 16 -; GFX9-NEXT: s_lshr_b32 s45, s26, 16 -; GFX9-NEXT: s_lshr_b32 s46, s25, 16 -; GFX9-NEXT: s_lshr_b32 s47, s24, 16 -; GFX9-NEXT: s_lshr_b32 s56, s23, 16 -; GFX9-NEXT: s_lshr_b32 s57, s22, 16 -; GFX9-NEXT: s_lshr_b32 s58, s21, 16 -; GFX9-NEXT: s_lshr_b32 s59, s20, 16 -; GFX9-NEXT: s_lshr_b32 s60, s19, 16 -; GFX9-NEXT: s_lshr_b32 s61, s18, 16 -; GFX9-NEXT: s_lshr_b32 s62, s17, 16 -; GFX9-NEXT: s_lshr_b32 s63, s16, 16 +; GFX9-NEXT: s_add_i32 s15, s15, 3 +; GFX9-NEXT: s_add_i32 s14, s14, 3 +; GFX9-NEXT: s_add_i32 s13, s13, 3 +; GFX9-NEXT: s_add_i32 s12, s12, 3 +; GFX9-NEXT: s_add_i32 s11, s11, 3 +; GFX9-NEXT: s_add_i32 s10, s10, 3 +; GFX9-NEXT: s_add_i32 s9, s9, 3 +; GFX9-NEXT: s_add_i32 s8, s8, 3 +; GFX9-NEXT: s_add_i32 s7, s7, 3 +; GFX9-NEXT: s_add_i32 s6, s6, 3 +; GFX9-NEXT: s_lshr_b32 s26, s25, 16 +; GFX9-NEXT: s_lshr_b32 s27, s24, 16 +; GFX9-NEXT: s_lshr_b32 s28, s23, 16 +; GFX9-NEXT: s_lshr_b32 s29, s22, 16 +; GFX9-NEXT: s_lshr_b32 s40, s21, 16 +; GFX9-NEXT: s_lshr_b32 s41, s20, 16 +; GFX9-NEXT: s_lshr_b32 s42, s19, 16 +; GFX9-NEXT: s_lshr_b32 s43, s18, 16 +; GFX9-NEXT: s_lshr_b32 s44, s17, 16 +; GFX9-NEXT: s_lshr_b32 s45, s16, 16 +; GFX9-NEXT: s_lshr_b32 s46, s15, 16 +; GFX9-NEXT: s_lshr_b32 s47, s14, 16 +; GFX9-NEXT: s_lshr_b32 s56, s13, 16 +; GFX9-NEXT: s_lshr_b32 s57, s12, 16 +; GFX9-NEXT: s_lshr_b32 s58, s11, 16 +; GFX9-NEXT: s_lshr_b32 s59, s10, 16 +; GFX9-NEXT: s_lshr_b32 s60, s9, 16 +; GFX9-NEXT: s_lshr_b32 s61, s8, 16 +; GFX9-NEXT: s_lshr_b32 s62, s7, 16 +; GFX9-NEXT: s_lshr_b32 s63, s6, 16 ; GFX9-NEXT: .LBB17_3: ; %end -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s16, s63 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s17, s62 -; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s61 -; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s60 -; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s59 -; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s58 -; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s57 -; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s56 -; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s47 -; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s46 -; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s45 -; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s44 -; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s43 -; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s42 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s41 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s40 -; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s15 -; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s14 -; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s13 -; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s12 +; GFX9-NEXT: s_pack_ll_b32_b16 s4, s6, s63 +; GFX9-NEXT: s_pack_ll_b32_b16 s5, s7, s62 +; GFX9-NEXT: s_pack_ll_b32_b16 s6, s8, s61 +; GFX9-NEXT: s_pack_ll_b32_b16 s7, s9, s60 +; GFX9-NEXT: s_pack_ll_b32_b16 s8, s10, s59 +; GFX9-NEXT: s_pack_ll_b32_b16 s9, s11, s58 +; GFX9-NEXT: s_pack_ll_b32_b16 s10, s12, s57 +; GFX9-NEXT: s_pack_ll_b32_b16 s11, s13, s56 +; GFX9-NEXT: s_pack_ll_b32_b16 s12, s14, s47 +; GFX9-NEXT: s_pack_ll_b32_b16 s13, s15, s46 +; GFX9-NEXT: s_pack_ll_b32_b16 s14, s16, s45 +; GFX9-NEXT: s_pack_ll_b32_b16 s15, s17, s44 +; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s43 +; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s42 +; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s41 +; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s40 +; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s29 +; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s28 +; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s27 +; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s26 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 -; GFX9-NEXT: v_mov_b32_e32 v2, s16 -; GFX9-NEXT: v_mov_b32_e32 v3, s17 -; GFX9-NEXT: v_mov_b32_e32 v4, s18 -; GFX9-NEXT: v_mov_b32_e32 v5, s19 -; GFX9-NEXT: v_mov_b32_e32 v6, s20 -; GFX9-NEXT: v_mov_b32_e32 v7, s21 -; GFX9-NEXT: v_mov_b32_e32 v8, s22 -; GFX9-NEXT: v_mov_b32_e32 v9, s23 -; GFX9-NEXT: v_mov_b32_e32 v10, s24 -; GFX9-NEXT: v_mov_b32_e32 v11, s25 -; GFX9-NEXT: v_mov_b32_e32 v12, s26 -; GFX9-NEXT: v_mov_b32_e32 v13, s27 -; GFX9-NEXT: v_mov_b32_e32 v14, s6 -; GFX9-NEXT: v_mov_b32_e32 v15, s7 -; GFX9-NEXT: v_mov_b32_e32 v16, s8 -; GFX9-NEXT: v_mov_b32_e32 v17, s9 -; GFX9-NEXT: v_mov_b32_e32 v18, s10 -; GFX9-NEXT: v_mov_b32_e32 v19, s11 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: v_mov_b32_e32 v4, s8 +; GFX9-NEXT: v_mov_b32_e32 v5, s9 +; GFX9-NEXT: v_mov_b32_e32 v6, s10 +; GFX9-NEXT: v_mov_b32_e32 v7, s11 +; GFX9-NEXT: v_mov_b32_e32 v8, s12 +; GFX9-NEXT: v_mov_b32_e32 v9, s13 +; GFX9-NEXT: v_mov_b32_e32 v10, s14 +; GFX9-NEXT: v_mov_b32_e32 v11, s15 +; GFX9-NEXT: v_mov_b32_e32 v12, s16 +; GFX9-NEXT: v_mov_b32_e32 v13, s17 +; GFX9-NEXT: v_mov_b32_e32 v14, s18 +; GFX9-NEXT: v_mov_b32_e32 v15, s19 +; GFX9-NEXT: v_mov_b32_e32 v16, s20 +; GFX9-NEXT: v_mov_b32_e32 v17, s21 +; GFX9-NEXT: v_mov_b32_e32 v18, s22 +; GFX9-NEXT: v_mov_b32_e32 v19, s23 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: .LBB17_4: ; GFX9-NEXT: ; implicit-def: $sgpr63 @@ -6747,38 +6770,65 @@ define inreg <40 x half> @bitcast_v20i32_to_v40f16_scalar(<20 x i32> inreg %a, i ; GFX9-NEXT: ; implicit-def: $sgpr42 ; GFX9-NEXT: ; implicit-def: $sgpr41 ; GFX9-NEXT: ; implicit-def: $sgpr40 -; GFX9-NEXT: ; implicit-def: $sgpr15 -; GFX9-NEXT: ; implicit-def: $sgpr14 -; GFX9-NEXT: ; implicit-def: $sgpr13 -; GFX9-NEXT: ; implicit-def: $sgpr12 +; GFX9-NEXT: ; implicit-def: $sgpr29 +; GFX9-NEXT: ; implicit-def: $sgpr28 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr26 ; GFX9-NEXT: s_branch .LBB17_2 ; ; GFX11-LABEL: bitcast_v20i32_to_v40f16_scalar: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v3, s0 :: v_dual_mov_b32 v4, s1 +; GFX11-NEXT: v_dual_mov_b32 v5, s2 :: v_dual_mov_b32 v6, s3 +; GFX11-NEXT: v_dual_mov_b32 v7, s16 :: v_dual_mov_b32 v8, s17 +; GFX11-NEXT: v_dual_mov_b32 v9, s18 :: v_dual_mov_b32 v10, s19 +; GFX11-NEXT: v_dual_mov_b32 v11, s20 :: v_dual_mov_b32 v12, s21 +; GFX11-NEXT: v_dual_mov_b32 v13, s22 :: v_dual_mov_b32 v14, s23 +; GFX11-NEXT: v_dual_mov_b32 v15, s24 :: v_dual_mov_b32 v16, s25 +; GFX11-NEXT: v_dual_mov_b32 v17, s26 :: v_dual_mov_b32 v18, s27 +; GFX11-NEXT: v_dual_mov_b32 v19, s28 :: v_dual_mov_b32 v20, s29 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 -; GFX11-NEXT: v_readfirstlane_b32 s5, v0 -; GFX11-NEXT: v_readfirstlane_b32 s4, v1 +; GFX11-NEXT: v_readfirstlane_b32 s0, v3 +; GFX11-NEXT: v_readfirstlane_b32 s1, v4 +; GFX11-NEXT: v_readfirstlane_b32 s2, v5 +; GFX11-NEXT: v_readfirstlane_b32 s3, v6 +; GFX11-NEXT: v_readfirstlane_b32 s4, v7 +; GFX11-NEXT: v_readfirstlane_b32 s5, v8 +; GFX11-NEXT: v_readfirstlane_b32 s6, v9 +; GFX11-NEXT: v_readfirstlane_b32 s7, v10 +; GFX11-NEXT: v_readfirstlane_b32 s8, v11 +; GFX11-NEXT: v_readfirstlane_b32 s9, v12 +; GFX11-NEXT: v_readfirstlane_b32 s10, v13 +; GFX11-NEXT: v_readfirstlane_b32 s11, v14 +; GFX11-NEXT: v_readfirstlane_b32 s12, v15 +; GFX11-NEXT: v_readfirstlane_b32 s13, v16 +; GFX11-NEXT: v_readfirstlane_b32 s14, v17 +; GFX11-NEXT: v_readfirstlane_b32 s15, v18 +; GFX11-NEXT: v_readfirstlane_b32 s16, v19 +; GFX11-NEXT: v_readfirstlane_b32 s17, v20 +; GFX11-NEXT: v_readfirstlane_b32 s19, v0 +; GFX11-NEXT: v_readfirstlane_b32 s18, v1 ; GFX11-NEXT: s_mov_b32 s58, 0 -; GFX11-NEXT: s_and_b32 s6, vcc_lo, exec_lo +; GFX11-NEXT: s_and_b32 s20, vcc_lo, exec_lo ; GFX11-NEXT: s_cbranch_scc0 .LBB17_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: s_lshr_b32 s6, s4, 16 -; GFX11-NEXT: s_lshr_b32 s7, s5, 16 -; GFX11-NEXT: s_lshr_b32 s8, s29, 16 -; GFX11-NEXT: s_lshr_b32 s9, s28, 16 -; GFX11-NEXT: s_lshr_b32 s10, s27, 16 -; GFX11-NEXT: s_lshr_b32 s11, s26, 16 -; GFX11-NEXT: s_lshr_b32 s12, s25, 16 -; GFX11-NEXT: s_lshr_b32 s13, s24, 16 -; GFX11-NEXT: s_lshr_b32 s14, s23, 16 -; GFX11-NEXT: s_lshr_b32 s15, s22, 16 -; GFX11-NEXT: s_lshr_b32 s40, s21, 16 -; GFX11-NEXT: s_lshr_b32 s41, s20, 16 -; GFX11-NEXT: s_lshr_b32 s42, s19, 16 -; GFX11-NEXT: s_lshr_b32 s43, s18, 16 -; GFX11-NEXT: s_lshr_b32 s44, s17, 16 -; GFX11-NEXT: s_lshr_b32 s45, s16, 16 +; GFX11-NEXT: s_lshr_b32 s20, s18, 16 +; GFX11-NEXT: s_lshr_b32 s21, s19, 16 +; GFX11-NEXT: s_lshr_b32 s22, s17, 16 +; GFX11-NEXT: s_lshr_b32 s23, s16, 16 +; GFX11-NEXT: s_lshr_b32 s24, s15, 16 +; GFX11-NEXT: s_lshr_b32 s25, s14, 16 +; GFX11-NEXT: s_lshr_b32 s26, s13, 16 +; GFX11-NEXT: s_lshr_b32 s27, s12, 16 +; GFX11-NEXT: s_lshr_b32 s28, s11, 16 +; GFX11-NEXT: s_lshr_b32 s29, s10, 16 +; GFX11-NEXT: s_lshr_b32 s40, s9, 16 +; GFX11-NEXT: s_lshr_b32 s41, s8, 16 +; GFX11-NEXT: s_lshr_b32 s42, s7, 16 +; GFX11-NEXT: s_lshr_b32 s43, s6, 16 +; GFX11-NEXT: s_lshr_b32 s44, s5, 16 +; GFX11-NEXT: s_lshr_b32 s45, s4, 16 ; GFX11-NEXT: s_lshr_b32 s46, s3, 16 ; GFX11-NEXT: s_lshr_b32 s47, s2, 16 ; GFX11-NEXT: s_lshr_b32 s56, s1, 16 @@ -6786,42 +6836,42 @@ define inreg <40 x half> @bitcast_v20i32_to_v40f16_scalar(<20 x i32> inreg %a, i ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58 ; GFX11-NEXT: s_cbranch_vccnz .LBB17_3 ; GFX11-NEXT: .LBB17_2: ; %cmp.true -; GFX11-NEXT: s_add_i32 s4, s4, 3 -; GFX11-NEXT: s_add_i32 s5, s5, 3 -; GFX11-NEXT: s_add_i32 s29, s29, 3 -; GFX11-NEXT: s_add_i32 s28, s28, 3 -; GFX11-NEXT: s_add_i32 s27, s27, 3 -; GFX11-NEXT: s_add_i32 s26, s26, 3 -; GFX11-NEXT: s_add_i32 s25, s25, 3 -; GFX11-NEXT: s_add_i32 s24, s24, 3 -; GFX11-NEXT: s_add_i32 s23, s23, 3 -; GFX11-NEXT: s_add_i32 s22, s22, 3 -; GFX11-NEXT: s_add_i32 s21, s21, 3 -; GFX11-NEXT: s_add_i32 s20, s20, 3 -; GFX11-NEXT: s_add_i32 s19, s19, 3 ; GFX11-NEXT: s_add_i32 s18, s18, 3 +; GFX11-NEXT: s_add_i32 s19, s19, 3 ; GFX11-NEXT: s_add_i32 s17, s17, 3 ; GFX11-NEXT: s_add_i32 s16, s16, 3 +; GFX11-NEXT: s_add_i32 s15, s15, 3 +; GFX11-NEXT: s_add_i32 s14, s14, 3 +; GFX11-NEXT: s_add_i32 s13, s13, 3 +; GFX11-NEXT: s_add_i32 s12, s12, 3 +; GFX11-NEXT: s_add_i32 s11, s11, 3 +; GFX11-NEXT: s_add_i32 s10, s10, 3 +; GFX11-NEXT: s_add_i32 s9, s9, 3 +; GFX11-NEXT: s_add_i32 s8, s8, 3 +; GFX11-NEXT: s_add_i32 s7, s7, 3 +; GFX11-NEXT: s_add_i32 s6, s6, 3 +; GFX11-NEXT: s_add_i32 s5, s5, 3 +; GFX11-NEXT: s_add_i32 s4, s4, 3 ; GFX11-NEXT: s_add_i32 s3, s3, 3 ; GFX11-NEXT: s_add_i32 s2, s2, 3 ; GFX11-NEXT: s_add_i32 s1, s1, 3 ; GFX11-NEXT: s_add_i32 s0, s0, 3 -; GFX11-NEXT: s_lshr_b32 s6, s4, 16 -; GFX11-NEXT: s_lshr_b32 s7, s5, 16 -; GFX11-NEXT: s_lshr_b32 s8, s29, 16 -; GFX11-NEXT: s_lshr_b32 s9, s28, 16 -; GFX11-NEXT: s_lshr_b32 s10, s27, 16 -; GFX11-NEXT: s_lshr_b32 s11, s26, 16 -; GFX11-NEXT: s_lshr_b32 s12, s25, 16 -; GFX11-NEXT: s_lshr_b32 s13, s24, 16 -; GFX11-NEXT: s_lshr_b32 s14, s23, 16 -; GFX11-NEXT: s_lshr_b32 s15, s22, 16 -; GFX11-NEXT: s_lshr_b32 s40, s21, 16 -; GFX11-NEXT: s_lshr_b32 s41, s20, 16 -; GFX11-NEXT: s_lshr_b32 s42, s19, 16 -; GFX11-NEXT: s_lshr_b32 s43, s18, 16 -; GFX11-NEXT: s_lshr_b32 s44, s17, 16 -; GFX11-NEXT: s_lshr_b32 s45, s16, 16 +; GFX11-NEXT: s_lshr_b32 s20, s18, 16 +; GFX11-NEXT: s_lshr_b32 s21, s19, 16 +; GFX11-NEXT: s_lshr_b32 s22, s17, 16 +; GFX11-NEXT: s_lshr_b32 s23, s16, 16 +; GFX11-NEXT: s_lshr_b32 s24, s15, 16 +; GFX11-NEXT: s_lshr_b32 s25, s14, 16 +; GFX11-NEXT: s_lshr_b32 s26, s13, 16 +; GFX11-NEXT: s_lshr_b32 s27, s12, 16 +; GFX11-NEXT: s_lshr_b32 s28, s11, 16 +; GFX11-NEXT: s_lshr_b32 s29, s10, 16 +; GFX11-NEXT: s_lshr_b32 s40, s9, 16 +; GFX11-NEXT: s_lshr_b32 s41, s8, 16 +; GFX11-NEXT: s_lshr_b32 s42, s7, 16 +; GFX11-NEXT: s_lshr_b32 s43, s6, 16 +; GFX11-NEXT: s_lshr_b32 s44, s5, 16 +; GFX11-NEXT: s_lshr_b32 s45, s4, 16 ; GFX11-NEXT: s_lshr_b32 s46, s3, 16 ; GFX11-NEXT: s_lshr_b32 s47, s2, 16 ; GFX11-NEXT: s_lshr_b32 s56, s1, 16 @@ -6832,32 +6882,32 @@ define inreg <40 x half> @bitcast_v20i32_to_v40f16_scalar(<20 x i32> inreg %a, i ; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s56 ; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s47 ; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s46 -; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s45 -; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s44 -; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s43 -; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s42 -; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s41 -; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s40 -; GFX11-NEXT: s_pack_ll_b32_b16 s15, s22, s15 -; GFX11-NEXT: s_pack_ll_b32_b16 s14, s23, s14 -; GFX11-NEXT: s_pack_ll_b32_b16 s13, s24, s13 -; GFX11-NEXT: s_pack_ll_b32_b16 s12, s25, s12 -; GFX11-NEXT: s_pack_ll_b32_b16 s11, s26, s11 -; GFX11-NEXT: s_pack_ll_b32_b16 s10, s27, s10 -; GFX11-NEXT: s_pack_ll_b32_b16 s9, s28, s9 -; GFX11-NEXT: s_pack_ll_b32_b16 s8, s29, s8 -; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s7 -; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s6 +; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s45 +; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s44 +; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s43 +; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s42 +; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s41 +; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s40 +; GFX11-NEXT: s_pack_ll_b32_b16 s10, s10, s29 +; GFX11-NEXT: s_pack_ll_b32_b16 s11, s11, s28 +; GFX11-NEXT: s_pack_ll_b32_b16 s12, s12, s27 +; GFX11-NEXT: s_pack_ll_b32_b16 s13, s13, s26 +; GFX11-NEXT: s_pack_ll_b32_b16 s14, s14, s25 +; GFX11-NEXT: s_pack_ll_b32_b16 s15, s15, s24 +; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s23 +; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s22 +; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s21 +; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s20 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 -; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 -; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 -; GFX11-NEXT: v_dual_mov_b32 v10, s15 :: v_dual_mov_b32 v11, s14 -; GFX11-NEXT: v_dual_mov_b32 v12, s13 :: v_dual_mov_b32 v13, s12 -; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v15, s10 -; GFX11-NEXT: v_dual_mov_b32 v16, s9 :: v_dual_mov_b32 v17, s8 -; GFX11-NEXT: v_dual_mov_b32 v18, s5 :: v_dual_mov_b32 v19, s4 +; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-NEXT: v_dual_mov_b32 v18, s19 :: v_dual_mov_b32 v19, s18 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: .LBB17_4: ; GFX11-NEXT: ; implicit-def: $sgpr57 @@ -6870,16 +6920,16 @@ define inreg <40 x half> @bitcast_v20i32_to_v40f16_scalar(<20 x i32> inreg %a, i ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr41 ; GFX11-NEXT: ; implicit-def: $sgpr40 -; GFX11-NEXT: ; implicit-def: $sgpr15 -; GFX11-NEXT: ; implicit-def: $sgpr14 -; GFX11-NEXT: ; implicit-def: $sgpr13 -; GFX11-NEXT: ; implicit-def: $sgpr12 -; GFX11-NEXT: ; implicit-def: $sgpr11 -; GFX11-NEXT: ; implicit-def: $sgpr10 -; GFX11-NEXT: ; implicit-def: $sgpr9 -; GFX11-NEXT: ; implicit-def: $sgpr8 -; GFX11-NEXT: ; implicit-def: $sgpr7 -; GFX11-NEXT: ; implicit-def: $sgpr6 +; GFX11-NEXT: ; implicit-def: $sgpr29 +; GFX11-NEXT: ; implicit-def: $sgpr28 +; GFX11-NEXT: ; implicit-def: $sgpr27 +; GFX11-NEXT: ; implicit-def: $sgpr26 +; GFX11-NEXT: ; implicit-def: $sgpr25 +; GFX11-NEXT: ; implicit-def: $sgpr24 +; GFX11-NEXT: ; implicit-def: $sgpr23 +; GFX11-NEXT: ; implicit-def: $sgpr22 +; GFX11-NEXT: ; implicit-def: $sgpr21 +; GFX11-NEXT: ; implicit-def: $sgpr20 ; GFX11-NEXT: s_branch .LBB17_2 %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -8520,269 +8570,100 @@ define inreg <20 x i32> @bitcast_v40f16_to_v20i32_scalar(<40 x half> inreg %a, i ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44 -; GFX11-TRUE16-NEXT: s_clause 0xa -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB19_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB19_3 ; GFX11-TRUE16-NEXT: .LBB19_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s40 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s41 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v186, 0x200, v186 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v185, 0x200, v185 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s0 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s1 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s2 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, s3 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, s4 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v35, 0x200, s5 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v44, 0x200, s6 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v54, 0x200, s7 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v65, 0x200, s8 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v77, 0x200, s9 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v90, 0x200, s10 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v104, 0x200, s11 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v119, 0x200, s12 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v135, 0x200, s13 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v152, 0x200, s14 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v170, 0x200, s15 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, s6 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, s7 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, s8 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s9 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, s10 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, s11 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, s12 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, s13 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s14 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, s15 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, s16 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: .LBB19_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v17, v170 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v186 :: v_dual_mov_b32 v19, v185 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xa -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:296 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v14, v119 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB19_4: -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB19_2 ; ; GFX11-FAKE16-LABEL: bitcast_v40f16_to_v20i32_scalar: @@ -11740,6 +11621,17 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) { ; SI-LABEL: bitcast_v40i16_to_v20f32: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v52, v6 +; SI-NEXT: v_mov_b32_e32 v53, v4 +; SI-NEXT: v_mov_b32_e32 v54, v2 +; SI-NEXT: v_mov_b32_e32 v55, v0 +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:36 +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:28 +; SI-NEXT: v_mov_b32_e32 v49, v12 +; SI-NEXT: v_mov_b32_e32 v50, v10 +; SI-NEXT: v_mov_b32_e32 v51, v8 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill @@ -11761,17 +11653,6 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v52, v6 -; SI-NEXT: v_mov_b32_e32 v53, v4 -; SI-NEXT: v_mov_b32_e32 v54, v2 -; SI-NEXT: v_mov_b32_e32 v55, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:36 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32 -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:28 -; SI-NEXT: v_mov_b32_e32 v49, v12 -; SI-NEXT: v_mov_b32_e32 v50, v10 -; SI-NEXT: v_mov_b32_e32 v51, v8 ; SI-NEXT: v_mov_b32_e32 v37, v20 ; SI-NEXT: v_mov_b32_e32 v38, v18 ; SI-NEXT: v_mov_b32_e32 v39, v16 @@ -11793,13 +11674,10 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) { ; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v27 ; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v29 ; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:4 -; SI-NEXT: s_waitcnt vmcnt(4) +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v0 -; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v4 -; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24 @@ -12025,7 +11903,7 @@ define <20 x float> @bitcast_v40i16_to_v20f32(<40 x i16> %a, i32 %b) { ; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15 ; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17 ; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18 -; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19 +; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19 ; SI-NEXT: .LBB30_4: ; %end ; SI-NEXT: s_or_b64 exec, exec, s[4:5] ; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload @@ -13113,269 +12991,100 @@ define inreg <20 x float> @bitcast_v40i16_to_v20f32_scalar(<40 x i16> inreg %a, ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44 -; GFX11-TRUE16-NEXT: s_clause 0xa -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB31_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB31_3 ; GFX11-TRUE16-NEXT: .LBB31_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s40, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s41, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v186, v186, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v185, v185, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s0, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s1, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s2, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, s3, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, s4, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v35, s5, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v44, s6, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v54, s7, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v65, s8, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v77, s9, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v90, s10, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v104, s11, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v119, s12, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v135, s13, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v152, s14, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v170, s15, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, s6, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, s7, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, s8, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s9, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, s10, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, s11, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, s12, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, s13, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s14, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, s15, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, s16, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: .LBB31_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v17, v170 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v186 :: v_dual_mov_b32 v19, v185 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xa -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:296 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v14, v119 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB31_4: -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB31_2 ; ; GFX11-FAKE16-LABEL: bitcast_v40i16_to_v20f32_scalar: @@ -14277,316 +13986,348 @@ define inreg <40 x half> @bitcast_v20f32_to_v40f16_scalar(<20 x float> inreg %a, ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 -; SI-NEXT: v_readfirstlane_b32 s11, v1 -; SI-NEXT: v_readfirstlane_b32 s10, v2 -; SI-NEXT: v_readfirstlane_b32 s8, v3 -; SI-NEXT: v_readfirstlane_b32 s7, v4 -; SI-NEXT: v_readfirstlane_b32 s6, v5 +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v60, s16 +; SI-NEXT: v_mov_b32_e32 v59, s17 +; SI-NEXT: v_mov_b32_e32 v58, s18 +; SI-NEXT: v_mov_b32_e32 v57, s19 +; SI-NEXT: v_mov_b32_e32 v56, s20 +; SI-NEXT: v_mov_b32_e32 v47, s21 +; SI-NEXT: v_mov_b32_e32 v46, s22 +; SI-NEXT: v_mov_b32_e32 v45, s23 +; SI-NEXT: v_mov_b32_e32 v44, s24 +; SI-NEXT: v_mov_b32_e32 v41, s25 +; SI-NEXT: v_mov_b32_e32 v40, s26 +; SI-NEXT: v_mov_b32_e32 v55, s27 +; SI-NEXT: v_mov_b32_e32 v42, s28 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec -; SI-NEXT: v_readfirstlane_b32 s9, v6 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v43, s29 ; SI-NEXT: s_cbranch_scc0 .LBB33_4 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: s_lshr_b32 s4, s9, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v1, s4 -; SI-NEXT: s_lshr_b32 s4, s6, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v2, s4 -; SI-NEXT: s_lshr_b32 s4, s7, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v4, s4 -; SI-NEXT: s_lshr_b32 s4, s8, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v6, s4 -; SI-NEXT: s_lshr_b32 s4, s10, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v8, s4 -; SI-NEXT: s_lshr_b32 s4, s11, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v10, s4 -; SI-NEXT: s_lshr_b32 s4, s29, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v12, s4 -; SI-NEXT: s_lshr_b32 s4, s28, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v14, s4 -; SI-NEXT: s_lshr_b32 s4, s27, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v16, s4 -; SI-NEXT: s_lshr_b32 s4, s26, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v19, s4 -; SI-NEXT: s_lshr_b32 s4, s25, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v21, s4 -; SI-NEXT: s_lshr_b32 s4, s24, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v23, s4 -; SI-NEXT: s_lshr_b32 s4, s23, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v25, s4 -; SI-NEXT: s_lshr_b32 s4, s22, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v27, s4 -; SI-NEXT: s_lshr_b32 s4, s21, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s4 -; SI-NEXT: s_lshr_b32 s4, s20, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v31, s4 -; SI-NEXT: s_lshr_b32 s4, s19, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v34, s4 -; SI-NEXT: s_lshr_b32 s4, s18, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v36, s4 -; SI-NEXT: s_lshr_b32 s4, s17, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v38, s4 -; SI-NEXT: s_lshr_b32 s4, s16, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v48, s4 -; SI-NEXT: v_cvt_f32_f16_e32 v3, s9 -; SI-NEXT: v_cvt_f32_f16_e32 v5, s6 -; SI-NEXT: v_cvt_f32_f16_e32 v7, s7 -; SI-NEXT: v_cvt_f32_f16_e32 v9, s8 -; SI-NEXT: v_cvt_f32_f16_e32 v11, s10 -; SI-NEXT: v_cvt_f32_f16_e32 v13, s11 -; SI-NEXT: v_cvt_f32_f16_e32 v15, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v17, s28 -; SI-NEXT: v_cvt_f32_f16_e32 v18, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v20, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v22, s25 -; SI-NEXT: v_cvt_f32_f16_e32 v24, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v26, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v28, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v30, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v32, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v33, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v35, s18 -; SI-NEXT: v_cvt_f32_f16_e32 v37, s17 -; SI-NEXT: v_cvt_f32_f16_e32 v39, s16 +; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v10, v9 +; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v12, v9 +; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v14, v9 +; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v16, v9 +; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v43 +; SI-NEXT: v_cvt_f32_f16_e32 v18, v9 +; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v42 +; SI-NEXT: v_cvt_f32_f16_e32 v20, v9 +; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v55 +; SI-NEXT: v_cvt_f32_f16_e32 v22, v9 +; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v40 +; SI-NEXT: v_cvt_f32_f16_e32 v25, v9 +; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v41 +; SI-NEXT: v_cvt_f32_f16_e32 v27, v9 +; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v44 +; SI-NEXT: v_cvt_f32_f16_e32 v29, v9 +; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v45 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v9 +; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v46 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v9 +; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v47 +; SI-NEXT: v_cvt_f32_f16_e32 v35, v9 +; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v56 +; SI-NEXT: v_cvt_f32_f16_e32 v37, v9 +; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v57 +; SI-NEXT: v_cvt_f32_f16_e32 v48, v9 +; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v58 +; SI-NEXT: v_cvt_f32_f16_e32 v50, v9 +; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v59 +; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6 +; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v52, v9 +; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v60 +; SI-NEXT: v_cvt_f32_f16_e32 v7, v7 +; SI-NEXT: v_cvt_f32_f16_e32 v8, v8 +; SI-NEXT: v_cvt_f32_f16_e32 v54, v9 +; SI-NEXT: v_cvt_f32_f16_e32 v9, v6 +; SI-NEXT: v_cvt_f32_f16_e32 v11, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v13, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v15, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v17, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v19, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v21, v43 +; SI-NEXT: v_cvt_f32_f16_e32 v23, v42 +; SI-NEXT: v_cvt_f32_f16_e32 v24, v55 +; SI-NEXT: v_cvt_f32_f16_e32 v26, v40 +; SI-NEXT: v_cvt_f32_f16_e32 v28, v41 +; SI-NEXT: v_cvt_f32_f16_e32 v30, v44 +; SI-NEXT: v_cvt_f32_f16_e32 v32, v45 +; SI-NEXT: v_cvt_f32_f16_e32 v34, v46 +; SI-NEXT: v_cvt_f32_f16_e32 v36, v47 +; SI-NEXT: v_cvt_f32_f16_e32 v38, v56 +; SI-NEXT: v_cvt_f32_f16_e32 v39, v57 +; SI-NEXT: v_cvt_f32_f16_e32 v49, v58 +; SI-NEXT: v_cvt_f32_f16_e32 v51, v59 +; SI-NEXT: v_cvt_f32_f16_e32 v53, v60 ; SI-NEXT: s_cbranch_execnz .LBB33_3 ; SI-NEXT: .LBB33_2: ; %cmp.true -; SI-NEXT: v_add_f32_e64 v1, s16, 1.0 -; SI-NEXT: v_add_f32_e64 v2, s17, 1.0 -; SI-NEXT: v_add_f32_e64 v4, s18, 1.0 -; SI-NEXT: v_add_f32_e64 v6, s19, 1.0 -; SI-NEXT: v_add_f32_e64 v8, s20, 1.0 -; SI-NEXT: v_add_f32_e64 v10, s21, 1.0 -; SI-NEXT: v_add_f32_e64 v12, s22, 1.0 -; SI-NEXT: v_add_f32_e64 v14, s23, 1.0 -; SI-NEXT: v_add_f32_e64 v16, s24, 1.0 -; SI-NEXT: v_add_f32_e64 v19, s25, 1.0 -; SI-NEXT: v_add_f32_e64 v20, s26, 1.0 -; SI-NEXT: v_add_f32_e64 v18, s27, 1.0 -; SI-NEXT: v_add_f32_e64 v17, s28, 1.0 -; SI-NEXT: v_add_f32_e64 v15, s29, 1.0 -; SI-NEXT: v_add_f32_e64 v13, s11, 1.0 -; SI-NEXT: v_add_f32_e64 v11, s10, 1.0 -; SI-NEXT: v_add_f32_e64 v9, s8, 1.0 -; SI-NEXT: v_add_f32_e64 v7, s7, 1.0 -; SI-NEXT: v_add_f32_e64 v5, s6, 1.0 -; SI-NEXT: v_add_f32_e64 v3, s9, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v1 -; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v2 -; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v4 -; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v6 -; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v8 -; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v10 -; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v12 -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v14 -; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v16 -; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v19 -; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v20 -; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v18 -; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v17 -; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v15 -; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v13 -; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v11 -; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v9 -; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v7 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v5 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v5, v5 -; SI-NEXT: v_cvt_f32_f16_e32 v7, v7 -; SI-NEXT: v_cvt_f32_f16_e32 v9, v9 -; SI-NEXT: v_cvt_f32_f16_e32 v11, v11 -; SI-NEXT: v_cvt_f32_f16_e32 v13, v13 -; SI-NEXT: v_cvt_f32_f16_e32 v15, v15 -; SI-NEXT: v_cvt_f32_f16_e32 v17, v17 -; SI-NEXT: v_cvt_f32_f16_e32 v18, v18 -; SI-NEXT: v_cvt_f32_f16_e32 v20, v20 -; SI-NEXT: v_cvt_f32_f16_e32 v22, v19 -; SI-NEXT: v_cvt_f32_f16_e32 v24, v16 -; SI-NEXT: v_cvt_f32_f16_e32 v26, v14 -; SI-NEXT: v_cvt_f32_f16_e32 v28, v12 -; SI-NEXT: v_cvt_f32_f16_e32 v30, v10 -; SI-NEXT: v_cvt_f32_f16_e32 v32, v8 -; SI-NEXT: v_cvt_f32_f16_e32 v33, v6 -; SI-NEXT: v_cvt_f32_f16_e32 v35, v4 -; SI-NEXT: v_cvt_f32_f16_e32 v37, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v39, v1 -; SI-NEXT: v_cvt_f32_f16_e32 v1, v42 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v41 -; SI-NEXT: v_cvt_f32_f16_e32 v4, v40 -; SI-NEXT: v_cvt_f32_f16_e32 v6, v55 -; SI-NEXT: v_cvt_f32_f16_e32 v8, v54 -; SI-NEXT: v_cvt_f32_f16_e32 v10, v53 -; SI-NEXT: v_cvt_f32_f16_e32 v12, v52 -; SI-NEXT: v_cvt_f32_f16_e32 v14, v51 -; SI-NEXT: v_cvt_f32_f16_e32 v16, v50 -; SI-NEXT: v_cvt_f32_f16_e32 v19, v49 +; SI-NEXT: v_add_f32_e32 v7, 1.0, v60 +; SI-NEXT: v_add_f32_e32 v8, 1.0, v59 +; SI-NEXT: v_add_f32_e32 v10, 1.0, v58 +; SI-NEXT: v_add_f32_e32 v12, 1.0, v57 +; SI-NEXT: v_add_f32_e32 v14, 1.0, v56 +; SI-NEXT: v_add_f32_e32 v16, 1.0, v47 +; SI-NEXT: v_add_f32_e32 v18, 1.0, v46 +; SI-NEXT: v_add_f32_e32 v20, 1.0, v45 +; SI-NEXT: v_add_f32_e32 v22, 1.0, v44 +; SI-NEXT: v_add_f32_e32 v25, 1.0, v41 +; SI-NEXT: v_add_f32_e32 v26, 1.0, v40 +; SI-NEXT: v_add_f32_e32 v24, 1.0, v55 +; SI-NEXT: v_add_f32_e32 v23, 1.0, v42 +; SI-NEXT: v_add_f32_e32 v21, 1.0, v43 +; SI-NEXT: v_add_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_add_f32_e32 v2, 1.0, v2 +; SI-NEXT: v_add_f32_e32 v3, 1.0, v3 +; SI-NEXT: v_add_f32_e32 v4, 1.0, v4 +; SI-NEXT: v_add_f32_e32 v5, 1.0, v5 +; SI-NEXT: v_add_f32_e32 v6, 1.0, v6 +; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v7 +; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v8 +; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v10 +; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v12 +; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v14 +; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v16 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v18 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v20 +; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v22 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v25 +; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v26 +; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v24 +; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v23 +; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v21 +; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v1 +; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v2 +; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v3 +; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v4 +; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v5 +; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v6 +; SI-NEXT: v_cvt_f32_f16_e32 v9, v6 +; SI-NEXT: v_cvt_f32_f16_e32 v11, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v13, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v15, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v17, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v19, v1 ; SI-NEXT: v_cvt_f32_f16_e32 v21, v21 ; SI-NEXT: v_cvt_f32_f16_e32 v23, v23 -; SI-NEXT: v_cvt_f32_f16_e32 v25, v25 +; SI-NEXT: v_cvt_f32_f16_e32 v24, v24 +; SI-NEXT: v_cvt_f32_f16_e32 v26, v26 +; SI-NEXT: v_cvt_f32_f16_e32 v28, v25 +; SI-NEXT: v_cvt_f32_f16_e32 v30, v22 +; SI-NEXT: v_cvt_f32_f16_e32 v32, v20 +; SI-NEXT: v_cvt_f32_f16_e32 v34, v18 +; SI-NEXT: v_cvt_f32_f16_e32 v36, v16 +; SI-NEXT: v_cvt_f32_f16_e32 v38, v14 +; SI-NEXT: v_cvt_f32_f16_e32 v39, v12 +; SI-NEXT: v_cvt_f32_f16_e32 v49, v10 +; SI-NEXT: v_cvt_f32_f16_e32 v51, v8 +; SI-NEXT: v_cvt_f32_f16_e32 v53, v7 +; SI-NEXT: v_cvt_f32_f16_e32 v7, v56 +; SI-NEXT: v_cvt_f32_f16_e32 v8, v47 +; SI-NEXT: v_cvt_f32_f16_e32 v10, v46 +; SI-NEXT: v_cvt_f32_f16_e32 v12, v45 +; SI-NEXT: v_cvt_f32_f16_e32 v14, v44 +; SI-NEXT: v_cvt_f32_f16_e32 v16, v43 +; SI-NEXT: v_cvt_f32_f16_e32 v18, v42 +; SI-NEXT: v_cvt_f32_f16_e32 v20, v41 +; SI-NEXT: v_cvt_f32_f16_e32 v22, v55 +; SI-NEXT: v_cvt_f32_f16_e32 v25, v40 ; SI-NEXT: v_cvt_f32_f16_e32 v27, v27 ; SI-NEXT: v_cvt_f32_f16_e32 v29, v29 ; SI-NEXT: v_cvt_f32_f16_e32 v31, v31 -; SI-NEXT: v_cvt_f32_f16_e32 v34, v34 -; SI-NEXT: v_cvt_f32_f16_e32 v36, v36 -; SI-NEXT: v_cvt_f32_f16_e32 v38, v38 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v33 +; SI-NEXT: v_cvt_f32_f16_e32 v35, v35 +; SI-NEXT: v_cvt_f32_f16_e32 v37, v37 ; SI-NEXT: v_cvt_f32_f16_e32 v48, v48 +; SI-NEXT: v_cvt_f32_f16_e32 v50, v50 +; SI-NEXT: v_cvt_f32_f16_e32 v52, v52 +; SI-NEXT: v_cvt_f32_f16_e32 v54, v54 ; SI-NEXT: .LBB33_3: ; %end -; SI-NEXT: v_cvt_f16_f32_e32 v48, v48 -; SI-NEXT: v_cvt_f16_f32_e32 v39, v39 -; SI-NEXT: v_cvt_f16_f32_e32 v38, v38 -; SI-NEXT: v_cvt_f16_f32_e32 v37, v37 -; SI-NEXT: v_cvt_f16_f32_e32 v36, v36 -; SI-NEXT: v_cvt_f16_f32_e32 v35, v35 -; SI-NEXT: v_cvt_f16_f32_e32 v34, v34 -; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v48 -; SI-NEXT: v_cvt_f16_f32_e32 v33, v33 -; SI-NEXT: v_cvt_f16_f32_e32 v31, v31 -; SI-NEXT: v_or_b32_e32 v39, v39, v48 -; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v38 -; SI-NEXT: v_cvt_f16_f32_e32 v32, v32 -; SI-NEXT: v_cvt_f16_f32_e32 v29, v29 -; SI-NEXT: buffer_store_dword v39, v0, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v54 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v53 +; SI-NEXT: v_cvt_f16_f32_e32 v3, v52 +; SI-NEXT: v_cvt_f16_f32_e32 v4, v51 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3 +; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v39, vcc, 4, v0 -; SI-NEXT: v_or_b32_e32 v37, v37, v38 -; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v36 -; SI-NEXT: v_cvt_f16_f32_e32 v30, v30 -; SI-NEXT: v_cvt_f16_f32_e32 v27, v27 -; SI-NEXT: buffer_store_dword v37, v39, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0 +; SI-NEXT: v_or_b32_e32 v2, v4, v2 +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v50 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v37, vcc, 8, v0 -; SI-NEXT: v_or_b32_e32 v35, v35, v36 -; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v34 -; SI-NEXT: v_cvt_f16_f32_e32 v28, v28 -; SI-NEXT: v_cvt_f16_f32_e32 v25, v25 -; SI-NEXT: buffer_store_dword v35, v37, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v2, v49 +; SI-NEXT: v_add_i32_e32 v3, vcc, 8, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v35, vcc, 12, v0 -; SI-NEXT: v_or_b32_e32 v33, v33, v34 -; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31 -; SI-NEXT: v_cvt_f16_f32_e32 v26, v26 -; SI-NEXT: v_cvt_f16_f32_e32 v23, v23 -; SI-NEXT: buffer_store_dword v33, v35, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v48 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v39 +; SI-NEXT: v_add_i32_e32 v3, vcc, 12, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v33, vcc, 16, v0 -; SI-NEXT: v_or_b32_e32 v31, v32, v31 -; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29 -; SI-NEXT: v_cvt_f16_f32_e32 v24, v24 -; SI-NEXT: v_cvt_f16_f32_e32 v21, v21 -; SI-NEXT: buffer_store_dword v31, v33, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v37 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v38 +; SI-NEXT: v_add_i32_e32 v3, vcc, 16, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v31, vcc, 20, v0 -; SI-NEXT: v_or_b32_e32 v29, v30, v29 -; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27 -; SI-NEXT: v_cvt_f16_f32_e32 v22, v22 -; SI-NEXT: v_cvt_f16_f32_e32 v19, v19 -; SI-NEXT: buffer_store_dword v29, v31, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v35 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v36 +; SI-NEXT: v_add_i32_e32 v3, vcc, 20, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v29, vcc, 24, v0 -; SI-NEXT: v_or_b32_e32 v27, v28, v27 -; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; SI-NEXT: v_cvt_f16_f32_e32 v20, v20 -; SI-NEXT: v_cvt_f16_f32_e32 v16, v16 -; SI-NEXT: buffer_store_dword v27, v29, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v33 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v34 +; SI-NEXT: v_add_i32_e32 v3, vcc, 24, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v27, vcc, 28, v0 -; SI-NEXT: v_or_b32_e32 v25, v26, v25 -; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; SI-NEXT: v_cvt_f16_f32_e32 v18, v18 -; SI-NEXT: buffer_store_dword v25, v27, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v31 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v32 +; SI-NEXT: v_add_i32_e32 v3, vcc, 28, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v25, vcc, 32, v0 -; SI-NEXT: v_or_b32_e32 v23, v24, v23 -; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; SI-NEXT: buffer_store_dword v23, v25, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v29 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v30 +; SI-NEXT: v_add_i32_e32 v3, vcc, 32, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v23, vcc, 36, v0 -; SI-NEXT: v_or_b32_e32 v21, v22, v21 -; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; SI-NEXT: buffer_store_dword v21, v23, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v27 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v28 +; SI-NEXT: v_add_i32_e32 v3, vcc, 36, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v21, vcc, 40, v0 -; SI-NEXT: v_or_b32_e32 v19, v20, v19 -; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; SI-NEXT: buffer_store_dword v19, v21, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v25 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v26 +; SI-NEXT: v_add_i32_e32 v3, vcc, 40, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v19, vcc, 44, v0 -; SI-NEXT: v_or_b32_e32 v16, v18, v16 -; SI-NEXT: v_cvt_f16_f32_e32 v14, v14 -; SI-NEXT: buffer_store_dword v16, v19, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v22 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v24 +; SI-NEXT: v_add_i32_e32 v3, vcc, 44, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v16, v17 -; SI-NEXT: v_add_i32_e32 v17, vcc, 48, v0 -; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; SI-NEXT: v_or_b32_e32 v14, v16, v14 -; SI-NEXT: v_cvt_f16_f32_e32 v12, v12 -; SI-NEXT: buffer_store_dword v14, v17, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v20 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v23 +; SI-NEXT: v_add_i32_e32 v3, vcc, 48, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v14, v15 -; SI-NEXT: v_add_i32_e32 v15, vcc, 52, v0 -; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; SI-NEXT: v_or_b32_e32 v12, v14, v12 -; SI-NEXT: v_cvt_f16_f32_e32 v10, v10 -; SI-NEXT: buffer_store_dword v12, v15, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v18 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v21 +; SI-NEXT: v_add_i32_e32 v3, vcc, 52, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v12, v13 -; SI-NEXT: v_add_i32_e32 v13, vcc, 56, v0 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v12, v10 -; SI-NEXT: v_cvt_f16_f32_e32 v8, v8 -; SI-NEXT: buffer_store_dword v10, v13, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v16 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v19 +; SI-NEXT: v_add_i32_e32 v3, vcc, 56, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v10, v11 -; SI-NEXT: v_add_i32_e32 v11, vcc, 60, v0 -; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; SI-NEXT: v_or_b32_e32 v8, v10, v8 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v6 -; SI-NEXT: buffer_store_dword v8, v11, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v14 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v17 +; SI-NEXT: v_add_i32_e32 v3, vcc, 60, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v8, v9 -; SI-NEXT: v_add_i32_e32 v9, vcc, 64, v0 -; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; SI-NEXT: v_or_b32_e32 v6, v8, v6 -; SI-NEXT: v_cvt_f16_f32_e32 v4, v4 -; SI-NEXT: buffer_store_dword v6, v9, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v12 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v15 +; SI-NEXT: v_add_i32_e32 v3, vcc, 64, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v6, v7 -; SI-NEXT: v_add_i32_e32 v7, vcc, 0x44, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v6, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: buffer_store_dword v4, v7, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v10 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v13 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x44, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v5 -; SI-NEXT: v_add_i32_e32 v5, vcc, 0x48, v0 -; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; SI-NEXT: v_or_b32_e32 v2, v4, v2 -; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 -; SI-NEXT: buffer_store_dword v2, v5, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v8 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v11 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x48, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v2, v3 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v7 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v9 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x4c, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] ; SI-NEXT: .LBB33_4: +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr54 +; SI-NEXT: ; implicit-def: $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr52 +; SI-NEXT: ; implicit-def: $vgpr49 +; SI-NEXT: ; implicit-def: $vgpr50 ; SI-NEXT: ; implicit-def: $vgpr39 ; SI-NEXT: ; implicit-def: $vgpr48 -; SI-NEXT: ; implicit-def: $vgpr37 ; SI-NEXT: ; implicit-def: $vgpr38 -; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr37 ; SI-NEXT: ; implicit-def: $vgpr36 -; SI-NEXT: ; implicit-def: $vgpr33 +; SI-NEXT: ; implicit-def: $vgpr35 ; SI-NEXT: ; implicit-def: $vgpr34 +; SI-NEXT: ; implicit-def: $vgpr33 ; SI-NEXT: ; implicit-def: $vgpr32 ; SI-NEXT: ; implicit-def: $vgpr31 ; SI-NEXT: ; implicit-def: $vgpr30 @@ -14596,12 +14337,12 @@ define inreg <40 x half> @bitcast_v20f32_to_v40f16_scalar(<20 x float> inreg %a, ; SI-NEXT: ; implicit-def: $vgpr26 ; SI-NEXT: ; implicit-def: $vgpr25 ; SI-NEXT: ; implicit-def: $vgpr24 -; SI-NEXT: ; implicit-def: $vgpr23 ; SI-NEXT: ; implicit-def: $vgpr22 -; SI-NEXT: ; implicit-def: $vgpr21 +; SI-NEXT: ; implicit-def: $vgpr23 ; SI-NEXT: ; implicit-def: $vgpr20 -; SI-NEXT: ; implicit-def: $vgpr19 +; SI-NEXT: ; implicit-def: $vgpr21 ; SI-NEXT: ; implicit-def: $vgpr18 +; SI-NEXT: ; implicit-def: $vgpr19 ; SI-NEXT: ; implicit-def: $vgpr16 ; SI-NEXT: ; implicit-def: $vgpr17 ; SI-NEXT: ; implicit-def: $vgpr14 @@ -14612,13 +14353,7 @@ define inreg <40 x half> @bitcast_v20f32_to_v40f16_scalar(<20 x float> inreg %a, ; SI-NEXT: ; implicit-def: $vgpr11 ; SI-NEXT: ; implicit-def: $vgpr8 ; SI-NEXT: ; implicit-def: $vgpr9 -; SI-NEXT: ; implicit-def: $vgpr6 ; SI-NEXT: ; implicit-def: $vgpr7 -; SI-NEXT: ; implicit-def: $vgpr4 -; SI-NEXT: ; implicit-def: $vgpr5 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr3 -; SI-NEXT: ; implicit-def: $vgpr1 ; SI-NEXT: s_branch .LBB33_2 ; ; VI-LABEL: bitcast_v20f32_to_v40f16_scalar: @@ -16833,269 +16568,100 @@ define inreg <20 x float> @bitcast_v40f16_to_v20f32_scalar(<40 x half> inreg %a, ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44 -; GFX11-TRUE16-NEXT: s_clause 0xa -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB35_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB35_3 ; GFX11-TRUE16-NEXT: .LBB35_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s40 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s41 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v186, 0x200, v186 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v185, 0x200, v185 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s0 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s1 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s2 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, s3 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, s4 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v35, 0x200, s5 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v44, 0x200, s6 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v54, 0x200, s7 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v65, 0x200, s8 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v77, 0x200, s9 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v90, 0x200, s10 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v104, 0x200, s11 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v119, 0x200, s12 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v135, 0x200, s13 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v152, 0x200, s14 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v170, 0x200, s15 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, s6 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, s7 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, s8 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s9 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, s10 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, s11 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, s12 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, s13 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s14 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, s15 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, s16 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: .LBB35_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v17, v170 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v186 :: v_dual_mov_b32 v19, v185 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xa -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:296 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v14, v119 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB35_4: -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB35_2 ; ; GFX11-FAKE16-LABEL: bitcast_v40f16_to_v20f32_scalar: @@ -18545,36 +18111,64 @@ define inreg <40 x i16> @bitcast_v10i64_to_v40i16_scalar(<10 x i64> inreg %a, i3 ; SI-LABEL: bitcast_v10i64_to_v40i16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v8, s16 +; SI-NEXT: v_mov_b32_e32 v9, s17 +; SI-NEXT: v_mov_b32_e32 v10, s18 +; SI-NEXT: v_mov_b32_e32 v11, s19 +; SI-NEXT: v_mov_b32_e32 v12, s20 +; SI-NEXT: v_mov_b32_e32 v13, s21 +; SI-NEXT: v_mov_b32_e32 v14, s22 +; SI-NEXT: v_mov_b32_e32 v15, s23 +; SI-NEXT: v_mov_b32_e32 v16, s24 +; SI-NEXT: v_mov_b32_e32 v17, s25 +; SI-NEXT: v_mov_b32_e32 v18, s26 +; SI-NEXT: v_mov_b32_e32 v19, s27 +; SI-NEXT: v_readfirstlane_b32 s22, v8 +; SI-NEXT: v_mov_b32_e32 v8, s28 +; SI-NEXT: v_readfirstlane_b32 s23, v9 +; SI-NEXT: v_mov_b32_e32 v9, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 +; SI-NEXT: v_readfirstlane_b32 s20, v10 +; SI-NEXT: v_readfirstlane_b32 s21, v11 +; SI-NEXT: v_readfirstlane_b32 s18, v12 +; SI-NEXT: v_readfirstlane_b32 s19, v13 +; SI-NEXT: v_readfirstlane_b32 s16, v14 +; SI-NEXT: v_readfirstlane_b32 s17, v15 +; SI-NEXT: v_readfirstlane_b32 s14, v16 +; SI-NEXT: v_readfirstlane_b32 s15, v17 +; SI-NEXT: v_readfirstlane_b32 s12, v18 +; SI-NEXT: v_readfirstlane_b32 s13, v19 +; SI-NEXT: v_readfirstlane_b32 s10, v8 +; SI-NEXT: v_readfirstlane_b32 s11, v9 ; SI-NEXT: v_readfirstlane_b32 s8, v1 ; SI-NEXT: v_readfirstlane_b32 s9, v2 ; SI-NEXT: v_readfirstlane_b32 s6, v3 ; SI-NEXT: v_readfirstlane_b32 s7, v4 ; SI-NEXT: v_readfirstlane_b32 s4, v5 -; SI-NEXT: s_and_b64 s[10:11], vcc, exec +; SI-NEXT: s_and_b64 s[24:25], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v6 ; SI-NEXT: s_cbranch_scc0 .LBB41_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s72, s5, 16 ; SI-NEXT: s_lshr_b32 s73, s7, 16 ; SI-NEXT: s_lshr_b32 s74, s9, 16 -; SI-NEXT: s_lshr_b32 s75, s29, 16 -; SI-NEXT: s_lshr_b32 s76, s27, 16 -; SI-NEXT: s_lshr_b32 s77, s25, 16 -; SI-NEXT: s_lshr_b32 s78, s23, 16 -; SI-NEXT: s_lshr_b32 s79, s21, 16 -; SI-NEXT: s_lshr_b32 s88, s19, 16 -; SI-NEXT: s_lshr_b32 s89, s17, 16 -; SI-NEXT: s_lshr_b64 s[10:11], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[12:13], s[6:7], 16 -; SI-NEXT: s_lshr_b64 s[14:15], s[8:9], 16 -; SI-NEXT: s_lshr_b64 s[40:41], s[28:29], 16 -; SI-NEXT: s_lshr_b64 s[42:43], s[26:27], 16 -; SI-NEXT: s_lshr_b64 s[44:45], s[24:25], 16 -; SI-NEXT: s_lshr_b64 s[46:47], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[56:57], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[58:59], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[60:61], s[16:17], 16 +; SI-NEXT: s_lshr_b32 s75, s11, 16 +; SI-NEXT: s_lshr_b32 s76, s13, 16 +; SI-NEXT: s_lshr_b32 s77, s15, 16 +; SI-NEXT: s_lshr_b32 s78, s17, 16 +; SI-NEXT: s_lshr_b32 s79, s19, 16 +; SI-NEXT: s_lshr_b32 s88, s21, 16 +; SI-NEXT: s_lshr_b32 s89, s23, 16 +; SI-NEXT: s_lshr_b64 s[24:25], s[4:5], 16 +; SI-NEXT: s_lshr_b64 s[26:27], s[6:7], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[8:9], 16 +; SI-NEXT: s_lshr_b64 s[40:41], s[10:11], 16 +; SI-NEXT: s_lshr_b64 s[42:43], s[12:13], 16 +; SI-NEXT: s_lshr_b64 s[44:45], s[14:15], 16 +; SI-NEXT: s_lshr_b64 s[46:47], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[56:57], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[58:59], s[20:21], 16 +; SI-NEXT: s_lshr_b64 s[60:61], s[22:23], 16 ; SI-NEXT: s_cbranch_execnz .LBB41_3 ; SI-NEXT: .LBB41_2: ; %cmp.true ; SI-NEXT: s_add_u32 s4, s4, 3 @@ -18583,139 +18177,139 @@ define inreg <40 x i16> @bitcast_v10i64_to_v40i16_scalar(<10 x i64> inreg %a, i3 ; SI-NEXT: s_addc_u32 s7, s7, 0 ; SI-NEXT: s_add_u32 s8, s8, 3 ; SI-NEXT: s_addc_u32 s9, s9, 0 -; SI-NEXT: s_add_u32 s28, s28, 3 -; SI-NEXT: s_addc_u32 s29, s29, 0 -; SI-NEXT: s_add_u32 s26, s26, 3 -; SI-NEXT: s_addc_u32 s27, s27, 0 -; SI-NEXT: s_add_u32 s24, s24, 3 -; SI-NEXT: s_addc_u32 s25, s25, 0 -; SI-NEXT: s_add_u32 s22, s22, 3 -; SI-NEXT: s_addc_u32 s23, s23, 0 -; SI-NEXT: s_add_u32 s20, s20, 3 -; SI-NEXT: s_addc_u32 s21, s21, 0 -; SI-NEXT: s_add_u32 s18, s18, 3 -; SI-NEXT: s_addc_u32 s19, s19, 0 +; SI-NEXT: s_add_u32 s10, s10, 3 +; SI-NEXT: s_addc_u32 s11, s11, 0 +; SI-NEXT: s_add_u32 s12, s12, 3 +; SI-NEXT: s_addc_u32 s13, s13, 0 +; SI-NEXT: s_add_u32 s14, s14, 3 +; SI-NEXT: s_addc_u32 s15, s15, 0 ; SI-NEXT: s_add_u32 s16, s16, 3 ; SI-NEXT: s_addc_u32 s17, s17, 0 +; SI-NEXT: s_add_u32 s18, s18, 3 +; SI-NEXT: s_addc_u32 s19, s19, 0 +; SI-NEXT: s_add_u32 s20, s20, 3 +; SI-NEXT: s_addc_u32 s21, s21, 0 +; SI-NEXT: s_add_u32 s22, s22, 3 +; SI-NEXT: s_addc_u32 s23, s23, 0 ; SI-NEXT: s_lshr_b32 s72, s5, 16 ; SI-NEXT: s_lshr_b32 s73, s7, 16 ; SI-NEXT: s_lshr_b32 s74, s9, 16 -; SI-NEXT: s_lshr_b32 s75, s29, 16 -; SI-NEXT: s_lshr_b32 s76, s27, 16 -; SI-NEXT: s_lshr_b32 s77, s25, 16 -; SI-NEXT: s_lshr_b32 s78, s23, 16 -; SI-NEXT: s_lshr_b32 s79, s21, 16 -; SI-NEXT: s_lshr_b32 s88, s19, 16 -; SI-NEXT: s_lshr_b32 s89, s17, 16 -; SI-NEXT: s_lshr_b64 s[10:11], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[12:13], s[6:7], 16 -; SI-NEXT: s_lshr_b64 s[14:15], s[8:9], 16 -; SI-NEXT: s_lshr_b64 s[40:41], s[28:29], 16 -; SI-NEXT: s_lshr_b64 s[42:43], s[26:27], 16 -; SI-NEXT: s_lshr_b64 s[44:45], s[24:25], 16 -; SI-NEXT: s_lshr_b64 s[46:47], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[56:57], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[58:59], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[60:61], s[16:17], 16 +; SI-NEXT: s_lshr_b32 s75, s11, 16 +; SI-NEXT: s_lshr_b32 s76, s13, 16 +; SI-NEXT: s_lshr_b32 s77, s15, 16 +; SI-NEXT: s_lshr_b32 s78, s17, 16 +; SI-NEXT: s_lshr_b32 s79, s19, 16 +; SI-NEXT: s_lshr_b32 s88, s21, 16 +; SI-NEXT: s_lshr_b32 s89, s23, 16 +; SI-NEXT: s_lshr_b64 s[24:25], s[4:5], 16 +; SI-NEXT: s_lshr_b64 s[26:27], s[6:7], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[8:9], 16 +; SI-NEXT: s_lshr_b64 s[40:41], s[10:11], 16 +; SI-NEXT: s_lshr_b64 s[42:43], s[12:13], 16 +; SI-NEXT: s_lshr_b64 s[44:45], s[14:15], 16 +; SI-NEXT: s_lshr_b64 s[46:47], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[56:57], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[58:59], s[20:21], 16 +; SI-NEXT: s_lshr_b64 s[60:61], s[22:23], 16 ; SI-NEXT: .LBB41_3: ; %end -; SI-NEXT: s_lshl_b32 s11, s60, 16 -; SI-NEXT: s_and_b32 s13, s16, 0xffff -; SI-NEXT: s_or_b32 s11, s13, s11 -; SI-NEXT: v_mov_b32_e32 v1, s11 -; SI-NEXT: s_and_b32 s11, s17, 0xffff -; SI-NEXT: s_lshl_b32 s13, s89, 16 -; SI-NEXT: s_or_b32 s11, s11, s13 -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_lshl_b32 s11, s58, 16 -; SI-NEXT: s_and_b32 s13, s18, 0xffff -; SI-NEXT: s_or_b32 s11, s13, s11 +; SI-NEXT: s_lshl_b32 s25, s60, 16 +; SI-NEXT: s_and_b32 s22, s22, 0xffff +; SI-NEXT: s_or_b32 s22, s22, s25 +; SI-NEXT: v_mov_b32_e32 v1, s22 +; SI-NEXT: s_and_b32 s22, s23, 0xffff +; SI-NEXT: s_lshl_b32 s23, s89, 16 +; SI-NEXT: s_or_b32 s22, s22, s23 +; SI-NEXT: v_mov_b32_e32 v2, s22 +; SI-NEXT: s_lshl_b32 s22, s58, 16 +; SI-NEXT: s_and_b32 s20, s20, 0xffff +; SI-NEXT: s_or_b32 s20, s20, s22 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s19, 0xffff -; SI-NEXT: s_lshl_b32 s13, s88, 16 +; SI-NEXT: v_mov_b32_e32 v2, s20 +; SI-NEXT: s_and_b32 s20, s21, 0xffff +; SI-NEXT: s_lshl_b32 s21, s88, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s20, s20, s21 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s20, 0xffff -; SI-NEXT: s_lshl_b32 s13, s56, 16 +; SI-NEXT: v_mov_b32_e32 v2, s20 +; SI-NEXT: s_and_b32 s18, s18, 0xffff +; SI-NEXT: s_lshl_b32 s20, s56, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 12, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s18, s18, s20 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s21, 0xffff -; SI-NEXT: s_lshl_b32 s13, s79, 16 +; SI-NEXT: v_mov_b32_e32 v2, s18 +; SI-NEXT: s_and_b32 s18, s19, 0xffff +; SI-NEXT: s_lshl_b32 s19, s79, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s18, s18, s19 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s22, 0xffff -; SI-NEXT: s_lshl_b32 s13, s46, 16 +; SI-NEXT: v_mov_b32_e32 v2, s18 +; SI-NEXT: s_and_b32 s16, s16, 0xffff +; SI-NEXT: s_lshl_b32 s18, s46, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 20, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s16, s16, s18 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s23, 0xffff -; SI-NEXT: s_lshl_b32 s13, s78, 16 +; SI-NEXT: v_mov_b32_e32 v2, s16 +; SI-NEXT: s_and_b32 s16, s17, 0xffff +; SI-NEXT: s_lshl_b32 s17, s78, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s16, s16, s17 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s24, 0xffff -; SI-NEXT: s_lshl_b32 s13, s44, 16 +; SI-NEXT: v_mov_b32_e32 v2, s16 +; SI-NEXT: s_and_b32 s14, s14, 0xffff +; SI-NEXT: s_lshl_b32 s16, s44, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 28, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s14, s14, s16 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s25, 0xffff -; SI-NEXT: s_lshl_b32 s13, s77, 16 +; SI-NEXT: v_mov_b32_e32 v2, s14 +; SI-NEXT: s_and_b32 s14, s15, 0xffff +; SI-NEXT: s_lshl_b32 s15, s77, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s14, s14, s15 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s26, 0xffff -; SI-NEXT: s_lshl_b32 s13, s42, 16 +; SI-NEXT: v_mov_b32_e32 v2, s14 +; SI-NEXT: s_and_b32 s12, s12, 0xffff +; SI-NEXT: s_lshl_b32 s14, s42, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 36, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s12, s12, s14 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s27, 0xffff +; SI-NEXT: v_mov_b32_e32 v2, s12 +; SI-NEXT: s_and_b32 s12, s13, 0xffff ; SI-NEXT: s_lshl_b32 s13, s76, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s12, s12, s13 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s28, 0xffff -; SI-NEXT: s_lshl_b32 s13, s40, 16 +; SI-NEXT: v_mov_b32_e32 v2, s12 +; SI-NEXT: s_and_b32 s10, s10, 0xffff +; SI-NEXT: s_lshl_b32 s12, s40, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 44, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s10, s10, s12 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 -; SI-NEXT: s_and_b32 s11, s29, 0xffff -; SI-NEXT: s_lshl_b32 s13, s75, 16 +; SI-NEXT: v_mov_b32_e32 v2, s10 +; SI-NEXT: s_and_b32 s10, s11, 0xffff +; SI-NEXT: s_lshl_b32 s11, s75, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0 -; SI-NEXT: s_or_b32 s11, s11, s13 +; SI-NEXT: s_or_b32 s10, s10, s11 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s11 +; SI-NEXT: v_mov_b32_e32 v2, s10 ; SI-NEXT: s_and_b32 s8, s8, 0xffff -; SI-NEXT: s_lshl_b32 s11, s14, 16 +; SI-NEXT: s_lshl_b32 s10, s28, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 52, v0 -; SI-NEXT: s_or_b32 s8, s8, s11 +; SI-NEXT: s_or_b32 s8, s8, s10 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s8 @@ -18727,7 +18321,7 @@ define inreg <40 x i16> @bitcast_v10i64_to_v40i16_scalar(<10 x i64> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s8 ; SI-NEXT: s_and_b32 s6, s6, 0xffff -; SI-NEXT: s_lshl_b32 s8, s12, 16 +; SI-NEXT: s_lshl_b32 s8, s26, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 60, v0 ; SI-NEXT: s_or_b32 s6, s6, s8 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen @@ -18741,7 +18335,7 @@ define inreg <40 x i16> @bitcast_v10i64_to_v40i16_scalar(<10 x i64> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s6 ; SI-NEXT: s_and_b32 s4, s4, 0xffff -; SI-NEXT: s_lshl_b32 s6, s10, 16 +; SI-NEXT: s_lshl_b32 s6, s24, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x44, v0 ; SI-NEXT: s_or_b32 s4, s4, s6 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen @@ -18772,18 +18366,46 @@ define inreg <40 x i16> @bitcast_v10i64_to_v40i16_scalar(<10 x i64> inreg %a, i3 ; SI-NEXT: ; implicit-def: $sgpr76 ; SI-NEXT: ; implicit-def: $sgpr40 ; SI-NEXT: ; implicit-def: $sgpr75 -; SI-NEXT: ; implicit-def: $sgpr14 +; SI-NEXT: ; implicit-def: $sgpr28 ; SI-NEXT: ; implicit-def: $sgpr74 -; SI-NEXT: ; implicit-def: $sgpr12 +; SI-NEXT: ; implicit-def: $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr73 -; SI-NEXT: ; implicit-def: $sgpr10 +; SI-NEXT: ; implicit-def: $sgpr24 ; SI-NEXT: ; implicit-def: $sgpr72 ; SI-NEXT: s_branch .LBB41_2 ; ; VI-LABEL: bitcast_v10i64_to_v40i16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v7, s16 +; VI-NEXT: v_mov_b32_e32 v8, s17 +; VI-NEXT: v_mov_b32_e32 v9, s18 +; VI-NEXT: v_mov_b32_e32 v10, s19 +; VI-NEXT: v_mov_b32_e32 v11, s20 +; VI-NEXT: v_mov_b32_e32 v12, s21 +; VI-NEXT: v_mov_b32_e32 v13, s22 +; VI-NEXT: v_mov_b32_e32 v14, s23 +; VI-NEXT: v_mov_b32_e32 v15, s24 +; VI-NEXT: v_mov_b32_e32 v16, s25 +; VI-NEXT: v_mov_b32_e32 v17, s26 +; VI-NEXT: v_mov_b32_e32 v18, s27 +; VI-NEXT: v_mov_b32_e32 v19, s28 +; VI-NEXT: v_readfirstlane_b32 s25, v7 +; VI-NEXT: v_mov_b32_e32 v7, s29 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 +; VI-NEXT: v_readfirstlane_b32 s24, v8 +; VI-NEXT: v_readfirstlane_b32 s23, v9 +; VI-NEXT: v_readfirstlane_b32 s22, v10 +; VI-NEXT: v_readfirstlane_b32 s21, v11 +; VI-NEXT: v_readfirstlane_b32 s20, v12 +; VI-NEXT: v_readfirstlane_b32 s19, v13 +; VI-NEXT: v_readfirstlane_b32 s18, v14 +; VI-NEXT: v_readfirstlane_b32 s17, v15 +; VI-NEXT: v_readfirstlane_b32 s16, v16 +; VI-NEXT: v_readfirstlane_b32 s15, v17 +; VI-NEXT: v_readfirstlane_b32 s14, v18 +; VI-NEXT: v_readfirstlane_b32 s13, v19 +; VI-NEXT: v_readfirstlane_b32 s12, v7 ; VI-NEXT: v_readfirstlane_b32 s11, v0 ; VI-NEXT: v_readfirstlane_b32 s10, v1 ; VI-NEXT: v_readfirstlane_b32 s9, v2 @@ -18793,26 +18415,26 @@ define inreg <40 x i16> @bitcast_v10i64_to_v40i16_scalar(<10 x i64> inreg %a, i3 ; VI-NEXT: v_readfirstlane_b32 s7, v5 ; VI-NEXT: s_cbranch_scc0 .LBB41_4 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_lshr_b32 s12, s7, 16 -; VI-NEXT: s_lshr_b32 s13, s6, 16 -; VI-NEXT: s_lshr_b32 s14, s8, 16 -; VI-NEXT: s_lshr_b32 s15, s9, 16 +; VI-NEXT: s_lshr_b32 s26, s7, 16 +; VI-NEXT: s_lshr_b32 s27, s6, 16 +; VI-NEXT: s_lshr_b32 s28, s8, 16 +; VI-NEXT: s_lshr_b32 s29, s9, 16 ; VI-NEXT: s_lshr_b32 s40, s10, 16 ; VI-NEXT: s_lshr_b32 s41, s11, 16 -; VI-NEXT: s_lshr_b32 s42, s29, 16 -; VI-NEXT: s_lshr_b32 s43, s28, 16 -; VI-NEXT: s_lshr_b32 s44, s27, 16 -; VI-NEXT: s_lshr_b32 s45, s26, 16 -; VI-NEXT: s_lshr_b32 s46, s25, 16 -; VI-NEXT: s_lshr_b32 s47, s24, 16 -; VI-NEXT: s_lshr_b32 s56, s23, 16 -; VI-NEXT: s_lshr_b32 s57, s22, 16 -; VI-NEXT: s_lshr_b32 s58, s21, 16 -; VI-NEXT: s_lshr_b32 s59, s20, 16 -; VI-NEXT: s_lshr_b32 s60, s19, 16 -; VI-NEXT: s_lshr_b32 s61, s18, 16 -; VI-NEXT: s_lshr_b32 s62, s17, 16 -; VI-NEXT: s_lshr_b32 s63, s16, 16 +; VI-NEXT: s_lshr_b32 s42, s12, 16 +; VI-NEXT: s_lshr_b32 s43, s13, 16 +; VI-NEXT: s_lshr_b32 s44, s14, 16 +; VI-NEXT: s_lshr_b32 s45, s15, 16 +; VI-NEXT: s_lshr_b32 s46, s16, 16 +; VI-NEXT: s_lshr_b32 s47, s17, 16 +; VI-NEXT: s_lshr_b32 s56, s18, 16 +; VI-NEXT: s_lshr_b32 s57, s19, 16 +; VI-NEXT: s_lshr_b32 s58, s20, 16 +; VI-NEXT: s_lshr_b32 s59, s21, 16 +; VI-NEXT: s_lshr_b32 s60, s22, 16 +; VI-NEXT: s_lshr_b32 s61, s23, 16 +; VI-NEXT: s_lshr_b32 s62, s24, 16 +; VI-NEXT: s_lshr_b32 s63, s25, 16 ; VI-NEXT: s_cbranch_execnz .LBB41_3 ; VI-NEXT: .LBB41_2: ; %cmp.true ; VI-NEXT: s_add_u32 s6, s6, 3 @@ -18821,115 +18443,115 @@ define inreg <40 x i16> @bitcast_v10i64_to_v40i16_scalar(<10 x i64> inreg %a, i3 ; VI-NEXT: s_addc_u32 s8, s8, 0 ; VI-NEXT: s_add_u32 s11, s11, 3 ; VI-NEXT: s_addc_u32 s10, s10, 0 -; VI-NEXT: s_add_u32 s28, s28, 3 -; VI-NEXT: s_addc_u32 s29, s29, 0 -; VI-NEXT: s_add_u32 s26, s26, 3 -; VI-NEXT: s_addc_u32 s27, s27, 0 -; VI-NEXT: s_add_u32 s24, s24, 3 -; VI-NEXT: s_addc_u32 s25, s25, 0 -; VI-NEXT: s_add_u32 s22, s22, 3 -; VI-NEXT: s_addc_u32 s23, s23, 0 -; VI-NEXT: s_add_u32 s20, s20, 3 -; VI-NEXT: s_addc_u32 s21, s21, 0 -; VI-NEXT: s_add_u32 s18, s18, 3 -; VI-NEXT: s_addc_u32 s19, s19, 0 -; VI-NEXT: s_add_u32 s16, s16, 3 -; VI-NEXT: s_addc_u32 s17, s17, 0 -; VI-NEXT: s_lshr_b32 s12, s7, 16 -; VI-NEXT: s_lshr_b32 s13, s6, 16 -; VI-NEXT: s_lshr_b32 s14, s8, 16 -; VI-NEXT: s_lshr_b32 s15, s9, 16 +; VI-NEXT: s_add_u32 s13, s13, 3 +; VI-NEXT: s_addc_u32 s12, s12, 0 +; VI-NEXT: s_add_u32 s15, s15, 3 +; VI-NEXT: s_addc_u32 s14, s14, 0 +; VI-NEXT: s_add_u32 s17, s17, 3 +; VI-NEXT: s_addc_u32 s16, s16, 0 +; VI-NEXT: s_add_u32 s19, s19, 3 +; VI-NEXT: s_addc_u32 s18, s18, 0 +; VI-NEXT: s_add_u32 s21, s21, 3 +; VI-NEXT: s_addc_u32 s20, s20, 0 +; VI-NEXT: s_add_u32 s23, s23, 3 +; VI-NEXT: s_addc_u32 s22, s22, 0 +; VI-NEXT: s_add_u32 s25, s25, 3 +; VI-NEXT: s_addc_u32 s24, s24, 0 +; VI-NEXT: s_lshr_b32 s26, s7, 16 +; VI-NEXT: s_lshr_b32 s27, s6, 16 +; VI-NEXT: s_lshr_b32 s28, s8, 16 +; VI-NEXT: s_lshr_b32 s29, s9, 16 ; VI-NEXT: s_lshr_b32 s40, s10, 16 ; VI-NEXT: s_lshr_b32 s41, s11, 16 -; VI-NEXT: s_lshr_b32 s42, s29, 16 -; VI-NEXT: s_lshr_b32 s43, s28, 16 -; VI-NEXT: s_lshr_b32 s44, s27, 16 -; VI-NEXT: s_lshr_b32 s45, s26, 16 -; VI-NEXT: s_lshr_b32 s46, s25, 16 -; VI-NEXT: s_lshr_b32 s47, s24, 16 -; VI-NEXT: s_lshr_b32 s56, s23, 16 -; VI-NEXT: s_lshr_b32 s57, s22, 16 -; VI-NEXT: s_lshr_b32 s58, s21, 16 -; VI-NEXT: s_lshr_b32 s59, s20, 16 -; VI-NEXT: s_lshr_b32 s60, s19, 16 -; VI-NEXT: s_lshr_b32 s61, s18, 16 -; VI-NEXT: s_lshr_b32 s62, s17, 16 -; VI-NEXT: s_lshr_b32 s63, s16, 16 +; VI-NEXT: s_lshr_b32 s42, s12, 16 +; VI-NEXT: s_lshr_b32 s43, s13, 16 +; VI-NEXT: s_lshr_b32 s44, s14, 16 +; VI-NEXT: s_lshr_b32 s45, s15, 16 +; VI-NEXT: s_lshr_b32 s46, s16, 16 +; VI-NEXT: s_lshr_b32 s47, s17, 16 +; VI-NEXT: s_lshr_b32 s56, s18, 16 +; VI-NEXT: s_lshr_b32 s57, s19, 16 +; VI-NEXT: s_lshr_b32 s58, s20, 16 +; VI-NEXT: s_lshr_b32 s59, s21, 16 +; VI-NEXT: s_lshr_b32 s60, s22, 16 +; VI-NEXT: s_lshr_b32 s61, s23, 16 +; VI-NEXT: s_lshr_b32 s62, s24, 16 +; VI-NEXT: s_lshr_b32 s63, s25, 16 ; VI-NEXT: .LBB41_3: ; %end -; VI-NEXT: s_and_b32 s4, 0xffff, s16 +; VI-NEXT: s_and_b32 s4, 0xffff, s25 ; VI-NEXT: s_lshl_b32 s5, s63, 16 ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_and_b32 s5, 0xffff, s17 -; VI-NEXT: s_lshl_b32 s16, s62, 16 -; VI-NEXT: s_or_b32 s5, s5, s16 -; VI-NEXT: s_and_b32 s16, 0xffff, s18 -; VI-NEXT: s_lshl_b32 s17, s61, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, 0xffff, s19 -; VI-NEXT: s_lshl_b32 s18, s60, 16 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s18, 0xffff, s20 -; VI-NEXT: s_lshl_b32 s19, s59, 16 -; VI-NEXT: s_or_b32 s18, s18, s19 -; VI-NEXT: s_and_b32 s19, 0xffff, s21 -; VI-NEXT: s_lshl_b32 s20, s58, 16 -; VI-NEXT: s_or_b32 s19, s19, s20 -; VI-NEXT: s_and_b32 s20, 0xffff, s22 -; VI-NEXT: s_lshl_b32 s21, s57, 16 -; VI-NEXT: s_or_b32 s20, s20, s21 -; VI-NEXT: s_and_b32 s21, 0xffff, s23 -; VI-NEXT: s_lshl_b32 s22, s56, 16 -; VI-NEXT: s_or_b32 s21, s21, s22 -; VI-NEXT: s_and_b32 s22, 0xffff, s24 -; VI-NEXT: s_lshl_b32 s23, s47, 16 -; VI-NEXT: s_or_b32 s22, s22, s23 -; VI-NEXT: s_and_b32 s23, 0xffff, s25 -; VI-NEXT: s_lshl_b32 s24, s46, 16 +; VI-NEXT: s_and_b32 s5, 0xffff, s24 +; VI-NEXT: s_lshl_b32 s24, s62, 16 +; VI-NEXT: s_or_b32 s5, s5, s24 +; VI-NEXT: s_and_b32 s23, 0xffff, s23 +; VI-NEXT: s_lshl_b32 s24, s61, 16 ; VI-NEXT: s_or_b32 s23, s23, s24 -; VI-NEXT: s_and_b32 s24, 0xffff, s26 -; VI-NEXT: s_lshl_b32 s25, s45, 16 -; VI-NEXT: s_or_b32 s24, s24, s25 -; VI-NEXT: s_and_b32 s25, 0xffff, s27 -; VI-NEXT: s_lshl_b32 s26, s44, 16 -; VI-NEXT: s_or_b32 s25, s25, s26 -; VI-NEXT: s_and_b32 s26, 0xffff, s28 -; VI-NEXT: s_lshl_b32 s27, s43, 16 -; VI-NEXT: s_or_b32 s26, s26, s27 -; VI-NEXT: s_and_b32 s27, 0xffff, s29 -; VI-NEXT: s_lshl_b32 s28, s42, 16 -; VI-NEXT: s_or_b32 s27, s27, s28 +; VI-NEXT: s_and_b32 s22, 0xffff, s22 +; VI-NEXT: s_lshl_b32 s24, s60, 16 +; VI-NEXT: s_or_b32 s22, s22, s24 +; VI-NEXT: s_and_b32 s21, 0xffff, s21 +; VI-NEXT: s_lshl_b32 s24, s59, 16 +; VI-NEXT: s_or_b32 s21, s21, s24 +; VI-NEXT: s_and_b32 s20, 0xffff, s20 +; VI-NEXT: s_lshl_b32 s24, s58, 16 +; VI-NEXT: s_or_b32 s20, s20, s24 +; VI-NEXT: s_and_b32 s19, 0xffff, s19 +; VI-NEXT: s_lshl_b32 s24, s57, 16 +; VI-NEXT: s_or_b32 s19, s19, s24 +; VI-NEXT: s_and_b32 s18, 0xffff, s18 +; VI-NEXT: s_lshl_b32 s24, s56, 16 +; VI-NEXT: s_or_b32 s18, s18, s24 +; VI-NEXT: s_and_b32 s17, 0xffff, s17 +; VI-NEXT: s_lshl_b32 s24, s47, 16 +; VI-NEXT: s_or_b32 s17, s17, s24 +; VI-NEXT: s_and_b32 s16, 0xffff, s16 +; VI-NEXT: s_lshl_b32 s24, s46, 16 +; VI-NEXT: s_or_b32 s16, s16, s24 +; VI-NEXT: s_and_b32 s15, 0xffff, s15 +; VI-NEXT: s_lshl_b32 s24, s45, 16 +; VI-NEXT: s_or_b32 s15, s15, s24 +; VI-NEXT: s_and_b32 s14, 0xffff, s14 +; VI-NEXT: s_lshl_b32 s24, s44, 16 +; VI-NEXT: s_or_b32 s14, s14, s24 +; VI-NEXT: s_and_b32 s13, 0xffff, s13 +; VI-NEXT: s_lshl_b32 s24, s43, 16 +; VI-NEXT: s_or_b32 s13, s13, s24 +; VI-NEXT: s_and_b32 s12, 0xffff, s12 +; VI-NEXT: s_lshl_b32 s24, s42, 16 +; VI-NEXT: s_or_b32 s12, s12, s24 ; VI-NEXT: s_and_b32 s11, 0xffff, s11 -; VI-NEXT: s_lshl_b32 s28, s41, 16 -; VI-NEXT: s_or_b32 s11, s11, s28 +; VI-NEXT: s_lshl_b32 s24, s41, 16 +; VI-NEXT: s_or_b32 s11, s11, s24 ; VI-NEXT: s_and_b32 s10, 0xffff, s10 -; VI-NEXT: s_lshl_b32 s28, s40, 16 +; VI-NEXT: s_lshl_b32 s24, s40, 16 +; VI-NEXT: s_or_b32 s10, s10, s24 ; VI-NEXT: s_and_b32 s9, 0xffff, s9 -; VI-NEXT: s_lshl_b32 s15, s15, 16 +; VI-NEXT: s_lshl_b32 s24, s29, 16 +; VI-NEXT: s_or_b32 s9, s9, s24 ; VI-NEXT: s_and_b32 s8, 0xffff, s8 -; VI-NEXT: s_lshl_b32 s14, s14, 16 +; VI-NEXT: s_lshl_b32 s24, s28, 16 +; VI-NEXT: s_or_b32 s8, s8, s24 ; VI-NEXT: s_and_b32 s6, 0xffff, s6 -; VI-NEXT: s_lshl_b32 s13, s13, 16 +; VI-NEXT: s_lshl_b32 s24, s27, 16 +; VI-NEXT: s_or_b32 s6, s6, s24 ; VI-NEXT: s_and_b32 s7, 0xffff, s7 -; VI-NEXT: s_lshl_b32 s12, s12, 16 -; VI-NEXT: s_or_b32 s10, s10, s28 -; VI-NEXT: s_or_b32 s9, s9, s15 -; VI-NEXT: s_or_b32 s8, s8, s14 -; VI-NEXT: s_or_b32 s6, s6, s13 -; VI-NEXT: s_or_b32 s7, s7, s12 +; VI-NEXT: s_lshl_b32 s24, s26, 16 +; VI-NEXT: s_or_b32 s7, s7, s24 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s5 -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: v_mov_b32_e32 v3, s17 -; VI-NEXT: v_mov_b32_e32 v4, s18 -; VI-NEXT: v_mov_b32_e32 v5, s19 -; VI-NEXT: v_mov_b32_e32 v6, s20 -; VI-NEXT: v_mov_b32_e32 v7, s21 -; VI-NEXT: v_mov_b32_e32 v8, s22 -; VI-NEXT: v_mov_b32_e32 v9, s23 -; VI-NEXT: v_mov_b32_e32 v10, s24 -; VI-NEXT: v_mov_b32_e32 v11, s25 -; VI-NEXT: v_mov_b32_e32 v12, s26 -; VI-NEXT: v_mov_b32_e32 v13, s27 +; VI-NEXT: v_mov_b32_e32 v2, s23 +; VI-NEXT: v_mov_b32_e32 v3, s22 +; VI-NEXT: v_mov_b32_e32 v4, s21 +; VI-NEXT: v_mov_b32_e32 v5, s20 +; VI-NEXT: v_mov_b32_e32 v6, s19 +; VI-NEXT: v_mov_b32_e32 v7, s18 +; VI-NEXT: v_mov_b32_e32 v8, s17 +; VI-NEXT: v_mov_b32_e32 v9, s16 +; VI-NEXT: v_mov_b32_e32 v10, s15 +; VI-NEXT: v_mov_b32_e32 v11, s14 +; VI-NEXT: v_mov_b32_e32 v12, s13 +; VI-NEXT: v_mov_b32_e32 v13, s12 ; VI-NEXT: v_mov_b32_e32 v14, s11 ; VI-NEXT: v_mov_b32_e32 v15, s10 ; VI-NEXT: v_mov_b32_e32 v16, s9 @@ -18954,57 +18576,75 @@ define inreg <40 x i16> @bitcast_v10i64_to_v40i16_scalar(<10 x i64> inreg %a, i3 ; VI-NEXT: ; implicit-def: $sgpr42 ; VI-NEXT: ; implicit-def: $sgpr41 ; VI-NEXT: ; implicit-def: $sgpr40 -; VI-NEXT: ; implicit-def: $sgpr15 -; VI-NEXT: ; implicit-def: $sgpr14 -; VI-NEXT: ; implicit-def: $sgpr13 -; VI-NEXT: ; implicit-def: $sgpr12 +; VI-NEXT: ; implicit-def: $sgpr29 +; VI-NEXT: ; implicit-def: $sgpr28 +; VI-NEXT: ; implicit-def: $sgpr27 +; VI-NEXT: ; implicit-def: $sgpr26 ; VI-NEXT: s_branch .LBB41_2 ; ; GFX9-LABEL: bitcast_v10i64_to_v40i16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v7, s16 +; GFX9-NEXT: v_mov_b32_e32 v8, s17 +; GFX9-NEXT: v_mov_b32_e32 v9, s18 +; GFX9-NEXT: v_mov_b32_e32 v10, s19 +; GFX9-NEXT: v_mov_b32_e32 v11, s20 +; GFX9-NEXT: v_mov_b32_e32 v12, s21 +; GFX9-NEXT: v_mov_b32_e32 v13, s22 +; GFX9-NEXT: v_mov_b32_e32 v14, s23 +; GFX9-NEXT: v_mov_b32_e32 v15, s24 +; GFX9-NEXT: v_mov_b32_e32 v16, s25 +; GFX9-NEXT: v_mov_b32_e32 v17, s26 +; GFX9-NEXT: v_mov_b32_e32 v18, s27 +; GFX9-NEXT: v_mov_b32_e32 v19, s28 +; GFX9-NEXT: v_readfirstlane_b32 s6, v7 +; GFX9-NEXT: v_mov_b32_e32 v7, s29 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 -; GFX9-NEXT: v_readfirstlane_b32 s6, v0 -; GFX9-NEXT: v_readfirstlane_b32 s7, v1 -; GFX9-NEXT: v_readfirstlane_b32 s8, v2 -; GFX9-NEXT: v_readfirstlane_b32 s9, v3 -; GFX9-NEXT: v_readfirstlane_b32 s10, v4 +; GFX9-NEXT: v_readfirstlane_b32 s7, v8 +; GFX9-NEXT: v_readfirstlane_b32 s8, v9 +; GFX9-NEXT: v_readfirstlane_b32 s9, v10 +; GFX9-NEXT: v_readfirstlane_b32 s10, v11 +; GFX9-NEXT: v_readfirstlane_b32 s11, v12 +; GFX9-NEXT: v_readfirstlane_b32 s12, v13 +; GFX9-NEXT: v_readfirstlane_b32 s13, v14 +; GFX9-NEXT: v_readfirstlane_b32 s14, v15 +; GFX9-NEXT: v_readfirstlane_b32 s15, v16 +; GFX9-NEXT: v_readfirstlane_b32 s16, v17 +; GFX9-NEXT: v_readfirstlane_b32 s17, v18 +; GFX9-NEXT: v_readfirstlane_b32 s18, v19 +; GFX9-NEXT: v_readfirstlane_b32 s19, v7 +; GFX9-NEXT: v_readfirstlane_b32 s20, v0 +; GFX9-NEXT: v_readfirstlane_b32 s21, v1 +; GFX9-NEXT: v_readfirstlane_b32 s22, v2 +; GFX9-NEXT: v_readfirstlane_b32 s23, v3 +; GFX9-NEXT: v_readfirstlane_b32 s24, v4 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec -; GFX9-NEXT: v_readfirstlane_b32 s11, v5 +; GFX9-NEXT: v_readfirstlane_b32 s25, v5 ; GFX9-NEXT: s_cbranch_scc0 .LBB41_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false -; GFX9-NEXT: s_lshr_b32 s12, s11, 16 -; GFX9-NEXT: s_lshr_b32 s13, s10, 16 -; GFX9-NEXT: s_lshr_b32 s14, s9, 16 -; GFX9-NEXT: s_lshr_b32 s15, s8, 16 -; GFX9-NEXT: s_lshr_b32 s40, s7, 16 -; GFX9-NEXT: s_lshr_b32 s41, s6, 16 -; GFX9-NEXT: s_lshr_b32 s42, s29, 16 -; GFX9-NEXT: s_lshr_b32 s43, s28, 16 -; GFX9-NEXT: s_lshr_b32 s44, s27, 16 -; GFX9-NEXT: s_lshr_b32 s45, s26, 16 -; GFX9-NEXT: s_lshr_b32 s46, s25, 16 -; GFX9-NEXT: s_lshr_b32 s47, s24, 16 -; GFX9-NEXT: s_lshr_b32 s56, s23, 16 -; GFX9-NEXT: s_lshr_b32 s57, s22, 16 -; GFX9-NEXT: s_lshr_b32 s58, s21, 16 -; GFX9-NEXT: s_lshr_b32 s59, s20, 16 -; GFX9-NEXT: s_lshr_b32 s60, s19, 16 -; GFX9-NEXT: s_lshr_b32 s61, s18, 16 -; GFX9-NEXT: s_lshr_b32 s62, s17, 16 -; GFX9-NEXT: s_lshr_b32 s63, s16, 16 +; GFX9-NEXT: s_lshr_b32 s26, s25, 16 +; GFX9-NEXT: s_lshr_b32 s27, s24, 16 +; GFX9-NEXT: s_lshr_b32 s28, s23, 16 +; GFX9-NEXT: s_lshr_b32 s29, s22, 16 +; GFX9-NEXT: s_lshr_b32 s40, s21, 16 +; GFX9-NEXT: s_lshr_b32 s41, s20, 16 +; GFX9-NEXT: s_lshr_b32 s42, s19, 16 +; GFX9-NEXT: s_lshr_b32 s43, s18, 16 +; GFX9-NEXT: s_lshr_b32 s44, s17, 16 +; GFX9-NEXT: s_lshr_b32 s45, s16, 16 +; GFX9-NEXT: s_lshr_b32 s46, s15, 16 +; GFX9-NEXT: s_lshr_b32 s47, s14, 16 +; GFX9-NEXT: s_lshr_b32 s56, s13, 16 +; GFX9-NEXT: s_lshr_b32 s57, s12, 16 +; GFX9-NEXT: s_lshr_b32 s58, s11, 16 +; GFX9-NEXT: s_lshr_b32 s59, s10, 16 +; GFX9-NEXT: s_lshr_b32 s60, s9, 16 +; GFX9-NEXT: s_lshr_b32 s61, s8, 16 +; GFX9-NEXT: s_lshr_b32 s62, s7, 16 +; GFX9-NEXT: s_lshr_b32 s63, s6, 16 ; GFX9-NEXT: s_cbranch_execnz .LBB41_3 ; GFX9-NEXT: .LBB41_2: ; %cmp.true -; GFX9-NEXT: s_add_u32 s10, s10, 3 -; GFX9-NEXT: s_addc_u32 s11, s11, 0 -; GFX9-NEXT: s_add_u32 s8, s8, 3 -; GFX9-NEXT: s_addc_u32 s9, s9, 0 -; GFX9-NEXT: s_add_u32 s6, s6, 3 -; GFX9-NEXT: s_addc_u32 s7, s7, 0 -; GFX9-NEXT: s_add_u32 s28, s28, 3 -; GFX9-NEXT: s_addc_u32 s29, s29, 0 -; GFX9-NEXT: s_add_u32 s26, s26, 3 -; GFX9-NEXT: s_addc_u32 s27, s27, 0 ; GFX9-NEXT: s_add_u32 s24, s24, 3 ; GFX9-NEXT: s_addc_u32 s25, s25, 0 ; GFX9-NEXT: s_add_u32 s22, s22, 3 @@ -19015,67 +18655,77 @@ define inreg <40 x i16> @bitcast_v10i64_to_v40i16_scalar(<10 x i64> inreg %a, i3 ; GFX9-NEXT: s_addc_u32 s19, s19, 0 ; GFX9-NEXT: s_add_u32 s16, s16, 3 ; GFX9-NEXT: s_addc_u32 s17, s17, 0 -; GFX9-NEXT: s_lshr_b32 s12, s11, 16 -; GFX9-NEXT: s_lshr_b32 s13, s10, 16 -; GFX9-NEXT: s_lshr_b32 s14, s9, 16 -; GFX9-NEXT: s_lshr_b32 s15, s8, 16 -; GFX9-NEXT: s_lshr_b32 s40, s7, 16 -; GFX9-NEXT: s_lshr_b32 s41, s6, 16 -; GFX9-NEXT: s_lshr_b32 s42, s29, 16 -; GFX9-NEXT: s_lshr_b32 s43, s28, 16 -; GFX9-NEXT: s_lshr_b32 s44, s27, 16 -; GFX9-NEXT: s_lshr_b32 s45, s26, 16 -; GFX9-NEXT: s_lshr_b32 s46, s25, 16 -; GFX9-NEXT: s_lshr_b32 s47, s24, 16 -; GFX9-NEXT: s_lshr_b32 s56, s23, 16 -; GFX9-NEXT: s_lshr_b32 s57, s22, 16 -; GFX9-NEXT: s_lshr_b32 s58, s21, 16 -; GFX9-NEXT: s_lshr_b32 s59, s20, 16 -; GFX9-NEXT: s_lshr_b32 s60, s19, 16 -; GFX9-NEXT: s_lshr_b32 s61, s18, 16 -; GFX9-NEXT: s_lshr_b32 s62, s17, 16 -; GFX9-NEXT: s_lshr_b32 s63, s16, 16 +; GFX9-NEXT: s_add_u32 s14, s14, 3 +; GFX9-NEXT: s_addc_u32 s15, s15, 0 +; GFX9-NEXT: s_add_u32 s12, s12, 3 +; GFX9-NEXT: s_addc_u32 s13, s13, 0 +; GFX9-NEXT: s_add_u32 s10, s10, 3 +; GFX9-NEXT: s_addc_u32 s11, s11, 0 +; GFX9-NEXT: s_add_u32 s8, s8, 3 +; GFX9-NEXT: s_addc_u32 s9, s9, 0 +; GFX9-NEXT: s_add_u32 s6, s6, 3 +; GFX9-NEXT: s_addc_u32 s7, s7, 0 +; GFX9-NEXT: s_lshr_b32 s26, s25, 16 +; GFX9-NEXT: s_lshr_b32 s27, s24, 16 +; GFX9-NEXT: s_lshr_b32 s28, s23, 16 +; GFX9-NEXT: s_lshr_b32 s29, s22, 16 +; GFX9-NEXT: s_lshr_b32 s40, s21, 16 +; GFX9-NEXT: s_lshr_b32 s41, s20, 16 +; GFX9-NEXT: s_lshr_b32 s42, s19, 16 +; GFX9-NEXT: s_lshr_b32 s43, s18, 16 +; GFX9-NEXT: s_lshr_b32 s44, s17, 16 +; GFX9-NEXT: s_lshr_b32 s45, s16, 16 +; GFX9-NEXT: s_lshr_b32 s46, s15, 16 +; GFX9-NEXT: s_lshr_b32 s47, s14, 16 +; GFX9-NEXT: s_lshr_b32 s56, s13, 16 +; GFX9-NEXT: s_lshr_b32 s57, s12, 16 +; GFX9-NEXT: s_lshr_b32 s58, s11, 16 +; GFX9-NEXT: s_lshr_b32 s59, s10, 16 +; GFX9-NEXT: s_lshr_b32 s60, s9, 16 +; GFX9-NEXT: s_lshr_b32 s61, s8, 16 +; GFX9-NEXT: s_lshr_b32 s62, s7, 16 +; GFX9-NEXT: s_lshr_b32 s63, s6, 16 ; GFX9-NEXT: .LBB41_3: ; %end -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s16, s63 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s17, s62 -; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s61 -; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s60 -; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s59 -; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s58 -; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s57 -; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s56 -; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s47 -; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s46 -; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s45 -; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s44 -; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s43 -; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s42 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s41 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s40 -; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s15 -; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s14 -; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s13 -; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s12 +; GFX9-NEXT: s_pack_ll_b32_b16 s4, s6, s63 +; GFX9-NEXT: s_pack_ll_b32_b16 s5, s7, s62 +; GFX9-NEXT: s_pack_ll_b32_b16 s6, s8, s61 +; GFX9-NEXT: s_pack_ll_b32_b16 s7, s9, s60 +; GFX9-NEXT: s_pack_ll_b32_b16 s8, s10, s59 +; GFX9-NEXT: s_pack_ll_b32_b16 s9, s11, s58 +; GFX9-NEXT: s_pack_ll_b32_b16 s10, s12, s57 +; GFX9-NEXT: s_pack_ll_b32_b16 s11, s13, s56 +; GFX9-NEXT: s_pack_ll_b32_b16 s12, s14, s47 +; GFX9-NEXT: s_pack_ll_b32_b16 s13, s15, s46 +; GFX9-NEXT: s_pack_ll_b32_b16 s14, s16, s45 +; GFX9-NEXT: s_pack_ll_b32_b16 s15, s17, s44 +; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s43 +; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s42 +; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s41 +; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s40 +; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s29 +; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s28 +; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s27 +; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s26 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 -; GFX9-NEXT: v_mov_b32_e32 v2, s16 -; GFX9-NEXT: v_mov_b32_e32 v3, s17 -; GFX9-NEXT: v_mov_b32_e32 v4, s18 -; GFX9-NEXT: v_mov_b32_e32 v5, s19 -; GFX9-NEXT: v_mov_b32_e32 v6, s20 -; GFX9-NEXT: v_mov_b32_e32 v7, s21 -; GFX9-NEXT: v_mov_b32_e32 v8, s22 -; GFX9-NEXT: v_mov_b32_e32 v9, s23 -; GFX9-NEXT: v_mov_b32_e32 v10, s24 -; GFX9-NEXT: v_mov_b32_e32 v11, s25 -; GFX9-NEXT: v_mov_b32_e32 v12, s26 -; GFX9-NEXT: v_mov_b32_e32 v13, s27 -; GFX9-NEXT: v_mov_b32_e32 v14, s6 -; GFX9-NEXT: v_mov_b32_e32 v15, s7 -; GFX9-NEXT: v_mov_b32_e32 v16, s8 -; GFX9-NEXT: v_mov_b32_e32 v17, s9 -; GFX9-NEXT: v_mov_b32_e32 v18, s10 -; GFX9-NEXT: v_mov_b32_e32 v19, s11 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: v_mov_b32_e32 v4, s8 +; GFX9-NEXT: v_mov_b32_e32 v5, s9 +; GFX9-NEXT: v_mov_b32_e32 v6, s10 +; GFX9-NEXT: v_mov_b32_e32 v7, s11 +; GFX9-NEXT: v_mov_b32_e32 v8, s12 +; GFX9-NEXT: v_mov_b32_e32 v9, s13 +; GFX9-NEXT: v_mov_b32_e32 v10, s14 +; GFX9-NEXT: v_mov_b32_e32 v11, s15 +; GFX9-NEXT: v_mov_b32_e32 v12, s16 +; GFX9-NEXT: v_mov_b32_e32 v13, s17 +; GFX9-NEXT: v_mov_b32_e32 v14, s18 +; GFX9-NEXT: v_mov_b32_e32 v15, s19 +; GFX9-NEXT: v_mov_b32_e32 v16, s20 +; GFX9-NEXT: v_mov_b32_e32 v17, s21 +; GFX9-NEXT: v_mov_b32_e32 v18, s22 +; GFX9-NEXT: v_mov_b32_e32 v19, s23 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: .LBB41_4: ; GFX9-NEXT: ; implicit-def: $sgpr63 @@ -19094,38 +18744,65 @@ define inreg <40 x i16> @bitcast_v10i64_to_v40i16_scalar(<10 x i64> inreg %a, i3 ; GFX9-NEXT: ; implicit-def: $sgpr42 ; GFX9-NEXT: ; implicit-def: $sgpr41 ; GFX9-NEXT: ; implicit-def: $sgpr40 -; GFX9-NEXT: ; implicit-def: $sgpr15 -; GFX9-NEXT: ; implicit-def: $sgpr14 -; GFX9-NEXT: ; implicit-def: $sgpr13 -; GFX9-NEXT: ; implicit-def: $sgpr12 +; GFX9-NEXT: ; implicit-def: $sgpr29 +; GFX9-NEXT: ; implicit-def: $sgpr28 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr26 ; GFX9-NEXT: s_branch .LBB41_2 ; ; GFX11-LABEL: bitcast_v10i64_to_v40i16_scalar: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v3, s0 :: v_dual_mov_b32 v4, s1 +; GFX11-NEXT: v_dual_mov_b32 v5, s2 :: v_dual_mov_b32 v6, s3 +; GFX11-NEXT: v_dual_mov_b32 v7, s16 :: v_dual_mov_b32 v8, s17 +; GFX11-NEXT: v_dual_mov_b32 v9, s18 :: v_dual_mov_b32 v10, s19 +; GFX11-NEXT: v_dual_mov_b32 v11, s20 :: v_dual_mov_b32 v12, s21 +; GFX11-NEXT: v_dual_mov_b32 v13, s22 :: v_dual_mov_b32 v14, s23 +; GFX11-NEXT: v_dual_mov_b32 v15, s24 :: v_dual_mov_b32 v16, s25 +; GFX11-NEXT: v_dual_mov_b32 v17, s26 :: v_dual_mov_b32 v18, s27 +; GFX11-NEXT: v_dual_mov_b32 v19, s28 :: v_dual_mov_b32 v20, s29 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 -; GFX11-NEXT: v_readfirstlane_b32 s5, v0 -; GFX11-NEXT: v_readfirstlane_b32 s4, v1 +; GFX11-NEXT: v_readfirstlane_b32 s0, v3 +; GFX11-NEXT: v_readfirstlane_b32 s1, v4 +; GFX11-NEXT: v_readfirstlane_b32 s2, v5 +; GFX11-NEXT: v_readfirstlane_b32 s3, v6 +; GFX11-NEXT: v_readfirstlane_b32 s4, v7 +; GFX11-NEXT: v_readfirstlane_b32 s5, v8 +; GFX11-NEXT: v_readfirstlane_b32 s6, v9 +; GFX11-NEXT: v_readfirstlane_b32 s7, v10 +; GFX11-NEXT: v_readfirstlane_b32 s8, v11 +; GFX11-NEXT: v_readfirstlane_b32 s9, v12 +; GFX11-NEXT: v_readfirstlane_b32 s10, v13 +; GFX11-NEXT: v_readfirstlane_b32 s11, v14 +; GFX11-NEXT: v_readfirstlane_b32 s12, v15 +; GFX11-NEXT: v_readfirstlane_b32 s13, v16 +; GFX11-NEXT: v_readfirstlane_b32 s14, v17 +; GFX11-NEXT: v_readfirstlane_b32 s15, v18 +; GFX11-NEXT: v_readfirstlane_b32 s16, v19 +; GFX11-NEXT: v_readfirstlane_b32 s17, v20 +; GFX11-NEXT: v_readfirstlane_b32 s19, v0 +; GFX11-NEXT: v_readfirstlane_b32 s18, v1 ; GFX11-NEXT: s_mov_b32 s58, 0 -; GFX11-NEXT: s_and_b32 s6, vcc_lo, exec_lo +; GFX11-NEXT: s_and_b32 s20, vcc_lo, exec_lo ; GFX11-NEXT: s_cbranch_scc0 .LBB41_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: s_lshr_b32 s6, s4, 16 -; GFX11-NEXT: s_lshr_b32 s7, s5, 16 -; GFX11-NEXT: s_lshr_b32 s8, s29, 16 -; GFX11-NEXT: s_lshr_b32 s9, s28, 16 -; GFX11-NEXT: s_lshr_b32 s10, s27, 16 -; GFX11-NEXT: s_lshr_b32 s11, s26, 16 -; GFX11-NEXT: s_lshr_b32 s12, s25, 16 -; GFX11-NEXT: s_lshr_b32 s13, s24, 16 -; GFX11-NEXT: s_lshr_b32 s14, s23, 16 -; GFX11-NEXT: s_lshr_b32 s15, s22, 16 -; GFX11-NEXT: s_lshr_b32 s40, s21, 16 -; GFX11-NEXT: s_lshr_b32 s41, s20, 16 -; GFX11-NEXT: s_lshr_b32 s42, s19, 16 -; GFX11-NEXT: s_lshr_b32 s43, s18, 16 -; GFX11-NEXT: s_lshr_b32 s44, s17, 16 -; GFX11-NEXT: s_lshr_b32 s45, s16, 16 +; GFX11-NEXT: s_lshr_b32 s20, s18, 16 +; GFX11-NEXT: s_lshr_b32 s21, s19, 16 +; GFX11-NEXT: s_lshr_b32 s22, s17, 16 +; GFX11-NEXT: s_lshr_b32 s23, s16, 16 +; GFX11-NEXT: s_lshr_b32 s24, s15, 16 +; GFX11-NEXT: s_lshr_b32 s25, s14, 16 +; GFX11-NEXT: s_lshr_b32 s26, s13, 16 +; GFX11-NEXT: s_lshr_b32 s27, s12, 16 +; GFX11-NEXT: s_lshr_b32 s28, s11, 16 +; GFX11-NEXT: s_lshr_b32 s29, s10, 16 +; GFX11-NEXT: s_lshr_b32 s40, s9, 16 +; GFX11-NEXT: s_lshr_b32 s41, s8, 16 +; GFX11-NEXT: s_lshr_b32 s42, s7, 16 +; GFX11-NEXT: s_lshr_b32 s43, s6, 16 +; GFX11-NEXT: s_lshr_b32 s44, s5, 16 +; GFX11-NEXT: s_lshr_b32 s45, s4, 16 ; GFX11-NEXT: s_lshr_b32 s46, s3, 16 ; GFX11-NEXT: s_lshr_b32 s47, s2, 16 ; GFX11-NEXT: s_lshr_b32 s56, s1, 16 @@ -19133,42 +18810,42 @@ define inreg <40 x i16> @bitcast_v10i64_to_v40i16_scalar(<10 x i64> inreg %a, i3 ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58 ; GFX11-NEXT: s_cbranch_vccnz .LBB41_3 ; GFX11-NEXT: .LBB41_2: ; %cmp.true -; GFX11-NEXT: s_add_u32 s5, s5, 3 -; GFX11-NEXT: s_addc_u32 s4, s4, 0 -; GFX11-NEXT: s_add_u32 s28, s28, 3 -; GFX11-NEXT: s_addc_u32 s29, s29, 0 -; GFX11-NEXT: s_add_u32 s26, s26, 3 -; GFX11-NEXT: s_addc_u32 s27, s27, 0 -; GFX11-NEXT: s_add_u32 s24, s24, 3 -; GFX11-NEXT: s_addc_u32 s25, s25, 0 -; GFX11-NEXT: s_add_u32 s22, s22, 3 -; GFX11-NEXT: s_addc_u32 s23, s23, 0 -; GFX11-NEXT: s_add_u32 s20, s20, 3 -; GFX11-NEXT: s_addc_u32 s21, s21, 0 -; GFX11-NEXT: s_add_u32 s18, s18, 3 -; GFX11-NEXT: s_addc_u32 s19, s19, 0 +; GFX11-NEXT: s_add_u32 s19, s19, 3 +; GFX11-NEXT: s_addc_u32 s18, s18, 0 ; GFX11-NEXT: s_add_u32 s16, s16, 3 ; GFX11-NEXT: s_addc_u32 s17, s17, 0 +; GFX11-NEXT: s_add_u32 s14, s14, 3 +; GFX11-NEXT: s_addc_u32 s15, s15, 0 +; GFX11-NEXT: s_add_u32 s12, s12, 3 +; GFX11-NEXT: s_addc_u32 s13, s13, 0 +; GFX11-NEXT: s_add_u32 s10, s10, 3 +; GFX11-NEXT: s_addc_u32 s11, s11, 0 +; GFX11-NEXT: s_add_u32 s8, s8, 3 +; GFX11-NEXT: s_addc_u32 s9, s9, 0 +; GFX11-NEXT: s_add_u32 s6, s6, 3 +; GFX11-NEXT: s_addc_u32 s7, s7, 0 +; GFX11-NEXT: s_add_u32 s4, s4, 3 +; GFX11-NEXT: s_addc_u32 s5, s5, 0 ; GFX11-NEXT: s_add_u32 s2, s2, 3 ; GFX11-NEXT: s_addc_u32 s3, s3, 0 ; GFX11-NEXT: s_add_u32 s0, s0, 3 ; GFX11-NEXT: s_addc_u32 s1, s1, 0 -; GFX11-NEXT: s_lshr_b32 s6, s4, 16 -; GFX11-NEXT: s_lshr_b32 s7, s5, 16 -; GFX11-NEXT: s_lshr_b32 s8, s29, 16 -; GFX11-NEXT: s_lshr_b32 s9, s28, 16 -; GFX11-NEXT: s_lshr_b32 s10, s27, 16 -; GFX11-NEXT: s_lshr_b32 s11, s26, 16 -; GFX11-NEXT: s_lshr_b32 s12, s25, 16 -; GFX11-NEXT: s_lshr_b32 s13, s24, 16 -; GFX11-NEXT: s_lshr_b32 s14, s23, 16 -; GFX11-NEXT: s_lshr_b32 s15, s22, 16 -; GFX11-NEXT: s_lshr_b32 s40, s21, 16 -; GFX11-NEXT: s_lshr_b32 s41, s20, 16 -; GFX11-NEXT: s_lshr_b32 s42, s19, 16 -; GFX11-NEXT: s_lshr_b32 s43, s18, 16 -; GFX11-NEXT: s_lshr_b32 s44, s17, 16 -; GFX11-NEXT: s_lshr_b32 s45, s16, 16 +; GFX11-NEXT: s_lshr_b32 s20, s18, 16 +; GFX11-NEXT: s_lshr_b32 s21, s19, 16 +; GFX11-NEXT: s_lshr_b32 s22, s17, 16 +; GFX11-NEXT: s_lshr_b32 s23, s16, 16 +; GFX11-NEXT: s_lshr_b32 s24, s15, 16 +; GFX11-NEXT: s_lshr_b32 s25, s14, 16 +; GFX11-NEXT: s_lshr_b32 s26, s13, 16 +; GFX11-NEXT: s_lshr_b32 s27, s12, 16 +; GFX11-NEXT: s_lshr_b32 s28, s11, 16 +; GFX11-NEXT: s_lshr_b32 s29, s10, 16 +; GFX11-NEXT: s_lshr_b32 s40, s9, 16 +; GFX11-NEXT: s_lshr_b32 s41, s8, 16 +; GFX11-NEXT: s_lshr_b32 s42, s7, 16 +; GFX11-NEXT: s_lshr_b32 s43, s6, 16 +; GFX11-NEXT: s_lshr_b32 s44, s5, 16 +; GFX11-NEXT: s_lshr_b32 s45, s4, 16 ; GFX11-NEXT: s_lshr_b32 s46, s3, 16 ; GFX11-NEXT: s_lshr_b32 s47, s2, 16 ; GFX11-NEXT: s_lshr_b32 s56, s1, 16 @@ -19179,32 +18856,32 @@ define inreg <40 x i16> @bitcast_v10i64_to_v40i16_scalar(<10 x i64> inreg %a, i3 ; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s56 ; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s47 ; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s46 -; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s45 -; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s44 -; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s43 -; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s42 -; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s41 -; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s40 -; GFX11-NEXT: s_pack_ll_b32_b16 s15, s22, s15 -; GFX11-NEXT: s_pack_ll_b32_b16 s14, s23, s14 -; GFX11-NEXT: s_pack_ll_b32_b16 s13, s24, s13 -; GFX11-NEXT: s_pack_ll_b32_b16 s12, s25, s12 -; GFX11-NEXT: s_pack_ll_b32_b16 s11, s26, s11 -; GFX11-NEXT: s_pack_ll_b32_b16 s10, s27, s10 -; GFX11-NEXT: s_pack_ll_b32_b16 s9, s28, s9 -; GFX11-NEXT: s_pack_ll_b32_b16 s8, s29, s8 -; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s7 -; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s6 +; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s45 +; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s44 +; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s43 +; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s42 +; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s41 +; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s40 +; GFX11-NEXT: s_pack_ll_b32_b16 s10, s10, s29 +; GFX11-NEXT: s_pack_ll_b32_b16 s11, s11, s28 +; GFX11-NEXT: s_pack_ll_b32_b16 s12, s12, s27 +; GFX11-NEXT: s_pack_ll_b32_b16 s13, s13, s26 +; GFX11-NEXT: s_pack_ll_b32_b16 s14, s14, s25 +; GFX11-NEXT: s_pack_ll_b32_b16 s15, s15, s24 +; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s23 +; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s22 +; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s21 +; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s20 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 -; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 -; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 -; GFX11-NEXT: v_dual_mov_b32 v10, s15 :: v_dual_mov_b32 v11, s14 -; GFX11-NEXT: v_dual_mov_b32 v12, s13 :: v_dual_mov_b32 v13, s12 -; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v15, s10 -; GFX11-NEXT: v_dual_mov_b32 v16, s9 :: v_dual_mov_b32 v17, s8 -; GFX11-NEXT: v_dual_mov_b32 v18, s5 :: v_dual_mov_b32 v19, s4 +; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-NEXT: v_dual_mov_b32 v18, s19 :: v_dual_mov_b32 v19, s18 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: .LBB41_4: ; GFX11-NEXT: ; implicit-def: $sgpr57 @@ -19217,16 +18894,16 @@ define inreg <40 x i16> @bitcast_v10i64_to_v40i16_scalar(<10 x i64> inreg %a, i3 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr41 ; GFX11-NEXT: ; implicit-def: $sgpr40 -; GFX11-NEXT: ; implicit-def: $sgpr15 -; GFX11-NEXT: ; implicit-def: $sgpr14 -; GFX11-NEXT: ; implicit-def: $sgpr13 -; GFX11-NEXT: ; implicit-def: $sgpr12 -; GFX11-NEXT: ; implicit-def: $sgpr11 -; GFX11-NEXT: ; implicit-def: $sgpr10 -; GFX11-NEXT: ; implicit-def: $sgpr9 -; GFX11-NEXT: ; implicit-def: $sgpr8 -; GFX11-NEXT: ; implicit-def: $sgpr7 -; GFX11-NEXT: ; implicit-def: $sgpr6 +; GFX11-NEXT: ; implicit-def: $sgpr29 +; GFX11-NEXT: ; implicit-def: $sgpr28 +; GFX11-NEXT: ; implicit-def: $sgpr27 +; GFX11-NEXT: ; implicit-def: $sgpr26 +; GFX11-NEXT: ; implicit-def: $sgpr25 +; GFX11-NEXT: ; implicit-def: $sgpr24 +; GFX11-NEXT: ; implicit-def: $sgpr23 +; GFX11-NEXT: ; implicit-def: $sgpr22 +; GFX11-NEXT: ; implicit-def: $sgpr21 +; GFX11-NEXT: ; implicit-def: $sgpr20 ; GFX11-NEXT: s_branch .LBB41_2 %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -19249,6 +18926,17 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) { ; SI-LABEL: bitcast_v40i16_to_v10i64: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v52, v6 +; SI-NEXT: v_mov_b32_e32 v53, v4 +; SI-NEXT: v_mov_b32_e32 v54, v2 +; SI-NEXT: v_mov_b32_e32 v55, v0 +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:36 +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:28 +; SI-NEXT: v_mov_b32_e32 v49, v12 +; SI-NEXT: v_mov_b32_e32 v50, v10 +; SI-NEXT: v_mov_b32_e32 v51, v8 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill @@ -19270,17 +18958,6 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v52, v6 -; SI-NEXT: v_mov_b32_e32 v53, v4 -; SI-NEXT: v_mov_b32_e32 v54, v2 -; SI-NEXT: v_mov_b32_e32 v55, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:36 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32 -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:28 -; SI-NEXT: v_mov_b32_e32 v49, v12 -; SI-NEXT: v_mov_b32_e32 v50, v10 -; SI-NEXT: v_mov_b32_e32 v51, v8 ; SI-NEXT: v_mov_b32_e32 v37, v20 ; SI-NEXT: v_mov_b32_e32 v38, v18 ; SI-NEXT: v_mov_b32_e32 v39, v16 @@ -19302,13 +18979,10 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) { ; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v27 ; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v29 ; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:4 -; SI-NEXT: s_waitcnt vmcnt(4) +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v0 -; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v4 -; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24 @@ -19534,7 +19208,7 @@ define <10 x i64> @bitcast_v40i16_to_v10i64(<40 x i16> %a, i32 %b) { ; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15 ; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17 ; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18 -; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19 +; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19 ; SI-NEXT: .LBB42_4: ; %end ; SI-NEXT: s_or_b64 exec, exec, s[4:5] ; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload @@ -20622,269 +20296,100 @@ define inreg <10 x i64> @bitcast_v40i16_to_v10i64_scalar(<40 x i16> inreg %a, i3 ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44 -; GFX11-TRUE16-NEXT: s_clause 0xa -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB43_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB43_3 ; GFX11-TRUE16-NEXT: .LBB43_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s40, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s41, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v186, v186, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v185, v185, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s0, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s1, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s2, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, s3, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, s4, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v35, s5, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v44, s6, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v54, s7, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v65, s8, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v77, s9, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v90, s10, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v104, s11, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v119, s12, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v135, s13, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v152, s14, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v170, s15, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, s6, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, s7, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, s8, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s9, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, s10, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, s11, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, s12, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, s13, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s14, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, s15, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, s16, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: .LBB43_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v17, v170 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v186 :: v_dual_mov_b32 v19, v185 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xa -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:296 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v14, v119 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB43_4: -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB43_2 ; ; GFX11-FAKE16-LABEL: bitcast_v40i16_to_v10i64_scalar: @@ -21815,7 +21320,35 @@ define inreg <40 x half> @bitcast_v10i64_to_v40f16_scalar(<10 x i64> inreg %a, i ; SI-LABEL: bitcast_v10i64_to_v40f16_scalar: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v8, s16 +; SI-NEXT: v_mov_b32_e32 v9, s17 +; SI-NEXT: v_mov_b32_e32 v10, s18 +; SI-NEXT: v_mov_b32_e32 v11, s19 +; SI-NEXT: v_mov_b32_e32 v12, s20 +; SI-NEXT: v_mov_b32_e32 v13, s21 +; SI-NEXT: v_mov_b32_e32 v14, s22 +; SI-NEXT: v_mov_b32_e32 v15, s23 +; SI-NEXT: v_mov_b32_e32 v16, s24 +; SI-NEXT: v_mov_b32_e32 v17, s25 +; SI-NEXT: v_mov_b32_e32 v18, s26 +; SI-NEXT: v_mov_b32_e32 v19, s27 +; SI-NEXT: v_readfirstlane_b32 s22, v8 +; SI-NEXT: v_mov_b32_e32 v8, s28 +; SI-NEXT: v_readfirstlane_b32 s25, v9 +; SI-NEXT: v_mov_b32_e32 v9, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 +; SI-NEXT: v_readfirstlane_b32 s23, v10 +; SI-NEXT: v_readfirstlane_b32 s24, v11 +; SI-NEXT: v_readfirstlane_b32 s20, v12 +; SI-NEXT: v_readfirstlane_b32 s21, v13 +; SI-NEXT: v_readfirstlane_b32 s18, v14 +; SI-NEXT: v_readfirstlane_b32 s19, v15 +; SI-NEXT: v_readfirstlane_b32 s16, v16 +; SI-NEXT: v_readfirstlane_b32 s17, v17 +; SI-NEXT: v_readfirstlane_b32 s14, v18 +; SI-NEXT: v_readfirstlane_b32 s15, v19 +; SI-NEXT: v_readfirstlane_b32 s12, v8 +; SI-NEXT: v_readfirstlane_b32 s13, v9 ; SI-NEXT: v_readfirstlane_b32 s10, v1 ; SI-NEXT: v_readfirstlane_b32 s11, v2 ; SI-NEXT: v_readfirstlane_b32 s7, v3 @@ -21837,33 +21370,33 @@ define inreg <40 x half> @bitcast_v10i64_to_v40f16_scalar(<10 x i64> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v8, s4 ; SI-NEXT: s_lshr_b32 s4, s10, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v10, s4 -; SI-NEXT: s_lshr_b32 s4, s29, 16 +; SI-NEXT: s_lshr_b32 s4, s13, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v12, s4 -; SI-NEXT: s_lshr_b32 s4, s28, 16 +; SI-NEXT: s_lshr_b32 s4, s12, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v14, s4 -; SI-NEXT: s_lshr_b32 s4, s27, 16 +; SI-NEXT: s_lshr_b32 s4, s15, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v16, s4 -; SI-NEXT: s_lshr_b32 s4, s26, 16 +; SI-NEXT: s_lshr_b32 s4, s14, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v19, s4 -; SI-NEXT: s_lshr_b32 s4, s25, 16 +; SI-NEXT: s_lshr_b32 s4, s17, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v21, s4 -; SI-NEXT: s_lshr_b32 s4, s24, 16 +; SI-NEXT: s_lshr_b32 s4, s16, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v23, s4 -; SI-NEXT: s_lshr_b32 s4, s23, 16 +; SI-NEXT: s_lshr_b32 s4, s19, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v25, s4 -; SI-NEXT: s_lshr_b32 s4, s22, 16 +; SI-NEXT: s_lshr_b32 s4, s18, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v27, s4 ; SI-NEXT: s_lshr_b32 s4, s21, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v29, s4 ; SI-NEXT: s_lshr_b32 s4, s20, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v31, s4 -; SI-NEXT: s_lshr_b32 s4, s19, 16 +; SI-NEXT: s_lshr_b32 s4, s24, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v34, s4 -; SI-NEXT: s_lshr_b32 s4, s18, 16 +; SI-NEXT: s_lshr_b32 s4, s23, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v36, s4 -; SI-NEXT: s_lshr_b32 s4, s17, 16 +; SI-NEXT: s_lshr_b32 s4, s25, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v38, s4 -; SI-NEXT: s_lshr_b32 s4, s16, 16 +; SI-NEXT: s_lshr_b32 s4, s22, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v48, s4 ; SI-NEXT: v_cvt_f32_f16_e32 v3, s9 ; SI-NEXT: v_cvt_f32_f16_e32 v5, s6 @@ -21871,50 +21404,50 @@ define inreg <40 x half> @bitcast_v10i64_to_v40f16_scalar(<10 x i64> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v9, s7 ; SI-NEXT: v_cvt_f32_f16_e32 v11, s11 ; SI-NEXT: v_cvt_f32_f16_e32 v13, s10 -; SI-NEXT: v_cvt_f32_f16_e32 v15, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v17, s28 -; SI-NEXT: v_cvt_f32_f16_e32 v18, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v20, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v22, s25 -; SI-NEXT: v_cvt_f32_f16_e32 v24, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v26, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v28, s22 +; SI-NEXT: v_cvt_f32_f16_e32 v15, s13 +; SI-NEXT: v_cvt_f32_f16_e32 v17, s12 +; SI-NEXT: v_cvt_f32_f16_e32 v18, s15 +; SI-NEXT: v_cvt_f32_f16_e32 v20, s14 +; SI-NEXT: v_cvt_f32_f16_e32 v22, s17 +; SI-NEXT: v_cvt_f32_f16_e32 v24, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v26, s19 +; SI-NEXT: v_cvt_f32_f16_e32 v28, s18 ; SI-NEXT: v_cvt_f32_f16_e32 v30, s21 ; SI-NEXT: v_cvt_f32_f16_e32 v32, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v33, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v35, s18 -; SI-NEXT: v_cvt_f32_f16_e32 v37, s17 -; SI-NEXT: v_cvt_f32_f16_e32 v39, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v33, s24 +; SI-NEXT: v_cvt_f32_f16_e32 v35, s23 +; SI-NEXT: v_cvt_f32_f16_e32 v37, s25 +; SI-NEXT: v_cvt_f32_f16_e32 v39, s22 ; SI-NEXT: s_cbranch_execnz .LBB45_3 ; SI-NEXT: .LBB45_2: ; %cmp.true -; SI-NEXT: s_add_u32 s4, s16, 3 -; SI-NEXT: s_addc_u32 s5, s17, 0 -; SI-NEXT: s_lshr_b32 s12, s4, 16 -; SI-NEXT: s_lshr_b32 s13, s5, 16 -; SI-NEXT: s_add_u32 s14, s18, 3 -; SI-NEXT: s_addc_u32 s15, s19, 0 -; SI-NEXT: s_lshr_b32 s16, s14, 16 -; SI-NEXT: s_lshr_b32 s17, s15, 16 -; SI-NEXT: s_add_u32 s18, s20, 3 -; SI-NEXT: s_addc_u32 s19, s21, 0 -; SI-NEXT: s_lshr_b32 s20, s18, 16 -; SI-NEXT: s_lshr_b32 s21, s19, 16 -; SI-NEXT: s_add_u32 s22, s22, 3 -; SI-NEXT: s_addc_u32 s23, s23, 0 -; SI-NEXT: s_lshr_b32 s40, s22, 16 -; SI-NEXT: s_lshr_b32 s41, s23, 16 -; SI-NEXT: s_add_u32 s24, s24, 3 -; SI-NEXT: s_addc_u32 s25, s25, 0 -; SI-NEXT: s_lshr_b32 s42, s24, 16 -; SI-NEXT: s_lshr_b32 s43, s25, 16 -; SI-NEXT: s_add_u32 s26, s26, 3 -; SI-NEXT: s_addc_u32 s27, s27, 0 -; SI-NEXT: s_lshr_b32 s44, s26, 16 -; SI-NEXT: s_lshr_b32 s45, s27, 16 -; SI-NEXT: s_add_u32 s28, s28, 3 -; SI-NEXT: s_addc_u32 s29, s29, 0 -; SI-NEXT: s_lshr_b32 s46, s28, 16 -; SI-NEXT: s_lshr_b32 s47, s29, 16 +; SI-NEXT: s_add_u32 s4, s22, 3 +; SI-NEXT: s_addc_u32 s5, s25, 0 +; SI-NEXT: s_lshr_b32 s22, s4, 16 +; SI-NEXT: s_lshr_b32 s25, s5, 16 +; SI-NEXT: s_add_u32 s23, s23, 3 +; SI-NEXT: s_addc_u32 s24, s24, 0 +; SI-NEXT: s_lshr_b32 s26, s23, 16 +; SI-NEXT: s_lshr_b32 s27, s24, 16 +; SI-NEXT: s_add_u32 s20, s20, 3 +; SI-NEXT: s_addc_u32 s21, s21, 0 +; SI-NEXT: s_lshr_b32 s28, s20, 16 +; SI-NEXT: s_lshr_b32 s29, s21, 16 +; SI-NEXT: s_add_u32 s18, s18, 3 +; SI-NEXT: s_addc_u32 s19, s19, 0 +; SI-NEXT: s_lshr_b32 s40, s18, 16 +; SI-NEXT: s_lshr_b32 s41, s19, 16 +; SI-NEXT: s_add_u32 s16, s16, 3 +; SI-NEXT: s_addc_u32 s17, s17, 0 +; SI-NEXT: s_lshr_b32 s42, s16, 16 +; SI-NEXT: s_lshr_b32 s43, s17, 16 +; SI-NEXT: s_add_u32 s14, s14, 3 +; SI-NEXT: s_addc_u32 s15, s15, 0 +; SI-NEXT: s_lshr_b32 s44, s14, 16 +; SI-NEXT: s_lshr_b32 s45, s15, 16 +; SI-NEXT: s_add_u32 s12, s12, 3 +; SI-NEXT: s_addc_u32 s13, s13, 0 +; SI-NEXT: s_lshr_b32 s46, s12, 16 +; SI-NEXT: s_lshr_b32 s47, s13, 16 ; SI-NEXT: s_add_u32 s10, s10, 3 ; SI-NEXT: s_addc_u32 s11, s11, 0 ; SI-NEXT: s_lshr_b32 s56, s10, 16 @@ -21933,18 +21466,18 @@ define inreg <40 x half> @bitcast_v10i64_to_v40f16_scalar(<10 x i64> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v9, s7 ; SI-NEXT: v_cvt_f32_f16_e32 v11, s11 ; SI-NEXT: v_cvt_f32_f16_e32 v13, s10 -; SI-NEXT: v_cvt_f32_f16_e32 v15, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v17, s28 -; SI-NEXT: v_cvt_f32_f16_e32 v18, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v20, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v22, s25 -; SI-NEXT: v_cvt_f32_f16_e32 v24, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v26, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v28, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v30, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v32, s18 -; SI-NEXT: v_cvt_f32_f16_e32 v33, s15 -; SI-NEXT: v_cvt_f32_f16_e32 v35, s14 +; SI-NEXT: v_cvt_f32_f16_e32 v15, s13 +; SI-NEXT: v_cvt_f32_f16_e32 v17, s12 +; SI-NEXT: v_cvt_f32_f16_e32 v18, s15 +; SI-NEXT: v_cvt_f32_f16_e32 v20, s14 +; SI-NEXT: v_cvt_f32_f16_e32 v22, s17 +; SI-NEXT: v_cvt_f32_f16_e32 v24, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v26, s19 +; SI-NEXT: v_cvt_f32_f16_e32 v28, s18 +; SI-NEXT: v_cvt_f32_f16_e32 v30, s21 +; SI-NEXT: v_cvt_f32_f16_e32 v32, s20 +; SI-NEXT: v_cvt_f32_f16_e32 v33, s24 +; SI-NEXT: v_cvt_f32_f16_e32 v35, s23 ; SI-NEXT: v_cvt_f32_f16_e32 v37, s5 ; SI-NEXT: v_cvt_f32_f16_e32 v39, s4 ; SI-NEXT: v_cvt_f32_f16_e32 v1, s61 @@ -21961,12 +21494,12 @@ define inreg <40 x half> @bitcast_v10i64_to_v40f16_scalar(<10 x i64> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v23, s42 ; SI-NEXT: v_cvt_f32_f16_e32 v25, s41 ; SI-NEXT: v_cvt_f32_f16_e32 v27, s40 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v31, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v34, s17 -; SI-NEXT: v_cvt_f32_f16_e32 v36, s16 -; SI-NEXT: v_cvt_f32_f16_e32 v38, s13 -; SI-NEXT: v_cvt_f32_f16_e32 v48, s12 +; SI-NEXT: v_cvt_f32_f16_e32 v29, s29 +; SI-NEXT: v_cvt_f32_f16_e32 v31, s28 +; SI-NEXT: v_cvt_f32_f16_e32 v34, s27 +; SI-NEXT: v_cvt_f32_f16_e32 v36, s26 +; SI-NEXT: v_cvt_f32_f16_e32 v38, s25 +; SI-NEXT: v_cvt_f32_f16_e32 v48, s22 ; SI-NEXT: .LBB45_3: ; %end ; SI-NEXT: v_cvt_f16_f32_e32 v48, v48 ; SI-NEXT: v_cvt_f16_f32_e32 v39, v39 @@ -22154,7 +21687,35 @@ define inreg <40 x half> @bitcast_v10i64_to_v40f16_scalar(<10 x i64> inreg %a, i ; VI-LABEL: bitcast_v10i64_to_v40f16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_mov_b32_e32 v7, s16 +; VI-NEXT: v_mov_b32_e32 v8, s17 +; VI-NEXT: v_mov_b32_e32 v9, s18 +; VI-NEXT: v_mov_b32_e32 v10, s19 +; VI-NEXT: v_mov_b32_e32 v11, s20 +; VI-NEXT: v_mov_b32_e32 v12, s21 +; VI-NEXT: v_mov_b32_e32 v13, s22 +; VI-NEXT: v_mov_b32_e32 v14, s23 +; VI-NEXT: v_mov_b32_e32 v15, s24 +; VI-NEXT: v_mov_b32_e32 v16, s25 +; VI-NEXT: v_mov_b32_e32 v17, s26 +; VI-NEXT: v_mov_b32_e32 v18, s27 +; VI-NEXT: v_mov_b32_e32 v19, s28 +; VI-NEXT: v_readfirstlane_b32 s25, v7 +; VI-NEXT: v_mov_b32_e32 v7, s29 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 +; VI-NEXT: v_readfirstlane_b32 s24, v8 +; VI-NEXT: v_readfirstlane_b32 s23, v9 +; VI-NEXT: v_readfirstlane_b32 s22, v10 +; VI-NEXT: v_readfirstlane_b32 s21, v11 +; VI-NEXT: v_readfirstlane_b32 s20, v12 +; VI-NEXT: v_readfirstlane_b32 s19, v13 +; VI-NEXT: v_readfirstlane_b32 s18, v14 +; VI-NEXT: v_readfirstlane_b32 s17, v15 +; VI-NEXT: v_readfirstlane_b32 s16, v16 +; VI-NEXT: v_readfirstlane_b32 s15, v17 +; VI-NEXT: v_readfirstlane_b32 s14, v18 +; VI-NEXT: v_readfirstlane_b32 s13, v19 +; VI-NEXT: v_readfirstlane_b32 s12, v7 ; VI-NEXT: v_readfirstlane_b32 s11, v0 ; VI-NEXT: v_readfirstlane_b32 s10, v1 ; VI-NEXT: v_readfirstlane_b32 s9, v2 @@ -22164,26 +21725,26 @@ define inreg <40 x half> @bitcast_v10i64_to_v40f16_scalar(<10 x i64> inreg %a, i ; VI-NEXT: v_readfirstlane_b32 s7, v5 ; VI-NEXT: s_cbranch_scc0 .LBB45_4 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_lshr_b32 s12, s7, 16 -; VI-NEXT: s_lshr_b32 s13, s6, 16 -; VI-NEXT: s_lshr_b32 s14, s8, 16 -; VI-NEXT: s_lshr_b32 s15, s9, 16 +; VI-NEXT: s_lshr_b32 s26, s7, 16 +; VI-NEXT: s_lshr_b32 s27, s6, 16 +; VI-NEXT: s_lshr_b32 s28, s8, 16 +; VI-NEXT: s_lshr_b32 s29, s9, 16 ; VI-NEXT: s_lshr_b32 s40, s10, 16 ; VI-NEXT: s_lshr_b32 s41, s11, 16 -; VI-NEXT: s_lshr_b32 s42, s29, 16 -; VI-NEXT: s_lshr_b32 s43, s28, 16 -; VI-NEXT: s_lshr_b32 s44, s27, 16 -; VI-NEXT: s_lshr_b32 s45, s26, 16 -; VI-NEXT: s_lshr_b32 s46, s25, 16 -; VI-NEXT: s_lshr_b32 s47, s24, 16 -; VI-NEXT: s_lshr_b32 s56, s23, 16 -; VI-NEXT: s_lshr_b32 s57, s22, 16 -; VI-NEXT: s_lshr_b32 s58, s21, 16 -; VI-NEXT: s_lshr_b32 s59, s20, 16 -; VI-NEXT: s_lshr_b32 s60, s19, 16 -; VI-NEXT: s_lshr_b32 s61, s18, 16 -; VI-NEXT: s_lshr_b32 s62, s17, 16 -; VI-NEXT: s_lshr_b32 s63, s16, 16 +; VI-NEXT: s_lshr_b32 s42, s12, 16 +; VI-NEXT: s_lshr_b32 s43, s13, 16 +; VI-NEXT: s_lshr_b32 s44, s14, 16 +; VI-NEXT: s_lshr_b32 s45, s15, 16 +; VI-NEXT: s_lshr_b32 s46, s16, 16 +; VI-NEXT: s_lshr_b32 s47, s17, 16 +; VI-NEXT: s_lshr_b32 s56, s18, 16 +; VI-NEXT: s_lshr_b32 s57, s19, 16 +; VI-NEXT: s_lshr_b32 s58, s20, 16 +; VI-NEXT: s_lshr_b32 s59, s21, 16 +; VI-NEXT: s_lshr_b32 s60, s22, 16 +; VI-NEXT: s_lshr_b32 s61, s23, 16 +; VI-NEXT: s_lshr_b32 s62, s24, 16 +; VI-NEXT: s_lshr_b32 s63, s25, 16 ; VI-NEXT: s_cbranch_execnz .LBB45_3 ; VI-NEXT: .LBB45_2: ; %cmp.true ; VI-NEXT: s_add_u32 s6, s6, 3 @@ -22192,115 +21753,115 @@ define inreg <40 x half> @bitcast_v10i64_to_v40f16_scalar(<10 x i64> inreg %a, i ; VI-NEXT: s_addc_u32 s8, s8, 0 ; VI-NEXT: s_add_u32 s11, s11, 3 ; VI-NEXT: s_addc_u32 s10, s10, 0 -; VI-NEXT: s_add_u32 s28, s28, 3 -; VI-NEXT: s_addc_u32 s29, s29, 0 -; VI-NEXT: s_add_u32 s26, s26, 3 -; VI-NEXT: s_addc_u32 s27, s27, 0 -; VI-NEXT: s_add_u32 s24, s24, 3 -; VI-NEXT: s_addc_u32 s25, s25, 0 -; VI-NEXT: s_add_u32 s22, s22, 3 -; VI-NEXT: s_addc_u32 s23, s23, 0 -; VI-NEXT: s_add_u32 s20, s20, 3 -; VI-NEXT: s_addc_u32 s21, s21, 0 -; VI-NEXT: s_add_u32 s18, s18, 3 -; VI-NEXT: s_addc_u32 s19, s19, 0 -; VI-NEXT: s_add_u32 s16, s16, 3 -; VI-NEXT: s_addc_u32 s17, s17, 0 -; VI-NEXT: s_lshr_b32 s12, s7, 16 -; VI-NEXT: s_lshr_b32 s13, s6, 16 -; VI-NEXT: s_lshr_b32 s14, s8, 16 -; VI-NEXT: s_lshr_b32 s15, s9, 16 +; VI-NEXT: s_add_u32 s13, s13, 3 +; VI-NEXT: s_addc_u32 s12, s12, 0 +; VI-NEXT: s_add_u32 s15, s15, 3 +; VI-NEXT: s_addc_u32 s14, s14, 0 +; VI-NEXT: s_add_u32 s17, s17, 3 +; VI-NEXT: s_addc_u32 s16, s16, 0 +; VI-NEXT: s_add_u32 s19, s19, 3 +; VI-NEXT: s_addc_u32 s18, s18, 0 +; VI-NEXT: s_add_u32 s21, s21, 3 +; VI-NEXT: s_addc_u32 s20, s20, 0 +; VI-NEXT: s_add_u32 s23, s23, 3 +; VI-NEXT: s_addc_u32 s22, s22, 0 +; VI-NEXT: s_add_u32 s25, s25, 3 +; VI-NEXT: s_addc_u32 s24, s24, 0 +; VI-NEXT: s_lshr_b32 s26, s7, 16 +; VI-NEXT: s_lshr_b32 s27, s6, 16 +; VI-NEXT: s_lshr_b32 s28, s8, 16 +; VI-NEXT: s_lshr_b32 s29, s9, 16 ; VI-NEXT: s_lshr_b32 s40, s10, 16 ; VI-NEXT: s_lshr_b32 s41, s11, 16 -; VI-NEXT: s_lshr_b32 s42, s29, 16 -; VI-NEXT: s_lshr_b32 s43, s28, 16 -; VI-NEXT: s_lshr_b32 s44, s27, 16 -; VI-NEXT: s_lshr_b32 s45, s26, 16 -; VI-NEXT: s_lshr_b32 s46, s25, 16 -; VI-NEXT: s_lshr_b32 s47, s24, 16 -; VI-NEXT: s_lshr_b32 s56, s23, 16 -; VI-NEXT: s_lshr_b32 s57, s22, 16 -; VI-NEXT: s_lshr_b32 s58, s21, 16 -; VI-NEXT: s_lshr_b32 s59, s20, 16 -; VI-NEXT: s_lshr_b32 s60, s19, 16 -; VI-NEXT: s_lshr_b32 s61, s18, 16 -; VI-NEXT: s_lshr_b32 s62, s17, 16 -; VI-NEXT: s_lshr_b32 s63, s16, 16 +; VI-NEXT: s_lshr_b32 s42, s12, 16 +; VI-NEXT: s_lshr_b32 s43, s13, 16 +; VI-NEXT: s_lshr_b32 s44, s14, 16 +; VI-NEXT: s_lshr_b32 s45, s15, 16 +; VI-NEXT: s_lshr_b32 s46, s16, 16 +; VI-NEXT: s_lshr_b32 s47, s17, 16 +; VI-NEXT: s_lshr_b32 s56, s18, 16 +; VI-NEXT: s_lshr_b32 s57, s19, 16 +; VI-NEXT: s_lshr_b32 s58, s20, 16 +; VI-NEXT: s_lshr_b32 s59, s21, 16 +; VI-NEXT: s_lshr_b32 s60, s22, 16 +; VI-NEXT: s_lshr_b32 s61, s23, 16 +; VI-NEXT: s_lshr_b32 s62, s24, 16 +; VI-NEXT: s_lshr_b32 s63, s25, 16 ; VI-NEXT: .LBB45_3: ; %end -; VI-NEXT: s_and_b32 s4, 0xffff, s16 +; VI-NEXT: s_and_b32 s4, 0xffff, s25 ; VI-NEXT: s_lshl_b32 s5, s63, 16 ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_and_b32 s5, 0xffff, s17 -; VI-NEXT: s_lshl_b32 s16, s62, 16 -; VI-NEXT: s_or_b32 s5, s5, s16 -; VI-NEXT: s_and_b32 s16, 0xffff, s18 -; VI-NEXT: s_lshl_b32 s17, s61, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, 0xffff, s19 -; VI-NEXT: s_lshl_b32 s18, s60, 16 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s18, 0xffff, s20 -; VI-NEXT: s_lshl_b32 s19, s59, 16 -; VI-NEXT: s_or_b32 s18, s18, s19 -; VI-NEXT: s_and_b32 s19, 0xffff, s21 -; VI-NEXT: s_lshl_b32 s20, s58, 16 -; VI-NEXT: s_or_b32 s19, s19, s20 -; VI-NEXT: s_and_b32 s20, 0xffff, s22 -; VI-NEXT: s_lshl_b32 s21, s57, 16 -; VI-NEXT: s_or_b32 s20, s20, s21 -; VI-NEXT: s_and_b32 s21, 0xffff, s23 -; VI-NEXT: s_lshl_b32 s22, s56, 16 -; VI-NEXT: s_or_b32 s21, s21, s22 -; VI-NEXT: s_and_b32 s22, 0xffff, s24 -; VI-NEXT: s_lshl_b32 s23, s47, 16 -; VI-NEXT: s_or_b32 s22, s22, s23 -; VI-NEXT: s_and_b32 s23, 0xffff, s25 -; VI-NEXT: s_lshl_b32 s24, s46, 16 +; VI-NEXT: s_and_b32 s5, 0xffff, s24 +; VI-NEXT: s_lshl_b32 s24, s62, 16 +; VI-NEXT: s_or_b32 s5, s5, s24 +; VI-NEXT: s_and_b32 s23, 0xffff, s23 +; VI-NEXT: s_lshl_b32 s24, s61, 16 ; VI-NEXT: s_or_b32 s23, s23, s24 -; VI-NEXT: s_and_b32 s24, 0xffff, s26 -; VI-NEXT: s_lshl_b32 s25, s45, 16 -; VI-NEXT: s_or_b32 s24, s24, s25 -; VI-NEXT: s_and_b32 s25, 0xffff, s27 -; VI-NEXT: s_lshl_b32 s26, s44, 16 -; VI-NEXT: s_or_b32 s25, s25, s26 -; VI-NEXT: s_and_b32 s26, 0xffff, s28 -; VI-NEXT: s_lshl_b32 s27, s43, 16 -; VI-NEXT: s_or_b32 s26, s26, s27 -; VI-NEXT: s_and_b32 s27, 0xffff, s29 -; VI-NEXT: s_lshl_b32 s28, s42, 16 -; VI-NEXT: s_or_b32 s27, s27, s28 +; VI-NEXT: s_and_b32 s22, 0xffff, s22 +; VI-NEXT: s_lshl_b32 s24, s60, 16 +; VI-NEXT: s_or_b32 s22, s22, s24 +; VI-NEXT: s_and_b32 s21, 0xffff, s21 +; VI-NEXT: s_lshl_b32 s24, s59, 16 +; VI-NEXT: s_or_b32 s21, s21, s24 +; VI-NEXT: s_and_b32 s20, 0xffff, s20 +; VI-NEXT: s_lshl_b32 s24, s58, 16 +; VI-NEXT: s_or_b32 s20, s20, s24 +; VI-NEXT: s_and_b32 s19, 0xffff, s19 +; VI-NEXT: s_lshl_b32 s24, s57, 16 +; VI-NEXT: s_or_b32 s19, s19, s24 +; VI-NEXT: s_and_b32 s18, 0xffff, s18 +; VI-NEXT: s_lshl_b32 s24, s56, 16 +; VI-NEXT: s_or_b32 s18, s18, s24 +; VI-NEXT: s_and_b32 s17, 0xffff, s17 +; VI-NEXT: s_lshl_b32 s24, s47, 16 +; VI-NEXT: s_or_b32 s17, s17, s24 +; VI-NEXT: s_and_b32 s16, 0xffff, s16 +; VI-NEXT: s_lshl_b32 s24, s46, 16 +; VI-NEXT: s_or_b32 s16, s16, s24 +; VI-NEXT: s_and_b32 s15, 0xffff, s15 +; VI-NEXT: s_lshl_b32 s24, s45, 16 +; VI-NEXT: s_or_b32 s15, s15, s24 +; VI-NEXT: s_and_b32 s14, 0xffff, s14 +; VI-NEXT: s_lshl_b32 s24, s44, 16 +; VI-NEXT: s_or_b32 s14, s14, s24 +; VI-NEXT: s_and_b32 s13, 0xffff, s13 +; VI-NEXT: s_lshl_b32 s24, s43, 16 +; VI-NEXT: s_or_b32 s13, s13, s24 +; VI-NEXT: s_and_b32 s12, 0xffff, s12 +; VI-NEXT: s_lshl_b32 s24, s42, 16 +; VI-NEXT: s_or_b32 s12, s12, s24 ; VI-NEXT: s_and_b32 s11, 0xffff, s11 -; VI-NEXT: s_lshl_b32 s28, s41, 16 -; VI-NEXT: s_or_b32 s11, s11, s28 +; VI-NEXT: s_lshl_b32 s24, s41, 16 +; VI-NEXT: s_or_b32 s11, s11, s24 ; VI-NEXT: s_and_b32 s10, 0xffff, s10 -; VI-NEXT: s_lshl_b32 s28, s40, 16 +; VI-NEXT: s_lshl_b32 s24, s40, 16 +; VI-NEXT: s_or_b32 s10, s10, s24 ; VI-NEXT: s_and_b32 s9, 0xffff, s9 -; VI-NEXT: s_lshl_b32 s15, s15, 16 +; VI-NEXT: s_lshl_b32 s24, s29, 16 +; VI-NEXT: s_or_b32 s9, s9, s24 ; VI-NEXT: s_and_b32 s8, 0xffff, s8 -; VI-NEXT: s_lshl_b32 s14, s14, 16 +; VI-NEXT: s_lshl_b32 s24, s28, 16 +; VI-NEXT: s_or_b32 s8, s8, s24 ; VI-NEXT: s_and_b32 s6, 0xffff, s6 -; VI-NEXT: s_lshl_b32 s13, s13, 16 +; VI-NEXT: s_lshl_b32 s24, s27, 16 +; VI-NEXT: s_or_b32 s6, s6, s24 ; VI-NEXT: s_and_b32 s7, 0xffff, s7 -; VI-NEXT: s_lshl_b32 s12, s12, 16 -; VI-NEXT: s_or_b32 s10, s10, s28 -; VI-NEXT: s_or_b32 s9, s9, s15 -; VI-NEXT: s_or_b32 s8, s8, s14 -; VI-NEXT: s_or_b32 s6, s6, s13 -; VI-NEXT: s_or_b32 s7, s7, s12 +; VI-NEXT: s_lshl_b32 s24, s26, 16 +; VI-NEXT: s_or_b32 s7, s7, s24 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v1, s5 -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: v_mov_b32_e32 v3, s17 -; VI-NEXT: v_mov_b32_e32 v4, s18 -; VI-NEXT: v_mov_b32_e32 v5, s19 -; VI-NEXT: v_mov_b32_e32 v6, s20 -; VI-NEXT: v_mov_b32_e32 v7, s21 -; VI-NEXT: v_mov_b32_e32 v8, s22 -; VI-NEXT: v_mov_b32_e32 v9, s23 -; VI-NEXT: v_mov_b32_e32 v10, s24 -; VI-NEXT: v_mov_b32_e32 v11, s25 -; VI-NEXT: v_mov_b32_e32 v12, s26 -; VI-NEXT: v_mov_b32_e32 v13, s27 +; VI-NEXT: v_mov_b32_e32 v2, s23 +; VI-NEXT: v_mov_b32_e32 v3, s22 +; VI-NEXT: v_mov_b32_e32 v4, s21 +; VI-NEXT: v_mov_b32_e32 v5, s20 +; VI-NEXT: v_mov_b32_e32 v6, s19 +; VI-NEXT: v_mov_b32_e32 v7, s18 +; VI-NEXT: v_mov_b32_e32 v8, s17 +; VI-NEXT: v_mov_b32_e32 v9, s16 +; VI-NEXT: v_mov_b32_e32 v10, s15 +; VI-NEXT: v_mov_b32_e32 v11, s14 +; VI-NEXT: v_mov_b32_e32 v12, s13 +; VI-NEXT: v_mov_b32_e32 v13, s12 ; VI-NEXT: v_mov_b32_e32 v14, s11 ; VI-NEXT: v_mov_b32_e32 v15, s10 ; VI-NEXT: v_mov_b32_e32 v16, s9 @@ -22325,57 +21886,75 @@ define inreg <40 x half> @bitcast_v10i64_to_v40f16_scalar(<10 x i64> inreg %a, i ; VI-NEXT: ; implicit-def: $sgpr42 ; VI-NEXT: ; implicit-def: $sgpr41 ; VI-NEXT: ; implicit-def: $sgpr40 -; VI-NEXT: ; implicit-def: $sgpr15 -; VI-NEXT: ; implicit-def: $sgpr14 -; VI-NEXT: ; implicit-def: $sgpr13 -; VI-NEXT: ; implicit-def: $sgpr12 +; VI-NEXT: ; implicit-def: $sgpr29 +; VI-NEXT: ; implicit-def: $sgpr28 +; VI-NEXT: ; implicit-def: $sgpr27 +; VI-NEXT: ; implicit-def: $sgpr26 ; VI-NEXT: s_branch .LBB45_2 ; ; GFX9-LABEL: bitcast_v10i64_to_v40f16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v7, s16 +; GFX9-NEXT: v_mov_b32_e32 v8, s17 +; GFX9-NEXT: v_mov_b32_e32 v9, s18 +; GFX9-NEXT: v_mov_b32_e32 v10, s19 +; GFX9-NEXT: v_mov_b32_e32 v11, s20 +; GFX9-NEXT: v_mov_b32_e32 v12, s21 +; GFX9-NEXT: v_mov_b32_e32 v13, s22 +; GFX9-NEXT: v_mov_b32_e32 v14, s23 +; GFX9-NEXT: v_mov_b32_e32 v15, s24 +; GFX9-NEXT: v_mov_b32_e32 v16, s25 +; GFX9-NEXT: v_mov_b32_e32 v17, s26 +; GFX9-NEXT: v_mov_b32_e32 v18, s27 +; GFX9-NEXT: v_mov_b32_e32 v19, s28 +; GFX9-NEXT: v_readfirstlane_b32 s6, v7 +; GFX9-NEXT: v_mov_b32_e32 v7, s29 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 -; GFX9-NEXT: v_readfirstlane_b32 s6, v0 -; GFX9-NEXT: v_readfirstlane_b32 s7, v1 -; GFX9-NEXT: v_readfirstlane_b32 s8, v2 -; GFX9-NEXT: v_readfirstlane_b32 s9, v3 -; GFX9-NEXT: v_readfirstlane_b32 s10, v4 +; GFX9-NEXT: v_readfirstlane_b32 s7, v8 +; GFX9-NEXT: v_readfirstlane_b32 s8, v9 +; GFX9-NEXT: v_readfirstlane_b32 s9, v10 +; GFX9-NEXT: v_readfirstlane_b32 s10, v11 +; GFX9-NEXT: v_readfirstlane_b32 s11, v12 +; GFX9-NEXT: v_readfirstlane_b32 s12, v13 +; GFX9-NEXT: v_readfirstlane_b32 s13, v14 +; GFX9-NEXT: v_readfirstlane_b32 s14, v15 +; GFX9-NEXT: v_readfirstlane_b32 s15, v16 +; GFX9-NEXT: v_readfirstlane_b32 s16, v17 +; GFX9-NEXT: v_readfirstlane_b32 s17, v18 +; GFX9-NEXT: v_readfirstlane_b32 s18, v19 +; GFX9-NEXT: v_readfirstlane_b32 s19, v7 +; GFX9-NEXT: v_readfirstlane_b32 s20, v0 +; GFX9-NEXT: v_readfirstlane_b32 s21, v1 +; GFX9-NEXT: v_readfirstlane_b32 s22, v2 +; GFX9-NEXT: v_readfirstlane_b32 s23, v3 +; GFX9-NEXT: v_readfirstlane_b32 s24, v4 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec -; GFX9-NEXT: v_readfirstlane_b32 s11, v5 +; GFX9-NEXT: v_readfirstlane_b32 s25, v5 ; GFX9-NEXT: s_cbranch_scc0 .LBB45_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false -; GFX9-NEXT: s_lshr_b32 s12, s11, 16 -; GFX9-NEXT: s_lshr_b32 s13, s10, 16 -; GFX9-NEXT: s_lshr_b32 s14, s9, 16 -; GFX9-NEXT: s_lshr_b32 s15, s8, 16 -; GFX9-NEXT: s_lshr_b32 s40, s7, 16 -; GFX9-NEXT: s_lshr_b32 s41, s6, 16 -; GFX9-NEXT: s_lshr_b32 s42, s29, 16 -; GFX9-NEXT: s_lshr_b32 s43, s28, 16 -; GFX9-NEXT: s_lshr_b32 s44, s27, 16 -; GFX9-NEXT: s_lshr_b32 s45, s26, 16 -; GFX9-NEXT: s_lshr_b32 s46, s25, 16 -; GFX9-NEXT: s_lshr_b32 s47, s24, 16 -; GFX9-NEXT: s_lshr_b32 s56, s23, 16 -; GFX9-NEXT: s_lshr_b32 s57, s22, 16 -; GFX9-NEXT: s_lshr_b32 s58, s21, 16 -; GFX9-NEXT: s_lshr_b32 s59, s20, 16 -; GFX9-NEXT: s_lshr_b32 s60, s19, 16 -; GFX9-NEXT: s_lshr_b32 s61, s18, 16 -; GFX9-NEXT: s_lshr_b32 s62, s17, 16 -; GFX9-NEXT: s_lshr_b32 s63, s16, 16 +; GFX9-NEXT: s_lshr_b32 s26, s25, 16 +; GFX9-NEXT: s_lshr_b32 s27, s24, 16 +; GFX9-NEXT: s_lshr_b32 s28, s23, 16 +; GFX9-NEXT: s_lshr_b32 s29, s22, 16 +; GFX9-NEXT: s_lshr_b32 s40, s21, 16 +; GFX9-NEXT: s_lshr_b32 s41, s20, 16 +; GFX9-NEXT: s_lshr_b32 s42, s19, 16 +; GFX9-NEXT: s_lshr_b32 s43, s18, 16 +; GFX9-NEXT: s_lshr_b32 s44, s17, 16 +; GFX9-NEXT: s_lshr_b32 s45, s16, 16 +; GFX9-NEXT: s_lshr_b32 s46, s15, 16 +; GFX9-NEXT: s_lshr_b32 s47, s14, 16 +; GFX9-NEXT: s_lshr_b32 s56, s13, 16 +; GFX9-NEXT: s_lshr_b32 s57, s12, 16 +; GFX9-NEXT: s_lshr_b32 s58, s11, 16 +; GFX9-NEXT: s_lshr_b32 s59, s10, 16 +; GFX9-NEXT: s_lshr_b32 s60, s9, 16 +; GFX9-NEXT: s_lshr_b32 s61, s8, 16 +; GFX9-NEXT: s_lshr_b32 s62, s7, 16 +; GFX9-NEXT: s_lshr_b32 s63, s6, 16 ; GFX9-NEXT: s_cbranch_execnz .LBB45_3 ; GFX9-NEXT: .LBB45_2: ; %cmp.true -; GFX9-NEXT: s_add_u32 s10, s10, 3 -; GFX9-NEXT: s_addc_u32 s11, s11, 0 -; GFX9-NEXT: s_add_u32 s8, s8, 3 -; GFX9-NEXT: s_addc_u32 s9, s9, 0 -; GFX9-NEXT: s_add_u32 s6, s6, 3 -; GFX9-NEXT: s_addc_u32 s7, s7, 0 -; GFX9-NEXT: s_add_u32 s28, s28, 3 -; GFX9-NEXT: s_addc_u32 s29, s29, 0 -; GFX9-NEXT: s_add_u32 s26, s26, 3 -; GFX9-NEXT: s_addc_u32 s27, s27, 0 ; GFX9-NEXT: s_add_u32 s24, s24, 3 ; GFX9-NEXT: s_addc_u32 s25, s25, 0 ; GFX9-NEXT: s_add_u32 s22, s22, 3 @@ -22386,67 +21965,77 @@ define inreg <40 x half> @bitcast_v10i64_to_v40f16_scalar(<10 x i64> inreg %a, i ; GFX9-NEXT: s_addc_u32 s19, s19, 0 ; GFX9-NEXT: s_add_u32 s16, s16, 3 ; GFX9-NEXT: s_addc_u32 s17, s17, 0 -; GFX9-NEXT: s_lshr_b32 s12, s11, 16 -; GFX9-NEXT: s_lshr_b32 s13, s10, 16 -; GFX9-NEXT: s_lshr_b32 s14, s9, 16 -; GFX9-NEXT: s_lshr_b32 s15, s8, 16 -; GFX9-NEXT: s_lshr_b32 s40, s7, 16 -; GFX9-NEXT: s_lshr_b32 s41, s6, 16 -; GFX9-NEXT: s_lshr_b32 s42, s29, 16 -; GFX9-NEXT: s_lshr_b32 s43, s28, 16 -; GFX9-NEXT: s_lshr_b32 s44, s27, 16 -; GFX9-NEXT: s_lshr_b32 s45, s26, 16 -; GFX9-NEXT: s_lshr_b32 s46, s25, 16 -; GFX9-NEXT: s_lshr_b32 s47, s24, 16 -; GFX9-NEXT: s_lshr_b32 s56, s23, 16 -; GFX9-NEXT: s_lshr_b32 s57, s22, 16 -; GFX9-NEXT: s_lshr_b32 s58, s21, 16 -; GFX9-NEXT: s_lshr_b32 s59, s20, 16 -; GFX9-NEXT: s_lshr_b32 s60, s19, 16 -; GFX9-NEXT: s_lshr_b32 s61, s18, 16 -; GFX9-NEXT: s_lshr_b32 s62, s17, 16 -; GFX9-NEXT: s_lshr_b32 s63, s16, 16 +; GFX9-NEXT: s_add_u32 s14, s14, 3 +; GFX9-NEXT: s_addc_u32 s15, s15, 0 +; GFX9-NEXT: s_add_u32 s12, s12, 3 +; GFX9-NEXT: s_addc_u32 s13, s13, 0 +; GFX9-NEXT: s_add_u32 s10, s10, 3 +; GFX9-NEXT: s_addc_u32 s11, s11, 0 +; GFX9-NEXT: s_add_u32 s8, s8, 3 +; GFX9-NEXT: s_addc_u32 s9, s9, 0 +; GFX9-NEXT: s_add_u32 s6, s6, 3 +; GFX9-NEXT: s_addc_u32 s7, s7, 0 +; GFX9-NEXT: s_lshr_b32 s26, s25, 16 +; GFX9-NEXT: s_lshr_b32 s27, s24, 16 +; GFX9-NEXT: s_lshr_b32 s28, s23, 16 +; GFX9-NEXT: s_lshr_b32 s29, s22, 16 +; GFX9-NEXT: s_lshr_b32 s40, s21, 16 +; GFX9-NEXT: s_lshr_b32 s41, s20, 16 +; GFX9-NEXT: s_lshr_b32 s42, s19, 16 +; GFX9-NEXT: s_lshr_b32 s43, s18, 16 +; GFX9-NEXT: s_lshr_b32 s44, s17, 16 +; GFX9-NEXT: s_lshr_b32 s45, s16, 16 +; GFX9-NEXT: s_lshr_b32 s46, s15, 16 +; GFX9-NEXT: s_lshr_b32 s47, s14, 16 +; GFX9-NEXT: s_lshr_b32 s56, s13, 16 +; GFX9-NEXT: s_lshr_b32 s57, s12, 16 +; GFX9-NEXT: s_lshr_b32 s58, s11, 16 +; GFX9-NEXT: s_lshr_b32 s59, s10, 16 +; GFX9-NEXT: s_lshr_b32 s60, s9, 16 +; GFX9-NEXT: s_lshr_b32 s61, s8, 16 +; GFX9-NEXT: s_lshr_b32 s62, s7, 16 +; GFX9-NEXT: s_lshr_b32 s63, s6, 16 ; GFX9-NEXT: .LBB45_3: ; %end -; GFX9-NEXT: s_pack_ll_b32_b16 s4, s16, s63 -; GFX9-NEXT: s_pack_ll_b32_b16 s5, s17, s62 -; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s61 -; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s60 -; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s59 -; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s58 -; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s57 -; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s56 -; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s47 -; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s46 -; GFX9-NEXT: s_pack_ll_b32_b16 s24, s26, s45 -; GFX9-NEXT: s_pack_ll_b32_b16 s25, s27, s44 -; GFX9-NEXT: s_pack_ll_b32_b16 s26, s28, s43 -; GFX9-NEXT: s_pack_ll_b32_b16 s27, s29, s42 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s41 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s40 -; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s15 -; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s14 -; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s13 -; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s12 +; GFX9-NEXT: s_pack_ll_b32_b16 s4, s6, s63 +; GFX9-NEXT: s_pack_ll_b32_b16 s5, s7, s62 +; GFX9-NEXT: s_pack_ll_b32_b16 s6, s8, s61 +; GFX9-NEXT: s_pack_ll_b32_b16 s7, s9, s60 +; GFX9-NEXT: s_pack_ll_b32_b16 s8, s10, s59 +; GFX9-NEXT: s_pack_ll_b32_b16 s9, s11, s58 +; GFX9-NEXT: s_pack_ll_b32_b16 s10, s12, s57 +; GFX9-NEXT: s_pack_ll_b32_b16 s11, s13, s56 +; GFX9-NEXT: s_pack_ll_b32_b16 s12, s14, s47 +; GFX9-NEXT: s_pack_ll_b32_b16 s13, s15, s46 +; GFX9-NEXT: s_pack_ll_b32_b16 s14, s16, s45 +; GFX9-NEXT: s_pack_ll_b32_b16 s15, s17, s44 +; GFX9-NEXT: s_pack_ll_b32_b16 s16, s18, s43 +; GFX9-NEXT: s_pack_ll_b32_b16 s17, s19, s42 +; GFX9-NEXT: s_pack_ll_b32_b16 s18, s20, s41 +; GFX9-NEXT: s_pack_ll_b32_b16 s19, s21, s40 +; GFX9-NEXT: s_pack_ll_b32_b16 s20, s22, s29 +; GFX9-NEXT: s_pack_ll_b32_b16 s21, s23, s28 +; GFX9-NEXT: s_pack_ll_b32_b16 s22, s24, s27 +; GFX9-NEXT: s_pack_ll_b32_b16 s23, s25, s26 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s5 -; GFX9-NEXT: v_mov_b32_e32 v2, s16 -; GFX9-NEXT: v_mov_b32_e32 v3, s17 -; GFX9-NEXT: v_mov_b32_e32 v4, s18 -; GFX9-NEXT: v_mov_b32_e32 v5, s19 -; GFX9-NEXT: v_mov_b32_e32 v6, s20 -; GFX9-NEXT: v_mov_b32_e32 v7, s21 -; GFX9-NEXT: v_mov_b32_e32 v8, s22 -; GFX9-NEXT: v_mov_b32_e32 v9, s23 -; GFX9-NEXT: v_mov_b32_e32 v10, s24 -; GFX9-NEXT: v_mov_b32_e32 v11, s25 -; GFX9-NEXT: v_mov_b32_e32 v12, s26 -; GFX9-NEXT: v_mov_b32_e32 v13, s27 -; GFX9-NEXT: v_mov_b32_e32 v14, s6 -; GFX9-NEXT: v_mov_b32_e32 v15, s7 -; GFX9-NEXT: v_mov_b32_e32 v16, s8 -; GFX9-NEXT: v_mov_b32_e32 v17, s9 -; GFX9-NEXT: v_mov_b32_e32 v18, s10 -; GFX9-NEXT: v_mov_b32_e32 v19, s11 +; GFX9-NEXT: v_mov_b32_e32 v2, s6 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: v_mov_b32_e32 v4, s8 +; GFX9-NEXT: v_mov_b32_e32 v5, s9 +; GFX9-NEXT: v_mov_b32_e32 v6, s10 +; GFX9-NEXT: v_mov_b32_e32 v7, s11 +; GFX9-NEXT: v_mov_b32_e32 v8, s12 +; GFX9-NEXT: v_mov_b32_e32 v9, s13 +; GFX9-NEXT: v_mov_b32_e32 v10, s14 +; GFX9-NEXT: v_mov_b32_e32 v11, s15 +; GFX9-NEXT: v_mov_b32_e32 v12, s16 +; GFX9-NEXT: v_mov_b32_e32 v13, s17 +; GFX9-NEXT: v_mov_b32_e32 v14, s18 +; GFX9-NEXT: v_mov_b32_e32 v15, s19 +; GFX9-NEXT: v_mov_b32_e32 v16, s20 +; GFX9-NEXT: v_mov_b32_e32 v17, s21 +; GFX9-NEXT: v_mov_b32_e32 v18, s22 +; GFX9-NEXT: v_mov_b32_e32 v19, s23 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: .LBB45_4: ; GFX9-NEXT: ; implicit-def: $sgpr63 @@ -22465,38 +22054,65 @@ define inreg <40 x half> @bitcast_v10i64_to_v40f16_scalar(<10 x i64> inreg %a, i ; GFX9-NEXT: ; implicit-def: $sgpr42 ; GFX9-NEXT: ; implicit-def: $sgpr41 ; GFX9-NEXT: ; implicit-def: $sgpr40 -; GFX9-NEXT: ; implicit-def: $sgpr15 -; GFX9-NEXT: ; implicit-def: $sgpr14 -; GFX9-NEXT: ; implicit-def: $sgpr13 -; GFX9-NEXT: ; implicit-def: $sgpr12 +; GFX9-NEXT: ; implicit-def: $sgpr29 +; GFX9-NEXT: ; implicit-def: $sgpr28 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr26 ; GFX9-NEXT: s_branch .LBB45_2 ; ; GFX11-LABEL: bitcast_v10i64_to_v40f16_scalar: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v3, s0 :: v_dual_mov_b32 v4, s1 +; GFX11-NEXT: v_dual_mov_b32 v5, s2 :: v_dual_mov_b32 v6, s3 +; GFX11-NEXT: v_dual_mov_b32 v7, s16 :: v_dual_mov_b32 v8, s17 +; GFX11-NEXT: v_dual_mov_b32 v9, s18 :: v_dual_mov_b32 v10, s19 +; GFX11-NEXT: v_dual_mov_b32 v11, s20 :: v_dual_mov_b32 v12, s21 +; GFX11-NEXT: v_dual_mov_b32 v13, s22 :: v_dual_mov_b32 v14, s23 +; GFX11-NEXT: v_dual_mov_b32 v15, s24 :: v_dual_mov_b32 v16, s25 +; GFX11-NEXT: v_dual_mov_b32 v17, s26 :: v_dual_mov_b32 v18, s27 +; GFX11-NEXT: v_dual_mov_b32 v19, s28 :: v_dual_mov_b32 v20, s29 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 -; GFX11-NEXT: v_readfirstlane_b32 s5, v0 -; GFX11-NEXT: v_readfirstlane_b32 s4, v1 +; GFX11-NEXT: v_readfirstlane_b32 s0, v3 +; GFX11-NEXT: v_readfirstlane_b32 s1, v4 +; GFX11-NEXT: v_readfirstlane_b32 s2, v5 +; GFX11-NEXT: v_readfirstlane_b32 s3, v6 +; GFX11-NEXT: v_readfirstlane_b32 s4, v7 +; GFX11-NEXT: v_readfirstlane_b32 s5, v8 +; GFX11-NEXT: v_readfirstlane_b32 s6, v9 +; GFX11-NEXT: v_readfirstlane_b32 s7, v10 +; GFX11-NEXT: v_readfirstlane_b32 s8, v11 +; GFX11-NEXT: v_readfirstlane_b32 s9, v12 +; GFX11-NEXT: v_readfirstlane_b32 s10, v13 +; GFX11-NEXT: v_readfirstlane_b32 s11, v14 +; GFX11-NEXT: v_readfirstlane_b32 s12, v15 +; GFX11-NEXT: v_readfirstlane_b32 s13, v16 +; GFX11-NEXT: v_readfirstlane_b32 s14, v17 +; GFX11-NEXT: v_readfirstlane_b32 s15, v18 +; GFX11-NEXT: v_readfirstlane_b32 s16, v19 +; GFX11-NEXT: v_readfirstlane_b32 s17, v20 +; GFX11-NEXT: v_readfirstlane_b32 s19, v0 +; GFX11-NEXT: v_readfirstlane_b32 s18, v1 ; GFX11-NEXT: s_mov_b32 s58, 0 -; GFX11-NEXT: s_and_b32 s6, vcc_lo, exec_lo +; GFX11-NEXT: s_and_b32 s20, vcc_lo, exec_lo ; GFX11-NEXT: s_cbranch_scc0 .LBB45_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: s_lshr_b32 s6, s4, 16 -; GFX11-NEXT: s_lshr_b32 s7, s5, 16 -; GFX11-NEXT: s_lshr_b32 s8, s29, 16 -; GFX11-NEXT: s_lshr_b32 s9, s28, 16 -; GFX11-NEXT: s_lshr_b32 s10, s27, 16 -; GFX11-NEXT: s_lshr_b32 s11, s26, 16 -; GFX11-NEXT: s_lshr_b32 s12, s25, 16 -; GFX11-NEXT: s_lshr_b32 s13, s24, 16 -; GFX11-NEXT: s_lshr_b32 s14, s23, 16 -; GFX11-NEXT: s_lshr_b32 s15, s22, 16 -; GFX11-NEXT: s_lshr_b32 s40, s21, 16 -; GFX11-NEXT: s_lshr_b32 s41, s20, 16 -; GFX11-NEXT: s_lshr_b32 s42, s19, 16 -; GFX11-NEXT: s_lshr_b32 s43, s18, 16 -; GFX11-NEXT: s_lshr_b32 s44, s17, 16 -; GFX11-NEXT: s_lshr_b32 s45, s16, 16 +; GFX11-NEXT: s_lshr_b32 s20, s18, 16 +; GFX11-NEXT: s_lshr_b32 s21, s19, 16 +; GFX11-NEXT: s_lshr_b32 s22, s17, 16 +; GFX11-NEXT: s_lshr_b32 s23, s16, 16 +; GFX11-NEXT: s_lshr_b32 s24, s15, 16 +; GFX11-NEXT: s_lshr_b32 s25, s14, 16 +; GFX11-NEXT: s_lshr_b32 s26, s13, 16 +; GFX11-NEXT: s_lshr_b32 s27, s12, 16 +; GFX11-NEXT: s_lshr_b32 s28, s11, 16 +; GFX11-NEXT: s_lshr_b32 s29, s10, 16 +; GFX11-NEXT: s_lshr_b32 s40, s9, 16 +; GFX11-NEXT: s_lshr_b32 s41, s8, 16 +; GFX11-NEXT: s_lshr_b32 s42, s7, 16 +; GFX11-NEXT: s_lshr_b32 s43, s6, 16 +; GFX11-NEXT: s_lshr_b32 s44, s5, 16 +; GFX11-NEXT: s_lshr_b32 s45, s4, 16 ; GFX11-NEXT: s_lshr_b32 s46, s3, 16 ; GFX11-NEXT: s_lshr_b32 s47, s2, 16 ; GFX11-NEXT: s_lshr_b32 s56, s1, 16 @@ -22504,42 +22120,42 @@ define inreg <40 x half> @bitcast_v10i64_to_v40f16_scalar(<10 x i64> inreg %a, i ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58 ; GFX11-NEXT: s_cbranch_vccnz .LBB45_3 ; GFX11-NEXT: .LBB45_2: ; %cmp.true -; GFX11-NEXT: s_add_u32 s5, s5, 3 -; GFX11-NEXT: s_addc_u32 s4, s4, 0 -; GFX11-NEXT: s_add_u32 s28, s28, 3 -; GFX11-NEXT: s_addc_u32 s29, s29, 0 -; GFX11-NEXT: s_add_u32 s26, s26, 3 -; GFX11-NEXT: s_addc_u32 s27, s27, 0 -; GFX11-NEXT: s_add_u32 s24, s24, 3 -; GFX11-NEXT: s_addc_u32 s25, s25, 0 -; GFX11-NEXT: s_add_u32 s22, s22, 3 -; GFX11-NEXT: s_addc_u32 s23, s23, 0 -; GFX11-NEXT: s_add_u32 s20, s20, 3 -; GFX11-NEXT: s_addc_u32 s21, s21, 0 -; GFX11-NEXT: s_add_u32 s18, s18, 3 -; GFX11-NEXT: s_addc_u32 s19, s19, 0 +; GFX11-NEXT: s_add_u32 s19, s19, 3 +; GFX11-NEXT: s_addc_u32 s18, s18, 0 ; GFX11-NEXT: s_add_u32 s16, s16, 3 ; GFX11-NEXT: s_addc_u32 s17, s17, 0 +; GFX11-NEXT: s_add_u32 s14, s14, 3 +; GFX11-NEXT: s_addc_u32 s15, s15, 0 +; GFX11-NEXT: s_add_u32 s12, s12, 3 +; GFX11-NEXT: s_addc_u32 s13, s13, 0 +; GFX11-NEXT: s_add_u32 s10, s10, 3 +; GFX11-NEXT: s_addc_u32 s11, s11, 0 +; GFX11-NEXT: s_add_u32 s8, s8, 3 +; GFX11-NEXT: s_addc_u32 s9, s9, 0 +; GFX11-NEXT: s_add_u32 s6, s6, 3 +; GFX11-NEXT: s_addc_u32 s7, s7, 0 +; GFX11-NEXT: s_add_u32 s4, s4, 3 +; GFX11-NEXT: s_addc_u32 s5, s5, 0 ; GFX11-NEXT: s_add_u32 s2, s2, 3 ; GFX11-NEXT: s_addc_u32 s3, s3, 0 ; GFX11-NEXT: s_add_u32 s0, s0, 3 ; GFX11-NEXT: s_addc_u32 s1, s1, 0 -; GFX11-NEXT: s_lshr_b32 s6, s4, 16 -; GFX11-NEXT: s_lshr_b32 s7, s5, 16 -; GFX11-NEXT: s_lshr_b32 s8, s29, 16 -; GFX11-NEXT: s_lshr_b32 s9, s28, 16 -; GFX11-NEXT: s_lshr_b32 s10, s27, 16 -; GFX11-NEXT: s_lshr_b32 s11, s26, 16 -; GFX11-NEXT: s_lshr_b32 s12, s25, 16 -; GFX11-NEXT: s_lshr_b32 s13, s24, 16 -; GFX11-NEXT: s_lshr_b32 s14, s23, 16 -; GFX11-NEXT: s_lshr_b32 s15, s22, 16 -; GFX11-NEXT: s_lshr_b32 s40, s21, 16 -; GFX11-NEXT: s_lshr_b32 s41, s20, 16 -; GFX11-NEXT: s_lshr_b32 s42, s19, 16 -; GFX11-NEXT: s_lshr_b32 s43, s18, 16 -; GFX11-NEXT: s_lshr_b32 s44, s17, 16 -; GFX11-NEXT: s_lshr_b32 s45, s16, 16 +; GFX11-NEXT: s_lshr_b32 s20, s18, 16 +; GFX11-NEXT: s_lshr_b32 s21, s19, 16 +; GFX11-NEXT: s_lshr_b32 s22, s17, 16 +; GFX11-NEXT: s_lshr_b32 s23, s16, 16 +; GFX11-NEXT: s_lshr_b32 s24, s15, 16 +; GFX11-NEXT: s_lshr_b32 s25, s14, 16 +; GFX11-NEXT: s_lshr_b32 s26, s13, 16 +; GFX11-NEXT: s_lshr_b32 s27, s12, 16 +; GFX11-NEXT: s_lshr_b32 s28, s11, 16 +; GFX11-NEXT: s_lshr_b32 s29, s10, 16 +; GFX11-NEXT: s_lshr_b32 s40, s9, 16 +; GFX11-NEXT: s_lshr_b32 s41, s8, 16 +; GFX11-NEXT: s_lshr_b32 s42, s7, 16 +; GFX11-NEXT: s_lshr_b32 s43, s6, 16 +; GFX11-NEXT: s_lshr_b32 s44, s5, 16 +; GFX11-NEXT: s_lshr_b32 s45, s4, 16 ; GFX11-NEXT: s_lshr_b32 s46, s3, 16 ; GFX11-NEXT: s_lshr_b32 s47, s2, 16 ; GFX11-NEXT: s_lshr_b32 s56, s1, 16 @@ -22550,32 +22166,32 @@ define inreg <40 x half> @bitcast_v10i64_to_v40f16_scalar(<10 x i64> inreg %a, i ; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s56 ; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s47 ; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s46 -; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s45 -; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s44 -; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s43 -; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s42 -; GFX11-NEXT: s_pack_ll_b32_b16 s20, s20, s41 -; GFX11-NEXT: s_pack_ll_b32_b16 s21, s21, s40 -; GFX11-NEXT: s_pack_ll_b32_b16 s15, s22, s15 -; GFX11-NEXT: s_pack_ll_b32_b16 s14, s23, s14 -; GFX11-NEXT: s_pack_ll_b32_b16 s13, s24, s13 -; GFX11-NEXT: s_pack_ll_b32_b16 s12, s25, s12 -; GFX11-NEXT: s_pack_ll_b32_b16 s11, s26, s11 -; GFX11-NEXT: s_pack_ll_b32_b16 s10, s27, s10 -; GFX11-NEXT: s_pack_ll_b32_b16 s9, s28, s9 -; GFX11-NEXT: s_pack_ll_b32_b16 s8, s29, s8 -; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s7 -; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s6 +; GFX11-NEXT: s_pack_ll_b32_b16 s4, s4, s45 +; GFX11-NEXT: s_pack_ll_b32_b16 s5, s5, s44 +; GFX11-NEXT: s_pack_ll_b32_b16 s6, s6, s43 +; GFX11-NEXT: s_pack_ll_b32_b16 s7, s7, s42 +; GFX11-NEXT: s_pack_ll_b32_b16 s8, s8, s41 +; GFX11-NEXT: s_pack_ll_b32_b16 s9, s9, s40 +; GFX11-NEXT: s_pack_ll_b32_b16 s10, s10, s29 +; GFX11-NEXT: s_pack_ll_b32_b16 s11, s11, s28 +; GFX11-NEXT: s_pack_ll_b32_b16 s12, s12, s27 +; GFX11-NEXT: s_pack_ll_b32_b16 s13, s13, s26 +; GFX11-NEXT: s_pack_ll_b32_b16 s14, s14, s25 +; GFX11-NEXT: s_pack_ll_b32_b16 s15, s15, s24 +; GFX11-NEXT: s_pack_ll_b32_b16 s16, s16, s23 +; GFX11-NEXT: s_pack_ll_b32_b16 s17, s17, s22 +; GFX11-NEXT: s_pack_ll_b32_b16 s19, s19, s21 +; GFX11-NEXT: s_pack_ll_b32_b16 s18, s18, s20 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 -; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 -; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 -; GFX11-NEXT: v_dual_mov_b32 v10, s15 :: v_dual_mov_b32 v11, s14 -; GFX11-NEXT: v_dual_mov_b32 v12, s13 :: v_dual_mov_b32 v13, s12 -; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v15, s10 -; GFX11-NEXT: v_dual_mov_b32 v16, s9 :: v_dual_mov_b32 v17, s8 -; GFX11-NEXT: v_dual_mov_b32 v18, s5 :: v_dual_mov_b32 v19, s4 +; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-NEXT: v_dual_mov_b32 v18, s19 :: v_dual_mov_b32 v19, s18 ; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: .LBB45_4: ; GFX11-NEXT: ; implicit-def: $sgpr57 @@ -22588,16 +22204,16 @@ define inreg <40 x half> @bitcast_v10i64_to_v40f16_scalar(<10 x i64> inreg %a, i ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr41 ; GFX11-NEXT: ; implicit-def: $sgpr40 -; GFX11-NEXT: ; implicit-def: $sgpr15 -; GFX11-NEXT: ; implicit-def: $sgpr14 -; GFX11-NEXT: ; implicit-def: $sgpr13 -; GFX11-NEXT: ; implicit-def: $sgpr12 -; GFX11-NEXT: ; implicit-def: $sgpr11 -; GFX11-NEXT: ; implicit-def: $sgpr10 -; GFX11-NEXT: ; implicit-def: $sgpr9 -; GFX11-NEXT: ; implicit-def: $sgpr8 -; GFX11-NEXT: ; implicit-def: $sgpr7 -; GFX11-NEXT: ; implicit-def: $sgpr6 +; GFX11-NEXT: ; implicit-def: $sgpr29 +; GFX11-NEXT: ; implicit-def: $sgpr28 +; GFX11-NEXT: ; implicit-def: $sgpr27 +; GFX11-NEXT: ; implicit-def: $sgpr26 +; GFX11-NEXT: ; implicit-def: $sgpr25 +; GFX11-NEXT: ; implicit-def: $sgpr24 +; GFX11-NEXT: ; implicit-def: $sgpr23 +; GFX11-NEXT: ; implicit-def: $sgpr22 +; GFX11-NEXT: ; implicit-def: $sgpr21 +; GFX11-NEXT: ; implicit-def: $sgpr20 ; GFX11-NEXT: s_branch .LBB45_2 %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -24238,269 +23854,100 @@ define inreg <10 x i64> @bitcast_v40f16_to_v10i64_scalar(<40 x half> inreg %a, i ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44 -; GFX11-TRUE16-NEXT: s_clause 0xa -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB47_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB47_3 ; GFX11-TRUE16-NEXT: .LBB47_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s40 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s41 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v186, 0x200, v186 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v185, 0x200, v185 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s0 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s1 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s2 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, s3 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, s4 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v35, 0x200, s5 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v44, 0x200, s6 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v54, 0x200, s7 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v65, 0x200, s8 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v77, 0x200, s9 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v90, 0x200, s10 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v104, 0x200, s11 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v119, 0x200, s12 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v135, 0x200, s13 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v152, 0x200, s14 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v170, 0x200, s15 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, s6 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, s7 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, s8 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s9 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, s10 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, s11 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, s12 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, s13 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s14 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, s15 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, s16 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: .LBB47_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v17, v170 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v186 :: v_dual_mov_b32 v19, v185 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xa -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:296 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v14, v119 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB47_4: -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB47_2 ; ; GFX11-FAKE16-LABEL: bitcast_v40f16_to_v10i64_scalar: @@ -25988,6 +25435,17 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) { ; SI-LABEL: bitcast_v40i16_to_v10f64: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_mov_b32_e32 v52, v6 +; SI-NEXT: v_mov_b32_e32 v53, v4 +; SI-NEXT: v_mov_b32_e32 v54, v2 +; SI-NEXT: v_mov_b32_e32 v55, v0 +; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:36 +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:28 +; SI-NEXT: v_mov_b32_e32 v49, v12 +; SI-NEXT: v_mov_b32_e32 v50, v10 +; SI-NEXT: v_mov_b32_e32 v51, v8 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill @@ -26009,17 +25467,6 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v52, v6 -; SI-NEXT: v_mov_b32_e32 v53, v4 -; SI-NEXT: v_mov_b32_e32 v54, v2 -; SI-NEXT: v_mov_b32_e32 v55, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:36 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32 -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:28 -; SI-NEXT: v_mov_b32_e32 v49, v12 -; SI-NEXT: v_mov_b32_e32 v50, v10 -; SI-NEXT: v_mov_b32_e32 v51, v8 ; SI-NEXT: v_mov_b32_e32 v37, v20 ; SI-NEXT: v_mov_b32_e32 v38, v18 ; SI-NEXT: v_mov_b32_e32 v39, v16 @@ -26041,13 +25488,10 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) { ; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v27 ; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v29 ; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:4 -; SI-NEXT: s_waitcnt vmcnt(4) +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v0 -; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v4 -; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24 @@ -26273,7 +25717,7 @@ define <10 x double> @bitcast_v40i16_to_v10f64(<40 x i16> %a, i32 %b) { ; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15 ; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v17 ; SI-NEXT: v_add_i32_e32 v18, vcc, s6, v18 -; SI-NEXT: v_add_i32_e32 v19, vcc, s6, v19 +; SI-NEXT: v_add_i32_e32 v19, vcc, 0x30000, v19 ; SI-NEXT: .LBB50_4: ; %end ; SI-NEXT: s_or_b64 exec, exec, s[4:5] ; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload @@ -27361,269 +26805,100 @@ define inreg <10 x double> @bitcast_v40i16_to_v10f64_scalar(<40 x i16> inreg %a, ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44 -; GFX11-TRUE16-NEXT: s_clause 0xa -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB51_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB51_3 ; GFX11-TRUE16-NEXT: .LBB51_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s40, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s41, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v186, v186, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v185, v185, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s0, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s1, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s2, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v20, s3, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v27, s4, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v35, s5, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v44, s6, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v54, s7, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v65, s8, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v77, s9, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v90, s10, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v104, s11, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v119, s12, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v135, s13, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v152, s14, 3 op_sel_hi:[1,0] -; GFX11-TRUE16-NEXT: v_pk_add_u16 v170, s15, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, s6, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, s7, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, s8, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, s9, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, s10, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, s11, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, s12, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, s13, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, s14, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, s15, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, s16, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v17, s17, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0] +; GFX11-TRUE16-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0] ; GFX11-TRUE16-NEXT: .LBB51_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v17, v170 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v186 :: v_dual_mov_b32 v19, v185 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xa -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:296 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v14, v119 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB51_4: -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB51_2 ; ; GFX11-FAKE16-LABEL: bitcast_v40i16_to_v10f64_scalar: @@ -28485,341 +27760,368 @@ define inreg <40 x half> @bitcast_v10f64_to_v40f16_scalar(<10 x double> inreg %a ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 -; SI-NEXT: v_readfirstlane_b32 s8, v1 -; SI-NEXT: v_readfirstlane_b32 s9, v2 -; SI-NEXT: v_readfirstlane_b32 s6, v3 -; SI-NEXT: v_readfirstlane_b32 s7, v4 -; SI-NEXT: v_readfirstlane_b32 s4, v5 -; SI-NEXT: s_and_b64 s[10:11], vcc, exec -; SI-NEXT: v_readfirstlane_b32 s5, v6 -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v20, s16 +; SI-NEXT: v_mov_b32_e32 v21, s17 +; SI-NEXT: v_mov_b32_e32 v18, s18 +; SI-NEXT: v_mov_b32_e32 v19, s19 +; SI-NEXT: v_mov_b32_e32 v16, s20 +; SI-NEXT: v_mov_b32_e32 v17, s21 +; SI-NEXT: v_mov_b32_e32 v14, s22 +; SI-NEXT: v_mov_b32_e32 v15, s23 +; SI-NEXT: v_mov_b32_e32 v12, s24 +; SI-NEXT: v_mov_b32_e32 v13, s25 +; SI-NEXT: v_mov_b32_e32 v8, s26 +; SI-NEXT: v_mov_b32_e32 v9, s27 +; SI-NEXT: s_and_b64 s[4:5], vcc, exec +; SI-NEXT: v_mov_b32_e32 v10, s28 +; SI-NEXT: v_mov_b32_e32 v11, s29 +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB53_4 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: s_lshr_b32 s10, s5, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v1, s10 -; SI-NEXT: s_lshr_b32 s10, s4, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v2, s10 -; SI-NEXT: s_lshr_b32 s10, s7, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v4, s10 -; SI-NEXT: s_lshr_b32 s10, s6, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v6, s10 -; SI-NEXT: s_lshr_b32 s10, s9, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v8, s10 -; SI-NEXT: s_lshr_b32 s10, s8, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v10, s10 -; SI-NEXT: s_lshr_b32 s10, s29, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v12, s10 -; SI-NEXT: s_lshr_b32 s10, s28, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v14, s10 -; SI-NEXT: s_lshr_b32 s10, s27, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v16, s10 -; SI-NEXT: s_lshr_b32 s10, s26, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v19, s10 -; SI-NEXT: s_lshr_b32 s10, s25, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v21, s10 -; SI-NEXT: s_lshr_b32 s10, s24, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v23, s10 -; SI-NEXT: s_lshr_b32 s10, s23, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v25, s10 -; SI-NEXT: s_lshr_b32 s10, s22, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v27, s10 -; SI-NEXT: s_lshr_b32 s10, s21, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s10 -; SI-NEXT: s_lshr_b32 s10, s20, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v31, s10 -; SI-NEXT: s_lshr_b32 s10, s19, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v34, s10 -; SI-NEXT: s_lshr_b32 s10, s18, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v36, s10 -; SI-NEXT: s_lshr_b32 s10, s17, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v38, s10 -; SI-NEXT: s_lshr_b32 s10, s16, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v48, s10 -; SI-NEXT: v_cvt_f32_f16_e32 v3, s5 -; SI-NEXT: v_cvt_f32_f16_e32 v5, s4 -; SI-NEXT: v_cvt_f32_f16_e32 v7, s7 -; SI-NEXT: v_cvt_f32_f16_e32 v9, s6 -; SI-NEXT: v_cvt_f32_f16_e32 v11, s9 -; SI-NEXT: v_cvt_f32_f16_e32 v13, s8 -; SI-NEXT: v_cvt_f32_f16_e32 v15, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v17, s28 -; SI-NEXT: v_cvt_f32_f16_e32 v18, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v20, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v22, s25 -; SI-NEXT: v_cvt_f32_f16_e32 v24, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v26, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v28, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v30, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v32, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v33, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v35, s18 -; SI-NEXT: v_cvt_f32_f16_e32 v37, s17 -; SI-NEXT: v_cvt_f32_f16_e32 v39, s16 -; SI-NEXT: s_cbranch_execnz .LBB53_3 -; SI-NEXT: .LBB53_2: ; %cmp.true -; SI-NEXT: v_add_f64 v[1:2], s[16:17], 1.0 -; SI-NEXT: v_add_f64 v[34:35], s[18:19], 1.0 -; SI-NEXT: v_add_f64 v[29:30], s[20:21], 1.0 -; SI-NEXT: v_add_f64 v[25:26], s[22:23], 1.0 -; SI-NEXT: v_add_f64 v[21:22], s[24:25], 1.0 -; SI-NEXT: v_add_f64 v[19:20], s[26:27], 1.0 -; SI-NEXT: v_add_f64 v[14:15], s[28:29], 1.0 -; SI-NEXT: v_add_f64 v[10:11], s[8:9], 1.0 -; SI-NEXT: v_add_f64 v[6:7], s[6:7], 1.0 -; SI-NEXT: v_add_f64 v[4:5], s[4:5], 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v1 -; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v2 -; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v34 -; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v35 -; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v29 -; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v30 -; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v25 -; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v26 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v24, v23 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v26, v23 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v28, v23 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v30, v23 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v11 +; SI-NEXT: v_cvt_f32_f16_e32 v32, v23 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v10 +; SI-NEXT: v_cvt_f32_f16_e32 v34, v23 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v9 +; SI-NEXT: v_cvt_f32_f16_e32 v36, v23 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v8 +; SI-NEXT: v_cvt_f32_f16_e32 v39, v23 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13 +; SI-NEXT: v_cvt_f32_f16_e32 v49, v23 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v12 +; SI-NEXT: v_cvt_f32_f16_e32 v51, v23 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v15 +; SI-NEXT: v_cvt_f32_f16_e32 v53, v23 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v14 +; SI-NEXT: v_cvt_f32_f16_e32 v55, v23 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v17 +; SI-NEXT: v_cvt_f32_f16_e32 v41, v23 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v16 +; SI-NEXT: v_cvt_f32_f16_e32 v43, v23 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v19 +; SI-NEXT: s_waitcnt expcnt(6) +; SI-NEXT: v_cvt_f32_f16_e32 v46, v23 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v18 +; SI-NEXT: s_waitcnt expcnt(4) +; SI-NEXT: v_cvt_f32_f16_e32 v56, v23 ; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v21 -; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v22 -; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v19 -; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v20 -; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v14 -; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v15 -; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v10 -; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v11 -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v6 +; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6 +; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v5 ; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v7 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v4 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v5 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v5 -; SI-NEXT: v_cvt_f32_f16_e32 v5, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v58, v23 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v20 ; SI-NEXT: v_cvt_f32_f16_e32 v7, v7 -; SI-NEXT: v_cvt_f32_f16_e32 v9, v6 -; SI-NEXT: v_cvt_f32_f16_e32 v11, v11 -; SI-NEXT: v_cvt_f32_f16_e32 v13, v10 -; SI-NEXT: v_cvt_f32_f16_e32 v15, v15 -; SI-NEXT: v_cvt_f32_f16_e32 v17, v14 -; SI-NEXT: v_cvt_f32_f16_e32 v18, v20 -; SI-NEXT: v_cvt_f32_f16_e32 v20, v19 ; SI-NEXT: v_cvt_f32_f16_e32 v22, v22 -; SI-NEXT: v_cvt_f32_f16_e32 v24, v21 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v60, v23 +; SI-NEXT: v_cvt_f32_f16_e32 v23, v6 +; SI-NEXT: v_cvt_f32_f16_e32 v25, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v27, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v29, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v35, v11 +; SI-NEXT: v_cvt_f32_f16_e32 v37, v10 +; SI-NEXT: v_cvt_f32_f16_e32 v38, v9 +; SI-NEXT: v_cvt_f32_f16_e32 v48, v8 +; SI-NEXT: v_cvt_f32_f16_e32 v50, v13 +; SI-NEXT: v_cvt_f32_f16_e32 v52, v12 +; SI-NEXT: v_cvt_f32_f16_e32 v54, v15 +; SI-NEXT: v_cvt_f32_f16_e32 v40, v14 +; SI-NEXT: v_cvt_f32_f16_e32 v42, v17 +; SI-NEXT: v_cvt_f32_f16_e32 v44, v16 +; SI-NEXT: v_cvt_f32_f16_e32 v45, v19 +; SI-NEXT: v_cvt_f32_f16_e32 v47, v18 +; SI-NEXT: v_cvt_f32_f16_e32 v57, v21 +; SI-NEXT: v_cvt_f32_f16_e32 v59, v20 +; SI-NEXT: s_cbranch_execnz .LBB53_3 +; SI-NEXT: .LBB53_2: ; %cmp.true +; SI-NEXT: v_add_f64 v[20:21], v[20:21], 1.0 +; SI-NEXT: v_add_f64 v[18:19], v[18:19], 1.0 +; SI-NEXT: v_add_f64 v[16:17], v[16:17], 1.0 +; SI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0 +; SI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0 +; SI-NEXT: v_add_f64 v[7:8], v[8:9], 1.0 +; SI-NEXT: v_add_f64 v[9:10], v[10:11], 1.0 +; SI-NEXT: v_add_f64 v[1:2], v[1:2], 1.0 +; SI-NEXT: v_add_f64 v[3:4], v[3:4], 1.0 +; SI-NEXT: v_add_f64 v[5:6], v[5:6], 1.0 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v20 +; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v21 +; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v18 +; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v19 +; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v16 +; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v17 +; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v14 +; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v15 +; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v12 +; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v13 +; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v7 +; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v8 +; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v9 +; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v10 +; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v1 +; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v2 +; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v3 +; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v4 +; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v5 +; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v6 +; SI-NEXT: v_cvt_f32_f16_e32 v23, v6 +; SI-NEXT: v_cvt_f32_f16_e32 v25, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v27, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v29, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v35, v10 +; SI-NEXT: v_cvt_f32_f16_e32 v37, v9 +; SI-NEXT: v_cvt_f32_f16_e32 v38, v8 +; SI-NEXT: v_cvt_f32_f16_e32 v48, v7 +; SI-NEXT: v_cvt_f32_f16_e32 v50, v13 +; SI-NEXT: v_cvt_f32_f16_e32 v52, v12 +; SI-NEXT: v_cvt_f32_f16_e32 v54, v15 +; SI-NEXT: v_cvt_f32_f16_e32 v40, v14 +; SI-NEXT: v_cvt_f32_f16_e32 v42, v17 +; SI-NEXT: v_cvt_f32_f16_e32 v44, v16 +; SI-NEXT: v_cvt_f32_f16_e32 v45, v19 +; SI-NEXT: v_cvt_f32_f16_e32 v47, v18 +; SI-NEXT: v_cvt_f32_f16_e32 v57, v21 +; SI-NEXT: v_cvt_f32_f16_e32 v59, v20 +; SI-NEXT: v_cvt_f32_f16_e32 v7, v36 +; SI-NEXT: v_cvt_f32_f16_e32 v22, v22 +; SI-NEXT: v_cvt_f32_f16_e32 v24, v24 ; SI-NEXT: v_cvt_f32_f16_e32 v26, v26 -; SI-NEXT: v_cvt_f32_f16_e32 v28, v25 +; SI-NEXT: v_cvt_f32_f16_e32 v28, v28 ; SI-NEXT: v_cvt_f32_f16_e32 v30, v30 -; SI-NEXT: v_cvt_f32_f16_e32 v32, v29 -; SI-NEXT: v_cvt_f32_f16_e32 v33, v35 -; SI-NEXT: v_cvt_f32_f16_e32 v35, v34 -; SI-NEXT: v_cvt_f32_f16_e32 v37, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v39, v1 -; SI-NEXT: v_cvt_f32_f16_e32 v1, v43 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v42 -; SI-NEXT: v_cvt_f32_f16_e32 v4, v41 -; SI-NEXT: v_cvt_f32_f16_e32 v6, v40 -; SI-NEXT: v_cvt_f32_f16_e32 v8, v8 -; SI-NEXT: v_cvt_f32_f16_e32 v10, v55 -; SI-NEXT: v_cvt_f32_f16_e32 v12, v12 -; SI-NEXT: v_cvt_f32_f16_e32 v14, v54 -; SI-NEXT: v_cvt_f32_f16_e32 v16, v16 -; SI-NEXT: v_cvt_f32_f16_e32 v19, v53 -; SI-NEXT: v_cvt_f32_f16_e32 v21, v52 -; SI-NEXT: v_cvt_f32_f16_e32 v23, v23 -; SI-NEXT: v_cvt_f32_f16_e32 v25, v51 -; SI-NEXT: v_cvt_f32_f16_e32 v27, v27 -; SI-NEXT: v_cvt_f32_f16_e32 v29, v50 -; SI-NEXT: v_cvt_f32_f16_e32 v31, v31 -; SI-NEXT: v_cvt_f32_f16_e32 v34, v49 -; SI-NEXT: v_cvt_f32_f16_e32 v36, v36 -; SI-NEXT: v_cvt_f32_f16_e32 v38, v38 -; SI-NEXT: v_cvt_f32_f16_e32 v48, v48 +; SI-NEXT: v_cvt_f32_f16_e32 v32, v32 +; SI-NEXT: v_cvt_f32_f16_e32 v34, v34 +; SI-NEXT: v_cvt_f32_f16_e32 v36, v11 +; SI-NEXT: v_cvt_f32_f16_e32 v39, v39 +; SI-NEXT: v_cvt_f32_f16_e32 v49, v49 +; SI-NEXT: v_cvt_f32_f16_e32 v51, v51 +; SI-NEXT: v_cvt_f32_f16_e32 v53, v53 +; SI-NEXT: v_cvt_f32_f16_e32 v55, v55 +; SI-NEXT: v_cvt_f32_f16_e32 v41, v41 +; SI-NEXT: v_cvt_f32_f16_e32 v43, v43 +; SI-NEXT: v_cvt_f32_f16_e32 v46, v46 +; SI-NEXT: v_cvt_f32_f16_e32 v56, v56 +; SI-NEXT: v_cvt_f32_f16_e32 v58, v58 +; SI-NEXT: v_cvt_f32_f16_e32 v60, v60 ; SI-NEXT: .LBB53_3: ; %end -; SI-NEXT: v_cvt_f16_f32_e32 v48, v48 -; SI-NEXT: v_cvt_f16_f32_e32 v39, v39 -; SI-NEXT: v_cvt_f16_f32_e32 v38, v38 -; SI-NEXT: v_cvt_f16_f32_e32 v37, v37 -; SI-NEXT: v_cvt_f16_f32_e32 v36, v36 -; SI-NEXT: v_cvt_f16_f32_e32 v35, v35 -; SI-NEXT: v_cvt_f16_f32_e32 v34, v34 -; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v48 -; SI-NEXT: v_cvt_f16_f32_e32 v33, v33 -; SI-NEXT: v_cvt_f16_f32_e32 v31, v31 -; SI-NEXT: v_or_b32_e32 v39, v39, v48 -; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v38 -; SI-NEXT: v_cvt_f16_f32_e32 v32, v32 -; SI-NEXT: v_cvt_f16_f32_e32 v29, v29 -; SI-NEXT: buffer_store_dword v39, v0, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v60 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v59 +; SI-NEXT: v_cvt_f16_f32_e32 v3, v58 +; SI-NEXT: v_cvt_f16_f32_e32 v4, v57 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3 +; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v39, vcc, 4, v0 -; SI-NEXT: v_or_b32_e32 v37, v37, v38 -; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v36 -; SI-NEXT: v_cvt_f16_f32_e32 v30, v30 -; SI-NEXT: v_cvt_f16_f32_e32 v27, v27 -; SI-NEXT: buffer_store_dword v37, v39, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0 +; SI-NEXT: v_or_b32_e32 v2, v4, v2 +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v56 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v37, vcc, 8, v0 -; SI-NEXT: v_or_b32_e32 v35, v35, v36 -; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v34 -; SI-NEXT: v_cvt_f16_f32_e32 v28, v28 -; SI-NEXT: v_cvt_f16_f32_e32 v25, v25 -; SI-NEXT: buffer_store_dword v35, v37, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v2, v47 +; SI-NEXT: v_add_i32_e32 v3, vcc, 8, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v35, vcc, 12, v0 -; SI-NEXT: v_or_b32_e32 v33, v33, v34 -; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31 -; SI-NEXT: v_cvt_f16_f32_e32 v26, v26 -; SI-NEXT: v_cvt_f16_f32_e32 v23, v23 -; SI-NEXT: buffer_store_dword v33, v35, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v46 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v45 +; SI-NEXT: v_add_i32_e32 v3, vcc, 12, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v33, vcc, 16, v0 -; SI-NEXT: v_or_b32_e32 v31, v32, v31 -; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29 -; SI-NEXT: v_cvt_f16_f32_e32 v24, v24 -; SI-NEXT: v_cvt_f16_f32_e32 v21, v21 -; SI-NEXT: buffer_store_dword v31, v33, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v43 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v44 +; SI-NEXT: v_add_i32_e32 v3, vcc, 16, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v31, vcc, 20, v0 -; SI-NEXT: v_or_b32_e32 v29, v30, v29 -; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27 -; SI-NEXT: v_cvt_f16_f32_e32 v22, v22 -; SI-NEXT: v_cvt_f16_f32_e32 v19, v19 -; SI-NEXT: buffer_store_dword v29, v31, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v41 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v42 +; SI-NEXT: v_add_i32_e32 v3, vcc, 20, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v29, vcc, 24, v0 -; SI-NEXT: v_or_b32_e32 v27, v28, v27 -; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; SI-NEXT: v_cvt_f16_f32_e32 v20, v20 -; SI-NEXT: v_cvt_f16_f32_e32 v16, v16 -; SI-NEXT: buffer_store_dword v27, v29, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v55 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v40 +; SI-NEXT: v_add_i32_e32 v3, vcc, 24, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v27, vcc, 28, v0 -; SI-NEXT: v_or_b32_e32 v25, v26, v25 -; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; SI-NEXT: v_cvt_f16_f32_e32 v18, v18 -; SI-NEXT: buffer_store_dword v25, v27, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v53 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v54 +; SI-NEXT: v_add_i32_e32 v3, vcc, 28, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v25, vcc, 32, v0 -; SI-NEXT: v_or_b32_e32 v23, v24, v23 -; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; SI-NEXT: buffer_store_dword v23, v25, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v51 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v52 +; SI-NEXT: v_add_i32_e32 v3, vcc, 32, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v23, vcc, 36, v0 -; SI-NEXT: v_or_b32_e32 v21, v22, v21 -; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; SI-NEXT: buffer_store_dword v21, v23, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v49 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v50 +; SI-NEXT: v_add_i32_e32 v3, vcc, 36, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v21, vcc, 40, v0 -; SI-NEXT: v_or_b32_e32 v19, v20, v19 -; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; SI-NEXT: buffer_store_dword v19, v21, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v39 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v48 +; SI-NEXT: v_add_i32_e32 v3, vcc, 40, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_i32_e32 v19, vcc, 44, v0 -; SI-NEXT: v_or_b32_e32 v16, v18, v16 -; SI-NEXT: v_cvt_f16_f32_e32 v14, v14 -; SI-NEXT: buffer_store_dword v16, v19, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v36 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v38 +; SI-NEXT: v_add_i32_e32 v3, vcc, 44, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v16, v17 -; SI-NEXT: v_add_i32_e32 v17, vcc, 48, v0 -; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; SI-NEXT: v_or_b32_e32 v14, v16, v14 -; SI-NEXT: v_cvt_f16_f32_e32 v12, v12 -; SI-NEXT: buffer_store_dword v14, v17, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v34 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v37 +; SI-NEXT: v_add_i32_e32 v3, vcc, 48, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v14, v15 -; SI-NEXT: v_add_i32_e32 v15, vcc, 52, v0 -; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; SI-NEXT: v_or_b32_e32 v12, v14, v12 -; SI-NEXT: v_cvt_f16_f32_e32 v10, v10 -; SI-NEXT: buffer_store_dword v12, v15, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v32 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v35 +; SI-NEXT: v_add_i32_e32 v3, vcc, 52, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v12, v13 -; SI-NEXT: v_add_i32_e32 v13, vcc, 56, v0 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v12, v10 -; SI-NEXT: v_cvt_f16_f32_e32 v8, v8 -; SI-NEXT: buffer_store_dword v10, v13, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v30 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v33 +; SI-NEXT: v_add_i32_e32 v3, vcc, 56, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v10, v11 -; SI-NEXT: v_add_i32_e32 v11, vcc, 60, v0 -; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; SI-NEXT: v_or_b32_e32 v8, v10, v8 -; SI-NEXT: v_cvt_f16_f32_e32 v6, v6 -; SI-NEXT: buffer_store_dword v8, v11, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v28 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v31 +; SI-NEXT: v_add_i32_e32 v3, vcc, 60, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v8, v9 -; SI-NEXT: v_add_i32_e32 v9, vcc, 64, v0 -; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; SI-NEXT: v_or_b32_e32 v6, v8, v6 -; SI-NEXT: v_cvt_f16_f32_e32 v4, v4 -; SI-NEXT: buffer_store_dword v6, v9, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v26 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v29 +; SI-NEXT: v_add_i32_e32 v3, vcc, 64, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v6, v7 -; SI-NEXT: v_add_i32_e32 v7, vcc, 0x44, v0 -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_or_b32_e32 v4, v6, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: buffer_store_dword v4, v7, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v24 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v27 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x44, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v4, v5 -; SI-NEXT: v_add_i32_e32 v5, vcc, 0x48, v0 -; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; SI-NEXT: v_or_b32_e32 v2, v4, v2 -; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 -; SI-NEXT: buffer_store_dword v2, v5, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v1, v22 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v25 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x48, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v2, v3 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v7 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v23 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x4c, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] ; SI-NEXT: .LBB53_4: -; SI-NEXT: ; implicit-def: $vgpr39 +; SI-NEXT: ; implicit-def: $vgpr59 +; SI-NEXT: ; implicit-def: $vgpr60 +; SI-NEXT: ; implicit-def: $vgpr57 +; SI-NEXT: ; implicit-def: $vgpr58 +; SI-NEXT: ; implicit-def: $vgpr47 +; SI-NEXT: ; implicit-def: $vgpr56 +; SI-NEXT: ; implicit-def: $vgpr45 +; SI-NEXT: ; implicit-def: $vgpr46 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr43 +; SI-NEXT: ; implicit-def: $vgpr42 +; SI-NEXT: ; implicit-def: $vgpr41 +; SI-NEXT: ; implicit-def: $vgpr40 +; SI-NEXT: ; implicit-def: $vgpr55 +; SI-NEXT: ; implicit-def: $vgpr54 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr52 +; SI-NEXT: ; implicit-def: $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; implicit-def: $vgpr49 ; SI-NEXT: ; implicit-def: $vgpr48 -; SI-NEXT: ; implicit-def: $vgpr37 +; SI-NEXT: ; implicit-def: $vgpr39 ; SI-NEXT: ; implicit-def: $vgpr38 -; SI-NEXT: ; implicit-def: $vgpr35 ; SI-NEXT: ; implicit-def: $vgpr36 -; SI-NEXT: ; implicit-def: $vgpr33 +; SI-NEXT: ; implicit-def: $vgpr37 ; SI-NEXT: ; implicit-def: $vgpr34 +; SI-NEXT: ; implicit-def: $vgpr35 ; SI-NEXT: ; implicit-def: $vgpr32 -; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr33 ; SI-NEXT: ; implicit-def: $vgpr30 -; SI-NEXT: ; implicit-def: $vgpr29 +; SI-NEXT: ; implicit-def: $vgpr31 ; SI-NEXT: ; implicit-def: $vgpr28 -; SI-NEXT: ; implicit-def: $vgpr27 +; SI-NEXT: ; implicit-def: $vgpr29 ; SI-NEXT: ; implicit-def: $vgpr26 -; SI-NEXT: ; implicit-def: $vgpr25 +; SI-NEXT: ; implicit-def: $vgpr27 ; SI-NEXT: ; implicit-def: $vgpr24 -; SI-NEXT: ; implicit-def: $vgpr23 +; SI-NEXT: ; implicit-def: $vgpr25 ; SI-NEXT: ; implicit-def: $vgpr22 -; SI-NEXT: ; implicit-def: $vgpr21 -; SI-NEXT: ; implicit-def: $vgpr20 -; SI-NEXT: ; implicit-def: $vgpr19 -; SI-NEXT: ; implicit-def: $vgpr18 -; SI-NEXT: ; implicit-def: $vgpr16 -; SI-NEXT: ; implicit-def: $vgpr17 -; SI-NEXT: ; implicit-def: $vgpr14 -; SI-NEXT: ; implicit-def: $vgpr15 -; SI-NEXT: ; implicit-def: $vgpr12 -; SI-NEXT: ; implicit-def: $vgpr13 -; SI-NEXT: ; implicit-def: $vgpr10 -; SI-NEXT: ; implicit-def: $vgpr11 -; SI-NEXT: ; implicit-def: $vgpr8 -; SI-NEXT: ; implicit-def: $vgpr9 -; SI-NEXT: ; implicit-def: $vgpr6 +; SI-NEXT: ; implicit-def: $vgpr23 ; SI-NEXT: ; implicit-def: $vgpr7 -; SI-NEXT: ; implicit-def: $vgpr4 -; SI-NEXT: ; implicit-def: $vgpr5 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr3 -; SI-NEXT: ; implicit-def: $vgpr1 ; SI-NEXT: s_branch .LBB53_2 ; ; VI-LABEL: bitcast_v10f64_to_v40f16_scalar: @@ -31014,269 +30316,100 @@ define inreg <10 x double> @bitcast_v40f16_to_v10f64_scalar(<40 x half> inreg %a ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:296 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:172 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:44 -; GFX11-TRUE16-NEXT: s_clause 0xa -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v175, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v184, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v185, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v186, s32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v185, v1 :: v_dual_mov_b32 v186, v0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s19, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s16, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s0, 16 -; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s40, s0, s40 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s41, s1, s41 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s2, s46 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s3, s45 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s16, s44 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s17, s43 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s5 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s6 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s7 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s8 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s9 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s11 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s26, s12 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s27, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s28, s14 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s29, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s29, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s27, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s14, s26, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s25, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s24, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s23, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s22, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s21, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s20, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s19, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s18, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s17, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s3, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s1, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s0, 16 +; GFX11-TRUE16-NEXT: s_mov_b32 s40, 0 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s46 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s45 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s44 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s43 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s16, s4 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s17, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s18, s6 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s19, s7 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s20, s8 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s21, s9 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s22, s10 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s23, s11 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s12, s24, s12 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s13, s25, s13 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s14, s26, s14 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s15, s27, s15 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s16, s28, s42 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s17, s29, s41 ; GFX11-TRUE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB55_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s40 :: v_dual_mov_b32 v5, s0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s41 :: v_dual_mov_b32 v9, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s2 :: v_dual_mov_b32 v27, s4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v35, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v44, s6 :: v_dual_mov_b32 v65, s8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s7 :: v_dual_mov_b32 v77, s9 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v90, s10 :: v_dual_mov_b32 v119, s12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v104, s11 :: v_dual_mov_b32 v135, s13 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v152, s14 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v170, s15 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s40 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB55_3 ; GFX11-TRUE16-NEXT: .LBB55_2: ; %cmp.true -; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s40 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s41 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v186, 0x200, v186 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v185, 0x200, v185 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s0 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s1 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s2 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v20, 0x200, s3 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v27, 0x200, s4 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v35, 0x200, s5 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v44, 0x200, s6 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v54, 0x200, s7 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v65, 0x200, s8 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v77, 0x200, s9 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v90, 0x200, s10 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v104, 0x200, s11 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v119, 0x200, s12 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v135, 0x200, s13 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v152, 0x200, s14 op_sel_hi:[0,1] -; GFX11-TRUE16-NEXT: v_pk_add_f16 v170, 0x200, s15 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, s6 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, s7 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, s8 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, s9 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, s10 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, s11 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, s12 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, s13 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, s14 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, s15 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, s16 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v17, 0x200, s17 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1] +; GFX11-TRUE16-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1] ; GFX11-TRUE16-NEXT: .LBB55_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v35 :: v_dual_mov_b32 v8, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v77 :: v_dual_mov_b32 v12, v90 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v104 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, v135 :: v_dual_mov_b32 v16, v152 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v17, v170 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v186 :: v_dual_mov_b32 v19, v185 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v186, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v185, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v184, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v175, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0xa -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:284 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:288 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:292 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:296 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v9 :: v_dual_mov_b32 v4, v14 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v20 :: v_dual_mov_b32 v6, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v54 :: v_dual_mov_b32 v10, v65 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v14, v119 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB55_4: -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175_vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17 ; GFX11-TRUE16-NEXT: s_branch .LBB55_2 ; ; GFX11-FAKE16-LABEL: bitcast_v40f16_to_v10f64_scalar: @@ -31389,6 +30522,17 @@ define <40 x half> @bitcast_v40i16_to_v40f16(<40 x i16> %a, i32 %b) { ; SI-LABEL: bitcast_v40i16_to_v40f16: ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:4 +; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:40 +; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:36 +; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:32 +; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:28 +; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:24 +; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:20 +; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:16 +; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:12 +; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:8 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill @@ -31405,17 +30549,6 @@ define <40 x half> @bitcast_v40i16_to_v40f16(<40 x i16> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:4 -; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:40 -; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:36 -; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:32 -; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:28 -; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:24 -; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:20 -; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:16 -; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:12 -; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:8 ; SI-NEXT: ; implicit-def: $vgpr40 ; SI-NEXT: ; kill: killed $vgpr40 ; SI-NEXT: ; implicit-def: $vgpr40 @@ -31472,7 +30605,7 @@ define <40 x half> @bitcast_v40i16_to_v40f16(<40 x i16> %a, i32 %b) { ; SI-NEXT: ; implicit-def: $vgpr42 ; SI-NEXT: ; kill: killed $vgpr40 ; SI-NEXT: ; implicit-def: $vgpr40 -; SI-NEXT: s_waitcnt vmcnt(8) +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 ; SI-NEXT: ; implicit-def: $vgpr31 ; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc @@ -31523,7 +30656,6 @@ define <40 x half> @bitcast_v40i16_to_v40f16(<40 x i16> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f32_f16_e32 v1, v30 -; SI-NEXT: s_waitcnt vmcnt(7) ; SI-NEXT: v_cvt_f32_f16_e32 v40, v48 ; SI-NEXT: ; implicit-def: $vgpr2 ; SI-NEXT: ; implicit-def: $vgpr3 @@ -31623,7 +30755,6 @@ define <40 x half> @bitcast_v40i16_to_v40f16(<40 x i16> %a, i32 %b) { ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f32_f16_e32 v1, v27 ; SI-NEXT: v_add_i32_e32 v39, vcc, 3, v39 -; SI-NEXT: s_waitcnt vmcnt(5) ; SI-NEXT: v_add_i32_e32 v49, vcc, 3, v49 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -31643,7 +30774,6 @@ define <40 x half> @bitcast_v40i16_to_v40f16(<40 x i16> %a, i32 %b) { ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f32_f16_e32 v1, v38 -; SI-NEXT: s_waitcnt vmcnt(8) ; SI-NEXT: v_add_i32_e32 v48, vcc, 3, v48 ; SI-NEXT: v_add_i32_e32 v24, vcc, 3, v24 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill |