diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll | 84823 |
1 files changed, 40807 insertions, 44016 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll index 08e64da..4c5c56a 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll @@ -7459,53 +7459,81 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_writelane_b32 v20, s30, 0 -; SI-NEXT: v_writelane_b32 v20, s31, 1 -; SI-NEXT: v_writelane_b32 v20, s34, 2 -; SI-NEXT: v_writelane_b32 v20, s35, 3 -; SI-NEXT: v_writelane_b32 v20, s36, 4 -; SI-NEXT: v_writelane_b32 v20, s37, 5 -; SI-NEXT: v_writelane_b32 v20, s38, 6 -; SI-NEXT: v_writelane_b32 v20, s39, 7 -; SI-NEXT: v_writelane_b32 v20, s48, 8 -; SI-NEXT: v_writelane_b32 v20, s49, 9 -; SI-NEXT: v_writelane_b32 v20, s50, 10 -; SI-NEXT: v_writelane_b32 v20, s51, 11 -; SI-NEXT: v_writelane_b32 v20, s52, 12 -; SI-NEXT: v_writelane_b32 v20, s53, 13 -; SI-NEXT: v_writelane_b32 v20, s54, 14 -; SI-NEXT: v_writelane_b32 v20, s55, 15 -; SI-NEXT: v_writelane_b32 v20, s64, 16 -; SI-NEXT: v_writelane_b32 v20, s65, 17 -; SI-NEXT: v_writelane_b32 v20, s66, 18 -; SI-NEXT: v_writelane_b32 v20, s67, 19 -; SI-NEXT: v_writelane_b32 v20, s68, 20 -; SI-NEXT: v_writelane_b32 v20, s69, 21 -; SI-NEXT: v_writelane_b32 v20, s70, 22 -; SI-NEXT: v_writelane_b32 v20, s71, 23 -; SI-NEXT: v_writelane_b32 v20, s80, 24 -; SI-NEXT: v_writelane_b32 v20, s81, 25 -; SI-NEXT: v_writelane_b32 v20, s82, 26 -; SI-NEXT: v_writelane_b32 v20, s83, 27 -; SI-NEXT: v_writelane_b32 v20, s84, 28 -; SI-NEXT: v_writelane_b32 v20, s85, 29 -; SI-NEXT: v_writelane_b32 v20, s86, 30 -; SI-NEXT: v_writelane_b32 v20, s87, 31 -; SI-NEXT: v_writelane_b32 v20, s96, 32 -; SI-NEXT: v_writelane_b32 v20, s97, 33 +; SI-NEXT: v_writelane_b32 v21, s30, 0 +; SI-NEXT: v_writelane_b32 v21, s31, 1 +; SI-NEXT: v_writelane_b32 v21, s34, 2 +; SI-NEXT: v_writelane_b32 v21, s35, 3 +; SI-NEXT: v_writelane_b32 v21, s36, 4 +; SI-NEXT: v_writelane_b32 v21, s37, 5 +; SI-NEXT: v_writelane_b32 v21, s38, 6 +; SI-NEXT: v_writelane_b32 v21, s39, 7 +; SI-NEXT: v_writelane_b32 v21, s48, 8 +; SI-NEXT: v_writelane_b32 v21, s49, 9 +; SI-NEXT: v_writelane_b32 v21, s50, 10 +; SI-NEXT: v_writelane_b32 v21, s51, 11 +; SI-NEXT: v_writelane_b32 v21, s52, 12 +; SI-NEXT: v_writelane_b32 v21, s53, 13 +; SI-NEXT: v_writelane_b32 v21, s54, 14 +; SI-NEXT: v_writelane_b32 v21, s55, 15 +; SI-NEXT: v_writelane_b32 v21, s64, 16 +; SI-NEXT: v_writelane_b32 v21, s65, 17 +; SI-NEXT: v_writelane_b32 v21, s66, 18 +; SI-NEXT: v_writelane_b32 v21, s67, 19 +; SI-NEXT: v_writelane_b32 v21, s68, 20 +; SI-NEXT: v_mov_b32_e32 v20, s16 +; SI-NEXT: v_writelane_b32 v21, s69, 21 +; SI-NEXT: v_readfirstlane_b32 s56, v20 +; SI-NEXT: v_mov_b32_e32 v20, s17 +; SI-NEXT: v_writelane_b32 v21, s70, 22 +; SI-NEXT: v_readfirstlane_b32 s57, v20 +; SI-NEXT: v_mov_b32_e32 v20, s18 +; SI-NEXT: v_writelane_b32 v21, s71, 23 +; SI-NEXT: v_readfirstlane_b32 s46, v20 +; SI-NEXT: v_mov_b32_e32 v20, s19 +; SI-NEXT: v_writelane_b32 v21, s80, 24 +; SI-NEXT: v_readfirstlane_b32 s47, v20 +; SI-NEXT: v_mov_b32_e32 v20, s20 +; SI-NEXT: v_writelane_b32 v21, s81, 25 +; SI-NEXT: v_readfirstlane_b32 s44, v20 +; SI-NEXT: v_mov_b32_e32 v20, s21 +; SI-NEXT: v_writelane_b32 v21, s82, 26 +; SI-NEXT: v_readfirstlane_b32 s45, v20 +; SI-NEXT: v_mov_b32_e32 v20, s22 +; SI-NEXT: v_writelane_b32 v21, s83, 27 +; SI-NEXT: v_readfirstlane_b32 s42, v20 +; SI-NEXT: v_mov_b32_e32 v20, s23 +; SI-NEXT: v_writelane_b32 v21, s84, 28 +; SI-NEXT: v_readfirstlane_b32 s43, v20 +; SI-NEXT: v_mov_b32_e32 v20, s24 +; SI-NEXT: v_writelane_b32 v21, s85, 29 +; SI-NEXT: v_readfirstlane_b32 s40, v20 +; SI-NEXT: v_mov_b32_e32 v20, s25 +; SI-NEXT: v_writelane_b32 v21, s86, 30 +; SI-NEXT: v_readfirstlane_b32 s41, v20 +; SI-NEXT: v_mov_b32_e32 v20, s26 +; SI-NEXT: v_writelane_b32 v21, s87, 31 +; SI-NEXT: v_readfirstlane_b32 s24, v20 +; SI-NEXT: v_mov_b32_e32 v20, s27 +; SI-NEXT: v_writelane_b32 v21, s96, 32 +; SI-NEXT: v_readfirstlane_b32 s25, v20 +; SI-NEXT: v_mov_b32_e32 v20, s28 +; SI-NEXT: v_writelane_b32 v21, s97, 33 +; SI-NEXT: v_readfirstlane_b32 s22, v20 +; SI-NEXT: v_mov_b32_e32 v20, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_writelane_b32 v20, s98, 34 -; SI-NEXT: v_readfirstlane_b32 s44, v1 -; SI-NEXT: v_readfirstlane_b32 s45, v2 -; SI-NEXT: v_readfirstlane_b32 s42, v3 -; SI-NEXT: v_readfirstlane_b32 s43, v4 -; SI-NEXT: v_readfirstlane_b32 s40, v5 -; SI-NEXT: v_readfirstlane_b32 s41, v6 +; SI-NEXT: v_writelane_b32 v21, s98, 34 +; SI-NEXT: v_readfirstlane_b32 s23, v20 +; SI-NEXT: v_readfirstlane_b32 s20, v1 +; SI-NEXT: v_readfirstlane_b32 s21, v2 +; SI-NEXT: v_readfirstlane_b32 s18, v3 +; SI-NEXT: v_readfirstlane_b32 s19, v4 +; SI-NEXT: v_readfirstlane_b32 s16, v5 +; SI-NEXT: v_readfirstlane_b32 s17, v6 ; SI-NEXT: v_readfirstlane_b32 s14, v7 ; SI-NEXT: v_readfirstlane_b32 s15, v8 ; SI-NEXT: v_readfirstlane_b32 s12, v9 @@ -7517,665 +7545,665 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s6, v15 ; SI-NEXT: v_readfirstlane_b32 s7, v16 ; SI-NEXT: v_readfirstlane_b32 s4, v17 -; SI-NEXT: s_and_b64 s[46:47], vcc, exec +; SI-NEXT: s_and_b64 s[26:27], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v18 -; SI-NEXT: v_writelane_b32 v20, s99, 35 +; SI-NEXT: v_writelane_b32 v21, s99, 35 +; SI-NEXT: ; implicit-def: $vgpr23 : SGPR spill to VGPR lane ; SI-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane -; SI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane ; SI-NEXT: s_cbranch_scc0 .LBB13_4 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: s_lshr_b32 s46, s5, 24 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v22, s46, 42 -; SI-NEXT: s_lshr_b32 s46, s5, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 43 -; SI-NEXT: s_lshr_b32 s46, s5, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 44 -; SI-NEXT: s_lshr_b32 s46, s7, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 45 -; SI-NEXT: s_lshr_b32 s46, s7, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 46 -; SI-NEXT: s_lshr_b32 s46, s7, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 47 -; SI-NEXT: s_lshr_b32 s46, s9, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 48 -; SI-NEXT: s_lshr_b32 s46, s9, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 49 -; SI-NEXT: s_lshr_b32 s46, s11, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 50 -; SI-NEXT: s_lshr_b32 s46, s11, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 51 -; SI-NEXT: s_lshr_b32 s46, s11, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 52 -; SI-NEXT: s_lshr_b32 s46, s13, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 53 -; SI-NEXT: s_lshr_b32 s46, s13, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 54 -; SI-NEXT: s_lshr_b32 s46, s13, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 55 -; SI-NEXT: s_lshr_b32 s46, s15, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 56 -; SI-NEXT: s_lshr_b32 s46, s15, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 57 -; SI-NEXT: s_lshr_b32 s46, s15, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 58 -; SI-NEXT: s_lshr_b32 s46, s41, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 59 -; SI-NEXT: s_lshr_b32 s46, s41, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 60 -; SI-NEXT: s_lshr_b32 s46, s41, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 61 -; SI-NEXT: s_lshr_b32 s46, s43, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 62 -; SI-NEXT: s_lshr_b32 s46, s43, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 63 -; SI-NEXT: s_lshr_b32 s46, s43, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 0 -; SI-NEXT: s_lshr_b32 s46, s45, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 1 -; SI-NEXT: s_lshr_b32 s46, s45, 16 -; SI-NEXT: v_writelane_b32 v21, s46, 2 -; SI-NEXT: s_lshr_b32 s46, s45, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 3 -; SI-NEXT: s_lshr_b32 s46, s29, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 4 -; SI-NEXT: s_lshr_b32 s46, s29, 16 -; SI-NEXT: v_writelane_b32 v21, s46, 5 -; SI-NEXT: s_lshr_b32 s46, s29, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 6 -; SI-NEXT: s_lshr_b32 s46, s27, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 7 -; SI-NEXT: s_lshr_b32 s46, s27, 16 -; SI-NEXT: v_writelane_b32 v21, s46, 8 -; SI-NEXT: s_lshr_b32 s46, s27, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 9 -; SI-NEXT: s_lshr_b32 s46, s25, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 10 -; SI-NEXT: s_lshr_b32 s46, s25, 16 -; SI-NEXT: v_writelane_b32 v21, s46, 11 -; SI-NEXT: s_lshr_b32 s46, s25, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 12 -; SI-NEXT: s_lshr_b32 s46, s23, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 13 -; SI-NEXT: s_lshr_b32 s46, s23, 16 -; SI-NEXT: v_writelane_b32 v21, s46, 14 -; SI-NEXT: s_lshr_b32 s46, s23, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 15 -; SI-NEXT: s_lshr_b32 s46, s21, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 16 -; SI-NEXT: s_lshr_b32 s46, s21, 16 -; SI-NEXT: v_writelane_b32 v21, s46, 17 -; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 40 -; SI-NEXT: v_writelane_b32 v22, s47, 41 -; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 38 -; SI-NEXT: v_writelane_b32 v22, s47, 39 -; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 36 -; SI-NEXT: v_writelane_b32 v22, s47, 37 -; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 34 -; SI-NEXT: v_writelane_b32 v22, s47, 35 -; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 32 -; SI-NEXT: v_writelane_b32 v22, s47, 33 -; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 30 -; SI-NEXT: v_writelane_b32 v22, s47, 31 -; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 28 -; SI-NEXT: v_writelane_b32 v22, s47, 29 -; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 26 -; SI-NEXT: v_writelane_b32 v22, s47, 27 -; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 24 -; SI-NEXT: v_writelane_b32 v22, s47, 25 -; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 22 -; SI-NEXT: v_writelane_b32 v22, s47, 23 -; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 20 -; SI-NEXT: v_writelane_b32 v22, s47, 21 -; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 18 -; SI-NEXT: v_writelane_b32 v22, s47, 19 -; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 16 -; SI-NEXT: v_writelane_b32 v22, s47, 17 -; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 14 -; SI-NEXT: v_writelane_b32 v22, s47, 15 -; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 12 -; SI-NEXT: v_writelane_b32 v22, s47, 13 -; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 10 -; SI-NEXT: v_writelane_b32 v22, s47, 11 -; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 8 -; SI-NEXT: v_writelane_b32 v22, s47, 9 -; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 6 -; SI-NEXT: v_writelane_b32 v22, s47, 7 -; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 4 -; SI-NEXT: v_writelane_b32 v22, s47, 5 -; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 2 -; SI-NEXT: v_writelane_b32 v22, s47, 3 -; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 0 +; SI-NEXT: s_lshr_b32 s26, s5, 24 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_writelane_b32 v23, s26, 42 +; SI-NEXT: s_lshr_b32 s26, s5, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 43 +; SI-NEXT: s_lshr_b32 s26, s5, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 44 +; SI-NEXT: s_lshr_b32 s26, s7, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 45 +; SI-NEXT: s_lshr_b32 s26, s7, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 46 +; SI-NEXT: s_lshr_b32 s26, s7, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 47 +; SI-NEXT: s_lshr_b32 s26, s9, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 48 +; SI-NEXT: s_lshr_b32 s26, s9, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 49 +; SI-NEXT: s_lshr_b32 s26, s11, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 50 +; SI-NEXT: s_lshr_b32 s26, s11, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 51 +; SI-NEXT: s_lshr_b32 s26, s11, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 52 +; SI-NEXT: s_lshr_b32 s26, s13, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 53 +; SI-NEXT: s_lshr_b32 s26, s13, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 54 +; SI-NEXT: s_lshr_b32 s26, s13, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 55 +; SI-NEXT: s_lshr_b32 s26, s15, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 56 +; SI-NEXT: s_lshr_b32 s26, s15, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 57 +; SI-NEXT: s_lshr_b32 s26, s15, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 58 +; SI-NEXT: s_lshr_b32 s26, s17, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 59 +; SI-NEXT: s_lshr_b32 s26, s17, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 60 +; SI-NEXT: s_lshr_b32 s26, s17, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 61 +; SI-NEXT: s_lshr_b32 s26, s19, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 62 +; SI-NEXT: s_lshr_b32 s26, s19, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 63 +; SI-NEXT: s_lshr_b32 s26, s19, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 0 +; SI-NEXT: s_lshr_b32 s26, s21, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 1 +; SI-NEXT: s_lshr_b32 s26, s21, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 2 +; SI-NEXT: s_lshr_b32 s26, s21, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 3 +; SI-NEXT: s_lshr_b32 s26, s23, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 4 +; SI-NEXT: s_lshr_b32 s26, s23, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 5 +; SI-NEXT: s_lshr_b32 s26, s23, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 6 +; SI-NEXT: s_lshr_b32 s26, s25, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 7 +; SI-NEXT: s_lshr_b32 s26, s25, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 8 +; SI-NEXT: s_lshr_b32 s26, s25, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 9 +; SI-NEXT: s_lshr_b32 s26, s41, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 10 +; SI-NEXT: s_lshr_b32 s26, s41, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 11 +; SI-NEXT: s_lshr_b32 s26, s41, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 12 +; SI-NEXT: s_lshr_b32 s26, s43, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 13 +; SI-NEXT: s_lshr_b32 s26, s43, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 14 +; SI-NEXT: s_lshr_b32 s26, s43, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 15 +; SI-NEXT: s_lshr_b32 s26, s45, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 16 +; SI-NEXT: s_lshr_b32 s26, s45, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 17 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 40 +; SI-NEXT: v_writelane_b32 v23, s27, 41 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 38 +; SI-NEXT: v_writelane_b32 v23, s27, 39 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 36 +; SI-NEXT: v_writelane_b32 v23, s27, 37 +; SI-NEXT: s_lshr_b64 s[26:27], s[6:7], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 34 +; SI-NEXT: v_writelane_b32 v23, s27, 35 +; SI-NEXT: s_lshr_b64 s[26:27], s[6:7], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 32 +; SI-NEXT: v_writelane_b32 v23, s27, 33 +; SI-NEXT: s_lshr_b64 s[26:27], s[6:7], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 30 +; SI-NEXT: v_writelane_b32 v23, s27, 31 +; SI-NEXT: s_lshr_b64 s[26:27], s[8:9], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 28 +; SI-NEXT: v_writelane_b32 v23, s27, 29 +; SI-NEXT: s_lshr_b64 s[26:27], s[8:9], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 26 +; SI-NEXT: v_writelane_b32 v23, s27, 27 +; SI-NEXT: s_lshr_b64 s[26:27], s[8:9], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 24 +; SI-NEXT: v_writelane_b32 v23, s27, 25 +; SI-NEXT: s_lshr_b64 s[26:27], s[10:11], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 22 +; SI-NEXT: v_writelane_b32 v23, s27, 23 +; SI-NEXT: s_lshr_b64 s[26:27], s[10:11], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 20 +; SI-NEXT: v_writelane_b32 v23, s27, 21 +; SI-NEXT: s_lshr_b64 s[26:27], s[10:11], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 18 +; SI-NEXT: v_writelane_b32 v23, s27, 19 +; SI-NEXT: s_lshr_b64 s[26:27], s[12:13], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 16 +; SI-NEXT: v_writelane_b32 v23, s27, 17 +; SI-NEXT: s_lshr_b64 s[26:27], s[12:13], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 14 +; SI-NEXT: v_writelane_b32 v23, s27, 15 +; SI-NEXT: s_lshr_b64 s[26:27], s[12:13], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 12 +; SI-NEXT: v_writelane_b32 v23, s27, 13 +; SI-NEXT: s_lshr_b64 s[26:27], s[14:15], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 10 +; SI-NEXT: v_writelane_b32 v23, s27, 11 +; SI-NEXT: s_lshr_b64 s[26:27], s[14:15], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 8 +; SI-NEXT: v_writelane_b32 v23, s27, 9 +; SI-NEXT: s_lshr_b64 s[26:27], s[14:15], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 6 +; SI-NEXT: v_writelane_b32 v23, s27, 7 +; SI-NEXT: s_lshr_b64 s[26:27], s[16:17], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 4 +; SI-NEXT: v_writelane_b32 v23, s27, 5 +; SI-NEXT: s_lshr_b64 s[26:27], s[16:17], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 2 +; SI-NEXT: v_writelane_b32 v23, s27, 3 +; SI-NEXT: s_lshr_b64 s[26:27], s[16:17], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 0 ; SI-NEXT: s_lshr_b32 s50, s9, 24 -; SI-NEXT: s_lshr_b32 s51, s21, 8 -; SI-NEXT: s_lshr_b32 s48, s19, 24 -; SI-NEXT: s_lshr_b32 s52, s19, 16 -; SI-NEXT: s_lshr_b32 s53, s19, 8 -; SI-NEXT: s_lshr_b32 s54, s17, 24 -; SI-NEXT: s_lshr_b32 s55, s17, 16 -; SI-NEXT: s_lshr_b32 s49, s17, 8 -; SI-NEXT: v_writelane_b32 v22, s47, 1 -; SI-NEXT: s_lshr_b64 s[64:65], s[42:43], 24 -; SI-NEXT: s_lshr_b64 s[66:67], s[42:43], 16 -; SI-NEXT: s_lshr_b64 s[68:69], s[42:43], 8 -; SI-NEXT: s_lshr_b64 s[70:71], s[44:45], 24 -; SI-NEXT: s_lshr_b64 s[80:81], s[44:45], 16 -; SI-NEXT: s_lshr_b64 s[82:83], s[44:45], 8 -; SI-NEXT: s_lshr_b64 s[84:85], s[28:29], 24 -; SI-NEXT: s_lshr_b64 s[86:87], s[28:29], 16 -; SI-NEXT: s_lshr_b64 s[96:97], s[28:29], 8 -; SI-NEXT: s_lshr_b64 s[98:99], s[26:27], 24 -; SI-NEXT: s_lshr_b64 s[46:47], s[26:27], 16 -; SI-NEXT: s_lshr_b64 s[56:57], s[26:27], 8 -; SI-NEXT: s_lshr_b64 s[58:59], s[24:25], 24 -; SI-NEXT: s_lshr_b64 s[60:61], s[24:25], 16 -; SI-NEXT: s_lshr_b64 s[62:63], s[24:25], 8 -; SI-NEXT: s_lshr_b64 s[72:73], s[22:23], 24 -; SI-NEXT: s_lshr_b64 s[74:75], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[76:77], s[22:23], 8 -; SI-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 -; SI-NEXT: s_lshr_b64 s[88:89], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[90:91], s[20:21], 8 -; SI-NEXT: s_lshr_b64 s[92:93], s[18:19], 24 -; SI-NEXT: s_lshr_b64 s[94:95], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[30:31], s[18:19], 8 -; SI-NEXT: s_lshr_b64 s[34:35], s[16:17], 24 -; SI-NEXT: s_lshr_b64 s[36:37], s[16:17], 16 -; SI-NEXT: s_lshr_b64 s[38:39], s[16:17], 8 +; SI-NEXT: s_lshr_b32 s51, s45, 8 +; SI-NEXT: s_lshr_b32 s48, s47, 24 +; SI-NEXT: s_lshr_b32 s52, s47, 16 +; SI-NEXT: s_lshr_b32 s53, s47, 8 +; SI-NEXT: s_lshr_b32 s54, s57, 24 +; SI-NEXT: s_lshr_b32 s55, s57, 16 +; SI-NEXT: s_lshr_b32 s49, s57, 8 +; SI-NEXT: v_writelane_b32 v23, s27, 1 +; SI-NEXT: s_lshr_b64 s[64:65], s[18:19], 24 +; SI-NEXT: s_lshr_b64 s[66:67], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[68:69], s[18:19], 8 +; SI-NEXT: s_lshr_b64 s[70:71], s[20:21], 24 +; SI-NEXT: s_lshr_b64 s[80:81], s[20:21], 16 +; SI-NEXT: s_lshr_b64 s[82:83], s[20:21], 8 +; SI-NEXT: s_lshr_b64 s[84:85], s[22:23], 24 +; SI-NEXT: s_lshr_b64 s[86:87], s[22:23], 16 +; SI-NEXT: s_lshr_b64 s[96:97], s[22:23], 8 +; SI-NEXT: s_lshr_b64 s[98:99], s[24:25], 24 +; SI-NEXT: s_lshr_b64 s[26:27], s[24:25], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[24:25], 8 +; SI-NEXT: s_lshr_b64 s[58:59], s[40:41], 24 +; SI-NEXT: s_lshr_b64 s[60:61], s[40:41], 16 +; SI-NEXT: s_lshr_b64 s[62:63], s[40:41], 8 +; SI-NEXT: s_lshr_b64 s[72:73], s[42:43], 24 +; SI-NEXT: s_lshr_b64 s[74:75], s[42:43], 16 +; SI-NEXT: s_lshr_b64 s[76:77], s[42:43], 8 +; SI-NEXT: s_lshr_b64 s[78:79], s[44:45], 24 +; SI-NEXT: s_lshr_b64 s[88:89], s[44:45], 16 +; SI-NEXT: s_lshr_b64 s[90:91], s[44:45], 8 +; SI-NEXT: s_lshr_b64 s[92:93], s[46:47], 24 +; SI-NEXT: s_lshr_b64 s[94:95], s[46:47], 16 +; SI-NEXT: s_lshr_b64 s[30:31], s[46:47], 8 +; SI-NEXT: s_lshr_b64 s[34:35], s[56:57], 24 +; SI-NEXT: s_lshr_b64 s[36:37], s[56:57], 16 +; SI-NEXT: s_lshr_b64 s[38:39], s[56:57], 8 ; SI-NEXT: s_cbranch_execnz .LBB13_3 ; SI-NEXT: .LBB13_2: ; %cmp.true ; SI-NEXT: s_add_i32 s5, s5, 3 ; SI-NEXT: s_add_i32 s4, s4, 3 -; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 40 -; SI-NEXT: v_writelane_b32 v22, s47, 41 -; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 38 -; SI-NEXT: v_writelane_b32 v22, s47, 39 -; SI-NEXT: s_lshr_b32 s46, s5, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 42 -; SI-NEXT: s_lshr_b32 s46, s5, 16 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 40 +; SI-NEXT: v_writelane_b32 v23, s27, 41 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 38 +; SI-NEXT: v_writelane_b32 v23, s27, 39 +; SI-NEXT: s_lshr_b32 s26, s5, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 42 +; SI-NEXT: s_lshr_b32 s26, s5, 16 ; SI-NEXT: s_add_i32 s7, s7, 3 -; SI-NEXT: v_writelane_b32 v22, s46, 43 -; SI-NEXT: s_lshr_b32 s46, s5, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 44 -; SI-NEXT: s_lshr_b32 s46, s7, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 45 -; SI-NEXT: s_lshr_b32 s46, s7, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 43 +; SI-NEXT: s_lshr_b32 s26, s5, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 44 +; SI-NEXT: s_lshr_b32 s26, s7, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 45 +; SI-NEXT: s_lshr_b32 s26, s7, 16 ; SI-NEXT: s_add_i32 s9, s9, 3 -; SI-NEXT: v_writelane_b32 v22, s46, 46 -; SI-NEXT: s_lshr_b32 s46, s7, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 47 -; SI-NEXT: s_lshr_b32 s46, s9, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 46 +; SI-NEXT: s_lshr_b32 s26, s7, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 47 +; SI-NEXT: s_lshr_b32 s26, s9, 16 ; SI-NEXT: s_add_i32 s11, s11, 3 -; SI-NEXT: v_writelane_b32 v22, s46, 48 -; SI-NEXT: s_lshr_b32 s46, s9, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 49 -; SI-NEXT: s_lshr_b32 s46, s11, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 50 -; SI-NEXT: s_lshr_b32 s46, s11, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 48 +; SI-NEXT: s_lshr_b32 s26, s9, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 49 +; SI-NEXT: s_lshr_b32 s26, s11, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 50 +; SI-NEXT: s_lshr_b32 s26, s11, 16 ; SI-NEXT: s_add_i32 s13, s13, 3 -; SI-NEXT: v_writelane_b32 v22, s46, 51 -; SI-NEXT: s_lshr_b32 s46, s11, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 52 -; SI-NEXT: s_lshr_b32 s46, s13, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 53 -; SI-NEXT: s_lshr_b32 s46, s13, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 51 +; SI-NEXT: s_lshr_b32 s26, s11, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 52 +; SI-NEXT: s_lshr_b32 s26, s13, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 53 +; SI-NEXT: s_lshr_b32 s26, s13, 16 ; SI-NEXT: s_add_i32 s15, s15, 3 -; SI-NEXT: v_writelane_b32 v22, s46, 54 -; SI-NEXT: s_lshr_b32 s46, s13, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 55 -; SI-NEXT: s_lshr_b32 s46, s15, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 56 -; SI-NEXT: s_lshr_b32 s46, s15, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 54 +; SI-NEXT: s_lshr_b32 s26, s13, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 55 +; SI-NEXT: s_lshr_b32 s26, s15, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 56 +; SI-NEXT: s_lshr_b32 s26, s15, 16 +; SI-NEXT: s_add_i32 s17, s17, 3 +; SI-NEXT: v_writelane_b32 v23, s26, 57 +; SI-NEXT: s_lshr_b32 s26, s15, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 58 +; SI-NEXT: s_lshr_b32 s26, s17, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 59 +; SI-NEXT: s_lshr_b32 s26, s17, 16 +; SI-NEXT: s_add_i32 s19, s19, 3 +; SI-NEXT: v_writelane_b32 v23, s26, 60 +; SI-NEXT: s_lshr_b32 s26, s17, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 61 +; SI-NEXT: s_lshr_b32 s26, s19, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 62 +; SI-NEXT: s_lshr_b32 s26, s19, 16 +; SI-NEXT: s_add_i32 s21, s21, 3 +; SI-NEXT: v_writelane_b32 v23, s26, 63 +; SI-NEXT: s_lshr_b32 s26, s19, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 0 +; SI-NEXT: s_lshr_b32 s26, s21, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 1 +; SI-NEXT: s_lshr_b32 s26, s21, 16 +; SI-NEXT: s_add_i32 s23, s23, 3 +; SI-NEXT: v_writelane_b32 v22, s26, 2 +; SI-NEXT: s_lshr_b32 s26, s21, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 3 +; SI-NEXT: s_lshr_b32 s26, s23, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 4 +; SI-NEXT: s_lshr_b32 s26, s23, 16 +; SI-NEXT: s_add_i32 s25, s25, 3 +; SI-NEXT: v_writelane_b32 v22, s26, 5 +; SI-NEXT: s_lshr_b32 s26, s23, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 6 +; SI-NEXT: s_lshr_b32 s26, s25, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 7 +; SI-NEXT: s_lshr_b32 s26, s25, 16 ; SI-NEXT: s_add_i32 s41, s41, 3 -; SI-NEXT: v_writelane_b32 v22, s46, 57 -; SI-NEXT: s_lshr_b32 s46, s15, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 58 -; SI-NEXT: s_lshr_b32 s46, s41, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 59 -; SI-NEXT: s_lshr_b32 s46, s41, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 8 +; SI-NEXT: s_lshr_b32 s26, s25, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 9 +; SI-NEXT: s_lshr_b32 s26, s41, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 10 +; SI-NEXT: s_lshr_b32 s26, s41, 16 ; SI-NEXT: s_add_i32 s43, s43, 3 -; SI-NEXT: v_writelane_b32 v22, s46, 60 -; SI-NEXT: s_lshr_b32 s46, s41, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 61 -; SI-NEXT: s_lshr_b32 s46, s43, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 62 -; SI-NEXT: s_lshr_b32 s46, s43, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 11 +; SI-NEXT: s_lshr_b32 s26, s41, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 12 +; SI-NEXT: s_lshr_b32 s26, s43, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 13 +; SI-NEXT: s_lshr_b32 s26, s43, 16 ; SI-NEXT: s_add_i32 s45, s45, 3 -; SI-NEXT: v_writelane_b32 v22, s46, 63 -; SI-NEXT: s_lshr_b32 s46, s43, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 0 -; SI-NEXT: s_lshr_b32 s46, s45, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 1 -; SI-NEXT: s_lshr_b32 s46, s45, 16 -; SI-NEXT: s_add_i32 s29, s29, 3 -; SI-NEXT: v_writelane_b32 v21, s46, 2 -; SI-NEXT: s_lshr_b32 s46, s45, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 3 -; SI-NEXT: s_lshr_b32 s46, s29, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 4 -; SI-NEXT: s_lshr_b32 s46, s29, 16 -; SI-NEXT: s_add_i32 s27, s27, 3 -; SI-NEXT: v_writelane_b32 v21, s46, 5 -; SI-NEXT: s_lshr_b32 s46, s29, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 6 -; SI-NEXT: s_lshr_b32 s46, s27, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 7 -; SI-NEXT: s_lshr_b32 s46, s27, 16 -; SI-NEXT: s_add_i32 s25, s25, 3 -; SI-NEXT: v_writelane_b32 v21, s46, 8 -; SI-NEXT: s_lshr_b32 s46, s27, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 9 -; SI-NEXT: s_lshr_b32 s46, s25, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 10 -; SI-NEXT: s_lshr_b32 s46, s25, 16 -; SI-NEXT: s_add_i32 s23, s23, 3 -; SI-NEXT: v_writelane_b32 v21, s46, 11 -; SI-NEXT: s_lshr_b32 s46, s25, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 12 -; SI-NEXT: s_lshr_b32 s46, s23, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 13 -; SI-NEXT: s_lshr_b32 s46, s23, 16 -; SI-NEXT: s_add_i32 s21, s21, 3 -; SI-NEXT: v_writelane_b32 v21, s46, 14 -; SI-NEXT: s_lshr_b32 s46, s23, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 15 -; SI-NEXT: s_lshr_b32 s46, s21, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 16 -; SI-NEXT: s_lshr_b32 s46, s21, 16 -; SI-NEXT: v_writelane_b32 v21, s46, 17 -; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 8 +; SI-NEXT: v_writelane_b32 v22, s26, 14 +; SI-NEXT: s_lshr_b32 s26, s43, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 15 +; SI-NEXT: s_lshr_b32 s26, s45, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 16 +; SI-NEXT: s_lshr_b32 s26, s45, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 17 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 8 ; SI-NEXT: s_add_i32 s6, s6, 3 -; SI-NEXT: v_writelane_b32 v22, s46, 36 -; SI-NEXT: v_writelane_b32 v22, s47, 37 -; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 34 -; SI-NEXT: v_writelane_b32 v22, s47, 35 -; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 32 -; SI-NEXT: v_writelane_b32 v22, s47, 33 -; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 36 +; SI-NEXT: v_writelane_b32 v23, s27, 37 +; SI-NEXT: s_lshr_b64 s[26:27], s[6:7], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 34 +; SI-NEXT: v_writelane_b32 v23, s27, 35 +; SI-NEXT: s_lshr_b64 s[26:27], s[6:7], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 32 +; SI-NEXT: v_writelane_b32 v23, s27, 33 +; SI-NEXT: s_lshr_b64 s[26:27], s[6:7], 8 ; SI-NEXT: s_add_i32 s8, s8, 3 -; SI-NEXT: v_writelane_b32 v22, s46, 30 -; SI-NEXT: v_writelane_b32 v22, s47, 31 -; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 28 -; SI-NEXT: v_writelane_b32 v22, s47, 29 -; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 26 -; SI-NEXT: v_writelane_b32 v22, s47, 27 -; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 30 +; SI-NEXT: v_writelane_b32 v23, s27, 31 +; SI-NEXT: s_lshr_b64 s[26:27], s[8:9], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 28 +; SI-NEXT: v_writelane_b32 v23, s27, 29 +; SI-NEXT: s_lshr_b64 s[26:27], s[8:9], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 26 +; SI-NEXT: v_writelane_b32 v23, s27, 27 +; SI-NEXT: s_lshr_b64 s[26:27], s[8:9], 8 ; SI-NEXT: s_add_i32 s10, s10, 3 -; SI-NEXT: v_writelane_b32 v22, s46, 24 -; SI-NEXT: v_writelane_b32 v22, s47, 25 -; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 22 -; SI-NEXT: v_writelane_b32 v22, s47, 23 -; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 20 -; SI-NEXT: v_writelane_b32 v22, s47, 21 -; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 24 +; SI-NEXT: v_writelane_b32 v23, s27, 25 +; SI-NEXT: s_lshr_b64 s[26:27], s[10:11], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 22 +; SI-NEXT: v_writelane_b32 v23, s27, 23 +; SI-NEXT: s_lshr_b64 s[26:27], s[10:11], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 20 +; SI-NEXT: v_writelane_b32 v23, s27, 21 +; SI-NEXT: s_lshr_b64 s[26:27], s[10:11], 8 ; SI-NEXT: s_add_i32 s12, s12, 3 -; SI-NEXT: v_writelane_b32 v22, s46, 18 -; SI-NEXT: v_writelane_b32 v22, s47, 19 -; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 16 -; SI-NEXT: v_writelane_b32 v22, s47, 17 -; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 14 -; SI-NEXT: v_writelane_b32 v22, s47, 15 -; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 18 +; SI-NEXT: v_writelane_b32 v23, s27, 19 +; SI-NEXT: s_lshr_b64 s[26:27], s[12:13], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 16 +; SI-NEXT: v_writelane_b32 v23, s27, 17 +; SI-NEXT: s_lshr_b64 s[26:27], s[12:13], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 14 +; SI-NEXT: v_writelane_b32 v23, s27, 15 +; SI-NEXT: s_lshr_b64 s[26:27], s[12:13], 8 ; SI-NEXT: s_add_i32 s14, s14, 3 -; SI-NEXT: v_writelane_b32 v22, s46, 12 -; SI-NEXT: v_writelane_b32 v22, s47, 13 -; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 10 -; SI-NEXT: v_writelane_b32 v22, s47, 11 -; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 8 -; SI-NEXT: v_writelane_b32 v22, s47, 9 -; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 8 -; SI-NEXT: s_add_i32 s40, s40, 3 -; SI-NEXT: v_writelane_b32 v22, s46, 6 -; SI-NEXT: v_writelane_b32 v22, s47, 7 -; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 4 -; SI-NEXT: v_writelane_b32 v22, s47, 5 -; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 2 -; SI-NEXT: v_writelane_b32 v22, s47, 3 -; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 8 -; SI-NEXT: s_add_i32 s17, s17, 3 +; SI-NEXT: v_writelane_b32 v23, s26, 12 +; SI-NEXT: v_writelane_b32 v23, s27, 13 +; SI-NEXT: s_lshr_b64 s[26:27], s[14:15], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 10 +; SI-NEXT: v_writelane_b32 v23, s27, 11 +; SI-NEXT: s_lshr_b64 s[26:27], s[14:15], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 8 +; SI-NEXT: v_writelane_b32 v23, s27, 9 +; SI-NEXT: s_lshr_b64 s[26:27], s[14:15], 8 ; SI-NEXT: s_add_i32 s16, s16, 3 -; SI-NEXT: s_add_i32 s19, s19, 3 -; SI-NEXT: s_add_i32 s18, s18, 3 -; SI-NEXT: s_add_i32 s20, s20, 3 -; SI-NEXT: s_add_i32 s22, s22, 3 -; SI-NEXT: s_add_i32 s24, s24, 3 -; SI-NEXT: s_add_i32 s26, s26, 3 -; SI-NEXT: s_add_i32 s28, s28, 3 +; SI-NEXT: v_writelane_b32 v23, s26, 6 +; SI-NEXT: v_writelane_b32 v23, s27, 7 +; SI-NEXT: s_lshr_b64 s[26:27], s[16:17], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 4 +; SI-NEXT: v_writelane_b32 v23, s27, 5 +; SI-NEXT: s_lshr_b64 s[26:27], s[16:17], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 2 +; SI-NEXT: v_writelane_b32 v23, s27, 3 +; SI-NEXT: s_lshr_b64 s[26:27], s[16:17], 8 +; SI-NEXT: s_add_i32 s57, s57, 3 +; SI-NEXT: s_add_i32 s56, s56, 3 +; SI-NEXT: s_add_i32 s47, s47, 3 +; SI-NEXT: s_add_i32 s46, s46, 3 ; SI-NEXT: s_add_i32 s44, s44, 3 ; SI-NEXT: s_add_i32 s42, s42, 3 -; SI-NEXT: v_writelane_b32 v22, s46, 0 +; SI-NEXT: s_add_i32 s40, s40, 3 +; SI-NEXT: s_add_i32 s24, s24, 3 +; SI-NEXT: s_add_i32 s22, s22, 3 +; SI-NEXT: s_add_i32 s20, s20, 3 +; SI-NEXT: s_add_i32 s18, s18, 3 +; SI-NEXT: v_writelane_b32 v23, s26, 0 ; SI-NEXT: s_lshr_b32 s50, s9, 24 -; SI-NEXT: s_lshr_b32 s51, s21, 8 -; SI-NEXT: s_lshr_b32 s48, s19, 24 -; SI-NEXT: s_lshr_b32 s52, s19, 16 -; SI-NEXT: s_lshr_b32 s53, s19, 8 -; SI-NEXT: s_lshr_b32 s54, s17, 24 -; SI-NEXT: s_lshr_b32 s55, s17, 16 -; SI-NEXT: s_lshr_b32 s49, s17, 8 -; SI-NEXT: v_writelane_b32 v22, s47, 1 -; SI-NEXT: s_lshr_b64 s[64:65], s[42:43], 24 -; SI-NEXT: s_lshr_b64 s[66:67], s[42:43], 16 -; SI-NEXT: s_lshr_b64 s[68:69], s[42:43], 8 -; SI-NEXT: s_lshr_b64 s[70:71], s[44:45], 24 -; SI-NEXT: s_lshr_b64 s[80:81], s[44:45], 16 -; SI-NEXT: s_lshr_b64 s[82:83], s[44:45], 8 -; SI-NEXT: s_lshr_b64 s[84:85], s[28:29], 24 -; SI-NEXT: s_lshr_b64 s[86:87], s[28:29], 16 -; SI-NEXT: s_lshr_b64 s[96:97], s[28:29], 8 -; SI-NEXT: s_lshr_b64 s[98:99], s[26:27], 24 -; SI-NEXT: s_lshr_b64 s[46:47], s[26:27], 16 -; SI-NEXT: s_lshr_b64 s[56:57], s[26:27], 8 -; SI-NEXT: s_lshr_b64 s[58:59], s[24:25], 24 -; SI-NEXT: s_lshr_b64 s[60:61], s[24:25], 16 -; SI-NEXT: s_lshr_b64 s[62:63], s[24:25], 8 -; SI-NEXT: s_lshr_b64 s[72:73], s[22:23], 24 -; SI-NEXT: s_lshr_b64 s[74:75], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[76:77], s[22:23], 8 -; SI-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 -; SI-NEXT: s_lshr_b64 s[88:89], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[90:91], s[20:21], 8 -; SI-NEXT: s_lshr_b64 s[92:93], s[18:19], 24 -; SI-NEXT: s_lshr_b64 s[94:95], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[30:31], s[18:19], 8 -; SI-NEXT: s_lshr_b64 s[34:35], s[16:17], 24 -; SI-NEXT: s_lshr_b64 s[36:37], s[16:17], 16 -; SI-NEXT: s_lshr_b64 s[38:39], s[16:17], 8 +; SI-NEXT: s_lshr_b32 s51, s45, 8 +; SI-NEXT: s_lshr_b32 s48, s47, 24 +; SI-NEXT: s_lshr_b32 s52, s47, 16 +; SI-NEXT: s_lshr_b32 s53, s47, 8 +; SI-NEXT: s_lshr_b32 s54, s57, 24 +; SI-NEXT: s_lshr_b32 s55, s57, 16 +; SI-NEXT: s_lshr_b32 s49, s57, 8 +; SI-NEXT: v_writelane_b32 v23, s27, 1 +; SI-NEXT: s_lshr_b64 s[64:65], s[18:19], 24 +; SI-NEXT: s_lshr_b64 s[66:67], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[68:69], s[18:19], 8 +; SI-NEXT: s_lshr_b64 s[70:71], s[20:21], 24 +; SI-NEXT: s_lshr_b64 s[80:81], s[20:21], 16 +; SI-NEXT: s_lshr_b64 s[82:83], s[20:21], 8 +; SI-NEXT: s_lshr_b64 s[84:85], s[22:23], 24 +; SI-NEXT: s_lshr_b64 s[86:87], s[22:23], 16 +; SI-NEXT: s_lshr_b64 s[96:97], s[22:23], 8 +; SI-NEXT: s_lshr_b64 s[98:99], s[24:25], 24 +; SI-NEXT: s_lshr_b64 s[26:27], s[24:25], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[24:25], 8 +; SI-NEXT: s_lshr_b64 s[58:59], s[40:41], 24 +; SI-NEXT: s_lshr_b64 s[60:61], s[40:41], 16 +; SI-NEXT: s_lshr_b64 s[62:63], s[40:41], 8 +; SI-NEXT: s_lshr_b64 s[72:73], s[42:43], 24 +; SI-NEXT: s_lshr_b64 s[74:75], s[42:43], 16 +; SI-NEXT: s_lshr_b64 s[76:77], s[42:43], 8 +; SI-NEXT: s_lshr_b64 s[78:79], s[44:45], 24 +; SI-NEXT: s_lshr_b64 s[88:89], s[44:45], 16 +; SI-NEXT: s_lshr_b64 s[90:91], s[44:45], 8 +; SI-NEXT: s_lshr_b64 s[92:93], s[46:47], 24 +; SI-NEXT: s_lshr_b64 s[94:95], s[46:47], 16 +; SI-NEXT: s_lshr_b64 s[30:31], s[46:47], 8 +; SI-NEXT: s_lshr_b64 s[34:35], s[56:57], 24 +; SI-NEXT: s_lshr_b64 s[36:37], s[56:57], 16 +; SI-NEXT: s_lshr_b64 s[38:39], s[56:57], 8 ; SI-NEXT: .LBB13_3: ; %end -; SI-NEXT: s_lshl_b32 s47, s38, 8 -; SI-NEXT: s_and_b32 s16, s16, 0xff -; SI-NEXT: s_or_b32 s16, s16, s47 -; SI-NEXT: s_and_b32 s47, s36, 0xff -; SI-NEXT: s_lshl_b32 s57, s34, 24 -; SI-NEXT: s_lshl_b32 s47, s47, 16 -; SI-NEXT: s_or_b32 s47, s57, s47 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s47 -; SI-NEXT: v_mov_b32_e32 v1, s16 -; SI-NEXT: s_and_b32 s16, s17, 0xff -; SI-NEXT: s_lshl_b32 s17, s49, 8 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: s_and_b32 s17, s55, 0xff -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_lshl_b32 s47, s54, 24 -; SI-NEXT: s_or_b32 s17, s47, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_lshl_b32 s16, s30, 8 -; SI-NEXT: s_and_b32 s17, s18, 0xff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: s_and_b32 s17, s94, 0xff -; SI-NEXT: s_lshl_b32 s18, s92, 24 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v3, s16 -; SI-NEXT: s_and_b32 s16, s19, 0xff -; SI-NEXT: s_lshl_b32 s17, s53, 8 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: s_and_b32 s17, s52, 0xff -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_lshl_b32 s18, s48, 24 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v4, s16 -; SI-NEXT: s_lshl_b32 s16, s90, 8 -; SI-NEXT: s_and_b32 s17, s20, 0xff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: s_and_b32 s17, s88, 0xff -; SI-NEXT: s_lshl_b32 s18, s78, 24 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v5, s16 -; SI-NEXT: s_and_b32 s16, s21, 0xff -; SI-NEXT: s_lshl_b32 s17, s51, 8 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 17 -; SI-NEXT: s_and_b32 s17, s17, 0xff -; SI-NEXT: v_readlane_b32 s18, v21, 16 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_lshl_b32 s18, s18, 24 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v6, s16 -; SI-NEXT: s_lshl_b32 s16, s76, 8 -; SI-NEXT: s_and_b32 s17, s22, 0xff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: s_and_b32 s17, s74, 0xff -; SI-NEXT: s_lshl_b32 s18, s72, 24 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 15 -; SI-NEXT: v_mov_b32_e32 v7, s16 -; SI-NEXT: s_and_b32 s16, s23, 0xff -; SI-NEXT: s_lshl_b32 s17, s17, 8 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 14 -; SI-NEXT: s_and_b32 s17, s17, 0xff -; SI-NEXT: v_readlane_b32 s18, v21, 13 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_lshl_b32 s18, s18, 24 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v8, s16 -; SI-NEXT: s_lshl_b32 s16, s62, 8 -; SI-NEXT: s_and_b32 s17, s24, 0xff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: s_and_b32 s17, s60, 0xff -; SI-NEXT: s_lshl_b32 s18, s58, 24 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 12 -; SI-NEXT: v_mov_b32_e32 v9, s16 -; SI-NEXT: s_and_b32 s16, s25, 0xff -; SI-NEXT: s_lshl_b32 s17, s17, 8 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 11 -; SI-NEXT: s_and_b32 s17, s17, 0xff -; SI-NEXT: v_readlane_b32 s18, v21, 10 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_lshl_b32 s18, s18, 24 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v10, s16 -; SI-NEXT: s_lshl_b32 s16, s56, 8 -; SI-NEXT: s_and_b32 s17, s26, 0xff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: s_and_b32 s17, s46, 0xff -; SI-NEXT: s_lshl_b32 s18, s98, 24 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 9 -; SI-NEXT: v_mov_b32_e32 v11, s16 -; SI-NEXT: s_and_b32 s16, s27, 0xff -; SI-NEXT: s_lshl_b32 s17, s17, 8 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 8 -; SI-NEXT: s_and_b32 s17, s17, 0xff -; SI-NEXT: v_readlane_b32 s18, v21, 7 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_lshl_b32 s18, s18, 24 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v12, s16 -; SI-NEXT: s_lshl_b32 s16, s96, 8 -; SI-NEXT: s_and_b32 s17, s28, 0xff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: s_and_b32 s17, s86, 0xff -; SI-NEXT: s_lshl_b32 s18, s84, 24 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 6 -; SI-NEXT: v_mov_b32_e32 v13, s16 -; SI-NEXT: s_and_b32 s16, s29, 0xff -; SI-NEXT: s_lshl_b32 s17, s17, 8 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 5 -; SI-NEXT: s_and_b32 s17, s17, 0xff -; SI-NEXT: v_readlane_b32 s18, v21, 4 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_lshl_b32 s18, s18, 24 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v14, s16 -; SI-NEXT: s_lshl_b32 s16, s82, 8 -; SI-NEXT: s_and_b32 s17, s44, 0xff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: s_and_b32 s17, s80, 0xff -; SI-NEXT: s_lshl_b32 s18, s70, 24 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 3 -; SI-NEXT: v_mov_b32_e32 v15, s16 -; SI-NEXT: s_and_b32 s16, s45, 0xff -; SI-NEXT: s_lshl_b32 s17, s17, 8 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 2 -; SI-NEXT: s_and_b32 s17, s17, 0xff -; SI-NEXT: v_readlane_b32 s18, v21, 1 +; SI-NEXT: s_lshl_b32 s27, s38, 8 +; SI-NEXT: s_and_b32 s29, s56, 0xff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: s_and_b32 s29, s36, 0xff +; SI-NEXT: s_lshl_b32 s56, s34, 24 +; SI-NEXT: s_lshl_b32 s29, s29, 16 +; SI-NEXT: s_or_b32 s29, s56, s29 +; SI-NEXT: s_and_b32 s27, s27, 0xffff +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v1, s27 +; SI-NEXT: s_and_b32 s27, s57, 0xff +; SI-NEXT: s_lshl_b32 s29, s49, 8 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: s_and_b32 s29, s55, 0xff +; SI-NEXT: s_lshl_b32 s29, s29, 16 +; SI-NEXT: s_lshl_b32 s56, s54, 24 +; SI-NEXT: s_or_b32 s29, s56, s29 +; SI-NEXT: s_and_b32 s27, s27, 0xffff +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_lshl_b32 s27, s30, 8 +; SI-NEXT: s_and_b32 s29, s46, 0xff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: s_and_b32 s29, s94, 0xff +; SI-NEXT: s_lshl_b32 s46, s92, 24 +; SI-NEXT: s_lshl_b32 s29, s29, 16 +; SI-NEXT: s_or_b32 s29, s46, s29 +; SI-NEXT: s_and_b32 s27, s27, 0xffff +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v3, s27 +; SI-NEXT: s_and_b32 s27, s47, 0xff +; SI-NEXT: s_lshl_b32 s29, s53, 8 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: s_and_b32 s29, s52, 0xff +; SI-NEXT: s_lshl_b32 s29, s29, 16 +; SI-NEXT: s_lshl_b32 s46, s48, 24 +; SI-NEXT: s_or_b32 s29, s46, s29 +; SI-NEXT: s_and_b32 s27, s27, 0xffff +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v4, s27 +; SI-NEXT: s_lshl_b32 s27, s90, 8 +; SI-NEXT: s_and_b32 s29, s44, 0xff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: s_and_b32 s29, s88, 0xff +; SI-NEXT: s_lshl_b32 s44, s78, 24 +; SI-NEXT: s_lshl_b32 s29, s29, 16 +; SI-NEXT: s_or_b32 s29, s44, s29 +; SI-NEXT: s_and_b32 s27, s27, 0xffff +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v5, s27 +; SI-NEXT: s_and_b32 s27, s45, 0xff +; SI-NEXT: s_lshl_b32 s29, s51, 8 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_readlane_b32 s29, v22, 17 +; SI-NEXT: s_and_b32 s29, s29, 0xff +; SI-NEXT: v_readlane_b32 s44, v22, 16 +; SI-NEXT: s_lshl_b32 s29, s29, 16 +; SI-NEXT: s_lshl_b32 s44, s44, 24 +; SI-NEXT: s_or_b32 s29, s44, s29 +; SI-NEXT: s_and_b32 s27, s27, 0xffff +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v6, s27 +; SI-NEXT: s_lshl_b32 s27, s76, 8 +; SI-NEXT: s_and_b32 s29, s42, 0xff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: s_and_b32 s29, s74, 0xff +; SI-NEXT: s_lshl_b32 s42, s72, 24 +; SI-NEXT: s_lshl_b32 s29, s29, 16 +; SI-NEXT: s_or_b32 s29, s42, s29 +; SI-NEXT: s_and_b32 s27, s27, 0xffff +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_readlane_b32 s29, v22, 15 +; SI-NEXT: v_mov_b32_e32 v7, s27 +; SI-NEXT: s_and_b32 s27, s43, 0xff +; SI-NEXT: s_lshl_b32 s29, s29, 8 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_readlane_b32 s29, v22, 14 +; SI-NEXT: s_and_b32 s29, s29, 0xff +; SI-NEXT: v_readlane_b32 s42, v22, 13 +; SI-NEXT: s_lshl_b32 s29, s29, 16 +; SI-NEXT: s_lshl_b32 s42, s42, 24 +; SI-NEXT: s_or_b32 s29, s42, s29 +; SI-NEXT: s_and_b32 s27, s27, 0xffff +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v8, s27 +; SI-NEXT: s_lshl_b32 s27, s62, 8 +; SI-NEXT: s_and_b32 s29, s40, 0xff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: s_and_b32 s29, s60, 0xff +; SI-NEXT: s_lshl_b32 s40, s58, 24 +; SI-NEXT: s_lshl_b32 s29, s29, 16 +; SI-NEXT: s_or_b32 s29, s40, s29 +; SI-NEXT: s_and_b32 s27, s27, 0xffff +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_readlane_b32 s29, v22, 12 +; SI-NEXT: v_mov_b32_e32 v9, s27 +; SI-NEXT: s_and_b32 s27, s41, 0xff +; SI-NEXT: s_lshl_b32 s29, s29, 8 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_readlane_b32 s29, v22, 11 +; SI-NEXT: s_and_b32 s29, s29, 0xff +; SI-NEXT: v_readlane_b32 s40, v22, 10 +; SI-NEXT: s_lshl_b32 s29, s29, 16 +; SI-NEXT: s_lshl_b32 s40, s40, 24 +; SI-NEXT: s_or_b32 s29, s40, s29 +; SI-NEXT: s_and_b32 s27, s27, 0xffff +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v10, s27 +; SI-NEXT: s_lshl_b32 s27, s28, 8 +; SI-NEXT: s_and_b32 s24, s24, 0xff +; SI-NEXT: s_and_b32 s26, s26, 0xff +; SI-NEXT: s_or_b32 s24, s24, s27 +; SI-NEXT: s_lshl_b32 s27, s98, 24 +; SI-NEXT: s_lshl_b32 s26, s26, 16 +; SI-NEXT: s_or_b32 s26, s27, s26 +; SI-NEXT: s_and_b32 s24, s24, 0xffff +; SI-NEXT: s_or_b32 s24, s24, s26 +; SI-NEXT: v_mov_b32_e32 v11, s24 +; SI-NEXT: s_and_b32 s24, s25, 0xff +; SI-NEXT: v_readlane_b32 s25, v22, 9 +; SI-NEXT: s_lshl_b32 s25, s25, 8 +; SI-NEXT: s_or_b32 s24, s24, s25 +; SI-NEXT: v_readlane_b32 s25, v22, 8 +; SI-NEXT: s_and_b32 s25, s25, 0xff +; SI-NEXT: v_readlane_b32 s26, v22, 7 +; SI-NEXT: s_lshl_b32 s25, s25, 16 +; SI-NEXT: s_lshl_b32 s26, s26, 24 +; SI-NEXT: s_or_b32 s25, s26, s25 +; SI-NEXT: s_and_b32 s24, s24, 0xffff +; SI-NEXT: s_or_b32 s24, s24, s25 +; SI-NEXT: v_mov_b32_e32 v12, s24 +; SI-NEXT: s_lshl_b32 s24, s96, 8 +; SI-NEXT: s_and_b32 s22, s22, 0xff +; SI-NEXT: s_or_b32 s22, s22, s24 +; SI-NEXT: s_and_b32 s24, s86, 0xff +; SI-NEXT: s_lshl_b32 s25, s84, 24 +; SI-NEXT: s_lshl_b32 s24, s24, 16 +; SI-NEXT: s_or_b32 s24, s25, s24 +; SI-NEXT: s_and_b32 s22, s22, 0xffff +; SI-NEXT: s_or_b32 s22, s22, s24 +; SI-NEXT: v_mov_b32_e32 v13, s22 +; SI-NEXT: s_and_b32 s22, s23, 0xff +; SI-NEXT: v_readlane_b32 s23, v22, 6 +; SI-NEXT: s_lshl_b32 s23, s23, 8 +; SI-NEXT: s_or_b32 s22, s22, s23 +; SI-NEXT: v_readlane_b32 s23, v22, 5 +; SI-NEXT: s_and_b32 s23, s23, 0xff +; SI-NEXT: v_readlane_b32 s24, v22, 4 +; SI-NEXT: s_lshl_b32 s23, s23, 16 +; SI-NEXT: s_lshl_b32 s24, s24, 24 +; SI-NEXT: s_or_b32 s23, s24, s23 +; SI-NEXT: s_and_b32 s22, s22, 0xffff +; SI-NEXT: s_or_b32 s22, s22, s23 +; SI-NEXT: v_mov_b32_e32 v14, s22 +; SI-NEXT: s_lshl_b32 s22, s82, 8 +; SI-NEXT: s_and_b32 s20, s20, 0xff +; SI-NEXT: s_or_b32 s20, s20, s22 +; SI-NEXT: s_and_b32 s22, s80, 0xff +; SI-NEXT: s_lshl_b32 s23, s70, 24 +; SI-NEXT: s_lshl_b32 s22, s22, 16 +; SI-NEXT: s_or_b32 s22, s23, s22 +; SI-NEXT: s_and_b32 s20, s20, 0xffff +; SI-NEXT: s_or_b32 s20, s20, s22 +; SI-NEXT: v_mov_b32_e32 v15, s20 +; SI-NEXT: s_and_b32 s20, s21, 0xff +; SI-NEXT: v_readlane_b32 s21, v22, 3 +; SI-NEXT: s_lshl_b32 s21, s21, 8 +; SI-NEXT: s_or_b32 s20, s20, s21 +; SI-NEXT: v_readlane_b32 s21, v22, 2 +; SI-NEXT: s_and_b32 s21, s21, 0xff +; SI-NEXT: v_readlane_b32 s22, v22, 1 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_lshl_b32 s18, s18, 24 +; SI-NEXT: s_lshl_b32 s21, s21, 16 +; SI-NEXT: s_lshl_b32 s22, s22, 24 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff +; SI-NEXT: s_or_b32 s21, s22, s21 +; SI-NEXT: s_and_b32 s20, s20, 0xffff ; SI-NEXT: buffer_store_dword v3, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 12, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s20, s20, s21 ; SI-NEXT: buffer_store_dword v4, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0 -; SI-NEXT: v_mov_b32_e32 v16, s16 -; SI-NEXT: s_lshl_b32 s16, s68, 8 -; SI-NEXT: s_and_b32 s17, s42, 0xff +; SI-NEXT: v_mov_b32_e32 v16, s20 +; SI-NEXT: s_lshl_b32 s20, s68, 8 +; SI-NEXT: s_and_b32 s18, s18, 0xff ; SI-NEXT: buffer_store_dword v5, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 20, v0 -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: s_and_b32 s17, s66, 0xff +; SI-NEXT: s_or_b32 s18, s18, s20 +; SI-NEXT: s_and_b32 s20, s66, 0xff ; SI-NEXT: buffer_store_dword v6, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0 -; SI-NEXT: s_lshl_b32 s18, s64, 24 -; SI-NEXT: s_lshl_b32 s17, s17, 16 +; SI-NEXT: s_lshl_b32 s21, s64, 24 +; SI-NEXT: s_lshl_b32 s20, s20, 16 ; SI-NEXT: buffer_store_dword v7, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 28, v0 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff +; SI-NEXT: s_or_b32 s20, s21, s20 +; SI-NEXT: s_and_b32 s18, s18, 0xffff ; SI-NEXT: buffer_store_dword v8, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s18, s18, s20 ; SI-NEXT: buffer_store_dword v9, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 36, v0 -; SI-NEXT: v_readlane_b32 s17, v21, 0 ; SI-NEXT: buffer_store_dword v10, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0 -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s43, 0xff -; SI-NEXT: s_lshl_b32 s17, s17, 8 +; SI-NEXT: v_mov_b32_e32 v2, s18 +; SI-NEXT: s_and_b32 s18, s19, 0xff +; SI-NEXT: v_readlane_b32 s19, v22, 0 ; SI-NEXT: buffer_store_dword v11, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 44, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v22, 63 +; SI-NEXT: s_lshl_b32 s19, s19, 8 ; SI-NEXT: buffer_store_dword v12, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0 -; SI-NEXT: s_and_b32 s17, s17, 0xff -; SI-NEXT: v_readlane_b32 s18, v22, 62 +; SI-NEXT: s_or_b32 s18, s18, s19 +; SI-NEXT: v_readlane_b32 s19, v23, 63 ; SI-NEXT: buffer_store_dword v13, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 52, v0 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_lshl_b32 s18, s18, 24 +; SI-NEXT: s_and_b32 s19, s19, 0xff +; SI-NEXT: v_readlane_b32 s20, v23, 62 ; SI-NEXT: buffer_store_dword v14, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 56, v0 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: v_readlane_b32 s18, v22, 0 +; SI-NEXT: s_lshl_b32 s19, s19, 16 +; SI-NEXT: s_lshl_b32 s20, s20, 24 ; SI-NEXT: buffer_store_dword v15, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 60, v0 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: v_readlane_b32 s19, v22, 1 +; SI-NEXT: s_and_b32 s18, s18, 0xffff +; SI-NEXT: s_or_b32 s19, s20, s19 ; SI-NEXT: buffer_store_dword v16, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 64, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: s_lshl_b32 s17, s18, 8 -; SI-NEXT: v_readlane_b32 s18, v22, 2 +; SI-NEXT: s_or_b32 s18, s18, s19 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s40, 0xff -; SI-NEXT: v_readlane_b32 s19, v22, 3 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: s_and_b32 s17, s18, 0xff -; SI-NEXT: v_readlane_b32 s18, v22, 4 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_lshl_b32 s18, s18, 24 +; SI-NEXT: v_mov_b32_e32 v2, s18 +; SI-NEXT: v_readlane_b32 s18, v23, 0 +; SI-NEXT: s_and_b32 s16, s16, 0xff +; SI-NEXT: v_readlane_b32 s19, v23, 1 +; SI-NEXT: s_lshl_b32 s18, s18, 8 +; SI-NEXT: s_or_b32 s16, s16, s18 +; SI-NEXT: v_readlane_b32 s18, v23, 2 +; SI-NEXT: v_readlane_b32 s19, v23, 3 +; SI-NEXT: s_and_b32 s18, s18, 0xff +; SI-NEXT: v_readlane_b32 s20, v23, 4 +; SI-NEXT: s_lshl_b32 s18, s18, 16 +; SI-NEXT: s_lshl_b32 s19, s20, 24 ; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s17, s18, s17 +; SI-NEXT: s_or_b32 s18, s19, s18 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x44, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v22, 61 +; SI-NEXT: s_or_b32 s16, s16, s18 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s41, 0xff +; SI-NEXT: s_and_b32 s16, s17, 0xff +; SI-NEXT: v_readlane_b32 s17, v23, 61 ; SI-NEXT: s_lshl_b32 s17, s17, 8 ; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v22, 60 +; SI-NEXT: v_readlane_b32 s17, v23, 60 ; SI-NEXT: s_and_b32 s17, s17, 0xff -; SI-NEXT: v_readlane_b32 s18, v22, 59 +; SI-NEXT: v_readlane_b32 s18, v23, 59 ; SI-NEXT: s_lshl_b32 s17, s17, 16 ; SI-NEXT: s_lshl_b32 s18, s18, 24 ; SI-NEXT: s_and_b32 s16, s16, 0xffff @@ -8185,16 +8213,15 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: v_readlane_b32 s16, v22, 6 +; SI-NEXT: v_readlane_b32 s16, v23, 6 ; SI-NEXT: s_and_b32 s14, s14, 0xff -; SI-NEXT: v_readlane_b32 s17, v22, 7 +; SI-NEXT: v_readlane_b32 s17, v23, 7 ; SI-NEXT: s_lshl_b32 s16, s16, 8 -; SI-NEXT: v_readlane_b32 s19, v22, 5 ; SI-NEXT: s_or_b32 s14, s14, s16 -; SI-NEXT: v_readlane_b32 s16, v22, 8 -; SI-NEXT: v_readlane_b32 s17, v22, 9 +; SI-NEXT: v_readlane_b32 s16, v23, 8 +; SI-NEXT: v_readlane_b32 s17, v23, 9 ; SI-NEXT: s_and_b32 s16, s16, 0xff -; SI-NEXT: v_readlane_b32 s18, v22, 10 +; SI-NEXT: v_readlane_b32 s18, v23, 10 ; SI-NEXT: s_lshl_b32 s16, s16, 16 ; SI-NEXT: s_lshl_b32 s17, s18, 24 ; SI-NEXT: s_and_b32 s14, s14, 0xffff @@ -8205,12 +8232,12 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s14 ; SI-NEXT: s_and_b32 s14, s15, 0xff -; SI-NEXT: v_readlane_b32 s15, v22, 58 +; SI-NEXT: v_readlane_b32 s15, v23, 58 ; SI-NEXT: s_lshl_b32 s15, s15, 8 ; SI-NEXT: s_or_b32 s14, s14, s15 -; SI-NEXT: v_readlane_b32 s15, v22, 57 +; SI-NEXT: v_readlane_b32 s15, v23, 57 ; SI-NEXT: s_and_b32 s15, s15, 0xff -; SI-NEXT: v_readlane_b32 s16, v22, 56 +; SI-NEXT: v_readlane_b32 s16, v23, 56 ; SI-NEXT: s_lshl_b32 s15, s15, 16 ; SI-NEXT: s_lshl_b32 s16, s16, 24 ; SI-NEXT: s_and_b32 s14, s14, 0xffff @@ -8220,15 +8247,15 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s14 -; SI-NEXT: v_readlane_b32 s14, v22, 12 +; SI-NEXT: v_readlane_b32 s14, v23, 12 ; SI-NEXT: s_and_b32 s12, s12, 0xff -; SI-NEXT: v_readlane_b32 s15, v22, 13 +; SI-NEXT: v_readlane_b32 s15, v23, 13 ; SI-NEXT: s_lshl_b32 s14, s14, 8 ; SI-NEXT: s_or_b32 s12, s12, s14 -; SI-NEXT: v_readlane_b32 s14, v22, 14 -; SI-NEXT: v_readlane_b32 s15, v22, 15 +; SI-NEXT: v_readlane_b32 s14, v23, 14 +; SI-NEXT: v_readlane_b32 s15, v23, 15 ; SI-NEXT: s_and_b32 s14, s14, 0xff -; SI-NEXT: v_readlane_b32 s16, v22, 16 +; SI-NEXT: v_readlane_b32 s16, v23, 16 ; SI-NEXT: s_lshl_b32 s14, s14, 16 ; SI-NEXT: s_lshl_b32 s15, s16, 24 ; SI-NEXT: s_and_b32 s12, s12, 0xffff @@ -8239,12 +8266,12 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s12 ; SI-NEXT: s_and_b32 s12, s13, 0xff -; SI-NEXT: v_readlane_b32 s13, v22, 55 +; SI-NEXT: v_readlane_b32 s13, v23, 55 ; SI-NEXT: s_lshl_b32 s13, s13, 8 ; SI-NEXT: s_or_b32 s12, s12, s13 -; SI-NEXT: v_readlane_b32 s13, v22, 54 +; SI-NEXT: v_readlane_b32 s13, v23, 54 ; SI-NEXT: s_and_b32 s13, s13, 0xff -; SI-NEXT: v_readlane_b32 s14, v22, 53 +; SI-NEXT: v_readlane_b32 s14, v23, 53 ; SI-NEXT: s_lshl_b32 s13, s13, 16 ; SI-NEXT: s_lshl_b32 s14, s14, 24 ; SI-NEXT: s_and_b32 s12, s12, 0xffff @@ -8254,15 +8281,15 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s12 -; SI-NEXT: v_readlane_b32 s12, v22, 18 +; SI-NEXT: v_readlane_b32 s12, v23, 18 ; SI-NEXT: s_and_b32 s10, s10, 0xff -; SI-NEXT: v_readlane_b32 s13, v22, 19 +; SI-NEXT: v_readlane_b32 s13, v23, 19 ; SI-NEXT: s_lshl_b32 s12, s12, 8 ; SI-NEXT: s_or_b32 s10, s10, s12 -; SI-NEXT: v_readlane_b32 s12, v22, 20 -; SI-NEXT: v_readlane_b32 s13, v22, 21 +; SI-NEXT: v_readlane_b32 s12, v23, 20 +; SI-NEXT: v_readlane_b32 s13, v23, 21 ; SI-NEXT: s_and_b32 s12, s12, 0xff -; SI-NEXT: v_readlane_b32 s14, v22, 22 +; SI-NEXT: v_readlane_b32 s14, v23, 22 ; SI-NEXT: s_lshl_b32 s12, s12, 16 ; SI-NEXT: s_lshl_b32 s13, s14, 24 ; SI-NEXT: s_and_b32 s10, s10, 0xffff @@ -8273,12 +8300,12 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s10 ; SI-NEXT: s_and_b32 s10, s11, 0xff -; SI-NEXT: v_readlane_b32 s11, v22, 52 +; SI-NEXT: v_readlane_b32 s11, v23, 52 ; SI-NEXT: s_lshl_b32 s11, s11, 8 ; SI-NEXT: s_or_b32 s10, s10, s11 -; SI-NEXT: v_readlane_b32 s11, v22, 51 +; SI-NEXT: v_readlane_b32 s11, v23, 51 ; SI-NEXT: s_and_b32 s11, s11, 0xff -; SI-NEXT: v_readlane_b32 s12, v22, 50 +; SI-NEXT: v_readlane_b32 s12, v23, 50 ; SI-NEXT: s_lshl_b32 s11, s11, 16 ; SI-NEXT: s_lshl_b32 s12, s12, 24 ; SI-NEXT: s_and_b32 s10, s10, 0xffff @@ -8288,15 +8315,15 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s10 -; SI-NEXT: v_readlane_b32 s10, v22, 24 +; SI-NEXT: v_readlane_b32 s10, v23, 24 ; SI-NEXT: s_and_b32 s8, s8, 0xff -; SI-NEXT: v_readlane_b32 s11, v22, 25 +; SI-NEXT: v_readlane_b32 s11, v23, 25 ; SI-NEXT: s_lshl_b32 s10, s10, 8 ; SI-NEXT: s_or_b32 s8, s8, s10 -; SI-NEXT: v_readlane_b32 s10, v22, 26 -; SI-NEXT: v_readlane_b32 s11, v22, 27 +; SI-NEXT: v_readlane_b32 s10, v23, 26 +; SI-NEXT: v_readlane_b32 s11, v23, 27 ; SI-NEXT: s_and_b32 s10, s10, 0xff -; SI-NEXT: v_readlane_b32 s12, v22, 28 +; SI-NEXT: v_readlane_b32 s12, v23, 28 ; SI-NEXT: s_lshl_b32 s10, s10, 16 ; SI-NEXT: s_lshl_b32 s11, s12, 24 ; SI-NEXT: s_and_b32 s8, s8, 0xffff @@ -8307,10 +8334,10 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s8 ; SI-NEXT: s_and_b32 s8, s9, 0xff -; SI-NEXT: v_readlane_b32 s9, v22, 49 +; SI-NEXT: v_readlane_b32 s9, v23, 49 ; SI-NEXT: s_lshl_b32 s9, s9, 8 ; SI-NEXT: s_or_b32 s8, s8, s9 -; SI-NEXT: v_readlane_b32 s9, v22, 48 +; SI-NEXT: v_readlane_b32 s9, v23, 48 ; SI-NEXT: s_and_b32 s9, s9, 0xff ; SI-NEXT: s_lshl_b32 s9, s9, 16 ; SI-NEXT: s_lshl_b32 s10, s50, 24 @@ -8321,15 +8348,15 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s8 -; SI-NEXT: v_readlane_b32 s8, v22, 30 +; SI-NEXT: v_readlane_b32 s8, v23, 30 ; SI-NEXT: s_and_b32 s6, s6, 0xff -; SI-NEXT: v_readlane_b32 s9, v22, 31 +; SI-NEXT: v_readlane_b32 s9, v23, 31 ; SI-NEXT: s_lshl_b32 s8, s8, 8 ; SI-NEXT: s_or_b32 s6, s6, s8 -; SI-NEXT: v_readlane_b32 s8, v22, 32 -; SI-NEXT: v_readlane_b32 s9, v22, 33 +; SI-NEXT: v_readlane_b32 s8, v23, 32 +; SI-NEXT: v_readlane_b32 s9, v23, 33 ; SI-NEXT: s_and_b32 s8, s8, 0xff -; SI-NEXT: v_readlane_b32 s10, v22, 34 +; SI-NEXT: v_readlane_b32 s10, v23, 34 ; SI-NEXT: s_lshl_b32 s8, s8, 16 ; SI-NEXT: s_lshl_b32 s9, s10, 24 ; SI-NEXT: s_and_b32 s6, s6, 0xffff @@ -8340,12 +8367,12 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s6 ; SI-NEXT: s_and_b32 s6, s7, 0xff -; SI-NEXT: v_readlane_b32 s7, v22, 47 +; SI-NEXT: v_readlane_b32 s7, v23, 47 ; SI-NEXT: s_lshl_b32 s7, s7, 8 ; SI-NEXT: s_or_b32 s6, s6, s7 -; SI-NEXT: v_readlane_b32 s7, v22, 46 +; SI-NEXT: v_readlane_b32 s7, v23, 46 ; SI-NEXT: s_and_b32 s7, s7, 0xff -; SI-NEXT: v_readlane_b32 s8, v22, 45 +; SI-NEXT: v_readlane_b32 s8, v23, 45 ; SI-NEXT: s_lshl_b32 s7, s7, 16 ; SI-NEXT: s_lshl_b32 s8, s8, 24 ; SI-NEXT: s_and_b32 s6, s6, 0xffff @@ -8355,15 +8382,15 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s6 -; SI-NEXT: v_readlane_b32 s6, v22, 36 +; SI-NEXT: v_readlane_b32 s6, v23, 36 ; SI-NEXT: s_and_b32 s4, s4, 0xff -; SI-NEXT: v_readlane_b32 s7, v22, 37 +; SI-NEXT: v_readlane_b32 s7, v23, 37 ; SI-NEXT: s_lshl_b32 s6, s6, 8 ; SI-NEXT: s_or_b32 s4, s4, s6 -; SI-NEXT: v_readlane_b32 s6, v22, 38 -; SI-NEXT: v_readlane_b32 s7, v22, 39 +; SI-NEXT: v_readlane_b32 s6, v23, 38 +; SI-NEXT: v_readlane_b32 s7, v23, 39 ; SI-NEXT: s_and_b32 s6, s6, 0xff -; SI-NEXT: v_readlane_b32 s8, v22, 40 +; SI-NEXT: v_readlane_b32 s8, v23, 40 ; SI-NEXT: s_lshl_b32 s6, s6, 16 ; SI-NEXT: s_lshl_b32 s7, s8, 24 ; SI-NEXT: s_and_b32 s4, s4, 0xffff @@ -8374,12 +8401,12 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s4 ; SI-NEXT: s_and_b32 s4, s5, 0xff -; SI-NEXT: v_readlane_b32 s5, v22, 44 +; SI-NEXT: v_readlane_b32 s5, v23, 44 ; SI-NEXT: s_lshl_b32 s5, s5, 8 ; SI-NEXT: s_or_b32 s4, s4, s5 -; SI-NEXT: v_readlane_b32 s5, v22, 43 +; SI-NEXT: v_readlane_b32 s5, v23, 43 ; SI-NEXT: s_and_b32 s5, s5, 0xff -; SI-NEXT: v_readlane_b32 s6, v22, 42 +; SI-NEXT: v_readlane_b32 s6, v23, 42 ; SI-NEXT: s_lshl_b32 s5, s5, 16 ; SI-NEXT: s_lshl_b32 s6, s6, 24 ; SI-NEXT: s_and_b32 s4, s4, 0xffff @@ -8389,206 +8416,207 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 -; SI-NEXT: v_readlane_b32 s19, v22, 11 -; SI-NEXT: v_readlane_b32 s17, v22, 17 -; SI-NEXT: v_readlane_b32 s15, v22, 23 -; SI-NEXT: v_readlane_b32 s13, v22, 29 -; SI-NEXT: v_readlane_b32 s11, v22, 35 -; SI-NEXT: v_readlane_b32 s9, v22, 41 +; SI-NEXT: v_readlane_b32 s21, v23, 5 +; SI-NEXT: v_readlane_b32 s19, v23, 11 +; SI-NEXT: v_readlane_b32 s17, v23, 17 +; SI-NEXT: v_readlane_b32 s15, v23, 23 +; SI-NEXT: v_readlane_b32 s13, v23, 29 +; SI-NEXT: v_readlane_b32 s11, v23, 35 +; SI-NEXT: v_readlane_b32 s9, v23, 41 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s99, v20, 35 -; SI-NEXT: v_readlane_b32 s98, v20, 34 -; SI-NEXT: v_readlane_b32 s97, v20, 33 -; SI-NEXT: v_readlane_b32 s96, v20, 32 -; SI-NEXT: v_readlane_b32 s87, v20, 31 -; SI-NEXT: v_readlane_b32 s86, v20, 30 -; SI-NEXT: v_readlane_b32 s85, v20, 29 -; SI-NEXT: v_readlane_b32 s84, v20, 28 -; SI-NEXT: v_readlane_b32 s83, v20, 27 -; SI-NEXT: v_readlane_b32 s82, v20, 26 -; SI-NEXT: v_readlane_b32 s81, v20, 25 -; SI-NEXT: v_readlane_b32 s80, v20, 24 -; SI-NEXT: v_readlane_b32 s71, v20, 23 -; SI-NEXT: v_readlane_b32 s70, v20, 22 -; SI-NEXT: v_readlane_b32 s69, v20, 21 -; SI-NEXT: v_readlane_b32 s68, v20, 20 -; SI-NEXT: v_readlane_b32 s67, v20, 19 -; SI-NEXT: v_readlane_b32 s66, v20, 18 -; SI-NEXT: v_readlane_b32 s65, v20, 17 -; SI-NEXT: v_readlane_b32 s64, v20, 16 -; SI-NEXT: v_readlane_b32 s55, v20, 15 -; SI-NEXT: v_readlane_b32 s54, v20, 14 -; SI-NEXT: v_readlane_b32 s53, v20, 13 -; SI-NEXT: v_readlane_b32 s52, v20, 12 -; SI-NEXT: v_readlane_b32 s51, v20, 11 -; SI-NEXT: v_readlane_b32 s50, v20, 10 -; SI-NEXT: v_readlane_b32 s49, v20, 9 -; SI-NEXT: v_readlane_b32 s48, v20, 8 -; SI-NEXT: v_readlane_b32 s39, v20, 7 -; SI-NEXT: v_readlane_b32 s38, v20, 6 -; SI-NEXT: v_readlane_b32 s37, v20, 5 -; SI-NEXT: v_readlane_b32 s36, v20, 4 -; SI-NEXT: v_readlane_b32 s35, v20, 3 -; SI-NEXT: v_readlane_b32 s34, v20, 2 -; SI-NEXT: v_readlane_b32 s31, v20, 1 -; SI-NEXT: v_readlane_b32 s30, v20, 0 +; SI-NEXT: v_readlane_b32 s99, v21, 35 +; SI-NEXT: v_readlane_b32 s98, v21, 34 +; SI-NEXT: v_readlane_b32 s97, v21, 33 +; SI-NEXT: v_readlane_b32 s96, v21, 32 +; SI-NEXT: v_readlane_b32 s87, v21, 31 +; SI-NEXT: v_readlane_b32 s86, v21, 30 +; SI-NEXT: v_readlane_b32 s85, v21, 29 +; SI-NEXT: v_readlane_b32 s84, v21, 28 +; SI-NEXT: v_readlane_b32 s83, v21, 27 +; SI-NEXT: v_readlane_b32 s82, v21, 26 +; SI-NEXT: v_readlane_b32 s81, v21, 25 +; SI-NEXT: v_readlane_b32 s80, v21, 24 +; SI-NEXT: v_readlane_b32 s71, v21, 23 +; SI-NEXT: v_readlane_b32 s70, v21, 22 +; SI-NEXT: v_readlane_b32 s69, v21, 21 +; SI-NEXT: v_readlane_b32 s68, v21, 20 +; SI-NEXT: v_readlane_b32 s67, v21, 19 +; SI-NEXT: v_readlane_b32 s66, v21, 18 +; SI-NEXT: v_readlane_b32 s65, v21, 17 +; SI-NEXT: v_readlane_b32 s64, v21, 16 +; SI-NEXT: v_readlane_b32 s55, v21, 15 +; SI-NEXT: v_readlane_b32 s54, v21, 14 +; SI-NEXT: v_readlane_b32 s53, v21, 13 +; SI-NEXT: v_readlane_b32 s52, v21, 12 +; SI-NEXT: v_readlane_b32 s51, v21, 11 +; SI-NEXT: v_readlane_b32 s50, v21, 10 +; SI-NEXT: v_readlane_b32 s49, v21, 9 +; SI-NEXT: v_readlane_b32 s48, v21, 8 +; SI-NEXT: v_readlane_b32 s39, v21, 7 +; SI-NEXT: v_readlane_b32 s38, v21, 6 +; SI-NEXT: v_readlane_b32 s37, v21, 5 +; SI-NEXT: v_readlane_b32 s36, v21, 4 +; SI-NEXT: v_readlane_b32 s35, v21, 3 +; SI-NEXT: v_readlane_b32 s34, v21, 2 +; SI-NEXT: v_readlane_b32 s31, v21, 1 +; SI-NEXT: v_readlane_b32 s30, v21, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] ; SI-NEXT: .LBB13_4: ; SI-NEXT: ; implicit-def: $sgpr51 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v22, s50, 0 -; SI-NEXT: v_writelane_b32 v22, s51, 1 +; SI-NEXT: v_writelane_b32 v23, s50, 0 +; SI-NEXT: v_writelane_b32 v23, s51, 1 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s50, 2 -; SI-NEXT: v_writelane_b32 v22, s51, 3 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s50, 2 +; SI-NEXT: v_writelane_b32 v23, s51, 3 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s50, 4 -; SI-NEXT: v_writelane_b32 v22, s51, 5 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s50, 4 +; SI-NEXT: v_writelane_b32 v23, s51, 5 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s50, 6 -; SI-NEXT: v_writelane_b32 v22, s51, 7 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s50, 6 +; SI-NEXT: v_writelane_b32 v23, s51, 7 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s50, 8 -; SI-NEXT: v_writelane_b32 v22, s51, 9 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s50, 8 +; SI-NEXT: v_writelane_b32 v23, s51, 9 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s50, 10 -; SI-NEXT: v_writelane_b32 v22, s51, 11 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s50, 10 +; SI-NEXT: v_writelane_b32 v23, s51, 11 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s50, 12 -; SI-NEXT: v_writelane_b32 v22, s51, 13 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s50, 12 +; SI-NEXT: v_writelane_b32 v23, s51, 13 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s50, 14 -; SI-NEXT: v_writelane_b32 v22, s51, 15 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s50, 14 +; SI-NEXT: v_writelane_b32 v23, s51, 15 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s50, 16 -; SI-NEXT: v_writelane_b32 v22, s51, 17 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s50, 16 +; SI-NEXT: v_writelane_b32 v23, s51, 17 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s50, 18 -; SI-NEXT: v_writelane_b32 v22, s51, 19 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s50, 18 +; SI-NEXT: v_writelane_b32 v23, s51, 19 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s50, 20 -; SI-NEXT: v_writelane_b32 v22, s51, 21 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s50, 20 +; SI-NEXT: v_writelane_b32 v23, s51, 21 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s50, 22 -; SI-NEXT: v_writelane_b32 v22, s51, 23 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s50, 22 +; SI-NEXT: v_writelane_b32 v23, s51, 23 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s50, 24 -; SI-NEXT: v_writelane_b32 v22, s51, 25 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s50, 24 +; SI-NEXT: v_writelane_b32 v23, s51, 25 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s50, 26 -; SI-NEXT: v_writelane_b32 v22, s51, 27 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s50, 26 +; SI-NEXT: v_writelane_b32 v23, s51, 27 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s50, 28 -; SI-NEXT: v_writelane_b32 v22, s51, 29 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s50, 28 +; SI-NEXT: v_writelane_b32 v23, s51, 29 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s50, 30 -; SI-NEXT: v_writelane_b32 v22, s51, 31 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s50, 30 +; SI-NEXT: v_writelane_b32 v23, s51, 31 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s50, 32 -; SI-NEXT: v_writelane_b32 v22, s51, 33 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s50, 32 +; SI-NEXT: v_writelane_b32 v23, s51, 33 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s50, 34 -; SI-NEXT: v_writelane_b32 v22, s51, 35 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s50, 34 +; SI-NEXT: v_writelane_b32 v23, s51, 35 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s50, 36 -; SI-NEXT: v_writelane_b32 v22, s51, 37 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s50, 36 +; SI-NEXT: v_writelane_b32 v23, s51, 37 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s50, 38 -; SI-NEXT: v_writelane_b32 v22, s51, 39 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s50, 38 +; SI-NEXT: v_writelane_b32 v23, s51, 39 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr49 ; SI-NEXT: ; implicit-def: $sgpr55 ; SI-NEXT: ; implicit-def: $sgpr54 ; SI-NEXT: ; implicit-def: $sgpr53 ; SI-NEXT: ; implicit-def: $sgpr52 ; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; kill: killed $sgpr46 +; SI-NEXT: ; kill: killed $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr38 ; SI-NEXT: ; implicit-def: $sgpr36 ; SI-NEXT: ; implicit-def: $sgpr34 @@ -8604,9 +8632,9 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: ; implicit-def: $sgpr62 ; SI-NEXT: ; implicit-def: $sgpr60 ; SI-NEXT: ; implicit-def: $sgpr58 -; SI-NEXT: ; implicit-def: $sgpr56 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s50, 40 +; SI-NEXT: ; implicit-def: $sgpr28 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s50, 40 ; SI-NEXT: ; implicit-def: $sgpr98 ; SI-NEXT: ; implicit-def: $sgpr96 ; SI-NEXT: ; implicit-def: $sgpr86 @@ -8617,7 +8645,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: ; implicit-def: $sgpr68 ; SI-NEXT: ; implicit-def: $sgpr66 ; SI-NEXT: ; implicit-def: $sgpr64 -; SI-NEXT: v_writelane_b32 v22, s51, 41 +; SI-NEXT: v_writelane_b32 v23, s51, 41 ; SI-NEXT: ; implicit-def: $sgpr50 ; SI-NEXT: s_branch .LBB13_2 ; @@ -8625,47 +8653,75 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v20, s30, 0 -; VI-NEXT: v_writelane_b32 v20, s31, 1 -; VI-NEXT: v_writelane_b32 v20, s34, 2 -; VI-NEXT: v_writelane_b32 v20, s35, 3 -; VI-NEXT: v_writelane_b32 v20, s36, 4 -; VI-NEXT: v_writelane_b32 v20, s37, 5 -; VI-NEXT: v_writelane_b32 v20, s38, 6 -; VI-NEXT: v_writelane_b32 v20, s39, 7 -; VI-NEXT: v_writelane_b32 v20, s48, 8 -; VI-NEXT: v_writelane_b32 v20, s49, 9 -; VI-NEXT: v_writelane_b32 v20, s50, 10 -; VI-NEXT: v_writelane_b32 v20, s51, 11 -; VI-NEXT: v_writelane_b32 v20, s52, 12 -; VI-NEXT: v_writelane_b32 v20, s53, 13 -; VI-NEXT: v_writelane_b32 v20, s54, 14 -; VI-NEXT: v_writelane_b32 v20, s55, 15 -; VI-NEXT: v_writelane_b32 v20, s64, 16 -; VI-NEXT: v_writelane_b32 v20, s65, 17 -; VI-NEXT: v_writelane_b32 v20, s66, 18 -; VI-NEXT: v_writelane_b32 v20, s67, 19 -; VI-NEXT: v_writelane_b32 v20, s68, 20 -; VI-NEXT: v_writelane_b32 v20, s69, 21 -; VI-NEXT: v_writelane_b32 v20, s70, 22 -; VI-NEXT: v_writelane_b32 v20, s71, 23 -; VI-NEXT: v_writelane_b32 v20, s80, 24 -; VI-NEXT: v_writelane_b32 v20, s81, 25 -; VI-NEXT: v_writelane_b32 v20, s82, 26 -; VI-NEXT: v_writelane_b32 v20, s83, 27 -; VI-NEXT: v_writelane_b32 v20, s84, 28 -; VI-NEXT: v_writelane_b32 v20, s85, 29 +; VI-NEXT: v_writelane_b32 v21, s30, 0 +; VI-NEXT: v_writelane_b32 v21, s31, 1 +; VI-NEXT: v_writelane_b32 v21, s34, 2 +; VI-NEXT: v_writelane_b32 v21, s35, 3 +; VI-NEXT: v_writelane_b32 v21, s36, 4 +; VI-NEXT: v_writelane_b32 v21, s37, 5 +; VI-NEXT: v_writelane_b32 v21, s38, 6 +; VI-NEXT: v_writelane_b32 v21, s39, 7 +; VI-NEXT: v_writelane_b32 v21, s48, 8 +; VI-NEXT: v_writelane_b32 v21, s49, 9 +; VI-NEXT: v_writelane_b32 v21, s50, 10 +; VI-NEXT: v_writelane_b32 v21, s51, 11 +; VI-NEXT: v_writelane_b32 v21, s52, 12 +; VI-NEXT: v_writelane_b32 v21, s53, 13 +; VI-NEXT: v_writelane_b32 v21, s54, 14 +; VI-NEXT: v_writelane_b32 v21, s55, 15 +; VI-NEXT: v_writelane_b32 v21, s64, 16 +; VI-NEXT: v_mov_b32_e32 v20, s16 +; VI-NEXT: v_writelane_b32 v21, s65, 17 +; VI-NEXT: v_readfirstlane_b32 s56, v20 +; VI-NEXT: v_mov_b32_e32 v20, s17 +; VI-NEXT: v_writelane_b32 v21, s66, 18 +; VI-NEXT: v_readfirstlane_b32 s57, v20 +; VI-NEXT: v_mov_b32_e32 v20, s18 +; VI-NEXT: v_writelane_b32 v21, s67, 19 +; VI-NEXT: v_readfirstlane_b32 s46, v20 +; VI-NEXT: v_mov_b32_e32 v20, s19 +; VI-NEXT: v_writelane_b32 v21, s68, 20 +; VI-NEXT: v_readfirstlane_b32 s47, v20 +; VI-NEXT: v_mov_b32_e32 v20, s20 +; VI-NEXT: v_writelane_b32 v21, s69, 21 +; VI-NEXT: v_readfirstlane_b32 s44, v20 +; VI-NEXT: v_mov_b32_e32 v20, s21 +; VI-NEXT: v_writelane_b32 v21, s70, 22 +; VI-NEXT: v_readfirstlane_b32 s45, v20 +; VI-NEXT: v_mov_b32_e32 v20, s22 +; VI-NEXT: v_writelane_b32 v21, s71, 23 +; VI-NEXT: v_readfirstlane_b32 s42, v20 +; VI-NEXT: v_mov_b32_e32 v20, s23 +; VI-NEXT: v_writelane_b32 v21, s80, 24 +; VI-NEXT: v_readfirstlane_b32 s43, v20 +; VI-NEXT: v_mov_b32_e32 v20, s24 +; VI-NEXT: v_writelane_b32 v21, s81, 25 +; VI-NEXT: v_readfirstlane_b32 s40, v20 +; VI-NEXT: v_mov_b32_e32 v20, s25 +; VI-NEXT: v_writelane_b32 v21, s82, 26 +; VI-NEXT: v_readfirstlane_b32 s41, v20 +; VI-NEXT: v_mov_b32_e32 v20, s26 +; VI-NEXT: v_writelane_b32 v21, s83, 27 +; VI-NEXT: v_readfirstlane_b32 s24, v20 +; VI-NEXT: v_mov_b32_e32 v20, s27 +; VI-NEXT: v_writelane_b32 v21, s84, 28 +; VI-NEXT: v_readfirstlane_b32 s25, v20 +; VI-NEXT: v_mov_b32_e32 v20, s28 +; VI-NEXT: v_writelane_b32 v21, s85, 29 +; VI-NEXT: v_readfirstlane_b32 s22, v20 +; VI-NEXT: v_mov_b32_e32 v20, s29 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; VI-NEXT: v_writelane_b32 v20, s86, 30 -; VI-NEXT: v_readfirstlane_b32 s44, v1 -; VI-NEXT: v_readfirstlane_b32 s45, v2 -; VI-NEXT: v_readfirstlane_b32 s42, v3 -; VI-NEXT: v_readfirstlane_b32 s43, v4 -; VI-NEXT: v_readfirstlane_b32 s40, v5 -; VI-NEXT: v_readfirstlane_b32 s41, v6 +; VI-NEXT: v_writelane_b32 v21, s86, 30 +; VI-NEXT: v_readfirstlane_b32 s23, v20 +; VI-NEXT: v_readfirstlane_b32 s20, v1 +; VI-NEXT: v_readfirstlane_b32 s21, v2 +; VI-NEXT: v_readfirstlane_b32 s18, v3 +; VI-NEXT: v_readfirstlane_b32 s19, v4 +; VI-NEXT: v_readfirstlane_b32 s16, v5 +; VI-NEXT: v_readfirstlane_b32 s17, v6 ; VI-NEXT: v_readfirstlane_b32 s14, v7 ; VI-NEXT: v_readfirstlane_b32 s15, v8 ; VI-NEXT: v_readfirstlane_b32 s12, v9 @@ -8677,609 +8733,609 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; VI-NEXT: v_readfirstlane_b32 s6, v15 ; VI-NEXT: v_readfirstlane_b32 s7, v16 ; VI-NEXT: v_readfirstlane_b32 s4, v17 -; VI-NEXT: s_and_b64 s[46:47], vcc, exec +; VI-NEXT: s_and_b64 s[26:27], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s5, v18 -; VI-NEXT: v_writelane_b32 v20, s87, 31 -; VI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane +; VI-NEXT: v_writelane_b32 v21, s87, 31 +; VI-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane ; VI-NEXT: s_cbranch_scc0 .LBB13_4 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_lshr_b32 s46, s5, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 8 -; VI-NEXT: s_lshr_b32 s46, s5, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 9 -; VI-NEXT: s_lshr_b32 s46, s5, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 10 -; VI-NEXT: s_lshr_b32 s46, s4, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 11 -; VI-NEXT: s_lshr_b32 s46, s4, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 12 -; VI-NEXT: s_lshr_b32 s46, s7, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 13 -; VI-NEXT: s_lshr_b32 s46, s7, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 14 -; VI-NEXT: s_lshr_b32 s46, s7, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 15 -; VI-NEXT: s_lshr_b32 s46, s6, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 16 -; VI-NEXT: s_lshr_b32 s46, s6, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 17 -; VI-NEXT: s_lshr_b32 s46, s9, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 18 -; VI-NEXT: s_lshr_b32 s46, s9, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 19 -; VI-NEXT: s_lshr_b32 s46, s9, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 20 -; VI-NEXT: s_lshr_b32 s46, s8, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 21 -; VI-NEXT: s_lshr_b32 s46, s8, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 22 -; VI-NEXT: s_lshr_b32 s46, s11, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 23 -; VI-NEXT: s_lshr_b32 s46, s11, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 24 -; VI-NEXT: s_lshr_b32 s46, s11, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 25 -; VI-NEXT: s_lshr_b32 s46, s10, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 26 -; VI-NEXT: s_lshr_b32 s46, s10, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 27 -; VI-NEXT: s_lshr_b32 s46, s13, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 28 -; VI-NEXT: s_lshr_b32 s46, s13, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 29 -; VI-NEXT: s_lshr_b32 s46, s13, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 30 -; VI-NEXT: s_lshr_b32 s46, s12, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 31 -; VI-NEXT: s_lshr_b32 s46, s12, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 32 -; VI-NEXT: s_lshr_b32 s46, s15, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 33 -; VI-NEXT: s_lshr_b32 s46, s15, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 34 -; VI-NEXT: s_lshr_b32 s46, s15, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 35 -; VI-NEXT: s_lshr_b32 s46, s14, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 36 -; VI-NEXT: s_lshr_b32 s46, s14, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 37 -; VI-NEXT: s_lshr_b32 s46, s41, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 38 -; VI-NEXT: s_lshr_b32 s46, s41, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 39 -; VI-NEXT: s_lshr_b32 s46, s41, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 40 -; VI-NEXT: s_lshr_b32 s46, s40, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 41 -; VI-NEXT: s_lshr_b32 s46, s40, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 42 -; VI-NEXT: s_lshr_b32 s46, s43, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 43 -; VI-NEXT: s_lshr_b32 s46, s43, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 44 -; VI-NEXT: s_lshr_b32 s46, s43, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 45 -; VI-NEXT: s_lshr_b32 s46, s42, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 46 -; VI-NEXT: s_lshr_b32 s46, s42, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 47 -; VI-NEXT: s_lshr_b32 s46, s45, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 48 -; VI-NEXT: s_lshr_b32 s46, s45, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 49 -; VI-NEXT: s_lshr_b32 s46, s45, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 50 -; VI-NEXT: s_lshr_b32 s46, s44, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 51 -; VI-NEXT: s_lshr_b32 s46, s44, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 52 -; VI-NEXT: s_lshr_b32 s46, s29, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 53 -; VI-NEXT: s_lshr_b32 s46, s29, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 54 -; VI-NEXT: s_lshr_b32 s46, s29, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 55 -; VI-NEXT: s_lshr_b32 s46, s28, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 56 -; VI-NEXT: s_lshr_b32 s46, s28, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 57 -; VI-NEXT: s_lshr_b32 s46, s27, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 58 -; VI-NEXT: s_lshr_b32 s46, s27, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 59 +; VI-NEXT: s_lshr_b32 s26, s5, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 8 +; VI-NEXT: s_lshr_b32 s26, s5, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 9 +; VI-NEXT: s_lshr_b32 s26, s5, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 10 +; VI-NEXT: s_lshr_b32 s26, s4, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 11 +; VI-NEXT: s_lshr_b32 s26, s4, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 12 +; VI-NEXT: s_lshr_b32 s26, s7, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 13 +; VI-NEXT: s_lshr_b32 s26, s7, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 14 +; VI-NEXT: s_lshr_b32 s26, s7, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 15 +; VI-NEXT: s_lshr_b32 s26, s6, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 16 +; VI-NEXT: s_lshr_b32 s26, s6, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 17 +; VI-NEXT: s_lshr_b32 s26, s9, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 18 +; VI-NEXT: s_lshr_b32 s26, s9, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 19 +; VI-NEXT: s_lshr_b32 s26, s9, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 20 +; VI-NEXT: s_lshr_b32 s26, s8, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 21 +; VI-NEXT: s_lshr_b32 s26, s8, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 22 +; VI-NEXT: s_lshr_b32 s26, s11, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 23 +; VI-NEXT: s_lshr_b32 s26, s11, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 24 +; VI-NEXT: s_lshr_b32 s26, s11, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 25 +; VI-NEXT: s_lshr_b32 s26, s10, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 26 +; VI-NEXT: s_lshr_b32 s26, s10, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 27 +; VI-NEXT: s_lshr_b32 s26, s13, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 28 +; VI-NEXT: s_lshr_b32 s26, s13, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 29 +; VI-NEXT: s_lshr_b32 s26, s13, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 30 +; VI-NEXT: s_lshr_b32 s26, s12, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 31 +; VI-NEXT: s_lshr_b32 s26, s12, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 32 +; VI-NEXT: s_lshr_b32 s26, s15, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 33 +; VI-NEXT: s_lshr_b32 s26, s15, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 34 +; VI-NEXT: s_lshr_b32 s26, s15, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 35 +; VI-NEXT: s_lshr_b32 s26, s14, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 36 +; VI-NEXT: s_lshr_b32 s26, s14, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 37 +; VI-NEXT: s_lshr_b32 s26, s17, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 38 +; VI-NEXT: s_lshr_b32 s26, s17, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 39 +; VI-NEXT: s_lshr_b32 s26, s17, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 40 +; VI-NEXT: s_lshr_b32 s26, s16, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 41 +; VI-NEXT: s_lshr_b32 s26, s16, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 42 +; VI-NEXT: s_lshr_b32 s26, s19, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 43 +; VI-NEXT: s_lshr_b32 s26, s19, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 44 +; VI-NEXT: s_lshr_b32 s26, s19, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 45 +; VI-NEXT: s_lshr_b32 s26, s18, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 46 +; VI-NEXT: s_lshr_b32 s26, s18, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 47 +; VI-NEXT: s_lshr_b32 s26, s21, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 48 +; VI-NEXT: s_lshr_b32 s26, s21, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 49 +; VI-NEXT: s_lshr_b32 s26, s21, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 50 +; VI-NEXT: s_lshr_b32 s26, s20, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 51 +; VI-NEXT: s_lshr_b32 s26, s20, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 52 +; VI-NEXT: s_lshr_b32 s26, s23, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 53 +; VI-NEXT: s_lshr_b32 s26, s23, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 54 +; VI-NEXT: s_lshr_b32 s26, s23, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 55 +; VI-NEXT: s_lshr_b32 s26, s22, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 56 +; VI-NEXT: s_lshr_b32 s26, s22, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 57 +; VI-NEXT: s_lshr_b32 s26, s25, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 58 +; VI-NEXT: s_lshr_b32 s26, s25, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 59 ; VI-NEXT: s_lshr_b64 s[60:61], s[4:5], 24 -; VI-NEXT: v_writelane_b32 v21, s60, 6 -; VI-NEXT: v_writelane_b32 v21, s61, 7 +; VI-NEXT: v_writelane_b32 v22, s60, 6 +; VI-NEXT: v_writelane_b32 v22, s61, 7 ; VI-NEXT: s_lshr_b64 s[60:61], s[6:7], 24 -; VI-NEXT: v_writelane_b32 v21, s60, 4 -; VI-NEXT: v_writelane_b32 v21, s61, 5 +; VI-NEXT: v_writelane_b32 v22, s60, 4 +; VI-NEXT: v_writelane_b32 v22, s61, 5 ; VI-NEXT: s_lshr_b64 s[60:61], s[8:9], 24 -; VI-NEXT: v_writelane_b32 v21, s60, 2 -; VI-NEXT: v_writelane_b32 v21, s61, 3 +; VI-NEXT: v_writelane_b32 v22, s60, 2 +; VI-NEXT: v_writelane_b32 v22, s61, 3 ; VI-NEXT: s_lshr_b64 s[60:61], s[10:11], 24 -; VI-NEXT: v_writelane_b32 v21, s60, 0 -; VI-NEXT: s_lshr_b32 s66, s27, 8 -; VI-NEXT: s_lshr_b32 s67, s26, 16 -; VI-NEXT: s_lshr_b32 s68, s26, 8 -; VI-NEXT: s_lshr_b32 s69, s25, 24 -; VI-NEXT: s_lshr_b32 s70, s25, 16 -; VI-NEXT: s_lshr_b32 s71, s25, 8 -; VI-NEXT: s_lshr_b32 s80, s24, 16 -; VI-NEXT: s_lshr_b32 s81, s24, 8 -; VI-NEXT: s_lshr_b32 s82, s23, 24 -; VI-NEXT: s_lshr_b32 s83, s23, 16 -; VI-NEXT: s_lshr_b32 s84, s23, 8 -; VI-NEXT: s_lshr_b32 s85, s22, 16 -; VI-NEXT: s_lshr_b32 s86, s22, 8 -; VI-NEXT: s_lshr_b32 s87, s21, 24 -; VI-NEXT: s_lshr_b32 s50, s21, 16 -; VI-NEXT: s_lshr_b32 s46, s21, 8 -; VI-NEXT: s_lshr_b32 s47, s20, 16 -; VI-NEXT: s_lshr_b32 s56, s20, 8 -; VI-NEXT: s_lshr_b32 s57, s19, 24 -; VI-NEXT: s_lshr_b32 s51, s19, 16 -; VI-NEXT: s_lshr_b32 s52, s19, 8 -; VI-NEXT: s_lshr_b32 s53, s18, 16 -; VI-NEXT: s_lshr_b32 s54, s18, 8 -; VI-NEXT: s_lshr_b32 s58, s17, 24 -; VI-NEXT: s_lshr_b32 s59, s17, 16 -; VI-NEXT: s_lshr_b32 s55, s17, 8 -; VI-NEXT: s_lshr_b32 s64, s16, 16 -; VI-NEXT: s_lshr_b32 s65, s16, 8 -; VI-NEXT: v_writelane_b32 v21, s61, 1 +; VI-NEXT: v_writelane_b32 v22, s60, 0 +; VI-NEXT: s_lshr_b32 s66, s25, 8 +; VI-NEXT: s_lshr_b32 s67, s24, 16 +; VI-NEXT: s_lshr_b32 s68, s24, 8 +; VI-NEXT: s_lshr_b32 s69, s41, 24 +; VI-NEXT: s_lshr_b32 s70, s41, 16 +; VI-NEXT: s_lshr_b32 s71, s41, 8 +; VI-NEXT: s_lshr_b32 s80, s40, 16 +; VI-NEXT: s_lshr_b32 s81, s40, 8 +; VI-NEXT: s_lshr_b32 s82, s43, 24 +; VI-NEXT: s_lshr_b32 s83, s43, 16 +; VI-NEXT: s_lshr_b32 s84, s43, 8 +; VI-NEXT: s_lshr_b32 s85, s42, 16 +; VI-NEXT: s_lshr_b32 s86, s42, 8 +; VI-NEXT: s_lshr_b32 s87, s45, 24 +; VI-NEXT: s_lshr_b32 s50, s45, 16 +; VI-NEXT: s_lshr_b32 s26, s45, 8 +; VI-NEXT: s_lshr_b32 s27, s44, 16 +; VI-NEXT: s_lshr_b32 s28, s44, 8 +; VI-NEXT: s_lshr_b32 s29, s47, 24 +; VI-NEXT: s_lshr_b32 s51, s47, 16 +; VI-NEXT: s_lshr_b32 s52, s47, 8 +; VI-NEXT: s_lshr_b32 s53, s46, 16 +; VI-NEXT: s_lshr_b32 s54, s46, 8 +; VI-NEXT: s_lshr_b32 s58, s57, 24 +; VI-NEXT: s_lshr_b32 s59, s57, 16 +; VI-NEXT: s_lshr_b32 s55, s57, 8 +; VI-NEXT: s_lshr_b32 s64, s56, 16 +; VI-NEXT: s_lshr_b32 s65, s56, 8 +; VI-NEXT: v_writelane_b32 v22, s61, 1 ; VI-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 ; VI-NEXT: s_lshr_b64 s[72:73], s[14:15], 24 -; VI-NEXT: s_lshr_b64 s[74:75], s[40:41], 24 -; VI-NEXT: s_lshr_b64 s[76:77], s[42:43], 24 -; VI-NEXT: s_lshr_b64 s[78:79], s[44:45], 24 -; VI-NEXT: s_lshr_b64 s[88:89], s[28:29], 24 -; VI-NEXT: s_lshr_b64 s[90:91], s[26:27], 24 -; VI-NEXT: s_lshr_b64 s[30:31], s[24:25], 24 -; VI-NEXT: s_lshr_b64 s[34:35], s[22:23], 24 -; VI-NEXT: s_lshr_b64 s[36:37], s[20:21], 24 -; VI-NEXT: s_lshr_b64 s[38:39], s[18:19], 24 -; VI-NEXT: s_lshr_b64 s[48:49], s[16:17], 24 +; VI-NEXT: s_lshr_b64 s[74:75], s[16:17], 24 +; VI-NEXT: s_lshr_b64 s[76:77], s[18:19], 24 +; VI-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 +; VI-NEXT: s_lshr_b64 s[88:89], s[22:23], 24 +; VI-NEXT: s_lshr_b64 s[90:91], s[24:25], 24 +; VI-NEXT: s_lshr_b64 s[30:31], s[40:41], 24 +; VI-NEXT: s_lshr_b64 s[34:35], s[42:43], 24 +; VI-NEXT: s_lshr_b64 s[36:37], s[44:45], 24 +; VI-NEXT: s_lshr_b64 s[38:39], s[46:47], 24 +; VI-NEXT: s_lshr_b64 s[48:49], s[56:57], 24 ; VI-NEXT: s_cbranch_execnz .LBB13_3 ; VI-NEXT: .LBB13_2: ; %cmp.true ; VI-NEXT: s_add_i32 s5, s5, 3 -; VI-NEXT: s_lshr_b32 s46, s5, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 8 -; VI-NEXT: s_lshr_b32 s46, s5, 16 +; VI-NEXT: s_lshr_b32 s26, s5, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 8 +; VI-NEXT: s_lshr_b32 s26, s5, 16 ; VI-NEXT: s_add_i32 s4, s4, 3 -; VI-NEXT: v_writelane_b32 v21, s46, 9 -; VI-NEXT: s_lshr_b32 s46, s5, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 10 -; VI-NEXT: s_lshr_b32 s46, s4, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 9 +; VI-NEXT: s_lshr_b32 s26, s5, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 10 +; VI-NEXT: s_lshr_b32 s26, s4, 16 ; VI-NEXT: s_add_i32 s7, s7, 3 -; VI-NEXT: v_writelane_b32 v21, s46, 11 -; VI-NEXT: s_lshr_b32 s46, s4, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 12 -; VI-NEXT: s_lshr_b32 s46, s7, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 13 -; VI-NEXT: s_lshr_b32 s46, s7, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 11 +; VI-NEXT: s_lshr_b32 s26, s4, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 12 +; VI-NEXT: s_lshr_b32 s26, s7, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 13 +; VI-NEXT: s_lshr_b32 s26, s7, 16 ; VI-NEXT: s_add_i32 s6, s6, 3 -; VI-NEXT: v_writelane_b32 v21, s46, 14 -; VI-NEXT: s_lshr_b32 s46, s7, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 15 -; VI-NEXT: s_lshr_b32 s46, s6, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 14 +; VI-NEXT: s_lshr_b32 s26, s7, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 15 +; VI-NEXT: s_lshr_b32 s26, s6, 16 ; VI-NEXT: s_add_i32 s9, s9, 3 -; VI-NEXT: v_writelane_b32 v21, s46, 16 -; VI-NEXT: s_lshr_b32 s46, s6, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 17 -; VI-NEXT: s_lshr_b32 s46, s9, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 18 -; VI-NEXT: s_lshr_b32 s46, s9, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 16 +; VI-NEXT: s_lshr_b32 s26, s6, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 17 +; VI-NEXT: s_lshr_b32 s26, s9, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 18 +; VI-NEXT: s_lshr_b32 s26, s9, 16 ; VI-NEXT: s_add_i32 s8, s8, 3 -; VI-NEXT: v_writelane_b32 v21, s46, 19 -; VI-NEXT: s_lshr_b32 s46, s9, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 20 -; VI-NEXT: s_lshr_b32 s46, s8, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 19 +; VI-NEXT: s_lshr_b32 s26, s9, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 20 +; VI-NEXT: s_lshr_b32 s26, s8, 16 ; VI-NEXT: s_add_i32 s11, s11, 3 -; VI-NEXT: v_writelane_b32 v21, s46, 21 -; VI-NEXT: s_lshr_b32 s46, s8, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 22 -; VI-NEXT: s_lshr_b32 s46, s11, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 23 -; VI-NEXT: s_lshr_b32 s46, s11, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 21 +; VI-NEXT: s_lshr_b32 s26, s8, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 22 +; VI-NEXT: s_lshr_b32 s26, s11, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 23 +; VI-NEXT: s_lshr_b32 s26, s11, 16 ; VI-NEXT: s_add_i32 s10, s10, 3 -; VI-NEXT: v_writelane_b32 v21, s46, 24 -; VI-NEXT: s_lshr_b32 s46, s11, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 25 -; VI-NEXT: s_lshr_b32 s46, s10, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 24 +; VI-NEXT: s_lshr_b32 s26, s11, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 25 +; VI-NEXT: s_lshr_b32 s26, s10, 16 ; VI-NEXT: s_add_i32 s13, s13, 3 -; VI-NEXT: v_writelane_b32 v21, s46, 26 -; VI-NEXT: s_lshr_b32 s46, s10, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 27 -; VI-NEXT: s_lshr_b32 s46, s13, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 28 -; VI-NEXT: s_lshr_b32 s46, s13, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 26 +; VI-NEXT: s_lshr_b32 s26, s10, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 27 +; VI-NEXT: s_lshr_b32 s26, s13, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 28 +; VI-NEXT: s_lshr_b32 s26, s13, 16 ; VI-NEXT: s_add_i32 s12, s12, 3 -; VI-NEXT: v_writelane_b32 v21, s46, 29 -; VI-NEXT: s_lshr_b32 s46, s13, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 30 -; VI-NEXT: s_lshr_b32 s46, s12, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 29 +; VI-NEXT: s_lshr_b32 s26, s13, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 30 +; VI-NEXT: s_lshr_b32 s26, s12, 16 ; VI-NEXT: s_add_i32 s15, s15, 3 -; VI-NEXT: v_writelane_b32 v21, s46, 31 -; VI-NEXT: s_lshr_b32 s46, s12, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 32 -; VI-NEXT: s_lshr_b32 s46, s15, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 33 -; VI-NEXT: s_lshr_b32 s46, s15, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 31 +; VI-NEXT: s_lshr_b32 s26, s12, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 32 +; VI-NEXT: s_lshr_b32 s26, s15, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 33 +; VI-NEXT: s_lshr_b32 s26, s15, 16 ; VI-NEXT: s_add_i32 s14, s14, 3 -; VI-NEXT: v_writelane_b32 v21, s46, 34 -; VI-NEXT: s_lshr_b32 s46, s15, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 35 -; VI-NEXT: s_lshr_b32 s46, s14, 16 -; VI-NEXT: s_add_i32 s41, s41, 3 -; VI-NEXT: v_writelane_b32 v21, s46, 36 -; VI-NEXT: s_lshr_b32 s46, s14, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 37 -; VI-NEXT: s_lshr_b32 s46, s41, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 38 -; VI-NEXT: s_lshr_b32 s46, s41, 16 -; VI-NEXT: s_add_i32 s40, s40, 3 -; VI-NEXT: v_writelane_b32 v21, s46, 39 -; VI-NEXT: s_lshr_b32 s46, s41, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 40 -; VI-NEXT: s_lshr_b32 s46, s40, 16 -; VI-NEXT: s_add_i32 s43, s43, 3 -; VI-NEXT: v_writelane_b32 v21, s46, 41 -; VI-NEXT: s_lshr_b32 s46, s40, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 42 -; VI-NEXT: s_lshr_b32 s46, s43, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 43 -; VI-NEXT: s_lshr_b32 s46, s43, 16 -; VI-NEXT: s_add_i32 s42, s42, 3 -; VI-NEXT: v_writelane_b32 v21, s46, 44 -; VI-NEXT: s_lshr_b32 s46, s43, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 45 -; VI-NEXT: s_lshr_b32 s46, s42, 16 -; VI-NEXT: s_add_i32 s45, s45, 3 -; VI-NEXT: v_writelane_b32 v21, s46, 46 -; VI-NEXT: s_lshr_b32 s46, s42, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 47 -; VI-NEXT: s_lshr_b32 s46, s45, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 48 -; VI-NEXT: s_lshr_b32 s46, s45, 16 -; VI-NEXT: s_add_i32 s44, s44, 3 -; VI-NEXT: v_writelane_b32 v21, s46, 49 -; VI-NEXT: s_lshr_b32 s46, s45, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 50 -; VI-NEXT: s_lshr_b32 s46, s44, 16 -; VI-NEXT: s_add_i32 s29, s29, 3 -; VI-NEXT: v_writelane_b32 v21, s46, 51 -; VI-NEXT: s_lshr_b32 s46, s44, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 52 -; VI-NEXT: s_lshr_b32 s46, s29, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 53 -; VI-NEXT: s_lshr_b32 s46, s29, 16 -; VI-NEXT: s_add_i32 s28, s28, 3 -; VI-NEXT: v_writelane_b32 v21, s46, 54 -; VI-NEXT: s_lshr_b32 s46, s29, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 55 -; VI-NEXT: s_lshr_b32 s46, s28, 16 -; VI-NEXT: s_add_i32 s27, s27, 3 -; VI-NEXT: v_writelane_b32 v21, s46, 56 -; VI-NEXT: s_lshr_b32 s46, s28, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 57 -; VI-NEXT: s_lshr_b32 s46, s27, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 58 -; VI-NEXT: s_lshr_b32 s46, s27, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 59 -; VI-NEXT: s_lshr_b64 s[60:61], s[4:5], 24 -; VI-NEXT: v_writelane_b32 v21, s60, 6 -; VI-NEXT: v_writelane_b32 v21, s61, 7 -; VI-NEXT: s_lshr_b64 s[60:61], s[6:7], 24 -; VI-NEXT: v_writelane_b32 v21, s60, 4 -; VI-NEXT: v_writelane_b32 v21, s61, 5 -; VI-NEXT: s_lshr_b64 s[60:61], s[8:9], 24 -; VI-NEXT: v_writelane_b32 v21, s60, 2 +; VI-NEXT: v_writelane_b32 v22, s26, 34 +; VI-NEXT: s_lshr_b32 s26, s15, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 35 +; VI-NEXT: s_lshr_b32 s26, s14, 16 ; VI-NEXT: s_add_i32 s17, s17, 3 +; VI-NEXT: v_writelane_b32 v22, s26, 36 +; VI-NEXT: s_lshr_b32 s26, s14, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 37 +; VI-NEXT: s_lshr_b32 s26, s17, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 38 +; VI-NEXT: s_lshr_b32 s26, s17, 16 ; VI-NEXT: s_add_i32 s16, s16, 3 +; VI-NEXT: v_writelane_b32 v22, s26, 39 +; VI-NEXT: s_lshr_b32 s26, s17, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 40 +; VI-NEXT: s_lshr_b32 s26, s16, 16 ; VI-NEXT: s_add_i32 s19, s19, 3 +; VI-NEXT: v_writelane_b32 v22, s26, 41 +; VI-NEXT: s_lshr_b32 s26, s16, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 42 +; VI-NEXT: s_lshr_b32 s26, s19, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 43 +; VI-NEXT: s_lshr_b32 s26, s19, 16 ; VI-NEXT: s_add_i32 s18, s18, 3 +; VI-NEXT: v_writelane_b32 v22, s26, 44 +; VI-NEXT: s_lshr_b32 s26, s19, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 45 +; VI-NEXT: s_lshr_b32 s26, s18, 16 ; VI-NEXT: s_add_i32 s21, s21, 3 +; VI-NEXT: v_writelane_b32 v22, s26, 46 +; VI-NEXT: s_lshr_b32 s26, s18, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 47 +; VI-NEXT: s_lshr_b32 s26, s21, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 48 +; VI-NEXT: s_lshr_b32 s26, s21, 16 ; VI-NEXT: s_add_i32 s20, s20, 3 +; VI-NEXT: v_writelane_b32 v22, s26, 49 +; VI-NEXT: s_lshr_b32 s26, s21, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 50 +; VI-NEXT: s_lshr_b32 s26, s20, 16 ; VI-NEXT: s_add_i32 s23, s23, 3 +; VI-NEXT: v_writelane_b32 v22, s26, 51 +; VI-NEXT: s_lshr_b32 s26, s20, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 52 +; VI-NEXT: s_lshr_b32 s26, s23, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 53 +; VI-NEXT: s_lshr_b32 s26, s23, 16 ; VI-NEXT: s_add_i32 s22, s22, 3 +; VI-NEXT: v_writelane_b32 v22, s26, 54 +; VI-NEXT: s_lshr_b32 s26, s23, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 55 +; VI-NEXT: s_lshr_b32 s26, s22, 16 ; VI-NEXT: s_add_i32 s25, s25, 3 +; VI-NEXT: v_writelane_b32 v22, s26, 56 +; VI-NEXT: s_lshr_b32 s26, s22, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 57 +; VI-NEXT: s_lshr_b32 s26, s25, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 58 +; VI-NEXT: s_lshr_b32 s26, s25, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 59 +; VI-NEXT: s_lshr_b64 s[60:61], s[4:5], 24 +; VI-NEXT: v_writelane_b32 v22, s60, 6 +; VI-NEXT: v_writelane_b32 v22, s61, 7 +; VI-NEXT: s_lshr_b64 s[60:61], s[6:7], 24 +; VI-NEXT: v_writelane_b32 v22, s60, 4 +; VI-NEXT: v_writelane_b32 v22, s61, 5 +; VI-NEXT: s_lshr_b64 s[60:61], s[8:9], 24 +; VI-NEXT: v_writelane_b32 v22, s60, 2 +; VI-NEXT: s_add_i32 s57, s57, 3 +; VI-NEXT: s_add_i32 s56, s56, 3 +; VI-NEXT: s_add_i32 s47, s47, 3 +; VI-NEXT: s_add_i32 s46, s46, 3 +; VI-NEXT: s_add_i32 s45, s45, 3 +; VI-NEXT: s_add_i32 s44, s44, 3 +; VI-NEXT: s_add_i32 s43, s43, 3 +; VI-NEXT: s_add_i32 s42, s42, 3 +; VI-NEXT: s_add_i32 s41, s41, 3 +; VI-NEXT: s_add_i32 s40, s40, 3 ; VI-NEXT: s_add_i32 s24, s24, 3 -; VI-NEXT: s_add_i32 s26, s26, 3 -; VI-NEXT: v_writelane_b32 v21, s61, 3 +; VI-NEXT: v_writelane_b32 v22, s61, 3 ; VI-NEXT: s_lshr_b64 s[60:61], s[10:11], 24 -; VI-NEXT: s_lshr_b32 s66, s27, 8 -; VI-NEXT: s_lshr_b32 s67, s26, 16 -; VI-NEXT: s_lshr_b32 s68, s26, 8 -; VI-NEXT: s_lshr_b32 s69, s25, 24 -; VI-NEXT: s_lshr_b32 s70, s25, 16 -; VI-NEXT: s_lshr_b32 s71, s25, 8 -; VI-NEXT: s_lshr_b32 s80, s24, 16 -; VI-NEXT: s_lshr_b32 s81, s24, 8 -; VI-NEXT: s_lshr_b32 s82, s23, 24 -; VI-NEXT: s_lshr_b32 s83, s23, 16 -; VI-NEXT: s_lshr_b32 s84, s23, 8 -; VI-NEXT: s_lshr_b32 s85, s22, 16 -; VI-NEXT: s_lshr_b32 s86, s22, 8 -; VI-NEXT: s_lshr_b32 s87, s21, 24 -; VI-NEXT: s_lshr_b32 s50, s21, 16 -; VI-NEXT: s_lshr_b32 s46, s21, 8 -; VI-NEXT: s_lshr_b32 s47, s20, 16 -; VI-NEXT: s_lshr_b32 s56, s20, 8 -; VI-NEXT: s_lshr_b32 s57, s19, 24 -; VI-NEXT: s_lshr_b32 s51, s19, 16 -; VI-NEXT: s_lshr_b32 s52, s19, 8 -; VI-NEXT: s_lshr_b32 s53, s18, 16 -; VI-NEXT: s_lshr_b32 s54, s18, 8 -; VI-NEXT: s_lshr_b32 s58, s17, 24 -; VI-NEXT: s_lshr_b32 s59, s17, 16 -; VI-NEXT: s_lshr_b32 s55, s17, 8 -; VI-NEXT: s_lshr_b32 s64, s16, 16 -; VI-NEXT: s_lshr_b32 s65, s16, 8 -; VI-NEXT: v_writelane_b32 v21, s60, 0 +; VI-NEXT: s_lshr_b32 s66, s25, 8 +; VI-NEXT: s_lshr_b32 s67, s24, 16 +; VI-NEXT: s_lshr_b32 s68, s24, 8 +; VI-NEXT: s_lshr_b32 s69, s41, 24 +; VI-NEXT: s_lshr_b32 s70, s41, 16 +; VI-NEXT: s_lshr_b32 s71, s41, 8 +; VI-NEXT: s_lshr_b32 s80, s40, 16 +; VI-NEXT: s_lshr_b32 s81, s40, 8 +; VI-NEXT: s_lshr_b32 s82, s43, 24 +; VI-NEXT: s_lshr_b32 s83, s43, 16 +; VI-NEXT: s_lshr_b32 s84, s43, 8 +; VI-NEXT: s_lshr_b32 s85, s42, 16 +; VI-NEXT: s_lshr_b32 s86, s42, 8 +; VI-NEXT: s_lshr_b32 s87, s45, 24 +; VI-NEXT: s_lshr_b32 s50, s45, 16 +; VI-NEXT: s_lshr_b32 s26, s45, 8 +; VI-NEXT: s_lshr_b32 s27, s44, 16 +; VI-NEXT: s_lshr_b32 s28, s44, 8 +; VI-NEXT: s_lshr_b32 s29, s47, 24 +; VI-NEXT: s_lshr_b32 s51, s47, 16 +; VI-NEXT: s_lshr_b32 s52, s47, 8 +; VI-NEXT: s_lshr_b32 s53, s46, 16 +; VI-NEXT: s_lshr_b32 s54, s46, 8 +; VI-NEXT: s_lshr_b32 s58, s57, 24 +; VI-NEXT: s_lshr_b32 s59, s57, 16 +; VI-NEXT: s_lshr_b32 s55, s57, 8 +; VI-NEXT: s_lshr_b32 s64, s56, 16 +; VI-NEXT: s_lshr_b32 s65, s56, 8 +; VI-NEXT: v_writelane_b32 v22, s60, 0 ; VI-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 ; VI-NEXT: s_lshr_b64 s[72:73], s[14:15], 24 -; VI-NEXT: s_lshr_b64 s[74:75], s[40:41], 24 -; VI-NEXT: s_lshr_b64 s[76:77], s[42:43], 24 -; VI-NEXT: s_lshr_b64 s[78:79], s[44:45], 24 -; VI-NEXT: s_lshr_b64 s[88:89], s[28:29], 24 -; VI-NEXT: s_lshr_b64 s[90:91], s[26:27], 24 -; VI-NEXT: s_lshr_b64 s[30:31], s[24:25], 24 -; VI-NEXT: s_lshr_b64 s[34:35], s[22:23], 24 -; VI-NEXT: s_lshr_b64 s[36:37], s[20:21], 24 -; VI-NEXT: s_lshr_b64 s[38:39], s[18:19], 24 -; VI-NEXT: s_lshr_b64 s[48:49], s[16:17], 24 -; VI-NEXT: v_writelane_b32 v21, s61, 1 +; VI-NEXT: s_lshr_b64 s[74:75], s[16:17], 24 +; VI-NEXT: s_lshr_b64 s[76:77], s[18:19], 24 +; VI-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 +; VI-NEXT: s_lshr_b64 s[88:89], s[22:23], 24 +; VI-NEXT: s_lshr_b64 s[90:91], s[24:25], 24 +; VI-NEXT: s_lshr_b64 s[30:31], s[40:41], 24 +; VI-NEXT: s_lshr_b64 s[34:35], s[42:43], 24 +; VI-NEXT: s_lshr_b64 s[36:37], s[44:45], 24 +; VI-NEXT: s_lshr_b64 s[38:39], s[46:47], 24 +; VI-NEXT: s_lshr_b64 s[48:49], s[56:57], 24 +; VI-NEXT: v_writelane_b32 v22, s61, 1 ; VI-NEXT: .LBB13_3: ; %end ; VI-NEXT: s_lshl_b32 s61, s65, 8 -; VI-NEXT: s_and_b32 s16, s16, 0xff -; VI-NEXT: s_or_b32 s16, s16, s61 +; VI-NEXT: s_and_b32 s56, s56, 0xff +; VI-NEXT: s_or_b32 s56, s56, s61 ; VI-NEXT: s_lshl_b32 s61, s48, 8 ; VI-NEXT: s_and_b32 s63, s64, 0xff ; VI-NEXT: s_or_b32 s61, s63, s61 -; VI-NEXT: s_and_b32 s16, s16, 0xffff +; VI-NEXT: s_and_b32 s56, s56, 0xffff ; VI-NEXT: s_lshl_b32 s61, s61, 16 -; VI-NEXT: s_or_b32 s16, s16, s61 -; VI-NEXT: v_mov_b32_e32 v1, s16 -; VI-NEXT: s_and_b32 s16, s17, 0xff -; VI-NEXT: s_lshl_b32 s17, s55, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, s59, 0xff +; VI-NEXT: s_or_b32 s56, s56, s61 +; VI-NEXT: v_mov_b32_e32 v1, s56 +; VI-NEXT: s_and_b32 s56, s57, 0xff +; VI-NEXT: s_lshl_b32 s57, s55, 8 +; VI-NEXT: s_or_b32 s56, s56, s57 +; VI-NEXT: s_and_b32 s57, s59, 0xff ; VI-NEXT: s_lshl_b32 s58, s58, 8 -; VI-NEXT: s_or_b32 s17, s17, s58 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: s_lshl_b32 s16, s54, 8 -; VI-NEXT: s_and_b32 s17, s18, 0xff -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s38, 8 -; VI-NEXT: s_and_b32 s18, s53, 0xff -; VI-NEXT: s_or_b32 s17, s18, s17 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v3, s16 -; VI-NEXT: s_and_b32 s16, s19, 0xff -; VI-NEXT: s_lshl_b32 s17, s52, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, s51, 0xff -; VI-NEXT: s_lshl_b32 s18, s57, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v4, s16 -; VI-NEXT: s_lshl_b32 s16, s56, 8 -; VI-NEXT: s_and_b32 s17, s20, 0xff -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s36, 8 -; VI-NEXT: s_and_b32 s18, s47, 0xff -; VI-NEXT: s_or_b32 s17, s18, s17 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v5, s16 -; VI-NEXT: s_and_b32 s16, s21, 0xff -; VI-NEXT: s_lshl_b32 s17, s46, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, s50, 0xff -; VI-NEXT: s_lshl_b32 s18, s87, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v6, s16 -; VI-NEXT: s_lshl_b32 s16, s86, 8 -; VI-NEXT: s_and_b32 s17, s22, 0xff -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s34, 8 -; VI-NEXT: s_and_b32 s18, s85, 0xff -; VI-NEXT: s_or_b32 s17, s18, s17 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v7, s16 -; VI-NEXT: s_and_b32 s16, s23, 0xff -; VI-NEXT: s_lshl_b32 s17, s84, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, s83, 0xff -; VI-NEXT: s_lshl_b32 s18, s82, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v8, s16 -; VI-NEXT: s_lshl_b32 s16, s81, 8 -; VI-NEXT: s_and_b32 s17, s24, 0xff -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s30, 8 -; VI-NEXT: s_and_b32 s18, s80, 0xff -; VI-NEXT: s_or_b32 s17, s18, s17 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v9, s16 -; VI-NEXT: s_and_b32 s16, s25, 0xff -; VI-NEXT: s_lshl_b32 s17, s71, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, s70, 0xff -; VI-NEXT: s_lshl_b32 s18, s69, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v10, s16 -; VI-NEXT: s_lshl_b32 s16, s68, 8 -; VI-NEXT: s_and_b32 s17, s26, 0xff -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s90, 8 -; VI-NEXT: s_and_b32 s18, s67, 0xff -; VI-NEXT: s_or_b32 s17, s18, s17 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v11, s16 -; VI-NEXT: s_and_b32 s16, s27, 0xff -; VI-NEXT: s_lshl_b32 s17, s66, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 59 -; VI-NEXT: v_readlane_b32 s18, v21, 58 -; VI-NEXT: s_and_b32 s17, s17, 0xff -; VI-NEXT: s_lshl_b32 s18, s18, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v12, s16 -; VI-NEXT: v_readlane_b32 s16, v21, 57 -; VI-NEXT: s_lshl_b32 s16, s16, 8 -; VI-NEXT: s_and_b32 s17, s28, 0xff -; VI-NEXT: v_readlane_b32 s18, v21, 56 -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s88, 8 -; VI-NEXT: s_and_b32 s18, s18, 0xff -; VI-NEXT: s_or_b32 s17, s18, s17 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 55 -; VI-NEXT: v_mov_b32_e32 v13, s16 -; VI-NEXT: s_and_b32 s16, s29, 0xff -; VI-NEXT: s_lshl_b32 s17, s17, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 54 -; VI-NEXT: v_readlane_b32 s18, v21, 53 -; VI-NEXT: s_and_b32 s17, s17, 0xff -; VI-NEXT: s_lshl_b32 s18, s18, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v14, s16 -; VI-NEXT: v_readlane_b32 s16, v21, 52 -; VI-NEXT: s_lshl_b32 s16, s16, 8 -; VI-NEXT: s_and_b32 s17, s44, 0xff -; VI-NEXT: v_readlane_b32 s18, v21, 51 -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s78, 8 -; VI-NEXT: s_and_b32 s18, s18, 0xff -; VI-NEXT: s_or_b32 s17, s18, s17 +; VI-NEXT: s_or_b32 s57, s57, s58 +; VI-NEXT: s_and_b32 s56, s56, 0xffff +; VI-NEXT: s_lshl_b32 s57, s57, 16 +; VI-NEXT: s_or_b32 s56, s56, s57 +; VI-NEXT: v_mov_b32_e32 v2, s56 +; VI-NEXT: s_lshl_b32 s56, s54, 8 +; VI-NEXT: s_and_b32 s46, s46, 0xff +; VI-NEXT: s_or_b32 s46, s46, s56 +; VI-NEXT: s_lshl_b32 s56, s38, 8 +; VI-NEXT: s_and_b32 s57, s53, 0xff +; VI-NEXT: s_or_b32 s56, s57, s56 +; VI-NEXT: s_and_b32 s46, s46, 0xffff +; VI-NEXT: s_lshl_b32 s56, s56, 16 +; VI-NEXT: s_or_b32 s46, s46, s56 +; VI-NEXT: v_mov_b32_e32 v3, s46 +; VI-NEXT: s_and_b32 s46, s47, 0xff +; VI-NEXT: s_lshl_b32 s47, s52, 8 +; VI-NEXT: s_or_b32 s46, s46, s47 +; VI-NEXT: s_and_b32 s47, s51, 0xff +; VI-NEXT: s_lshl_b32 s29, s29, 8 +; VI-NEXT: s_or_b32 s29, s47, s29 +; VI-NEXT: s_and_b32 s46, s46, 0xffff +; VI-NEXT: s_lshl_b32 s29, s29, 16 +; VI-NEXT: s_or_b32 s29, s46, s29 +; VI-NEXT: v_mov_b32_e32 v4, s29 +; VI-NEXT: s_lshl_b32 s28, s28, 8 +; VI-NEXT: s_and_b32 s29, s44, 0xff +; VI-NEXT: s_or_b32 s28, s29, s28 +; VI-NEXT: s_lshl_b32 s29, s36, 8 +; VI-NEXT: s_and_b32 s27, s27, 0xff +; VI-NEXT: s_or_b32 s27, s27, s29 +; VI-NEXT: s_and_b32 s28, s28, 0xffff +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s27, s28, s27 +; VI-NEXT: v_mov_b32_e32 v5, s27 +; VI-NEXT: s_and_b32 s27, s45, 0xff +; VI-NEXT: s_lshl_b32 s26, s26, 8 +; VI-NEXT: s_or_b32 s26, s27, s26 +; VI-NEXT: s_and_b32 s27, s50, 0xff +; VI-NEXT: s_lshl_b32 s28, s87, 8 +; VI-NEXT: s_or_b32 s27, s27, s28 +; VI-NEXT: s_and_b32 s26, s26, 0xffff +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s26, s26, s27 +; VI-NEXT: v_mov_b32_e32 v6, s26 +; VI-NEXT: s_lshl_b32 s26, s86, 8 +; VI-NEXT: s_and_b32 s27, s42, 0xff +; VI-NEXT: s_or_b32 s26, s27, s26 +; VI-NEXT: s_lshl_b32 s27, s34, 8 +; VI-NEXT: s_and_b32 s28, s85, 0xff +; VI-NEXT: s_or_b32 s27, s28, s27 +; VI-NEXT: s_and_b32 s26, s26, 0xffff +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s26, s26, s27 +; VI-NEXT: v_mov_b32_e32 v7, s26 +; VI-NEXT: s_and_b32 s26, s43, 0xff +; VI-NEXT: s_lshl_b32 s27, s84, 8 +; VI-NEXT: s_or_b32 s26, s26, s27 +; VI-NEXT: s_and_b32 s27, s83, 0xff +; VI-NEXT: s_lshl_b32 s28, s82, 8 +; VI-NEXT: s_or_b32 s27, s27, s28 +; VI-NEXT: s_and_b32 s26, s26, 0xffff +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s26, s26, s27 +; VI-NEXT: v_mov_b32_e32 v8, s26 +; VI-NEXT: s_lshl_b32 s26, s81, 8 +; VI-NEXT: s_and_b32 s27, s40, 0xff +; VI-NEXT: s_or_b32 s26, s27, s26 +; VI-NEXT: s_lshl_b32 s27, s30, 8 +; VI-NEXT: s_and_b32 s28, s80, 0xff +; VI-NEXT: s_or_b32 s27, s28, s27 +; VI-NEXT: s_and_b32 s26, s26, 0xffff +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s26, s26, s27 +; VI-NEXT: v_mov_b32_e32 v9, s26 +; VI-NEXT: s_and_b32 s26, s41, 0xff +; VI-NEXT: s_lshl_b32 s27, s71, 8 +; VI-NEXT: s_or_b32 s26, s26, s27 +; VI-NEXT: s_and_b32 s27, s70, 0xff +; VI-NEXT: s_lshl_b32 s28, s69, 8 +; VI-NEXT: s_or_b32 s27, s27, s28 +; VI-NEXT: s_and_b32 s26, s26, 0xffff +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s26, s26, s27 +; VI-NEXT: v_mov_b32_e32 v10, s26 +; VI-NEXT: s_lshl_b32 s26, s68, 8 +; VI-NEXT: s_and_b32 s24, s24, 0xff +; VI-NEXT: s_or_b32 s24, s24, s26 +; VI-NEXT: s_lshl_b32 s26, s90, 8 +; VI-NEXT: s_and_b32 s27, s67, 0xff +; VI-NEXT: s_or_b32 s26, s27, s26 +; VI-NEXT: s_and_b32 s24, s24, 0xffff +; VI-NEXT: s_lshl_b32 s26, s26, 16 +; VI-NEXT: s_or_b32 s24, s24, s26 +; VI-NEXT: v_mov_b32_e32 v11, s24 +; VI-NEXT: s_and_b32 s24, s25, 0xff +; VI-NEXT: s_lshl_b32 s25, s66, 8 +; VI-NEXT: s_or_b32 s24, s24, s25 +; VI-NEXT: v_readlane_b32 s25, v22, 59 +; VI-NEXT: v_readlane_b32 s26, v22, 58 +; VI-NEXT: s_and_b32 s25, s25, 0xff +; VI-NEXT: s_lshl_b32 s26, s26, 8 +; VI-NEXT: s_or_b32 s25, s25, s26 +; VI-NEXT: s_and_b32 s24, s24, 0xffff +; VI-NEXT: s_lshl_b32 s25, s25, 16 +; VI-NEXT: s_or_b32 s24, s24, s25 +; VI-NEXT: v_mov_b32_e32 v12, s24 +; VI-NEXT: v_readlane_b32 s24, v22, 57 +; VI-NEXT: s_lshl_b32 s24, s24, 8 +; VI-NEXT: s_and_b32 s22, s22, 0xff +; VI-NEXT: v_readlane_b32 s25, v22, 56 +; VI-NEXT: s_or_b32 s22, s22, s24 +; VI-NEXT: s_lshl_b32 s24, s88, 8 +; VI-NEXT: s_and_b32 s25, s25, 0xff +; VI-NEXT: s_or_b32 s24, s25, s24 +; VI-NEXT: s_and_b32 s22, s22, 0xffff +; VI-NEXT: s_lshl_b32 s24, s24, 16 +; VI-NEXT: s_or_b32 s22, s22, s24 +; VI-NEXT: v_mov_b32_e32 v13, s22 +; VI-NEXT: s_and_b32 s22, s23, 0xff +; VI-NEXT: v_readlane_b32 s23, v22, 55 +; VI-NEXT: s_lshl_b32 s23, s23, 8 +; VI-NEXT: s_or_b32 s22, s22, s23 +; VI-NEXT: v_readlane_b32 s23, v22, 54 +; VI-NEXT: v_readlane_b32 s24, v22, 53 +; VI-NEXT: s_and_b32 s23, s23, 0xff +; VI-NEXT: s_lshl_b32 s24, s24, 8 +; VI-NEXT: s_or_b32 s23, s23, s24 +; VI-NEXT: s_and_b32 s22, s22, 0xffff +; VI-NEXT: s_lshl_b32 s23, s23, 16 +; VI-NEXT: s_or_b32 s22, s22, s23 +; VI-NEXT: v_mov_b32_e32 v14, s22 +; VI-NEXT: v_readlane_b32 s22, v22, 52 +; VI-NEXT: s_lshl_b32 s22, s22, 8 +; VI-NEXT: s_and_b32 s20, s20, 0xff +; VI-NEXT: v_readlane_b32 s23, v22, 51 +; VI-NEXT: s_or_b32 s20, s20, s22 +; VI-NEXT: s_lshl_b32 s22, s78, 8 +; VI-NEXT: s_and_b32 s23, s23, 0xff +; VI-NEXT: s_or_b32 s22, s23, s22 +; VI-NEXT: s_and_b32 s20, s20, 0xffff +; VI-NEXT: s_lshl_b32 s22, s22, 16 +; VI-NEXT: s_or_b32 s20, s20, s22 ; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 4, v0 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 +; VI-NEXT: v_mov_b32_e32 v15, s20 +; VI-NEXT: s_and_b32 s20, s21, 0xff +; VI-NEXT: v_readlane_b32 s21, v22, 50 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 8, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 50 +; VI-NEXT: s_lshl_b32 s21, s21, 8 ; VI-NEXT: buffer_store_dword v3, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 12, v0 -; VI-NEXT: v_mov_b32_e32 v15, s16 -; VI-NEXT: s_and_b32 s16, s45, 0xff -; VI-NEXT: s_lshl_b32 s17, s17, 8 +; VI-NEXT: s_or_b32 s20, s20, s21 ; VI-NEXT: buffer_store_dword v4, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 16, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 +; VI-NEXT: v_readlane_b32 s21, v22, 49 +; VI-NEXT: v_readlane_b32 s22, v22, 48 ; VI-NEXT: buffer_store_dword v5, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 20, v0 -; VI-NEXT: v_readlane_b32 s17, v21, 49 -; VI-NEXT: v_readlane_b32 s18, v21, 48 +; VI-NEXT: s_and_b32 s21, s21, 0xff +; VI-NEXT: s_lshl_b32 s22, s22, 8 ; VI-NEXT: buffer_store_dword v6, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 24, v0 -; VI-NEXT: s_and_b32 s17, s17, 0xff -; VI-NEXT: s_lshl_b32 s18, s18, 8 +; VI-NEXT: s_or_b32 s21, s21, s22 ; VI-NEXT: buffer_store_dword v7, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 28, v0 -; VI-NEXT: s_or_b32 s17, s17, s18 +; VI-NEXT: s_and_b32 s20, s20, 0xffff +; VI-NEXT: s_lshl_b32 s21, s21, 16 ; VI-NEXT: buffer_store_dword v8, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 32, v0 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 +; VI-NEXT: s_or_b32 s20, s20, s21 ; VI-NEXT: buffer_store_dword v9, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 36, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 47 +; VI-NEXT: v_mov_b32_e32 v2, s20 +; VI-NEXT: v_readlane_b32 s20, v22, 47 ; VI-NEXT: buffer_store_dword v10, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 40, v0 -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: s_and_b32 s16, s42, 0xff -; VI-NEXT: s_lshl_b32 s17, s17, 8 +; VI-NEXT: s_and_b32 s18, s18, 0xff +; VI-NEXT: s_lshl_b32 s20, s20, 8 ; VI-NEXT: buffer_store_dword v11, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 44, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 46 +; VI-NEXT: s_or_b32 s18, s18, s20 +; VI-NEXT: v_readlane_b32 s20, v22, 46 ; VI-NEXT: buffer_store_dword v12, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 48, v0 -; VI-NEXT: s_and_b32 s17, s17, 0xff -; VI-NEXT: s_lshl_b32 s18, s76, 8 +; VI-NEXT: s_and_b32 s20, s20, 0xff +; VI-NEXT: s_lshl_b32 s21, s76, 8 ; VI-NEXT: buffer_store_dword v13, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 52, v0 -; VI-NEXT: s_or_b32 s17, s17, s18 +; VI-NEXT: s_or_b32 s20, s20, s21 ; VI-NEXT: buffer_store_dword v14, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 56, v0 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 +; VI-NEXT: s_and_b32 s18, s18, 0xffff +; VI-NEXT: s_lshl_b32 s20, s20, 16 ; VI-NEXT: buffer_store_dword v15, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 60, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 45 +; VI-NEXT: s_or_b32 s18, s18, s20 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: s_and_b32 s16, s43, 0xff -; VI-NEXT: s_lshl_b32 s17, s17, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 44 -; VI-NEXT: v_readlane_b32 s18, v21, 43 -; VI-NEXT: s_and_b32 s17, s17, 0xff -; VI-NEXT: s_lshl_b32 s18, s18, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 +; VI-NEXT: v_mov_b32_e32 v2, s18 +; VI-NEXT: s_and_b32 s18, s19, 0xff +; VI-NEXT: v_readlane_b32 s19, v22, 45 +; VI-NEXT: s_lshl_b32 s19, s19, 8 +; VI-NEXT: s_or_b32 s18, s18, s19 +; VI-NEXT: v_readlane_b32 s19, v22, 44 +; VI-NEXT: v_readlane_b32 s20, v22, 43 +; VI-NEXT: s_and_b32 s19, s19, 0xff +; VI-NEXT: s_lshl_b32 s20, s20, 8 +; VI-NEXT: s_or_b32 s19, s19, s20 +; VI-NEXT: s_and_b32 s18, s18, 0xffff +; VI-NEXT: s_lshl_b32 s19, s19, 16 ; VI-NEXT: v_add_u32_e32 v1, vcc, 64, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 42 +; VI-NEXT: s_or_b32 s18, s18, s19 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: s_and_b32 s16, s40, 0xff -; VI-NEXT: s_lshl_b32 s17, s17, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 41 -; VI-NEXT: s_and_b32 s17, s17, 0xff -; VI-NEXT: s_lshl_b32 s18, s74, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 +; VI-NEXT: v_mov_b32_e32 v2, s18 +; VI-NEXT: v_readlane_b32 s18, v22, 42 +; VI-NEXT: s_and_b32 s16, s16, 0xff +; VI-NEXT: s_lshl_b32 s18, s18, 8 +; VI-NEXT: s_or_b32 s16, s16, s18 +; VI-NEXT: v_readlane_b32 s18, v22, 41 +; VI-NEXT: s_and_b32 s18, s18, 0xff +; VI-NEXT: s_lshl_b32 s19, s74, 8 +; VI-NEXT: s_or_b32 s18, s18, s19 ; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 +; VI-NEXT: s_lshl_b32 s18, s18, 16 ; VI-NEXT: v_add_u32_e32 v1, vcc, 0x44, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 40 +; VI-NEXT: s_or_b32 s16, s16, s18 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: s_and_b32 s16, s41, 0xff +; VI-NEXT: s_and_b32 s16, s17, 0xff +; VI-NEXT: v_readlane_b32 s17, v22, 40 ; VI-NEXT: s_lshl_b32 s17, s17, 8 ; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 39 -; VI-NEXT: v_readlane_b32 s18, v21, 38 +; VI-NEXT: v_readlane_b32 s17, v22, 39 +; VI-NEXT: v_readlane_b32 s18, v22, 38 ; VI-NEXT: s_and_b32 s17, s17, 0xff ; VI-NEXT: s_lshl_b32 s18, s18, 8 ; VI-NEXT: s_or_b32 s17, s17, s18 @@ -9289,11 +9345,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; VI-NEXT: s_or_b32 s16, s16, s17 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: v_readlane_b32 s16, v21, 37 +; VI-NEXT: v_readlane_b32 s16, v22, 37 ; VI-NEXT: s_and_b32 s14, s14, 0xff ; VI-NEXT: s_lshl_b32 s16, s16, 8 ; VI-NEXT: s_or_b32 s14, s14, s16 -; VI-NEXT: v_readlane_b32 s16, v21, 36 +; VI-NEXT: v_readlane_b32 s16, v22, 36 ; VI-NEXT: s_and_b32 s16, s16, 0xff ; VI-NEXT: s_lshl_b32 s17, s72, 8 ; VI-NEXT: s_or_b32 s16, s16, s17 @@ -9304,11 +9360,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s14 ; VI-NEXT: s_and_b32 s14, s15, 0xff -; VI-NEXT: v_readlane_b32 s15, v21, 35 +; VI-NEXT: v_readlane_b32 s15, v22, 35 ; VI-NEXT: s_lshl_b32 s15, s15, 8 ; VI-NEXT: s_or_b32 s14, s14, s15 -; VI-NEXT: v_readlane_b32 s15, v21, 34 -; VI-NEXT: v_readlane_b32 s16, v21, 33 +; VI-NEXT: v_readlane_b32 s15, v22, 34 +; VI-NEXT: v_readlane_b32 s16, v22, 33 ; VI-NEXT: s_and_b32 s15, s15, 0xff ; VI-NEXT: s_lshl_b32 s16, s16, 8 ; VI-NEXT: s_or_b32 s15, s15, s16 @@ -9318,11 +9374,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; VI-NEXT: s_or_b32 s14, s14, s15 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s14 -; VI-NEXT: v_readlane_b32 s14, v21, 32 +; VI-NEXT: v_readlane_b32 s14, v22, 32 ; VI-NEXT: s_and_b32 s12, s12, 0xff ; VI-NEXT: s_lshl_b32 s14, s14, 8 ; VI-NEXT: s_or_b32 s12, s12, s14 -; VI-NEXT: v_readlane_b32 s14, v21, 31 +; VI-NEXT: v_readlane_b32 s14, v22, 31 ; VI-NEXT: s_and_b32 s14, s14, 0xff ; VI-NEXT: s_lshl_b32 s15, s62, 8 ; VI-NEXT: s_or_b32 s14, s14, s15 @@ -9333,11 +9389,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s12 ; VI-NEXT: s_and_b32 s12, s13, 0xff -; VI-NEXT: v_readlane_b32 s13, v21, 30 +; VI-NEXT: v_readlane_b32 s13, v22, 30 ; VI-NEXT: s_lshl_b32 s13, s13, 8 ; VI-NEXT: s_or_b32 s12, s12, s13 -; VI-NEXT: v_readlane_b32 s13, v21, 29 -; VI-NEXT: v_readlane_b32 s14, v21, 28 +; VI-NEXT: v_readlane_b32 s13, v22, 29 +; VI-NEXT: v_readlane_b32 s14, v22, 28 ; VI-NEXT: s_and_b32 s13, s13, 0xff ; VI-NEXT: s_lshl_b32 s14, s14, 8 ; VI-NEXT: s_or_b32 s13, s13, s14 @@ -9347,12 +9403,12 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; VI-NEXT: s_or_b32 s12, s12, s13 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s12 -; VI-NEXT: v_readlane_b32 s12, v21, 27 +; VI-NEXT: v_readlane_b32 s12, v22, 27 ; VI-NEXT: s_and_b32 s10, s10, 0xff ; VI-NEXT: s_lshl_b32 s12, s12, 8 ; VI-NEXT: s_or_b32 s10, s10, s12 -; VI-NEXT: v_readlane_b32 s12, v21, 26 -; VI-NEXT: v_readlane_b32 s14, v21, 0 +; VI-NEXT: v_readlane_b32 s12, v22, 26 +; VI-NEXT: v_readlane_b32 s14, v22, 0 ; VI-NEXT: s_and_b32 s12, s12, 0xff ; VI-NEXT: s_lshl_b32 s13, s14, 8 ; VI-NEXT: s_or_b32 s12, s12, s13 @@ -9363,11 +9419,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s10 ; VI-NEXT: s_and_b32 s10, s11, 0xff -; VI-NEXT: v_readlane_b32 s11, v21, 25 +; VI-NEXT: v_readlane_b32 s11, v22, 25 ; VI-NEXT: s_lshl_b32 s11, s11, 8 ; VI-NEXT: s_or_b32 s10, s10, s11 -; VI-NEXT: v_readlane_b32 s11, v21, 24 -; VI-NEXT: v_readlane_b32 s12, v21, 23 +; VI-NEXT: v_readlane_b32 s11, v22, 24 +; VI-NEXT: v_readlane_b32 s12, v22, 23 ; VI-NEXT: s_and_b32 s11, s11, 0xff ; VI-NEXT: s_lshl_b32 s12, s12, 8 ; VI-NEXT: s_or_b32 s11, s11, s12 @@ -9377,12 +9433,12 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; VI-NEXT: s_or_b32 s10, s10, s11 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s10 -; VI-NEXT: v_readlane_b32 s10, v21, 22 +; VI-NEXT: v_readlane_b32 s10, v22, 22 ; VI-NEXT: s_and_b32 s8, s8, 0xff ; VI-NEXT: s_lshl_b32 s10, s10, 8 ; VI-NEXT: s_or_b32 s8, s8, s10 -; VI-NEXT: v_readlane_b32 s10, v21, 21 -; VI-NEXT: v_readlane_b32 s12, v21, 2 +; VI-NEXT: v_readlane_b32 s10, v22, 21 +; VI-NEXT: v_readlane_b32 s12, v22, 2 ; VI-NEXT: s_and_b32 s10, s10, 0xff ; VI-NEXT: s_lshl_b32 s11, s12, 8 ; VI-NEXT: s_or_b32 s10, s10, s11 @@ -9393,11 +9449,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s8 ; VI-NEXT: s_and_b32 s8, s9, 0xff -; VI-NEXT: v_readlane_b32 s9, v21, 20 +; VI-NEXT: v_readlane_b32 s9, v22, 20 ; VI-NEXT: s_lshl_b32 s9, s9, 8 ; VI-NEXT: s_or_b32 s8, s8, s9 -; VI-NEXT: v_readlane_b32 s9, v21, 19 -; VI-NEXT: v_readlane_b32 s10, v21, 18 +; VI-NEXT: v_readlane_b32 s9, v22, 19 +; VI-NEXT: v_readlane_b32 s10, v22, 18 ; VI-NEXT: s_and_b32 s9, s9, 0xff ; VI-NEXT: s_lshl_b32 s10, s10, 8 ; VI-NEXT: s_or_b32 s9, s9, s10 @@ -9407,12 +9463,12 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; VI-NEXT: s_or_b32 s8, s8, s9 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s8 -; VI-NEXT: v_readlane_b32 s8, v21, 17 +; VI-NEXT: v_readlane_b32 s8, v22, 17 ; VI-NEXT: s_and_b32 s6, s6, 0xff ; VI-NEXT: s_lshl_b32 s8, s8, 8 ; VI-NEXT: s_or_b32 s6, s6, s8 -; VI-NEXT: v_readlane_b32 s8, v21, 16 -; VI-NEXT: v_readlane_b32 s10, v21, 4 +; VI-NEXT: v_readlane_b32 s8, v22, 16 +; VI-NEXT: v_readlane_b32 s10, v22, 4 ; VI-NEXT: s_and_b32 s8, s8, 0xff ; VI-NEXT: s_lshl_b32 s9, s10, 8 ; VI-NEXT: s_or_b32 s8, s8, s9 @@ -9423,11 +9479,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s6 ; VI-NEXT: s_and_b32 s6, s7, 0xff -; VI-NEXT: v_readlane_b32 s7, v21, 15 +; VI-NEXT: v_readlane_b32 s7, v22, 15 ; VI-NEXT: s_lshl_b32 s7, s7, 8 ; VI-NEXT: s_or_b32 s6, s6, s7 -; VI-NEXT: v_readlane_b32 s7, v21, 14 -; VI-NEXT: v_readlane_b32 s8, v21, 13 +; VI-NEXT: v_readlane_b32 s7, v22, 14 +; VI-NEXT: v_readlane_b32 s8, v22, 13 ; VI-NEXT: s_and_b32 s7, s7, 0xff ; VI-NEXT: s_lshl_b32 s8, s8, 8 ; VI-NEXT: s_or_b32 s7, s7, s8 @@ -9437,12 +9493,12 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; VI-NEXT: s_or_b32 s6, s6, s7 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s6 -; VI-NEXT: v_readlane_b32 s6, v21, 12 +; VI-NEXT: v_readlane_b32 s6, v22, 12 ; VI-NEXT: s_and_b32 s4, s4, 0xff ; VI-NEXT: s_lshl_b32 s6, s6, 8 ; VI-NEXT: s_or_b32 s4, s4, s6 -; VI-NEXT: v_readlane_b32 s6, v21, 11 -; VI-NEXT: v_readlane_b32 s8, v21, 6 +; VI-NEXT: v_readlane_b32 s6, v22, 11 +; VI-NEXT: v_readlane_b32 s8, v22, 6 ; VI-NEXT: s_and_b32 s6, s6, 0xff ; VI-NEXT: s_lshl_b32 s7, s8, 8 ; VI-NEXT: s_or_b32 s6, s6, s7 @@ -9453,11 +9509,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s4 ; VI-NEXT: s_and_b32 s4, s5, 0xff -; VI-NEXT: v_readlane_b32 s5, v21, 10 +; VI-NEXT: v_readlane_b32 s5, v22, 10 ; VI-NEXT: s_lshl_b32 s5, s5, 8 ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: v_readlane_b32 s5, v21, 9 -; VI-NEXT: v_readlane_b32 s6, v21, 8 +; VI-NEXT: v_readlane_b32 s5, v22, 9 +; VI-NEXT: v_readlane_b32 s6, v22, 8 ; VI-NEXT: s_and_b32 s5, s5, 0xff ; VI-NEXT: s_lshl_b32 s6, s6, 8 ; VI-NEXT: s_or_b32 s5, s5, s6 @@ -9468,46 +9524,46 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0 ; VI-NEXT: v_mov_b32_e32 v1, s4 -; VI-NEXT: v_readlane_b32 s15, v21, 1 -; VI-NEXT: v_readlane_b32 s13, v21, 3 -; VI-NEXT: v_readlane_b32 s11, v21, 5 -; VI-NEXT: v_readlane_b32 s9, v21, 7 +; VI-NEXT: v_readlane_b32 s15, v22, 1 +; VI-NEXT: v_readlane_b32 s13, v22, 3 +; VI-NEXT: v_readlane_b32 s11, v22, 5 +; VI-NEXT: v_readlane_b32 s9, v22, 7 ; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; VI-NEXT: v_readlane_b32 s87, v20, 31 -; VI-NEXT: v_readlane_b32 s86, v20, 30 -; VI-NEXT: v_readlane_b32 s85, v20, 29 -; VI-NEXT: v_readlane_b32 s84, v20, 28 -; VI-NEXT: v_readlane_b32 s83, v20, 27 -; VI-NEXT: v_readlane_b32 s82, v20, 26 -; VI-NEXT: v_readlane_b32 s81, v20, 25 -; VI-NEXT: v_readlane_b32 s80, v20, 24 -; VI-NEXT: v_readlane_b32 s71, v20, 23 -; VI-NEXT: v_readlane_b32 s70, v20, 22 -; VI-NEXT: v_readlane_b32 s69, v20, 21 -; VI-NEXT: v_readlane_b32 s68, v20, 20 -; VI-NEXT: v_readlane_b32 s67, v20, 19 -; VI-NEXT: v_readlane_b32 s66, v20, 18 -; VI-NEXT: v_readlane_b32 s65, v20, 17 -; VI-NEXT: v_readlane_b32 s64, v20, 16 -; VI-NEXT: v_readlane_b32 s55, v20, 15 -; VI-NEXT: v_readlane_b32 s54, v20, 14 -; VI-NEXT: v_readlane_b32 s53, v20, 13 -; VI-NEXT: v_readlane_b32 s52, v20, 12 -; VI-NEXT: v_readlane_b32 s51, v20, 11 -; VI-NEXT: v_readlane_b32 s50, v20, 10 -; VI-NEXT: v_readlane_b32 s49, v20, 9 -; VI-NEXT: v_readlane_b32 s48, v20, 8 -; VI-NEXT: v_readlane_b32 s39, v20, 7 -; VI-NEXT: v_readlane_b32 s38, v20, 6 -; VI-NEXT: v_readlane_b32 s37, v20, 5 -; VI-NEXT: v_readlane_b32 s36, v20, 4 -; VI-NEXT: v_readlane_b32 s35, v20, 3 -; VI-NEXT: v_readlane_b32 s34, v20, 2 -; VI-NEXT: v_readlane_b32 s31, v20, 1 -; VI-NEXT: v_readlane_b32 s30, v20, 0 +; VI-NEXT: v_readlane_b32 s87, v21, 31 +; VI-NEXT: v_readlane_b32 s86, v21, 30 +; VI-NEXT: v_readlane_b32 s85, v21, 29 +; VI-NEXT: v_readlane_b32 s84, v21, 28 +; VI-NEXT: v_readlane_b32 s83, v21, 27 +; VI-NEXT: v_readlane_b32 s82, v21, 26 +; VI-NEXT: v_readlane_b32 s81, v21, 25 +; VI-NEXT: v_readlane_b32 s80, v21, 24 +; VI-NEXT: v_readlane_b32 s71, v21, 23 +; VI-NEXT: v_readlane_b32 s70, v21, 22 +; VI-NEXT: v_readlane_b32 s69, v21, 21 +; VI-NEXT: v_readlane_b32 s68, v21, 20 +; VI-NEXT: v_readlane_b32 s67, v21, 19 +; VI-NEXT: v_readlane_b32 s66, v21, 18 +; VI-NEXT: v_readlane_b32 s65, v21, 17 +; VI-NEXT: v_readlane_b32 s64, v21, 16 +; VI-NEXT: v_readlane_b32 s55, v21, 15 +; VI-NEXT: v_readlane_b32 s54, v21, 14 +; VI-NEXT: v_readlane_b32 s53, v21, 13 +; VI-NEXT: v_readlane_b32 s52, v21, 12 +; VI-NEXT: v_readlane_b32 s51, v21, 11 +; VI-NEXT: v_readlane_b32 s50, v21, 10 +; VI-NEXT: v_readlane_b32 s49, v21, 9 +; VI-NEXT: v_readlane_b32 s48, v21, 8 +; VI-NEXT: v_readlane_b32 s39, v21, 7 +; VI-NEXT: v_readlane_b32 s38, v21, 6 +; VI-NEXT: v_readlane_b32 s37, v21, 5 +; VI-NEXT: v_readlane_b32 s36, v21, 4 +; VI-NEXT: v_readlane_b32 s35, v21, 3 +; VI-NEXT: v_readlane_b32 s34, v21, 2 +; VI-NEXT: v_readlane_b32 s31, v21, 1 +; VI-NEXT: v_readlane_b32 s30, v21, 0 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_setpc_b64 s[30:31] @@ -9525,10 +9581,10 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; VI-NEXT: ; implicit-def: $sgpr53 ; VI-NEXT: ; implicit-def: $sgpr52 ; VI-NEXT: ; implicit-def: $sgpr51 -; VI-NEXT: ; implicit-def: $sgpr57 -; VI-NEXT: ; implicit-def: $sgpr56 -; VI-NEXT: ; implicit-def: $sgpr47 -; VI-NEXT: ; implicit-def: $sgpr46 +; VI-NEXT: ; implicit-def: $sgpr29 +; VI-NEXT: ; implicit-def: $sgpr28 +; VI-NEXT: ; implicit-def: $sgpr27 +; VI-NEXT: ; implicit-def: $sgpr26 ; VI-NEXT: ; implicit-def: $sgpr50 ; VI-NEXT: ; implicit-def: $sgpr87 ; VI-NEXT: ; implicit-def: $sgpr86 @@ -9657,68 +9713,96 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; VI-NEXT: ; implicit-def: $sgpr60 ; VI-NEXT: ; kill: killed $sgpr60 ; VI-NEXT: ; implicit-def: $sgpr60 -; VI-NEXT: v_writelane_b32 v21, s60, 0 -; VI-NEXT: v_writelane_b32 v21, s61, 1 +; VI-NEXT: v_writelane_b32 v22, s60, 0 +; VI-NEXT: v_writelane_b32 v22, s61, 1 ; VI-NEXT: ; implicit-def: $sgpr60 -; VI-NEXT: v_writelane_b32 v21, s60, 2 -; VI-NEXT: v_writelane_b32 v21, s61, 3 +; VI-NEXT: v_writelane_b32 v22, s60, 2 +; VI-NEXT: v_writelane_b32 v22, s61, 3 ; VI-NEXT: ; implicit-def: $sgpr60 -; VI-NEXT: v_writelane_b32 v21, s60, 4 -; VI-NEXT: v_writelane_b32 v21, s61, 5 +; VI-NEXT: v_writelane_b32 v22, s60, 4 +; VI-NEXT: v_writelane_b32 v22, s61, 5 ; VI-NEXT: ; implicit-def: $sgpr60 -; VI-NEXT: v_writelane_b32 v21, s60, 6 -; VI-NEXT: v_writelane_b32 v21, s61, 7 +; VI-NEXT: v_writelane_b32 v22, s60, 6 +; VI-NEXT: v_writelane_b32 v22, s61, 7 ; VI-NEXT: s_branch .LBB13_2 ; ; GFX9-LABEL: bitcast_v32i32_to_v128i8_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v20, s30, 0 -; GFX9-NEXT: v_writelane_b32 v20, s31, 1 -; GFX9-NEXT: v_writelane_b32 v20, s34, 2 -; GFX9-NEXT: v_writelane_b32 v20, s35, 3 -; GFX9-NEXT: v_writelane_b32 v20, s36, 4 -; GFX9-NEXT: v_writelane_b32 v20, s37, 5 -; GFX9-NEXT: v_writelane_b32 v20, s38, 6 -; GFX9-NEXT: v_writelane_b32 v20, s39, 7 -; GFX9-NEXT: v_writelane_b32 v20, s48, 8 -; GFX9-NEXT: v_writelane_b32 v20, s49, 9 -; GFX9-NEXT: v_writelane_b32 v20, s50, 10 -; GFX9-NEXT: v_writelane_b32 v20, s51, 11 -; GFX9-NEXT: v_writelane_b32 v20, s52, 12 -; GFX9-NEXT: v_writelane_b32 v20, s53, 13 -; GFX9-NEXT: v_writelane_b32 v20, s54, 14 -; GFX9-NEXT: v_writelane_b32 v20, s55, 15 -; GFX9-NEXT: v_writelane_b32 v20, s64, 16 -; GFX9-NEXT: v_writelane_b32 v20, s65, 17 -; GFX9-NEXT: v_writelane_b32 v20, s66, 18 -; GFX9-NEXT: v_writelane_b32 v20, s67, 19 -; GFX9-NEXT: v_writelane_b32 v20, s68, 20 -; GFX9-NEXT: v_writelane_b32 v20, s69, 21 -; GFX9-NEXT: v_writelane_b32 v20, s70, 22 -; GFX9-NEXT: v_writelane_b32 v20, s71, 23 -; GFX9-NEXT: v_writelane_b32 v20, s80, 24 -; GFX9-NEXT: v_writelane_b32 v20, s81, 25 -; GFX9-NEXT: v_writelane_b32 v20, s82, 26 -; GFX9-NEXT: v_writelane_b32 v20, s83, 27 -; GFX9-NEXT: v_writelane_b32 v20, s84, 28 -; GFX9-NEXT: v_writelane_b32 v20, s85, 29 -; GFX9-NEXT: v_writelane_b32 v20, s86, 30 -; GFX9-NEXT: v_writelane_b32 v20, s87, 31 -; GFX9-NEXT: v_writelane_b32 v20, s96, 32 -; GFX9-NEXT: v_writelane_b32 v20, s97, 33 +; GFX9-NEXT: v_writelane_b32 v21, s30, 0 +; GFX9-NEXT: v_writelane_b32 v21, s31, 1 +; GFX9-NEXT: v_writelane_b32 v21, s34, 2 +; GFX9-NEXT: v_writelane_b32 v21, s35, 3 +; GFX9-NEXT: v_writelane_b32 v21, s36, 4 +; GFX9-NEXT: v_writelane_b32 v21, s37, 5 +; GFX9-NEXT: v_writelane_b32 v21, s38, 6 +; GFX9-NEXT: v_writelane_b32 v21, s39, 7 +; GFX9-NEXT: v_writelane_b32 v21, s48, 8 +; GFX9-NEXT: v_writelane_b32 v21, s49, 9 +; GFX9-NEXT: v_writelane_b32 v21, s50, 10 +; GFX9-NEXT: v_writelane_b32 v21, s51, 11 +; GFX9-NEXT: v_writelane_b32 v21, s52, 12 +; GFX9-NEXT: v_writelane_b32 v21, s53, 13 +; GFX9-NEXT: v_writelane_b32 v21, s54, 14 +; GFX9-NEXT: v_writelane_b32 v21, s55, 15 +; GFX9-NEXT: v_writelane_b32 v21, s64, 16 +; GFX9-NEXT: v_writelane_b32 v21, s65, 17 +; GFX9-NEXT: v_writelane_b32 v21, s66, 18 +; GFX9-NEXT: v_writelane_b32 v21, s67, 19 +; GFX9-NEXT: v_writelane_b32 v21, s68, 20 +; GFX9-NEXT: v_mov_b32_e32 v20, s16 +; GFX9-NEXT: v_writelane_b32 v21, s69, 21 +; GFX9-NEXT: v_readfirstlane_b32 s56, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s17 +; GFX9-NEXT: v_writelane_b32 v21, s70, 22 +; GFX9-NEXT: v_readfirstlane_b32 s57, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s18 +; GFX9-NEXT: v_writelane_b32 v21, s71, 23 +; GFX9-NEXT: v_readfirstlane_b32 s46, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s19 +; GFX9-NEXT: v_writelane_b32 v21, s80, 24 +; GFX9-NEXT: v_readfirstlane_b32 s47, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s20 +; GFX9-NEXT: v_writelane_b32 v21, s81, 25 +; GFX9-NEXT: v_readfirstlane_b32 s44, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s21 +; GFX9-NEXT: v_writelane_b32 v21, s82, 26 +; GFX9-NEXT: v_readfirstlane_b32 s45, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s22 +; GFX9-NEXT: v_writelane_b32 v21, s83, 27 +; GFX9-NEXT: v_readfirstlane_b32 s42, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s23 +; GFX9-NEXT: v_writelane_b32 v21, s84, 28 +; GFX9-NEXT: v_readfirstlane_b32 s43, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s24 +; GFX9-NEXT: v_writelane_b32 v21, s85, 29 +; GFX9-NEXT: v_readfirstlane_b32 s40, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s25 +; GFX9-NEXT: v_writelane_b32 v21, s86, 30 +; GFX9-NEXT: v_readfirstlane_b32 s41, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s26 +; GFX9-NEXT: v_writelane_b32 v21, s87, 31 +; GFX9-NEXT: v_readfirstlane_b32 s24, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s27 +; GFX9-NEXT: v_writelane_b32 v21, s96, 32 +; GFX9-NEXT: v_readfirstlane_b32 s25, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s28 +; GFX9-NEXT: v_writelane_b32 v21, s97, 33 +; GFX9-NEXT: v_readfirstlane_b32 s22, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s29 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; GFX9-NEXT: v_writelane_b32 v20, s98, 34 -; GFX9-NEXT: v_readfirstlane_b32 s44, v1 -; GFX9-NEXT: v_readfirstlane_b32 s45, v2 -; GFX9-NEXT: v_readfirstlane_b32 s42, v3 -; GFX9-NEXT: v_readfirstlane_b32 s43, v4 -; GFX9-NEXT: v_readfirstlane_b32 s40, v5 -; GFX9-NEXT: v_readfirstlane_b32 s41, v6 +; GFX9-NEXT: v_writelane_b32 v21, s98, 34 +; GFX9-NEXT: v_readfirstlane_b32 s23, v20 +; GFX9-NEXT: v_readfirstlane_b32 s20, v1 +; GFX9-NEXT: v_readfirstlane_b32 s21, v2 +; GFX9-NEXT: v_readfirstlane_b32 s18, v3 +; GFX9-NEXT: v_readfirstlane_b32 s19, v4 +; GFX9-NEXT: v_readfirstlane_b32 s16, v5 +; GFX9-NEXT: v_readfirstlane_b32 s17, v6 ; GFX9-NEXT: v_readfirstlane_b32 s14, v7 ; GFX9-NEXT: v_readfirstlane_b32 s15, v8 ; GFX9-NEXT: v_readfirstlane_b32 s12, v9 @@ -9730,485 +9814,484 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX9-NEXT: v_readfirstlane_b32 s6, v15 ; GFX9-NEXT: v_readfirstlane_b32 s7, v16 ; GFX9-NEXT: v_readfirstlane_b32 s4, v17 -; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_and_b64 s[26:27], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s5, v18 -; GFX9-NEXT: v_writelane_b32 v20, s99, 35 -; GFX9-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane +; GFX9-NEXT: v_writelane_b32 v21, s99, 35 +; GFX9-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane ; GFX9-NEXT: s_cbranch_scc0 .LBB13_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false -; GFX9-NEXT: s_lshr_b32 s46, s5, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 2 -; GFX9-NEXT: s_lshr_b32 s46, s5, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 3 -; GFX9-NEXT: s_lshr_b32 s46, s5, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 4 -; GFX9-NEXT: s_lshr_b32 s46, s4, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 5 -; GFX9-NEXT: s_lshr_b32 s46, s4, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 6 -; GFX9-NEXT: s_lshr_b32 s46, s7, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 7 -; GFX9-NEXT: s_lshr_b32 s46, s7, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 8 -; GFX9-NEXT: s_lshr_b32 s46, s7, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 9 -; GFX9-NEXT: s_lshr_b32 s46, s6, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 10 -; GFX9-NEXT: s_lshr_b32 s46, s6, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 11 -; GFX9-NEXT: s_lshr_b32 s46, s9, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 12 -; GFX9-NEXT: s_lshr_b32 s46, s9, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 13 -; GFX9-NEXT: s_lshr_b32 s46, s9, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 14 -; GFX9-NEXT: s_lshr_b32 s46, s8, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 15 -; GFX9-NEXT: s_lshr_b32 s46, s8, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 16 -; GFX9-NEXT: s_lshr_b32 s46, s11, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 17 -; GFX9-NEXT: s_lshr_b32 s46, s11, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 18 -; GFX9-NEXT: s_lshr_b32 s46, s11, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 19 -; GFX9-NEXT: s_lshr_b32 s46, s10, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 20 -; GFX9-NEXT: s_lshr_b32 s46, s10, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 21 -; GFX9-NEXT: s_lshr_b32 s46, s13, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 22 -; GFX9-NEXT: s_lshr_b32 s46, s13, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 23 -; GFX9-NEXT: s_lshr_b32 s46, s13, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 24 -; GFX9-NEXT: s_lshr_b32 s46, s12, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 25 -; GFX9-NEXT: s_lshr_b32 s46, s12, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 26 -; GFX9-NEXT: s_lshr_b32 s46, s15, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 27 -; GFX9-NEXT: s_lshr_b32 s46, s15, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 28 -; GFX9-NEXT: s_lshr_b32 s46, s15, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 29 -; GFX9-NEXT: s_lshr_b32 s46, s14, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 30 -; GFX9-NEXT: s_lshr_b32 s46, s14, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 31 -; GFX9-NEXT: s_lshr_b32 s46, s41, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 32 -; GFX9-NEXT: s_lshr_b32 s46, s41, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 33 -; GFX9-NEXT: s_lshr_b32 s46, s41, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 34 -; GFX9-NEXT: s_lshr_b32 s46, s40, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 35 -; GFX9-NEXT: s_lshr_b32 s46, s40, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 36 -; GFX9-NEXT: s_lshr_b32 s46, s43, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 37 -; GFX9-NEXT: s_lshr_b32 s46, s43, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 38 -; GFX9-NEXT: s_lshr_b32 s46, s43, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 39 -; GFX9-NEXT: s_lshr_b32 s46, s42, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 40 -; GFX9-NEXT: s_lshr_b32 s46, s42, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 41 -; GFX9-NEXT: s_lshr_b32 s46, s45, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 42 -; GFX9-NEXT: s_lshr_b32 s46, s45, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 43 -; GFX9-NEXT: s_lshr_b32 s46, s45, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 44 -; GFX9-NEXT: s_lshr_b32 s46, s44, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 45 -; GFX9-NEXT: s_lshr_b32 s46, s44, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 46 -; GFX9-NEXT: s_lshr_b32 s46, s29, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 47 -; GFX9-NEXT: s_lshr_b32 s46, s29, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 48 -; GFX9-NEXT: s_lshr_b32 s46, s29, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 49 -; GFX9-NEXT: s_lshr_b32 s46, s28, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 50 -; GFX9-NEXT: s_lshr_b64 s[56:57], s[4:5], 24 -; GFX9-NEXT: v_writelane_b32 v21, s56, 0 -; GFX9-NEXT: s_lshr_b32 s82, s28, 8 -; GFX9-NEXT: s_lshr_b32 s83, s27, 24 -; GFX9-NEXT: s_lshr_b32 s81, s27, 16 -; GFX9-NEXT: s_lshr_b32 s84, s27, 8 -; GFX9-NEXT: s_lshr_b32 s85, s26, 16 -; GFX9-NEXT: s_lshr_b32 s86, s26, 8 -; GFX9-NEXT: s_lshr_b32 s87, s25, 24 -; GFX9-NEXT: s_lshr_b32 s96, s25, 16 -; GFX9-NEXT: s_lshr_b32 s97, s25, 8 -; GFX9-NEXT: s_lshr_b32 s98, s24, 16 -; GFX9-NEXT: s_lshr_b32 s99, s24, 8 -; GFX9-NEXT: s_lshr_b32 s38, s23, 24 -; GFX9-NEXT: s_lshr_b32 s39, s23, 16 -; GFX9-NEXT: s_lshr_b32 s48, s23, 8 -; GFX9-NEXT: s_lshr_b32 s49, s22, 16 -; GFX9-NEXT: s_lshr_b32 s50, s22, 8 -; GFX9-NEXT: s_lshr_b32 s51, s21, 24 -; GFX9-NEXT: s_lshr_b32 s52, s21, 16 -; GFX9-NEXT: s_lshr_b32 s53, s21, 8 -; GFX9-NEXT: s_lshr_b32 s54, s20, 16 -; GFX9-NEXT: s_lshr_b32 s55, s20, 8 -; GFX9-NEXT: s_lshr_b32 s64, s19, 24 -; GFX9-NEXT: s_lshr_b32 s65, s19, 16 -; GFX9-NEXT: s_lshr_b32 s66, s19, 8 -; GFX9-NEXT: s_lshr_b32 s67, s18, 16 -; GFX9-NEXT: s_lshr_b32 s68, s18, 8 -; GFX9-NEXT: s_lshr_b32 s69, s17, 24 -; GFX9-NEXT: s_lshr_b32 s70, s17, 16 -; GFX9-NEXT: s_lshr_b32 s71, s17, 8 -; GFX9-NEXT: s_lshr_b32 s80, s16, 16 -; GFX9-NEXT: s_lshr_b32 s46, s16, 8 -; GFX9-NEXT: v_writelane_b32 v21, s57, 1 -; GFX9-NEXT: s_lshr_b64 s[56:57], s[6:7], 24 +; GFX9-NEXT: s_lshr_b32 s26, s5, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 2 +; GFX9-NEXT: s_lshr_b32 s26, s5, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 3 +; GFX9-NEXT: s_lshr_b32 s26, s5, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 4 +; GFX9-NEXT: s_lshr_b32 s26, s4, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 5 +; GFX9-NEXT: s_lshr_b32 s26, s4, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 6 +; GFX9-NEXT: s_lshr_b32 s26, s7, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 7 +; GFX9-NEXT: s_lshr_b32 s26, s7, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 8 +; GFX9-NEXT: s_lshr_b32 s26, s7, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 9 +; GFX9-NEXT: s_lshr_b32 s26, s6, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 10 +; GFX9-NEXT: s_lshr_b32 s26, s6, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 11 +; GFX9-NEXT: s_lshr_b32 s26, s9, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 12 +; GFX9-NEXT: s_lshr_b32 s26, s9, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 13 +; GFX9-NEXT: s_lshr_b32 s26, s9, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 14 +; GFX9-NEXT: s_lshr_b32 s26, s8, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 15 +; GFX9-NEXT: s_lshr_b32 s26, s8, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 16 +; GFX9-NEXT: s_lshr_b32 s26, s11, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 17 +; GFX9-NEXT: s_lshr_b32 s26, s11, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 18 +; GFX9-NEXT: s_lshr_b32 s26, s11, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 19 +; GFX9-NEXT: s_lshr_b32 s26, s10, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 20 +; GFX9-NEXT: s_lshr_b32 s26, s10, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 21 +; GFX9-NEXT: s_lshr_b32 s26, s13, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 22 +; GFX9-NEXT: s_lshr_b32 s26, s13, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 23 +; GFX9-NEXT: s_lshr_b32 s26, s13, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 24 +; GFX9-NEXT: s_lshr_b32 s26, s12, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 25 +; GFX9-NEXT: s_lshr_b32 s26, s12, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 26 +; GFX9-NEXT: s_lshr_b32 s26, s15, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 27 +; GFX9-NEXT: s_lshr_b32 s26, s15, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 28 +; GFX9-NEXT: s_lshr_b32 s26, s15, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 29 +; GFX9-NEXT: s_lshr_b32 s26, s14, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 30 +; GFX9-NEXT: s_lshr_b32 s26, s14, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 31 +; GFX9-NEXT: s_lshr_b32 s26, s17, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 32 +; GFX9-NEXT: s_lshr_b32 s26, s17, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 33 +; GFX9-NEXT: s_lshr_b32 s26, s17, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 34 +; GFX9-NEXT: s_lshr_b32 s26, s16, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 35 +; GFX9-NEXT: s_lshr_b32 s26, s16, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 36 +; GFX9-NEXT: s_lshr_b32 s26, s19, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 37 +; GFX9-NEXT: s_lshr_b32 s26, s19, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 38 +; GFX9-NEXT: s_lshr_b32 s26, s19, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 39 +; GFX9-NEXT: s_lshr_b32 s26, s18, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 40 +; GFX9-NEXT: s_lshr_b32 s26, s18, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 41 +; GFX9-NEXT: s_lshr_b32 s26, s21, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 42 +; GFX9-NEXT: s_lshr_b32 s26, s21, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 43 +; GFX9-NEXT: s_lshr_b32 s26, s21, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 44 +; GFX9-NEXT: s_lshr_b32 s26, s20, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 45 +; GFX9-NEXT: s_lshr_b32 s26, s20, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 46 +; GFX9-NEXT: s_lshr_b32 s26, s23, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 47 +; GFX9-NEXT: s_lshr_b32 s26, s23, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 48 +; GFX9-NEXT: s_lshr_b32 s26, s23, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 49 +; GFX9-NEXT: s_lshr_b32 s26, s22, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 50 +; GFX9-NEXT: s_lshr_b64 s[28:29], s[4:5], 24 +; GFX9-NEXT: v_writelane_b32 v22, s28, 0 +; GFX9-NEXT: s_lshr_b32 s82, s22, 8 +; GFX9-NEXT: s_lshr_b32 s83, s25, 24 +; GFX9-NEXT: s_lshr_b32 s81, s25, 16 +; GFX9-NEXT: s_lshr_b32 s84, s25, 8 +; GFX9-NEXT: s_lshr_b32 s85, s24, 16 +; GFX9-NEXT: s_lshr_b32 s86, s24, 8 +; GFX9-NEXT: s_lshr_b32 s87, s41, 24 +; GFX9-NEXT: s_lshr_b32 s96, s41, 16 +; GFX9-NEXT: s_lshr_b32 s97, s41, 8 +; GFX9-NEXT: s_lshr_b32 s98, s40, 16 +; GFX9-NEXT: s_lshr_b32 s99, s40, 8 +; GFX9-NEXT: s_lshr_b32 s38, s43, 24 +; GFX9-NEXT: s_lshr_b32 s39, s43, 16 +; GFX9-NEXT: s_lshr_b32 s48, s43, 8 +; GFX9-NEXT: s_lshr_b32 s49, s42, 16 +; GFX9-NEXT: s_lshr_b32 s50, s42, 8 +; GFX9-NEXT: s_lshr_b32 s51, s45, 24 +; GFX9-NEXT: s_lshr_b32 s52, s45, 16 +; GFX9-NEXT: s_lshr_b32 s53, s45, 8 +; GFX9-NEXT: s_lshr_b32 s54, s44, 16 +; GFX9-NEXT: s_lshr_b32 s55, s44, 8 +; GFX9-NEXT: s_lshr_b32 s64, s47, 24 +; GFX9-NEXT: s_lshr_b32 s65, s47, 16 +; GFX9-NEXT: s_lshr_b32 s66, s47, 8 +; GFX9-NEXT: s_lshr_b32 s67, s46, 16 +; GFX9-NEXT: s_lshr_b32 s68, s46, 8 +; GFX9-NEXT: s_lshr_b32 s69, s57, 24 +; GFX9-NEXT: s_lshr_b32 s70, s57, 16 +; GFX9-NEXT: s_lshr_b32 s71, s57, 8 +; GFX9-NEXT: s_lshr_b32 s80, s56, 16 +; GFX9-NEXT: s_lshr_b32 s26, s56, 8 +; GFX9-NEXT: v_writelane_b32 v22, s29, 1 +; GFX9-NEXT: s_lshr_b64 s[28:29], s[6:7], 24 ; GFX9-NEXT: s_lshr_b64 s[58:59], s[8:9], 24 ; GFX9-NEXT: s_lshr_b64 s[60:61], s[10:11], 24 ; GFX9-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 ; GFX9-NEXT: s_lshr_b64 s[72:73], s[14:15], 24 -; GFX9-NEXT: s_lshr_b64 s[74:75], s[40:41], 24 -; GFX9-NEXT: s_lshr_b64 s[76:77], s[42:43], 24 -; GFX9-NEXT: s_lshr_b64 s[78:79], s[44:45], 24 -; GFX9-NEXT: s_lshr_b64 s[88:89], s[28:29], 24 -; GFX9-NEXT: s_lshr_b64 s[90:91], s[26:27], 24 -; GFX9-NEXT: s_lshr_b64 s[92:93], s[24:25], 24 -; GFX9-NEXT: s_lshr_b64 s[94:95], s[22:23], 24 -; GFX9-NEXT: s_lshr_b64 s[30:31], s[20:21], 24 -; GFX9-NEXT: s_lshr_b64 s[34:35], s[18:19], 24 -; GFX9-NEXT: s_lshr_b64 s[36:37], s[16:17], 24 +; GFX9-NEXT: s_lshr_b64 s[74:75], s[16:17], 24 +; GFX9-NEXT: s_lshr_b64 s[76:77], s[18:19], 24 +; GFX9-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 +; GFX9-NEXT: s_lshr_b64 s[88:89], s[22:23], 24 +; GFX9-NEXT: s_lshr_b64 s[90:91], s[24:25], 24 +; GFX9-NEXT: s_lshr_b64 s[92:93], s[40:41], 24 +; GFX9-NEXT: s_lshr_b64 s[94:95], s[42:43], 24 +; GFX9-NEXT: s_lshr_b64 s[30:31], s[44:45], 24 +; GFX9-NEXT: s_lshr_b64 s[34:35], s[46:47], 24 +; GFX9-NEXT: s_lshr_b64 s[36:37], s[56:57], 24 ; GFX9-NEXT: s_cbranch_execnz .LBB13_3 ; GFX9-NEXT: .LBB13_2: ; %cmp.true ; GFX9-NEXT: s_add_i32 s5, s5, 3 -; GFX9-NEXT: s_lshr_b32 s46, s5, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 2 -; GFX9-NEXT: s_lshr_b32 s46, s5, 16 +; GFX9-NEXT: s_lshr_b32 s26, s5, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 2 +; GFX9-NEXT: s_lshr_b32 s26, s5, 16 ; GFX9-NEXT: s_add_i32 s4, s4, 3 -; GFX9-NEXT: v_writelane_b32 v21, s46, 3 -; GFX9-NEXT: s_lshr_b32 s46, s5, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 4 -; GFX9-NEXT: s_lshr_b32 s46, s4, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 3 +; GFX9-NEXT: s_lshr_b32 s26, s5, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 4 +; GFX9-NEXT: s_lshr_b32 s26, s4, 16 ; GFX9-NEXT: s_add_i32 s7, s7, 3 -; GFX9-NEXT: v_writelane_b32 v21, s46, 5 -; GFX9-NEXT: s_lshr_b32 s46, s4, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 6 -; GFX9-NEXT: s_lshr_b32 s46, s7, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 7 -; GFX9-NEXT: s_lshr_b32 s46, s7, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 5 +; GFX9-NEXT: s_lshr_b32 s26, s4, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 6 +; GFX9-NEXT: s_lshr_b32 s26, s7, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 7 +; GFX9-NEXT: s_lshr_b32 s26, s7, 16 ; GFX9-NEXT: s_add_i32 s6, s6, 3 -; GFX9-NEXT: v_writelane_b32 v21, s46, 8 -; GFX9-NEXT: s_lshr_b32 s46, s7, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 9 -; GFX9-NEXT: s_lshr_b32 s46, s6, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 8 +; GFX9-NEXT: s_lshr_b32 s26, s7, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 9 +; GFX9-NEXT: s_lshr_b32 s26, s6, 16 ; GFX9-NEXT: s_add_i32 s9, s9, 3 -; GFX9-NEXT: v_writelane_b32 v21, s46, 10 -; GFX9-NEXT: s_lshr_b32 s46, s6, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 11 -; GFX9-NEXT: s_lshr_b32 s46, s9, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 12 -; GFX9-NEXT: s_lshr_b32 s46, s9, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 10 +; GFX9-NEXT: s_lshr_b32 s26, s6, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 11 +; GFX9-NEXT: s_lshr_b32 s26, s9, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 12 +; GFX9-NEXT: s_lshr_b32 s26, s9, 16 ; GFX9-NEXT: s_add_i32 s8, s8, 3 -; GFX9-NEXT: v_writelane_b32 v21, s46, 13 -; GFX9-NEXT: s_lshr_b32 s46, s9, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 14 -; GFX9-NEXT: s_lshr_b32 s46, s8, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 13 +; GFX9-NEXT: s_lshr_b32 s26, s9, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 14 +; GFX9-NEXT: s_lshr_b32 s26, s8, 16 ; GFX9-NEXT: s_add_i32 s11, s11, 3 -; GFX9-NEXT: v_writelane_b32 v21, s46, 15 -; GFX9-NEXT: s_lshr_b32 s46, s8, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 16 -; GFX9-NEXT: s_lshr_b32 s46, s11, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 17 -; GFX9-NEXT: s_lshr_b32 s46, s11, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 15 +; GFX9-NEXT: s_lshr_b32 s26, s8, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 16 +; GFX9-NEXT: s_lshr_b32 s26, s11, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 17 +; GFX9-NEXT: s_lshr_b32 s26, s11, 16 ; GFX9-NEXT: s_add_i32 s10, s10, 3 -; GFX9-NEXT: v_writelane_b32 v21, s46, 18 -; GFX9-NEXT: s_lshr_b32 s46, s11, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 19 -; GFX9-NEXT: s_lshr_b32 s46, s10, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 18 +; GFX9-NEXT: s_lshr_b32 s26, s11, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 19 +; GFX9-NEXT: s_lshr_b32 s26, s10, 16 ; GFX9-NEXT: s_add_i32 s13, s13, 3 -; GFX9-NEXT: v_writelane_b32 v21, s46, 20 -; GFX9-NEXT: s_lshr_b32 s46, s10, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 21 -; GFX9-NEXT: s_lshr_b32 s46, s13, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 22 -; GFX9-NEXT: s_lshr_b32 s46, s13, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 20 +; GFX9-NEXT: s_lshr_b32 s26, s10, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 21 +; GFX9-NEXT: s_lshr_b32 s26, s13, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 22 +; GFX9-NEXT: s_lshr_b32 s26, s13, 16 ; GFX9-NEXT: s_add_i32 s12, s12, 3 -; GFX9-NEXT: v_writelane_b32 v21, s46, 23 -; GFX9-NEXT: s_lshr_b32 s46, s13, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 24 -; GFX9-NEXT: s_lshr_b32 s46, s12, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 23 +; GFX9-NEXT: s_lshr_b32 s26, s13, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 24 +; GFX9-NEXT: s_lshr_b32 s26, s12, 16 ; GFX9-NEXT: s_add_i32 s15, s15, 3 -; GFX9-NEXT: v_writelane_b32 v21, s46, 25 -; GFX9-NEXT: s_lshr_b32 s46, s12, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 26 -; GFX9-NEXT: s_lshr_b32 s46, s15, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 27 -; GFX9-NEXT: s_lshr_b32 s46, s15, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 25 +; GFX9-NEXT: s_lshr_b32 s26, s12, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 26 +; GFX9-NEXT: s_lshr_b32 s26, s15, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 27 +; GFX9-NEXT: s_lshr_b32 s26, s15, 16 ; GFX9-NEXT: s_add_i32 s14, s14, 3 -; GFX9-NEXT: v_writelane_b32 v21, s46, 28 -; GFX9-NEXT: s_lshr_b32 s46, s15, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 29 -; GFX9-NEXT: s_lshr_b32 s46, s14, 16 -; GFX9-NEXT: s_add_i32 s41, s41, 3 -; GFX9-NEXT: v_writelane_b32 v21, s46, 30 -; GFX9-NEXT: s_lshr_b32 s46, s14, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 31 -; GFX9-NEXT: s_lshr_b32 s46, s41, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 32 -; GFX9-NEXT: s_lshr_b32 s46, s41, 16 -; GFX9-NEXT: s_add_i32 s40, s40, 3 -; GFX9-NEXT: v_writelane_b32 v21, s46, 33 -; GFX9-NEXT: s_lshr_b32 s46, s41, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 34 -; GFX9-NEXT: s_lshr_b32 s46, s40, 16 -; GFX9-NEXT: s_add_i32 s43, s43, 3 -; GFX9-NEXT: v_writelane_b32 v21, s46, 35 -; GFX9-NEXT: s_lshr_b32 s46, s40, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 36 -; GFX9-NEXT: s_lshr_b32 s46, s43, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 37 -; GFX9-NEXT: s_lshr_b32 s46, s43, 16 -; GFX9-NEXT: s_add_i32 s42, s42, 3 -; GFX9-NEXT: v_writelane_b32 v21, s46, 38 -; GFX9-NEXT: s_lshr_b32 s46, s43, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 39 -; GFX9-NEXT: s_lshr_b32 s46, s42, 16 -; GFX9-NEXT: s_add_i32 s45, s45, 3 -; GFX9-NEXT: v_writelane_b32 v21, s46, 40 -; GFX9-NEXT: s_lshr_b32 s46, s42, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 41 -; GFX9-NEXT: s_lshr_b32 s46, s45, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 42 -; GFX9-NEXT: s_lshr_b32 s46, s45, 16 -; GFX9-NEXT: s_add_i32 s44, s44, 3 -; GFX9-NEXT: v_writelane_b32 v21, s46, 43 -; GFX9-NEXT: s_lshr_b32 s46, s45, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 44 -; GFX9-NEXT: s_lshr_b32 s46, s44, 16 -; GFX9-NEXT: s_add_i32 s29, s29, 3 -; GFX9-NEXT: v_writelane_b32 v21, s46, 45 -; GFX9-NEXT: s_lshr_b32 s46, s44, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 46 -; GFX9-NEXT: s_lshr_b32 s46, s29, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 47 -; GFX9-NEXT: s_lshr_b32 s46, s29, 16 -; GFX9-NEXT: s_add_i32 s28, s28, 3 -; GFX9-NEXT: v_writelane_b32 v21, s46, 48 -; GFX9-NEXT: s_lshr_b32 s46, s29, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 49 -; GFX9-NEXT: s_lshr_b32 s46, s28, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 50 -; GFX9-NEXT: s_lshr_b64 s[56:57], s[4:5], 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 28 +; GFX9-NEXT: s_lshr_b32 s26, s15, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 29 +; GFX9-NEXT: s_lshr_b32 s26, s14, 16 ; GFX9-NEXT: s_add_i32 s17, s17, 3 +; GFX9-NEXT: v_writelane_b32 v22, s26, 30 +; GFX9-NEXT: s_lshr_b32 s26, s14, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 31 +; GFX9-NEXT: s_lshr_b32 s26, s17, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 32 +; GFX9-NEXT: s_lshr_b32 s26, s17, 16 ; GFX9-NEXT: s_add_i32 s16, s16, 3 +; GFX9-NEXT: v_writelane_b32 v22, s26, 33 +; GFX9-NEXT: s_lshr_b32 s26, s17, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 34 +; GFX9-NEXT: s_lshr_b32 s26, s16, 16 ; GFX9-NEXT: s_add_i32 s19, s19, 3 +; GFX9-NEXT: v_writelane_b32 v22, s26, 35 +; GFX9-NEXT: s_lshr_b32 s26, s16, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 36 +; GFX9-NEXT: s_lshr_b32 s26, s19, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 37 +; GFX9-NEXT: s_lshr_b32 s26, s19, 16 ; GFX9-NEXT: s_add_i32 s18, s18, 3 +; GFX9-NEXT: v_writelane_b32 v22, s26, 38 +; GFX9-NEXT: s_lshr_b32 s26, s19, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 39 +; GFX9-NEXT: s_lshr_b32 s26, s18, 16 ; GFX9-NEXT: s_add_i32 s21, s21, 3 +; GFX9-NEXT: v_writelane_b32 v22, s26, 40 +; GFX9-NEXT: s_lshr_b32 s26, s18, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 41 +; GFX9-NEXT: s_lshr_b32 s26, s21, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 42 +; GFX9-NEXT: s_lshr_b32 s26, s21, 16 ; GFX9-NEXT: s_add_i32 s20, s20, 3 +; GFX9-NEXT: v_writelane_b32 v22, s26, 43 +; GFX9-NEXT: s_lshr_b32 s26, s21, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 44 +; GFX9-NEXT: s_lshr_b32 s26, s20, 16 ; GFX9-NEXT: s_add_i32 s23, s23, 3 +; GFX9-NEXT: v_writelane_b32 v22, s26, 45 +; GFX9-NEXT: s_lshr_b32 s26, s20, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 46 +; GFX9-NEXT: s_lshr_b32 s26, s23, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 47 +; GFX9-NEXT: s_lshr_b32 s26, s23, 16 ; GFX9-NEXT: s_add_i32 s22, s22, 3 +; GFX9-NEXT: v_writelane_b32 v22, s26, 48 +; GFX9-NEXT: s_lshr_b32 s26, s23, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 49 +; GFX9-NEXT: s_lshr_b32 s26, s22, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 50 +; GFX9-NEXT: s_lshr_b64 s[28:29], s[4:5], 24 +; GFX9-NEXT: s_add_i32 s57, s57, 3 +; GFX9-NEXT: s_add_i32 s56, s56, 3 +; GFX9-NEXT: s_add_i32 s47, s47, 3 +; GFX9-NEXT: s_add_i32 s46, s46, 3 +; GFX9-NEXT: s_add_i32 s45, s45, 3 +; GFX9-NEXT: s_add_i32 s44, s44, 3 +; GFX9-NEXT: s_add_i32 s43, s43, 3 +; GFX9-NEXT: s_add_i32 s42, s42, 3 +; GFX9-NEXT: s_add_i32 s41, s41, 3 +; GFX9-NEXT: s_add_i32 s40, s40, 3 ; GFX9-NEXT: s_add_i32 s25, s25, 3 ; GFX9-NEXT: s_add_i32 s24, s24, 3 -; GFX9-NEXT: s_add_i32 s27, s27, 3 -; GFX9-NEXT: s_add_i32 s26, s26, 3 -; GFX9-NEXT: v_writelane_b32 v21, s56, 0 -; GFX9-NEXT: s_lshr_b32 s82, s28, 8 -; GFX9-NEXT: s_lshr_b32 s83, s27, 24 -; GFX9-NEXT: s_lshr_b32 s81, s27, 16 -; GFX9-NEXT: s_lshr_b32 s84, s27, 8 -; GFX9-NEXT: s_lshr_b32 s85, s26, 16 -; GFX9-NEXT: s_lshr_b32 s86, s26, 8 -; GFX9-NEXT: s_lshr_b32 s87, s25, 24 -; GFX9-NEXT: s_lshr_b32 s96, s25, 16 -; GFX9-NEXT: s_lshr_b32 s97, s25, 8 -; GFX9-NEXT: s_lshr_b32 s98, s24, 16 -; GFX9-NEXT: s_lshr_b32 s99, s24, 8 -; GFX9-NEXT: s_lshr_b32 s38, s23, 24 -; GFX9-NEXT: s_lshr_b32 s39, s23, 16 -; GFX9-NEXT: s_lshr_b32 s48, s23, 8 -; GFX9-NEXT: s_lshr_b32 s49, s22, 16 -; GFX9-NEXT: s_lshr_b32 s50, s22, 8 -; GFX9-NEXT: s_lshr_b32 s51, s21, 24 -; GFX9-NEXT: s_lshr_b32 s52, s21, 16 -; GFX9-NEXT: s_lshr_b32 s53, s21, 8 -; GFX9-NEXT: s_lshr_b32 s54, s20, 16 -; GFX9-NEXT: s_lshr_b32 s55, s20, 8 -; GFX9-NEXT: s_lshr_b32 s64, s19, 24 -; GFX9-NEXT: s_lshr_b32 s65, s19, 16 -; GFX9-NEXT: s_lshr_b32 s66, s19, 8 -; GFX9-NEXT: s_lshr_b32 s67, s18, 16 -; GFX9-NEXT: s_lshr_b32 s68, s18, 8 -; GFX9-NEXT: s_lshr_b32 s69, s17, 24 -; GFX9-NEXT: s_lshr_b32 s70, s17, 16 -; GFX9-NEXT: s_lshr_b32 s71, s17, 8 -; GFX9-NEXT: s_lshr_b32 s80, s16, 16 -; GFX9-NEXT: s_lshr_b32 s46, s16, 8 -; GFX9-NEXT: v_writelane_b32 v21, s57, 1 -; GFX9-NEXT: s_lshr_b64 s[56:57], s[6:7], 24 +; GFX9-NEXT: v_writelane_b32 v22, s28, 0 +; GFX9-NEXT: s_lshr_b32 s82, s22, 8 +; GFX9-NEXT: s_lshr_b32 s83, s25, 24 +; GFX9-NEXT: s_lshr_b32 s81, s25, 16 +; GFX9-NEXT: s_lshr_b32 s84, s25, 8 +; GFX9-NEXT: s_lshr_b32 s85, s24, 16 +; GFX9-NEXT: s_lshr_b32 s86, s24, 8 +; GFX9-NEXT: s_lshr_b32 s87, s41, 24 +; GFX9-NEXT: s_lshr_b32 s96, s41, 16 +; GFX9-NEXT: s_lshr_b32 s97, s41, 8 +; GFX9-NEXT: s_lshr_b32 s98, s40, 16 +; GFX9-NEXT: s_lshr_b32 s99, s40, 8 +; GFX9-NEXT: s_lshr_b32 s38, s43, 24 +; GFX9-NEXT: s_lshr_b32 s39, s43, 16 +; GFX9-NEXT: s_lshr_b32 s48, s43, 8 +; GFX9-NEXT: s_lshr_b32 s49, s42, 16 +; GFX9-NEXT: s_lshr_b32 s50, s42, 8 +; GFX9-NEXT: s_lshr_b32 s51, s45, 24 +; GFX9-NEXT: s_lshr_b32 s52, s45, 16 +; GFX9-NEXT: s_lshr_b32 s53, s45, 8 +; GFX9-NEXT: s_lshr_b32 s54, s44, 16 +; GFX9-NEXT: s_lshr_b32 s55, s44, 8 +; GFX9-NEXT: s_lshr_b32 s64, s47, 24 +; GFX9-NEXT: s_lshr_b32 s65, s47, 16 +; GFX9-NEXT: s_lshr_b32 s66, s47, 8 +; GFX9-NEXT: s_lshr_b32 s67, s46, 16 +; GFX9-NEXT: s_lshr_b32 s68, s46, 8 +; GFX9-NEXT: s_lshr_b32 s69, s57, 24 +; GFX9-NEXT: s_lshr_b32 s70, s57, 16 +; GFX9-NEXT: s_lshr_b32 s71, s57, 8 +; GFX9-NEXT: s_lshr_b32 s80, s56, 16 +; GFX9-NEXT: s_lshr_b32 s26, s56, 8 +; GFX9-NEXT: v_writelane_b32 v22, s29, 1 +; GFX9-NEXT: s_lshr_b64 s[28:29], s[6:7], 24 ; GFX9-NEXT: s_lshr_b64 s[58:59], s[8:9], 24 ; GFX9-NEXT: s_lshr_b64 s[60:61], s[10:11], 24 ; GFX9-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 ; GFX9-NEXT: s_lshr_b64 s[72:73], s[14:15], 24 -; GFX9-NEXT: s_lshr_b64 s[74:75], s[40:41], 24 -; GFX9-NEXT: s_lshr_b64 s[76:77], s[42:43], 24 -; GFX9-NEXT: s_lshr_b64 s[78:79], s[44:45], 24 -; GFX9-NEXT: s_lshr_b64 s[88:89], s[28:29], 24 -; GFX9-NEXT: s_lshr_b64 s[90:91], s[26:27], 24 -; GFX9-NEXT: s_lshr_b64 s[92:93], s[24:25], 24 -; GFX9-NEXT: s_lshr_b64 s[94:95], s[22:23], 24 -; GFX9-NEXT: s_lshr_b64 s[30:31], s[20:21], 24 -; GFX9-NEXT: s_lshr_b64 s[34:35], s[18:19], 24 -; GFX9-NEXT: s_lshr_b64 s[36:37], s[16:17], 24 +; GFX9-NEXT: s_lshr_b64 s[74:75], s[16:17], 24 +; GFX9-NEXT: s_lshr_b64 s[76:77], s[18:19], 24 +; GFX9-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 +; GFX9-NEXT: s_lshr_b64 s[88:89], s[22:23], 24 +; GFX9-NEXT: s_lshr_b64 s[90:91], s[24:25], 24 +; GFX9-NEXT: s_lshr_b64 s[92:93], s[40:41], 24 +; GFX9-NEXT: s_lshr_b64 s[94:95], s[42:43], 24 +; GFX9-NEXT: s_lshr_b64 s[30:31], s[44:45], 24 +; GFX9-NEXT: s_lshr_b64 s[34:35], s[46:47], 24 +; GFX9-NEXT: s_lshr_b64 s[36:37], s[56:57], 24 ; GFX9-NEXT: .LBB13_3: ; %end -; GFX9-NEXT: s_lshl_b32 s46, s46, 8 -; GFX9-NEXT: s_and_b32 s16, s16, 0xff -; GFX9-NEXT: s_or_b32 s16, s16, s46 -; GFX9-NEXT: s_lshl_b32 s46, s36, 8 -; GFX9-NEXT: s_and_b32 s47, s80, 0xff -; GFX9-NEXT: s_or_b32 s46, s47, s46 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s46, s46, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s46 -; GFX9-NEXT: v_mov_b32_e32 v1, s16 -; GFX9-NEXT: s_and_b32 s16, s17, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s71, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: s_and_b32 s17, s70, 0xff -; GFX9-NEXT: s_lshl_b32 s46, s69, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s46 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v2, s16 -; GFX9-NEXT: s_lshl_b32 s16, s68, 8 -; GFX9-NEXT: s_and_b32 s17, s18, 0xff -; GFX9-NEXT: s_or_b32 s16, s17, s16 -; GFX9-NEXT: s_lshl_b32 s17, s34, 8 -; GFX9-NEXT: s_and_b32 s18, s67, 0xff -; GFX9-NEXT: s_or_b32 s17, s18, s17 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v3, s16 -; GFX9-NEXT: s_and_b32 s16, s19, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s66, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: s_and_b32 s17, s65, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s64, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v4, s16 -; GFX9-NEXT: s_lshl_b32 s16, s55, 8 -; GFX9-NEXT: s_and_b32 s17, s20, 0xff -; GFX9-NEXT: s_or_b32 s16, s17, s16 -; GFX9-NEXT: s_lshl_b32 s17, s30, 8 -; GFX9-NEXT: s_and_b32 s18, s54, 0xff -; GFX9-NEXT: s_or_b32 s17, s18, s17 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v5, s16 -; GFX9-NEXT: s_and_b32 s16, s21, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s53, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: s_and_b32 s17, s52, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s51, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v6, s16 -; GFX9-NEXT: s_lshl_b32 s16, s50, 8 -; GFX9-NEXT: s_and_b32 s17, s22, 0xff -; GFX9-NEXT: s_or_b32 s16, s17, s16 -; GFX9-NEXT: s_lshl_b32 s17, s94, 8 -; GFX9-NEXT: s_and_b32 s18, s49, 0xff -; GFX9-NEXT: s_or_b32 s17, s18, s17 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v7, s16 -; GFX9-NEXT: s_and_b32 s16, s23, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s48, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: s_and_b32 s17, s39, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s38, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v8, s16 -; GFX9-NEXT: s_lshl_b32 s16, s99, 8 -; GFX9-NEXT: s_and_b32 s17, s24, 0xff -; GFX9-NEXT: s_or_b32 s16, s17, s16 -; GFX9-NEXT: s_lshl_b32 s17, s92, 8 -; GFX9-NEXT: s_and_b32 s18, s98, 0xff -; GFX9-NEXT: s_or_b32 s17, s18, s17 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v9, s16 -; GFX9-NEXT: s_and_b32 s16, s25, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s97, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: s_and_b32 s17, s96, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s87, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v10, s16 -; GFX9-NEXT: s_lshl_b32 s16, s86, 8 -; GFX9-NEXT: s_and_b32 s17, s26, 0xff -; GFX9-NEXT: s_or_b32 s16, s17, s16 -; GFX9-NEXT: s_lshl_b32 s17, s90, 8 -; GFX9-NEXT: s_and_b32 s18, s85, 0xff -; GFX9-NEXT: s_or_b32 s17, s18, s17 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v11, s16 -; GFX9-NEXT: s_and_b32 s16, s27, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s84, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: s_and_b32 s17, s81, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s83, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v12, s16 -; GFX9-NEXT: s_lshl_b32 s16, s82, 8 -; GFX9-NEXT: s_and_b32 s17, s28, 0xff -; GFX9-NEXT: v_readlane_b32 s18, v21, 50 -; GFX9-NEXT: s_or_b32 s16, s17, s16 -; GFX9-NEXT: s_lshl_b32 s17, s88, 8 -; GFX9-NEXT: s_and_b32 s18, s18, 0xff -; GFX9-NEXT: s_or_b32 s17, s18, s17 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 49 -; GFX9-NEXT: v_mov_b32_e32 v13, s16 -; GFX9-NEXT: s_and_b32 s16, s29, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s17, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 48 -; GFX9-NEXT: v_readlane_b32 s18, v21, 47 -; GFX9-NEXT: s_and_b32 s17, s17, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s18, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 46 +; GFX9-NEXT: s_lshl_b32 s26, s26, 8 +; GFX9-NEXT: s_and_b32 s27, s56, 0xff +; GFX9-NEXT: s_or_b32 s26, s27, s26 +; GFX9-NEXT: s_lshl_b32 s27, s36, 8 +; GFX9-NEXT: s_and_b32 s29, s80, 0xff +; GFX9-NEXT: s_or_b32 s27, s29, s27 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v1, s26 +; GFX9-NEXT: s_and_b32 s26, s57, 0xff +; GFX9-NEXT: s_lshl_b32 s27, s71, 8 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: s_and_b32 s27, s70, 0xff +; GFX9-NEXT: s_lshl_b32 s29, s69, 8 +; GFX9-NEXT: s_or_b32 s27, s27, s29 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v2, s26 +; GFX9-NEXT: s_lshl_b32 s26, s68, 8 +; GFX9-NEXT: s_and_b32 s27, s46, 0xff +; GFX9-NEXT: s_or_b32 s26, s27, s26 +; GFX9-NEXT: s_lshl_b32 s27, s34, 8 +; GFX9-NEXT: s_and_b32 s29, s67, 0xff +; GFX9-NEXT: s_or_b32 s27, s29, s27 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v3, s26 +; GFX9-NEXT: s_and_b32 s26, s47, 0xff +; GFX9-NEXT: s_lshl_b32 s27, s66, 8 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: s_and_b32 s27, s65, 0xff +; GFX9-NEXT: s_lshl_b32 s29, s64, 8 +; GFX9-NEXT: s_or_b32 s27, s27, s29 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v4, s26 +; GFX9-NEXT: s_lshl_b32 s26, s55, 8 +; GFX9-NEXT: s_and_b32 s27, s44, 0xff +; GFX9-NEXT: s_or_b32 s26, s27, s26 +; GFX9-NEXT: s_lshl_b32 s27, s30, 8 +; GFX9-NEXT: s_and_b32 s29, s54, 0xff +; GFX9-NEXT: s_or_b32 s27, s29, s27 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v5, s26 +; GFX9-NEXT: s_and_b32 s26, s45, 0xff +; GFX9-NEXT: s_lshl_b32 s27, s53, 8 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: s_and_b32 s27, s52, 0xff +; GFX9-NEXT: s_lshl_b32 s29, s51, 8 +; GFX9-NEXT: s_or_b32 s27, s27, s29 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v6, s26 +; GFX9-NEXT: s_lshl_b32 s26, s50, 8 +; GFX9-NEXT: s_and_b32 s27, s42, 0xff +; GFX9-NEXT: s_or_b32 s26, s27, s26 +; GFX9-NEXT: s_lshl_b32 s27, s94, 8 +; GFX9-NEXT: s_and_b32 s29, s49, 0xff +; GFX9-NEXT: s_or_b32 s27, s29, s27 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v7, s26 +; GFX9-NEXT: s_and_b32 s26, s43, 0xff +; GFX9-NEXT: s_lshl_b32 s27, s48, 8 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: s_and_b32 s27, s39, 0xff +; GFX9-NEXT: s_lshl_b32 s29, s38, 8 +; GFX9-NEXT: s_or_b32 s27, s27, s29 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v8, s26 +; GFX9-NEXT: s_lshl_b32 s26, s99, 8 +; GFX9-NEXT: s_and_b32 s27, s40, 0xff +; GFX9-NEXT: s_or_b32 s26, s27, s26 +; GFX9-NEXT: s_lshl_b32 s27, s92, 8 +; GFX9-NEXT: s_and_b32 s29, s98, 0xff +; GFX9-NEXT: s_or_b32 s27, s29, s27 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v9, s26 +; GFX9-NEXT: s_and_b32 s26, s41, 0xff +; GFX9-NEXT: s_lshl_b32 s27, s97, 8 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: s_and_b32 s27, s96, 0xff +; GFX9-NEXT: s_lshl_b32 s29, s87, 8 +; GFX9-NEXT: s_or_b32 s27, s27, s29 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v10, s26 +; GFX9-NEXT: s_lshl_b32 s26, s86, 8 +; GFX9-NEXT: s_and_b32 s24, s24, 0xff +; GFX9-NEXT: s_or_b32 s24, s24, s26 +; GFX9-NEXT: s_lshl_b32 s26, s90, 8 +; GFX9-NEXT: s_and_b32 s27, s85, 0xff +; GFX9-NEXT: s_or_b32 s26, s27, s26 +; GFX9-NEXT: s_and_b32 s24, s24, 0xffff +; GFX9-NEXT: s_lshl_b32 s26, s26, 16 +; GFX9-NEXT: s_or_b32 s24, s24, s26 +; GFX9-NEXT: v_mov_b32_e32 v11, s24 +; GFX9-NEXT: s_and_b32 s24, s25, 0xff +; GFX9-NEXT: s_lshl_b32 s25, s84, 8 +; GFX9-NEXT: s_or_b32 s24, s24, s25 +; GFX9-NEXT: s_and_b32 s25, s81, 0xff +; GFX9-NEXT: s_lshl_b32 s26, s83, 8 +; GFX9-NEXT: s_or_b32 s25, s25, s26 +; GFX9-NEXT: s_and_b32 s24, s24, 0xffff +; GFX9-NEXT: s_lshl_b32 s25, s25, 16 +; GFX9-NEXT: s_or_b32 s24, s24, s25 +; GFX9-NEXT: v_mov_b32_e32 v12, s24 +; GFX9-NEXT: s_lshl_b32 s24, s82, 8 +; GFX9-NEXT: s_and_b32 s22, s22, 0xff +; GFX9-NEXT: v_readlane_b32 s25, v22, 50 +; GFX9-NEXT: s_or_b32 s22, s22, s24 +; GFX9-NEXT: s_lshl_b32 s24, s88, 8 +; GFX9-NEXT: s_and_b32 s25, s25, 0xff +; GFX9-NEXT: s_or_b32 s24, s25, s24 +; GFX9-NEXT: s_and_b32 s22, s22, 0xffff +; GFX9-NEXT: s_lshl_b32 s24, s24, 16 +; GFX9-NEXT: s_or_b32 s22, s22, s24 +; GFX9-NEXT: v_mov_b32_e32 v13, s22 +; GFX9-NEXT: s_and_b32 s22, s23, 0xff +; GFX9-NEXT: v_readlane_b32 s23, v22, 49 +; GFX9-NEXT: s_lshl_b32 s23, s23, 8 +; GFX9-NEXT: s_or_b32 s22, s22, s23 +; GFX9-NEXT: v_readlane_b32 s23, v22, 48 +; GFX9-NEXT: v_readlane_b32 s24, v22, 47 +; GFX9-NEXT: s_and_b32 s23, s23, 0xff +; GFX9-NEXT: s_lshl_b32 s24, s24, 8 +; GFX9-NEXT: s_or_b32 s23, s23, s24 +; GFX9-NEXT: s_and_b32 s22, s22, 0xffff +; GFX9-NEXT: s_lshl_b32 s23, s23, 16 +; GFX9-NEXT: s_or_b32 s22, s22, s23 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:4 ; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:8 @@ -10222,79 +10305,80 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:40 ; GFX9-NEXT: buffer_store_dword v12, v0, s[0:3], 0 offen offset:44 ; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:48 -; GFX9-NEXT: v_mov_b32_e32 v1, s16 -; GFX9-NEXT: s_and_b32 s16, s44, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s17, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 45 -; GFX9-NEXT: s_and_b32 s17, s17, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s78, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 44 +; GFX9-NEXT: v_mov_b32_e32 v1, s22 +; GFX9-NEXT: v_readlane_b32 s22, v22, 46 +; GFX9-NEXT: s_and_b32 s20, s20, 0xff +; GFX9-NEXT: s_lshl_b32 s22, s22, 8 +; GFX9-NEXT: s_or_b32 s20, s20, s22 +; GFX9-NEXT: v_readlane_b32 s22, v22, 45 +; GFX9-NEXT: s_and_b32 s22, s22, 0xff +; GFX9-NEXT: s_lshl_b32 s23, s78, 8 +; GFX9-NEXT: s_or_b32 s22, s22, s23 +; GFX9-NEXT: s_and_b32 s20, s20, 0xffff +; GFX9-NEXT: s_lshl_b32 s22, s22, 16 +; GFX9-NEXT: s_or_b32 s20, s20, s22 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52 -; GFX9-NEXT: v_mov_b32_e32 v1, s16 -; GFX9-NEXT: s_and_b32 s16, s45, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s17, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 43 -; GFX9-NEXT: v_readlane_b32 s18, v21, 42 -; GFX9-NEXT: s_and_b32 s17, s17, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s18, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 41 +; GFX9-NEXT: v_mov_b32_e32 v1, s20 +; GFX9-NEXT: s_and_b32 s20, s21, 0xff +; GFX9-NEXT: v_readlane_b32 s21, v22, 44 +; GFX9-NEXT: s_lshl_b32 s21, s21, 8 +; GFX9-NEXT: s_or_b32 s20, s20, s21 +; GFX9-NEXT: v_readlane_b32 s21, v22, 43 +; GFX9-NEXT: v_readlane_b32 s22, v22, 42 +; GFX9-NEXT: s_and_b32 s21, s21, 0xff +; GFX9-NEXT: s_lshl_b32 s22, s22, 8 +; GFX9-NEXT: s_or_b32 s21, s21, s22 +; GFX9-NEXT: s_and_b32 s20, s20, 0xffff +; GFX9-NEXT: s_lshl_b32 s21, s21, 16 +; GFX9-NEXT: s_or_b32 s20, s20, s21 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56 -; GFX9-NEXT: v_mov_b32_e32 v1, s16 -; GFX9-NEXT: s_and_b32 s16, s42, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s17, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 40 -; GFX9-NEXT: s_and_b32 s17, s17, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s76, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 39 +; GFX9-NEXT: v_mov_b32_e32 v1, s20 +; GFX9-NEXT: v_readlane_b32 s20, v22, 41 +; GFX9-NEXT: s_and_b32 s18, s18, 0xff +; GFX9-NEXT: s_lshl_b32 s20, s20, 8 +; GFX9-NEXT: s_or_b32 s18, s18, s20 +; GFX9-NEXT: v_readlane_b32 s20, v22, 40 +; GFX9-NEXT: s_and_b32 s20, s20, 0xff +; GFX9-NEXT: s_lshl_b32 s21, s76, 8 +; GFX9-NEXT: s_or_b32 s20, s20, s21 +; GFX9-NEXT: s_and_b32 s18, s18, 0xffff +; GFX9-NEXT: s_lshl_b32 s20, s20, 16 +; GFX9-NEXT: s_or_b32 s18, s18, s20 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60 -; GFX9-NEXT: v_mov_b32_e32 v1, s16 -; GFX9-NEXT: s_and_b32 s16, s43, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s17, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 38 -; GFX9-NEXT: v_readlane_b32 s18, v21, 37 -; GFX9-NEXT: s_and_b32 s17, s17, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s18, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 36 +; GFX9-NEXT: v_mov_b32_e32 v1, s18 +; GFX9-NEXT: s_and_b32 s18, s19, 0xff +; GFX9-NEXT: v_readlane_b32 s19, v22, 39 +; GFX9-NEXT: s_lshl_b32 s19, s19, 8 +; GFX9-NEXT: s_or_b32 s18, s18, s19 +; GFX9-NEXT: v_readlane_b32 s19, v22, 38 +; GFX9-NEXT: v_readlane_b32 s20, v22, 37 +; GFX9-NEXT: s_and_b32 s19, s19, 0xff +; GFX9-NEXT: s_lshl_b32 s20, s20, 8 +; GFX9-NEXT: s_or_b32 s19, s19, s20 +; GFX9-NEXT: s_and_b32 s18, s18, 0xffff +; GFX9-NEXT: s_lshl_b32 s19, s19, 16 +; GFX9-NEXT: s_or_b32 s18, s18, s19 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:64 -; GFX9-NEXT: v_mov_b32_e32 v1, s16 -; GFX9-NEXT: s_and_b32 s16, s40, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s17, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 35 -; GFX9-NEXT: s_and_b32 s17, s17, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s74, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 +; GFX9-NEXT: v_mov_b32_e32 v1, s18 +; GFX9-NEXT: v_readlane_b32 s18, v22, 36 +; GFX9-NEXT: s_and_b32 s16, s16, 0xff +; GFX9-NEXT: s_lshl_b32 s18, s18, 8 +; GFX9-NEXT: s_or_b32 s16, s16, s18 +; GFX9-NEXT: v_readlane_b32 s18, v22, 35 +; GFX9-NEXT: s_and_b32 s18, s18, 0xff +; GFX9-NEXT: s_lshl_b32 s19, s74, 8 +; GFX9-NEXT: s_or_b32 s18, s18, s19 ; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 34 +; GFX9-NEXT: s_lshl_b32 s18, s18, 16 +; GFX9-NEXT: s_or_b32 s16, s16, s18 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:68 ; GFX9-NEXT: v_mov_b32_e32 v1, s16 -; GFX9-NEXT: s_and_b32 s16, s41, 0xff +; GFX9-NEXT: s_and_b32 s16, s17, 0xff +; GFX9-NEXT: v_readlane_b32 s17, v22, 34 ; GFX9-NEXT: s_lshl_b32 s17, s17, 8 ; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 33 -; GFX9-NEXT: v_readlane_b32 s18, v21, 32 +; GFX9-NEXT: v_readlane_b32 s17, v22, 33 +; GFX9-NEXT: v_readlane_b32 s18, v22, 32 ; GFX9-NEXT: s_and_b32 s17, s17, 0xff ; GFX9-NEXT: s_lshl_b32 s18, s18, 8 ; GFX9-NEXT: s_or_b32 s17, s17, s18 @@ -10303,11 +10387,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX9-NEXT: s_or_b32 s16, s16, s17 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:72 ; GFX9-NEXT: v_mov_b32_e32 v1, s16 -; GFX9-NEXT: v_readlane_b32 s16, v21, 31 +; GFX9-NEXT: v_readlane_b32 s16, v22, 31 ; GFX9-NEXT: s_and_b32 s14, s14, 0xff ; GFX9-NEXT: s_lshl_b32 s16, s16, 8 ; GFX9-NEXT: s_or_b32 s14, s14, s16 -; GFX9-NEXT: v_readlane_b32 s16, v21, 30 +; GFX9-NEXT: v_readlane_b32 s16, v22, 30 ; GFX9-NEXT: s_and_b32 s16, s16, 0xff ; GFX9-NEXT: s_lshl_b32 s17, s72, 8 ; GFX9-NEXT: s_or_b32 s16, s16, s17 @@ -10317,11 +10401,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:76 ; GFX9-NEXT: v_mov_b32_e32 v1, s14 ; GFX9-NEXT: s_and_b32 s14, s15, 0xff -; GFX9-NEXT: v_readlane_b32 s15, v21, 29 +; GFX9-NEXT: v_readlane_b32 s15, v22, 29 ; GFX9-NEXT: s_lshl_b32 s15, s15, 8 ; GFX9-NEXT: s_or_b32 s14, s14, s15 -; GFX9-NEXT: v_readlane_b32 s15, v21, 28 -; GFX9-NEXT: v_readlane_b32 s16, v21, 27 +; GFX9-NEXT: v_readlane_b32 s15, v22, 28 +; GFX9-NEXT: v_readlane_b32 s16, v22, 27 ; GFX9-NEXT: s_and_b32 s15, s15, 0xff ; GFX9-NEXT: s_lshl_b32 s16, s16, 8 ; GFX9-NEXT: s_or_b32 s15, s15, s16 @@ -10330,11 +10414,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX9-NEXT: s_or_b32 s14, s14, s15 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:80 ; GFX9-NEXT: v_mov_b32_e32 v1, s14 -; GFX9-NEXT: v_readlane_b32 s14, v21, 26 +; GFX9-NEXT: v_readlane_b32 s14, v22, 26 ; GFX9-NEXT: s_and_b32 s12, s12, 0xff ; GFX9-NEXT: s_lshl_b32 s14, s14, 8 ; GFX9-NEXT: s_or_b32 s12, s12, s14 -; GFX9-NEXT: v_readlane_b32 s14, v21, 25 +; GFX9-NEXT: v_readlane_b32 s14, v22, 25 ; GFX9-NEXT: s_and_b32 s14, s14, 0xff ; GFX9-NEXT: s_lshl_b32 s15, s62, 8 ; GFX9-NEXT: s_or_b32 s14, s14, s15 @@ -10344,11 +10428,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:84 ; GFX9-NEXT: v_mov_b32_e32 v1, s12 ; GFX9-NEXT: s_and_b32 s12, s13, 0xff -; GFX9-NEXT: v_readlane_b32 s13, v21, 24 +; GFX9-NEXT: v_readlane_b32 s13, v22, 24 ; GFX9-NEXT: s_lshl_b32 s13, s13, 8 ; GFX9-NEXT: s_or_b32 s12, s12, s13 -; GFX9-NEXT: v_readlane_b32 s13, v21, 23 -; GFX9-NEXT: v_readlane_b32 s14, v21, 22 +; GFX9-NEXT: v_readlane_b32 s13, v22, 23 +; GFX9-NEXT: v_readlane_b32 s14, v22, 22 ; GFX9-NEXT: s_and_b32 s13, s13, 0xff ; GFX9-NEXT: s_lshl_b32 s14, s14, 8 ; GFX9-NEXT: s_or_b32 s13, s13, s14 @@ -10357,11 +10441,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX9-NEXT: s_or_b32 s12, s12, s13 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:88 ; GFX9-NEXT: v_mov_b32_e32 v1, s12 -; GFX9-NEXT: v_readlane_b32 s12, v21, 21 +; GFX9-NEXT: v_readlane_b32 s12, v22, 21 ; GFX9-NEXT: s_and_b32 s10, s10, 0xff ; GFX9-NEXT: s_lshl_b32 s12, s12, 8 ; GFX9-NEXT: s_or_b32 s10, s10, s12 -; GFX9-NEXT: v_readlane_b32 s12, v21, 20 +; GFX9-NEXT: v_readlane_b32 s12, v22, 20 ; GFX9-NEXT: s_and_b32 s12, s12, 0xff ; GFX9-NEXT: s_lshl_b32 s13, s60, 8 ; GFX9-NEXT: s_or_b32 s12, s12, s13 @@ -10371,11 +10455,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:92 ; GFX9-NEXT: v_mov_b32_e32 v1, s10 ; GFX9-NEXT: s_and_b32 s10, s11, 0xff -; GFX9-NEXT: v_readlane_b32 s11, v21, 19 +; GFX9-NEXT: v_readlane_b32 s11, v22, 19 ; GFX9-NEXT: s_lshl_b32 s11, s11, 8 ; GFX9-NEXT: s_or_b32 s10, s10, s11 -; GFX9-NEXT: v_readlane_b32 s11, v21, 18 -; GFX9-NEXT: v_readlane_b32 s12, v21, 17 +; GFX9-NEXT: v_readlane_b32 s11, v22, 18 +; GFX9-NEXT: v_readlane_b32 s12, v22, 17 ; GFX9-NEXT: s_and_b32 s11, s11, 0xff ; GFX9-NEXT: s_lshl_b32 s12, s12, 8 ; GFX9-NEXT: s_or_b32 s11, s11, s12 @@ -10384,11 +10468,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX9-NEXT: s_or_b32 s10, s10, s11 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:96 ; GFX9-NEXT: v_mov_b32_e32 v1, s10 -; GFX9-NEXT: v_readlane_b32 s10, v21, 16 +; GFX9-NEXT: v_readlane_b32 s10, v22, 16 ; GFX9-NEXT: s_and_b32 s8, s8, 0xff ; GFX9-NEXT: s_lshl_b32 s10, s10, 8 ; GFX9-NEXT: s_or_b32 s8, s8, s10 -; GFX9-NEXT: v_readlane_b32 s10, v21, 15 +; GFX9-NEXT: v_readlane_b32 s10, v22, 15 ; GFX9-NEXT: s_and_b32 s10, s10, 0xff ; GFX9-NEXT: s_lshl_b32 s11, s58, 8 ; GFX9-NEXT: s_or_b32 s10, s10, s11 @@ -10398,11 +10482,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:100 ; GFX9-NEXT: v_mov_b32_e32 v1, s8 ; GFX9-NEXT: s_and_b32 s8, s9, 0xff -; GFX9-NEXT: v_readlane_b32 s9, v21, 14 +; GFX9-NEXT: v_readlane_b32 s9, v22, 14 ; GFX9-NEXT: s_lshl_b32 s9, s9, 8 ; GFX9-NEXT: s_or_b32 s8, s8, s9 -; GFX9-NEXT: v_readlane_b32 s9, v21, 13 -; GFX9-NEXT: v_readlane_b32 s10, v21, 12 +; GFX9-NEXT: v_readlane_b32 s9, v22, 13 +; GFX9-NEXT: v_readlane_b32 s10, v22, 12 ; GFX9-NEXT: s_and_b32 s9, s9, 0xff ; GFX9-NEXT: s_lshl_b32 s10, s10, 8 ; GFX9-NEXT: s_or_b32 s9, s9, s10 @@ -10411,13 +10495,13 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX9-NEXT: s_or_b32 s8, s8, s9 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:104 ; GFX9-NEXT: v_mov_b32_e32 v1, s8 -; GFX9-NEXT: v_readlane_b32 s8, v21, 11 +; GFX9-NEXT: v_readlane_b32 s8, v22, 11 ; GFX9-NEXT: s_and_b32 s6, s6, 0xff ; GFX9-NEXT: s_lshl_b32 s8, s8, 8 ; GFX9-NEXT: s_or_b32 s6, s6, s8 -; GFX9-NEXT: v_readlane_b32 s8, v21, 10 +; GFX9-NEXT: v_readlane_b32 s8, v22, 10 ; GFX9-NEXT: s_and_b32 s8, s8, 0xff -; GFX9-NEXT: s_lshl_b32 s9, s56, 8 +; GFX9-NEXT: s_lshl_b32 s9, s28, 8 ; GFX9-NEXT: s_or_b32 s8, s8, s9 ; GFX9-NEXT: s_and_b32 s6, s6, 0xffff ; GFX9-NEXT: s_lshl_b32 s8, s8, 16 @@ -10425,11 +10509,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:108 ; GFX9-NEXT: v_mov_b32_e32 v1, s6 ; GFX9-NEXT: s_and_b32 s6, s7, 0xff -; GFX9-NEXT: v_readlane_b32 s7, v21, 9 +; GFX9-NEXT: v_readlane_b32 s7, v22, 9 ; GFX9-NEXT: s_lshl_b32 s7, s7, 8 ; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: v_readlane_b32 s7, v21, 8 -; GFX9-NEXT: v_readlane_b32 s8, v21, 7 +; GFX9-NEXT: v_readlane_b32 s7, v22, 8 +; GFX9-NEXT: v_readlane_b32 s8, v22, 7 ; GFX9-NEXT: s_and_b32 s7, s7, 0xff ; GFX9-NEXT: s_lshl_b32 s8, s8, 8 ; GFX9-NEXT: s_or_b32 s7, s7, s8 @@ -10438,12 +10522,12 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX9-NEXT: s_or_b32 s6, s6, s7 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:112 ; GFX9-NEXT: v_mov_b32_e32 v1, s6 -; GFX9-NEXT: v_readlane_b32 s6, v21, 6 +; GFX9-NEXT: v_readlane_b32 s6, v22, 6 ; GFX9-NEXT: s_and_b32 s4, s4, 0xff ; GFX9-NEXT: s_lshl_b32 s6, s6, 8 ; GFX9-NEXT: s_or_b32 s4, s4, s6 -; GFX9-NEXT: v_readlane_b32 s6, v21, 5 -; GFX9-NEXT: v_readlane_b32 s8, v21, 0 +; GFX9-NEXT: v_readlane_b32 s6, v22, 5 +; GFX9-NEXT: v_readlane_b32 s8, v22, 0 ; GFX9-NEXT: s_and_b32 s6, s6, 0xff ; GFX9-NEXT: s_lshl_b32 s7, s8, 8 ; GFX9-NEXT: s_or_b32 s6, s6, s7 @@ -10453,11 +10537,11 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:116 ; GFX9-NEXT: v_mov_b32_e32 v1, s4 ; GFX9-NEXT: s_and_b32 s4, s5, 0xff -; GFX9-NEXT: v_readlane_b32 s5, v21, 4 +; GFX9-NEXT: v_readlane_b32 s5, v22, 4 ; GFX9-NEXT: s_lshl_b32 s5, s5, 8 ; GFX9-NEXT: s_or_b32 s4, s4, s5 -; GFX9-NEXT: v_readlane_b32 s5, v21, 3 -; GFX9-NEXT: v_readlane_b32 s6, v21, 2 +; GFX9-NEXT: v_readlane_b32 s5, v22, 3 +; GFX9-NEXT: v_readlane_b32 s6, v22, 2 ; GFX9-NEXT: s_and_b32 s5, s5, 0xff ; GFX9-NEXT: s_lshl_b32 s6, s6, 8 ; GFX9-NEXT: s_or_b32 s5, s5, s6 @@ -10466,61 +10550,61 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX9-NEXT: s_or_b32 s4, s4, s5 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120 ; GFX9-NEXT: v_mov_b32_e32 v1, s4 -; GFX9-NEXT: v_readlane_b32 s9, v21, 1 +; GFX9-NEXT: v_readlane_b32 s9, v22, 1 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124 -; GFX9-NEXT: v_readlane_b32 s99, v20, 35 -; GFX9-NEXT: v_readlane_b32 s98, v20, 34 -; GFX9-NEXT: v_readlane_b32 s97, v20, 33 -; GFX9-NEXT: v_readlane_b32 s96, v20, 32 -; GFX9-NEXT: v_readlane_b32 s87, v20, 31 -; GFX9-NEXT: v_readlane_b32 s86, v20, 30 -; GFX9-NEXT: v_readlane_b32 s85, v20, 29 -; GFX9-NEXT: v_readlane_b32 s84, v20, 28 -; GFX9-NEXT: v_readlane_b32 s83, v20, 27 -; GFX9-NEXT: v_readlane_b32 s82, v20, 26 -; GFX9-NEXT: v_readlane_b32 s81, v20, 25 -; GFX9-NEXT: v_readlane_b32 s80, v20, 24 -; GFX9-NEXT: v_readlane_b32 s71, v20, 23 -; GFX9-NEXT: v_readlane_b32 s70, v20, 22 -; GFX9-NEXT: v_readlane_b32 s69, v20, 21 -; GFX9-NEXT: v_readlane_b32 s68, v20, 20 -; GFX9-NEXT: v_readlane_b32 s67, v20, 19 -; GFX9-NEXT: v_readlane_b32 s66, v20, 18 -; GFX9-NEXT: v_readlane_b32 s65, v20, 17 -; GFX9-NEXT: v_readlane_b32 s64, v20, 16 -; GFX9-NEXT: v_readlane_b32 s55, v20, 15 -; GFX9-NEXT: v_readlane_b32 s54, v20, 14 -; GFX9-NEXT: v_readlane_b32 s53, v20, 13 -; GFX9-NEXT: v_readlane_b32 s52, v20, 12 -; GFX9-NEXT: v_readlane_b32 s51, v20, 11 -; GFX9-NEXT: v_readlane_b32 s50, v20, 10 -; GFX9-NEXT: v_readlane_b32 s49, v20, 9 -; GFX9-NEXT: v_readlane_b32 s48, v20, 8 -; GFX9-NEXT: v_readlane_b32 s39, v20, 7 -; GFX9-NEXT: v_readlane_b32 s38, v20, 6 -; GFX9-NEXT: v_readlane_b32 s37, v20, 5 -; GFX9-NEXT: v_readlane_b32 s36, v20, 4 -; GFX9-NEXT: v_readlane_b32 s35, v20, 3 -; GFX9-NEXT: v_readlane_b32 s34, v20, 2 -; GFX9-NEXT: v_readlane_b32 s31, v20, 1 -; GFX9-NEXT: v_readlane_b32 s30, v20, 0 +; GFX9-NEXT: v_readlane_b32 s99, v21, 35 +; GFX9-NEXT: v_readlane_b32 s98, v21, 34 +; GFX9-NEXT: v_readlane_b32 s97, v21, 33 +; GFX9-NEXT: v_readlane_b32 s96, v21, 32 +; GFX9-NEXT: v_readlane_b32 s87, v21, 31 +; GFX9-NEXT: v_readlane_b32 s86, v21, 30 +; GFX9-NEXT: v_readlane_b32 s85, v21, 29 +; GFX9-NEXT: v_readlane_b32 s84, v21, 28 +; GFX9-NEXT: v_readlane_b32 s83, v21, 27 +; GFX9-NEXT: v_readlane_b32 s82, v21, 26 +; GFX9-NEXT: v_readlane_b32 s81, v21, 25 +; GFX9-NEXT: v_readlane_b32 s80, v21, 24 +; GFX9-NEXT: v_readlane_b32 s71, v21, 23 +; GFX9-NEXT: v_readlane_b32 s70, v21, 22 +; GFX9-NEXT: v_readlane_b32 s69, v21, 21 +; GFX9-NEXT: v_readlane_b32 s68, v21, 20 +; GFX9-NEXT: v_readlane_b32 s67, v21, 19 +; GFX9-NEXT: v_readlane_b32 s66, v21, 18 +; GFX9-NEXT: v_readlane_b32 s65, v21, 17 +; GFX9-NEXT: v_readlane_b32 s64, v21, 16 +; GFX9-NEXT: v_readlane_b32 s55, v21, 15 +; GFX9-NEXT: v_readlane_b32 s54, v21, 14 +; GFX9-NEXT: v_readlane_b32 s53, v21, 13 +; GFX9-NEXT: v_readlane_b32 s52, v21, 12 +; GFX9-NEXT: v_readlane_b32 s51, v21, 11 +; GFX9-NEXT: v_readlane_b32 s50, v21, 10 +; GFX9-NEXT: v_readlane_b32 s49, v21, 9 +; GFX9-NEXT: v_readlane_b32 s48, v21, 8 +; GFX9-NEXT: v_readlane_b32 s39, v21, 7 +; GFX9-NEXT: v_readlane_b32 s38, v21, 6 +; GFX9-NEXT: v_readlane_b32 s37, v21, 5 +; GFX9-NEXT: v_readlane_b32 s36, v21, 4 +; GFX9-NEXT: v_readlane_b32 s35, v21, 3 +; GFX9-NEXT: v_readlane_b32 s34, v21, 2 +; GFX9-NEXT: v_readlane_b32 s31, v21, 1 +; GFX9-NEXT: v_readlane_b32 s30, v21, 0 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: .LBB13_4: -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 ; GFX9-NEXT: ; implicit-def: $sgpr83 ; GFX9-NEXT: ; implicit-def: $sgpr82 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: v_writelane_b32 v21, s82, 0 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: v_writelane_b32 v22, s82, 0 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr26 ; GFX9-NEXT: ; implicit-def: $sgpr80 ; GFX9-NEXT: ; implicit-def: $sgpr71 ; GFX9-NEXT: ; implicit-def: $sgpr70 @@ -10563,101 +10647,101 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX9-NEXT: ; implicit-def: $sgpr62 ; GFX9-NEXT: ; implicit-def: $sgpr60 ; GFX9-NEXT: ; implicit-def: $sgpr58 -; GFX9-NEXT: ; implicit-def: $sgpr56 -; GFX9-NEXT: v_writelane_b32 v21, s83, 1 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 +; GFX9-NEXT: ; implicit-def: $sgpr28 +; GFX9-NEXT: v_writelane_b32 v22, s83, 1 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 ; GFX9-NEXT: ; implicit-def: $sgpr82 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 ; GFX9-NEXT: s_branch .LBB13_2 ; ; GFX11-LABEL: bitcast_v32i32_to_v128i8_scalar: @@ -10665,213 +10749,240 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX11-NEXT: s_clause 0x3 ; 16-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v16, s32 -; GFX11-NEXT: scratch_store_b32 off, v17, s32 offset:4 -; GFX11-NEXT: scratch_store_b32 off, v18, s32 offset:8 -; GFX11-NEXT: scratch_store_b32 off, v19, s32 offset:12 +; GFX11-NEXT: scratch_store_b32 off, v34, s32 +; GFX11-NEXT: scratch_store_b32 off, v35, s32 offset:4 +; GFX11-NEXT: scratch_store_b32 off, v36, s32 offset:8 +; GFX11-NEXT: scratch_store_b32 off, v37, s32 offset:12 ; GFX11-NEXT: s_mov_b32 exec_lo, s4 -; GFX11-NEXT: v_writelane_b32 v16, s30, 0 -; GFX11-NEXT: v_writelane_b32 v17, s96, 0 +; GFX11-NEXT: v_writelane_b32 v34, s30, 0 +; GFX11-NEXT: v_writelane_b32 v35, s96, 0 +; GFX11-NEXT: v_dual_mov_b32 v16, s0 :: v_dual_mov_b32 v17, s1 +; GFX11-NEXT: v_dual_mov_b32 v18, s2 :: v_dual_mov_b32 v19, s3 +; GFX11-NEXT: v_writelane_b32 v34, s31, 1 +; GFX11-NEXT: v_writelane_b32 v35, s97, 1 +; GFX11-NEXT: v_dual_mov_b32 v20, s16 :: v_dual_mov_b32 v21, s17 +; GFX11-NEXT: v_dual_mov_b32 v22, s18 :: v_dual_mov_b32 v23, s19 +; GFX11-NEXT: v_writelane_b32 v34, s34, 2 +; GFX11-NEXT: v_writelane_b32 v35, s98, 2 +; GFX11-NEXT: v_dual_mov_b32 v24, s20 :: v_dual_mov_b32 v25, s21 +; GFX11-NEXT: v_dual_mov_b32 v26, s22 :: v_dual_mov_b32 v27, s23 +; GFX11-NEXT: v_writelane_b32 v34, s35, 3 +; GFX11-NEXT: v_writelane_b32 v35, s99, 3 +; GFX11-NEXT: v_dual_mov_b32 v28, s24 :: v_dual_mov_b32 v29, s25 +; GFX11-NEXT: v_dual_mov_b32 v30, s26 :: v_dual_mov_b32 v31, s27 +; GFX11-NEXT: v_writelane_b32 v34, s36, 4 +; GFX11-NEXT: v_writelane_b32 v35, s100, 4 +; GFX11-NEXT: v_dual_mov_b32 v32, s28 :: v_dual_mov_b32 v33, s29 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 -; GFX11-NEXT: v_readfirstlane_b32 s40, v1 -; GFX11-NEXT: v_readfirstlane_b32 s41, v2 -; GFX11-NEXT: v_writelane_b32 v16, s31, 1 -; GFX11-NEXT: v_writelane_b32 v17, s97, 1 -; GFX11-NEXT: v_readfirstlane_b32 s14, v3 -; GFX11-NEXT: v_readfirstlane_b32 s15, v4 -; GFX11-NEXT: v_readfirstlane_b32 s12, v5 -; GFX11-NEXT: v_writelane_b32 v16, s34, 2 -; GFX11-NEXT: v_writelane_b32 v17, s98, 2 -; GFX11-NEXT: v_readfirstlane_b32 s13, v6 -; GFX11-NEXT: v_readfirstlane_b32 s10, v7 -; GFX11-NEXT: v_readfirstlane_b32 s11, v8 -; GFX11-NEXT: v_writelane_b32 v16, s35, 3 -; GFX11-NEXT: v_writelane_b32 v17, s99, 3 -; GFX11-NEXT: v_readfirstlane_b32 s8, v9 -; GFX11-NEXT: v_readfirstlane_b32 s9, v10 -; GFX11-NEXT: v_readfirstlane_b32 s6, v11 -; GFX11-NEXT: v_writelane_b32 v16, s36, 4 -; GFX11-NEXT: v_writelane_b32 v17, s100, 4 -; GFX11-NEXT: v_readfirstlane_b32 s7, v12 -; GFX11-NEXT: v_readfirstlane_b32 s4, v13 -; GFX11-NEXT: v_readfirstlane_b32 s5, v14 -; GFX11-NEXT: v_writelane_b32 v16, s37, 5 -; GFX11-NEXT: v_writelane_b32 v17, s101, 5 +; GFX11-NEXT: v_writelane_b32 v34, s37, 5 +; GFX11-NEXT: v_writelane_b32 v35, s101, 5 +; GFX11-NEXT: v_readfirstlane_b32 s40, v16 +; GFX11-NEXT: v_readfirstlane_b32 s41, v17 +; GFX11-NEXT: v_readfirstlane_b32 s28, v18 +; GFX11-NEXT: v_writelane_b32 v34, s38, 6 +; GFX11-NEXT: v_writelane_b32 v35, s102, 6 +; GFX11-NEXT: v_readfirstlane_b32 s29, v19 +; GFX11-NEXT: v_readfirstlane_b32 s26, v20 +; GFX11-NEXT: v_readfirstlane_b32 s27, v21 +; GFX11-NEXT: v_writelane_b32 v34, s39, 7 +; GFX11-NEXT: v_writelane_b32 v35, s103, 7 +; GFX11-NEXT: v_readfirstlane_b32 s24, v22 +; GFX11-NEXT: v_readfirstlane_b32 s25, v23 +; GFX11-NEXT: v_readfirstlane_b32 s22, v24 +; GFX11-NEXT: v_writelane_b32 v34, s48, 8 +; GFX11-NEXT: v_readfirstlane_b32 s23, v25 +; GFX11-NEXT: v_readfirstlane_b32 s20, v26 +; GFX11-NEXT: v_readfirstlane_b32 s21, v27 +; GFX11-NEXT: v_readfirstlane_b32 s18, v28 +; GFX11-NEXT: v_writelane_b32 v34, s49, 9 +; GFX11-NEXT: v_readfirstlane_b32 s19, v29 +; GFX11-NEXT: v_readfirstlane_b32 s16, v30 +; GFX11-NEXT: v_readfirstlane_b32 s17, v31 +; GFX11-NEXT: v_readfirstlane_b32 s14, v32 +; GFX11-NEXT: v_writelane_b32 v34, s50, 10 +; GFX11-NEXT: v_readfirstlane_b32 s15, v33 +; GFX11-NEXT: v_readfirstlane_b32 s12, v1 +; GFX11-NEXT: v_readfirstlane_b32 s13, v2 +; GFX11-NEXT: v_readfirstlane_b32 s10, v3 +; GFX11-NEXT: v_writelane_b32 v34, s51, 11 +; GFX11-NEXT: v_readfirstlane_b32 s11, v4 +; GFX11-NEXT: v_readfirstlane_b32 s8, v5 +; GFX11-NEXT: v_readfirstlane_b32 s9, v6 +; GFX11-NEXT: v_readfirstlane_b32 s6, v7 +; GFX11-NEXT: v_writelane_b32 v34, s52, 12 +; GFX11-NEXT: v_readfirstlane_b32 s7, v8 +; GFX11-NEXT: v_readfirstlane_b32 s4, v9 +; GFX11-NEXT: v_readfirstlane_b32 s5, v10 +; GFX11-NEXT: v_readfirstlane_b32 s2, v11 +; GFX11-NEXT: v_writelane_b32 v34, s53, 13 +; GFX11-NEXT: v_readfirstlane_b32 s3, v12 +; GFX11-NEXT: v_readfirstlane_b32 s0, v13 +; GFX11-NEXT: v_readfirstlane_b32 s1, v14 ; GFX11-NEXT: s_mov_b32 s101, 0 +; GFX11-NEXT: v_writelane_b32 v34, s54, 14 ; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo -; GFX11-NEXT: ; implicit-def: $vgpr19 : SGPR spill to VGPR lane -; GFX11-NEXT: ; implicit-def: $vgpr18 : SGPR spill to VGPR lane -; GFX11-NEXT: v_writelane_b32 v16, s38, 6 -; GFX11-NEXT: v_writelane_b32 v17, s102, 6 -; GFX11-NEXT: v_writelane_b32 v16, s39, 7 -; GFX11-NEXT: v_writelane_b32 v17, s103, 7 -; GFX11-NEXT: v_writelane_b32 v16, s48, 8 -; GFX11-NEXT: v_writelane_b32 v17, s104, 8 -; GFX11-NEXT: v_writelane_b32 v16, s49, 9 -; GFX11-NEXT: v_writelane_b32 v16, s50, 10 -; GFX11-NEXT: v_writelane_b32 v16, s51, 11 -; GFX11-NEXT: v_writelane_b32 v16, s52, 12 -; GFX11-NEXT: v_writelane_b32 v16, s53, 13 -; GFX11-NEXT: v_writelane_b32 v16, s54, 14 -; GFX11-NEXT: v_writelane_b32 v16, s55, 15 -; GFX11-NEXT: v_writelane_b32 v16, s64, 16 -; GFX11-NEXT: v_writelane_b32 v16, s65, 17 -; GFX11-NEXT: v_writelane_b32 v16, s66, 18 -; GFX11-NEXT: v_writelane_b32 v16, s67, 19 -; GFX11-NEXT: v_writelane_b32 v16, s68, 20 -; GFX11-NEXT: v_writelane_b32 v16, s69, 21 -; GFX11-NEXT: v_writelane_b32 v16, s70, 22 -; GFX11-NEXT: v_writelane_b32 v16, s71, 23 -; GFX11-NEXT: v_writelane_b32 v16, s80, 24 -; GFX11-NEXT: v_writelane_b32 v16, s81, 25 -; GFX11-NEXT: v_writelane_b32 v16, s82, 26 -; GFX11-NEXT: v_writelane_b32 v16, s83, 27 -; GFX11-NEXT: v_writelane_b32 v16, s84, 28 -; GFX11-NEXT: v_writelane_b32 v16, s85, 29 -; GFX11-NEXT: v_writelane_b32 v16, s86, 30 -; GFX11-NEXT: v_writelane_b32 v16, s87, 31 +; GFX11-NEXT: v_writelane_b32 v35, s104, 8 +; GFX11-NEXT: ; implicit-def: $vgpr37 : SGPR spill to VGPR lane +; GFX11-NEXT: ; implicit-def: $vgpr36 : SGPR spill to VGPR lane +; GFX11-NEXT: v_writelane_b32 v34, s55, 15 +; GFX11-NEXT: v_writelane_b32 v34, s64, 16 +; GFX11-NEXT: v_writelane_b32 v34, s65, 17 +; GFX11-NEXT: v_writelane_b32 v34, s66, 18 +; GFX11-NEXT: v_writelane_b32 v34, s67, 19 +; GFX11-NEXT: v_writelane_b32 v34, s68, 20 +; GFX11-NEXT: v_writelane_b32 v34, s69, 21 +; GFX11-NEXT: v_writelane_b32 v34, s70, 22 +; GFX11-NEXT: v_writelane_b32 v34, s71, 23 +; GFX11-NEXT: v_writelane_b32 v34, s80, 24 +; GFX11-NEXT: v_writelane_b32 v34, s81, 25 +; GFX11-NEXT: v_writelane_b32 v34, s82, 26 +; GFX11-NEXT: v_writelane_b32 v34, s83, 27 +; GFX11-NEXT: v_writelane_b32 v34, s84, 28 +; GFX11-NEXT: v_writelane_b32 v34, s85, 29 +; GFX11-NEXT: v_writelane_b32 v34, s86, 30 +; GFX11-NEXT: v_writelane_b32 v34, s87, 31 ; GFX11-NEXT: s_cbranch_scc0 .LBB13_2 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: s_lshr_b32 s43, s25, 8 -; GFX11-NEXT: s_lshr_b64 s[62:63], s[4:5], 24 -; GFX11-NEXT: v_writelane_b32 v19, s43, 16 -; GFX11-NEXT: s_lshr_b32 s43, s24, 16 -; GFX11-NEXT: s_lshr_b32 s104, s5, 24 -; GFX11-NEXT: s_lshr_b32 s102, s5, 16 -; GFX11-NEXT: s_lshr_b32 s103, s5, 8 -; GFX11-NEXT: v_writelane_b32 v19, s43, 17 -; GFX11-NEXT: s_lshr_b32 s43, s24, 8 -; GFX11-NEXT: s_lshr_b32 s57, s4, 16 -; GFX11-NEXT: s_lshr_b32 s47, s4, 8 -; GFX11-NEXT: s_lshr_b32 s46, s7, 24 -; GFX11-NEXT: v_writelane_b32 v19, s43, 18 -; GFX11-NEXT: s_lshr_b32 s43, s23, 24 -; GFX11-NEXT: s_lshr_b32 vcc_hi, s7, 16 -; GFX11-NEXT: s_lshr_b32 s34, s7, 8 -; GFX11-NEXT: s_lshr_b32 s69, s6, 16 -; GFX11-NEXT: v_writelane_b32 v19, s43, 19 -; GFX11-NEXT: s_lshr_b32 s43, s23, 16 -; GFX11-NEXT: s_lshr_b32 s56, s6, 8 -; GFX11-NEXT: s_lshr_b32 s35, s9, 24 -; GFX11-NEXT: s_lshr_b32 s36, s9, 16 -; GFX11-NEXT: v_writelane_b32 v19, s43, 20 -; GFX11-NEXT: s_lshr_b32 s43, s23, 8 -; GFX11-NEXT: s_lshr_b32 s37, s9, 8 -; GFX11-NEXT: s_lshr_b32 s38, s8, 16 -; GFX11-NEXT: s_lshr_b32 s39, s8, 8 -; GFX11-NEXT: v_writelane_b32 v19, s43, 21 -; GFX11-NEXT: s_lshr_b32 s43, s22, 16 -; GFX11-NEXT: s_lshr_b32 s48, s11, 24 -; GFX11-NEXT: s_lshr_b32 s49, s11, 16 -; GFX11-NEXT: s_lshr_b32 s50, s11, 8 -; GFX11-NEXT: v_writelane_b32 v19, s43, 22 -; GFX11-NEXT: s_lshr_b32 s43, s22, 8 -; GFX11-NEXT: s_lshr_b32 s51, s10, 16 -; GFX11-NEXT: s_lshr_b32 s52, s10, 8 -; GFX11-NEXT: s_lshr_b32 s53, s13, 24 -; GFX11-NEXT: v_writelane_b32 v19, s43, 23 +; GFX11-NEXT: s_lshr_b32 s43, s19, 8 +; GFX11-NEXT: s_lshr_b64 s[62:63], s[0:1], 24 +; GFX11-NEXT: v_writelane_b32 v37, s43, 16 +; GFX11-NEXT: s_lshr_b32 s43, s18, 16 +; GFX11-NEXT: s_lshr_b32 s104, s1, 24 +; GFX11-NEXT: s_lshr_b32 s102, s1, 16 +; GFX11-NEXT: s_lshr_b32 s103, s1, 8 +; GFX11-NEXT: v_writelane_b32 v37, s43, 17 +; GFX11-NEXT: s_lshr_b32 s43, s18, 8 +; GFX11-NEXT: s_lshr_b32 s57, s0, 16 +; GFX11-NEXT: s_lshr_b32 s47, s0, 8 +; GFX11-NEXT: s_lshr_b32 s46, s3, 24 +; GFX11-NEXT: v_writelane_b32 v37, s43, 18 ; GFX11-NEXT: s_lshr_b32 s43, s21, 24 -; GFX11-NEXT: s_lshr_b32 s54, s13, 16 -; GFX11-NEXT: s_lshr_b32 s55, s13, 8 -; GFX11-NEXT: s_lshr_b32 s64, s12, 16 -; GFX11-NEXT: v_writelane_b32 v19, s43, 24 +; GFX11-NEXT: s_lshr_b32 vcc_hi, s3, 16 +; GFX11-NEXT: s_lshr_b32 s34, s3, 8 +; GFX11-NEXT: s_lshr_b32 s69, s2, 16 +; GFX11-NEXT: v_writelane_b32 v37, s43, 19 ; GFX11-NEXT: s_lshr_b32 s43, s21, 16 -; GFX11-NEXT: s_lshr_b32 s65, s12, 8 -; GFX11-NEXT: s_lshr_b32 s66, s15, 24 -; GFX11-NEXT: s_lshr_b32 s67, s15, 16 -; GFX11-NEXT: v_writelane_b32 v19, s43, 25 +; GFX11-NEXT: s_lshr_b32 s56, s2, 8 +; GFX11-NEXT: s_lshr_b32 s35, s5, 24 +; GFX11-NEXT: s_lshr_b32 s36, s5, 16 +; GFX11-NEXT: v_writelane_b32 v37, s43, 20 ; GFX11-NEXT: s_lshr_b32 s43, s21, 8 -; GFX11-NEXT: s_lshr_b32 s68, s15, 8 -; GFX11-NEXT: s_lshr_b32 s59, s14, 16 -; GFX11-NEXT: s_lshr_b32 s58, s14, 8 -; GFX11-NEXT: v_writelane_b32 v19, s43, 26 +; GFX11-NEXT: s_lshr_b32 s37, s5, 8 +; GFX11-NEXT: s_lshr_b32 s38, s4, 16 +; GFX11-NEXT: s_lshr_b32 s39, s4, 8 +; GFX11-NEXT: v_writelane_b32 v37, s43, 21 ; GFX11-NEXT: s_lshr_b32 s43, s20, 16 -; GFX11-NEXT: s_lshr_b32 s70, s41, 24 -; GFX11-NEXT: s_lshr_b32 s71, s41, 16 -; GFX11-NEXT: s_lshr_b32 s60, s41, 8 -; GFX11-NEXT: v_writelane_b32 v19, s43, 27 +; GFX11-NEXT: s_lshr_b32 s48, s7, 24 +; GFX11-NEXT: s_lshr_b32 s49, s7, 16 +; GFX11-NEXT: s_lshr_b32 s50, s7, 8 +; GFX11-NEXT: v_writelane_b32 v37, s43, 22 ; GFX11-NEXT: s_lshr_b32 s43, s20, 8 -; GFX11-NEXT: s_lshr_b32 s80, s40, 16 -; GFX11-NEXT: s_lshr_b32 s61, s40, 8 -; GFX11-NEXT: s_lshr_b32 s81, s29, 24 -; GFX11-NEXT: v_writelane_b32 v19, s43, 28 -; GFX11-NEXT: s_lshr_b32 s43, s19, 24 -; GFX11-NEXT: s_lshr_b32 s82, s29, 16 -; GFX11-NEXT: s_lshr_b32 s83, s29, 8 -; GFX11-NEXT: s_lshr_b32 s84, s28, 16 -; GFX11-NEXT: v_writelane_b32 v19, s43, 29 -; GFX11-NEXT: s_lshr_b32 s43, s19, 16 -; GFX11-NEXT: s_lshr_b32 s85, s28, 8 -; GFX11-NEXT: s_lshr_b32 s86, s27, 24 -; GFX11-NEXT: s_lshr_b32 s72, s27, 16 -; GFX11-NEXT: v_writelane_b32 v19, s43, 30 -; GFX11-NEXT: s_lshr_b32 s43, s19, 8 -; GFX11-NEXT: s_lshr_b32 s87, s27, 8 -; GFX11-NEXT: s_lshr_b32 s73, s26, 16 -; GFX11-NEXT: s_lshr_b32 s96, s26, 8 -; GFX11-NEXT: v_writelane_b32 v19, s43, 31 -; GFX11-NEXT: s_lshr_b32 s43, s18, 16 -; GFX11-NEXT: s_lshr_b32 s97, s25, 24 -; GFX11-NEXT: v_writelane_b32 v18, s43, 0 -; GFX11-NEXT: s_lshr_b32 s43, s18, 8 -; GFX11-NEXT: v_writelane_b32 v19, s62, 14 -; GFX11-NEXT: s_lshr_b32 s42, s25, 16 -; GFX11-NEXT: s_lshr_b32 s74, s2, 16 -; GFX11-NEXT: v_writelane_b32 v18, s43, 1 -; GFX11-NEXT: s_lshr_b32 s43, s17, 24 -; GFX11-NEXT: v_writelane_b32 v19, s63, 15 +; GFX11-NEXT: s_lshr_b32 s51, s6, 16 +; GFX11-NEXT: s_lshr_b32 s52, s6, 8 +; GFX11-NEXT: s_lshr_b32 s53, s9, 24 +; GFX11-NEXT: v_writelane_b32 v37, s43, 23 +; GFX11-NEXT: s_lshr_b32 s43, s23, 24 +; GFX11-NEXT: s_lshr_b32 s54, s9, 16 +; GFX11-NEXT: s_lshr_b32 s55, s9, 8 +; GFX11-NEXT: s_lshr_b32 s64, s8, 16 +; GFX11-NEXT: v_writelane_b32 v37, s43, 24 +; GFX11-NEXT: s_lshr_b32 s43, s23, 16 +; GFX11-NEXT: s_lshr_b32 s65, s8, 8 +; GFX11-NEXT: s_lshr_b32 s66, s11, 24 +; GFX11-NEXT: s_lshr_b32 s67, s11, 16 +; GFX11-NEXT: v_writelane_b32 v37, s43, 25 +; GFX11-NEXT: s_lshr_b32 s43, s23, 8 +; GFX11-NEXT: s_lshr_b32 s68, s11, 8 +; GFX11-NEXT: s_lshr_b32 s59, s10, 16 +; GFX11-NEXT: s_lshr_b32 s58, s10, 8 +; GFX11-NEXT: v_writelane_b32 v37, s43, 26 +; GFX11-NEXT: s_lshr_b32 s43, s22, 16 +; GFX11-NEXT: s_lshr_b32 s70, s13, 24 +; GFX11-NEXT: s_lshr_b32 s71, s13, 16 +; GFX11-NEXT: s_lshr_b32 s60, s13, 8 +; GFX11-NEXT: v_writelane_b32 v37, s43, 27 +; GFX11-NEXT: s_lshr_b32 s43, s22, 8 +; GFX11-NEXT: s_lshr_b32 s80, s12, 16 +; GFX11-NEXT: s_lshr_b32 s61, s12, 8 +; GFX11-NEXT: s_lshr_b32 s81, s15, 24 +; GFX11-NEXT: v_writelane_b32 v37, s43, 28 +; GFX11-NEXT: s_lshr_b32 s43, s25, 24 +; GFX11-NEXT: s_lshr_b32 s82, s15, 16 +; GFX11-NEXT: s_lshr_b32 s83, s15, 8 +; GFX11-NEXT: s_lshr_b32 s84, s14, 16 +; GFX11-NEXT: v_writelane_b32 v37, s43, 29 +; GFX11-NEXT: s_lshr_b32 s43, s25, 16 +; GFX11-NEXT: s_lshr_b32 s85, s14, 8 +; GFX11-NEXT: s_lshr_b32 s86, s17, 24 +; GFX11-NEXT: s_lshr_b32 s72, s17, 16 +; GFX11-NEXT: v_writelane_b32 v37, s43, 30 +; GFX11-NEXT: s_lshr_b32 s43, s25, 8 +; GFX11-NEXT: s_lshr_b32 s87, s17, 8 +; GFX11-NEXT: s_lshr_b32 s73, s16, 16 +; GFX11-NEXT: s_lshr_b32 s96, s16, 8 +; GFX11-NEXT: v_writelane_b32 v37, s43, 31 +; GFX11-NEXT: s_lshr_b32 s43, s24, 16 +; GFX11-NEXT: s_lshr_b32 s97, s19, 24 +; GFX11-NEXT: v_writelane_b32 v36, s43, 0 +; GFX11-NEXT: s_lshr_b32 s43, s24, 8 +; GFX11-NEXT: v_writelane_b32 v37, s62, 14 +; GFX11-NEXT: s_lshr_b32 s42, s19, 16 +; GFX11-NEXT: s_lshr_b32 s74, s28, 16 +; GFX11-NEXT: v_writelane_b32 v36, s43, 1 +; GFX11-NEXT: s_lshr_b32 s43, s27, 24 +; GFX11-NEXT: v_writelane_b32 v37, s63, 15 +; GFX11-NEXT: s_lshr_b64 s[62:63], s[2:3], 24 +; GFX11-NEXT: s_lshr_b32 s98, s41, 24 +; GFX11-NEXT: v_writelane_b32 v36, s43, 2 +; GFX11-NEXT: s_lshr_b32 s43, s27, 16 +; GFX11-NEXT: v_writelane_b32 v37, s62, 12 +; GFX11-NEXT: s_lshr_b32 s99, s41, 16 +; GFX11-NEXT: s_lshr_b32 s100, s41, 8 +; GFX11-NEXT: v_writelane_b32 v36, s43, 3 +; GFX11-NEXT: s_lshr_b32 s43, s27, 8 +; GFX11-NEXT: v_writelane_b32 v37, s63, 13 +; GFX11-NEXT: s_lshr_b64 s[62:63], s[4:5], 24 +; GFX11-NEXT: s_lshr_b32 s44, s40, 16 +; GFX11-NEXT: v_writelane_b32 v36, s43, 4 +; GFX11-NEXT: s_lshr_b32 s43, s26, 16 +; GFX11-NEXT: v_writelane_b32 v37, s62, 10 +; GFX11-NEXT: s_lshr_b32 s45, s40, 8 +; GFX11-NEXT: s_lshr_b64 s[76:77], s[16:17], 24 +; GFX11-NEXT: v_writelane_b32 v36, s43, 5 +; GFX11-NEXT: s_lshr_b32 s43, s26, 8 +; GFX11-NEXT: v_writelane_b32 v37, s63, 11 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[6:7], 24 -; GFX11-NEXT: s_lshr_b32 s98, s1, 24 -; GFX11-NEXT: v_writelane_b32 v18, s43, 2 -; GFX11-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-NEXT: v_writelane_b32 v19, s62, 12 -; GFX11-NEXT: s_lshr_b32 s99, s1, 16 -; GFX11-NEXT: s_lshr_b32 s100, s1, 8 -; GFX11-NEXT: v_writelane_b32 v18, s43, 3 -; GFX11-NEXT: s_lshr_b32 s43, s17, 8 -; GFX11-NEXT: v_writelane_b32 v19, s63, 13 +; GFX11-NEXT: s_lshr_b64 s[88:89], s[18:19], 24 +; GFX11-NEXT: v_writelane_b32 v36, s43, 6 +; GFX11-NEXT: s_lshr_b32 s43, s29, 24 +; GFX11-NEXT: v_writelane_b32 v37, s62, 8 +; GFX11-NEXT: s_lshr_b64 s[78:79], s[22:23], 24 +; GFX11-NEXT: s_lshr_b64 s[90:91], s[24:25], 24 +; GFX11-NEXT: v_writelane_b32 v36, s43, 7 +; GFX11-NEXT: s_lshr_b32 s43, s29, 16 +; GFX11-NEXT: v_writelane_b32 v37, s63, 9 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[8:9], 24 -; GFX11-NEXT: s_lshr_b32 s44, s0, 16 -; GFX11-NEXT: v_writelane_b32 v18, s43, 4 -; GFX11-NEXT: s_lshr_b32 s43, s16, 16 -; GFX11-NEXT: v_writelane_b32 v19, s62, 10 -; GFX11-NEXT: s_lshr_b32 s45, s0, 8 -; GFX11-NEXT: s_lshr_b64 s[76:77], s[26:27], 24 -; GFX11-NEXT: v_writelane_b32 v18, s43, 5 -; GFX11-NEXT: s_lshr_b32 s43, s16, 8 -; GFX11-NEXT: v_writelane_b32 v19, s63, 11 +; GFX11-NEXT: s_lshr_b64 s[92:93], s[26:27], 24 +; GFX11-NEXT: v_writelane_b32 v36, s43, 8 +; GFX11-NEXT: s_lshr_b32 s43, s29, 8 +; GFX11-NEXT: v_writelane_b32 v37, s62, 6 +; GFX11-NEXT: s_lshr_b64 s[94:95], s[28:29], 24 +; GFX11-NEXT: s_lshr_b64 s[30:31], s[40:41], 24 +; GFX11-NEXT: v_writelane_b32 v36, s43, 9 +; GFX11-NEXT: s_lshr_b32 s43, s28, 8 +; GFX11-NEXT: v_writelane_b32 v37, s63, 7 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[10:11], 24 -; GFX11-NEXT: s_lshr_b64 s[88:89], s[24:25], 24 -; GFX11-NEXT: v_writelane_b32 v18, s43, 6 -; GFX11-NEXT: s_lshr_b32 s43, s3, 24 -; GFX11-NEXT: v_writelane_b32 v19, s62, 8 -; GFX11-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 -; GFX11-NEXT: s_lshr_b64 s[90:91], s[18:19], 24 -; GFX11-NEXT: v_writelane_b32 v18, s43, 7 -; GFX11-NEXT: s_lshr_b32 s43, s3, 16 -; GFX11-NEXT: v_writelane_b32 v19, s63, 9 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_writelane_b32 v37, s62, 4 +; GFX11-NEXT: v_writelane_b32 v37, s63, 5 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 -; GFX11-NEXT: s_lshr_b64 s[92:93], s[16:17], 24 -; GFX11-NEXT: v_writelane_b32 v18, s43, 8 -; GFX11-NEXT: s_lshr_b32 s43, s3, 8 -; GFX11-NEXT: v_writelane_b32 v19, s62, 6 -; GFX11-NEXT: s_lshr_b64 s[94:95], s[2:3], 24 -; GFX11-NEXT: s_lshr_b64 s[30:31], s[0:1], 24 -; GFX11-NEXT: v_writelane_b32 v18, s43, 9 -; GFX11-NEXT: s_lshr_b32 s43, s2, 8 -; GFX11-NEXT: v_writelane_b32 v19, s63, 7 +; GFX11-NEXT: v_writelane_b32 v37, s62, 2 +; GFX11-NEXT: v_writelane_b32 v37, s63, 3 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[14:15], 24 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_writelane_b32 v19, s62, 4 -; GFX11-NEXT: v_writelane_b32 v19, s63, 5 -; GFX11-NEXT: s_lshr_b64 s[62:63], s[40:41], 24 -; GFX11-NEXT: v_writelane_b32 v19, s62, 2 -; GFX11-NEXT: v_writelane_b32 v19, s63, 3 -; GFX11-NEXT: s_lshr_b64 s[62:63], s[28:29], 24 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_writelane_b32 v19, s62, 0 -; GFX11-NEXT: v_writelane_b32 v19, s63, 1 -; GFX11-NEXT: s_lshr_b64 s[62:63], s[22:23], 24 +; GFX11-NEXT: v_writelane_b32 v37, s62, 0 +; GFX11-NEXT: v_writelane_b32 v37, s63, 1 +; GFX11-NEXT: s_lshr_b64 s[62:63], s[20:21], 24 ; GFX11-NEXT: s_branch .LBB13_3 ; GFX11-NEXT: .LBB13_2: ; GFX11-NEXT: ; implicit-def: $vcc_hi @@ -10879,7 +10990,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: s_mov_b32 s101, -1 -; GFX11-NEXT: v_writelane_b32 v19, vcc_lo, 0 +; GFX11-NEXT: v_writelane_b32 v37, vcc_lo, 0 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr42 @@ -10889,7 +11000,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr42 -; GFX11-NEXT: v_writelane_b32 v19, vcc_hi, 1 +; GFX11-NEXT: v_writelane_b32 v37, vcc_hi, 1 ; GFX11-NEXT: ; implicit-def: $vcc_lo ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr42 @@ -10901,7 +11012,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr42 -; GFX11-NEXT: v_writelane_b32 v19, vcc_lo, 2 +; GFX11-NEXT: v_writelane_b32 v37, vcc_lo, 2 ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; kill: killed $sgpr42 @@ -10912,7 +11023,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr42 -; GFX11-NEXT: v_writelane_b32 v19, vcc_hi, 3 +; GFX11-NEXT: v_writelane_b32 v37, vcc_hi, 3 ; GFX11-NEXT: ; implicit-def: $vcc_lo ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr42 @@ -10924,7 +11035,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr42 -; GFX11-NEXT: v_writelane_b32 v19, vcc_lo, 4 +; GFX11-NEXT: v_writelane_b32 v37, vcc_lo, 4 ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; kill: killed $sgpr42 @@ -10935,7 +11046,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr42 -; GFX11-NEXT: v_writelane_b32 v19, vcc_hi, 5 +; GFX11-NEXT: v_writelane_b32 v37, vcc_hi, 5 ; GFX11-NEXT: ; implicit-def: $vcc_lo ; GFX11-NEXT: ; implicit-def: $sgpr45 ; GFX11-NEXT: ; implicit-def: $sgpr44 @@ -10999,20 +11110,20 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX11-NEXT: ; implicit-def: $sgpr104 ; GFX11-NEXT: ; implicit-def: $sgpr88 ; GFX11-NEXT: ; implicit-def: $sgpr76 -; GFX11-NEXT: v_writelane_b32 v19, vcc_lo, 6 -; GFX11-NEXT: v_writelane_b32 v19, vcc_hi, 7 +; GFX11-NEXT: v_writelane_b32 v37, vcc_lo, 6 +; GFX11-NEXT: v_writelane_b32 v37, vcc_hi, 7 ; GFX11-NEXT: ; implicit-def: $vcc_lo -; GFX11-NEXT: v_writelane_b32 v19, vcc_lo, 8 -; GFX11-NEXT: v_writelane_b32 v19, vcc_hi, 9 +; GFX11-NEXT: v_writelane_b32 v37, vcc_lo, 8 +; GFX11-NEXT: v_writelane_b32 v37, vcc_hi, 9 ; GFX11-NEXT: ; implicit-def: $vcc_lo -; GFX11-NEXT: v_writelane_b32 v19, vcc_lo, 10 -; GFX11-NEXT: v_writelane_b32 v19, vcc_hi, 11 +; GFX11-NEXT: v_writelane_b32 v37, vcc_lo, 10 +; GFX11-NEXT: v_writelane_b32 v37, vcc_hi, 11 ; GFX11-NEXT: ; implicit-def: $vcc_lo -; GFX11-NEXT: v_writelane_b32 v19, vcc_lo, 12 -; GFX11-NEXT: v_writelane_b32 v19, vcc_hi, 13 +; GFX11-NEXT: v_writelane_b32 v37, vcc_lo, 12 +; GFX11-NEXT: v_writelane_b32 v37, vcc_hi, 13 ; GFX11-NEXT: ; implicit-def: $vcc_lo -; GFX11-NEXT: v_writelane_b32 v19, vcc_lo, 14 -; GFX11-NEXT: v_writelane_b32 v19, vcc_hi, 15 +; GFX11-NEXT: v_writelane_b32 v37, vcc_lo, 14 +; GFX11-NEXT: v_writelane_b32 v37, vcc_hi, 15 ; GFX11-NEXT: .LBB13_3: ; %Flow ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s101 ; GFX11-NEXT: s_mov_b32 s101, s104 @@ -11021,587 +11132,588 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3 ; GFX11-NEXT: s_mov_b32 s69, s42 ; GFX11-NEXT: s_cbranch_vccnz .LBB13_5 ; GFX11-NEXT: ; %bb.4: ; %cmp.true -; GFX11-NEXT: s_add_i32 s25, s25, 3 -; GFX11-NEXT: s_add_i32 s24, s24, 3 -; GFX11-NEXT: s_lshr_b32 s42, s25, 8 -; GFX11-NEXT: s_add_i32 s23, s23, 3 -; GFX11-NEXT: v_writelane_b32 v19, s42, 16 -; GFX11-NEXT: s_lshr_b32 s42, s24, 16 -; GFX11-NEXT: s_add_i32 s22, s22, 3 +; GFX11-NEXT: s_add_i32 s19, s19, 3 +; GFX11-NEXT: s_add_i32 s18, s18, 3 +; GFX11-NEXT: s_lshr_b32 s42, s19, 8 ; GFX11-NEXT: s_add_i32 s21, s21, 3 +; GFX11-NEXT: v_writelane_b32 v37, s42, 16 +; GFX11-NEXT: s_lshr_b32 s42, s18, 16 ; GFX11-NEXT: s_add_i32 s20, s20, 3 -; GFX11-NEXT: v_writelane_b32 v19, s42, 17 -; GFX11-NEXT: s_lshr_b32 s42, s24, 8 -; GFX11-NEXT: s_add_i32 s19, s19, 3 +; GFX11-NEXT: s_add_i32 s23, s23, 3 +; GFX11-NEXT: s_add_i32 s22, s22, 3 +; GFX11-NEXT: v_writelane_b32 v37, s42, 17 +; GFX11-NEXT: s_lshr_b32 s42, s18, 8 +; GFX11-NEXT: s_add_i32 s25, s25, 3 +; GFX11-NEXT: s_add_i32 s1, s1, 3 +; GFX11-NEXT: s_add_i32 s0, s0, 3 +; GFX11-NEXT: v_writelane_b32 v37, s42, 18 +; GFX11-NEXT: s_lshr_b32 s42, s21, 24 +; GFX11-NEXT: s_lshr_b64 s[62:63], s[0:1], 24 +; GFX11-NEXT: s_add_i32 s3, s3, 3 +; GFX11-NEXT: s_add_i32 s2, s2, 3 +; GFX11-NEXT: v_writelane_b32 v37, s42, 19 +; GFX11-NEXT: s_lshr_b32 s42, s21, 16 ; GFX11-NEXT: s_add_i32 s5, s5, 3 ; GFX11-NEXT: s_add_i32 s4, s4, 3 -; GFX11-NEXT: v_writelane_b32 v19, s42, 18 -; GFX11-NEXT: s_lshr_b32 s42, s23, 24 -; GFX11-NEXT: s_lshr_b64 s[62:63], s[4:5], 24 ; GFX11-NEXT: s_add_i32 s7, s7, 3 +; GFX11-NEXT: v_writelane_b32 v37, s42, 20 +; GFX11-NEXT: s_lshr_b32 s42, s21, 8 ; GFX11-NEXT: s_add_i32 s6, s6, 3 -; GFX11-NEXT: v_writelane_b32 v19, s42, 19 -; GFX11-NEXT: s_lshr_b32 s42, s23, 16 +; GFX11-NEXT: s_add_i32 s24, s24, 3 ; GFX11-NEXT: s_add_i32 s9, s9, 3 +; GFX11-NEXT: v_writelane_b32 v37, s42, 21 +; GFX11-NEXT: s_lshr_b32 s42, s20, 16 ; GFX11-NEXT: s_add_i32 s8, s8, 3 +; GFX11-NEXT: s_add_i32 s27, s27, 3 ; GFX11-NEXT: s_add_i32 s11, s11, 3 -; GFX11-NEXT: v_writelane_b32 v19, s42, 20 -; GFX11-NEXT: s_lshr_b32 s42, s23, 8 +; GFX11-NEXT: v_writelane_b32 v37, s42, 22 +; GFX11-NEXT: s_lshr_b32 s42, s20, 8 ; GFX11-NEXT: s_add_i32 s10, s10, 3 -; GFX11-NEXT: s_add_i32 s18, s18, 3 +; GFX11-NEXT: s_add_i32 s26, s26, 3 ; GFX11-NEXT: s_add_i32 s13, s13, 3 -; GFX11-NEXT: v_writelane_b32 v19, s42, 21 -; GFX11-NEXT: s_lshr_b32 s42, s22, 16 +; GFX11-NEXT: v_writelane_b32 v37, s42, 23 +; GFX11-NEXT: s_lshr_b32 s42, s23, 24 ; GFX11-NEXT: s_add_i32 s12, s12, 3 -; GFX11-NEXT: s_add_i32 s17, s17, 3 +; GFX11-NEXT: s_add_i32 s29, s29, 3 ; GFX11-NEXT: s_add_i32 s15, s15, 3 -; GFX11-NEXT: v_writelane_b32 v19, s42, 22 -; GFX11-NEXT: s_lshr_b32 s42, s22, 8 +; GFX11-NEXT: v_writelane_b32 v37, s42, 24 +; GFX11-NEXT: s_lshr_b32 s42, s23, 16 ; GFX11-NEXT: s_add_i32 s14, s14, 3 -; GFX11-NEXT: s_add_i32 s16, s16, 3 ; GFX11-NEXT: s_add_i32 s41, s41, 3 -; GFX11-NEXT: v_writelane_b32 v19, s42, 23 -; GFX11-NEXT: s_lshr_b32 s42, s21, 24 ; GFX11-NEXT: s_add_i32 s40, s40, 3 -; GFX11-NEXT: s_add_i32 s3, s3, 3 -; GFX11-NEXT: s_add_i32 s29, s29, 3 -; GFX11-NEXT: v_writelane_b32 v19, s42, 24 -; GFX11-NEXT: s_lshr_b32 s42, s21, 16 +; GFX11-NEXT: v_writelane_b32 v37, s42, 25 +; GFX11-NEXT: s_lshr_b32 s42, s23, 8 ; GFX11-NEXT: s_add_i32 s28, s28, 3 -; GFX11-NEXT: s_add_i32 s1, s1, 3 -; GFX11-NEXT: s_add_i32 s0, s0, 3 -; GFX11-NEXT: v_writelane_b32 v19, s42, 25 -; GFX11-NEXT: s_lshr_b32 s42, s21, 8 -; GFX11-NEXT: s_add_i32 s2, s2, 3 -; GFX11-NEXT: s_add_i32 s27, s27, 3 -; GFX11-NEXT: s_add_i32 s26, s26, 3 -; GFX11-NEXT: v_writelane_b32 v19, s42, 26 -; GFX11-NEXT: s_lshr_b32 s42, s20, 16 -; GFX11-NEXT: s_lshr_b32 s101, s5, 24 -; GFX11-NEXT: s_lshr_b32 s102, s5, 16 -; GFX11-NEXT: s_lshr_b32 s103, s5, 8 -; GFX11-NEXT: v_writelane_b32 v19, s42, 27 -; GFX11-NEXT: s_lshr_b32 s42, s20, 8 -; GFX11-NEXT: s_lshr_b32 s104, s4, 16 -; GFX11-NEXT: s_lshr_b32 s47, s4, 8 -; GFX11-NEXT: s_lshr_b32 s46, s7, 24 -; GFX11-NEXT: v_writelane_b32 v19, s42, 28 -; GFX11-NEXT: s_lshr_b32 s42, s19, 24 -; GFX11-NEXT: s_lshr_b32 vcc_hi, s7, 16 -; GFX11-NEXT: s_lshr_b32 s34, s7, 8 -; GFX11-NEXT: s_lshr_b32 s57, s6, 16 -; GFX11-NEXT: v_writelane_b32 v19, s42, 29 -; GFX11-NEXT: s_lshr_b32 s42, s19, 16 -; GFX11-NEXT: s_lshr_b32 s56, s6, 8 -; GFX11-NEXT: s_lshr_b32 s35, s9, 24 -; GFX11-NEXT: s_lshr_b32 s36, s9, 16 -; GFX11-NEXT: v_writelane_b32 v19, s42, 30 -; GFX11-NEXT: s_lshr_b32 s42, s19, 8 -; GFX11-NEXT: s_lshr_b32 s37, s9, 8 -; GFX11-NEXT: s_lshr_b32 s38, s8, 16 -; GFX11-NEXT: s_lshr_b32 s39, s8, 8 -; GFX11-NEXT: v_writelane_b32 v19, s42, 31 -; GFX11-NEXT: s_lshr_b32 s42, s18, 16 -; GFX11-NEXT: s_lshr_b32 s48, s11, 24 -; GFX11-NEXT: v_writelane_b32 v18, s42, 0 -; GFX11-NEXT: s_lshr_b32 s42, s18, 8 -; GFX11-NEXT: v_writelane_b32 v19, s62, 14 -; GFX11-NEXT: s_lshr_b32 s49, s11, 16 -; GFX11-NEXT: s_lshr_b32 s50, s11, 8 -; GFX11-NEXT: v_writelane_b32 v18, s42, 1 -; GFX11-NEXT: s_lshr_b32 s42, s17, 24 -; GFX11-NEXT: v_writelane_b32 v19, s63, 15 +; GFX11-NEXT: s_add_i32 s17, s17, 3 +; GFX11-NEXT: s_add_i32 s16, s16, 3 +; GFX11-NEXT: v_writelane_b32 v37, s42, 26 +; GFX11-NEXT: s_lshr_b32 s42, s22, 16 +; GFX11-NEXT: s_lshr_b32 s101, s1, 24 +; GFX11-NEXT: s_lshr_b32 s102, s1, 16 +; GFX11-NEXT: s_lshr_b32 s103, s1, 8 +; GFX11-NEXT: v_writelane_b32 v37, s42, 27 +; GFX11-NEXT: s_lshr_b32 s42, s22, 8 +; GFX11-NEXT: s_lshr_b32 s104, s0, 16 +; GFX11-NEXT: s_lshr_b32 s47, s0, 8 +; GFX11-NEXT: s_lshr_b32 s46, s3, 24 +; GFX11-NEXT: v_writelane_b32 v37, s42, 28 +; GFX11-NEXT: s_lshr_b32 s42, s25, 24 +; GFX11-NEXT: s_lshr_b32 vcc_hi, s3, 16 +; GFX11-NEXT: s_lshr_b32 s34, s3, 8 +; GFX11-NEXT: s_lshr_b32 s57, s2, 16 +; GFX11-NEXT: v_writelane_b32 v37, s42, 29 +; GFX11-NEXT: s_lshr_b32 s42, s25, 16 +; GFX11-NEXT: s_lshr_b32 s56, s2, 8 +; GFX11-NEXT: s_lshr_b32 s35, s5, 24 +; GFX11-NEXT: s_lshr_b32 s36, s5, 16 +; GFX11-NEXT: v_writelane_b32 v37, s42, 30 +; GFX11-NEXT: s_lshr_b32 s42, s25, 8 +; GFX11-NEXT: s_lshr_b32 s37, s5, 8 +; GFX11-NEXT: s_lshr_b32 s38, s4, 16 +; GFX11-NEXT: s_lshr_b32 s39, s4, 8 +; GFX11-NEXT: v_writelane_b32 v37, s42, 31 +; GFX11-NEXT: s_lshr_b32 s42, s24, 16 +; GFX11-NEXT: s_lshr_b32 s48, s7, 24 +; GFX11-NEXT: v_writelane_b32 v36, s42, 0 +; GFX11-NEXT: s_lshr_b32 s42, s24, 8 +; GFX11-NEXT: v_writelane_b32 v37, s62, 14 +; GFX11-NEXT: s_lshr_b32 s49, s7, 16 +; GFX11-NEXT: s_lshr_b32 s50, s7, 8 +; GFX11-NEXT: v_writelane_b32 v36, s42, 1 +; GFX11-NEXT: s_lshr_b32 s42, s27, 24 +; GFX11-NEXT: v_writelane_b32 v37, s63, 15 +; GFX11-NEXT: s_lshr_b64 s[62:63], s[2:3], 24 +; GFX11-NEXT: s_lshr_b32 s51, s6, 16 +; GFX11-NEXT: v_writelane_b32 v36, s42, 2 +; GFX11-NEXT: s_lshr_b32 s42, s27, 16 +; GFX11-NEXT: v_writelane_b32 v37, s62, 12 +; GFX11-NEXT: s_lshr_b32 s52, s6, 8 +; GFX11-NEXT: s_lshr_b32 s53, s9, 24 +; GFX11-NEXT: v_writelane_b32 v36, s42, 3 +; GFX11-NEXT: s_lshr_b32 s42, s27, 8 +; GFX11-NEXT: v_writelane_b32 v37, s63, 13 +; GFX11-NEXT: s_lshr_b64 s[62:63], s[4:5], 24 +; GFX11-NEXT: s_lshr_b32 s54, s9, 16 +; GFX11-NEXT: v_writelane_b32 v36, s42, 4 +; GFX11-NEXT: s_lshr_b32 s42, s26, 16 +; GFX11-NEXT: v_writelane_b32 v37, s62, 10 +; GFX11-NEXT: s_lshr_b32 s55, s9, 8 +; GFX11-NEXT: s_lshr_b32 s64, s8, 16 +; GFX11-NEXT: v_writelane_b32 v36, s42, 5 +; GFX11-NEXT: s_lshr_b32 s42, s26, 8 +; GFX11-NEXT: v_writelane_b32 v37, s63, 11 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[6:7], 24 -; GFX11-NEXT: s_lshr_b32 s51, s10, 16 -; GFX11-NEXT: v_writelane_b32 v18, s42, 2 -; GFX11-NEXT: s_lshr_b32 s42, s17, 16 -; GFX11-NEXT: v_writelane_b32 v19, s62, 12 -; GFX11-NEXT: s_lshr_b32 s52, s10, 8 -; GFX11-NEXT: s_lshr_b32 s53, s13, 24 -; GFX11-NEXT: v_writelane_b32 v18, s42, 3 -; GFX11-NEXT: s_lshr_b32 s42, s17, 8 -; GFX11-NEXT: v_writelane_b32 v19, s63, 13 +; GFX11-NEXT: s_lshr_b32 s65, s8, 8 +; GFX11-NEXT: v_writelane_b32 v36, s42, 6 +; GFX11-NEXT: s_lshr_b32 s42, s29, 24 +; GFX11-NEXT: v_writelane_b32 v37, s62, 8 +; GFX11-NEXT: s_lshr_b32 s66, s11, 24 +; GFX11-NEXT: s_lshr_b32 s67, s11, 16 +; GFX11-NEXT: v_writelane_b32 v36, s42, 7 +; GFX11-NEXT: s_lshr_b32 s42, s29, 16 +; GFX11-NEXT: v_writelane_b32 v37, s63, 9 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[8:9], 24 -; GFX11-NEXT: s_lshr_b32 s54, s13, 16 -; GFX11-NEXT: v_writelane_b32 v18, s42, 4 -; GFX11-NEXT: s_lshr_b32 s42, s16, 16 -; GFX11-NEXT: v_writelane_b32 v19, s62, 10 -; GFX11-NEXT: s_lshr_b32 s55, s13, 8 -; GFX11-NEXT: s_lshr_b32 s64, s12, 16 -; GFX11-NEXT: v_writelane_b32 v18, s42, 5 -; GFX11-NEXT: s_lshr_b32 s42, s16, 8 -; GFX11-NEXT: v_writelane_b32 v19, s63, 11 +; GFX11-NEXT: s_lshr_b32 s68, s11, 8 +; GFX11-NEXT: v_writelane_b32 v36, s42, 8 +; GFX11-NEXT: s_lshr_b32 s59, s10, 16 +; GFX11-NEXT: v_writelane_b32 v37, s62, 6 +; GFX11-NEXT: s_lshr_b32 s58, s10, 8 +; GFX11-NEXT: s_lshr_b32 s70, s13, 24 +; GFX11-NEXT: s_lshr_b32 s71, s13, 16 +; GFX11-NEXT: s_lshr_b32 s60, s13, 8 +; GFX11-NEXT: v_writelane_b32 v37, s63, 7 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[10:11], 24 -; GFX11-NEXT: s_lshr_b32 s65, s12, 8 -; GFX11-NEXT: v_writelane_b32 v18, s42, 6 -; GFX11-NEXT: s_lshr_b32 s42, s3, 24 -; GFX11-NEXT: v_writelane_b32 v19, s62, 8 -; GFX11-NEXT: s_lshr_b32 s66, s15, 24 -; GFX11-NEXT: s_lshr_b32 s67, s15, 16 -; GFX11-NEXT: v_writelane_b32 v18, s42, 7 -; GFX11-NEXT: s_lshr_b32 s42, s3, 16 -; GFX11-NEXT: v_writelane_b32 v19, s63, 9 +; GFX11-NEXT: s_lshr_b32 s80, s12, 16 +; GFX11-NEXT: s_lshr_b32 s61, s12, 8 +; GFX11-NEXT: s_lshr_b32 s81, s15, 24 +; GFX11-NEXT: v_writelane_b32 v37, s62, 4 +; GFX11-NEXT: s_lshr_b32 s82, s15, 16 +; GFX11-NEXT: s_lshr_b32 s83, s15, 8 +; GFX11-NEXT: s_lshr_b32 s84, s14, 16 +; GFX11-NEXT: s_lshr_b32 s85, s14, 8 +; GFX11-NEXT: v_writelane_b32 v37, s63, 5 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 -; GFX11-NEXT: s_lshr_b32 s68, s15, 8 -; GFX11-NEXT: v_writelane_b32 v18, s42, 8 -; GFX11-NEXT: s_lshr_b32 s59, s14, 16 -; GFX11-NEXT: v_writelane_b32 v19, s62, 6 -; GFX11-NEXT: s_lshr_b32 s58, s14, 8 -; GFX11-NEXT: s_lshr_b32 s70, s41, 24 -; GFX11-NEXT: s_lshr_b32 s71, s41, 16 -; GFX11-NEXT: s_lshr_b32 s60, s41, 8 -; GFX11-NEXT: v_writelane_b32 v19, s63, 7 +; GFX11-NEXT: s_lshr_b32 s86, s17, 24 +; GFX11-NEXT: s_lshr_b32 s72, s17, 16 +; GFX11-NEXT: s_lshr_b32 s87, s17, 8 +; GFX11-NEXT: v_writelane_b32 v37, s62, 2 +; GFX11-NEXT: s_lshr_b32 s73, s16, 16 +; GFX11-NEXT: s_lshr_b32 s96, s16, 8 +; GFX11-NEXT: s_lshr_b32 s97, s19, 24 +; GFX11-NEXT: s_lshr_b32 s69, s19, 16 +; GFX11-NEXT: v_writelane_b32 v37, s63, 3 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[14:15], 24 -; GFX11-NEXT: s_lshr_b32 s80, s40, 16 -; GFX11-NEXT: s_lshr_b32 s61, s40, 8 -; GFX11-NEXT: s_lshr_b32 s81, s29, 24 -; GFX11-NEXT: v_writelane_b32 v19, s62, 4 -; GFX11-NEXT: s_lshr_b32 s82, s29, 16 -; GFX11-NEXT: s_lshr_b32 s83, s29, 8 -; GFX11-NEXT: s_lshr_b32 s84, s28, 16 -; GFX11-NEXT: s_lshr_b32 s85, s28, 8 -; GFX11-NEXT: v_writelane_b32 v19, s63, 5 -; GFX11-NEXT: s_lshr_b64 s[62:63], s[40:41], 24 -; GFX11-NEXT: s_lshr_b32 s86, s27, 24 -; GFX11-NEXT: s_lshr_b32 s72, s27, 16 -; GFX11-NEXT: s_lshr_b32 s87, s27, 8 -; GFX11-NEXT: v_writelane_b32 v19, s62, 2 -; GFX11-NEXT: s_lshr_b32 s73, s26, 16 -; GFX11-NEXT: s_lshr_b32 s96, s26, 8 -; GFX11-NEXT: s_lshr_b32 s97, s25, 24 -; GFX11-NEXT: s_lshr_b32 s69, s25, 16 -; GFX11-NEXT: v_writelane_b32 v19, s63, 3 -; GFX11-NEXT: s_lshr_b64 s[62:63], s[28:29], 24 -; GFX11-NEXT: s_lshr_b32 s42, s3, 8 -; GFX11-NEXT: s_lshr_b32 s74, s2, 16 -; GFX11-NEXT: s_lshr_b32 s43, s2, 8 -; GFX11-NEXT: v_writelane_b32 v19, s62, 0 -; GFX11-NEXT: s_lshr_b32 s98, s1, 24 -; GFX11-NEXT: s_lshr_b32 s99, s1, 16 -; GFX11-NEXT: s_lshr_b32 s100, s1, 8 -; GFX11-NEXT: s_lshr_b32 s44, s0, 16 -; GFX11-NEXT: s_lshr_b32 s45, s0, 8 -; GFX11-NEXT: v_writelane_b32 v19, s63, 1 -; GFX11-NEXT: s_lshr_b64 s[76:77], s[26:27], 24 -; GFX11-NEXT: s_lshr_b64 s[88:89], s[24:25], 24 -; GFX11-NEXT: s_lshr_b64 s[62:63], s[22:23], 24 -; GFX11-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 -; GFX11-NEXT: s_lshr_b64 s[90:91], s[18:19], 24 -; GFX11-NEXT: s_lshr_b64 s[92:93], s[16:17], 24 -; GFX11-NEXT: s_lshr_b64 s[94:95], s[2:3], 24 -; GFX11-NEXT: s_lshr_b64 s[30:31], s[0:1], 24 -; GFX11-NEXT: v_writelane_b32 v18, s42, 9 +; GFX11-NEXT: s_lshr_b32 s42, s29, 8 +; GFX11-NEXT: s_lshr_b32 s74, s28, 16 +; GFX11-NEXT: s_lshr_b32 s43, s28, 8 +; GFX11-NEXT: v_writelane_b32 v37, s62, 0 +; GFX11-NEXT: s_lshr_b32 s98, s41, 24 +; GFX11-NEXT: s_lshr_b32 s99, s41, 16 +; GFX11-NEXT: s_lshr_b32 s100, s41, 8 +; GFX11-NEXT: s_lshr_b32 s44, s40, 16 +; GFX11-NEXT: s_lshr_b32 s45, s40, 8 +; GFX11-NEXT: v_writelane_b32 v37, s63, 1 +; GFX11-NEXT: s_lshr_b64 s[76:77], s[16:17], 24 +; GFX11-NEXT: s_lshr_b64 s[88:89], s[18:19], 24 +; GFX11-NEXT: s_lshr_b64 s[62:63], s[20:21], 24 +; GFX11-NEXT: s_lshr_b64 s[78:79], s[22:23], 24 +; GFX11-NEXT: s_lshr_b64 s[90:91], s[24:25], 24 +; GFX11-NEXT: s_lshr_b64 s[92:93], s[26:27], 24 +; GFX11-NEXT: s_lshr_b64 s[94:95], s[28:29], 24 +; GFX11-NEXT: s_lshr_b64 s[30:31], s[40:41], 24 +; GFX11-NEXT: v_writelane_b32 v36, s42, 9 ; GFX11-NEXT: .LBB13_5: ; %end ; GFX11-NEXT: s_lshl_b32 s43, s43, 8 -; GFX11-NEXT: s_and_b32 s2, s2, 0xff +; GFX11-NEXT: s_and_b32 s28, s28, 0xff ; GFX11-NEXT: s_and_b32 s42, s74, 0xff -; GFX11-NEXT: s_or_b32 s2, s2, s43 +; GFX11-NEXT: s_or_b32 s28, s28, s43 ; GFX11-NEXT: s_lshl_b32 s43, s94, 8 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_and_b32 s28, s28, 0xffff +; GFX11-NEXT: s_or_b32 s42, s42, s43 +; GFX11-NEXT: s_and_b32 s29, s29, 0xff +; GFX11-NEXT: s_lshl_b32 s42, s42, 16 +; GFX11-NEXT: v_readlane_b32 s43, v36, 7 +; GFX11-NEXT: s_or_b32 s28, s28, s42 +; GFX11-NEXT: v_readlane_b32 s42, v36, 9 +; GFX11-NEXT: s_and_b32 s26, s26, 0xff +; GFX11-NEXT: s_and_b32 s27, s27, 0xff +; GFX11-NEXT: s_lshl_b32 s43, s43, 8 +; GFX11-NEXT: s_and_b32 s24, s24, 0xff +; GFX11-NEXT: s_lshl_b32 s42, s42, 8 +; GFX11-NEXT: s_and_b32 s25, s25, 0xff +; GFX11-NEXT: s_or_b32 s29, s29, s42 +; GFX11-NEXT: v_readlane_b32 s42, v36, 8 +; GFX11-NEXT: s_and_b32 s29, s29, 0xffff +; GFX11-NEXT: s_and_b32 s22, s22, 0xff +; GFX11-NEXT: s_and_b32 s23, s23, 0xff +; GFX11-NEXT: s_and_b32 s20, s20, 0xff +; GFX11-NEXT: s_and_b32 s42, s42, 0xff +; GFX11-NEXT: s_and_b32 s21, s21, 0xff ; GFX11-NEXT: s_or_b32 s42, s42, s43 ; GFX11-NEXT: s_lshl_b32 s45, s45, 8 ; GFX11-NEXT: s_lshl_b32 s42, s42, 16 -; GFX11-NEXT: s_and_b32 s0, s0, 0xff -; GFX11-NEXT: s_or_b32 s2, s2, s42 -; GFX11-NEXT: v_readlane_b32 s42, v18, 9 -; GFX11-NEXT: s_or_b32 s0, s0, s45 +; GFX11-NEXT: s_and_b32 s40, s40, 0xff +; GFX11-NEXT: s_or_b32 s29, s29, s42 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v3, s28 :: v_dual_mov_b32 v4, s29 +; GFX11-NEXT: v_readlane_b32 s28, v36, 6 +; GFX11-NEXT: v_readlane_b32 s29, v36, 5 +; GFX11-NEXT: s_or_b32 s40, s40, s45 ; GFX11-NEXT: s_lshl_b32 s45, s30, 8 ; GFX11-NEXT: s_and_b32 s44, s44, 0xff -; GFX11-NEXT: s_and_b32 s3, s3, 0xff +; GFX11-NEXT: s_lshl_b32 s28, s28, 8 +; GFX11-NEXT: s_and_b32 s29, s29, 0xff +; GFX11-NEXT: s_or_b32 s26, s26, s28 +; GFX11-NEXT: s_lshl_b32 s28, s92, 8 +; GFX11-NEXT: s_and_b32 s26, s26, 0xffff +; GFX11-NEXT: s_or_b32 s28, s29, s28 +; GFX11-NEXT: v_readlane_b32 s29, v36, 2 +; GFX11-NEXT: s_lshl_b32 s28, s28, 16 ; GFX11-NEXT: s_or_b32 s44, s44, s45 -; GFX11-NEXT: s_lshl_b32 s42, s42, 8 -; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_or_b32 s26, s26, s28 +; GFX11-NEXT: v_readlane_b32 s28, v36, 4 +; GFX11-NEXT: s_lshl_b32 s29, s29, 8 +; GFX11-NEXT: s_and_b32 s18, s18, 0xff +; GFX11-NEXT: s_and_b32 s40, s40, 0xffff ; GFX11-NEXT: s_lshl_b32 s44, s44, 16 -; GFX11-NEXT: s_or_b32 s3, s3, s42 -; GFX11-NEXT: v_readlane_b32 s42, v18, 8 -; GFX11-NEXT: v_readlane_b32 s43, v18, 7 -; GFX11-NEXT: s_or_b32 s0, s0, s44 -; GFX11-NEXT: s_and_b32 s1, s1, 0xff +; GFX11-NEXT: s_lshl_b32 s28, s28, 8 +; GFX11-NEXT: s_or_b32 s40, s40, s44 +; GFX11-NEXT: s_or_b32 s27, s27, s28 +; GFX11-NEXT: v_readlane_b32 s28, v36, 3 +; GFX11-NEXT: s_and_b32 s27, s27, 0xffff +; GFX11-NEXT: s_and_b32 s41, s41, 0xff ; GFX11-NEXT: s_lshl_b32 s44, s100, 8 ; GFX11-NEXT: s_lshl_b32 s45, s98, 8 -; GFX11-NEXT: s_or_b32 s1, s1, s44 +; GFX11-NEXT: s_and_b32 s28, s28, 0xff +; GFX11-NEXT: s_or_b32 s41, s41, s44 +; GFX11-NEXT: s_or_b32 s28, s28, s29 +; GFX11-NEXT: v_readlane_b32 s29, v36, 0 +; GFX11-NEXT: s_lshl_b32 s28, s28, 16 ; GFX11-NEXT: s_and_b32 s44, s99, 0xff -; GFX11-NEXT: s_and_b32 s42, s42, 0xff +; GFX11-NEXT: s_or_b32 s27, s27, s28 +; GFX11-NEXT: v_readlane_b32 s28, v36, 1 +; GFX11-NEXT: s_and_b32 s29, s29, 0xff +; GFX11-NEXT: v_dual_mov_b32 v5, s26 :: v_dual_mov_b32 v6, s27 +; GFX11-NEXT: v_readlane_b32 s26, v37, 19 +; GFX11-NEXT: s_lshl_b32 s28, s28, 8 ; GFX11-NEXT: s_or_b32 s44, s44, s45 -; GFX11-NEXT: s_lshl_b32 s43, s43, 8 -; GFX11-NEXT: s_and_b32 s1, s1, 0xffff +; GFX11-NEXT: s_or_b32 s24, s24, s28 +; GFX11-NEXT: s_lshl_b32 s28, s90, 8 +; GFX11-NEXT: s_and_b32 s24, s24, 0xffff +; GFX11-NEXT: s_or_b32 s28, s29, s28 +; GFX11-NEXT: v_readlane_b32 s29, v37, 29 +; GFX11-NEXT: s_lshl_b32 s28, s28, 16 +; GFX11-NEXT: s_lshl_b32 s26, s26, 8 +; GFX11-NEXT: s_or_b32 s24, s24, s28 +; GFX11-NEXT: v_readlane_b32 s28, v37, 31 +; GFX11-NEXT: s_lshl_b32 s29, s29, 8 +; GFX11-NEXT: s_and_b32 s19, s19, 0xff +; GFX11-NEXT: s_and_b32 s41, s41, 0xffff ; GFX11-NEXT: s_lshl_b32 s44, s44, 16 -; GFX11-NEXT: s_or_b32 s42, s42, s43 -; GFX11-NEXT: s_or_b32 s1, s1, s44 -; GFX11-NEXT: s_and_b32 s3, s3, 0xffff -; GFX11-NEXT: s_lshl_b32 s42, s42, 16 -; GFX11-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1 -; GFX11-NEXT: v_readlane_b32 s0, v18, 6 -; GFX11-NEXT: s_or_b32 s3, s3, s42 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3 -; GFX11-NEXT: v_readlane_b32 s2, v18, 5 -; GFX11-NEXT: s_lshl_b32 s0, s0, 8 -; GFX11-NEXT: s_and_b32 s1, s16, 0xff -; GFX11-NEXT: v_readlane_b32 s3, v18, 2 -; GFX11-NEXT: s_or_b32 s0, s1, s0 -; GFX11-NEXT: s_lshl_b32 s1, s92, 8 -; GFX11-NEXT: s_and_b32 s2, s2, 0xff -; GFX11-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-NEXT: s_or_b32 s1, s2, s1 -; GFX11-NEXT: v_readlane_b32 s2, v18, 4 -; GFX11-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-NEXT: s_lshl_b32 s3, s3, 8 -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_and_b32 s1, s17, 0xff -; GFX11-NEXT: s_lshl_b32 s2, s2, 8 -; GFX11-NEXT: v_readlane_b32 s16, v18, 0 -; GFX11-NEXT: s_or_b32 s1, s1, s2 -; GFX11-NEXT: v_readlane_b32 s2, v18, 3 -; GFX11-NEXT: s_and_b32 s1, s1, 0xffff -; GFX11-NEXT: v_readlane_b32 s17, v19, 29 -; GFX11-NEXT: s_and_b32 s16, s16, 0xff -; GFX11-NEXT: v_readlane_b32 s100, v17, 4 -; GFX11-NEXT: s_and_b32 s2, s2, 0xff -; GFX11-NEXT: v_readlane_b32 s99, v17, 3 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_and_b32 s3, s18, 0xff -; GFX11-NEXT: s_lshl_b32 s2, s2, 16 -; GFX11-NEXT: s_lshl_b32 s17, s17, 8 -; GFX11-NEXT: s_or_b32 s1, s1, s2 -; GFX11-NEXT: v_readlane_b32 s2, v18, 1 -; GFX11-NEXT: v_dual_mov_b32 v5, s0 :: v_dual_mov_b32 v6, s1 -; GFX11-NEXT: v_readlane_b32 s0, v19, 28 -; GFX11-NEXT: s_and_b32 s1, s20, 0xff -; GFX11-NEXT: s_lshl_b32 s2, s2, 8 -; GFX11-NEXT: v_readlane_b32 s18, v19, 19 -; GFX11-NEXT: s_or_b32 s2, s3, s2 -; GFX11-NEXT: s_lshl_b32 s3, s90, 8 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_or_b32 s3, s16, s3 -; GFX11-NEXT: v_readlane_b32 s16, v19, 31 -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_lshl_b32 s0, s0, 8 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_and_b32 s3, s19, 0xff -; GFX11-NEXT: s_lshl_b32 s16, s16, 8 -; GFX11-NEXT: s_or_b32 s0, s1, s0 -; GFX11-NEXT: s_or_b32 s3, s3, s16 -; GFX11-NEXT: v_readlane_b32 s16, v19, 30 -; GFX11-NEXT: s_and_b32 s3, s3, 0xffff -; GFX11-NEXT: s_lshl_b32 s1, s78, 8 -; GFX11-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-NEXT: s_lshl_b32 s18, s18, 8 +; GFX11-NEXT: s_lshl_b32 s28, s28, 8 +; GFX11-NEXT: s_or_b32 s41, s41, s44 +; GFX11-NEXT: s_or_b32 s25, s25, s28 +; GFX11-NEXT: v_readlane_b32 s28, v37, 30 +; GFX11-NEXT: s_and_b32 s25, s25, 0xffff +; GFX11-NEXT: v_dual_mov_b32 v1, s40 :: v_dual_mov_b32 v2, s41 ; GFX11-NEXT: s_and_b32 s16, s16, 0xff -; GFX11-NEXT: s_lshl_b32 s19, s86, 8 -; GFX11-NEXT: s_or_b32 s16, s16, s17 -; GFX11-NEXT: v_readlane_b32 s17, v19, 21 -; GFX11-NEXT: s_lshl_b32 s16, s16, 16 -; GFX11-NEXT: v_readlane_b32 s98, v17, 2 -; GFX11-NEXT: s_or_b32 s3, s3, s16 +; GFX11-NEXT: s_and_b32 s28, s28, 0xff +; GFX11-NEXT: s_and_b32 s17, s17, 0xff +; GFX11-NEXT: s_or_b32 s28, s28, s29 +; GFX11-NEXT: s_and_b32 s14, s14, 0xff +; GFX11-NEXT: s_lshl_b32 s28, s28, 16 +; GFX11-NEXT: s_and_b32 s15, s15, 0xff +; GFX11-NEXT: s_or_b32 s25, s25, s28 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v8, s3 -; GFX11-NEXT: v_readlane_b32 s2, v19, 27 -; GFX11-NEXT: v_readlane_b32 s3, v19, 24 -; GFX11-NEXT: v_readlane_b32 s16, v19, 22 -; GFX11-NEXT: s_lshl_b32 s17, s17, 8 +; GFX11-NEXT: v_dual_mov_b32 v7, s24 :: v_dual_mov_b32 v8, s25 +; GFX11-NEXT: v_readlane_b32 s24, v37, 28 +; GFX11-NEXT: v_readlane_b32 s25, v37, 27 ; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off ; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:16 +; GFX11-NEXT: s_and_b32 s12, s12, 0xff +; GFX11-NEXT: s_lshl_b32 s24, s24, 8 +; GFX11-NEXT: s_and_b32 s25, s25, 0xff +; GFX11-NEXT: s_or_b32 s22, s22, s24 +; GFX11-NEXT: s_lshl_b32 s24, s78, 8 +; GFX11-NEXT: s_and_b32 s22, s22, 0xffff +; GFX11-NEXT: s_or_b32 s24, s25, s24 +; GFX11-NEXT: v_readlane_b32 s25, v37, 24 +; GFX11-NEXT: s_lshl_b32 s24, s24, 16 +; GFX11-NEXT: s_and_b32 s13, s13, 0xff +; GFX11-NEXT: s_or_b32 s22, s22, s24 +; GFX11-NEXT: v_readlane_b32 s24, v37, 26 +; GFX11-NEXT: s_lshl_b32 s25, s25, 8 +; GFX11-NEXT: s_and_b32 s10, s10, 0xff +; GFX11-NEXT: s_and_b32 s11, s11, 0xff +; GFX11-NEXT: s_and_b32 s8, s8, 0xff +; GFX11-NEXT: s_lshl_b32 s24, s24, 8 +; GFX11-NEXT: s_and_b32 s9, s9, 0xff +; GFX11-NEXT: s_or_b32 s23, s23, s24 +; GFX11-NEXT: v_readlane_b32 s24, v37, 25 +; GFX11-NEXT: s_and_b32 s23, s23, 0xffff +; GFX11-NEXT: s_and_b32 s6, s6, 0xff +; GFX11-NEXT: s_and_b32 s7, s7, 0xff +; GFX11-NEXT: s_and_b32 s4, s4, 0xff +; GFX11-NEXT: s_and_b32 s24, s24, 0xff +; GFX11-NEXT: s_and_b32 s5, s5, 0xff +; GFX11-NEXT: s_or_b32 s24, s24, s25 +; GFX11-NEXT: v_readlane_b32 s25, v37, 22 +; GFX11-NEXT: s_lshl_b32 s24, s24, 16 ; GFX11-NEXT: s_and_b32 s2, s2, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s3, 8 -; GFX11-NEXT: s_or_b32 s1, s2, s1 -; GFX11-NEXT: v_readlane_b32 s2, v19, 26 -; GFX11-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-NEXT: s_and_b32 s16, s16, 0xff -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_and_b32 s1, s21, 0xff -; GFX11-NEXT: s_lshl_b32 s2, s2, 8 -; GFX11-NEXT: v_readlane_b32 s86, v16, 30 -; GFX11-NEXT: s_or_b32 s1, s1, s2 -; GFX11-NEXT: v_readlane_b32 s2, v19, 25 -; GFX11-NEXT: s_and_b32 s1, s1, 0xffff -; GFX11-NEXT: v_readlane_b32 s31, v16, 1 -; GFX11-NEXT: v_readlane_b32 s30, v16, 0 -; GFX11-NEXT: s_and_b32 s2, s2, 0xff -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_and_b32 s3, s22, 0xff -; GFX11-NEXT: s_lshl_b32 s2, s2, 16 -; GFX11-NEXT: s_or_b32 s1, s1, s2 -; GFX11-NEXT: v_readlane_b32 s2, v19, 23 -; GFX11-NEXT: v_dual_mov_b32 v9, s0 :: v_dual_mov_b32 v10, s1 -; GFX11-NEXT: v_readlane_b32 s1, v19, 18 -; GFX11-NEXT: s_and_b32 s0, s24, 0xff -; GFX11-NEXT: s_lshl_b32 s2, s2, 8 +; GFX11-NEXT: s_or_b32 s23, s23, s24 +; GFX11-NEXT: v_readlane_b32 s24, v37, 23 +; GFX11-NEXT: s_and_b32 s25, s25, 0xff +; GFX11-NEXT: v_dual_mov_b32 v9, s22 :: v_dual_mov_b32 v10, s23 +; GFX11-NEXT: s_lshl_b32 s22, s88, 8 +; GFX11-NEXT: s_lshl_b32 s24, s24, 8 +; GFX11-NEXT: s_lshl_b32 s23, s97, 8 +; GFX11-NEXT: s_or_b32 s20, s20, s24 +; GFX11-NEXT: s_lshl_b32 s24, s62, 8 +; GFX11-NEXT: s_and_b32 s20, s20, 0xffff +; GFX11-NEXT: s_or_b32 s24, s25, s24 +; GFX11-NEXT: v_readlane_b32 s25, v37, 21 +; GFX11-NEXT: s_lshl_b32 s24, s24, 16 +; GFX11-NEXT: s_and_b32 s3, s3, 0xff +; GFX11-NEXT: s_or_b32 s20, s20, s24 +; GFX11-NEXT: s_and_b32 s0, s0, 0xff +; GFX11-NEXT: s_lshl_b32 s25, s25, 8 +; GFX11-NEXT: s_and_b32 s1, s1, 0xff +; GFX11-NEXT: s_or_b32 s21, s21, s25 +; GFX11-NEXT: v_readlane_b32 s25, v37, 20 +; GFX11-NEXT: s_and_b32 s21, s21, 0xffff +; GFX11-NEXT: v_readlane_b32 s100, v35, 4 +; GFX11-NEXT: v_readlane_b32 s99, v35, 3 +; GFX11-NEXT: v_readlane_b32 s98, v35, 2 +; GFX11-NEXT: s_and_b32 s25, s25, 0xff +; GFX11-NEXT: v_readlane_b32 s97, v35, 1 +; GFX11-NEXT: s_or_b32 s25, s25, s26 +; GFX11-NEXT: v_readlane_b32 s31, v34, 1 +; GFX11-NEXT: s_lshl_b32 s24, s25, 16 +; GFX11-NEXT: v_readlane_b32 s30, v34, 0 +; GFX11-NEXT: s_or_b32 s21, s21, s24 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: s_or_b32 s2, s3, s2 -; GFX11-NEXT: s_lshl_b32 s3, s62, 8 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_or_b32 s3, s16, s3 -; GFX11-NEXT: s_and_b32 s16, s23, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_or_b32 s16, s16, s17 -; GFX11-NEXT: v_readlane_b32 s17, v19, 20 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_and_b32 s3, s16, 0xffff -; GFX11-NEXT: s_lshl_b32 s1, s1, 8 -; GFX11-NEXT: s_and_b32 s17, s17, 0xff -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_or_b32 s17, s17, s18 -; GFX11-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-NEXT: s_lshl_b32 s16, s17, 16 -; GFX11-NEXT: s_lshl_b32 s17, s97, 8 -; GFX11-NEXT: s_or_b32 s3, s3, s16 +; GFX11-NEXT: v_dual_mov_b32 v11, s20 :: v_dual_mov_b32 v12, s21 +; GFX11-NEXT: v_readlane_b32 s20, v37, 18 +; GFX11-NEXT: v_readlane_b32 s21, v37, 17 +; GFX11-NEXT: s_lshl_b32 s20, s20, 8 +; GFX11-NEXT: s_and_b32 s21, s21, 0xff +; GFX11-NEXT: s_or_b32 s18, s18, s20 +; GFX11-NEXT: s_or_b32 s20, s21, s22 +; GFX11-NEXT: v_readlane_b32 s21, v37, 16 +; GFX11-NEXT: s_and_b32 s22, s69, 0xff +; GFX11-NEXT: s_and_b32 s18, s18, 0xffff +; GFX11-NEXT: s_lshl_b32 s20, s20, 16 +; GFX11-NEXT: v_readlane_b32 s69, v34, 21 +; GFX11-NEXT: s_lshl_b32 s21, s21, 8 +; GFX11-NEXT: s_or_b32 s18, s18, s20 +; GFX11-NEXT: s_or_b32 s19, s19, s21 +; GFX11-NEXT: s_or_b32 s21, s22, s23 +; GFX11-NEXT: s_and_b32 s19, s19, 0xffff +; GFX11-NEXT: s_lshl_b32 s21, s21, 16 +; GFX11-NEXT: s_lshl_b32 s20, s96, 8 +; GFX11-NEXT: s_or_b32 s19, s19, s21 +; GFX11-NEXT: s_and_b32 s21, s73, 0xff +; GFX11-NEXT: s_lshl_b32 s22, s76, 8 +; GFX11-NEXT: s_or_b32 s16, s16, s20 +; GFX11-NEXT: s_or_b32 s20, s21, s22 +; GFX11-NEXT: s_lshl_b32 s21, s87, 8 +; GFX11-NEXT: s_and_b32 s22, s72, 0xff +; GFX11-NEXT: s_lshl_b32 s23, s86, 8 +; GFX11-NEXT: s_or_b32 s17, s17, s21 +; GFX11-NEXT: s_or_b32 s21, s22, s23 +; GFX11-NEXT: v_dual_mov_b32 v1, s18 :: v_dual_mov_b32 v2, s19 +; GFX11-NEXT: v_readlane_b32 s18, v37, 0 +; GFX11-NEXT: s_and_b32 s16, s16, 0xffff +; GFX11-NEXT: s_lshl_b32 s20, s20, 16 +; GFX11-NEXT: s_and_b32 s17, s17, 0xffff +; GFX11-NEXT: s_lshl_b32 s21, s21, 16 +; GFX11-NEXT: s_or_b32 s16, s16, s20 +; GFX11-NEXT: s_or_b32 s17, s17, s21 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v12, s3 -; GFX11-NEXT: v_readlane_b32 s2, v19, 17 -; GFX11-NEXT: s_lshl_b32 s3, s88, 8 -; GFX11-NEXT: s_and_b32 s16, s69, 0xff -; GFX11-NEXT: s_and_b32 s18, s72, 0xff -; GFX11-NEXT: v_readlane_b32 s97, v17, 1 -; GFX11-NEXT: s_and_b32 s2, s2, 0xff -; GFX11-NEXT: v_readlane_b32 s69, v16, 21 -; GFX11-NEXT: s_or_b32 s1, s2, s3 -; GFX11-NEXT: v_readlane_b32 s3, v19, 16 -; GFX11-NEXT: s_and_b32 s2, s25, 0xff -; GFX11-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_lshl_b32 s3, s3, 8 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s16, s17 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_and_b32 s16, s73, 0xff -; GFX11-NEXT: s_or_b32 s1, s2, s3 -; GFX11-NEXT: s_and_b32 s2, s26, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s96, 8 -; GFX11-NEXT: s_lshl_b32 s17, s76, 8 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s16, s17 -; GFX11-NEXT: s_and_b32 s16, s27, 0xff -; GFX11-NEXT: s_lshl_b32 s17, s87, 8 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_or_b32 s16, s16, s17 +; GFX11-NEXT: v_dual_mov_b32 v3, s16 :: v_dual_mov_b32 v4, s17 +; GFX11-NEXT: s_lshl_b32 s16, s85, 8 +; GFX11-NEXT: s_and_b32 s17, s84, 0xff +; GFX11-NEXT: s_lshl_b32 s18, s18, 8 +; GFX11-NEXT: v_readlane_b32 s19, v37, 1 +; GFX11-NEXT: s_or_b32 s14, s14, s16 +; GFX11-NEXT: s_or_b32 s16, s17, s18 +; GFX11-NEXT: s_lshl_b32 s17, s83, 8 +; GFX11-NEXT: s_and_b32 s18, s82, 0xff +; GFX11-NEXT: s_lshl_b32 s19, s81, 8 +; GFX11-NEXT: s_or_b32 s15, s15, s17 ; GFX11-NEXT: s_or_b32 s17, s18, s19 -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_and_b32 s16, s16, 0xffff +; GFX11-NEXT: v_readlane_b32 s18, v37, 2 +; GFX11-NEXT: s_and_b32 s14, s14, 0xffff +; GFX11-NEXT: s_lshl_b32 s16, s16, 16 +; GFX11-NEXT: s_and_b32 s15, s15, 0xffff ; GFX11-NEXT: s_lshl_b32 s17, s17, 16 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s16, s17 -; GFX11-NEXT: v_readlane_b32 s16, v19, 0 -; GFX11-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1 -; GFX11-NEXT: v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3 -; GFX11-NEXT: s_and_b32 s0, s28, 0xff -; GFX11-NEXT: s_lshl_b32 s1, s85, 8 -; GFX11-NEXT: s_and_b32 s2, s84, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s16, 8 -; GFX11-NEXT: v_readlane_b32 s17, v19, 1 -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_or_b32 s1, s2, s3 -; GFX11-NEXT: s_and_b32 s2, s29, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s83, 8 -; GFX11-NEXT: s_and_b32 s16, s82, 0xff -; GFX11-NEXT: s_lshl_b32 s17, s81, 8 -; GFX11-NEXT: v_readlane_b32 s18, v19, 2 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s16, s17 -; GFX11-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_or_b32 s1, s2, s3 -; GFX11-NEXT: s_and_b32 s2, s40, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s61, 8 -; GFX11-NEXT: s_and_b32 s16, s80, 0xff -; GFX11-NEXT: s_lshl_b32 s17, s18, 8 -; GFX11-NEXT: v_readlane_b32 s19, v19, 3 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s16, s17 -; GFX11-NEXT: s_and_b32 s16, s41, 0xff +; GFX11-NEXT: s_or_b32 s14, s14, s16 +; GFX11-NEXT: s_or_b32 s15, s15, s17 +; GFX11-NEXT: s_lshl_b32 s16, s61, 8 +; GFX11-NEXT: s_and_b32 s17, s80, 0xff +; GFX11-NEXT: s_lshl_b32 s18, s18, 8 +; GFX11-NEXT: v_readlane_b32 s19, v37, 3 +; GFX11-NEXT: s_or_b32 s12, s12, s16 +; GFX11-NEXT: s_or_b32 s16, s17, s18 ; GFX11-NEXT: s_lshl_b32 s17, s60, 8 ; GFX11-NEXT: s_and_b32 s18, s71, 0xff ; GFX11-NEXT: s_lshl_b32 s19, s70, 8 -; GFX11-NEXT: s_or_b32 s16, s16, s17 +; GFX11-NEXT: s_or_b32 s13, s13, s17 ; GFX11-NEXT: s_or_b32 s17, s18, s19 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_and_b32 s16, s16, 0xffff +; GFX11-NEXT: v_dual_mov_b32 v5, s14 :: v_dual_mov_b32 v6, s15 +; GFX11-NEXT: v_readlane_b32 s14, v37, 4 +; GFX11-NEXT: s_and_b32 s12, s12, 0xffff +; GFX11-NEXT: s_lshl_b32 s16, s16, 16 +; GFX11-NEXT: s_and_b32 s13, s13, 0xffff ; GFX11-NEXT: s_lshl_b32 s17, s17, 16 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s16, s17 -; GFX11-NEXT: v_readlane_b32 s16, v19, 4 -; GFX11-NEXT: v_dual_mov_b32 v5, s0 :: v_dual_mov_b32 v6, s1 -; GFX11-NEXT: v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v8, s3 -; GFX11-NEXT: s_and_b32 s0, s14, 0xff -; GFX11-NEXT: s_lshl_b32 s1, s58, 8 -; GFX11-NEXT: s_and_b32 s2, s59, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s16, 8 -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_or_b32 s1, s2, s3 -; GFX11-NEXT: s_and_b32 s2, s15, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s68, 8 +; GFX11-NEXT: s_or_b32 s12, s12, s16 +; GFX11-NEXT: s_or_b32 s13, s13, s17 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v7, s12 :: v_dual_mov_b32 v8, s13 +; GFX11-NEXT: s_lshl_b32 s12, s58, 8 +; GFX11-NEXT: s_and_b32 s13, s59, 0xff +; GFX11-NEXT: s_lshl_b32 s14, s14, 8 +; GFX11-NEXT: v_readlane_b32 s15, v37, 5 +; GFX11-NEXT: s_or_b32 s10, s10, s12 +; GFX11-NEXT: s_or_b32 s12, s13, s14 +; GFX11-NEXT: s_lshl_b32 s13, s68, 8 ; GFX11-NEXT: s_and_b32 s14, s67, 0xff ; GFX11-NEXT: s_lshl_b32 s15, s66, 8 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s14, s15 -; GFX11-NEXT: v_readlane_b32 s14, v19, 6 -; GFX11-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_or_b32 s1, s2, s3 -; GFX11-NEXT: s_and_b32 s2, s12, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s65, 8 -; GFX11-NEXT: s_and_b32 s12, s64, 0xff +; GFX11-NEXT: s_or_b32 s11, s11, s13 +; GFX11-NEXT: s_or_b32 s13, s14, s15 +; GFX11-NEXT: v_readlane_b32 s14, v37, 6 +; GFX11-NEXT: s_and_b32 s10, s10, 0xffff +; GFX11-NEXT: s_lshl_b32 s12, s12, 16 +; GFX11-NEXT: s_and_b32 s11, s11, 0xffff +; GFX11-NEXT: s_lshl_b32 s13, s13, 16 +; GFX11-NEXT: s_or_b32 s10, s10, s12 +; GFX11-NEXT: s_or_b32 s11, s11, s13 +; GFX11-NEXT: s_lshl_b32 s12, s65, 8 +; GFX11-NEXT: s_and_b32 s13, s64, 0xff ; GFX11-NEXT: s_lshl_b32 s14, s14, 8 -; GFX11-NEXT: v_readlane_b32 s15, v19, 7 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s12, s14 -; GFX11-NEXT: s_and_b32 s12, s13, 0xff +; GFX11-NEXT: v_readlane_b32 s15, v37, 7 +; GFX11-NEXT: s_or_b32 s8, s8, s12 +; GFX11-NEXT: s_or_b32 s12, s13, s14 ; GFX11-NEXT: s_lshl_b32 s13, s55, 8 ; GFX11-NEXT: s_and_b32 s14, s54, 0xff ; GFX11-NEXT: s_lshl_b32 s15, s53, 8 -; GFX11-NEXT: s_or_b32 s12, s12, s13 +; GFX11-NEXT: s_or_b32 s9, s9, s13 ; GFX11-NEXT: s_or_b32 s13, s14, s15 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_and_b32 s12, s12, 0xffff -; GFX11-NEXT: s_lshl_b32 s13, s13, 16 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s12, s13 -; GFX11-NEXT: v_readlane_b32 s12, v19, 8 ; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: scratch_store_b128 v0, v[9:12], off offset:32 ; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:48 -; GFX11-NEXT: v_dual_mov_b32 v9, s0 :: v_dual_mov_b32 v10, s1 -; GFX11-NEXT: v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v12, s3 -; GFX11-NEXT: s_and_b32 s0, s10, 0xff -; GFX11-NEXT: s_lshl_b32 s1, s52, 8 -; GFX11-NEXT: s_and_b32 s2, s51, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s12, 8 -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_or_b32 s1, s2, s3 -; GFX11-NEXT: s_and_b32 s2, s11, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s50, 8 +; GFX11-NEXT: v_dual_mov_b32 v9, s10 :: v_dual_mov_b32 v10, s11 +; GFX11-NEXT: v_readlane_b32 s10, v37, 8 +; GFX11-NEXT: s_and_b32 s8, s8, 0xffff +; GFX11-NEXT: s_lshl_b32 s12, s12, 16 +; GFX11-NEXT: s_and_b32 s9, s9, 0xffff +; GFX11-NEXT: s_lshl_b32 s13, s13, 16 +; GFX11-NEXT: s_or_b32 s8, s8, s12 +; GFX11-NEXT: s_or_b32 s9, s9, s13 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v11, s8 :: v_dual_mov_b32 v12, s9 +; GFX11-NEXT: s_lshl_b32 s8, s52, 8 +; GFX11-NEXT: s_and_b32 s9, s51, 0xff +; GFX11-NEXT: s_lshl_b32 s10, s10, 8 +; GFX11-NEXT: v_readlane_b32 s11, v37, 9 +; GFX11-NEXT: s_or_b32 s6, s6, s8 +; GFX11-NEXT: s_or_b32 s8, s9, s10 +; GFX11-NEXT: s_lshl_b32 s9, s50, 8 ; GFX11-NEXT: s_and_b32 s10, s49, 0xff ; GFX11-NEXT: s_lshl_b32 s11, s48, 8 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s10, s11 -; GFX11-NEXT: v_readlane_b32 s10, v19, 10 -; GFX11-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_or_b32 s1, s2, s3 -; GFX11-NEXT: s_and_b32 s2, s8, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s39, 8 -; GFX11-NEXT: s_and_b32 s8, s38, 0xff +; GFX11-NEXT: s_or_b32 s7, s7, s9 +; GFX11-NEXT: s_or_b32 s9, s10, s11 +; GFX11-NEXT: v_readlane_b32 s10, v37, 10 +; GFX11-NEXT: s_and_b32 s6, s6, 0xffff +; GFX11-NEXT: s_lshl_b32 s8, s8, 16 +; GFX11-NEXT: s_and_b32 s7, s7, 0xffff +; GFX11-NEXT: s_lshl_b32 s9, s9, 16 +; GFX11-NEXT: s_or_b32 s6, s6, s8 +; GFX11-NEXT: s_or_b32 s7, s7, s9 +; GFX11-NEXT: s_lshl_b32 s8, s39, 8 +; GFX11-NEXT: s_and_b32 s9, s38, 0xff ; GFX11-NEXT: s_lshl_b32 s10, s10, 8 -; GFX11-NEXT: v_readlane_b32 s11, v19, 11 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s8, s10 -; GFX11-NEXT: s_and_b32 s8, s9, 0xff +; GFX11-NEXT: v_readlane_b32 s11, v37, 11 +; GFX11-NEXT: s_or_b32 s4, s4, s8 +; GFX11-NEXT: s_or_b32 s8, s9, s10 ; GFX11-NEXT: s_lshl_b32 s9, s37, 8 ; GFX11-NEXT: s_and_b32 s10, s36, 0xff ; GFX11-NEXT: s_lshl_b32 s11, s35, 8 -; GFX11-NEXT: s_or_b32 s8, s8, s9 +; GFX11-NEXT: s_or_b32 s5, s5, s9 ; GFX11-NEXT: s_or_b32 s9, s10, s11 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_and_b32 s8, s8, 0xffff +; GFX11-NEXT: v_dual_mov_b32 v1, s6 :: v_dual_mov_b32 v2, s7 +; GFX11-NEXT: v_readlane_b32 s6, v37, 12 +; GFX11-NEXT: s_and_b32 s4, s4, 0xffff +; GFX11-NEXT: s_lshl_b32 s8, s8, 16 +; GFX11-NEXT: s_and_b32 s5, s5, 0xffff ; GFX11-NEXT: s_lshl_b32 s9, s9, 16 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s8, s9 -; GFX11-NEXT: v_readlane_b32 s8, v19, 12 -; GFX11-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1 -; GFX11-NEXT: v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3 -; GFX11-NEXT: s_and_b32 s0, s6, 0xff -; GFX11-NEXT: s_lshl_b32 s1, s56, 8 -; GFX11-NEXT: s_and_b32 s2, s57, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s8, 8 -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_or_b32 s1, s2, s3 -; GFX11-NEXT: s_and_b32 s2, s7, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s34, 8 +; GFX11-NEXT: s_or_b32 s4, s4, s8 +; GFX11-NEXT: s_or_b32 s5, s5, s9 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5 +; GFX11-NEXT: s_lshl_b32 s4, s56, 8 +; GFX11-NEXT: s_and_b32 s5, s57, 0xff +; GFX11-NEXT: s_lshl_b32 s6, s6, 8 +; GFX11-NEXT: v_readlane_b32 s7, v37, 13 +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: s_or_b32 s4, s5, s6 +; GFX11-NEXT: s_lshl_b32 s5, s34, 8 ; GFX11-NEXT: s_and_b32 s6, vcc_hi, 0xff ; GFX11-NEXT: s_lshl_b32 s7, s46, 8 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s6, s7 -; GFX11-NEXT: v_readlane_b32 s6, v19, 14 -; GFX11-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-NEXT: s_lshl_b32 s1, s1, 16 +; GFX11-NEXT: s_or_b32 s3, s3, s5 +; GFX11-NEXT: s_or_b32 s5, s6, s7 +; GFX11-NEXT: v_readlane_b32 s6, v37, 14 ; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_or_b32 s1, s2, s3 -; GFX11-NEXT: s_and_b32 s2, s4, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s47, 8 -; GFX11-NEXT: s_and_b32 s4, s104, 0xff +; GFX11-NEXT: s_lshl_b32 s4, s4, 16 +; GFX11-NEXT: s_and_b32 s3, s3, 0xffff +; GFX11-NEXT: s_lshl_b32 s5, s5, 16 +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: s_or_b32 s3, s3, s5 +; GFX11-NEXT: s_lshl_b32 s4, s47, 8 +; GFX11-NEXT: s_and_b32 s5, s104, 0xff ; GFX11-NEXT: s_lshl_b32 s6, s6, 8 -; GFX11-NEXT: v_readlane_b32 s7, v19, 15 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s4, s6 -; GFX11-NEXT: s_and_b32 s4, s5, 0xff +; GFX11-NEXT: v_readlane_b32 s7, v37, 15 +; GFX11-NEXT: s_or_b32 s0, s0, s4 +; GFX11-NEXT: s_or_b32 s4, s5, s6 ; GFX11-NEXT: s_lshl_b32 s5, s103, 8 ; GFX11-NEXT: s_and_b32 s6, s102, 0xff ; GFX11-NEXT: s_lshl_b32 s7, s101, 8 -; GFX11-NEXT: s_or_b32 s4, s4, s5 +; GFX11-NEXT: s_or_b32 s1, s1, s5 ; GFX11-NEXT: s_or_b32 s5, s6, s7 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_and_b32 s4, s4, 0xffff +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_lshl_b32 s4, s4, 16 +; GFX11-NEXT: s_and_b32 s1, s1, 0xffff ; GFX11-NEXT: s_lshl_b32 s5, s5, 16 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s4, s5 +; GFX11-NEXT: s_or_b32 s0, s0, s4 +; GFX11-NEXT: s_or_b32 s1, s1, s5 ; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:64 -; GFX11-NEXT: v_dual_mov_b32 v5, s0 :: v_dual_mov_b32 v6, s1 -; GFX11-NEXT: v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v8, s3 -; GFX11-NEXT: v_readlane_b32 s17, v19, 5 -; GFX11-NEXT: v_readlane_b32 s13, v19, 9 -; GFX11-NEXT: v_readlane_b32 s9, v19, 13 +; GFX11-NEXT: v_dual_mov_b32 v5, s2 :: v_dual_mov_b32 v6, s3 +; GFX11-NEXT: v_dual_mov_b32 v7, s0 :: v_dual_mov_b32 v8, s1 ; GFX11-NEXT: s_clause 0x2 ; GFX11-NEXT: scratch_store_b128 v0, v[9:12], off offset:80 ; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:96 ; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:112 -; GFX11-NEXT: v_readlane_b32 s104, v17, 8 -; GFX11-NEXT: v_readlane_b32 s103, v17, 7 -; GFX11-NEXT: v_readlane_b32 s102, v17, 6 -; GFX11-NEXT: v_readlane_b32 s101, v17, 5 -; GFX11-NEXT: v_readlane_b32 s96, v17, 0 -; GFX11-NEXT: v_readlane_b32 s87, v16, 31 -; GFX11-NEXT: v_readlane_b32 s85, v16, 29 -; GFX11-NEXT: v_readlane_b32 s84, v16, 28 -; GFX11-NEXT: v_readlane_b32 s83, v16, 27 -; GFX11-NEXT: v_readlane_b32 s82, v16, 26 -; GFX11-NEXT: v_readlane_b32 s81, v16, 25 -; GFX11-NEXT: v_readlane_b32 s80, v16, 24 -; GFX11-NEXT: v_readlane_b32 s71, v16, 23 -; GFX11-NEXT: v_readlane_b32 s70, v16, 22 -; GFX11-NEXT: v_readlane_b32 s68, v16, 20 -; GFX11-NEXT: v_readlane_b32 s67, v16, 19 -; GFX11-NEXT: v_readlane_b32 s66, v16, 18 -; GFX11-NEXT: v_readlane_b32 s65, v16, 17 -; GFX11-NEXT: v_readlane_b32 s64, v16, 16 -; GFX11-NEXT: v_readlane_b32 s55, v16, 15 -; GFX11-NEXT: v_readlane_b32 s54, v16, 14 -; GFX11-NEXT: v_readlane_b32 s53, v16, 13 -; GFX11-NEXT: v_readlane_b32 s52, v16, 12 -; GFX11-NEXT: v_readlane_b32 s51, v16, 11 -; GFX11-NEXT: v_readlane_b32 s50, v16, 10 -; GFX11-NEXT: v_readlane_b32 s49, v16, 9 -; GFX11-NEXT: v_readlane_b32 s48, v16, 8 -; GFX11-NEXT: v_readlane_b32 s39, v16, 7 -; GFX11-NEXT: v_readlane_b32 s38, v16, 6 -; GFX11-NEXT: v_readlane_b32 s37, v16, 5 -; GFX11-NEXT: v_readlane_b32 s36, v16, 4 -; GFX11-NEXT: v_readlane_b32 s35, v16, 3 -; GFX11-NEXT: v_readlane_b32 s34, v16, 2 +; GFX11-NEXT: v_readlane_b32 s104, v35, 8 +; GFX11-NEXT: v_readlane_b32 s103, v35, 7 +; GFX11-NEXT: v_readlane_b32 s102, v35, 6 +; GFX11-NEXT: v_readlane_b32 s101, v35, 5 +; GFX11-NEXT: v_readlane_b32 s96, v35, 0 +; GFX11-NEXT: v_readlane_b32 s87, v34, 31 +; GFX11-NEXT: v_readlane_b32 s86, v34, 30 +; GFX11-NEXT: v_readlane_b32 s85, v34, 29 +; GFX11-NEXT: v_readlane_b32 s84, v34, 28 +; GFX11-NEXT: v_readlane_b32 s83, v34, 27 +; GFX11-NEXT: v_readlane_b32 s82, v34, 26 +; GFX11-NEXT: v_readlane_b32 s81, v34, 25 +; GFX11-NEXT: v_readlane_b32 s80, v34, 24 +; GFX11-NEXT: v_readlane_b32 s71, v34, 23 +; GFX11-NEXT: v_readlane_b32 s70, v34, 22 +; GFX11-NEXT: v_readlane_b32 s68, v34, 20 +; GFX11-NEXT: v_readlane_b32 s67, v34, 19 +; GFX11-NEXT: v_readlane_b32 s66, v34, 18 +; GFX11-NEXT: v_readlane_b32 s65, v34, 17 +; GFX11-NEXT: v_readlane_b32 s64, v34, 16 +; GFX11-NEXT: v_readlane_b32 s55, v34, 15 +; GFX11-NEXT: v_readlane_b32 s54, v34, 14 +; GFX11-NEXT: v_readlane_b32 s53, v34, 13 +; GFX11-NEXT: v_readlane_b32 s52, v34, 12 +; GFX11-NEXT: v_readlane_b32 s51, v34, 11 +; GFX11-NEXT: v_readlane_b32 s50, v34, 10 +; GFX11-NEXT: v_readlane_b32 s49, v34, 9 +; GFX11-NEXT: v_readlane_b32 s48, v34, 8 +; GFX11-NEXT: v_readlane_b32 s39, v34, 7 +; GFX11-NEXT: v_readlane_b32 s38, v34, 6 +; GFX11-NEXT: v_readlane_b32 s37, v34, 5 +; GFX11-NEXT: v_readlane_b32 s36, v34, 4 +; GFX11-NEXT: v_readlane_b32 s35, v34, 3 +; GFX11-NEXT: v_readlane_b32 s34, v34, 2 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: s_clause 0x3 ; 16-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v16, off, s32 -; GFX11-NEXT: scratch_load_b32 v17, off, s32 offset:4 -; GFX11-NEXT: scratch_load_b32 v18, off, s32 offset:8 -; GFX11-NEXT: scratch_load_b32 v19, off, s32 offset:12 +; GFX11-NEXT: scratch_load_b32 v34, off, s32 +; GFX11-NEXT: scratch_load_b32 v35, off, s32 offset:4 +; GFX11-NEXT: scratch_load_b32 v36, off, s32 offset:8 +; GFX11-NEXT: scratch_load_b32 v37, off, s32 offset:12 ; GFX11-NEXT: s_mov_b32 exec_lo, s0 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] @@ -23464,47 +23576,75 @@ define inreg <64 x bfloat> @bitcast_v32i32_to_v64bf16_scalar(<32 x i32> inreg %a ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_writelane_b32 v20, s30, 0 -; SI-NEXT: v_writelane_b32 v20, s31, 1 -; SI-NEXT: v_writelane_b32 v20, s34, 2 -; SI-NEXT: v_writelane_b32 v20, s35, 3 -; SI-NEXT: v_writelane_b32 v20, s36, 4 -; SI-NEXT: v_writelane_b32 v20, s37, 5 -; SI-NEXT: v_writelane_b32 v20, s38, 6 -; SI-NEXT: v_writelane_b32 v20, s39, 7 -; SI-NEXT: v_writelane_b32 v20, s48, 8 -; SI-NEXT: v_writelane_b32 v20, s49, 9 -; SI-NEXT: v_writelane_b32 v20, s50, 10 -; SI-NEXT: v_writelane_b32 v20, s51, 11 -; SI-NEXT: v_writelane_b32 v20, s52, 12 -; SI-NEXT: v_writelane_b32 v20, s53, 13 -; SI-NEXT: v_writelane_b32 v20, s54, 14 -; SI-NEXT: v_writelane_b32 v20, s55, 15 -; SI-NEXT: v_writelane_b32 v20, s64, 16 -; SI-NEXT: v_writelane_b32 v20, s65, 17 -; SI-NEXT: v_writelane_b32 v20, s66, 18 -; SI-NEXT: v_writelane_b32 v20, s67, 19 -; SI-NEXT: v_writelane_b32 v20, s68, 20 -; SI-NEXT: v_writelane_b32 v20, s69, 21 -; SI-NEXT: v_writelane_b32 v20, s70, 22 -; SI-NEXT: v_writelane_b32 v20, s71, 23 -; SI-NEXT: v_writelane_b32 v20, s80, 24 -; SI-NEXT: v_writelane_b32 v20, s81, 25 -; SI-NEXT: v_writelane_b32 v20, s82, 26 -; SI-NEXT: v_writelane_b32 v20, s83, 27 -; SI-NEXT: v_writelane_b32 v20, s84, 28 -; SI-NEXT: v_writelane_b32 v20, s85, 29 -; SI-NEXT: v_writelane_b32 v20, s86, 30 -; SI-NEXT: v_writelane_b32 v20, s87, 31 -; SI-NEXT: v_writelane_b32 v20, s96, 32 -; SI-NEXT: v_writelane_b32 v20, s97, 33 -; SI-NEXT: v_writelane_b32 v20, s98, 34 +; SI-NEXT: v_writelane_b32 v21, s30, 0 +; SI-NEXT: v_writelane_b32 v21, s31, 1 +; SI-NEXT: v_writelane_b32 v21, s34, 2 +; SI-NEXT: v_writelane_b32 v21, s35, 3 +; SI-NEXT: v_writelane_b32 v21, s36, 4 +; SI-NEXT: v_writelane_b32 v21, s37, 5 +; SI-NEXT: v_writelane_b32 v21, s38, 6 +; SI-NEXT: v_writelane_b32 v21, s39, 7 +; SI-NEXT: v_writelane_b32 v21, s48, 8 +; SI-NEXT: v_writelane_b32 v21, s49, 9 +; SI-NEXT: v_writelane_b32 v21, s50, 10 +; SI-NEXT: v_writelane_b32 v21, s51, 11 +; SI-NEXT: v_writelane_b32 v21, s52, 12 +; SI-NEXT: v_writelane_b32 v21, s53, 13 +; SI-NEXT: v_writelane_b32 v21, s54, 14 +; SI-NEXT: v_writelane_b32 v21, s55, 15 +; SI-NEXT: v_writelane_b32 v21, s64, 16 +; SI-NEXT: v_writelane_b32 v21, s65, 17 +; SI-NEXT: v_writelane_b32 v21, s66, 18 +; SI-NEXT: v_writelane_b32 v21, s67, 19 +; SI-NEXT: v_writelane_b32 v21, s68, 20 +; SI-NEXT: v_writelane_b32 v21, s69, 21 +; SI-NEXT: v_mov_b32_e32 v20, s16 +; SI-NEXT: v_writelane_b32 v21, s70, 22 +; SI-NEXT: v_readfirstlane_b32 s48, v20 +; SI-NEXT: v_mov_b32_e32 v20, s17 +; SI-NEXT: v_writelane_b32 v21, s71, 23 +; SI-NEXT: v_readfirstlane_b32 s49, v20 +; SI-NEXT: v_mov_b32_e32 v20, s18 +; SI-NEXT: v_writelane_b32 v21, s80, 24 +; SI-NEXT: v_readfirstlane_b32 s50, v20 +; SI-NEXT: v_mov_b32_e32 v20, s19 +; SI-NEXT: v_writelane_b32 v21, s81, 25 +; SI-NEXT: v_readfirstlane_b32 s51, v20 +; SI-NEXT: v_mov_b32_e32 v20, s20 +; SI-NEXT: v_writelane_b32 v21, s82, 26 +; SI-NEXT: v_readfirstlane_b32 s52, v20 +; SI-NEXT: v_mov_b32_e32 v20, s21 +; SI-NEXT: v_writelane_b32 v21, s83, 27 +; SI-NEXT: v_readfirstlane_b32 s53, v20 +; SI-NEXT: v_mov_b32_e32 v20, s22 +; SI-NEXT: v_writelane_b32 v21, s84, 28 +; SI-NEXT: v_readfirstlane_b32 s54, v20 +; SI-NEXT: v_mov_b32_e32 v20, s23 +; SI-NEXT: v_writelane_b32 v21, s85, 29 +; SI-NEXT: v_readfirstlane_b32 s55, v20 +; SI-NEXT: v_mov_b32_e32 v20, s24 +; SI-NEXT: v_writelane_b32 v21, s86, 30 +; SI-NEXT: v_readfirstlane_b32 s64, v20 +; SI-NEXT: v_mov_b32_e32 v20, s25 +; SI-NEXT: v_writelane_b32 v21, s87, 31 +; SI-NEXT: v_readfirstlane_b32 s65, v20 +; SI-NEXT: v_mov_b32_e32 v20, s26 +; SI-NEXT: v_writelane_b32 v21, s96, 32 +; SI-NEXT: v_readfirstlane_b32 s66, v20 +; SI-NEXT: v_mov_b32_e32 v20, s27 +; SI-NEXT: v_writelane_b32 v21, s97, 33 +; SI-NEXT: v_readfirstlane_b32 s67, v20 +; SI-NEXT: v_mov_b32_e32 v20, s28 +; SI-NEXT: v_writelane_b32 v21, s98, 34 +; SI-NEXT: v_readfirstlane_b32 s68, v20 +; SI-NEXT: v_mov_b32_e32 v20, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_writelane_b32 v20, s99, 35 +; SI-NEXT: v_writelane_b32 v21, s99, 35 +; SI-NEXT: v_readfirstlane_b32 s69, v20 ; SI-NEXT: v_readfirstlane_b32 s70, v1 ; SI-NEXT: v_readfirstlane_b32 s71, v2 ; SI-NEXT: v_readfirstlane_b32 s80, v3 @@ -23524,97 +23664,83 @@ define inreg <64 x bfloat> @bitcast_v32i32_to_v64bf16_scalar(<32 x i32> inreg %a ; SI-NEXT: v_readfirstlane_b32 s8, v17 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s9, v18 -; SI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane +; SI-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane ; SI-NEXT: s_cbranch_scc0 .LBB17_2 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: s_and_b32 s4, s17, 0xffff0000 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v21, s4, 1 -; SI-NEXT: s_lshl_b32 s4, s17, 16 -; SI-NEXT: v_writelane_b32 v21, s4, 0 -; SI-NEXT: s_and_b32 s4, s16, 0xffff0000 -; SI-NEXT: v_writelane_b32 v21, s4, 2 -; SI-NEXT: s_lshl_b32 s4, s16, 16 +; SI-NEXT: s_and_b32 s4, s49, 0xffff0000 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_writelane_b32 v22, s4, 1 +; SI-NEXT: s_lshl_b32 s4, s49, 16 +; SI-NEXT: v_writelane_b32 v22, s4, 0 +; SI-NEXT: s_and_b32 s4, s48, 0xffff0000 +; SI-NEXT: v_writelane_b32 v22, s4, 2 +; SI-NEXT: s_lshl_b32 s4, s48, 16 ; SI-NEXT: s_and_b32 s11, s9, 0xffff0000 ; SI-NEXT: s_lshl_b32 s10, s9, 16 ; SI-NEXT: s_and_b32 s13, s8, 0xffff0000 ; SI-NEXT: s_lshl_b32 s12, s8, 16 ; SI-NEXT: s_and_b32 s15, s7, 0xffff0000 ; SI-NEXT: s_lshl_b32 s14, s7, 16 -; SI-NEXT: s_and_b32 s41, s6, 0xffff0000 -; SI-NEXT: s_lshl_b32 s40, s6, 16 -; SI-NEXT: s_and_b32 s43, s99, 0xffff0000 -; SI-NEXT: s_lshl_b32 s42, s99, 16 -; SI-NEXT: s_and_b32 s45, s98, 0xffff0000 -; SI-NEXT: s_lshl_b32 s44, s98, 16 -; SI-NEXT: s_and_b32 s47, s97, 0xffff0000 -; SI-NEXT: s_lshl_b32 s46, s97, 16 -; SI-NEXT: s_and_b32 s57, s96, 0xffff0000 -; SI-NEXT: s_lshl_b32 s56, s96, 16 -; SI-NEXT: s_and_b32 s59, s87, 0xffff0000 -; SI-NEXT: s_lshl_b32 s58, s87, 16 -; SI-NEXT: s_and_b32 s61, s86, 0xffff0000 -; SI-NEXT: s_lshl_b32 s60, s86, 16 -; SI-NEXT: s_and_b32 s63, s85, 0xffff0000 -; SI-NEXT: s_lshl_b32 s62, s85, 16 -; SI-NEXT: s_and_b32 s73, s84, 0xffff0000 -; SI-NEXT: s_lshl_b32 s72, s84, 16 -; SI-NEXT: s_and_b32 s75, s83, 0xffff0000 -; SI-NEXT: s_lshl_b32 s74, s83, 16 -; SI-NEXT: s_and_b32 s77, s82, 0xffff0000 -; SI-NEXT: s_lshl_b32 s76, s82, 16 -; SI-NEXT: s_and_b32 s79, s81, 0xffff0000 -; SI-NEXT: s_lshl_b32 s78, s81, 16 -; SI-NEXT: s_and_b32 s89, s80, 0xffff0000 -; SI-NEXT: s_lshl_b32 s88, s80, 16 -; SI-NEXT: s_and_b32 s91, s71, 0xffff0000 -; SI-NEXT: s_lshl_b32 s90, s71, 16 -; SI-NEXT: s_and_b32 s93, s70, 0xffff0000 -; SI-NEXT: s_lshl_b32 s92, s70, 16 -; SI-NEXT: s_and_b32 s95, s29, 0xffff0000 -; SI-NEXT: s_lshl_b32 s94, s29, 16 -; SI-NEXT: s_and_b32 s31, s28, 0xffff0000 -; SI-NEXT: s_lshl_b32 s30, s28, 16 -; SI-NEXT: s_and_b32 s35, s27, 0xffff0000 -; SI-NEXT: s_lshl_b32 s34, s27, 16 -; SI-NEXT: s_and_b32 s37, s26, 0xffff0000 -; SI-NEXT: s_lshl_b32 s36, s26, 16 -; SI-NEXT: s_and_b32 s39, s25, 0xffff0000 -; SI-NEXT: s_lshl_b32 s38, s25, 16 -; SI-NEXT: s_and_b32 s49, s24, 0xffff0000 -; SI-NEXT: s_lshl_b32 s48, s24, 16 -; SI-NEXT: s_and_b32 s51, s23, 0xffff0000 -; SI-NEXT: s_lshl_b32 s50, s23, 16 -; SI-NEXT: s_and_b32 s53, s22, 0xffff0000 -; SI-NEXT: s_lshl_b32 s52, s22, 16 -; SI-NEXT: s_and_b32 s55, s21, 0xffff0000 -; SI-NEXT: s_lshl_b32 s54, s21, 16 -; SI-NEXT: s_and_b32 s65, s20, 0xffff0000 -; SI-NEXT: s_lshl_b32 s64, s20, 16 -; SI-NEXT: s_and_b32 s67, s19, 0xffff0000 -; SI-NEXT: s_lshl_b32 s66, s19, 16 -; SI-NEXT: s_and_b32 s69, s18, 0xffff0000 -; SI-NEXT: s_lshl_b32 s68, s18, 16 -; SI-NEXT: v_writelane_b32 v21, s4, 3 +; SI-NEXT: s_and_b32 s17, s6, 0xffff0000 +; SI-NEXT: s_lshl_b32 s16, s6, 16 +; SI-NEXT: s_and_b32 s19, s99, 0xffff0000 +; SI-NEXT: s_lshl_b32 s18, s99, 16 +; SI-NEXT: s_and_b32 s21, s98, 0xffff0000 +; SI-NEXT: s_lshl_b32 s20, s98, 16 +; SI-NEXT: s_and_b32 s23, s97, 0xffff0000 +; SI-NEXT: s_lshl_b32 s22, s97, 16 +; SI-NEXT: s_and_b32 s25, s96, 0xffff0000 +; SI-NEXT: s_lshl_b32 s24, s96, 16 +; SI-NEXT: s_and_b32 s27, s87, 0xffff0000 +; SI-NEXT: s_lshl_b32 s26, s87, 16 +; SI-NEXT: s_and_b32 s29, s86, 0xffff0000 +; SI-NEXT: s_lshl_b32 s28, s86, 16 +; SI-NEXT: s_and_b32 s41, s85, 0xffff0000 +; SI-NEXT: s_lshl_b32 s40, s85, 16 +; SI-NEXT: s_and_b32 s43, s84, 0xffff0000 +; SI-NEXT: s_lshl_b32 s42, s84, 16 +; SI-NEXT: s_and_b32 s45, s83, 0xffff0000 +; SI-NEXT: s_lshl_b32 s44, s83, 16 +; SI-NEXT: s_and_b32 s47, s82, 0xffff0000 +; SI-NEXT: s_lshl_b32 s46, s82, 16 +; SI-NEXT: s_and_b32 s57, s81, 0xffff0000 +; SI-NEXT: s_lshl_b32 s56, s81, 16 +; SI-NEXT: s_and_b32 s59, s80, 0xffff0000 +; SI-NEXT: s_lshl_b32 s58, s80, 16 +; SI-NEXT: s_and_b32 s61, s71, 0xffff0000 +; SI-NEXT: s_lshl_b32 s60, s71, 16 +; SI-NEXT: s_and_b32 s63, s70, 0xffff0000 +; SI-NEXT: s_lshl_b32 s62, s70, 16 +; SI-NEXT: s_and_b32 s73, s69, 0xffff0000 +; SI-NEXT: s_lshl_b32 s72, s69, 16 +; SI-NEXT: s_and_b32 s75, s68, 0xffff0000 +; SI-NEXT: s_lshl_b32 s74, s68, 16 +; SI-NEXT: s_and_b32 s77, s67, 0xffff0000 +; SI-NEXT: s_lshl_b32 s76, s67, 16 +; SI-NEXT: s_and_b32 s79, s66, 0xffff0000 +; SI-NEXT: s_lshl_b32 s78, s66, 16 +; SI-NEXT: s_and_b32 s89, s65, 0xffff0000 +; SI-NEXT: s_lshl_b32 s88, s65, 16 +; SI-NEXT: s_and_b32 s91, s64, 0xffff0000 +; SI-NEXT: s_lshl_b32 s90, s64, 16 +; SI-NEXT: s_and_b32 s93, s55, 0xffff0000 +; SI-NEXT: s_lshl_b32 s92, s55, 16 +; SI-NEXT: s_and_b32 s95, s54, 0xffff0000 +; SI-NEXT: s_lshl_b32 s94, s54, 16 +; SI-NEXT: s_and_b32 s31, s53, 0xffff0000 +; SI-NEXT: s_lshl_b32 s30, s53, 16 +; SI-NEXT: s_and_b32 s35, s52, 0xffff0000 +; SI-NEXT: s_lshl_b32 s34, s52, 16 +; SI-NEXT: s_and_b32 s37, s51, 0xffff0000 +; SI-NEXT: s_lshl_b32 s36, s51, 16 +; SI-NEXT: s_and_b32 s39, s50, 0xffff0000 +; SI-NEXT: s_lshl_b32 s38, s50, 16 +; SI-NEXT: v_writelane_b32 v22, s4, 3 ; SI-NEXT: s_mov_b64 s[4:5], 0 ; SI-NEXT: s_branch .LBB17_3 ; SI-NEXT: .LBB17_2: ; SI-NEXT: ; implicit-def: $sgpr4 ; SI-NEXT: ; kill: killed $sgpr4 -; SI-NEXT: ; implicit-def: $sgpr68 -; SI-NEXT: ; implicit-def: $sgpr69 -; SI-NEXT: ; implicit-def: $sgpr66 -; SI-NEXT: ; implicit-def: $sgpr67 -; SI-NEXT: ; implicit-def: $sgpr64 -; SI-NEXT: ; implicit-def: $sgpr65 -; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; implicit-def: $sgpr55 -; SI-NEXT: ; implicit-def: $sgpr52 -; SI-NEXT: ; implicit-def: $sgpr53 -; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; implicit-def: $sgpr51 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr49 ; SI-NEXT: ; implicit-def: $sgpr38 ; SI-NEXT: ; implicit-def: $sgpr39 ; SI-NEXT: ; implicit-def: $sgpr36 @@ -23655,6 +23781,20 @@ define inreg <64 x bfloat> @bitcast_v32i32_to_v64bf16_scalar(<32 x i32> inreg %a ; SI-NEXT: ; implicit-def: $sgpr43 ; SI-NEXT: ; implicit-def: $sgpr40 ; SI-NEXT: ; implicit-def: $sgpr41 +; SI-NEXT: ; implicit-def: $sgpr28 +; SI-NEXT: ; implicit-def: $sgpr29 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr27 +; SI-NEXT: ; implicit-def: $sgpr24 +; SI-NEXT: ; implicit-def: $sgpr25 +; SI-NEXT: ; implicit-def: $sgpr22 +; SI-NEXT: ; implicit-def: $sgpr23 +; SI-NEXT: ; implicit-def: $sgpr20 +; SI-NEXT: ; implicit-def: $sgpr21 +; SI-NEXT: ; implicit-def: $sgpr18 +; SI-NEXT: ; implicit-def: $sgpr19 +; SI-NEXT: ; implicit-def: $sgpr16 +; SI-NEXT: ; implicit-def: $sgpr17 ; SI-NEXT: ; implicit-def: $sgpr14 ; SI-NEXT: ; implicit-def: $sgpr15 ; SI-NEXT: ; implicit-def: $sgpr12 @@ -23676,8 +23816,22 @@ define inreg <64 x bfloat> @bitcast_v32i32_to_v64bf16_scalar(<32 x i32> inreg %a ; SI-NEXT: s_mov_b32 s11, s13 ; SI-NEXT: s_mov_b32 s12, s14 ; SI-NEXT: s_mov_b32 s13, s15 -; SI-NEXT: s_mov_b32 s14, s40 -; SI-NEXT: s_mov_b32 s15, s41 +; SI-NEXT: s_mov_b32 s14, s16 +; SI-NEXT: s_mov_b32 s15, s17 +; SI-NEXT: s_mov_b32 s16, s18 +; SI-NEXT: s_mov_b32 s17, s19 +; SI-NEXT: s_mov_b32 s18, s20 +; SI-NEXT: s_mov_b32 s19, s21 +; SI-NEXT: s_mov_b32 s20, s22 +; SI-NEXT: s_mov_b32 s21, s23 +; SI-NEXT: s_mov_b32 s22, s24 +; SI-NEXT: s_mov_b32 s23, s25 +; SI-NEXT: s_mov_b32 s24, s26 +; SI-NEXT: s_mov_b32 s25, s27 +; SI-NEXT: s_mov_b32 s26, s28 +; SI-NEXT: s_mov_b32 s27, s29 +; SI-NEXT: s_mov_b32 s28, s40 +; SI-NEXT: s_mov_b32 s29, s41 ; SI-NEXT: s_mov_b32 s40, s42 ; SI-NEXT: s_mov_b32 s41, s43 ; SI-NEXT: s_mov_b32 s42, s44 @@ -23692,30 +23846,25 @@ define inreg <64 x bfloat> @bitcast_v32i32_to_v64bf16_scalar(<32 x i32> inreg %a ; SI-NEXT: s_mov_b32 s59, s61 ; SI-NEXT: s_mov_b32 s60, s62 ; SI-NEXT: s_mov_b32 s61, s63 -; SI-NEXT: s_mov_b32 s62, s72 -; SI-NEXT: s_mov_b32 s63, s73 -; SI-NEXT: s_mov_b32 s72, s74 -; SI-NEXT: s_mov_b32 s73, s75 -; SI-NEXT: s_mov_b32 s74, s76 -; SI-NEXT: v_readlane_b32 s75, v21, 0 -; SI-NEXT: v_readlane_b32 s76, v21, 1 +; SI-NEXT: v_readlane_b32 s62, v22, 0 +; SI-NEXT: v_readlane_b32 s63, v22, 1 ; SI-NEXT: s_cbranch_vccnz .LBB17_5 ; SI-NEXT: ; %bb.4: ; %cmp.true -; SI-NEXT: s_add_i32 s16, s16, 3 +; SI-NEXT: s_add_i32 s48, s48, 3 ; SI-NEXT: s_add_i32 s6, s6, 3 -; SI-NEXT: s_add_i32 s17, s17, 3 -; SI-NEXT: s_add_i32 s18, s18, 3 -; SI-NEXT: s_add_i32 s19, s19, 3 -; SI-NEXT: s_add_i32 s20, s20, 3 -; SI-NEXT: s_add_i32 s21, s21, 3 -; SI-NEXT: s_add_i32 s22, s22, 3 -; SI-NEXT: s_add_i32 s23, s23, 3 -; SI-NEXT: s_add_i32 s24, s24, 3 -; SI-NEXT: s_add_i32 s25, s25, 3 -; SI-NEXT: s_add_i32 s26, s26, 3 -; SI-NEXT: s_add_i32 s27, s27, 3 -; SI-NEXT: s_add_i32 s28, s28, 3 -; SI-NEXT: s_add_i32 s29, s29, 3 +; SI-NEXT: s_add_i32 s49, s49, 3 +; SI-NEXT: s_add_i32 s50, s50, 3 +; SI-NEXT: s_add_i32 s51, s51, 3 +; SI-NEXT: s_add_i32 s52, s52, 3 +; SI-NEXT: s_add_i32 s53, s53, 3 +; SI-NEXT: s_add_i32 s54, s54, 3 +; SI-NEXT: s_add_i32 s55, s55, 3 +; SI-NEXT: s_add_i32 s64, s64, 3 +; SI-NEXT: s_add_i32 s65, s65, 3 +; SI-NEXT: s_add_i32 s66, s66, 3 +; SI-NEXT: s_add_i32 s67, s67, 3 +; SI-NEXT: s_add_i32 s68, s68, 3 +; SI-NEXT: s_add_i32 s69, s69, 3 ; SI-NEXT: s_add_i32 s70, s70, 3 ; SI-NEXT: s_add_i32 s71, s71, 3 ; SI-NEXT: s_add_i32 s80, s80, 3 @@ -23735,335 +23884,335 @@ define inreg <64 x bfloat> @bitcast_v32i32_to_v64bf16_scalar(<32 x i32> inreg %a ; SI-NEXT: s_add_i32 s9, s9, 3 ; SI-NEXT: s_and_b32 s15, s6, 0xffff0000 ; SI-NEXT: s_lshl_b32 s14, s6, 16 -; SI-NEXT: s_and_b32 s6, s16, 0xffff0000 +; SI-NEXT: s_and_b32 s6, s48, 0xffff0000 ; SI-NEXT: s_and_b32 s5, s9, 0xffff0000 ; SI-NEXT: s_lshl_b32 s4, s9, 16 ; SI-NEXT: s_and_b32 s11, s8, 0xffff0000 ; SI-NEXT: s_lshl_b32 s10, s8, 16 ; SI-NEXT: s_and_b32 s13, s7, 0xffff0000 ; SI-NEXT: s_lshl_b32 s12, s7, 16 -; SI-NEXT: s_and_b32 s41, s99, 0xffff0000 -; SI-NEXT: s_lshl_b32 s40, s99, 16 -; SI-NEXT: s_and_b32 s43, s98, 0xffff0000 -; SI-NEXT: s_lshl_b32 s42, s98, 16 -; SI-NEXT: s_and_b32 s45, s97, 0xffff0000 -; SI-NEXT: s_lshl_b32 s44, s97, 16 -; SI-NEXT: s_and_b32 s47, s96, 0xffff0000 -; SI-NEXT: s_lshl_b32 s46, s96, 16 -; SI-NEXT: s_and_b32 s57, s87, 0xffff0000 -; SI-NEXT: s_lshl_b32 s56, s87, 16 -; SI-NEXT: s_and_b32 s59, s86, 0xffff0000 -; SI-NEXT: s_lshl_b32 s58, s86, 16 -; SI-NEXT: s_and_b32 s61, s85, 0xffff0000 -; SI-NEXT: s_lshl_b32 s60, s85, 16 -; SI-NEXT: s_and_b32 s63, s84, 0xffff0000 -; SI-NEXT: s_lshl_b32 s62, s84, 16 -; SI-NEXT: s_and_b32 s73, s83, 0xffff0000 -; SI-NEXT: s_lshl_b32 s72, s83, 16 -; SI-NEXT: s_and_b32 s77, s82, 0xffff0000 -; SI-NEXT: s_lshl_b32 s74, s82, 16 -; SI-NEXT: s_and_b32 s79, s81, 0xffff0000 -; SI-NEXT: s_lshl_b32 s78, s81, 16 -; SI-NEXT: s_and_b32 s89, s80, 0xffff0000 -; SI-NEXT: s_lshl_b32 s88, s80, 16 -; SI-NEXT: s_and_b32 s91, s71, 0xffff0000 -; SI-NEXT: s_lshl_b32 s90, s71, 16 -; SI-NEXT: s_and_b32 s93, s70, 0xffff0000 -; SI-NEXT: s_lshl_b32 s92, s70, 16 -; SI-NEXT: s_and_b32 s95, s29, 0xffff0000 -; SI-NEXT: s_lshl_b32 s94, s29, 16 -; SI-NEXT: s_and_b32 s31, s28, 0xffff0000 -; SI-NEXT: s_lshl_b32 s30, s28, 16 -; SI-NEXT: s_and_b32 s35, s27, 0xffff0000 -; SI-NEXT: s_lshl_b32 s34, s27, 16 -; SI-NEXT: s_and_b32 s37, s26, 0xffff0000 -; SI-NEXT: s_lshl_b32 s36, s26, 16 -; SI-NEXT: s_and_b32 s39, s25, 0xffff0000 -; SI-NEXT: s_lshl_b32 s38, s25, 16 -; SI-NEXT: s_and_b32 s49, s24, 0xffff0000 -; SI-NEXT: s_lshl_b32 s48, s24, 16 -; SI-NEXT: s_and_b32 s51, s23, 0xffff0000 -; SI-NEXT: s_lshl_b32 s50, s23, 16 -; SI-NEXT: s_and_b32 s53, s22, 0xffff0000 -; SI-NEXT: s_lshl_b32 s52, s22, 16 -; SI-NEXT: s_and_b32 s55, s21, 0xffff0000 -; SI-NEXT: s_lshl_b32 s54, s21, 16 -; SI-NEXT: s_and_b32 s65, s20, 0xffff0000 -; SI-NEXT: s_lshl_b32 s64, s20, 16 -; SI-NEXT: s_and_b32 s67, s19, 0xffff0000 -; SI-NEXT: s_lshl_b32 s66, s19, 16 -; SI-NEXT: s_and_b32 s69, s18, 0xffff0000 -; SI-NEXT: s_lshl_b32 s68, s18, 16 -; SI-NEXT: s_and_b32 s76, s17, 0xffff0000 -; SI-NEXT: s_lshl_b32 s75, s17, 16 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v21, s6, 2 -; SI-NEXT: s_lshl_b32 s6, s16, 16 -; SI-NEXT: v_writelane_b32 v21, s6, 3 +; SI-NEXT: s_and_b32 s17, s99, 0xffff0000 +; SI-NEXT: s_lshl_b32 s16, s99, 16 +; SI-NEXT: s_and_b32 s19, s98, 0xffff0000 +; SI-NEXT: s_lshl_b32 s18, s98, 16 +; SI-NEXT: s_and_b32 s21, s97, 0xffff0000 +; SI-NEXT: s_lshl_b32 s20, s97, 16 +; SI-NEXT: s_and_b32 s23, s96, 0xffff0000 +; SI-NEXT: s_lshl_b32 s22, s96, 16 +; SI-NEXT: s_and_b32 s25, s87, 0xffff0000 +; SI-NEXT: s_lshl_b32 s24, s87, 16 +; SI-NEXT: s_and_b32 s27, s86, 0xffff0000 +; SI-NEXT: s_lshl_b32 s26, s86, 16 +; SI-NEXT: s_and_b32 s29, s85, 0xffff0000 +; SI-NEXT: s_lshl_b32 s28, s85, 16 +; SI-NEXT: s_and_b32 s41, s84, 0xffff0000 +; SI-NEXT: s_lshl_b32 s40, s84, 16 +; SI-NEXT: s_and_b32 s43, s83, 0xffff0000 +; SI-NEXT: s_lshl_b32 s42, s83, 16 +; SI-NEXT: s_and_b32 s45, s82, 0xffff0000 +; SI-NEXT: s_lshl_b32 s44, s82, 16 +; SI-NEXT: s_and_b32 s47, s81, 0xffff0000 +; SI-NEXT: s_lshl_b32 s46, s81, 16 +; SI-NEXT: s_and_b32 s57, s80, 0xffff0000 +; SI-NEXT: s_lshl_b32 s56, s80, 16 +; SI-NEXT: s_and_b32 s59, s71, 0xffff0000 +; SI-NEXT: s_lshl_b32 s58, s71, 16 +; SI-NEXT: s_and_b32 s61, s70, 0xffff0000 +; SI-NEXT: s_lshl_b32 s60, s70, 16 +; SI-NEXT: s_and_b32 s73, s69, 0xffff0000 +; SI-NEXT: s_lshl_b32 s72, s69, 16 +; SI-NEXT: s_and_b32 s75, s68, 0xffff0000 +; SI-NEXT: s_lshl_b32 s74, s68, 16 +; SI-NEXT: s_and_b32 s77, s67, 0xffff0000 +; SI-NEXT: s_lshl_b32 s76, s67, 16 +; SI-NEXT: s_and_b32 s79, s66, 0xffff0000 +; SI-NEXT: s_lshl_b32 s78, s66, 16 +; SI-NEXT: s_and_b32 s89, s65, 0xffff0000 +; SI-NEXT: s_lshl_b32 s88, s65, 16 +; SI-NEXT: s_and_b32 s91, s64, 0xffff0000 +; SI-NEXT: s_lshl_b32 s90, s64, 16 +; SI-NEXT: s_and_b32 s93, s55, 0xffff0000 +; SI-NEXT: s_lshl_b32 s92, s55, 16 +; SI-NEXT: s_and_b32 s95, s54, 0xffff0000 +; SI-NEXT: s_lshl_b32 s94, s54, 16 +; SI-NEXT: s_and_b32 s31, s53, 0xffff0000 +; SI-NEXT: s_lshl_b32 s30, s53, 16 +; SI-NEXT: s_and_b32 s35, s52, 0xffff0000 +; SI-NEXT: s_lshl_b32 s34, s52, 16 +; SI-NEXT: s_and_b32 s37, s51, 0xffff0000 +; SI-NEXT: s_lshl_b32 s36, s51, 16 +; SI-NEXT: s_and_b32 s39, s50, 0xffff0000 +; SI-NEXT: s_lshl_b32 s38, s50, 16 +; SI-NEXT: s_and_b32 s63, s49, 0xffff0000 +; SI-NEXT: s_lshl_b32 s62, s49, 16 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_writelane_b32 v22, s6, 2 +; SI-NEXT: s_lshl_b32 s6, s48, 16 +; SI-NEXT: v_writelane_b32 v22, s6, 3 ; SI-NEXT: .LBB17_5: ; %end -; SI-NEXT: v_readlane_b32 s6, v21, 2 +; SI-NEXT: v_readlane_b32 s6, v22, 2 ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s6 -; SI-NEXT: v_readlane_b32 s6, v21, 3 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s6 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_readlane_b32 s6, v22, 3 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s6 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_readlane_b32 s99, v21, 35 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s76 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s75 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s63 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s62 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s69 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s68 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s39 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s38 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s67 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s66 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s37 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s36 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s65 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s64 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s35 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s34 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s55 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s54 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s31 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s30 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s53 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s52 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s95 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s94 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s51 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s50 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s93 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s92 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s49 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s48 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s91 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s90 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s39 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s38 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s89 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s88 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s37 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s36 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s79 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s78 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s35 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s34 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s77 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s76 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s31 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s30 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s75 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s74 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s95 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s94 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s73 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s72 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s93 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s92 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s61 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s60 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s91 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s90 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s59 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s58 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s89 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s88 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s57 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s56 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 64, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s79 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s78 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s47 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s46 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s77 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s74 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s45 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s44 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x48, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s73 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s72 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s43 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s42 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s63 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s62 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s41 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s40 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x50, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s61 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s60 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s29 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s28 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s59 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s58 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s27 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s26 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x58, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s57 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s56 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s25 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s24 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s47 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s46 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s23 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s22 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x60, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s45 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s44 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s21 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s20 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x64, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s43 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s42 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s19 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s18 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x68, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s41 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s40 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s17 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s16 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s15 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s14 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s14 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x70, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s13 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s12 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s12 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s11 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s10 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s10 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s5 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s99, v20, 35 -; SI-NEXT: v_readlane_b32 s98, v20, 34 -; SI-NEXT: v_readlane_b32 s97, v20, 33 -; SI-NEXT: v_readlane_b32 s96, v20, 32 -; SI-NEXT: v_readlane_b32 s87, v20, 31 -; SI-NEXT: v_readlane_b32 s86, v20, 30 -; SI-NEXT: v_readlane_b32 s85, v20, 29 -; SI-NEXT: v_readlane_b32 s84, v20, 28 -; SI-NEXT: v_readlane_b32 s83, v20, 27 -; SI-NEXT: v_readlane_b32 s82, v20, 26 -; SI-NEXT: v_readlane_b32 s81, v20, 25 -; SI-NEXT: v_readlane_b32 s80, v20, 24 -; SI-NEXT: v_readlane_b32 s71, v20, 23 -; SI-NEXT: v_readlane_b32 s70, v20, 22 -; SI-NEXT: v_readlane_b32 s69, v20, 21 -; SI-NEXT: v_readlane_b32 s68, v20, 20 -; SI-NEXT: v_readlane_b32 s67, v20, 19 -; SI-NEXT: v_readlane_b32 s66, v20, 18 -; SI-NEXT: v_readlane_b32 s65, v20, 17 -; SI-NEXT: v_readlane_b32 s64, v20, 16 -; SI-NEXT: v_readlane_b32 s55, v20, 15 -; SI-NEXT: v_readlane_b32 s54, v20, 14 -; SI-NEXT: v_readlane_b32 s53, v20, 13 -; SI-NEXT: v_readlane_b32 s52, v20, 12 -; SI-NEXT: v_readlane_b32 s51, v20, 11 -; SI-NEXT: v_readlane_b32 s50, v20, 10 -; SI-NEXT: v_readlane_b32 s49, v20, 9 -; SI-NEXT: v_readlane_b32 s48, v20, 8 -; SI-NEXT: v_readlane_b32 s39, v20, 7 -; SI-NEXT: v_readlane_b32 s38, v20, 6 -; SI-NEXT: v_readlane_b32 s37, v20, 5 -; SI-NEXT: v_readlane_b32 s36, v20, 4 -; SI-NEXT: v_readlane_b32 s35, v20, 3 -; SI-NEXT: v_readlane_b32 s34, v20, 2 -; SI-NEXT: v_readlane_b32 s31, v20, 1 -; SI-NEXT: v_readlane_b32 s30, v20, 0 +; SI-NEXT: v_readlane_b32 s98, v21, 34 +; SI-NEXT: v_readlane_b32 s97, v21, 33 +; SI-NEXT: v_readlane_b32 s96, v21, 32 +; SI-NEXT: v_readlane_b32 s87, v21, 31 +; SI-NEXT: v_readlane_b32 s86, v21, 30 +; SI-NEXT: v_readlane_b32 s85, v21, 29 +; SI-NEXT: v_readlane_b32 s84, v21, 28 +; SI-NEXT: v_readlane_b32 s83, v21, 27 +; SI-NEXT: v_readlane_b32 s82, v21, 26 +; SI-NEXT: v_readlane_b32 s81, v21, 25 +; SI-NEXT: v_readlane_b32 s80, v21, 24 +; SI-NEXT: v_readlane_b32 s71, v21, 23 +; SI-NEXT: v_readlane_b32 s70, v21, 22 +; SI-NEXT: v_readlane_b32 s69, v21, 21 +; SI-NEXT: v_readlane_b32 s68, v21, 20 +; SI-NEXT: v_readlane_b32 s67, v21, 19 +; SI-NEXT: v_readlane_b32 s66, v21, 18 +; SI-NEXT: v_readlane_b32 s65, v21, 17 +; SI-NEXT: v_readlane_b32 s64, v21, 16 +; SI-NEXT: v_readlane_b32 s55, v21, 15 +; SI-NEXT: v_readlane_b32 s54, v21, 14 +; SI-NEXT: v_readlane_b32 s53, v21, 13 +; SI-NEXT: v_readlane_b32 s52, v21, 12 +; SI-NEXT: v_readlane_b32 s51, v21, 11 +; SI-NEXT: v_readlane_b32 s50, v21, 10 +; SI-NEXT: v_readlane_b32 s49, v21, 9 +; SI-NEXT: v_readlane_b32 s48, v21, 8 +; SI-NEXT: v_readlane_b32 s39, v21, 7 +; SI-NEXT: v_readlane_b32 s38, v21, 6 +; SI-NEXT: v_readlane_b32 s37, v21, 5 +; SI-NEXT: v_readlane_b32 s36, v21, 4 +; SI-NEXT: v_readlane_b32 s35, v21, 3 +; SI-NEXT: v_readlane_b32 s34, v21, 2 +; SI-NEXT: v_readlane_b32 s31, v21, 1 +; SI-NEXT: v_readlane_b32 s30, v21, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] @@ -27302,562 +27451,737 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v52, v30 -; SI-NEXT: v_mov_b32_e32 v53, v28 -; SI-NEXT: v_mov_b32_e32 v40, v12 -; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:76 -; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 -; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:8 -; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:4 -; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:16 -; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:12 -; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:24 -; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:20 -; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:32 -; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:28 -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:40 -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:36 -; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:44 +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76 +; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 +; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:16 +; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:24 +; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:32 +; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:40 +; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48 +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:56 +; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:64 +; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:72 +; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:4 +; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:12 +; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:20 +; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28 +; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:36 +; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:44 +; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:52 +; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:60 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:68 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:56 -; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:52 -; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:64 -; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:60 -; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72 -; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:68 -; SI-NEXT: v_mov_b32_e32 v55, v14 -; SI-NEXT: v_mul_f32_e32 v14, 1.0, v0 -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v6 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v63, 1.0, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v8 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v7 +; SI-NEXT: v_mov_b32_e32 v43, v21 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v10 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11 +; SI-NEXT: v_mov_b32_e32 v54, v29 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v43 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v16 -; SI-NEXT: v_mul_f32_e32 v58, 1.0, v1 -; SI-NEXT: v_mul_f32_e32 v56, 1.0, v3 -; SI-NEXT: v_mul_f32_e32 v54, 1.0, v2 -; SI-NEXT: v_mul_f32_e32 v44, 1.0, v5 -; SI-NEXT: v_mul_f32_e32 v46, 1.0, v4 -; SI-NEXT: v_mul_f32_e32 v61, 1.0, v7 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v54 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v41, v23 +; SI-NEXT: v_mov_b32_e32 v29, v20 +; SI-NEXT: v_mul_f32_e32 v57, 1.0, v3 ; SI-NEXT: v_mul_f32_e32 v59, 1.0, v9 -; SI-NEXT: v_mul_f32_e32 v57, 1.0, v11 -; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13 -; SI-NEXT: v_mul_f32_e32 v47, 1.0, v40 -; SI-NEXT: v_mul_f32_e32 v45, 1.0, v15 -; SI-NEXT: v_mul_f32_e32 v15, 1.0, v17 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; SI-NEXT: v_mul_f32_e32 v16, 1.0, v19 -; SI-NEXT: v_mul_f32_e32 v43, 1.0, v18 -; SI-NEXT: v_mul_f32_e32 v17, 1.0, v21 -; SI-NEXT: v_mul_f32_e32 v41, 1.0, v20 -; SI-NEXT: v_mul_f32_e32 v18, 1.0, v23 -; SI-NEXT: v_mul_f32_e32 v40, 1.0, v22 -; SI-NEXT: v_mul_f32_e32 v19, 1.0, v25 -; SI-NEXT: v_mul_f32_e32 v55, 1.0, v24 -; SI-NEXT: v_mul_f32_e32 v20, 1.0, v27 -; SI-NEXT: v_mul_f32_e32 v21, 1.0, v29 -; SI-NEXT: v_mul_f32_e32 v53, 1.0, v53 -; SI-NEXT: v_mul_f32_e32 v52, 1.0, v52 +; SI-NEXT: v_mul_f32_e32 v61, 1.0, v13 +; SI-NEXT: v_mul_f32_e32 v23, 1.0, v15 +; SI-NEXT: v_mul_f32_e32 v44, 1.0, v17 +; SI-NEXT: v_mul_f32_e32 v21, 1.0, v19 +; SI-NEXT: v_mul_f32_e32 v20, 1.0, v41 +; SI-NEXT: v_mul_f32_e32 v17, 1.0, v25 +; SI-NEXT: v_mul_f32_e32 v15, 1.0, v27 +; SI-NEXT: v_mul_f32_e64 v25, 1.0, s17 +; SI-NEXT: v_mul_f32_e64 v3, 1.0, s21 +; SI-NEXT: v_mul_f32_e64 v5, 1.0, s25 +; SI-NEXT: v_mul_f32_e64 v7, 1.0, s29 +; SI-NEXT: v_mul_f32_e32 v9, 1.0, v2 +; SI-NEXT: v_mul_f32_e32 v54, 1.0, v4 +; SI-NEXT: v_mul_f32_e32 v11, 1.0, v6 +; SI-NEXT: v_mul_f32_e32 v56, 1.0, v8 +; SI-NEXT: v_mul_f32_e32 v13, 1.0, v10 +; SI-NEXT: v_mul_f32_e32 v58, 1.0, v12 +; SI-NEXT: v_mul_f32_e32 v60, 1.0, v14 +; SI-NEXT: v_mul_f32_e32 v62, 1.0, v16 +; SI-NEXT: v_mul_f32_e32 v47, 1.0, v22 +; SI-NEXT: v_mul_f32_e32 v22, 1.0, v28 +; SI-NEXT: v_mul_f32_e64 v19, 1.0, s16 +; SI-NEXT: v_mul_f32_e64 v14, 1.0, s20 +; SI-NEXT: v_mul_f32_e64 v16, 1.0, s22 +; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v32 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v33 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v34 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v35 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v37 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v38 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v39 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v48 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v49 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v0, 1.0, s17 -; SI-NEXT: v_mul_f32_e64 v3, 1.0, s16 ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s19 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s18 -; SI-NEXT: v_mul_f32_e64 v4, 1.0, s21 -; SI-NEXT: v_mul_f32_e64 v8, 1.0, s20 -; SI-NEXT: v_mul_f32_e64 v10, 1.0, s23 -; SI-NEXT: v_mul_f32_e64 v9, 1.0, s22 -; SI-NEXT: v_mul_f32_e64 v5, 1.0, s27 -; SI-NEXT: v_mul_f32_e64 v11, 1.0, s26 -; SI-NEXT: v_mul_f32_e64 v6, 1.0, s29 -; SI-NEXT: v_mul_f32_e64 v7, 1.0, s28 +; SI-NEXT: v_mul_f32_e32 v39, 1.0, v0 ; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v48 -; SI-NEXT: v_mul_f32_e32 v48, 1.0, v26 -; SI-NEXT: v_mul_f32_e32 v22, 1.0, v51 +; SI-NEXT: v_mul_f32_e32 v0, 1.0, v45 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill ; SI-NEXT: s_and_b64 s[4:5], vcc, exec -; SI-NEXT: v_mul_f32_e32 v23, 1.0, v37 -; SI-NEXT: v_mul_f32_e32 v51, 1.0, v50 -; SI-NEXT: v_mul_f32_e32 v24, 1.0, v38 -; SI-NEXT: v_mul_f32_e32 v50, 1.0, v49 -; SI-NEXT: v_mul_f32_e32 v25, 1.0, v39 -; SI-NEXT: v_mul_f32_e32 v49, 1.0, v30 -; SI-NEXT: v_mul_f32_e32 v26, 1.0, v28 -; SI-NEXT: v_mul_f32_e32 v39, 1.0, v12 -; SI-NEXT: v_mul_f32_e32 v27, 1.0, v31 -; SI-NEXT: s_waitcnt vmcnt(13) -; SI-NEXT: v_mul_f32_e32 v38, 1.0, v60 -; SI-NEXT: s_waitcnt vmcnt(12) +; SI-NEXT: v_mul_f32_e64 v35, 1.0, s23 +; SI-NEXT: v_mul_f32_e64 v33, 1.0, s27 +; SI-NEXT: v_mul_f32_e32 v32, 1.0, v18 +; SI-NEXT: v_mul_f32_e32 v34, 1.0, v29 +; SI-NEXT: v_mul_f32_e32 v36, 1.0, v24 +; SI-NEXT: v_mul_f32_e32 v38, 1.0, v26 +; SI-NEXT: v_mul_f32_e32 v31, 1.0, v30 +; SI-NEXT: v_mul_f32_e32 v24, 1.0, v51 +; SI-NEXT: v_mul_f32_e32 v41, 1.0, v53 +; SI-NEXT: v_mul_f32_e32 v26, 1.0, v55 +; SI-NEXT: v_mul_f32_e32 v43, 1.0, v40 ; SI-NEXT: v_mul_f32_e32 v28, 1.0, v42 -; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_mul_f32_e32 v37, 1.0, v62 -; SI-NEXT: s_waitcnt vmcnt(10) -; SI-NEXT: v_mul_f32_e32 v29, 1.0, v63 -; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_mul_f32_e32 v32, 1.0, v32 -; SI-NEXT: s_waitcnt vmcnt(8) -; SI-NEXT: v_mul_f32_e32 v30, 1.0, v33 -; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_mul_f32_e32 v31, 1.0, v34 -; SI-NEXT: s_waitcnt vmcnt(6) -; SI-NEXT: v_mul_f32_e32 v33, 1.0, v35 -; SI-NEXT: s_waitcnt vmcnt(5) -; SI-NEXT: v_mul_f32_e32 v42, 1.0, v36 -; SI-NEXT: v_mul_f32_e64 v12, 1.0, s25 -; SI-NEXT: v_mul_f32_e64 v34, 1.0, s24 -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v51, 1.0, v50 +; SI-NEXT: v_mul_f32_e32 v53, 1.0, v52 +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_mul_f32_e32 v0, 1.0, v46 +; SI-NEXT: v_mul_f32_e64 v48, 1.0, s18 +; SI-NEXT: v_mul_f32_e64 v18, 1.0, s24 +; SI-NEXT: v_mul_f32_e64 v29, 1.0, s26 +; SI-NEXT: v_mul_f32_e64 v45, 1.0, s28 +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB19_2 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; SI-NEXT: s_waitcnt expcnt(6) -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_alignbit_b32 v0, v0, v3, 16 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4 -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v10 -; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; SI-NEXT: v_alignbit_b32 v2, v2, v8, 16 -; SI-NEXT: v_alignbit_b32 v3, v3, v9, 16 -; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16 -; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v58 -; SI-NEXT: s_waitcnt expcnt(5) -; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v56 -; SI-NEXT: s_waitcnt expcnt(4) -; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v44 -; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; SI-NEXT: v_alignbit_b32 v5, v5, v11, 16 -; SI-NEXT: v_alignbit_b32 v7, v7, v14, 16 -; SI-NEXT: v_alignbit_b32 v8, v8, v54, 16 -; SI-NEXT: v_alignbit_b32 v9, v9, v46, 16 -; SI-NEXT: v_mov_b32_e32 v62, v61 -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v61 -; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; SI-NEXT: v_mov_b32_e32 v60, v59 -; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v59 -; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; SI-NEXT: v_mov_b32_e32 v56, v47 -; SI-NEXT: v_alignbit_b32 v13, v13, v47, 16 -; SI-NEXT: v_mov_b32_e32 v46, v45 -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v45 -; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v12 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v57 -; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22 -; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23 -; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 -; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26 -; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28 -; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29 -; SI-NEXT: v_alignbit_b32 v30, v30, v31, 16 -; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v33 -; SI-NEXT: v_alignbit_b32 v4, v4, v34, 16 -; SI-NEXT: v_mov_b32_e32 v63, v44 -; SI-NEXT: v_mov_b32_e32 v58, v57 -; SI-NEXT: v_mov_b32_e32 v44, v43 -; SI-NEXT: v_alignbit_b32 v16, v16, v43, 16 -; SI-NEXT: v_mov_b32_e32 v43, v41 -; SI-NEXT: v_alignbit_b32 v17, v17, v41, 16 -; SI-NEXT: v_alignbit_b32 v18, v18, v40, 16 -; SI-NEXT: v_mov_b32_e32 v40, v55 -; SI-NEXT: v_alignbit_b32 v19, v19, v55, 16 -; SI-NEXT: v_alignbit_b32 v20, v20, v48, 16 -; SI-NEXT: v_mov_b32_e32 v48, v53 -; SI-NEXT: v_alignbit_b32 v21, v21, v53, 16 -; SI-NEXT: v_alignbit_b32 v22, v22, v52, 16 -; SI-NEXT: v_mov_b32_e32 v52, v51 -; SI-NEXT: v_alignbit_b32 v23, v23, v51, 16 -; SI-NEXT: v_alignbit_b32 v24, v24, v50, 16 -; SI-NEXT: v_mov_b32_e32 v50, v49 -; SI-NEXT: v_alignbit_b32 v25, v25, v49, 16 -; SI-NEXT: v_mov_b32_e32 v36, v39 -; SI-NEXT: v_alignbit_b32 v26, v26, v39, 16 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v34, v38 -; SI-NEXT: v_alignbit_b32 v27, v27, v38, 16 -; SI-NEXT: v_mov_b32_e32 v35, v37 -; SI-NEXT: v_alignbit_b32 v28, v28, v37, 16 -; SI-NEXT: v_mov_b32_e32 v37, v32 -; SI-NEXT: v_alignbit_b32 v29, v29, v32, 16 -; SI-NEXT: v_alignbit_b32 v31, v31, v42, 16 +; SI-NEXT: v_mov_b32_e32 v0, v19 +; SI-NEXT: v_mov_b32_e32 v37, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v25 +; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v33 +; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v7 +; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v63 +; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v57 +; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v61 +; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v23 +; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v44 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v21 +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 s[4:5], 0 -; SI-NEXT: v_mov_b32_e32 v32, v33 -; SI-NEXT: v_mov_b32_e32 v33, v42 -; SI-NEXT: s_waitcnt vmcnt(4) -; SI-NEXT: v_alignbit_b32 v10, v10, v61, 16 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_alignbit_b32 v12, v12, v54, 16 -; SI-NEXT: v_mov_b32_e32 v41, v61 +; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v1 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[0:1], v[19:20], 16 +; SI-NEXT: v_mov_b32_e32 v1, v48 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[1:2], v[48:49], 16 +; SI-NEXT: v_mov_b32_e32 v2, v14 +; SI-NEXT: v_mov_b32_e32 v49, v15 +; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v3 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[2:3], v[14:15], 16 +; SI-NEXT: v_mov_b32_e32 v3, v16 +; SI-NEXT: v_mov_b32_e32 v20, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v35 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[3:4], v[16:17], 16 +; SI-NEXT: v_mov_b32_e32 v4, v18 +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v5 +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[4:5], v[18:19], 16 +; SI-NEXT: v_mov_b32_e32 v5, v29 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[5:6], v[29:30], 16 +; SI-NEXT: v_mov_b32_e32 v6, v45 +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[6:7], v[45:46], 16 +; SI-NEXT: v_mov_b32_e32 v7, v39 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[7:8], v[39:40], 16 +; SI-NEXT: v_mov_b32_e32 v8, v9 +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v37 +; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v20 +; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v49 +; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[8:9], v[9:10], 16 +; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v9 +; SI-NEXT: v_mov_b32_e32 v9, v54 +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[9:10], v[54:55], 16 +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v55, v13 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v10 +; SI-NEXT: v_mov_b32_e32 v10, v11 +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[10:11], v[11:12], 16 +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v11 +; SI-NEXT: v_mov_b32_e32 v11, v56 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[11:12], v[56:57], 16 +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v56, v44 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v12 +; SI-NEXT: v_lshr_b64 v[12:13], v[13:14], 16 +; SI-NEXT: v_mov_b32_e32 v13, v58 +; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[13:14], v[58:59], 16 +; SI-NEXT: v_mov_b32_e32 v14, v60 +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[14:15], v[60:61], 16 +; SI-NEXT: v_mov_b32_e32 v15, v62 +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[15:16], v[62:63], 16 +; SI-NEXT: v_mov_b32_e32 v16, v32 +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[16:17], v[32:33], 16 +; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v27 +; SI-NEXT: v_mov_b32_e32 v33, v34 +; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_alignbit_b32 v11, v11, v59, 16 -; SI-NEXT: v_mov_b32_e32 v55, v59 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_alignbit_b32 v14, v14, v45, 16 +; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v17 +; SI-NEXT: v_mov_b32_e32 v40, v17 +; SI-NEXT: v_lshr_b64 v[17:18], v[34:35], 16 +; SI-NEXT: v_lshr_b64 v[18:19], v[47:48], 16 +; SI-NEXT: v_lshr_b64 v[19:20], v[36:37], 16 +; SI-NEXT: v_mov_b32_e32 v20, v38 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[20:21], v[38:39], 16 +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; SI-NEXT: v_mov_b32_e32 v34, v47 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_alignbit_b32 v15, v15, v47, 16 -; SI-NEXT: v_mov_b32_e32 v51, v47 -; SI-NEXT: v_mov_b32_e32 v53, v45 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v21 +; SI-NEXT: v_mov_b32_e32 v21, v22 +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[21:22], v[22:23], 16 +; SI-NEXT: v_mov_b32_e32 v22, v31 +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[22:23], v[31:32], 16 +; SI-NEXT: v_mov_b32_e32 v23, v24 +; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[23:24], v[24:25], 16 +; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v52 +; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v30 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v24 +; SI-NEXT: v_mov_b32_e32 v24, v41 +; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[24:25], v[41:42], 16 +; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v41, v26 +; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v50 +; SI-NEXT: v_mov_b32_e32 v42, v51 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v25 +; SI-NEXT: v_lshr_b64 v[25:26], v[26:27], 16 +; SI-NEXT: v_mov_b32_e32 v26, v43 +; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[26:27], v[43:44], 16 +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v43, v28 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v27 +; SI-NEXT: v_lshr_b64 v[27:28], v[28:29], 16 +; SI-NEXT: v_lshr_b64 v[28:29], v[51:52], 16 +; SI-NEXT: v_lshr_b64 v[29:30], v[53:54], 16 +; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v52, v53 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v30 +; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshr_b64 v[30:31], v[31:32], 16 +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v57 +; SI-NEXT: v_mov_b32_e32 v53, v31 +; SI-NEXT: v_lshr_b64 v[31:32], v[31:32], 16 ; SI-NEXT: s_branch .LBB19_3 ; SI-NEXT: .LBB19_2: -; SI-NEXT: v_mov_b32_e32 v63, v44 -; SI-NEXT: v_mov_b32_e32 v44, v43 -; SI-NEXT: v_mov_b32_e32 v43, v41 -; SI-NEXT: v_mov_b32_e32 v40, v55 -; SI-NEXT: v_mov_b32_e32 v48, v53 -; SI-NEXT: v_mov_b32_e32 v52, v51 -; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload -; SI-NEXT: v_mov_b32_e32 v62, v61 -; SI-NEXT: v_mov_b32_e32 v60, v59 -; SI-NEXT: v_mov_b32_e32 v58, v57 -; SI-NEXT: v_mov_b32_e32 v56, v47 -; SI-NEXT: v_mov_b32_e32 v46, v45 -; SI-NEXT: v_mov_b32_e32 v50, v49 -; SI-NEXT: v_mov_b32_e32 v36, v39 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v34, v38 -; SI-NEXT: v_mov_b32_e32 v35, v37 -; SI-NEXT: v_mov_b32_e32 v37, v32 +; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill +; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v56, v44 +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v55, v13 +; SI-NEXT: s_waitcnt expcnt(2) +; SI-NEXT: v_mov_b32_e32 v33, v34 +; SI-NEXT: v_mov_b32_e32 v34, v47 +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_mov_b32_e32 v43, v28 +; SI-NEXT: v_mov_b32_e32 v52, v53 +; SI-NEXT: v_mov_b32_e32 v53, v0 ; SI-NEXT: s_mov_b64 s[4:5], -1 -; SI-NEXT: v_mov_b32_e32 v32, v33 -; SI-NEXT: v_mov_b32_e32 v33, v42 +; SI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_mov_b32_e32 v41, v26 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v42, v51 ; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; SI-NEXT: .LBB19_3: ; %Flow -; SI-NEXT: v_mov_b32_e32 v38, v50 -; SI-NEXT: v_mov_b32_e32 v39, v52 -; SI-NEXT: v_mov_b32_e32 v49, v40 -; SI-NEXT: v_mov_b32_e32 v50, v43 -; SI-NEXT: v_mov_b32_e32 v43, v44 -; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v37, v34 +; SI-NEXT: v_mov_b32_e32 v34, v33 +; SI-NEXT: v_mov_b32_e32 v35, v56 +; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: v_mov_b32_e32 v32, v40 +; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload ; SI-NEXT: s_andn2_b64 vcc, exec, s[4:5] +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_mov_b32_e32 v33, v38 +; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v51, v46 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v54, v46 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v44, v46 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v45, v56 +; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v47, v56 +; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v58, v60 +; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload ; SI-NEXT: s_cbranch_vccnz .LBB19_5 ; SI-NEXT: ; %bb.4: ; %cmp.true -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v44 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v57 +; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v61 +; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v49 ; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8 ; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v40 +; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v39 ; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 ; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v63 -; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 -; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v62 -; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 -; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v60 +; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v59 ; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 ; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v58 -; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 -; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v46 -; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 -; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32 +; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v40 +; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 +; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v35 +; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 +; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v32 +; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 +; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v53 ; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32 -; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 ; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 +; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16 -; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 -; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16 +; SI-NEXT: v_lshr_b64 v[1:2], v[2:3], 16 +; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v60 +; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 ; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 ; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 -; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; SI-NEXT: s_waitcnt vmcnt(13) ; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 ; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 ; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 -; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; SI-NEXT: s_waitcnt vmcnt(12) +; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 +; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; SI-NEXT: s_waitcnt vmcnt(8) +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; SI-NEXT: s_waitcnt vmcnt(7) +; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15 ; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 ; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 ; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; SI-NEXT: s_waitcnt vmcnt(13) ; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 ; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 ; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; SI-NEXT: s_waitcnt vmcnt(12) -; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 -; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 -; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22 -; SI-NEXT: s_waitcnt vmcnt(10) -; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 -; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23 -; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 -; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; SI-NEXT: s_waitcnt vmcnt(8) -; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 -; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 -; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26 -; SI-NEXT: s_waitcnt vmcnt(6) -; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 -; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; SI-NEXT: s_waitcnt vmcnt(5) +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 +; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 +; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 ; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 ; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28 -; SI-NEXT: s_waitcnt vmcnt(4) +; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 ; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 ; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 +; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26 ; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 -; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 -; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 -; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16 -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v58 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16 +; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v56 ; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 -; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16 -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16 +; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v47 ; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 -; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16 -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16 +; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v45 ; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 -; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16 -; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v45 +; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16 +; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v46 ; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 -; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16 -; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v42 +; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16 +; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v44 ; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8 -; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16 -; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v52 +; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16 +; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v54 ; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 -; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16 -; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v41 +; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16 +; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v51 ; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 -; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16 -; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v55 +; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16 +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v50 ; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 -; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16 -; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v54 +; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16 +; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v55 ; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 -; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16 -; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v56 +; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16 +; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v48 ; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 -; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16 -; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v53 +; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16 +; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v38 ; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 -; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16 -; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v51 +; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16 +; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v33 ; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 -; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16 -; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v43 +; SI-NEXT: v_lshr_b64 v[15:16], v[15:16], 16 +; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 +; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 ; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; SI-NEXT: v_alignbit_b32 v16, v17, v16, 16 -; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v50 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 ; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 -; SI-NEXT: v_alignbit_b32 v17, v18, v17, 16 -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; SI-NEXT: v_lshr_b64 v[16:17], v[16:17], 16 +; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v34 +; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 +; SI-NEXT: v_lshr_b64 v[17:18], v[17:18], 16 +; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v37 ; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; SI-NEXT: v_alignbit_b32 v18, v19, v18, 16 -; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v49 +; SI-NEXT: v_lshr_b64 v[18:19], v[18:19], 16 +; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v36 ; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 -; SI-NEXT: v_alignbit_b32 v19, v20, v19, 16 -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshr_b64 v[19:20], v[19:20], 16 +; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v33 +; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; SI-NEXT: v_lshr_b64 v[32:33], v[32:33], 16 +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 ; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 -; SI-NEXT: v_alignbit_b32 v20, v21, v20, 16 -; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v48 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 +; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; SI-NEXT: v_lshr_b64 v[20:21], v[20:21], 16 +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 ; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 -; SI-NEXT: v_alignbit_b32 v21, v22, v21, 16 -; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 ; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 -; SI-NEXT: v_alignbit_b32 v22, v23, v22, 16 -; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v39 +; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; SI-NEXT: v_lshr_b64 v[21:22], v[21:22], 16 +; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; SI-NEXT: v_lshr_b64 v[22:23], v[22:23], 16 +; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 ; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 -; SI-NEXT: v_alignbit_b32 v23, v24, v23, 16 -; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 ; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 -; SI-NEXT: v_alignbit_b32 v24, v25, v24, 16 -; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v38 +; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; SI-NEXT: v_lshr_b64 v[23:24], v[23:24], 16 +; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 ; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 -; SI-NEXT: v_alignbit_b32 v25, v26, v25, 16 -; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v36 +; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; SI-NEXT: v_lshr_b64 v[24:25], v[24:25], 16 +; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v41 +; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 +; SI-NEXT: v_lshr_b64 v[25:26], v[25:26], 16 +; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 ; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 -; SI-NEXT: v_alignbit_b32 v26, v27, v26, 16 -; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v34 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 ; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 -; SI-NEXT: v_alignbit_b32 v27, v28, v27, 16 -; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v35 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; SI-NEXT: v_lshr_b64 v[26:27], v[26:27], 16 +; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v43 +; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 +; SI-NEXT: v_lshr_b64 v[27:28], v[27:28], 16 +; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v42 ; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 -; SI-NEXT: v_alignbit_b32 v28, v29, v28, 16 -; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v37 +; SI-NEXT: v_lshr_b64 v[28:29], v[28:29], 16 +; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v52 ; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 -; SI-NEXT: v_alignbit_b32 v29, v30, v29, 16 -; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshr_b64 v[29:30], v[29:30], 16 +; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 ; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 -; SI-NEXT: v_alignbit_b32 v30, v31, v30, 16 -; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v33 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 ; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 -; SI-NEXT: v_alignbit_b32 v31, v32, v31, 16 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31 +; SI-NEXT: v_lshr_b64 v[30:31], v[30:31], 16 +; SI-NEXT: v_mov_b32_e32 v31, v32 ; SI-NEXT: .LBB19_5: ; %end ; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload @@ -27885,36 +28209,39 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a ; VI-NEXT: v_mov_b32_e32 v31, v17 ; VI-NEXT: v_mov_b32_e32 v30, v16 ; VI-NEXT: v_mov_b32_e32 v29, v15 -; VI-NEXT: v_mov_b32_e32 v28, v14 ; VI-NEXT: v_mov_b32_e32 v27, v13 -; VI-NEXT: v_mov_b32_e32 v26, v12 ; VI-NEXT: v_mov_b32_e32 v25, v11 -; VI-NEXT: v_mov_b32_e32 v24, v10 ; VI-NEXT: v_mov_b32_e32 v23, v9 -; VI-NEXT: v_mov_b32_e32 v22, v8 ; VI-NEXT: v_mov_b32_e32 v21, v7 -; VI-NEXT: v_mov_b32_e32 v20, v6 ; VI-NEXT: v_mov_b32_e32 v19, v5 -; VI-NEXT: v_mov_b32_e32 v32, v4 ; VI-NEXT: v_mov_b32_e32 v17, v3 -; VI-NEXT: v_mov_b32_e32 v16, v2 ; VI-NEXT: v_mov_b32_e32 v15, v1 +; VI-NEXT: v_mov_b32_e32 v28, v14 +; VI-NEXT: v_mov_b32_e32 v26, v12 +; VI-NEXT: v_mov_b32_e32 v24, v10 +; VI-NEXT: v_mov_b32_e32 v22, v8 +; VI-NEXT: v_mov_b32_e32 v20, v6 +; VI-NEXT: v_mov_b32_e32 v32, v4 +; VI-NEXT: v_mov_b32_e32 v16, v2 ; VI-NEXT: v_mov_b32_e32 v14, v0 -; VI-NEXT: v_mov_b32_e32 v0, s16 -; VI-NEXT: v_mov_b32_e32 v1, s17 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec -; VI-NEXT: v_mov_b32_e32 v2, s18 +; VI-NEXT: v_mov_b32_e32 v1, s17 ; VI-NEXT: v_mov_b32_e32 v3, s19 -; VI-NEXT: v_mov_b32_e32 v4, s20 ; VI-NEXT: v_mov_b32_e32 v5, s21 -; VI-NEXT: v_mov_b32_e32 v6, s22 ; VI-NEXT: v_mov_b32_e32 v7, s23 -; VI-NEXT: v_mov_b32_e32 v8, s24 ; VI-NEXT: v_mov_b32_e32 v9, s25 -; VI-NEXT: v_mov_b32_e32 v10, s26 ; VI-NEXT: v_mov_b32_e32 v11, s27 -; VI-NEXT: v_mov_b32_e32 v12, s28 ; VI-NEXT: v_mov_b32_e32 v13, s29 +; VI-NEXT: v_mov_b32_e32 v0, s16 +; VI-NEXT: v_mov_b32_e32 v2, s18 +; VI-NEXT: v_mov_b32_e32 v4, s20 +; VI-NEXT: v_mov_b32_e32 v6, s22 +; VI-NEXT: v_mov_b32_e32 v8, s24 +; VI-NEXT: v_mov_b32_e32 v10, s26 +; VI-NEXT: v_mov_b32_e32 v12, s28 +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB19_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_cbranch_execnz .LBB19_3 @@ -27923,580 +28250,600 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a ; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 ; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 ; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 ; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 ; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v15, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v15 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_bfe_u32 v18, v15, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc +; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15 +; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18 ; VI-NEXT: v_or_b32_e32 v34, 0x400000, v15 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 -; VI-NEXT: v_cndmask_b32_e32 v15, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; VI-NEXT: v_alignbit_b32 v15, v15, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v14 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v15, v18, v34, vcc +; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v15 +; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v14 +; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; VI-NEXT: v_bfe_u32 v18, v15, 16, 1 +; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15 ; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18 ; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v14, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v14 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v14 +; VI-NEXT: v_lshrrev_b64 v[34:35], 16, v[33:34] +; VI-NEXT: v_or_b32_e32 v33, 0x400000, v15 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 +; VI-NEXT: v_bfe_u32 v15, v14, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v35, v18, v33, vcc +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v14 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 +; VI-NEXT: v_or_b32_e32 v18, 0x400000, v14 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 -; VI-NEXT: v_cndmask_b32_e32 v14, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; VI-NEXT: v_alignbit_b32 v14, v14, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v13 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v14, v15, v18, vcc +; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v14 +; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[35:36] +; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v13 +; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; VI-NEXT: v_bfe_u32 v18, v15, 16, 1 +; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15 ; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18 ; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v13, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v13 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v13 +; VI-NEXT: v_or_b32_e32 v33, 0x400000, v15 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 +; VI-NEXT: v_bfe_u32 v15, v13, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v35, v18, v33, vcc +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 +; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 -; VI-NEXT: v_cndmask_b32_e32 v13, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; VI-NEXT: v_alignbit_b32 v13, v13, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v12 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v13, v15, v18, vcc +; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v13 +; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v12 +; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; VI-NEXT: v_bfe_u32 v15, v13, 16, 1 +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13 ; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 ; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v12, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v12 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v12 +; VI-NEXT: v_lshrrev_b64 v[35:36], 16, v[35:36] +; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 +; VI-NEXT: v_bfe_u32 v13, v12, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v36, v15, v18, vcc +; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v12 +; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 +; VI-NEXT: v_or_b32_e32 v15, 0x400000, v12 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 -; VI-NEXT: v_cndmask_b32_e32 v12, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; VI-NEXT: v_alignbit_b32 v12, v12, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v11 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v12, v13, v15, vcc +; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v12 +; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[36:37] +; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v11 +; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; VI-NEXT: v_bfe_u32 v15, v13, 16, 1 +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13 ; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 ; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v11, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v11 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v11 +; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 +; VI-NEXT: v_bfe_u32 v13, v11, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v36, v15, v18, vcc +; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11 +; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 +; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 -; VI-NEXT: v_cndmask_b32_e32 v11, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; VI-NEXT: v_alignbit_b32 v11, v11, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v10 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v11, v13, v15, vcc +; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v11 +; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; VI-NEXT: v_bfe_u32 v13, v11, 16, 1 +; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11 ; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 ; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v10, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v10 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v10 +; VI-NEXT: v_lshrrev_b64 v[36:37], 16, v[36:37] +; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 +; VI-NEXT: v_bfe_u32 v11, v10, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v37, v13, v15, vcc +; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v10 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 +; VI-NEXT: v_or_b32_e32 v13, 0x400000, v10 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 -; VI-NEXT: v_cndmask_b32_e32 v10, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; VI-NEXT: v_alignbit_b32 v10, v10, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v9 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v10, v11, v13, vcc +; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v10 +; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[37:38] +; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v9 +; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; VI-NEXT: v_bfe_u32 v13, v11, 16, 1 +; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11 ; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 ; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v9, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v9 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v9 +; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 +; VI-NEXT: v_bfe_u32 v11, v9, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v37, v13, v15, vcc +; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 +; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 -; VI-NEXT: v_cndmask_b32_e32 v9, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; VI-NEXT: v_alignbit_b32 v9, v9, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v8 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc +; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9 +; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v8 +; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 +; VI-NEXT: v_bfe_u32 v11, v9, 16, 1 +; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9 ; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 ; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v8, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v8 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v8 +; VI-NEXT: v_lshrrev_b64 v[37:38], 16, v[37:38] +; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 +; VI-NEXT: v_bfe_u32 v9, v8, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v38, v11, v13, vcc +; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9 +; VI-NEXT: v_or_b32_e32 v11, 0x400000, v8 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8 -; VI-NEXT: v_cndmask_b32_e32 v8, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; VI-NEXT: v_alignbit_b32 v8, v8, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v7 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v8, v9, v11, vcc +; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8 +; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[38:39] +; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v7 +; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 +; VI-NEXT: v_bfe_u32 v11, v9, 16, 1 +; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9 ; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 ; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v7, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v7 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v7 +; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 +; VI-NEXT: v_bfe_u32 v9, v7, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v38, v11, v13, vcc +; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9 +; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 -; VI-NEXT: v_cndmask_b32_e32 v7, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; VI-NEXT: v_alignbit_b32 v7, v7, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v6 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v7, v9, v11, vcc +; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v7 +; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v6 +; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 +; VI-NEXT: v_bfe_u32 v9, v7, 16, 1 +; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7 ; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9 ; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v6, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v6 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v6 +; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 +; VI-NEXT: v_bfe_u32 v7, v6, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v48, v9, v11, vcc +; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v6 +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7 +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v6 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; VI-NEXT: v_cndmask_b32_e32 v6, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; VI-NEXT: v_alignbit_b32 v6, v6, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v5 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v6, v7, v9, vcc +; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6 +; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[48:49] +; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v5 +; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 +; VI-NEXT: v_bfe_u32 v9, v7, 16, 1 +; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7 ; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9 ; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v5, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v5 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v5 +; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 +; VI-NEXT: v_bfe_u32 v7, v5, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v48, v9, v11, vcc +; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5 +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7 +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; VI-NEXT: v_cndmask_b32_e32 v5, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; VI-NEXT: v_alignbit_b32 v5, v5, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v4 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc +; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v5 +; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v4 +; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 +; VI-NEXT: v_bfe_u32 v7, v5, 16, 1 +; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5 ; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7 ; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v4, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v4 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v4 +; VI-NEXT: v_lshrrev_b64 v[48:49], 16, v[48:49] +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 +; VI-NEXT: v_bfe_u32 v5, v4, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v49, v7, v9, vcc +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v4 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; VI-NEXT: v_cndmask_b32_e32 v4, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; VI-NEXT: v_alignbit_b32 v4, v4, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v3 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc +; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v4 +; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[49:50] +; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v3 +; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 +; VI-NEXT: v_bfe_u32 v7, v5, 16, 1 +; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5 ; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7 ; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v3, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v3 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v3 +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v49, v7, v9, vcc +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; VI-NEXT: v_cndmask_b32_e32 v3, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; VI-NEXT: v_alignbit_b32 v3, v3, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v2 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v3 +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 ; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 ; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v2 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v2 +; VI-NEXT: v_lshrrev_b64 v[49:50], 16, v[49:50] +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v50, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: v_alignbit_b32 v2, v2, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v1 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v2 +; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[50:51] +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v1 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 ; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 ; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v1 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v50, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; VI-NEXT: v_alignbit_b32 v1, v1, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v0 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 ; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v0, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v0 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v0 +; VI-NEXT: v_lshrrev_b64 v[50:51], 16, v[50:51] +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_bfe_u32 v1, v0, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v51, v3, v5, vcc +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1 +; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; VI-NEXT: v_cndmask_b32_e32 v0, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; VI-NEXT: v_alignbit_b32 v0, v0, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v31 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v31, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v31 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v31 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31 -; VI-NEXT: v_cndmask_b32_e32 v31, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; VI-NEXT: v_alignbit_b32 v31, v31, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v30 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v30, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v30 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v30 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 -; VI-NEXT: v_cndmask_b32_e32 v30, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; VI-NEXT: v_alignbit_b32 v30, v30, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v29 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v29, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v29 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v29 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 -; VI-NEXT: v_cndmask_b32_e32 v29, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v29 -; VI-NEXT: v_alignbit_b32 v29, v29, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v28 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v28, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v28 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v28 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 -; VI-NEXT: v_cndmask_b32_e32 v28, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v28 -; VI-NEXT: v_alignbit_b32 v28, v28, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v27 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v27, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v27 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v27 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 -; VI-NEXT: v_cndmask_b32_e32 v27, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; VI-NEXT: v_alignbit_b32 v27, v27, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v26 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v26, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v26 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v26 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 -; VI-NEXT: v_cndmask_b32_e32 v26, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v26 -; VI-NEXT: v_alignbit_b32 v26, v26, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v25 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v25, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v25 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v25 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 -; VI-NEXT: v_cndmask_b32_e32 v25, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 -; VI-NEXT: v_alignbit_b32 v25, v25, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v24 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v24, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v24 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v24 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; VI-NEXT: v_cndmask_b32_e32 v24, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; VI-NEXT: v_alignbit_b32 v24, v24, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v23 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v23, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v23 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v23 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 -; VI-NEXT: v_cndmask_b32_e32 v23, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v23 -; VI-NEXT: v_alignbit_b32 v23, v23, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v22 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v22, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v22 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v22 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 -; VI-NEXT: v_cndmask_b32_e32 v22, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v22 -; VI-NEXT: v_alignbit_b32 v22, v22, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v21 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v21, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v21 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v21 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 -; VI-NEXT: v_cndmask_b32_e32 v21, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; VI-NEXT: v_alignbit_b32 v21, v21, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v20 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v20, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v20 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v20 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 -; VI-NEXT: v_cndmask_b32_e32 v20, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; VI-NEXT: v_alignbit_b32 v20, v20, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v19 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v19, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v19 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v19 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 -; VI-NEXT: v_cndmask_b32_e32 v19, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; VI-NEXT: v_alignbit_b32 v19, v19, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v32 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v32, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 -; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; VI-NEXT: v_alignbit_b32 v32, v32, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v17 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v17, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v17 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v17 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 -; VI-NEXT: v_cndmask_b32_e32 v17, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; VI-NEXT: v_alignbit_b32 v17, v17, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v16 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v16, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v16 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v16 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16 -; VI-NEXT: v_cndmask_b32_e32 v16, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; VI-NEXT: v_alignbit_b32 v16, v16, v18, 16 +; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc +; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v0 +; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[51:52] +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v31 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v31 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v51, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v30 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v30 +; VI-NEXT: v_lshrrev_b64 v[51:52], 16, v[51:52] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v52, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v29 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v29 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[30:31], 16, v[52:53] +; VI-NEXT: v_cndmask_b32_e32 v52, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v28 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v28 +; VI-NEXT: v_lshrrev_b64 v[52:53], 16, v[52:53] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v53, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v27 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v27 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[28:29], 16, v[53:54] +; VI-NEXT: v_cndmask_b32_e32 v53, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v26 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v26 +; VI-NEXT: v_lshrrev_b64 v[53:54], 16, v[53:54] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v54, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v25 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v25 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[26:27], 16, v[54:55] +; VI-NEXT: v_cndmask_b32_e32 v54, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v24 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v24 +; VI-NEXT: v_lshrrev_b64 v[38:39], 16, v[38:39] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v39, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v23 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v23 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[24:25], 16, v[39:40] +; VI-NEXT: v_cndmask_b32_e32 v39, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v22 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v22 +; VI-NEXT: v_lshrrev_b64 v[39:40], 16, v[39:40] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v40, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v21 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v21 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[22:23], 16, v[40:41] +; VI-NEXT: v_cndmask_b32_e32 v40, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v20 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v20 +; VI-NEXT: v_lshrrev_b64 v[40:41], 16, v[40:41] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v41, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v19 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v19 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v18, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v32 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v32 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v31, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v17 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v17 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[20:21], 16, v[41:42] +; VI-NEXT: v_cndmask_b32_e32 v41, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v16 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v16 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v15, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b64 v[54:55], 16, v[54:55] +; VI-NEXT: v_lshrrev_b64 v[18:19], 16, v[18:19] +; VI-NEXT: v_lshrrev_b64 v[41:42], 16, v[41:42] +; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v1 +; VI-NEXT: v_lshrrev_b64 v[32:33], 16, v[31:32] +; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[15:16] +; VI-NEXT: v_mov_b32_e32 v1, v50 +; VI-NEXT: v_mov_b32_e32 v3, v49 +; VI-NEXT: v_mov_b32_e32 v5, v48 +; VI-NEXT: v_mov_b32_e32 v7, v38 +; VI-NEXT: v_mov_b32_e32 v9, v37 +; VI-NEXT: v_mov_b32_e32 v11, v36 +; VI-NEXT: v_mov_b32_e32 v13, v35 +; VI-NEXT: v_mov_b32_e32 v15, v34 +; VI-NEXT: v_mov_b32_e32 v17, v41 +; VI-NEXT: v_mov_b32_e32 v19, v18 +; VI-NEXT: v_mov_b32_e32 v21, v40 +; VI-NEXT: v_mov_b32_e32 v23, v39 +; VI-NEXT: v_mov_b32_e32 v25, v54 +; VI-NEXT: v_mov_b32_e32 v27, v53 +; VI-NEXT: v_mov_b32_e32 v29, v52 +; VI-NEXT: v_mov_b32_e32 v31, v51 ; VI-NEXT: .LBB19_3: ; %end +; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload ; VI-NEXT: v_mov_b32_e32 v18, v32 +; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_setpc_b64 s[30:31] ; VI-NEXT: .LBB19_4: ; VI-NEXT: s_branch .LBB19_2 @@ -29161,100 +29508,26 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 -; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:156 -; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:28 -; GFX11-TRUE16-NEXT: s_clause 0x6 ; 28-byte Folded Spill -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v167, v13 :: v_dual_mov_b32 v176, v12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v177, v11 :: v_dual_mov_b32 v178, v10 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v179, v9 :: v_dual_mov_b32 v180, v8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v181, v7 :: v_dual_mov_b32 v182, v6 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v183, v5 :: v_dual_mov_b32 v168, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v169, v3 :: v_dual_mov_b32 v170, v2 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v171, v1 :: v_dual_mov_b32 v172, v0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v174, s28 :: v_dual_mov_b32 v173, s29 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, v13 :: v_dual_mov_b32 v30, v12 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, 0 ; GFX11-TRUE16-NEXT: s_and_b32 s5, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB19_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v135, s0 :: v_dual_mov_b32 v134, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v132, s2 :: v_dual_mov_b32 v129, s3 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v125, s16 :: v_dual_mov_b32 v120, s17 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v114, s18 :: v_dual_mov_b32 v107, s19 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v99, s20 :: v_dual_mov_b32 v90, s21 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v80, s22 :: v_dual_mov_b32 v69, s23 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v57, s24 :: v_dual_mov_b32 v44, s25 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, s26 :: v_dual_mov_b32 v15, s27 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 ; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB19_3 ; GFX11-TRUE16-NEXT: .LBB19_2: ; %cmp.true @@ -29265,972 +29538,674 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a ; GFX11-TRUE16-NEXT: s_and_b32 s4, s26, 0xffff0000 ; GFX11-TRUE16-NEXT: s_lshl_b32 s6, s26, 16 ; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1 +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1 ; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v1 +; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s6 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3 ; GFX11-TRUE16-NEXT: s_and_b32 s5, s25, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s7, s25, 16 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s6 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0 ; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s5 -; GFX11-TRUE16-NEXT: s_and_b32 s4, s24, 0xffff0000 +; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s25, 16 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v8 :: v_dual_add_nc_u32 v7, v7, v3 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v7, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v3 -; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s7 -; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v9, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v3 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v6, 16, 1 ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v4 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7 -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s24, 16 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v7, v2 :: v_dual_add_nc_u32 v7, v8, v5 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v9, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v4 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v7 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v6 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v6 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: s_and_b32 s4, s24, 0xffff0000 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v10, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc_lo +; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v6 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v3 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1 +; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s24, 16 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v7, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v9, v5 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v7 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v7 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v6 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v3 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v1.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 16, v2 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.h, v4.l -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s23, 0xffff0000 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v57.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s23, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s22, 0xffff0000 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v1.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s22, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v9 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v0.l +; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s21, 0xffff0000 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s21, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s21, 16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3 +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v6 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s20, 0xffff0000 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v90, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v90.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s20, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s19, 0xffff0000 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v1.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8 ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v32 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v32, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s19, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v32 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v0.l +; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s18, 0xffff0000 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v107, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v107.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s18, 16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3 +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v6 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s17, 0xffff0000 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s17, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: s_and_b32 s4, s16, 0xffff0000 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v32, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v32 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v1.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v32 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v3, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX11-TRUE16-NEXT: s_and_b32 s4, s16, 0xffff0000 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v33, v3 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v120, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v120.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v34, 16, 1 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s16, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s3, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v125, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v125.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s3 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v32, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16 +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v33, 16, 1 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s3 ; GFX11-TRUE16-NEXT: s_and_b32 s3, s2, 0xffff0000 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v35, v32 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v35, 0x40c00000, s3 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v32 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v33 +; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v35, 16, 1 ; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v34 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v1.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v32, v35 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s2 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v34 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s3 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s2 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 ; GFX11-TRUE16-NEXT: s_and_b32 s2, s1, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s2 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1 -; GFX11-TRUE16-NEXT: s_and_b32 s1, s0, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_add_f32_e64 v37, 0x40c00000, s2 +; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v32, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v134.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v167 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v167 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v167.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v176 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v176 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v176.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v177 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v177 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v177.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v178 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v178 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v178, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v179 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v179 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v179.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v180 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v180 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v180.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v181 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v181 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v181.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v182 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v182 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v182.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v183 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v183 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v183.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v168 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v168 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v168, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v168.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v169 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v169 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v169, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v169.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v170 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v170 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v170, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v170.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v171 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v171 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v171, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v171.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v172 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v172 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v172, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v172.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v173 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v173 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v37, 16, 1 +; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v33, vcc_lo +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, v36, v32 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v34, v37 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s1 +; GFX11-TRUE16-NEXT: s_and_b32 s1, s0, 0xffff0000 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v0.l +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v32 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v35, 0x40c00000, s1 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v173, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v173.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v174 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v33, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v2, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, v38, v34 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v32, v35 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v31 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v36 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v36, 0x40c00000, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v33, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v36 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v37 :: v_dual_add_nc_u32 v33, v33, v36 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v32.l +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v30 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v0 +; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v33, v33, v35 :: v_dual_add_nc_u32 v0, v0, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v33 +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v32.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v36, v37 :: v_dual_add_f32 v31, 0x40c00000, v31 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v33, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v31, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, v38, v31 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v29 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v36 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v31 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v30, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v30 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v34, v30 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_and_b32 v37, 0xffff0000, v28 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v33.l +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v30, v34, v36 :: v_dual_add_nc_u32 v33, v33, v35 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v29, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_dual_add_f32 v28, 0x40c00000, v28 :: v_dual_add_nc_u32 v35, v37, v29 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v32.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v33, v33, v36 :: v_dual_add_nc_u32 v32, v38, v34 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v29 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v27 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v35, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v28, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v28 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_add_nc_u32 v35, v35, v28 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v26 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v33.l +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX11-TRUE16-NEXT: v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_add_f32 v27, 0x40c00000, v27 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, v33, v34 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v28, v35, v36 :: v_dual_add_f32 v35, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v27, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v37, v27 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v27 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v38, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v25 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v26, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v26 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v34, v26 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_and_b32 v37, 0xffff0000, v24 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v33.l +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_add_f32 v25, 0x40c00000, v25 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v32.l +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v25, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v38, v34 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v23 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, v33, v35 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, v37, v25 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v25 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v35, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v24, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v24 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v33.l +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_and_b32 v37, 0xffff0000, v22 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, v35, v24 +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v174 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v24, v35, v36 :: v_dual_add_nc_u32 v33, v33, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v23, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v37, v23 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v23 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v38, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v21 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v22, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v22 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v34, v22 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_and_b32 v37, 0xffff0000, v20 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v33.l +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, v33, v35 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v32.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v38, v34 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v19 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v21, 16, 1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v21 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, v37, v21 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v174, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v174.h, v0.l +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v35, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v20, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v20 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_add_nc_u32 v35, v35, v20 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v33.l +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v18 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, v33, v34 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v20, v35, v36 :: v_dual_add_f32 v35, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v19, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v37, v19 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v19 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v32.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v38, v35 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v17 +; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v18, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, v39, v18 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v33.l +; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v34, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v38 :: v_dual_add_nc_u32 v33, 0x7fff, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v18 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v16 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, v36, v34 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_lshlrev_b32 v16, 16, v16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v33, v35 :: v_dual_add_f32 v33, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v36 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v17, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v33, 16, 1 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v17 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v35, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, v37, v17 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, v38, v33 +; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v16, 16, 1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v33 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 0x7fff, v37 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, v35, v16 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v48, 0x400000, v16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v32.l +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v37, v38, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v36, v39, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v35, v48, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v34.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v33.l ; GFX11-TRUE16-NEXT: .LBB19_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v125 :: v_dual_mov_b32 v5, v120 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v114 :: v_dual_mov_b32 v7, v107 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v99 :: v_dual_mov_b32 v9, v90 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v57 :: v_dual_mov_b32 v13, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v30 :: v_dual_mov_b32 v17, v173 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, v174 :: v_dual_mov_b32 v19, v171 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v172 :: v_dual_mov_b32 v21, v169 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, v170 :: v_dual_mov_b32 v23, v183 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, v168 :: v_dual_mov_b32 v25, v181 -; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0x6 ; 28-byte Folded Reload -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:280 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v135 :: v_dual_mov_b32 v1, v134 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v132 :: v_dual_mov_b32 v3, v129 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v80 :: v_dual_mov_b32 v11, v69 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v24, v182 :: v_dual_mov_b32 v27, v179 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v180 :: v_dual_mov_b32 v29, v177 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v178 :: v_dual_mov_b32 v31, v167 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v30, v176 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB19_4: -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 ; GFX11-TRUE16-NEXT: s_branch .LBB19_2 ; ; GFX11-FAKE16-LABEL: bitcast_v64bf16_to_v32i32_scalar: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 -; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:288 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:284 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:280 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:276 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:272 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:268 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:264 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:260 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:256 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:252 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:248 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:244 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:240 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:236 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:232 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:228 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:224 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:220 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:216 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:212 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:208 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:204 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:200 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:196 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:192 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:188 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:184 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:180 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:176 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:172 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:168 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:164 -; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:160 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:156 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:152 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:148 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:144 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:140 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:136 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:132 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:128 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:124 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:120 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:116 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:112 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:108 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:104 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:100 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:96 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:92 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:88 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v139, s32 offset:84 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v140, s32 offset:80 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v141, s32 offset:76 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v142, s32 offset:72 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v143, s32 offset:68 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v152, s32 offset:64 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v153, s32 offset:60 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v154, s32 offset:56 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v155, s32 offset:52 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v156, s32 offset:48 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v157, s32 offset:44 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v158, s32 offset:40 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v159, s32 offset:36 -; GFX11-FAKE16-NEXT: s_clause 0x8 ; 36-byte Folded Spill -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v168, s32 offset:32 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v169, s32 offset:28 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v170, s32 offset:24 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v171, s32 offset:20 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v172, s32 offset:16 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v173, s32 offset:12 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v174, s32 offset:8 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v175, s32 offset:4 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v184, s32 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v178, v13 :: v_dual_mov_b32 v179, v12 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v180, v11 :: v_dual_mov_b32 v181, v9 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v182, v10 :: v_dual_mov_b32 v169, v7 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v170, v8 :: v_dual_mov_b32 v177, v3 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v176, v6 :: v_dual_mov_b32 v171, v4 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v174, v5 :: v_dual_mov_b32 v173, v0 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v184, v2 :: v_dual_mov_b32 v175, v1 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v183, s28 :: v_dual_mov_b32 v172, s29 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v13 :: v_dual_mov_b32 v30, v12 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 ; GFX11-FAKE16-NEXT: s_mov_b32 s4, 0 ; GFX11-FAKE16-NEXT: s_and_b32 s5, vcc_lo, exec_lo ; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB19_4 ; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, s0 :: v_dual_mov_b32 v37, s2 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, s1 :: v_dual_mov_b32 v41, s3 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v46, s16 :: v_dual_mov_b32 v59, s18 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, s17 :: v_dual_mov_b32 v67, s19 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v76, s20 :: v_dual_mov_b32 v97, s22 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v86, s21 :: v_dual_mov_b32 v109, s23 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v122, s24 :: v_dual_mov_b32 v151, s26 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v136, s25 :: v_dual_mov_b32 v15, s27 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 ; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4 ; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB19_3 ; GFX11-FAKE16-NEXT: .LBB19_2: ; %cmp.true @@ -30238,762 +30213,674 @@ define inreg <32 x i32> @bitcast_v64bf16_to_v32i32_scalar(<64 x bfloat> inreg %a ; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s27, 16 ; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s5 ; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s26, 16 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s26, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s6 +; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s26, 16 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 ; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1 ; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s6 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1 +; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1 ; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1 -; GFX11-FAKE16-NEXT: s_lshl_b32 s7, s25, 16 +; GFX11-FAKE16-NEXT: s_and_b32 s5, s25, 0xffff0000 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0 -; GFX11-FAKE16-NEXT: s_and_b32 s5, s25, 0xffff0000 -; GFX11-FAKE16-NEXT: s_and_b32 s4, s24, 0xffff0000 ; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s5 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v183 +; GFX11-FAKE16-NEXT: s_lshl_b32 s7, s25, 16 +; GFX11-FAKE16-NEXT: s_and_b32 s4, s24, 0xffff0000 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s24, 16 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v9, v3 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v5 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v9, v3 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v6, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v7, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v7 :: v_dual_add_nc_u32 v2, 0x7fff, v2 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v5 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s7 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v3 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 +; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v6, 16, 1 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v8, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v1, 16, v0 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v3, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v10, v6 +; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v1, 16, v0 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v5, v6 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v7, v9, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s23, 16 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v0, 16, v1 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 ; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s24, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v6 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v8 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s23, 0xffff0000 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo ; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v5 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v9 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v1, v7 :: v_dual_and_b32 v1, 0xffff, v2 -; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v9, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v6 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v7, v9 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s23, 16 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v151, v0, 16, v1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6 -; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v4, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: s_and_b32 s4, s22, 0xffff0000 -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v12, 16, 1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v11, v7 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v3 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s22, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v5 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v6 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v8 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v9, v12 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v10, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v12 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s22, 16 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1 +; GFX11-FAKE16-NEXT: s_and_b32 s4, s22, 0xffff0000 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6 +; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s21, 0xffff0000 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v6, v9, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v11, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v14, v10 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v5 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v7 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v13 :: v_dual_add_nc_u32 v7, v9, v11 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v12 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v10 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s21, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v11 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v13, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v16, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s21, 16 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 +; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s20, 0xffff0000 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v7, v14 :: v_dual_add_nc_u32 v10, v10, v13 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v8 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v13 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v11 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v12, v16 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s20, 16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11 -; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v12, 16, 1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v10, v14, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s20, 16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6 +; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s19, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, v18, v12 -; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v17, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s19, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v13 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v14 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, v16, v19 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v12 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v14 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s19, 16 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 +; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s18, 0xffff0000 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v16, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, v21, v17 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v11 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v13 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v20 :: v_dual_add_nc_u32 v13, v16, v18 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v19 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v17 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s18, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v18 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v19, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v20, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v22, 16, 1 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s18, 16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v6 +; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s17, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, v17, v20 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v13, v21 :: v_dual_and_b32 v13, 0xffff, v14 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v20 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v19, v22 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s17, 16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v22 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18 -; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v19, 16, 1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v17, v21, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s17, 16 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v32, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s5 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s16, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, v24, v19 -; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v25, 16, 1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v18, v23 :: v_dual_and_b32 v17, 0xffff, v16 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s16, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v20 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v21 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, v22, v25 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v19 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v24, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_bfe_u32 v27, v23, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x7fff, v21 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v25 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s16, 16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1 +; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v32, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v6 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v33 :: v_dual_add_nc_u32 v5, v7, v32 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v0, 16, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v32 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s5 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s3, 0xffff0000 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v22, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v24, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v25, v27, v23 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v18 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v20 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v21, v26 :: v_dual_add_nc_u32 v20, v22, v24 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, 0x7fff, v25 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v23 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v26, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 ; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v24 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v28, 0x40c00000, s3 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v25, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v26, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; GFX11-FAKE16-NEXT: v_bfe_u32 v25, v28, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v33, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v5 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v34, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s3 ; GFX11-FAKE16-NEXT: s_and_b32 s3, s2, 0xffff0000 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v24, v20, v27 :: v_dual_add_nc_u32 v23, v23, v26 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v21 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v22 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v26 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, 0x7fff, v23 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v24 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, v25, v28 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s3 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v33 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v32, v33 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v34, 16, 1 ; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, 0x400000, v28 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, 0x7fff, v24 -; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v25, 16, 1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v31, 0x40c00000, s2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v23, v27, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v33, v34 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v32, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v32 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v32 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v35, vcc_lo +; GFX11-FAKE16-NEXT: v_add_f32_e64 v35, 0x40c00000, s2 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v33 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v34 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s3 +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s2, s1, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, v30, v25 -; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v31, 16, 1 ; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v29, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e64 v29, 0x40c00000, s2 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v22 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v26 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v26, 0x7fff, v27 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, v28, v31 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v25 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v30, 0x40c00000, s1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v29, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, 0x7fff, v27 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v31 -; GFX11-FAKE16-NEXT: s_and_b32 s1, s0, 0xffff0000 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v26, v28, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v30, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, v33, v29 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v24 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v26 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v27, v27, v32 :: v_dual_add_nc_u32 v26, v28, v30 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v33, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v35 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v33 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v28, 0x7fff, v31 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, 0x400000, v29 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v4, v33 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v36, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v36, 0x40c00000, s1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v34 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s2 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v36, 16, 1 +; GFX11-FAKE16-NEXT: s_and_b32 s1, s0, 0xffff0000 ; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v26, 0x7fff, v26 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v30 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v28, v31, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v29, v32, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v32 -; GFX11-FAKE16-NEXT: v_bfe_u32 v31, v34, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v26, v33, vcc_lo -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v28 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v28, v29, v32 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v178 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v30 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v30, v31, v34 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v178 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v28, 0x7fff, v28 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v33, 0x40c00000, v33 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v109, v5, 16, v7 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v30, 0x7fff, v30 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v28, v35, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v32, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v36 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v38, 0x40c00000, s0 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v32, v34 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v33 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v36 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v35 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v35, 0x40c00000, s1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v34 +; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v38, 16, 1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v33, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v29 +; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v2, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v0, 16, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v33, v35 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v36, v38 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v38 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v34 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v31 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v32 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v31, 0x40c00000, v31 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v34, 16, 1 ; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v31, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v37, v33 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v30, v36, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v179 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v35, v31 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v33 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v179 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v31 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v1, 16, v32 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v36, v34 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v31 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v30 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v31 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 ; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v180 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v36 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v34, v38, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v36, 16, 1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v35, 16, 1 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v38, 16, v180 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_add_f32 v37, 0x40c00000, v37 :: v_dual_add_nc_u32 v34, v34, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v33, v35 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v38 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v33 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v34 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v31, v35, v37 :: v_dual_add_nc_u32 v32, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v30, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v33 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v35, v36 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v29 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v30 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v38 :: v_dual_lshlrev_b32 v29, 16, v29 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v30 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v36 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v32 -; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v37, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v34, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v29, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v32, 16, v31 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v178, v31, 16, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, v36, v37 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v33, v48 :: v_dual_lshlrev_b32 v36, 16, v182 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v38 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v33, v38 :: v_dual_add_nc_u32 v32, v34, v35 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v35, v38 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v182 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v34 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v37 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, 0x7fff, v31 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v179, v32, 16, v34 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v30 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v136, v2, 16, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v36, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v36 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v36, v29 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v28 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v29 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v31, v31, v48 :: v_dual_add_nc_u32 v38, v38, v35 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v37, v36 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v181 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v38 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v38, 16, v181 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v37, 0x40c00000, v37 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v38 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v39, vcc_lo +; GFX11-FAKE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v30 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v34, v37, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v33 -; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v37, 16, 1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v48, vcc_lo -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v180, v31, 16, v33 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v35, v37 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v170 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v38 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v36, v38 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_lshlrev_b32 v36, 16, v170 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v28, 16, 1 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v33, 16, v30 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v28 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v38 :: v_dual_add_nc_u32 v33, v35, v28 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v36 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v27 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v37 -; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v36, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v182, v31, 16, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, v38, v35 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, v39, v36 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v48, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v36 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v27, 0x40c00000, v27 :: v_dual_cndmask_b32 v28, v33, v37 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, 0x7fff, v31 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff, v29 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v27, 16, 1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v34, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v32, 16, v29 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v27 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v37 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v169 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v31, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v34, v35 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v36, v27 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v26 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v28 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v32, 16, v28 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v34, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v26, 16, 1 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v39, 16, v169 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v181, v32, 16, v33 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v37, 0x40c00000, v37 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v176 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v48, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v39 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v37, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v37 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v34 -; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v36, 16, 1 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v38 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v35, v37 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v176 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v32, v36 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v25 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v36 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v37, v26 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v26 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v36 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 -; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v49, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v36 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v32, v37, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v27 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v170, v33, 16, v31 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v49, v35 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v48 :: v_dual_add_nc_u32 v33, v37, v38 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v174 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v25, 0x40c00000, v25 :: v_dual_lshlrev_b32 v36, 16, v24 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v34, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v33, 16, v27 +; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v25, 16, 1 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v35 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v36 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v33, v25 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v25 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v36, 16, 1 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v26 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v24, 16, 1 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v23 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v33, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v39, v36 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v32, 16, v26 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v35, v24 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v36 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v38 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_cndmask_b32 v34, v34, v36 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v174 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v32 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v35, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_cndmask_b32 v33, v33, v39 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v169, v31, 16, v32 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, v37, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v34 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v31, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v24 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v35, vcc_lo +; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v22 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v171 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v34, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v32, 16, v25 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v33 +; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v23, 16, 1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v35 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v38, 16, v177 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, v31, v36 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v176, v33, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v37 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v32, v23 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v24, 16, v33 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v34 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v32, 0x40c00000, v32 :: v_dual_lshlrev_b32 v37, 16, v171 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, 0x7fff, v31 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v38 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v36 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v36 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37 -; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v32, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v32 -; GFX11-FAKE16-NEXT: v_bfe_u32 v50, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v31, v31, v34 :: v_dual_add_nc_u32 v36, v37, v32 -; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v177 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v37, 0x40c00000, v37 :: v_dual_add_nc_u32 v34, v34, v35 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v23 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v22 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v36, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v32, v34 :: v_dual_add_nc_u32 v34, v35, v36 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v21 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v22, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 -; GFX11-FAKE16-NEXT: v_bfe_u32 v49, v37, 16, 1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v50, v38 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v38 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v184 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_add_f32 v21, 0x40c00000, v21 :: v_dual_add_nc_u32 v32, v32, v22 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v34, v34, v48 :: v_dual_add_nc_u32 v35, v49, v37 +; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v21, 16, 1 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v21 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v23 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v48, v21 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v32, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v39, v35 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v20 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v184 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_cndmask_b32 v21, v36, v37 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v38 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v37 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v37, 0x40c00000, v50 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31 +; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v20, 16, 1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v39, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v33, 16, v23 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v34, 16, v22 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v36 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v38, 0x40c00000, v48 :: v_dual_cndmask_b32 v35, v35, v49 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v36 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v34 -; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v37, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff, v36 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v174, v33, 16, v31 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v171, v32, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, v48, v37 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v175 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v175 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v39, v39, v38 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v177, v35, 16, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, 0x7fff, v31 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v37 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v34, 0x40c00000, v34 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v39 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v38 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v37, v20 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v19 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v32, 16, v21 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v35 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v20 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v34, 0x40c00000, v34 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v36 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v33, v35 :: v_dual_and_b32 v33, 0xffff0000, v18 +; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v19, 16, 1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v34, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_lshlrev_b32 v18, 16, v18 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v38, v19 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_add_nc_u32 v35, v35, v34 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v19 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v34, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v31, v35, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v173 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v173 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v33 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_cndmask_b32 v32, v32, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v37, v33 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, v39, v34 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v34 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_nc_u32 v37, v37, v33 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v36, v38, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, 0x7fff, v37 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v38, v38, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v122, v3, 16, v6 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v37, v39, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v37 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v33 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v18 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v35, v39, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v18, 16, 1 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, 0x7fff, v38 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v48 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v36, v49 :: v_dual_lshlrev_b32 v48, 16, v183 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v38 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v48, 0x40c00000, v48 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v37, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v172 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v39, 16, v172 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v36, v38 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v55, 0x400000, v48 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v18 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v36, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v17 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v16 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v17, 0x40c00000, v17 ; GFX11-FAKE16-NEXT: v_add_f32_e32 v37, 0x40c00000, v37 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v39, 0x40c00000, v39 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v34 -; GFX11-FAKE16-NEXT: v_bfe_u32 v50, v37, 16, 1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v39, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v49, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v39 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v50, 0x40c00000, v51 :: v_dual_add_nc_u32 v49, v50, v37 -; GFX11-FAKE16-NEXT: v_bfe_u32 v51, v48, 16, 1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v38, v38, v39 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v53, 0x400000, v37 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v35, v38, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v49, 0x7fff, v49 -; GFX11-FAKE16-NEXT: v_bfe_u32 v52, v50, 16, 1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v51, v51, v48 +; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v17, 16, 1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v17 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v38, v39, v36 +; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v37, 16, 1 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v17 +; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v16, 16, 1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v51, 0x400000, v37 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v38, 0x7fff, v38 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v36 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v35 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v52, v52, v50 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v38, v38, v54 :: v_dual_add_nc_u32 v51, 0x7fff, v51 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v39, 0x7fff, v52 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v52, 0x400000, v50 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v38 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v51, v55, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v39, v39, v37 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v36 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v48, v48, v16 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v39, 0x7fff, v39 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v35, v50, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v184, v32, 16, v31 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v175, v33, 16, v34 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff, v38 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v48 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v49, v53, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v173, v35, 16, v36 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v97, v8, 16, v10 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff, v48 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v37 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v39, v52, vcc_lo -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v86, v9, 16, v12 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v76, v11, 16, v13 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v67, v14, 16, v17 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v172, v37, 16, v38 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v39 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v59, v16, 16, v19 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v52, v18, 16, v20 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v46, v21, 16, v23 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v41, v22, 16, v25 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v183, v39, 16, v48 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v37, v24, 16, v27 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v34, v26, 16, v28 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v32, v29, 16, v30 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v48 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v16 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v39, v51, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v18 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v38, v49, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v32, 16, v20 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v34, 16, v19 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v33, 16, v18 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v36 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v35, v48, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v37 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v36, 16, v17 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff, v35 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v16, 16, v35 ; GFX11-FAKE16-NEXT: .LBB19_3: ; %end -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, v41 :: v_dual_mov_b32 v4, v46 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, v59 :: v_dual_mov_b32 v9, v86 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v7, v67 :: v_dual_mov_b32 v8, v76 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, v97 :: v_dual_mov_b32 v13, v136 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v11, v109 :: v_dual_mov_b32 v12, v122 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, v151 :: v_dual_mov_b32 v17, v172 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, v173 :: v_dual_mov_b32 v19, v175 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v20, v184 :: v_dual_mov_b32 v23, v174 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v22, v171 :: v_dual_mov_b32 v25, v169 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v26, v170 :: v_dual_mov_b32 v29, v180 -; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-FAKE16-NEXT: scratch_load_b32 v184, off, s32 -; GFX11-FAKE16-NEXT: scratch_load_b32 v175, off, s32 offset:4 -; GFX11-FAKE16-NEXT: scratch_load_b32 v174, off, s32 offset:8 -; GFX11-FAKE16-NEXT: scratch_load_b32 v173, off, s32 offset:12 -; GFX11-FAKE16-NEXT: scratch_load_b32 v172, off, s32 offset:16 -; GFX11-FAKE16-NEXT: scratch_load_b32 v171, off, s32 offset:20 -; GFX11-FAKE16-NEXT: scratch_load_b32 v170, off, s32 offset:24 -; GFX11-FAKE16-NEXT: scratch_load_b32 v169, off, s32 offset:28 -; GFX11-FAKE16-NEXT: scratch_load_b32 v168, off, s32 offset:32 -; GFX11-FAKE16-NEXT: scratch_load_b32 v159, off, s32 offset:36 -; GFX11-FAKE16-NEXT: scratch_load_b32 v158, off, s32 offset:40 -; GFX11-FAKE16-NEXT: scratch_load_b32 v157, off, s32 offset:44 -; GFX11-FAKE16-NEXT: scratch_load_b32 v156, off, s32 offset:48 -; GFX11-FAKE16-NEXT: scratch_load_b32 v155, off, s32 offset:52 -; GFX11-FAKE16-NEXT: scratch_load_b32 v154, off, s32 offset:56 -; GFX11-FAKE16-NEXT: scratch_load_b32 v153, off, s32 offset:60 -; GFX11-FAKE16-NEXT: scratch_load_b32 v152, off, s32 offset:64 -; GFX11-FAKE16-NEXT: scratch_load_b32 v143, off, s32 offset:68 -; GFX11-FAKE16-NEXT: scratch_load_b32 v142, off, s32 offset:72 -; GFX11-FAKE16-NEXT: scratch_load_b32 v141, off, s32 offset:76 -; GFX11-FAKE16-NEXT: scratch_load_b32 v140, off, s32 offset:80 -; GFX11-FAKE16-NEXT: scratch_load_b32 v139, off, s32 offset:84 -; GFX11-FAKE16-NEXT: scratch_load_b32 v138, off, s32 offset:88 -; GFX11-FAKE16-NEXT: scratch_load_b32 v137, off, s32 offset:92 -; GFX11-FAKE16-NEXT: scratch_load_b32 v136, off, s32 offset:96 -; GFX11-FAKE16-NEXT: scratch_load_b32 v127, off, s32 offset:100 -; GFX11-FAKE16-NEXT: scratch_load_b32 v126, off, s32 offset:104 -; GFX11-FAKE16-NEXT: scratch_load_b32 v125, off, s32 offset:108 -; GFX11-FAKE16-NEXT: scratch_load_b32 v124, off, s32 offset:112 -; GFX11-FAKE16-NEXT: scratch_load_b32 v123, off, s32 offset:116 -; GFX11-FAKE16-NEXT: scratch_load_b32 v122, off, s32 offset:120 -; GFX11-FAKE16-NEXT: scratch_load_b32 v121, off, s32 offset:124 -; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-FAKE16-NEXT: scratch_load_b32 v120, off, s32 offset:128 -; GFX11-FAKE16-NEXT: scratch_load_b32 v111, off, s32 offset:132 -; GFX11-FAKE16-NEXT: scratch_load_b32 v110, off, s32 offset:136 -; GFX11-FAKE16-NEXT: scratch_load_b32 v109, off, s32 offset:140 -; GFX11-FAKE16-NEXT: scratch_load_b32 v108, off, s32 offset:144 -; GFX11-FAKE16-NEXT: scratch_load_b32 v107, off, s32 offset:148 -; GFX11-FAKE16-NEXT: scratch_load_b32 v106, off, s32 offset:152 -; GFX11-FAKE16-NEXT: scratch_load_b32 v105, off, s32 offset:156 -; GFX11-FAKE16-NEXT: scratch_load_b32 v104, off, s32 offset:160 -; GFX11-FAKE16-NEXT: scratch_load_b32 v95, off, s32 offset:164 -; GFX11-FAKE16-NEXT: scratch_load_b32 v94, off, s32 offset:168 -; GFX11-FAKE16-NEXT: scratch_load_b32 v93, off, s32 offset:172 -; GFX11-FAKE16-NEXT: scratch_load_b32 v92, off, s32 offset:176 -; GFX11-FAKE16-NEXT: scratch_load_b32 v91, off, s32 offset:180 -; GFX11-FAKE16-NEXT: scratch_load_b32 v90, off, s32 offset:184 -; GFX11-FAKE16-NEXT: scratch_load_b32 v89, off, s32 offset:188 -; GFX11-FAKE16-NEXT: scratch_load_b32 v88, off, s32 offset:192 -; GFX11-FAKE16-NEXT: scratch_load_b32 v79, off, s32 offset:196 -; GFX11-FAKE16-NEXT: scratch_load_b32 v78, off, s32 offset:200 -; GFX11-FAKE16-NEXT: scratch_load_b32 v77, off, s32 offset:204 -; GFX11-FAKE16-NEXT: scratch_load_b32 v76, off, s32 offset:208 -; GFX11-FAKE16-NEXT: scratch_load_b32 v75, off, s32 offset:212 -; GFX11-FAKE16-NEXT: scratch_load_b32 v74, off, s32 offset:216 -; GFX11-FAKE16-NEXT: scratch_load_b32 v73, off, s32 offset:220 -; GFX11-FAKE16-NEXT: scratch_load_b32 v72, off, s32 offset:224 -; GFX11-FAKE16-NEXT: scratch_load_b32 v63, off, s32 offset:228 -; GFX11-FAKE16-NEXT: scratch_load_b32 v62, off, s32 offset:232 -; GFX11-FAKE16-NEXT: scratch_load_b32 v61, off, s32 offset:236 -; GFX11-FAKE16-NEXT: scratch_load_b32 v60, off, s32 offset:240 -; GFX11-FAKE16-NEXT: scratch_load_b32 v59, off, s32 offset:244 -; GFX11-FAKE16-NEXT: scratch_load_b32 v58, off, s32 offset:248 -; GFX11-FAKE16-NEXT: scratch_load_b32 v57, off, s32 offset:252 -; GFX11-FAKE16-NEXT: s_clause 0x8 ; 36-byte Folded Reload -; GFX11-FAKE16-NEXT: scratch_load_b32 v56, off, s32 offset:256 -; GFX11-FAKE16-NEXT: scratch_load_b32 v47, off, s32 offset:260 -; GFX11-FAKE16-NEXT: scratch_load_b32 v46, off, s32 offset:264 -; GFX11-FAKE16-NEXT: scratch_load_b32 v45, off, s32 offset:268 -; GFX11-FAKE16-NEXT: scratch_load_b32 v44, off, s32 offset:272 -; GFX11-FAKE16-NEXT: scratch_load_b32 v43, off, s32 offset:276 -; GFX11-FAKE16-NEXT: scratch_load_b32 v42, off, s32 offset:280 -; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s32 offset:284 -; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 offset:288 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, v32 :: v_dual_mov_b32 v1, v34 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, v37 :: v_dual_mov_b32 v5, v52 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, v183 :: v_dual_mov_b32 v21, v177 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v24, v176 :: v_dual_mov_b32 v27, v181 -; GFX11-FAKE16-NEXT: v_mov_b32_e32 v28, v182 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v30, v179 :: v_dual_mov_b32 v31, v178 -; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-FAKE16-NEXT: .LBB19_4: -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr15 ; GFX11-FAKE16-NEXT: s_branch .LBB19_2 %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -31981,20 +31868,48 @@ define inreg <64 x half> @bitcast_v32i32_to_v64f16_scalar(<32 x i32> inreg %a, i ; SI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] +; SI-NEXT: v_mov_b32_e32 v20, s16 +; SI-NEXT: v_readfirstlane_b32 s40, v20 +; SI-NEXT: v_mov_b32_e32 v20, s17 +; SI-NEXT: v_readfirstlane_b32 s41, v20 +; SI-NEXT: v_mov_b32_e32 v20, s18 +; SI-NEXT: v_readfirstlane_b32 s42, v20 +; SI-NEXT: v_mov_b32_e32 v20, s19 +; SI-NEXT: v_readfirstlane_b32 s43, v20 +; SI-NEXT: v_mov_b32_e32 v20, s20 +; SI-NEXT: v_readfirstlane_b32 s44, v20 +; SI-NEXT: v_mov_b32_e32 v20, s21 +; SI-NEXT: v_readfirstlane_b32 s45, v20 +; SI-NEXT: v_mov_b32_e32 v20, s22 +; SI-NEXT: v_readfirstlane_b32 s46, v20 +; SI-NEXT: v_mov_b32_e32 v20, s23 +; SI-NEXT: v_readfirstlane_b32 s47, v20 +; SI-NEXT: v_mov_b32_e32 v20, s24 +; SI-NEXT: v_readfirstlane_b32 s24, v20 +; SI-NEXT: v_mov_b32_e32 v20, s25 +; SI-NEXT: v_readfirstlane_b32 s25, v20 +; SI-NEXT: v_mov_b32_e32 v20, s26 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_writelane_b32 v63, s30, 0 +; SI-NEXT: v_readfirstlane_b32 s26, v20 +; SI-NEXT: v_mov_b32_e32 v20, s27 ; SI-NEXT: v_writelane_b32 v63, s31, 1 +; SI-NEXT: v_readfirstlane_b32 s27, v20 +; SI-NEXT: v_mov_b32_e32 v20, s28 ; SI-NEXT: v_writelane_b32 v63, s34, 2 +; SI-NEXT: v_readfirstlane_b32 s28, v20 +; SI-NEXT: v_mov_b32_e32 v20, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; SI-NEXT: v_writelane_b32 v63, s35, 3 -; SI-NEXT: v_readfirstlane_b32 s47, v1 -; SI-NEXT: v_readfirstlane_b32 s46, v2 -; SI-NEXT: v_readfirstlane_b32 s45, v3 -; SI-NEXT: v_readfirstlane_b32 s44, v4 -; SI-NEXT: v_readfirstlane_b32 s43, v5 -; SI-NEXT: v_readfirstlane_b32 s42, v6 -; SI-NEXT: v_readfirstlane_b32 s41, v7 -; SI-NEXT: v_readfirstlane_b32 s40, v8 +; SI-NEXT: v_readfirstlane_b32 s29, v20 +; SI-NEXT: v_readfirstlane_b32 s23, v1 +; SI-NEXT: v_readfirstlane_b32 s22, v2 +; SI-NEXT: v_readfirstlane_b32 s21, v3 +; SI-NEXT: v_readfirstlane_b32 s20, v4 +; SI-NEXT: v_readfirstlane_b32 s19, v5 +; SI-NEXT: v_readfirstlane_b32 s18, v6 +; SI-NEXT: v_readfirstlane_b32 s17, v7 +; SI-NEXT: v_readfirstlane_b32 s16, v8 ; SI-NEXT: v_readfirstlane_b32 s15, v9 ; SI-NEXT: v_readfirstlane_b32 s14, v10 ; SI-NEXT: v_readfirstlane_b32 s13, v11 @@ -32047,21 +31962,21 @@ define inreg <64 x half> @bitcast_v32i32_to_v64f16_scalar(<32 x i32> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v15, s4 ; SI-NEXT: s_lshr_b32 s4, s15, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v17, s4 -; SI-NEXT: s_lshr_b32 s4, s40, 16 +; SI-NEXT: s_lshr_b32 s4, s16, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v19, s4 -; SI-NEXT: s_lshr_b32 s4, s41, 16 +; SI-NEXT: s_lshr_b32 s4, s17, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v21, s4 -; SI-NEXT: s_lshr_b32 s4, s42, 16 +; SI-NEXT: s_lshr_b32 s4, s18, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v23, s4 -; SI-NEXT: s_lshr_b32 s4, s43, 16 +; SI-NEXT: s_lshr_b32 s4, s19, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v26, s4 -; SI-NEXT: s_lshr_b32 s4, s44, 16 +; SI-NEXT: s_lshr_b32 s4, s20, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v28, s4 -; SI-NEXT: s_lshr_b32 s4, s45, 16 +; SI-NEXT: s_lshr_b32 s4, s21, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v30, s4 -; SI-NEXT: s_lshr_b32 s4, s46, 16 +; SI-NEXT: s_lshr_b32 s4, s22, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v32, s4 -; SI-NEXT: s_lshr_b32 s4, s47, 16 +; SI-NEXT: s_lshr_b32 s4, s23, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v34, s4 ; SI-NEXT: s_lshr_b32 s4, s29, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v36, s4 @@ -32075,21 +31990,21 @@ define inreg <64 x half> @bitcast_v32i32_to_v64f16_scalar(<32 x i32> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v53, s4 ; SI-NEXT: s_lshr_b32 s4, s24, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v55, s4 -; SI-NEXT: s_lshr_b32 s4, s23, 16 +; SI-NEXT: s_lshr_b32 s4, s47, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v41, s4 -; SI-NEXT: s_lshr_b32 s4, s22, 16 +; SI-NEXT: s_lshr_b32 s4, s46, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v43, s4 -; SI-NEXT: s_lshr_b32 s4, s21, 16 +; SI-NEXT: s_lshr_b32 s4, s45, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v45, s4 -; SI-NEXT: s_lshr_b32 s4, s20, 16 +; SI-NEXT: s_lshr_b32 s4, s44, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v47, s4 -; SI-NEXT: s_lshr_b32 s4, s19, 16 +; SI-NEXT: s_lshr_b32 s4, s43, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v57, s4 -; SI-NEXT: s_lshr_b32 s4, s18, 16 +; SI-NEXT: s_lshr_b32 s4, s42, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v58, s4 -; SI-NEXT: s_lshr_b32 s4, s17, 16 +; SI-NEXT: s_lshr_b32 s4, s41, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v59, s4 -; SI-NEXT: s_lshr_b32 s4, s16, 16 +; SI-NEXT: s_lshr_b32 s4, s40, 16 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; SI-NEXT: v_cvt_f32_f16_e32 v61, s4 ; SI-NEXT: v_cvt_f32_f16_e32 v8, s7 @@ -32100,29 +32015,29 @@ define inreg <64 x half> @bitcast_v32i32_to_v64f16_scalar(<32 x i32> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v18, s13 ; SI-NEXT: v_cvt_f32_f16_e32 v20, s14 ; SI-NEXT: v_cvt_f32_f16_e32 v22, s15 -; SI-NEXT: v_cvt_f32_f16_e32 v24, s40 -; SI-NEXT: v_cvt_f32_f16_e32 v25, s41 -; SI-NEXT: v_cvt_f32_f16_e32 v27, s42 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s43 -; SI-NEXT: v_cvt_f32_f16_e32 v31, s44 -; SI-NEXT: v_cvt_f32_f16_e32 v33, s45 -; SI-NEXT: v_cvt_f32_f16_e32 v35, s46 -; SI-NEXT: v_cvt_f32_f16_e32 v37, s47 +; SI-NEXT: v_cvt_f32_f16_e32 v24, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v25, s17 +; SI-NEXT: v_cvt_f32_f16_e32 v27, s18 +; SI-NEXT: v_cvt_f32_f16_e32 v29, s19 +; SI-NEXT: v_cvt_f32_f16_e32 v31, s20 +; SI-NEXT: v_cvt_f32_f16_e32 v33, s21 +; SI-NEXT: v_cvt_f32_f16_e32 v35, s22 +; SI-NEXT: v_cvt_f32_f16_e32 v37, s23 ; SI-NEXT: v_cvt_f32_f16_e32 v39, s29 ; SI-NEXT: v_cvt_f32_f16_e32 v49, s28 ; SI-NEXT: v_cvt_f32_f16_e32 v50, s27 ; SI-NEXT: v_cvt_f32_f16_e32 v52, s26 ; SI-NEXT: v_cvt_f32_f16_e32 v54, s25 ; SI-NEXT: v_cvt_f32_f16_e32 v40, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v42, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v44, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v46, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v56, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v60, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v62, s18 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v1, s17 -; SI-NEXT: v_cvt_f32_f16_e32 v2, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v42, s47 +; SI-NEXT: v_cvt_f32_f16_e32 v44, s46 +; SI-NEXT: v_cvt_f32_f16_e32 v46, s45 +; SI-NEXT: v_cvt_f32_f16_e32 v56, s44 +; SI-NEXT: v_cvt_f32_f16_e32 v60, s43 +; SI-NEXT: v_cvt_f32_f16_e32 v62, s42 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, s41 +; SI-NEXT: v_cvt_f32_f16_e32 v2, s40 ; SI-NEXT: s_cbranch_execnz .LBB21_3 ; SI-NEXT: .LBB21_2: ; %cmp.true ; SI-NEXT: s_add_i32 s9, s9, 3 @@ -32130,31 +32045,31 @@ define inreg <64 x half> @bitcast_v32i32_to_v64f16_scalar(<32 x i32> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v3, s35 ; SI-NEXT: s_add_i32 s6, s6, 3 ; SI-NEXT: s_lshr_b32 s34, s6, 16 -; SI-NEXT: s_add_i32 s16, s16, 3 +; SI-NEXT: s_add_i32 s40, s40, 3 ; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f32_f16_e32 v3, s34 -; SI-NEXT: s_add_i32 s17, s17, 3 -; SI-NEXT: s_add_i32 s18, s18, 3 -; SI-NEXT: s_add_i32 s19, s19, 3 -; SI-NEXT: s_add_i32 s20, s20, 3 -; SI-NEXT: s_add_i32 s21, s21, 3 -; SI-NEXT: s_add_i32 s22, s22, 3 -; SI-NEXT: s_add_i32 s23, s23, 3 +; SI-NEXT: s_add_i32 s41, s41, 3 +; SI-NEXT: s_add_i32 s42, s42, 3 +; SI-NEXT: s_add_i32 s43, s43, 3 +; SI-NEXT: s_add_i32 s44, s44, 3 +; SI-NEXT: s_add_i32 s45, s45, 3 +; SI-NEXT: s_add_i32 s46, s46, 3 +; SI-NEXT: s_add_i32 s47, s47, 3 ; SI-NEXT: s_add_i32 s24, s24, 3 ; SI-NEXT: s_add_i32 s25, s25, 3 ; SI-NEXT: s_add_i32 s26, s26, 3 ; SI-NEXT: s_add_i32 s27, s27, 3 ; SI-NEXT: s_add_i32 s28, s28, 3 ; SI-NEXT: s_add_i32 s29, s29, 3 -; SI-NEXT: s_add_i32 s47, s47, 3 -; SI-NEXT: s_add_i32 s46, s46, 3 -; SI-NEXT: s_add_i32 s45, s45, 3 -; SI-NEXT: s_add_i32 s44, s44, 3 -; SI-NEXT: s_add_i32 s43, s43, 3 -; SI-NEXT: s_add_i32 s42, s42, 3 -; SI-NEXT: s_add_i32 s41, s41, 3 -; SI-NEXT: s_add_i32 s40, s40, 3 +; SI-NEXT: s_add_i32 s23, s23, 3 +; SI-NEXT: s_add_i32 s22, s22, 3 +; SI-NEXT: s_add_i32 s21, s21, 3 +; SI-NEXT: s_add_i32 s20, s20, 3 +; SI-NEXT: s_add_i32 s19, s19, 3 +; SI-NEXT: s_add_i32 s18, s18, 3 +; SI-NEXT: s_add_i32 s17, s17, 3 +; SI-NEXT: s_add_i32 s16, s16, 3 ; SI-NEXT: s_add_i32 s15, s15, 3 ; SI-NEXT: s_add_i32 s14, s14, 3 ; SI-NEXT: s_add_i32 s13, s13, 3 @@ -32163,28 +32078,28 @@ define inreg <64 x half> @bitcast_v32i32_to_v64f16_scalar(<32 x i32> inreg %a, i ; SI-NEXT: s_add_i32 s10, s10, 3 ; SI-NEXT: s_add_i32 s8, s8, 3 ; SI-NEXT: s_add_i32 s7, s7, 3 -; SI-NEXT: s_lshr_b32 s4, s16, 16 -; SI-NEXT: s_lshr_b32 s5, s17, 16 -; SI-NEXT: s_lshr_b32 s56, s18, 16 -; SI-NEXT: s_lshr_b32 s57, s19, 16 -; SI-NEXT: s_lshr_b32 s58, s20, 16 -; SI-NEXT: s_lshr_b32 s59, s21, 16 -; SI-NEXT: s_lshr_b32 s60, s22, 16 -; SI-NEXT: s_lshr_b32 s61, s23, 16 +; SI-NEXT: s_lshr_b32 s4, s40, 16 +; SI-NEXT: s_lshr_b32 s5, s41, 16 +; SI-NEXT: s_lshr_b32 s56, s42, 16 +; SI-NEXT: s_lshr_b32 s57, s43, 16 +; SI-NEXT: s_lshr_b32 s58, s44, 16 +; SI-NEXT: s_lshr_b32 s59, s45, 16 +; SI-NEXT: s_lshr_b32 s60, s46, 16 +; SI-NEXT: s_lshr_b32 s61, s47, 16 ; SI-NEXT: s_lshr_b32 s62, s24, 16 ; SI-NEXT: s_lshr_b32 s63, s25, 16 ; SI-NEXT: s_lshr_b32 s72, s26, 16 ; SI-NEXT: s_lshr_b32 s73, s27, 16 ; SI-NEXT: s_lshr_b32 s74, s28, 16 ; SI-NEXT: s_lshr_b32 s75, s29, 16 -; SI-NEXT: s_lshr_b32 s76, s47, 16 -; SI-NEXT: s_lshr_b32 s77, s46, 16 -; SI-NEXT: s_lshr_b32 s78, s45, 16 -; SI-NEXT: s_lshr_b32 s79, s44, 16 -; SI-NEXT: s_lshr_b32 s88, s43, 16 -; SI-NEXT: s_lshr_b32 s89, s42, 16 -; SI-NEXT: s_lshr_b32 s90, s41, 16 -; SI-NEXT: s_lshr_b32 s91, s40, 16 +; SI-NEXT: s_lshr_b32 s76, s23, 16 +; SI-NEXT: s_lshr_b32 s77, s22, 16 +; SI-NEXT: s_lshr_b32 s78, s21, 16 +; SI-NEXT: s_lshr_b32 s79, s20, 16 +; SI-NEXT: s_lshr_b32 s88, s19, 16 +; SI-NEXT: s_lshr_b32 s89, s18, 16 +; SI-NEXT: s_lshr_b32 s90, s17, 16 +; SI-NEXT: s_lshr_b32 s91, s16, 16 ; SI-NEXT: s_lshr_b32 s92, s15, 16 ; SI-NEXT: s_lshr_b32 s93, s14, 16 ; SI-NEXT: s_lshr_b32 s94, s13, 16 @@ -32203,28 +32118,28 @@ define inreg <64 x half> @bitcast_v32i32_to_v64f16_scalar(<32 x i32> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v18, s13 ; SI-NEXT: v_cvt_f32_f16_e32 v20, s14 ; SI-NEXT: v_cvt_f32_f16_e32 v22, s15 -; SI-NEXT: v_cvt_f32_f16_e32 v24, s40 -; SI-NEXT: v_cvt_f32_f16_e32 v25, s41 -; SI-NEXT: v_cvt_f32_f16_e32 v27, s42 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s43 -; SI-NEXT: v_cvt_f32_f16_e32 v31, s44 -; SI-NEXT: v_cvt_f32_f16_e32 v33, s45 -; SI-NEXT: v_cvt_f32_f16_e32 v35, s46 -; SI-NEXT: v_cvt_f32_f16_e32 v37, s47 +; SI-NEXT: v_cvt_f32_f16_e32 v24, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v25, s17 +; SI-NEXT: v_cvt_f32_f16_e32 v27, s18 +; SI-NEXT: v_cvt_f32_f16_e32 v29, s19 +; SI-NEXT: v_cvt_f32_f16_e32 v31, s20 +; SI-NEXT: v_cvt_f32_f16_e32 v33, s21 +; SI-NEXT: v_cvt_f32_f16_e32 v35, s22 +; SI-NEXT: v_cvt_f32_f16_e32 v37, s23 ; SI-NEXT: v_cvt_f32_f16_e32 v39, s29 ; SI-NEXT: v_cvt_f32_f16_e32 v49, s28 ; SI-NEXT: v_cvt_f32_f16_e32 v50, s27 ; SI-NEXT: v_cvt_f32_f16_e32 v52, s26 ; SI-NEXT: v_cvt_f32_f16_e32 v54, s25 ; SI-NEXT: v_cvt_f32_f16_e32 v40, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v42, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v44, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v46, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v56, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v60, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v62, s18 -; SI-NEXT: v_cvt_f32_f16_e32 v1, s17 -; SI-NEXT: v_cvt_f32_f16_e32 v2, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v42, s47 +; SI-NEXT: v_cvt_f32_f16_e32 v44, s46 +; SI-NEXT: v_cvt_f32_f16_e32 v46, s45 +; SI-NEXT: v_cvt_f32_f16_e32 v56, s44 +; SI-NEXT: v_cvt_f32_f16_e32 v60, s43 +; SI-NEXT: v_cvt_f32_f16_e32 v62, s42 +; SI-NEXT: v_cvt_f32_f16_e32 v1, s41 +; SI-NEXT: v_cvt_f32_f16_e32 v2, s40 ; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f32_f16_e32 v3, s31 @@ -34712,252 +34627,80 @@ define inreg <32 x i32> @bitcast_v64f16_to_v32i32_scalar(<64 x half> inreg %a, i ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292 -; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288 -; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284 -; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280 -; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276 -; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272 -; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268 -; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264 -; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260 -; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256 -; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252 -; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248 -; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244 -; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240 -; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236 -; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232 -; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228 -; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224 -; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220 -; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216 -; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212 -; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208 -; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204 -; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200 -; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196 -; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192 -; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188 -; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184 -; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180 -; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176 -; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172 -; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164 -; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160 -; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156 -; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152 -; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148 -; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144 -; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140 -; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136 -; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132 -; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128 -; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124 -; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120 -; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116 -; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112 -; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108 -; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104 -; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100 -; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96 -; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92 -; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88 -; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84 -; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80 -; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76 -; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72 -; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68 -; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64 -; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60 -; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56 -; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52 -; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48 -; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44 -; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40 -; GFX11-NEXT: s_clause 0x9 ; 40-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36 -; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32 -; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28 -; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24 -; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20 -; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16 -; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12 -; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8 -; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4 -; GFX11-NEXT: scratch_store_b32 off, v185, s32 -; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12 -; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10 -; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8 -; GFX11-NEXT: v_dual_mov_b32 v182, v7 :: v_dual_mov_b32 v183, v6 -; GFX11-NEXT: v_dual_mov_b32 v170, v5 :: v_dual_mov_b32 v171, v4 -; GFX11-NEXT: v_dual_mov_b32 v172, v3 :: v_dual_mov_b32 v173, v2 -; GFX11-NEXT: v_dual_mov_b32 v174, v1 :: v_dual_mov_b32 v175, v0 -; GFX11-NEXT: v_dual_mov_b32 v184, s28 :: v_dual_mov_b32 v185, s29 +; GFX11-NEXT: v_dual_mov_b32 v31, v13 :: v_dual_mov_b32 v30, v12 +; GFX11-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 +; GFX11-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 ; GFX11-NEXT: s_mov_b32 s4, 0 ; GFX11-NEXT: s_and_b32 s5, vcc_lo, exec_lo ; GFX11-NEXT: s_cbranch_scc0 .LBB23_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: v_dual_mov_b32 v47, s0 :: v_dual_mov_b32 v52, s2 -; GFX11-NEXT: v_dual_mov_b32 v49, s1 :: v_dual_mov_b32 v56, s3 -; GFX11-NEXT: v_dual_mov_b32 v61, s16 :: v_dual_mov_b32 v74, s18 -; GFX11-NEXT: v_dual_mov_b32 v67, s17 :: v_dual_mov_b32 v82, s19 -; GFX11-NEXT: v_dual_mov_b32 v91, s20 :: v_dual_mov_b32 v112, s22 -; GFX11-NEXT: v_dual_mov_b32 v101, s21 :: v_dual_mov_b32 v124, s23 -; GFX11-NEXT: v_dual_mov_b32 v137, s24 :: v_dual_mov_b32 v14, s26 -; GFX11-NEXT: v_dual_mov_b32 v151, s25 :: v_dual_mov_b32 v30, s27 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 +; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 +; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 +; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 +; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 +; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4 ; GFX11-NEXT: s_cbranch_vccnz .LBB23_3 ; GFX11-NEXT: .LBB23_2: ; %cmp.true -; GFX11-NEXT: v_pk_add_f16 v30, 0x200, s27 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s27 op_sel_hi:[0,1] ; GFX11-NEXT: v_pk_add_f16 v14, 0x200, s26 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v176, 0x200, v176 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v177, 0x200, v177 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v178, 0x200, v178 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v179, 0x200, v179 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v180, 0x200, v180 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v181, 0x200, v181 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v182, 0x200, v182 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v183, 0x200, v183 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v170, 0x200, v170 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v171, 0x200, v171 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v172, 0x200, v172 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v173, 0x200, v173 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v174, 0x200, v174 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v175, 0x200, v175 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v185, 0x200, v185 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v184, 0x200, v184 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v151, 0x200, s25 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v137, 0x200, s24 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v124, 0x200, s23 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v112, 0x200, s22 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v101, 0x200, s21 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v91, 0x200, s20 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v82, 0x200, s19 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v74, 0x200, s18 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v67, 0x200, s17 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v61, 0x200, s16 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v56, 0x200, s3 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v52, 0x200, s2 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v49, 0x200, s1 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v47, 0x200, s0 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s25 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s24 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s23 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s22 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s21 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v31, 0x200, v31 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v30, 0x200, v30 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1] ; GFX11-NEXT: .LBB23_3: ; %end -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_dual_mov_b32 v0, v47 :: v_dual_mov_b32 v1, v49 -; GFX11-NEXT: v_dual_mov_b32 v3, v56 :: v_dual_mov_b32 v4, v61 -; GFX11-NEXT: v_dual_mov_b32 v6, v74 :: v_dual_mov_b32 v9, v101 -; GFX11-NEXT: v_dual_mov_b32 v7, v82 :: v_dual_mov_b32 v8, v91 -; GFX11-NEXT: v_dual_mov_b32 v11, v124 :: v_dual_mov_b32 v12, v137 -; GFX11-NEXT: v_dual_mov_b32 v15, v30 :: v_dual_mov_b32 v16, v184 -; GFX11-NEXT: v_dual_mov_b32 v17, v185 :: v_dual_mov_b32 v18, v175 -; GFX11-NEXT: v_dual_mov_b32 v19, v174 :: v_dual_mov_b32 v20, v173 -; GFX11-NEXT: v_dual_mov_b32 v21, v172 :: v_dual_mov_b32 v22, v171 -; GFX11-NEXT: v_dual_mov_b32 v23, v170 :: v_dual_mov_b32 v24, v183 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v185, off, s32 -; GFX11-NEXT: scratch_load_b32 v184, off, s32 offset:4 -; GFX11-NEXT: scratch_load_b32 v175, off, s32 offset:8 -; GFX11-NEXT: scratch_load_b32 v174, off, s32 offset:12 -; GFX11-NEXT: scratch_load_b32 v173, off, s32 offset:16 -; GFX11-NEXT: scratch_load_b32 v172, off, s32 offset:20 -; GFX11-NEXT: scratch_load_b32 v171, off, s32 offset:24 -; GFX11-NEXT: scratch_load_b32 v170, off, s32 offset:28 -; GFX11-NEXT: scratch_load_b32 v169, off, s32 offset:32 -; GFX11-NEXT: scratch_load_b32 v168, off, s32 offset:36 -; GFX11-NEXT: scratch_load_b32 v159, off, s32 offset:40 -; GFX11-NEXT: scratch_load_b32 v158, off, s32 offset:44 -; GFX11-NEXT: scratch_load_b32 v157, off, s32 offset:48 -; GFX11-NEXT: scratch_load_b32 v156, off, s32 offset:52 -; GFX11-NEXT: scratch_load_b32 v155, off, s32 offset:56 -; GFX11-NEXT: scratch_load_b32 v154, off, s32 offset:60 -; GFX11-NEXT: scratch_load_b32 v153, off, s32 offset:64 -; GFX11-NEXT: scratch_load_b32 v152, off, s32 offset:68 -; GFX11-NEXT: scratch_load_b32 v143, off, s32 offset:72 -; GFX11-NEXT: scratch_load_b32 v142, off, s32 offset:76 -; GFX11-NEXT: scratch_load_b32 v141, off, s32 offset:80 -; GFX11-NEXT: scratch_load_b32 v140, off, s32 offset:84 -; GFX11-NEXT: scratch_load_b32 v139, off, s32 offset:88 -; GFX11-NEXT: scratch_load_b32 v138, off, s32 offset:92 -; GFX11-NEXT: scratch_load_b32 v137, off, s32 offset:96 -; GFX11-NEXT: scratch_load_b32 v136, off, s32 offset:100 -; GFX11-NEXT: scratch_load_b32 v127, off, s32 offset:104 -; GFX11-NEXT: scratch_load_b32 v126, off, s32 offset:108 -; GFX11-NEXT: scratch_load_b32 v125, off, s32 offset:112 -; GFX11-NEXT: scratch_load_b32 v124, off, s32 offset:116 -; GFX11-NEXT: scratch_load_b32 v123, off, s32 offset:120 -; GFX11-NEXT: scratch_load_b32 v122, off, s32 offset:124 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v121, off, s32 offset:128 -; GFX11-NEXT: scratch_load_b32 v120, off, s32 offset:132 -; GFX11-NEXT: scratch_load_b32 v111, off, s32 offset:136 -; GFX11-NEXT: scratch_load_b32 v110, off, s32 offset:140 -; GFX11-NEXT: scratch_load_b32 v109, off, s32 offset:144 -; GFX11-NEXT: scratch_load_b32 v108, off, s32 offset:148 -; GFX11-NEXT: scratch_load_b32 v107, off, s32 offset:152 -; GFX11-NEXT: scratch_load_b32 v106, off, s32 offset:156 -; GFX11-NEXT: scratch_load_b32 v105, off, s32 offset:160 -; GFX11-NEXT: scratch_load_b32 v104, off, s32 offset:164 -; GFX11-NEXT: scratch_load_b32 v95, off, s32 offset:168 -; GFX11-NEXT: scratch_load_b32 v94, off, s32 offset:172 -; GFX11-NEXT: scratch_load_b32 v93, off, s32 offset:176 -; GFX11-NEXT: scratch_load_b32 v92, off, s32 offset:180 -; GFX11-NEXT: scratch_load_b32 v91, off, s32 offset:184 -; GFX11-NEXT: scratch_load_b32 v90, off, s32 offset:188 -; GFX11-NEXT: scratch_load_b32 v89, off, s32 offset:192 -; GFX11-NEXT: scratch_load_b32 v88, off, s32 offset:196 -; GFX11-NEXT: scratch_load_b32 v79, off, s32 offset:200 -; GFX11-NEXT: scratch_load_b32 v78, off, s32 offset:204 -; GFX11-NEXT: scratch_load_b32 v77, off, s32 offset:208 -; GFX11-NEXT: scratch_load_b32 v76, off, s32 offset:212 -; GFX11-NEXT: scratch_load_b32 v75, off, s32 offset:216 -; GFX11-NEXT: scratch_load_b32 v74, off, s32 offset:220 -; GFX11-NEXT: scratch_load_b32 v73, off, s32 offset:224 -; GFX11-NEXT: scratch_load_b32 v72, off, s32 offset:228 -; GFX11-NEXT: scratch_load_b32 v63, off, s32 offset:232 -; GFX11-NEXT: scratch_load_b32 v62, off, s32 offset:236 -; GFX11-NEXT: scratch_load_b32 v61, off, s32 offset:240 -; GFX11-NEXT: scratch_load_b32 v60, off, s32 offset:244 -; GFX11-NEXT: scratch_load_b32 v59, off, s32 offset:248 -; GFX11-NEXT: scratch_load_b32 v58, off, s32 offset:252 -; GFX11-NEXT: s_clause 0x9 ; 40-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v57, off, s32 offset:256 -; GFX11-NEXT: scratch_load_b32 v56, off, s32 offset:260 -; GFX11-NEXT: scratch_load_b32 v47, off, s32 offset:264 -; GFX11-NEXT: scratch_load_b32 v46, off, s32 offset:268 -; GFX11-NEXT: scratch_load_b32 v45, off, s32 offset:272 -; GFX11-NEXT: scratch_load_b32 v44, off, s32 offset:276 -; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:280 -; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:284 -; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:288 -; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:292 -; GFX11-NEXT: v_dual_mov_b32 v2, v52 :: v_dual_mov_b32 v5, v67 -; GFX11-NEXT: v_dual_mov_b32 v10, v112 :: v_dual_mov_b32 v13, v151 -; GFX11-NEXT: v_dual_mov_b32 v25, v182 :: v_dual_mov_b32 v26, v181 -; GFX11-NEXT: v_dual_mov_b32 v27, v180 :: v_dual_mov_b32 v28, v179 -; GFX11-NEXT: v_dual_mov_b32 v29, v178 :: v_dual_mov_b32 v30, v177 -; GFX11-NEXT: v_mov_b32_e32 v31, v176 -; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: .LBB23_4: -; GFX11-NEXT: ; implicit-def: $vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78 -; GFX11-NEXT: ; implicit-def: $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79 -; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-NEXT: ; implicit-def: $vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81 -; GFX11-NEXT: ; implicit-def: $vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84 -; GFX11-NEXT: ; implicit-def: $vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88 -; GFX11-NEXT: ; implicit-def: $vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93 -; GFX11-NEXT: ; implicit-def: $vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99 -; GFX11-NEXT: ; implicit-def: $vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106 -; GFX11-NEXT: ; implicit-def: $vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114 -; GFX11-NEXT: ; implicit-def: $vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123 -; GFX11-NEXT: ; implicit-def: $vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133 -; GFX11-NEXT: ; implicit-def: $vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144 -; GFX11-NEXT: ; implicit-def: $vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156 -; GFX11-NEXT: ; implicit-def: $vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169 +; GFX11-NEXT: ; implicit-def: $vgpr0 +; GFX11-NEXT: ; implicit-def: $vgpr1 +; GFX11-NEXT: ; implicit-def: $vgpr2 +; GFX11-NEXT: ; implicit-def: $vgpr3 +; GFX11-NEXT: ; implicit-def: $vgpr4 +; GFX11-NEXT: ; implicit-def: $vgpr5 +; GFX11-NEXT: ; implicit-def: $vgpr6 +; GFX11-NEXT: ; implicit-def: $vgpr7 +; GFX11-NEXT: ; implicit-def: $vgpr8 +; GFX11-NEXT: ; implicit-def: $vgpr9 +; GFX11-NEXT: ; implicit-def: $vgpr10 +; GFX11-NEXT: ; implicit-def: $vgpr11 +; GFX11-NEXT: ; implicit-def: $vgpr12 +; GFX11-NEXT: ; implicit-def: $vgpr13 +; GFX11-NEXT: ; implicit-def: $vgpr14 +; GFX11-NEXT: ; implicit-def: $vgpr15 ; GFX11-NEXT: s_branch .LBB23_2 %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -35539,37 +35282,65 @@ define inreg <64 x i16> @bitcast_v32i32_to_v64i16_scalar(<32 x i32> inreg %a, i3 ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v20, s30, 0 -; SI-NEXT: v_writelane_b32 v20, s31, 1 -; SI-NEXT: v_writelane_b32 v20, s34, 2 -; SI-NEXT: v_writelane_b32 v20, s35, 3 -; SI-NEXT: v_writelane_b32 v20, s36, 4 -; SI-NEXT: v_writelane_b32 v20, s37, 5 -; SI-NEXT: v_writelane_b32 v20, s38, 6 -; SI-NEXT: v_writelane_b32 v20, s39, 7 -; SI-NEXT: v_writelane_b32 v20, s48, 8 -; SI-NEXT: v_writelane_b32 v20, s49, 9 -; SI-NEXT: v_writelane_b32 v20, s50, 10 -; SI-NEXT: v_writelane_b32 v20, s51, 11 -; SI-NEXT: v_writelane_b32 v20, s52, 12 -; SI-NEXT: v_writelane_b32 v20, s53, 13 -; SI-NEXT: v_writelane_b32 v20, s54, 14 -; SI-NEXT: v_writelane_b32 v20, s55, 15 -; SI-NEXT: v_writelane_b32 v20, s64, 16 -; SI-NEXT: v_writelane_b32 v20, s65, 17 -; SI-NEXT: v_writelane_b32 v20, s66, 18 -; SI-NEXT: v_writelane_b32 v20, s67, 19 +; SI-NEXT: v_writelane_b32 v21, s30, 0 +; SI-NEXT: v_writelane_b32 v21, s31, 1 +; SI-NEXT: v_writelane_b32 v21, s34, 2 +; SI-NEXT: v_writelane_b32 v21, s35, 3 +; SI-NEXT: v_writelane_b32 v21, s36, 4 +; SI-NEXT: v_writelane_b32 v21, s37, 5 +; SI-NEXT: v_writelane_b32 v21, s38, 6 +; SI-NEXT: v_mov_b32_e32 v20, s16 +; SI-NEXT: v_writelane_b32 v21, s39, 7 +; SI-NEXT: v_readfirstlane_b32 s56, v20 +; SI-NEXT: v_mov_b32_e32 v20, s17 +; SI-NEXT: v_writelane_b32 v21, s48, 8 +; SI-NEXT: v_readfirstlane_b32 s57, v20 +; SI-NEXT: v_mov_b32_e32 v20, s18 +; SI-NEXT: v_writelane_b32 v21, s49, 9 +; SI-NEXT: v_readfirstlane_b32 s46, v20 +; SI-NEXT: v_mov_b32_e32 v20, s19 +; SI-NEXT: v_writelane_b32 v21, s50, 10 +; SI-NEXT: v_readfirstlane_b32 s47, v20 +; SI-NEXT: v_mov_b32_e32 v20, s20 +; SI-NEXT: v_writelane_b32 v21, s51, 11 +; SI-NEXT: v_readfirstlane_b32 s44, v20 +; SI-NEXT: v_mov_b32_e32 v20, s21 +; SI-NEXT: v_writelane_b32 v21, s52, 12 +; SI-NEXT: v_readfirstlane_b32 s45, v20 +; SI-NEXT: v_mov_b32_e32 v20, s22 +; SI-NEXT: v_writelane_b32 v21, s53, 13 +; SI-NEXT: v_readfirstlane_b32 s42, v20 +; SI-NEXT: v_mov_b32_e32 v20, s23 +; SI-NEXT: v_writelane_b32 v21, s54, 14 +; SI-NEXT: v_readfirstlane_b32 s43, v20 +; SI-NEXT: v_mov_b32_e32 v20, s24 +; SI-NEXT: v_writelane_b32 v21, s55, 15 +; SI-NEXT: v_readfirstlane_b32 s40, v20 +; SI-NEXT: v_mov_b32_e32 v20, s25 +; SI-NEXT: v_writelane_b32 v21, s64, 16 +; SI-NEXT: v_readfirstlane_b32 s41, v20 +; SI-NEXT: v_mov_b32_e32 v20, s26 +; SI-NEXT: v_writelane_b32 v21, s65, 17 +; SI-NEXT: v_readfirstlane_b32 s24, v20 +; SI-NEXT: v_mov_b32_e32 v20, s27 +; SI-NEXT: v_writelane_b32 v21, s66, 18 +; SI-NEXT: v_readfirstlane_b32 s25, v20 +; SI-NEXT: v_mov_b32_e32 v20, s28 +; SI-NEXT: v_writelane_b32 v21, s67, 19 +; SI-NEXT: v_readfirstlane_b32 s22, v20 +; SI-NEXT: v_mov_b32_e32 v20, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_writelane_b32 v20, s68, 20 -; SI-NEXT: v_readfirstlane_b32 s44, v1 -; SI-NEXT: v_readfirstlane_b32 s45, v2 -; SI-NEXT: v_readfirstlane_b32 s42, v3 -; SI-NEXT: v_readfirstlane_b32 s43, v4 -; SI-NEXT: v_readfirstlane_b32 s40, v5 -; SI-NEXT: v_readfirstlane_b32 s41, v6 +; SI-NEXT: v_writelane_b32 v21, s68, 20 +; SI-NEXT: v_readfirstlane_b32 s23, v20 +; SI-NEXT: v_readfirstlane_b32 s20, v1 +; SI-NEXT: v_readfirstlane_b32 s21, v2 +; SI-NEXT: v_readfirstlane_b32 s18, v3 +; SI-NEXT: v_readfirstlane_b32 s19, v4 +; SI-NEXT: v_readfirstlane_b32 s16, v5 +; SI-NEXT: v_readfirstlane_b32 s17, v6 ; SI-NEXT: v_readfirstlane_b32 s14, v7 ; SI-NEXT: v_readfirstlane_b32 s15, v8 ; SI-NEXT: v_readfirstlane_b32 s12, v9 @@ -35581,9 +35352,9 @@ define inreg <64 x i16> @bitcast_v32i32_to_v64i16_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s6, v15 ; SI-NEXT: v_readfirstlane_b32 s7, v16 ; SI-NEXT: v_readfirstlane_b32 s4, v17 -; SI-NEXT: s_and_b64 s[46:47], vcc, exec +; SI-NEXT: s_and_b64 s[26:27], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v18 -; SI-NEXT: v_writelane_b32 v20, s69, 21 +; SI-NEXT: v_writelane_b32 v21, s69, 21 ; SI-NEXT: s_cbranch_scc0 .LBB25_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s38, s5, 16 @@ -35592,54 +35363,54 @@ define inreg <64 x i16> @bitcast_v32i32_to_v64i16_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: s_lshr_b32 s49, s11, 16 ; SI-NEXT: s_lshr_b32 s50, s13, 16 ; SI-NEXT: s_lshr_b32 s51, s15, 16 -; SI-NEXT: s_lshr_b32 s52, s41, 16 -; SI-NEXT: s_lshr_b32 s53, s43, 16 -; SI-NEXT: s_lshr_b32 s54, s45, 16 -; SI-NEXT: s_lshr_b32 s55, s29, 16 -; SI-NEXT: s_lshr_b32 s64, s27, 16 -; SI-NEXT: s_lshr_b32 s65, s25, 16 -; SI-NEXT: s_lshr_b32 s66, s23, 16 -; SI-NEXT: s_lshr_b32 s67, s21, 16 -; SI-NEXT: s_lshr_b32 s68, s19, 16 -; SI-NEXT: s_lshr_b32 s69, s17, 16 -; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[56:57], s[6:7], 16 +; SI-NEXT: s_lshr_b32 s52, s17, 16 +; SI-NEXT: s_lshr_b32 s53, s19, 16 +; SI-NEXT: s_lshr_b32 s54, s21, 16 +; SI-NEXT: s_lshr_b32 s55, s23, 16 +; SI-NEXT: s_lshr_b32 s64, s25, 16 +; SI-NEXT: s_lshr_b32 s65, s41, 16 +; SI-NEXT: s_lshr_b32 s66, s43, 16 +; SI-NEXT: s_lshr_b32 s67, s45, 16 +; SI-NEXT: s_lshr_b32 s68, s47, 16 +; SI-NEXT: s_lshr_b32 s69, s57, 16 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[6:7], 16 ; SI-NEXT: s_lshr_b64 s[58:59], s[8:9], 16 ; SI-NEXT: s_lshr_b64 s[60:61], s[10:11], 16 ; SI-NEXT: s_lshr_b64 s[62:63], s[12:13], 16 ; SI-NEXT: s_lshr_b64 s[72:73], s[14:15], 16 -; SI-NEXT: s_lshr_b64 s[74:75], s[40:41], 16 -; SI-NEXT: s_lshr_b64 s[76:77], s[42:43], 16 -; SI-NEXT: s_lshr_b64 s[78:79], s[44:45], 16 -; SI-NEXT: s_lshr_b64 s[88:89], s[28:29], 16 -; SI-NEXT: s_lshr_b64 s[90:91], s[26:27], 16 -; SI-NEXT: s_lshr_b64 s[92:93], s[24:25], 16 -; SI-NEXT: s_lshr_b64 s[94:95], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[30:31], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[34:35], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[36:37], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[74:75], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[76:77], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[78:79], s[20:21], 16 +; SI-NEXT: s_lshr_b64 s[88:89], s[22:23], 16 +; SI-NEXT: s_lshr_b64 s[90:91], s[24:25], 16 +; SI-NEXT: s_lshr_b64 s[92:93], s[40:41], 16 +; SI-NEXT: s_lshr_b64 s[94:95], s[42:43], 16 +; SI-NEXT: s_lshr_b64 s[30:31], s[44:45], 16 +; SI-NEXT: s_lshr_b64 s[34:35], s[46:47], 16 +; SI-NEXT: s_lshr_b64 s[36:37], s[56:57], 16 ; SI-NEXT: s_cbranch_execnz .LBB25_3 ; SI-NEXT: .LBB25_2: ; %cmp.true -; SI-NEXT: s_add_i32 s17, s17, 3 -; SI-NEXT: s_add_i32 s16, s16, 3 -; SI-NEXT: s_add_i32 s19, s19, 3 -; SI-NEXT: s_add_i32 s18, s18, 3 -; SI-NEXT: s_add_i32 s21, s21, 3 -; SI-NEXT: s_add_i32 s20, s20, 3 -; SI-NEXT: s_add_i32 s23, s23, 3 -; SI-NEXT: s_add_i32 s22, s22, 3 -; SI-NEXT: s_add_i32 s25, s25, 3 -; SI-NEXT: s_add_i32 s24, s24, 3 -; SI-NEXT: s_add_i32 s27, s27, 3 -; SI-NEXT: s_add_i32 s26, s26, 3 -; SI-NEXT: s_add_i32 s29, s29, 3 -; SI-NEXT: s_add_i32 s28, s28, 3 +; SI-NEXT: s_add_i32 s57, s57, 3 +; SI-NEXT: s_add_i32 s56, s56, 3 +; SI-NEXT: s_add_i32 s47, s47, 3 +; SI-NEXT: s_add_i32 s46, s46, 3 ; SI-NEXT: s_add_i32 s45, s45, 3 ; SI-NEXT: s_add_i32 s44, s44, 3 ; SI-NEXT: s_add_i32 s43, s43, 3 ; SI-NEXT: s_add_i32 s42, s42, 3 ; SI-NEXT: s_add_i32 s41, s41, 3 ; SI-NEXT: s_add_i32 s40, s40, 3 +; SI-NEXT: s_add_i32 s25, s25, 3 +; SI-NEXT: s_add_i32 s24, s24, 3 +; SI-NEXT: s_add_i32 s23, s23, 3 +; SI-NEXT: s_add_i32 s22, s22, 3 +; SI-NEXT: s_add_i32 s21, s21, 3 +; SI-NEXT: s_add_i32 s20, s20, 3 +; SI-NEXT: s_add_i32 s19, s19, 3 +; SI-NEXT: s_add_i32 s18, s18, 3 +; SI-NEXT: s_add_i32 s17, s17, 3 +; SI-NEXT: s_add_i32 s16, s16, 3 ; SI-NEXT: s_add_i32 s15, s15, 3 ; SI-NEXT: s_add_i32 s14, s14, 3 ; SI-NEXT: s_add_i32 s13, s13, 3 @@ -35652,166 +35423,166 @@ define inreg <64 x i16> @bitcast_v32i32_to_v64i16_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: s_add_i32 s6, s6, 3 ; SI-NEXT: s_add_i32 s5, s5, 3 ; SI-NEXT: s_add_i32 s4, s4, 3 -; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[56:57], s[6:7], 16 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[6:7], 16 ; SI-NEXT: s_lshr_b64 s[58:59], s[8:9], 16 ; SI-NEXT: s_lshr_b64 s[60:61], s[10:11], 16 ; SI-NEXT: s_lshr_b64 s[62:63], s[12:13], 16 ; SI-NEXT: s_lshr_b64 s[72:73], s[14:15], 16 -; SI-NEXT: s_lshr_b64 s[74:75], s[40:41], 16 -; SI-NEXT: s_lshr_b64 s[76:77], s[42:43], 16 -; SI-NEXT: s_lshr_b64 s[78:79], s[44:45], 16 -; SI-NEXT: s_lshr_b64 s[88:89], s[28:29], 16 +; SI-NEXT: s_lshr_b64 s[74:75], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[76:77], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[78:79], s[20:21], 16 +; SI-NEXT: s_lshr_b64 s[88:89], s[22:23], 16 ; SI-NEXT: s_lshr_b32 s38, s5, 16 ; SI-NEXT: s_lshr_b32 s39, s7, 16 ; SI-NEXT: s_lshr_b32 s48, s9, 16 ; SI-NEXT: s_lshr_b32 s49, s11, 16 ; SI-NEXT: s_lshr_b32 s50, s13, 16 ; SI-NEXT: s_lshr_b32 s51, s15, 16 -; SI-NEXT: s_lshr_b32 s52, s41, 16 -; SI-NEXT: s_lshr_b32 s53, s43, 16 -; SI-NEXT: s_lshr_b32 s54, s45, 16 -; SI-NEXT: s_lshr_b32 s55, s29, 16 -; SI-NEXT: s_lshr_b32 s64, s27, 16 -; SI-NEXT: s_lshr_b32 s65, s25, 16 -; SI-NEXT: s_lshr_b32 s66, s23, 16 -; SI-NEXT: s_lshr_b32 s67, s21, 16 -; SI-NEXT: s_lshr_b32 s68, s19, 16 -; SI-NEXT: s_lshr_b32 s69, s17, 16 -; SI-NEXT: s_lshr_b64 s[90:91], s[26:27], 16 -; SI-NEXT: s_lshr_b64 s[92:93], s[24:25], 16 -; SI-NEXT: s_lshr_b64 s[94:95], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[30:31], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[34:35], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[36:37], s[16:17], 16 +; SI-NEXT: s_lshr_b32 s52, s17, 16 +; SI-NEXT: s_lshr_b32 s53, s19, 16 +; SI-NEXT: s_lshr_b32 s54, s21, 16 +; SI-NEXT: s_lshr_b32 s55, s23, 16 +; SI-NEXT: s_lshr_b32 s64, s25, 16 +; SI-NEXT: s_lshr_b32 s65, s41, 16 +; SI-NEXT: s_lshr_b32 s66, s43, 16 +; SI-NEXT: s_lshr_b32 s67, s45, 16 +; SI-NEXT: s_lshr_b32 s68, s47, 16 +; SI-NEXT: s_lshr_b32 s69, s57, 16 +; SI-NEXT: s_lshr_b64 s[90:91], s[24:25], 16 +; SI-NEXT: s_lshr_b64 s[92:93], s[40:41], 16 +; SI-NEXT: s_lshr_b64 s[94:95], s[42:43], 16 +; SI-NEXT: s_lshr_b64 s[30:31], s[44:45], 16 +; SI-NEXT: s_lshr_b64 s[34:35], s[46:47], 16 +; SI-NEXT: s_lshr_b64 s[36:37], s[56:57], 16 ; SI-NEXT: .LBB25_3: ; %end -; SI-NEXT: s_lshl_b32 s47, s36, 16 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s47 -; SI-NEXT: v_mov_b32_e32 v1, s16 -; SI-NEXT: s_and_b32 s16, s17, 0xffff -; SI-NEXT: s_lshl_b32 s17, s69, 16 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_lshl_b32 s16, s34, 16 -; SI-NEXT: s_and_b32 s17, s18, 0xffff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: v_mov_b32_e32 v3, s16 -; SI-NEXT: s_and_b32 s16, s19, 0xffff -; SI-NEXT: s_lshl_b32 s17, s68, 16 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v4, s16 -; SI-NEXT: s_lshl_b32 s16, s30, 16 -; SI-NEXT: s_and_b32 s17, s20, 0xffff -; SI-NEXT: s_or_b32 s16, s17, s16 +; SI-NEXT: s_lshl_b32 s27, s36, 16 +; SI-NEXT: s_and_b32 s29, s56, 0xffff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: v_mov_b32_e32 v1, s27 +; SI-NEXT: s_and_b32 s27, s57, 0xffff +; SI-NEXT: s_lshl_b32 s29, s69, 16 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_lshl_b32 s27, s34, 16 +; SI-NEXT: s_and_b32 s29, s46, 0xffff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: v_mov_b32_e32 v3, s27 +; SI-NEXT: s_and_b32 s27, s47, 0xffff +; SI-NEXT: s_lshl_b32 s29, s68, 16 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v4, s27 +; SI-NEXT: s_lshl_b32 s27, s30, 16 +; SI-NEXT: s_and_b32 s29, s44, 0xffff +; SI-NEXT: s_or_b32 s27, s29, s27 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0 -; SI-NEXT: v_mov_b32_e32 v5, s16 +; SI-NEXT: v_mov_b32_e32 v5, s27 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0 -; SI-NEXT: s_and_b32 s16, s21, 0xffff -; SI-NEXT: s_lshl_b32 s17, s67, 16 +; SI-NEXT: s_and_b32 s27, s45, 0xffff +; SI-NEXT: s_lshl_b32 s29, s67, 16 ; SI-NEXT: buffer_store_dword v3, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 12, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s27, s27, s29 ; SI-NEXT: buffer_store_dword v4, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0 ; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s22, 0xffff -; SI-NEXT: s_lshl_b32 s17, s94, 16 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_and_b32 s27, s42, 0xffff +; SI-NEXT: s_lshl_b32 s29, s94, 16 ; SI-NEXT: buffer_store_dword v5, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 20, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s27, s27, s29 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s23, 0xffff -; SI-NEXT: s_lshl_b32 s17, s66, 16 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_and_b32 s27, s43, 0xffff +; SI-NEXT: s_lshl_b32 s29, s66, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s27, s27, s29 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s24, 0xffff -; SI-NEXT: s_lshl_b32 s17, s92, 16 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_and_b32 s27, s40, 0xffff +; SI-NEXT: s_lshl_b32 s29, s92, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 28, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s27, s27, s29 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s25, 0xffff -; SI-NEXT: s_lshl_b32 s17, s65, 16 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_and_b32 s27, s41, 0xffff +; SI-NEXT: s_lshl_b32 s29, s65, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s27, s27, s29 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s26, 0xffff -; SI-NEXT: s_lshl_b32 s17, s90, 16 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_and_b32 s24, s24, 0xffff +; SI-NEXT: s_lshl_b32 s27, s90, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 36, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s24, s24, s27 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s27, 0xffff -; SI-NEXT: s_lshl_b32 s17, s64, 16 +; SI-NEXT: v_mov_b32_e32 v2, s24 +; SI-NEXT: s_and_b32 s24, s25, 0xffff +; SI-NEXT: s_lshl_b32 s25, s64, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s24, s24, s25 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s28, 0xffff -; SI-NEXT: s_lshl_b32 s17, s88, 16 +; SI-NEXT: v_mov_b32_e32 v2, s24 +; SI-NEXT: s_and_b32 s22, s22, 0xffff +; SI-NEXT: s_lshl_b32 s24, s88, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 44, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s22, s22, s24 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s29, 0xffff -; SI-NEXT: s_lshl_b32 s17, s55, 16 +; SI-NEXT: v_mov_b32_e32 v2, s22 +; SI-NEXT: s_and_b32 s22, s23, 0xffff +; SI-NEXT: s_lshl_b32 s23, s55, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s22, s22, s23 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s44, 0xffff -; SI-NEXT: s_lshl_b32 s17, s78, 16 +; SI-NEXT: v_mov_b32_e32 v2, s22 +; SI-NEXT: s_and_b32 s20, s20, 0xffff +; SI-NEXT: s_lshl_b32 s22, s78, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 52, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s20, s20, s22 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s45, 0xffff -; SI-NEXT: s_lshl_b32 s17, s54, 16 +; SI-NEXT: v_mov_b32_e32 v2, s20 +; SI-NEXT: s_and_b32 s20, s21, 0xffff +; SI-NEXT: s_lshl_b32 s21, s54, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 56, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s20, s20, s21 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s42, 0xffff -; SI-NEXT: s_lshl_b32 s17, s76, 16 +; SI-NEXT: v_mov_b32_e32 v2, s20 +; SI-NEXT: s_and_b32 s18, s18, 0xffff +; SI-NEXT: s_lshl_b32 s20, s76, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 60, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s18, s18, s20 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s43, 0xffff -; SI-NEXT: s_lshl_b32 s17, s53, 16 +; SI-NEXT: v_mov_b32_e32 v2, s18 +; SI-NEXT: s_and_b32 s18, s19, 0xffff +; SI-NEXT: s_lshl_b32 s19, s53, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 64, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s18, s18, s19 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s40, 0xffff -; SI-NEXT: s_lshl_b32 s17, s74, 16 +; SI-NEXT: v_mov_b32_e32 v2, s18 +; SI-NEXT: s_and_b32 s16, s16, 0xffff +; SI-NEXT: s_lshl_b32 s18, s74, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x44, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s16, s16, s18 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s41, 0xffff +; SI-NEXT: s_and_b32 s16, s17, 0xffff ; SI-NEXT: s_lshl_b32 s17, s52, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x48, v0 ; SI-NEXT: s_or_b32 s16, s16, s17 @@ -35875,7 +35646,7 @@ define inreg <64 x i16> @bitcast_v32i32_to_v64i16_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s8 ; SI-NEXT: s_and_b32 s6, s6, 0xffff -; SI-NEXT: s_lshl_b32 s8, s56, 16 +; SI-NEXT: s_lshl_b32 s8, s28, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x6c, v0 ; SI-NEXT: s_or_b32 s6, s6, s8 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen @@ -35889,7 +35660,7 @@ define inreg <64 x i16> @bitcast_v32i32_to_v64i16_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s6 ; SI-NEXT: s_and_b32 s4, s4, 0xffff -; SI-NEXT: s_lshl_b32 s6, s46, 16 +; SI-NEXT: s_lshl_b32 s6, s26, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x74, v0 ; SI-NEXT: s_or_b32 s4, s4, s6 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen @@ -35903,30 +35674,30 @@ define inreg <64 x i16> @bitcast_v32i32_to_v64i16_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s69, v20, 21 -; SI-NEXT: v_readlane_b32 s68, v20, 20 -; SI-NEXT: v_readlane_b32 s67, v20, 19 -; SI-NEXT: v_readlane_b32 s66, v20, 18 -; SI-NEXT: v_readlane_b32 s65, v20, 17 -; SI-NEXT: v_readlane_b32 s64, v20, 16 -; SI-NEXT: v_readlane_b32 s55, v20, 15 -; SI-NEXT: v_readlane_b32 s54, v20, 14 -; SI-NEXT: v_readlane_b32 s53, v20, 13 -; SI-NEXT: v_readlane_b32 s52, v20, 12 -; SI-NEXT: v_readlane_b32 s51, v20, 11 -; SI-NEXT: v_readlane_b32 s50, v20, 10 -; SI-NEXT: v_readlane_b32 s49, v20, 9 -; SI-NEXT: v_readlane_b32 s48, v20, 8 -; SI-NEXT: v_readlane_b32 s39, v20, 7 -; SI-NEXT: v_readlane_b32 s38, v20, 6 -; SI-NEXT: v_readlane_b32 s37, v20, 5 -; SI-NEXT: v_readlane_b32 s36, v20, 4 -; SI-NEXT: v_readlane_b32 s35, v20, 3 -; SI-NEXT: v_readlane_b32 s34, v20, 2 -; SI-NEXT: v_readlane_b32 s31, v20, 1 -; SI-NEXT: v_readlane_b32 s30, v20, 0 +; SI-NEXT: v_readlane_b32 s69, v21, 21 +; SI-NEXT: v_readlane_b32 s68, v21, 20 +; SI-NEXT: v_readlane_b32 s67, v21, 19 +; SI-NEXT: v_readlane_b32 s66, v21, 18 +; SI-NEXT: v_readlane_b32 s65, v21, 17 +; SI-NEXT: v_readlane_b32 s64, v21, 16 +; SI-NEXT: v_readlane_b32 s55, v21, 15 +; SI-NEXT: v_readlane_b32 s54, v21, 14 +; SI-NEXT: v_readlane_b32 s53, v21, 13 +; SI-NEXT: v_readlane_b32 s52, v21, 12 +; SI-NEXT: v_readlane_b32 s51, v21, 11 +; SI-NEXT: v_readlane_b32 s50, v21, 10 +; SI-NEXT: v_readlane_b32 s49, v21, 9 +; SI-NEXT: v_readlane_b32 s48, v21, 8 +; SI-NEXT: v_readlane_b32 s39, v21, 7 +; SI-NEXT: v_readlane_b32 s38, v21, 6 +; SI-NEXT: v_readlane_b32 s37, v21, 5 +; SI-NEXT: v_readlane_b32 s36, v21, 4 +; SI-NEXT: v_readlane_b32 s35, v21, 3 +; SI-NEXT: v_readlane_b32 s34, v21, 2 +; SI-NEXT: v_readlane_b32 s31, v21, 1 +; SI-NEXT: v_readlane_b32 s30, v21, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] @@ -35961,8 +35732,8 @@ define inreg <64 x i16> @bitcast_v32i32_to_v64i16_scalar(<32 x i32> inreg %a, i3 ; SI-NEXT: ; implicit-def: $sgpr39 ; SI-NEXT: ; implicit-def: $sgpr38 ; SI-NEXT: ; implicit-def: $sgpr58 -; SI-NEXT: ; implicit-def: $sgpr56 -; SI-NEXT: ; implicit-def: $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr28 +; SI-NEXT: ; implicit-def: $sgpr26 ; SI-NEXT: s_branch .LBB25_2 ; ; VI-LABEL: bitcast_v32i32_to_v64i16_scalar: @@ -37454,23 +37225,51 @@ define inreg <32 x i32> @bitcast_v64i16_to_v32i32_scalar(<64 x i16> inreg %a, i3 ; VI-LABEL: bitcast_v64i16_to_v32i32_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 +; VI-NEXT: v_mov_b32_e32 v19, s16 ; VI-NEXT: v_readfirstlane_b32 s6, v2 +; VI-NEXT: v_mov_b32_e32 v2, s17 ; VI-NEXT: v_readfirstlane_b32 s7, v3 +; VI-NEXT: v_mov_b32_e32 v3, s18 ; VI-NEXT: v_readfirstlane_b32 s8, v4 +; VI-NEXT: v_mov_b32_e32 v4, s19 ; VI-NEXT: v_readfirstlane_b32 s9, v5 +; VI-NEXT: v_mov_b32_e32 v5, s20 ; VI-NEXT: v_readfirstlane_b32 s10, v6 +; VI-NEXT: v_mov_b32_e32 v6, s21 ; VI-NEXT: v_readfirstlane_b32 s11, v7 +; VI-NEXT: v_mov_b32_e32 v7, s22 ; VI-NEXT: v_readfirstlane_b32 s12, v8 +; VI-NEXT: v_mov_b32_e32 v8, s23 ; VI-NEXT: v_readfirstlane_b32 s13, v9 +; VI-NEXT: v_mov_b32_e32 v9, s24 ; VI-NEXT: v_readfirstlane_b32 s14, v10 +; VI-NEXT: v_mov_b32_e32 v10, s25 ; VI-NEXT: v_readfirstlane_b32 s15, v11 -; VI-NEXT: v_readfirstlane_b32 s40, v12 -; VI-NEXT: v_readfirstlane_b32 s41, v13 -; VI-NEXT: v_readfirstlane_b32 s42, v14 -; VI-NEXT: v_readfirstlane_b32 s43, v15 -; VI-NEXT: v_readfirstlane_b32 s44, v16 -; VI-NEXT: v_readfirstlane_b32 s45, v17 +; VI-NEXT: v_mov_b32_e32 v11, s26 +; VI-NEXT: v_readfirstlane_b32 s16, v12 +; VI-NEXT: v_mov_b32_e32 v12, s27 +; VI-NEXT: v_readfirstlane_b32 s17, v13 +; VI-NEXT: v_mov_b32_e32 v13, s28 +; VI-NEXT: v_readfirstlane_b32 s18, v14 +; VI-NEXT: v_mov_b32_e32 v14, s29 +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 +; VI-NEXT: v_readfirstlane_b32 s19, v15 +; VI-NEXT: v_readfirstlane_b32 s20, v16 +; VI-NEXT: v_readfirstlane_b32 s21, v17 +; VI-NEXT: v_readfirstlane_b32 s22, v19 +; VI-NEXT: v_readfirstlane_b32 s23, v2 +; VI-NEXT: v_readfirstlane_b32 s24, v3 +; VI-NEXT: v_readfirstlane_b32 s25, v4 +; VI-NEXT: v_readfirstlane_b32 s26, v5 +; VI-NEXT: v_readfirstlane_b32 s27, v6 +; VI-NEXT: v_readfirstlane_b32 s28, v7 +; VI-NEXT: v_readfirstlane_b32 s29, v8 +; VI-NEXT: v_readfirstlane_b32 s40, v9 +; VI-NEXT: v_readfirstlane_b32 s41, v10 +; VI-NEXT: v_readfirstlane_b32 s42, v11 +; VI-NEXT: v_readfirstlane_b32 s43, v12 +; VI-NEXT: v_readfirstlane_b32 s44, v13 +; VI-NEXT: v_readfirstlane_b32 s45, v14 ; VI-NEXT: v_readfirstlane_b32 s46, v0 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s47, v1 @@ -37487,8 +37286,38 @@ define inreg <32 x i32> @bitcast_v64i16_to_v32i32_scalar(<64 x i16> inreg %a, i3 ; VI-NEXT: s_and_b32 s4, s46, 0xffff0000 ; VI-NEXT: s_and_b32 s5, s5, 0xffff ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s29, 3 +; VI-NEXT: s_add_i32 s5, s45, 3 ; VI-NEXT: s_add_i32 s46, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s45, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s44, 3 +; VI-NEXT: s_add_i32 s45, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s44, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s43, 3 +; VI-NEXT: s_add_i32 s44, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s43, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s42, 3 +; VI-NEXT: s_add_i32 s43, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s42, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s41, 3 +; VI-NEXT: s_add_i32 s42, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s41, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s40, 3 +; VI-NEXT: s_add_i32 s41, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s40, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s29, 3 +; VI-NEXT: s_add_i32 s40, s4, 0x30000 ; VI-NEXT: s_and_b32 s4, s29, 0xffff0000 ; VI-NEXT: s_and_b32 s5, s5, 0xffff ; VI-NEXT: s_or_b32 s4, s4, s5 @@ -37557,38 +37386,8 @@ define inreg <32 x i32> @bitcast_v64i16_to_v32i32_scalar(<64 x i16> inreg %a, i3 ; VI-NEXT: s_and_b32 s4, s16, 0xffff0000 ; VI-NEXT: s_and_b32 s5, s5, 0xffff ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s45, 3 -; VI-NEXT: s_add_i32 s16, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s45, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s44, 3 -; VI-NEXT: s_add_i32 s45, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s44, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s43, 3 -; VI-NEXT: s_add_i32 s44, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s43, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s42, 3 -; VI-NEXT: s_add_i32 s43, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s42, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s41, 3 -; VI-NEXT: s_add_i32 s42, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s41, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s40, 3 -; VI-NEXT: s_add_i32 s41, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s40, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 ; VI-NEXT: s_add_i32 s5, s15, 3 -; VI-NEXT: s_add_i32 s40, s4, 0x30000 +; VI-NEXT: s_add_i32 s16, s4, 0x30000 ; VI-NEXT: s_and_b32 s4, s15, 0xffff0000 ; VI-NEXT: s_and_b32 s5, s5, 0xffff ; VI-NEXT: s_or_b32 s4, s4, s5 @@ -37639,20 +37438,20 @@ define inreg <32 x i32> @bitcast_v64i16_to_v32i32_scalar(<64 x i16> inreg %a, i3 ; VI-NEXT: s_or_b32 s4, s4, s5 ; VI-NEXT: s_add_i32 s6, s4, 0x30000 ; VI-NEXT: .LBB27_3: ; %end -; VI-NEXT: v_mov_b32_e32 v0, s16 -; VI-NEXT: v_mov_b32_e32 v1, s17 -; VI-NEXT: v_mov_b32_e32 v2, s18 -; VI-NEXT: v_mov_b32_e32 v3, s19 -; VI-NEXT: v_mov_b32_e32 v4, s20 -; VI-NEXT: v_mov_b32_e32 v5, s21 -; VI-NEXT: v_mov_b32_e32 v6, s22 -; VI-NEXT: v_mov_b32_e32 v7, s23 -; VI-NEXT: v_mov_b32_e32 v8, s24 -; VI-NEXT: v_mov_b32_e32 v9, s25 -; VI-NEXT: v_mov_b32_e32 v10, s26 -; VI-NEXT: v_mov_b32_e32 v11, s27 -; VI-NEXT: v_mov_b32_e32 v12, s28 -; VI-NEXT: v_mov_b32_e32 v13, s29 +; VI-NEXT: v_mov_b32_e32 v0, s22 +; VI-NEXT: v_mov_b32_e32 v1, s23 +; VI-NEXT: v_mov_b32_e32 v2, s24 +; VI-NEXT: v_mov_b32_e32 v3, s25 +; VI-NEXT: v_mov_b32_e32 v4, s26 +; VI-NEXT: v_mov_b32_e32 v5, s27 +; VI-NEXT: v_mov_b32_e32 v6, s28 +; VI-NEXT: v_mov_b32_e32 v7, s29 +; VI-NEXT: v_mov_b32_e32 v8, s40 +; VI-NEXT: v_mov_b32_e32 v9, s41 +; VI-NEXT: v_mov_b32_e32 v10, s42 +; VI-NEXT: v_mov_b32_e32 v11, s43 +; VI-NEXT: v_mov_b32_e32 v12, s44 +; VI-NEXT: v_mov_b32_e32 v13, s45 ; VI-NEXT: v_mov_b32_e32 v14, s46 ; VI-NEXT: v_mov_b32_e32 v15, s47 ; VI-NEXT: v_mov_b32_e32 v16, s6 @@ -37665,12 +37464,12 @@ define inreg <32 x i32> @bitcast_v64i16_to_v32i32_scalar(<64 x i16> inreg %a, i3 ; VI-NEXT: v_mov_b32_e32 v23, s13 ; VI-NEXT: v_mov_b32_e32 v24, s14 ; VI-NEXT: v_mov_b32_e32 v25, s15 -; VI-NEXT: v_mov_b32_e32 v26, s40 -; VI-NEXT: v_mov_b32_e32 v27, s41 -; VI-NEXT: v_mov_b32_e32 v28, s42 -; VI-NEXT: v_mov_b32_e32 v29, s43 -; VI-NEXT: v_mov_b32_e32 v30, s44 -; VI-NEXT: v_mov_b32_e32 v31, s45 +; VI-NEXT: v_mov_b32_e32 v26, s16 +; VI-NEXT: v_mov_b32_e32 v27, s17 +; VI-NEXT: v_mov_b32_e32 v28, s18 +; VI-NEXT: v_mov_b32_e32 v29, s19 +; VI-NEXT: v_mov_b32_e32 v30, s20 +; VI-NEXT: v_mov_b32_e32 v31, s21 ; VI-NEXT: s_setpc_b64 s[30:31] ; VI-NEXT: .LBB27_4: ; VI-NEXT: s_branch .LBB27_2 @@ -37758,252 +37557,80 @@ define inreg <32 x i32> @bitcast_v64i16_to_v32i32_scalar(<64 x i16> inreg %a, i3 ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292 -; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288 -; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284 -; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280 -; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276 -; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272 -; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268 -; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264 -; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260 -; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256 -; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252 -; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248 -; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244 -; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240 -; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236 -; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232 -; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228 -; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224 -; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220 -; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216 -; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212 -; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208 -; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204 -; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200 -; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196 -; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192 -; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188 -; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184 -; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180 -; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176 -; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172 -; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164 -; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160 -; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156 -; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152 -; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148 -; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144 -; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140 -; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136 -; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132 -; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128 -; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124 -; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120 -; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116 -; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112 -; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108 -; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104 -; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100 -; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96 -; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92 -; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88 -; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84 -; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80 -; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76 -; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72 -; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68 -; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64 -; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60 -; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56 -; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52 -; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48 -; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44 -; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40 -; GFX11-NEXT: s_clause 0x9 ; 40-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36 -; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32 -; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28 -; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24 -; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20 -; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16 -; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12 -; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8 -; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4 -; GFX11-NEXT: scratch_store_b32 off, v185, s32 -; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12 -; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10 -; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8 -; GFX11-NEXT: v_dual_mov_b32 v182, v7 :: v_dual_mov_b32 v183, v6 -; GFX11-NEXT: v_dual_mov_b32 v170, v5 :: v_dual_mov_b32 v171, v4 -; GFX11-NEXT: v_dual_mov_b32 v172, v3 :: v_dual_mov_b32 v173, v2 -; GFX11-NEXT: v_dual_mov_b32 v174, v1 :: v_dual_mov_b32 v175, v0 -; GFX11-NEXT: v_dual_mov_b32 v184, s28 :: v_dual_mov_b32 v185, s29 +; GFX11-NEXT: v_dual_mov_b32 v31, v13 :: v_dual_mov_b32 v30, v12 +; GFX11-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 +; GFX11-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 ; GFX11-NEXT: s_mov_b32 s4, 0 ; GFX11-NEXT: s_and_b32 s5, vcc_lo, exec_lo ; GFX11-NEXT: s_cbranch_scc0 .LBB27_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: v_dual_mov_b32 v47, s0 :: v_dual_mov_b32 v52, s2 -; GFX11-NEXT: v_dual_mov_b32 v49, s1 :: v_dual_mov_b32 v56, s3 -; GFX11-NEXT: v_dual_mov_b32 v61, s16 :: v_dual_mov_b32 v74, s18 -; GFX11-NEXT: v_dual_mov_b32 v67, s17 :: v_dual_mov_b32 v82, s19 -; GFX11-NEXT: v_dual_mov_b32 v91, s20 :: v_dual_mov_b32 v112, s22 -; GFX11-NEXT: v_dual_mov_b32 v101, s21 :: v_dual_mov_b32 v124, s23 -; GFX11-NEXT: v_dual_mov_b32 v137, s24 :: v_dual_mov_b32 v14, s26 -; GFX11-NEXT: v_dual_mov_b32 v151, s25 :: v_dual_mov_b32 v30, s27 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 +; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 +; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 +; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 +; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 +; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4 ; GFX11-NEXT: s_cbranch_vccnz .LBB27_3 ; GFX11-NEXT: .LBB27_2: ; %cmp.true -; GFX11-NEXT: v_pk_add_u16 v30, s27, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v15, s27, 3 op_sel_hi:[1,0] ; GFX11-NEXT: v_pk_add_u16 v14, s26, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v176, v176, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v177, v177, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v178, v178, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v179, v179, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v180, v180, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v181, v181, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v182, v182, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v183, v183, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v170, v170, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v171, v171, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v172, v172, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v173, v173, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v174, v174, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v175, v175, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v185, v185, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v184, v184, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v151, s25, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v137, s24, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v124, s23, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v112, s22, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v101, s21, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v91, s20, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v82, s19, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v74, s18, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v67, s17, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v61, s16, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v56, s3, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v52, s2, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v49, s1, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v47, s0, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v13, s25, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v12, s24, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v11, s23, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v10, s22, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v31, v31, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v30, v30, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0] ; GFX11-NEXT: .LBB27_3: ; %end -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_dual_mov_b32 v0, v47 :: v_dual_mov_b32 v1, v49 -; GFX11-NEXT: v_dual_mov_b32 v3, v56 :: v_dual_mov_b32 v4, v61 -; GFX11-NEXT: v_dual_mov_b32 v6, v74 :: v_dual_mov_b32 v9, v101 -; GFX11-NEXT: v_dual_mov_b32 v7, v82 :: v_dual_mov_b32 v8, v91 -; GFX11-NEXT: v_dual_mov_b32 v11, v124 :: v_dual_mov_b32 v12, v137 -; GFX11-NEXT: v_dual_mov_b32 v15, v30 :: v_dual_mov_b32 v16, v184 -; GFX11-NEXT: v_dual_mov_b32 v17, v185 :: v_dual_mov_b32 v18, v175 -; GFX11-NEXT: v_dual_mov_b32 v19, v174 :: v_dual_mov_b32 v20, v173 -; GFX11-NEXT: v_dual_mov_b32 v21, v172 :: v_dual_mov_b32 v22, v171 -; GFX11-NEXT: v_dual_mov_b32 v23, v170 :: v_dual_mov_b32 v24, v183 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v185, off, s32 -; GFX11-NEXT: scratch_load_b32 v184, off, s32 offset:4 -; GFX11-NEXT: scratch_load_b32 v175, off, s32 offset:8 -; GFX11-NEXT: scratch_load_b32 v174, off, s32 offset:12 -; GFX11-NEXT: scratch_load_b32 v173, off, s32 offset:16 -; GFX11-NEXT: scratch_load_b32 v172, off, s32 offset:20 -; GFX11-NEXT: scratch_load_b32 v171, off, s32 offset:24 -; GFX11-NEXT: scratch_load_b32 v170, off, s32 offset:28 -; GFX11-NEXT: scratch_load_b32 v169, off, s32 offset:32 -; GFX11-NEXT: scratch_load_b32 v168, off, s32 offset:36 -; GFX11-NEXT: scratch_load_b32 v159, off, s32 offset:40 -; GFX11-NEXT: scratch_load_b32 v158, off, s32 offset:44 -; GFX11-NEXT: scratch_load_b32 v157, off, s32 offset:48 -; GFX11-NEXT: scratch_load_b32 v156, off, s32 offset:52 -; GFX11-NEXT: scratch_load_b32 v155, off, s32 offset:56 -; GFX11-NEXT: scratch_load_b32 v154, off, s32 offset:60 -; GFX11-NEXT: scratch_load_b32 v153, off, s32 offset:64 -; GFX11-NEXT: scratch_load_b32 v152, off, s32 offset:68 -; GFX11-NEXT: scratch_load_b32 v143, off, s32 offset:72 -; GFX11-NEXT: scratch_load_b32 v142, off, s32 offset:76 -; GFX11-NEXT: scratch_load_b32 v141, off, s32 offset:80 -; GFX11-NEXT: scratch_load_b32 v140, off, s32 offset:84 -; GFX11-NEXT: scratch_load_b32 v139, off, s32 offset:88 -; GFX11-NEXT: scratch_load_b32 v138, off, s32 offset:92 -; GFX11-NEXT: scratch_load_b32 v137, off, s32 offset:96 -; GFX11-NEXT: scratch_load_b32 v136, off, s32 offset:100 -; GFX11-NEXT: scratch_load_b32 v127, off, s32 offset:104 -; GFX11-NEXT: scratch_load_b32 v126, off, s32 offset:108 -; GFX11-NEXT: scratch_load_b32 v125, off, s32 offset:112 -; GFX11-NEXT: scratch_load_b32 v124, off, s32 offset:116 -; GFX11-NEXT: scratch_load_b32 v123, off, s32 offset:120 -; GFX11-NEXT: scratch_load_b32 v122, off, s32 offset:124 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v121, off, s32 offset:128 -; GFX11-NEXT: scratch_load_b32 v120, off, s32 offset:132 -; GFX11-NEXT: scratch_load_b32 v111, off, s32 offset:136 -; GFX11-NEXT: scratch_load_b32 v110, off, s32 offset:140 -; GFX11-NEXT: scratch_load_b32 v109, off, s32 offset:144 -; GFX11-NEXT: scratch_load_b32 v108, off, s32 offset:148 -; GFX11-NEXT: scratch_load_b32 v107, off, s32 offset:152 -; GFX11-NEXT: scratch_load_b32 v106, off, s32 offset:156 -; GFX11-NEXT: scratch_load_b32 v105, off, s32 offset:160 -; GFX11-NEXT: scratch_load_b32 v104, off, s32 offset:164 -; GFX11-NEXT: scratch_load_b32 v95, off, s32 offset:168 -; GFX11-NEXT: scratch_load_b32 v94, off, s32 offset:172 -; GFX11-NEXT: scratch_load_b32 v93, off, s32 offset:176 -; GFX11-NEXT: scratch_load_b32 v92, off, s32 offset:180 -; GFX11-NEXT: scratch_load_b32 v91, off, s32 offset:184 -; GFX11-NEXT: scratch_load_b32 v90, off, s32 offset:188 -; GFX11-NEXT: scratch_load_b32 v89, off, s32 offset:192 -; GFX11-NEXT: scratch_load_b32 v88, off, s32 offset:196 -; GFX11-NEXT: scratch_load_b32 v79, off, s32 offset:200 -; GFX11-NEXT: scratch_load_b32 v78, off, s32 offset:204 -; GFX11-NEXT: scratch_load_b32 v77, off, s32 offset:208 -; GFX11-NEXT: scratch_load_b32 v76, off, s32 offset:212 -; GFX11-NEXT: scratch_load_b32 v75, off, s32 offset:216 -; GFX11-NEXT: scratch_load_b32 v74, off, s32 offset:220 -; GFX11-NEXT: scratch_load_b32 v73, off, s32 offset:224 -; GFX11-NEXT: scratch_load_b32 v72, off, s32 offset:228 -; GFX11-NEXT: scratch_load_b32 v63, off, s32 offset:232 -; GFX11-NEXT: scratch_load_b32 v62, off, s32 offset:236 -; GFX11-NEXT: scratch_load_b32 v61, off, s32 offset:240 -; GFX11-NEXT: scratch_load_b32 v60, off, s32 offset:244 -; GFX11-NEXT: scratch_load_b32 v59, off, s32 offset:248 -; GFX11-NEXT: scratch_load_b32 v58, off, s32 offset:252 -; GFX11-NEXT: s_clause 0x9 ; 40-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v57, off, s32 offset:256 -; GFX11-NEXT: scratch_load_b32 v56, off, s32 offset:260 -; GFX11-NEXT: scratch_load_b32 v47, off, s32 offset:264 -; GFX11-NEXT: scratch_load_b32 v46, off, s32 offset:268 -; GFX11-NEXT: scratch_load_b32 v45, off, s32 offset:272 -; GFX11-NEXT: scratch_load_b32 v44, off, s32 offset:276 -; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:280 -; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:284 -; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:288 -; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:292 -; GFX11-NEXT: v_dual_mov_b32 v2, v52 :: v_dual_mov_b32 v5, v67 -; GFX11-NEXT: v_dual_mov_b32 v10, v112 :: v_dual_mov_b32 v13, v151 -; GFX11-NEXT: v_dual_mov_b32 v25, v182 :: v_dual_mov_b32 v26, v181 -; GFX11-NEXT: v_dual_mov_b32 v27, v180 :: v_dual_mov_b32 v28, v179 -; GFX11-NEXT: v_dual_mov_b32 v29, v178 :: v_dual_mov_b32 v30, v177 -; GFX11-NEXT: v_mov_b32_e32 v31, v176 -; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: .LBB27_4: -; GFX11-NEXT: ; implicit-def: $vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78 -; GFX11-NEXT: ; implicit-def: $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79 -; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-NEXT: ; implicit-def: $vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81 -; GFX11-NEXT: ; implicit-def: $vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84 -; GFX11-NEXT: ; implicit-def: $vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88 -; GFX11-NEXT: ; implicit-def: $vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93 -; GFX11-NEXT: ; implicit-def: $vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99 -; GFX11-NEXT: ; implicit-def: $vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106 -; GFX11-NEXT: ; implicit-def: $vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114 -; GFX11-NEXT: ; implicit-def: $vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123 -; GFX11-NEXT: ; implicit-def: $vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133 -; GFX11-NEXT: ; implicit-def: $vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144 -; GFX11-NEXT: ; implicit-def: $vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156 -; GFX11-NEXT: ; implicit-def: $vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169 +; GFX11-NEXT: ; implicit-def: $vgpr0 +; GFX11-NEXT: ; implicit-def: $vgpr1 +; GFX11-NEXT: ; implicit-def: $vgpr2 +; GFX11-NEXT: ; implicit-def: $vgpr3 +; GFX11-NEXT: ; implicit-def: $vgpr4 +; GFX11-NEXT: ; implicit-def: $vgpr5 +; GFX11-NEXT: ; implicit-def: $vgpr6 +; GFX11-NEXT: ; implicit-def: $vgpr7 +; GFX11-NEXT: ; implicit-def: $vgpr8 +; GFX11-NEXT: ; implicit-def: $vgpr9 +; GFX11-NEXT: ; implicit-def: $vgpr10 +; GFX11-NEXT: ; implicit-def: $vgpr11 +; GFX11-NEXT: ; implicit-def: $vgpr12 +; GFX11-NEXT: ; implicit-def: $vgpr13 +; GFX11-NEXT: ; implicit-def: $vgpr14 +; GFX11-NEXT: ; implicit-def: $vgpr15 ; GFX11-NEXT: s_branch .LBB27_2 %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -44329,9 +43956,9 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: s_or_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(2) ; SI-NEXT: v_writelane_b32 v63, s30, 0 @@ -44356,40 +43983,68 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; SI-NEXT: v_writelane_b32 v63, s67, 19 ; SI-NEXT: v_writelane_b32 v63, s68, 20 ; SI-NEXT: v_writelane_b32 v63, s69, 21 +; SI-NEXT: v_mov_b32_e32 v20, s16 ; SI-NEXT: v_writelane_b32 v63, s70, 22 +; SI-NEXT: v_readfirstlane_b32 s58, v20 +; SI-NEXT: v_mov_b32_e32 v20, s17 ; SI-NEXT: v_writelane_b32 v63, s71, 23 +; SI-NEXT: v_readfirstlane_b32 s59, v20 +; SI-NEXT: v_mov_b32_e32 v20, s18 ; SI-NEXT: v_writelane_b32 v63, s80, 24 +; SI-NEXT: v_readfirstlane_b32 s56, v20 +; SI-NEXT: v_mov_b32_e32 v20, s19 ; SI-NEXT: v_writelane_b32 v63, s81, 25 +; SI-NEXT: v_readfirstlane_b32 s57, v20 +; SI-NEXT: v_mov_b32_e32 v20, s20 ; SI-NEXT: v_writelane_b32 v63, s82, 26 +; SI-NEXT: v_readfirstlane_b32 s46, v20 +; SI-NEXT: v_mov_b32_e32 v20, s21 ; SI-NEXT: v_writelane_b32 v63, s83, 27 +; SI-NEXT: v_readfirstlane_b32 s47, v20 +; SI-NEXT: v_mov_b32_e32 v20, s22 ; SI-NEXT: v_writelane_b32 v63, s84, 28 +; SI-NEXT: v_readfirstlane_b32 s44, v20 +; SI-NEXT: v_mov_b32_e32 v20, s23 ; SI-NEXT: v_writelane_b32 v63, s85, 29 +; SI-NEXT: v_readfirstlane_b32 s45, v20 +; SI-NEXT: v_mov_b32_e32 v20, s24 ; SI-NEXT: v_writelane_b32 v63, s86, 30 +; SI-NEXT: v_readfirstlane_b32 s42, v20 +; SI-NEXT: v_mov_b32_e32 v20, s25 ; SI-NEXT: v_writelane_b32 v63, s87, 31 +; SI-NEXT: v_readfirstlane_b32 s43, v20 +; SI-NEXT: v_mov_b32_e32 v20, s26 ; SI-NEXT: v_writelane_b32 v63, s96, 32 +; SI-NEXT: v_readfirstlane_b32 s40, v20 +; SI-NEXT: v_mov_b32_e32 v20, s27 ; SI-NEXT: v_writelane_b32 v63, s97, 33 +; SI-NEXT: v_readfirstlane_b32 s41, v20 +; SI-NEXT: v_mov_b32_e32 v20, s28 ; SI-NEXT: v_writelane_b32 v63, s98, 34 +; SI-NEXT: v_readfirstlane_b32 s24, v20 +; SI-NEXT: v_mov_b32_e32 v20, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; SI-NEXT: v_writelane_b32 v63, s99, 35 -; SI-NEXT: v_readfirstlane_b32 s44, v1 -; SI-NEXT: v_readfirstlane_b32 s45, v2 -; SI-NEXT: v_readfirstlane_b32 s42, v3 -; SI-NEXT: v_readfirstlane_b32 s43, v4 -; SI-NEXT: v_readfirstlane_b32 s40, v5 -; SI-NEXT: v_readfirstlane_b32 s41, v6 -; SI-NEXT: v_readfirstlane_b32 s14, v7 -; SI-NEXT: v_readfirstlane_b32 s15, v8 -; SI-NEXT: v_readfirstlane_b32 s12, v9 -; SI-NEXT: v_readfirstlane_b32 s13, v10 -; SI-NEXT: v_readfirstlane_b32 s10, v11 -; SI-NEXT: v_readfirstlane_b32 s11, v12 -; SI-NEXT: v_readfirstlane_b32 s8, v13 -; SI-NEXT: v_readfirstlane_b32 s9, v14 -; SI-NEXT: v_readfirstlane_b32 s6, v15 -; SI-NEXT: v_readfirstlane_b32 s7, v16 -; SI-NEXT: v_readfirstlane_b32 s4, v17 -; SI-NEXT: s_and_b64 s[46:47], vcc, exec -; SI-NEXT: v_readfirstlane_b32 s5, v18 +; SI-NEXT: v_readfirstlane_b32 s25, v20 +; SI-NEXT: v_readfirstlane_b32 s22, v1 +; SI-NEXT: v_readfirstlane_b32 s23, v2 +; SI-NEXT: v_readfirstlane_b32 s20, v3 +; SI-NEXT: v_readfirstlane_b32 s21, v4 +; SI-NEXT: v_readfirstlane_b32 s18, v5 +; SI-NEXT: v_readfirstlane_b32 s19, v6 +; SI-NEXT: v_readfirstlane_b32 s16, v7 +; SI-NEXT: v_readfirstlane_b32 s17, v8 +; SI-NEXT: v_readfirstlane_b32 s14, v9 +; SI-NEXT: v_readfirstlane_b32 s15, v10 +; SI-NEXT: v_readfirstlane_b32 s12, v11 +; SI-NEXT: v_readfirstlane_b32 s13, v12 +; SI-NEXT: v_readfirstlane_b32 s10, v13 +; SI-NEXT: v_readfirstlane_b32 s11, v14 +; SI-NEXT: v_readfirstlane_b32 s8, v15 +; SI-NEXT: v_readfirstlane_b32 s9, v16 +; SI-NEXT: v_readfirstlane_b32 s6, v17 +; SI-NEXT: s_and_b64 s[4:5], vcc, exec +; SI-NEXT: v_readfirstlane_b32 s7, v18 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill @@ -44407,497 +44062,551 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; SI-NEXT: s_cbranch_scc0 .LBB37_3 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: s_lshr_b32 s46, s5, 24 -; SI-NEXT: v_writelane_b32 v62, s46, 17 -; SI-NEXT: s_lshr_b32 s46, s5, 16 -; SI-NEXT: v_writelane_b32 v62, s46, 16 -; SI-NEXT: s_lshr_b32 s46, s5, 8 -; SI-NEXT: v_writelane_b32 v62, s46, 15 -; SI-NEXT: s_lshr_b32 s46, s7, 24 -; SI-NEXT: v_writelane_b32 v62, s46, 14 -; SI-NEXT: s_lshr_b32 s46, s7, 16 -; SI-NEXT: v_writelane_b32 v62, s46, 13 -; SI-NEXT: s_lshr_b32 s46, s7, 8 -; SI-NEXT: v_writelane_b32 v62, s46, 12 -; SI-NEXT: s_lshr_b32 s46, s9, 24 -; SI-NEXT: v_writelane_b32 v62, s46, 11 -; SI-NEXT: s_lshr_b32 s46, s9, 16 -; SI-NEXT: v_writelane_b32 v62, s46, 10 -; SI-NEXT: s_lshr_b32 s46, s9, 8 -; SI-NEXT: v_writelane_b32 v62, s46, 9 -; SI-NEXT: s_lshr_b32 s46, s11, 24 -; SI-NEXT: v_writelane_b32 v62, s46, 8 -; SI-NEXT: s_lshr_b32 s46, s11, 16 -; SI-NEXT: v_writelane_b32 v62, s46, 7 -; SI-NEXT: s_lshr_b32 s46, s11, 8 -; SI-NEXT: v_writelane_b32 v62, s46, 6 -; SI-NEXT: s_lshr_b32 s46, s13, 24 -; SI-NEXT: v_writelane_b32 v62, s46, 5 -; SI-NEXT: s_lshr_b32 s46, s13, 16 -; SI-NEXT: v_writelane_b32 v62, s46, 4 -; SI-NEXT: s_lshr_b32 s46, s13, 8 -; SI-NEXT: v_writelane_b32 v62, s46, 3 -; SI-NEXT: s_lshr_b32 s46, s15, 24 -; SI-NEXT: v_writelane_b32 v62, s46, 2 -; SI-NEXT: s_lshr_b32 s46, s15, 16 -; SI-NEXT: v_writelane_b32 v62, s46, 1 -; SI-NEXT: s_lshr_b32 s46, s15, 8 -; SI-NEXT: v_writelane_b32 v62, s46, 0 -; SI-NEXT: s_lshr_b32 s46, s41, 24 -; SI-NEXT: v_writelane_b32 v61, s46, 63 -; SI-NEXT: s_lshr_b32 s46, s41, 16 -; SI-NEXT: v_writelane_b32 v61, s46, 62 -; SI-NEXT: s_lshr_b32 s46, s41, 8 -; SI-NEXT: v_writelane_b32 v61, s46, 61 -; SI-NEXT: s_lshr_b32 s46, s43, 24 -; SI-NEXT: v_writelane_b32 v61, s46, 60 -; SI-NEXT: s_lshr_b32 s46, s43, 16 -; SI-NEXT: v_writelane_b32 v61, s46, 59 -; SI-NEXT: s_lshr_b32 s46, s43, 8 -; SI-NEXT: v_writelane_b32 v61, s46, 58 -; SI-NEXT: s_lshr_b32 s46, s45, 24 -; SI-NEXT: v_writelane_b32 v61, s46, 57 -; SI-NEXT: s_lshr_b32 s46, s45, 16 -; SI-NEXT: v_writelane_b32 v61, s46, 56 -; SI-NEXT: s_lshr_b32 s46, s45, 8 -; SI-NEXT: v_writelane_b32 v61, s46, 55 -; SI-NEXT: s_lshr_b32 s46, s29, 24 -; SI-NEXT: v_writelane_b32 v61, s46, 54 -; SI-NEXT: s_lshr_b32 s46, s29, 16 -; SI-NEXT: v_writelane_b32 v61, s46, 53 -; SI-NEXT: s_lshr_b32 s46, s29, 8 -; SI-NEXT: v_writelane_b32 v61, s46, 52 -; SI-NEXT: s_lshr_b32 s46, s27, 24 -; SI-NEXT: v_writelane_b32 v61, s46, 51 -; SI-NEXT: s_lshr_b32 s46, s27, 16 -; SI-NEXT: v_writelane_b32 v61, s46, 50 -; SI-NEXT: s_lshr_b32 s46, s27, 8 -; SI-NEXT: v_writelane_b32 v61, s46, 49 -; SI-NEXT: s_lshr_b32 s46, s25, 24 -; SI-NEXT: v_writelane_b32 v61, s46, 48 -; SI-NEXT: s_lshr_b32 s46, s25, 16 -; SI-NEXT: v_writelane_b32 v61, s46, 47 -; SI-NEXT: s_lshr_b32 s46, s25, 8 -; SI-NEXT: v_writelane_b32 v61, s46, 46 -; SI-NEXT: s_lshr_b32 s46, s23, 24 -; SI-NEXT: v_writelane_b32 v61, s46, 45 -; SI-NEXT: s_lshr_b32 s46, s23, 16 -; SI-NEXT: v_writelane_b32 v61, s46, 44 -; SI-NEXT: s_lshr_b32 s46, s23, 8 -; SI-NEXT: v_writelane_b32 v61, s46, 43 -; SI-NEXT: s_lshr_b32 s46, s21, 24 -; SI-NEXT: v_writelane_b32 v61, s46, 42 -; SI-NEXT: s_lshr_b32 s46, s21, 16 -; SI-NEXT: v_writelane_b32 v61, s46, 41 -; SI-NEXT: s_lshr_b32 s46, s21, 8 -; SI-NEXT: v_writelane_b32 v61, s46, 40 -; SI-NEXT: s_lshr_b32 s46, s19, 24 -; SI-NEXT: v_writelane_b32 v61, s46, 39 -; SI-NEXT: s_lshr_b32 s46, s19, 16 -; SI-NEXT: v_writelane_b32 v61, s46, 38 -; SI-NEXT: s_lshr_b32 s46, s19, 8 -; SI-NEXT: v_writelane_b32 v61, s46, 37 -; SI-NEXT: s_lshr_b32 s46, s17, 24 -; SI-NEXT: v_writelane_b32 v61, s46, 36 -; SI-NEXT: s_lshr_b32 s46, s17, 16 -; SI-NEXT: v_writelane_b32 v61, s46, 35 -; SI-NEXT: s_lshr_b32 s46, s17, 8 -; SI-NEXT: v_writelane_b32 v61, s46, 34 -; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 24 -; SI-NEXT: v_writelane_b32 v61, s46, 32 -; SI-NEXT: v_writelane_b32 v61, s47, 33 -; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 8 -; SI-NEXT: v_writelane_b32 v61, s46, 30 -; SI-NEXT: v_writelane_b32 v61, s47, 31 -; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 24 -; SI-NEXT: v_writelane_b32 v61, s46, 28 -; SI-NEXT: v_writelane_b32 v61, s47, 29 -; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 16 -; SI-NEXT: v_writelane_b32 v61, s46, 26 -; SI-NEXT: v_writelane_b32 v61, s47, 27 -; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 8 -; SI-NEXT: v_writelane_b32 v61, s46, 24 -; SI-NEXT: v_writelane_b32 v61, s47, 25 -; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 24 -; SI-NEXT: v_writelane_b32 v61, s46, 22 -; SI-NEXT: v_writelane_b32 v61, s47, 23 -; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 16 -; SI-NEXT: v_writelane_b32 v61, s46, 20 -; SI-NEXT: v_writelane_b32 v61, s47, 21 -; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 8 -; SI-NEXT: v_writelane_b32 v61, s46, 18 -; SI-NEXT: v_writelane_b32 v61, s47, 19 -; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 24 -; SI-NEXT: v_writelane_b32 v61, s46, 16 -; SI-NEXT: v_writelane_b32 v61, s47, 17 -; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 16 -; SI-NEXT: v_writelane_b32 v61, s46, 14 -; SI-NEXT: v_writelane_b32 v61, s47, 15 -; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 8 -; SI-NEXT: v_writelane_b32 v61, s46, 12 -; SI-NEXT: v_writelane_b32 v61, s47, 13 -; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 24 -; SI-NEXT: v_writelane_b32 v61, s46, 10 -; SI-NEXT: v_writelane_b32 v61, s47, 11 -; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 16 -; SI-NEXT: v_writelane_b32 v61, s46, 8 -; SI-NEXT: v_writelane_b32 v61, s47, 9 -; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 8 -; SI-NEXT: v_writelane_b32 v61, s46, 6 -; SI-NEXT: v_writelane_b32 v61, s47, 7 -; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 24 -; SI-NEXT: v_writelane_b32 v61, s46, 4 -; SI-NEXT: v_writelane_b32 v61, s47, 5 -; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 16 -; SI-NEXT: v_writelane_b32 v61, s46, 2 -; SI-NEXT: v_writelane_b32 v61, s47, 3 -; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 8 -; SI-NEXT: v_writelane_b32 v61, s46, 0 -; SI-NEXT: s_lshr_b64 s[48:49], s[4:5], 16 -; SI-NEXT: v_writelane_b32 v61, s47, 1 -; SI-NEXT: s_lshr_b64 s[50:51], s[40:41], 24 -; SI-NEXT: s_lshr_b64 s[52:53], s[40:41], 16 -; SI-NEXT: s_lshr_b64 s[54:55], s[40:41], 8 +; SI-NEXT: s_lshr_b32 s4, s7, 24 +; SI-NEXT: v_writelane_b32 v62, s4, 17 +; SI-NEXT: s_lshr_b32 s4, s9, 24 +; SI-NEXT: v_writelane_b32 v62, s4, 16 +; SI-NEXT: s_lshr_b32 s4, s11, 24 +; SI-NEXT: v_writelane_b32 v62, s4, 15 +; SI-NEXT: s_lshr_b32 s4, s11, 16 +; SI-NEXT: v_writelane_b32 v62, s4, 14 +; SI-NEXT: s_lshr_b32 s4, s13, 24 +; SI-NEXT: v_writelane_b32 v62, s4, 13 +; SI-NEXT: s_lshr_b32 s4, s13, 16 +; SI-NEXT: v_writelane_b32 v62, s4, 12 +; SI-NEXT: s_lshr_b32 s4, s13, 8 +; SI-NEXT: v_writelane_b32 v62, s4, 11 +; SI-NEXT: s_lshr_b32 s4, s15, 24 +; SI-NEXT: v_writelane_b32 v62, s4, 10 +; SI-NEXT: s_lshr_b32 s4, s15, 16 +; SI-NEXT: v_writelane_b32 v62, s4, 9 +; SI-NEXT: s_lshr_b32 s4, s15, 8 +; SI-NEXT: v_writelane_b32 v62, s4, 8 +; SI-NEXT: s_lshr_b32 s4, s17, 24 +; SI-NEXT: v_writelane_b32 v62, s4, 7 +; SI-NEXT: s_lshr_b32 s4, s17, 16 +; SI-NEXT: v_writelane_b32 v62, s4, 6 +; SI-NEXT: s_lshr_b32 s4, s17, 8 +; SI-NEXT: v_writelane_b32 v62, s4, 5 +; SI-NEXT: s_lshr_b32 s4, s19, 24 +; SI-NEXT: v_writelane_b32 v62, s4, 4 +; SI-NEXT: s_lshr_b32 s4, s19, 16 +; SI-NEXT: v_writelane_b32 v62, s4, 3 +; SI-NEXT: s_lshr_b32 s4, s19, 8 +; SI-NEXT: v_writelane_b32 v62, s4, 2 +; SI-NEXT: s_lshr_b32 s4, s21, 24 +; SI-NEXT: v_writelane_b32 v62, s4, 1 +; SI-NEXT: s_lshr_b32 s4, s21, 16 +; SI-NEXT: v_writelane_b32 v62, s4, 0 +; SI-NEXT: s_lshr_b32 s4, s21, 8 +; SI-NEXT: v_writelane_b32 v61, s4, 63 +; SI-NEXT: s_lshr_b32 s4, s23, 24 +; SI-NEXT: v_writelane_b32 v61, s4, 62 +; SI-NEXT: s_lshr_b32 s4, s23, 16 +; SI-NEXT: v_writelane_b32 v61, s4, 61 +; SI-NEXT: s_lshr_b32 s4, s23, 8 +; SI-NEXT: v_writelane_b32 v61, s4, 60 +; SI-NEXT: s_lshr_b32 s4, s25, 24 +; SI-NEXT: v_writelane_b32 v61, s4, 59 +; SI-NEXT: s_lshr_b32 s4, s25, 16 +; SI-NEXT: v_writelane_b32 v61, s4, 58 +; SI-NEXT: s_lshr_b32 s4, s25, 8 +; SI-NEXT: v_writelane_b32 v61, s4, 57 +; SI-NEXT: s_lshr_b32 s4, s41, 24 +; SI-NEXT: v_writelane_b32 v61, s4, 56 +; SI-NEXT: s_lshr_b32 s4, s41, 16 +; SI-NEXT: v_writelane_b32 v61, s4, 55 +; SI-NEXT: s_lshr_b32 s4, s41, 8 +; SI-NEXT: v_writelane_b32 v61, s4, 54 +; SI-NEXT: s_lshr_b32 s4, s43, 24 +; SI-NEXT: v_writelane_b32 v61, s4, 53 +; SI-NEXT: s_lshr_b32 s4, s43, 16 +; SI-NEXT: v_writelane_b32 v61, s4, 52 +; SI-NEXT: s_lshr_b32 s4, s43, 8 +; SI-NEXT: v_writelane_b32 v61, s4, 51 +; SI-NEXT: s_lshr_b32 s4, s45, 24 +; SI-NEXT: v_writelane_b32 v61, s4, 50 +; SI-NEXT: s_lshr_b32 s4, s45, 16 +; SI-NEXT: v_writelane_b32 v61, s4, 49 +; SI-NEXT: s_lshr_b32 s4, s45, 8 +; SI-NEXT: v_writelane_b32 v61, s4, 48 +; SI-NEXT: s_lshr_b32 s4, s47, 24 +; SI-NEXT: v_writelane_b32 v61, s4, 47 +; SI-NEXT: s_lshr_b32 s4, s47, 16 +; SI-NEXT: v_writelane_b32 v61, s4, 46 +; SI-NEXT: s_lshr_b32 s4, s47, 8 +; SI-NEXT: v_writelane_b32 v61, s4, 45 +; SI-NEXT: s_lshr_b32 s4, s57, 16 +; SI-NEXT: v_writelane_b32 v61, s4, 44 +; SI-NEXT: s_lshr_b32 s4, s57, 8 +; SI-NEXT: v_writelane_b32 v61, s4, 43 +; SI-NEXT: s_lshr_b32 s4, s59, 8 +; SI-NEXT: v_writelane_b32 v61, s4, 42 +; SI-NEXT: s_lshr_b64 s[4:5], s[6:7], 24 +; SI-NEXT: v_writelane_b32 v61, s4, 40 +; SI-NEXT: v_writelane_b32 v61, s5, 41 +; SI-NEXT: s_lshr_b64 s[4:5], s[6:7], 16 +; SI-NEXT: v_writelane_b32 v61, s4, 38 +; SI-NEXT: v_writelane_b32 v61, s5, 39 +; SI-NEXT: s_lshr_b64 s[4:5], s[6:7], 8 +; SI-NEXT: v_writelane_b32 v61, s4, 36 +; SI-NEXT: v_writelane_b32 v61, s5, 37 +; SI-NEXT: s_lshr_b64 s[4:5], s[8:9], 24 +; SI-NEXT: v_writelane_b32 v61, s4, 34 +; SI-NEXT: v_writelane_b32 v61, s5, 35 +; SI-NEXT: s_lshr_b64 s[4:5], s[8:9], 16 +; SI-NEXT: v_writelane_b32 v61, s4, 32 +; SI-NEXT: v_writelane_b32 v61, s5, 33 +; SI-NEXT: s_lshr_b64 s[4:5], s[8:9], 8 +; SI-NEXT: v_writelane_b32 v61, s4, 30 +; SI-NEXT: v_writelane_b32 v61, s5, 31 +; SI-NEXT: s_lshr_b64 s[4:5], s[10:11], 8 +; SI-NEXT: v_writelane_b32 v61, s4, 28 +; SI-NEXT: v_writelane_b32 v61, s5, 29 +; SI-NEXT: s_lshr_b64 s[4:5], s[12:13], 8 +; SI-NEXT: v_writelane_b32 v61, s4, 26 +; SI-NEXT: v_writelane_b32 v61, s5, 27 +; SI-NEXT: s_lshr_b64 s[4:5], s[14:15], 8 +; SI-NEXT: v_writelane_b32 v61, s4, 24 +; SI-NEXT: v_writelane_b32 v61, s5, 25 +; SI-NEXT: s_lshr_b64 s[4:5], s[16:17], 8 +; SI-NEXT: v_writelane_b32 v61, s4, 22 +; SI-NEXT: v_writelane_b32 v61, s5, 23 +; SI-NEXT: s_lshr_b64 s[4:5], s[18:19], 24 +; SI-NEXT: v_writelane_b32 v61, s4, 20 +; SI-NEXT: v_writelane_b32 v61, s5, 21 +; SI-NEXT: s_lshr_b64 s[4:5], s[18:19], 8 +; SI-NEXT: v_writelane_b32 v61, s4, 18 +; SI-NEXT: v_writelane_b32 v61, s5, 19 +; SI-NEXT: s_lshr_b64 s[4:5], s[20:21], 8 +; SI-NEXT: v_writelane_b32 v61, s4, 16 +; SI-NEXT: v_writelane_b32 v61, s5, 17 +; SI-NEXT: s_lshr_b64 s[4:5], s[22:23], 8 +; SI-NEXT: v_writelane_b32 v61, s4, 14 +; SI-NEXT: v_writelane_b32 v61, s5, 15 +; SI-NEXT: s_lshr_b64 s[4:5], s[24:25], 8 +; SI-NEXT: v_writelane_b32 v61, s4, 12 +; SI-NEXT: v_writelane_b32 v61, s5, 13 +; SI-NEXT: s_lshr_b64 s[4:5], s[40:41], 8 +; SI-NEXT: v_writelane_b32 v61, s4, 10 +; SI-NEXT: v_writelane_b32 v61, s5, 11 +; SI-NEXT: s_lshr_b64 s[4:5], s[42:43], 8 +; SI-NEXT: v_writelane_b32 v61, s4, 8 +; SI-NEXT: v_writelane_b32 v61, s5, 9 +; SI-NEXT: s_lshr_b64 s[4:5], s[44:45], 8 +; SI-NEXT: v_writelane_b32 v61, s4, 6 +; SI-NEXT: v_writelane_b32 v61, s5, 7 +; SI-NEXT: s_lshr_b64 s[4:5], s[46:47], 8 +; SI-NEXT: v_writelane_b32 v61, s4, 4 +; SI-NEXT: v_writelane_b32 v61, s5, 5 +; SI-NEXT: s_lshr_b64 s[4:5], s[56:57], 8 +; SI-NEXT: v_writelane_b32 v61, s4, 2 +; SI-NEXT: v_writelane_b32 v61, s5, 3 +; SI-NEXT: s_lshr_b64 s[4:5], s[58:59], 24 +; SI-NEXT: v_writelane_b32 v61, s4, 0 +; SI-NEXT: s_lshr_b32 s27, s7, 16 +; SI-NEXT: s_lshr_b32 s29, s7, 8 +; SI-NEXT: s_lshr_b32 s61, s9, 16 +; SI-NEXT: s_lshr_b32 s26, s9, 8 +; SI-NEXT: s_lshr_b32 s28, s11, 8 +; SI-NEXT: s_lshr_b32 s60, s57, 24 +; SI-NEXT: s_lshr_b32 s96, s59, 24 +; SI-NEXT: s_lshr_b32 s97, s59, 16 +; SI-NEXT: s_lshr_b64 s[62:63], s[10:11], 24 +; SI-NEXT: s_lshr_b64 s[72:73], s[10:11], 16 +; SI-NEXT: s_lshr_b64 s[74:75], s[12:13], 24 +; SI-NEXT: s_lshr_b64 s[76:77], s[12:13], 16 +; SI-NEXT: s_lshr_b64 s[78:79], s[14:15], 24 +; SI-NEXT: s_lshr_b64 s[88:89], s[14:15], 16 +; SI-NEXT: s_lshr_b64 s[90:91], s[16:17], 24 +; SI-NEXT: s_lshr_b64 s[92:93], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[94:95], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[30:31], s[20:21], 24 +; SI-NEXT: s_lshr_b64 s[34:35], s[20:21], 16 +; SI-NEXT: s_lshr_b64 s[36:37], s[22:23], 24 +; SI-NEXT: s_lshr_b64 s[38:39], s[22:23], 16 +; SI-NEXT: s_lshr_b64 s[48:49], s[24:25], 24 +; SI-NEXT: s_lshr_b64 s[50:51], s[24:25], 16 +; SI-NEXT: s_lshr_b64 s[52:53], s[40:41], 24 +; SI-NEXT: s_lshr_b64 s[54:55], s[40:41], 16 ; SI-NEXT: s_lshr_b64 s[64:65], s[42:43], 24 ; SI-NEXT: s_lshr_b64 s[66:67], s[42:43], 16 -; SI-NEXT: s_lshr_b64 s[68:69], s[42:43], 8 -; SI-NEXT: s_lshr_b64 s[70:71], s[44:45], 24 -; SI-NEXT: s_lshr_b64 s[80:81], s[44:45], 16 -; SI-NEXT: s_lshr_b64 s[82:83], s[44:45], 8 -; SI-NEXT: s_lshr_b64 s[84:85], s[28:29], 24 -; SI-NEXT: s_lshr_b64 s[86:87], s[28:29], 16 -; SI-NEXT: s_lshr_b64 s[96:97], s[28:29], 8 -; SI-NEXT: s_lshr_b64 s[98:99], s[26:27], 24 -; SI-NEXT: s_lshr_b64 s[46:47], s[26:27], 16 -; SI-NEXT: s_lshr_b64 s[56:57], s[26:27], 8 -; SI-NEXT: s_lshr_b64 s[58:59], s[24:25], 24 -; SI-NEXT: s_lshr_b64 s[60:61], s[24:25], 16 -; SI-NEXT: s_lshr_b64 s[62:63], s[24:25], 8 -; SI-NEXT: s_lshr_b64 s[72:73], s[22:23], 24 -; SI-NEXT: s_lshr_b64 s[74:75], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[76:77], s[22:23], 8 -; SI-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 -; SI-NEXT: s_lshr_b64 s[88:89], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[90:91], s[20:21], 8 -; SI-NEXT: s_lshr_b64 s[92:93], s[18:19], 24 -; SI-NEXT: s_lshr_b64 s[94:95], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[30:31], s[18:19], 8 -; SI-NEXT: s_lshr_b64 s[34:35], s[16:17], 24 -; SI-NEXT: s_lshr_b64 s[36:37], s[16:17], 16 -; SI-NEXT: s_lshr_b64 s[38:39], s[16:17], 8 +; SI-NEXT: s_lshr_b64 s[68:69], s[44:45], 24 +; SI-NEXT: s_lshr_b64 s[70:71], s[44:45], 16 +; SI-NEXT: s_lshr_b64 s[80:81], s[46:47], 24 +; SI-NEXT: s_lshr_b64 s[82:83], s[46:47], 16 +; SI-NEXT: s_lshr_b64 s[84:85], s[56:57], 24 +; SI-NEXT: s_lshr_b64 s[86:87], s[56:57], 16 +; SI-NEXT: v_writelane_b32 v61, s5, 1 +; SI-NEXT: s_lshr_b64 s[98:99], s[58:59], 16 +; SI-NEXT: s_lshr_b64 s[4:5], s[58:59], 8 ; SI-NEXT: s_cbranch_execnz .LBB37_4 ; SI-NEXT: .LBB37_2: ; %cmp.true -; SI-NEXT: v_add_f32_e64 v2, s5, 1.0 -; SI-NEXT: v_add_f32_e64 v1, s4, 1.0 -; SI-NEXT: v_lshr_b64 v[13:14], v[1:2], 24 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[1:2], 16 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[1:2], 8 -; SI-NEXT: v_add_f32_e64 v4, s7, 1.0 -; SI-NEXT: v_add_f32_e64 v3, s6, 1.0 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[3:4], 24 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[3:4], 16 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[3:4], 8 -; SI-NEXT: v_add_f32_e64 v6, s9, 1.0 -; SI-NEXT: v_add_f32_e64 v5, s8, 1.0 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[5:6], 24 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[5:6], 16 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[5:6], 8 -; SI-NEXT: v_add_f32_e64 v8, s11, 1.0 -; SI-NEXT: v_add_f32_e64 v7, s10, 1.0 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[7:8], 24 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[7:8], 16 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[7:8], 8 -; SI-NEXT: v_add_f32_e64 v10, s13, 1.0 -; SI-NEXT: v_add_f32_e64 v9, s12, 1.0 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[9:10], 24 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[9:10], 16 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[9:10], 8 -; SI-NEXT: v_add_f32_e64 v12, s15, 1.0 -; SI-NEXT: v_add_f32_e64 v11, s14, 1.0 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[11:12], 24 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[11:12], 16 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[11:12], 8 -; SI-NEXT: v_add_f32_e64 v16, s41, 1.0 -; SI-NEXT: v_add_f32_e64 v15, s40, 1.0 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[15:16], 24 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[15:16], 16 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[15:16], 8 -; SI-NEXT: v_add_f32_e64 v21, s43, 1.0 -; SI-NEXT: v_add_f32_e64 v20, s42, 1.0 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[20:21], 24 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[20:21], 16 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[20:21], 8 -; SI-NEXT: v_add_f32_e64 v26, s45, 1.0 -; SI-NEXT: v_add_f32_e64 v25, s44, 1.0 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[25:26], 24 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[25:26], 16 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[25:26], 8 -; SI-NEXT: v_add_f32_e64 v30, s29, 1.0 -; SI-NEXT: v_add_f32_e64 v29, s28, 1.0 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[29:30], 24 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[29:30], 16 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[29:30], 8 -; SI-NEXT: v_add_f32_e64 v36, s27, 1.0 -; SI-NEXT: v_add_f32_e64 v35, s26, 1.0 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[35:36], 24 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[35:36], 16 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[35:36], 8 -; SI-NEXT: v_add_f32_e64 v49, s25, 1.0 -; SI-NEXT: v_add_f32_e64 v48, s24, 1.0 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[48:49], 24 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[13:14], v[48:49], 16 -; SI-NEXT: v_lshrrev_b32_e32 v14, 24, v2 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v2 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 8, v2 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 24, v4 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v4 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 8, v4 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 24, v6 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v6 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: v_add_f32_e64 v1, s14, 1.0 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; SI-NEXT: v_readfirstlane_b32 s14, v1 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 8, v6 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; SI-NEXT: v_add_f32_e64 v1, s12, 1.0 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; SI-NEXT: v_readfirstlane_b32 s12, v1 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 24, v8 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; SI-NEXT: v_add_f32_e64 v1, s10, 1.0 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; SI-NEXT: v_readfirstlane_b32 s10, v1 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v8 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; SI-NEXT: v_add_f32_e64 v1, s8, 1.0 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; SI-NEXT: v_readfirstlane_b32 s8, v1 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 8, v8 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; SI-NEXT: v_add_f32_e64 v1, s7, 1.0 +; SI-NEXT: v_add_f32_e64 v2, s6, 1.0 +; SI-NEXT: v_add_f32_e64 v13, s19, 1.0 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: v_readfirstlane_b32 s6, v2 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 24, v10 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 24, v1 +; SI-NEXT: v_add_f32_e64 v15, s21, 1.0 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v10 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v13 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 8, v10 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 24, v15 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 24, v12 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v15 +; SI-NEXT: v_add_f32_e64 v17, s23, 1.0 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v12 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v15 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 8, v12 -; SI-NEXT: v_lshr_b64 v[17:18], v[48:49], 8 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 24, v17 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 24, v16 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v17 +; SI-NEXT: v_add_f32_e64 v19, s25, 1.0 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v16 -; SI-NEXT: v_add_f32_e64 v53, s23, 1.0 -; SI-NEXT: v_add_f32_e64 v52, s22, 1.0 -; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v17 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 8, v16 -; SI-NEXT: v_lshr_b64 v[17:18], v[52:53], 24 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 24, v19 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 24, v21 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v19 +; SI-NEXT: v_add_f32_e64 v21, s41, 1.0 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v21 -; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v19 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 8, v21 -; SI-NEXT: v_lshr_b64 v[17:18], v[52:53], 16 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 24, v21 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 24, v26 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v21 +; SI-NEXT: v_add_f32_e64 v37, s59, 1.0 +; SI-NEXT: v_add_f32_e64 v48, s58, 1.0 +; SI-NEXT: v_add_f32_e64 v32, s57, 1.0 +; SI-NEXT: v_add_f32_e64 v36, s56, 1.0 +; SI-NEXT: v_add_f32_e64 v29, s47, 1.0 +; SI-NEXT: v_add_f32_e64 v31, s46, 1.0 +; SI-NEXT: v_add_f32_e64 v25, s45, 1.0 +; SI-NEXT: v_add_f32_e64 v27, s44, 1.0 +; SI-NEXT: v_add_f32_e64 v23, s43, 1.0 +; SI-NEXT: v_add_f32_e64 v24, s42, 1.0 +; SI-NEXT: v_add_f32_e64 v22, s40, 1.0 +; SI-NEXT: v_add_f32_e64 v20, s24, 1.0 +; SI-NEXT: v_add_f32_e64 v18, s22, 1.0 +; SI-NEXT: v_add_f32_e64 v16, s20, 1.0 +; SI-NEXT: v_add_f32_e64 v14, s18, 1.0 +; SI-NEXT: v_add_f32_e64 v11, s17, 1.0 +; SI-NEXT: v_add_f32_e64 v12, s16, 1.0 +; SI-NEXT: v_add_f32_e64 v9, s15, 1.0 +; SI-NEXT: v_add_f32_e64 v7, s13, 1.0 +; SI-NEXT: v_add_f32_e64 v5, s11, 1.0 +; SI-NEXT: v_add_f32_e64 v3, s9, 1.0 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v21 +; SI-NEXT: v_readfirstlane_b32 s4, v48 +; SI-NEXT: v_readfirstlane_b32 s5, v37 +; SI-NEXT: v_readfirstlane_b32 s56, v36 +; SI-NEXT: v_readfirstlane_b32 s57, v32 +; SI-NEXT: v_readfirstlane_b32 s46, v31 +; SI-NEXT: v_readfirstlane_b32 s47, v29 +; SI-NEXT: v_readfirstlane_b32 s44, v27 +; SI-NEXT: v_readfirstlane_b32 s45, v25 +; SI-NEXT: v_readfirstlane_b32 s42, v24 +; SI-NEXT: v_readfirstlane_b32 s43, v23 +; SI-NEXT: v_readfirstlane_b32 s40, v22 +; SI-NEXT: v_readfirstlane_b32 s41, v21 +; SI-NEXT: v_readfirstlane_b32 s24, v20 +; SI-NEXT: v_readfirstlane_b32 s25, v19 +; SI-NEXT: v_readfirstlane_b32 s22, v18 +; SI-NEXT: v_readfirstlane_b32 s23, v17 +; SI-NEXT: v_readfirstlane_b32 s20, v16 +; SI-NEXT: v_readfirstlane_b32 s21, v15 +; SI-NEXT: v_readfirstlane_b32 s18, v14 +; SI-NEXT: v_readfirstlane_b32 s19, v13 +; SI-NEXT: v_readfirstlane_b32 s16, v12 +; SI-NEXT: v_readfirstlane_b32 s17, v11 +; SI-NEXT: v_readfirstlane_b32 s15, v9 +; SI-NEXT: v_readfirstlane_b32 s13, v7 +; SI-NEXT: v_readfirstlane_b32 s11, v5 +; SI-NEXT: v_readfirstlane_b32 s9, v3 +; SI-NEXT: v_readfirstlane_b32 s7, v1 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v2, 24, v23 +; SI-NEXT: s_lshr_b64 s[26:27], s[6:7], 24 +; SI-NEXT: s_lshr_b64 s[28:29], s[6:7], 16 +; SI-NEXT: s_lshr_b64 s[6:7], s[6:7], 8 +; SI-NEXT: s_lshr_b64 s[58:59], s[8:9], 24 +; SI-NEXT: s_lshr_b64 s[60:61], s[8:9], 16 +; SI-NEXT: s_lshr_b64 s[8:9], s[8:9], 8 +; SI-NEXT: s_lshr_b64 s[62:63], s[10:11], 24 +; SI-NEXT: s_lshr_b64 s[72:73], s[10:11], 16 +; SI-NEXT: s_lshr_b64 s[10:11], s[10:11], 8 +; SI-NEXT: s_lshr_b64 s[74:75], s[12:13], 24 +; SI-NEXT: s_lshr_b64 s[76:77], s[12:13], 16 +; SI-NEXT: s_lshr_b64 s[12:13], s[12:13], 8 +; SI-NEXT: s_lshr_b64 s[78:79], s[14:15], 24 +; SI-NEXT: s_lshr_b64 s[88:89], s[14:15], 16 +; SI-NEXT: s_lshr_b64 s[14:15], s[14:15], 8 +; SI-NEXT: s_lshr_b64 s[90:91], s[16:17], 24 +; SI-NEXT: s_lshr_b64 s[92:93], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[16:17], s[16:17], 8 +; SI-NEXT: s_lshr_b64 s[94:95], s[18:19], 24 +; SI-NEXT: s_lshr_b64 s[96:97], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[18:19], s[18:19], 8 +; SI-NEXT: s_lshr_b64 s[30:31], s[20:21], 24 +; SI-NEXT: s_lshr_b64 s[34:35], s[20:21], 16 +; SI-NEXT: s_lshr_b64 s[20:21], s[20:21], 8 +; SI-NEXT: s_lshr_b64 s[36:37], s[22:23], 24 +; SI-NEXT: s_lshr_b64 s[38:39], s[22:23], 16 +; SI-NEXT: s_lshr_b64 s[22:23], s[22:23], 8 +; SI-NEXT: s_lshr_b64 s[48:49], s[24:25], 24 +; SI-NEXT: s_lshr_b64 s[50:51], s[24:25], 16 +; SI-NEXT: s_lshr_b64 s[24:25], s[24:25], 8 +; SI-NEXT: s_lshr_b64 s[52:53], s[40:41], 24 +; SI-NEXT: s_lshr_b64 s[54:55], s[40:41], 16 +; SI-NEXT: s_lshr_b64 s[40:41], s[40:41], 8 +; SI-NEXT: s_lshr_b64 s[64:65], s[42:43], 24 +; SI-NEXT: s_lshr_b64 s[66:67], s[42:43], 16 +; SI-NEXT: s_lshr_b64 s[42:43], s[42:43], 8 +; SI-NEXT: s_lshr_b64 s[68:69], s[44:45], 24 +; SI-NEXT: s_lshr_b64 s[70:71], s[44:45], 16 +; SI-NEXT: s_lshr_b64 s[44:45], s[44:45], 8 +; SI-NEXT: s_lshr_b64 s[80:81], s[46:47], 24 +; SI-NEXT: s_lshr_b64 s[82:83], s[46:47], 16 +; SI-NEXT: s_lshr_b64 s[46:47], s[46:47], 8 +; SI-NEXT: s_lshr_b64 s[84:85], s[56:57], 24 +; SI-NEXT: s_lshr_b64 s[86:87], s[56:57], 16 +; SI-NEXT: s_lshr_b64 s[56:57], s[56:57], 8 +; SI-NEXT: s_lshr_b64 vcc, s[4:5], 24 +; SI-NEXT: s_lshr_b64 s[98:99], s[4:5], 16 +; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 8 +; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v1 +; SI-NEXT: v_lshrrev_b32_e32 v41, 8, v1 +; SI-NEXT: v_lshrrev_b32_e32 v42, 24, v3 +; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v3 +; SI-NEXT: v_lshrrev_b32_e32 v44, 8, v3 +; SI-NEXT: v_lshrrev_b32_e32 v45, 24, v5 +; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v5 +; SI-NEXT: v_lshrrev_b32_e32 v47, 8, v5 +; SI-NEXT: v_lshrrev_b32_e32 v56, 24, v7 +; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v7 +; SI-NEXT: v_lshrrev_b32_e32 v58, 8, v7 +; SI-NEXT: v_lshrrev_b32_e32 v59, 24, v9 +; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v9 +; SI-NEXT: v_lshrrev_b32_e32 v26, 8, v9 +; SI-NEXT: v_lshrrev_b32_e32 v28, 24, v11 +; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v11 +; SI-NEXT: v_lshrrev_b32_e32 v33, 8, v11 +; SI-NEXT: v_lshrrev_b32_e32 v34, 24, v13 +; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v13 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v26 -; SI-NEXT: v_add_f32_e64 v41, s21, 1.0 -; SI-NEXT: v_add_f32_e64 v40, s20, 1.0 -; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 8, v26 -; SI-NEXT: v_add_f32_e64 v58, s17, 1.0 -; SI-NEXT: v_add_f32_e64 v57, s16, 1.0 -; SI-NEXT: v_add_f32_e64 v46, s19, 1.0 -; SI-NEXT: v_add_f32_e64 v45, s18, 1.0 -; SI-NEXT: v_lshr_b64 v[17:18], v[52:53], 8 -; SI-NEXT: v_lshr_b64 v[31:32], v[40:41], 16 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 24, v30 -; SI-NEXT: v_lshr_b64 v[32:33], v[40:41], 8 -; SI-NEXT: v_lshr_b64 v[37:38], v[45:46], 16 -; SI-NEXT: v_lshr_b64 v[42:43], v[57:58], 16 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v30 -; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill -; SI-NEXT: v_lshr_b64 v[27:28], v[40:41], 24 -; SI-NEXT: v_lshr_b64 v[33:34], v[45:46], 24 -; SI-NEXT: v_lshr_b64 v[38:39], v[45:46], 8 -; SI-NEXT: v_lshr_b64 v[50:51], v[57:58], 24 -; SI-NEXT: v_lshr_b64 v[43:44], v[57:58], 8 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 8, v30 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill -; SI-NEXT: v_lshrrev_b32_e32 v55, 24, v36 -; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v36 -; SI-NEXT: v_lshrrev_b32_e32 v47, 8, v36 -; SI-NEXT: v_lshrrev_b32_e32 v56, 24, v49 -; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v49 -; SI-NEXT: v_lshrrev_b32_e32 v60, 8, v49 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v14, 24, v53 -; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v53 -; SI-NEXT: v_lshrrev_b32_e32 v17, 8, v53 -; SI-NEXT: v_lshrrev_b32_e32 v24, 24, v41 -; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v41 -; SI-NEXT: v_lshrrev_b32_e32 v34, 8, v41 -; SI-NEXT: v_lshrrev_b32_e32 v18, 24, v46 -; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v46 -; SI-NEXT: v_lshrrev_b32_e32 v23, 8, v46 -; SI-NEXT: v_lshrrev_b32_e32 v39, 24, v58 -; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v58 -; SI-NEXT: v_lshrrev_b32_e32 v54, 8, v58 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v23 +; SI-NEXT: v_lshrrev_b32_e32 v38, 8, v23 +; SI-NEXT: v_lshrrev_b32_e32 v39, 24, v25 +; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v25 +; SI-NEXT: v_lshrrev_b32_e32 v4, 8, v25 +; SI-NEXT: v_lshrrev_b32_e32 v50, 24, v29 +; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v29 +; SI-NEXT: v_lshrrev_b32_e32 v6, 8, v29 +; SI-NEXT: v_lshrrev_b32_e32 v52, 24, v32 +; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v32 +; SI-NEXT: v_lshrrev_b32_e32 v53, 8, v32 +; SI-NEXT: v_lshrrev_b32_e32 v54, 24, v37 +; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v37 +; SI-NEXT: v_lshrrev_b32_e32 v10, 8, v37 ; SI-NEXT: s_branch .LBB37_5 ; SI-NEXT: .LBB37_3: -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 0 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 1 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr61 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 0 +; SI-NEXT: v_writelane_b32 v61, s61, 1 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 2 +; SI-NEXT: v_writelane_b32 v61, s61, 3 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 4 +; SI-NEXT: v_writelane_b32 v61, s61, 5 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 6 +; SI-NEXT: v_writelane_b32 v61, s61, 7 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 8 +; SI-NEXT: v_writelane_b32 v61, s61, 9 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 10 +; SI-NEXT: v_writelane_b32 v61, s61, 11 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 12 +; SI-NEXT: v_writelane_b32 v61, s61, 13 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 14 +; SI-NEXT: v_writelane_b32 v61, s61, 15 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 16 +; SI-NEXT: v_writelane_b32 v61, s61, 17 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 18 +; SI-NEXT: v_writelane_b32 v61, s61, 19 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 20 +; SI-NEXT: v_writelane_b32 v61, s61, 21 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 22 +; SI-NEXT: v_writelane_b32 v61, s61, 23 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 24 +; SI-NEXT: v_writelane_b32 v61, s61, 25 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 26 +; SI-NEXT: v_writelane_b32 v61, s61, 27 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 28 +; SI-NEXT: v_writelane_b32 v61, s61, 29 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 30 +; SI-NEXT: v_writelane_b32 v61, s61, 31 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 32 +; SI-NEXT: v_writelane_b32 v61, s61, 33 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 34 +; SI-NEXT: v_writelane_b32 v61, s61, 35 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 36 +; SI-NEXT: v_writelane_b32 v61, s61, 37 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 38 +; SI-NEXT: v_writelane_b32 v61, s61, 39 +; SI-NEXT: ; implicit-def: $sgpr60 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr97 +; SI-NEXT: ; implicit-def: $sgpr96 +; SI-NEXT: ; implicit-def: $sgpr28 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr29 +; SI-NEXT: ; implicit-def: $sgpr27 +; SI-NEXT: ; kill: killed $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s60, 40 +; SI-NEXT: v_writelane_b32 v61, s61, 41 +; SI-NEXT: ; implicit-def: $sgpr98 +; SI-NEXT: ; implicit-def: $sgpr86 +; SI-NEXT: ; implicit-def: $sgpr84 +; SI-NEXT: ; implicit-def: $sgpr82 +; SI-NEXT: ; implicit-def: $sgpr80 +; SI-NEXT: ; implicit-def: $sgpr70 +; SI-NEXT: ; implicit-def: $sgpr68 +; SI-NEXT: ; implicit-def: $sgpr66 +; SI-NEXT: ; implicit-def: $sgpr64 +; SI-NEXT: ; implicit-def: $sgpr54 +; SI-NEXT: ; implicit-def: $sgpr52 +; SI-NEXT: ; implicit-def: $sgpr50 ; SI-NEXT: ; implicit-def: $sgpr48 ; SI-NEXT: ; implicit-def: $sgpr38 ; SI-NEXT: ; implicit-def: $sgpr36 @@ -44913,633 +44622,335 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; SI-NEXT: ; implicit-def: $sgpr72 ; SI-NEXT: ; implicit-def: $sgpr62 ; SI-NEXT: ; implicit-def: $sgpr60 -; SI-NEXT: ; implicit-def: $sgpr58 -; SI-NEXT: ; implicit-def: $sgpr56 -; SI-NEXT: ; implicit-def: $sgpr98 -; SI-NEXT: ; implicit-def: $sgpr96 -; SI-NEXT: ; implicit-def: $sgpr86 -; SI-NEXT: ; implicit-def: $sgpr84 -; SI-NEXT: ; implicit-def: $sgpr82 -; SI-NEXT: ; implicit-def: $sgpr80 -; SI-NEXT: ; implicit-def: $sgpr70 -; SI-NEXT: ; implicit-def: $sgpr68 -; SI-NEXT: ; implicit-def: $sgpr66 -; SI-NEXT: ; implicit-def: $sgpr64 -; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; implicit-def: $sgpr52 -; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 2 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 3 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 4 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 5 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 6 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 7 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 8 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 9 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 10 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 11 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 12 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 13 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 14 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 15 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 16 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 17 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 18 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 19 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 20 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 21 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 22 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 23 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 24 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 25 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 26 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 27 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 28 -; SI-NEXT: v_writelane_b32 v61, s49, 29 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 30 -; SI-NEXT: v_writelane_b32 v61, s49, 31 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 32 -; SI-NEXT: v_writelane_b32 v61, s49, 33 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr48 ; SI-NEXT: s_branch .LBB37_2 ; SI-NEXT: .LBB37_4: -; SI-NEXT: v_mov_b32_e32 v1, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 34 -; SI-NEXT: v_mov_b32_e32 v54, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 35 -; SI-NEXT: v_mov_b32_e32 v51, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 36 -; SI-NEXT: v_mov_b32_e32 v39, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 37 -; SI-NEXT: v_mov_b32_e32 v23, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 38 -; SI-NEXT: v_mov_b32_e32 v22, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 39 -; SI-NEXT: v_mov_b32_e32 v18, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 40 -; SI-NEXT: v_mov_b32_e32 v34, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 41 -; SI-NEXT: v_mov_b32_e32 v28, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 42 -; SI-NEXT: v_mov_b32_e32 v24, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 43 -; SI-NEXT: v_mov_b32_e32 v17, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 44 -; SI-NEXT: v_mov_b32_e32 v19, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 45 -; SI-NEXT: v_mov_b32_e32 v14, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 46 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v60, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 47 -; SI-NEXT: v_mov_b32_e32 v59, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 48 -; SI-NEXT: v_mov_b32_e32 v56, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 49 -; SI-NEXT: v_mov_b32_e32 v47, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 50 -; SI-NEXT: v_mov_b32_e32 v44, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 51 -; SI-NEXT: v_mov_b32_e32 v55, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 52 -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 53 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 54 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 55 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 56 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 57 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 58 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 59 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 60 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 61 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 62 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 63 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 0 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 1 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 2 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 3 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 4 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 5 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 6 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v1, s58 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload +; SI-NEXT: v_readlane_b32 s5, v61, 42 +; SI-NEXT: v_mov_b32_e32 v10, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 43 +; SI-NEXT: v_mov_b32_e32 v53, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 44 +; SI-NEXT: v_mov_b32_e32 v8, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 45 +; SI-NEXT: v_mov_b32_e32 v6, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 46 +; SI-NEXT: v_mov_b32_e32 v51, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 47 +; SI-NEXT: v_mov_b32_e32 v50, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 48 +; SI-NEXT: v_mov_b32_e32 v4, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 49 +; SI-NEXT: v_mov_b32_e32 v49, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 50 +; SI-NEXT: v_mov_b32_e32 v39, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 51 +; SI-NEXT: v_mov_b32_e32 v38, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 52 +; SI-NEXT: v_mov_b32_e32 v2, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 53 +; SI-NEXT: v_mov_b32_e32 v12, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 54 +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v12, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 55 +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v12, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 56 +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v12, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 57 +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v12, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 58 +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v12, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 59 +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v12, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 60 +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v12, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 61 +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v12, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 62 +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v12, s5 +; SI-NEXT: v_readlane_b32 s5, v61, 63 +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v12, s5 +; SI-NEXT: v_readlane_b32 s5, v62, 0 +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v12, s5 +; SI-NEXT: v_readlane_b32 s5, v62, 1 +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v12, s5 +; SI-NEXT: v_readlane_b32 s5, v62, 2 +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v12, s5 +; SI-NEXT: v_readlane_b32 s5, v62, 3 +; SI-NEXT: v_mov_b32_e32 v35, s5 +; SI-NEXT: v_readlane_b32 s5, v62, 4 +; SI-NEXT: v_mov_b32_e32 v34, s5 +; SI-NEXT: v_readlane_b32 s5, v62, 5 +; SI-NEXT: v_mov_b32_e32 v33, s5 +; SI-NEXT: v_readlane_b32 s5, v62, 6 +; SI-NEXT: v_mov_b32_e32 v30, s5 +; SI-NEXT: v_readlane_b32 s5, v62, 7 +; SI-NEXT: v_mov_b32_e32 v28, s5 +; SI-NEXT: v_readlane_b32 s5, v62, 8 +; SI-NEXT: v_mov_b32_e32 v26, s5 +; SI-NEXT: v_readlane_b32 s5, v62, 9 +; SI-NEXT: v_mov_b32_e32 v60, s5 +; SI-NEXT: v_readlane_b32 s5, v62, 10 +; SI-NEXT: v_mov_b32_e32 v59, s5 +; SI-NEXT: v_readlane_b32 s5, v62, 11 +; SI-NEXT: v_mov_b32_e32 v58, s5 +; SI-NEXT: v_readlane_b32 s5, v62, 12 +; SI-NEXT: v_mov_b32_e32 v57, s5 +; SI-NEXT: v_readlane_b32 s5, v62, 13 +; SI-NEXT: v_mov_b32_e32 v1, s14 +; SI-NEXT: v_mov_b32_e32 v56, s5 +; SI-NEXT: v_readlane_b32 s5, v62, 14 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 7 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v1, s12 +; SI-NEXT: v_mov_b32_e32 v46, s5 +; SI-NEXT: v_readlane_b32 s5, v62, 15 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 8 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v1, s10 +; SI-NEXT: v_mov_b32_e32 v45, s5 +; SI-NEXT: v_readlane_b32 s5, v62, 16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 9 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v1, s8 +; SI-NEXT: v_mov_b32_e32 v42, s5 +; SI-NEXT: v_readlane_b32 s5, v62, 17 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 10 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v1, s6 +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v12, s5 +; SI-NEXT: v_mov_b32_e32 v37, s59 +; SI-NEXT: v_mov_b32_e32 v32, s57 +; SI-NEXT: v_mov_b32_e32 v29, s47 +; SI-NEXT: v_mov_b32_e32 v25, s45 +; SI-NEXT: v_mov_b32_e32 v23, s43 +; SI-NEXT: v_mov_b32_e32 v21, s41 +; SI-NEXT: v_mov_b32_e32 v19, s25 +; SI-NEXT: v_mov_b32_e32 v17, s23 +; SI-NEXT: v_mov_b32_e32 v15, s21 +; SI-NEXT: v_mov_b32_e32 v13, s19 +; SI-NEXT: v_mov_b32_e32 v11, s17 +; SI-NEXT: v_mov_b32_e32 v9, s15 +; SI-NEXT: v_mov_b32_e32 v7, s13 +; SI-NEXT: v_mov_b32_e32 v5, s11 +; SI-NEXT: v_mov_b32_e32 v3, s9 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v1, s7 +; SI-NEXT: v_mov_b32_e32 v54, s96 +; SI-NEXT: v_mov_b32_e32 v52, s60 +; SI-NEXT: v_mov_b32_e32 v47, s28 +; SI-NEXT: v_mov_b32_e32 v44, s26 +; SI-NEXT: v_mov_b32_e32 v43, s61 +; SI-NEXT: v_mov_b32_e32 v41, s29 +; SI-NEXT: v_mov_b32_e32 v40, s27 +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 11 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v12, s16 +; SI-NEXT: v_mov_b32_e32 v14, s18 +; SI-NEXT: v_mov_b32_e32 v16, s20 +; SI-NEXT: v_mov_b32_e32 v18, s22 +; SI-NEXT: v_mov_b32_e32 v20, s24 +; SI-NEXT: v_mov_b32_e32 v22, s40 +; SI-NEXT: v_mov_b32_e32 v24, s42 +; SI-NEXT: v_mov_b32_e32 v27, s44 +; SI-NEXT: v_mov_b32_e32 v31, s46 +; SI-NEXT: v_mov_b32_e32 v36, s56 +; SI-NEXT: v_readlane_b32 s26, v61, 40 +; SI-NEXT: v_readlane_b32 s28, v61, 38 +; SI-NEXT: v_readlane_b32 s6, v61, 36 +; SI-NEXT: v_readlane_b32 s58, v61, 34 +; SI-NEXT: v_readlane_b32 s60, v61, 32 +; SI-NEXT: v_readlane_b32 s8, v61, 30 +; SI-NEXT: v_readlane_b32 s10, v61, 28 +; SI-NEXT: v_readlane_b32 s12, v61, 26 +; SI-NEXT: v_readlane_b32 s14, v61, 24 +; SI-NEXT: v_readlane_b32 s16, v61, 22 +; SI-NEXT: s_mov_b32 s96, s94 +; SI-NEXT: v_readlane_b32 s94, v61, 20 +; SI-NEXT: v_readlane_b32 s18, v61, 18 +; SI-NEXT: v_readlane_b32 s20, v61, 16 +; SI-NEXT: v_readlane_b32 s22, v61, 14 +; SI-NEXT: v_readlane_b32 s24, v61, 12 +; SI-NEXT: v_readlane_b32 s40, v61, 10 +; SI-NEXT: v_readlane_b32 s42, v61, 8 +; SI-NEXT: v_readlane_b32 s44, v61, 6 +; SI-NEXT: v_readlane_b32 s46, v61, 4 +; SI-NEXT: v_readlane_b32 s56, v61, 2 +; SI-NEXT: v_readlane_b32 vcc_lo, v61, 0 +; SI-NEXT: v_mov_b32_e32 v55, s97 +; SI-NEXT: v_readlane_b32 s27, v61, 41 +; SI-NEXT: v_readlane_b32 s29, v61, 39 +; SI-NEXT: v_readlane_b32 s7, v61, 37 +; SI-NEXT: v_readlane_b32 s59, v61, 35 +; SI-NEXT: v_readlane_b32 s61, v61, 33 +; SI-NEXT: v_readlane_b32 s9, v61, 31 +; SI-NEXT: v_readlane_b32 s11, v61, 29 +; SI-NEXT: v_readlane_b32 s13, v61, 27 +; SI-NEXT: v_readlane_b32 s15, v61, 25 +; SI-NEXT: v_readlane_b32 s17, v61, 23 +; SI-NEXT: v_readlane_b32 s95, v61, 21 +; SI-NEXT: v_readlane_b32 s19, v61, 19 +; SI-NEXT: v_readlane_b32 s21, v61, 17 +; SI-NEXT: v_readlane_b32 s23, v61, 15 +; SI-NEXT: v_readlane_b32 s25, v61, 13 +; SI-NEXT: v_readlane_b32 s41, v61, 11 +; SI-NEXT: v_readlane_b32 s43, v61, 9 +; SI-NEXT: v_readlane_b32 s45, v61, 7 +; SI-NEXT: v_readlane_b32 s47, v61, 5 +; SI-NEXT: v_readlane_b32 s57, v61, 3 +; SI-NEXT: v_readlane_b32 vcc_hi, v61, 1 +; SI-NEXT: .LBB37_5: ; %end +; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: v_and_b32_e32 v48, 0xff, v48 +; SI-NEXT: s_lshl_b32 s4, s4, 8 +; SI-NEXT: v_or_b32_e32 v48, s4, v48 +; SI-NEXT: s_and_b32 s4, s98, 0xff +; SI-NEXT: s_lshl_b32 s4, s4, 16 +; SI-NEXT: s_lshl_b32 s5, vcc_lo, 24 +; SI-NEXT: v_and_b32_e32 v48, 0xffff, v48 +; SI-NEXT: s_or_b32 s4, s5, s4 +; SI-NEXT: v_and_b32_e32 v37, 0xff, v37 +; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v10 +; SI-NEXT: v_or_b32_e32 v48, s4, v48 +; SI-NEXT: v_or_b32_e32 v10, v37, v10 +; SI-NEXT: v_and_b32_e32 v37, 0xff, v55 +; SI-NEXT: buffer_store_dword v48, v0, s[0:3], 0 offen +; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v37 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 12 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v48, 24, v54 +; SI-NEXT: v_or_b32_e32 v37, v48, v37 +; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10 +; SI-NEXT: v_or_b32_e32 v10, v10, v37 +; SI-NEXT: v_add_i32_e32 v37, vcc, 4, v0 +; SI-NEXT: buffer_store_dword v10, v37, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 13 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: v_and_b32_e32 v10, 0xff, v36 +; SI-NEXT: s_lshl_b32 s4, s56, 8 +; SI-NEXT: v_or_b32_e32 v10, s4, v10 +; SI-NEXT: s_and_b32 s4, s86, 0xff +; SI-NEXT: s_lshl_b32 s4, s4, 16 +; SI-NEXT: s_lshl_b32 s5, s84, 24 +; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10 +; SI-NEXT: s_or_b32 s4, s5, s4 +; SI-NEXT: v_or_b32_e32 v10, s4, v10 +; SI-NEXT: v_add_i32_e32 v36, vcc, 8, v0 +; SI-NEXT: buffer_store_dword v10, v36, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 14 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: v_and_b32_e32 v10, 0xff, v32 +; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v53 +; SI-NEXT: v_and_b32_e32 v8, 0xff, v8 +; SI-NEXT: v_or_b32_e32 v10, v10, v32 +; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; SI-NEXT: v_lshlrev_b32_e32 v32, 24, v52 +; SI-NEXT: v_or_b32_e32 v8, v32, v8 +; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10 +; SI-NEXT: v_or_b32_e32 v8, v10, v8 +; SI-NEXT: v_add_i32_e32 v10, vcc, 12, v0 +; SI-NEXT: buffer_store_dword v8, v10, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 15 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: v_and_b32_e32 v8, 0xff, v31 +; SI-NEXT: s_lshl_b32 s4, s46, 8 +; SI-NEXT: v_or_b32_e32 v8, s4, v8 +; SI-NEXT: s_and_b32 s4, s82, 0xff +; SI-NEXT: s_lshl_b32 s4, s4, 16 +; SI-NEXT: s_lshl_b32 s5, s80, 24 +; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8 +; SI-NEXT: s_or_b32 s4, s5, s4 +; SI-NEXT: v_or_b32_e32 v8, s4, v8 +; SI-NEXT: v_add_i32_e32 v10, vcc, 16, v0 +; SI-NEXT: buffer_store_dword v8, v10, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 16 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: v_and_b32_e32 v8, 0xff, v29 +; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6 +; SI-NEXT: v_or_b32_e32 v6, v8, v6 +; SI-NEXT: v_and_b32_e32 v8, 0xff, v51 +; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v50 +; SI-NEXT: v_or_b32_e32 v8, v10, v8 +; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6 +; SI-NEXT: v_or_b32_e32 v6, v6, v8 +; SI-NEXT: v_add_i32_e32 v8, vcc, 20, v0 +; SI-NEXT: buffer_store_dword v6, v8, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 17 -; SI-NEXT: v_mov_b32_e32 v2, s5 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: v_and_b32_e32 v6, 0xff, v27 +; SI-NEXT: s_lshl_b32 s4, s44, 8 +; SI-NEXT: v_or_b32_e32 v6, s4, v6 +; SI-NEXT: s_and_b32 s4, s70, 0xff +; SI-NEXT: s_lshl_b32 s4, s4, 16 +; SI-NEXT: s_lshl_b32 s5, s68, 24 +; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6 +; SI-NEXT: s_or_b32 s4, s5, s4 +; SI-NEXT: v_or_b32_e32 v6, s4, v6 +; SI-NEXT: v_add_i32_e32 v8, vcc, 24, v0 +; SI-NEXT: buffer_store_dword v6, v8, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 32 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: v_and_b32_e32 v6, 0xff, v25 +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: v_and_b32_e32 v6, 0xff, v49 +; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v39 +; SI-NEXT: v_or_b32_e32 v6, v8, v6 +; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4 +; SI-NEXT: v_or_b32_e32 v4, v4, v6 +; SI-NEXT: v_add_i32_e32 v6, vcc, 28, v0 +; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s48 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill -; SI-NEXT: v_readlane_b32 s5, v61, 33 -; SI-NEXT: v_readlane_b32 s4, v61, 30 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill -; SI-NEXT: v_readlane_b32 s5, v61, 31 -; SI-NEXT: v_readlane_b32 s4, v61, 28 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill -; SI-NEXT: v_readlane_b32 s5, v61, 29 -; SI-NEXT: v_readlane_b32 s4, v61, 26 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill -; SI-NEXT: v_readlane_b32 s5, v61, 27 -; SI-NEXT: v_readlane_b32 s4, v61, 24 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill -; SI-NEXT: v_readlane_b32 s5, v61, 25 -; SI-NEXT: v_readlane_b32 s4, v61, 22 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill -; SI-NEXT: v_readlane_b32 s5, v61, 23 -; SI-NEXT: v_readlane_b32 s4, v61, 20 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill -; SI-NEXT: v_readlane_b32 s5, v61, 21 -; SI-NEXT: v_readlane_b32 s4, v61, 18 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill -; SI-NEXT: v_readlane_b32 s5, v61, 19 -; SI-NEXT: v_readlane_b32 s4, v61, 16 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; SI-NEXT: v_readlane_b32 s5, v61, 17 -; SI-NEXT: v_readlane_b32 s4, v61, 14 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; SI-NEXT: v_readlane_b32 s5, v61, 15 -; SI-NEXT: v_readlane_b32 s4, v61, 12 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; SI-NEXT: v_readlane_b32 s5, v61, 13 -; SI-NEXT: v_readlane_b32 s4, v61, 10 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; SI-NEXT: v_readlane_b32 s5, v61, 11 -; SI-NEXT: v_readlane_b32 s4, v61, 8 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; SI-NEXT: v_readlane_b32 s5, v61, 9 -; SI-NEXT: v_readlane_b32 s4, v61, 6 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill -; SI-NEXT: v_readlane_b32 s5, v61, 7 -; SI-NEXT: v_readlane_b32 s4, v61, 4 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; SI-NEXT: v_readlane_b32 s5, v61, 5 -; SI-NEXT: v_readlane_b32 s4, v61, 2 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; SI-NEXT: v_readlane_b32 s5, v61, 3 -; SI-NEXT: v_readlane_b32 s4, v61, 0 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s4 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s50 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s52 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s54 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s64 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s66 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s68 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s70 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s80 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s82 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s84 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s86 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s96 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v13, s98 -; SI-NEXT: v_mov_b32_e32 v27, s62 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_mov_b32_e32 v13, s46 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v27, s72 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_mov_b32_e32 v13, s56 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v27, s74 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_mov_b32_e32 v13, s58 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v27, s76 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v57, s16 -; SI-NEXT: v_mov_b32_e32 v58, s17 -; SI-NEXT: v_mov_b32_e32 v45, s18 -; SI-NEXT: v_mov_b32_e32 v46, s19 -; SI-NEXT: v_mov_b32_e32 v40, s20 -; SI-NEXT: v_mov_b32_e32 v41, s21 -; SI-NEXT: v_mov_b32_e32 v52, s22 -; SI-NEXT: v_mov_b32_e32 v53, s23 -; SI-NEXT: v_mov_b32_e32 v48, s24 -; SI-NEXT: v_mov_b32_e32 v49, s25 -; SI-NEXT: v_mov_b32_e32 v35, s26 -; SI-NEXT: v_mov_b32_e32 v36, s27 -; SI-NEXT: v_mov_b32_e32 v29, s28 -; SI-NEXT: v_mov_b32_e32 v30, s29 -; SI-NEXT: v_mov_b32_e32 v25, s44 -; SI-NEXT: v_mov_b32_e32 v26, s45 -; SI-NEXT: v_mov_b32_e32 v20, s42 -; SI-NEXT: v_mov_b32_e32 v21, s43 -; SI-NEXT: v_mov_b32_e32 v15, s40 -; SI-NEXT: v_mov_b32_e32 v16, s41 -; SI-NEXT: v_mov_b32_e32 v11, s14 -; SI-NEXT: v_mov_b32_e32 v12, s15 -; SI-NEXT: v_mov_b32_e32 v9, s12 -; SI-NEXT: v_mov_b32_e32 v10, s13 -; SI-NEXT: v_mov_b32_e32 v7, s10 -; SI-NEXT: v_mov_b32_e32 v8, s11 -; SI-NEXT: v_mov_b32_e32 v5, s8 -; SI-NEXT: v_mov_b32_e32 v6, s9 -; SI-NEXT: v_mov_b32_e32 v3, s6 -; SI-NEXT: v_mov_b32_e32 v4, s7 -; SI-NEXT: v_readlane_b32 s5, v61, 1 -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_mov_b32_e32 v13, s60 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v27, s78 -; SI-NEXT: v_mov_b32_e32 v31, s88 -; SI-NEXT: v_mov_b32_e32 v32, s90 -; SI-NEXT: v_mov_b32_e32 v33, s92 -; SI-NEXT: v_mov_b32_e32 v37, s94 -; SI-NEXT: v_mov_b32_e32 v38, s30 -; SI-NEXT: v_mov_b32_e32 v50, s34 -; SI-NEXT: v_mov_b32_e32 v42, s36 -; SI-NEXT: v_mov_b32_e32 v43, s38 -; SI-NEXT: .LBB37_5: ; %end -; SI-NEXT: v_lshlrev_b32_e32 v43, 8, v43 -; SI-NEXT: v_and_b32_e32 v57, 0xff, v57 -; SI-NEXT: v_and_b32_e32 v42, 0xff, v42 -; SI-NEXT: v_or_b32_e32 v43, v57, v43 -; SI-NEXT: v_lshlrev_b32_e32 v50, 24, v50 -; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v42 -; SI-NEXT: v_or_b32_e32 v50, v50, v42 -; SI-NEXT: v_and_b32_e32 v42, 0xffff, v43 -; SI-NEXT: v_or_b32_e32 v50, v42, v50 -; SI-NEXT: buffer_store_dword v50, v0, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v50, 0xff, v58 -; SI-NEXT: v_lshlrev_b32_e32 v54, 8, v54 -; SI-NEXT: v_and_b32_e32 v51, 0xff, v51 -; SI-NEXT: v_or_b32_e32 v50, v50, v54 -; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v51 -; SI-NEXT: v_lshlrev_b32_e32 v39, 24, v39 -; SI-NEXT: v_or_b32_e32 v39, v39, v51 -; SI-NEXT: v_and_b32_e32 v50, 0xffff, v50 -; SI-NEXT: v_or_b32_e32 v39, v50, v39 -; SI-NEXT: v_add_i32_e32 v50, vcc, 4, v0 -; SI-NEXT: buffer_store_dword v39, v50, s[0:3], 0 offen -; SI-NEXT: v_lshlrev_b32_e32 v38, 8, v38 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v39, 0xff, v45 -; SI-NEXT: v_and_b32_e32 v37, 0xff, v37 -; SI-NEXT: v_or_b32_e32 v38, v39, v38 -; SI-NEXT: v_lshlrev_b32_e32 v33, 24, v33 -; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v37 -; SI-NEXT: v_or_b32_e32 v33, v33, v37 -; SI-NEXT: v_and_b32_e32 v37, 0xffff, v38 -; SI-NEXT: v_or_b32_e32 v33, v37, v33 -; SI-NEXT: v_add_i32_e32 v37, vcc, 8, v0 -; SI-NEXT: buffer_store_dword v33, v37, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v4, 0xff, v24 +; SI-NEXT: s_lshl_b32 s4, s42, 8 +; SI-NEXT: v_or_b32_e32 v4, s4, v4 +; SI-NEXT: s_and_b32 s4, s66, 0xff +; SI-NEXT: s_lshl_b32 s4, s4, 16 +; SI-NEXT: s_lshl_b32 s5, s64, 24 +; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4 +; SI-NEXT: s_or_b32 s4, s5, s4 +; SI-NEXT: v_or_b32_e32 v4, s4, v4 +; SI-NEXT: v_add_i32_e32 v6, vcc, 32, v0 +; SI-NEXT: buffer_store_dword v4, v6, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v33, 0xff, v46 -; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v23 -; SI-NEXT: v_and_b32_e32 v22, 0xff, v22 -; SI-NEXT: v_or_b32_e32 v23, v33, v23 -; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18 -; SI-NEXT: v_or_b32_e32 v18, v18, v22 -; SI-NEXT: v_and_b32_e32 v22, 0xffff, v23 -; SI-NEXT: v_or_b32_e32 v18, v22, v18 -; SI-NEXT: v_add_i32_e32 v22, vcc, 12, v0 -; SI-NEXT: buffer_store_dword v18, v22, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v32 -; SI-NEXT: v_and_b32_e32 v22, 0xff, v40 -; SI-NEXT: v_or_b32_e32 v18, v22, v18 -; SI-NEXT: v_and_b32_e32 v22, 0xff, v31 -; SI-NEXT: v_lshlrev_b32_e32 v23, 24, v27 -; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; SI-NEXT: v_or_b32_e32 v22, v23, v22 -; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18 -; SI-NEXT: v_or_b32_e32 v18, v18, v22 -; SI-NEXT: v_add_i32_e32 v22, vcc, 16, v0 -; SI-NEXT: buffer_store_dword v18, v22, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v18, 0xff, v41 -; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v34 -; SI-NEXT: v_or_b32_e32 v18, v18, v22 -; SI-NEXT: v_and_b32_e32 v22, 0xff, v28 -; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; SI-NEXT: v_lshlrev_b32_e32 v23, 24, v24 -; SI-NEXT: v_or_b32_e32 v22, v23, v22 -; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18 -; SI-NEXT: v_or_b32_e32 v18, v18, v22 -; SI-NEXT: v_add_i32_e32 v22, vcc, 20, v0 -; SI-NEXT: buffer_store_dword v18, v22, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload -; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14 -; SI-NEXT: v_and_b32_e32 v13, 0xff, v13 -; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; SI-NEXT: v_and_b32_e32 v11, 0xff, v11 -; SI-NEXT: v_and_b32_e32 v9, 0xff, v9 -; SI-NEXT: v_and_b32_e32 v7, 0xff, v7 -; SI-NEXT: v_and_b32_e32 v5, 0xff, v5 -; SI-NEXT: v_and_b32_e32 v6, 0xff, v6 -; SI-NEXT: v_and_b32_e32 v3, 0xff, v3 +; SI-NEXT: v_and_b32_e32 v4, 0xff, v23 +; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v38 +; SI-NEXT: v_or_b32_e32 v4, v4, v6 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v2, 0xff, v2 +; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4 +; SI-NEXT: s_lshl_b32 s4, s40, 8 +; SI-NEXT: s_lshl_b32 s5, s52, 24 ; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 ; SI-NEXT: v_readlane_b32 s99, v63, 35 ; SI-NEXT: v_readlane_b32 s98, v63, 34 ; SI-NEXT: v_readlane_b32 s97, v63, 33 -; SI-NEXT: v_readlane_b32 s96, v63, 32 ; SI-NEXT: v_readlane_b32 s87, v63, 31 ; SI-NEXT: v_readlane_b32 s86, v63, 30 ; SI-NEXT: v_readlane_b32 s85, v63, 29 @@ -45557,488 +44968,324 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; SI-NEXT: v_readlane_b32 s65, v63, 17 ; SI-NEXT: v_readlane_b32 s64, v63, 16 ; SI-NEXT: v_readlane_b32 s55, v63, 15 -; SI-NEXT: v_readlane_b32 s54, v63, 14 ; SI-NEXT: v_readlane_b32 s53, v63, 13 ; SI-NEXT: v_readlane_b32 s52, v63, 12 ; SI-NEXT: v_readlane_b32 s51, v63, 11 -; SI-NEXT: v_readlane_b32 s50, v63, 10 ; SI-NEXT: v_readlane_b32 s49, v63, 9 -; SI-NEXT: v_readlane_b32 s48, v63, 8 ; SI-NEXT: v_readlane_b32 s39, v63, 7 -; SI-NEXT: v_readlane_b32 s38, v63, 6 ; SI-NEXT: v_readlane_b32 s37, v63, 5 -; SI-NEXT: v_readlane_b32 s36, v63, 4 ; SI-NEXT: v_readlane_b32 s35, v63, 3 -; SI-NEXT: v_readlane_b32 s34, v63, 2 ; SI-NEXT: v_readlane_b32 s31, v63, 1 -; SI-NEXT: v_readlane_b32 s30, v63, 0 -; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v22 -; SI-NEXT: v_and_b32_e32 v22, 0xff, v52 -; SI-NEXT: v_or_b32_e32 v18, v22, v18 -; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v22, 0xff, v22 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v23, 24, v23 -; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; SI-NEXT: v_or_b32_e32 v22, v23, v22 -; SI-NEXT: v_or_b32_e32 v18, v18, v22 -; SI-NEXT: v_add_i32_e32 v22, vcc, 24, v0 -; SI-NEXT: buffer_store_dword v18, v22, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v18, 0xff, v53 -; SI-NEXT: v_or_b32_e32 v17, v18, v17 -; SI-NEXT: v_and_b32_e32 v18, 0xff, v19 -; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; SI-NEXT: v_or_b32_e32 v14, v14, v18 -; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17 -; SI-NEXT: v_or_b32_e32 v14, v17, v14 -; SI-NEXT: v_add_i32_e32 v17, vcc, 28, v0 -; SI-NEXT: buffer_store_dword v14, v17, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v17 -; SI-NEXT: v_and_b32_e32 v17, 0xff, v48 -; SI-NEXT: v_or_b32_e32 v14, v17, v14 -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17 -; SI-NEXT: v_or_b32_e32 v13, v17, v13 -; SI-NEXT: v_or_b32_e32 v13, v14, v13 -; SI-NEXT: v_add_i32_e32 v14, vcc, 32, v0 -; SI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v13, 0xff, v49 -; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v60 -; SI-NEXT: v_or_b32_e32 v13, v13, v14 -; SI-NEXT: v_and_b32_e32 v14, 0xff, v59 -; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v56 -; SI-NEXT: v_or_b32_e32 v14, v17, v14 -; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13 -; SI-NEXT: v_or_b32_e32 v13, v13, v14 -; SI-NEXT: v_add_i32_e32 v14, vcc, 36, v0 -; SI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_and_b32_e32 v14, 0xff, v35 -; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13 -; SI-NEXT: v_or_b32_e32 v13, v14, v13 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v14, 0xff, v17 -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload -; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17 -; SI-NEXT: v_or_b32_e32 v14, v17, v14 -; SI-NEXT: v_or_b32_e32 v13, v13, v14 -; SI-NEXT: v_add_i32_e32 v14, vcc, 40, v0 -; SI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v13, 0xff, v36 -; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v47 -; SI-NEXT: v_or_b32_e32 v13, v13, v14 -; SI-NEXT: v_and_b32_e32 v14, 0xff, v44 -; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v55 -; SI-NEXT: v_or_b32_e32 v14, v17, v14 -; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13 -; SI-NEXT: v_or_b32_e32 v13, v13, v14 -; SI-NEXT: v_add_i32_e32 v14, vcc, 44, v0 -; SI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_and_b32_e32 v14, 0xff, v29 -; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13 -; SI-NEXT: v_or_b32_e32 v13, v14, v13 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v14, 0xff, v17 -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload -; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17 -; SI-NEXT: v_or_b32_e32 v14, v17, v14 -; SI-NEXT: v_or_b32_e32 v13, v13, v14 -; SI-NEXT: v_add_i32_e32 v14, vcc, 48, v0 -; SI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v13, 0xff, v30 -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14 -; SI-NEXT: v_or_b32_e32 v13, v13, v14 -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17 -; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v14, 0xff, v14 -; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; SI-NEXT: v_or_b32_e32 v14, v17, v14 -; SI-NEXT: v_or_b32_e32 v13, v13, v14 -; SI-NEXT: v_add_i32_e32 v14, vcc, 52, v0 -; SI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6 +; SI-NEXT: v_or_b32_e32 v2, v6, v2 +; SI-NEXT: v_or_b32_e32 v2, v4, v2 +; SI-NEXT: v_add_i32_e32 v4, vcc, 36, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_and_b32_e32 v14, 0xff, v25 -; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13 -; SI-NEXT: v_or_b32_e32 v13, v14, v13 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v14, 0xff, v17 -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17 -; SI-NEXT: v_or_b32_e32 v14, v17, v14 -; SI-NEXT: v_or_b32_e32 v13, v13, v14 -; SI-NEXT: v_add_i32_e32 v14, vcc, 56, v0 -; SI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v2, 0xff, v22 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: s_and_b32 s4, s54, 0xff +; SI-NEXT: s_lshl_b32 s4, s4, 16 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: s_or_b32 s4, s5, s4 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: v_add_i32_e32 v4, vcc, 40, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v13, 0xff, v26 -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v2, 0xff, v21 +; SI-NEXT: s_lshl_b32 s4, s24, 8 +; SI-NEXT: s_lshl_b32 s5, s48, 24 +; SI-NEXT: v_readlane_b32 s54, v63, 14 +; SI-NEXT: v_readlane_b32 s48, v63, 8 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14 -; SI-NEXT: v_or_b32_e32 v13, v13, v14 -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17 -; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13 +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v14, 0xff, v14 -; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; SI-NEXT: v_or_b32_e32 v14, v17, v14 -; SI-NEXT: v_or_b32_e32 v13, v13, v14 -; SI-NEXT: v_add_i32_e32 v14, vcc, 60, v0 -; SI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v4, 0xff, v4 +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 44, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_and_b32_e32 v14, 0xff, v20 -; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13 -; SI-NEXT: v_or_b32_e32 v13, v14, v13 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v14, 0xff, v17 -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload -; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17 -; SI-NEXT: v_or_b32_e32 v14, v17, v14 -; SI-NEXT: v_or_b32_e32 v13, v13, v14 -; SI-NEXT: v_add_i32_e32 v14, vcc, 64, v0 -; SI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v2, 0xff, v20 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: s_and_b32 s4, s50, 0xff +; SI-NEXT: s_lshl_b32 s4, s4, 16 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: s_or_b32 s4, s5, s4 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: v_add_i32_e32 v4, vcc, 48, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v13, 0xff, v21 -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v2, 0xff, v19 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; SI-NEXT: s_lshl_b32 s4, s22, 8 +; SI-NEXT: s_lshl_b32 s5, s36, 24 +; SI-NEXT: v_readlane_b32 s50, v63, 10 +; SI-NEXT: v_readlane_b32 s36, v63, 4 ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14 -; SI-NEXT: v_or_b32_e32 v13, v13, v14 -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17 -; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13 +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v14, 0xff, v14 -; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; SI-NEXT: v_or_b32_e32 v14, v17, v14 -; SI-NEXT: v_or_b32_e32 v13, v13, v14 -; SI-NEXT: v_add_i32_e32 v14, vcc, 0x44, v0 -; SI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v4, 0xff, v4 +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 52, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v14, 0xff, v15 -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload -; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13 -; SI-NEXT: v_or_b32_e32 v13, v14, v13 -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v17 -; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13 -; SI-NEXT: v_and_b32_e32 v14, 0xff, v14 -; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; SI-NEXT: v_or_b32_e32 v14, v15, v14 -; SI-NEXT: v_or_b32_e32 v13, v13, v14 -; SI-NEXT: v_add_i32_e32 v14, vcc, 0x48, v0 -; SI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v2, 0xff, v18 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: s_and_b32 s4, s38, 0xff +; SI-NEXT: s_lshl_b32 s4, s4, 16 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: s_or_b32 s4, s5, s4 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: v_add_i32_e32 v4, vcc, 56, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v13, 0xff, v16 -; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v2, 0xff, v17 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; SI-NEXT: s_lshl_b32 s4, s20, 8 +; SI-NEXT: s_lshl_b32 s5, s30, 24 +; SI-NEXT: v_readlane_b32 s38, v63, 6 +; SI-NEXT: v_readlane_b32 s30, v63, 0 ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14 -; SI-NEXT: v_or_b32_e32 v13, v13, v14 -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15 -; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13 +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v14, 0xff, v14 -; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; SI-NEXT: v_or_b32_e32 v14, v15, v14 -; SI-NEXT: v_or_b32_e32 v13, v13, v14 -; SI-NEXT: v_add_i32_e32 v14, vcc, 0x4c, v0 -; SI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v4, 0xff, v4 +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 60, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13 -; SI-NEXT: v_or_b32_e32 v11, v11, v13 -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v13, 0xff, v13 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14 -; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; SI-NEXT: v_or_b32_e32 v13, v14, v13 -; SI-NEXT: v_or_b32_e32 v11, v11, v13 -; SI-NEXT: v_add_i32_e32 v13, vcc, 0x50, v0 -; SI-NEXT: buffer_store_dword v11, v13, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v2, 0xff, v16 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: s_and_b32 s4, s34, 0xff +; SI-NEXT: s_lshl_b32 s4, s4, 16 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: s_or_b32 s4, s5, s4 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: v_add_i32_e32 v4, vcc, 64, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v11, 0xff, v12 -; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v2, 0xff, v15 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; SI-NEXT: s_lshl_b32 s4, s18, 8 +; SI-NEXT: s_lshl_b32 s5, s94, 24 +; SI-NEXT: v_readlane_b32 s34, v63, 2 ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v12 -; SI-NEXT: v_or_b32_e32 v11, v11, v12 -; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13 -; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11 +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v12, 0xff, v12 -; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; SI-NEXT: v_or_b32_e32 v12, v13, v12 -; SI-NEXT: v_or_b32_e32 v11, v11, v12 -; SI-NEXT: v_add_i32_e32 v12, vcc, 0x54, v0 -; SI-NEXT: buffer_store_dword v11, v12, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v4, 0xff, v4 +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 0x44, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v11 -; SI-NEXT: v_or_b32_e32 v9, v9, v11 -; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v11, 0xff, v11 -; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12 -; SI-NEXT: v_or_b32_e32 v11, v12, v11 -; SI-NEXT: v_or_b32_e32 v9, v9, v11 -; SI-NEXT: v_add_i32_e32 v11, vcc, 0x58, v0 -; SI-NEXT: buffer_store_dword v9, v11, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v2, 0xff, v14 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: s_and_b32 s4, s96, 0xff +; SI-NEXT: s_lshl_b32 s4, s4, 16 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: s_or_b32 s4, s5, s4 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: v_add_i32_e32 v4, vcc, 0x48, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v9, 0xff, v10 -; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v10 -; SI-NEXT: v_or_b32_e32 v9, v9, v10 -; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v11 -; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9 +; SI-NEXT: v_and_b32_e32 v2, 0xff, v13 +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v34 +; SI-NEXT: s_lshl_b32 s4, s16, 8 +; SI-NEXT: s_lshl_b32 s5, s90, 24 +; SI-NEXT: v_readlane_b32 s96, v63, 32 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v10, 0xff, v10 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v11, v10 -; SI-NEXT: v_or_b32_e32 v9, v9, v10 -; SI-NEXT: v_add_i32_e32 v10, vcc, 0x5c, v0 -; SI-NEXT: buffer_store_dword v9, v10, s[0:3], 0 offen +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_and_b32_e32 v4, 0xff, v35 +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 0x4c, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9 -; SI-NEXT: v_or_b32_e32 v7, v7, v9 -; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v9, 0xff, v9 -; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v10 -; SI-NEXT: v_or_b32_e32 v9, v10, v9 -; SI-NEXT: v_or_b32_e32 v7, v7, v9 -; SI-NEXT: v_add_i32_e32 v9, vcc, 0x60, v0 -; SI-NEXT: buffer_store_dword v7, v9, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v2, 0xff, v12 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: s_and_b32 s4, s92, 0xff +; SI-NEXT: s_lshl_b32 s4, s4, 16 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: s_or_b32 s4, s5, s4 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: v_add_i32_e32 v4, vcc, 0x50, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v7, 0xff, v8 -; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8 -; SI-NEXT: v_or_b32_e32 v7, v7, v8 -; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v9 -; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7 +; SI-NEXT: v_and_b32_e32 v2, 0xff, v11 +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v33 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_and_b32_e32 v4, 0xff, v30 +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v28 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 0x54, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; SI-NEXT: s_lshl_b32 s4, s14, 8 +; SI-NEXT: s_lshl_b32 s5, s78, 24 +; SI-NEXT: v_add_i32_e32 v4, vcc, 0x58, v0 +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v59 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v8, 0xff, v8 -; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; SI-NEXT: v_or_b32_e32 v8, v9, v8 -; SI-NEXT: v_or_b32_e32 v7, v7, v8 -; SI-NEXT: v_add_i32_e32 v8, vcc, 0x64, v0 -; SI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v2, 0xff, v2 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: s_and_b32 s4, s88, 0xff +; SI-NEXT: s_lshl_b32 s4, s4, 16 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: s_or_b32 s4, s5, s4 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v7 -; SI-NEXT: v_or_b32_e32 v5, v5, v7 -; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v7, 0xff, v7 -; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v8 -; SI-NEXT: v_or_b32_e32 v7, v8, v7 -; SI-NEXT: v_or_b32_e32 v5, v5, v7 -; SI-NEXT: v_add_i32_e32 v7, vcc, 0x68, v0 -; SI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v2, 0xff, v9 +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v26 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_and_b32_e32 v4, 0xff, v60 +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 0x5c, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5 -; SI-NEXT: v_or_b32_e32 v5, v6, v5 -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v7 -; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; SI-NEXT: s_lshl_b32 s4, s12, 8 +; SI-NEXT: s_lshl_b32 s5, s74, 24 +; SI-NEXT: v_add_i32_e32 v4, vcc, 0x60, v0 +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v56 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v6, 0xff, v6 -; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; SI-NEXT: v_or_b32_e32 v6, v7, v6 -; SI-NEXT: v_or_b32_e32 v5, v5, v6 -; SI-NEXT: v_add_i32_e32 v6, vcc, 0x6c, v0 -; SI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v2, 0xff, v2 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: s_and_b32 s4, s76, 0xff +; SI-NEXT: s_lshl_b32 s4, s4, 16 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: s_or_b32 s4, s5, s4 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5 -; SI-NEXT: v_or_b32_e32 v3, v3, v5 -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v5, 0xff, v5 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6 -; SI-NEXT: v_or_b32_e32 v5, v6, v5 -; SI-NEXT: v_or_b32_e32 v3, v3, v5 -; SI-NEXT: v_add_i32_e32 v5, vcc, 0x70, v0 -; SI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v2, 0xff, v7 +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v58 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_and_b32_e32 v4, 0xff, v57 +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 0x64, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v3, 0xff, v4 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4 -; SI-NEXT: v_or_b32_e32 v3, v3, v4 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v5 -; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; SI-NEXT: s_lshl_b32 s4, s10, 8 +; SI-NEXT: s_lshl_b32 s5, s62, 24 +; SI-NEXT: v_add_i32_e32 v4, vcc, 0x68, v0 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v4, 0xff, v4 +; SI-NEXT: v_and_b32_e32 v2, 0xff, v2 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: s_and_b32 s4, s72, 0xff +; SI-NEXT: s_lshl_b32 s4, s4, 16 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: s_or_b32 s4, s5, s4 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_and_b32_e32 v2, 0xff, v5 +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v47 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_and_b32_e32 v4, 0xff, v46 ; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v45 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: v_or_b32_e32 v3, v3, v4 -; SI-NEXT: v_add_i32_e32 v4, vcc, 0x74, v0 -; SI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 0x6c, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3 -; SI-NEXT: v_or_b32_e32 v1, v1, v3 -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v3, 0xff, v3 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; SI-NEXT: s_lshl_b32 s4, s8, 8 +; SI-NEXT: s_lshl_b32 s5, s58, 24 +; SI-NEXT: v_add_i32_e32 v4, vcc, 0x70, v0 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v2, 0xff, v2 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: s_and_b32 s4, s60, 0xff +; SI-NEXT: s_lshl_b32 s4, s4, 16 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: s_or_b32 s4, s5, s4 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_and_b32_e32 v2, 0xff, v3 +; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v44 +; SI-NEXT: v_or_b32_e32 v2, v2, v3 +; SI-NEXT: v_and_b32_e32 v3, 0xff, v43 ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4 +; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v42 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; SI-NEXT: v_or_b32_e32 v3, v4, v3 -; SI-NEXT: v_or_b32_e32 v1, v1, v3 -; SI-NEXT: v_add_i32_e32 v3, vcc, 0x78, v0 -; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: v_or_b32_e32 v2, v2, v3 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x74, v0 +; SI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v2 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; SI-NEXT: s_lshl_b32 s4, s6, 8 +; SI-NEXT: s_lshl_b32 s5, s26, 24 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x78, v0 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; SI-NEXT: v_or_b32_e32 v1, v1, v2 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v2, 0xff, v2 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: s_and_b32 s4, s28, 0xff +; SI-NEXT: s_lshl_b32 s4, s4, 16 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: s_or_b32 s4, s5, s4 +; SI-NEXT: v_or_b32_e32 v2, s4, v2 +; SI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v41 +; SI-NEXT: v_or_b32_e32 v1, v1, v2 +; SI-NEXT: v_and_b32_e32 v2, 0xff, v40 ; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3 ; SI-NEXT: v_or_b32_e32 v2, v3, v2 ; SI-NEXT: v_or_b32_e32 v1, v1, v2 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen @@ -46056,9 +45303,9 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload ; SI-NEXT: s_or_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] @@ -46088,27 +45335,55 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; VI-NEXT: v_writelane_b32 v63, s55, 15 ; VI-NEXT: v_writelane_b32 v63, s64, 16 ; VI-NEXT: v_writelane_b32 v63, s65, 17 +; VI-NEXT: v_mov_b32_e32 v20, s16 ; VI-NEXT: v_writelane_b32 v63, s66, 18 +; VI-NEXT: v_readfirstlane_b32 s56, v20 +; VI-NEXT: v_mov_b32_e32 v20, s17 ; VI-NEXT: v_writelane_b32 v63, s67, 19 +; VI-NEXT: v_readfirstlane_b32 s57, v20 +; VI-NEXT: v_mov_b32_e32 v20, s18 ; VI-NEXT: v_writelane_b32 v63, s68, 20 +; VI-NEXT: v_readfirstlane_b32 s46, v20 +; VI-NEXT: v_mov_b32_e32 v20, s19 ; VI-NEXT: v_writelane_b32 v63, s69, 21 +; VI-NEXT: v_readfirstlane_b32 s47, v20 +; VI-NEXT: v_mov_b32_e32 v20, s20 ; VI-NEXT: v_writelane_b32 v63, s70, 22 +; VI-NEXT: v_readfirstlane_b32 s44, v20 +; VI-NEXT: v_mov_b32_e32 v20, s21 ; VI-NEXT: v_writelane_b32 v63, s71, 23 +; VI-NEXT: v_readfirstlane_b32 s45, v20 +; VI-NEXT: v_mov_b32_e32 v20, s22 ; VI-NEXT: v_writelane_b32 v63, s80, 24 +; VI-NEXT: v_readfirstlane_b32 s42, v20 +; VI-NEXT: v_mov_b32_e32 v20, s23 ; VI-NEXT: v_writelane_b32 v63, s81, 25 +; VI-NEXT: v_readfirstlane_b32 s43, v20 +; VI-NEXT: v_mov_b32_e32 v20, s24 ; VI-NEXT: v_writelane_b32 v63, s82, 26 +; VI-NEXT: v_readfirstlane_b32 s40, v20 +; VI-NEXT: v_mov_b32_e32 v20, s25 ; VI-NEXT: v_writelane_b32 v63, s83, 27 +; VI-NEXT: v_readfirstlane_b32 s41, v20 +; VI-NEXT: v_mov_b32_e32 v20, s26 ; VI-NEXT: v_writelane_b32 v63, s84, 28 +; VI-NEXT: v_readfirstlane_b32 s24, v20 +; VI-NEXT: v_mov_b32_e32 v20, s27 ; VI-NEXT: v_writelane_b32 v63, s85, 29 +; VI-NEXT: v_readfirstlane_b32 s25, v20 +; VI-NEXT: v_mov_b32_e32 v20, s28 ; VI-NEXT: v_writelane_b32 v63, s86, 30 +; VI-NEXT: v_readfirstlane_b32 s22, v20 +; VI-NEXT: v_mov_b32_e32 v20, s29 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; VI-NEXT: v_writelane_b32 v63, s87, 31 -; VI-NEXT: v_readfirstlane_b32 s44, v1 -; VI-NEXT: v_readfirstlane_b32 s45, v2 -; VI-NEXT: v_readfirstlane_b32 s42, v3 -; VI-NEXT: v_readfirstlane_b32 s43, v4 -; VI-NEXT: v_readfirstlane_b32 s40, v5 -; VI-NEXT: v_readfirstlane_b32 s41, v6 +; VI-NEXT: v_readfirstlane_b32 s23, v20 +; VI-NEXT: v_readfirstlane_b32 s20, v1 +; VI-NEXT: v_readfirstlane_b32 s21, v2 +; VI-NEXT: v_readfirstlane_b32 s18, v3 +; VI-NEXT: v_readfirstlane_b32 s19, v4 +; VI-NEXT: v_readfirstlane_b32 s16, v5 +; VI-NEXT: v_readfirstlane_b32 s17, v6 ; VI-NEXT: v_readfirstlane_b32 s14, v7 ; VI-NEXT: v_readfirstlane_b32 s15, v8 ; VI-NEXT: v_readfirstlane_b32 s12, v9 @@ -46120,7 +45395,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; VI-NEXT: v_readfirstlane_b32 s6, v15 ; VI-NEXT: v_readfirstlane_b32 s7, v16 ; VI-NEXT: v_readfirstlane_b32 s4, v17 -; VI-NEXT: s_and_b64 s[46:47], vcc, exec +; VI-NEXT: s_and_b64 s[26:27], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s5, v18 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill @@ -46139,160 +45414,160 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; VI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; VI-NEXT: s_cbranch_scc0 .LBB37_3 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_lshr_b32 s46, s5, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 57 -; VI-NEXT: s_lshr_b32 s46, s5, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 56 -; VI-NEXT: s_lshr_b32 s46, s5, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 55 -; VI-NEXT: s_lshr_b32 s46, s4, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 54 -; VI-NEXT: s_lshr_b32 s46, s4, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 53 -; VI-NEXT: s_lshr_b32 s46, s7, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 52 -; VI-NEXT: s_lshr_b32 s46, s7, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 51 -; VI-NEXT: s_lshr_b32 s46, s7, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 50 -; VI-NEXT: s_lshr_b32 s46, s6, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 49 -; VI-NEXT: s_lshr_b32 s46, s6, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 48 -; VI-NEXT: s_lshr_b32 s46, s9, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 47 -; VI-NEXT: s_lshr_b32 s46, s9, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 46 -; VI-NEXT: s_lshr_b32 s46, s9, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 45 -; VI-NEXT: s_lshr_b32 s46, s8, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 44 -; VI-NEXT: s_lshr_b32 s46, s8, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 43 -; VI-NEXT: s_lshr_b32 s46, s11, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 42 -; VI-NEXT: s_lshr_b32 s46, s11, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 41 -; VI-NEXT: s_lshr_b32 s46, s11, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 40 -; VI-NEXT: s_lshr_b32 s46, s10, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 39 -; VI-NEXT: s_lshr_b32 s46, s10, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 38 -; VI-NEXT: s_lshr_b32 s46, s13, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 37 -; VI-NEXT: s_lshr_b32 s46, s13, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 36 -; VI-NEXT: s_lshr_b32 s46, s13, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 35 -; VI-NEXT: s_lshr_b32 s46, s12, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 34 -; VI-NEXT: s_lshr_b32 s46, s12, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 33 -; VI-NEXT: s_lshr_b32 s46, s15, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 32 -; VI-NEXT: s_lshr_b32 s46, s15, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 31 -; VI-NEXT: s_lshr_b32 s46, s15, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 30 -; VI-NEXT: s_lshr_b32 s46, s14, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 29 -; VI-NEXT: s_lshr_b32 s46, s14, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 28 -; VI-NEXT: s_lshr_b32 s46, s41, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 27 -; VI-NEXT: s_lshr_b32 s46, s41, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 26 -; VI-NEXT: s_lshr_b32 s46, s41, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 25 -; VI-NEXT: s_lshr_b32 s46, s40, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 24 -; VI-NEXT: s_lshr_b32 s46, s40, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 23 -; VI-NEXT: s_lshr_b32 s46, s43, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 22 -; VI-NEXT: s_lshr_b32 s46, s43, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 21 -; VI-NEXT: s_lshr_b32 s46, s43, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 20 -; VI-NEXT: s_lshr_b32 s46, s42, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 19 -; VI-NEXT: s_lshr_b32 s46, s42, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 18 -; VI-NEXT: s_lshr_b32 s46, s45, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 17 -; VI-NEXT: s_lshr_b32 s46, s45, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 16 -; VI-NEXT: s_lshr_b32 s46, s45, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 15 -; VI-NEXT: s_lshr_b32 s46, s44, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 14 -; VI-NEXT: s_lshr_b32 s46, s44, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 13 -; VI-NEXT: s_lshr_b32 s46, s29, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 12 -; VI-NEXT: s_lshr_b32 s46, s29, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 11 -; VI-NEXT: s_lshr_b32 s46, s29, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 10 -; VI-NEXT: s_lshr_b32 s46, s28, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 9 -; VI-NEXT: s_lshr_b32 s46, s28, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 8 -; VI-NEXT: s_lshr_b32 s46, s27, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 7 -; VI-NEXT: s_lshr_b32 s46, s27, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 6 -; VI-NEXT: s_lshr_b32 s46, s27, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 5 -; VI-NEXT: s_lshr_b32 s46, s26, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 4 -; VI-NEXT: s_lshr_b32 s46, s26, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 3 -; VI-NEXT: s_lshr_b32 s46, s25, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 2 -; VI-NEXT: s_lshr_b32 s46, s25, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 1 -; VI-NEXT: s_lshr_b32 s46, s24, 16 -; VI-NEXT: s_lshr_b32 s80, s25, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 0 -; VI-NEXT: s_lshr_b32 s81, s24, 8 -; VI-NEXT: s_lshr_b32 s82, s23, 24 -; VI-NEXT: s_lshr_b32 s83, s23, 16 -; VI-NEXT: s_lshr_b32 s85, s23, 8 -; VI-NEXT: s_lshr_b32 s84, s22, 16 -; VI-NEXT: s_lshr_b32 s86, s22, 8 -; VI-NEXT: s_lshr_b32 s87, s21, 24 -; VI-NEXT: s_lshr_b32 s50, s21, 16 -; VI-NEXT: s_lshr_b32 s52, s21, 8 -; VI-NEXT: s_lshr_b32 s51, s20, 16 -; VI-NEXT: s_lshr_b32 s53, s20, 8 -; VI-NEXT: s_lshr_b32 s54, s19, 24 -; VI-NEXT: s_lshr_b32 s55, s19, 16 -; VI-NEXT: s_lshr_b32 s65, s19, 8 -; VI-NEXT: s_lshr_b32 s64, s18, 16 -; VI-NEXT: s_lshr_b32 s66, s18, 8 -; VI-NEXT: s_lshr_b32 s67, s17, 24 -; VI-NEXT: s_lshr_b32 s68, s17, 16 -; VI-NEXT: s_lshr_b32 s70, s17, 8 -; VI-NEXT: s_lshr_b32 s69, s16, 16 -; VI-NEXT: s_lshr_b32 s71, s16, 8 -; VI-NEXT: s_lshr_b64 s[46:47], s[4:5], 24 -; VI-NEXT: s_lshr_b64 s[56:57], s[6:7], 24 +; VI-NEXT: s_lshr_b32 s26, s5, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 57 +; VI-NEXT: s_lshr_b32 s26, s5, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 56 +; VI-NEXT: s_lshr_b32 s26, s5, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 55 +; VI-NEXT: s_lshr_b32 s26, s4, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 54 +; VI-NEXT: s_lshr_b32 s26, s4, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 53 +; VI-NEXT: s_lshr_b32 s26, s7, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 52 +; VI-NEXT: s_lshr_b32 s26, s7, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 51 +; VI-NEXT: s_lshr_b32 s26, s7, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 50 +; VI-NEXT: s_lshr_b32 s26, s6, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 49 +; VI-NEXT: s_lshr_b32 s26, s6, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 48 +; VI-NEXT: s_lshr_b32 s26, s9, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 47 +; VI-NEXT: s_lshr_b32 s26, s9, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 46 +; VI-NEXT: s_lshr_b32 s26, s9, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 45 +; VI-NEXT: s_lshr_b32 s26, s8, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 44 +; VI-NEXT: s_lshr_b32 s26, s8, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 43 +; VI-NEXT: s_lshr_b32 s26, s11, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 42 +; VI-NEXT: s_lshr_b32 s26, s11, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 41 +; VI-NEXT: s_lshr_b32 s26, s11, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 40 +; VI-NEXT: s_lshr_b32 s26, s10, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 39 +; VI-NEXT: s_lshr_b32 s26, s10, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 38 +; VI-NEXT: s_lshr_b32 s26, s13, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 37 +; VI-NEXT: s_lshr_b32 s26, s13, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 36 +; VI-NEXT: s_lshr_b32 s26, s13, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 35 +; VI-NEXT: s_lshr_b32 s26, s12, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 34 +; VI-NEXT: s_lshr_b32 s26, s12, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 33 +; VI-NEXT: s_lshr_b32 s26, s15, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 32 +; VI-NEXT: s_lshr_b32 s26, s15, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 31 +; VI-NEXT: s_lshr_b32 s26, s15, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 30 +; VI-NEXT: s_lshr_b32 s26, s14, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 29 +; VI-NEXT: s_lshr_b32 s26, s14, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 28 +; VI-NEXT: s_lshr_b32 s26, s17, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 27 +; VI-NEXT: s_lshr_b32 s26, s17, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 26 +; VI-NEXT: s_lshr_b32 s26, s17, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 25 +; VI-NEXT: s_lshr_b32 s26, s16, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 24 +; VI-NEXT: s_lshr_b32 s26, s16, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 23 +; VI-NEXT: s_lshr_b32 s26, s19, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 22 +; VI-NEXT: s_lshr_b32 s26, s19, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 21 +; VI-NEXT: s_lshr_b32 s26, s19, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 20 +; VI-NEXT: s_lshr_b32 s26, s18, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 19 +; VI-NEXT: s_lshr_b32 s26, s18, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 18 +; VI-NEXT: s_lshr_b32 s26, s21, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 17 +; VI-NEXT: s_lshr_b32 s26, s21, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 16 +; VI-NEXT: s_lshr_b32 s26, s21, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 15 +; VI-NEXT: s_lshr_b32 s26, s20, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 14 +; VI-NEXT: s_lshr_b32 s26, s20, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 13 +; VI-NEXT: s_lshr_b32 s26, s23, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 12 +; VI-NEXT: s_lshr_b32 s26, s23, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 11 +; VI-NEXT: s_lshr_b32 s26, s23, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 10 +; VI-NEXT: s_lshr_b32 s26, s22, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 9 +; VI-NEXT: s_lshr_b32 s26, s22, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 8 +; VI-NEXT: s_lshr_b32 s26, s25, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 7 +; VI-NEXT: s_lshr_b32 s26, s25, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 6 +; VI-NEXT: s_lshr_b32 s26, s25, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 5 +; VI-NEXT: s_lshr_b32 s26, s24, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 4 +; VI-NEXT: s_lshr_b32 s26, s24, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 3 +; VI-NEXT: s_lshr_b32 s26, s41, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 2 +; VI-NEXT: s_lshr_b32 s26, s41, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 1 +; VI-NEXT: s_lshr_b32 s26, s40, 16 +; VI-NEXT: s_lshr_b32 s80, s41, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 0 +; VI-NEXT: s_lshr_b32 s81, s40, 8 +; VI-NEXT: s_lshr_b32 s82, s43, 24 +; VI-NEXT: s_lshr_b32 s83, s43, 16 +; VI-NEXT: s_lshr_b32 s85, s43, 8 +; VI-NEXT: s_lshr_b32 s84, s42, 16 +; VI-NEXT: s_lshr_b32 s86, s42, 8 +; VI-NEXT: s_lshr_b32 s87, s45, 24 +; VI-NEXT: s_lshr_b32 s50, s45, 16 +; VI-NEXT: s_lshr_b32 s52, s45, 8 +; VI-NEXT: s_lshr_b32 s51, s44, 16 +; VI-NEXT: s_lshr_b32 s53, s44, 8 +; VI-NEXT: s_lshr_b32 s54, s47, 24 +; VI-NEXT: s_lshr_b32 s55, s47, 16 +; VI-NEXT: s_lshr_b32 s65, s47, 8 +; VI-NEXT: s_lshr_b32 s64, s46, 16 +; VI-NEXT: s_lshr_b32 s66, s46, 8 +; VI-NEXT: s_lshr_b32 s67, s57, 24 +; VI-NEXT: s_lshr_b32 s68, s57, 16 +; VI-NEXT: s_lshr_b32 s70, s57, 8 +; VI-NEXT: s_lshr_b32 s69, s56, 16 +; VI-NEXT: s_lshr_b32 s71, s56, 8 +; VI-NEXT: s_lshr_b64 s[26:27], s[4:5], 24 +; VI-NEXT: s_lshr_b64 s[28:29], s[6:7], 24 ; VI-NEXT: s_lshr_b64 s[58:59], s[8:9], 24 ; VI-NEXT: s_lshr_b64 s[60:61], s[10:11], 24 ; VI-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 ; VI-NEXT: s_lshr_b64 s[72:73], s[14:15], 24 -; VI-NEXT: s_lshr_b64 s[74:75], s[40:41], 24 -; VI-NEXT: s_lshr_b64 s[76:77], s[42:43], 24 -; VI-NEXT: s_lshr_b64 s[78:79], s[44:45], 24 -; VI-NEXT: s_lshr_b64 s[88:89], s[28:29], 24 -; VI-NEXT: s_lshr_b64 s[90:91], s[26:27], 24 -; VI-NEXT: s_lshr_b64 s[30:31], s[24:25], 24 -; VI-NEXT: s_lshr_b64 s[34:35], s[22:23], 24 -; VI-NEXT: s_lshr_b64 s[36:37], s[20:21], 24 -; VI-NEXT: s_lshr_b64 s[38:39], s[18:19], 24 -; VI-NEXT: s_lshr_b64 s[48:49], s[16:17], 24 +; VI-NEXT: s_lshr_b64 s[74:75], s[16:17], 24 +; VI-NEXT: s_lshr_b64 s[76:77], s[18:19], 24 +; VI-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 +; VI-NEXT: s_lshr_b64 s[88:89], s[22:23], 24 +; VI-NEXT: s_lshr_b64 s[90:91], s[24:25], 24 +; VI-NEXT: s_lshr_b64 s[30:31], s[40:41], 24 +; VI-NEXT: s_lshr_b64 s[34:35], s[42:43], 24 +; VI-NEXT: s_lshr_b64 s[36:37], s[44:45], 24 +; VI-NEXT: s_lshr_b64 s[38:39], s[46:47], 24 +; VI-NEXT: s_lshr_b64 s[48:49], s[56:57], 24 ; VI-NEXT: s_cbranch_execnz .LBB37_4 ; VI-NEXT: .LBB37_2: ; %cmp.true ; VI-NEXT: v_add_f32_e64 v2, s5, 1.0 @@ -46323,28 +45598,28 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[11:12] -; VI-NEXT: v_add_f32_e64 v14, s41, 1.0 -; VI-NEXT: v_add_f32_e64 v13, s40, 1.0 +; VI-NEXT: v_add_f32_e64 v14, s17, 1.0 +; VI-NEXT: v_add_f32_e64 v13, s16, 1.0 ; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill ; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[13:14] -; VI-NEXT: v_add_f32_e64 v16, s43, 1.0 -; VI-NEXT: v_add_f32_e64 v15, s42, 1.0 +; VI-NEXT: v_add_f32_e64 v16, s19, 1.0 +; VI-NEXT: v_add_f32_e64 v15, s18, 1.0 ; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill ; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[15:16] -; VI-NEXT: v_add_f32_e64 v18, s45, 1.0 -; VI-NEXT: v_add_f32_e64 v17, s44, 1.0 +; VI-NEXT: v_add_f32_e64 v18, s21, 1.0 +; VI-NEXT: v_add_f32_e64 v17, s20, 1.0 ; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill ; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[17:18] -; VI-NEXT: v_add_f32_e64 v20, s29, 1.0 -; VI-NEXT: v_add_f32_e64 v19, s28, 1.0 +; VI-NEXT: v_add_f32_e64 v20, s23, 1.0 +; VI-NEXT: v_add_f32_e64 v19, s22, 1.0 ; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill ; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[19:20] -; VI-NEXT: v_add_f32_e64 v22, s27, 1.0 -; VI-NEXT: v_add_f32_e64 v21, s26, 1.0 +; VI-NEXT: v_add_f32_e64 v22, s25, 1.0 +; VI-NEXT: v_add_f32_e64 v21, s24, 1.0 ; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill ; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[21:22] @@ -46453,21 +45728,21 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v22 ; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill ; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v22 -; VI-NEXT: v_add_f32_e64 v28, s21, 1.0 -; VI-NEXT: v_add_f32_e64 v27, s20, 1.0 +; VI-NEXT: v_add_f32_e64 v28, s45, 1.0 +; VI-NEXT: v_add_f32_e64 v27, s44, 1.0 ; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill ; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v22 -; VI-NEXT: v_add_f32_e64 v30, s19, 1.0 -; VI-NEXT: v_add_f32_e64 v29, s18, 1.0 -; VI-NEXT: v_add_f32_e64 v24, s25, 1.0 -; VI-NEXT: v_add_f32_e64 v23, s24, 1.0 +; VI-NEXT: v_add_f32_e64 v30, s47, 1.0 +; VI-NEXT: v_add_f32_e64 v29, s46, 1.0 +; VI-NEXT: v_add_f32_e64 v24, s41, 1.0 +; VI-NEXT: v_add_f32_e64 v23, s40, 1.0 ; VI-NEXT: v_lshrrev_b64 v[39:40], 24, v[27:28] ; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill ; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v21 -; VI-NEXT: v_add_f32_e64 v32, s17, 1.0 -; VI-NEXT: v_add_f32_e64 v31, s16, 1.0 -; VI-NEXT: v_add_f32_e64 v26, s23, 1.0 -; VI-NEXT: v_add_f32_e64 v25, s22, 1.0 +; VI-NEXT: v_add_f32_e64 v32, s57, 1.0 +; VI-NEXT: v_add_f32_e64 v31, s56, 1.0 +; VI-NEXT: v_add_f32_e64 v26, s43, 1.0 +; VI-NEXT: v_add_f32_e64 v25, s42, 1.0 ; VI-NEXT: v_lshrrev_b64 v[53:54], 24, v[23:24] ; VI-NEXT: v_lshrrev_b64 v[40:41], 24, v[29:30] ; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill @@ -46503,10 +45778,10 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; VI-NEXT: v_lshrrev_b32_e32 v35, 8, v31 ; VI-NEXT: s_branch .LBB37_5 ; VI-NEXT: .LBB37_3: -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 ; VI-NEXT: ; implicit-def: $sgpr71 ; VI-NEXT: ; implicit-def: $sgpr69 ; VI-NEXT: ; implicit-def: $sgpr70 @@ -46543,126 +45818,126 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; VI-NEXT: ; implicit-def: $sgpr62 ; VI-NEXT: ; implicit-def: $sgpr60 ; VI-NEXT: ; implicit-def: $sgpr58 -; VI-NEXT: ; implicit-def: $sgpr56 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 +; VI-NEXT: ; implicit-def: $sgpr28 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 ; VI-NEXT: s_branch .LBB37_2 ; VI-NEXT: .LBB37_4: -; VI-NEXT: v_mov_b32_e32 v53, s46 +; VI-NEXT: v_mov_b32_e32 v53, s26 ; VI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v53, s56 +; VI-NEXT: v_mov_b32_e32 v53, s28 ; VI-NEXT: v_mov_b32_e32 v1, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 0 ; VI-NEXT: v_mov_b32_e32 v48, s4 @@ -46841,26 +46116,26 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; VI-NEXT: v_readlane_b32 s4, v62, 57 ; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v39, s4 -; VI-NEXT: v_mov_b32_e32 v31, s16 -; VI-NEXT: v_mov_b32_e32 v32, s17 -; VI-NEXT: v_mov_b32_e32 v29, s18 -; VI-NEXT: v_mov_b32_e32 v30, s19 -; VI-NEXT: v_mov_b32_e32 v27, s20 -; VI-NEXT: v_mov_b32_e32 v28, s21 -; VI-NEXT: v_mov_b32_e32 v25, s22 -; VI-NEXT: v_mov_b32_e32 v26, s23 -; VI-NEXT: v_mov_b32_e32 v23, s24 -; VI-NEXT: v_mov_b32_e32 v24, s25 -; VI-NEXT: v_mov_b32_e32 v21, s26 -; VI-NEXT: v_mov_b32_e32 v22, s27 -; VI-NEXT: v_mov_b32_e32 v19, s28 -; VI-NEXT: v_mov_b32_e32 v20, s29 -; VI-NEXT: v_mov_b32_e32 v17, s44 -; VI-NEXT: v_mov_b32_e32 v18, s45 -; VI-NEXT: v_mov_b32_e32 v15, s42 -; VI-NEXT: v_mov_b32_e32 v16, s43 -; VI-NEXT: v_mov_b32_e32 v13, s40 -; VI-NEXT: v_mov_b32_e32 v14, s41 +; VI-NEXT: v_mov_b32_e32 v31, s56 +; VI-NEXT: v_mov_b32_e32 v32, s57 +; VI-NEXT: v_mov_b32_e32 v29, s46 +; VI-NEXT: v_mov_b32_e32 v30, s47 +; VI-NEXT: v_mov_b32_e32 v27, s44 +; VI-NEXT: v_mov_b32_e32 v28, s45 +; VI-NEXT: v_mov_b32_e32 v25, s42 +; VI-NEXT: v_mov_b32_e32 v26, s43 +; VI-NEXT: v_mov_b32_e32 v23, s40 +; VI-NEXT: v_mov_b32_e32 v24, s41 +; VI-NEXT: v_mov_b32_e32 v21, s24 +; VI-NEXT: v_mov_b32_e32 v22, s25 +; VI-NEXT: v_mov_b32_e32 v19, s22 +; VI-NEXT: v_mov_b32_e32 v20, s23 +; VI-NEXT: v_mov_b32_e32 v17, s20 +; VI-NEXT: v_mov_b32_e32 v18, s21 +; VI-NEXT: v_mov_b32_e32 v15, s18 +; VI-NEXT: v_mov_b32_e32 v16, s19 +; VI-NEXT: v_mov_b32_e32 v13, s16 +; VI-NEXT: v_mov_b32_e32 v14, s17 ; VI-NEXT: v_mov_b32_e32 v11, s14 ; VI-NEXT: v_mov_b32_e32 v12, s15 ; VI-NEXT: v_mov_b32_e32 v9, s12 @@ -47363,27 +46638,55 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; GFX9-NEXT: v_writelane_b32 v63, s67, 19 ; GFX9-NEXT: v_writelane_b32 v63, s68, 20 ; GFX9-NEXT: v_writelane_b32 v63, s69, 21 +; GFX9-NEXT: v_mov_b32_e32 v20, s16 ; GFX9-NEXT: v_writelane_b32 v63, s70, 22 +; GFX9-NEXT: v_readfirstlane_b32 s56, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s17 ; GFX9-NEXT: v_writelane_b32 v63, s71, 23 +; GFX9-NEXT: v_readfirstlane_b32 s57, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s18 ; GFX9-NEXT: v_writelane_b32 v63, s80, 24 +; GFX9-NEXT: v_readfirstlane_b32 s46, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s19 ; GFX9-NEXT: v_writelane_b32 v63, s81, 25 +; GFX9-NEXT: v_readfirstlane_b32 s47, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s20 ; GFX9-NEXT: v_writelane_b32 v63, s82, 26 +; GFX9-NEXT: v_readfirstlane_b32 s44, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s21 ; GFX9-NEXT: v_writelane_b32 v63, s83, 27 +; GFX9-NEXT: v_readfirstlane_b32 s45, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s22 ; GFX9-NEXT: v_writelane_b32 v63, s84, 28 +; GFX9-NEXT: v_readfirstlane_b32 s42, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s23 ; GFX9-NEXT: v_writelane_b32 v63, s85, 29 +; GFX9-NEXT: v_readfirstlane_b32 s43, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s24 ; GFX9-NEXT: v_writelane_b32 v63, s86, 30 +; GFX9-NEXT: v_readfirstlane_b32 s40, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s25 ; GFX9-NEXT: v_writelane_b32 v63, s87, 31 +; GFX9-NEXT: v_readfirstlane_b32 s41, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s26 ; GFX9-NEXT: v_writelane_b32 v63, s96, 32 +; GFX9-NEXT: v_readfirstlane_b32 s24, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s27 ; GFX9-NEXT: v_writelane_b32 v63, s97, 33 +; GFX9-NEXT: v_readfirstlane_b32 s25, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s28 ; GFX9-NEXT: v_writelane_b32 v63, s98, 34 +; GFX9-NEXT: v_readfirstlane_b32 s22, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s29 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; GFX9-NEXT: v_writelane_b32 v63, s99, 35 -; GFX9-NEXT: v_readfirstlane_b32 s44, v1 -; GFX9-NEXT: v_readfirstlane_b32 s45, v2 -; GFX9-NEXT: v_readfirstlane_b32 s42, v3 -; GFX9-NEXT: v_readfirstlane_b32 s43, v4 -; GFX9-NEXT: v_readfirstlane_b32 s40, v5 -; GFX9-NEXT: v_readfirstlane_b32 s41, v6 +; GFX9-NEXT: v_readfirstlane_b32 s23, v20 +; GFX9-NEXT: v_readfirstlane_b32 s20, v1 +; GFX9-NEXT: v_readfirstlane_b32 s21, v2 +; GFX9-NEXT: v_readfirstlane_b32 s18, v3 +; GFX9-NEXT: v_readfirstlane_b32 s19, v4 +; GFX9-NEXT: v_readfirstlane_b32 s16, v5 +; GFX9-NEXT: v_readfirstlane_b32 s17, v6 ; GFX9-NEXT: v_readfirstlane_b32 s14, v7 ; GFX9-NEXT: v_readfirstlane_b32 s15, v8 ; GFX9-NEXT: v_readfirstlane_b32 s12, v9 @@ -47395,7 +46698,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; GFX9-NEXT: v_readfirstlane_b32 s6, v15 ; GFX9-NEXT: v_readfirstlane_b32 s7, v16 ; GFX9-NEXT: v_readfirstlane_b32 s4, v17 -; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_and_b64 s[26:27], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s5, v18 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill @@ -47414,152 +46717,152 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; GFX9-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; GFX9-NEXT: s_cbranch_scc0 .LBB37_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false -; GFX9-NEXT: s_lshr_b32 s46, s5, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 49 -; GFX9-NEXT: s_lshr_b32 s46, s5, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 48 -; GFX9-NEXT: s_lshr_b32 s46, s5, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 47 -; GFX9-NEXT: s_lshr_b32 s46, s4, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 46 -; GFX9-NEXT: s_lshr_b32 s46, s4, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 45 -; GFX9-NEXT: s_lshr_b32 s46, s7, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 44 -; GFX9-NEXT: s_lshr_b32 s46, s7, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 43 -; GFX9-NEXT: s_lshr_b32 s46, s7, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 42 -; GFX9-NEXT: s_lshr_b32 s46, s6, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 41 -; GFX9-NEXT: s_lshr_b32 s46, s6, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 40 -; GFX9-NEXT: s_lshr_b32 s46, s9, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 39 -; GFX9-NEXT: s_lshr_b32 s46, s9, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 38 -; GFX9-NEXT: s_lshr_b32 s46, s9, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 37 -; GFX9-NEXT: s_lshr_b32 s46, s8, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 36 -; GFX9-NEXT: s_lshr_b32 s46, s8, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 35 -; GFX9-NEXT: s_lshr_b32 s46, s11, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 34 -; GFX9-NEXT: s_lshr_b32 s46, s11, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 33 -; GFX9-NEXT: s_lshr_b32 s46, s11, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 32 -; GFX9-NEXT: s_lshr_b32 s46, s10, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 31 -; GFX9-NEXT: s_lshr_b32 s46, s10, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 30 -; GFX9-NEXT: s_lshr_b32 s46, s13, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 29 -; GFX9-NEXT: s_lshr_b32 s46, s13, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 28 -; GFX9-NEXT: s_lshr_b32 s46, s13, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 27 -; GFX9-NEXT: s_lshr_b32 s46, s12, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 26 -; GFX9-NEXT: s_lshr_b32 s46, s12, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 25 -; GFX9-NEXT: s_lshr_b32 s46, s15, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 24 -; GFX9-NEXT: s_lshr_b32 s46, s15, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 23 -; GFX9-NEXT: s_lshr_b32 s46, s15, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 22 -; GFX9-NEXT: s_lshr_b32 s46, s14, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 21 -; GFX9-NEXT: s_lshr_b32 s46, s14, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 20 -; GFX9-NEXT: s_lshr_b32 s46, s41, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 19 -; GFX9-NEXT: s_lshr_b32 s46, s41, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 18 -; GFX9-NEXT: s_lshr_b32 s46, s41, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 17 -; GFX9-NEXT: s_lshr_b32 s46, s40, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 16 -; GFX9-NEXT: s_lshr_b32 s46, s40, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 15 -; GFX9-NEXT: s_lshr_b32 s46, s43, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 14 -; GFX9-NEXT: s_lshr_b32 s46, s43, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 13 -; GFX9-NEXT: s_lshr_b32 s46, s43, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 12 -; GFX9-NEXT: s_lshr_b32 s46, s42, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 11 -; GFX9-NEXT: s_lshr_b32 s46, s42, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 10 -; GFX9-NEXT: s_lshr_b32 s46, s45, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 9 -; GFX9-NEXT: s_lshr_b32 s46, s45, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 8 -; GFX9-NEXT: s_lshr_b32 s46, s45, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 7 -; GFX9-NEXT: s_lshr_b32 s46, s44, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 6 -; GFX9-NEXT: s_lshr_b32 s46, s44, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 5 -; GFX9-NEXT: s_lshr_b32 s46, s29, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 4 -; GFX9-NEXT: s_lshr_b32 s46, s29, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 3 -; GFX9-NEXT: s_lshr_b32 s46, s29, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 2 -; GFX9-NEXT: s_lshr_b32 s46, s28, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 1 -; GFX9-NEXT: s_lshr_b32 s46, s28, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 0 -; GFX9-NEXT: s_lshr_b32 s82, s27, 24 -; GFX9-NEXT: s_lshr_b32 s83, s27, 16 -; GFX9-NEXT: s_lshr_b32 s85, s27, 8 -; GFX9-NEXT: s_lshr_b32 s84, s26, 16 -; GFX9-NEXT: s_lshr_b32 s86, s26, 8 -; GFX9-NEXT: s_lshr_b32 s87, s25, 24 -; GFX9-NEXT: s_lshr_b32 s96, s25, 16 -; GFX9-NEXT: s_lshr_b32 s98, s25, 8 -; GFX9-NEXT: s_lshr_b32 s97, s24, 16 -; GFX9-NEXT: s_lshr_b32 s99, s24, 8 -; GFX9-NEXT: s_lshr_b32 s38, s23, 24 -; GFX9-NEXT: s_lshr_b32 s39, s23, 16 -; GFX9-NEXT: s_lshr_b32 s49, s23, 8 -; GFX9-NEXT: s_lshr_b32 s48, s22, 16 -; GFX9-NEXT: s_lshr_b32 s50, s22, 8 -; GFX9-NEXT: s_lshr_b32 s51, s21, 24 -; GFX9-NEXT: s_lshr_b32 s52, s21, 16 -; GFX9-NEXT: s_lshr_b32 s54, s21, 8 -; GFX9-NEXT: s_lshr_b32 s53, s20, 16 -; GFX9-NEXT: s_lshr_b32 s55, s20, 8 -; GFX9-NEXT: s_lshr_b32 s64, s19, 24 -; GFX9-NEXT: s_lshr_b32 s65, s19, 16 -; GFX9-NEXT: s_lshr_b32 s67, s19, 8 -; GFX9-NEXT: s_lshr_b32 s66, s18, 16 -; GFX9-NEXT: s_lshr_b32 s68, s18, 8 -; GFX9-NEXT: s_lshr_b32 s69, s17, 24 -; GFX9-NEXT: s_lshr_b32 s70, s17, 16 -; GFX9-NEXT: s_lshr_b32 s80, s17, 8 -; GFX9-NEXT: s_lshr_b32 s71, s16, 16 -; GFX9-NEXT: s_lshr_b32 s81, s16, 8 -; GFX9-NEXT: s_lshr_b64 s[46:47], s[4:5], 24 -; GFX9-NEXT: s_lshr_b64 s[56:57], s[6:7], 24 +; GFX9-NEXT: s_lshr_b32 s26, s5, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 49 +; GFX9-NEXT: s_lshr_b32 s26, s5, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 48 +; GFX9-NEXT: s_lshr_b32 s26, s5, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 47 +; GFX9-NEXT: s_lshr_b32 s26, s4, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 46 +; GFX9-NEXT: s_lshr_b32 s26, s4, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 45 +; GFX9-NEXT: s_lshr_b32 s26, s7, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 44 +; GFX9-NEXT: s_lshr_b32 s26, s7, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 43 +; GFX9-NEXT: s_lshr_b32 s26, s7, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 42 +; GFX9-NEXT: s_lshr_b32 s26, s6, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 41 +; GFX9-NEXT: s_lshr_b32 s26, s6, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 40 +; GFX9-NEXT: s_lshr_b32 s26, s9, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 39 +; GFX9-NEXT: s_lshr_b32 s26, s9, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 38 +; GFX9-NEXT: s_lshr_b32 s26, s9, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 37 +; GFX9-NEXT: s_lshr_b32 s26, s8, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 36 +; GFX9-NEXT: s_lshr_b32 s26, s8, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 35 +; GFX9-NEXT: s_lshr_b32 s26, s11, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 34 +; GFX9-NEXT: s_lshr_b32 s26, s11, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 33 +; GFX9-NEXT: s_lshr_b32 s26, s11, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 32 +; GFX9-NEXT: s_lshr_b32 s26, s10, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 31 +; GFX9-NEXT: s_lshr_b32 s26, s10, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 30 +; GFX9-NEXT: s_lshr_b32 s26, s13, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 29 +; GFX9-NEXT: s_lshr_b32 s26, s13, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 28 +; GFX9-NEXT: s_lshr_b32 s26, s13, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 27 +; GFX9-NEXT: s_lshr_b32 s26, s12, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 26 +; GFX9-NEXT: s_lshr_b32 s26, s12, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 25 +; GFX9-NEXT: s_lshr_b32 s26, s15, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 24 +; GFX9-NEXT: s_lshr_b32 s26, s15, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 23 +; GFX9-NEXT: s_lshr_b32 s26, s15, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 22 +; GFX9-NEXT: s_lshr_b32 s26, s14, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 21 +; GFX9-NEXT: s_lshr_b32 s26, s14, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 20 +; GFX9-NEXT: s_lshr_b32 s26, s17, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 19 +; GFX9-NEXT: s_lshr_b32 s26, s17, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 18 +; GFX9-NEXT: s_lshr_b32 s26, s17, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 17 +; GFX9-NEXT: s_lshr_b32 s26, s16, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 16 +; GFX9-NEXT: s_lshr_b32 s26, s16, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 15 +; GFX9-NEXT: s_lshr_b32 s26, s19, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 14 +; GFX9-NEXT: s_lshr_b32 s26, s19, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 13 +; GFX9-NEXT: s_lshr_b32 s26, s19, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 12 +; GFX9-NEXT: s_lshr_b32 s26, s18, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 11 +; GFX9-NEXT: s_lshr_b32 s26, s18, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 10 +; GFX9-NEXT: s_lshr_b32 s26, s21, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 9 +; GFX9-NEXT: s_lshr_b32 s26, s21, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 8 +; GFX9-NEXT: s_lshr_b32 s26, s21, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 7 +; GFX9-NEXT: s_lshr_b32 s26, s20, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 6 +; GFX9-NEXT: s_lshr_b32 s26, s20, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 5 +; GFX9-NEXT: s_lshr_b32 s26, s23, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 4 +; GFX9-NEXT: s_lshr_b32 s26, s23, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 3 +; GFX9-NEXT: s_lshr_b32 s26, s23, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 2 +; GFX9-NEXT: s_lshr_b32 s26, s22, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 1 +; GFX9-NEXT: s_lshr_b32 s26, s22, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 0 +; GFX9-NEXT: s_lshr_b32 s82, s25, 24 +; GFX9-NEXT: s_lshr_b32 s83, s25, 16 +; GFX9-NEXT: s_lshr_b32 s85, s25, 8 +; GFX9-NEXT: s_lshr_b32 s84, s24, 16 +; GFX9-NEXT: s_lshr_b32 s86, s24, 8 +; GFX9-NEXT: s_lshr_b32 s87, s41, 24 +; GFX9-NEXT: s_lshr_b32 s96, s41, 16 +; GFX9-NEXT: s_lshr_b32 s98, s41, 8 +; GFX9-NEXT: s_lshr_b32 s97, s40, 16 +; GFX9-NEXT: s_lshr_b32 s99, s40, 8 +; GFX9-NEXT: s_lshr_b32 s38, s43, 24 +; GFX9-NEXT: s_lshr_b32 s39, s43, 16 +; GFX9-NEXT: s_lshr_b32 s49, s43, 8 +; GFX9-NEXT: s_lshr_b32 s48, s42, 16 +; GFX9-NEXT: s_lshr_b32 s50, s42, 8 +; GFX9-NEXT: s_lshr_b32 s51, s45, 24 +; GFX9-NEXT: s_lshr_b32 s52, s45, 16 +; GFX9-NEXT: s_lshr_b32 s54, s45, 8 +; GFX9-NEXT: s_lshr_b32 s53, s44, 16 +; GFX9-NEXT: s_lshr_b32 s55, s44, 8 +; GFX9-NEXT: s_lshr_b32 s64, s47, 24 +; GFX9-NEXT: s_lshr_b32 s65, s47, 16 +; GFX9-NEXT: s_lshr_b32 s67, s47, 8 +; GFX9-NEXT: s_lshr_b32 s66, s46, 16 +; GFX9-NEXT: s_lshr_b32 s68, s46, 8 +; GFX9-NEXT: s_lshr_b32 s69, s57, 24 +; GFX9-NEXT: s_lshr_b32 s70, s57, 16 +; GFX9-NEXT: s_lshr_b32 s80, s57, 8 +; GFX9-NEXT: s_lshr_b32 s71, s56, 16 +; GFX9-NEXT: s_lshr_b32 s81, s56, 8 +; GFX9-NEXT: s_lshr_b64 s[26:27], s[4:5], 24 +; GFX9-NEXT: s_lshr_b64 s[28:29], s[6:7], 24 ; GFX9-NEXT: s_lshr_b64 s[58:59], s[8:9], 24 ; GFX9-NEXT: s_lshr_b64 s[60:61], s[10:11], 24 ; GFX9-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 ; GFX9-NEXT: s_lshr_b64 s[72:73], s[14:15], 24 -; GFX9-NEXT: s_lshr_b64 s[74:75], s[40:41], 24 -; GFX9-NEXT: s_lshr_b64 s[76:77], s[42:43], 24 -; GFX9-NEXT: s_lshr_b64 s[78:79], s[44:45], 24 -; GFX9-NEXT: s_lshr_b64 s[88:89], s[28:29], 24 -; GFX9-NEXT: s_lshr_b64 s[90:91], s[26:27], 24 -; GFX9-NEXT: s_lshr_b64 s[92:93], s[24:25], 24 -; GFX9-NEXT: s_lshr_b64 s[94:95], s[22:23], 24 -; GFX9-NEXT: s_lshr_b64 s[30:31], s[20:21], 24 -; GFX9-NEXT: s_lshr_b64 s[34:35], s[18:19], 24 -; GFX9-NEXT: s_lshr_b64 s[36:37], s[16:17], 24 +; GFX9-NEXT: s_lshr_b64 s[74:75], s[16:17], 24 +; GFX9-NEXT: s_lshr_b64 s[76:77], s[18:19], 24 +; GFX9-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 +; GFX9-NEXT: s_lshr_b64 s[88:89], s[22:23], 24 +; GFX9-NEXT: s_lshr_b64 s[90:91], s[24:25], 24 +; GFX9-NEXT: s_lshr_b64 s[92:93], s[40:41], 24 +; GFX9-NEXT: s_lshr_b64 s[94:95], s[42:43], 24 +; GFX9-NEXT: s_lshr_b64 s[30:31], s[44:45], 24 +; GFX9-NEXT: s_lshr_b64 s[34:35], s[46:47], 24 +; GFX9-NEXT: s_lshr_b64 s[36:37], s[56:57], 24 ; GFX9-NEXT: s_cbranch_execnz .LBB37_4 ; GFX9-NEXT: .LBB37_2: ; %cmp.true ; GFX9-NEXT: v_add_f32_e64 v2, s5, 1.0 @@ -47595,44 +46898,44 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[11:12] -; GFX9-NEXT: v_add_f32_e64 v14, s41, 1.0 -; GFX9-NEXT: v_add_f32_e64 v13, s40, 1.0 +; GFX9-NEXT: v_add_f32_e64 v14, s17, 1.0 +; GFX9-NEXT: v_add_f32_e64 v13, s16, 1.0 ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[13:14] -; GFX9-NEXT: v_add_f32_e64 v23, s43, 1.0 -; GFX9-NEXT: v_add_f32_e64 v22, s42, 1.0 +; GFX9-NEXT: v_add_f32_e64 v23, s19, 1.0 +; GFX9-NEXT: v_add_f32_e64 v22, s18, 1.0 ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[22:23] -; GFX9-NEXT: v_add_f32_e64 v25, s45, 1.0 -; GFX9-NEXT: v_add_f32_e64 v24, s44, 1.0 +; GFX9-NEXT: v_add_f32_e64 v25, s21, 1.0 +; GFX9-NEXT: v_add_f32_e64 v24, s20, 1.0 ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[24:25] -; GFX9-NEXT: v_add_f32_e64 v27, s29, 1.0 -; GFX9-NEXT: v_add_f32_e64 v26, s28, 1.0 +; GFX9-NEXT: v_add_f32_e64 v27, s23, 1.0 +; GFX9-NEXT: v_add_f32_e64 v26, s22, 1.0 ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[26:27] -; GFX9-NEXT: v_add_f32_e64 v29, s27, 1.0 -; GFX9-NEXT: v_add_f32_e64 v28, s26, 1.0 +; GFX9-NEXT: v_add_f32_e64 v29, s25, 1.0 +; GFX9-NEXT: v_add_f32_e64 v28, s24, 1.0 ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[28:29] -; GFX9-NEXT: v_add_f32_e64 v31, s25, 1.0 -; GFX9-NEXT: v_add_f32_e64 v30, s24, 1.0 +; GFX9-NEXT: v_add_f32_e64 v31, s41, 1.0 +; GFX9-NEXT: v_add_f32_e64 v30, s40, 1.0 ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[30:31] -; GFX9-NEXT: v_add_f32_e64 v33, s23, 1.0 -; GFX9-NEXT: v_add_f32_e64 v32, s22, 1.0 +; GFX9-NEXT: v_add_f32_e64 v33, s43, 1.0 +; GFX9-NEXT: v_add_f32_e64 v32, s42, 1.0 ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill @@ -47739,17 +47042,17 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v31 ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v30 -; GFX9-NEXT: v_add_f32_e64 v35, s21, 1.0 -; GFX9-NEXT: v_add_f32_e64 v34, s20, 1.0 +; GFX9-NEXT: v_add_f32_e64 v35, s45, 1.0 +; GFX9-NEXT: v_add_f32_e64 v34, s44, 1.0 ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v33 -; GFX9-NEXT: v_add_f32_e64 v37, s19, 1.0 -; GFX9-NEXT: v_add_f32_e64 v36, s18, 1.0 +; GFX9-NEXT: v_add_f32_e64 v37, s47, 1.0 +; GFX9-NEXT: v_add_f32_e64 v36, s46, 1.0 ; GFX9-NEXT: v_lshrrev_b64 v[40:41], 24, v[34:35] ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v33 -; GFX9-NEXT: v_add_f32_e64 v39, s17, 1.0 -; GFX9-NEXT: v_add_f32_e64 v38, s16, 1.0 +; GFX9-NEXT: v_add_f32_e64 v39, s57, 1.0 +; GFX9-NEXT: v_add_f32_e64 v38, s56, 1.0 ; GFX9-NEXT: v_lshrrev_b64 v[41:42], 24, v[36:37] ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v32 @@ -47785,10 +47088,10 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; GFX9-NEXT: v_lshrrev_b32_e32 v48, 8, v38 ; GFX9-NEXT: s_branch .LBB37_5 ; GFX9-NEXT: .LBB37_3: -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 ; GFX9-NEXT: ; implicit-def: $sgpr81 ; GFX9-NEXT: ; implicit-def: $sgpr71 ; GFX9-NEXT: ; implicit-def: $sgpr80 @@ -47833,104 +47136,104 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; GFX9-NEXT: ; implicit-def: $sgpr62 ; GFX9-NEXT: ; implicit-def: $sgpr60 ; GFX9-NEXT: ; implicit-def: $sgpr58 -; GFX9-NEXT: ; implicit-def: $sgpr56 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr28 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 ; GFX9-NEXT: s_branch .LBB37_2 ; GFX9-NEXT: .LBB37_4: ; GFX9-NEXT: v_mov_b32_e32 v52, s48 @@ -48096,11 +47399,11 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v40, s4 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v40, s46 +; GFX9-NEXT: v_mov_b32_e32 v40, s26 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v40, s56 +; GFX9-NEXT: v_mov_b32_e32 v40, s28 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill @@ -48149,26 +47452,26 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v38, s16 -; GFX9-NEXT: v_mov_b32_e32 v39, s17 -; GFX9-NEXT: v_mov_b32_e32 v36, s18 -; GFX9-NEXT: v_mov_b32_e32 v37, s19 -; GFX9-NEXT: v_mov_b32_e32 v34, s20 -; GFX9-NEXT: v_mov_b32_e32 v35, s21 -; GFX9-NEXT: v_mov_b32_e32 v32, s22 -; GFX9-NEXT: v_mov_b32_e32 v33, s23 -; GFX9-NEXT: v_mov_b32_e32 v30, s24 -; GFX9-NEXT: v_mov_b32_e32 v31, s25 -; GFX9-NEXT: v_mov_b32_e32 v28, s26 -; GFX9-NEXT: v_mov_b32_e32 v29, s27 -; GFX9-NEXT: v_mov_b32_e32 v26, s28 -; GFX9-NEXT: v_mov_b32_e32 v27, s29 -; GFX9-NEXT: v_mov_b32_e32 v24, s44 -; GFX9-NEXT: v_mov_b32_e32 v25, s45 -; GFX9-NEXT: v_mov_b32_e32 v22, s42 -; GFX9-NEXT: v_mov_b32_e32 v23, s43 -; GFX9-NEXT: v_mov_b32_e32 v13, s40 -; GFX9-NEXT: v_mov_b32_e32 v14, s41 +; GFX9-NEXT: v_mov_b32_e32 v38, s56 +; GFX9-NEXT: v_mov_b32_e32 v39, s57 +; GFX9-NEXT: v_mov_b32_e32 v36, s46 +; GFX9-NEXT: v_mov_b32_e32 v37, s47 +; GFX9-NEXT: v_mov_b32_e32 v34, s44 +; GFX9-NEXT: v_mov_b32_e32 v35, s45 +; GFX9-NEXT: v_mov_b32_e32 v32, s42 +; GFX9-NEXT: v_mov_b32_e32 v33, s43 +; GFX9-NEXT: v_mov_b32_e32 v30, s40 +; GFX9-NEXT: v_mov_b32_e32 v31, s41 +; GFX9-NEXT: v_mov_b32_e32 v28, s24 +; GFX9-NEXT: v_mov_b32_e32 v29, s25 +; GFX9-NEXT: v_mov_b32_e32 v26, s22 +; GFX9-NEXT: v_mov_b32_e32 v27, s23 +; GFX9-NEXT: v_mov_b32_e32 v24, s20 +; GFX9-NEXT: v_mov_b32_e32 v25, s21 +; GFX9-NEXT: v_mov_b32_e32 v22, s18 +; GFX9-NEXT: v_mov_b32_e32 v23, s19 +; GFX9-NEXT: v_mov_b32_e32 v13, s16 +; GFX9-NEXT: v_mov_b32_e32 v14, s17 ; GFX9-NEXT: v_mov_b32_e32 v11, s14 ; GFX9-NEXT: v_mov_b32_e32 v12, s15 ; GFX9-NEXT: v_mov_b32_e32 v9, s12 @@ -48626,32 +47929,70 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; GFX11-NEXT: s_mov_b32 exec_lo, s4 ; GFX11-NEXT: v_writelane_b32 v75, s30, 0 ; GFX11-NEXT: v_writelane_b32 v76, s96, 0 -; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 -; GFX11-NEXT: v_readfirstlane_b32 s40, v1 -; GFX11-NEXT: v_readfirstlane_b32 s41, v2 +; GFX11-NEXT: v_dual_mov_b32 v16, s0 :: v_dual_mov_b32 v17, s1 +; GFX11-NEXT: v_dual_mov_b32 v18, s2 :: v_dual_mov_b32 v19, s3 ; GFX11-NEXT: v_writelane_b32 v75, s31, 1 ; GFX11-NEXT: v_writelane_b32 v76, s97, 1 -; GFX11-NEXT: v_readfirstlane_b32 s14, v3 -; GFX11-NEXT: v_readfirstlane_b32 s15, v4 -; GFX11-NEXT: v_readfirstlane_b32 s4, v5 +; GFX11-NEXT: v_dual_mov_b32 v20, s16 :: v_dual_mov_b32 v21, s17 +; GFX11-NEXT: v_dual_mov_b32 v22, s18 :: v_dual_mov_b32 v23, s19 ; GFX11-NEXT: v_writelane_b32 v75, s34, 2 ; GFX11-NEXT: v_writelane_b32 v76, s98, 2 -; GFX11-NEXT: v_readfirstlane_b32 s5, v6 -; GFX11-NEXT: v_readfirstlane_b32 s6, v7 -; GFX11-NEXT: v_readfirstlane_b32 s7, v8 +; GFX11-NEXT: v_dual_mov_b32 v24, s20 :: v_dual_mov_b32 v25, s21 +; GFX11-NEXT: v_dual_mov_b32 v26, s22 :: v_dual_mov_b32 v27, s23 ; GFX11-NEXT: v_writelane_b32 v75, s35, 3 ; GFX11-NEXT: v_writelane_b32 v76, s99, 3 -; GFX11-NEXT: v_readfirstlane_b32 s8, v9 -; GFX11-NEXT: v_readfirstlane_b32 s9, v10 -; GFX11-NEXT: v_readfirstlane_b32 s10, v11 +; GFX11-NEXT: v_dual_mov_b32 v28, s24 :: v_dual_mov_b32 v29, s25 +; GFX11-NEXT: v_dual_mov_b32 v30, s26 :: v_dual_mov_b32 v31, s27 ; GFX11-NEXT: v_writelane_b32 v75, s36, 4 ; GFX11-NEXT: v_writelane_b32 v76, s100, 4 -; GFX11-NEXT: v_readfirstlane_b32 s11, v12 -; GFX11-NEXT: v_readfirstlane_b32 s12, v13 -; GFX11-NEXT: v_readfirstlane_b32 s13, v14 +; GFX11-NEXT: v_dual_mov_b32 v32, s28 :: v_dual_mov_b32 v33, s29 +; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 ; GFX11-NEXT: v_writelane_b32 v75, s37, 5 ; GFX11-NEXT: v_writelane_b32 v76, s101, 5 +; GFX11-NEXT: v_readfirstlane_b32 s40, v16 +; GFX11-NEXT: v_readfirstlane_b32 s41, v17 +; GFX11-NEXT: v_readfirstlane_b32 s28, v18 +; GFX11-NEXT: v_writelane_b32 v75, s38, 6 +; GFX11-NEXT: v_writelane_b32 v76, s102, 6 +; GFX11-NEXT: v_readfirstlane_b32 s29, v19 +; GFX11-NEXT: v_readfirstlane_b32 s26, v20 +; GFX11-NEXT: v_readfirstlane_b32 s27, v21 +; GFX11-NEXT: v_writelane_b32 v75, s39, 7 +; GFX11-NEXT: v_writelane_b32 v76, s103, 7 +; GFX11-NEXT: v_readfirstlane_b32 s24, v22 +; GFX11-NEXT: v_readfirstlane_b32 s25, v23 +; GFX11-NEXT: v_readfirstlane_b32 s22, v24 +; GFX11-NEXT: v_writelane_b32 v75, s48, 8 +; GFX11-NEXT: v_readfirstlane_b32 s23, v25 +; GFX11-NEXT: v_readfirstlane_b32 s20, v26 +; GFX11-NEXT: v_readfirstlane_b32 s21, v27 +; GFX11-NEXT: v_readfirstlane_b32 s18, v28 +; GFX11-NEXT: v_writelane_b32 v75, s49, 9 +; GFX11-NEXT: v_readfirstlane_b32 s19, v29 +; GFX11-NEXT: v_readfirstlane_b32 s16, v30 +; GFX11-NEXT: v_readfirstlane_b32 s17, v31 +; GFX11-NEXT: v_readfirstlane_b32 s14, v32 +; GFX11-NEXT: v_writelane_b32 v75, s50, 10 +; GFX11-NEXT: v_readfirstlane_b32 s15, v33 +; GFX11-NEXT: v_readfirstlane_b32 s12, v1 +; GFX11-NEXT: v_readfirstlane_b32 s13, v2 +; GFX11-NEXT: v_readfirstlane_b32 s10, v3 +; GFX11-NEXT: v_writelane_b32 v75, s51, 11 +; GFX11-NEXT: v_readfirstlane_b32 s11, v4 +; GFX11-NEXT: v_readfirstlane_b32 s0, v5 +; GFX11-NEXT: v_readfirstlane_b32 s1, v6 +; GFX11-NEXT: v_readfirstlane_b32 s2, v7 +; GFX11-NEXT: v_writelane_b32 v75, s52, 12 +; GFX11-NEXT: v_readfirstlane_b32 s3, v8 +; GFX11-NEXT: v_readfirstlane_b32 s4, v9 +; GFX11-NEXT: v_readfirstlane_b32 s5, v10 +; GFX11-NEXT: v_readfirstlane_b32 s6, v11 +; GFX11-NEXT: v_writelane_b32 v75, s53, 13 +; GFX11-NEXT: v_readfirstlane_b32 s7, v12 +; GFX11-NEXT: v_readfirstlane_b32 s8, v13 +; GFX11-NEXT: v_readfirstlane_b32 s9, v14 ; GFX11-NEXT: s_mov_b32 vcc_hi, 0 +; GFX11-NEXT: v_writelane_b32 v75, s54, 14 ; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo ; GFX11-NEXT: s_clause 0x12 ; 76-byte Folded Spill ; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:72 @@ -48673,20 +48014,9 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:8 ; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:4 ; GFX11-NEXT: scratch_store_b32 off, v74, s32 -; GFX11-NEXT: v_writelane_b32 v75, s38, 6 -; GFX11-NEXT: v_writelane_b32 v76, s102, 6 +; GFX11-NEXT: v_writelane_b32 v76, s104, 8 ; GFX11-NEXT: ; implicit-def: $vgpr77 : SGPR spill to VGPR lane ; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane -; GFX11-NEXT: v_writelane_b32 v75, s39, 7 -; GFX11-NEXT: v_writelane_b32 v76, s103, 7 -; GFX11-NEXT: v_writelane_b32 v75, s48, 8 -; GFX11-NEXT: v_writelane_b32 v76, s104, 8 -; GFX11-NEXT: v_writelane_b32 v75, s49, 9 -; GFX11-NEXT: v_writelane_b32 v75, s50, 10 -; GFX11-NEXT: v_writelane_b32 v75, s51, 11 -; GFX11-NEXT: v_writelane_b32 v75, s52, 12 -; GFX11-NEXT: v_writelane_b32 v75, s53, 13 -; GFX11-NEXT: v_writelane_b32 v75, s54, 14 ; GFX11-NEXT: v_writelane_b32 v75, s55, 15 ; GFX11-NEXT: v_writelane_b32 v75, s64, 16 ; GFX11-NEXT: v_writelane_b32 v75, s65, 17 @@ -48706,190 +48036,190 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; GFX11-NEXT: v_writelane_b32 v75, s87, 31 ; GFX11-NEXT: s_cbranch_scc0 .LBB37_3 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: s_lshr_b32 s42, s13, 24 -; GFX11-NEXT: s_lshr_b32 s36, s27, 16 +; GFX11-NEXT: s_lshr_b32 s42, s9, 24 +; GFX11-NEXT: s_lshr_b32 s36, s17, 16 ; GFX11-NEXT: v_writelane_b32 v78, s42, 8 -; GFX11-NEXT: s_lshr_b32 s42, s13, 16 -; GFX11-NEXT: s_lshr_b32 s38, s27, 8 -; GFX11-NEXT: s_lshr_b32 s37, s26, 16 -; GFX11-NEXT: s_lshr_b32 s39, s26, 8 +; GFX11-NEXT: s_lshr_b32 s42, s9, 16 +; GFX11-NEXT: s_lshr_b32 s38, s17, 8 +; GFX11-NEXT: s_lshr_b32 s37, s16, 16 +; GFX11-NEXT: s_lshr_b32 s39, s16, 8 ; GFX11-NEXT: v_writelane_b32 v78, s42, 7 -; GFX11-NEXT: s_lshr_b32 s42, s13, 8 -; GFX11-NEXT: s_lshr_b32 s48, s25, 24 -; GFX11-NEXT: s_lshr_b32 s49, s25, 16 -; GFX11-NEXT: s_lshr_b32 s51, s25, 8 +; GFX11-NEXT: s_lshr_b32 s42, s9, 8 +; GFX11-NEXT: s_lshr_b32 s48, s19, 24 +; GFX11-NEXT: s_lshr_b32 s49, s19, 16 +; GFX11-NEXT: s_lshr_b32 s51, s19, 8 ; GFX11-NEXT: v_writelane_b32 v78, s42, 6 -; GFX11-NEXT: s_lshr_b32 s42, s12, 16 -; GFX11-NEXT: s_lshr_b32 s50, s24, 16 -; GFX11-NEXT: s_lshr_b32 s52, s24, 8 -; GFX11-NEXT: s_lshr_b32 s53, s23, 24 +; GFX11-NEXT: s_lshr_b32 s42, s8, 16 +; GFX11-NEXT: s_lshr_b32 s50, s18, 16 +; GFX11-NEXT: s_lshr_b32 s52, s18, 8 +; GFX11-NEXT: s_lshr_b32 s53, s21, 24 ; GFX11-NEXT: v_writelane_b32 v78, s42, 5 -; GFX11-NEXT: s_lshr_b32 s42, s12, 8 -; GFX11-NEXT: s_lshr_b32 s54, s23, 16 -; GFX11-NEXT: s_lshr_b32 s64, s23, 8 -; GFX11-NEXT: s_lshr_b32 s55, s22, 16 +; GFX11-NEXT: s_lshr_b32 s42, s8, 8 +; GFX11-NEXT: s_lshr_b32 s54, s21, 16 +; GFX11-NEXT: s_lshr_b32 s64, s21, 8 +; GFX11-NEXT: s_lshr_b32 s55, s20, 16 ; GFX11-NEXT: v_writelane_b32 v78, s42, 4 -; GFX11-NEXT: s_lshr_b32 s42, s11, 24 -; GFX11-NEXT: s_lshr_b32 s65, s22, 8 -; GFX11-NEXT: s_lshr_b32 s66, s21, 24 -; GFX11-NEXT: s_lshr_b32 s67, s21, 16 +; GFX11-NEXT: s_lshr_b32 s42, s7, 24 +; GFX11-NEXT: s_lshr_b32 s65, s20, 8 +; GFX11-NEXT: s_lshr_b32 s66, s23, 24 +; GFX11-NEXT: s_lshr_b32 s67, s23, 16 ; GFX11-NEXT: v_writelane_b32 v78, s42, 3 -; GFX11-NEXT: s_lshr_b32 s42, s11, 16 -; GFX11-NEXT: s_lshr_b32 s69, s21, 8 -; GFX11-NEXT: s_lshr_b32 s68, s20, 16 -; GFX11-NEXT: s_lshr_b32 s70, s20, 8 +; GFX11-NEXT: s_lshr_b32 s42, s7, 16 +; GFX11-NEXT: s_lshr_b32 s69, s23, 8 +; GFX11-NEXT: s_lshr_b32 s68, s22, 16 +; GFX11-NEXT: s_lshr_b32 s70, s22, 8 ; GFX11-NEXT: v_writelane_b32 v78, s42, 2 -; GFX11-NEXT: s_lshr_b32 s42, s11, 8 -; GFX11-NEXT: s_lshr_b32 s71, s19, 24 -; GFX11-NEXT: s_lshr_b32 s80, s19, 16 -; GFX11-NEXT: s_lshr_b32 s82, s19, 8 +; GFX11-NEXT: s_lshr_b32 s42, s7, 8 +; GFX11-NEXT: s_lshr_b32 s71, s25, 24 +; GFX11-NEXT: s_lshr_b32 s80, s25, 16 +; GFX11-NEXT: s_lshr_b32 s82, s25, 8 ; GFX11-NEXT: v_writelane_b32 v78, s42, 1 -; GFX11-NEXT: s_lshr_b32 s42, s10, 16 -; GFX11-NEXT: s_lshr_b32 s81, s18, 16 -; GFX11-NEXT: s_lshr_b32 s83, s18, 8 -; GFX11-NEXT: s_lshr_b32 s84, s17, 24 +; GFX11-NEXT: s_lshr_b32 s42, s6, 16 +; GFX11-NEXT: s_lshr_b32 s81, s24, 16 +; GFX11-NEXT: s_lshr_b32 s83, s24, 8 +; GFX11-NEXT: s_lshr_b32 s84, s27, 24 ; GFX11-NEXT: v_writelane_b32 v78, s42, 0 -; GFX11-NEXT: s_lshr_b32 s42, s10, 8 -; GFX11-NEXT: s_lshr_b32 s85, s17, 16 +; GFX11-NEXT: s_lshr_b32 s42, s6, 8 +; GFX11-NEXT: s_lshr_b32 s85, s27, 16 ; GFX11-NEXT: v_writelane_b32 v77, s42, 31 -; GFX11-NEXT: s_lshr_b32 s42, s9, 24 -; GFX11-NEXT: s_lshr_b32 s87, s17, 8 -; GFX11-NEXT: s_lshr_b32 s86, s16, 16 -; GFX11-NEXT: s_lshr_b32 s96, s16, 8 +; GFX11-NEXT: s_lshr_b32 s42, s5, 24 +; GFX11-NEXT: s_lshr_b32 s87, s27, 8 +; GFX11-NEXT: s_lshr_b32 s86, s26, 16 +; GFX11-NEXT: s_lshr_b32 s96, s26, 8 ; GFX11-NEXT: v_writelane_b32 v77, s42, 30 -; GFX11-NEXT: s_lshr_b32 s42, s9, 16 -; GFX11-NEXT: s_lshr_b32 s97, s3, 24 -; GFX11-NEXT: s_lshr_b32 s98, s3, 16 -; GFX11-NEXT: s_lshr_b32 s100, s3, 8 +; GFX11-NEXT: s_lshr_b32 s42, s5, 16 +; GFX11-NEXT: s_lshr_b32 s97, s29, 24 +; GFX11-NEXT: s_lshr_b32 s98, s29, 16 +; GFX11-NEXT: s_lshr_b32 s100, s29, 8 ; GFX11-NEXT: v_writelane_b32 v77, s42, 29 -; GFX11-NEXT: s_lshr_b32 s42, s9, 8 -; GFX11-NEXT: s_lshr_b32 s99, s2, 16 -; GFX11-NEXT: s_lshr_b32 s101, s2, 8 -; GFX11-NEXT: s_lshr_b32 s102, s1, 24 +; GFX11-NEXT: s_lshr_b32 s42, s5, 8 +; GFX11-NEXT: s_lshr_b32 s99, s28, 16 +; GFX11-NEXT: s_lshr_b32 s101, s28, 8 +; GFX11-NEXT: s_lshr_b32 s102, s41, 24 ; GFX11-NEXT: v_writelane_b32 v77, s42, 28 -; GFX11-NEXT: s_lshr_b32 s42, s8, 16 -; GFX11-NEXT: s_lshr_b32 s103, s1, 16 -; GFX11-NEXT: s_lshr_b32 s34, s1, 8 -; GFX11-NEXT: s_lshr_b32 s104, s0, 16 +; GFX11-NEXT: s_lshr_b32 s42, s4, 16 +; GFX11-NEXT: s_lshr_b32 s103, s41, 16 +; GFX11-NEXT: s_lshr_b32 s34, s41, 8 +; GFX11-NEXT: s_lshr_b32 s104, s40, 16 ; GFX11-NEXT: v_writelane_b32 v77, s42, 27 -; GFX11-NEXT: s_lshr_b32 s42, s8, 8 -; GFX11-NEXT: s_lshr_b32 s35, s0, 8 -; GFX11-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 -; GFX11-NEXT: s_lshr_b64 s[72:73], s[10:11], 24 +; GFX11-NEXT: s_lshr_b32 s42, s4, 8 +; GFX11-NEXT: s_lshr_b32 s35, s40, 8 +; GFX11-NEXT: s_lshr_b64 s[62:63], s[8:9], 24 +; GFX11-NEXT: s_lshr_b64 s[72:73], s[6:7], 24 ; GFX11-NEXT: v_writelane_b32 v77, s42, 26 -; GFX11-NEXT: s_lshr_b32 s42, s7, 24 -; GFX11-NEXT: s_lshr_b64 s[74:75], s[8:9], 24 -; GFX11-NEXT: s_lshr_b64 s[76:77], s[6:7], 24 -; GFX11-NEXT: s_lshr_b64 s[78:79], s[4:5], 24 +; GFX11-NEXT: s_lshr_b32 s42, s3, 24 +; GFX11-NEXT: s_lshr_b64 s[74:75], s[4:5], 24 +; GFX11-NEXT: s_lshr_b64 s[76:77], s[2:3], 24 +; GFX11-NEXT: s_lshr_b64 s[78:79], s[0:1], 24 ; GFX11-NEXT: v_writelane_b32 v77, s42, 25 -; GFX11-NEXT: s_lshr_b32 s42, s7, 16 -; GFX11-NEXT: s_lshr_b64 s[88:89], s[14:15], 24 -; GFX11-NEXT: s_lshr_b64 s[90:91], s[40:41], 24 -; GFX11-NEXT: s_lshr_b64 s[92:93], s[28:29], 24 +; GFX11-NEXT: s_lshr_b32 s42, s3, 16 +; GFX11-NEXT: s_lshr_b64 s[88:89], s[10:11], 24 +; GFX11-NEXT: s_lshr_b64 s[90:91], s[12:13], 24 +; GFX11-NEXT: s_lshr_b64 s[92:93], s[14:15], 24 ; GFX11-NEXT: v_writelane_b32 v77, s42, 24 -; GFX11-NEXT: s_lshr_b32 s42, s7, 8 -; GFX11-NEXT: s_lshr_b64 s[94:95], s[26:27], 24 -; GFX11-NEXT: s_lshr_b64 s[30:31], s[24:25], 24 -; GFX11-NEXT: s_lshr_b64 s[60:61], s[22:23], 24 +; GFX11-NEXT: s_lshr_b32 s42, s3, 8 +; GFX11-NEXT: s_lshr_b64 s[94:95], s[16:17], 24 +; GFX11-NEXT: s_lshr_b64 s[30:31], s[18:19], 24 +; GFX11-NEXT: s_lshr_b64 s[60:61], s[20:21], 24 ; GFX11-NEXT: v_writelane_b32 v77, s42, 23 -; GFX11-NEXT: s_lshr_b32 s42, s6, 16 -; GFX11-NEXT: s_lshr_b64 s[58:59], s[20:21], 24 -; GFX11-NEXT: s_lshr_b64 s[56:57], s[18:19], 24 -; GFX11-NEXT: s_lshr_b64 s[46:47], s[16:17], 24 +; GFX11-NEXT: s_lshr_b32 s42, s2, 16 +; GFX11-NEXT: s_lshr_b64 s[58:59], s[22:23], 24 +; GFX11-NEXT: s_lshr_b64 s[56:57], s[24:25], 24 +; GFX11-NEXT: s_lshr_b64 s[46:47], s[26:27], 24 ; GFX11-NEXT: v_writelane_b32 v77, s42, 22 -; GFX11-NEXT: s_lshr_b32 s42, s6, 8 -; GFX11-NEXT: s_lshr_b64 s[44:45], s[2:3], 24 +; GFX11-NEXT: s_lshr_b32 s42, s2, 8 +; GFX11-NEXT: s_lshr_b64 s[44:45], s[28:29], 24 ; GFX11-NEXT: v_writelane_b32 v77, s42, 21 -; GFX11-NEXT: s_lshr_b32 s42, s5, 24 +; GFX11-NEXT: s_lshr_b32 s42, s1, 24 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: v_writelane_b32 v77, s42, 20 -; GFX11-NEXT: s_lshr_b32 s42, s5, 16 +; GFX11-NEXT: s_lshr_b32 s42, s1, 16 ; GFX11-NEXT: v_writelane_b32 v77, s42, 19 -; GFX11-NEXT: s_lshr_b32 s42, s5, 8 +; GFX11-NEXT: s_lshr_b32 s42, s1, 8 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: v_writelane_b32 v77, s42, 18 -; GFX11-NEXT: s_lshr_b32 s42, s4, 16 +; GFX11-NEXT: s_lshr_b32 s42, s0, 16 ; GFX11-NEXT: v_writelane_b32 v77, s42, 17 -; GFX11-NEXT: s_lshr_b32 s42, s4, 8 +; GFX11-NEXT: s_lshr_b32 s42, s0, 8 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: v_writelane_b32 v77, s42, 16 -; GFX11-NEXT: s_lshr_b32 s42, s15, 24 +; GFX11-NEXT: s_lshr_b32 s42, s11, 24 ; GFX11-NEXT: v_writelane_b32 v77, s42, 15 -; GFX11-NEXT: s_lshr_b32 s42, s15, 16 +; GFX11-NEXT: s_lshr_b32 s42, s11, 16 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: v_writelane_b32 v77, s42, 14 -; GFX11-NEXT: s_lshr_b32 s42, s15, 8 +; GFX11-NEXT: s_lshr_b32 s42, s11, 8 ; GFX11-NEXT: v_writelane_b32 v77, s42, 13 -; GFX11-NEXT: s_lshr_b32 s42, s14, 16 +; GFX11-NEXT: s_lshr_b32 s42, s10, 16 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: v_writelane_b32 v77, s42, 12 -; GFX11-NEXT: s_lshr_b32 s42, s14, 8 +; GFX11-NEXT: s_lshr_b32 s42, s10, 8 ; GFX11-NEXT: v_writelane_b32 v77, s42, 11 -; GFX11-NEXT: s_lshr_b32 s42, s41, 24 +; GFX11-NEXT: s_lshr_b32 s42, s13, 24 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: v_writelane_b32 v77, s42, 10 -; GFX11-NEXT: s_lshr_b32 s42, s41, 16 +; GFX11-NEXT: s_lshr_b32 s42, s13, 16 ; GFX11-NEXT: v_writelane_b32 v77, s42, 9 -; GFX11-NEXT: s_lshr_b32 s42, s41, 8 +; GFX11-NEXT: s_lshr_b32 s42, s13, 8 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: v_writelane_b32 v77, s42, 8 -; GFX11-NEXT: s_lshr_b32 s42, s40, 16 +; GFX11-NEXT: s_lshr_b32 s42, s12, 16 ; GFX11-NEXT: v_writelane_b32 v77, s42, 7 -; GFX11-NEXT: s_lshr_b32 s42, s40, 8 +; GFX11-NEXT: s_lshr_b32 s42, s12, 8 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: v_writelane_b32 v77, s42, 6 -; GFX11-NEXT: s_lshr_b32 s42, s29, 24 +; GFX11-NEXT: s_lshr_b32 s42, s15, 24 ; GFX11-NEXT: v_writelane_b32 v77, s42, 5 -; GFX11-NEXT: s_lshr_b32 s42, s29, 16 +; GFX11-NEXT: s_lshr_b32 s42, s15, 16 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: v_writelane_b32 v77, s42, 4 -; GFX11-NEXT: s_lshr_b32 s42, s29, 8 +; GFX11-NEXT: s_lshr_b32 s42, s15, 8 ; GFX11-NEXT: v_writelane_b32 v77, s42, 3 -; GFX11-NEXT: s_lshr_b32 s42, s28, 16 +; GFX11-NEXT: s_lshr_b32 s42, s14, 16 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: v_writelane_b32 v77, s42, 2 -; GFX11-NEXT: s_lshr_b32 s42, s28, 8 +; GFX11-NEXT: s_lshr_b32 s42, s14, 8 ; GFX11-NEXT: v_writelane_b32 v77, s42, 1 -; GFX11-NEXT: s_lshr_b32 s42, s27, 24 +; GFX11-NEXT: s_lshr_b32 s42, s17, 24 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: v_writelane_b32 v77, s42, 0 -; GFX11-NEXT: s_lshr_b64 s[42:43], s[0:1], 24 +; GFX11-NEXT: s_lshr_b64 s[42:43], s[40:41], 24 ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, vcc_hi ; GFX11-NEXT: s_cbranch_vccnz .LBB37_4 ; GFX11-NEXT: .LBB37_2: ; %cmp.true -; GFX11-NEXT: v_add_f32_e64 v22, s27, 1.0 -; GFX11-NEXT: v_add_f32_e64 v21, s26, 1.0 -; GFX11-NEXT: v_add_f32_e64 v24, s25, 1.0 -; GFX11-NEXT: v_add_f32_e64 v23, s24, 1.0 -; GFX11-NEXT: v_add_f32_e64 v29, s23, 1.0 -; GFX11-NEXT: v_add_f32_e64 v28, s22, 1.0 -; GFX11-NEXT: v_add_f32_e64 v31, s21, 1.0 -; GFX11-NEXT: v_add_f32_e64 v30, s20, 1.0 -; GFX11-NEXT: v_add_f32_e64 v35, s19, 1.0 -; GFX11-NEXT: v_add_f32_e64 v34, s18, 1.0 -; GFX11-NEXT: v_add_f32_e64 v37, s17, 1.0 -; GFX11-NEXT: v_add_f32_e64 v36, s16, 1.0 -; GFX11-NEXT: v_add_f32_e64 v6, s9, 1.0 -; GFX11-NEXT: v_add_f32_e64 v5, s8, 1.0 +; GFX11-NEXT: v_add_f32_e64 v22, s17, 1.0 +; GFX11-NEXT: v_add_f32_e64 v21, s16, 1.0 +; GFX11-NEXT: v_add_f32_e64 v24, s19, 1.0 +; GFX11-NEXT: v_add_f32_e64 v23, s18, 1.0 +; GFX11-NEXT: v_add_f32_e64 v29, s21, 1.0 +; GFX11-NEXT: v_add_f32_e64 v28, s20, 1.0 +; GFX11-NEXT: v_add_f32_e64 v31, s23, 1.0 +; GFX11-NEXT: v_add_f32_e64 v30, s22, 1.0 +; GFX11-NEXT: v_add_f32_e64 v35, s25, 1.0 +; GFX11-NEXT: v_add_f32_e64 v34, s24, 1.0 +; GFX11-NEXT: v_add_f32_e64 v37, s27, 1.0 +; GFX11-NEXT: v_add_f32_e64 v36, s26, 1.0 +; GFX11-NEXT: v_add_f32_e64 v6, s5, 1.0 +; GFX11-NEXT: v_add_f32_e64 v5, s4, 1.0 ; GFX11-NEXT: v_lshrrev_b64 v[64:65], 24, v[21:22] -; GFX11-NEXT: v_add_f32_e64 v53, s1, 1.0 -; GFX11-NEXT: v_add_f32_e64 v52, s0, 1.0 -; GFX11-NEXT: v_add_f32_e64 v49, s3, 1.0 -; GFX11-NEXT: v_add_f32_e64 v48, s2, 1.0 -; GFX11-NEXT: v_add_f32_e64 v18, s29, 1.0 -; GFX11-NEXT: v_add_f32_e64 v17, s28, 1.0 -; GFX11-NEXT: v_add_f32_e64 v14, s41, 1.0 -; GFX11-NEXT: v_add_f32_e64 v13, s40, 1.0 -; GFX11-NEXT: v_add_f32_e64 v12, s15, 1.0 -; GFX11-NEXT: v_add_f32_e64 v11, s14, 1.0 -; GFX11-NEXT: v_add_f32_e64 v10, s5, 1.0 -; GFX11-NEXT: v_add_f32_e64 v8, s7, 1.0 -; GFX11-NEXT: v_add_f32_e64 v4, s11, 1.0 -; GFX11-NEXT: v_add_f32_e64 v2, s13, 1.0 -; GFX11-NEXT: v_add_f32_e64 v1, s12, 1.0 -; GFX11-NEXT: v_add_f32_e64 v3, s10, 1.0 -; GFX11-NEXT: v_add_f32_e64 v7, s6, 1.0 -; GFX11-NEXT: v_add_f32_e64 v9, s4, 1.0 +; GFX11-NEXT: v_add_f32_e64 v53, s41, 1.0 +; GFX11-NEXT: v_add_f32_e64 v52, s40, 1.0 +; GFX11-NEXT: v_add_f32_e64 v49, s29, 1.0 +; GFX11-NEXT: v_add_f32_e64 v48, s28, 1.0 +; GFX11-NEXT: v_add_f32_e64 v18, s15, 1.0 +; GFX11-NEXT: v_add_f32_e64 v17, s14, 1.0 +; GFX11-NEXT: v_add_f32_e64 v14, s13, 1.0 +; GFX11-NEXT: v_add_f32_e64 v13, s12, 1.0 +; GFX11-NEXT: v_add_f32_e64 v12, s11, 1.0 +; GFX11-NEXT: v_add_f32_e64 v11, s10, 1.0 +; GFX11-NEXT: v_add_f32_e64 v10, s1, 1.0 +; GFX11-NEXT: v_add_f32_e64 v8, s3, 1.0 +; GFX11-NEXT: v_add_f32_e64 v4, s7, 1.0 +; GFX11-NEXT: v_add_f32_e64 v2, s9, 1.0 +; GFX11-NEXT: v_add_f32_e64 v1, s8, 1.0 +; GFX11-NEXT: v_add_f32_e64 v3, s6, 1.0 +; GFX11-NEXT: v_add_f32_e64 v7, s2, 1.0 +; GFX11-NEXT: v_add_f32_e64 v9, s0, 1.0 ; GFX11-NEXT: v_lshrrev_b64 v[65:66], 24, v[23:24] ; GFX11-NEXT: v_lshrrev_b64 v[66:67], 24, v[28:29] ; GFX11-NEXT: v_lshrrev_b64 v[67:68], 24, v[30:31] @@ -49126,41 +48456,41 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a, ; GFX11-NEXT: ; kill: killed $sgpr43 ; GFX11-NEXT: s_branch .LBB37_2 ; GFX11-NEXT: .LBB37_4: -; GFX11-NEXT: v_dual_mov_b32 v52, s0 :: v_dual_mov_b32 v53, s1 +; GFX11-NEXT: v_dual_mov_b32 v9, s0 :: v_dual_mov_b32 v10, s1 ; GFX11-NEXT: v_readlane_b32 s0, v77, 0 -; GFX11-NEXT: v_dual_mov_b32 v147, s36 :: v_dual_mov_b32 v48, s2 -; GFX11-NEXT: v_dual_mov_b32 v49, s3 :: v_dual_mov_b32 v36, s16 +; GFX11-NEXT: v_dual_mov_b32 v147, s36 :: v_dual_mov_b32 v52, s40 +; GFX11-NEXT: v_dual_mov_b32 v53, s41 :: v_dual_mov_b32 v48, s28 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_dual_mov_b32 v37, s17 :: v_dual_mov_b32 v148, s0 +; GFX11-NEXT: v_dual_mov_b32 v49, s29 :: v_dual_mov_b32 v148, s0 ; GFX11-NEXT: v_readlane_b32 s0, v77, 1 -; GFX11-NEXT: v_dual_mov_b32 v34, s18 :: v_dual_mov_b32 v35, s19 -; GFX11-NEXT: v_dual_mov_b32 v30, s20 :: v_dual_mov_b32 v31, s21 +; GFX11-NEXT: v_dual_mov_b32 v36, s26 :: v_dual_mov_b32 v37, s27 +; GFX11-NEXT: v_dual_mov_b32 v34, s24 :: v_dual_mov_b32 v35, s25 ; GFX11-NEXT: v_mov_b32_e32 v146, s0 ; GFX11-NEXT: v_readlane_b32 s0, v77, 2 -; GFX11-NEXT: v_dual_mov_b32 v28, s22 :: v_dual_mov_b32 v29, s23 -; GFX11-NEXT: v_dual_mov_b32 v23, s24 :: v_dual_mov_b32 v24, s25 +; GFX11-NEXT: v_dual_mov_b32 v30, s22 :: v_dual_mov_b32 v31, s23 +; GFX11-NEXT: v_dual_mov_b32 v28, s20 :: v_dual_mov_b32 v29, s21 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_mov_b32_e32 v145, s0 ; GFX11-NEXT: v_readlane_b32 s0, v77, 3 -; GFX11-NEXT: v_dual_mov_b32 v21, s26 :: v_dual_mov_b32 v22, s27 -; GFX11-NEXT: v_dual_mov_b32 v17, s28 :: v_dual_mov_b32 v18, s29 +; GFX11-NEXT: v_dual_mov_b32 v23, s18 :: v_dual_mov_b32 v24, s19 +; GFX11-NEXT: v_dual_mov_b32 v21, s16 :: v_dual_mov_b32 v22, s17 ; GFX11-NEXT: v_mov_b32_e32 v144, s0 ; GFX11-NEXT: v_readlane_b32 s0, v77, 4 -; GFX11-NEXT: v_dual_mov_b32 v13, s40 :: v_dual_mov_b32 v14, s41 -; GFX11-NEXT: v_dual_mov_b32 v11, s14 :: v_dual_mov_b32 v12, s15 +; GFX11-NEXT: v_dual_mov_b32 v17, s14 :: v_dual_mov_b32 v18, s15 +; GFX11-NEXT: v_dual_mov_b32 v13, s12 :: v_dual_mov_b32 v14, s13 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_mov_b32_e32 v134, s0 ; GFX11-NEXT: v_readlane_b32 s0, v77, 5 -; GFX11-NEXT: v_dual_mov_b32 v9, s4 :: v_dual_mov_b32 v10, s5 -; GFX11-NEXT: v_dual_mov_b32 v7, s6 :: v_dual_mov_b32 v8, s7 +; GFX11-NEXT: v_dual_mov_b32 v11, s10 :: v_dual_mov_b32 v12, s11 +; GFX11-NEXT: v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v8, s3 ; GFX11-NEXT: v_mov_b32_e32 v135, s0 ; GFX11-NEXT: v_readlane_b32 s0, v77, 6 -; GFX11-NEXT: v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, s9 -; GFX11-NEXT: v_dual_mov_b32 v3, s10 :: v_dual_mov_b32 v4, s11 +; GFX11-NEXT: v_dual_mov_b32 v5, s4 :: v_dual_mov_b32 v6, s5 +; GFX11-NEXT: v_dual_mov_b32 v3, s6 :: v_dual_mov_b32 v4, s7 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_mov_b32_e32 v133, s0 ; GFX11-NEXT: v_readlane_b32 s0, v77, 7 -; GFX11-NEXT: v_dual_mov_b32 v1, s12 :: v_dual_mov_b32 v2, s13 +; GFX11-NEXT: v_dual_mov_b32 v1, s8 :: v_dual_mov_b32 v2, s9 ; GFX11-NEXT: v_dual_mov_b32 v74, s35 :: v_dual_mov_b32 v73, s104 ; GFX11-NEXT: v_mov_b32_e32 v132, s0 ; GFX11-NEXT: v_readlane_b32 s0, v77, 8 @@ -61512,31 +60842,59 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg ; SI-NEXT: v_writelane_b32 v63, s67, 19 ; SI-NEXT: v_writelane_b32 v63, s68, 20 ; SI-NEXT: v_writelane_b32 v63, s69, 21 +; SI-NEXT: v_mov_b32_e32 v20, s16 ; SI-NEXT: v_writelane_b32 v63, s70, 22 +; SI-NEXT: v_readfirstlane_b32 s6, v20 +; SI-NEXT: v_mov_b32_e32 v20, s17 ; SI-NEXT: v_writelane_b32 v63, s71, 23 +; SI-NEXT: v_readfirstlane_b32 s7, v20 +; SI-NEXT: v_mov_b32_e32 v20, s18 ; SI-NEXT: v_writelane_b32 v63, s80, 24 +; SI-NEXT: v_readfirstlane_b32 s10, v20 +; SI-NEXT: v_mov_b32_e32 v20, s19 ; SI-NEXT: v_writelane_b32 v63, s81, 25 +; SI-NEXT: v_readfirstlane_b32 s12, v20 +; SI-NEXT: v_mov_b32_e32 v20, s20 ; SI-NEXT: v_writelane_b32 v63, s82, 26 +; SI-NEXT: v_readfirstlane_b32 s14, v20 +; SI-NEXT: v_mov_b32_e32 v20, s21 ; SI-NEXT: v_writelane_b32 v63, s83, 27 +; SI-NEXT: v_readfirstlane_b32 s8, v20 +; SI-NEXT: v_mov_b32_e32 v20, s22 ; SI-NEXT: v_writelane_b32 v63, s84, 28 +; SI-NEXT: v_readfirstlane_b32 s9, v20 +; SI-NEXT: v_mov_b32_e32 v20, s23 ; SI-NEXT: v_writelane_b32 v63, s85, 29 +; SI-NEXT: v_readfirstlane_b32 s11, v20 +; SI-NEXT: v_mov_b32_e32 v20, s24 ; SI-NEXT: v_writelane_b32 v63, s86, 30 +; SI-NEXT: v_readfirstlane_b32 s13, v20 +; SI-NEXT: v_mov_b32_e32 v20, s25 ; SI-NEXT: v_writelane_b32 v63, s87, 31 +; SI-NEXT: v_readfirstlane_b32 s15, v20 +; SI-NEXT: v_mov_b32_e32 v20, s26 ; SI-NEXT: v_writelane_b32 v63, s96, 32 +; SI-NEXT: v_readfirstlane_b32 s16, v20 +; SI-NEXT: v_mov_b32_e32 v20, s27 ; SI-NEXT: v_writelane_b32 v63, s97, 33 +; SI-NEXT: v_readfirstlane_b32 s17, v20 +; SI-NEXT: v_mov_b32_e32 v20, s28 ; SI-NEXT: v_writelane_b32 v63, s98, 34 +; SI-NEXT: v_readfirstlane_b32 s18, v20 +; SI-NEXT: v_mov_b32_e32 v20, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; SI-NEXT: v_writelane_b32 v63, s99, 35 -; SI-NEXT: v_readfirstlane_b32 s6, v1 -; SI-NEXT: v_readfirstlane_b32 s7, v2 -; SI-NEXT: v_readfirstlane_b32 s8, v3 -; SI-NEXT: v_readfirstlane_b32 s9, v4 -; SI-NEXT: v_readfirstlane_b32 s10, v5 -; SI-NEXT: v_readfirstlane_b32 s11, v6 -; SI-NEXT: v_readfirstlane_b32 s12, v7 -; SI-NEXT: v_readfirstlane_b32 s13, v8 -; SI-NEXT: v_readfirstlane_b32 s14, v9 -; SI-NEXT: v_readfirstlane_b32 s15, v10 +; SI-NEXT: v_readfirstlane_b32 s19, v20 +; SI-NEXT: v_readfirstlane_b32 s20, v1 +; SI-NEXT: v_readfirstlane_b32 s21, v2 +; SI-NEXT: v_readfirstlane_b32 s22, v3 +; SI-NEXT: v_readfirstlane_b32 s23, v4 +; SI-NEXT: v_readfirstlane_b32 s24, v5 +; SI-NEXT: v_readfirstlane_b32 s25, v6 +; SI-NEXT: v_readfirstlane_b32 s26, v7 +; SI-NEXT: v_readfirstlane_b32 s27, v8 +; SI-NEXT: v_readfirstlane_b32 s28, v9 +; SI-NEXT: v_readfirstlane_b32 s29, v10 ; SI-NEXT: v_readfirstlane_b32 s40, v11 ; SI-NEXT: v_readfirstlane_b32 s41, v12 ; SI-NEXT: v_readfirstlane_b32 s42, v13 @@ -61583,86 +60941,86 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg ; SI-NEXT: s_lshl_b32 s77, s41, 16 ; SI-NEXT: s_and_b32 s78, s40, 0xffff0000 ; SI-NEXT: s_lshl_b32 s79, s40, 16 -; SI-NEXT: s_and_b32 s88, s15, 0xffff0000 -; SI-NEXT: s_lshl_b32 s89, s15, 16 -; SI-NEXT: s_and_b32 s90, s14, 0xffff0000 -; SI-NEXT: s_lshl_b32 s91, s14, 16 -; SI-NEXT: s_and_b32 s92, s13, 0xffff0000 -; SI-NEXT: s_lshl_b32 s93, s13, 16 -; SI-NEXT: s_and_b32 s94, s12, 0xffff0000 -; SI-NEXT: s_lshl_b32 s95, s12, 16 -; SI-NEXT: s_and_b32 s30, s11, 0xffff0000 -; SI-NEXT: s_lshl_b32 s31, s11, 16 -; SI-NEXT: s_and_b32 s34, s10, 0xffff0000 -; SI-NEXT: s_lshl_b32 s35, s10, 16 -; SI-NEXT: s_and_b32 s36, s9, 0xffff0000 -; SI-NEXT: s_lshl_b32 s37, s9, 16 -; SI-NEXT: s_and_b32 s38, s8, 0xffff0000 -; SI-NEXT: s_lshl_b32 s39, s8, 16 -; SI-NEXT: s_and_b32 s48, s7, 0xffff0000 -; SI-NEXT: s_lshl_b32 s49, s7, 16 -; SI-NEXT: s_and_b32 s50, s6, 0xffff0000 -; SI-NEXT: s_lshl_b32 s51, s6, 16 -; SI-NEXT: s_and_b32 s52, s29, 0xffff0000 -; SI-NEXT: s_lshl_b32 s53, s29, 16 -; SI-NEXT: s_and_b32 s54, s28, 0xffff0000 -; SI-NEXT: s_lshl_b32 s55, s28, 16 -; SI-NEXT: s_and_b32 s64, s27, 0xffff0000 -; SI-NEXT: s_lshl_b32 s65, s27, 16 -; SI-NEXT: s_and_b32 s66, s26, 0xffff0000 -; SI-NEXT: s_lshl_b32 s67, s26, 16 -; SI-NEXT: s_and_b32 s68, s25, 0xffff0000 -; SI-NEXT: s_lshl_b32 s69, s25, 16 -; SI-NEXT: s_and_b32 s70, s24, 0xffff0000 -; SI-NEXT: s_lshl_b32 s71, s24, 16 -; SI-NEXT: s_and_b32 s80, s23, 0xffff0000 -; SI-NEXT: s_lshl_b32 s81, s23, 16 -; SI-NEXT: s_and_b32 s82, s22, 0xffff0000 -; SI-NEXT: s_lshl_b32 s83, s22, 16 -; SI-NEXT: s_and_b32 s84, s21, 0xffff0000 -; SI-NEXT: s_lshl_b32 s85, s21, 16 -; SI-NEXT: s_and_b32 s86, s20, 0xffff0000 -; SI-NEXT: s_lshl_b32 s87, s20, 16 -; SI-NEXT: s_and_b32 s96, s19, 0xffff0000 -; SI-NEXT: s_lshl_b32 s97, s19, 16 -; SI-NEXT: s_and_b32 s98, s18, 0xffff0000 -; SI-NEXT: s_lshl_b32 s99, s18, 16 -; SI-NEXT: s_and_b32 s56, s17, 0xffff0000 -; SI-NEXT: s_lshl_b32 s57, s17, 16 -; SI-NEXT: s_and_b32 s58, s16, 0xffff0000 -; SI-NEXT: s_lshl_b32 s59, s16, 16 +; SI-NEXT: s_and_b32 s88, s29, 0xffff0000 +; SI-NEXT: s_lshl_b32 s89, s29, 16 +; SI-NEXT: s_and_b32 s90, s28, 0xffff0000 +; SI-NEXT: s_lshl_b32 s91, s28, 16 +; SI-NEXT: s_and_b32 s92, s27, 0xffff0000 +; SI-NEXT: s_lshl_b32 s93, s27, 16 +; SI-NEXT: s_and_b32 s94, s26, 0xffff0000 +; SI-NEXT: s_lshl_b32 s95, s26, 16 +; SI-NEXT: s_and_b32 s30, s25, 0xffff0000 +; SI-NEXT: s_lshl_b32 s31, s25, 16 +; SI-NEXT: s_and_b32 s34, s24, 0xffff0000 +; SI-NEXT: s_lshl_b32 s35, s24, 16 +; SI-NEXT: s_and_b32 s36, s23, 0xffff0000 +; SI-NEXT: s_lshl_b32 s37, s23, 16 +; SI-NEXT: s_and_b32 s38, s22, 0xffff0000 +; SI-NEXT: s_lshl_b32 s39, s22, 16 +; SI-NEXT: s_and_b32 s48, s21, 0xffff0000 +; SI-NEXT: s_lshl_b32 s49, s21, 16 +; SI-NEXT: s_and_b32 s50, s20, 0xffff0000 +; SI-NEXT: s_lshl_b32 s51, s20, 16 +; SI-NEXT: s_and_b32 s52, s19, 0xffff0000 +; SI-NEXT: s_lshl_b32 s53, s19, 16 +; SI-NEXT: s_and_b32 s54, s18, 0xffff0000 +; SI-NEXT: s_lshl_b32 s55, s18, 16 +; SI-NEXT: s_and_b32 s64, s17, 0xffff0000 +; SI-NEXT: s_lshl_b32 s65, s17, 16 +; SI-NEXT: s_and_b32 s66, s16, 0xffff0000 +; SI-NEXT: s_lshl_b32 s67, s16, 16 +; SI-NEXT: s_and_b32 s68, s15, 0xffff0000 +; SI-NEXT: s_lshl_b32 s69, s15, 16 +; SI-NEXT: s_and_b32 s70, s13, 0xffff0000 +; SI-NEXT: s_lshl_b32 s71, s13, 16 +; SI-NEXT: s_and_b32 s80, s11, 0xffff0000 +; SI-NEXT: s_lshl_b32 s81, s11, 16 +; SI-NEXT: s_and_b32 s82, s9, 0xffff0000 +; SI-NEXT: s_lshl_b32 s83, s9, 16 +; SI-NEXT: s_and_b32 s84, s8, 0xffff0000 +; SI-NEXT: s_lshl_b32 s85, s8, 16 +; SI-NEXT: s_and_b32 s86, s14, 0xffff0000 +; SI-NEXT: s_lshl_b32 s87, s14, 16 +; SI-NEXT: s_and_b32 s96, s12, 0xffff0000 +; SI-NEXT: s_lshl_b32 s97, s12, 16 +; SI-NEXT: s_and_b32 s98, s10, 0xffff0000 +; SI-NEXT: s_lshl_b32 s99, s10, 16 +; SI-NEXT: s_and_b32 s56, s7, 0xffff0000 +; SI-NEXT: s_lshl_b32 s57, s7, 16 +; SI-NEXT: s_and_b32 s58, s6, 0xffff0000 +; SI-NEXT: s_lshl_b32 s59, s6, 16 ; SI-NEXT: s_cbranch_execnz .LBB41_4 ; SI-NEXT: .LBB41_2: ; %cmp.true -; SI-NEXT: v_add_f32_e64 v2, s19, 1.0 +; SI-NEXT: v_add_f32_e64 v2, s12, 1.0 ; SI-NEXT: v_add_f32_e64 v4, s47, 1.0 -; SI-NEXT: v_add_f32_e64 v1, s18, 1.0 +; SI-NEXT: v_add_f32_e64 v1, s10, 1.0 ; SI-NEXT: v_add_f32_e64 v6, s46, 1.0 ; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v4 ; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; SI-NEXT: s_waitcnt expcnt(3) ; SI-NEXT: v_and_b32_e32 v58, 0xffff0000, v2 ; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v2 -; SI-NEXT: v_add_f32_e64 v2, s17, 1.0 -; SI-NEXT: v_add_f32_e64 v3, s20, 1.0 -; SI-NEXT: v_add_f32_e64 v45, s21, 1.0 -; SI-NEXT: v_add_f32_e64 v43, s22, 1.0 -; SI-NEXT: v_add_f32_e64 v41, s23, 1.0 -; SI-NEXT: v_add_f32_e64 v55, s24, 1.0 -; SI-NEXT: v_add_f32_e64 v53, s25, 1.0 -; SI-NEXT: v_add_f32_e64 v51, s26, 1.0 -; SI-NEXT: v_add_f32_e64 v49, s27, 1.0 -; SI-NEXT: v_add_f32_e64 v39, s28, 1.0 -; SI-NEXT: v_add_f32_e64 v37, s29, 1.0 -; SI-NEXT: v_add_f32_e64 v35, s6, 1.0 -; SI-NEXT: v_add_f32_e64 v33, s7, 1.0 -; SI-NEXT: v_add_f32_e64 v31, s8, 1.0 -; SI-NEXT: v_add_f32_e64 v29, s9, 1.0 -; SI-NEXT: v_add_f32_e64 v27, s10, 1.0 -; SI-NEXT: v_add_f32_e64 v25, s11, 1.0 -; SI-NEXT: v_add_f32_e64 v23, s12, 1.0 -; SI-NEXT: v_add_f32_e64 v21, s13, 1.0 -; SI-NEXT: v_add_f32_e64 v19, s14, 1.0 -; SI-NEXT: v_add_f32_e64 v17, s15, 1.0 +; SI-NEXT: v_add_f32_e64 v2, s7, 1.0 +; SI-NEXT: v_add_f32_e64 v3, s14, 1.0 +; SI-NEXT: v_add_f32_e64 v45, s8, 1.0 +; SI-NEXT: v_add_f32_e64 v43, s9, 1.0 +; SI-NEXT: v_add_f32_e64 v41, s11, 1.0 +; SI-NEXT: v_add_f32_e64 v55, s13, 1.0 +; SI-NEXT: v_add_f32_e64 v53, s15, 1.0 +; SI-NEXT: v_add_f32_e64 v51, s16, 1.0 +; SI-NEXT: v_add_f32_e64 v49, s17, 1.0 +; SI-NEXT: v_add_f32_e64 v39, s18, 1.0 +; SI-NEXT: v_add_f32_e64 v37, s19, 1.0 +; SI-NEXT: v_add_f32_e64 v35, s20, 1.0 +; SI-NEXT: v_add_f32_e64 v33, s21, 1.0 +; SI-NEXT: v_add_f32_e64 v31, s22, 1.0 +; SI-NEXT: v_add_f32_e64 v29, s23, 1.0 +; SI-NEXT: v_add_f32_e64 v27, s24, 1.0 +; SI-NEXT: v_add_f32_e64 v25, s25, 1.0 +; SI-NEXT: v_add_f32_e64 v23, s26, 1.0 +; SI-NEXT: v_add_f32_e64 v21, s27, 1.0 +; SI-NEXT: v_add_f32_e64 v19, s28, 1.0 +; SI-NEXT: v_add_f32_e64 v17, s29, 1.0 ; SI-NEXT: v_add_f32_e64 v15, s40, 1.0 ; SI-NEXT: v_add_f32_e64 v13, s41, 1.0 ; SI-NEXT: v_add_f32_e64 v11, s42, 1.0 @@ -61678,7 +61036,7 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg ; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v1 ; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 ; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v2 -; SI-NEXT: v_add_f32_e64 v2, s16, 1.0 +; SI-NEXT: v_add_f32_e64 v2, s6, 1.0 ; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -61886,214 +61244,213 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg ; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 ; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16 +; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16 ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 ; SI-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v61 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v61 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v60 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v59 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v59 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v58 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v57 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v57 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v56 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v47 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v47 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v46 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v45 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v45 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v44 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v43 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v43 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v42 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v41 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v41 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v40 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v55 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v55 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v54 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v53 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v53 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v52 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v51 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v51 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v50 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v49 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v49 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v48 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v39 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v39 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v38 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v37 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v37 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v35 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v35 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v34 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v33 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v33 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v32 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v31 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v31 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 64, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v30 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v29 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v29 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v28 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v27 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v27 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x48, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v26 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v25 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v25 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v24 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v23 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v23 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x50, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v22 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v21 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v21 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v20 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v19 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v19 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x58, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v18 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v17 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v17 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v16 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v15 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v15 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x60, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v14 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v13 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v13 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x64, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v12 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v11 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x68, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v10 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v9 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v7 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v7 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x70, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v6 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v5 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload ; SI-NEXT: v_readlane_b32 s99, v63, 35 ; SI-NEXT: v_readlane_b32 s98, v63, 34 ; SI-NEXT: v_readlane_b32 s97, v63, 33 @@ -62130,22 +61487,23 @@ define inreg <64 x bfloat> @bitcast_v32f32_to_v64bf16_scalar(<32 x float> inreg ; SI-NEXT: v_readlane_b32 s34, v63, 2 ; SI-NEXT: v_readlane_b32 s31, v63, 1 ; SI-NEXT: v_readlane_b32 s30, v63, 0 -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v4 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload @@ -65386,562 +64744,737 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v52, v30 -; SI-NEXT: v_mov_b32_e32 v53, v28 -; SI-NEXT: v_mov_b32_e32 v40, v12 -; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:76 -; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 -; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:8 -; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:4 -; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:16 -; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:12 -; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:24 -; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:20 -; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:32 -; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:28 -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:40 -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:36 -; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:44 +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76 +; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 +; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:16 +; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:24 +; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:32 +; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:40 +; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48 +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:56 +; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:64 +; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:72 +; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:4 +; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:12 +; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:20 +; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28 +; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:36 +; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:44 +; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:52 +; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:60 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:68 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:56 -; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:52 -; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:64 -; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:60 -; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72 -; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:68 -; SI-NEXT: v_mov_b32_e32 v55, v14 -; SI-NEXT: v_mul_f32_e32 v14, 1.0, v0 -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v6 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v63, 1.0, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v8 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v7 +; SI-NEXT: v_mov_b32_e32 v43, v21 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v10 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11 +; SI-NEXT: v_mov_b32_e32 v54, v29 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v43 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v16 -; SI-NEXT: v_mul_f32_e32 v58, 1.0, v1 -; SI-NEXT: v_mul_f32_e32 v56, 1.0, v3 -; SI-NEXT: v_mul_f32_e32 v54, 1.0, v2 -; SI-NEXT: v_mul_f32_e32 v44, 1.0, v5 -; SI-NEXT: v_mul_f32_e32 v46, 1.0, v4 -; SI-NEXT: v_mul_f32_e32 v61, 1.0, v7 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v54 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v41, v23 +; SI-NEXT: v_mov_b32_e32 v29, v20 +; SI-NEXT: v_mul_f32_e32 v57, 1.0, v3 ; SI-NEXT: v_mul_f32_e32 v59, 1.0, v9 -; SI-NEXT: v_mul_f32_e32 v57, 1.0, v11 -; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13 -; SI-NEXT: v_mul_f32_e32 v47, 1.0, v40 -; SI-NEXT: v_mul_f32_e32 v45, 1.0, v15 -; SI-NEXT: v_mul_f32_e32 v15, 1.0, v17 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; SI-NEXT: v_mul_f32_e32 v16, 1.0, v19 -; SI-NEXT: v_mul_f32_e32 v43, 1.0, v18 -; SI-NEXT: v_mul_f32_e32 v17, 1.0, v21 -; SI-NEXT: v_mul_f32_e32 v41, 1.0, v20 -; SI-NEXT: v_mul_f32_e32 v18, 1.0, v23 -; SI-NEXT: v_mul_f32_e32 v40, 1.0, v22 -; SI-NEXT: v_mul_f32_e32 v19, 1.0, v25 -; SI-NEXT: v_mul_f32_e32 v55, 1.0, v24 -; SI-NEXT: v_mul_f32_e32 v20, 1.0, v27 -; SI-NEXT: v_mul_f32_e32 v21, 1.0, v29 -; SI-NEXT: v_mul_f32_e32 v53, 1.0, v53 -; SI-NEXT: v_mul_f32_e32 v52, 1.0, v52 +; SI-NEXT: v_mul_f32_e32 v61, 1.0, v13 +; SI-NEXT: v_mul_f32_e32 v23, 1.0, v15 +; SI-NEXT: v_mul_f32_e32 v44, 1.0, v17 +; SI-NEXT: v_mul_f32_e32 v21, 1.0, v19 +; SI-NEXT: v_mul_f32_e32 v20, 1.0, v41 +; SI-NEXT: v_mul_f32_e32 v17, 1.0, v25 +; SI-NEXT: v_mul_f32_e32 v15, 1.0, v27 +; SI-NEXT: v_mul_f32_e64 v25, 1.0, s17 +; SI-NEXT: v_mul_f32_e64 v3, 1.0, s21 +; SI-NEXT: v_mul_f32_e64 v5, 1.0, s25 +; SI-NEXT: v_mul_f32_e64 v7, 1.0, s29 +; SI-NEXT: v_mul_f32_e32 v9, 1.0, v2 +; SI-NEXT: v_mul_f32_e32 v54, 1.0, v4 +; SI-NEXT: v_mul_f32_e32 v11, 1.0, v6 +; SI-NEXT: v_mul_f32_e32 v56, 1.0, v8 +; SI-NEXT: v_mul_f32_e32 v13, 1.0, v10 +; SI-NEXT: v_mul_f32_e32 v58, 1.0, v12 +; SI-NEXT: v_mul_f32_e32 v60, 1.0, v14 +; SI-NEXT: v_mul_f32_e32 v62, 1.0, v16 +; SI-NEXT: v_mul_f32_e32 v47, 1.0, v22 +; SI-NEXT: v_mul_f32_e32 v22, 1.0, v28 +; SI-NEXT: v_mul_f32_e64 v19, 1.0, s16 +; SI-NEXT: v_mul_f32_e64 v14, 1.0, s20 +; SI-NEXT: v_mul_f32_e64 v16, 1.0, s22 +; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v32 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v33 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v34 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v35 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v37 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v38 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v39 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v48 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v49 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v0, 1.0, s17 -; SI-NEXT: v_mul_f32_e64 v3, 1.0, s16 ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s19 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s18 -; SI-NEXT: v_mul_f32_e64 v4, 1.0, s21 -; SI-NEXT: v_mul_f32_e64 v8, 1.0, s20 -; SI-NEXT: v_mul_f32_e64 v10, 1.0, s23 -; SI-NEXT: v_mul_f32_e64 v9, 1.0, s22 -; SI-NEXT: v_mul_f32_e64 v5, 1.0, s27 -; SI-NEXT: v_mul_f32_e64 v11, 1.0, s26 -; SI-NEXT: v_mul_f32_e64 v6, 1.0, s29 -; SI-NEXT: v_mul_f32_e64 v7, 1.0, s28 +; SI-NEXT: v_mul_f32_e32 v39, 1.0, v0 ; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v48 -; SI-NEXT: v_mul_f32_e32 v48, 1.0, v26 -; SI-NEXT: v_mul_f32_e32 v22, 1.0, v51 +; SI-NEXT: v_mul_f32_e32 v0, 1.0, v45 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill ; SI-NEXT: s_and_b64 s[4:5], vcc, exec -; SI-NEXT: v_mul_f32_e32 v23, 1.0, v37 -; SI-NEXT: v_mul_f32_e32 v51, 1.0, v50 -; SI-NEXT: v_mul_f32_e32 v24, 1.0, v38 -; SI-NEXT: v_mul_f32_e32 v50, 1.0, v49 -; SI-NEXT: v_mul_f32_e32 v25, 1.0, v39 -; SI-NEXT: v_mul_f32_e32 v49, 1.0, v30 -; SI-NEXT: v_mul_f32_e32 v26, 1.0, v28 -; SI-NEXT: v_mul_f32_e32 v39, 1.0, v12 -; SI-NEXT: v_mul_f32_e32 v27, 1.0, v31 -; SI-NEXT: s_waitcnt vmcnt(13) -; SI-NEXT: v_mul_f32_e32 v38, 1.0, v60 -; SI-NEXT: s_waitcnt vmcnt(12) +; SI-NEXT: v_mul_f32_e64 v35, 1.0, s23 +; SI-NEXT: v_mul_f32_e64 v33, 1.0, s27 +; SI-NEXT: v_mul_f32_e32 v32, 1.0, v18 +; SI-NEXT: v_mul_f32_e32 v34, 1.0, v29 +; SI-NEXT: v_mul_f32_e32 v36, 1.0, v24 +; SI-NEXT: v_mul_f32_e32 v38, 1.0, v26 +; SI-NEXT: v_mul_f32_e32 v31, 1.0, v30 +; SI-NEXT: v_mul_f32_e32 v24, 1.0, v51 +; SI-NEXT: v_mul_f32_e32 v41, 1.0, v53 +; SI-NEXT: v_mul_f32_e32 v26, 1.0, v55 +; SI-NEXT: v_mul_f32_e32 v43, 1.0, v40 ; SI-NEXT: v_mul_f32_e32 v28, 1.0, v42 -; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_mul_f32_e32 v37, 1.0, v62 -; SI-NEXT: s_waitcnt vmcnt(10) -; SI-NEXT: v_mul_f32_e32 v29, 1.0, v63 -; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_mul_f32_e32 v32, 1.0, v32 -; SI-NEXT: s_waitcnt vmcnt(8) -; SI-NEXT: v_mul_f32_e32 v30, 1.0, v33 -; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_mul_f32_e32 v31, 1.0, v34 -; SI-NEXT: s_waitcnt vmcnt(6) -; SI-NEXT: v_mul_f32_e32 v33, 1.0, v35 -; SI-NEXT: s_waitcnt vmcnt(5) -; SI-NEXT: v_mul_f32_e32 v42, 1.0, v36 -; SI-NEXT: v_mul_f32_e64 v12, 1.0, s25 -; SI-NEXT: v_mul_f32_e64 v34, 1.0, s24 -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v51, 1.0, v50 +; SI-NEXT: v_mul_f32_e32 v53, 1.0, v52 +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_mul_f32_e32 v0, 1.0, v46 +; SI-NEXT: v_mul_f32_e64 v48, 1.0, s18 +; SI-NEXT: v_mul_f32_e64 v18, 1.0, s24 +; SI-NEXT: v_mul_f32_e64 v29, 1.0, s26 +; SI-NEXT: v_mul_f32_e64 v45, 1.0, s28 +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB43_2 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; SI-NEXT: s_waitcnt expcnt(6) -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_alignbit_b32 v0, v0, v3, 16 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4 -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v10 -; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; SI-NEXT: v_alignbit_b32 v2, v2, v8, 16 -; SI-NEXT: v_alignbit_b32 v3, v3, v9, 16 -; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16 -; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v58 -; SI-NEXT: s_waitcnt expcnt(5) -; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v56 -; SI-NEXT: s_waitcnt expcnt(4) -; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v44 -; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; SI-NEXT: v_alignbit_b32 v5, v5, v11, 16 -; SI-NEXT: v_alignbit_b32 v7, v7, v14, 16 -; SI-NEXT: v_alignbit_b32 v8, v8, v54, 16 -; SI-NEXT: v_alignbit_b32 v9, v9, v46, 16 -; SI-NEXT: v_mov_b32_e32 v62, v61 -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v61 -; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; SI-NEXT: v_mov_b32_e32 v60, v59 -; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v59 -; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; SI-NEXT: v_mov_b32_e32 v56, v47 -; SI-NEXT: v_alignbit_b32 v13, v13, v47, 16 -; SI-NEXT: v_mov_b32_e32 v46, v45 -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v45 -; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v12 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v57 -; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22 -; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23 -; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 -; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26 -; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28 -; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29 -; SI-NEXT: v_alignbit_b32 v30, v30, v31, 16 -; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v33 -; SI-NEXT: v_alignbit_b32 v4, v4, v34, 16 -; SI-NEXT: v_mov_b32_e32 v63, v44 -; SI-NEXT: v_mov_b32_e32 v58, v57 -; SI-NEXT: v_mov_b32_e32 v44, v43 -; SI-NEXT: v_alignbit_b32 v16, v16, v43, 16 -; SI-NEXT: v_mov_b32_e32 v43, v41 -; SI-NEXT: v_alignbit_b32 v17, v17, v41, 16 -; SI-NEXT: v_alignbit_b32 v18, v18, v40, 16 -; SI-NEXT: v_mov_b32_e32 v40, v55 -; SI-NEXT: v_alignbit_b32 v19, v19, v55, 16 -; SI-NEXT: v_alignbit_b32 v20, v20, v48, 16 -; SI-NEXT: v_mov_b32_e32 v48, v53 -; SI-NEXT: v_alignbit_b32 v21, v21, v53, 16 -; SI-NEXT: v_alignbit_b32 v22, v22, v52, 16 -; SI-NEXT: v_mov_b32_e32 v52, v51 -; SI-NEXT: v_alignbit_b32 v23, v23, v51, 16 -; SI-NEXT: v_alignbit_b32 v24, v24, v50, 16 -; SI-NEXT: v_mov_b32_e32 v50, v49 -; SI-NEXT: v_alignbit_b32 v25, v25, v49, 16 -; SI-NEXT: v_mov_b32_e32 v36, v39 -; SI-NEXT: v_alignbit_b32 v26, v26, v39, 16 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v34, v38 -; SI-NEXT: v_alignbit_b32 v27, v27, v38, 16 -; SI-NEXT: v_mov_b32_e32 v35, v37 -; SI-NEXT: v_alignbit_b32 v28, v28, v37, 16 -; SI-NEXT: v_mov_b32_e32 v37, v32 -; SI-NEXT: v_alignbit_b32 v29, v29, v32, 16 -; SI-NEXT: v_alignbit_b32 v31, v31, v42, 16 +; SI-NEXT: v_mov_b32_e32 v0, v19 +; SI-NEXT: v_mov_b32_e32 v37, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v25 +; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v33 +; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v7 +; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v63 +; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v57 +; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v61 +; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v23 +; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v44 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v21 +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 s[4:5], 0 -; SI-NEXT: v_mov_b32_e32 v32, v33 -; SI-NEXT: v_mov_b32_e32 v33, v42 -; SI-NEXT: s_waitcnt vmcnt(4) -; SI-NEXT: v_alignbit_b32 v10, v10, v61, 16 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_alignbit_b32 v12, v12, v54, 16 -; SI-NEXT: v_mov_b32_e32 v41, v61 +; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v1 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[0:1], v[19:20], 16 +; SI-NEXT: v_mov_b32_e32 v1, v48 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[1:2], v[48:49], 16 +; SI-NEXT: v_mov_b32_e32 v2, v14 +; SI-NEXT: v_mov_b32_e32 v49, v15 +; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v3 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[2:3], v[14:15], 16 +; SI-NEXT: v_mov_b32_e32 v3, v16 +; SI-NEXT: v_mov_b32_e32 v20, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v35 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[3:4], v[16:17], 16 +; SI-NEXT: v_mov_b32_e32 v4, v18 +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v5 +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[4:5], v[18:19], 16 +; SI-NEXT: v_mov_b32_e32 v5, v29 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[5:6], v[29:30], 16 +; SI-NEXT: v_mov_b32_e32 v6, v45 +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[6:7], v[45:46], 16 +; SI-NEXT: v_mov_b32_e32 v7, v39 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[7:8], v[39:40], 16 +; SI-NEXT: v_mov_b32_e32 v8, v9 +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v37 +; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v20 +; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v49 +; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[8:9], v[9:10], 16 +; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v9 +; SI-NEXT: v_mov_b32_e32 v9, v54 +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[9:10], v[54:55], 16 +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v55, v13 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v10 +; SI-NEXT: v_mov_b32_e32 v10, v11 +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[10:11], v[11:12], 16 +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v11 +; SI-NEXT: v_mov_b32_e32 v11, v56 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[11:12], v[56:57], 16 +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v56, v44 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v12 +; SI-NEXT: v_lshr_b64 v[12:13], v[13:14], 16 +; SI-NEXT: v_mov_b32_e32 v13, v58 +; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[13:14], v[58:59], 16 +; SI-NEXT: v_mov_b32_e32 v14, v60 +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[14:15], v[60:61], 16 +; SI-NEXT: v_mov_b32_e32 v15, v62 +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[15:16], v[62:63], 16 +; SI-NEXT: v_mov_b32_e32 v16, v32 +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[16:17], v[32:33], 16 +; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v27 +; SI-NEXT: v_mov_b32_e32 v33, v34 +; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_alignbit_b32 v11, v11, v59, 16 -; SI-NEXT: v_mov_b32_e32 v55, v59 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_alignbit_b32 v14, v14, v45, 16 +; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v17 +; SI-NEXT: v_mov_b32_e32 v40, v17 +; SI-NEXT: v_lshr_b64 v[17:18], v[34:35], 16 +; SI-NEXT: v_lshr_b64 v[18:19], v[47:48], 16 +; SI-NEXT: v_lshr_b64 v[19:20], v[36:37], 16 +; SI-NEXT: v_mov_b32_e32 v20, v38 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[20:21], v[38:39], 16 +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; SI-NEXT: v_mov_b32_e32 v34, v47 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v21 +; SI-NEXT: v_mov_b32_e32 v21, v22 +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[21:22], v[22:23], 16 +; SI-NEXT: v_mov_b32_e32 v22, v31 +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[22:23], v[31:32], 16 +; SI-NEXT: v_mov_b32_e32 v23, v24 +; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[23:24], v[24:25], 16 +; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v52 +; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v30 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v24 +; SI-NEXT: v_mov_b32_e32 v24, v41 +; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[24:25], v[41:42], 16 +; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v41, v26 +; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v50 +; SI-NEXT: v_mov_b32_e32 v42, v51 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v25 +; SI-NEXT: v_lshr_b64 v[25:26], v[26:27], 16 +; SI-NEXT: v_mov_b32_e32 v26, v43 +; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[26:27], v[43:44], 16 +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v43, v28 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_alignbit_b32 v15, v15, v47, 16 -; SI-NEXT: v_mov_b32_e32 v51, v47 -; SI-NEXT: v_mov_b32_e32 v53, v45 +; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v27 +; SI-NEXT: v_lshr_b64 v[27:28], v[28:29], 16 +; SI-NEXT: v_lshr_b64 v[28:29], v[51:52], 16 +; SI-NEXT: v_lshr_b64 v[29:30], v[53:54], 16 +; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v52, v53 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v30 +; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshr_b64 v[30:31], v[31:32], 16 +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v57 +; SI-NEXT: v_mov_b32_e32 v53, v31 +; SI-NEXT: v_lshr_b64 v[31:32], v[31:32], 16 ; SI-NEXT: s_branch .LBB43_3 ; SI-NEXT: .LBB43_2: -; SI-NEXT: v_mov_b32_e32 v63, v44 -; SI-NEXT: v_mov_b32_e32 v44, v43 -; SI-NEXT: v_mov_b32_e32 v43, v41 -; SI-NEXT: v_mov_b32_e32 v40, v55 -; SI-NEXT: v_mov_b32_e32 v48, v53 -; SI-NEXT: v_mov_b32_e32 v52, v51 -; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload -; SI-NEXT: v_mov_b32_e32 v62, v61 -; SI-NEXT: v_mov_b32_e32 v60, v59 -; SI-NEXT: v_mov_b32_e32 v58, v57 -; SI-NEXT: v_mov_b32_e32 v56, v47 -; SI-NEXT: v_mov_b32_e32 v46, v45 -; SI-NEXT: v_mov_b32_e32 v50, v49 -; SI-NEXT: v_mov_b32_e32 v36, v39 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v34, v38 -; SI-NEXT: v_mov_b32_e32 v35, v37 -; SI-NEXT: v_mov_b32_e32 v37, v32 +; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill +; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v56, v44 +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v55, v13 +; SI-NEXT: s_waitcnt expcnt(2) +; SI-NEXT: v_mov_b32_e32 v33, v34 +; SI-NEXT: v_mov_b32_e32 v34, v47 +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_mov_b32_e32 v43, v28 +; SI-NEXT: v_mov_b32_e32 v52, v53 +; SI-NEXT: v_mov_b32_e32 v53, v0 ; SI-NEXT: s_mov_b64 s[4:5], -1 -; SI-NEXT: v_mov_b32_e32 v32, v33 -; SI-NEXT: v_mov_b32_e32 v33, v42 +; SI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_mov_b32_e32 v41, v26 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v42, v51 ; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; SI-NEXT: .LBB43_3: ; %Flow -; SI-NEXT: v_mov_b32_e32 v38, v50 -; SI-NEXT: v_mov_b32_e32 v39, v52 -; SI-NEXT: v_mov_b32_e32 v49, v40 -; SI-NEXT: v_mov_b32_e32 v50, v43 -; SI-NEXT: v_mov_b32_e32 v43, v44 -; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v37, v34 +; SI-NEXT: v_mov_b32_e32 v34, v33 +; SI-NEXT: v_mov_b32_e32 v35, v56 +; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: v_mov_b32_e32 v32, v40 +; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload ; SI-NEXT: s_andn2_b64 vcc, exec, s[4:5] +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_mov_b32_e32 v33, v38 +; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v51, v46 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v54, v46 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v44, v46 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v45, v56 +; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v47, v56 +; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v58, v60 +; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload ; SI-NEXT: s_cbranch_vccnz .LBB43_5 ; SI-NEXT: ; %bb.4: ; %cmp.true -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v44 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v57 +; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v61 +; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v49 ; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8 ; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v40 +; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v39 ; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 ; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v63 -; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 -; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v62 -; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 -; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v60 +; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v59 ; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 ; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v58 -; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 -; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v46 -; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 -; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32 +; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v40 +; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 +; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v35 +; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 +; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v32 +; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 +; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v53 ; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32 -; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 ; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 +; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16 -; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 -; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16 +; SI-NEXT: v_lshr_b64 v[1:2], v[2:3], 16 +; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v60 +; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 ; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 ; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 -; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; SI-NEXT: s_waitcnt vmcnt(13) ; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 ; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 ; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 -; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; SI-NEXT: s_waitcnt vmcnt(12) +; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 +; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; SI-NEXT: s_waitcnt vmcnt(8) +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; SI-NEXT: s_waitcnt vmcnt(7) +; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15 ; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 ; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 ; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; SI-NEXT: s_waitcnt vmcnt(13) ; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 ; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 ; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; SI-NEXT: s_waitcnt vmcnt(12) -; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 -; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 -; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22 -; SI-NEXT: s_waitcnt vmcnt(10) -; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 -; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23 -; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 -; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; SI-NEXT: s_waitcnt vmcnt(8) -; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 -; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 -; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26 -; SI-NEXT: s_waitcnt vmcnt(6) -; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 -; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; SI-NEXT: s_waitcnt vmcnt(5) +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 +; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 +; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 ; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 ; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28 -; SI-NEXT: s_waitcnt vmcnt(4) +; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 ; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 ; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 +; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26 ; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 -; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 -; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 -; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16 -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v58 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16 +; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v56 ; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 -; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16 -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16 +; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v47 ; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 -; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16 -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16 +; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v45 ; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 -; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16 -; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v45 +; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16 +; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v46 ; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 -; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16 -; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v42 +; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16 +; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v44 ; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8 -; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16 -; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v52 +; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16 +; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v54 ; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 -; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16 -; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v41 +; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16 +; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v51 ; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 -; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16 -; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v55 +; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16 +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v50 ; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 -; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16 -; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v54 +; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16 +; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v55 ; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 -; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16 -; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v56 +; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16 +; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v48 ; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 -; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16 -; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v53 +; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16 +; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v38 ; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 -; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16 -; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v51 +; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16 +; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v33 ; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 -; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16 -; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v43 +; SI-NEXT: v_lshr_b64 v[15:16], v[15:16], 16 +; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 +; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 ; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; SI-NEXT: v_alignbit_b32 v16, v17, v16, 16 -; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v50 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 ; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 -; SI-NEXT: v_alignbit_b32 v17, v18, v17, 16 -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; SI-NEXT: v_lshr_b64 v[16:17], v[16:17], 16 +; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v34 +; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 +; SI-NEXT: v_lshr_b64 v[17:18], v[17:18], 16 +; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v37 ; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; SI-NEXT: v_alignbit_b32 v18, v19, v18, 16 -; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v49 +; SI-NEXT: v_lshr_b64 v[18:19], v[18:19], 16 +; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v36 ; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 -; SI-NEXT: v_alignbit_b32 v19, v20, v19, 16 -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshr_b64 v[19:20], v[19:20], 16 +; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v33 +; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; SI-NEXT: v_lshr_b64 v[32:33], v[32:33], 16 +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 ; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 -; SI-NEXT: v_alignbit_b32 v20, v21, v20, 16 -; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v48 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 +; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; SI-NEXT: v_lshr_b64 v[20:21], v[20:21], 16 +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 ; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 -; SI-NEXT: v_alignbit_b32 v21, v22, v21, 16 -; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 ; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 -; SI-NEXT: v_alignbit_b32 v22, v23, v22, 16 -; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v39 +; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; SI-NEXT: v_lshr_b64 v[21:22], v[21:22], 16 +; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; SI-NEXT: v_lshr_b64 v[22:23], v[22:23], 16 +; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 ; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 -; SI-NEXT: v_alignbit_b32 v23, v24, v23, 16 -; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 ; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 -; SI-NEXT: v_alignbit_b32 v24, v25, v24, 16 -; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v38 +; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; SI-NEXT: v_lshr_b64 v[23:24], v[23:24], 16 +; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 ; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 -; SI-NEXT: v_alignbit_b32 v25, v26, v25, 16 -; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v36 +; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; SI-NEXT: v_lshr_b64 v[24:25], v[24:25], 16 +; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v41 +; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 +; SI-NEXT: v_lshr_b64 v[25:26], v[25:26], 16 +; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 ; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 -; SI-NEXT: v_alignbit_b32 v26, v27, v26, 16 -; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v34 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 ; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 -; SI-NEXT: v_alignbit_b32 v27, v28, v27, 16 -; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v35 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; SI-NEXT: v_lshr_b64 v[26:27], v[26:27], 16 +; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v43 +; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 +; SI-NEXT: v_lshr_b64 v[27:28], v[27:28], 16 +; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v42 ; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 -; SI-NEXT: v_alignbit_b32 v28, v29, v28, 16 -; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v37 +; SI-NEXT: v_lshr_b64 v[28:29], v[28:29], 16 +; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v52 ; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 -; SI-NEXT: v_alignbit_b32 v29, v30, v29, 16 -; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshr_b64 v[29:30], v[29:30], 16 +; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 ; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 -; SI-NEXT: v_alignbit_b32 v30, v31, v30, 16 -; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v33 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 ; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 -; SI-NEXT: v_alignbit_b32 v31, v32, v31, 16 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31 +; SI-NEXT: v_lshr_b64 v[30:31], v[30:31], 16 +; SI-NEXT: v_mov_b32_e32 v31, v32 ; SI-NEXT: .LBB43_5: ; %end ; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload @@ -65969,36 +65502,39 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg ; VI-NEXT: v_mov_b32_e32 v31, v17 ; VI-NEXT: v_mov_b32_e32 v30, v16 ; VI-NEXT: v_mov_b32_e32 v29, v15 -; VI-NEXT: v_mov_b32_e32 v28, v14 ; VI-NEXT: v_mov_b32_e32 v27, v13 -; VI-NEXT: v_mov_b32_e32 v26, v12 ; VI-NEXT: v_mov_b32_e32 v25, v11 -; VI-NEXT: v_mov_b32_e32 v24, v10 ; VI-NEXT: v_mov_b32_e32 v23, v9 -; VI-NEXT: v_mov_b32_e32 v22, v8 ; VI-NEXT: v_mov_b32_e32 v21, v7 -; VI-NEXT: v_mov_b32_e32 v20, v6 ; VI-NEXT: v_mov_b32_e32 v19, v5 -; VI-NEXT: v_mov_b32_e32 v32, v4 ; VI-NEXT: v_mov_b32_e32 v17, v3 -; VI-NEXT: v_mov_b32_e32 v16, v2 ; VI-NEXT: v_mov_b32_e32 v15, v1 +; VI-NEXT: v_mov_b32_e32 v28, v14 +; VI-NEXT: v_mov_b32_e32 v26, v12 +; VI-NEXT: v_mov_b32_e32 v24, v10 +; VI-NEXT: v_mov_b32_e32 v22, v8 +; VI-NEXT: v_mov_b32_e32 v20, v6 +; VI-NEXT: v_mov_b32_e32 v32, v4 +; VI-NEXT: v_mov_b32_e32 v16, v2 ; VI-NEXT: v_mov_b32_e32 v14, v0 -; VI-NEXT: v_mov_b32_e32 v0, s16 -; VI-NEXT: v_mov_b32_e32 v1, s17 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec -; VI-NEXT: v_mov_b32_e32 v2, s18 +; VI-NEXT: v_mov_b32_e32 v1, s17 ; VI-NEXT: v_mov_b32_e32 v3, s19 -; VI-NEXT: v_mov_b32_e32 v4, s20 ; VI-NEXT: v_mov_b32_e32 v5, s21 -; VI-NEXT: v_mov_b32_e32 v6, s22 ; VI-NEXT: v_mov_b32_e32 v7, s23 -; VI-NEXT: v_mov_b32_e32 v8, s24 ; VI-NEXT: v_mov_b32_e32 v9, s25 -; VI-NEXT: v_mov_b32_e32 v10, s26 ; VI-NEXT: v_mov_b32_e32 v11, s27 -; VI-NEXT: v_mov_b32_e32 v12, s28 ; VI-NEXT: v_mov_b32_e32 v13, s29 +; VI-NEXT: v_mov_b32_e32 v0, s16 +; VI-NEXT: v_mov_b32_e32 v2, s18 +; VI-NEXT: v_mov_b32_e32 v4, s20 +; VI-NEXT: v_mov_b32_e32 v6, s22 +; VI-NEXT: v_mov_b32_e32 v8, s24 +; VI-NEXT: v_mov_b32_e32 v10, s26 +; VI-NEXT: v_mov_b32_e32 v12, s28 +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB43_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_cbranch_execnz .LBB43_3 @@ -66007,580 +65543,600 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg ; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 ; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 ; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 ; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 ; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v15, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v15 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_bfe_u32 v18, v15, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc +; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15 +; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18 ; VI-NEXT: v_or_b32_e32 v34, 0x400000, v15 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 -; VI-NEXT: v_cndmask_b32_e32 v15, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; VI-NEXT: v_alignbit_b32 v15, v15, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v14 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v15, v18, v34, vcc +; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v15 +; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v14 +; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; VI-NEXT: v_bfe_u32 v18, v15, 16, 1 +; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15 ; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18 ; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v14, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v14 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v14 +; VI-NEXT: v_lshrrev_b64 v[34:35], 16, v[33:34] +; VI-NEXT: v_or_b32_e32 v33, 0x400000, v15 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 +; VI-NEXT: v_bfe_u32 v15, v14, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v35, v18, v33, vcc +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v14 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 +; VI-NEXT: v_or_b32_e32 v18, 0x400000, v14 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 -; VI-NEXT: v_cndmask_b32_e32 v14, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; VI-NEXT: v_alignbit_b32 v14, v14, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v13 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v14, v15, v18, vcc +; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v14 +; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[35:36] +; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v13 +; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; VI-NEXT: v_bfe_u32 v18, v15, 16, 1 +; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15 ; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18 ; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v13, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v13 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v13 +; VI-NEXT: v_or_b32_e32 v33, 0x400000, v15 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 +; VI-NEXT: v_bfe_u32 v15, v13, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v35, v18, v33, vcc +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 +; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 -; VI-NEXT: v_cndmask_b32_e32 v13, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; VI-NEXT: v_alignbit_b32 v13, v13, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v12 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v13, v15, v18, vcc +; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v13 +; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v12 +; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; VI-NEXT: v_bfe_u32 v15, v13, 16, 1 +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13 ; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 ; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v12, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v12 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v12 +; VI-NEXT: v_lshrrev_b64 v[35:36], 16, v[35:36] +; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 +; VI-NEXT: v_bfe_u32 v13, v12, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v36, v15, v18, vcc +; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v12 +; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 +; VI-NEXT: v_or_b32_e32 v15, 0x400000, v12 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 -; VI-NEXT: v_cndmask_b32_e32 v12, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; VI-NEXT: v_alignbit_b32 v12, v12, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v11 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v12, v13, v15, vcc +; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v12 +; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[36:37] +; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v11 +; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; VI-NEXT: v_bfe_u32 v15, v13, 16, 1 +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13 ; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 ; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v11, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v11 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v11 +; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 +; VI-NEXT: v_bfe_u32 v13, v11, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v36, v15, v18, vcc +; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11 +; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 +; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 -; VI-NEXT: v_cndmask_b32_e32 v11, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; VI-NEXT: v_alignbit_b32 v11, v11, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v10 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v11, v13, v15, vcc +; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v11 +; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; VI-NEXT: v_bfe_u32 v13, v11, 16, 1 +; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11 ; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 ; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v10, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v10 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v10 +; VI-NEXT: v_lshrrev_b64 v[36:37], 16, v[36:37] +; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 +; VI-NEXT: v_bfe_u32 v11, v10, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v37, v13, v15, vcc +; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v10 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 +; VI-NEXT: v_or_b32_e32 v13, 0x400000, v10 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 -; VI-NEXT: v_cndmask_b32_e32 v10, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; VI-NEXT: v_alignbit_b32 v10, v10, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v9 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v10, v11, v13, vcc +; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v10 +; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[37:38] +; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v9 +; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; VI-NEXT: v_bfe_u32 v13, v11, 16, 1 +; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11 ; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 ; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v9, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v9 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v9 +; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 +; VI-NEXT: v_bfe_u32 v11, v9, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v37, v13, v15, vcc +; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 +; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 -; VI-NEXT: v_cndmask_b32_e32 v9, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; VI-NEXT: v_alignbit_b32 v9, v9, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v8 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc +; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9 +; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v8 +; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 +; VI-NEXT: v_bfe_u32 v11, v9, 16, 1 +; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9 ; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 ; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v8, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v8 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v8 +; VI-NEXT: v_lshrrev_b64 v[37:38], 16, v[37:38] +; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 +; VI-NEXT: v_bfe_u32 v9, v8, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v38, v11, v13, vcc +; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9 +; VI-NEXT: v_or_b32_e32 v11, 0x400000, v8 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8 -; VI-NEXT: v_cndmask_b32_e32 v8, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; VI-NEXT: v_alignbit_b32 v8, v8, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v7 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v8, v9, v11, vcc +; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8 +; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[38:39] +; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v7 +; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 +; VI-NEXT: v_bfe_u32 v11, v9, 16, 1 +; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9 ; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 ; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v7, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v7 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v7 +; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 +; VI-NEXT: v_bfe_u32 v9, v7, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v38, v11, v13, vcc +; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9 +; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 -; VI-NEXT: v_cndmask_b32_e32 v7, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; VI-NEXT: v_alignbit_b32 v7, v7, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v6 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v7, v9, v11, vcc +; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v7 +; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v6 +; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 +; VI-NEXT: v_bfe_u32 v9, v7, 16, 1 +; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7 ; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9 ; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v6, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v6 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v6 +; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 +; VI-NEXT: v_bfe_u32 v7, v6, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v48, v9, v11, vcc +; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v6 +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7 +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v6 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; VI-NEXT: v_cndmask_b32_e32 v6, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; VI-NEXT: v_alignbit_b32 v6, v6, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v5 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v6, v7, v9, vcc +; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6 +; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[48:49] +; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v5 +; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 +; VI-NEXT: v_bfe_u32 v9, v7, 16, 1 +; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7 ; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9 ; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v5, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v5 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v5 +; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 +; VI-NEXT: v_bfe_u32 v7, v5, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v48, v9, v11, vcc +; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5 +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7 +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; VI-NEXT: v_cndmask_b32_e32 v5, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; VI-NEXT: v_alignbit_b32 v5, v5, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v4 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc +; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v5 +; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v4 +; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 +; VI-NEXT: v_bfe_u32 v7, v5, 16, 1 +; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5 ; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7 ; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v4, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v4 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v4 +; VI-NEXT: v_lshrrev_b64 v[48:49], 16, v[48:49] +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 +; VI-NEXT: v_bfe_u32 v5, v4, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v49, v7, v9, vcc +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v4 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; VI-NEXT: v_cndmask_b32_e32 v4, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; VI-NEXT: v_alignbit_b32 v4, v4, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v3 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc +; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v4 +; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[49:50] +; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v3 +; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 +; VI-NEXT: v_bfe_u32 v7, v5, 16, 1 +; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5 ; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7 ; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v3, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v3 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v3 +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v49, v7, v9, vcc +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; VI-NEXT: v_cndmask_b32_e32 v3, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; VI-NEXT: v_alignbit_b32 v3, v3, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v2 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v3 +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 ; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 ; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v2 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v2 +; VI-NEXT: v_lshrrev_b64 v[49:50], 16, v[49:50] +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v50, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: v_alignbit_b32 v2, v2, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v1 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v2 +; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[50:51] +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v1 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 ; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 ; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v1 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v50, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; VI-NEXT: v_alignbit_b32 v1, v1, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v0 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 ; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v0, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v0 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v0 +; VI-NEXT: v_lshrrev_b64 v[50:51], 16, v[50:51] +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_bfe_u32 v1, v0, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v51, v3, v5, vcc +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1 +; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; VI-NEXT: v_cndmask_b32_e32 v0, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; VI-NEXT: v_alignbit_b32 v0, v0, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v31 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v31, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v31 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v31 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31 -; VI-NEXT: v_cndmask_b32_e32 v31, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; VI-NEXT: v_alignbit_b32 v31, v31, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v30 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v30, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v30 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v30 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 -; VI-NEXT: v_cndmask_b32_e32 v30, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; VI-NEXT: v_alignbit_b32 v30, v30, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v29 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v29, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v29 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v29 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 -; VI-NEXT: v_cndmask_b32_e32 v29, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v29 -; VI-NEXT: v_alignbit_b32 v29, v29, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v28 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v28, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v28 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v28 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 -; VI-NEXT: v_cndmask_b32_e32 v28, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v28 -; VI-NEXT: v_alignbit_b32 v28, v28, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v27 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v27, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v27 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v27 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 -; VI-NEXT: v_cndmask_b32_e32 v27, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; VI-NEXT: v_alignbit_b32 v27, v27, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v26 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v26, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v26 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v26 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 -; VI-NEXT: v_cndmask_b32_e32 v26, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v26 -; VI-NEXT: v_alignbit_b32 v26, v26, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v25 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v25, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v25 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v25 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 -; VI-NEXT: v_cndmask_b32_e32 v25, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 -; VI-NEXT: v_alignbit_b32 v25, v25, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v24 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v24, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v24 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v24 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; VI-NEXT: v_cndmask_b32_e32 v24, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; VI-NEXT: v_alignbit_b32 v24, v24, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v23 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v23, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v23 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v23 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 -; VI-NEXT: v_cndmask_b32_e32 v23, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v23 -; VI-NEXT: v_alignbit_b32 v23, v23, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v22 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v22, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v22 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v22 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 -; VI-NEXT: v_cndmask_b32_e32 v22, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v22 -; VI-NEXT: v_alignbit_b32 v22, v22, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v21 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v21, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v21 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v21 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 -; VI-NEXT: v_cndmask_b32_e32 v21, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; VI-NEXT: v_alignbit_b32 v21, v21, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v20 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v20, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v20 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v20 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 -; VI-NEXT: v_cndmask_b32_e32 v20, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; VI-NEXT: v_alignbit_b32 v20, v20, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v19 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v19, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v19 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v19 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 -; VI-NEXT: v_cndmask_b32_e32 v19, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; VI-NEXT: v_alignbit_b32 v19, v19, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v32 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v32, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 -; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; VI-NEXT: v_alignbit_b32 v32, v32, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v17 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v17, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v17 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v17 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 -; VI-NEXT: v_cndmask_b32_e32 v17, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; VI-NEXT: v_alignbit_b32 v17, v17, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v16 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v16, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v16 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v16 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16 -; VI-NEXT: v_cndmask_b32_e32 v16, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; VI-NEXT: v_alignbit_b32 v16, v16, v18, 16 +; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc +; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v0 +; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[51:52] +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v31 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v31 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v51, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v30 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v30 +; VI-NEXT: v_lshrrev_b64 v[51:52], 16, v[51:52] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v52, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v29 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v29 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[30:31], 16, v[52:53] +; VI-NEXT: v_cndmask_b32_e32 v52, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v28 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v28 +; VI-NEXT: v_lshrrev_b64 v[52:53], 16, v[52:53] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v53, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v27 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v27 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[28:29], 16, v[53:54] +; VI-NEXT: v_cndmask_b32_e32 v53, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v26 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v26 +; VI-NEXT: v_lshrrev_b64 v[53:54], 16, v[53:54] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v54, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v25 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v25 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[26:27], 16, v[54:55] +; VI-NEXT: v_cndmask_b32_e32 v54, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v24 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v24 +; VI-NEXT: v_lshrrev_b64 v[38:39], 16, v[38:39] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v39, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v23 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v23 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[24:25], 16, v[39:40] +; VI-NEXT: v_cndmask_b32_e32 v39, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v22 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v22 +; VI-NEXT: v_lshrrev_b64 v[39:40], 16, v[39:40] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v40, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v21 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v21 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[22:23], 16, v[40:41] +; VI-NEXT: v_cndmask_b32_e32 v40, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v20 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v20 +; VI-NEXT: v_lshrrev_b64 v[40:41], 16, v[40:41] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v41, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v19 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v19 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v18, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v32 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v32 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v31, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v17 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v17 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[20:21], 16, v[41:42] +; VI-NEXT: v_cndmask_b32_e32 v41, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v16 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v16 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v15, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b64 v[54:55], 16, v[54:55] +; VI-NEXT: v_lshrrev_b64 v[18:19], 16, v[18:19] +; VI-NEXT: v_lshrrev_b64 v[41:42], 16, v[41:42] +; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v1 +; VI-NEXT: v_lshrrev_b64 v[32:33], 16, v[31:32] +; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[15:16] +; VI-NEXT: v_mov_b32_e32 v1, v50 +; VI-NEXT: v_mov_b32_e32 v3, v49 +; VI-NEXT: v_mov_b32_e32 v5, v48 +; VI-NEXT: v_mov_b32_e32 v7, v38 +; VI-NEXT: v_mov_b32_e32 v9, v37 +; VI-NEXT: v_mov_b32_e32 v11, v36 +; VI-NEXT: v_mov_b32_e32 v13, v35 +; VI-NEXT: v_mov_b32_e32 v15, v34 +; VI-NEXT: v_mov_b32_e32 v17, v41 +; VI-NEXT: v_mov_b32_e32 v19, v18 +; VI-NEXT: v_mov_b32_e32 v21, v40 +; VI-NEXT: v_mov_b32_e32 v23, v39 +; VI-NEXT: v_mov_b32_e32 v25, v54 +; VI-NEXT: v_mov_b32_e32 v27, v53 +; VI-NEXT: v_mov_b32_e32 v29, v52 +; VI-NEXT: v_mov_b32_e32 v31, v51 ; VI-NEXT: .LBB43_3: ; %end +; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload ; VI-NEXT: v_mov_b32_e32 v18, v32 +; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_setpc_b64 s[30:31] ; VI-NEXT: .LBB43_4: ; VI-NEXT: s_branch .LBB43_2 @@ -67245,100 +66801,26 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 -; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:156 -; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:28 -; GFX11-TRUE16-NEXT: s_clause 0x6 ; 28-byte Folded Spill -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v167, v13 :: v_dual_mov_b32 v176, v12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v177, v11 :: v_dual_mov_b32 v178, v10 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v179, v9 :: v_dual_mov_b32 v180, v8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v181, v7 :: v_dual_mov_b32 v182, v6 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v183, v5 :: v_dual_mov_b32 v168, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v169, v3 :: v_dual_mov_b32 v170, v2 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v171, v1 :: v_dual_mov_b32 v172, v0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v174, s28 :: v_dual_mov_b32 v173, s29 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, v13 :: v_dual_mov_b32 v30, v12 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, 0 ; GFX11-TRUE16-NEXT: s_and_b32 s5, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB43_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v135, s0 :: v_dual_mov_b32 v134, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v132, s2 :: v_dual_mov_b32 v129, s3 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v125, s16 :: v_dual_mov_b32 v120, s17 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v114, s18 :: v_dual_mov_b32 v107, s19 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v99, s20 :: v_dual_mov_b32 v90, s21 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v80, s22 :: v_dual_mov_b32 v69, s23 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v57, s24 :: v_dual_mov_b32 v44, s25 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, s26 :: v_dual_mov_b32 v15, s27 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 ; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB43_3 ; GFX11-TRUE16-NEXT: .LBB43_2: ; %cmp.true @@ -67349,972 +66831,674 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg ; GFX11-TRUE16-NEXT: s_and_b32 s4, s26, 0xffff0000 ; GFX11-TRUE16-NEXT: s_lshl_b32 s6, s26, 16 ; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1 +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1 ; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v1 +; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s6 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3 ; GFX11-TRUE16-NEXT: s_and_b32 s5, s25, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s7, s25, 16 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s6 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0 ; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s5 -; GFX11-TRUE16-NEXT: s_and_b32 s4, s24, 0xffff0000 +; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s25, 16 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v8 :: v_dual_add_nc_u32 v7, v7, v3 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v7, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v3 -; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s7 -; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v9, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v3 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v6, 16, 1 ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v4 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7 -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s24, 16 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v7, v2 :: v_dual_add_nc_u32 v7, v8, v5 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v9, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v4 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v7 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v6 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v6 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: s_and_b32 s4, s24, 0xffff0000 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v10, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc_lo +; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v6 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v3 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1 +; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s24, 16 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v7, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v9, v5 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v7 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v7 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v6 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v3 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v1.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 16, v2 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.h, v4.l -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s23, 0xffff0000 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v57.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s23, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s22, 0xffff0000 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v1.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s22, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v9 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v0.l +; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s21, 0xffff0000 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s21, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s21, 16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3 +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v6 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s20, 0xffff0000 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v90, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v90.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s20, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s19, 0xffff0000 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v1.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8 ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v32 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v32, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s19, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v32 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v0.l +; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s18, 0xffff0000 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v107, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v107.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s18, 16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3 +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v6 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s17, 0xffff0000 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s17, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: s_and_b32 s4, s16, 0xffff0000 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v32, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v32 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v1.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v32 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v3, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX11-TRUE16-NEXT: s_and_b32 s4, s16, 0xffff0000 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v33, v3 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v120, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v120.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v34, 16, 1 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s16, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s3, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v125, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v125.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s3 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v32, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16 +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v33, 16, 1 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s3 ; GFX11-TRUE16-NEXT: s_and_b32 s3, s2, 0xffff0000 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v35, v32 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v35, 0x40c00000, s3 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v32 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v33 +; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v35, 16, 1 ; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v34 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v1.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v32, v35 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s2 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v34 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s3 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s2 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 ; GFX11-TRUE16-NEXT: s_and_b32 s2, s1, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s2 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1 -; GFX11-TRUE16-NEXT: s_and_b32 s1, s0, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v134.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v167 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v167 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v167.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v176 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v176 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v176.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v177 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v177 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v177.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v178 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v178 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v178, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v179 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v179 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v179.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v180 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v180 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v180.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v181 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v181 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v181.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v182 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v182 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v182.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v183 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v183 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v183.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v168 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v168 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v168, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v168.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v169 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v169 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v169, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v169.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v170 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v170 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v37, 0x40c00000, s2 +; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v32, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v170, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v170.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v171 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v171 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v171, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v171.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v172 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v172 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v172, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v172.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v173 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v173 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v37, 16, 1 +; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v33, vcc_lo +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, v36, v32 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v34, v37 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s1 +; GFX11-TRUE16-NEXT: s_and_b32 s1, s0, 0xffff0000 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v0.l +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v32 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v35, 0x40c00000, s1 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v173, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v173.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v174 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v33, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v2, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, v38, v34 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v32, v35 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v31 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v36 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v36, 0x40c00000, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v33, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v36 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v37 :: v_dual_add_nc_u32 v33, v33, v36 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v32.l +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v30 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v0 +; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v33, v33, v35 :: v_dual_add_nc_u32 v0, v0, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v33 +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v32.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v36, v37 :: v_dual_add_f32 v31, 0x40c00000, v31 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v33, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v31, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, v38, v31 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v29 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v36 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v31 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v30, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v30 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v34, v30 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_and_b32 v37, 0xffff0000, v28 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v33.l +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v30, v34, v36 :: v_dual_add_nc_u32 v33, v33, v35 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v29, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_dual_add_f32 v28, 0x40c00000, v28 :: v_dual_add_nc_u32 v35, v37, v29 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v32.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v33, v33, v36 :: v_dual_add_nc_u32 v32, v38, v34 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v29 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v27 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v35, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v28, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v28 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_add_nc_u32 v35, v35, v28 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v26 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v33.l +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX11-TRUE16-NEXT: v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_add_f32 v27, 0x40c00000, v27 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, v33, v34 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v28, v35, v36 :: v_dual_add_f32 v35, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v27, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v37, v27 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v27 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v38, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v25 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v26, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v26 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v34, v26 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_and_b32 v37, 0xffff0000, v24 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v33.l +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_add_f32 v25, 0x40c00000, v25 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v32.l +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v25, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v38, v34 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v23 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, v33, v35 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, v37, v25 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v25 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v35, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v24, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v24 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v33.l +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_and_b32 v37, 0xffff0000, v22 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, v35, v24 +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v174 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v24, v35, v36 :: v_dual_add_nc_u32 v33, v33, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v23, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v37, v23 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v23 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v38, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v21 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v22, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v22 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v34, v22 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_and_b32 v37, 0xffff0000, v20 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v33.l +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, v33, v35 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v32.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v38, v34 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v19 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v21, 16, 1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v21 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, v37, v21 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v174, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v174.h, v0.l +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v35, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v20, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v20 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_add_nc_u32 v35, v35, v20 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v33.l +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v18 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, v33, v34 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v20, v35, v36 :: v_dual_add_f32 v35, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v19, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v37, v19 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v19 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v32.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v38, v35 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v17 +; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v18, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, v39, v18 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v33.l +; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v34, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v38 :: v_dual_add_nc_u32 v33, 0x7fff, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v18 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v16 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, v36, v34 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_lshlrev_b32 v16, 16, v16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v33, v35 :: v_dual_add_f32 v33, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v36 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v17, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v33, 16, 1 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v17 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v35, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, v37, v17 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, v38, v33 +; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v16, 16, 1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v33 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 0x7fff, v37 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, v35, v16 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v48, 0x400000, v16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v32.l +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v37, v38, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v36, v39, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v35, v48, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v34.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v33.l ; GFX11-TRUE16-NEXT: .LBB43_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v125 :: v_dual_mov_b32 v5, v120 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v114 :: v_dual_mov_b32 v7, v107 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v99 :: v_dual_mov_b32 v9, v90 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v57 :: v_dual_mov_b32 v13, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v30 :: v_dual_mov_b32 v17, v173 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, v174 :: v_dual_mov_b32 v19, v171 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v172 :: v_dual_mov_b32 v21, v169 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, v170 :: v_dual_mov_b32 v23, v183 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, v168 :: v_dual_mov_b32 v25, v181 -; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0x6 ; 28-byte Folded Reload -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:280 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v135 :: v_dual_mov_b32 v1, v134 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v132 :: v_dual_mov_b32 v3, v129 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v80 :: v_dual_mov_b32 v11, v69 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v24, v182 :: v_dual_mov_b32 v27, v179 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v180 :: v_dual_mov_b32 v29, v177 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v178 :: v_dual_mov_b32 v31, v167 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v30, v176 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB43_4: -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 ; GFX11-TRUE16-NEXT: s_branch .LBB43_2 ; ; GFX11-FAKE16-LABEL: bitcast_v64bf16_to_v32f32_scalar: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 -; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:288 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:284 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:280 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:276 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:272 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:268 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:264 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:260 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:256 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:252 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:248 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:244 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:240 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:236 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:232 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:228 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:224 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:220 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:216 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:212 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:208 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:204 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:200 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:196 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:192 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:188 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:184 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:180 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:176 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:172 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:168 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:164 -; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:160 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:156 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:152 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:148 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:144 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:140 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:136 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:132 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:128 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:124 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:120 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:116 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:112 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:108 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:104 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:100 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:96 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:92 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:88 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v139, s32 offset:84 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v140, s32 offset:80 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v141, s32 offset:76 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v142, s32 offset:72 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v143, s32 offset:68 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v152, s32 offset:64 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v153, s32 offset:60 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v154, s32 offset:56 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v155, s32 offset:52 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v156, s32 offset:48 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v157, s32 offset:44 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v158, s32 offset:40 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v159, s32 offset:36 -; GFX11-FAKE16-NEXT: s_clause 0x8 ; 36-byte Folded Spill -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v168, s32 offset:32 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v169, s32 offset:28 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v170, s32 offset:24 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v171, s32 offset:20 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v172, s32 offset:16 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v173, s32 offset:12 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v174, s32 offset:8 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v175, s32 offset:4 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v184, s32 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v178, v13 :: v_dual_mov_b32 v179, v12 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v180, v11 :: v_dual_mov_b32 v181, v9 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v182, v10 :: v_dual_mov_b32 v169, v7 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v170, v8 :: v_dual_mov_b32 v177, v3 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v176, v6 :: v_dual_mov_b32 v171, v4 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v174, v5 :: v_dual_mov_b32 v173, v0 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v184, v2 :: v_dual_mov_b32 v175, v1 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v183, s28 :: v_dual_mov_b32 v172, s29 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v13 :: v_dual_mov_b32 v30, v12 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 ; GFX11-FAKE16-NEXT: s_mov_b32 s4, 0 ; GFX11-FAKE16-NEXT: s_and_b32 s5, vcc_lo, exec_lo ; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB43_4 ; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, s0 :: v_dual_mov_b32 v37, s2 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, s1 :: v_dual_mov_b32 v41, s3 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v46, s16 :: v_dual_mov_b32 v59, s18 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, s17 :: v_dual_mov_b32 v67, s19 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v76, s20 :: v_dual_mov_b32 v97, s22 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v86, s21 :: v_dual_mov_b32 v109, s23 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v122, s24 :: v_dual_mov_b32 v151, s26 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v136, s25 :: v_dual_mov_b32 v15, s27 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 ; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4 ; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB43_3 ; GFX11-FAKE16-NEXT: .LBB43_2: ; %cmp.true @@ -68322,762 +67506,674 @@ define inreg <32 x float> @bitcast_v64bf16_to_v32f32_scalar(<64 x bfloat> inreg ; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s27, 16 ; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s5 ; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s26, 16 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s26, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s6 +; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s26, 16 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 ; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1 ; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s6 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1 +; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1 ; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1 -; GFX11-FAKE16-NEXT: s_lshl_b32 s7, s25, 16 +; GFX11-FAKE16-NEXT: s_and_b32 s5, s25, 0xffff0000 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0 -; GFX11-FAKE16-NEXT: s_and_b32 s5, s25, 0xffff0000 -; GFX11-FAKE16-NEXT: s_and_b32 s4, s24, 0xffff0000 ; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s5 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v183 +; GFX11-FAKE16-NEXT: s_lshl_b32 s7, s25, 16 +; GFX11-FAKE16-NEXT: s_and_b32 s4, s24, 0xffff0000 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s24, 16 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v9, v3 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v5 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v9, v3 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v6, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v7, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v7 :: v_dual_add_nc_u32 v2, 0x7fff, v2 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v5 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s7 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v3 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 +; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v6, 16, 1 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v8, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v1, 16, v0 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v3, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v10, v6 +; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v1, 16, v0 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v5, v6 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v7, v9, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s23, 16 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v0, 16, v1 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 ; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s24, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v6 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v8 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s23, 0xffff0000 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo ; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v5 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v9 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v1, v7 :: v_dual_and_b32 v1, 0xffff, v2 -; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v9, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v6 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v7, v9 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s23, 16 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v151, v0, 16, v1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6 -; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v4, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: s_and_b32 s4, s22, 0xffff0000 -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v12, 16, 1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v11, v7 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v3 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s22, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v5 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v6 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v8 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v9, v12 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v10, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v12 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s22, 16 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1 +; GFX11-FAKE16-NEXT: s_and_b32 s4, s22, 0xffff0000 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6 +; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s21, 0xffff0000 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v6, v9, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v11, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v14, v10 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v5 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v7 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v13 :: v_dual_add_nc_u32 v7, v9, v11 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v12 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v10 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s21, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v11 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v13, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v16, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s21, 16 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 +; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s20, 0xffff0000 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v7, v14 :: v_dual_add_nc_u32 v10, v10, v13 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v8 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v13 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v11 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v12, v16 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s20, 16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11 -; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v12, 16, 1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v10, v14, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s20, 16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6 +; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s19, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, v18, v12 -; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v17, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s19, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v13 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v14 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, v16, v19 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v12 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v14 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s19, 16 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 +; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s18, 0xffff0000 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v16, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, v21, v17 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v11 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v13 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v20 :: v_dual_add_nc_u32 v13, v16, v18 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v19 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v17 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s18, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v18 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v19, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v20, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v22, 16, 1 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s18, 16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v6 +; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s17, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, v17, v20 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v13, v21 :: v_dual_and_b32 v13, 0xffff, v14 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v20 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v19, v22 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s17, 16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v22 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18 -; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v19, 16, 1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v17, v21, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s17, 16 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v32, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s5 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s16, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, v24, v19 -; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v25, 16, 1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v18, v23 :: v_dual_and_b32 v17, 0xffff, v16 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s16, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v20 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v21 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, v22, v25 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v19 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v24, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_bfe_u32 v27, v23, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x7fff, v21 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v25 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s16, 16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1 +; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v32, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v6 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v33 :: v_dual_add_nc_u32 v5, v7, v32 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v0, 16, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v32 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s5 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s3, 0xffff0000 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v22, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v24, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v25, v27, v23 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v18 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v20 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v21, v26 :: v_dual_add_nc_u32 v20, v22, v24 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, 0x7fff, v25 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v23 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v26, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 ; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v24 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v28, 0x40c00000, s3 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v25, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v26, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; GFX11-FAKE16-NEXT: v_bfe_u32 v25, v28, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v33, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v5 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v34, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s3 ; GFX11-FAKE16-NEXT: s_and_b32 s3, s2, 0xffff0000 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v24, v20, v27 :: v_dual_add_nc_u32 v23, v23, v26 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v21 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v22 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v26 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, 0x7fff, v23 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v24 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, v25, v28 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s3 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v33 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v32, v33 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v34, 16, 1 ; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, 0x400000, v28 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, 0x7fff, v24 -; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v25, 16, 1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v31, 0x40c00000, s2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v23, v27, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v33, v34 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v32, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v32 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v32 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v35, vcc_lo +; GFX11-FAKE16-NEXT: v_add_f32_e64 v35, 0x40c00000, s2 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v33 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v34 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s3 +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s2, s1, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, v30, v25 -; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v31, 16, 1 ; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v29, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e64 v29, 0x40c00000, s2 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v22 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v26 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v26, 0x7fff, v27 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, v28, v31 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v25 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v30, 0x40c00000, s1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v29, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, 0x7fff, v27 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v31 -; GFX11-FAKE16-NEXT: s_and_b32 s1, s0, 0xffff0000 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v26, v28, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v30, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, v33, v29 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v24 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v26 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v27, v27, v32 :: v_dual_add_nc_u32 v26, v28, v30 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v33, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v35 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v33 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v28, 0x7fff, v31 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, 0x400000, v29 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v4, v33 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v36, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v36, 0x40c00000, s1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v34 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s2 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v36, 16, 1 +; GFX11-FAKE16-NEXT: s_and_b32 s1, s0, 0xffff0000 ; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v26, 0x7fff, v26 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v30 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v28, v31, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v29, v32, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v32 -; GFX11-FAKE16-NEXT: v_bfe_u32 v31, v34, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v26, v33, vcc_lo -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v28 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v28, v29, v32 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v178 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v30 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v30, v31, v34 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v178 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v28, 0x7fff, v28 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v33, 0x40c00000, v33 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v109, v5, 16, v7 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v30, 0x7fff, v30 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v28, v35, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v32, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v36 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v38, 0x40c00000, s0 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v32, v34 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v33 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v36 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v35 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v35, 0x40c00000, s1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v34 +; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v38, 16, 1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v33, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v29 +; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v2, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v0, 16, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v33, v35 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v36, v38 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v38 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v34 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v31 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v32 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v31, 0x40c00000, v31 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v34, 16, 1 ; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v31, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v37, v33 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v30, v36, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v179 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v35, v31 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v33 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v179 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v31 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v1, 16, v32 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v36, v34 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v31 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v30 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v31 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 ; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v180 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v36 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v34, v38, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v36, 16, 1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v35, 16, 1 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v38, 16, v180 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_add_f32 v37, 0x40c00000, v37 :: v_dual_add_nc_u32 v34, v34, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v33, v35 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v38 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v33 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v34 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v31, v35, v37 :: v_dual_add_nc_u32 v32, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v30, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v33 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v35, v36 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v29 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v30 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v38 :: v_dual_lshlrev_b32 v29, 16, v29 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v30 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v36 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v32 -; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v37, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v34, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v29, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v32, 16, v31 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v178, v31, 16, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, v36, v37 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v33, v48 :: v_dual_lshlrev_b32 v36, 16, v182 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v38 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v33, v38 :: v_dual_add_nc_u32 v32, v34, v35 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v35, v38 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v182 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v34 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v37 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, 0x7fff, v31 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v179, v32, 16, v34 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v30 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v136, v2, 16, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v36, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v36 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v36, v29 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v28 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v29 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v31, v31, v48 :: v_dual_add_nc_u32 v38, v38, v35 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v37, v36 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v181 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v38 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v38, 16, v181 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v37, 0x40c00000, v37 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v38 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v39, vcc_lo +; GFX11-FAKE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v30 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v34, v37, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v33 -; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v37, 16, 1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v48, vcc_lo -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v180, v31, 16, v33 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v35, v37 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v170 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v38 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v36, v38 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_lshlrev_b32 v36, 16, v170 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v28, 16, 1 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v33, 16, v30 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v28 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v38 :: v_dual_add_nc_u32 v33, v35, v28 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v36 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v27 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v37 -; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v36, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v182, v31, 16, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, v38, v35 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, v39, v36 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v48, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v36 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v27, 0x40c00000, v27 :: v_dual_cndmask_b32 v28, v33, v37 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, 0x7fff, v31 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff, v29 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v27, 16, 1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v34, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v32, 16, v29 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v27 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v37 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v169 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v31, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v34, v35 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v36, v27 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v26 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v28 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v32, 16, v28 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v34, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v26, 16, 1 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v39, 16, v169 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v181, v32, 16, v33 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v37, 0x40c00000, v37 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v176 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v48, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v39 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v37, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v37 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v34 -; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v36, 16, 1 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v38 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v35, v37 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v176 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v32, v36 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v25 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v36 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v37, v26 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v26 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v36 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 -; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v49, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v36 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v32, v37, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v27 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v170, v33, 16, v31 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v49, v35 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v48 :: v_dual_add_nc_u32 v33, v37, v38 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v174 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v25, 0x40c00000, v25 :: v_dual_lshlrev_b32 v36, 16, v24 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v34, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v33, 16, v27 +; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v25, 16, 1 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v35 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v36 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v33, v25 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v25 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v36, 16, 1 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v26 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v24, 16, 1 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v23 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v33, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v39, v36 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v32, 16, v26 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v35, v24 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v36 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v38 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_cndmask_b32 v34, v34, v36 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v174 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v32 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v35, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_cndmask_b32 v33, v33, v39 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v169, v31, 16, v32 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, v37, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v34 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v31, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v24 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v35, vcc_lo +; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v22 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v171 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v34, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v32, 16, v25 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v33 +; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v23, 16, 1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v35 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v38, 16, v177 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, v31, v36 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v176, v33, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v37 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v32, v23 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v24, 16, v33 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v34 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v32, 0x40c00000, v32 :: v_dual_lshlrev_b32 v37, 16, v171 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, 0x7fff, v31 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v38 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v36 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v36 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37 -; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v32, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v32 -; GFX11-FAKE16-NEXT: v_bfe_u32 v50, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v31, v31, v34 :: v_dual_add_nc_u32 v36, v37, v32 -; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v177 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v37, 0x40c00000, v37 :: v_dual_add_nc_u32 v34, v34, v35 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v23 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v22 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v36, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v32, v34 :: v_dual_add_nc_u32 v34, v35, v36 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v21 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v22, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 -; GFX11-FAKE16-NEXT: v_bfe_u32 v49, v37, 16, 1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v50, v38 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v38 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v184 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_add_f32 v21, 0x40c00000, v21 :: v_dual_add_nc_u32 v32, v32, v22 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v34, v34, v48 :: v_dual_add_nc_u32 v35, v49, v37 +; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v21, 16, 1 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v21 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v23 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v48, v21 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v32, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v39, v35 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v20 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v184 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_cndmask_b32 v21, v36, v37 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v38 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v37 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v37, 0x40c00000, v50 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31 +; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v20, 16, 1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v39, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v33, 16, v23 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v34, 16, v22 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v36 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v38, 0x40c00000, v48 :: v_dual_cndmask_b32 v35, v35, v49 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v36 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v34 -; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v37, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff, v36 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v174, v33, 16, v31 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v171, v32, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, v48, v37 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v175 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v175 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v39, v39, v38 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v177, v35, 16, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, 0x7fff, v31 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v37 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v34, 0x40c00000, v34 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v39 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v38 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v37, v20 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v19 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v32, 16, v21 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v35 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v20 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v34, 0x40c00000, v34 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v36 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v33, v35 :: v_dual_and_b32 v33, 0xffff0000, v18 +; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v19, 16, 1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v34, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_lshlrev_b32 v18, 16, v18 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v38, v19 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_add_nc_u32 v35, v35, v34 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v19 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v34, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v31, v35, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v173 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v173 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v33 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_cndmask_b32 v32, v32, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v37, v33 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, v39, v34 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v34 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_nc_u32 v37, v37, v33 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v36, v38, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, 0x7fff, v37 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v38, v38, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v122, v3, 16, v6 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v37, v39, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v37 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v33 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v18 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v35, v39, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v18, 16, 1 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, 0x7fff, v38 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v48 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v36, v49 :: v_dual_lshlrev_b32 v48, 16, v183 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v38 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v48, 0x40c00000, v48 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v37, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v172 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v39, 16, v172 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v36, v38 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v55, 0x400000, v48 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v18 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v36, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v17 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v16 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v17, 0x40c00000, v17 ; GFX11-FAKE16-NEXT: v_add_f32_e32 v37, 0x40c00000, v37 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v39, 0x40c00000, v39 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v34 -; GFX11-FAKE16-NEXT: v_bfe_u32 v50, v37, 16, 1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v39, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v49, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v39 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v50, 0x40c00000, v51 :: v_dual_add_nc_u32 v49, v50, v37 -; GFX11-FAKE16-NEXT: v_bfe_u32 v51, v48, 16, 1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v38, v38, v39 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v53, 0x400000, v37 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v35, v38, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v49, 0x7fff, v49 -; GFX11-FAKE16-NEXT: v_bfe_u32 v52, v50, 16, 1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v51, v51, v48 +; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v17, 16, 1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v17 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v38, v39, v36 +; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v37, 16, 1 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v17 +; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v16, 16, 1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v51, 0x400000, v37 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v38, 0x7fff, v38 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v36 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v35 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v52, v52, v50 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v38, v38, v54 :: v_dual_add_nc_u32 v51, 0x7fff, v51 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v39, 0x7fff, v52 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v52, 0x400000, v50 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v38 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v51, v55, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v39, v39, v37 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v36 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v48, v48, v16 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v39, 0x7fff, v39 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v35, v50, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v184, v32, 16, v31 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v175, v33, 16, v34 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff, v38 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v48 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v49, v53, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v173, v35, 16, v36 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v97, v8, 16, v10 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff, v48 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v37 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v39, v52, vcc_lo -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v86, v9, 16, v12 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v76, v11, 16, v13 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v67, v14, 16, v17 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v172, v37, 16, v38 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v39 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v59, v16, 16, v19 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v52, v18, 16, v20 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v46, v21, 16, v23 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v41, v22, 16, v25 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v183, v39, 16, v48 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v37, v24, 16, v27 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v34, v26, 16, v28 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v32, v29, 16, v30 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v48 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v16 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v39, v51, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v18 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v38, v49, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v32, 16, v20 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v34, 16, v19 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v33, 16, v18 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v36 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v35, v48, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v37 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v36, 16, v17 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff, v35 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v16, 16, v35 ; GFX11-FAKE16-NEXT: .LBB43_3: ; %end -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, v41 :: v_dual_mov_b32 v4, v46 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, v59 :: v_dual_mov_b32 v9, v86 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v7, v67 :: v_dual_mov_b32 v8, v76 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, v97 :: v_dual_mov_b32 v13, v136 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v11, v109 :: v_dual_mov_b32 v12, v122 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, v151 :: v_dual_mov_b32 v17, v172 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, v173 :: v_dual_mov_b32 v19, v175 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v20, v184 :: v_dual_mov_b32 v23, v174 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v22, v171 :: v_dual_mov_b32 v25, v169 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v26, v170 :: v_dual_mov_b32 v29, v180 -; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-FAKE16-NEXT: scratch_load_b32 v184, off, s32 -; GFX11-FAKE16-NEXT: scratch_load_b32 v175, off, s32 offset:4 -; GFX11-FAKE16-NEXT: scratch_load_b32 v174, off, s32 offset:8 -; GFX11-FAKE16-NEXT: scratch_load_b32 v173, off, s32 offset:12 -; GFX11-FAKE16-NEXT: scratch_load_b32 v172, off, s32 offset:16 -; GFX11-FAKE16-NEXT: scratch_load_b32 v171, off, s32 offset:20 -; GFX11-FAKE16-NEXT: scratch_load_b32 v170, off, s32 offset:24 -; GFX11-FAKE16-NEXT: scratch_load_b32 v169, off, s32 offset:28 -; GFX11-FAKE16-NEXT: scratch_load_b32 v168, off, s32 offset:32 -; GFX11-FAKE16-NEXT: scratch_load_b32 v159, off, s32 offset:36 -; GFX11-FAKE16-NEXT: scratch_load_b32 v158, off, s32 offset:40 -; GFX11-FAKE16-NEXT: scratch_load_b32 v157, off, s32 offset:44 -; GFX11-FAKE16-NEXT: scratch_load_b32 v156, off, s32 offset:48 -; GFX11-FAKE16-NEXT: scratch_load_b32 v155, off, s32 offset:52 -; GFX11-FAKE16-NEXT: scratch_load_b32 v154, off, s32 offset:56 -; GFX11-FAKE16-NEXT: scratch_load_b32 v153, off, s32 offset:60 -; GFX11-FAKE16-NEXT: scratch_load_b32 v152, off, s32 offset:64 -; GFX11-FAKE16-NEXT: scratch_load_b32 v143, off, s32 offset:68 -; GFX11-FAKE16-NEXT: scratch_load_b32 v142, off, s32 offset:72 -; GFX11-FAKE16-NEXT: scratch_load_b32 v141, off, s32 offset:76 -; GFX11-FAKE16-NEXT: scratch_load_b32 v140, off, s32 offset:80 -; GFX11-FAKE16-NEXT: scratch_load_b32 v139, off, s32 offset:84 -; GFX11-FAKE16-NEXT: scratch_load_b32 v138, off, s32 offset:88 -; GFX11-FAKE16-NEXT: scratch_load_b32 v137, off, s32 offset:92 -; GFX11-FAKE16-NEXT: scratch_load_b32 v136, off, s32 offset:96 -; GFX11-FAKE16-NEXT: scratch_load_b32 v127, off, s32 offset:100 -; GFX11-FAKE16-NEXT: scratch_load_b32 v126, off, s32 offset:104 -; GFX11-FAKE16-NEXT: scratch_load_b32 v125, off, s32 offset:108 -; GFX11-FAKE16-NEXT: scratch_load_b32 v124, off, s32 offset:112 -; GFX11-FAKE16-NEXT: scratch_load_b32 v123, off, s32 offset:116 -; GFX11-FAKE16-NEXT: scratch_load_b32 v122, off, s32 offset:120 -; GFX11-FAKE16-NEXT: scratch_load_b32 v121, off, s32 offset:124 -; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-FAKE16-NEXT: scratch_load_b32 v120, off, s32 offset:128 -; GFX11-FAKE16-NEXT: scratch_load_b32 v111, off, s32 offset:132 -; GFX11-FAKE16-NEXT: scratch_load_b32 v110, off, s32 offset:136 -; GFX11-FAKE16-NEXT: scratch_load_b32 v109, off, s32 offset:140 -; GFX11-FAKE16-NEXT: scratch_load_b32 v108, off, s32 offset:144 -; GFX11-FAKE16-NEXT: scratch_load_b32 v107, off, s32 offset:148 -; GFX11-FAKE16-NEXT: scratch_load_b32 v106, off, s32 offset:152 -; GFX11-FAKE16-NEXT: scratch_load_b32 v105, off, s32 offset:156 -; GFX11-FAKE16-NEXT: scratch_load_b32 v104, off, s32 offset:160 -; GFX11-FAKE16-NEXT: scratch_load_b32 v95, off, s32 offset:164 -; GFX11-FAKE16-NEXT: scratch_load_b32 v94, off, s32 offset:168 -; GFX11-FAKE16-NEXT: scratch_load_b32 v93, off, s32 offset:172 -; GFX11-FAKE16-NEXT: scratch_load_b32 v92, off, s32 offset:176 -; GFX11-FAKE16-NEXT: scratch_load_b32 v91, off, s32 offset:180 -; GFX11-FAKE16-NEXT: scratch_load_b32 v90, off, s32 offset:184 -; GFX11-FAKE16-NEXT: scratch_load_b32 v89, off, s32 offset:188 -; GFX11-FAKE16-NEXT: scratch_load_b32 v88, off, s32 offset:192 -; GFX11-FAKE16-NEXT: scratch_load_b32 v79, off, s32 offset:196 -; GFX11-FAKE16-NEXT: scratch_load_b32 v78, off, s32 offset:200 -; GFX11-FAKE16-NEXT: scratch_load_b32 v77, off, s32 offset:204 -; GFX11-FAKE16-NEXT: scratch_load_b32 v76, off, s32 offset:208 -; GFX11-FAKE16-NEXT: scratch_load_b32 v75, off, s32 offset:212 -; GFX11-FAKE16-NEXT: scratch_load_b32 v74, off, s32 offset:216 -; GFX11-FAKE16-NEXT: scratch_load_b32 v73, off, s32 offset:220 -; GFX11-FAKE16-NEXT: scratch_load_b32 v72, off, s32 offset:224 -; GFX11-FAKE16-NEXT: scratch_load_b32 v63, off, s32 offset:228 -; GFX11-FAKE16-NEXT: scratch_load_b32 v62, off, s32 offset:232 -; GFX11-FAKE16-NEXT: scratch_load_b32 v61, off, s32 offset:236 -; GFX11-FAKE16-NEXT: scratch_load_b32 v60, off, s32 offset:240 -; GFX11-FAKE16-NEXT: scratch_load_b32 v59, off, s32 offset:244 -; GFX11-FAKE16-NEXT: scratch_load_b32 v58, off, s32 offset:248 -; GFX11-FAKE16-NEXT: scratch_load_b32 v57, off, s32 offset:252 -; GFX11-FAKE16-NEXT: s_clause 0x8 ; 36-byte Folded Reload -; GFX11-FAKE16-NEXT: scratch_load_b32 v56, off, s32 offset:256 -; GFX11-FAKE16-NEXT: scratch_load_b32 v47, off, s32 offset:260 -; GFX11-FAKE16-NEXT: scratch_load_b32 v46, off, s32 offset:264 -; GFX11-FAKE16-NEXT: scratch_load_b32 v45, off, s32 offset:268 -; GFX11-FAKE16-NEXT: scratch_load_b32 v44, off, s32 offset:272 -; GFX11-FAKE16-NEXT: scratch_load_b32 v43, off, s32 offset:276 -; GFX11-FAKE16-NEXT: scratch_load_b32 v42, off, s32 offset:280 -; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s32 offset:284 -; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 offset:288 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, v32 :: v_dual_mov_b32 v1, v34 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, v37 :: v_dual_mov_b32 v5, v52 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, v183 :: v_dual_mov_b32 v21, v177 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v24, v176 :: v_dual_mov_b32 v27, v181 -; GFX11-FAKE16-NEXT: v_mov_b32_e32 v28, v182 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v30, v179 :: v_dual_mov_b32 v31, v178 -; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-FAKE16-NEXT: .LBB43_4: -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr15 ; GFX11-FAKE16-NEXT: s_branch .LBB43_2 %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -70047,25 +69143,6 @@ define inreg <64 x half> @bitcast_v32f32_to_v64f16_scalar(<32 x float> inreg %a, ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_readfirstlane_b32 s47, v1 -; SI-NEXT: v_readfirstlane_b32 s46, v2 -; SI-NEXT: v_readfirstlane_b32 s45, v3 -; SI-NEXT: v_readfirstlane_b32 s44, v4 -; SI-NEXT: v_readfirstlane_b32 s43, v5 -; SI-NEXT: v_readfirstlane_b32 s42, v6 -; SI-NEXT: v_readfirstlane_b32 s41, v7 -; SI-NEXT: v_readfirstlane_b32 s40, v8 -; SI-NEXT: v_readfirstlane_b32 s15, v9 -; SI-NEXT: v_readfirstlane_b32 s14, v10 -; SI-NEXT: v_readfirstlane_b32 s13, v11 -; SI-NEXT: v_readfirstlane_b32 s12, v12 -; SI-NEXT: v_readfirstlane_b32 s11, v13 -; SI-NEXT: v_readfirstlane_b32 s10, v14 -; SI-NEXT: v_readfirstlane_b32 s8, v15 -; SI-NEXT: v_readfirstlane_b32 s7, v16 -; SI-NEXT: v_readfirstlane_b32 s6, v17 -; SI-NEXT: s_and_b64 s[4:5], vcc, exec -; SI-NEXT: v_readfirstlane_b32 s9, v18 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -70082,484 +69159,653 @@ define inreg <64 x half> @bitcast_v32f32_to_v64f16_scalar(<32 x float> inreg %a, ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v42, s16 +; SI-NEXT: s_and_b64 s[4:5], vcc, exec +; SI-NEXT: v_mov_b32_e32 v43, s17 +; SI-NEXT: v_mov_b32_e32 v41, s18 +; SI-NEXT: v_mov_b32_e32 v40, s19 +; SI-NEXT: v_mov_b32_e32 v55, s20 +; SI-NEXT: v_mov_b32_e32 v54, s21 +; SI-NEXT: v_mov_b32_e32 v53, s22 +; SI-NEXT: v_mov_b32_e32 v52, s23 +; SI-NEXT: v_mov_b32_e32 v51, s24 +; SI-NEXT: v_mov_b32_e32 v50, s25 +; SI-NEXT: v_mov_b32_e32 v49, s26 +; SI-NEXT: v_mov_b32_e32 v39, s27 +; SI-NEXT: v_mov_b32_e32 v38, s28 +; SI-NEXT: v_mov_b32_e32 v37, s29 ; SI-NEXT: s_cbranch_scc0 .LBB45_4 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: s_lshr_b32 s4, s9, 16 -; SI-NEXT: s_waitcnt expcnt(5) -; SI-NEXT: v_cvt_f32_f16_e32 v58, s4 -; SI-NEXT: s_lshr_b32 s4, s6, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v43, s4 -; SI-NEXT: s_lshr_b32 s4, s7, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v55, s4 -; SI-NEXT: s_lshr_b32 s4, s8, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v51, s4 -; SI-NEXT: s_lshr_b32 s4, s10, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v39, s4 -; SI-NEXT: s_lshr_b32 s4, s11, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v35, s4 -; SI-NEXT: s_lshr_b32 s4, s12, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v32, s4 -; SI-NEXT: s_lshr_b32 s4, s13, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v13, s4 -; SI-NEXT: s_lshr_b32 s4, s14, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v11, s4 -; SI-NEXT: s_lshr_b32 s4, s15, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v9, s4 -; SI-NEXT: s_lshr_b32 s4, s40, 16 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v53 +; SI-NEXT: v_cvt_f32_f16_e32 v21, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v54 +; SI-NEXT: v_cvt_f32_f16_e32 v24, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v55 +; SI-NEXT: v_cvt_f32_f16_e32 v26, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v40 +; SI-NEXT: v_cvt_f32_f16_e32 v28, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v41 +; SI-NEXT: v_cvt_f32_f16_e32 v30, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v43 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v42 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v20 +; SI-NEXT: v_cvt_f32_f16_e32 v20, v18 +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v18 ; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_cvt_f32_f16_e32 v61, s4 -; SI-NEXT: s_lshr_b32 s4, s41, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v23, s4 -; SI-NEXT: s_lshr_b32 s4, s42, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v25, s4 -; SI-NEXT: s_lshr_b32 s4, s43, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v27, s4 -; SI-NEXT: s_lshr_b32 s4, s44, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s4 -; SI-NEXT: s_lshr_b32 s4, s45, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v31, s4 -; SI-NEXT: s_lshr_b32 s4, s46, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v33, s4 -; SI-NEXT: s_lshr_b32 s4, s47, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v36, s4 -; SI-NEXT: s_lshr_b32 s4, s29, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v38, s4 -; SI-NEXT: s_lshr_b32 s4, s28, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v48, s4 -; SI-NEXT: s_lshr_b32 s4, s27, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v50, s4 -; SI-NEXT: s_lshr_b32 s4, s26, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v52, s4 -; SI-NEXT: s_lshr_b32 s4, s25, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v54, s4 -; SI-NEXT: s_lshr_b32 s4, s24, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v40, s4 -; SI-NEXT: s_lshr_b32 s4, s23, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v1, s14 -; SI-NEXT: v_cvt_f32_f16_e32 v42, s4 -; SI-NEXT: s_lshr_b32 s4, s22, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v44, s4 -; SI-NEXT: s_lshr_b32 s4, s21, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v46, s4 -; SI-NEXT: s_lshr_b32 s4, s20, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v56, s4 -; SI-NEXT: s_lshr_b32 s4, s19, 16 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f32_f16_e32 v61, v19 +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v17 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v17 +; SI-NEXT: v_cvt_f32_f16_e32 v59, v19 +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v16 +; SI-NEXT: v_cvt_f32_f16_e32 v57, v19 +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v15 +; SI-NEXT: v_cvt_f32_f16_e32 v47, v19 +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v14 +; SI-NEXT: v_cvt_f32_f16_e32 v45, v19 +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v13 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v1, s15 -; SI-NEXT: v_cvt_f32_f16_e32 v3, s4 -; SI-NEXT: s_lshr_b32 s4, s18, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v47, s4 -; SI-NEXT: s_lshr_b32 s4, s17, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v60, s4 -; SI-NEXT: s_lshr_b32 s4, s16, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v62, s4 -; SI-NEXT: v_cvt_f32_f16_e32 v5, s9 -; SI-NEXT: v_cvt_f32_f16_e32 v6, s6 -; SI-NEXT: v_cvt_f32_f16_e32 v7, s7 -; SI-NEXT: v_cvt_f32_f16_e32 v41, s8 -; SI-NEXT: v_cvt_f32_f16_e32 v45, s10 -; SI-NEXT: v_cvt_f32_f16_e32 v59, s11 -; SI-NEXT: v_cvt_f32_f16_e32 v63, s12 -; SI-NEXT: v_cvt_f32_f16_e32 v57, s13 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill -; SI-NEXT: v_cvt_f32_f16_e32 v22, s40 -; SI-NEXT: v_cvt_f32_f16_e32 v24, s41 -; SI-NEXT: v_cvt_f32_f16_e32 v26, s42 -; SI-NEXT: v_cvt_f32_f16_e32 v28, s43 -; SI-NEXT: v_cvt_f32_f16_e32 v30, s44 -; SI-NEXT: v_cvt_f32_f16_e32 v15, s45 -; SI-NEXT: v_cvt_f32_f16_e32 v34, s46 -; SI-NEXT: v_cvt_f32_f16_e32 v17, s47 -; SI-NEXT: v_cvt_f32_f16_e32 v37, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v19, s28 -; SI-NEXT: v_cvt_f32_f16_e32 v49, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v16, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v53, s25 -; SI-NEXT: v_cvt_f32_f16_e32 v12, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v14, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v8, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v20, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v4, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v10, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v18, s18 -; SI-NEXT: v_cvt_f32_f16_e32 v21, s17 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v1, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v20, v16 +; SI-NEXT: v_cvt_f32_f16_e32 v44, v19 +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v12 +; SI-NEXT: v_cvt_f32_f16_e32 v19, v19 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v15 +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v11 +; SI-NEXT: v_cvt_f32_f16_e32 v19, v19 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v14 +; SI-NEXT: v_cvt_f32_f16_e32 v63, v39 +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v10 +; SI-NEXT: v_cvt_f32_f16_e32 v19, v19 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v13 +; SI-NEXT: v_cvt_f32_f16_e32 v22, v50 +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v9 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v12 +; SI-NEXT: v_cvt_f32_f16_e32 v19, v19 +; SI-NEXT: v_cvt_f32_f16_e32 v23, v51 +; SI-NEXT: v_cvt_f32_f16_e32 v25, v52 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v11 +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v8 +; SI-NEXT: v_cvt_f32_f16_e32 v19, v19 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v10 +; SI-NEXT: v_cvt_f32_f16_e32 v27, v53 +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v7 +; SI-NEXT: v_cvt_f32_f16_e32 v19, v19 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v9 +; SI-NEXT: v_cvt_f32_f16_e32 v29, v54 +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v6 +; SI-NEXT: v_cvt_f32_f16_e32 v19, v19 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v8 +; SI-NEXT: v_cvt_f32_f16_e32 v32, v55 +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v5 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v7 +; SI-NEXT: v_cvt_f32_f16_e32 v19, v19 +; SI-NEXT: v_cvt_f32_f16_e32 v34, v40 +; SI-NEXT: v_cvt_f32_f16_e32 v35, v41 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v6 +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v19, v19 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v36, v43 +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v19, v19 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v48, v42 +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v19, v19 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v3 +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v1 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v19, v19 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v1 +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v37 +; SI-NEXT: v_cvt_f32_f16_e32 v19, v19 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v37 +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v38 +; SI-NEXT: v_cvt_f32_f16_e32 v46, v19 +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v39 +; SI-NEXT: v_cvt_f32_f16_e32 v56, v19 +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v49 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v38 +; SI-NEXT: v_cvt_f32_f16_e32 v58, v19 +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v50 +; SI-NEXT: v_cvt_f32_f16_e32 v60, v19 +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v51 +; SI-NEXT: v_cvt_f32_f16_e32 v62, v19 +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v52 +; SI-NEXT: v_cvt_f32_f16_e32 v19, v19 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v49 ; SI-NEXT: s_cbranch_execnz .LBB45_3 ; SI-NEXT: .LBB45_2: ; %cmp.true -; SI-NEXT: v_add_f32_e64 v1, s18, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; SI-NEXT: v_add_f32_e32 v5, 1.0, v5 +; SI-NEXT: v_add_f32_e32 v24, 1.0, v41 +; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v5, v5 +; SI-NEXT: v_add_f32_e32 v12, 1.0, v12 +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v12 +; SI-NEXT: v_add_f32_e32 v11, 1.0, v11 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_f32_e64 v2, s19, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; SI-NEXT: v_add_f32_e64 v4, s20, 1.0 -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f32_f16_e32 v5, v62 +; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v11 +; SI-NEXT: v_add_f32_e32 v10, 1.0, v10 +; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v10 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v4 -; SI-NEXT: v_add_f32_e64 v24, s41, 1.0 -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill -; SI-NEXT: v_add_f32_e64 v23, s29, 1.0 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v24 -; SI-NEXT: v_add_f32_e64 v37, s10, 1.0 -; SI-NEXT: v_add_f32_e64 v45, s9, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v23 -; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v37 -; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v45 -; SI-NEXT: v_cvt_f32_f16_e32 v5, v45 -; SI-NEXT: v_cvt_f32_f16_e32 v45, v37 -; SI-NEXT: v_cvt_f32_f16_e32 v37, v23 -; SI-NEXT: v_cvt_f32_f16_e32 v23, v3 -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e64 v41, s6, 1.0 -; SI-NEXT: v_add_f32_e64 v19, s14, 1.0 -; SI-NEXT: v_add_f32_e64 v15, s12, 1.0 -; SI-NEXT: v_cvt_f32_f16_e32 v7, v41 -; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v15 -; SI-NEXT: v_cvt_f32_f16_e32 v63, v15 -; SI-NEXT: v_cvt_f32_f16_e32 v15, v19 -; SI-NEXT: v_add_f32_e64 v18, s27, 1.0 -; SI-NEXT: v_add_f32_e64 v49, s8, 1.0 -; SI-NEXT: v_add_f32_e64 v10, s23, 1.0 -; SI-NEXT: v_add_f32_e64 v14, s25, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v18 -; SI-NEXT: v_add_f32_e64 v21, s28, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v49 -; SI-NEXT: v_add_f32_e64 v53, s7, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v41 -; SI-NEXT: v_cvt_f32_f16_e32 v41, v49 -; SI-NEXT: v_cvt_f32_f16_e32 v49, v18 -; SI-NEXT: v_cvt_f32_f16_e32 v18, v1 -; SI-NEXT: v_add_f32_e64 v1, s17, 1.0 -; SI-NEXT: v_add_f32_e64 v6, s21, 1.0 -; SI-NEXT: v_add_f32_e64 v8, s22, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v10 -; SI-NEXT: v_add_f32_e64 v12, s24, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v14 -; SI-NEXT: v_add_f32_e64 v16, s26, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v21 -; SI-NEXT: v_add_f32_e64 v25, s47, 1.0 -; SI-NEXT: v_add_f32_e64 v27, s46, 1.0 -; SI-NEXT: v_add_f32_e64 v29, s45, 1.0 -; SI-NEXT: v_add_f32_e64 v28, s43, 1.0 -; SI-NEXT: v_add_f32_e64 v26, s42, 1.0 -; SI-NEXT: v_add_f32_e64 v20, s15, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v19 -; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v53 -; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v7, v53 -; SI-NEXT: v_cvt_f32_f16_e32 v19, v21 -; SI-NEXT: v_cvt_f32_f16_e32 v53, v14 -; SI-NEXT: v_cvt_f32_f16_e32 v14, v10 -; SI-NEXT: v_cvt_f32_f16_e32 v10, v2 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 -; SI-NEXT: v_cvt_f32_f16_e32 v21, v1 -; SI-NEXT: v_add_f32_e64 v1, s16, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v6 +; SI-NEXT: v_cvt_f32_f16_e32 v5, v60 +; SI-NEXT: v_add_f32_e32 v9, 1.0, v9 +; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v9 +; SI-NEXT: v_add_f32_e32 v8, 1.0, v8 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v5, v58 ; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v8 -; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v12 -; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v16 -; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v25 -; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v27 -; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v29 -; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v28 -; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v26 -; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v20 -; SI-NEXT: v_add_f32_e64 v17, s13, 1.0 -; SI-NEXT: v_add_f32_e64 v34, s11, 1.0 -; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; SI-NEXT: v_add_f32_e32 v7, 1.0, v7 +; SI-NEXT: v_add_f32_e32 v21, 1.0, v43 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v15, v20 -; SI-NEXT: v_cvt_f32_f16_e32 v20, v6 -; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v1 -; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v17 -; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v34 -; SI-NEXT: v_cvt_f32_f16_e32 v59, v34 -; SI-NEXT: v_cvt_f32_f16_e32 v57, v17 -; SI-NEXT: v_cvt_f32_f16_e32 v34, v27 -; SI-NEXT: v_cvt_f32_f16_e32 v17, v25 -; SI-NEXT: v_cvt_f32_f16_e32 v58, v47 -; SI-NEXT: v_cvt_f32_f16_e32 v25, v31 -; SI-NEXT: v_cvt_f32_f16_e32 v27, v62 -; SI-NEXT: v_cvt_f32_f16_e32 v31, v33 -; SI-NEXT: v_cvt_f32_f16_e32 v33, v36 -; SI-NEXT: v_cvt_f32_f16_e32 v36, v38 -; SI-NEXT: v_cvt_f32_f16_e32 v38, v48 -; SI-NEXT: v_cvt_f32_f16_e32 v48, v50 -; SI-NEXT: v_cvt_f32_f16_e32 v50, v52 -; SI-NEXT: v_cvt_f32_f16_e32 v52, v54 -; SI-NEXT: v_cvt_f32_f16_e32 v54, v40 -; SI-NEXT: v_cvt_f32_f16_e32 v40, v42 -; SI-NEXT: v_cvt_f32_f16_e32 v42, v44 -; SI-NEXT: v_cvt_f32_f16_e32 v44, v46 -; SI-NEXT: v_cvt_f32_f16_e32 v46, v56 -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_cvt_f32_f16_e32 v56, v3 -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload -; SI-NEXT: v_cvt_f32_f16_e32 v62, v6 -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e64 v30, s44, 1.0 -; SI-NEXT: v_add_f32_e64 v22, s40, 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v30 -; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v22 -; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill -; SI-NEXT: v_cvt_f32_f16_e32 v22, v22 -; SI-NEXT: v_cvt_f32_f16_e32 v24, v24 -; SI-NEXT: v_cvt_f32_f16_e32 v26, v26 -; SI-NEXT: v_cvt_f32_f16_e32 v28, v28 -; SI-NEXT: v_cvt_f32_f16_e32 v30, v30 +; SI-NEXT: v_cvt_f32_f16_e32 v5, v56 +; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v7 +; SI-NEXT: v_add_f32_e32 v6, 1.0, v6 +; SI-NEXT: v_add_f32_e32 v19, 1.0, v42 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v15, v29 -; SI-NEXT: v_cvt_f32_f16_e32 v16, v16 -; SI-NEXT: v_cvt_f32_f16_e32 v12, v12 -; SI-NEXT: v_cvt_f32_f16_e32 v8, v8 -; SI-NEXT: v_cvt_f32_f16_e32 v4, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v5, v46 +; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v6 +; SI-NEXT: v_add_f32_e32 v4, 1.0, v4 +; SI-NEXT: v_add_f32_e32 v28, 1.0, v40 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v5, v43 +; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v4 +; SI-NEXT: v_add_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_add_f32_e32 v3, 1.0, v3 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v5, v42 +; SI-NEXT: v_add_f32_e32 v30, 1.0, v55 +; SI-NEXT: v_add_f32_e32 v27, 1.0, v53 +; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v1 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v5, v41 +; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v3 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 -; SI-NEXT: v_cvt_f32_f16_e32 v43, v43 -; SI-NEXT: v_cvt_f32_f16_e32 v55, v55 -; SI-NEXT: v_cvt_f32_f16_e32 v51, v51 -; SI-NEXT: v_cvt_f32_f16_e32 v39, v39 -; SI-NEXT: v_cvt_f32_f16_e32 v35, v35 -; SI-NEXT: v_cvt_f32_f16_e32 v32, v32 +; SI-NEXT: v_add_f32_e32 v35, 1.0, v37 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v5, v40 +; SI-NEXT: v_add_f32_e32 v2, 1.0, v2 +; SI-NEXT: v_add_f32_e32 v29, 1.0, v54 +; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v2 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v5, v55 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v35 +; SI-NEXT: v_add_f32_e32 v34, 1.0, v38 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v5, v54 +; SI-NEXT: v_cvt_f32_f16_e32 v4, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v34 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v5, v53 +; SI-NEXT: v_add_f32_e32 v25, 1.0, v52 +; SI-NEXT: v_add_f32_e32 v23, 1.0, v51 +; SI-NEXT: v_add_f32_e32 v22, 1.0, v50 +; SI-NEXT: v_add_f32_e32 v20, 1.0, v49 +; SI-NEXT: v_add_f32_e32 v32, 1.0, v39 +; SI-NEXT: v_add_f32_e32 v13, 1.0, v13 +; SI-NEXT: v_add_f32_e32 v14, 1.0, v14 +; SI-NEXT: v_add_f32_e32 v15, 1.0, v15 +; SI-NEXT: v_add_f32_e32 v16, 1.0, v16 +; SI-NEXT: v_add_f32_e32 v17, 1.0, v17 +; SI-NEXT: v_add_f32_e32 v18, 1.0, v18 +; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v30 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v29 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v27 +; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v25 +; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v23 +; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v22 +; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v20 +; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v32 +; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v34 +; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v35 +; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v13 +; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v14 +; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v15 +; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v16 +; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v17 +; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v18 +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v28 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v24 +; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v21 +; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v19 +; SI-NEXT: v_cvt_f32_f16_e32 v18, v18 +; SI-NEXT: v_cvt_f32_f16_e32 v17, v17 +; SI-NEXT: v_cvt_f32_f16_e32 v16, v16 +; SI-NEXT: v_cvt_f32_f16_e32 v15, v15 +; SI-NEXT: v_cvt_f32_f16_e32 v14, v14 ; SI-NEXT: v_cvt_f32_f16_e32 v13, v13 +; SI-NEXT: v_cvt_f32_f16_e32 v12, v12 ; SI-NEXT: v_cvt_f32_f16_e32 v11, v11 +; SI-NEXT: v_cvt_f32_f16_e32 v10, v10 ; SI-NEXT: v_cvt_f32_f16_e32 v9, v9 +; SI-NEXT: v_cvt_f32_f16_e32 v8, v8 +; SI-NEXT: v_cvt_f32_f16_e32 v7, v7 +; SI-NEXT: v_cvt_f32_f16_e32 v6, v6 +; SI-NEXT: v_cvt_f32_f16_e32 v63, v32 +; SI-NEXT: v_cvt_f32_f16_e32 v20, v20 +; SI-NEXT: v_cvt_f32_f16_e32 v22, v22 +; SI-NEXT: v_cvt_f32_f16_e32 v23, v23 +; SI-NEXT: v_cvt_f32_f16_e32 v25, v25 +; SI-NEXT: v_cvt_f32_f16_e32 v27, v27 +; SI-NEXT: v_cvt_f32_f16_e32 v29, v29 +; SI-NEXT: v_cvt_f32_f16_e32 v32, v30 +; SI-NEXT: v_cvt_f32_f16_e32 v34, v28 +; SI-NEXT: v_cvt_f32_f16_e32 v35, v24 +; SI-NEXT: v_cvt_f32_f16_e32 v36, v21 +; SI-NEXT: v_cvt_f32_f16_e32 v48, v19 ; SI-NEXT: v_cvt_f32_f16_e32 v61, v61 -; SI-NEXT: v_cvt_f32_f16_e32 v29, v60 -; SI-NEXT: v_cvt_f32_f16_e32 v60, v2 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f32_f16_e32 v59, v59 +; SI-NEXT: v_cvt_f32_f16_e32 v57, v57 ; SI-NEXT: v_cvt_f32_f16_e32 v47, v47 +; SI-NEXT: v_cvt_f32_f16_e32 v45, v45 +; SI-NEXT: v_cvt_f32_f16_e32 v44, v44 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v5, v37 +; SI-NEXT: v_cvt_f32_f16_e32 v46, v38 +; SI-NEXT: v_cvt_f32_f16_e32 v56, v39 +; SI-NEXT: v_cvt_f32_f16_e32 v58, v49 +; SI-NEXT: v_cvt_f32_f16_e32 v60, v50 +; SI-NEXT: v_cvt_f32_f16_e32 v62, v51 +; SI-NEXT: v_cvt_f32_f16_e32 v19, v52 +; SI-NEXT: v_cvt_f32_f16_e32 v21, v33 +; SI-NEXT: v_cvt_f32_f16_e32 v24, v31 +; SI-NEXT: v_cvt_f32_f16_e32 v26, v26 +; SI-NEXT: v_cvt_f32_f16_e32 v28, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v30, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v4 +; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill ; SI-NEXT: .LBB45_3: ; %end -; SI-NEXT: v_cvt_f16_f32_e32 v2, v62 -; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 -; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; SI-NEXT: v_or_b32_e32 v1, v1, v2 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v33 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v48 +; SI-NEXT: v_add_i32_e32 v3, vcc, 12, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v60 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v21 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v31 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v36 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v47 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v18 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v30 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v35 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v3 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v10 -; SI-NEXT: v_add_i32_e32 v3, vcc, 12, v0 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v28 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v34 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v56 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v4 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v26 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v32 ; SI-NEXT: v_add_i32_e32 v3, vcc, 16, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v46 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v20 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v24 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v29 ; SI-NEXT: v_add_i32_e32 v3, vcc, 20, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v44 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v8 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v21 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v27 ; SI-NEXT: v_add_i32_e32 v3, vcc, 24, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v42 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v14 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v19 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v25 ; SI-NEXT: v_add_i32_e32 v3, vcc, 28, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v40 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v12 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v62 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v23 ; SI-NEXT: v_add_i32_e32 v3, vcc, 32, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v54 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v53 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v60 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v22 ; SI-NEXT: v_add_i32_e32 v3, vcc, 36, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v52 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v16 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v58 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v20 ; SI-NEXT: v_add_i32_e32 v3, vcc, 40, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v50 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v49 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v56 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v63 ; SI-NEXT: v_add_i32_e32 v3, vcc, 44, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v48 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v19 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v46 ; SI-NEXT: v_add_i32_e32 v3, vcc, 48, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v38 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v37 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload ; SI-NEXT: v_add_i32_e32 v3, vcc, 52, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v36 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v17 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload ; SI-NEXT: v_add_i32_e32 v3, vcc, 56, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v33 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v34 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload ; SI-NEXT: v_add_i32_e32 v3, vcc, 60, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v31 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v15 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload ; SI-NEXT: v_add_i32_e32 v3, vcc, 64, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v29 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v30 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x44, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v27 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v28 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x48, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v25 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v26 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x4c, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v23 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v24 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x50, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v61 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v22 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x54, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v9 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x58, v0 -; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v11 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x5c, v0 -; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v13 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v57 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x60, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v32 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v63 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x64, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v35 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v59 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v44 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x68, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v39 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v45 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v45 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x6c, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v51 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v41 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v47 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x70, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v55 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v7 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v57 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x74, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v43 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v6 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v59 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x78, v0 +; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v58 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v5 -; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v61 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload @@ -70581,72 +69827,103 @@ define inreg <64 x half> @bitcast_v32f32_to_v64f16_scalar(<32 x float> inreg %a, ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] ; SI-NEXT: .LBB45_4: -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr62 -; SI-NEXT: ; implicit-def: $vgpr21 -; SI-NEXT: ; implicit-def: $vgpr60 -; SI-NEXT: ; implicit-def: $vgpr18 -; SI-NEXT: ; implicit-def: $vgpr47 -; SI-NEXT: ; implicit-def: $vgpr10 -; SI-NEXT: ; implicit-def: $vgpr3 -; SI-NEXT: ; implicit-def: $vgpr4 -; SI-NEXT: ; implicit-def: $vgpr56 -; SI-NEXT: ; implicit-def: $vgpr20 -; SI-NEXT: ; implicit-def: $vgpr46 -; SI-NEXT: ; implicit-def: $vgpr8 ; SI-NEXT: ; implicit-def: $vgpr44 -; SI-NEXT: ; implicit-def: $vgpr14 -; SI-NEXT: ; implicit-def: $vgpr42 -; SI-NEXT: ; implicit-def: $vgpr12 -; SI-NEXT: ; implicit-def: $vgpr40 -; SI-NEXT: ; implicit-def: $vgpr53 -; SI-NEXT: ; implicit-def: $vgpr54 -; SI-NEXT: ; implicit-def: $vgpr16 -; SI-NEXT: ; implicit-def: $vgpr52 -; SI-NEXT: ; implicit-def: $vgpr49 -; SI-NEXT: ; implicit-def: $vgpr50 -; SI-NEXT: ; implicit-def: $vgpr19 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr45 +; SI-NEXT: ; implicit-def: $vgpr47 +; SI-NEXT: ; implicit-def: $vgpr57 +; SI-NEXT: ; implicit-def: $vgpr59 +; SI-NEXT: ; implicit-def: $vgpr61 ; SI-NEXT: ; implicit-def: $vgpr48 -; SI-NEXT: ; implicit-def: $vgpr37 -; SI-NEXT: ; implicit-def: $vgpr38 -; SI-NEXT: ; implicit-def: $vgpr17 -; SI-NEXT: ; implicit-def: $vgpr36 -; SI-NEXT: ; implicit-def: $vgpr34 ; SI-NEXT: ; implicit-def: $vgpr33 -; SI-NEXT: ; implicit-def: $vgpr15 +; SI-NEXT: ; implicit-def: $vgpr36 ; SI-NEXT: ; implicit-def: $vgpr31 +; SI-NEXT: ; implicit-def: $vgpr35 ; SI-NEXT: ; implicit-def: $vgpr30 -; SI-NEXT: ; implicit-def: $vgpr29 +; SI-NEXT: ; implicit-def: $vgpr34 ; SI-NEXT: ; implicit-def: $vgpr28 -; SI-NEXT: ; implicit-def: $vgpr27 +; SI-NEXT: ; implicit-def: $vgpr32 ; SI-NEXT: ; implicit-def: $vgpr26 -; SI-NEXT: ; implicit-def: $vgpr25 +; SI-NEXT: ; implicit-def: $vgpr29 ; SI-NEXT: ; implicit-def: $vgpr24 +; SI-NEXT: ; implicit-def: $vgpr27 +; SI-NEXT: ; implicit-def: $vgpr21 +; SI-NEXT: ; implicit-def: $vgpr25 +; SI-NEXT: ; implicit-def: $vgpr19 ; SI-NEXT: ; implicit-def: $vgpr23 +; SI-NEXT: ; implicit-def: $vgpr62 ; SI-NEXT: ; implicit-def: $vgpr22 -; SI-NEXT: ; implicit-def: $vgpr61 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr9 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr11 -; SI-NEXT: ; implicit-def: $vgpr57 -; SI-NEXT: ; implicit-def: $vgpr13 +; SI-NEXT: ; implicit-def: $vgpr60 +; SI-NEXT: ; implicit-def: $vgpr20 +; SI-NEXT: ; implicit-def: $vgpr58 ; SI-NEXT: ; implicit-def: $vgpr63 -; SI-NEXT: ; implicit-def: $vgpr32 -; SI-NEXT: ; implicit-def: $vgpr59 -; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr56 +; SI-NEXT: ; implicit-def: $vgpr46 +; SI-NEXT: ; kill: killed $vgpr45 ; SI-NEXT: ; implicit-def: $vgpr45 -; SI-NEXT: ; implicit-def: $vgpr39 -; SI-NEXT: ; implicit-def: $vgpr41 -; SI-NEXT: ; implicit-def: $vgpr51 -; SI-NEXT: ; implicit-def: $vgpr7 -; SI-NEXT: ; implicit-def: $vgpr55 -; SI-NEXT: ; implicit-def: $vgpr6 -; SI-NEXT: ; implicit-def: $vgpr43 -; SI-NEXT: ; implicit-def: $vgpr5 -; SI-NEXT: ; implicit-def: $vgpr58 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; kill: killed $vgpr47 +; SI-NEXT: ; implicit-def: $vgpr47 +; SI-NEXT: ; kill: killed $vgpr57 +; SI-NEXT: ; implicit-def: $vgpr57 +; SI-NEXT: ; kill: killed $vgpr59 +; SI-NEXT: ; implicit-def: $vgpr59 +; SI-NEXT: ; kill: killed $vgpr61 +; SI-NEXT: ; implicit-def: $vgpr61 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; kill: killed $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr44 ; SI-NEXT: s_branch .LBB45_2 ; ; VI-LABEL: bitcast_v32f32_to_v64f16_scalar: @@ -72767,252 +72044,80 @@ define inreg <32 x float> @bitcast_v64f16_to_v32f32_scalar(<64 x half> inreg %a, ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292 -; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288 -; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284 -; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280 -; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276 -; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272 -; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268 -; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264 -; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260 -; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256 -; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252 -; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248 -; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244 -; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240 -; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236 -; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232 -; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228 -; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224 -; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220 -; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216 -; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212 -; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208 -; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204 -; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200 -; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196 -; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192 -; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188 -; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184 -; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180 -; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176 -; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172 -; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164 -; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160 -; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156 -; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152 -; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148 -; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144 -; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140 -; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136 -; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132 -; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128 -; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124 -; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120 -; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116 -; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112 -; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108 -; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104 -; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100 -; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96 -; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92 -; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88 -; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84 -; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80 -; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76 -; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72 -; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68 -; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64 -; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60 -; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56 -; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52 -; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48 -; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44 -; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40 -; GFX11-NEXT: s_clause 0x9 ; 40-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36 -; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32 -; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28 -; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24 -; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20 -; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16 -; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12 -; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8 -; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4 -; GFX11-NEXT: scratch_store_b32 off, v185, s32 -; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12 -; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10 -; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8 -; GFX11-NEXT: v_dual_mov_b32 v182, v7 :: v_dual_mov_b32 v183, v6 -; GFX11-NEXT: v_dual_mov_b32 v170, v5 :: v_dual_mov_b32 v171, v4 -; GFX11-NEXT: v_dual_mov_b32 v172, v3 :: v_dual_mov_b32 v173, v2 -; GFX11-NEXT: v_dual_mov_b32 v174, v1 :: v_dual_mov_b32 v175, v0 -; GFX11-NEXT: v_dual_mov_b32 v184, s28 :: v_dual_mov_b32 v185, s29 +; GFX11-NEXT: v_dual_mov_b32 v31, v13 :: v_dual_mov_b32 v30, v12 +; GFX11-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 +; GFX11-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 ; GFX11-NEXT: s_mov_b32 s4, 0 ; GFX11-NEXT: s_and_b32 s5, vcc_lo, exec_lo ; GFX11-NEXT: s_cbranch_scc0 .LBB47_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: v_dual_mov_b32 v47, s0 :: v_dual_mov_b32 v52, s2 -; GFX11-NEXT: v_dual_mov_b32 v49, s1 :: v_dual_mov_b32 v56, s3 -; GFX11-NEXT: v_dual_mov_b32 v61, s16 :: v_dual_mov_b32 v74, s18 -; GFX11-NEXT: v_dual_mov_b32 v67, s17 :: v_dual_mov_b32 v82, s19 -; GFX11-NEXT: v_dual_mov_b32 v91, s20 :: v_dual_mov_b32 v112, s22 -; GFX11-NEXT: v_dual_mov_b32 v101, s21 :: v_dual_mov_b32 v124, s23 -; GFX11-NEXT: v_dual_mov_b32 v137, s24 :: v_dual_mov_b32 v14, s26 -; GFX11-NEXT: v_dual_mov_b32 v151, s25 :: v_dual_mov_b32 v30, s27 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 +; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 +; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 +; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 +; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 +; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4 ; GFX11-NEXT: s_cbranch_vccnz .LBB47_3 ; GFX11-NEXT: .LBB47_2: ; %cmp.true -; GFX11-NEXT: v_pk_add_f16 v30, 0x200, s27 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s27 op_sel_hi:[0,1] ; GFX11-NEXT: v_pk_add_f16 v14, 0x200, s26 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v176, 0x200, v176 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v177, 0x200, v177 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v178, 0x200, v178 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v179, 0x200, v179 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v180, 0x200, v180 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v181, 0x200, v181 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v182, 0x200, v182 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v183, 0x200, v183 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v170, 0x200, v170 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v171, 0x200, v171 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v172, 0x200, v172 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v173, 0x200, v173 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v174, 0x200, v174 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v175, 0x200, v175 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v185, 0x200, v185 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v184, 0x200, v184 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v151, 0x200, s25 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v137, 0x200, s24 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v124, 0x200, s23 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v112, 0x200, s22 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v101, 0x200, s21 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v91, 0x200, s20 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v82, 0x200, s19 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v74, 0x200, s18 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v67, 0x200, s17 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v61, 0x200, s16 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v56, 0x200, s3 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v52, 0x200, s2 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v49, 0x200, s1 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v47, 0x200, s0 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s25 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s24 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s23 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s22 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s21 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v31, 0x200, v31 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v30, 0x200, v30 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1] ; GFX11-NEXT: .LBB47_3: ; %end -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_dual_mov_b32 v0, v47 :: v_dual_mov_b32 v1, v49 -; GFX11-NEXT: v_dual_mov_b32 v3, v56 :: v_dual_mov_b32 v4, v61 -; GFX11-NEXT: v_dual_mov_b32 v6, v74 :: v_dual_mov_b32 v9, v101 -; GFX11-NEXT: v_dual_mov_b32 v7, v82 :: v_dual_mov_b32 v8, v91 -; GFX11-NEXT: v_dual_mov_b32 v11, v124 :: v_dual_mov_b32 v12, v137 -; GFX11-NEXT: v_dual_mov_b32 v15, v30 :: v_dual_mov_b32 v16, v184 -; GFX11-NEXT: v_dual_mov_b32 v17, v185 :: v_dual_mov_b32 v18, v175 -; GFX11-NEXT: v_dual_mov_b32 v19, v174 :: v_dual_mov_b32 v20, v173 -; GFX11-NEXT: v_dual_mov_b32 v21, v172 :: v_dual_mov_b32 v22, v171 -; GFX11-NEXT: v_dual_mov_b32 v23, v170 :: v_dual_mov_b32 v24, v183 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v185, off, s32 -; GFX11-NEXT: scratch_load_b32 v184, off, s32 offset:4 -; GFX11-NEXT: scratch_load_b32 v175, off, s32 offset:8 -; GFX11-NEXT: scratch_load_b32 v174, off, s32 offset:12 -; GFX11-NEXT: scratch_load_b32 v173, off, s32 offset:16 -; GFX11-NEXT: scratch_load_b32 v172, off, s32 offset:20 -; GFX11-NEXT: scratch_load_b32 v171, off, s32 offset:24 -; GFX11-NEXT: scratch_load_b32 v170, off, s32 offset:28 -; GFX11-NEXT: scratch_load_b32 v169, off, s32 offset:32 -; GFX11-NEXT: scratch_load_b32 v168, off, s32 offset:36 -; GFX11-NEXT: scratch_load_b32 v159, off, s32 offset:40 -; GFX11-NEXT: scratch_load_b32 v158, off, s32 offset:44 -; GFX11-NEXT: scratch_load_b32 v157, off, s32 offset:48 -; GFX11-NEXT: scratch_load_b32 v156, off, s32 offset:52 -; GFX11-NEXT: scratch_load_b32 v155, off, s32 offset:56 -; GFX11-NEXT: scratch_load_b32 v154, off, s32 offset:60 -; GFX11-NEXT: scratch_load_b32 v153, off, s32 offset:64 -; GFX11-NEXT: scratch_load_b32 v152, off, s32 offset:68 -; GFX11-NEXT: scratch_load_b32 v143, off, s32 offset:72 -; GFX11-NEXT: scratch_load_b32 v142, off, s32 offset:76 -; GFX11-NEXT: scratch_load_b32 v141, off, s32 offset:80 -; GFX11-NEXT: scratch_load_b32 v140, off, s32 offset:84 -; GFX11-NEXT: scratch_load_b32 v139, off, s32 offset:88 -; GFX11-NEXT: scratch_load_b32 v138, off, s32 offset:92 -; GFX11-NEXT: scratch_load_b32 v137, off, s32 offset:96 -; GFX11-NEXT: scratch_load_b32 v136, off, s32 offset:100 -; GFX11-NEXT: scratch_load_b32 v127, off, s32 offset:104 -; GFX11-NEXT: scratch_load_b32 v126, off, s32 offset:108 -; GFX11-NEXT: scratch_load_b32 v125, off, s32 offset:112 -; GFX11-NEXT: scratch_load_b32 v124, off, s32 offset:116 -; GFX11-NEXT: scratch_load_b32 v123, off, s32 offset:120 -; GFX11-NEXT: scratch_load_b32 v122, off, s32 offset:124 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v121, off, s32 offset:128 -; GFX11-NEXT: scratch_load_b32 v120, off, s32 offset:132 -; GFX11-NEXT: scratch_load_b32 v111, off, s32 offset:136 -; GFX11-NEXT: scratch_load_b32 v110, off, s32 offset:140 -; GFX11-NEXT: scratch_load_b32 v109, off, s32 offset:144 -; GFX11-NEXT: scratch_load_b32 v108, off, s32 offset:148 -; GFX11-NEXT: scratch_load_b32 v107, off, s32 offset:152 -; GFX11-NEXT: scratch_load_b32 v106, off, s32 offset:156 -; GFX11-NEXT: scratch_load_b32 v105, off, s32 offset:160 -; GFX11-NEXT: scratch_load_b32 v104, off, s32 offset:164 -; GFX11-NEXT: scratch_load_b32 v95, off, s32 offset:168 -; GFX11-NEXT: scratch_load_b32 v94, off, s32 offset:172 -; GFX11-NEXT: scratch_load_b32 v93, off, s32 offset:176 -; GFX11-NEXT: scratch_load_b32 v92, off, s32 offset:180 -; GFX11-NEXT: scratch_load_b32 v91, off, s32 offset:184 -; GFX11-NEXT: scratch_load_b32 v90, off, s32 offset:188 -; GFX11-NEXT: scratch_load_b32 v89, off, s32 offset:192 -; GFX11-NEXT: scratch_load_b32 v88, off, s32 offset:196 -; GFX11-NEXT: scratch_load_b32 v79, off, s32 offset:200 -; GFX11-NEXT: scratch_load_b32 v78, off, s32 offset:204 -; GFX11-NEXT: scratch_load_b32 v77, off, s32 offset:208 -; GFX11-NEXT: scratch_load_b32 v76, off, s32 offset:212 -; GFX11-NEXT: scratch_load_b32 v75, off, s32 offset:216 -; GFX11-NEXT: scratch_load_b32 v74, off, s32 offset:220 -; GFX11-NEXT: scratch_load_b32 v73, off, s32 offset:224 -; GFX11-NEXT: scratch_load_b32 v72, off, s32 offset:228 -; GFX11-NEXT: scratch_load_b32 v63, off, s32 offset:232 -; GFX11-NEXT: scratch_load_b32 v62, off, s32 offset:236 -; GFX11-NEXT: scratch_load_b32 v61, off, s32 offset:240 -; GFX11-NEXT: scratch_load_b32 v60, off, s32 offset:244 -; GFX11-NEXT: scratch_load_b32 v59, off, s32 offset:248 -; GFX11-NEXT: scratch_load_b32 v58, off, s32 offset:252 -; GFX11-NEXT: s_clause 0x9 ; 40-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v57, off, s32 offset:256 -; GFX11-NEXT: scratch_load_b32 v56, off, s32 offset:260 -; GFX11-NEXT: scratch_load_b32 v47, off, s32 offset:264 -; GFX11-NEXT: scratch_load_b32 v46, off, s32 offset:268 -; GFX11-NEXT: scratch_load_b32 v45, off, s32 offset:272 -; GFX11-NEXT: scratch_load_b32 v44, off, s32 offset:276 -; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:280 -; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:284 -; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:288 -; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:292 -; GFX11-NEXT: v_dual_mov_b32 v2, v52 :: v_dual_mov_b32 v5, v67 -; GFX11-NEXT: v_dual_mov_b32 v10, v112 :: v_dual_mov_b32 v13, v151 -; GFX11-NEXT: v_dual_mov_b32 v25, v182 :: v_dual_mov_b32 v26, v181 -; GFX11-NEXT: v_dual_mov_b32 v27, v180 :: v_dual_mov_b32 v28, v179 -; GFX11-NEXT: v_dual_mov_b32 v29, v178 :: v_dual_mov_b32 v30, v177 -; GFX11-NEXT: v_mov_b32_e32 v31, v176 -; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: .LBB47_4: -; GFX11-NEXT: ; implicit-def: $vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78 -; GFX11-NEXT: ; implicit-def: $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79 -; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-NEXT: ; implicit-def: $vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81 -; GFX11-NEXT: ; implicit-def: $vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84 -; GFX11-NEXT: ; implicit-def: $vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88 -; GFX11-NEXT: ; implicit-def: $vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93 -; GFX11-NEXT: ; implicit-def: $vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99 -; GFX11-NEXT: ; implicit-def: $vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106 -; GFX11-NEXT: ; implicit-def: $vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114 -; GFX11-NEXT: ; implicit-def: $vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123 -; GFX11-NEXT: ; implicit-def: $vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133 -; GFX11-NEXT: ; implicit-def: $vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144 -; GFX11-NEXT: ; implicit-def: $vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156 -; GFX11-NEXT: ; implicit-def: $vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169 +; GFX11-NEXT: ; implicit-def: $vgpr0 +; GFX11-NEXT: ; implicit-def: $vgpr1 +; GFX11-NEXT: ; implicit-def: $vgpr2 +; GFX11-NEXT: ; implicit-def: $vgpr3 +; GFX11-NEXT: ; implicit-def: $vgpr4 +; GFX11-NEXT: ; implicit-def: $vgpr5 +; GFX11-NEXT: ; implicit-def: $vgpr6 +; GFX11-NEXT: ; implicit-def: $vgpr7 +; GFX11-NEXT: ; implicit-def: $vgpr8 +; GFX11-NEXT: ; implicit-def: $vgpr9 +; GFX11-NEXT: ; implicit-def: $vgpr10 +; GFX11-NEXT: ; implicit-def: $vgpr11 +; GFX11-NEXT: ; implicit-def: $vgpr12 +; GFX11-NEXT: ; implicit-def: $vgpr13 +; GFX11-NEXT: ; implicit-def: $vgpr14 +; GFX11-NEXT: ; implicit-def: $vgpr15 ; GFX11-NEXT: s_branch .LBB47_2 %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -75463,23 +74568,51 @@ define inreg <32 x float> @bitcast_v64i16_to_v32f32_scalar(<64 x i16> inreg %a, ; VI-LABEL: bitcast_v64i16_to_v32f32_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 +; VI-NEXT: v_mov_b32_e32 v19, s16 ; VI-NEXT: v_readfirstlane_b32 s6, v2 +; VI-NEXT: v_mov_b32_e32 v2, s17 ; VI-NEXT: v_readfirstlane_b32 s7, v3 +; VI-NEXT: v_mov_b32_e32 v3, s18 ; VI-NEXT: v_readfirstlane_b32 s8, v4 +; VI-NEXT: v_mov_b32_e32 v4, s19 ; VI-NEXT: v_readfirstlane_b32 s9, v5 +; VI-NEXT: v_mov_b32_e32 v5, s20 ; VI-NEXT: v_readfirstlane_b32 s10, v6 +; VI-NEXT: v_mov_b32_e32 v6, s21 ; VI-NEXT: v_readfirstlane_b32 s11, v7 +; VI-NEXT: v_mov_b32_e32 v7, s22 ; VI-NEXT: v_readfirstlane_b32 s12, v8 +; VI-NEXT: v_mov_b32_e32 v8, s23 ; VI-NEXT: v_readfirstlane_b32 s13, v9 +; VI-NEXT: v_mov_b32_e32 v9, s24 ; VI-NEXT: v_readfirstlane_b32 s14, v10 +; VI-NEXT: v_mov_b32_e32 v10, s25 ; VI-NEXT: v_readfirstlane_b32 s15, v11 -; VI-NEXT: v_readfirstlane_b32 s40, v12 -; VI-NEXT: v_readfirstlane_b32 s41, v13 -; VI-NEXT: v_readfirstlane_b32 s42, v14 -; VI-NEXT: v_readfirstlane_b32 s43, v15 -; VI-NEXT: v_readfirstlane_b32 s44, v16 -; VI-NEXT: v_readfirstlane_b32 s45, v17 +; VI-NEXT: v_mov_b32_e32 v11, s26 +; VI-NEXT: v_readfirstlane_b32 s16, v12 +; VI-NEXT: v_mov_b32_e32 v12, s27 +; VI-NEXT: v_readfirstlane_b32 s17, v13 +; VI-NEXT: v_mov_b32_e32 v13, s28 +; VI-NEXT: v_readfirstlane_b32 s18, v14 +; VI-NEXT: v_mov_b32_e32 v14, s29 +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 +; VI-NEXT: v_readfirstlane_b32 s19, v15 +; VI-NEXT: v_readfirstlane_b32 s20, v16 +; VI-NEXT: v_readfirstlane_b32 s21, v17 +; VI-NEXT: v_readfirstlane_b32 s22, v19 +; VI-NEXT: v_readfirstlane_b32 s23, v2 +; VI-NEXT: v_readfirstlane_b32 s24, v3 +; VI-NEXT: v_readfirstlane_b32 s25, v4 +; VI-NEXT: v_readfirstlane_b32 s26, v5 +; VI-NEXT: v_readfirstlane_b32 s27, v6 +; VI-NEXT: v_readfirstlane_b32 s28, v7 +; VI-NEXT: v_readfirstlane_b32 s29, v8 +; VI-NEXT: v_readfirstlane_b32 s40, v9 +; VI-NEXT: v_readfirstlane_b32 s41, v10 +; VI-NEXT: v_readfirstlane_b32 s42, v11 +; VI-NEXT: v_readfirstlane_b32 s43, v12 +; VI-NEXT: v_readfirstlane_b32 s44, v13 +; VI-NEXT: v_readfirstlane_b32 s45, v14 ; VI-NEXT: v_readfirstlane_b32 s46, v0 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s47, v1 @@ -75496,8 +74629,38 @@ define inreg <32 x float> @bitcast_v64i16_to_v32f32_scalar(<64 x i16> inreg %a, ; VI-NEXT: s_and_b32 s4, s46, 0xffff0000 ; VI-NEXT: s_and_b32 s5, s5, 0xffff ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s29, 3 +; VI-NEXT: s_add_i32 s5, s45, 3 ; VI-NEXT: s_add_i32 s46, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s45, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s44, 3 +; VI-NEXT: s_add_i32 s45, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s44, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s43, 3 +; VI-NEXT: s_add_i32 s44, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s43, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s42, 3 +; VI-NEXT: s_add_i32 s43, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s42, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s41, 3 +; VI-NEXT: s_add_i32 s42, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s41, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s40, 3 +; VI-NEXT: s_add_i32 s41, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s40, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s29, 3 +; VI-NEXT: s_add_i32 s40, s4, 0x30000 ; VI-NEXT: s_and_b32 s4, s29, 0xffff0000 ; VI-NEXT: s_and_b32 s5, s5, 0xffff ; VI-NEXT: s_or_b32 s4, s4, s5 @@ -75566,38 +74729,8 @@ define inreg <32 x float> @bitcast_v64i16_to_v32f32_scalar(<64 x i16> inreg %a, ; VI-NEXT: s_and_b32 s4, s16, 0xffff0000 ; VI-NEXT: s_and_b32 s5, s5, 0xffff ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s45, 3 -; VI-NEXT: s_add_i32 s16, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s45, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s44, 3 -; VI-NEXT: s_add_i32 s45, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s44, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s43, 3 -; VI-NEXT: s_add_i32 s44, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s43, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s42, 3 -; VI-NEXT: s_add_i32 s43, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s42, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s41, 3 -; VI-NEXT: s_add_i32 s42, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s41, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s40, 3 -; VI-NEXT: s_add_i32 s41, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s40, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 ; VI-NEXT: s_add_i32 s5, s15, 3 -; VI-NEXT: s_add_i32 s40, s4, 0x30000 +; VI-NEXT: s_add_i32 s16, s4, 0x30000 ; VI-NEXT: s_and_b32 s4, s15, 0xffff0000 ; VI-NEXT: s_and_b32 s5, s5, 0xffff ; VI-NEXT: s_or_b32 s4, s4, s5 @@ -75648,20 +74781,20 @@ define inreg <32 x float> @bitcast_v64i16_to_v32f32_scalar(<64 x i16> inreg %a, ; VI-NEXT: s_or_b32 s4, s4, s5 ; VI-NEXT: s_add_i32 s6, s4, 0x30000 ; VI-NEXT: .LBB51_3: ; %end -; VI-NEXT: v_mov_b32_e32 v0, s16 -; VI-NEXT: v_mov_b32_e32 v1, s17 -; VI-NEXT: v_mov_b32_e32 v2, s18 -; VI-NEXT: v_mov_b32_e32 v3, s19 -; VI-NEXT: v_mov_b32_e32 v4, s20 -; VI-NEXT: v_mov_b32_e32 v5, s21 -; VI-NEXT: v_mov_b32_e32 v6, s22 -; VI-NEXT: v_mov_b32_e32 v7, s23 -; VI-NEXT: v_mov_b32_e32 v8, s24 -; VI-NEXT: v_mov_b32_e32 v9, s25 -; VI-NEXT: v_mov_b32_e32 v10, s26 -; VI-NEXT: v_mov_b32_e32 v11, s27 -; VI-NEXT: v_mov_b32_e32 v12, s28 -; VI-NEXT: v_mov_b32_e32 v13, s29 +; VI-NEXT: v_mov_b32_e32 v0, s22 +; VI-NEXT: v_mov_b32_e32 v1, s23 +; VI-NEXT: v_mov_b32_e32 v2, s24 +; VI-NEXT: v_mov_b32_e32 v3, s25 +; VI-NEXT: v_mov_b32_e32 v4, s26 +; VI-NEXT: v_mov_b32_e32 v5, s27 +; VI-NEXT: v_mov_b32_e32 v6, s28 +; VI-NEXT: v_mov_b32_e32 v7, s29 +; VI-NEXT: v_mov_b32_e32 v8, s40 +; VI-NEXT: v_mov_b32_e32 v9, s41 +; VI-NEXT: v_mov_b32_e32 v10, s42 +; VI-NEXT: v_mov_b32_e32 v11, s43 +; VI-NEXT: v_mov_b32_e32 v12, s44 +; VI-NEXT: v_mov_b32_e32 v13, s45 ; VI-NEXT: v_mov_b32_e32 v14, s46 ; VI-NEXT: v_mov_b32_e32 v15, s47 ; VI-NEXT: v_mov_b32_e32 v16, s6 @@ -75674,12 +74807,12 @@ define inreg <32 x float> @bitcast_v64i16_to_v32f32_scalar(<64 x i16> inreg %a, ; VI-NEXT: v_mov_b32_e32 v23, s13 ; VI-NEXT: v_mov_b32_e32 v24, s14 ; VI-NEXT: v_mov_b32_e32 v25, s15 -; VI-NEXT: v_mov_b32_e32 v26, s40 -; VI-NEXT: v_mov_b32_e32 v27, s41 -; VI-NEXT: v_mov_b32_e32 v28, s42 -; VI-NEXT: v_mov_b32_e32 v29, s43 -; VI-NEXT: v_mov_b32_e32 v30, s44 -; VI-NEXT: v_mov_b32_e32 v31, s45 +; VI-NEXT: v_mov_b32_e32 v26, s16 +; VI-NEXT: v_mov_b32_e32 v27, s17 +; VI-NEXT: v_mov_b32_e32 v28, s18 +; VI-NEXT: v_mov_b32_e32 v29, s19 +; VI-NEXT: v_mov_b32_e32 v30, s20 +; VI-NEXT: v_mov_b32_e32 v31, s21 ; VI-NEXT: s_setpc_b64 s[30:31] ; VI-NEXT: .LBB51_4: ; VI-NEXT: s_branch .LBB51_2 @@ -75767,252 +74900,80 @@ define inreg <32 x float> @bitcast_v64i16_to_v32f32_scalar(<64 x i16> inreg %a, ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292 -; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288 -; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284 -; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280 -; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276 -; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272 -; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268 -; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264 -; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260 -; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256 -; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252 -; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248 -; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244 -; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240 -; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236 -; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232 -; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228 -; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224 -; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220 -; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216 -; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212 -; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208 -; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204 -; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200 -; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196 -; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192 -; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188 -; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184 -; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180 -; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176 -; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172 -; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164 -; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160 -; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156 -; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152 -; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148 -; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144 -; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140 -; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136 -; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132 -; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128 -; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124 -; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120 -; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116 -; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112 -; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108 -; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104 -; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100 -; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96 -; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92 -; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88 -; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84 -; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80 -; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76 -; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72 -; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68 -; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64 -; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60 -; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56 -; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52 -; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48 -; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44 -; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40 -; GFX11-NEXT: s_clause 0x9 ; 40-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36 -; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32 -; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28 -; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24 -; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20 -; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16 -; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12 -; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8 -; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4 -; GFX11-NEXT: scratch_store_b32 off, v185, s32 -; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12 -; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10 -; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8 -; GFX11-NEXT: v_dual_mov_b32 v182, v7 :: v_dual_mov_b32 v183, v6 -; GFX11-NEXT: v_dual_mov_b32 v170, v5 :: v_dual_mov_b32 v171, v4 -; GFX11-NEXT: v_dual_mov_b32 v172, v3 :: v_dual_mov_b32 v173, v2 -; GFX11-NEXT: v_dual_mov_b32 v174, v1 :: v_dual_mov_b32 v175, v0 -; GFX11-NEXT: v_dual_mov_b32 v184, s28 :: v_dual_mov_b32 v185, s29 +; GFX11-NEXT: v_dual_mov_b32 v31, v13 :: v_dual_mov_b32 v30, v12 +; GFX11-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 +; GFX11-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 ; GFX11-NEXT: s_mov_b32 s4, 0 ; GFX11-NEXT: s_and_b32 s5, vcc_lo, exec_lo ; GFX11-NEXT: s_cbranch_scc0 .LBB51_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: v_dual_mov_b32 v47, s0 :: v_dual_mov_b32 v52, s2 -; GFX11-NEXT: v_dual_mov_b32 v49, s1 :: v_dual_mov_b32 v56, s3 -; GFX11-NEXT: v_dual_mov_b32 v61, s16 :: v_dual_mov_b32 v74, s18 -; GFX11-NEXT: v_dual_mov_b32 v67, s17 :: v_dual_mov_b32 v82, s19 -; GFX11-NEXT: v_dual_mov_b32 v91, s20 :: v_dual_mov_b32 v112, s22 -; GFX11-NEXT: v_dual_mov_b32 v101, s21 :: v_dual_mov_b32 v124, s23 -; GFX11-NEXT: v_dual_mov_b32 v137, s24 :: v_dual_mov_b32 v14, s26 -; GFX11-NEXT: v_dual_mov_b32 v151, s25 :: v_dual_mov_b32 v30, s27 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 +; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 +; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 +; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 +; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 +; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4 ; GFX11-NEXT: s_cbranch_vccnz .LBB51_3 ; GFX11-NEXT: .LBB51_2: ; %cmp.true -; GFX11-NEXT: v_pk_add_u16 v30, s27, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v15, s27, 3 op_sel_hi:[1,0] ; GFX11-NEXT: v_pk_add_u16 v14, s26, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v176, v176, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v177, v177, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v178, v178, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v179, v179, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v180, v180, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v181, v181, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v182, v182, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v183, v183, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v170, v170, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v171, v171, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v172, v172, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v173, v173, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v174, v174, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v175, v175, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v185, v185, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v184, v184, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v151, s25, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v137, s24, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v124, s23, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v112, s22, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v101, s21, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v91, s20, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v82, s19, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v74, s18, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v67, s17, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v61, s16, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v56, s3, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v52, s2, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v49, s1, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v47, s0, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v13, s25, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v12, s24, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v11, s23, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v10, s22, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v31, v31, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v30, v30, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0] ; GFX11-NEXT: .LBB51_3: ; %end -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_dual_mov_b32 v0, v47 :: v_dual_mov_b32 v1, v49 -; GFX11-NEXT: v_dual_mov_b32 v3, v56 :: v_dual_mov_b32 v4, v61 -; GFX11-NEXT: v_dual_mov_b32 v6, v74 :: v_dual_mov_b32 v9, v101 -; GFX11-NEXT: v_dual_mov_b32 v7, v82 :: v_dual_mov_b32 v8, v91 -; GFX11-NEXT: v_dual_mov_b32 v11, v124 :: v_dual_mov_b32 v12, v137 -; GFX11-NEXT: v_dual_mov_b32 v15, v30 :: v_dual_mov_b32 v16, v184 -; GFX11-NEXT: v_dual_mov_b32 v17, v185 :: v_dual_mov_b32 v18, v175 -; GFX11-NEXT: v_dual_mov_b32 v19, v174 :: v_dual_mov_b32 v20, v173 -; GFX11-NEXT: v_dual_mov_b32 v21, v172 :: v_dual_mov_b32 v22, v171 -; GFX11-NEXT: v_dual_mov_b32 v23, v170 :: v_dual_mov_b32 v24, v183 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v185, off, s32 -; GFX11-NEXT: scratch_load_b32 v184, off, s32 offset:4 -; GFX11-NEXT: scratch_load_b32 v175, off, s32 offset:8 -; GFX11-NEXT: scratch_load_b32 v174, off, s32 offset:12 -; GFX11-NEXT: scratch_load_b32 v173, off, s32 offset:16 -; GFX11-NEXT: scratch_load_b32 v172, off, s32 offset:20 -; GFX11-NEXT: scratch_load_b32 v171, off, s32 offset:24 -; GFX11-NEXT: scratch_load_b32 v170, off, s32 offset:28 -; GFX11-NEXT: scratch_load_b32 v169, off, s32 offset:32 -; GFX11-NEXT: scratch_load_b32 v168, off, s32 offset:36 -; GFX11-NEXT: scratch_load_b32 v159, off, s32 offset:40 -; GFX11-NEXT: scratch_load_b32 v158, off, s32 offset:44 -; GFX11-NEXT: scratch_load_b32 v157, off, s32 offset:48 -; GFX11-NEXT: scratch_load_b32 v156, off, s32 offset:52 -; GFX11-NEXT: scratch_load_b32 v155, off, s32 offset:56 -; GFX11-NEXT: scratch_load_b32 v154, off, s32 offset:60 -; GFX11-NEXT: scratch_load_b32 v153, off, s32 offset:64 -; GFX11-NEXT: scratch_load_b32 v152, off, s32 offset:68 -; GFX11-NEXT: scratch_load_b32 v143, off, s32 offset:72 -; GFX11-NEXT: scratch_load_b32 v142, off, s32 offset:76 -; GFX11-NEXT: scratch_load_b32 v141, off, s32 offset:80 -; GFX11-NEXT: scratch_load_b32 v140, off, s32 offset:84 -; GFX11-NEXT: scratch_load_b32 v139, off, s32 offset:88 -; GFX11-NEXT: scratch_load_b32 v138, off, s32 offset:92 -; GFX11-NEXT: scratch_load_b32 v137, off, s32 offset:96 -; GFX11-NEXT: scratch_load_b32 v136, off, s32 offset:100 -; GFX11-NEXT: scratch_load_b32 v127, off, s32 offset:104 -; GFX11-NEXT: scratch_load_b32 v126, off, s32 offset:108 -; GFX11-NEXT: scratch_load_b32 v125, off, s32 offset:112 -; GFX11-NEXT: scratch_load_b32 v124, off, s32 offset:116 -; GFX11-NEXT: scratch_load_b32 v123, off, s32 offset:120 -; GFX11-NEXT: scratch_load_b32 v122, off, s32 offset:124 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v121, off, s32 offset:128 -; GFX11-NEXT: scratch_load_b32 v120, off, s32 offset:132 -; GFX11-NEXT: scratch_load_b32 v111, off, s32 offset:136 -; GFX11-NEXT: scratch_load_b32 v110, off, s32 offset:140 -; GFX11-NEXT: scratch_load_b32 v109, off, s32 offset:144 -; GFX11-NEXT: scratch_load_b32 v108, off, s32 offset:148 -; GFX11-NEXT: scratch_load_b32 v107, off, s32 offset:152 -; GFX11-NEXT: scratch_load_b32 v106, off, s32 offset:156 -; GFX11-NEXT: scratch_load_b32 v105, off, s32 offset:160 -; GFX11-NEXT: scratch_load_b32 v104, off, s32 offset:164 -; GFX11-NEXT: scratch_load_b32 v95, off, s32 offset:168 -; GFX11-NEXT: scratch_load_b32 v94, off, s32 offset:172 -; GFX11-NEXT: scratch_load_b32 v93, off, s32 offset:176 -; GFX11-NEXT: scratch_load_b32 v92, off, s32 offset:180 -; GFX11-NEXT: scratch_load_b32 v91, off, s32 offset:184 -; GFX11-NEXT: scratch_load_b32 v90, off, s32 offset:188 -; GFX11-NEXT: scratch_load_b32 v89, off, s32 offset:192 -; GFX11-NEXT: scratch_load_b32 v88, off, s32 offset:196 -; GFX11-NEXT: scratch_load_b32 v79, off, s32 offset:200 -; GFX11-NEXT: scratch_load_b32 v78, off, s32 offset:204 -; GFX11-NEXT: scratch_load_b32 v77, off, s32 offset:208 -; GFX11-NEXT: scratch_load_b32 v76, off, s32 offset:212 -; GFX11-NEXT: scratch_load_b32 v75, off, s32 offset:216 -; GFX11-NEXT: scratch_load_b32 v74, off, s32 offset:220 -; GFX11-NEXT: scratch_load_b32 v73, off, s32 offset:224 -; GFX11-NEXT: scratch_load_b32 v72, off, s32 offset:228 -; GFX11-NEXT: scratch_load_b32 v63, off, s32 offset:232 -; GFX11-NEXT: scratch_load_b32 v62, off, s32 offset:236 -; GFX11-NEXT: scratch_load_b32 v61, off, s32 offset:240 -; GFX11-NEXT: scratch_load_b32 v60, off, s32 offset:244 -; GFX11-NEXT: scratch_load_b32 v59, off, s32 offset:248 -; GFX11-NEXT: scratch_load_b32 v58, off, s32 offset:252 -; GFX11-NEXT: s_clause 0x9 ; 40-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v57, off, s32 offset:256 -; GFX11-NEXT: scratch_load_b32 v56, off, s32 offset:260 -; GFX11-NEXT: scratch_load_b32 v47, off, s32 offset:264 -; GFX11-NEXT: scratch_load_b32 v46, off, s32 offset:268 -; GFX11-NEXT: scratch_load_b32 v45, off, s32 offset:272 -; GFX11-NEXT: scratch_load_b32 v44, off, s32 offset:276 -; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:280 -; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:284 -; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:288 -; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:292 -; GFX11-NEXT: v_dual_mov_b32 v2, v52 :: v_dual_mov_b32 v5, v67 -; GFX11-NEXT: v_dual_mov_b32 v10, v112 :: v_dual_mov_b32 v13, v151 -; GFX11-NEXT: v_dual_mov_b32 v25, v182 :: v_dual_mov_b32 v26, v181 -; GFX11-NEXT: v_dual_mov_b32 v27, v180 :: v_dual_mov_b32 v28, v179 -; GFX11-NEXT: v_dual_mov_b32 v29, v178 :: v_dual_mov_b32 v30, v177 -; GFX11-NEXT: v_mov_b32_e32 v31, v176 -; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: .LBB51_4: -; GFX11-NEXT: ; implicit-def: $vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78 -; GFX11-NEXT: ; implicit-def: $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79 -; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-NEXT: ; implicit-def: $vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81 -; GFX11-NEXT: ; implicit-def: $vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84 -; GFX11-NEXT: ; implicit-def: $vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88 -; GFX11-NEXT: ; implicit-def: $vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93 -; GFX11-NEXT: ; implicit-def: $vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99 -; GFX11-NEXT: ; implicit-def: $vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106 -; GFX11-NEXT: ; implicit-def: $vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114 -; GFX11-NEXT: ; implicit-def: $vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123 -; GFX11-NEXT: ; implicit-def: $vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133 -; GFX11-NEXT: ; implicit-def: $vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144 -; GFX11-NEXT: ; implicit-def: $vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156 -; GFX11-NEXT: ; implicit-def: $vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169 +; GFX11-NEXT: ; implicit-def: $vgpr0 +; GFX11-NEXT: ; implicit-def: $vgpr1 +; GFX11-NEXT: ; implicit-def: $vgpr2 +; GFX11-NEXT: ; implicit-def: $vgpr3 +; GFX11-NEXT: ; implicit-def: $vgpr4 +; GFX11-NEXT: ; implicit-def: $vgpr5 +; GFX11-NEXT: ; implicit-def: $vgpr6 +; GFX11-NEXT: ; implicit-def: $vgpr7 +; GFX11-NEXT: ; implicit-def: $vgpr8 +; GFX11-NEXT: ; implicit-def: $vgpr9 +; GFX11-NEXT: ; implicit-def: $vgpr10 +; GFX11-NEXT: ; implicit-def: $vgpr11 +; GFX11-NEXT: ; implicit-def: $vgpr12 +; GFX11-NEXT: ; implicit-def: $vgpr13 +; GFX11-NEXT: ; implicit-def: $vgpr14 +; GFX11-NEXT: ; implicit-def: $vgpr15 ; GFX11-NEXT: s_branch .LBB51_2 %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -81374,53 +80335,81 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_writelane_b32 v20, s30, 0 -; SI-NEXT: v_writelane_b32 v20, s31, 1 -; SI-NEXT: v_writelane_b32 v20, s34, 2 -; SI-NEXT: v_writelane_b32 v20, s35, 3 -; SI-NEXT: v_writelane_b32 v20, s36, 4 -; SI-NEXT: v_writelane_b32 v20, s37, 5 -; SI-NEXT: v_writelane_b32 v20, s38, 6 -; SI-NEXT: v_writelane_b32 v20, s39, 7 -; SI-NEXT: v_writelane_b32 v20, s48, 8 -; SI-NEXT: v_writelane_b32 v20, s49, 9 -; SI-NEXT: v_writelane_b32 v20, s50, 10 -; SI-NEXT: v_writelane_b32 v20, s51, 11 -; SI-NEXT: v_writelane_b32 v20, s52, 12 -; SI-NEXT: v_writelane_b32 v20, s53, 13 -; SI-NEXT: v_writelane_b32 v20, s54, 14 -; SI-NEXT: v_writelane_b32 v20, s55, 15 -; SI-NEXT: v_writelane_b32 v20, s64, 16 -; SI-NEXT: v_writelane_b32 v20, s65, 17 -; SI-NEXT: v_writelane_b32 v20, s66, 18 -; SI-NEXT: v_writelane_b32 v20, s67, 19 -; SI-NEXT: v_writelane_b32 v20, s68, 20 -; SI-NEXT: v_writelane_b32 v20, s69, 21 -; SI-NEXT: v_writelane_b32 v20, s70, 22 -; SI-NEXT: v_writelane_b32 v20, s71, 23 -; SI-NEXT: v_writelane_b32 v20, s80, 24 -; SI-NEXT: v_writelane_b32 v20, s81, 25 -; SI-NEXT: v_writelane_b32 v20, s82, 26 -; SI-NEXT: v_writelane_b32 v20, s83, 27 -; SI-NEXT: v_writelane_b32 v20, s84, 28 -; SI-NEXT: v_writelane_b32 v20, s85, 29 -; SI-NEXT: v_writelane_b32 v20, s86, 30 -; SI-NEXT: v_writelane_b32 v20, s87, 31 -; SI-NEXT: v_writelane_b32 v20, s96, 32 -; SI-NEXT: v_writelane_b32 v20, s97, 33 +; SI-NEXT: v_writelane_b32 v21, s30, 0 +; SI-NEXT: v_writelane_b32 v21, s31, 1 +; SI-NEXT: v_writelane_b32 v21, s34, 2 +; SI-NEXT: v_writelane_b32 v21, s35, 3 +; SI-NEXT: v_writelane_b32 v21, s36, 4 +; SI-NEXT: v_writelane_b32 v21, s37, 5 +; SI-NEXT: v_writelane_b32 v21, s38, 6 +; SI-NEXT: v_writelane_b32 v21, s39, 7 +; SI-NEXT: v_writelane_b32 v21, s48, 8 +; SI-NEXT: v_writelane_b32 v21, s49, 9 +; SI-NEXT: v_writelane_b32 v21, s50, 10 +; SI-NEXT: v_writelane_b32 v21, s51, 11 +; SI-NEXT: v_writelane_b32 v21, s52, 12 +; SI-NEXT: v_writelane_b32 v21, s53, 13 +; SI-NEXT: v_writelane_b32 v21, s54, 14 +; SI-NEXT: v_writelane_b32 v21, s55, 15 +; SI-NEXT: v_writelane_b32 v21, s64, 16 +; SI-NEXT: v_writelane_b32 v21, s65, 17 +; SI-NEXT: v_writelane_b32 v21, s66, 18 +; SI-NEXT: v_writelane_b32 v21, s67, 19 +; SI-NEXT: v_writelane_b32 v21, s68, 20 +; SI-NEXT: v_mov_b32_e32 v20, s16 +; SI-NEXT: v_writelane_b32 v21, s69, 21 +; SI-NEXT: v_readfirstlane_b32 s56, v20 +; SI-NEXT: v_mov_b32_e32 v20, s17 +; SI-NEXT: v_writelane_b32 v21, s70, 22 +; SI-NEXT: v_readfirstlane_b32 s57, v20 +; SI-NEXT: v_mov_b32_e32 v20, s18 +; SI-NEXT: v_writelane_b32 v21, s71, 23 +; SI-NEXT: v_readfirstlane_b32 s46, v20 +; SI-NEXT: v_mov_b32_e32 v20, s19 +; SI-NEXT: v_writelane_b32 v21, s80, 24 +; SI-NEXT: v_readfirstlane_b32 s47, v20 +; SI-NEXT: v_mov_b32_e32 v20, s20 +; SI-NEXT: v_writelane_b32 v21, s81, 25 +; SI-NEXT: v_readfirstlane_b32 s44, v20 +; SI-NEXT: v_mov_b32_e32 v20, s21 +; SI-NEXT: v_writelane_b32 v21, s82, 26 +; SI-NEXT: v_readfirstlane_b32 s45, v20 +; SI-NEXT: v_mov_b32_e32 v20, s22 +; SI-NEXT: v_writelane_b32 v21, s83, 27 +; SI-NEXT: v_readfirstlane_b32 s42, v20 +; SI-NEXT: v_mov_b32_e32 v20, s23 +; SI-NEXT: v_writelane_b32 v21, s84, 28 +; SI-NEXT: v_readfirstlane_b32 s43, v20 +; SI-NEXT: v_mov_b32_e32 v20, s24 +; SI-NEXT: v_writelane_b32 v21, s85, 29 +; SI-NEXT: v_readfirstlane_b32 s40, v20 +; SI-NEXT: v_mov_b32_e32 v20, s25 +; SI-NEXT: v_writelane_b32 v21, s86, 30 +; SI-NEXT: v_readfirstlane_b32 s41, v20 +; SI-NEXT: v_mov_b32_e32 v20, s26 +; SI-NEXT: v_writelane_b32 v21, s87, 31 +; SI-NEXT: v_readfirstlane_b32 s24, v20 +; SI-NEXT: v_mov_b32_e32 v20, s27 +; SI-NEXT: v_writelane_b32 v21, s96, 32 +; SI-NEXT: v_readfirstlane_b32 s25, v20 +; SI-NEXT: v_mov_b32_e32 v20, s28 +; SI-NEXT: v_writelane_b32 v21, s97, 33 +; SI-NEXT: v_readfirstlane_b32 s22, v20 +; SI-NEXT: v_mov_b32_e32 v20, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_writelane_b32 v20, s98, 34 -; SI-NEXT: v_readfirstlane_b32 s44, v1 -; SI-NEXT: v_readfirstlane_b32 s45, v2 -; SI-NEXT: v_readfirstlane_b32 s42, v3 -; SI-NEXT: v_readfirstlane_b32 s43, v4 -; SI-NEXT: v_readfirstlane_b32 s40, v5 -; SI-NEXT: v_readfirstlane_b32 s41, v6 +; SI-NEXT: v_writelane_b32 v21, s98, 34 +; SI-NEXT: v_readfirstlane_b32 s23, v20 +; SI-NEXT: v_readfirstlane_b32 s20, v1 +; SI-NEXT: v_readfirstlane_b32 s21, v2 +; SI-NEXT: v_readfirstlane_b32 s18, v3 +; SI-NEXT: v_readfirstlane_b32 s19, v4 +; SI-NEXT: v_readfirstlane_b32 s16, v5 +; SI-NEXT: v_readfirstlane_b32 s17, v6 ; SI-NEXT: v_readfirstlane_b32 s14, v7 ; SI-NEXT: v_readfirstlane_b32 s15, v8 ; SI-NEXT: v_readfirstlane_b32 s12, v9 @@ -81432,192 +80421,192 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s6, v15 ; SI-NEXT: v_readfirstlane_b32 s7, v16 ; SI-NEXT: v_readfirstlane_b32 s4, v17 -; SI-NEXT: s_and_b64 s[46:47], vcc, exec +; SI-NEXT: s_and_b64 s[26:27], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v18 -; SI-NEXT: v_writelane_b32 v20, s99, 35 +; SI-NEXT: v_writelane_b32 v21, s99, 35 +; SI-NEXT: ; implicit-def: $vgpr23 : SGPR spill to VGPR lane ; SI-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane -; SI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane ; SI-NEXT: s_cbranch_scc0 .LBB57_4 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: s_lshr_b32 s46, s5, 24 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v22, s46, 40 -; SI-NEXT: s_lshr_b32 s46, s5, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 41 -; SI-NEXT: s_lshr_b32 s46, s5, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 42 -; SI-NEXT: s_lshr_b32 s46, s7, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 43 -; SI-NEXT: s_lshr_b32 s46, s7, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 44 -; SI-NEXT: s_lshr_b32 s46, s7, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 45 -; SI-NEXT: s_lshr_b32 s46, s9, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 46 -; SI-NEXT: s_lshr_b32 s46, s9, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 47 -; SI-NEXT: s_lshr_b32 s46, s9, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 48 -; SI-NEXT: s_lshr_b32 s46, s11, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 49 -; SI-NEXT: s_lshr_b32 s46, s11, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 50 -; SI-NEXT: s_lshr_b32 s46, s11, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 51 -; SI-NEXT: s_lshr_b32 s46, s13, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 52 -; SI-NEXT: s_lshr_b32 s46, s13, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 53 -; SI-NEXT: s_lshr_b32 s46, s13, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 54 -; SI-NEXT: s_lshr_b32 s46, s15, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 55 -; SI-NEXT: s_lshr_b32 s46, s15, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 56 -; SI-NEXT: s_lshr_b32 s46, s15, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 57 -; SI-NEXT: s_lshr_b32 s46, s41, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 58 -; SI-NEXT: s_lshr_b32 s46, s41, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 59 -; SI-NEXT: s_lshr_b32 s46, s41, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 60 -; SI-NEXT: s_lshr_b32 s46, s43, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 61 -; SI-NEXT: s_lshr_b32 s46, s43, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 62 -; SI-NEXT: s_lshr_b32 s46, s43, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 63 -; SI-NEXT: s_lshr_b32 s46, s45, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 0 -; SI-NEXT: s_lshr_b32 s46, s45, 16 -; SI-NEXT: v_writelane_b32 v21, s46, 1 -; SI-NEXT: s_lshr_b32 s46, s45, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 2 -; SI-NEXT: s_lshr_b32 s46, s29, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 3 -; SI-NEXT: s_lshr_b32 s46, s29, 16 -; SI-NEXT: v_writelane_b32 v21, s46, 4 -; SI-NEXT: s_lshr_b32 s46, s29, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 5 -; SI-NEXT: s_lshr_b32 s46, s27, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 6 -; SI-NEXT: s_lshr_b32 s46, s27, 16 -; SI-NEXT: v_writelane_b32 v21, s46, 7 -; SI-NEXT: s_lshr_b32 s46, s27, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 8 -; SI-NEXT: s_lshr_b32 s46, s25, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 9 -; SI-NEXT: s_lshr_b32 s46, s25, 16 -; SI-NEXT: v_writelane_b32 v21, s46, 10 -; SI-NEXT: s_lshr_b32 s46, s25, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 11 -; SI-NEXT: s_lshr_b32 s46, s23, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 12 -; SI-NEXT: s_lshr_b32 s46, s23, 16 -; SI-NEXT: v_writelane_b32 v21, s46, 13 -; SI-NEXT: s_lshr_b32 s46, s23, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 14 -; SI-NEXT: s_lshr_b32 s46, s21, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 15 -; SI-NEXT: s_lshr_b32 s46, s21, 16 -; SI-NEXT: v_writelane_b32 v21, s46, 16 -; SI-NEXT: s_lshr_b32 s46, s21, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 17 -; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 38 -; SI-NEXT: v_writelane_b32 v22, s47, 39 -; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 36 -; SI-NEXT: v_writelane_b32 v22, s47, 37 -; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 34 -; SI-NEXT: v_writelane_b32 v22, s47, 35 -; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 32 -; SI-NEXT: v_writelane_b32 v22, s47, 33 -; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 30 -; SI-NEXT: v_writelane_b32 v22, s47, 31 -; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 28 -; SI-NEXT: v_writelane_b32 v22, s47, 29 -; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 26 -; SI-NEXT: v_writelane_b32 v22, s47, 27 -; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 24 -; SI-NEXT: v_writelane_b32 v22, s47, 25 -; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 22 -; SI-NEXT: v_writelane_b32 v22, s47, 23 -; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 20 -; SI-NEXT: v_writelane_b32 v22, s47, 21 -; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 18 -; SI-NEXT: v_writelane_b32 v22, s47, 19 -; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 16 -; SI-NEXT: v_writelane_b32 v22, s47, 17 -; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 14 -; SI-NEXT: v_writelane_b32 v22, s47, 15 -; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 12 -; SI-NEXT: v_writelane_b32 v22, s47, 13 -; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 10 -; SI-NEXT: v_writelane_b32 v22, s47, 11 -; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 8 -; SI-NEXT: v_writelane_b32 v22, s47, 9 -; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 6 -; SI-NEXT: v_writelane_b32 v22, s47, 7 -; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 4 -; SI-NEXT: v_writelane_b32 v22, s47, 5 -; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 2 -; SI-NEXT: v_writelane_b32 v22, s47, 3 -; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 0 -; SI-NEXT: s_lshr_b32 s49, s19, 24 -; SI-NEXT: s_lshr_b32 s48, s19, 16 -; SI-NEXT: s_lshr_b32 s50, s19, 8 -; SI-NEXT: s_lshr_b32 s51, s17, 24 -; SI-NEXT: s_lshr_b32 s52, s17, 16 -; SI-NEXT: s_lshr_b32 s53, s17, 8 +; SI-NEXT: s_lshr_b32 s26, s5, 24 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_writelane_b32 v23, s26, 40 +; SI-NEXT: s_lshr_b32 s26, s5, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 41 +; SI-NEXT: s_lshr_b32 s26, s5, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 42 +; SI-NEXT: s_lshr_b32 s26, s7, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 43 +; SI-NEXT: s_lshr_b32 s26, s7, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 44 +; SI-NEXT: s_lshr_b32 s26, s7, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 45 +; SI-NEXT: s_lshr_b32 s26, s9, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 46 +; SI-NEXT: s_lshr_b32 s26, s9, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 47 +; SI-NEXT: s_lshr_b32 s26, s9, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 48 +; SI-NEXT: s_lshr_b32 s26, s11, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 49 +; SI-NEXT: s_lshr_b32 s26, s11, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 50 +; SI-NEXT: s_lshr_b32 s26, s11, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 51 +; SI-NEXT: s_lshr_b32 s26, s13, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 52 +; SI-NEXT: s_lshr_b32 s26, s13, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 53 +; SI-NEXT: s_lshr_b32 s26, s13, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 54 +; SI-NEXT: s_lshr_b32 s26, s15, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 55 +; SI-NEXT: s_lshr_b32 s26, s15, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 56 +; SI-NEXT: s_lshr_b32 s26, s15, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 57 +; SI-NEXT: s_lshr_b32 s26, s17, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 58 +; SI-NEXT: s_lshr_b32 s26, s17, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 59 +; SI-NEXT: s_lshr_b32 s26, s17, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 60 +; SI-NEXT: s_lshr_b32 s26, s19, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 61 +; SI-NEXT: s_lshr_b32 s26, s19, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 62 +; SI-NEXT: s_lshr_b32 s26, s19, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 63 +; SI-NEXT: s_lshr_b32 s26, s21, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 0 +; SI-NEXT: s_lshr_b32 s26, s21, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 1 +; SI-NEXT: s_lshr_b32 s26, s21, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 2 +; SI-NEXT: s_lshr_b32 s26, s23, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 3 +; SI-NEXT: s_lshr_b32 s26, s23, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 4 +; SI-NEXT: s_lshr_b32 s26, s23, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 5 +; SI-NEXT: s_lshr_b32 s26, s25, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 6 +; SI-NEXT: s_lshr_b32 s26, s25, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 7 +; SI-NEXT: s_lshr_b32 s26, s25, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 8 +; SI-NEXT: s_lshr_b32 s26, s41, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 9 +; SI-NEXT: s_lshr_b32 s26, s41, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 10 +; SI-NEXT: s_lshr_b32 s26, s41, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 11 +; SI-NEXT: s_lshr_b32 s26, s43, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 12 +; SI-NEXT: s_lshr_b32 s26, s43, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 13 +; SI-NEXT: s_lshr_b32 s26, s43, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 14 +; SI-NEXT: s_lshr_b32 s26, s45, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 15 +; SI-NEXT: s_lshr_b32 s26, s45, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 16 +; SI-NEXT: s_lshr_b32 s26, s45, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 17 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 38 +; SI-NEXT: v_writelane_b32 v23, s27, 39 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 36 +; SI-NEXT: v_writelane_b32 v23, s27, 37 +; SI-NEXT: s_lshr_b64 s[26:27], s[6:7], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 34 +; SI-NEXT: v_writelane_b32 v23, s27, 35 +; SI-NEXT: s_lshr_b64 s[26:27], s[6:7], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 32 +; SI-NEXT: v_writelane_b32 v23, s27, 33 +; SI-NEXT: s_lshr_b64 s[26:27], s[6:7], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 30 +; SI-NEXT: v_writelane_b32 v23, s27, 31 +; SI-NEXT: s_lshr_b64 s[26:27], s[8:9], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 28 +; SI-NEXT: v_writelane_b32 v23, s27, 29 +; SI-NEXT: s_lshr_b64 s[26:27], s[8:9], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 26 +; SI-NEXT: v_writelane_b32 v23, s27, 27 +; SI-NEXT: s_lshr_b64 s[26:27], s[8:9], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 24 +; SI-NEXT: v_writelane_b32 v23, s27, 25 +; SI-NEXT: s_lshr_b64 s[26:27], s[10:11], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 22 +; SI-NEXT: v_writelane_b32 v23, s27, 23 +; SI-NEXT: s_lshr_b64 s[26:27], s[10:11], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 20 +; SI-NEXT: v_writelane_b32 v23, s27, 21 +; SI-NEXT: s_lshr_b64 s[26:27], s[10:11], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 18 +; SI-NEXT: v_writelane_b32 v23, s27, 19 +; SI-NEXT: s_lshr_b64 s[26:27], s[12:13], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 16 +; SI-NEXT: v_writelane_b32 v23, s27, 17 +; SI-NEXT: s_lshr_b64 s[26:27], s[12:13], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 14 +; SI-NEXT: v_writelane_b32 v23, s27, 15 +; SI-NEXT: s_lshr_b64 s[26:27], s[12:13], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 12 +; SI-NEXT: v_writelane_b32 v23, s27, 13 +; SI-NEXT: s_lshr_b64 s[26:27], s[14:15], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 10 +; SI-NEXT: v_writelane_b32 v23, s27, 11 +; SI-NEXT: s_lshr_b64 s[26:27], s[14:15], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 8 +; SI-NEXT: v_writelane_b32 v23, s27, 9 +; SI-NEXT: s_lshr_b64 s[26:27], s[14:15], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 6 +; SI-NEXT: v_writelane_b32 v23, s27, 7 +; SI-NEXT: s_lshr_b64 s[26:27], s[16:17], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 4 +; SI-NEXT: v_writelane_b32 v23, s27, 5 +; SI-NEXT: s_lshr_b64 s[26:27], s[16:17], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 2 +; SI-NEXT: v_writelane_b32 v23, s27, 3 +; SI-NEXT: s_lshr_b64 s[26:27], s[16:17], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 0 +; SI-NEXT: s_lshr_b32 s49, s47, 24 +; SI-NEXT: s_lshr_b32 s48, s47, 16 +; SI-NEXT: s_lshr_b32 s50, s47, 8 +; SI-NEXT: s_lshr_b32 s51, s57, 24 +; SI-NEXT: s_lshr_b32 s52, s57, 16 +; SI-NEXT: s_lshr_b32 s53, s57, 8 ; SI-NEXT: s_lshr_b64 s[54:55], s[4:5], 16 -; SI-NEXT: v_writelane_b32 v22, s47, 1 -; SI-NEXT: s_lshr_b64 s[64:65], s[42:43], 24 -; SI-NEXT: s_lshr_b64 s[66:67], s[42:43], 16 -; SI-NEXT: s_lshr_b64 s[68:69], s[42:43], 8 -; SI-NEXT: s_lshr_b64 s[70:71], s[44:45], 24 -; SI-NEXT: s_lshr_b64 s[80:81], s[44:45], 16 -; SI-NEXT: s_lshr_b64 s[82:83], s[44:45], 8 -; SI-NEXT: s_lshr_b64 s[84:85], s[28:29], 24 -; SI-NEXT: s_lshr_b64 s[86:87], s[28:29], 16 -; SI-NEXT: s_lshr_b64 s[96:97], s[28:29], 8 -; SI-NEXT: s_lshr_b64 s[98:99], s[26:27], 24 -; SI-NEXT: s_lshr_b64 s[46:47], s[26:27], 16 -; SI-NEXT: s_lshr_b64 s[56:57], s[26:27], 8 -; SI-NEXT: s_lshr_b64 s[58:59], s[24:25], 24 -; SI-NEXT: s_lshr_b64 s[60:61], s[24:25], 16 -; SI-NEXT: s_lshr_b64 s[62:63], s[24:25], 8 -; SI-NEXT: s_lshr_b64 s[72:73], s[22:23], 24 -; SI-NEXT: s_lshr_b64 s[74:75], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[76:77], s[22:23], 8 -; SI-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 -; SI-NEXT: s_lshr_b64 s[88:89], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[90:91], s[20:21], 8 -; SI-NEXT: s_lshr_b64 s[92:93], s[18:19], 24 -; SI-NEXT: s_lshr_b64 s[94:95], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[30:31], s[18:19], 8 -; SI-NEXT: s_lshr_b64 s[34:35], s[16:17], 24 -; SI-NEXT: s_lshr_b64 s[36:37], s[16:17], 16 -; SI-NEXT: s_lshr_b64 s[38:39], s[16:17], 8 +; SI-NEXT: v_writelane_b32 v23, s27, 1 +; SI-NEXT: s_lshr_b64 s[64:65], s[18:19], 24 +; SI-NEXT: s_lshr_b64 s[66:67], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[68:69], s[18:19], 8 +; SI-NEXT: s_lshr_b64 s[70:71], s[20:21], 24 +; SI-NEXT: s_lshr_b64 s[80:81], s[20:21], 16 +; SI-NEXT: s_lshr_b64 s[82:83], s[20:21], 8 +; SI-NEXT: s_lshr_b64 s[84:85], s[22:23], 24 +; SI-NEXT: s_lshr_b64 s[86:87], s[22:23], 16 +; SI-NEXT: s_lshr_b64 s[96:97], s[22:23], 8 +; SI-NEXT: s_lshr_b64 s[98:99], s[24:25], 24 +; SI-NEXT: s_lshr_b64 s[26:27], s[24:25], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[24:25], 8 +; SI-NEXT: s_lshr_b64 s[58:59], s[40:41], 24 +; SI-NEXT: s_lshr_b64 s[60:61], s[40:41], 16 +; SI-NEXT: s_lshr_b64 s[62:63], s[40:41], 8 +; SI-NEXT: s_lshr_b64 s[72:73], s[42:43], 24 +; SI-NEXT: s_lshr_b64 s[74:75], s[42:43], 16 +; SI-NEXT: s_lshr_b64 s[76:77], s[42:43], 8 +; SI-NEXT: s_lshr_b64 s[78:79], s[44:45], 24 +; SI-NEXT: s_lshr_b64 s[88:89], s[44:45], 16 +; SI-NEXT: s_lshr_b64 s[90:91], s[44:45], 8 +; SI-NEXT: s_lshr_b64 s[92:93], s[46:47], 24 +; SI-NEXT: s_lshr_b64 s[94:95], s[46:47], 16 +; SI-NEXT: s_lshr_b64 s[30:31], s[46:47], 8 +; SI-NEXT: s_lshr_b64 s[34:35], s[56:57], 24 +; SI-NEXT: s_lshr_b64 s[36:37], s[56:57], 16 +; SI-NEXT: s_lshr_b64 s[38:39], s[56:57], 8 ; SI-NEXT: s_cbranch_execnz .LBB57_3 ; SI-NEXT: .LBB57_2: ; %cmp.true ; SI-NEXT: s_add_u32 s4, s4, 3 @@ -81632,466 +80621,466 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: s_addc_u32 s13, s13, 0 ; SI-NEXT: s_add_u32 s14, s14, 3 ; SI-NEXT: s_addc_u32 s15, s15, 0 +; SI-NEXT: s_add_u32 s16, s16, 3 +; SI-NEXT: s_addc_u32 s17, s17, 0 +; SI-NEXT: s_add_u32 s18, s18, 3 +; SI-NEXT: s_addc_u32 s19, s19, 0 +; SI-NEXT: s_add_u32 s20, s20, 3 +; SI-NEXT: s_addc_u32 s21, s21, 0 +; SI-NEXT: s_add_u32 s22, s22, 3 +; SI-NEXT: s_addc_u32 s23, s23, 0 +; SI-NEXT: s_add_u32 s24, s24, 3 +; SI-NEXT: s_addc_u32 s25, s25, 0 ; SI-NEXT: s_add_u32 s40, s40, 3 ; SI-NEXT: s_addc_u32 s41, s41, 0 ; SI-NEXT: s_add_u32 s42, s42, 3 ; SI-NEXT: s_addc_u32 s43, s43, 0 ; SI-NEXT: s_add_u32 s44, s44, 3 ; SI-NEXT: s_addc_u32 s45, s45, 0 -; SI-NEXT: s_add_u32 s28, s28, 3 -; SI-NEXT: s_addc_u32 s29, s29, 0 -; SI-NEXT: s_add_u32 s26, s26, 3 -; SI-NEXT: s_addc_u32 s27, s27, 0 -; SI-NEXT: s_add_u32 s24, s24, 3 -; SI-NEXT: s_addc_u32 s25, s25, 0 -; SI-NEXT: s_add_u32 s22, s22, 3 -; SI-NEXT: s_addc_u32 s23, s23, 0 -; SI-NEXT: s_add_u32 s20, s20, 3 -; SI-NEXT: s_addc_u32 s21, s21, 0 -; SI-NEXT: s_add_u32 s18, s18, 3 -; SI-NEXT: s_addc_u32 s19, s19, 0 -; SI-NEXT: s_add_u32 s16, s16, 3 -; SI-NEXT: s_addc_u32 s17, s17, 0 -; SI-NEXT: s_lshr_b32 s46, s5, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 40 -; SI-NEXT: s_lshr_b32 s46, s5, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 41 -; SI-NEXT: s_lshr_b32 s46, s5, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 42 -; SI-NEXT: s_lshr_b32 s46, s7, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 43 -; SI-NEXT: s_lshr_b32 s46, s7, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 44 -; SI-NEXT: s_lshr_b32 s46, s7, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 45 -; SI-NEXT: s_lshr_b32 s46, s9, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 46 -; SI-NEXT: s_lshr_b32 s46, s9, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 47 -; SI-NEXT: s_lshr_b32 s46, s9, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 48 -; SI-NEXT: s_lshr_b32 s46, s11, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 49 -; SI-NEXT: s_lshr_b32 s46, s11, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 50 -; SI-NEXT: s_lshr_b32 s46, s11, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 51 -; SI-NEXT: s_lshr_b32 s46, s13, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 52 -; SI-NEXT: s_lshr_b32 s46, s13, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 53 -; SI-NEXT: s_lshr_b32 s46, s13, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 54 -; SI-NEXT: s_lshr_b32 s46, s15, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 55 -; SI-NEXT: s_lshr_b32 s46, s15, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 56 -; SI-NEXT: s_lshr_b32 s46, s15, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 57 -; SI-NEXT: s_lshr_b32 s46, s41, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 58 -; SI-NEXT: s_lshr_b32 s46, s41, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 59 -; SI-NEXT: s_lshr_b32 s46, s41, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 60 -; SI-NEXT: s_lshr_b32 s46, s43, 24 -; SI-NEXT: v_writelane_b32 v22, s46, 61 -; SI-NEXT: s_lshr_b32 s46, s43, 16 -; SI-NEXT: v_writelane_b32 v22, s46, 62 -; SI-NEXT: s_lshr_b32 s46, s43, 8 -; SI-NEXT: v_writelane_b32 v22, s46, 63 -; SI-NEXT: s_lshr_b32 s46, s45, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 0 -; SI-NEXT: s_lshr_b32 s46, s45, 16 -; SI-NEXT: v_writelane_b32 v21, s46, 1 -; SI-NEXT: s_lshr_b32 s46, s45, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 2 -; SI-NEXT: s_lshr_b32 s46, s29, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 3 -; SI-NEXT: s_lshr_b32 s46, s29, 16 -; SI-NEXT: v_writelane_b32 v21, s46, 4 -; SI-NEXT: s_lshr_b32 s46, s29, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 5 -; SI-NEXT: s_lshr_b32 s46, s27, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 6 -; SI-NEXT: s_lshr_b32 s46, s27, 16 -; SI-NEXT: v_writelane_b32 v21, s46, 7 -; SI-NEXT: s_lshr_b32 s46, s27, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 8 -; SI-NEXT: s_lshr_b32 s46, s25, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 9 -; SI-NEXT: s_lshr_b32 s46, s25, 16 -; SI-NEXT: v_writelane_b32 v21, s46, 10 -; SI-NEXT: s_lshr_b32 s46, s25, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 11 -; SI-NEXT: s_lshr_b32 s46, s23, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 12 -; SI-NEXT: s_lshr_b32 s46, s23, 16 -; SI-NEXT: v_writelane_b32 v21, s46, 13 -; SI-NEXT: s_lshr_b32 s46, s23, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 14 -; SI-NEXT: s_lshr_b32 s46, s21, 24 -; SI-NEXT: v_writelane_b32 v21, s46, 15 -; SI-NEXT: s_lshr_b32 s46, s21, 16 -; SI-NEXT: v_writelane_b32 v21, s46, 16 -; SI-NEXT: s_lshr_b32 s46, s21, 8 -; SI-NEXT: v_writelane_b32 v21, s46, 17 -; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 38 -; SI-NEXT: v_writelane_b32 v22, s47, 39 -; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 36 -; SI-NEXT: v_writelane_b32 v22, s47, 37 -; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 34 -; SI-NEXT: v_writelane_b32 v22, s47, 35 -; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 32 -; SI-NEXT: v_writelane_b32 v22, s47, 33 -; SI-NEXT: s_lshr_b64 s[46:47], s[6:7], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 30 -; SI-NEXT: v_writelane_b32 v22, s47, 31 -; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 28 -; SI-NEXT: v_writelane_b32 v22, s47, 29 -; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 26 -; SI-NEXT: v_writelane_b32 v22, s47, 27 -; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 24 -; SI-NEXT: v_writelane_b32 v22, s47, 25 -; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 22 -; SI-NEXT: v_writelane_b32 v22, s47, 23 -; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 20 -; SI-NEXT: v_writelane_b32 v22, s47, 21 -; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 18 -; SI-NEXT: v_writelane_b32 v22, s47, 19 -; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 16 -; SI-NEXT: v_writelane_b32 v22, s47, 17 -; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 14 -; SI-NEXT: v_writelane_b32 v22, s47, 15 -; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 12 -; SI-NEXT: v_writelane_b32 v22, s47, 13 -; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 10 -; SI-NEXT: v_writelane_b32 v22, s47, 11 -; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 8 -; SI-NEXT: v_writelane_b32 v22, s47, 9 -; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 6 -; SI-NEXT: v_writelane_b32 v22, s47, 7 -; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 24 -; SI-NEXT: v_writelane_b32 v22, s46, 4 -; SI-NEXT: v_writelane_b32 v22, s47, 5 -; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 16 -; SI-NEXT: v_writelane_b32 v22, s46, 2 -; SI-NEXT: v_writelane_b32 v22, s47, 3 -; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 8 -; SI-NEXT: v_writelane_b32 v22, s46, 0 -; SI-NEXT: s_lshr_b32 s49, s19, 24 -; SI-NEXT: s_lshr_b32 s48, s19, 16 -; SI-NEXT: s_lshr_b32 s50, s19, 8 -; SI-NEXT: s_lshr_b32 s51, s17, 24 -; SI-NEXT: s_lshr_b32 s52, s17, 16 -; SI-NEXT: s_lshr_b32 s53, s17, 8 +; SI-NEXT: s_add_u32 s46, s46, 3 +; SI-NEXT: s_addc_u32 s47, s47, 0 +; SI-NEXT: s_add_u32 s56, s56, 3 +; SI-NEXT: s_addc_u32 s57, s57, 0 +; SI-NEXT: s_lshr_b32 s26, s5, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 40 +; SI-NEXT: s_lshr_b32 s26, s5, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 41 +; SI-NEXT: s_lshr_b32 s26, s5, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 42 +; SI-NEXT: s_lshr_b32 s26, s7, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 43 +; SI-NEXT: s_lshr_b32 s26, s7, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 44 +; SI-NEXT: s_lshr_b32 s26, s7, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 45 +; SI-NEXT: s_lshr_b32 s26, s9, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 46 +; SI-NEXT: s_lshr_b32 s26, s9, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 47 +; SI-NEXT: s_lshr_b32 s26, s9, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 48 +; SI-NEXT: s_lshr_b32 s26, s11, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 49 +; SI-NEXT: s_lshr_b32 s26, s11, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 50 +; SI-NEXT: s_lshr_b32 s26, s11, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 51 +; SI-NEXT: s_lshr_b32 s26, s13, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 52 +; SI-NEXT: s_lshr_b32 s26, s13, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 53 +; SI-NEXT: s_lshr_b32 s26, s13, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 54 +; SI-NEXT: s_lshr_b32 s26, s15, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 55 +; SI-NEXT: s_lshr_b32 s26, s15, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 56 +; SI-NEXT: s_lshr_b32 s26, s15, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 57 +; SI-NEXT: s_lshr_b32 s26, s17, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 58 +; SI-NEXT: s_lshr_b32 s26, s17, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 59 +; SI-NEXT: s_lshr_b32 s26, s17, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 60 +; SI-NEXT: s_lshr_b32 s26, s19, 24 +; SI-NEXT: v_writelane_b32 v23, s26, 61 +; SI-NEXT: s_lshr_b32 s26, s19, 16 +; SI-NEXT: v_writelane_b32 v23, s26, 62 +; SI-NEXT: s_lshr_b32 s26, s19, 8 +; SI-NEXT: v_writelane_b32 v23, s26, 63 +; SI-NEXT: s_lshr_b32 s26, s21, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 0 +; SI-NEXT: s_lshr_b32 s26, s21, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 1 +; SI-NEXT: s_lshr_b32 s26, s21, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 2 +; SI-NEXT: s_lshr_b32 s26, s23, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 3 +; SI-NEXT: s_lshr_b32 s26, s23, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 4 +; SI-NEXT: s_lshr_b32 s26, s23, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 5 +; SI-NEXT: s_lshr_b32 s26, s25, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 6 +; SI-NEXT: s_lshr_b32 s26, s25, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 7 +; SI-NEXT: s_lshr_b32 s26, s25, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 8 +; SI-NEXT: s_lshr_b32 s26, s41, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 9 +; SI-NEXT: s_lshr_b32 s26, s41, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 10 +; SI-NEXT: s_lshr_b32 s26, s41, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 11 +; SI-NEXT: s_lshr_b32 s26, s43, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 12 +; SI-NEXT: s_lshr_b32 s26, s43, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 13 +; SI-NEXT: s_lshr_b32 s26, s43, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 14 +; SI-NEXT: s_lshr_b32 s26, s45, 24 +; SI-NEXT: v_writelane_b32 v22, s26, 15 +; SI-NEXT: s_lshr_b32 s26, s45, 16 +; SI-NEXT: v_writelane_b32 v22, s26, 16 +; SI-NEXT: s_lshr_b32 s26, s45, 8 +; SI-NEXT: v_writelane_b32 v22, s26, 17 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 38 +; SI-NEXT: v_writelane_b32 v23, s27, 39 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 36 +; SI-NEXT: v_writelane_b32 v23, s27, 37 +; SI-NEXT: s_lshr_b64 s[26:27], s[6:7], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 34 +; SI-NEXT: v_writelane_b32 v23, s27, 35 +; SI-NEXT: s_lshr_b64 s[26:27], s[6:7], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 32 +; SI-NEXT: v_writelane_b32 v23, s27, 33 +; SI-NEXT: s_lshr_b64 s[26:27], s[6:7], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 30 +; SI-NEXT: v_writelane_b32 v23, s27, 31 +; SI-NEXT: s_lshr_b64 s[26:27], s[8:9], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 28 +; SI-NEXT: v_writelane_b32 v23, s27, 29 +; SI-NEXT: s_lshr_b64 s[26:27], s[8:9], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 26 +; SI-NEXT: v_writelane_b32 v23, s27, 27 +; SI-NEXT: s_lshr_b64 s[26:27], s[8:9], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 24 +; SI-NEXT: v_writelane_b32 v23, s27, 25 +; SI-NEXT: s_lshr_b64 s[26:27], s[10:11], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 22 +; SI-NEXT: v_writelane_b32 v23, s27, 23 +; SI-NEXT: s_lshr_b64 s[26:27], s[10:11], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 20 +; SI-NEXT: v_writelane_b32 v23, s27, 21 +; SI-NEXT: s_lshr_b64 s[26:27], s[10:11], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 18 +; SI-NEXT: v_writelane_b32 v23, s27, 19 +; SI-NEXT: s_lshr_b64 s[26:27], s[12:13], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 16 +; SI-NEXT: v_writelane_b32 v23, s27, 17 +; SI-NEXT: s_lshr_b64 s[26:27], s[12:13], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 14 +; SI-NEXT: v_writelane_b32 v23, s27, 15 +; SI-NEXT: s_lshr_b64 s[26:27], s[12:13], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 12 +; SI-NEXT: v_writelane_b32 v23, s27, 13 +; SI-NEXT: s_lshr_b64 s[26:27], s[14:15], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 10 +; SI-NEXT: v_writelane_b32 v23, s27, 11 +; SI-NEXT: s_lshr_b64 s[26:27], s[14:15], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 8 +; SI-NEXT: v_writelane_b32 v23, s27, 9 +; SI-NEXT: s_lshr_b64 s[26:27], s[14:15], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 6 +; SI-NEXT: v_writelane_b32 v23, s27, 7 +; SI-NEXT: s_lshr_b64 s[26:27], s[16:17], 24 +; SI-NEXT: v_writelane_b32 v23, s26, 4 +; SI-NEXT: v_writelane_b32 v23, s27, 5 +; SI-NEXT: s_lshr_b64 s[26:27], s[16:17], 16 +; SI-NEXT: v_writelane_b32 v23, s26, 2 +; SI-NEXT: v_writelane_b32 v23, s27, 3 +; SI-NEXT: s_lshr_b64 s[26:27], s[16:17], 8 +; SI-NEXT: v_writelane_b32 v23, s26, 0 +; SI-NEXT: s_lshr_b32 s49, s47, 24 +; SI-NEXT: s_lshr_b32 s48, s47, 16 +; SI-NEXT: s_lshr_b32 s50, s47, 8 +; SI-NEXT: s_lshr_b32 s51, s57, 24 +; SI-NEXT: s_lshr_b32 s52, s57, 16 +; SI-NEXT: s_lshr_b32 s53, s57, 8 ; SI-NEXT: s_lshr_b64 s[54:55], s[4:5], 16 -; SI-NEXT: v_writelane_b32 v22, s47, 1 -; SI-NEXT: s_lshr_b64 s[64:65], s[42:43], 24 -; SI-NEXT: s_lshr_b64 s[66:67], s[42:43], 16 -; SI-NEXT: s_lshr_b64 s[68:69], s[42:43], 8 -; SI-NEXT: s_lshr_b64 s[70:71], s[44:45], 24 -; SI-NEXT: s_lshr_b64 s[80:81], s[44:45], 16 -; SI-NEXT: s_lshr_b64 s[82:83], s[44:45], 8 -; SI-NEXT: s_lshr_b64 s[84:85], s[28:29], 24 -; SI-NEXT: s_lshr_b64 s[86:87], s[28:29], 16 -; SI-NEXT: s_lshr_b64 s[96:97], s[28:29], 8 -; SI-NEXT: s_lshr_b64 s[98:99], s[26:27], 24 -; SI-NEXT: s_lshr_b64 s[46:47], s[26:27], 16 -; SI-NEXT: s_lshr_b64 s[56:57], s[26:27], 8 -; SI-NEXT: s_lshr_b64 s[58:59], s[24:25], 24 -; SI-NEXT: s_lshr_b64 s[60:61], s[24:25], 16 -; SI-NEXT: s_lshr_b64 s[62:63], s[24:25], 8 -; SI-NEXT: s_lshr_b64 s[72:73], s[22:23], 24 -; SI-NEXT: s_lshr_b64 s[74:75], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[76:77], s[22:23], 8 -; SI-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 -; SI-NEXT: s_lshr_b64 s[88:89], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[90:91], s[20:21], 8 -; SI-NEXT: s_lshr_b64 s[92:93], s[18:19], 24 -; SI-NEXT: s_lshr_b64 s[94:95], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[30:31], s[18:19], 8 -; SI-NEXT: s_lshr_b64 s[34:35], s[16:17], 24 -; SI-NEXT: s_lshr_b64 s[36:37], s[16:17], 16 -; SI-NEXT: s_lshr_b64 s[38:39], s[16:17], 8 +; SI-NEXT: v_writelane_b32 v23, s27, 1 +; SI-NEXT: s_lshr_b64 s[64:65], s[18:19], 24 +; SI-NEXT: s_lshr_b64 s[66:67], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[68:69], s[18:19], 8 +; SI-NEXT: s_lshr_b64 s[70:71], s[20:21], 24 +; SI-NEXT: s_lshr_b64 s[80:81], s[20:21], 16 +; SI-NEXT: s_lshr_b64 s[82:83], s[20:21], 8 +; SI-NEXT: s_lshr_b64 s[84:85], s[22:23], 24 +; SI-NEXT: s_lshr_b64 s[86:87], s[22:23], 16 +; SI-NEXT: s_lshr_b64 s[96:97], s[22:23], 8 +; SI-NEXT: s_lshr_b64 s[98:99], s[24:25], 24 +; SI-NEXT: s_lshr_b64 s[26:27], s[24:25], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[24:25], 8 +; SI-NEXT: s_lshr_b64 s[58:59], s[40:41], 24 +; SI-NEXT: s_lshr_b64 s[60:61], s[40:41], 16 +; SI-NEXT: s_lshr_b64 s[62:63], s[40:41], 8 +; SI-NEXT: s_lshr_b64 s[72:73], s[42:43], 24 +; SI-NEXT: s_lshr_b64 s[74:75], s[42:43], 16 +; SI-NEXT: s_lshr_b64 s[76:77], s[42:43], 8 +; SI-NEXT: s_lshr_b64 s[78:79], s[44:45], 24 +; SI-NEXT: s_lshr_b64 s[88:89], s[44:45], 16 +; SI-NEXT: s_lshr_b64 s[90:91], s[44:45], 8 +; SI-NEXT: s_lshr_b64 s[92:93], s[46:47], 24 +; SI-NEXT: s_lshr_b64 s[94:95], s[46:47], 16 +; SI-NEXT: s_lshr_b64 s[30:31], s[46:47], 8 +; SI-NEXT: s_lshr_b64 s[34:35], s[56:57], 24 +; SI-NEXT: s_lshr_b64 s[36:37], s[56:57], 16 +; SI-NEXT: s_lshr_b64 s[38:39], s[56:57], 8 ; SI-NEXT: .LBB57_3: ; %end -; SI-NEXT: s_lshl_b32 s47, s38, 8 -; SI-NEXT: s_and_b32 s16, s16, 0xff -; SI-NEXT: s_or_b32 s16, s16, s47 -; SI-NEXT: s_and_b32 s47, s36, 0xff -; SI-NEXT: s_lshl_b32 s57, s34, 24 -; SI-NEXT: s_lshl_b32 s47, s47, 16 -; SI-NEXT: s_or_b32 s47, s57, s47 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s47 -; SI-NEXT: v_mov_b32_e32 v1, s16 -; SI-NEXT: s_and_b32 s16, s17, 0xff -; SI-NEXT: s_lshl_b32 s17, s53, 8 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: s_and_b32 s17, s52, 0xff -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_lshl_b32 s47, s51, 24 -; SI-NEXT: s_or_b32 s17, s47, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_lshl_b32 s16, s30, 8 -; SI-NEXT: s_and_b32 s17, s18, 0xff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: s_and_b32 s17, s94, 0xff -; SI-NEXT: s_lshl_b32 s18, s92, 24 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v3, s16 -; SI-NEXT: s_and_b32 s16, s19, 0xff -; SI-NEXT: s_lshl_b32 s17, s50, 8 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: s_and_b32 s17, s48, 0xff -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_lshl_b32 s18, s49, 24 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v4, s16 -; SI-NEXT: s_lshl_b32 s16, s90, 8 -; SI-NEXT: s_and_b32 s17, s20, 0xff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: s_and_b32 s17, s88, 0xff -; SI-NEXT: s_lshl_b32 s18, s78, 24 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 17 -; SI-NEXT: v_mov_b32_e32 v5, s16 -; SI-NEXT: s_and_b32 s16, s21, 0xff -; SI-NEXT: s_lshl_b32 s17, s17, 8 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 16 -; SI-NEXT: s_and_b32 s17, s17, 0xff -; SI-NEXT: v_readlane_b32 s18, v21, 15 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_lshl_b32 s18, s18, 24 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v6, s16 -; SI-NEXT: s_lshl_b32 s16, s76, 8 -; SI-NEXT: s_and_b32 s17, s22, 0xff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: s_and_b32 s17, s74, 0xff -; SI-NEXT: s_lshl_b32 s18, s72, 24 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 14 -; SI-NEXT: v_mov_b32_e32 v7, s16 -; SI-NEXT: s_and_b32 s16, s23, 0xff -; SI-NEXT: s_lshl_b32 s17, s17, 8 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 13 -; SI-NEXT: s_and_b32 s17, s17, 0xff -; SI-NEXT: v_readlane_b32 s18, v21, 12 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_lshl_b32 s18, s18, 24 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v8, s16 -; SI-NEXT: s_lshl_b32 s16, s62, 8 -; SI-NEXT: s_and_b32 s17, s24, 0xff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: s_and_b32 s17, s60, 0xff -; SI-NEXT: s_lshl_b32 s18, s58, 24 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 11 -; SI-NEXT: v_mov_b32_e32 v9, s16 -; SI-NEXT: s_and_b32 s16, s25, 0xff -; SI-NEXT: s_lshl_b32 s17, s17, 8 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 10 -; SI-NEXT: s_and_b32 s17, s17, 0xff -; SI-NEXT: v_readlane_b32 s18, v21, 9 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_lshl_b32 s18, s18, 24 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v10, s16 -; SI-NEXT: s_lshl_b32 s16, s56, 8 -; SI-NEXT: s_and_b32 s17, s26, 0xff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: s_and_b32 s17, s46, 0xff -; SI-NEXT: s_lshl_b32 s18, s98, 24 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 8 -; SI-NEXT: v_mov_b32_e32 v11, s16 -; SI-NEXT: s_and_b32 s16, s27, 0xff -; SI-NEXT: s_lshl_b32 s17, s17, 8 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 7 -; SI-NEXT: s_and_b32 s17, s17, 0xff -; SI-NEXT: v_readlane_b32 s18, v21, 6 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_lshl_b32 s18, s18, 24 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v12, s16 -; SI-NEXT: s_lshl_b32 s16, s96, 8 -; SI-NEXT: s_and_b32 s17, s28, 0xff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: s_and_b32 s17, s86, 0xff -; SI-NEXT: s_lshl_b32 s18, s84, 24 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 5 -; SI-NEXT: v_mov_b32_e32 v13, s16 -; SI-NEXT: s_and_b32 s16, s29, 0xff -; SI-NEXT: s_lshl_b32 s17, s17, 8 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 4 -; SI-NEXT: s_and_b32 s17, s17, 0xff -; SI-NEXT: v_readlane_b32 s18, v21, 3 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_lshl_b32 s18, s18, 24 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v14, s16 -; SI-NEXT: s_lshl_b32 s16, s82, 8 -; SI-NEXT: s_and_b32 s17, s44, 0xff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: s_and_b32 s17, s80, 0xff -; SI-NEXT: s_lshl_b32 s18, s70, 24 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 2 -; SI-NEXT: v_mov_b32_e32 v15, s16 -; SI-NEXT: s_and_b32 s16, s45, 0xff -; SI-NEXT: s_lshl_b32 s17, s17, 8 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v21, 1 -; SI-NEXT: s_and_b32 s17, s17, 0xff -; SI-NEXT: v_readlane_b32 s18, v21, 0 +; SI-NEXT: s_lshl_b32 s27, s38, 8 +; SI-NEXT: s_and_b32 s29, s56, 0xff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: s_and_b32 s29, s36, 0xff +; SI-NEXT: s_lshl_b32 s56, s34, 24 +; SI-NEXT: s_lshl_b32 s29, s29, 16 +; SI-NEXT: s_or_b32 s29, s56, s29 +; SI-NEXT: s_and_b32 s27, s27, 0xffff +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v1, s27 +; SI-NEXT: s_and_b32 s27, s57, 0xff +; SI-NEXT: s_lshl_b32 s29, s53, 8 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: s_and_b32 s29, s52, 0xff +; SI-NEXT: s_lshl_b32 s29, s29, 16 +; SI-NEXT: s_lshl_b32 s56, s51, 24 +; SI-NEXT: s_or_b32 s29, s56, s29 +; SI-NEXT: s_and_b32 s27, s27, 0xffff +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_lshl_b32 s27, s30, 8 +; SI-NEXT: s_and_b32 s29, s46, 0xff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: s_and_b32 s29, s94, 0xff +; SI-NEXT: s_lshl_b32 s46, s92, 24 +; SI-NEXT: s_lshl_b32 s29, s29, 16 +; SI-NEXT: s_or_b32 s29, s46, s29 +; SI-NEXT: s_and_b32 s27, s27, 0xffff +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v3, s27 +; SI-NEXT: s_and_b32 s27, s47, 0xff +; SI-NEXT: s_lshl_b32 s29, s50, 8 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: s_and_b32 s29, s48, 0xff +; SI-NEXT: s_lshl_b32 s29, s29, 16 +; SI-NEXT: s_lshl_b32 s46, s49, 24 +; SI-NEXT: s_or_b32 s29, s46, s29 +; SI-NEXT: s_and_b32 s27, s27, 0xffff +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v4, s27 +; SI-NEXT: s_lshl_b32 s27, s90, 8 +; SI-NEXT: s_and_b32 s29, s44, 0xff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: s_and_b32 s29, s88, 0xff +; SI-NEXT: s_lshl_b32 s44, s78, 24 +; SI-NEXT: s_lshl_b32 s29, s29, 16 +; SI-NEXT: s_or_b32 s29, s44, s29 +; SI-NEXT: s_and_b32 s27, s27, 0xffff +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_readlane_b32 s29, v22, 17 +; SI-NEXT: v_mov_b32_e32 v5, s27 +; SI-NEXT: s_and_b32 s27, s45, 0xff +; SI-NEXT: s_lshl_b32 s29, s29, 8 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_readlane_b32 s29, v22, 16 +; SI-NEXT: s_and_b32 s29, s29, 0xff +; SI-NEXT: v_readlane_b32 s44, v22, 15 +; SI-NEXT: s_lshl_b32 s29, s29, 16 +; SI-NEXT: s_lshl_b32 s44, s44, 24 +; SI-NEXT: s_or_b32 s29, s44, s29 +; SI-NEXT: s_and_b32 s27, s27, 0xffff +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v6, s27 +; SI-NEXT: s_lshl_b32 s27, s76, 8 +; SI-NEXT: s_and_b32 s29, s42, 0xff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: s_and_b32 s29, s74, 0xff +; SI-NEXT: s_lshl_b32 s42, s72, 24 +; SI-NEXT: s_lshl_b32 s29, s29, 16 +; SI-NEXT: s_or_b32 s29, s42, s29 +; SI-NEXT: s_and_b32 s27, s27, 0xffff +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_readlane_b32 s29, v22, 14 +; SI-NEXT: v_mov_b32_e32 v7, s27 +; SI-NEXT: s_and_b32 s27, s43, 0xff +; SI-NEXT: s_lshl_b32 s29, s29, 8 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_readlane_b32 s29, v22, 13 +; SI-NEXT: s_and_b32 s29, s29, 0xff +; SI-NEXT: v_readlane_b32 s42, v22, 12 +; SI-NEXT: s_lshl_b32 s29, s29, 16 +; SI-NEXT: s_lshl_b32 s42, s42, 24 +; SI-NEXT: s_or_b32 s29, s42, s29 +; SI-NEXT: s_and_b32 s27, s27, 0xffff +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v8, s27 +; SI-NEXT: s_lshl_b32 s27, s62, 8 +; SI-NEXT: s_and_b32 s29, s40, 0xff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: s_and_b32 s29, s60, 0xff +; SI-NEXT: s_lshl_b32 s40, s58, 24 +; SI-NEXT: s_lshl_b32 s29, s29, 16 +; SI-NEXT: s_or_b32 s29, s40, s29 +; SI-NEXT: s_and_b32 s27, s27, 0xffff +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_readlane_b32 s29, v22, 11 +; SI-NEXT: v_mov_b32_e32 v9, s27 +; SI-NEXT: s_and_b32 s27, s41, 0xff +; SI-NEXT: s_lshl_b32 s29, s29, 8 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_readlane_b32 s29, v22, 10 +; SI-NEXT: s_and_b32 s29, s29, 0xff +; SI-NEXT: v_readlane_b32 s40, v22, 9 +; SI-NEXT: s_lshl_b32 s29, s29, 16 +; SI-NEXT: s_lshl_b32 s40, s40, 24 +; SI-NEXT: s_or_b32 s29, s40, s29 +; SI-NEXT: s_and_b32 s27, s27, 0xffff +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v10, s27 +; SI-NEXT: s_lshl_b32 s27, s28, 8 +; SI-NEXT: s_and_b32 s24, s24, 0xff +; SI-NEXT: s_and_b32 s26, s26, 0xff +; SI-NEXT: s_or_b32 s24, s24, s27 +; SI-NEXT: s_lshl_b32 s27, s98, 24 +; SI-NEXT: s_lshl_b32 s26, s26, 16 +; SI-NEXT: s_or_b32 s26, s27, s26 +; SI-NEXT: s_and_b32 s24, s24, 0xffff +; SI-NEXT: s_or_b32 s24, s24, s26 +; SI-NEXT: v_mov_b32_e32 v11, s24 +; SI-NEXT: s_and_b32 s24, s25, 0xff +; SI-NEXT: v_readlane_b32 s25, v22, 8 +; SI-NEXT: s_lshl_b32 s25, s25, 8 +; SI-NEXT: s_or_b32 s24, s24, s25 +; SI-NEXT: v_readlane_b32 s25, v22, 7 +; SI-NEXT: s_and_b32 s25, s25, 0xff +; SI-NEXT: v_readlane_b32 s26, v22, 6 +; SI-NEXT: s_lshl_b32 s25, s25, 16 +; SI-NEXT: s_lshl_b32 s26, s26, 24 +; SI-NEXT: s_or_b32 s25, s26, s25 +; SI-NEXT: s_and_b32 s24, s24, 0xffff +; SI-NEXT: s_or_b32 s24, s24, s25 +; SI-NEXT: v_mov_b32_e32 v12, s24 +; SI-NEXT: s_lshl_b32 s24, s96, 8 +; SI-NEXT: s_and_b32 s22, s22, 0xff +; SI-NEXT: s_or_b32 s22, s22, s24 +; SI-NEXT: s_and_b32 s24, s86, 0xff +; SI-NEXT: s_lshl_b32 s25, s84, 24 +; SI-NEXT: s_lshl_b32 s24, s24, 16 +; SI-NEXT: s_or_b32 s24, s25, s24 +; SI-NEXT: s_and_b32 s22, s22, 0xffff +; SI-NEXT: s_or_b32 s22, s22, s24 +; SI-NEXT: v_mov_b32_e32 v13, s22 +; SI-NEXT: s_and_b32 s22, s23, 0xff +; SI-NEXT: v_readlane_b32 s23, v22, 5 +; SI-NEXT: s_lshl_b32 s23, s23, 8 +; SI-NEXT: s_or_b32 s22, s22, s23 +; SI-NEXT: v_readlane_b32 s23, v22, 4 +; SI-NEXT: s_and_b32 s23, s23, 0xff +; SI-NEXT: v_readlane_b32 s24, v22, 3 +; SI-NEXT: s_lshl_b32 s23, s23, 16 +; SI-NEXT: s_lshl_b32 s24, s24, 24 +; SI-NEXT: s_or_b32 s23, s24, s23 +; SI-NEXT: s_and_b32 s22, s22, 0xffff +; SI-NEXT: s_or_b32 s22, s22, s23 +; SI-NEXT: v_mov_b32_e32 v14, s22 +; SI-NEXT: s_lshl_b32 s22, s82, 8 +; SI-NEXT: s_and_b32 s20, s20, 0xff +; SI-NEXT: s_or_b32 s20, s20, s22 +; SI-NEXT: s_and_b32 s22, s80, 0xff +; SI-NEXT: s_lshl_b32 s23, s70, 24 +; SI-NEXT: s_lshl_b32 s22, s22, 16 +; SI-NEXT: s_or_b32 s22, s23, s22 +; SI-NEXT: s_and_b32 s20, s20, 0xffff +; SI-NEXT: s_or_b32 s20, s20, s22 +; SI-NEXT: v_mov_b32_e32 v15, s20 +; SI-NEXT: s_and_b32 s20, s21, 0xff +; SI-NEXT: v_readlane_b32 s21, v22, 2 +; SI-NEXT: s_lshl_b32 s21, s21, 8 +; SI-NEXT: s_or_b32 s20, s20, s21 +; SI-NEXT: v_readlane_b32 s21, v22, 1 +; SI-NEXT: s_and_b32 s21, s21, 0xff +; SI-NEXT: v_readlane_b32 s22, v22, 0 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_lshl_b32 s18, s18, 24 +; SI-NEXT: s_lshl_b32 s21, s21, 16 +; SI-NEXT: s_lshl_b32 s22, s22, 24 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff +; SI-NEXT: s_or_b32 s21, s22, s21 +; SI-NEXT: s_and_b32 s20, s20, 0xffff ; SI-NEXT: buffer_store_dword v3, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 12, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s20, s20, s21 ; SI-NEXT: buffer_store_dword v4, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0 -; SI-NEXT: v_mov_b32_e32 v16, s16 -; SI-NEXT: s_lshl_b32 s16, s68, 8 -; SI-NEXT: s_and_b32 s17, s42, 0xff +; SI-NEXT: v_mov_b32_e32 v16, s20 +; SI-NEXT: s_lshl_b32 s20, s68, 8 +; SI-NEXT: s_and_b32 s18, s18, 0xff ; SI-NEXT: buffer_store_dword v5, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 20, v0 -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: s_and_b32 s17, s66, 0xff +; SI-NEXT: s_or_b32 s18, s18, s20 +; SI-NEXT: s_and_b32 s20, s66, 0xff ; SI-NEXT: buffer_store_dword v6, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0 -; SI-NEXT: s_lshl_b32 s18, s64, 24 -; SI-NEXT: s_lshl_b32 s17, s17, 16 +; SI-NEXT: s_lshl_b32 s21, s64, 24 +; SI-NEXT: s_lshl_b32 s20, s20, 16 ; SI-NEXT: buffer_store_dword v7, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 28, v0 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_and_b32 s16, s16, 0xffff +; SI-NEXT: s_or_b32 s20, s21, s20 +; SI-NEXT: s_and_b32 s18, s18, 0xffff ; SI-NEXT: buffer_store_dword v8, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s18, s18, s20 ; SI-NEXT: buffer_store_dword v9, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 36, v0 -; SI-NEXT: v_readlane_b32 s17, v22, 63 ; SI-NEXT: buffer_store_dword v10, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0 -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s43, 0xff -; SI-NEXT: s_lshl_b32 s17, s17, 8 +; SI-NEXT: v_mov_b32_e32 v2, s18 +; SI-NEXT: s_and_b32 s18, s19, 0xff +; SI-NEXT: v_readlane_b32 s19, v23, 63 ; SI-NEXT: buffer_store_dword v11, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 44, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v22, 62 +; SI-NEXT: s_lshl_b32 s19, s19, 8 ; SI-NEXT: buffer_store_dword v12, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0 -; SI-NEXT: s_and_b32 s17, s17, 0xff -; SI-NEXT: v_readlane_b32 s18, v22, 61 +; SI-NEXT: s_or_b32 s18, s18, s19 +; SI-NEXT: v_readlane_b32 s19, v23, 62 ; SI-NEXT: buffer_store_dword v13, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 52, v0 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_lshl_b32 s18, s18, 24 +; SI-NEXT: s_and_b32 s19, s19, 0xff +; SI-NEXT: v_readlane_b32 s20, v23, 61 ; SI-NEXT: buffer_store_dword v14, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 56, v0 -; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: v_readlane_b32 s18, v22, 0 +; SI-NEXT: s_lshl_b32 s19, s19, 16 +; SI-NEXT: s_lshl_b32 s20, s20, 24 ; SI-NEXT: buffer_store_dword v15, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 60, v0 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: v_readlane_b32 s19, v22, 1 +; SI-NEXT: s_and_b32 s18, s18, 0xffff +; SI-NEXT: s_or_b32 s19, s20, s19 ; SI-NEXT: buffer_store_dword v16, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 64, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: s_lshl_b32 s17, s18, 8 -; SI-NEXT: v_readlane_b32 s18, v22, 2 +; SI-NEXT: s_or_b32 s18, s18, s19 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s40, 0xff -; SI-NEXT: v_readlane_b32 s19, v22, 3 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: s_and_b32 s17, s18, 0xff -; SI-NEXT: v_readlane_b32 s18, v22, 4 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_lshl_b32 s18, s18, 24 +; SI-NEXT: v_mov_b32_e32 v2, s18 +; SI-NEXT: v_readlane_b32 s18, v23, 0 +; SI-NEXT: s_and_b32 s16, s16, 0xff +; SI-NEXT: v_readlane_b32 s19, v23, 1 +; SI-NEXT: s_lshl_b32 s18, s18, 8 +; SI-NEXT: s_or_b32 s16, s16, s18 +; SI-NEXT: v_readlane_b32 s18, v23, 2 +; SI-NEXT: v_readlane_b32 s19, v23, 3 +; SI-NEXT: s_and_b32 s18, s18, 0xff +; SI-NEXT: v_readlane_b32 s20, v23, 4 +; SI-NEXT: s_lshl_b32 s18, s18, 16 +; SI-NEXT: s_lshl_b32 s19, s20, 24 ; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s17, s18, s17 +; SI-NEXT: s_or_b32 s18, s19, s18 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x44, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v22, 60 +; SI-NEXT: s_or_b32 s16, s16, s18 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s41, 0xff +; SI-NEXT: s_and_b32 s16, s17, 0xff +; SI-NEXT: v_readlane_b32 s17, v23, 60 ; SI-NEXT: s_lshl_b32 s17, s17, 8 ; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_readlane_b32 s17, v22, 59 +; SI-NEXT: v_readlane_b32 s17, v23, 59 ; SI-NEXT: s_and_b32 s17, s17, 0xff -; SI-NEXT: v_readlane_b32 s18, v22, 58 +; SI-NEXT: v_readlane_b32 s18, v23, 58 ; SI-NEXT: s_lshl_b32 s17, s17, 16 ; SI-NEXT: s_lshl_b32 s18, s18, 24 ; SI-NEXT: s_and_b32 s16, s16, 0xffff @@ -82101,16 +81090,15 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: v_readlane_b32 s16, v22, 6 +; SI-NEXT: v_readlane_b32 s16, v23, 6 ; SI-NEXT: s_and_b32 s14, s14, 0xff -; SI-NEXT: v_readlane_b32 s17, v22, 7 +; SI-NEXT: v_readlane_b32 s17, v23, 7 ; SI-NEXT: s_lshl_b32 s16, s16, 8 -; SI-NEXT: v_readlane_b32 s19, v22, 5 ; SI-NEXT: s_or_b32 s14, s14, s16 -; SI-NEXT: v_readlane_b32 s16, v22, 8 -; SI-NEXT: v_readlane_b32 s17, v22, 9 +; SI-NEXT: v_readlane_b32 s16, v23, 8 +; SI-NEXT: v_readlane_b32 s17, v23, 9 ; SI-NEXT: s_and_b32 s16, s16, 0xff -; SI-NEXT: v_readlane_b32 s18, v22, 10 +; SI-NEXT: v_readlane_b32 s18, v23, 10 ; SI-NEXT: s_lshl_b32 s16, s16, 16 ; SI-NEXT: s_lshl_b32 s17, s18, 24 ; SI-NEXT: s_and_b32 s14, s14, 0xffff @@ -82121,12 +81109,12 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s14 ; SI-NEXT: s_and_b32 s14, s15, 0xff -; SI-NEXT: v_readlane_b32 s15, v22, 57 +; SI-NEXT: v_readlane_b32 s15, v23, 57 ; SI-NEXT: s_lshl_b32 s15, s15, 8 ; SI-NEXT: s_or_b32 s14, s14, s15 -; SI-NEXT: v_readlane_b32 s15, v22, 56 +; SI-NEXT: v_readlane_b32 s15, v23, 56 ; SI-NEXT: s_and_b32 s15, s15, 0xff -; SI-NEXT: v_readlane_b32 s16, v22, 55 +; SI-NEXT: v_readlane_b32 s16, v23, 55 ; SI-NEXT: s_lshl_b32 s15, s15, 16 ; SI-NEXT: s_lshl_b32 s16, s16, 24 ; SI-NEXT: s_and_b32 s14, s14, 0xffff @@ -82136,15 +81124,15 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s14 -; SI-NEXT: v_readlane_b32 s14, v22, 12 +; SI-NEXT: v_readlane_b32 s14, v23, 12 ; SI-NEXT: s_and_b32 s12, s12, 0xff -; SI-NEXT: v_readlane_b32 s15, v22, 13 +; SI-NEXT: v_readlane_b32 s15, v23, 13 ; SI-NEXT: s_lshl_b32 s14, s14, 8 ; SI-NEXT: s_or_b32 s12, s12, s14 -; SI-NEXT: v_readlane_b32 s14, v22, 14 -; SI-NEXT: v_readlane_b32 s15, v22, 15 +; SI-NEXT: v_readlane_b32 s14, v23, 14 +; SI-NEXT: v_readlane_b32 s15, v23, 15 ; SI-NEXT: s_and_b32 s14, s14, 0xff -; SI-NEXT: v_readlane_b32 s16, v22, 16 +; SI-NEXT: v_readlane_b32 s16, v23, 16 ; SI-NEXT: s_lshl_b32 s14, s14, 16 ; SI-NEXT: s_lshl_b32 s15, s16, 24 ; SI-NEXT: s_and_b32 s12, s12, 0xffff @@ -82155,12 +81143,12 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s12 ; SI-NEXT: s_and_b32 s12, s13, 0xff -; SI-NEXT: v_readlane_b32 s13, v22, 54 +; SI-NEXT: v_readlane_b32 s13, v23, 54 ; SI-NEXT: s_lshl_b32 s13, s13, 8 ; SI-NEXT: s_or_b32 s12, s12, s13 -; SI-NEXT: v_readlane_b32 s13, v22, 53 +; SI-NEXT: v_readlane_b32 s13, v23, 53 ; SI-NEXT: s_and_b32 s13, s13, 0xff -; SI-NEXT: v_readlane_b32 s14, v22, 52 +; SI-NEXT: v_readlane_b32 s14, v23, 52 ; SI-NEXT: s_lshl_b32 s13, s13, 16 ; SI-NEXT: s_lshl_b32 s14, s14, 24 ; SI-NEXT: s_and_b32 s12, s12, 0xffff @@ -82170,15 +81158,15 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s12 -; SI-NEXT: v_readlane_b32 s12, v22, 18 +; SI-NEXT: v_readlane_b32 s12, v23, 18 ; SI-NEXT: s_and_b32 s10, s10, 0xff -; SI-NEXT: v_readlane_b32 s13, v22, 19 +; SI-NEXT: v_readlane_b32 s13, v23, 19 ; SI-NEXT: s_lshl_b32 s12, s12, 8 ; SI-NEXT: s_or_b32 s10, s10, s12 -; SI-NEXT: v_readlane_b32 s12, v22, 20 -; SI-NEXT: v_readlane_b32 s13, v22, 21 +; SI-NEXT: v_readlane_b32 s12, v23, 20 +; SI-NEXT: v_readlane_b32 s13, v23, 21 ; SI-NEXT: s_and_b32 s12, s12, 0xff -; SI-NEXT: v_readlane_b32 s14, v22, 22 +; SI-NEXT: v_readlane_b32 s14, v23, 22 ; SI-NEXT: s_lshl_b32 s12, s12, 16 ; SI-NEXT: s_lshl_b32 s13, s14, 24 ; SI-NEXT: s_and_b32 s10, s10, 0xffff @@ -82189,12 +81177,12 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s10 ; SI-NEXT: s_and_b32 s10, s11, 0xff -; SI-NEXT: v_readlane_b32 s11, v22, 51 +; SI-NEXT: v_readlane_b32 s11, v23, 51 ; SI-NEXT: s_lshl_b32 s11, s11, 8 ; SI-NEXT: s_or_b32 s10, s10, s11 -; SI-NEXT: v_readlane_b32 s11, v22, 50 +; SI-NEXT: v_readlane_b32 s11, v23, 50 ; SI-NEXT: s_and_b32 s11, s11, 0xff -; SI-NEXT: v_readlane_b32 s12, v22, 49 +; SI-NEXT: v_readlane_b32 s12, v23, 49 ; SI-NEXT: s_lshl_b32 s11, s11, 16 ; SI-NEXT: s_lshl_b32 s12, s12, 24 ; SI-NEXT: s_and_b32 s10, s10, 0xffff @@ -82204,15 +81192,15 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s10 -; SI-NEXT: v_readlane_b32 s10, v22, 24 +; SI-NEXT: v_readlane_b32 s10, v23, 24 ; SI-NEXT: s_and_b32 s8, s8, 0xff -; SI-NEXT: v_readlane_b32 s11, v22, 25 +; SI-NEXT: v_readlane_b32 s11, v23, 25 ; SI-NEXT: s_lshl_b32 s10, s10, 8 ; SI-NEXT: s_or_b32 s8, s8, s10 -; SI-NEXT: v_readlane_b32 s10, v22, 26 -; SI-NEXT: v_readlane_b32 s11, v22, 27 +; SI-NEXT: v_readlane_b32 s10, v23, 26 +; SI-NEXT: v_readlane_b32 s11, v23, 27 ; SI-NEXT: s_and_b32 s10, s10, 0xff -; SI-NEXT: v_readlane_b32 s12, v22, 28 +; SI-NEXT: v_readlane_b32 s12, v23, 28 ; SI-NEXT: s_lshl_b32 s10, s10, 16 ; SI-NEXT: s_lshl_b32 s11, s12, 24 ; SI-NEXT: s_and_b32 s8, s8, 0xffff @@ -82223,12 +81211,12 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s8 ; SI-NEXT: s_and_b32 s8, s9, 0xff -; SI-NEXT: v_readlane_b32 s9, v22, 48 +; SI-NEXT: v_readlane_b32 s9, v23, 48 ; SI-NEXT: s_lshl_b32 s9, s9, 8 ; SI-NEXT: s_or_b32 s8, s8, s9 -; SI-NEXT: v_readlane_b32 s9, v22, 47 +; SI-NEXT: v_readlane_b32 s9, v23, 47 ; SI-NEXT: s_and_b32 s9, s9, 0xff -; SI-NEXT: v_readlane_b32 s10, v22, 46 +; SI-NEXT: v_readlane_b32 s10, v23, 46 ; SI-NEXT: s_lshl_b32 s9, s9, 16 ; SI-NEXT: s_lshl_b32 s10, s10, 24 ; SI-NEXT: s_and_b32 s8, s8, 0xffff @@ -82238,15 +81226,15 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s8 -; SI-NEXT: v_readlane_b32 s8, v22, 30 +; SI-NEXT: v_readlane_b32 s8, v23, 30 ; SI-NEXT: s_and_b32 s6, s6, 0xff -; SI-NEXT: v_readlane_b32 s9, v22, 31 +; SI-NEXT: v_readlane_b32 s9, v23, 31 ; SI-NEXT: s_lshl_b32 s8, s8, 8 ; SI-NEXT: s_or_b32 s6, s6, s8 -; SI-NEXT: v_readlane_b32 s8, v22, 32 -; SI-NEXT: v_readlane_b32 s9, v22, 33 +; SI-NEXT: v_readlane_b32 s8, v23, 32 +; SI-NEXT: v_readlane_b32 s9, v23, 33 ; SI-NEXT: s_and_b32 s8, s8, 0xff -; SI-NEXT: v_readlane_b32 s10, v22, 34 +; SI-NEXT: v_readlane_b32 s10, v23, 34 ; SI-NEXT: s_lshl_b32 s8, s8, 16 ; SI-NEXT: s_lshl_b32 s9, s10, 24 ; SI-NEXT: s_and_b32 s6, s6, 0xffff @@ -82257,12 +81245,12 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s6 ; SI-NEXT: s_and_b32 s6, s7, 0xff -; SI-NEXT: v_readlane_b32 s7, v22, 45 +; SI-NEXT: v_readlane_b32 s7, v23, 45 ; SI-NEXT: s_lshl_b32 s7, s7, 8 ; SI-NEXT: s_or_b32 s6, s6, s7 -; SI-NEXT: v_readlane_b32 s7, v22, 44 +; SI-NEXT: v_readlane_b32 s7, v23, 44 ; SI-NEXT: s_and_b32 s7, s7, 0xff -; SI-NEXT: v_readlane_b32 s8, v22, 43 +; SI-NEXT: v_readlane_b32 s8, v23, 43 ; SI-NEXT: s_lshl_b32 s7, s7, 16 ; SI-NEXT: s_lshl_b32 s8, s8, 24 ; SI-NEXT: s_and_b32 s6, s6, 0xffff @@ -82272,13 +81260,13 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s6 -; SI-NEXT: v_readlane_b32 s6, v22, 36 +; SI-NEXT: v_readlane_b32 s6, v23, 36 ; SI-NEXT: s_and_b32 s4, s4, 0xff ; SI-NEXT: s_lshl_b32 s6, s6, 8 -; SI-NEXT: v_readlane_b32 s7, v22, 37 +; SI-NEXT: v_readlane_b32 s7, v23, 37 ; SI-NEXT: s_or_b32 s4, s4, s6 ; SI-NEXT: s_and_b32 s6, s54, 0xff -; SI-NEXT: v_readlane_b32 s8, v22, 38 +; SI-NEXT: v_readlane_b32 s8, v23, 38 ; SI-NEXT: s_lshl_b32 s6, s6, 16 ; SI-NEXT: s_lshl_b32 s7, s8, 24 ; SI-NEXT: s_and_b32 s4, s4, 0xffff @@ -82289,12 +81277,12 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s4 ; SI-NEXT: s_and_b32 s4, s5, 0xff -; SI-NEXT: v_readlane_b32 s5, v22, 42 +; SI-NEXT: v_readlane_b32 s5, v23, 42 ; SI-NEXT: s_lshl_b32 s5, s5, 8 ; SI-NEXT: s_or_b32 s4, s4, s5 -; SI-NEXT: v_readlane_b32 s5, v22, 41 +; SI-NEXT: v_readlane_b32 s5, v23, 41 ; SI-NEXT: s_and_b32 s5, s5, 0xff -; SI-NEXT: v_readlane_b32 s6, v22, 40 +; SI-NEXT: v_readlane_b32 s6, v23, 40 ; SI-NEXT: s_lshl_b32 s5, s5, 16 ; SI-NEXT: s_lshl_b32 s6, s6, 24 ; SI-NEXT: s_and_b32 s4, s4, 0xffff @@ -82304,69 +81292,70 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 -; SI-NEXT: v_readlane_b32 s19, v22, 11 -; SI-NEXT: v_readlane_b32 s17, v22, 17 -; SI-NEXT: v_readlane_b32 s15, v22, 23 -; SI-NEXT: v_readlane_b32 s13, v22, 29 -; SI-NEXT: v_readlane_b32 s11, v22, 35 -; SI-NEXT: v_readlane_b32 s9, v22, 39 +; SI-NEXT: v_readlane_b32 s21, v23, 5 +; SI-NEXT: v_readlane_b32 s19, v23, 11 +; SI-NEXT: v_readlane_b32 s17, v23, 17 +; SI-NEXT: v_readlane_b32 s15, v23, 23 +; SI-NEXT: v_readlane_b32 s13, v23, 29 +; SI-NEXT: v_readlane_b32 s11, v23, 35 +; SI-NEXT: v_readlane_b32 s9, v23, 39 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s99, v20, 35 -; SI-NEXT: v_readlane_b32 s98, v20, 34 -; SI-NEXT: v_readlane_b32 s97, v20, 33 -; SI-NEXT: v_readlane_b32 s96, v20, 32 -; SI-NEXT: v_readlane_b32 s87, v20, 31 -; SI-NEXT: v_readlane_b32 s86, v20, 30 -; SI-NEXT: v_readlane_b32 s85, v20, 29 -; SI-NEXT: v_readlane_b32 s84, v20, 28 -; SI-NEXT: v_readlane_b32 s83, v20, 27 -; SI-NEXT: v_readlane_b32 s82, v20, 26 -; SI-NEXT: v_readlane_b32 s81, v20, 25 -; SI-NEXT: v_readlane_b32 s80, v20, 24 -; SI-NEXT: v_readlane_b32 s71, v20, 23 -; SI-NEXT: v_readlane_b32 s70, v20, 22 -; SI-NEXT: v_readlane_b32 s69, v20, 21 -; SI-NEXT: v_readlane_b32 s68, v20, 20 -; SI-NEXT: v_readlane_b32 s67, v20, 19 -; SI-NEXT: v_readlane_b32 s66, v20, 18 -; SI-NEXT: v_readlane_b32 s65, v20, 17 -; SI-NEXT: v_readlane_b32 s64, v20, 16 -; SI-NEXT: v_readlane_b32 s55, v20, 15 -; SI-NEXT: v_readlane_b32 s54, v20, 14 -; SI-NEXT: v_readlane_b32 s53, v20, 13 -; SI-NEXT: v_readlane_b32 s52, v20, 12 -; SI-NEXT: v_readlane_b32 s51, v20, 11 -; SI-NEXT: v_readlane_b32 s50, v20, 10 -; SI-NEXT: v_readlane_b32 s49, v20, 9 -; SI-NEXT: v_readlane_b32 s48, v20, 8 -; SI-NEXT: v_readlane_b32 s39, v20, 7 -; SI-NEXT: v_readlane_b32 s38, v20, 6 -; SI-NEXT: v_readlane_b32 s37, v20, 5 -; SI-NEXT: v_readlane_b32 s36, v20, 4 -; SI-NEXT: v_readlane_b32 s35, v20, 3 -; SI-NEXT: v_readlane_b32 s34, v20, 2 -; SI-NEXT: v_readlane_b32 s31, v20, 1 -; SI-NEXT: v_readlane_b32 s30, v20, 0 +; SI-NEXT: v_readlane_b32 s99, v21, 35 +; SI-NEXT: v_readlane_b32 s98, v21, 34 +; SI-NEXT: v_readlane_b32 s97, v21, 33 +; SI-NEXT: v_readlane_b32 s96, v21, 32 +; SI-NEXT: v_readlane_b32 s87, v21, 31 +; SI-NEXT: v_readlane_b32 s86, v21, 30 +; SI-NEXT: v_readlane_b32 s85, v21, 29 +; SI-NEXT: v_readlane_b32 s84, v21, 28 +; SI-NEXT: v_readlane_b32 s83, v21, 27 +; SI-NEXT: v_readlane_b32 s82, v21, 26 +; SI-NEXT: v_readlane_b32 s81, v21, 25 +; SI-NEXT: v_readlane_b32 s80, v21, 24 +; SI-NEXT: v_readlane_b32 s71, v21, 23 +; SI-NEXT: v_readlane_b32 s70, v21, 22 +; SI-NEXT: v_readlane_b32 s69, v21, 21 +; SI-NEXT: v_readlane_b32 s68, v21, 20 +; SI-NEXT: v_readlane_b32 s67, v21, 19 +; SI-NEXT: v_readlane_b32 s66, v21, 18 +; SI-NEXT: v_readlane_b32 s65, v21, 17 +; SI-NEXT: v_readlane_b32 s64, v21, 16 +; SI-NEXT: v_readlane_b32 s55, v21, 15 +; SI-NEXT: v_readlane_b32 s54, v21, 14 +; SI-NEXT: v_readlane_b32 s53, v21, 13 +; SI-NEXT: v_readlane_b32 s52, v21, 12 +; SI-NEXT: v_readlane_b32 s51, v21, 11 +; SI-NEXT: v_readlane_b32 s50, v21, 10 +; SI-NEXT: v_readlane_b32 s49, v21, 9 +; SI-NEXT: v_readlane_b32 s48, v21, 8 +; SI-NEXT: v_readlane_b32 s39, v21, 7 +; SI-NEXT: v_readlane_b32 s38, v21, 6 +; SI-NEXT: v_readlane_b32 s37, v21, 5 +; SI-NEXT: v_readlane_b32 s36, v21, 4 +; SI-NEXT: v_readlane_b32 s35, v21, 3 +; SI-NEXT: v_readlane_b32 s34, v21, 2 +; SI-NEXT: v_readlane_b32 s31, v21, 1 +; SI-NEXT: v_readlane_b32 s30, v21, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] ; SI-NEXT: .LBB57_4: -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v22, s54, 0 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s55, 1 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 +; SI-NEXT: v_writelane_b32 v23, s54, 0 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s55, 1 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr54 ; SI-NEXT: ; implicit-def: $sgpr53 ; SI-NEXT: ; implicit-def: $sgpr52 @@ -82389,7 +81378,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: ; implicit-def: $sgpr62 ; SI-NEXT: ; implicit-def: $sgpr60 ; SI-NEXT: ; implicit-def: $sgpr58 -; SI-NEXT: ; implicit-def: $sgpr56 +; SI-NEXT: ; implicit-def: $sgpr28 ; SI-NEXT: ; implicit-def: $sgpr98 ; SI-NEXT: ; implicit-def: $sgpr96 ; SI-NEXT: ; implicit-def: $sgpr86 @@ -82400,139 +81389,139 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: ; implicit-def: $sgpr68 ; SI-NEXT: ; implicit-def: $sgpr66 ; SI-NEXT: ; implicit-def: $sgpr64 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s54, 2 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s55, 3 -; SI-NEXT: ; implicit-def: $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s54, 2 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s55, 3 +; SI-NEXT: ; implicit-def: $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s54, 4 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s55, 5 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s54, 4 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s55, 5 ; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s54, 6 -; SI-NEXT: v_writelane_b32 v22, s55, 7 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s54, 6 +; SI-NEXT: v_writelane_b32 v23, s55, 7 ; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s54, 8 -; SI-NEXT: v_writelane_b32 v22, s55, 9 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s54, 8 +; SI-NEXT: v_writelane_b32 v23, s55, 9 ; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s54, 10 -; SI-NEXT: v_writelane_b32 v22, s55, 11 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s54, 10 +; SI-NEXT: v_writelane_b32 v23, s55, 11 ; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s54, 12 -; SI-NEXT: v_writelane_b32 v22, s55, 13 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s54, 12 +; SI-NEXT: v_writelane_b32 v23, s55, 13 ; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s54, 14 -; SI-NEXT: v_writelane_b32 v22, s55, 15 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s54, 14 +; SI-NEXT: v_writelane_b32 v23, s55, 15 ; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s54, 16 -; SI-NEXT: v_writelane_b32 v22, s55, 17 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s54, 16 +; SI-NEXT: v_writelane_b32 v23, s55, 17 ; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s54, 18 -; SI-NEXT: v_writelane_b32 v22, s55, 19 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s54, 18 +; SI-NEXT: v_writelane_b32 v23, s55, 19 ; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s54, 20 -; SI-NEXT: v_writelane_b32 v22, s55, 21 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s54, 20 +; SI-NEXT: v_writelane_b32 v23, s55, 21 ; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s54, 22 -; SI-NEXT: v_writelane_b32 v22, s55, 23 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s54, 22 +; SI-NEXT: v_writelane_b32 v23, s55, 23 ; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s54, 24 -; SI-NEXT: v_writelane_b32 v22, s55, 25 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s54, 24 +; SI-NEXT: v_writelane_b32 v23, s55, 25 ; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s54, 26 -; SI-NEXT: v_writelane_b32 v22, s55, 27 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s54, 26 +; SI-NEXT: v_writelane_b32 v23, s55, 27 ; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s54, 28 -; SI-NEXT: v_writelane_b32 v22, s55, 29 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s54, 28 +; SI-NEXT: v_writelane_b32 v23, s55, 29 ; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s54, 30 -; SI-NEXT: v_writelane_b32 v22, s55, 31 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s54, 30 +; SI-NEXT: v_writelane_b32 v23, s55, 31 ; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s54, 32 -; SI-NEXT: v_writelane_b32 v22, s55, 33 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s54, 32 +; SI-NEXT: v_writelane_b32 v23, s55, 33 ; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s54, 34 -; SI-NEXT: v_writelane_b32 v22, s55, 35 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s54, 34 +; SI-NEXT: v_writelane_b32 v23, s55, 35 ; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s54, 36 -; SI-NEXT: v_writelane_b32 v22, s55, 37 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s54, 36 +; SI-NEXT: v_writelane_b32 v23, s55, 37 ; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v22, s54, 38 -; SI-NEXT: v_writelane_b32 v22, s55, 39 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v23, s54, 38 +; SI-NEXT: v_writelane_b32 v23, s55, 39 ; SI-NEXT: ; implicit-def: $sgpr54 ; SI-NEXT: s_branch .LBB57_2 ; @@ -82540,47 +81529,75 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v20, s30, 0 -; VI-NEXT: v_writelane_b32 v20, s31, 1 -; VI-NEXT: v_writelane_b32 v20, s34, 2 -; VI-NEXT: v_writelane_b32 v20, s35, 3 -; VI-NEXT: v_writelane_b32 v20, s36, 4 -; VI-NEXT: v_writelane_b32 v20, s37, 5 -; VI-NEXT: v_writelane_b32 v20, s38, 6 -; VI-NEXT: v_writelane_b32 v20, s39, 7 -; VI-NEXT: v_writelane_b32 v20, s48, 8 -; VI-NEXT: v_writelane_b32 v20, s49, 9 -; VI-NEXT: v_writelane_b32 v20, s50, 10 -; VI-NEXT: v_writelane_b32 v20, s51, 11 -; VI-NEXT: v_writelane_b32 v20, s52, 12 -; VI-NEXT: v_writelane_b32 v20, s53, 13 -; VI-NEXT: v_writelane_b32 v20, s54, 14 -; VI-NEXT: v_writelane_b32 v20, s55, 15 -; VI-NEXT: v_writelane_b32 v20, s64, 16 -; VI-NEXT: v_writelane_b32 v20, s65, 17 -; VI-NEXT: v_writelane_b32 v20, s66, 18 -; VI-NEXT: v_writelane_b32 v20, s67, 19 -; VI-NEXT: v_writelane_b32 v20, s68, 20 -; VI-NEXT: v_writelane_b32 v20, s69, 21 -; VI-NEXT: v_writelane_b32 v20, s70, 22 -; VI-NEXT: v_writelane_b32 v20, s71, 23 -; VI-NEXT: v_writelane_b32 v20, s80, 24 -; VI-NEXT: v_writelane_b32 v20, s81, 25 -; VI-NEXT: v_writelane_b32 v20, s82, 26 -; VI-NEXT: v_writelane_b32 v20, s83, 27 -; VI-NEXT: v_writelane_b32 v20, s84, 28 -; VI-NEXT: v_writelane_b32 v20, s85, 29 +; VI-NEXT: v_writelane_b32 v21, s30, 0 +; VI-NEXT: v_writelane_b32 v21, s31, 1 +; VI-NEXT: v_writelane_b32 v21, s34, 2 +; VI-NEXT: v_writelane_b32 v21, s35, 3 +; VI-NEXT: v_writelane_b32 v21, s36, 4 +; VI-NEXT: v_writelane_b32 v21, s37, 5 +; VI-NEXT: v_writelane_b32 v21, s38, 6 +; VI-NEXT: v_writelane_b32 v21, s39, 7 +; VI-NEXT: v_writelane_b32 v21, s48, 8 +; VI-NEXT: v_writelane_b32 v21, s49, 9 +; VI-NEXT: v_writelane_b32 v21, s50, 10 +; VI-NEXT: v_writelane_b32 v21, s51, 11 +; VI-NEXT: v_writelane_b32 v21, s52, 12 +; VI-NEXT: v_writelane_b32 v21, s53, 13 +; VI-NEXT: v_writelane_b32 v21, s54, 14 +; VI-NEXT: v_writelane_b32 v21, s55, 15 +; VI-NEXT: v_writelane_b32 v21, s64, 16 +; VI-NEXT: v_mov_b32_e32 v20, s16 +; VI-NEXT: v_writelane_b32 v21, s65, 17 +; VI-NEXT: v_readfirstlane_b32 s56, v20 +; VI-NEXT: v_mov_b32_e32 v20, s17 +; VI-NEXT: v_writelane_b32 v21, s66, 18 +; VI-NEXT: v_readfirstlane_b32 s57, v20 +; VI-NEXT: v_mov_b32_e32 v20, s18 +; VI-NEXT: v_writelane_b32 v21, s67, 19 +; VI-NEXT: v_readfirstlane_b32 s46, v20 +; VI-NEXT: v_mov_b32_e32 v20, s19 +; VI-NEXT: v_writelane_b32 v21, s68, 20 +; VI-NEXT: v_readfirstlane_b32 s47, v20 +; VI-NEXT: v_mov_b32_e32 v20, s20 +; VI-NEXT: v_writelane_b32 v21, s69, 21 +; VI-NEXT: v_readfirstlane_b32 s44, v20 +; VI-NEXT: v_mov_b32_e32 v20, s21 +; VI-NEXT: v_writelane_b32 v21, s70, 22 +; VI-NEXT: v_readfirstlane_b32 s45, v20 +; VI-NEXT: v_mov_b32_e32 v20, s22 +; VI-NEXT: v_writelane_b32 v21, s71, 23 +; VI-NEXT: v_readfirstlane_b32 s42, v20 +; VI-NEXT: v_mov_b32_e32 v20, s23 +; VI-NEXT: v_writelane_b32 v21, s80, 24 +; VI-NEXT: v_readfirstlane_b32 s43, v20 +; VI-NEXT: v_mov_b32_e32 v20, s24 +; VI-NEXT: v_writelane_b32 v21, s81, 25 +; VI-NEXT: v_readfirstlane_b32 s40, v20 +; VI-NEXT: v_mov_b32_e32 v20, s25 +; VI-NEXT: v_writelane_b32 v21, s82, 26 +; VI-NEXT: v_readfirstlane_b32 s41, v20 +; VI-NEXT: v_mov_b32_e32 v20, s26 +; VI-NEXT: v_writelane_b32 v21, s83, 27 +; VI-NEXT: v_readfirstlane_b32 s24, v20 +; VI-NEXT: v_mov_b32_e32 v20, s27 +; VI-NEXT: v_writelane_b32 v21, s84, 28 +; VI-NEXT: v_readfirstlane_b32 s25, v20 +; VI-NEXT: v_mov_b32_e32 v20, s28 +; VI-NEXT: v_writelane_b32 v21, s85, 29 +; VI-NEXT: v_readfirstlane_b32 s22, v20 +; VI-NEXT: v_mov_b32_e32 v20, s29 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; VI-NEXT: v_writelane_b32 v20, s86, 30 -; VI-NEXT: v_readfirstlane_b32 s44, v1 -; VI-NEXT: v_readfirstlane_b32 s45, v2 -; VI-NEXT: v_readfirstlane_b32 s42, v3 -; VI-NEXT: v_readfirstlane_b32 s43, v4 -; VI-NEXT: v_readfirstlane_b32 s40, v5 -; VI-NEXT: v_readfirstlane_b32 s41, v6 +; VI-NEXT: v_writelane_b32 v21, s86, 30 +; VI-NEXT: v_readfirstlane_b32 s23, v20 +; VI-NEXT: v_readfirstlane_b32 s20, v1 +; VI-NEXT: v_readfirstlane_b32 s21, v2 +; VI-NEXT: v_readfirstlane_b32 s18, v3 +; VI-NEXT: v_readfirstlane_b32 s19, v4 +; VI-NEXT: v_readfirstlane_b32 s16, v5 +; VI-NEXT: v_readfirstlane_b32 s17, v6 ; VI-NEXT: v_readfirstlane_b32 s14, v7 ; VI-NEXT: v_readfirstlane_b32 s15, v8 ; VI-NEXT: v_readfirstlane_b32 s12, v9 @@ -82592,190 +81609,190 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI-NEXT: v_readfirstlane_b32 s6, v15 ; VI-NEXT: v_readfirstlane_b32 s7, v16 ; VI-NEXT: v_readfirstlane_b32 s4, v17 -; VI-NEXT: s_and_b64 s[46:47], vcc, exec +; VI-NEXT: s_and_b64 s[26:27], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s5, v18 -; VI-NEXT: v_writelane_b32 v20, s87, 31 -; VI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane +; VI-NEXT: v_writelane_b32 v21, s87, 31 +; VI-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane ; VI-NEXT: s_cbranch_scc0 .LBB57_4 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_lshr_b32 s46, s5, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 8 -; VI-NEXT: s_lshr_b32 s46, s5, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 9 -; VI-NEXT: s_lshr_b32 s46, s5, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 10 -; VI-NEXT: s_lshr_b32 s46, s4, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 11 -; VI-NEXT: s_lshr_b32 s46, s4, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 12 -; VI-NEXT: s_lshr_b32 s46, s7, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 13 -; VI-NEXT: s_lshr_b32 s46, s7, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 14 -; VI-NEXT: s_lshr_b32 s46, s7, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 15 -; VI-NEXT: s_lshr_b32 s46, s6, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 16 -; VI-NEXT: s_lshr_b32 s46, s6, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 17 -; VI-NEXT: s_lshr_b32 s46, s9, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 18 -; VI-NEXT: s_lshr_b32 s46, s9, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 19 -; VI-NEXT: s_lshr_b32 s46, s9, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 20 -; VI-NEXT: s_lshr_b32 s46, s8, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 21 -; VI-NEXT: s_lshr_b32 s46, s8, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 22 -; VI-NEXT: s_lshr_b32 s46, s11, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 23 -; VI-NEXT: s_lshr_b32 s46, s11, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 24 -; VI-NEXT: s_lshr_b32 s46, s11, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 25 -; VI-NEXT: s_lshr_b32 s46, s10, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 26 -; VI-NEXT: s_lshr_b32 s46, s10, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 27 -; VI-NEXT: s_lshr_b32 s46, s13, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 28 -; VI-NEXT: s_lshr_b32 s46, s13, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 29 -; VI-NEXT: s_lshr_b32 s46, s13, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 30 -; VI-NEXT: s_lshr_b32 s46, s12, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 31 -; VI-NEXT: s_lshr_b32 s46, s12, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 32 -; VI-NEXT: s_lshr_b32 s46, s15, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 33 -; VI-NEXT: s_lshr_b32 s46, s15, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 34 -; VI-NEXT: s_lshr_b32 s46, s15, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 35 -; VI-NEXT: s_lshr_b32 s46, s14, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 36 -; VI-NEXT: s_lshr_b32 s46, s14, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 37 -; VI-NEXT: s_lshr_b32 s46, s41, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 38 -; VI-NEXT: s_lshr_b32 s46, s41, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 39 -; VI-NEXT: s_lshr_b32 s46, s41, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 40 -; VI-NEXT: s_lshr_b32 s46, s40, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 41 -; VI-NEXT: s_lshr_b32 s46, s40, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 42 -; VI-NEXT: s_lshr_b32 s46, s43, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 43 -; VI-NEXT: s_lshr_b32 s46, s43, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 44 -; VI-NEXT: s_lshr_b32 s46, s43, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 45 -; VI-NEXT: s_lshr_b32 s46, s42, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 46 -; VI-NEXT: s_lshr_b32 s46, s42, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 47 -; VI-NEXT: s_lshr_b32 s46, s45, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 48 -; VI-NEXT: s_lshr_b32 s46, s45, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 49 -; VI-NEXT: s_lshr_b32 s46, s45, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 50 -; VI-NEXT: s_lshr_b32 s46, s44, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 51 -; VI-NEXT: s_lshr_b32 s46, s44, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 52 -; VI-NEXT: s_lshr_b32 s46, s29, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 53 -; VI-NEXT: s_lshr_b32 s46, s29, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 54 -; VI-NEXT: s_lshr_b32 s46, s29, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 55 -; VI-NEXT: s_lshr_b32 s46, s28, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 56 -; VI-NEXT: s_lshr_b32 s46, s28, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 57 -; VI-NEXT: s_lshr_b32 s46, s27, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 58 -; VI-NEXT: s_lshr_b32 s46, s27, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 59 +; VI-NEXT: s_lshr_b32 s26, s5, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 8 +; VI-NEXT: s_lshr_b32 s26, s5, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 9 +; VI-NEXT: s_lshr_b32 s26, s5, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 10 +; VI-NEXT: s_lshr_b32 s26, s4, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 11 +; VI-NEXT: s_lshr_b32 s26, s4, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 12 +; VI-NEXT: s_lshr_b32 s26, s7, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 13 +; VI-NEXT: s_lshr_b32 s26, s7, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 14 +; VI-NEXT: s_lshr_b32 s26, s7, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 15 +; VI-NEXT: s_lshr_b32 s26, s6, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 16 +; VI-NEXT: s_lshr_b32 s26, s6, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 17 +; VI-NEXT: s_lshr_b32 s26, s9, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 18 +; VI-NEXT: s_lshr_b32 s26, s9, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 19 +; VI-NEXT: s_lshr_b32 s26, s9, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 20 +; VI-NEXT: s_lshr_b32 s26, s8, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 21 +; VI-NEXT: s_lshr_b32 s26, s8, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 22 +; VI-NEXT: s_lshr_b32 s26, s11, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 23 +; VI-NEXT: s_lshr_b32 s26, s11, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 24 +; VI-NEXT: s_lshr_b32 s26, s11, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 25 +; VI-NEXT: s_lshr_b32 s26, s10, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 26 +; VI-NEXT: s_lshr_b32 s26, s10, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 27 +; VI-NEXT: s_lshr_b32 s26, s13, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 28 +; VI-NEXT: s_lshr_b32 s26, s13, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 29 +; VI-NEXT: s_lshr_b32 s26, s13, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 30 +; VI-NEXT: s_lshr_b32 s26, s12, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 31 +; VI-NEXT: s_lshr_b32 s26, s12, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 32 +; VI-NEXT: s_lshr_b32 s26, s15, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 33 +; VI-NEXT: s_lshr_b32 s26, s15, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 34 +; VI-NEXT: s_lshr_b32 s26, s15, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 35 +; VI-NEXT: s_lshr_b32 s26, s14, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 36 +; VI-NEXT: s_lshr_b32 s26, s14, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 37 +; VI-NEXT: s_lshr_b32 s26, s17, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 38 +; VI-NEXT: s_lshr_b32 s26, s17, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 39 +; VI-NEXT: s_lshr_b32 s26, s17, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 40 +; VI-NEXT: s_lshr_b32 s26, s16, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 41 +; VI-NEXT: s_lshr_b32 s26, s16, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 42 +; VI-NEXT: s_lshr_b32 s26, s19, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 43 +; VI-NEXT: s_lshr_b32 s26, s19, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 44 +; VI-NEXT: s_lshr_b32 s26, s19, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 45 +; VI-NEXT: s_lshr_b32 s26, s18, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 46 +; VI-NEXT: s_lshr_b32 s26, s18, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 47 +; VI-NEXT: s_lshr_b32 s26, s21, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 48 +; VI-NEXT: s_lshr_b32 s26, s21, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 49 +; VI-NEXT: s_lshr_b32 s26, s21, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 50 +; VI-NEXT: s_lshr_b32 s26, s20, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 51 +; VI-NEXT: s_lshr_b32 s26, s20, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 52 +; VI-NEXT: s_lshr_b32 s26, s23, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 53 +; VI-NEXT: s_lshr_b32 s26, s23, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 54 +; VI-NEXT: s_lshr_b32 s26, s23, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 55 +; VI-NEXT: s_lshr_b32 s26, s22, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 56 +; VI-NEXT: s_lshr_b32 s26, s22, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 57 +; VI-NEXT: s_lshr_b32 s26, s25, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 58 +; VI-NEXT: s_lshr_b32 s26, s25, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 59 ; VI-NEXT: s_lshr_b64 s[60:61], s[4:5], 24 -; VI-NEXT: v_writelane_b32 v21, s60, 6 -; VI-NEXT: v_writelane_b32 v21, s61, 7 +; VI-NEXT: v_writelane_b32 v22, s60, 6 +; VI-NEXT: v_writelane_b32 v22, s61, 7 ; VI-NEXT: s_lshr_b64 s[60:61], s[6:7], 24 -; VI-NEXT: v_writelane_b32 v21, s60, 4 -; VI-NEXT: v_writelane_b32 v21, s61, 5 +; VI-NEXT: v_writelane_b32 v22, s60, 4 +; VI-NEXT: v_writelane_b32 v22, s61, 5 ; VI-NEXT: s_lshr_b64 s[60:61], s[8:9], 24 -; VI-NEXT: v_writelane_b32 v21, s60, 2 -; VI-NEXT: v_writelane_b32 v21, s61, 3 +; VI-NEXT: v_writelane_b32 v22, s60, 2 +; VI-NEXT: v_writelane_b32 v22, s61, 3 ; VI-NEXT: s_lshr_b64 s[60:61], s[10:11], 24 -; VI-NEXT: v_writelane_b32 v21, s60, 0 -; VI-NEXT: s_lshr_b32 s66, s27, 8 -; VI-NEXT: s_lshr_b32 s67, s26, 16 -; VI-NEXT: s_lshr_b32 s68, s26, 8 -; VI-NEXT: s_lshr_b32 s69, s25, 24 -; VI-NEXT: s_lshr_b32 s70, s25, 16 -; VI-NEXT: s_lshr_b32 s71, s25, 8 -; VI-NEXT: s_lshr_b32 s80, s24, 16 -; VI-NEXT: s_lshr_b32 s81, s24, 8 -; VI-NEXT: s_lshr_b32 s82, s23, 24 -; VI-NEXT: s_lshr_b32 s83, s23, 16 -; VI-NEXT: s_lshr_b32 s84, s23, 8 -; VI-NEXT: s_lshr_b32 s85, s22, 16 -; VI-NEXT: s_lshr_b32 s86, s22, 8 -; VI-NEXT: s_lshr_b32 s87, s21, 24 -; VI-NEXT: s_lshr_b32 s50, s21, 16 -; VI-NEXT: s_lshr_b32 s46, s21, 8 -; VI-NEXT: s_lshr_b32 s47, s20, 16 -; VI-NEXT: s_lshr_b32 s56, s20, 8 -; VI-NEXT: s_lshr_b32 s57, s19, 24 -; VI-NEXT: s_lshr_b32 s51, s19, 16 -; VI-NEXT: s_lshr_b32 s52, s19, 8 -; VI-NEXT: s_lshr_b32 s53, s18, 16 -; VI-NEXT: s_lshr_b32 s54, s18, 8 -; VI-NEXT: s_lshr_b32 s58, s17, 24 -; VI-NEXT: s_lshr_b32 s59, s17, 16 -; VI-NEXT: s_lshr_b32 s55, s17, 8 -; VI-NEXT: s_lshr_b32 s64, s16, 16 -; VI-NEXT: s_lshr_b32 s65, s16, 8 -; VI-NEXT: v_writelane_b32 v21, s61, 1 +; VI-NEXT: v_writelane_b32 v22, s60, 0 +; VI-NEXT: s_lshr_b32 s66, s25, 8 +; VI-NEXT: s_lshr_b32 s67, s24, 16 +; VI-NEXT: s_lshr_b32 s68, s24, 8 +; VI-NEXT: s_lshr_b32 s69, s41, 24 +; VI-NEXT: s_lshr_b32 s70, s41, 16 +; VI-NEXT: s_lshr_b32 s71, s41, 8 +; VI-NEXT: s_lshr_b32 s80, s40, 16 +; VI-NEXT: s_lshr_b32 s81, s40, 8 +; VI-NEXT: s_lshr_b32 s82, s43, 24 +; VI-NEXT: s_lshr_b32 s83, s43, 16 +; VI-NEXT: s_lshr_b32 s84, s43, 8 +; VI-NEXT: s_lshr_b32 s85, s42, 16 +; VI-NEXT: s_lshr_b32 s86, s42, 8 +; VI-NEXT: s_lshr_b32 s87, s45, 24 +; VI-NEXT: s_lshr_b32 s50, s45, 16 +; VI-NEXT: s_lshr_b32 s26, s45, 8 +; VI-NEXT: s_lshr_b32 s27, s44, 16 +; VI-NEXT: s_lshr_b32 s28, s44, 8 +; VI-NEXT: s_lshr_b32 s29, s47, 24 +; VI-NEXT: s_lshr_b32 s51, s47, 16 +; VI-NEXT: s_lshr_b32 s52, s47, 8 +; VI-NEXT: s_lshr_b32 s53, s46, 16 +; VI-NEXT: s_lshr_b32 s54, s46, 8 +; VI-NEXT: s_lshr_b32 s58, s57, 24 +; VI-NEXT: s_lshr_b32 s59, s57, 16 +; VI-NEXT: s_lshr_b32 s55, s57, 8 +; VI-NEXT: s_lshr_b32 s64, s56, 16 +; VI-NEXT: s_lshr_b32 s65, s56, 8 +; VI-NEXT: v_writelane_b32 v22, s61, 1 ; VI-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 ; VI-NEXT: s_lshr_b64 s[72:73], s[14:15], 24 -; VI-NEXT: s_lshr_b64 s[74:75], s[40:41], 24 -; VI-NEXT: s_lshr_b64 s[76:77], s[42:43], 24 -; VI-NEXT: s_lshr_b64 s[78:79], s[44:45], 24 -; VI-NEXT: s_lshr_b64 s[88:89], s[28:29], 24 -; VI-NEXT: s_lshr_b64 s[90:91], s[26:27], 24 -; VI-NEXT: s_lshr_b64 s[30:31], s[24:25], 24 -; VI-NEXT: s_lshr_b64 s[34:35], s[22:23], 24 -; VI-NEXT: s_lshr_b64 s[36:37], s[20:21], 24 -; VI-NEXT: s_lshr_b64 s[38:39], s[18:19], 24 -; VI-NEXT: s_lshr_b64 s[48:49], s[16:17], 24 +; VI-NEXT: s_lshr_b64 s[74:75], s[16:17], 24 +; VI-NEXT: s_lshr_b64 s[76:77], s[18:19], 24 +; VI-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 +; VI-NEXT: s_lshr_b64 s[88:89], s[22:23], 24 +; VI-NEXT: s_lshr_b64 s[90:91], s[24:25], 24 +; VI-NEXT: s_lshr_b64 s[30:31], s[40:41], 24 +; VI-NEXT: s_lshr_b64 s[34:35], s[42:43], 24 +; VI-NEXT: s_lshr_b64 s[36:37], s[44:45], 24 +; VI-NEXT: s_lshr_b64 s[38:39], s[46:47], 24 +; VI-NEXT: s_lshr_b64 s[48:49], s[56:57], 24 ; VI-NEXT: s_cbranch_execnz .LBB57_3 ; VI-NEXT: .LBB57_2: ; %cmp.true -; VI-NEXT: s_add_u32 s16, s16, 3 -; VI-NEXT: s_addc_u32 s17, s17, 0 -; VI-NEXT: s_add_u32 s18, s18, 3 -; VI-NEXT: s_addc_u32 s19, s19, 0 -; VI-NEXT: s_add_u32 s20, s20, 3 -; VI-NEXT: s_addc_u32 s21, s21, 0 -; VI-NEXT: s_add_u32 s22, s22, 3 -; VI-NEXT: s_addc_u32 s23, s23, 0 -; VI-NEXT: s_add_u32 s24, s24, 3 -; VI-NEXT: s_addc_u32 s25, s25, 0 -; VI-NEXT: s_add_u32 s26, s26, 3 -; VI-NEXT: s_addc_u32 s27, s27, 0 -; VI-NEXT: s_add_u32 s28, s28, 3 -; VI-NEXT: s_addc_u32 s29, s29, 0 +; VI-NEXT: s_add_u32 s56, s56, 3 +; VI-NEXT: s_addc_u32 s57, s57, 0 +; VI-NEXT: s_add_u32 s46, s46, 3 +; VI-NEXT: s_addc_u32 s47, s47, 0 ; VI-NEXT: s_add_u32 s44, s44, 3 ; VI-NEXT: s_addc_u32 s45, s45, 0 ; VI-NEXT: s_add_u32 s42, s42, 3 ; VI-NEXT: s_addc_u32 s43, s43, 0 ; VI-NEXT: s_add_u32 s40, s40, 3 ; VI-NEXT: s_addc_u32 s41, s41, 0 +; VI-NEXT: s_add_u32 s24, s24, 3 +; VI-NEXT: s_addc_u32 s25, s25, 0 +; VI-NEXT: s_add_u32 s22, s22, 3 +; VI-NEXT: s_addc_u32 s23, s23, 0 +; VI-NEXT: s_add_u32 s20, s20, 3 +; VI-NEXT: s_addc_u32 s21, s21, 0 +; VI-NEXT: s_add_u32 s18, s18, 3 +; VI-NEXT: s_addc_u32 s19, s19, 0 +; VI-NEXT: s_add_u32 s16, s16, 3 +; VI-NEXT: s_addc_u32 s17, s17, 0 ; VI-NEXT: s_add_u32 s14, s14, 3 ; VI-NEXT: s_addc_u32 s15, s15, 0 ; VI-NEXT: s_add_u32 s12, s12, 3 @@ -82788,413 +81805,413 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI-NEXT: s_addc_u32 s7, s7, 0 ; VI-NEXT: s_add_u32 s4, s4, 3 ; VI-NEXT: s_addc_u32 s5, s5, 0 -; VI-NEXT: s_lshr_b32 s46, s5, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 8 -; VI-NEXT: s_lshr_b32 s46, s5, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 9 -; VI-NEXT: s_lshr_b32 s46, s5, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 10 -; VI-NEXT: s_lshr_b32 s46, s4, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 11 -; VI-NEXT: s_lshr_b32 s46, s4, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 12 -; VI-NEXT: s_lshr_b32 s46, s7, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 13 -; VI-NEXT: s_lshr_b32 s46, s7, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 14 -; VI-NEXT: s_lshr_b32 s46, s7, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 15 -; VI-NEXT: s_lshr_b32 s46, s6, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 16 -; VI-NEXT: s_lshr_b32 s46, s6, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 17 -; VI-NEXT: s_lshr_b32 s46, s9, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 18 -; VI-NEXT: s_lshr_b32 s46, s9, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 19 -; VI-NEXT: s_lshr_b32 s46, s9, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 20 -; VI-NEXT: s_lshr_b32 s46, s8, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 21 -; VI-NEXT: s_lshr_b32 s46, s8, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 22 -; VI-NEXT: s_lshr_b32 s46, s11, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 23 -; VI-NEXT: s_lshr_b32 s46, s11, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 24 -; VI-NEXT: s_lshr_b32 s46, s11, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 25 -; VI-NEXT: s_lshr_b32 s46, s10, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 26 -; VI-NEXT: s_lshr_b32 s46, s10, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 27 -; VI-NEXT: s_lshr_b32 s46, s13, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 28 -; VI-NEXT: s_lshr_b32 s46, s13, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 29 -; VI-NEXT: s_lshr_b32 s46, s13, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 30 -; VI-NEXT: s_lshr_b32 s46, s12, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 31 -; VI-NEXT: s_lshr_b32 s46, s12, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 32 -; VI-NEXT: s_lshr_b32 s46, s15, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 33 -; VI-NEXT: s_lshr_b32 s46, s15, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 34 -; VI-NEXT: s_lshr_b32 s46, s15, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 35 -; VI-NEXT: s_lshr_b32 s46, s14, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 36 -; VI-NEXT: s_lshr_b32 s46, s14, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 37 -; VI-NEXT: s_lshr_b32 s46, s41, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 38 -; VI-NEXT: s_lshr_b32 s46, s41, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 39 -; VI-NEXT: s_lshr_b32 s46, s41, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 40 -; VI-NEXT: s_lshr_b32 s46, s40, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 41 -; VI-NEXT: s_lshr_b32 s46, s40, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 42 -; VI-NEXT: s_lshr_b32 s46, s43, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 43 -; VI-NEXT: s_lshr_b32 s46, s43, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 44 -; VI-NEXT: s_lshr_b32 s46, s43, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 45 -; VI-NEXT: s_lshr_b32 s46, s42, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 46 -; VI-NEXT: s_lshr_b32 s46, s42, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 47 -; VI-NEXT: s_lshr_b32 s46, s45, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 48 -; VI-NEXT: s_lshr_b32 s46, s45, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 49 -; VI-NEXT: s_lshr_b32 s46, s45, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 50 -; VI-NEXT: s_lshr_b32 s46, s44, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 51 -; VI-NEXT: s_lshr_b32 s46, s44, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 52 -; VI-NEXT: s_lshr_b32 s46, s29, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 53 -; VI-NEXT: s_lshr_b32 s46, s29, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 54 -; VI-NEXT: s_lshr_b32 s46, s29, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 55 -; VI-NEXT: s_lshr_b32 s46, s28, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 56 -; VI-NEXT: s_lshr_b32 s46, s28, 8 -; VI-NEXT: v_writelane_b32 v21, s46, 57 -; VI-NEXT: s_lshr_b32 s46, s27, 24 -; VI-NEXT: v_writelane_b32 v21, s46, 58 -; VI-NEXT: s_lshr_b32 s46, s27, 16 -; VI-NEXT: v_writelane_b32 v21, s46, 59 +; VI-NEXT: s_lshr_b32 s26, s5, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 8 +; VI-NEXT: s_lshr_b32 s26, s5, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 9 +; VI-NEXT: s_lshr_b32 s26, s5, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 10 +; VI-NEXT: s_lshr_b32 s26, s4, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 11 +; VI-NEXT: s_lshr_b32 s26, s4, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 12 +; VI-NEXT: s_lshr_b32 s26, s7, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 13 +; VI-NEXT: s_lshr_b32 s26, s7, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 14 +; VI-NEXT: s_lshr_b32 s26, s7, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 15 +; VI-NEXT: s_lshr_b32 s26, s6, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 16 +; VI-NEXT: s_lshr_b32 s26, s6, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 17 +; VI-NEXT: s_lshr_b32 s26, s9, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 18 +; VI-NEXT: s_lshr_b32 s26, s9, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 19 +; VI-NEXT: s_lshr_b32 s26, s9, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 20 +; VI-NEXT: s_lshr_b32 s26, s8, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 21 +; VI-NEXT: s_lshr_b32 s26, s8, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 22 +; VI-NEXT: s_lshr_b32 s26, s11, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 23 +; VI-NEXT: s_lshr_b32 s26, s11, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 24 +; VI-NEXT: s_lshr_b32 s26, s11, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 25 +; VI-NEXT: s_lshr_b32 s26, s10, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 26 +; VI-NEXT: s_lshr_b32 s26, s10, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 27 +; VI-NEXT: s_lshr_b32 s26, s13, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 28 +; VI-NEXT: s_lshr_b32 s26, s13, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 29 +; VI-NEXT: s_lshr_b32 s26, s13, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 30 +; VI-NEXT: s_lshr_b32 s26, s12, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 31 +; VI-NEXT: s_lshr_b32 s26, s12, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 32 +; VI-NEXT: s_lshr_b32 s26, s15, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 33 +; VI-NEXT: s_lshr_b32 s26, s15, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 34 +; VI-NEXT: s_lshr_b32 s26, s15, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 35 +; VI-NEXT: s_lshr_b32 s26, s14, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 36 +; VI-NEXT: s_lshr_b32 s26, s14, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 37 +; VI-NEXT: s_lshr_b32 s26, s17, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 38 +; VI-NEXT: s_lshr_b32 s26, s17, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 39 +; VI-NEXT: s_lshr_b32 s26, s17, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 40 +; VI-NEXT: s_lshr_b32 s26, s16, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 41 +; VI-NEXT: s_lshr_b32 s26, s16, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 42 +; VI-NEXT: s_lshr_b32 s26, s19, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 43 +; VI-NEXT: s_lshr_b32 s26, s19, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 44 +; VI-NEXT: s_lshr_b32 s26, s19, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 45 +; VI-NEXT: s_lshr_b32 s26, s18, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 46 +; VI-NEXT: s_lshr_b32 s26, s18, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 47 +; VI-NEXT: s_lshr_b32 s26, s21, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 48 +; VI-NEXT: s_lshr_b32 s26, s21, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 49 +; VI-NEXT: s_lshr_b32 s26, s21, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 50 +; VI-NEXT: s_lshr_b32 s26, s20, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 51 +; VI-NEXT: s_lshr_b32 s26, s20, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 52 +; VI-NEXT: s_lshr_b32 s26, s23, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 53 +; VI-NEXT: s_lshr_b32 s26, s23, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 54 +; VI-NEXT: s_lshr_b32 s26, s23, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 55 +; VI-NEXT: s_lshr_b32 s26, s22, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 56 +; VI-NEXT: s_lshr_b32 s26, s22, 8 +; VI-NEXT: v_writelane_b32 v22, s26, 57 +; VI-NEXT: s_lshr_b32 s26, s25, 24 +; VI-NEXT: v_writelane_b32 v22, s26, 58 +; VI-NEXT: s_lshr_b32 s26, s25, 16 +; VI-NEXT: v_writelane_b32 v22, s26, 59 ; VI-NEXT: s_lshr_b64 s[60:61], s[4:5], 24 -; VI-NEXT: v_writelane_b32 v21, s60, 6 -; VI-NEXT: v_writelane_b32 v21, s61, 7 +; VI-NEXT: v_writelane_b32 v22, s60, 6 +; VI-NEXT: v_writelane_b32 v22, s61, 7 ; VI-NEXT: s_lshr_b64 s[60:61], s[6:7], 24 -; VI-NEXT: v_writelane_b32 v21, s60, 4 -; VI-NEXT: v_writelane_b32 v21, s61, 5 +; VI-NEXT: v_writelane_b32 v22, s60, 4 +; VI-NEXT: v_writelane_b32 v22, s61, 5 ; VI-NEXT: s_lshr_b64 s[60:61], s[8:9], 24 -; VI-NEXT: v_writelane_b32 v21, s60, 2 -; VI-NEXT: v_writelane_b32 v21, s61, 3 +; VI-NEXT: v_writelane_b32 v22, s60, 2 +; VI-NEXT: v_writelane_b32 v22, s61, 3 ; VI-NEXT: s_lshr_b64 s[60:61], s[10:11], 24 -; VI-NEXT: s_lshr_b32 s66, s27, 8 -; VI-NEXT: s_lshr_b32 s67, s26, 16 -; VI-NEXT: s_lshr_b32 s68, s26, 8 -; VI-NEXT: s_lshr_b32 s69, s25, 24 -; VI-NEXT: s_lshr_b32 s70, s25, 16 -; VI-NEXT: s_lshr_b32 s71, s25, 8 -; VI-NEXT: s_lshr_b32 s80, s24, 16 -; VI-NEXT: s_lshr_b32 s81, s24, 8 -; VI-NEXT: s_lshr_b32 s82, s23, 24 -; VI-NEXT: s_lshr_b32 s83, s23, 16 -; VI-NEXT: s_lshr_b32 s84, s23, 8 -; VI-NEXT: s_lshr_b32 s85, s22, 16 -; VI-NEXT: s_lshr_b32 s86, s22, 8 -; VI-NEXT: s_lshr_b32 s87, s21, 24 -; VI-NEXT: s_lshr_b32 s50, s21, 16 -; VI-NEXT: s_lshr_b32 s46, s21, 8 -; VI-NEXT: s_lshr_b32 s47, s20, 16 -; VI-NEXT: s_lshr_b32 s56, s20, 8 -; VI-NEXT: s_lshr_b32 s57, s19, 24 -; VI-NEXT: s_lshr_b32 s51, s19, 16 -; VI-NEXT: s_lshr_b32 s52, s19, 8 -; VI-NEXT: s_lshr_b32 s53, s18, 16 -; VI-NEXT: s_lshr_b32 s54, s18, 8 -; VI-NEXT: s_lshr_b32 s58, s17, 24 -; VI-NEXT: s_lshr_b32 s59, s17, 16 -; VI-NEXT: s_lshr_b32 s55, s17, 8 -; VI-NEXT: s_lshr_b32 s64, s16, 16 -; VI-NEXT: s_lshr_b32 s65, s16, 8 -; VI-NEXT: v_writelane_b32 v21, s60, 0 +; VI-NEXT: s_lshr_b32 s66, s25, 8 +; VI-NEXT: s_lshr_b32 s67, s24, 16 +; VI-NEXT: s_lshr_b32 s68, s24, 8 +; VI-NEXT: s_lshr_b32 s69, s41, 24 +; VI-NEXT: s_lshr_b32 s70, s41, 16 +; VI-NEXT: s_lshr_b32 s71, s41, 8 +; VI-NEXT: s_lshr_b32 s80, s40, 16 +; VI-NEXT: s_lshr_b32 s81, s40, 8 +; VI-NEXT: s_lshr_b32 s82, s43, 24 +; VI-NEXT: s_lshr_b32 s83, s43, 16 +; VI-NEXT: s_lshr_b32 s84, s43, 8 +; VI-NEXT: s_lshr_b32 s85, s42, 16 +; VI-NEXT: s_lshr_b32 s86, s42, 8 +; VI-NEXT: s_lshr_b32 s87, s45, 24 +; VI-NEXT: s_lshr_b32 s50, s45, 16 +; VI-NEXT: s_lshr_b32 s26, s45, 8 +; VI-NEXT: s_lshr_b32 s27, s44, 16 +; VI-NEXT: s_lshr_b32 s28, s44, 8 +; VI-NEXT: s_lshr_b32 s29, s47, 24 +; VI-NEXT: s_lshr_b32 s51, s47, 16 +; VI-NEXT: s_lshr_b32 s52, s47, 8 +; VI-NEXT: s_lshr_b32 s53, s46, 16 +; VI-NEXT: s_lshr_b32 s54, s46, 8 +; VI-NEXT: s_lshr_b32 s58, s57, 24 +; VI-NEXT: s_lshr_b32 s59, s57, 16 +; VI-NEXT: s_lshr_b32 s55, s57, 8 +; VI-NEXT: s_lshr_b32 s64, s56, 16 +; VI-NEXT: s_lshr_b32 s65, s56, 8 +; VI-NEXT: v_writelane_b32 v22, s60, 0 ; VI-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 ; VI-NEXT: s_lshr_b64 s[72:73], s[14:15], 24 -; VI-NEXT: s_lshr_b64 s[74:75], s[40:41], 24 -; VI-NEXT: s_lshr_b64 s[76:77], s[42:43], 24 -; VI-NEXT: s_lshr_b64 s[78:79], s[44:45], 24 -; VI-NEXT: s_lshr_b64 s[88:89], s[28:29], 24 -; VI-NEXT: s_lshr_b64 s[90:91], s[26:27], 24 -; VI-NEXT: s_lshr_b64 s[30:31], s[24:25], 24 -; VI-NEXT: s_lshr_b64 s[34:35], s[22:23], 24 -; VI-NEXT: s_lshr_b64 s[36:37], s[20:21], 24 -; VI-NEXT: s_lshr_b64 s[38:39], s[18:19], 24 -; VI-NEXT: s_lshr_b64 s[48:49], s[16:17], 24 -; VI-NEXT: v_writelane_b32 v21, s61, 1 +; VI-NEXT: s_lshr_b64 s[74:75], s[16:17], 24 +; VI-NEXT: s_lshr_b64 s[76:77], s[18:19], 24 +; VI-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 +; VI-NEXT: s_lshr_b64 s[88:89], s[22:23], 24 +; VI-NEXT: s_lshr_b64 s[90:91], s[24:25], 24 +; VI-NEXT: s_lshr_b64 s[30:31], s[40:41], 24 +; VI-NEXT: s_lshr_b64 s[34:35], s[42:43], 24 +; VI-NEXT: s_lshr_b64 s[36:37], s[44:45], 24 +; VI-NEXT: s_lshr_b64 s[38:39], s[46:47], 24 +; VI-NEXT: s_lshr_b64 s[48:49], s[56:57], 24 +; VI-NEXT: v_writelane_b32 v22, s61, 1 ; VI-NEXT: .LBB57_3: ; %end ; VI-NEXT: s_lshl_b32 s61, s65, 8 -; VI-NEXT: s_and_b32 s16, s16, 0xff -; VI-NEXT: s_or_b32 s16, s16, s61 +; VI-NEXT: s_and_b32 s56, s56, 0xff +; VI-NEXT: s_or_b32 s56, s56, s61 ; VI-NEXT: s_lshl_b32 s61, s48, 8 ; VI-NEXT: s_and_b32 s63, s64, 0xff ; VI-NEXT: s_or_b32 s61, s63, s61 -; VI-NEXT: s_and_b32 s16, s16, 0xffff +; VI-NEXT: s_and_b32 s56, s56, 0xffff ; VI-NEXT: s_lshl_b32 s61, s61, 16 -; VI-NEXT: s_or_b32 s16, s16, s61 -; VI-NEXT: v_mov_b32_e32 v1, s16 -; VI-NEXT: s_and_b32 s16, s17, 0xff -; VI-NEXT: s_lshl_b32 s17, s55, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, s59, 0xff +; VI-NEXT: s_or_b32 s56, s56, s61 +; VI-NEXT: v_mov_b32_e32 v1, s56 +; VI-NEXT: s_and_b32 s56, s57, 0xff +; VI-NEXT: s_lshl_b32 s57, s55, 8 +; VI-NEXT: s_or_b32 s56, s56, s57 +; VI-NEXT: s_and_b32 s57, s59, 0xff ; VI-NEXT: s_lshl_b32 s58, s58, 8 -; VI-NEXT: s_or_b32 s17, s17, s58 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: s_lshl_b32 s16, s54, 8 -; VI-NEXT: s_and_b32 s17, s18, 0xff -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s38, 8 -; VI-NEXT: s_and_b32 s18, s53, 0xff -; VI-NEXT: s_or_b32 s17, s18, s17 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v3, s16 -; VI-NEXT: s_and_b32 s16, s19, 0xff -; VI-NEXT: s_lshl_b32 s17, s52, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, s51, 0xff -; VI-NEXT: s_lshl_b32 s18, s57, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v4, s16 -; VI-NEXT: s_lshl_b32 s16, s56, 8 -; VI-NEXT: s_and_b32 s17, s20, 0xff -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s36, 8 -; VI-NEXT: s_and_b32 s18, s47, 0xff -; VI-NEXT: s_or_b32 s17, s18, s17 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v5, s16 -; VI-NEXT: s_and_b32 s16, s21, 0xff -; VI-NEXT: s_lshl_b32 s17, s46, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, s50, 0xff -; VI-NEXT: s_lshl_b32 s18, s87, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v6, s16 -; VI-NEXT: s_lshl_b32 s16, s86, 8 -; VI-NEXT: s_and_b32 s17, s22, 0xff -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s34, 8 -; VI-NEXT: s_and_b32 s18, s85, 0xff -; VI-NEXT: s_or_b32 s17, s18, s17 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v7, s16 -; VI-NEXT: s_and_b32 s16, s23, 0xff -; VI-NEXT: s_lshl_b32 s17, s84, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, s83, 0xff -; VI-NEXT: s_lshl_b32 s18, s82, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v8, s16 -; VI-NEXT: s_lshl_b32 s16, s81, 8 -; VI-NEXT: s_and_b32 s17, s24, 0xff -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s30, 8 -; VI-NEXT: s_and_b32 s18, s80, 0xff -; VI-NEXT: s_or_b32 s17, s18, s17 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v9, s16 -; VI-NEXT: s_and_b32 s16, s25, 0xff -; VI-NEXT: s_lshl_b32 s17, s71, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, s70, 0xff -; VI-NEXT: s_lshl_b32 s18, s69, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v10, s16 -; VI-NEXT: s_lshl_b32 s16, s68, 8 -; VI-NEXT: s_and_b32 s17, s26, 0xff -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s90, 8 -; VI-NEXT: s_and_b32 s18, s67, 0xff -; VI-NEXT: s_or_b32 s17, s18, s17 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v11, s16 -; VI-NEXT: s_and_b32 s16, s27, 0xff -; VI-NEXT: s_lshl_b32 s17, s66, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 59 -; VI-NEXT: v_readlane_b32 s18, v21, 58 -; VI-NEXT: s_and_b32 s17, s17, 0xff -; VI-NEXT: s_lshl_b32 s18, s18, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v12, s16 -; VI-NEXT: v_readlane_b32 s16, v21, 57 -; VI-NEXT: s_lshl_b32 s16, s16, 8 -; VI-NEXT: s_and_b32 s17, s28, 0xff -; VI-NEXT: v_readlane_b32 s18, v21, 56 -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s88, 8 -; VI-NEXT: s_and_b32 s18, s18, 0xff -; VI-NEXT: s_or_b32 s17, s18, s17 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 55 -; VI-NEXT: v_mov_b32_e32 v13, s16 -; VI-NEXT: s_and_b32 s16, s29, 0xff -; VI-NEXT: s_lshl_b32 s17, s17, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 54 -; VI-NEXT: v_readlane_b32 s18, v21, 53 -; VI-NEXT: s_and_b32 s17, s17, 0xff -; VI-NEXT: s_lshl_b32 s18, s18, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v14, s16 -; VI-NEXT: v_readlane_b32 s16, v21, 52 -; VI-NEXT: s_lshl_b32 s16, s16, 8 -; VI-NEXT: s_and_b32 s17, s44, 0xff -; VI-NEXT: v_readlane_b32 s18, v21, 51 -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s78, 8 -; VI-NEXT: s_and_b32 s18, s18, 0xff -; VI-NEXT: s_or_b32 s17, s18, s17 +; VI-NEXT: s_or_b32 s57, s57, s58 +; VI-NEXT: s_and_b32 s56, s56, 0xffff +; VI-NEXT: s_lshl_b32 s57, s57, 16 +; VI-NEXT: s_or_b32 s56, s56, s57 +; VI-NEXT: v_mov_b32_e32 v2, s56 +; VI-NEXT: s_lshl_b32 s56, s54, 8 +; VI-NEXT: s_and_b32 s46, s46, 0xff +; VI-NEXT: s_or_b32 s46, s46, s56 +; VI-NEXT: s_lshl_b32 s56, s38, 8 +; VI-NEXT: s_and_b32 s57, s53, 0xff +; VI-NEXT: s_or_b32 s56, s57, s56 +; VI-NEXT: s_and_b32 s46, s46, 0xffff +; VI-NEXT: s_lshl_b32 s56, s56, 16 +; VI-NEXT: s_or_b32 s46, s46, s56 +; VI-NEXT: v_mov_b32_e32 v3, s46 +; VI-NEXT: s_and_b32 s46, s47, 0xff +; VI-NEXT: s_lshl_b32 s47, s52, 8 +; VI-NEXT: s_or_b32 s46, s46, s47 +; VI-NEXT: s_and_b32 s47, s51, 0xff +; VI-NEXT: s_lshl_b32 s29, s29, 8 +; VI-NEXT: s_or_b32 s29, s47, s29 +; VI-NEXT: s_and_b32 s46, s46, 0xffff +; VI-NEXT: s_lshl_b32 s29, s29, 16 +; VI-NEXT: s_or_b32 s29, s46, s29 +; VI-NEXT: v_mov_b32_e32 v4, s29 +; VI-NEXT: s_lshl_b32 s28, s28, 8 +; VI-NEXT: s_and_b32 s29, s44, 0xff +; VI-NEXT: s_or_b32 s28, s29, s28 +; VI-NEXT: s_lshl_b32 s29, s36, 8 +; VI-NEXT: s_and_b32 s27, s27, 0xff +; VI-NEXT: s_or_b32 s27, s27, s29 +; VI-NEXT: s_and_b32 s28, s28, 0xffff +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s27, s28, s27 +; VI-NEXT: v_mov_b32_e32 v5, s27 +; VI-NEXT: s_and_b32 s27, s45, 0xff +; VI-NEXT: s_lshl_b32 s26, s26, 8 +; VI-NEXT: s_or_b32 s26, s27, s26 +; VI-NEXT: s_and_b32 s27, s50, 0xff +; VI-NEXT: s_lshl_b32 s28, s87, 8 +; VI-NEXT: s_or_b32 s27, s27, s28 +; VI-NEXT: s_and_b32 s26, s26, 0xffff +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s26, s26, s27 +; VI-NEXT: v_mov_b32_e32 v6, s26 +; VI-NEXT: s_lshl_b32 s26, s86, 8 +; VI-NEXT: s_and_b32 s27, s42, 0xff +; VI-NEXT: s_or_b32 s26, s27, s26 +; VI-NEXT: s_lshl_b32 s27, s34, 8 +; VI-NEXT: s_and_b32 s28, s85, 0xff +; VI-NEXT: s_or_b32 s27, s28, s27 +; VI-NEXT: s_and_b32 s26, s26, 0xffff +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s26, s26, s27 +; VI-NEXT: v_mov_b32_e32 v7, s26 +; VI-NEXT: s_and_b32 s26, s43, 0xff +; VI-NEXT: s_lshl_b32 s27, s84, 8 +; VI-NEXT: s_or_b32 s26, s26, s27 +; VI-NEXT: s_and_b32 s27, s83, 0xff +; VI-NEXT: s_lshl_b32 s28, s82, 8 +; VI-NEXT: s_or_b32 s27, s27, s28 +; VI-NEXT: s_and_b32 s26, s26, 0xffff +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s26, s26, s27 +; VI-NEXT: v_mov_b32_e32 v8, s26 +; VI-NEXT: s_lshl_b32 s26, s81, 8 +; VI-NEXT: s_and_b32 s27, s40, 0xff +; VI-NEXT: s_or_b32 s26, s27, s26 +; VI-NEXT: s_lshl_b32 s27, s30, 8 +; VI-NEXT: s_and_b32 s28, s80, 0xff +; VI-NEXT: s_or_b32 s27, s28, s27 +; VI-NEXT: s_and_b32 s26, s26, 0xffff +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s26, s26, s27 +; VI-NEXT: v_mov_b32_e32 v9, s26 +; VI-NEXT: s_and_b32 s26, s41, 0xff +; VI-NEXT: s_lshl_b32 s27, s71, 8 +; VI-NEXT: s_or_b32 s26, s26, s27 +; VI-NEXT: s_and_b32 s27, s70, 0xff +; VI-NEXT: s_lshl_b32 s28, s69, 8 +; VI-NEXT: s_or_b32 s27, s27, s28 +; VI-NEXT: s_and_b32 s26, s26, 0xffff +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s26, s26, s27 +; VI-NEXT: v_mov_b32_e32 v10, s26 +; VI-NEXT: s_lshl_b32 s26, s68, 8 +; VI-NEXT: s_and_b32 s24, s24, 0xff +; VI-NEXT: s_or_b32 s24, s24, s26 +; VI-NEXT: s_lshl_b32 s26, s90, 8 +; VI-NEXT: s_and_b32 s27, s67, 0xff +; VI-NEXT: s_or_b32 s26, s27, s26 +; VI-NEXT: s_and_b32 s24, s24, 0xffff +; VI-NEXT: s_lshl_b32 s26, s26, 16 +; VI-NEXT: s_or_b32 s24, s24, s26 +; VI-NEXT: v_mov_b32_e32 v11, s24 +; VI-NEXT: s_and_b32 s24, s25, 0xff +; VI-NEXT: s_lshl_b32 s25, s66, 8 +; VI-NEXT: s_or_b32 s24, s24, s25 +; VI-NEXT: v_readlane_b32 s25, v22, 59 +; VI-NEXT: v_readlane_b32 s26, v22, 58 +; VI-NEXT: s_and_b32 s25, s25, 0xff +; VI-NEXT: s_lshl_b32 s26, s26, 8 +; VI-NEXT: s_or_b32 s25, s25, s26 +; VI-NEXT: s_and_b32 s24, s24, 0xffff +; VI-NEXT: s_lshl_b32 s25, s25, 16 +; VI-NEXT: s_or_b32 s24, s24, s25 +; VI-NEXT: v_mov_b32_e32 v12, s24 +; VI-NEXT: v_readlane_b32 s24, v22, 57 +; VI-NEXT: s_lshl_b32 s24, s24, 8 +; VI-NEXT: s_and_b32 s22, s22, 0xff +; VI-NEXT: v_readlane_b32 s25, v22, 56 +; VI-NEXT: s_or_b32 s22, s22, s24 +; VI-NEXT: s_lshl_b32 s24, s88, 8 +; VI-NEXT: s_and_b32 s25, s25, 0xff +; VI-NEXT: s_or_b32 s24, s25, s24 +; VI-NEXT: s_and_b32 s22, s22, 0xffff +; VI-NEXT: s_lshl_b32 s24, s24, 16 +; VI-NEXT: s_or_b32 s22, s22, s24 +; VI-NEXT: v_mov_b32_e32 v13, s22 +; VI-NEXT: s_and_b32 s22, s23, 0xff +; VI-NEXT: v_readlane_b32 s23, v22, 55 +; VI-NEXT: s_lshl_b32 s23, s23, 8 +; VI-NEXT: s_or_b32 s22, s22, s23 +; VI-NEXT: v_readlane_b32 s23, v22, 54 +; VI-NEXT: v_readlane_b32 s24, v22, 53 +; VI-NEXT: s_and_b32 s23, s23, 0xff +; VI-NEXT: s_lshl_b32 s24, s24, 8 +; VI-NEXT: s_or_b32 s23, s23, s24 +; VI-NEXT: s_and_b32 s22, s22, 0xffff +; VI-NEXT: s_lshl_b32 s23, s23, 16 +; VI-NEXT: s_or_b32 s22, s22, s23 +; VI-NEXT: v_mov_b32_e32 v14, s22 +; VI-NEXT: v_readlane_b32 s22, v22, 52 +; VI-NEXT: s_lshl_b32 s22, s22, 8 +; VI-NEXT: s_and_b32 s20, s20, 0xff +; VI-NEXT: v_readlane_b32 s23, v22, 51 +; VI-NEXT: s_or_b32 s20, s20, s22 +; VI-NEXT: s_lshl_b32 s22, s78, 8 +; VI-NEXT: s_and_b32 s23, s23, 0xff +; VI-NEXT: s_or_b32 s22, s23, s22 +; VI-NEXT: s_and_b32 s20, s20, 0xffff +; VI-NEXT: s_lshl_b32 s22, s22, 16 +; VI-NEXT: s_or_b32 s20, s20, s22 ; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 4, v0 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 +; VI-NEXT: v_mov_b32_e32 v15, s20 +; VI-NEXT: s_and_b32 s20, s21, 0xff +; VI-NEXT: v_readlane_b32 s21, v22, 50 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 8, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 50 +; VI-NEXT: s_lshl_b32 s21, s21, 8 ; VI-NEXT: buffer_store_dword v3, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 12, v0 -; VI-NEXT: v_mov_b32_e32 v15, s16 -; VI-NEXT: s_and_b32 s16, s45, 0xff -; VI-NEXT: s_lshl_b32 s17, s17, 8 +; VI-NEXT: s_or_b32 s20, s20, s21 ; VI-NEXT: buffer_store_dword v4, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 16, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 +; VI-NEXT: v_readlane_b32 s21, v22, 49 +; VI-NEXT: v_readlane_b32 s22, v22, 48 ; VI-NEXT: buffer_store_dword v5, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 20, v0 -; VI-NEXT: v_readlane_b32 s17, v21, 49 -; VI-NEXT: v_readlane_b32 s18, v21, 48 +; VI-NEXT: s_and_b32 s21, s21, 0xff +; VI-NEXT: s_lshl_b32 s22, s22, 8 ; VI-NEXT: buffer_store_dword v6, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 24, v0 -; VI-NEXT: s_and_b32 s17, s17, 0xff -; VI-NEXT: s_lshl_b32 s18, s18, 8 +; VI-NEXT: s_or_b32 s21, s21, s22 ; VI-NEXT: buffer_store_dword v7, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 28, v0 -; VI-NEXT: s_or_b32 s17, s17, s18 +; VI-NEXT: s_and_b32 s20, s20, 0xffff +; VI-NEXT: s_lshl_b32 s21, s21, 16 ; VI-NEXT: buffer_store_dword v8, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 32, v0 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 +; VI-NEXT: s_or_b32 s20, s20, s21 ; VI-NEXT: buffer_store_dword v9, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 36, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 47 +; VI-NEXT: v_mov_b32_e32 v2, s20 +; VI-NEXT: v_readlane_b32 s20, v22, 47 ; VI-NEXT: buffer_store_dword v10, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 40, v0 -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: s_and_b32 s16, s42, 0xff -; VI-NEXT: s_lshl_b32 s17, s17, 8 +; VI-NEXT: s_and_b32 s18, s18, 0xff +; VI-NEXT: s_lshl_b32 s20, s20, 8 ; VI-NEXT: buffer_store_dword v11, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 44, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 46 +; VI-NEXT: s_or_b32 s18, s18, s20 +; VI-NEXT: v_readlane_b32 s20, v22, 46 ; VI-NEXT: buffer_store_dword v12, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 48, v0 -; VI-NEXT: s_and_b32 s17, s17, 0xff -; VI-NEXT: s_lshl_b32 s18, s76, 8 +; VI-NEXT: s_and_b32 s20, s20, 0xff +; VI-NEXT: s_lshl_b32 s21, s76, 8 ; VI-NEXT: buffer_store_dword v13, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 52, v0 -; VI-NEXT: s_or_b32 s17, s17, s18 +; VI-NEXT: s_or_b32 s20, s20, s21 ; VI-NEXT: buffer_store_dword v14, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 56, v0 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 +; VI-NEXT: s_and_b32 s18, s18, 0xffff +; VI-NEXT: s_lshl_b32 s20, s20, 16 ; VI-NEXT: buffer_store_dword v15, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 60, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 45 +; VI-NEXT: s_or_b32 s18, s18, s20 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: s_and_b32 s16, s43, 0xff -; VI-NEXT: s_lshl_b32 s17, s17, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 44 -; VI-NEXT: v_readlane_b32 s18, v21, 43 -; VI-NEXT: s_and_b32 s17, s17, 0xff -; VI-NEXT: s_lshl_b32 s18, s18, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 +; VI-NEXT: v_mov_b32_e32 v2, s18 +; VI-NEXT: s_and_b32 s18, s19, 0xff +; VI-NEXT: v_readlane_b32 s19, v22, 45 +; VI-NEXT: s_lshl_b32 s19, s19, 8 +; VI-NEXT: s_or_b32 s18, s18, s19 +; VI-NEXT: v_readlane_b32 s19, v22, 44 +; VI-NEXT: v_readlane_b32 s20, v22, 43 +; VI-NEXT: s_and_b32 s19, s19, 0xff +; VI-NEXT: s_lshl_b32 s20, s20, 8 +; VI-NEXT: s_or_b32 s19, s19, s20 +; VI-NEXT: s_and_b32 s18, s18, 0xffff +; VI-NEXT: s_lshl_b32 s19, s19, 16 ; VI-NEXT: v_add_u32_e32 v1, vcc, 64, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 42 +; VI-NEXT: s_or_b32 s18, s18, s19 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: s_and_b32 s16, s40, 0xff -; VI-NEXT: s_lshl_b32 s17, s17, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 41 -; VI-NEXT: s_and_b32 s17, s17, 0xff -; VI-NEXT: s_lshl_b32 s18, s74, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 +; VI-NEXT: v_mov_b32_e32 v2, s18 +; VI-NEXT: v_readlane_b32 s18, v22, 42 +; VI-NEXT: s_and_b32 s16, s16, 0xff +; VI-NEXT: s_lshl_b32 s18, s18, 8 +; VI-NEXT: s_or_b32 s16, s16, s18 +; VI-NEXT: v_readlane_b32 s18, v22, 41 +; VI-NEXT: s_and_b32 s18, s18, 0xff +; VI-NEXT: s_lshl_b32 s19, s74, 8 +; VI-NEXT: s_or_b32 s18, s18, s19 ; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 +; VI-NEXT: s_lshl_b32 s18, s18, 16 ; VI-NEXT: v_add_u32_e32 v1, vcc, 0x44, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 40 +; VI-NEXT: s_or_b32 s16, s16, s18 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: s_and_b32 s16, s41, 0xff +; VI-NEXT: s_and_b32 s16, s17, 0xff +; VI-NEXT: v_readlane_b32 s17, v22, 40 ; VI-NEXT: s_lshl_b32 s17, s17, 8 ; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 39 -; VI-NEXT: v_readlane_b32 s18, v21, 38 +; VI-NEXT: v_readlane_b32 s17, v22, 39 +; VI-NEXT: v_readlane_b32 s18, v22, 38 ; VI-NEXT: s_and_b32 s17, s17, 0xff ; VI-NEXT: s_lshl_b32 s18, s18, 8 ; VI-NEXT: s_or_b32 s17, s17, s18 @@ -83204,11 +82221,11 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI-NEXT: s_or_b32 s16, s16, s17 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: v_readlane_b32 s16, v21, 37 +; VI-NEXT: v_readlane_b32 s16, v22, 37 ; VI-NEXT: s_and_b32 s14, s14, 0xff ; VI-NEXT: s_lshl_b32 s16, s16, 8 ; VI-NEXT: s_or_b32 s14, s14, s16 -; VI-NEXT: v_readlane_b32 s16, v21, 36 +; VI-NEXT: v_readlane_b32 s16, v22, 36 ; VI-NEXT: s_and_b32 s16, s16, 0xff ; VI-NEXT: s_lshl_b32 s17, s72, 8 ; VI-NEXT: s_or_b32 s16, s16, s17 @@ -83219,11 +82236,11 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s14 ; VI-NEXT: s_and_b32 s14, s15, 0xff -; VI-NEXT: v_readlane_b32 s15, v21, 35 +; VI-NEXT: v_readlane_b32 s15, v22, 35 ; VI-NEXT: s_lshl_b32 s15, s15, 8 ; VI-NEXT: s_or_b32 s14, s14, s15 -; VI-NEXT: v_readlane_b32 s15, v21, 34 -; VI-NEXT: v_readlane_b32 s16, v21, 33 +; VI-NEXT: v_readlane_b32 s15, v22, 34 +; VI-NEXT: v_readlane_b32 s16, v22, 33 ; VI-NEXT: s_and_b32 s15, s15, 0xff ; VI-NEXT: s_lshl_b32 s16, s16, 8 ; VI-NEXT: s_or_b32 s15, s15, s16 @@ -83233,11 +82250,11 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI-NEXT: s_or_b32 s14, s14, s15 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s14 -; VI-NEXT: v_readlane_b32 s14, v21, 32 +; VI-NEXT: v_readlane_b32 s14, v22, 32 ; VI-NEXT: s_and_b32 s12, s12, 0xff ; VI-NEXT: s_lshl_b32 s14, s14, 8 ; VI-NEXT: s_or_b32 s12, s12, s14 -; VI-NEXT: v_readlane_b32 s14, v21, 31 +; VI-NEXT: v_readlane_b32 s14, v22, 31 ; VI-NEXT: s_and_b32 s14, s14, 0xff ; VI-NEXT: s_lshl_b32 s15, s62, 8 ; VI-NEXT: s_or_b32 s14, s14, s15 @@ -83248,11 +82265,11 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s12 ; VI-NEXT: s_and_b32 s12, s13, 0xff -; VI-NEXT: v_readlane_b32 s13, v21, 30 +; VI-NEXT: v_readlane_b32 s13, v22, 30 ; VI-NEXT: s_lshl_b32 s13, s13, 8 ; VI-NEXT: s_or_b32 s12, s12, s13 -; VI-NEXT: v_readlane_b32 s13, v21, 29 -; VI-NEXT: v_readlane_b32 s14, v21, 28 +; VI-NEXT: v_readlane_b32 s13, v22, 29 +; VI-NEXT: v_readlane_b32 s14, v22, 28 ; VI-NEXT: s_and_b32 s13, s13, 0xff ; VI-NEXT: s_lshl_b32 s14, s14, 8 ; VI-NEXT: s_or_b32 s13, s13, s14 @@ -83262,12 +82279,12 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI-NEXT: s_or_b32 s12, s12, s13 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s12 -; VI-NEXT: v_readlane_b32 s12, v21, 27 +; VI-NEXT: v_readlane_b32 s12, v22, 27 ; VI-NEXT: s_and_b32 s10, s10, 0xff ; VI-NEXT: s_lshl_b32 s12, s12, 8 ; VI-NEXT: s_or_b32 s10, s10, s12 -; VI-NEXT: v_readlane_b32 s12, v21, 26 -; VI-NEXT: v_readlane_b32 s14, v21, 0 +; VI-NEXT: v_readlane_b32 s12, v22, 26 +; VI-NEXT: v_readlane_b32 s14, v22, 0 ; VI-NEXT: s_and_b32 s12, s12, 0xff ; VI-NEXT: s_lshl_b32 s13, s14, 8 ; VI-NEXT: s_or_b32 s12, s12, s13 @@ -83278,11 +82295,11 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s10 ; VI-NEXT: s_and_b32 s10, s11, 0xff -; VI-NEXT: v_readlane_b32 s11, v21, 25 +; VI-NEXT: v_readlane_b32 s11, v22, 25 ; VI-NEXT: s_lshl_b32 s11, s11, 8 ; VI-NEXT: s_or_b32 s10, s10, s11 -; VI-NEXT: v_readlane_b32 s11, v21, 24 -; VI-NEXT: v_readlane_b32 s12, v21, 23 +; VI-NEXT: v_readlane_b32 s11, v22, 24 +; VI-NEXT: v_readlane_b32 s12, v22, 23 ; VI-NEXT: s_and_b32 s11, s11, 0xff ; VI-NEXT: s_lshl_b32 s12, s12, 8 ; VI-NEXT: s_or_b32 s11, s11, s12 @@ -83292,12 +82309,12 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI-NEXT: s_or_b32 s10, s10, s11 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s10 -; VI-NEXT: v_readlane_b32 s10, v21, 22 +; VI-NEXT: v_readlane_b32 s10, v22, 22 ; VI-NEXT: s_and_b32 s8, s8, 0xff ; VI-NEXT: s_lshl_b32 s10, s10, 8 ; VI-NEXT: s_or_b32 s8, s8, s10 -; VI-NEXT: v_readlane_b32 s10, v21, 21 -; VI-NEXT: v_readlane_b32 s12, v21, 2 +; VI-NEXT: v_readlane_b32 s10, v22, 21 +; VI-NEXT: v_readlane_b32 s12, v22, 2 ; VI-NEXT: s_and_b32 s10, s10, 0xff ; VI-NEXT: s_lshl_b32 s11, s12, 8 ; VI-NEXT: s_or_b32 s10, s10, s11 @@ -83308,11 +82325,11 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s8 ; VI-NEXT: s_and_b32 s8, s9, 0xff -; VI-NEXT: v_readlane_b32 s9, v21, 20 +; VI-NEXT: v_readlane_b32 s9, v22, 20 ; VI-NEXT: s_lshl_b32 s9, s9, 8 ; VI-NEXT: s_or_b32 s8, s8, s9 -; VI-NEXT: v_readlane_b32 s9, v21, 19 -; VI-NEXT: v_readlane_b32 s10, v21, 18 +; VI-NEXT: v_readlane_b32 s9, v22, 19 +; VI-NEXT: v_readlane_b32 s10, v22, 18 ; VI-NEXT: s_and_b32 s9, s9, 0xff ; VI-NEXT: s_lshl_b32 s10, s10, 8 ; VI-NEXT: s_or_b32 s9, s9, s10 @@ -83322,12 +82339,12 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI-NEXT: s_or_b32 s8, s8, s9 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s8 -; VI-NEXT: v_readlane_b32 s8, v21, 17 +; VI-NEXT: v_readlane_b32 s8, v22, 17 ; VI-NEXT: s_and_b32 s6, s6, 0xff ; VI-NEXT: s_lshl_b32 s8, s8, 8 ; VI-NEXT: s_or_b32 s6, s6, s8 -; VI-NEXT: v_readlane_b32 s8, v21, 16 -; VI-NEXT: v_readlane_b32 s10, v21, 4 +; VI-NEXT: v_readlane_b32 s8, v22, 16 +; VI-NEXT: v_readlane_b32 s10, v22, 4 ; VI-NEXT: s_and_b32 s8, s8, 0xff ; VI-NEXT: s_lshl_b32 s9, s10, 8 ; VI-NEXT: s_or_b32 s8, s8, s9 @@ -83338,11 +82355,11 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s6 ; VI-NEXT: s_and_b32 s6, s7, 0xff -; VI-NEXT: v_readlane_b32 s7, v21, 15 +; VI-NEXT: v_readlane_b32 s7, v22, 15 ; VI-NEXT: s_lshl_b32 s7, s7, 8 ; VI-NEXT: s_or_b32 s6, s6, s7 -; VI-NEXT: v_readlane_b32 s7, v21, 14 -; VI-NEXT: v_readlane_b32 s8, v21, 13 +; VI-NEXT: v_readlane_b32 s7, v22, 14 +; VI-NEXT: v_readlane_b32 s8, v22, 13 ; VI-NEXT: s_and_b32 s7, s7, 0xff ; VI-NEXT: s_lshl_b32 s8, s8, 8 ; VI-NEXT: s_or_b32 s7, s7, s8 @@ -83352,12 +82369,12 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI-NEXT: s_or_b32 s6, s6, s7 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s6 -; VI-NEXT: v_readlane_b32 s6, v21, 12 +; VI-NEXT: v_readlane_b32 s6, v22, 12 ; VI-NEXT: s_and_b32 s4, s4, 0xff ; VI-NEXT: s_lshl_b32 s6, s6, 8 ; VI-NEXT: s_or_b32 s4, s4, s6 -; VI-NEXT: v_readlane_b32 s6, v21, 11 -; VI-NEXT: v_readlane_b32 s8, v21, 6 +; VI-NEXT: v_readlane_b32 s6, v22, 11 +; VI-NEXT: v_readlane_b32 s8, v22, 6 ; VI-NEXT: s_and_b32 s6, s6, 0xff ; VI-NEXT: s_lshl_b32 s7, s8, 8 ; VI-NEXT: s_or_b32 s6, s6, s7 @@ -83368,11 +82385,11 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s4 ; VI-NEXT: s_and_b32 s4, s5, 0xff -; VI-NEXT: v_readlane_b32 s5, v21, 10 +; VI-NEXT: v_readlane_b32 s5, v22, 10 ; VI-NEXT: s_lshl_b32 s5, s5, 8 ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: v_readlane_b32 s5, v21, 9 -; VI-NEXT: v_readlane_b32 s6, v21, 8 +; VI-NEXT: v_readlane_b32 s5, v22, 9 +; VI-NEXT: v_readlane_b32 s6, v22, 8 ; VI-NEXT: s_and_b32 s5, s5, 0xff ; VI-NEXT: s_lshl_b32 s6, s6, 8 ; VI-NEXT: s_or_b32 s5, s5, s6 @@ -83383,46 +82400,46 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0 ; VI-NEXT: v_mov_b32_e32 v1, s4 -; VI-NEXT: v_readlane_b32 s15, v21, 1 -; VI-NEXT: v_readlane_b32 s13, v21, 3 -; VI-NEXT: v_readlane_b32 s11, v21, 5 -; VI-NEXT: v_readlane_b32 s9, v21, 7 +; VI-NEXT: v_readlane_b32 s15, v22, 1 +; VI-NEXT: v_readlane_b32 s13, v22, 3 +; VI-NEXT: v_readlane_b32 s11, v22, 5 +; VI-NEXT: v_readlane_b32 s9, v22, 7 ; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; VI-NEXT: v_readlane_b32 s87, v20, 31 -; VI-NEXT: v_readlane_b32 s86, v20, 30 -; VI-NEXT: v_readlane_b32 s85, v20, 29 -; VI-NEXT: v_readlane_b32 s84, v20, 28 -; VI-NEXT: v_readlane_b32 s83, v20, 27 -; VI-NEXT: v_readlane_b32 s82, v20, 26 -; VI-NEXT: v_readlane_b32 s81, v20, 25 -; VI-NEXT: v_readlane_b32 s80, v20, 24 -; VI-NEXT: v_readlane_b32 s71, v20, 23 -; VI-NEXT: v_readlane_b32 s70, v20, 22 -; VI-NEXT: v_readlane_b32 s69, v20, 21 -; VI-NEXT: v_readlane_b32 s68, v20, 20 -; VI-NEXT: v_readlane_b32 s67, v20, 19 -; VI-NEXT: v_readlane_b32 s66, v20, 18 -; VI-NEXT: v_readlane_b32 s65, v20, 17 -; VI-NEXT: v_readlane_b32 s64, v20, 16 -; VI-NEXT: v_readlane_b32 s55, v20, 15 -; VI-NEXT: v_readlane_b32 s54, v20, 14 -; VI-NEXT: v_readlane_b32 s53, v20, 13 -; VI-NEXT: v_readlane_b32 s52, v20, 12 -; VI-NEXT: v_readlane_b32 s51, v20, 11 -; VI-NEXT: v_readlane_b32 s50, v20, 10 -; VI-NEXT: v_readlane_b32 s49, v20, 9 -; VI-NEXT: v_readlane_b32 s48, v20, 8 -; VI-NEXT: v_readlane_b32 s39, v20, 7 -; VI-NEXT: v_readlane_b32 s38, v20, 6 -; VI-NEXT: v_readlane_b32 s37, v20, 5 -; VI-NEXT: v_readlane_b32 s36, v20, 4 -; VI-NEXT: v_readlane_b32 s35, v20, 3 -; VI-NEXT: v_readlane_b32 s34, v20, 2 -; VI-NEXT: v_readlane_b32 s31, v20, 1 -; VI-NEXT: v_readlane_b32 s30, v20, 0 +; VI-NEXT: v_readlane_b32 s87, v21, 31 +; VI-NEXT: v_readlane_b32 s86, v21, 30 +; VI-NEXT: v_readlane_b32 s85, v21, 29 +; VI-NEXT: v_readlane_b32 s84, v21, 28 +; VI-NEXT: v_readlane_b32 s83, v21, 27 +; VI-NEXT: v_readlane_b32 s82, v21, 26 +; VI-NEXT: v_readlane_b32 s81, v21, 25 +; VI-NEXT: v_readlane_b32 s80, v21, 24 +; VI-NEXT: v_readlane_b32 s71, v21, 23 +; VI-NEXT: v_readlane_b32 s70, v21, 22 +; VI-NEXT: v_readlane_b32 s69, v21, 21 +; VI-NEXT: v_readlane_b32 s68, v21, 20 +; VI-NEXT: v_readlane_b32 s67, v21, 19 +; VI-NEXT: v_readlane_b32 s66, v21, 18 +; VI-NEXT: v_readlane_b32 s65, v21, 17 +; VI-NEXT: v_readlane_b32 s64, v21, 16 +; VI-NEXT: v_readlane_b32 s55, v21, 15 +; VI-NEXT: v_readlane_b32 s54, v21, 14 +; VI-NEXT: v_readlane_b32 s53, v21, 13 +; VI-NEXT: v_readlane_b32 s52, v21, 12 +; VI-NEXT: v_readlane_b32 s51, v21, 11 +; VI-NEXT: v_readlane_b32 s50, v21, 10 +; VI-NEXT: v_readlane_b32 s49, v21, 9 +; VI-NEXT: v_readlane_b32 s48, v21, 8 +; VI-NEXT: v_readlane_b32 s39, v21, 7 +; VI-NEXT: v_readlane_b32 s38, v21, 6 +; VI-NEXT: v_readlane_b32 s37, v21, 5 +; VI-NEXT: v_readlane_b32 s36, v21, 4 +; VI-NEXT: v_readlane_b32 s35, v21, 3 +; VI-NEXT: v_readlane_b32 s34, v21, 2 +; VI-NEXT: v_readlane_b32 s31, v21, 1 +; VI-NEXT: v_readlane_b32 s30, v21, 0 ; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_setpc_b64 s[30:31] @@ -83440,10 +82457,10 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI-NEXT: ; implicit-def: $sgpr53 ; VI-NEXT: ; implicit-def: $sgpr52 ; VI-NEXT: ; implicit-def: $sgpr51 -; VI-NEXT: ; implicit-def: $sgpr57 -; VI-NEXT: ; implicit-def: $sgpr56 -; VI-NEXT: ; implicit-def: $sgpr47 -; VI-NEXT: ; implicit-def: $sgpr46 +; VI-NEXT: ; implicit-def: $sgpr29 +; VI-NEXT: ; implicit-def: $sgpr28 +; VI-NEXT: ; implicit-def: $sgpr27 +; VI-NEXT: ; implicit-def: $sgpr26 ; VI-NEXT: ; implicit-def: $sgpr50 ; VI-NEXT: ; implicit-def: $sgpr87 ; VI-NEXT: ; implicit-def: $sgpr86 @@ -83572,68 +82589,96 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; VI-NEXT: ; implicit-def: $sgpr60 ; VI-NEXT: ; kill: killed $sgpr60 ; VI-NEXT: ; implicit-def: $sgpr60 -; VI-NEXT: v_writelane_b32 v21, s60, 0 -; VI-NEXT: v_writelane_b32 v21, s61, 1 +; VI-NEXT: v_writelane_b32 v22, s60, 0 +; VI-NEXT: v_writelane_b32 v22, s61, 1 ; VI-NEXT: ; implicit-def: $sgpr60 -; VI-NEXT: v_writelane_b32 v21, s60, 2 -; VI-NEXT: v_writelane_b32 v21, s61, 3 +; VI-NEXT: v_writelane_b32 v22, s60, 2 +; VI-NEXT: v_writelane_b32 v22, s61, 3 ; VI-NEXT: ; implicit-def: $sgpr60 -; VI-NEXT: v_writelane_b32 v21, s60, 4 -; VI-NEXT: v_writelane_b32 v21, s61, 5 +; VI-NEXT: v_writelane_b32 v22, s60, 4 +; VI-NEXT: v_writelane_b32 v22, s61, 5 ; VI-NEXT: ; implicit-def: $sgpr60 -; VI-NEXT: v_writelane_b32 v21, s60, 6 -; VI-NEXT: v_writelane_b32 v21, s61, 7 +; VI-NEXT: v_writelane_b32 v22, s60, 6 +; VI-NEXT: v_writelane_b32 v22, s61, 7 ; VI-NEXT: s_branch .LBB57_2 ; ; GFX9-LABEL: bitcast_v16i64_to_v128i8_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v20, s30, 0 -; GFX9-NEXT: v_writelane_b32 v20, s31, 1 -; GFX9-NEXT: v_writelane_b32 v20, s34, 2 -; GFX9-NEXT: v_writelane_b32 v20, s35, 3 -; GFX9-NEXT: v_writelane_b32 v20, s36, 4 -; GFX9-NEXT: v_writelane_b32 v20, s37, 5 -; GFX9-NEXT: v_writelane_b32 v20, s38, 6 -; GFX9-NEXT: v_writelane_b32 v20, s39, 7 -; GFX9-NEXT: v_writelane_b32 v20, s48, 8 -; GFX9-NEXT: v_writelane_b32 v20, s49, 9 -; GFX9-NEXT: v_writelane_b32 v20, s50, 10 -; GFX9-NEXT: v_writelane_b32 v20, s51, 11 -; GFX9-NEXT: v_writelane_b32 v20, s52, 12 -; GFX9-NEXT: v_writelane_b32 v20, s53, 13 -; GFX9-NEXT: v_writelane_b32 v20, s54, 14 -; GFX9-NEXT: v_writelane_b32 v20, s55, 15 -; GFX9-NEXT: v_writelane_b32 v20, s64, 16 -; GFX9-NEXT: v_writelane_b32 v20, s65, 17 -; GFX9-NEXT: v_writelane_b32 v20, s66, 18 -; GFX9-NEXT: v_writelane_b32 v20, s67, 19 -; GFX9-NEXT: v_writelane_b32 v20, s68, 20 -; GFX9-NEXT: v_writelane_b32 v20, s69, 21 -; GFX9-NEXT: v_writelane_b32 v20, s70, 22 -; GFX9-NEXT: v_writelane_b32 v20, s71, 23 -; GFX9-NEXT: v_writelane_b32 v20, s80, 24 -; GFX9-NEXT: v_writelane_b32 v20, s81, 25 -; GFX9-NEXT: v_writelane_b32 v20, s82, 26 -; GFX9-NEXT: v_writelane_b32 v20, s83, 27 -; GFX9-NEXT: v_writelane_b32 v20, s84, 28 -; GFX9-NEXT: v_writelane_b32 v20, s85, 29 -; GFX9-NEXT: v_writelane_b32 v20, s86, 30 -; GFX9-NEXT: v_writelane_b32 v20, s87, 31 -; GFX9-NEXT: v_writelane_b32 v20, s96, 32 -; GFX9-NEXT: v_writelane_b32 v20, s97, 33 +; GFX9-NEXT: v_writelane_b32 v21, s30, 0 +; GFX9-NEXT: v_writelane_b32 v21, s31, 1 +; GFX9-NEXT: v_writelane_b32 v21, s34, 2 +; GFX9-NEXT: v_writelane_b32 v21, s35, 3 +; GFX9-NEXT: v_writelane_b32 v21, s36, 4 +; GFX9-NEXT: v_writelane_b32 v21, s37, 5 +; GFX9-NEXT: v_writelane_b32 v21, s38, 6 +; GFX9-NEXT: v_writelane_b32 v21, s39, 7 +; GFX9-NEXT: v_writelane_b32 v21, s48, 8 +; GFX9-NEXT: v_writelane_b32 v21, s49, 9 +; GFX9-NEXT: v_writelane_b32 v21, s50, 10 +; GFX9-NEXT: v_writelane_b32 v21, s51, 11 +; GFX9-NEXT: v_writelane_b32 v21, s52, 12 +; GFX9-NEXT: v_writelane_b32 v21, s53, 13 +; GFX9-NEXT: v_writelane_b32 v21, s54, 14 +; GFX9-NEXT: v_writelane_b32 v21, s55, 15 +; GFX9-NEXT: v_writelane_b32 v21, s64, 16 +; GFX9-NEXT: v_writelane_b32 v21, s65, 17 +; GFX9-NEXT: v_writelane_b32 v21, s66, 18 +; GFX9-NEXT: v_writelane_b32 v21, s67, 19 +; GFX9-NEXT: v_writelane_b32 v21, s68, 20 +; GFX9-NEXT: v_mov_b32_e32 v20, s16 +; GFX9-NEXT: v_writelane_b32 v21, s69, 21 +; GFX9-NEXT: v_readfirstlane_b32 s56, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s17 +; GFX9-NEXT: v_writelane_b32 v21, s70, 22 +; GFX9-NEXT: v_readfirstlane_b32 s57, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s18 +; GFX9-NEXT: v_writelane_b32 v21, s71, 23 +; GFX9-NEXT: v_readfirstlane_b32 s46, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s19 +; GFX9-NEXT: v_writelane_b32 v21, s80, 24 +; GFX9-NEXT: v_readfirstlane_b32 s47, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s20 +; GFX9-NEXT: v_writelane_b32 v21, s81, 25 +; GFX9-NEXT: v_readfirstlane_b32 s44, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s21 +; GFX9-NEXT: v_writelane_b32 v21, s82, 26 +; GFX9-NEXT: v_readfirstlane_b32 s45, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s22 +; GFX9-NEXT: v_writelane_b32 v21, s83, 27 +; GFX9-NEXT: v_readfirstlane_b32 s42, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s23 +; GFX9-NEXT: v_writelane_b32 v21, s84, 28 +; GFX9-NEXT: v_readfirstlane_b32 s43, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s24 +; GFX9-NEXT: v_writelane_b32 v21, s85, 29 +; GFX9-NEXT: v_readfirstlane_b32 s40, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s25 +; GFX9-NEXT: v_writelane_b32 v21, s86, 30 +; GFX9-NEXT: v_readfirstlane_b32 s41, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s26 +; GFX9-NEXT: v_writelane_b32 v21, s87, 31 +; GFX9-NEXT: v_readfirstlane_b32 s24, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s27 +; GFX9-NEXT: v_writelane_b32 v21, s96, 32 +; GFX9-NEXT: v_readfirstlane_b32 s25, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s28 +; GFX9-NEXT: v_writelane_b32 v21, s97, 33 +; GFX9-NEXT: v_readfirstlane_b32 s22, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s29 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; GFX9-NEXT: v_writelane_b32 v20, s98, 34 -; GFX9-NEXT: v_readfirstlane_b32 s44, v1 -; GFX9-NEXT: v_readfirstlane_b32 s45, v2 -; GFX9-NEXT: v_readfirstlane_b32 s42, v3 -; GFX9-NEXT: v_readfirstlane_b32 s43, v4 -; GFX9-NEXT: v_readfirstlane_b32 s40, v5 -; GFX9-NEXT: v_readfirstlane_b32 s41, v6 +; GFX9-NEXT: v_writelane_b32 v21, s98, 34 +; GFX9-NEXT: v_readfirstlane_b32 s23, v20 +; GFX9-NEXT: v_readfirstlane_b32 s20, v1 +; GFX9-NEXT: v_readfirstlane_b32 s21, v2 +; GFX9-NEXT: v_readfirstlane_b32 s18, v3 +; GFX9-NEXT: v_readfirstlane_b32 s19, v4 +; GFX9-NEXT: v_readfirstlane_b32 s16, v5 +; GFX9-NEXT: v_readfirstlane_b32 s17, v6 ; GFX9-NEXT: v_readfirstlane_b32 s14, v7 ; GFX9-NEXT: v_readfirstlane_b32 s15, v8 ; GFX9-NEXT: v_readfirstlane_b32 s12, v9 @@ -83645,181 +82690,181 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX9-NEXT: v_readfirstlane_b32 s6, v15 ; GFX9-NEXT: v_readfirstlane_b32 s7, v16 ; GFX9-NEXT: v_readfirstlane_b32 s4, v17 -; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_and_b64 s[26:27], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s5, v18 -; GFX9-NEXT: v_writelane_b32 v20, s99, 35 -; GFX9-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane +; GFX9-NEXT: v_writelane_b32 v21, s99, 35 +; GFX9-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane ; GFX9-NEXT: s_cbranch_scc0 .LBB57_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false -; GFX9-NEXT: s_lshr_b32 s46, s5, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 2 -; GFX9-NEXT: s_lshr_b32 s46, s5, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 3 -; GFX9-NEXT: s_lshr_b32 s46, s5, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 4 -; GFX9-NEXT: s_lshr_b32 s46, s4, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 5 -; GFX9-NEXT: s_lshr_b32 s46, s4, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 6 -; GFX9-NEXT: s_lshr_b32 s46, s7, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 7 -; GFX9-NEXT: s_lshr_b32 s46, s7, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 8 -; GFX9-NEXT: s_lshr_b32 s46, s7, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 9 -; GFX9-NEXT: s_lshr_b32 s46, s6, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 10 -; GFX9-NEXT: s_lshr_b32 s46, s6, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 11 -; GFX9-NEXT: s_lshr_b32 s46, s9, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 12 -; GFX9-NEXT: s_lshr_b32 s46, s9, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 13 -; GFX9-NEXT: s_lshr_b32 s46, s9, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 14 -; GFX9-NEXT: s_lshr_b32 s46, s8, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 15 -; GFX9-NEXT: s_lshr_b32 s46, s8, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 16 -; GFX9-NEXT: s_lshr_b32 s46, s11, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 17 -; GFX9-NEXT: s_lshr_b32 s46, s11, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 18 -; GFX9-NEXT: s_lshr_b32 s46, s11, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 19 -; GFX9-NEXT: s_lshr_b32 s46, s10, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 20 -; GFX9-NEXT: s_lshr_b32 s46, s10, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 21 -; GFX9-NEXT: s_lshr_b32 s46, s13, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 22 -; GFX9-NEXT: s_lshr_b32 s46, s13, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 23 -; GFX9-NEXT: s_lshr_b32 s46, s13, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 24 -; GFX9-NEXT: s_lshr_b32 s46, s12, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 25 -; GFX9-NEXT: s_lshr_b32 s46, s12, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 26 -; GFX9-NEXT: s_lshr_b32 s46, s15, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 27 -; GFX9-NEXT: s_lshr_b32 s46, s15, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 28 -; GFX9-NEXT: s_lshr_b32 s46, s15, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 29 -; GFX9-NEXT: s_lshr_b32 s46, s14, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 30 -; GFX9-NEXT: s_lshr_b32 s46, s14, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 31 -; GFX9-NEXT: s_lshr_b32 s46, s41, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 32 -; GFX9-NEXT: s_lshr_b32 s46, s41, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 33 -; GFX9-NEXT: s_lshr_b32 s46, s41, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 34 -; GFX9-NEXT: s_lshr_b32 s46, s40, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 35 -; GFX9-NEXT: s_lshr_b32 s46, s40, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 36 -; GFX9-NEXT: s_lshr_b32 s46, s43, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 37 -; GFX9-NEXT: s_lshr_b32 s46, s43, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 38 -; GFX9-NEXT: s_lshr_b32 s46, s43, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 39 -; GFX9-NEXT: s_lshr_b32 s46, s42, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 40 -; GFX9-NEXT: s_lshr_b32 s46, s42, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 41 -; GFX9-NEXT: s_lshr_b32 s46, s45, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 42 -; GFX9-NEXT: s_lshr_b32 s46, s45, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 43 -; GFX9-NEXT: s_lshr_b32 s46, s45, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 44 -; GFX9-NEXT: s_lshr_b32 s46, s44, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 45 -; GFX9-NEXT: s_lshr_b32 s46, s44, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 46 -; GFX9-NEXT: s_lshr_b32 s46, s29, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 47 -; GFX9-NEXT: s_lshr_b32 s46, s29, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 48 -; GFX9-NEXT: s_lshr_b32 s46, s29, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 49 -; GFX9-NEXT: s_lshr_b32 s46, s28, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 50 -; GFX9-NEXT: s_lshr_b64 s[56:57], s[4:5], 24 -; GFX9-NEXT: v_writelane_b32 v21, s56, 0 -; GFX9-NEXT: s_lshr_b32 s82, s28, 8 -; GFX9-NEXT: s_lshr_b32 s83, s27, 24 -; GFX9-NEXT: s_lshr_b32 s81, s27, 16 -; GFX9-NEXT: s_lshr_b32 s84, s27, 8 -; GFX9-NEXT: s_lshr_b32 s85, s26, 16 -; GFX9-NEXT: s_lshr_b32 s86, s26, 8 -; GFX9-NEXT: s_lshr_b32 s87, s25, 24 -; GFX9-NEXT: s_lshr_b32 s96, s25, 16 -; GFX9-NEXT: s_lshr_b32 s97, s25, 8 -; GFX9-NEXT: s_lshr_b32 s98, s24, 16 -; GFX9-NEXT: s_lshr_b32 s99, s24, 8 -; GFX9-NEXT: s_lshr_b32 s38, s23, 24 -; GFX9-NEXT: s_lshr_b32 s39, s23, 16 -; GFX9-NEXT: s_lshr_b32 s48, s23, 8 -; GFX9-NEXT: s_lshr_b32 s49, s22, 16 -; GFX9-NEXT: s_lshr_b32 s50, s22, 8 -; GFX9-NEXT: s_lshr_b32 s51, s21, 24 -; GFX9-NEXT: s_lshr_b32 s52, s21, 16 -; GFX9-NEXT: s_lshr_b32 s53, s21, 8 -; GFX9-NEXT: s_lshr_b32 s54, s20, 16 -; GFX9-NEXT: s_lshr_b32 s55, s20, 8 -; GFX9-NEXT: s_lshr_b32 s64, s19, 24 -; GFX9-NEXT: s_lshr_b32 s65, s19, 16 -; GFX9-NEXT: s_lshr_b32 s66, s19, 8 -; GFX9-NEXT: s_lshr_b32 s67, s18, 16 -; GFX9-NEXT: s_lshr_b32 s68, s18, 8 -; GFX9-NEXT: s_lshr_b32 s69, s17, 24 -; GFX9-NEXT: s_lshr_b32 s70, s17, 16 -; GFX9-NEXT: s_lshr_b32 s71, s17, 8 -; GFX9-NEXT: s_lshr_b32 s80, s16, 16 -; GFX9-NEXT: s_lshr_b32 s46, s16, 8 -; GFX9-NEXT: v_writelane_b32 v21, s57, 1 -; GFX9-NEXT: s_lshr_b64 s[56:57], s[6:7], 24 +; GFX9-NEXT: s_lshr_b32 s26, s5, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 2 +; GFX9-NEXT: s_lshr_b32 s26, s5, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 3 +; GFX9-NEXT: s_lshr_b32 s26, s5, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 4 +; GFX9-NEXT: s_lshr_b32 s26, s4, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 5 +; GFX9-NEXT: s_lshr_b32 s26, s4, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 6 +; GFX9-NEXT: s_lshr_b32 s26, s7, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 7 +; GFX9-NEXT: s_lshr_b32 s26, s7, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 8 +; GFX9-NEXT: s_lshr_b32 s26, s7, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 9 +; GFX9-NEXT: s_lshr_b32 s26, s6, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 10 +; GFX9-NEXT: s_lshr_b32 s26, s6, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 11 +; GFX9-NEXT: s_lshr_b32 s26, s9, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 12 +; GFX9-NEXT: s_lshr_b32 s26, s9, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 13 +; GFX9-NEXT: s_lshr_b32 s26, s9, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 14 +; GFX9-NEXT: s_lshr_b32 s26, s8, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 15 +; GFX9-NEXT: s_lshr_b32 s26, s8, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 16 +; GFX9-NEXT: s_lshr_b32 s26, s11, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 17 +; GFX9-NEXT: s_lshr_b32 s26, s11, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 18 +; GFX9-NEXT: s_lshr_b32 s26, s11, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 19 +; GFX9-NEXT: s_lshr_b32 s26, s10, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 20 +; GFX9-NEXT: s_lshr_b32 s26, s10, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 21 +; GFX9-NEXT: s_lshr_b32 s26, s13, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 22 +; GFX9-NEXT: s_lshr_b32 s26, s13, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 23 +; GFX9-NEXT: s_lshr_b32 s26, s13, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 24 +; GFX9-NEXT: s_lshr_b32 s26, s12, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 25 +; GFX9-NEXT: s_lshr_b32 s26, s12, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 26 +; GFX9-NEXT: s_lshr_b32 s26, s15, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 27 +; GFX9-NEXT: s_lshr_b32 s26, s15, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 28 +; GFX9-NEXT: s_lshr_b32 s26, s15, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 29 +; GFX9-NEXT: s_lshr_b32 s26, s14, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 30 +; GFX9-NEXT: s_lshr_b32 s26, s14, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 31 +; GFX9-NEXT: s_lshr_b32 s26, s17, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 32 +; GFX9-NEXT: s_lshr_b32 s26, s17, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 33 +; GFX9-NEXT: s_lshr_b32 s26, s17, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 34 +; GFX9-NEXT: s_lshr_b32 s26, s16, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 35 +; GFX9-NEXT: s_lshr_b32 s26, s16, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 36 +; GFX9-NEXT: s_lshr_b32 s26, s19, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 37 +; GFX9-NEXT: s_lshr_b32 s26, s19, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 38 +; GFX9-NEXT: s_lshr_b32 s26, s19, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 39 +; GFX9-NEXT: s_lshr_b32 s26, s18, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 40 +; GFX9-NEXT: s_lshr_b32 s26, s18, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 41 +; GFX9-NEXT: s_lshr_b32 s26, s21, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 42 +; GFX9-NEXT: s_lshr_b32 s26, s21, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 43 +; GFX9-NEXT: s_lshr_b32 s26, s21, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 44 +; GFX9-NEXT: s_lshr_b32 s26, s20, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 45 +; GFX9-NEXT: s_lshr_b32 s26, s20, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 46 +; GFX9-NEXT: s_lshr_b32 s26, s23, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 47 +; GFX9-NEXT: s_lshr_b32 s26, s23, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 48 +; GFX9-NEXT: s_lshr_b32 s26, s23, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 49 +; GFX9-NEXT: s_lshr_b32 s26, s22, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 50 +; GFX9-NEXT: s_lshr_b64 s[28:29], s[4:5], 24 +; GFX9-NEXT: v_writelane_b32 v22, s28, 0 +; GFX9-NEXT: s_lshr_b32 s82, s22, 8 +; GFX9-NEXT: s_lshr_b32 s83, s25, 24 +; GFX9-NEXT: s_lshr_b32 s81, s25, 16 +; GFX9-NEXT: s_lshr_b32 s84, s25, 8 +; GFX9-NEXT: s_lshr_b32 s85, s24, 16 +; GFX9-NEXT: s_lshr_b32 s86, s24, 8 +; GFX9-NEXT: s_lshr_b32 s87, s41, 24 +; GFX9-NEXT: s_lshr_b32 s96, s41, 16 +; GFX9-NEXT: s_lshr_b32 s97, s41, 8 +; GFX9-NEXT: s_lshr_b32 s98, s40, 16 +; GFX9-NEXT: s_lshr_b32 s99, s40, 8 +; GFX9-NEXT: s_lshr_b32 s38, s43, 24 +; GFX9-NEXT: s_lshr_b32 s39, s43, 16 +; GFX9-NEXT: s_lshr_b32 s48, s43, 8 +; GFX9-NEXT: s_lshr_b32 s49, s42, 16 +; GFX9-NEXT: s_lshr_b32 s50, s42, 8 +; GFX9-NEXT: s_lshr_b32 s51, s45, 24 +; GFX9-NEXT: s_lshr_b32 s52, s45, 16 +; GFX9-NEXT: s_lshr_b32 s53, s45, 8 +; GFX9-NEXT: s_lshr_b32 s54, s44, 16 +; GFX9-NEXT: s_lshr_b32 s55, s44, 8 +; GFX9-NEXT: s_lshr_b32 s64, s47, 24 +; GFX9-NEXT: s_lshr_b32 s65, s47, 16 +; GFX9-NEXT: s_lshr_b32 s66, s47, 8 +; GFX9-NEXT: s_lshr_b32 s67, s46, 16 +; GFX9-NEXT: s_lshr_b32 s68, s46, 8 +; GFX9-NEXT: s_lshr_b32 s69, s57, 24 +; GFX9-NEXT: s_lshr_b32 s70, s57, 16 +; GFX9-NEXT: s_lshr_b32 s71, s57, 8 +; GFX9-NEXT: s_lshr_b32 s80, s56, 16 +; GFX9-NEXT: s_lshr_b32 s26, s56, 8 +; GFX9-NEXT: v_writelane_b32 v22, s29, 1 +; GFX9-NEXT: s_lshr_b64 s[28:29], s[6:7], 24 ; GFX9-NEXT: s_lshr_b64 s[58:59], s[8:9], 24 ; GFX9-NEXT: s_lshr_b64 s[60:61], s[10:11], 24 ; GFX9-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 ; GFX9-NEXT: s_lshr_b64 s[72:73], s[14:15], 24 -; GFX9-NEXT: s_lshr_b64 s[74:75], s[40:41], 24 -; GFX9-NEXT: s_lshr_b64 s[76:77], s[42:43], 24 -; GFX9-NEXT: s_lshr_b64 s[78:79], s[44:45], 24 -; GFX9-NEXT: s_lshr_b64 s[88:89], s[28:29], 24 -; GFX9-NEXT: s_lshr_b64 s[90:91], s[26:27], 24 -; GFX9-NEXT: s_lshr_b64 s[92:93], s[24:25], 24 -; GFX9-NEXT: s_lshr_b64 s[94:95], s[22:23], 24 -; GFX9-NEXT: s_lshr_b64 s[30:31], s[20:21], 24 -; GFX9-NEXT: s_lshr_b64 s[34:35], s[18:19], 24 -; GFX9-NEXT: s_lshr_b64 s[36:37], s[16:17], 24 +; GFX9-NEXT: s_lshr_b64 s[74:75], s[16:17], 24 +; GFX9-NEXT: s_lshr_b64 s[76:77], s[18:19], 24 +; GFX9-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 +; GFX9-NEXT: s_lshr_b64 s[88:89], s[22:23], 24 +; GFX9-NEXT: s_lshr_b64 s[90:91], s[24:25], 24 +; GFX9-NEXT: s_lshr_b64 s[92:93], s[40:41], 24 +; GFX9-NEXT: s_lshr_b64 s[94:95], s[42:43], 24 +; GFX9-NEXT: s_lshr_b64 s[30:31], s[44:45], 24 +; GFX9-NEXT: s_lshr_b64 s[34:35], s[46:47], 24 +; GFX9-NEXT: s_lshr_b64 s[36:37], s[56:57], 24 ; GFX9-NEXT: s_cbranch_execnz .LBB57_3 ; GFX9-NEXT: .LBB57_2: ; %cmp.true -; GFX9-NEXT: s_add_u32 s16, s16, 3 -; GFX9-NEXT: s_addc_u32 s17, s17, 0 -; GFX9-NEXT: s_add_u32 s18, s18, 3 -; GFX9-NEXT: s_addc_u32 s19, s19, 0 -; GFX9-NEXT: s_add_u32 s20, s20, 3 -; GFX9-NEXT: s_addc_u32 s21, s21, 0 -; GFX9-NEXT: s_add_u32 s22, s22, 3 -; GFX9-NEXT: s_addc_u32 s23, s23, 0 -; GFX9-NEXT: s_add_u32 s24, s24, 3 -; GFX9-NEXT: s_addc_u32 s25, s25, 0 -; GFX9-NEXT: s_add_u32 s26, s26, 3 -; GFX9-NEXT: s_addc_u32 s27, s27, 0 -; GFX9-NEXT: s_add_u32 s28, s28, 3 -; GFX9-NEXT: s_addc_u32 s29, s29, 0 +; GFX9-NEXT: s_add_u32 s56, s56, 3 +; GFX9-NEXT: s_addc_u32 s57, s57, 0 +; GFX9-NEXT: s_add_u32 s46, s46, 3 +; GFX9-NEXT: s_addc_u32 s47, s47, 0 ; GFX9-NEXT: s_add_u32 s44, s44, 3 ; GFX9-NEXT: s_addc_u32 s45, s45, 0 ; GFX9-NEXT: s_add_u32 s42, s42, 3 ; GFX9-NEXT: s_addc_u32 s43, s43, 0 ; GFX9-NEXT: s_add_u32 s40, s40, 3 ; GFX9-NEXT: s_addc_u32 s41, s41, 0 +; GFX9-NEXT: s_add_u32 s24, s24, 3 +; GFX9-NEXT: s_addc_u32 s25, s25, 0 +; GFX9-NEXT: s_add_u32 s22, s22, 3 +; GFX9-NEXT: s_addc_u32 s23, s23, 0 +; GFX9-NEXT: s_add_u32 s20, s20, 3 +; GFX9-NEXT: s_addc_u32 s21, s21, 0 +; GFX9-NEXT: s_add_u32 s18, s18, 3 +; GFX9-NEXT: s_addc_u32 s19, s19, 0 +; GFX9-NEXT: s_add_u32 s16, s16, 3 +; GFX9-NEXT: s_addc_u32 s17, s17, 0 ; GFX9-NEXT: s_add_u32 s14, s14, 3 ; GFX9-NEXT: s_addc_u32 s15, s15, 0 ; GFX9-NEXT: s_add_u32 s12, s12, 3 @@ -83832,298 +82877,297 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX9-NEXT: s_addc_u32 s7, s7, 0 ; GFX9-NEXT: s_add_u32 s4, s4, 3 ; GFX9-NEXT: s_addc_u32 s5, s5, 0 -; GFX9-NEXT: s_lshr_b32 s46, s5, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 2 -; GFX9-NEXT: s_lshr_b32 s46, s5, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 3 -; GFX9-NEXT: s_lshr_b32 s46, s5, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 4 -; GFX9-NEXT: s_lshr_b32 s46, s4, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 5 -; GFX9-NEXT: s_lshr_b32 s46, s4, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 6 -; GFX9-NEXT: s_lshr_b32 s46, s7, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 7 -; GFX9-NEXT: s_lshr_b32 s46, s7, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 8 -; GFX9-NEXT: s_lshr_b32 s46, s7, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 9 -; GFX9-NEXT: s_lshr_b32 s46, s6, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 10 -; GFX9-NEXT: s_lshr_b32 s46, s6, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 11 -; GFX9-NEXT: s_lshr_b32 s46, s9, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 12 -; GFX9-NEXT: s_lshr_b32 s46, s9, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 13 -; GFX9-NEXT: s_lshr_b32 s46, s9, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 14 -; GFX9-NEXT: s_lshr_b32 s46, s8, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 15 -; GFX9-NEXT: s_lshr_b32 s46, s8, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 16 -; GFX9-NEXT: s_lshr_b32 s46, s11, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 17 -; GFX9-NEXT: s_lshr_b32 s46, s11, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 18 -; GFX9-NEXT: s_lshr_b32 s46, s11, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 19 -; GFX9-NEXT: s_lshr_b32 s46, s10, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 20 -; GFX9-NEXT: s_lshr_b32 s46, s10, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 21 -; GFX9-NEXT: s_lshr_b32 s46, s13, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 22 -; GFX9-NEXT: s_lshr_b32 s46, s13, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 23 -; GFX9-NEXT: s_lshr_b32 s46, s13, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 24 -; GFX9-NEXT: s_lshr_b32 s46, s12, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 25 -; GFX9-NEXT: s_lshr_b32 s46, s12, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 26 -; GFX9-NEXT: s_lshr_b32 s46, s15, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 27 -; GFX9-NEXT: s_lshr_b32 s46, s15, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 28 -; GFX9-NEXT: s_lshr_b32 s46, s15, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 29 -; GFX9-NEXT: s_lshr_b32 s46, s14, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 30 -; GFX9-NEXT: s_lshr_b32 s46, s14, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 31 -; GFX9-NEXT: s_lshr_b32 s46, s41, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 32 -; GFX9-NEXT: s_lshr_b32 s46, s41, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 33 -; GFX9-NEXT: s_lshr_b32 s46, s41, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 34 -; GFX9-NEXT: s_lshr_b32 s46, s40, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 35 -; GFX9-NEXT: s_lshr_b32 s46, s40, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 36 -; GFX9-NEXT: s_lshr_b32 s46, s43, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 37 -; GFX9-NEXT: s_lshr_b32 s46, s43, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 38 -; GFX9-NEXT: s_lshr_b32 s46, s43, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 39 -; GFX9-NEXT: s_lshr_b32 s46, s42, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 40 -; GFX9-NEXT: s_lshr_b32 s46, s42, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 41 -; GFX9-NEXT: s_lshr_b32 s46, s45, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 42 -; GFX9-NEXT: s_lshr_b32 s46, s45, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 43 -; GFX9-NEXT: s_lshr_b32 s46, s45, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 44 -; GFX9-NEXT: s_lshr_b32 s46, s44, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 45 -; GFX9-NEXT: s_lshr_b32 s46, s44, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 46 -; GFX9-NEXT: s_lshr_b32 s46, s29, 24 -; GFX9-NEXT: v_writelane_b32 v21, s46, 47 -; GFX9-NEXT: s_lshr_b32 s46, s29, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 48 -; GFX9-NEXT: s_lshr_b32 s46, s29, 8 -; GFX9-NEXT: v_writelane_b32 v21, s46, 49 -; GFX9-NEXT: s_lshr_b32 s46, s28, 16 -; GFX9-NEXT: v_writelane_b32 v21, s46, 50 -; GFX9-NEXT: s_lshr_b64 s[56:57], s[4:5], 24 -; GFX9-NEXT: v_writelane_b32 v21, s56, 0 -; GFX9-NEXT: s_lshr_b32 s82, s28, 8 -; GFX9-NEXT: s_lshr_b32 s83, s27, 24 -; GFX9-NEXT: s_lshr_b32 s81, s27, 16 -; GFX9-NEXT: s_lshr_b32 s84, s27, 8 -; GFX9-NEXT: s_lshr_b32 s85, s26, 16 -; GFX9-NEXT: s_lshr_b32 s86, s26, 8 -; GFX9-NEXT: s_lshr_b32 s87, s25, 24 -; GFX9-NEXT: s_lshr_b32 s96, s25, 16 -; GFX9-NEXT: s_lshr_b32 s97, s25, 8 -; GFX9-NEXT: s_lshr_b32 s98, s24, 16 -; GFX9-NEXT: s_lshr_b32 s99, s24, 8 -; GFX9-NEXT: s_lshr_b32 s38, s23, 24 -; GFX9-NEXT: s_lshr_b32 s39, s23, 16 -; GFX9-NEXT: s_lshr_b32 s48, s23, 8 -; GFX9-NEXT: s_lshr_b32 s49, s22, 16 -; GFX9-NEXT: s_lshr_b32 s50, s22, 8 -; GFX9-NEXT: s_lshr_b32 s51, s21, 24 -; GFX9-NEXT: s_lshr_b32 s52, s21, 16 -; GFX9-NEXT: s_lshr_b32 s53, s21, 8 -; GFX9-NEXT: s_lshr_b32 s54, s20, 16 -; GFX9-NEXT: s_lshr_b32 s55, s20, 8 -; GFX9-NEXT: s_lshr_b32 s64, s19, 24 -; GFX9-NEXT: s_lshr_b32 s65, s19, 16 -; GFX9-NEXT: s_lshr_b32 s66, s19, 8 -; GFX9-NEXT: s_lshr_b32 s67, s18, 16 -; GFX9-NEXT: s_lshr_b32 s68, s18, 8 -; GFX9-NEXT: s_lshr_b32 s69, s17, 24 -; GFX9-NEXT: s_lshr_b32 s70, s17, 16 -; GFX9-NEXT: s_lshr_b32 s71, s17, 8 -; GFX9-NEXT: s_lshr_b32 s80, s16, 16 -; GFX9-NEXT: s_lshr_b32 s46, s16, 8 -; GFX9-NEXT: v_writelane_b32 v21, s57, 1 -; GFX9-NEXT: s_lshr_b64 s[56:57], s[6:7], 24 +; GFX9-NEXT: s_lshr_b32 s26, s5, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 2 +; GFX9-NEXT: s_lshr_b32 s26, s5, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 3 +; GFX9-NEXT: s_lshr_b32 s26, s5, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 4 +; GFX9-NEXT: s_lshr_b32 s26, s4, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 5 +; GFX9-NEXT: s_lshr_b32 s26, s4, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 6 +; GFX9-NEXT: s_lshr_b32 s26, s7, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 7 +; GFX9-NEXT: s_lshr_b32 s26, s7, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 8 +; GFX9-NEXT: s_lshr_b32 s26, s7, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 9 +; GFX9-NEXT: s_lshr_b32 s26, s6, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 10 +; GFX9-NEXT: s_lshr_b32 s26, s6, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 11 +; GFX9-NEXT: s_lshr_b32 s26, s9, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 12 +; GFX9-NEXT: s_lshr_b32 s26, s9, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 13 +; GFX9-NEXT: s_lshr_b32 s26, s9, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 14 +; GFX9-NEXT: s_lshr_b32 s26, s8, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 15 +; GFX9-NEXT: s_lshr_b32 s26, s8, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 16 +; GFX9-NEXT: s_lshr_b32 s26, s11, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 17 +; GFX9-NEXT: s_lshr_b32 s26, s11, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 18 +; GFX9-NEXT: s_lshr_b32 s26, s11, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 19 +; GFX9-NEXT: s_lshr_b32 s26, s10, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 20 +; GFX9-NEXT: s_lshr_b32 s26, s10, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 21 +; GFX9-NEXT: s_lshr_b32 s26, s13, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 22 +; GFX9-NEXT: s_lshr_b32 s26, s13, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 23 +; GFX9-NEXT: s_lshr_b32 s26, s13, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 24 +; GFX9-NEXT: s_lshr_b32 s26, s12, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 25 +; GFX9-NEXT: s_lshr_b32 s26, s12, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 26 +; GFX9-NEXT: s_lshr_b32 s26, s15, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 27 +; GFX9-NEXT: s_lshr_b32 s26, s15, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 28 +; GFX9-NEXT: s_lshr_b32 s26, s15, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 29 +; GFX9-NEXT: s_lshr_b32 s26, s14, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 30 +; GFX9-NEXT: s_lshr_b32 s26, s14, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 31 +; GFX9-NEXT: s_lshr_b32 s26, s17, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 32 +; GFX9-NEXT: s_lshr_b32 s26, s17, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 33 +; GFX9-NEXT: s_lshr_b32 s26, s17, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 34 +; GFX9-NEXT: s_lshr_b32 s26, s16, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 35 +; GFX9-NEXT: s_lshr_b32 s26, s16, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 36 +; GFX9-NEXT: s_lshr_b32 s26, s19, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 37 +; GFX9-NEXT: s_lshr_b32 s26, s19, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 38 +; GFX9-NEXT: s_lshr_b32 s26, s19, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 39 +; GFX9-NEXT: s_lshr_b32 s26, s18, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 40 +; GFX9-NEXT: s_lshr_b32 s26, s18, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 41 +; GFX9-NEXT: s_lshr_b32 s26, s21, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 42 +; GFX9-NEXT: s_lshr_b32 s26, s21, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 43 +; GFX9-NEXT: s_lshr_b32 s26, s21, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 44 +; GFX9-NEXT: s_lshr_b32 s26, s20, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 45 +; GFX9-NEXT: s_lshr_b32 s26, s20, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 46 +; GFX9-NEXT: s_lshr_b32 s26, s23, 24 +; GFX9-NEXT: v_writelane_b32 v22, s26, 47 +; GFX9-NEXT: s_lshr_b32 s26, s23, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 48 +; GFX9-NEXT: s_lshr_b32 s26, s23, 8 +; GFX9-NEXT: v_writelane_b32 v22, s26, 49 +; GFX9-NEXT: s_lshr_b32 s26, s22, 16 +; GFX9-NEXT: v_writelane_b32 v22, s26, 50 +; GFX9-NEXT: s_lshr_b64 s[28:29], s[4:5], 24 +; GFX9-NEXT: v_writelane_b32 v22, s28, 0 +; GFX9-NEXT: s_lshr_b32 s82, s22, 8 +; GFX9-NEXT: s_lshr_b32 s83, s25, 24 +; GFX9-NEXT: s_lshr_b32 s81, s25, 16 +; GFX9-NEXT: s_lshr_b32 s84, s25, 8 +; GFX9-NEXT: s_lshr_b32 s85, s24, 16 +; GFX9-NEXT: s_lshr_b32 s86, s24, 8 +; GFX9-NEXT: s_lshr_b32 s87, s41, 24 +; GFX9-NEXT: s_lshr_b32 s96, s41, 16 +; GFX9-NEXT: s_lshr_b32 s97, s41, 8 +; GFX9-NEXT: s_lshr_b32 s98, s40, 16 +; GFX9-NEXT: s_lshr_b32 s99, s40, 8 +; GFX9-NEXT: s_lshr_b32 s38, s43, 24 +; GFX9-NEXT: s_lshr_b32 s39, s43, 16 +; GFX9-NEXT: s_lshr_b32 s48, s43, 8 +; GFX9-NEXT: s_lshr_b32 s49, s42, 16 +; GFX9-NEXT: s_lshr_b32 s50, s42, 8 +; GFX9-NEXT: s_lshr_b32 s51, s45, 24 +; GFX9-NEXT: s_lshr_b32 s52, s45, 16 +; GFX9-NEXT: s_lshr_b32 s53, s45, 8 +; GFX9-NEXT: s_lshr_b32 s54, s44, 16 +; GFX9-NEXT: s_lshr_b32 s55, s44, 8 +; GFX9-NEXT: s_lshr_b32 s64, s47, 24 +; GFX9-NEXT: s_lshr_b32 s65, s47, 16 +; GFX9-NEXT: s_lshr_b32 s66, s47, 8 +; GFX9-NEXT: s_lshr_b32 s67, s46, 16 +; GFX9-NEXT: s_lshr_b32 s68, s46, 8 +; GFX9-NEXT: s_lshr_b32 s69, s57, 24 +; GFX9-NEXT: s_lshr_b32 s70, s57, 16 +; GFX9-NEXT: s_lshr_b32 s71, s57, 8 +; GFX9-NEXT: s_lshr_b32 s80, s56, 16 +; GFX9-NEXT: s_lshr_b32 s26, s56, 8 +; GFX9-NEXT: v_writelane_b32 v22, s29, 1 +; GFX9-NEXT: s_lshr_b64 s[28:29], s[6:7], 24 ; GFX9-NEXT: s_lshr_b64 s[58:59], s[8:9], 24 ; GFX9-NEXT: s_lshr_b64 s[60:61], s[10:11], 24 ; GFX9-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 ; GFX9-NEXT: s_lshr_b64 s[72:73], s[14:15], 24 -; GFX9-NEXT: s_lshr_b64 s[74:75], s[40:41], 24 -; GFX9-NEXT: s_lshr_b64 s[76:77], s[42:43], 24 -; GFX9-NEXT: s_lshr_b64 s[78:79], s[44:45], 24 -; GFX9-NEXT: s_lshr_b64 s[88:89], s[28:29], 24 -; GFX9-NEXT: s_lshr_b64 s[90:91], s[26:27], 24 -; GFX9-NEXT: s_lshr_b64 s[92:93], s[24:25], 24 -; GFX9-NEXT: s_lshr_b64 s[94:95], s[22:23], 24 -; GFX9-NEXT: s_lshr_b64 s[30:31], s[20:21], 24 -; GFX9-NEXT: s_lshr_b64 s[34:35], s[18:19], 24 -; GFX9-NEXT: s_lshr_b64 s[36:37], s[16:17], 24 +; GFX9-NEXT: s_lshr_b64 s[74:75], s[16:17], 24 +; GFX9-NEXT: s_lshr_b64 s[76:77], s[18:19], 24 +; GFX9-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 +; GFX9-NEXT: s_lshr_b64 s[88:89], s[22:23], 24 +; GFX9-NEXT: s_lshr_b64 s[90:91], s[24:25], 24 +; GFX9-NEXT: s_lshr_b64 s[92:93], s[40:41], 24 +; GFX9-NEXT: s_lshr_b64 s[94:95], s[42:43], 24 +; GFX9-NEXT: s_lshr_b64 s[30:31], s[44:45], 24 +; GFX9-NEXT: s_lshr_b64 s[34:35], s[46:47], 24 +; GFX9-NEXT: s_lshr_b64 s[36:37], s[56:57], 24 ; GFX9-NEXT: .LBB57_3: ; %end -; GFX9-NEXT: s_lshl_b32 s46, s46, 8 -; GFX9-NEXT: s_and_b32 s16, s16, 0xff -; GFX9-NEXT: s_or_b32 s16, s16, s46 -; GFX9-NEXT: s_lshl_b32 s46, s36, 8 -; GFX9-NEXT: s_and_b32 s47, s80, 0xff -; GFX9-NEXT: s_or_b32 s46, s47, s46 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s46, s46, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s46 -; GFX9-NEXT: v_mov_b32_e32 v1, s16 -; GFX9-NEXT: s_and_b32 s16, s17, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s71, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: s_and_b32 s17, s70, 0xff -; GFX9-NEXT: s_lshl_b32 s46, s69, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s46 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v2, s16 -; GFX9-NEXT: s_lshl_b32 s16, s68, 8 -; GFX9-NEXT: s_and_b32 s17, s18, 0xff -; GFX9-NEXT: s_or_b32 s16, s17, s16 -; GFX9-NEXT: s_lshl_b32 s17, s34, 8 -; GFX9-NEXT: s_and_b32 s18, s67, 0xff -; GFX9-NEXT: s_or_b32 s17, s18, s17 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v3, s16 -; GFX9-NEXT: s_and_b32 s16, s19, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s66, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: s_and_b32 s17, s65, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s64, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v4, s16 -; GFX9-NEXT: s_lshl_b32 s16, s55, 8 -; GFX9-NEXT: s_and_b32 s17, s20, 0xff -; GFX9-NEXT: s_or_b32 s16, s17, s16 -; GFX9-NEXT: s_lshl_b32 s17, s30, 8 -; GFX9-NEXT: s_and_b32 s18, s54, 0xff -; GFX9-NEXT: s_or_b32 s17, s18, s17 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v5, s16 -; GFX9-NEXT: s_and_b32 s16, s21, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s53, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: s_and_b32 s17, s52, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s51, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v6, s16 -; GFX9-NEXT: s_lshl_b32 s16, s50, 8 -; GFX9-NEXT: s_and_b32 s17, s22, 0xff -; GFX9-NEXT: s_or_b32 s16, s17, s16 -; GFX9-NEXT: s_lshl_b32 s17, s94, 8 -; GFX9-NEXT: s_and_b32 s18, s49, 0xff -; GFX9-NEXT: s_or_b32 s17, s18, s17 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v7, s16 -; GFX9-NEXT: s_and_b32 s16, s23, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s48, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: s_and_b32 s17, s39, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s38, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v8, s16 -; GFX9-NEXT: s_lshl_b32 s16, s99, 8 -; GFX9-NEXT: s_and_b32 s17, s24, 0xff -; GFX9-NEXT: s_or_b32 s16, s17, s16 -; GFX9-NEXT: s_lshl_b32 s17, s92, 8 -; GFX9-NEXT: s_and_b32 s18, s98, 0xff -; GFX9-NEXT: s_or_b32 s17, s18, s17 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v9, s16 -; GFX9-NEXT: s_and_b32 s16, s25, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s97, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: s_and_b32 s17, s96, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s87, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v10, s16 -; GFX9-NEXT: s_lshl_b32 s16, s86, 8 -; GFX9-NEXT: s_and_b32 s17, s26, 0xff -; GFX9-NEXT: s_or_b32 s16, s17, s16 -; GFX9-NEXT: s_lshl_b32 s17, s90, 8 -; GFX9-NEXT: s_and_b32 s18, s85, 0xff -; GFX9-NEXT: s_or_b32 s17, s18, s17 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v11, s16 -; GFX9-NEXT: s_and_b32 s16, s27, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s84, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: s_and_b32 s17, s81, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s83, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_mov_b32_e32 v12, s16 -; GFX9-NEXT: s_lshl_b32 s16, s82, 8 -; GFX9-NEXT: s_and_b32 s17, s28, 0xff -; GFX9-NEXT: v_readlane_b32 s18, v21, 50 -; GFX9-NEXT: s_or_b32 s16, s17, s16 -; GFX9-NEXT: s_lshl_b32 s17, s88, 8 -; GFX9-NEXT: s_and_b32 s18, s18, 0xff -; GFX9-NEXT: s_or_b32 s17, s18, s17 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 49 -; GFX9-NEXT: v_mov_b32_e32 v13, s16 -; GFX9-NEXT: s_and_b32 s16, s29, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s17, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 48 -; GFX9-NEXT: v_readlane_b32 s18, v21, 47 -; GFX9-NEXT: s_and_b32 s17, s17, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s18, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 46 +; GFX9-NEXT: s_lshl_b32 s26, s26, 8 +; GFX9-NEXT: s_and_b32 s27, s56, 0xff +; GFX9-NEXT: s_or_b32 s26, s27, s26 +; GFX9-NEXT: s_lshl_b32 s27, s36, 8 +; GFX9-NEXT: s_and_b32 s29, s80, 0xff +; GFX9-NEXT: s_or_b32 s27, s29, s27 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v1, s26 +; GFX9-NEXT: s_and_b32 s26, s57, 0xff +; GFX9-NEXT: s_lshl_b32 s27, s71, 8 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: s_and_b32 s27, s70, 0xff +; GFX9-NEXT: s_lshl_b32 s29, s69, 8 +; GFX9-NEXT: s_or_b32 s27, s27, s29 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v2, s26 +; GFX9-NEXT: s_lshl_b32 s26, s68, 8 +; GFX9-NEXT: s_and_b32 s27, s46, 0xff +; GFX9-NEXT: s_or_b32 s26, s27, s26 +; GFX9-NEXT: s_lshl_b32 s27, s34, 8 +; GFX9-NEXT: s_and_b32 s29, s67, 0xff +; GFX9-NEXT: s_or_b32 s27, s29, s27 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v3, s26 +; GFX9-NEXT: s_and_b32 s26, s47, 0xff +; GFX9-NEXT: s_lshl_b32 s27, s66, 8 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: s_and_b32 s27, s65, 0xff +; GFX9-NEXT: s_lshl_b32 s29, s64, 8 +; GFX9-NEXT: s_or_b32 s27, s27, s29 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v4, s26 +; GFX9-NEXT: s_lshl_b32 s26, s55, 8 +; GFX9-NEXT: s_and_b32 s27, s44, 0xff +; GFX9-NEXT: s_or_b32 s26, s27, s26 +; GFX9-NEXT: s_lshl_b32 s27, s30, 8 +; GFX9-NEXT: s_and_b32 s29, s54, 0xff +; GFX9-NEXT: s_or_b32 s27, s29, s27 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v5, s26 +; GFX9-NEXT: s_and_b32 s26, s45, 0xff +; GFX9-NEXT: s_lshl_b32 s27, s53, 8 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: s_and_b32 s27, s52, 0xff +; GFX9-NEXT: s_lshl_b32 s29, s51, 8 +; GFX9-NEXT: s_or_b32 s27, s27, s29 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v6, s26 +; GFX9-NEXT: s_lshl_b32 s26, s50, 8 +; GFX9-NEXT: s_and_b32 s27, s42, 0xff +; GFX9-NEXT: s_or_b32 s26, s27, s26 +; GFX9-NEXT: s_lshl_b32 s27, s94, 8 +; GFX9-NEXT: s_and_b32 s29, s49, 0xff +; GFX9-NEXT: s_or_b32 s27, s29, s27 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v7, s26 +; GFX9-NEXT: s_and_b32 s26, s43, 0xff +; GFX9-NEXT: s_lshl_b32 s27, s48, 8 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: s_and_b32 s27, s39, 0xff +; GFX9-NEXT: s_lshl_b32 s29, s38, 8 +; GFX9-NEXT: s_or_b32 s27, s27, s29 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v8, s26 +; GFX9-NEXT: s_lshl_b32 s26, s99, 8 +; GFX9-NEXT: s_and_b32 s27, s40, 0xff +; GFX9-NEXT: s_or_b32 s26, s27, s26 +; GFX9-NEXT: s_lshl_b32 s27, s92, 8 +; GFX9-NEXT: s_and_b32 s29, s98, 0xff +; GFX9-NEXT: s_or_b32 s27, s29, s27 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v9, s26 +; GFX9-NEXT: s_and_b32 s26, s41, 0xff +; GFX9-NEXT: s_lshl_b32 s27, s97, 8 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: s_and_b32 s27, s96, 0xff +; GFX9-NEXT: s_lshl_b32 s29, s87, 8 +; GFX9-NEXT: s_or_b32 s27, s27, s29 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v10, s26 +; GFX9-NEXT: s_lshl_b32 s26, s86, 8 +; GFX9-NEXT: s_and_b32 s24, s24, 0xff +; GFX9-NEXT: s_or_b32 s24, s24, s26 +; GFX9-NEXT: s_lshl_b32 s26, s90, 8 +; GFX9-NEXT: s_and_b32 s27, s85, 0xff +; GFX9-NEXT: s_or_b32 s26, s27, s26 +; GFX9-NEXT: s_and_b32 s24, s24, 0xffff +; GFX9-NEXT: s_lshl_b32 s26, s26, 16 +; GFX9-NEXT: s_or_b32 s24, s24, s26 +; GFX9-NEXT: v_mov_b32_e32 v11, s24 +; GFX9-NEXT: s_and_b32 s24, s25, 0xff +; GFX9-NEXT: s_lshl_b32 s25, s84, 8 +; GFX9-NEXT: s_or_b32 s24, s24, s25 +; GFX9-NEXT: s_and_b32 s25, s81, 0xff +; GFX9-NEXT: s_lshl_b32 s26, s83, 8 +; GFX9-NEXT: s_or_b32 s25, s25, s26 +; GFX9-NEXT: s_and_b32 s24, s24, 0xffff +; GFX9-NEXT: s_lshl_b32 s25, s25, 16 +; GFX9-NEXT: s_or_b32 s24, s24, s25 +; GFX9-NEXT: v_mov_b32_e32 v12, s24 +; GFX9-NEXT: s_lshl_b32 s24, s82, 8 +; GFX9-NEXT: s_and_b32 s22, s22, 0xff +; GFX9-NEXT: v_readlane_b32 s25, v22, 50 +; GFX9-NEXT: s_or_b32 s22, s22, s24 +; GFX9-NEXT: s_lshl_b32 s24, s88, 8 +; GFX9-NEXT: s_and_b32 s25, s25, 0xff +; GFX9-NEXT: s_or_b32 s24, s25, s24 +; GFX9-NEXT: s_and_b32 s22, s22, 0xffff +; GFX9-NEXT: s_lshl_b32 s24, s24, 16 +; GFX9-NEXT: s_or_b32 s22, s22, s24 +; GFX9-NEXT: v_mov_b32_e32 v13, s22 +; GFX9-NEXT: s_and_b32 s22, s23, 0xff +; GFX9-NEXT: v_readlane_b32 s23, v22, 49 +; GFX9-NEXT: s_lshl_b32 s23, s23, 8 +; GFX9-NEXT: s_or_b32 s22, s22, s23 +; GFX9-NEXT: v_readlane_b32 s23, v22, 48 +; GFX9-NEXT: v_readlane_b32 s24, v22, 47 +; GFX9-NEXT: s_and_b32 s23, s23, 0xff +; GFX9-NEXT: s_lshl_b32 s24, s24, 8 +; GFX9-NEXT: s_or_b32 s23, s23, s24 +; GFX9-NEXT: s_and_b32 s22, s22, 0xffff +; GFX9-NEXT: s_lshl_b32 s23, s23, 16 +; GFX9-NEXT: s_or_b32 s22, s22, s23 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:4 ; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:8 @@ -84137,79 +83181,80 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:40 ; GFX9-NEXT: buffer_store_dword v12, v0, s[0:3], 0 offen offset:44 ; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:48 -; GFX9-NEXT: v_mov_b32_e32 v1, s16 -; GFX9-NEXT: s_and_b32 s16, s44, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s17, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 45 -; GFX9-NEXT: s_and_b32 s17, s17, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s78, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 44 +; GFX9-NEXT: v_mov_b32_e32 v1, s22 +; GFX9-NEXT: v_readlane_b32 s22, v22, 46 +; GFX9-NEXT: s_and_b32 s20, s20, 0xff +; GFX9-NEXT: s_lshl_b32 s22, s22, 8 +; GFX9-NEXT: s_or_b32 s20, s20, s22 +; GFX9-NEXT: v_readlane_b32 s22, v22, 45 +; GFX9-NEXT: s_and_b32 s22, s22, 0xff +; GFX9-NEXT: s_lshl_b32 s23, s78, 8 +; GFX9-NEXT: s_or_b32 s22, s22, s23 +; GFX9-NEXT: s_and_b32 s20, s20, 0xffff +; GFX9-NEXT: s_lshl_b32 s22, s22, 16 +; GFX9-NEXT: s_or_b32 s20, s20, s22 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52 -; GFX9-NEXT: v_mov_b32_e32 v1, s16 -; GFX9-NEXT: s_and_b32 s16, s45, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s17, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 43 -; GFX9-NEXT: v_readlane_b32 s18, v21, 42 -; GFX9-NEXT: s_and_b32 s17, s17, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s18, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 41 +; GFX9-NEXT: v_mov_b32_e32 v1, s20 +; GFX9-NEXT: s_and_b32 s20, s21, 0xff +; GFX9-NEXT: v_readlane_b32 s21, v22, 44 +; GFX9-NEXT: s_lshl_b32 s21, s21, 8 +; GFX9-NEXT: s_or_b32 s20, s20, s21 +; GFX9-NEXT: v_readlane_b32 s21, v22, 43 +; GFX9-NEXT: v_readlane_b32 s22, v22, 42 +; GFX9-NEXT: s_and_b32 s21, s21, 0xff +; GFX9-NEXT: s_lshl_b32 s22, s22, 8 +; GFX9-NEXT: s_or_b32 s21, s21, s22 +; GFX9-NEXT: s_and_b32 s20, s20, 0xffff +; GFX9-NEXT: s_lshl_b32 s21, s21, 16 +; GFX9-NEXT: s_or_b32 s20, s20, s21 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56 -; GFX9-NEXT: v_mov_b32_e32 v1, s16 -; GFX9-NEXT: s_and_b32 s16, s42, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s17, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 40 -; GFX9-NEXT: s_and_b32 s17, s17, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s76, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 39 +; GFX9-NEXT: v_mov_b32_e32 v1, s20 +; GFX9-NEXT: v_readlane_b32 s20, v22, 41 +; GFX9-NEXT: s_and_b32 s18, s18, 0xff +; GFX9-NEXT: s_lshl_b32 s20, s20, 8 +; GFX9-NEXT: s_or_b32 s18, s18, s20 +; GFX9-NEXT: v_readlane_b32 s20, v22, 40 +; GFX9-NEXT: s_and_b32 s20, s20, 0xff +; GFX9-NEXT: s_lshl_b32 s21, s76, 8 +; GFX9-NEXT: s_or_b32 s20, s20, s21 +; GFX9-NEXT: s_and_b32 s18, s18, 0xffff +; GFX9-NEXT: s_lshl_b32 s20, s20, 16 +; GFX9-NEXT: s_or_b32 s18, s18, s20 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60 -; GFX9-NEXT: v_mov_b32_e32 v1, s16 -; GFX9-NEXT: s_and_b32 s16, s43, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s17, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 38 -; GFX9-NEXT: v_readlane_b32 s18, v21, 37 -; GFX9-NEXT: s_and_b32 s17, s17, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s18, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 -; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 36 +; GFX9-NEXT: v_mov_b32_e32 v1, s18 +; GFX9-NEXT: s_and_b32 s18, s19, 0xff +; GFX9-NEXT: v_readlane_b32 s19, v22, 39 +; GFX9-NEXT: s_lshl_b32 s19, s19, 8 +; GFX9-NEXT: s_or_b32 s18, s18, s19 +; GFX9-NEXT: v_readlane_b32 s19, v22, 38 +; GFX9-NEXT: v_readlane_b32 s20, v22, 37 +; GFX9-NEXT: s_and_b32 s19, s19, 0xff +; GFX9-NEXT: s_lshl_b32 s20, s20, 8 +; GFX9-NEXT: s_or_b32 s19, s19, s20 +; GFX9-NEXT: s_and_b32 s18, s18, 0xffff +; GFX9-NEXT: s_lshl_b32 s19, s19, 16 +; GFX9-NEXT: s_or_b32 s18, s18, s19 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:64 -; GFX9-NEXT: v_mov_b32_e32 v1, s16 -; GFX9-NEXT: s_and_b32 s16, s40, 0xff -; GFX9-NEXT: s_lshl_b32 s17, s17, 8 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 35 -; GFX9-NEXT: s_and_b32 s17, s17, 0xff -; GFX9-NEXT: s_lshl_b32 s18, s74, 8 -; GFX9-NEXT: s_or_b32 s17, s17, s18 +; GFX9-NEXT: v_mov_b32_e32 v1, s18 +; GFX9-NEXT: v_readlane_b32 s18, v22, 36 +; GFX9-NEXT: s_and_b32 s16, s16, 0xff +; GFX9-NEXT: s_lshl_b32 s18, s18, 8 +; GFX9-NEXT: s_or_b32 s16, s16, s18 +; GFX9-NEXT: v_readlane_b32 s18, v22, 35 +; GFX9-NEXT: s_and_b32 s18, s18, 0xff +; GFX9-NEXT: s_lshl_b32 s19, s74, 8 +; GFX9-NEXT: s_or_b32 s18, s18, s19 ; GFX9-NEXT: s_and_b32 s16, s16, 0xffff -; GFX9-NEXT: s_lshl_b32 s17, s17, 16 -; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 34 +; GFX9-NEXT: s_lshl_b32 s18, s18, 16 +; GFX9-NEXT: s_or_b32 s16, s16, s18 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:68 ; GFX9-NEXT: v_mov_b32_e32 v1, s16 -; GFX9-NEXT: s_and_b32 s16, s41, 0xff +; GFX9-NEXT: s_and_b32 s16, s17, 0xff +; GFX9-NEXT: v_readlane_b32 s17, v22, 34 ; GFX9-NEXT: s_lshl_b32 s17, s17, 8 ; GFX9-NEXT: s_or_b32 s16, s16, s17 -; GFX9-NEXT: v_readlane_b32 s17, v21, 33 -; GFX9-NEXT: v_readlane_b32 s18, v21, 32 +; GFX9-NEXT: v_readlane_b32 s17, v22, 33 +; GFX9-NEXT: v_readlane_b32 s18, v22, 32 ; GFX9-NEXT: s_and_b32 s17, s17, 0xff ; GFX9-NEXT: s_lshl_b32 s18, s18, 8 ; GFX9-NEXT: s_or_b32 s17, s17, s18 @@ -84218,11 +83263,11 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX9-NEXT: s_or_b32 s16, s16, s17 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:72 ; GFX9-NEXT: v_mov_b32_e32 v1, s16 -; GFX9-NEXT: v_readlane_b32 s16, v21, 31 +; GFX9-NEXT: v_readlane_b32 s16, v22, 31 ; GFX9-NEXT: s_and_b32 s14, s14, 0xff ; GFX9-NEXT: s_lshl_b32 s16, s16, 8 ; GFX9-NEXT: s_or_b32 s14, s14, s16 -; GFX9-NEXT: v_readlane_b32 s16, v21, 30 +; GFX9-NEXT: v_readlane_b32 s16, v22, 30 ; GFX9-NEXT: s_and_b32 s16, s16, 0xff ; GFX9-NEXT: s_lshl_b32 s17, s72, 8 ; GFX9-NEXT: s_or_b32 s16, s16, s17 @@ -84232,11 +83277,11 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:76 ; GFX9-NEXT: v_mov_b32_e32 v1, s14 ; GFX9-NEXT: s_and_b32 s14, s15, 0xff -; GFX9-NEXT: v_readlane_b32 s15, v21, 29 +; GFX9-NEXT: v_readlane_b32 s15, v22, 29 ; GFX9-NEXT: s_lshl_b32 s15, s15, 8 ; GFX9-NEXT: s_or_b32 s14, s14, s15 -; GFX9-NEXT: v_readlane_b32 s15, v21, 28 -; GFX9-NEXT: v_readlane_b32 s16, v21, 27 +; GFX9-NEXT: v_readlane_b32 s15, v22, 28 +; GFX9-NEXT: v_readlane_b32 s16, v22, 27 ; GFX9-NEXT: s_and_b32 s15, s15, 0xff ; GFX9-NEXT: s_lshl_b32 s16, s16, 8 ; GFX9-NEXT: s_or_b32 s15, s15, s16 @@ -84245,11 +83290,11 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX9-NEXT: s_or_b32 s14, s14, s15 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:80 ; GFX9-NEXT: v_mov_b32_e32 v1, s14 -; GFX9-NEXT: v_readlane_b32 s14, v21, 26 +; GFX9-NEXT: v_readlane_b32 s14, v22, 26 ; GFX9-NEXT: s_and_b32 s12, s12, 0xff ; GFX9-NEXT: s_lshl_b32 s14, s14, 8 ; GFX9-NEXT: s_or_b32 s12, s12, s14 -; GFX9-NEXT: v_readlane_b32 s14, v21, 25 +; GFX9-NEXT: v_readlane_b32 s14, v22, 25 ; GFX9-NEXT: s_and_b32 s14, s14, 0xff ; GFX9-NEXT: s_lshl_b32 s15, s62, 8 ; GFX9-NEXT: s_or_b32 s14, s14, s15 @@ -84259,11 +83304,11 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:84 ; GFX9-NEXT: v_mov_b32_e32 v1, s12 ; GFX9-NEXT: s_and_b32 s12, s13, 0xff -; GFX9-NEXT: v_readlane_b32 s13, v21, 24 +; GFX9-NEXT: v_readlane_b32 s13, v22, 24 ; GFX9-NEXT: s_lshl_b32 s13, s13, 8 ; GFX9-NEXT: s_or_b32 s12, s12, s13 -; GFX9-NEXT: v_readlane_b32 s13, v21, 23 -; GFX9-NEXT: v_readlane_b32 s14, v21, 22 +; GFX9-NEXT: v_readlane_b32 s13, v22, 23 +; GFX9-NEXT: v_readlane_b32 s14, v22, 22 ; GFX9-NEXT: s_and_b32 s13, s13, 0xff ; GFX9-NEXT: s_lshl_b32 s14, s14, 8 ; GFX9-NEXT: s_or_b32 s13, s13, s14 @@ -84272,11 +83317,11 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX9-NEXT: s_or_b32 s12, s12, s13 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:88 ; GFX9-NEXT: v_mov_b32_e32 v1, s12 -; GFX9-NEXT: v_readlane_b32 s12, v21, 21 +; GFX9-NEXT: v_readlane_b32 s12, v22, 21 ; GFX9-NEXT: s_and_b32 s10, s10, 0xff ; GFX9-NEXT: s_lshl_b32 s12, s12, 8 ; GFX9-NEXT: s_or_b32 s10, s10, s12 -; GFX9-NEXT: v_readlane_b32 s12, v21, 20 +; GFX9-NEXT: v_readlane_b32 s12, v22, 20 ; GFX9-NEXT: s_and_b32 s12, s12, 0xff ; GFX9-NEXT: s_lshl_b32 s13, s60, 8 ; GFX9-NEXT: s_or_b32 s12, s12, s13 @@ -84286,11 +83331,11 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:92 ; GFX9-NEXT: v_mov_b32_e32 v1, s10 ; GFX9-NEXT: s_and_b32 s10, s11, 0xff -; GFX9-NEXT: v_readlane_b32 s11, v21, 19 +; GFX9-NEXT: v_readlane_b32 s11, v22, 19 ; GFX9-NEXT: s_lshl_b32 s11, s11, 8 ; GFX9-NEXT: s_or_b32 s10, s10, s11 -; GFX9-NEXT: v_readlane_b32 s11, v21, 18 -; GFX9-NEXT: v_readlane_b32 s12, v21, 17 +; GFX9-NEXT: v_readlane_b32 s11, v22, 18 +; GFX9-NEXT: v_readlane_b32 s12, v22, 17 ; GFX9-NEXT: s_and_b32 s11, s11, 0xff ; GFX9-NEXT: s_lshl_b32 s12, s12, 8 ; GFX9-NEXT: s_or_b32 s11, s11, s12 @@ -84299,11 +83344,11 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX9-NEXT: s_or_b32 s10, s10, s11 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:96 ; GFX9-NEXT: v_mov_b32_e32 v1, s10 -; GFX9-NEXT: v_readlane_b32 s10, v21, 16 +; GFX9-NEXT: v_readlane_b32 s10, v22, 16 ; GFX9-NEXT: s_and_b32 s8, s8, 0xff ; GFX9-NEXT: s_lshl_b32 s10, s10, 8 ; GFX9-NEXT: s_or_b32 s8, s8, s10 -; GFX9-NEXT: v_readlane_b32 s10, v21, 15 +; GFX9-NEXT: v_readlane_b32 s10, v22, 15 ; GFX9-NEXT: s_and_b32 s10, s10, 0xff ; GFX9-NEXT: s_lshl_b32 s11, s58, 8 ; GFX9-NEXT: s_or_b32 s10, s10, s11 @@ -84313,11 +83358,11 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:100 ; GFX9-NEXT: v_mov_b32_e32 v1, s8 ; GFX9-NEXT: s_and_b32 s8, s9, 0xff -; GFX9-NEXT: v_readlane_b32 s9, v21, 14 +; GFX9-NEXT: v_readlane_b32 s9, v22, 14 ; GFX9-NEXT: s_lshl_b32 s9, s9, 8 ; GFX9-NEXT: s_or_b32 s8, s8, s9 -; GFX9-NEXT: v_readlane_b32 s9, v21, 13 -; GFX9-NEXT: v_readlane_b32 s10, v21, 12 +; GFX9-NEXT: v_readlane_b32 s9, v22, 13 +; GFX9-NEXT: v_readlane_b32 s10, v22, 12 ; GFX9-NEXT: s_and_b32 s9, s9, 0xff ; GFX9-NEXT: s_lshl_b32 s10, s10, 8 ; GFX9-NEXT: s_or_b32 s9, s9, s10 @@ -84326,13 +83371,13 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX9-NEXT: s_or_b32 s8, s8, s9 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:104 ; GFX9-NEXT: v_mov_b32_e32 v1, s8 -; GFX9-NEXT: v_readlane_b32 s8, v21, 11 +; GFX9-NEXT: v_readlane_b32 s8, v22, 11 ; GFX9-NEXT: s_and_b32 s6, s6, 0xff ; GFX9-NEXT: s_lshl_b32 s8, s8, 8 ; GFX9-NEXT: s_or_b32 s6, s6, s8 -; GFX9-NEXT: v_readlane_b32 s8, v21, 10 +; GFX9-NEXT: v_readlane_b32 s8, v22, 10 ; GFX9-NEXT: s_and_b32 s8, s8, 0xff -; GFX9-NEXT: s_lshl_b32 s9, s56, 8 +; GFX9-NEXT: s_lshl_b32 s9, s28, 8 ; GFX9-NEXT: s_or_b32 s8, s8, s9 ; GFX9-NEXT: s_and_b32 s6, s6, 0xffff ; GFX9-NEXT: s_lshl_b32 s8, s8, 16 @@ -84340,11 +83385,11 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:108 ; GFX9-NEXT: v_mov_b32_e32 v1, s6 ; GFX9-NEXT: s_and_b32 s6, s7, 0xff -; GFX9-NEXT: v_readlane_b32 s7, v21, 9 +; GFX9-NEXT: v_readlane_b32 s7, v22, 9 ; GFX9-NEXT: s_lshl_b32 s7, s7, 8 ; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: v_readlane_b32 s7, v21, 8 -; GFX9-NEXT: v_readlane_b32 s8, v21, 7 +; GFX9-NEXT: v_readlane_b32 s7, v22, 8 +; GFX9-NEXT: v_readlane_b32 s8, v22, 7 ; GFX9-NEXT: s_and_b32 s7, s7, 0xff ; GFX9-NEXT: s_lshl_b32 s8, s8, 8 ; GFX9-NEXT: s_or_b32 s7, s7, s8 @@ -84353,12 +83398,12 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX9-NEXT: s_or_b32 s6, s6, s7 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:112 ; GFX9-NEXT: v_mov_b32_e32 v1, s6 -; GFX9-NEXT: v_readlane_b32 s6, v21, 6 +; GFX9-NEXT: v_readlane_b32 s6, v22, 6 ; GFX9-NEXT: s_and_b32 s4, s4, 0xff ; GFX9-NEXT: s_lshl_b32 s6, s6, 8 ; GFX9-NEXT: s_or_b32 s4, s4, s6 -; GFX9-NEXT: v_readlane_b32 s6, v21, 5 -; GFX9-NEXT: v_readlane_b32 s8, v21, 0 +; GFX9-NEXT: v_readlane_b32 s6, v22, 5 +; GFX9-NEXT: v_readlane_b32 s8, v22, 0 ; GFX9-NEXT: s_and_b32 s6, s6, 0xff ; GFX9-NEXT: s_lshl_b32 s7, s8, 8 ; GFX9-NEXT: s_or_b32 s6, s6, s7 @@ -84368,11 +83413,11 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:116 ; GFX9-NEXT: v_mov_b32_e32 v1, s4 ; GFX9-NEXT: s_and_b32 s4, s5, 0xff -; GFX9-NEXT: v_readlane_b32 s5, v21, 4 +; GFX9-NEXT: v_readlane_b32 s5, v22, 4 ; GFX9-NEXT: s_lshl_b32 s5, s5, 8 ; GFX9-NEXT: s_or_b32 s4, s4, s5 -; GFX9-NEXT: v_readlane_b32 s5, v21, 3 -; GFX9-NEXT: v_readlane_b32 s6, v21, 2 +; GFX9-NEXT: v_readlane_b32 s5, v22, 3 +; GFX9-NEXT: v_readlane_b32 s6, v22, 2 ; GFX9-NEXT: s_and_b32 s5, s5, 0xff ; GFX9-NEXT: s_lshl_b32 s6, s6, 8 ; GFX9-NEXT: s_or_b32 s5, s5, s6 @@ -84381,61 +83426,61 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX9-NEXT: s_or_b32 s4, s4, s5 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120 ; GFX9-NEXT: v_mov_b32_e32 v1, s4 -; GFX9-NEXT: v_readlane_b32 s9, v21, 1 +; GFX9-NEXT: v_readlane_b32 s9, v22, 1 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124 -; GFX9-NEXT: v_readlane_b32 s99, v20, 35 -; GFX9-NEXT: v_readlane_b32 s98, v20, 34 -; GFX9-NEXT: v_readlane_b32 s97, v20, 33 -; GFX9-NEXT: v_readlane_b32 s96, v20, 32 -; GFX9-NEXT: v_readlane_b32 s87, v20, 31 -; GFX9-NEXT: v_readlane_b32 s86, v20, 30 -; GFX9-NEXT: v_readlane_b32 s85, v20, 29 -; GFX9-NEXT: v_readlane_b32 s84, v20, 28 -; GFX9-NEXT: v_readlane_b32 s83, v20, 27 -; GFX9-NEXT: v_readlane_b32 s82, v20, 26 -; GFX9-NEXT: v_readlane_b32 s81, v20, 25 -; GFX9-NEXT: v_readlane_b32 s80, v20, 24 -; GFX9-NEXT: v_readlane_b32 s71, v20, 23 -; GFX9-NEXT: v_readlane_b32 s70, v20, 22 -; GFX9-NEXT: v_readlane_b32 s69, v20, 21 -; GFX9-NEXT: v_readlane_b32 s68, v20, 20 -; GFX9-NEXT: v_readlane_b32 s67, v20, 19 -; GFX9-NEXT: v_readlane_b32 s66, v20, 18 -; GFX9-NEXT: v_readlane_b32 s65, v20, 17 -; GFX9-NEXT: v_readlane_b32 s64, v20, 16 -; GFX9-NEXT: v_readlane_b32 s55, v20, 15 -; GFX9-NEXT: v_readlane_b32 s54, v20, 14 -; GFX9-NEXT: v_readlane_b32 s53, v20, 13 -; GFX9-NEXT: v_readlane_b32 s52, v20, 12 -; GFX9-NEXT: v_readlane_b32 s51, v20, 11 -; GFX9-NEXT: v_readlane_b32 s50, v20, 10 -; GFX9-NEXT: v_readlane_b32 s49, v20, 9 -; GFX9-NEXT: v_readlane_b32 s48, v20, 8 -; GFX9-NEXT: v_readlane_b32 s39, v20, 7 -; GFX9-NEXT: v_readlane_b32 s38, v20, 6 -; GFX9-NEXT: v_readlane_b32 s37, v20, 5 -; GFX9-NEXT: v_readlane_b32 s36, v20, 4 -; GFX9-NEXT: v_readlane_b32 s35, v20, 3 -; GFX9-NEXT: v_readlane_b32 s34, v20, 2 -; GFX9-NEXT: v_readlane_b32 s31, v20, 1 -; GFX9-NEXT: v_readlane_b32 s30, v20, 0 +; GFX9-NEXT: v_readlane_b32 s99, v21, 35 +; GFX9-NEXT: v_readlane_b32 s98, v21, 34 +; GFX9-NEXT: v_readlane_b32 s97, v21, 33 +; GFX9-NEXT: v_readlane_b32 s96, v21, 32 +; GFX9-NEXT: v_readlane_b32 s87, v21, 31 +; GFX9-NEXT: v_readlane_b32 s86, v21, 30 +; GFX9-NEXT: v_readlane_b32 s85, v21, 29 +; GFX9-NEXT: v_readlane_b32 s84, v21, 28 +; GFX9-NEXT: v_readlane_b32 s83, v21, 27 +; GFX9-NEXT: v_readlane_b32 s82, v21, 26 +; GFX9-NEXT: v_readlane_b32 s81, v21, 25 +; GFX9-NEXT: v_readlane_b32 s80, v21, 24 +; GFX9-NEXT: v_readlane_b32 s71, v21, 23 +; GFX9-NEXT: v_readlane_b32 s70, v21, 22 +; GFX9-NEXT: v_readlane_b32 s69, v21, 21 +; GFX9-NEXT: v_readlane_b32 s68, v21, 20 +; GFX9-NEXT: v_readlane_b32 s67, v21, 19 +; GFX9-NEXT: v_readlane_b32 s66, v21, 18 +; GFX9-NEXT: v_readlane_b32 s65, v21, 17 +; GFX9-NEXT: v_readlane_b32 s64, v21, 16 +; GFX9-NEXT: v_readlane_b32 s55, v21, 15 +; GFX9-NEXT: v_readlane_b32 s54, v21, 14 +; GFX9-NEXT: v_readlane_b32 s53, v21, 13 +; GFX9-NEXT: v_readlane_b32 s52, v21, 12 +; GFX9-NEXT: v_readlane_b32 s51, v21, 11 +; GFX9-NEXT: v_readlane_b32 s50, v21, 10 +; GFX9-NEXT: v_readlane_b32 s49, v21, 9 +; GFX9-NEXT: v_readlane_b32 s48, v21, 8 +; GFX9-NEXT: v_readlane_b32 s39, v21, 7 +; GFX9-NEXT: v_readlane_b32 s38, v21, 6 +; GFX9-NEXT: v_readlane_b32 s37, v21, 5 +; GFX9-NEXT: v_readlane_b32 s36, v21, 4 +; GFX9-NEXT: v_readlane_b32 s35, v21, 3 +; GFX9-NEXT: v_readlane_b32 s34, v21, 2 +; GFX9-NEXT: v_readlane_b32 s31, v21, 1 +; GFX9-NEXT: v_readlane_b32 s30, v21, 0 ; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: .LBB57_4: -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 ; GFX9-NEXT: ; implicit-def: $sgpr83 ; GFX9-NEXT: ; implicit-def: $sgpr82 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: v_writelane_b32 v21, s82, 0 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: v_writelane_b32 v22, s82, 0 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr26 ; GFX9-NEXT: ; implicit-def: $sgpr80 ; GFX9-NEXT: ; implicit-def: $sgpr71 ; GFX9-NEXT: ; implicit-def: $sgpr70 @@ -84478,101 +83523,101 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX9-NEXT: ; implicit-def: $sgpr62 ; GFX9-NEXT: ; implicit-def: $sgpr60 ; GFX9-NEXT: ; implicit-def: $sgpr58 -; GFX9-NEXT: ; implicit-def: $sgpr56 -; GFX9-NEXT: v_writelane_b32 v21, s83, 1 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 +; GFX9-NEXT: ; implicit-def: $sgpr28 +; GFX9-NEXT: v_writelane_b32 v22, s83, 1 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 ; GFX9-NEXT: ; implicit-def: $sgpr82 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 -; GFX9-NEXT: ; implicit-def: $sgpr47 -; GFX9-NEXT: ; kill: killed $sgpr47 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 +; GFX9-NEXT: ; implicit-def: $sgpr27 +; GFX9-NEXT: ; kill: killed $sgpr27 ; GFX9-NEXT: s_branch .LBB57_2 ; ; GFX11-LABEL: bitcast_v16i64_to_v128i8_scalar: @@ -84580,213 +83625,240 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_xor_saveexec_b32 s4, -1 ; GFX11-NEXT: s_clause 0x3 ; 16-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v16, s32 -; GFX11-NEXT: scratch_store_b32 off, v17, s32 offset:4 -; GFX11-NEXT: scratch_store_b32 off, v18, s32 offset:8 -; GFX11-NEXT: scratch_store_b32 off, v19, s32 offset:12 +; GFX11-NEXT: scratch_store_b32 off, v34, s32 +; GFX11-NEXT: scratch_store_b32 off, v35, s32 offset:4 +; GFX11-NEXT: scratch_store_b32 off, v36, s32 offset:8 +; GFX11-NEXT: scratch_store_b32 off, v37, s32 offset:12 ; GFX11-NEXT: s_mov_b32 exec_lo, s4 -; GFX11-NEXT: v_writelane_b32 v16, s30, 0 -; GFX11-NEXT: v_writelane_b32 v17, s96, 0 +; GFX11-NEXT: v_writelane_b32 v34, s30, 0 +; GFX11-NEXT: v_writelane_b32 v35, s96, 0 +; GFX11-NEXT: v_dual_mov_b32 v16, s0 :: v_dual_mov_b32 v17, s1 +; GFX11-NEXT: v_dual_mov_b32 v18, s2 :: v_dual_mov_b32 v19, s3 +; GFX11-NEXT: v_writelane_b32 v34, s31, 1 +; GFX11-NEXT: v_writelane_b32 v35, s97, 1 +; GFX11-NEXT: v_dual_mov_b32 v20, s16 :: v_dual_mov_b32 v21, s17 +; GFX11-NEXT: v_dual_mov_b32 v22, s18 :: v_dual_mov_b32 v23, s19 +; GFX11-NEXT: v_writelane_b32 v34, s34, 2 +; GFX11-NEXT: v_writelane_b32 v35, s98, 2 +; GFX11-NEXT: v_dual_mov_b32 v24, s20 :: v_dual_mov_b32 v25, s21 +; GFX11-NEXT: v_dual_mov_b32 v26, s22 :: v_dual_mov_b32 v27, s23 +; GFX11-NEXT: v_writelane_b32 v34, s35, 3 +; GFX11-NEXT: v_writelane_b32 v35, s99, 3 +; GFX11-NEXT: v_dual_mov_b32 v28, s24 :: v_dual_mov_b32 v29, s25 +; GFX11-NEXT: v_dual_mov_b32 v30, s26 :: v_dual_mov_b32 v31, s27 +; GFX11-NEXT: v_writelane_b32 v34, s36, 4 +; GFX11-NEXT: v_writelane_b32 v35, s100, 4 +; GFX11-NEXT: v_dual_mov_b32 v32, s28 :: v_dual_mov_b32 v33, s29 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 -; GFX11-NEXT: v_readfirstlane_b32 s40, v1 -; GFX11-NEXT: v_readfirstlane_b32 s41, v2 -; GFX11-NEXT: v_writelane_b32 v16, s31, 1 -; GFX11-NEXT: v_writelane_b32 v17, s97, 1 -; GFX11-NEXT: v_readfirstlane_b32 s14, v3 -; GFX11-NEXT: v_readfirstlane_b32 s15, v4 -; GFX11-NEXT: v_readfirstlane_b32 s12, v5 -; GFX11-NEXT: v_writelane_b32 v16, s34, 2 -; GFX11-NEXT: v_writelane_b32 v17, s98, 2 -; GFX11-NEXT: v_readfirstlane_b32 s13, v6 -; GFX11-NEXT: v_readfirstlane_b32 s10, v7 -; GFX11-NEXT: v_readfirstlane_b32 s11, v8 -; GFX11-NEXT: v_writelane_b32 v16, s35, 3 -; GFX11-NEXT: v_writelane_b32 v17, s99, 3 -; GFX11-NEXT: v_readfirstlane_b32 s8, v9 -; GFX11-NEXT: v_readfirstlane_b32 s9, v10 -; GFX11-NEXT: v_readfirstlane_b32 s6, v11 -; GFX11-NEXT: v_writelane_b32 v16, s36, 4 -; GFX11-NEXT: v_writelane_b32 v17, s100, 4 -; GFX11-NEXT: v_readfirstlane_b32 s7, v12 -; GFX11-NEXT: v_readfirstlane_b32 s4, v13 -; GFX11-NEXT: v_readfirstlane_b32 s5, v14 -; GFX11-NEXT: v_writelane_b32 v16, s37, 5 -; GFX11-NEXT: v_writelane_b32 v17, s101, 5 +; GFX11-NEXT: v_writelane_b32 v34, s37, 5 +; GFX11-NEXT: v_writelane_b32 v35, s101, 5 +; GFX11-NEXT: v_readfirstlane_b32 s40, v16 +; GFX11-NEXT: v_readfirstlane_b32 s41, v17 +; GFX11-NEXT: v_readfirstlane_b32 s28, v18 +; GFX11-NEXT: v_writelane_b32 v34, s38, 6 +; GFX11-NEXT: v_writelane_b32 v35, s102, 6 +; GFX11-NEXT: v_readfirstlane_b32 s29, v19 +; GFX11-NEXT: v_readfirstlane_b32 s26, v20 +; GFX11-NEXT: v_readfirstlane_b32 s27, v21 +; GFX11-NEXT: v_writelane_b32 v34, s39, 7 +; GFX11-NEXT: v_writelane_b32 v35, s103, 7 +; GFX11-NEXT: v_readfirstlane_b32 s24, v22 +; GFX11-NEXT: v_readfirstlane_b32 s25, v23 +; GFX11-NEXT: v_readfirstlane_b32 s22, v24 +; GFX11-NEXT: v_writelane_b32 v34, s48, 8 +; GFX11-NEXT: v_readfirstlane_b32 s23, v25 +; GFX11-NEXT: v_readfirstlane_b32 s20, v26 +; GFX11-NEXT: v_readfirstlane_b32 s21, v27 +; GFX11-NEXT: v_readfirstlane_b32 s18, v28 +; GFX11-NEXT: v_writelane_b32 v34, s49, 9 +; GFX11-NEXT: v_readfirstlane_b32 s19, v29 +; GFX11-NEXT: v_readfirstlane_b32 s16, v30 +; GFX11-NEXT: v_readfirstlane_b32 s17, v31 +; GFX11-NEXT: v_readfirstlane_b32 s14, v32 +; GFX11-NEXT: v_writelane_b32 v34, s50, 10 +; GFX11-NEXT: v_readfirstlane_b32 s15, v33 +; GFX11-NEXT: v_readfirstlane_b32 s12, v1 +; GFX11-NEXT: v_readfirstlane_b32 s13, v2 +; GFX11-NEXT: v_readfirstlane_b32 s10, v3 +; GFX11-NEXT: v_writelane_b32 v34, s51, 11 +; GFX11-NEXT: v_readfirstlane_b32 s11, v4 +; GFX11-NEXT: v_readfirstlane_b32 s8, v5 +; GFX11-NEXT: v_readfirstlane_b32 s9, v6 +; GFX11-NEXT: v_readfirstlane_b32 s6, v7 +; GFX11-NEXT: v_writelane_b32 v34, s52, 12 +; GFX11-NEXT: v_readfirstlane_b32 s7, v8 +; GFX11-NEXT: v_readfirstlane_b32 s4, v9 +; GFX11-NEXT: v_readfirstlane_b32 s5, v10 +; GFX11-NEXT: v_readfirstlane_b32 s2, v11 +; GFX11-NEXT: v_writelane_b32 v34, s53, 13 +; GFX11-NEXT: v_readfirstlane_b32 s3, v12 +; GFX11-NEXT: v_readfirstlane_b32 s0, v13 +; GFX11-NEXT: v_readfirstlane_b32 s1, v14 ; GFX11-NEXT: s_mov_b32 s101, 0 +; GFX11-NEXT: v_writelane_b32 v34, s54, 14 ; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo -; GFX11-NEXT: ; implicit-def: $vgpr19 : SGPR spill to VGPR lane -; GFX11-NEXT: ; implicit-def: $vgpr18 : SGPR spill to VGPR lane -; GFX11-NEXT: v_writelane_b32 v16, s38, 6 -; GFX11-NEXT: v_writelane_b32 v17, s102, 6 -; GFX11-NEXT: v_writelane_b32 v16, s39, 7 -; GFX11-NEXT: v_writelane_b32 v17, s103, 7 -; GFX11-NEXT: v_writelane_b32 v16, s48, 8 -; GFX11-NEXT: v_writelane_b32 v17, s104, 8 -; GFX11-NEXT: v_writelane_b32 v16, s49, 9 -; GFX11-NEXT: v_writelane_b32 v16, s50, 10 -; GFX11-NEXT: v_writelane_b32 v16, s51, 11 -; GFX11-NEXT: v_writelane_b32 v16, s52, 12 -; GFX11-NEXT: v_writelane_b32 v16, s53, 13 -; GFX11-NEXT: v_writelane_b32 v16, s54, 14 -; GFX11-NEXT: v_writelane_b32 v16, s55, 15 -; GFX11-NEXT: v_writelane_b32 v16, s64, 16 -; GFX11-NEXT: v_writelane_b32 v16, s65, 17 -; GFX11-NEXT: v_writelane_b32 v16, s66, 18 -; GFX11-NEXT: v_writelane_b32 v16, s67, 19 -; GFX11-NEXT: v_writelane_b32 v16, s68, 20 -; GFX11-NEXT: v_writelane_b32 v16, s69, 21 -; GFX11-NEXT: v_writelane_b32 v16, s70, 22 -; GFX11-NEXT: v_writelane_b32 v16, s71, 23 -; GFX11-NEXT: v_writelane_b32 v16, s80, 24 -; GFX11-NEXT: v_writelane_b32 v16, s81, 25 -; GFX11-NEXT: v_writelane_b32 v16, s82, 26 -; GFX11-NEXT: v_writelane_b32 v16, s83, 27 -; GFX11-NEXT: v_writelane_b32 v16, s84, 28 -; GFX11-NEXT: v_writelane_b32 v16, s85, 29 -; GFX11-NEXT: v_writelane_b32 v16, s86, 30 -; GFX11-NEXT: v_writelane_b32 v16, s87, 31 +; GFX11-NEXT: v_writelane_b32 v35, s104, 8 +; GFX11-NEXT: ; implicit-def: $vgpr37 : SGPR spill to VGPR lane +; GFX11-NEXT: ; implicit-def: $vgpr36 : SGPR spill to VGPR lane +; GFX11-NEXT: v_writelane_b32 v34, s55, 15 +; GFX11-NEXT: v_writelane_b32 v34, s64, 16 +; GFX11-NEXT: v_writelane_b32 v34, s65, 17 +; GFX11-NEXT: v_writelane_b32 v34, s66, 18 +; GFX11-NEXT: v_writelane_b32 v34, s67, 19 +; GFX11-NEXT: v_writelane_b32 v34, s68, 20 +; GFX11-NEXT: v_writelane_b32 v34, s69, 21 +; GFX11-NEXT: v_writelane_b32 v34, s70, 22 +; GFX11-NEXT: v_writelane_b32 v34, s71, 23 +; GFX11-NEXT: v_writelane_b32 v34, s80, 24 +; GFX11-NEXT: v_writelane_b32 v34, s81, 25 +; GFX11-NEXT: v_writelane_b32 v34, s82, 26 +; GFX11-NEXT: v_writelane_b32 v34, s83, 27 +; GFX11-NEXT: v_writelane_b32 v34, s84, 28 +; GFX11-NEXT: v_writelane_b32 v34, s85, 29 +; GFX11-NEXT: v_writelane_b32 v34, s86, 30 +; GFX11-NEXT: v_writelane_b32 v34, s87, 31 ; GFX11-NEXT: s_cbranch_scc0 .LBB57_2 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: s_lshr_b32 s43, s25, 8 -; GFX11-NEXT: s_lshr_b64 s[62:63], s[4:5], 24 -; GFX11-NEXT: v_writelane_b32 v19, s43, 16 -; GFX11-NEXT: s_lshr_b32 s43, s24, 16 -; GFX11-NEXT: s_lshr_b32 s104, s5, 24 -; GFX11-NEXT: s_lshr_b32 s102, s5, 16 -; GFX11-NEXT: s_lshr_b32 s103, s5, 8 -; GFX11-NEXT: v_writelane_b32 v19, s43, 17 -; GFX11-NEXT: s_lshr_b32 s43, s24, 8 -; GFX11-NEXT: s_lshr_b32 s57, s4, 16 -; GFX11-NEXT: s_lshr_b32 s47, s4, 8 -; GFX11-NEXT: s_lshr_b32 s46, s7, 24 -; GFX11-NEXT: v_writelane_b32 v19, s43, 18 -; GFX11-NEXT: s_lshr_b32 s43, s23, 24 -; GFX11-NEXT: s_lshr_b32 vcc_hi, s7, 16 -; GFX11-NEXT: s_lshr_b32 s34, s7, 8 -; GFX11-NEXT: s_lshr_b32 s69, s6, 16 -; GFX11-NEXT: v_writelane_b32 v19, s43, 19 -; GFX11-NEXT: s_lshr_b32 s43, s23, 16 -; GFX11-NEXT: s_lshr_b32 s56, s6, 8 -; GFX11-NEXT: s_lshr_b32 s35, s9, 24 -; GFX11-NEXT: s_lshr_b32 s36, s9, 16 -; GFX11-NEXT: v_writelane_b32 v19, s43, 20 -; GFX11-NEXT: s_lshr_b32 s43, s23, 8 -; GFX11-NEXT: s_lshr_b32 s37, s9, 8 -; GFX11-NEXT: s_lshr_b32 s38, s8, 16 -; GFX11-NEXT: s_lshr_b32 s39, s8, 8 -; GFX11-NEXT: v_writelane_b32 v19, s43, 21 -; GFX11-NEXT: s_lshr_b32 s43, s22, 16 -; GFX11-NEXT: s_lshr_b32 s48, s11, 24 -; GFX11-NEXT: s_lshr_b32 s49, s11, 16 -; GFX11-NEXT: s_lshr_b32 s50, s11, 8 -; GFX11-NEXT: v_writelane_b32 v19, s43, 22 -; GFX11-NEXT: s_lshr_b32 s43, s22, 8 -; GFX11-NEXT: s_lshr_b32 s51, s10, 16 -; GFX11-NEXT: s_lshr_b32 s52, s10, 8 -; GFX11-NEXT: s_lshr_b32 s53, s13, 24 -; GFX11-NEXT: v_writelane_b32 v19, s43, 23 +; GFX11-NEXT: s_lshr_b32 s43, s19, 8 +; GFX11-NEXT: s_lshr_b64 s[62:63], s[0:1], 24 +; GFX11-NEXT: v_writelane_b32 v37, s43, 16 +; GFX11-NEXT: s_lshr_b32 s43, s18, 16 +; GFX11-NEXT: s_lshr_b32 s104, s1, 24 +; GFX11-NEXT: s_lshr_b32 s102, s1, 16 +; GFX11-NEXT: s_lshr_b32 s103, s1, 8 +; GFX11-NEXT: v_writelane_b32 v37, s43, 17 +; GFX11-NEXT: s_lshr_b32 s43, s18, 8 +; GFX11-NEXT: s_lshr_b32 s57, s0, 16 +; GFX11-NEXT: s_lshr_b32 s47, s0, 8 +; GFX11-NEXT: s_lshr_b32 s46, s3, 24 +; GFX11-NEXT: v_writelane_b32 v37, s43, 18 ; GFX11-NEXT: s_lshr_b32 s43, s21, 24 -; GFX11-NEXT: s_lshr_b32 s54, s13, 16 -; GFX11-NEXT: s_lshr_b32 s55, s13, 8 -; GFX11-NEXT: s_lshr_b32 s64, s12, 16 -; GFX11-NEXT: v_writelane_b32 v19, s43, 24 +; GFX11-NEXT: s_lshr_b32 vcc_hi, s3, 16 +; GFX11-NEXT: s_lshr_b32 s34, s3, 8 +; GFX11-NEXT: s_lshr_b32 s69, s2, 16 +; GFX11-NEXT: v_writelane_b32 v37, s43, 19 ; GFX11-NEXT: s_lshr_b32 s43, s21, 16 -; GFX11-NEXT: s_lshr_b32 s65, s12, 8 -; GFX11-NEXT: s_lshr_b32 s66, s15, 24 -; GFX11-NEXT: s_lshr_b32 s67, s15, 16 -; GFX11-NEXT: v_writelane_b32 v19, s43, 25 +; GFX11-NEXT: s_lshr_b32 s56, s2, 8 +; GFX11-NEXT: s_lshr_b32 s35, s5, 24 +; GFX11-NEXT: s_lshr_b32 s36, s5, 16 +; GFX11-NEXT: v_writelane_b32 v37, s43, 20 ; GFX11-NEXT: s_lshr_b32 s43, s21, 8 -; GFX11-NEXT: s_lshr_b32 s68, s15, 8 -; GFX11-NEXT: s_lshr_b32 s59, s14, 16 -; GFX11-NEXT: s_lshr_b32 s58, s14, 8 -; GFX11-NEXT: v_writelane_b32 v19, s43, 26 +; GFX11-NEXT: s_lshr_b32 s37, s5, 8 +; GFX11-NEXT: s_lshr_b32 s38, s4, 16 +; GFX11-NEXT: s_lshr_b32 s39, s4, 8 +; GFX11-NEXT: v_writelane_b32 v37, s43, 21 ; GFX11-NEXT: s_lshr_b32 s43, s20, 16 -; GFX11-NEXT: s_lshr_b32 s70, s41, 24 -; GFX11-NEXT: s_lshr_b32 s71, s41, 16 -; GFX11-NEXT: s_lshr_b32 s60, s41, 8 -; GFX11-NEXT: v_writelane_b32 v19, s43, 27 +; GFX11-NEXT: s_lshr_b32 s48, s7, 24 +; GFX11-NEXT: s_lshr_b32 s49, s7, 16 +; GFX11-NEXT: s_lshr_b32 s50, s7, 8 +; GFX11-NEXT: v_writelane_b32 v37, s43, 22 ; GFX11-NEXT: s_lshr_b32 s43, s20, 8 -; GFX11-NEXT: s_lshr_b32 s80, s40, 16 -; GFX11-NEXT: s_lshr_b32 s61, s40, 8 -; GFX11-NEXT: s_lshr_b32 s81, s29, 24 -; GFX11-NEXT: v_writelane_b32 v19, s43, 28 -; GFX11-NEXT: s_lshr_b32 s43, s19, 24 -; GFX11-NEXT: s_lshr_b32 s82, s29, 16 -; GFX11-NEXT: s_lshr_b32 s83, s29, 8 -; GFX11-NEXT: s_lshr_b32 s84, s28, 16 -; GFX11-NEXT: v_writelane_b32 v19, s43, 29 -; GFX11-NEXT: s_lshr_b32 s43, s19, 16 -; GFX11-NEXT: s_lshr_b32 s85, s28, 8 -; GFX11-NEXT: s_lshr_b32 s86, s27, 24 -; GFX11-NEXT: s_lshr_b32 s72, s27, 16 -; GFX11-NEXT: v_writelane_b32 v19, s43, 30 -; GFX11-NEXT: s_lshr_b32 s43, s19, 8 -; GFX11-NEXT: s_lshr_b32 s87, s27, 8 -; GFX11-NEXT: s_lshr_b32 s73, s26, 16 -; GFX11-NEXT: s_lshr_b32 s96, s26, 8 -; GFX11-NEXT: v_writelane_b32 v19, s43, 31 -; GFX11-NEXT: s_lshr_b32 s43, s18, 16 -; GFX11-NEXT: s_lshr_b32 s97, s25, 24 -; GFX11-NEXT: v_writelane_b32 v18, s43, 0 -; GFX11-NEXT: s_lshr_b32 s43, s18, 8 -; GFX11-NEXT: v_writelane_b32 v19, s62, 14 -; GFX11-NEXT: s_lshr_b32 s42, s25, 16 -; GFX11-NEXT: s_lshr_b32 s74, s2, 16 -; GFX11-NEXT: v_writelane_b32 v18, s43, 1 -; GFX11-NEXT: s_lshr_b32 s43, s17, 24 -; GFX11-NEXT: v_writelane_b32 v19, s63, 15 +; GFX11-NEXT: s_lshr_b32 s51, s6, 16 +; GFX11-NEXT: s_lshr_b32 s52, s6, 8 +; GFX11-NEXT: s_lshr_b32 s53, s9, 24 +; GFX11-NEXT: v_writelane_b32 v37, s43, 23 +; GFX11-NEXT: s_lshr_b32 s43, s23, 24 +; GFX11-NEXT: s_lshr_b32 s54, s9, 16 +; GFX11-NEXT: s_lshr_b32 s55, s9, 8 +; GFX11-NEXT: s_lshr_b32 s64, s8, 16 +; GFX11-NEXT: v_writelane_b32 v37, s43, 24 +; GFX11-NEXT: s_lshr_b32 s43, s23, 16 +; GFX11-NEXT: s_lshr_b32 s65, s8, 8 +; GFX11-NEXT: s_lshr_b32 s66, s11, 24 +; GFX11-NEXT: s_lshr_b32 s67, s11, 16 +; GFX11-NEXT: v_writelane_b32 v37, s43, 25 +; GFX11-NEXT: s_lshr_b32 s43, s23, 8 +; GFX11-NEXT: s_lshr_b32 s68, s11, 8 +; GFX11-NEXT: s_lshr_b32 s59, s10, 16 +; GFX11-NEXT: s_lshr_b32 s58, s10, 8 +; GFX11-NEXT: v_writelane_b32 v37, s43, 26 +; GFX11-NEXT: s_lshr_b32 s43, s22, 16 +; GFX11-NEXT: s_lshr_b32 s70, s13, 24 +; GFX11-NEXT: s_lshr_b32 s71, s13, 16 +; GFX11-NEXT: s_lshr_b32 s60, s13, 8 +; GFX11-NEXT: v_writelane_b32 v37, s43, 27 +; GFX11-NEXT: s_lshr_b32 s43, s22, 8 +; GFX11-NEXT: s_lshr_b32 s80, s12, 16 +; GFX11-NEXT: s_lshr_b32 s61, s12, 8 +; GFX11-NEXT: s_lshr_b32 s81, s15, 24 +; GFX11-NEXT: v_writelane_b32 v37, s43, 28 +; GFX11-NEXT: s_lshr_b32 s43, s25, 24 +; GFX11-NEXT: s_lshr_b32 s82, s15, 16 +; GFX11-NEXT: s_lshr_b32 s83, s15, 8 +; GFX11-NEXT: s_lshr_b32 s84, s14, 16 +; GFX11-NEXT: v_writelane_b32 v37, s43, 29 +; GFX11-NEXT: s_lshr_b32 s43, s25, 16 +; GFX11-NEXT: s_lshr_b32 s85, s14, 8 +; GFX11-NEXT: s_lshr_b32 s86, s17, 24 +; GFX11-NEXT: s_lshr_b32 s72, s17, 16 +; GFX11-NEXT: v_writelane_b32 v37, s43, 30 +; GFX11-NEXT: s_lshr_b32 s43, s25, 8 +; GFX11-NEXT: s_lshr_b32 s87, s17, 8 +; GFX11-NEXT: s_lshr_b32 s73, s16, 16 +; GFX11-NEXT: s_lshr_b32 s96, s16, 8 +; GFX11-NEXT: v_writelane_b32 v37, s43, 31 +; GFX11-NEXT: s_lshr_b32 s43, s24, 16 +; GFX11-NEXT: s_lshr_b32 s97, s19, 24 +; GFX11-NEXT: v_writelane_b32 v36, s43, 0 +; GFX11-NEXT: s_lshr_b32 s43, s24, 8 +; GFX11-NEXT: v_writelane_b32 v37, s62, 14 +; GFX11-NEXT: s_lshr_b32 s42, s19, 16 +; GFX11-NEXT: s_lshr_b32 s74, s28, 16 +; GFX11-NEXT: v_writelane_b32 v36, s43, 1 +; GFX11-NEXT: s_lshr_b32 s43, s27, 24 +; GFX11-NEXT: v_writelane_b32 v37, s63, 15 +; GFX11-NEXT: s_lshr_b64 s[62:63], s[2:3], 24 +; GFX11-NEXT: s_lshr_b32 s98, s41, 24 +; GFX11-NEXT: v_writelane_b32 v36, s43, 2 +; GFX11-NEXT: s_lshr_b32 s43, s27, 16 +; GFX11-NEXT: v_writelane_b32 v37, s62, 12 +; GFX11-NEXT: s_lshr_b32 s99, s41, 16 +; GFX11-NEXT: s_lshr_b32 s100, s41, 8 +; GFX11-NEXT: v_writelane_b32 v36, s43, 3 +; GFX11-NEXT: s_lshr_b32 s43, s27, 8 +; GFX11-NEXT: v_writelane_b32 v37, s63, 13 +; GFX11-NEXT: s_lshr_b64 s[62:63], s[4:5], 24 +; GFX11-NEXT: s_lshr_b32 s44, s40, 16 +; GFX11-NEXT: v_writelane_b32 v36, s43, 4 +; GFX11-NEXT: s_lshr_b32 s43, s26, 16 +; GFX11-NEXT: v_writelane_b32 v37, s62, 10 +; GFX11-NEXT: s_lshr_b32 s45, s40, 8 +; GFX11-NEXT: s_lshr_b64 s[76:77], s[16:17], 24 +; GFX11-NEXT: v_writelane_b32 v36, s43, 5 +; GFX11-NEXT: s_lshr_b32 s43, s26, 8 +; GFX11-NEXT: v_writelane_b32 v37, s63, 11 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[6:7], 24 -; GFX11-NEXT: s_lshr_b32 s98, s1, 24 -; GFX11-NEXT: v_writelane_b32 v18, s43, 2 -; GFX11-NEXT: s_lshr_b32 s43, s17, 16 -; GFX11-NEXT: v_writelane_b32 v19, s62, 12 -; GFX11-NEXT: s_lshr_b32 s99, s1, 16 -; GFX11-NEXT: s_lshr_b32 s100, s1, 8 -; GFX11-NEXT: v_writelane_b32 v18, s43, 3 -; GFX11-NEXT: s_lshr_b32 s43, s17, 8 -; GFX11-NEXT: v_writelane_b32 v19, s63, 13 +; GFX11-NEXT: s_lshr_b64 s[88:89], s[18:19], 24 +; GFX11-NEXT: v_writelane_b32 v36, s43, 6 +; GFX11-NEXT: s_lshr_b32 s43, s29, 24 +; GFX11-NEXT: v_writelane_b32 v37, s62, 8 +; GFX11-NEXT: s_lshr_b64 s[78:79], s[22:23], 24 +; GFX11-NEXT: s_lshr_b64 s[90:91], s[24:25], 24 +; GFX11-NEXT: v_writelane_b32 v36, s43, 7 +; GFX11-NEXT: s_lshr_b32 s43, s29, 16 +; GFX11-NEXT: v_writelane_b32 v37, s63, 9 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[8:9], 24 -; GFX11-NEXT: s_lshr_b32 s44, s0, 16 -; GFX11-NEXT: v_writelane_b32 v18, s43, 4 -; GFX11-NEXT: s_lshr_b32 s43, s16, 16 -; GFX11-NEXT: v_writelane_b32 v19, s62, 10 -; GFX11-NEXT: s_lshr_b32 s45, s0, 8 -; GFX11-NEXT: s_lshr_b64 s[76:77], s[26:27], 24 -; GFX11-NEXT: v_writelane_b32 v18, s43, 5 -; GFX11-NEXT: s_lshr_b32 s43, s16, 8 -; GFX11-NEXT: v_writelane_b32 v19, s63, 11 +; GFX11-NEXT: s_lshr_b64 s[92:93], s[26:27], 24 +; GFX11-NEXT: v_writelane_b32 v36, s43, 8 +; GFX11-NEXT: s_lshr_b32 s43, s29, 8 +; GFX11-NEXT: v_writelane_b32 v37, s62, 6 +; GFX11-NEXT: s_lshr_b64 s[94:95], s[28:29], 24 +; GFX11-NEXT: s_lshr_b64 s[30:31], s[40:41], 24 +; GFX11-NEXT: v_writelane_b32 v36, s43, 9 +; GFX11-NEXT: s_lshr_b32 s43, s28, 8 +; GFX11-NEXT: v_writelane_b32 v37, s63, 7 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[10:11], 24 -; GFX11-NEXT: s_lshr_b64 s[88:89], s[24:25], 24 -; GFX11-NEXT: v_writelane_b32 v18, s43, 6 -; GFX11-NEXT: s_lshr_b32 s43, s3, 24 -; GFX11-NEXT: v_writelane_b32 v19, s62, 8 -; GFX11-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 -; GFX11-NEXT: s_lshr_b64 s[90:91], s[18:19], 24 -; GFX11-NEXT: v_writelane_b32 v18, s43, 7 -; GFX11-NEXT: s_lshr_b32 s43, s3, 16 -; GFX11-NEXT: v_writelane_b32 v19, s63, 9 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_writelane_b32 v37, s62, 4 +; GFX11-NEXT: v_writelane_b32 v37, s63, 5 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 -; GFX11-NEXT: s_lshr_b64 s[92:93], s[16:17], 24 -; GFX11-NEXT: v_writelane_b32 v18, s43, 8 -; GFX11-NEXT: s_lshr_b32 s43, s3, 8 -; GFX11-NEXT: v_writelane_b32 v19, s62, 6 -; GFX11-NEXT: s_lshr_b64 s[94:95], s[2:3], 24 -; GFX11-NEXT: s_lshr_b64 s[30:31], s[0:1], 24 -; GFX11-NEXT: v_writelane_b32 v18, s43, 9 -; GFX11-NEXT: s_lshr_b32 s43, s2, 8 -; GFX11-NEXT: v_writelane_b32 v19, s63, 7 +; GFX11-NEXT: v_writelane_b32 v37, s62, 2 +; GFX11-NEXT: v_writelane_b32 v37, s63, 3 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[14:15], 24 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_writelane_b32 v19, s62, 4 -; GFX11-NEXT: v_writelane_b32 v19, s63, 5 -; GFX11-NEXT: s_lshr_b64 s[62:63], s[40:41], 24 -; GFX11-NEXT: v_writelane_b32 v19, s62, 2 -; GFX11-NEXT: v_writelane_b32 v19, s63, 3 -; GFX11-NEXT: s_lshr_b64 s[62:63], s[28:29], 24 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_writelane_b32 v19, s62, 0 -; GFX11-NEXT: v_writelane_b32 v19, s63, 1 -; GFX11-NEXT: s_lshr_b64 s[62:63], s[22:23], 24 +; GFX11-NEXT: v_writelane_b32 v37, s62, 0 +; GFX11-NEXT: v_writelane_b32 v37, s63, 1 +; GFX11-NEXT: s_lshr_b64 s[62:63], s[20:21], 24 ; GFX11-NEXT: s_branch .LBB57_3 ; GFX11-NEXT: .LBB57_2: ; GFX11-NEXT: ; implicit-def: $vcc_hi @@ -84794,7 +83866,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: s_mov_b32 s101, -1 -; GFX11-NEXT: v_writelane_b32 v19, vcc_lo, 0 +; GFX11-NEXT: v_writelane_b32 v37, vcc_lo, 0 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr42 @@ -84804,7 +83876,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr42 -; GFX11-NEXT: v_writelane_b32 v19, vcc_hi, 1 +; GFX11-NEXT: v_writelane_b32 v37, vcc_hi, 1 ; GFX11-NEXT: ; implicit-def: $vcc_lo ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr42 @@ -84816,7 +83888,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr42 -; GFX11-NEXT: v_writelane_b32 v19, vcc_lo, 2 +; GFX11-NEXT: v_writelane_b32 v37, vcc_lo, 2 ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; kill: killed $sgpr42 @@ -84827,7 +83899,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr42 -; GFX11-NEXT: v_writelane_b32 v19, vcc_hi, 3 +; GFX11-NEXT: v_writelane_b32 v37, vcc_hi, 3 ; GFX11-NEXT: ; implicit-def: $vcc_lo ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr42 @@ -84839,7 +83911,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr42 -; GFX11-NEXT: v_writelane_b32 v19, vcc_lo, 4 +; GFX11-NEXT: v_writelane_b32 v37, vcc_lo, 4 ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; kill: killed $sgpr42 @@ -84850,7 +83922,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX11-NEXT: ; implicit-def: $sgpr42 ; GFX11-NEXT: ; kill: killed $sgpr42 ; GFX11-NEXT: ; implicit-def: $sgpr42 -; GFX11-NEXT: v_writelane_b32 v19, vcc_hi, 5 +; GFX11-NEXT: v_writelane_b32 v37, vcc_hi, 5 ; GFX11-NEXT: ; implicit-def: $vcc_lo ; GFX11-NEXT: ; implicit-def: $sgpr45 ; GFX11-NEXT: ; implicit-def: $sgpr44 @@ -84914,20 +83986,20 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX11-NEXT: ; implicit-def: $sgpr104 ; GFX11-NEXT: ; implicit-def: $sgpr88 ; GFX11-NEXT: ; implicit-def: $sgpr76 -; GFX11-NEXT: v_writelane_b32 v19, vcc_lo, 6 -; GFX11-NEXT: v_writelane_b32 v19, vcc_hi, 7 +; GFX11-NEXT: v_writelane_b32 v37, vcc_lo, 6 +; GFX11-NEXT: v_writelane_b32 v37, vcc_hi, 7 ; GFX11-NEXT: ; implicit-def: $vcc_lo -; GFX11-NEXT: v_writelane_b32 v19, vcc_lo, 8 -; GFX11-NEXT: v_writelane_b32 v19, vcc_hi, 9 +; GFX11-NEXT: v_writelane_b32 v37, vcc_lo, 8 +; GFX11-NEXT: v_writelane_b32 v37, vcc_hi, 9 ; GFX11-NEXT: ; implicit-def: $vcc_lo -; GFX11-NEXT: v_writelane_b32 v19, vcc_lo, 10 -; GFX11-NEXT: v_writelane_b32 v19, vcc_hi, 11 +; GFX11-NEXT: v_writelane_b32 v37, vcc_lo, 10 +; GFX11-NEXT: v_writelane_b32 v37, vcc_hi, 11 ; GFX11-NEXT: ; implicit-def: $vcc_lo -; GFX11-NEXT: v_writelane_b32 v19, vcc_lo, 12 -; GFX11-NEXT: v_writelane_b32 v19, vcc_hi, 13 +; GFX11-NEXT: v_writelane_b32 v37, vcc_lo, 12 +; GFX11-NEXT: v_writelane_b32 v37, vcc_hi, 13 ; GFX11-NEXT: ; implicit-def: $vcc_lo -; GFX11-NEXT: v_writelane_b32 v19, vcc_lo, 14 -; GFX11-NEXT: v_writelane_b32 v19, vcc_hi, 15 +; GFX11-NEXT: v_writelane_b32 v37, vcc_lo, 14 +; GFX11-NEXT: v_writelane_b32 v37, vcc_hi, 15 ; GFX11-NEXT: .LBB57_3: ; %Flow ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s101 ; GFX11-NEXT: s_mov_b32 s101, s104 @@ -84936,26 +84008,22 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX11-NEXT: s_mov_b32 s69, s42 ; GFX11-NEXT: s_cbranch_vccnz .LBB57_5 ; GFX11-NEXT: ; %bb.4: ; %cmp.true -; GFX11-NEXT: s_add_u32 s0, s0, 3 -; GFX11-NEXT: s_addc_u32 s1, s1, 0 -; GFX11-NEXT: s_add_u32 s2, s2, 3 -; GFX11-NEXT: s_addc_u32 s3, s3, 0 -; GFX11-NEXT: s_add_u32 s16, s16, 3 -; GFX11-NEXT: s_addc_u32 s17, s17, 0 -; GFX11-NEXT: s_add_u32 s18, s18, 3 -; GFX11-NEXT: s_addc_u32 s19, s19, 0 -; GFX11-NEXT: s_add_u32 s20, s20, 3 -; GFX11-NEXT: s_addc_u32 s21, s21, 0 -; GFX11-NEXT: s_add_u32 s22, s22, 3 -; GFX11-NEXT: s_addc_u32 s23, s23, 0 -; GFX11-NEXT: s_add_u32 s24, s24, 3 -; GFX11-NEXT: s_addc_u32 s25, s25, 0 -; GFX11-NEXT: s_add_u32 s26, s26, 3 -; GFX11-NEXT: s_addc_u32 s27, s27, 0 -; GFX11-NEXT: s_add_u32 s28, s28, 3 -; GFX11-NEXT: s_addc_u32 s29, s29, 0 ; GFX11-NEXT: s_add_u32 s40, s40, 3 ; GFX11-NEXT: s_addc_u32 s41, s41, 0 +; GFX11-NEXT: s_add_u32 s28, s28, 3 +; GFX11-NEXT: s_addc_u32 s29, s29, 0 +; GFX11-NEXT: s_add_u32 s26, s26, 3 +; GFX11-NEXT: s_addc_u32 s27, s27, 0 +; GFX11-NEXT: s_add_u32 s24, s24, 3 +; GFX11-NEXT: s_addc_u32 s25, s25, 0 +; GFX11-NEXT: s_add_u32 s22, s22, 3 +; GFX11-NEXT: s_addc_u32 s23, s23, 0 +; GFX11-NEXT: s_add_u32 s20, s20, 3 +; GFX11-NEXT: s_addc_u32 s21, s21, 0 +; GFX11-NEXT: s_add_u32 s18, s18, 3 +; GFX11-NEXT: s_addc_u32 s19, s19, 0 +; GFX11-NEXT: s_add_u32 s16, s16, 3 +; GFX11-NEXT: s_addc_u32 s17, s17, 0 ; GFX11-NEXT: s_add_u32 s14, s14, 3 ; GFX11-NEXT: s_addc_u32 s15, s15, 0 ; GFX11-NEXT: s_add_u32 s12, s12, 3 @@ -84968,557 +84036,562 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3 ; GFX11-NEXT: s_addc_u32 s7, s7, 0 ; GFX11-NEXT: s_add_u32 s4, s4, 3 ; GFX11-NEXT: s_addc_u32 s5, s5, 0 -; GFX11-NEXT: s_lshr_b32 s42, s25, 8 -; GFX11-NEXT: s_lshr_b64 s[62:63], s[4:5], 24 -; GFX11-NEXT: v_writelane_b32 v19, s42, 16 -; GFX11-NEXT: s_lshr_b32 s42, s24, 16 -; GFX11-NEXT: s_lshr_b32 s101, s5, 24 -; GFX11-NEXT: s_lshr_b32 s102, s5, 16 -; GFX11-NEXT: s_lshr_b32 s103, s5, 8 -; GFX11-NEXT: v_writelane_b32 v19, s42, 17 -; GFX11-NEXT: s_lshr_b32 s42, s24, 8 -; GFX11-NEXT: s_lshr_b32 s104, s4, 16 -; GFX11-NEXT: s_lshr_b32 s47, s4, 8 -; GFX11-NEXT: s_lshr_b32 s46, s7, 24 -; GFX11-NEXT: v_writelane_b32 v19, s42, 18 -; GFX11-NEXT: s_lshr_b32 s42, s23, 24 -; GFX11-NEXT: s_lshr_b32 vcc_hi, s7, 16 -; GFX11-NEXT: s_lshr_b32 s34, s7, 8 -; GFX11-NEXT: s_lshr_b32 s57, s6, 16 -; GFX11-NEXT: v_writelane_b32 v19, s42, 19 -; GFX11-NEXT: s_lshr_b32 s42, s23, 16 -; GFX11-NEXT: s_lshr_b32 s56, s6, 8 -; GFX11-NEXT: s_lshr_b32 s35, s9, 24 -; GFX11-NEXT: s_lshr_b32 s36, s9, 16 -; GFX11-NEXT: v_writelane_b32 v19, s42, 20 -; GFX11-NEXT: s_lshr_b32 s42, s23, 8 -; GFX11-NEXT: s_lshr_b32 s37, s9, 8 -; GFX11-NEXT: s_lshr_b32 s38, s8, 16 -; GFX11-NEXT: s_lshr_b32 s39, s8, 8 -; GFX11-NEXT: v_writelane_b32 v19, s42, 21 -; GFX11-NEXT: s_lshr_b32 s42, s22, 16 -; GFX11-NEXT: s_lshr_b32 s48, s11, 24 -; GFX11-NEXT: s_lshr_b32 s49, s11, 16 -; GFX11-NEXT: s_lshr_b32 s50, s11, 8 -; GFX11-NEXT: v_writelane_b32 v19, s42, 22 -; GFX11-NEXT: s_lshr_b32 s42, s22, 8 -; GFX11-NEXT: s_lshr_b32 s51, s10, 16 -; GFX11-NEXT: s_lshr_b32 s52, s10, 8 -; GFX11-NEXT: s_lshr_b32 s53, s13, 24 -; GFX11-NEXT: v_writelane_b32 v19, s42, 23 +; GFX11-NEXT: s_add_u32 s2, s2, 3 +; GFX11-NEXT: s_addc_u32 s3, s3, 0 +; GFX11-NEXT: s_add_u32 s0, s0, 3 +; GFX11-NEXT: s_addc_u32 s1, s1, 0 +; GFX11-NEXT: s_lshr_b32 s42, s19, 8 +; GFX11-NEXT: s_lshr_b64 s[62:63], s[0:1], 24 +; GFX11-NEXT: v_writelane_b32 v37, s42, 16 +; GFX11-NEXT: s_lshr_b32 s42, s18, 16 +; GFX11-NEXT: s_lshr_b32 s101, s1, 24 +; GFX11-NEXT: s_lshr_b32 s102, s1, 16 +; GFX11-NEXT: s_lshr_b32 s103, s1, 8 +; GFX11-NEXT: v_writelane_b32 v37, s42, 17 +; GFX11-NEXT: s_lshr_b32 s42, s18, 8 +; GFX11-NEXT: s_lshr_b32 s104, s0, 16 +; GFX11-NEXT: s_lshr_b32 s47, s0, 8 +; GFX11-NEXT: s_lshr_b32 s46, s3, 24 +; GFX11-NEXT: v_writelane_b32 v37, s42, 18 ; GFX11-NEXT: s_lshr_b32 s42, s21, 24 -; GFX11-NEXT: s_lshr_b32 s54, s13, 16 -; GFX11-NEXT: s_lshr_b32 s55, s13, 8 -; GFX11-NEXT: s_lshr_b32 s64, s12, 16 -; GFX11-NEXT: v_writelane_b32 v19, s42, 24 +; GFX11-NEXT: s_lshr_b32 vcc_hi, s3, 16 +; GFX11-NEXT: s_lshr_b32 s34, s3, 8 +; GFX11-NEXT: s_lshr_b32 s57, s2, 16 +; GFX11-NEXT: v_writelane_b32 v37, s42, 19 ; GFX11-NEXT: s_lshr_b32 s42, s21, 16 -; GFX11-NEXT: s_lshr_b32 s65, s12, 8 -; GFX11-NEXT: s_lshr_b32 s66, s15, 24 -; GFX11-NEXT: s_lshr_b32 s67, s15, 16 -; GFX11-NEXT: v_writelane_b32 v19, s42, 25 +; GFX11-NEXT: s_lshr_b32 s56, s2, 8 +; GFX11-NEXT: s_lshr_b32 s35, s5, 24 +; GFX11-NEXT: s_lshr_b32 s36, s5, 16 +; GFX11-NEXT: v_writelane_b32 v37, s42, 20 ; GFX11-NEXT: s_lshr_b32 s42, s21, 8 -; GFX11-NEXT: s_lshr_b32 s68, s15, 8 -; GFX11-NEXT: s_lshr_b32 s59, s14, 16 -; GFX11-NEXT: s_lshr_b32 s58, s14, 8 -; GFX11-NEXT: v_writelane_b32 v19, s42, 26 +; GFX11-NEXT: s_lshr_b32 s37, s5, 8 +; GFX11-NEXT: s_lshr_b32 s38, s4, 16 +; GFX11-NEXT: s_lshr_b32 s39, s4, 8 +; GFX11-NEXT: v_writelane_b32 v37, s42, 21 ; GFX11-NEXT: s_lshr_b32 s42, s20, 16 -; GFX11-NEXT: s_lshr_b32 s70, s41, 24 -; GFX11-NEXT: s_lshr_b32 s71, s41, 16 -; GFX11-NEXT: s_lshr_b32 s60, s41, 8 -; GFX11-NEXT: v_writelane_b32 v19, s42, 27 +; GFX11-NEXT: s_lshr_b32 s48, s7, 24 +; GFX11-NEXT: s_lshr_b32 s49, s7, 16 +; GFX11-NEXT: s_lshr_b32 s50, s7, 8 +; GFX11-NEXT: v_writelane_b32 v37, s42, 22 ; GFX11-NEXT: s_lshr_b32 s42, s20, 8 -; GFX11-NEXT: s_lshr_b32 s80, s40, 16 -; GFX11-NEXT: s_lshr_b32 s61, s40, 8 -; GFX11-NEXT: s_lshr_b32 s81, s29, 24 -; GFX11-NEXT: v_writelane_b32 v19, s42, 28 -; GFX11-NEXT: s_lshr_b32 s42, s19, 24 -; GFX11-NEXT: s_lshr_b32 s82, s29, 16 -; GFX11-NEXT: s_lshr_b32 s83, s29, 8 -; GFX11-NEXT: s_lshr_b32 s84, s28, 16 -; GFX11-NEXT: v_writelane_b32 v19, s42, 29 -; GFX11-NEXT: s_lshr_b32 s42, s19, 16 -; GFX11-NEXT: s_lshr_b32 s85, s28, 8 -; GFX11-NEXT: s_lshr_b32 s86, s27, 24 -; GFX11-NEXT: s_lshr_b32 s72, s27, 16 -; GFX11-NEXT: v_writelane_b32 v19, s42, 30 -; GFX11-NEXT: s_lshr_b32 s42, s19, 8 -; GFX11-NEXT: s_lshr_b32 s87, s27, 8 -; GFX11-NEXT: s_lshr_b32 s73, s26, 16 -; GFX11-NEXT: s_lshr_b32 s96, s26, 8 -; GFX11-NEXT: v_writelane_b32 v19, s42, 31 -; GFX11-NEXT: s_lshr_b32 s42, s18, 16 -; GFX11-NEXT: s_lshr_b32 s97, s25, 24 -; GFX11-NEXT: v_writelane_b32 v18, s42, 0 -; GFX11-NEXT: s_lshr_b32 s42, s18, 8 -; GFX11-NEXT: v_writelane_b32 v19, s62, 14 -; GFX11-NEXT: s_lshr_b32 s69, s25, 16 -; GFX11-NEXT: s_lshr_b32 s74, s2, 16 -; GFX11-NEXT: v_writelane_b32 v18, s42, 1 -; GFX11-NEXT: s_lshr_b32 s42, s17, 24 -; GFX11-NEXT: v_writelane_b32 v19, s63, 15 +; GFX11-NEXT: s_lshr_b32 s51, s6, 16 +; GFX11-NEXT: s_lshr_b32 s52, s6, 8 +; GFX11-NEXT: s_lshr_b32 s53, s9, 24 +; GFX11-NEXT: v_writelane_b32 v37, s42, 23 +; GFX11-NEXT: s_lshr_b32 s42, s23, 24 +; GFX11-NEXT: s_lshr_b32 s54, s9, 16 +; GFX11-NEXT: s_lshr_b32 s55, s9, 8 +; GFX11-NEXT: s_lshr_b32 s64, s8, 16 +; GFX11-NEXT: v_writelane_b32 v37, s42, 24 +; GFX11-NEXT: s_lshr_b32 s42, s23, 16 +; GFX11-NEXT: s_lshr_b32 s65, s8, 8 +; GFX11-NEXT: s_lshr_b32 s66, s11, 24 +; GFX11-NEXT: s_lshr_b32 s67, s11, 16 +; GFX11-NEXT: v_writelane_b32 v37, s42, 25 +; GFX11-NEXT: s_lshr_b32 s42, s23, 8 +; GFX11-NEXT: s_lshr_b32 s68, s11, 8 +; GFX11-NEXT: s_lshr_b32 s59, s10, 16 +; GFX11-NEXT: s_lshr_b32 s58, s10, 8 +; GFX11-NEXT: v_writelane_b32 v37, s42, 26 +; GFX11-NEXT: s_lshr_b32 s42, s22, 16 +; GFX11-NEXT: s_lshr_b32 s70, s13, 24 +; GFX11-NEXT: s_lshr_b32 s71, s13, 16 +; GFX11-NEXT: s_lshr_b32 s60, s13, 8 +; GFX11-NEXT: v_writelane_b32 v37, s42, 27 +; GFX11-NEXT: s_lshr_b32 s42, s22, 8 +; GFX11-NEXT: s_lshr_b32 s80, s12, 16 +; GFX11-NEXT: s_lshr_b32 s61, s12, 8 +; GFX11-NEXT: s_lshr_b32 s81, s15, 24 +; GFX11-NEXT: v_writelane_b32 v37, s42, 28 +; GFX11-NEXT: s_lshr_b32 s42, s25, 24 +; GFX11-NEXT: s_lshr_b32 s82, s15, 16 +; GFX11-NEXT: s_lshr_b32 s83, s15, 8 +; GFX11-NEXT: s_lshr_b32 s84, s14, 16 +; GFX11-NEXT: v_writelane_b32 v37, s42, 29 +; GFX11-NEXT: s_lshr_b32 s42, s25, 16 +; GFX11-NEXT: s_lshr_b32 s85, s14, 8 +; GFX11-NEXT: s_lshr_b32 s86, s17, 24 +; GFX11-NEXT: s_lshr_b32 s72, s17, 16 +; GFX11-NEXT: v_writelane_b32 v37, s42, 30 +; GFX11-NEXT: s_lshr_b32 s42, s25, 8 +; GFX11-NEXT: s_lshr_b32 s87, s17, 8 +; GFX11-NEXT: s_lshr_b32 s73, s16, 16 +; GFX11-NEXT: s_lshr_b32 s96, s16, 8 +; GFX11-NEXT: v_writelane_b32 v37, s42, 31 +; GFX11-NEXT: s_lshr_b32 s42, s24, 16 +; GFX11-NEXT: s_lshr_b32 s97, s19, 24 +; GFX11-NEXT: v_writelane_b32 v36, s42, 0 +; GFX11-NEXT: s_lshr_b32 s42, s24, 8 +; GFX11-NEXT: v_writelane_b32 v37, s62, 14 +; GFX11-NEXT: s_lshr_b32 s69, s19, 16 +; GFX11-NEXT: s_lshr_b32 s74, s28, 16 +; GFX11-NEXT: v_writelane_b32 v36, s42, 1 +; GFX11-NEXT: s_lshr_b32 s42, s27, 24 +; GFX11-NEXT: v_writelane_b32 v37, s63, 15 +; GFX11-NEXT: s_lshr_b64 s[62:63], s[2:3], 24 +; GFX11-NEXT: s_lshr_b32 s43, s28, 8 +; GFX11-NEXT: v_writelane_b32 v36, s42, 2 +; GFX11-NEXT: s_lshr_b32 s42, s27, 16 +; GFX11-NEXT: v_writelane_b32 v37, s62, 12 +; GFX11-NEXT: s_lshr_b32 s98, s41, 24 +; GFX11-NEXT: s_lshr_b32 s99, s41, 16 +; GFX11-NEXT: v_writelane_b32 v36, s42, 3 +; GFX11-NEXT: s_lshr_b32 s42, s27, 8 +; GFX11-NEXT: v_writelane_b32 v37, s63, 13 +; GFX11-NEXT: s_lshr_b64 s[62:63], s[4:5], 24 +; GFX11-NEXT: s_lshr_b32 s100, s41, 8 +; GFX11-NEXT: v_writelane_b32 v36, s42, 4 +; GFX11-NEXT: s_lshr_b32 s42, s26, 16 +; GFX11-NEXT: v_writelane_b32 v37, s62, 10 +; GFX11-NEXT: s_lshr_b32 s44, s40, 16 +; GFX11-NEXT: s_lshr_b32 s45, s40, 8 +; GFX11-NEXT: v_writelane_b32 v36, s42, 5 +; GFX11-NEXT: s_lshr_b32 s42, s26, 8 +; GFX11-NEXT: v_writelane_b32 v37, s63, 11 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[6:7], 24 -; GFX11-NEXT: s_lshr_b32 s43, s2, 8 -; GFX11-NEXT: v_writelane_b32 v18, s42, 2 -; GFX11-NEXT: s_lshr_b32 s42, s17, 16 -; GFX11-NEXT: v_writelane_b32 v19, s62, 12 -; GFX11-NEXT: s_lshr_b32 s98, s1, 24 -; GFX11-NEXT: s_lshr_b32 s99, s1, 16 -; GFX11-NEXT: v_writelane_b32 v18, s42, 3 -; GFX11-NEXT: s_lshr_b32 s42, s17, 8 -; GFX11-NEXT: v_writelane_b32 v19, s63, 13 +; GFX11-NEXT: s_lshr_b64 s[76:77], s[16:17], 24 +; GFX11-NEXT: v_writelane_b32 v36, s42, 6 +; GFX11-NEXT: s_lshr_b32 s42, s29, 24 +; GFX11-NEXT: v_writelane_b32 v37, s62, 8 +; GFX11-NEXT: s_lshr_b64 s[88:89], s[18:19], 24 +; GFX11-NEXT: s_lshr_b64 s[78:79], s[22:23], 24 +; GFX11-NEXT: v_writelane_b32 v36, s42, 7 +; GFX11-NEXT: s_lshr_b32 s42, s29, 16 +; GFX11-NEXT: v_writelane_b32 v37, s63, 9 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[8:9], 24 -; GFX11-NEXT: s_lshr_b32 s100, s1, 8 -; GFX11-NEXT: v_writelane_b32 v18, s42, 4 -; GFX11-NEXT: s_lshr_b32 s42, s16, 16 -; GFX11-NEXT: v_writelane_b32 v19, s62, 10 -; GFX11-NEXT: s_lshr_b32 s44, s0, 16 -; GFX11-NEXT: s_lshr_b32 s45, s0, 8 -; GFX11-NEXT: v_writelane_b32 v18, s42, 5 -; GFX11-NEXT: s_lshr_b32 s42, s16, 8 -; GFX11-NEXT: v_writelane_b32 v19, s63, 11 +; GFX11-NEXT: s_lshr_b64 s[90:91], s[24:25], 24 +; GFX11-NEXT: v_writelane_b32 v36, s42, 8 +; GFX11-NEXT: s_lshr_b32 s42, s29, 8 +; GFX11-NEXT: v_writelane_b32 v37, s62, 6 +; GFX11-NEXT: s_lshr_b64 s[92:93], s[26:27], 24 +; GFX11-NEXT: s_lshr_b64 s[94:95], s[28:29], 24 +; GFX11-NEXT: s_lshr_b64 s[30:31], s[40:41], 24 +; GFX11-NEXT: v_writelane_b32 v36, s42, 9 +; GFX11-NEXT: v_writelane_b32 v37, s63, 7 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[10:11], 24 -; GFX11-NEXT: s_lshr_b64 s[76:77], s[26:27], 24 -; GFX11-NEXT: v_writelane_b32 v18, s42, 6 -; GFX11-NEXT: s_lshr_b32 s42, s3, 24 -; GFX11-NEXT: v_writelane_b32 v19, s62, 8 -; GFX11-NEXT: s_lshr_b64 s[88:89], s[24:25], 24 -; GFX11-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 -; GFX11-NEXT: v_writelane_b32 v18, s42, 7 -; GFX11-NEXT: s_lshr_b32 s42, s3, 16 -; GFX11-NEXT: v_writelane_b32 v19, s63, 9 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_writelane_b32 v37, s62, 4 +; GFX11-NEXT: v_writelane_b32 v37, s63, 5 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 -; GFX11-NEXT: s_lshr_b64 s[90:91], s[18:19], 24 -; GFX11-NEXT: v_writelane_b32 v18, s42, 8 -; GFX11-NEXT: s_lshr_b32 s42, s3, 8 -; GFX11-NEXT: v_writelane_b32 v19, s62, 6 -; GFX11-NEXT: s_lshr_b64 s[92:93], s[16:17], 24 -; GFX11-NEXT: s_lshr_b64 s[94:95], s[2:3], 24 -; GFX11-NEXT: s_lshr_b64 s[30:31], s[0:1], 24 -; GFX11-NEXT: v_writelane_b32 v18, s42, 9 -; GFX11-NEXT: v_writelane_b32 v19, s63, 7 +; GFX11-NEXT: v_writelane_b32 v37, s62, 2 +; GFX11-NEXT: v_writelane_b32 v37, s63, 3 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[14:15], 24 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_writelane_b32 v19, s62, 4 -; GFX11-NEXT: v_writelane_b32 v19, s63, 5 -; GFX11-NEXT: s_lshr_b64 s[62:63], s[40:41], 24 -; GFX11-NEXT: v_writelane_b32 v19, s62, 2 -; GFX11-NEXT: v_writelane_b32 v19, s63, 3 -; GFX11-NEXT: s_lshr_b64 s[62:63], s[28:29], 24 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_writelane_b32 v19, s62, 0 -; GFX11-NEXT: v_writelane_b32 v19, s63, 1 -; GFX11-NEXT: s_lshr_b64 s[62:63], s[22:23], 24 +; GFX11-NEXT: v_writelane_b32 v37, s62, 0 +; GFX11-NEXT: v_writelane_b32 v37, s63, 1 +; GFX11-NEXT: s_lshr_b64 s[62:63], s[20:21], 24 ; GFX11-NEXT: .LBB57_5: ; %end ; GFX11-NEXT: s_lshl_b32 s43, s43, 8 -; GFX11-NEXT: s_and_b32 s2, s2, 0xff +; GFX11-NEXT: s_and_b32 s28, s28, 0xff ; GFX11-NEXT: s_and_b32 s42, s74, 0xff -; GFX11-NEXT: s_or_b32 s2, s2, s43 +; GFX11-NEXT: s_or_b32 s28, s28, s43 ; GFX11-NEXT: s_lshl_b32 s43, s94, 8 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_and_b32 s28, s28, 0xffff +; GFX11-NEXT: s_or_b32 s42, s42, s43 +; GFX11-NEXT: s_and_b32 s29, s29, 0xff +; GFX11-NEXT: s_lshl_b32 s42, s42, 16 +; GFX11-NEXT: v_readlane_b32 s43, v36, 7 +; GFX11-NEXT: s_or_b32 s28, s28, s42 +; GFX11-NEXT: v_readlane_b32 s42, v36, 9 +; GFX11-NEXT: s_and_b32 s26, s26, 0xff +; GFX11-NEXT: s_and_b32 s27, s27, 0xff +; GFX11-NEXT: s_lshl_b32 s43, s43, 8 +; GFX11-NEXT: s_and_b32 s24, s24, 0xff +; GFX11-NEXT: s_lshl_b32 s42, s42, 8 +; GFX11-NEXT: s_and_b32 s25, s25, 0xff +; GFX11-NEXT: s_or_b32 s29, s29, s42 +; GFX11-NEXT: v_readlane_b32 s42, v36, 8 +; GFX11-NEXT: s_and_b32 s29, s29, 0xffff +; GFX11-NEXT: s_and_b32 s22, s22, 0xff +; GFX11-NEXT: s_and_b32 s23, s23, 0xff +; GFX11-NEXT: s_and_b32 s20, s20, 0xff +; GFX11-NEXT: s_and_b32 s42, s42, 0xff +; GFX11-NEXT: s_and_b32 s21, s21, 0xff ; GFX11-NEXT: s_or_b32 s42, s42, s43 ; GFX11-NEXT: s_lshl_b32 s45, s45, 8 ; GFX11-NEXT: s_lshl_b32 s42, s42, 16 -; GFX11-NEXT: s_and_b32 s0, s0, 0xff -; GFX11-NEXT: s_or_b32 s2, s2, s42 -; GFX11-NEXT: v_readlane_b32 s42, v18, 9 -; GFX11-NEXT: s_or_b32 s0, s0, s45 +; GFX11-NEXT: s_and_b32 s40, s40, 0xff +; GFX11-NEXT: s_or_b32 s29, s29, s42 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v3, s28 :: v_dual_mov_b32 v4, s29 +; GFX11-NEXT: v_readlane_b32 s28, v36, 6 +; GFX11-NEXT: v_readlane_b32 s29, v36, 5 +; GFX11-NEXT: s_or_b32 s40, s40, s45 ; GFX11-NEXT: s_lshl_b32 s45, s30, 8 ; GFX11-NEXT: s_and_b32 s44, s44, 0xff -; GFX11-NEXT: s_and_b32 s3, s3, 0xff +; GFX11-NEXT: s_lshl_b32 s28, s28, 8 +; GFX11-NEXT: s_and_b32 s29, s29, 0xff +; GFX11-NEXT: s_or_b32 s26, s26, s28 +; GFX11-NEXT: s_lshl_b32 s28, s92, 8 +; GFX11-NEXT: s_and_b32 s26, s26, 0xffff +; GFX11-NEXT: s_or_b32 s28, s29, s28 +; GFX11-NEXT: v_readlane_b32 s29, v36, 2 +; GFX11-NEXT: s_lshl_b32 s28, s28, 16 ; GFX11-NEXT: s_or_b32 s44, s44, s45 -; GFX11-NEXT: s_lshl_b32 s42, s42, 8 -; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_or_b32 s26, s26, s28 +; GFX11-NEXT: v_readlane_b32 s28, v36, 4 +; GFX11-NEXT: s_lshl_b32 s29, s29, 8 +; GFX11-NEXT: s_and_b32 s18, s18, 0xff +; GFX11-NEXT: s_and_b32 s40, s40, 0xffff ; GFX11-NEXT: s_lshl_b32 s44, s44, 16 -; GFX11-NEXT: s_or_b32 s3, s3, s42 -; GFX11-NEXT: v_readlane_b32 s42, v18, 8 -; GFX11-NEXT: v_readlane_b32 s43, v18, 7 -; GFX11-NEXT: s_or_b32 s0, s0, s44 -; GFX11-NEXT: s_and_b32 s1, s1, 0xff +; GFX11-NEXT: s_lshl_b32 s28, s28, 8 +; GFX11-NEXT: s_or_b32 s40, s40, s44 +; GFX11-NEXT: s_or_b32 s27, s27, s28 +; GFX11-NEXT: v_readlane_b32 s28, v36, 3 +; GFX11-NEXT: s_and_b32 s27, s27, 0xffff +; GFX11-NEXT: s_and_b32 s41, s41, 0xff ; GFX11-NEXT: s_lshl_b32 s44, s100, 8 ; GFX11-NEXT: s_lshl_b32 s45, s98, 8 -; GFX11-NEXT: s_or_b32 s1, s1, s44 +; GFX11-NEXT: s_and_b32 s28, s28, 0xff +; GFX11-NEXT: s_or_b32 s41, s41, s44 +; GFX11-NEXT: s_or_b32 s28, s28, s29 +; GFX11-NEXT: v_readlane_b32 s29, v36, 0 +; GFX11-NEXT: s_lshl_b32 s28, s28, 16 ; GFX11-NEXT: s_and_b32 s44, s99, 0xff -; GFX11-NEXT: s_and_b32 s42, s42, 0xff +; GFX11-NEXT: s_or_b32 s27, s27, s28 +; GFX11-NEXT: v_readlane_b32 s28, v36, 1 +; GFX11-NEXT: s_and_b32 s29, s29, 0xff +; GFX11-NEXT: v_dual_mov_b32 v5, s26 :: v_dual_mov_b32 v6, s27 +; GFX11-NEXT: v_readlane_b32 s26, v37, 19 +; GFX11-NEXT: s_lshl_b32 s28, s28, 8 ; GFX11-NEXT: s_or_b32 s44, s44, s45 -; GFX11-NEXT: s_lshl_b32 s43, s43, 8 -; GFX11-NEXT: s_and_b32 s1, s1, 0xffff +; GFX11-NEXT: s_or_b32 s24, s24, s28 +; GFX11-NEXT: s_lshl_b32 s28, s90, 8 +; GFX11-NEXT: s_and_b32 s24, s24, 0xffff +; GFX11-NEXT: s_or_b32 s28, s29, s28 +; GFX11-NEXT: v_readlane_b32 s29, v37, 29 +; GFX11-NEXT: s_lshl_b32 s28, s28, 16 +; GFX11-NEXT: s_lshl_b32 s26, s26, 8 +; GFX11-NEXT: s_or_b32 s24, s24, s28 +; GFX11-NEXT: v_readlane_b32 s28, v37, 31 +; GFX11-NEXT: s_lshl_b32 s29, s29, 8 +; GFX11-NEXT: s_and_b32 s19, s19, 0xff +; GFX11-NEXT: s_and_b32 s41, s41, 0xffff ; GFX11-NEXT: s_lshl_b32 s44, s44, 16 -; GFX11-NEXT: s_or_b32 s42, s42, s43 -; GFX11-NEXT: s_or_b32 s1, s1, s44 -; GFX11-NEXT: s_and_b32 s3, s3, 0xffff -; GFX11-NEXT: s_lshl_b32 s42, s42, 16 -; GFX11-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1 -; GFX11-NEXT: v_readlane_b32 s0, v18, 6 -; GFX11-NEXT: s_or_b32 s3, s3, s42 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3 -; GFX11-NEXT: v_readlane_b32 s2, v18, 5 -; GFX11-NEXT: s_lshl_b32 s0, s0, 8 -; GFX11-NEXT: s_and_b32 s1, s16, 0xff -; GFX11-NEXT: v_readlane_b32 s3, v18, 2 -; GFX11-NEXT: s_or_b32 s0, s1, s0 -; GFX11-NEXT: s_lshl_b32 s1, s92, 8 -; GFX11-NEXT: s_and_b32 s2, s2, 0xff -; GFX11-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-NEXT: s_or_b32 s1, s2, s1 -; GFX11-NEXT: v_readlane_b32 s2, v18, 4 -; GFX11-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-NEXT: s_lshl_b32 s3, s3, 8 -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_and_b32 s1, s17, 0xff -; GFX11-NEXT: s_lshl_b32 s2, s2, 8 -; GFX11-NEXT: v_readlane_b32 s16, v18, 0 -; GFX11-NEXT: s_or_b32 s1, s1, s2 -; GFX11-NEXT: v_readlane_b32 s2, v18, 3 -; GFX11-NEXT: s_and_b32 s1, s1, 0xffff -; GFX11-NEXT: v_readlane_b32 s17, v19, 29 -; GFX11-NEXT: s_and_b32 s16, s16, 0xff -; GFX11-NEXT: v_readlane_b32 s100, v17, 4 -; GFX11-NEXT: s_and_b32 s2, s2, 0xff -; GFX11-NEXT: v_readlane_b32 s99, v17, 3 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_and_b32 s3, s18, 0xff -; GFX11-NEXT: s_lshl_b32 s2, s2, 16 -; GFX11-NEXT: s_lshl_b32 s17, s17, 8 -; GFX11-NEXT: s_or_b32 s1, s1, s2 -; GFX11-NEXT: v_readlane_b32 s2, v18, 1 -; GFX11-NEXT: v_dual_mov_b32 v5, s0 :: v_dual_mov_b32 v6, s1 -; GFX11-NEXT: v_readlane_b32 s0, v19, 28 -; GFX11-NEXT: s_and_b32 s1, s20, 0xff -; GFX11-NEXT: s_lshl_b32 s2, s2, 8 -; GFX11-NEXT: v_readlane_b32 s18, v19, 19 -; GFX11-NEXT: s_or_b32 s2, s3, s2 -; GFX11-NEXT: s_lshl_b32 s3, s90, 8 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_or_b32 s3, s16, s3 -; GFX11-NEXT: v_readlane_b32 s16, v19, 31 -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_lshl_b32 s0, s0, 8 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_and_b32 s3, s19, 0xff -; GFX11-NEXT: s_lshl_b32 s16, s16, 8 -; GFX11-NEXT: s_or_b32 s0, s1, s0 -; GFX11-NEXT: s_or_b32 s3, s3, s16 -; GFX11-NEXT: v_readlane_b32 s16, v19, 30 -; GFX11-NEXT: s_and_b32 s3, s3, 0xffff -; GFX11-NEXT: s_lshl_b32 s1, s78, 8 -; GFX11-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-NEXT: s_lshl_b32 s18, s18, 8 +; GFX11-NEXT: s_lshl_b32 s28, s28, 8 +; GFX11-NEXT: s_or_b32 s41, s41, s44 +; GFX11-NEXT: s_or_b32 s25, s25, s28 +; GFX11-NEXT: v_readlane_b32 s28, v37, 30 +; GFX11-NEXT: s_and_b32 s25, s25, 0xffff +; GFX11-NEXT: v_dual_mov_b32 v1, s40 :: v_dual_mov_b32 v2, s41 ; GFX11-NEXT: s_and_b32 s16, s16, 0xff -; GFX11-NEXT: s_lshl_b32 s19, s86, 8 -; GFX11-NEXT: s_or_b32 s16, s16, s17 -; GFX11-NEXT: v_readlane_b32 s17, v19, 21 -; GFX11-NEXT: s_lshl_b32 s16, s16, 16 -; GFX11-NEXT: v_readlane_b32 s98, v17, 2 -; GFX11-NEXT: s_or_b32 s3, s3, s16 +; GFX11-NEXT: s_and_b32 s28, s28, 0xff +; GFX11-NEXT: s_and_b32 s17, s17, 0xff +; GFX11-NEXT: s_or_b32 s28, s28, s29 +; GFX11-NEXT: s_and_b32 s14, s14, 0xff +; GFX11-NEXT: s_lshl_b32 s28, s28, 16 +; GFX11-NEXT: s_and_b32 s15, s15, 0xff +; GFX11-NEXT: s_or_b32 s25, s25, s28 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v8, s3 -; GFX11-NEXT: v_readlane_b32 s2, v19, 27 -; GFX11-NEXT: v_readlane_b32 s3, v19, 24 -; GFX11-NEXT: v_readlane_b32 s16, v19, 22 -; GFX11-NEXT: s_lshl_b32 s17, s17, 8 +; GFX11-NEXT: v_dual_mov_b32 v7, s24 :: v_dual_mov_b32 v8, s25 +; GFX11-NEXT: v_readlane_b32 s24, v37, 28 +; GFX11-NEXT: v_readlane_b32 s25, v37, 27 ; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off ; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:16 +; GFX11-NEXT: s_and_b32 s12, s12, 0xff +; GFX11-NEXT: s_lshl_b32 s24, s24, 8 +; GFX11-NEXT: s_and_b32 s25, s25, 0xff +; GFX11-NEXT: s_or_b32 s22, s22, s24 +; GFX11-NEXT: s_lshl_b32 s24, s78, 8 +; GFX11-NEXT: s_and_b32 s22, s22, 0xffff +; GFX11-NEXT: s_or_b32 s24, s25, s24 +; GFX11-NEXT: v_readlane_b32 s25, v37, 24 +; GFX11-NEXT: s_lshl_b32 s24, s24, 16 +; GFX11-NEXT: s_and_b32 s13, s13, 0xff +; GFX11-NEXT: s_or_b32 s22, s22, s24 +; GFX11-NEXT: v_readlane_b32 s24, v37, 26 +; GFX11-NEXT: s_lshl_b32 s25, s25, 8 +; GFX11-NEXT: s_and_b32 s10, s10, 0xff +; GFX11-NEXT: s_and_b32 s11, s11, 0xff +; GFX11-NEXT: s_and_b32 s8, s8, 0xff +; GFX11-NEXT: s_lshl_b32 s24, s24, 8 +; GFX11-NEXT: s_and_b32 s9, s9, 0xff +; GFX11-NEXT: s_or_b32 s23, s23, s24 +; GFX11-NEXT: v_readlane_b32 s24, v37, 25 +; GFX11-NEXT: s_and_b32 s23, s23, 0xffff +; GFX11-NEXT: s_and_b32 s6, s6, 0xff +; GFX11-NEXT: s_and_b32 s7, s7, 0xff +; GFX11-NEXT: s_and_b32 s4, s4, 0xff +; GFX11-NEXT: s_and_b32 s24, s24, 0xff +; GFX11-NEXT: s_and_b32 s5, s5, 0xff +; GFX11-NEXT: s_or_b32 s24, s24, s25 +; GFX11-NEXT: v_readlane_b32 s25, v37, 22 +; GFX11-NEXT: s_lshl_b32 s24, s24, 16 ; GFX11-NEXT: s_and_b32 s2, s2, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s3, 8 -; GFX11-NEXT: s_or_b32 s1, s2, s1 -; GFX11-NEXT: v_readlane_b32 s2, v19, 26 -; GFX11-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-NEXT: s_and_b32 s16, s16, 0xff -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_and_b32 s1, s21, 0xff -; GFX11-NEXT: s_lshl_b32 s2, s2, 8 -; GFX11-NEXT: v_readlane_b32 s86, v16, 30 -; GFX11-NEXT: s_or_b32 s1, s1, s2 -; GFX11-NEXT: v_readlane_b32 s2, v19, 25 -; GFX11-NEXT: s_and_b32 s1, s1, 0xffff -; GFX11-NEXT: v_readlane_b32 s31, v16, 1 -; GFX11-NEXT: v_readlane_b32 s30, v16, 0 -; GFX11-NEXT: s_and_b32 s2, s2, 0xff -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_and_b32 s3, s22, 0xff -; GFX11-NEXT: s_lshl_b32 s2, s2, 16 -; GFX11-NEXT: s_or_b32 s1, s1, s2 -; GFX11-NEXT: v_readlane_b32 s2, v19, 23 -; GFX11-NEXT: v_dual_mov_b32 v9, s0 :: v_dual_mov_b32 v10, s1 -; GFX11-NEXT: v_readlane_b32 s1, v19, 18 -; GFX11-NEXT: s_and_b32 s0, s24, 0xff -; GFX11-NEXT: s_lshl_b32 s2, s2, 8 +; GFX11-NEXT: s_or_b32 s23, s23, s24 +; GFX11-NEXT: v_readlane_b32 s24, v37, 23 +; GFX11-NEXT: s_and_b32 s25, s25, 0xff +; GFX11-NEXT: v_dual_mov_b32 v9, s22 :: v_dual_mov_b32 v10, s23 +; GFX11-NEXT: s_lshl_b32 s22, s88, 8 +; GFX11-NEXT: s_lshl_b32 s24, s24, 8 +; GFX11-NEXT: s_lshl_b32 s23, s97, 8 +; GFX11-NEXT: s_or_b32 s20, s20, s24 +; GFX11-NEXT: s_lshl_b32 s24, s62, 8 +; GFX11-NEXT: s_and_b32 s20, s20, 0xffff +; GFX11-NEXT: s_or_b32 s24, s25, s24 +; GFX11-NEXT: v_readlane_b32 s25, v37, 21 +; GFX11-NEXT: s_lshl_b32 s24, s24, 16 +; GFX11-NEXT: s_and_b32 s3, s3, 0xff +; GFX11-NEXT: s_or_b32 s20, s20, s24 +; GFX11-NEXT: s_and_b32 s0, s0, 0xff +; GFX11-NEXT: s_lshl_b32 s25, s25, 8 +; GFX11-NEXT: s_and_b32 s1, s1, 0xff +; GFX11-NEXT: s_or_b32 s21, s21, s25 +; GFX11-NEXT: v_readlane_b32 s25, v37, 20 +; GFX11-NEXT: s_and_b32 s21, s21, 0xffff +; GFX11-NEXT: v_readlane_b32 s100, v35, 4 +; GFX11-NEXT: v_readlane_b32 s99, v35, 3 +; GFX11-NEXT: v_readlane_b32 s98, v35, 2 +; GFX11-NEXT: s_and_b32 s25, s25, 0xff +; GFX11-NEXT: v_readlane_b32 s97, v35, 1 +; GFX11-NEXT: s_or_b32 s25, s25, s26 +; GFX11-NEXT: v_readlane_b32 s31, v34, 1 +; GFX11-NEXT: s_lshl_b32 s24, s25, 16 +; GFX11-NEXT: v_readlane_b32 s30, v34, 0 +; GFX11-NEXT: s_or_b32 s21, s21, s24 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: s_or_b32 s2, s3, s2 -; GFX11-NEXT: s_lshl_b32 s3, s62, 8 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_or_b32 s3, s16, s3 -; GFX11-NEXT: s_and_b32 s16, s23, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_or_b32 s16, s16, s17 -; GFX11-NEXT: v_readlane_b32 s17, v19, 20 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_and_b32 s3, s16, 0xffff -; GFX11-NEXT: s_lshl_b32 s1, s1, 8 -; GFX11-NEXT: s_and_b32 s17, s17, 0xff -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_or_b32 s17, s17, s18 -; GFX11-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-NEXT: s_lshl_b32 s16, s17, 16 -; GFX11-NEXT: s_lshl_b32 s17, s97, 8 -; GFX11-NEXT: s_or_b32 s3, s3, s16 +; GFX11-NEXT: v_dual_mov_b32 v11, s20 :: v_dual_mov_b32 v12, s21 +; GFX11-NEXT: v_readlane_b32 s20, v37, 18 +; GFX11-NEXT: v_readlane_b32 s21, v37, 17 +; GFX11-NEXT: s_lshl_b32 s20, s20, 8 +; GFX11-NEXT: s_and_b32 s21, s21, 0xff +; GFX11-NEXT: s_or_b32 s18, s18, s20 +; GFX11-NEXT: s_or_b32 s20, s21, s22 +; GFX11-NEXT: v_readlane_b32 s21, v37, 16 +; GFX11-NEXT: s_and_b32 s22, s69, 0xff +; GFX11-NEXT: s_and_b32 s18, s18, 0xffff +; GFX11-NEXT: s_lshl_b32 s20, s20, 16 +; GFX11-NEXT: v_readlane_b32 s69, v34, 21 +; GFX11-NEXT: s_lshl_b32 s21, s21, 8 +; GFX11-NEXT: s_or_b32 s18, s18, s20 +; GFX11-NEXT: s_or_b32 s19, s19, s21 +; GFX11-NEXT: s_or_b32 s21, s22, s23 +; GFX11-NEXT: s_and_b32 s19, s19, 0xffff +; GFX11-NEXT: s_lshl_b32 s21, s21, 16 +; GFX11-NEXT: s_lshl_b32 s20, s96, 8 +; GFX11-NEXT: s_or_b32 s19, s19, s21 +; GFX11-NEXT: s_and_b32 s21, s73, 0xff +; GFX11-NEXT: s_lshl_b32 s22, s76, 8 +; GFX11-NEXT: s_or_b32 s16, s16, s20 +; GFX11-NEXT: s_or_b32 s20, s21, s22 +; GFX11-NEXT: s_lshl_b32 s21, s87, 8 +; GFX11-NEXT: s_and_b32 s22, s72, 0xff +; GFX11-NEXT: s_lshl_b32 s23, s86, 8 +; GFX11-NEXT: s_or_b32 s17, s17, s21 +; GFX11-NEXT: s_or_b32 s21, s22, s23 +; GFX11-NEXT: v_dual_mov_b32 v1, s18 :: v_dual_mov_b32 v2, s19 +; GFX11-NEXT: v_readlane_b32 s18, v37, 0 +; GFX11-NEXT: s_and_b32 s16, s16, 0xffff +; GFX11-NEXT: s_lshl_b32 s20, s20, 16 +; GFX11-NEXT: s_and_b32 s17, s17, 0xffff +; GFX11-NEXT: s_lshl_b32 s21, s21, 16 +; GFX11-NEXT: s_or_b32 s16, s16, s20 +; GFX11-NEXT: s_or_b32 s17, s17, s21 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v12, s3 -; GFX11-NEXT: v_readlane_b32 s2, v19, 17 -; GFX11-NEXT: s_lshl_b32 s3, s88, 8 -; GFX11-NEXT: s_and_b32 s16, s69, 0xff -; GFX11-NEXT: s_and_b32 s18, s72, 0xff -; GFX11-NEXT: v_readlane_b32 s97, v17, 1 -; GFX11-NEXT: s_and_b32 s2, s2, 0xff -; GFX11-NEXT: v_readlane_b32 s69, v16, 21 -; GFX11-NEXT: s_or_b32 s1, s2, s3 -; GFX11-NEXT: v_readlane_b32 s3, v19, 16 -; GFX11-NEXT: s_and_b32 s2, s25, 0xff -; GFX11-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_lshl_b32 s3, s3, 8 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s16, s17 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_and_b32 s16, s73, 0xff -; GFX11-NEXT: s_or_b32 s1, s2, s3 -; GFX11-NEXT: s_and_b32 s2, s26, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s96, 8 -; GFX11-NEXT: s_lshl_b32 s17, s76, 8 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s16, s17 -; GFX11-NEXT: s_and_b32 s16, s27, 0xff -; GFX11-NEXT: s_lshl_b32 s17, s87, 8 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_or_b32 s16, s16, s17 +; GFX11-NEXT: v_dual_mov_b32 v3, s16 :: v_dual_mov_b32 v4, s17 +; GFX11-NEXT: s_lshl_b32 s16, s85, 8 +; GFX11-NEXT: s_and_b32 s17, s84, 0xff +; GFX11-NEXT: s_lshl_b32 s18, s18, 8 +; GFX11-NEXT: v_readlane_b32 s19, v37, 1 +; GFX11-NEXT: s_or_b32 s14, s14, s16 +; GFX11-NEXT: s_or_b32 s16, s17, s18 +; GFX11-NEXT: s_lshl_b32 s17, s83, 8 +; GFX11-NEXT: s_and_b32 s18, s82, 0xff +; GFX11-NEXT: s_lshl_b32 s19, s81, 8 +; GFX11-NEXT: s_or_b32 s15, s15, s17 ; GFX11-NEXT: s_or_b32 s17, s18, s19 -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_and_b32 s16, s16, 0xffff +; GFX11-NEXT: v_readlane_b32 s18, v37, 2 +; GFX11-NEXT: s_and_b32 s14, s14, 0xffff +; GFX11-NEXT: s_lshl_b32 s16, s16, 16 +; GFX11-NEXT: s_and_b32 s15, s15, 0xffff ; GFX11-NEXT: s_lshl_b32 s17, s17, 16 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s16, s17 -; GFX11-NEXT: v_readlane_b32 s16, v19, 0 -; GFX11-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1 -; GFX11-NEXT: v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3 -; GFX11-NEXT: s_and_b32 s0, s28, 0xff -; GFX11-NEXT: s_lshl_b32 s1, s85, 8 -; GFX11-NEXT: s_and_b32 s2, s84, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s16, 8 -; GFX11-NEXT: v_readlane_b32 s17, v19, 1 -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_or_b32 s1, s2, s3 -; GFX11-NEXT: s_and_b32 s2, s29, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s83, 8 -; GFX11-NEXT: s_and_b32 s16, s82, 0xff -; GFX11-NEXT: s_lshl_b32 s17, s81, 8 -; GFX11-NEXT: v_readlane_b32 s18, v19, 2 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s16, s17 -; GFX11-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_or_b32 s1, s2, s3 -; GFX11-NEXT: s_and_b32 s2, s40, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s61, 8 -; GFX11-NEXT: s_and_b32 s16, s80, 0xff -; GFX11-NEXT: s_lshl_b32 s17, s18, 8 -; GFX11-NEXT: v_readlane_b32 s19, v19, 3 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s16, s17 -; GFX11-NEXT: s_and_b32 s16, s41, 0xff +; GFX11-NEXT: s_or_b32 s14, s14, s16 +; GFX11-NEXT: s_or_b32 s15, s15, s17 +; GFX11-NEXT: s_lshl_b32 s16, s61, 8 +; GFX11-NEXT: s_and_b32 s17, s80, 0xff +; GFX11-NEXT: s_lshl_b32 s18, s18, 8 +; GFX11-NEXT: v_readlane_b32 s19, v37, 3 +; GFX11-NEXT: s_or_b32 s12, s12, s16 +; GFX11-NEXT: s_or_b32 s16, s17, s18 ; GFX11-NEXT: s_lshl_b32 s17, s60, 8 ; GFX11-NEXT: s_and_b32 s18, s71, 0xff ; GFX11-NEXT: s_lshl_b32 s19, s70, 8 -; GFX11-NEXT: s_or_b32 s16, s16, s17 +; GFX11-NEXT: s_or_b32 s13, s13, s17 ; GFX11-NEXT: s_or_b32 s17, s18, s19 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_and_b32 s16, s16, 0xffff +; GFX11-NEXT: v_dual_mov_b32 v5, s14 :: v_dual_mov_b32 v6, s15 +; GFX11-NEXT: v_readlane_b32 s14, v37, 4 +; GFX11-NEXT: s_and_b32 s12, s12, 0xffff +; GFX11-NEXT: s_lshl_b32 s16, s16, 16 +; GFX11-NEXT: s_and_b32 s13, s13, 0xffff ; GFX11-NEXT: s_lshl_b32 s17, s17, 16 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s16, s17 -; GFX11-NEXT: v_readlane_b32 s16, v19, 4 -; GFX11-NEXT: v_dual_mov_b32 v5, s0 :: v_dual_mov_b32 v6, s1 -; GFX11-NEXT: v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v8, s3 -; GFX11-NEXT: s_and_b32 s0, s14, 0xff -; GFX11-NEXT: s_lshl_b32 s1, s58, 8 -; GFX11-NEXT: s_and_b32 s2, s59, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s16, 8 -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_or_b32 s1, s2, s3 -; GFX11-NEXT: s_and_b32 s2, s15, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s68, 8 +; GFX11-NEXT: s_or_b32 s12, s12, s16 +; GFX11-NEXT: s_or_b32 s13, s13, s17 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v7, s12 :: v_dual_mov_b32 v8, s13 +; GFX11-NEXT: s_lshl_b32 s12, s58, 8 +; GFX11-NEXT: s_and_b32 s13, s59, 0xff +; GFX11-NEXT: s_lshl_b32 s14, s14, 8 +; GFX11-NEXT: v_readlane_b32 s15, v37, 5 +; GFX11-NEXT: s_or_b32 s10, s10, s12 +; GFX11-NEXT: s_or_b32 s12, s13, s14 +; GFX11-NEXT: s_lshl_b32 s13, s68, 8 ; GFX11-NEXT: s_and_b32 s14, s67, 0xff ; GFX11-NEXT: s_lshl_b32 s15, s66, 8 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s14, s15 -; GFX11-NEXT: v_readlane_b32 s14, v19, 6 -; GFX11-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_or_b32 s1, s2, s3 -; GFX11-NEXT: s_and_b32 s2, s12, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s65, 8 -; GFX11-NEXT: s_and_b32 s12, s64, 0xff +; GFX11-NEXT: s_or_b32 s11, s11, s13 +; GFX11-NEXT: s_or_b32 s13, s14, s15 +; GFX11-NEXT: v_readlane_b32 s14, v37, 6 +; GFX11-NEXT: s_and_b32 s10, s10, 0xffff +; GFX11-NEXT: s_lshl_b32 s12, s12, 16 +; GFX11-NEXT: s_and_b32 s11, s11, 0xffff +; GFX11-NEXT: s_lshl_b32 s13, s13, 16 +; GFX11-NEXT: s_or_b32 s10, s10, s12 +; GFX11-NEXT: s_or_b32 s11, s11, s13 +; GFX11-NEXT: s_lshl_b32 s12, s65, 8 +; GFX11-NEXT: s_and_b32 s13, s64, 0xff ; GFX11-NEXT: s_lshl_b32 s14, s14, 8 -; GFX11-NEXT: v_readlane_b32 s15, v19, 7 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s12, s14 -; GFX11-NEXT: s_and_b32 s12, s13, 0xff +; GFX11-NEXT: v_readlane_b32 s15, v37, 7 +; GFX11-NEXT: s_or_b32 s8, s8, s12 +; GFX11-NEXT: s_or_b32 s12, s13, s14 ; GFX11-NEXT: s_lshl_b32 s13, s55, 8 ; GFX11-NEXT: s_and_b32 s14, s54, 0xff ; GFX11-NEXT: s_lshl_b32 s15, s53, 8 -; GFX11-NEXT: s_or_b32 s12, s12, s13 +; GFX11-NEXT: s_or_b32 s9, s9, s13 ; GFX11-NEXT: s_or_b32 s13, s14, s15 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_and_b32 s12, s12, 0xffff -; GFX11-NEXT: s_lshl_b32 s13, s13, 16 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s12, s13 -; GFX11-NEXT: v_readlane_b32 s12, v19, 8 ; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: scratch_store_b128 v0, v[9:12], off offset:32 ; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:48 -; GFX11-NEXT: v_dual_mov_b32 v9, s0 :: v_dual_mov_b32 v10, s1 -; GFX11-NEXT: v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v12, s3 -; GFX11-NEXT: s_and_b32 s0, s10, 0xff -; GFX11-NEXT: s_lshl_b32 s1, s52, 8 -; GFX11-NEXT: s_and_b32 s2, s51, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s12, 8 -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_or_b32 s1, s2, s3 -; GFX11-NEXT: s_and_b32 s2, s11, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s50, 8 +; GFX11-NEXT: v_dual_mov_b32 v9, s10 :: v_dual_mov_b32 v10, s11 +; GFX11-NEXT: v_readlane_b32 s10, v37, 8 +; GFX11-NEXT: s_and_b32 s8, s8, 0xffff +; GFX11-NEXT: s_lshl_b32 s12, s12, 16 +; GFX11-NEXT: s_and_b32 s9, s9, 0xffff +; GFX11-NEXT: s_lshl_b32 s13, s13, 16 +; GFX11-NEXT: s_or_b32 s8, s8, s12 +; GFX11-NEXT: s_or_b32 s9, s9, s13 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v11, s8 :: v_dual_mov_b32 v12, s9 +; GFX11-NEXT: s_lshl_b32 s8, s52, 8 +; GFX11-NEXT: s_and_b32 s9, s51, 0xff +; GFX11-NEXT: s_lshl_b32 s10, s10, 8 +; GFX11-NEXT: v_readlane_b32 s11, v37, 9 +; GFX11-NEXT: s_or_b32 s6, s6, s8 +; GFX11-NEXT: s_or_b32 s8, s9, s10 +; GFX11-NEXT: s_lshl_b32 s9, s50, 8 ; GFX11-NEXT: s_and_b32 s10, s49, 0xff ; GFX11-NEXT: s_lshl_b32 s11, s48, 8 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s10, s11 -; GFX11-NEXT: v_readlane_b32 s10, v19, 10 -; GFX11-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_or_b32 s1, s2, s3 -; GFX11-NEXT: s_and_b32 s2, s8, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s39, 8 -; GFX11-NEXT: s_and_b32 s8, s38, 0xff +; GFX11-NEXT: s_or_b32 s7, s7, s9 +; GFX11-NEXT: s_or_b32 s9, s10, s11 +; GFX11-NEXT: v_readlane_b32 s10, v37, 10 +; GFX11-NEXT: s_and_b32 s6, s6, 0xffff +; GFX11-NEXT: s_lshl_b32 s8, s8, 16 +; GFX11-NEXT: s_and_b32 s7, s7, 0xffff +; GFX11-NEXT: s_lshl_b32 s9, s9, 16 +; GFX11-NEXT: s_or_b32 s6, s6, s8 +; GFX11-NEXT: s_or_b32 s7, s7, s9 +; GFX11-NEXT: s_lshl_b32 s8, s39, 8 +; GFX11-NEXT: s_and_b32 s9, s38, 0xff ; GFX11-NEXT: s_lshl_b32 s10, s10, 8 -; GFX11-NEXT: v_readlane_b32 s11, v19, 11 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s8, s10 -; GFX11-NEXT: s_and_b32 s8, s9, 0xff +; GFX11-NEXT: v_readlane_b32 s11, v37, 11 +; GFX11-NEXT: s_or_b32 s4, s4, s8 +; GFX11-NEXT: s_or_b32 s8, s9, s10 ; GFX11-NEXT: s_lshl_b32 s9, s37, 8 ; GFX11-NEXT: s_and_b32 s10, s36, 0xff ; GFX11-NEXT: s_lshl_b32 s11, s35, 8 -; GFX11-NEXT: s_or_b32 s8, s8, s9 +; GFX11-NEXT: s_or_b32 s5, s5, s9 ; GFX11-NEXT: s_or_b32 s9, s10, s11 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_and_b32 s8, s8, 0xffff +; GFX11-NEXT: v_dual_mov_b32 v1, s6 :: v_dual_mov_b32 v2, s7 +; GFX11-NEXT: v_readlane_b32 s6, v37, 12 +; GFX11-NEXT: s_and_b32 s4, s4, 0xffff +; GFX11-NEXT: s_lshl_b32 s8, s8, 16 +; GFX11-NEXT: s_and_b32 s5, s5, 0xffff ; GFX11-NEXT: s_lshl_b32 s9, s9, 16 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s8, s9 -; GFX11-NEXT: v_readlane_b32 s8, v19, 12 -; GFX11-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1 -; GFX11-NEXT: v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3 -; GFX11-NEXT: s_and_b32 s0, s6, 0xff -; GFX11-NEXT: s_lshl_b32 s1, s56, 8 -; GFX11-NEXT: s_and_b32 s2, s57, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s8, 8 -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_or_b32 s1, s2, s3 -; GFX11-NEXT: s_and_b32 s2, s7, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s34, 8 +; GFX11-NEXT: s_or_b32 s4, s4, s8 +; GFX11-NEXT: s_or_b32 s5, s5, s9 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5 +; GFX11-NEXT: s_lshl_b32 s4, s56, 8 +; GFX11-NEXT: s_and_b32 s5, s57, 0xff +; GFX11-NEXT: s_lshl_b32 s6, s6, 8 +; GFX11-NEXT: v_readlane_b32 s7, v37, 13 +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: s_or_b32 s4, s5, s6 +; GFX11-NEXT: s_lshl_b32 s5, s34, 8 ; GFX11-NEXT: s_and_b32 s6, vcc_hi, 0xff ; GFX11-NEXT: s_lshl_b32 s7, s46, 8 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s6, s7 -; GFX11-NEXT: v_readlane_b32 s6, v19, 14 -; GFX11-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-NEXT: s_lshl_b32 s1, s1, 16 +; GFX11-NEXT: s_or_b32 s3, s3, s5 +; GFX11-NEXT: s_or_b32 s5, s6, s7 +; GFX11-NEXT: v_readlane_b32 s6, v37, 14 ; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_or_b32 s0, s0, s1 -; GFX11-NEXT: s_or_b32 s1, s2, s3 -; GFX11-NEXT: s_and_b32 s2, s4, 0xff -; GFX11-NEXT: s_lshl_b32 s3, s47, 8 -; GFX11-NEXT: s_and_b32 s4, s104, 0xff +; GFX11-NEXT: s_lshl_b32 s4, s4, 16 +; GFX11-NEXT: s_and_b32 s3, s3, 0xffff +; GFX11-NEXT: s_lshl_b32 s5, s5, 16 +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: s_or_b32 s3, s3, s5 +; GFX11-NEXT: s_lshl_b32 s4, s47, 8 +; GFX11-NEXT: s_and_b32 s5, s104, 0xff ; GFX11-NEXT: s_lshl_b32 s6, s6, 8 -; GFX11-NEXT: v_readlane_b32 s7, v19, 15 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s4, s6 -; GFX11-NEXT: s_and_b32 s4, s5, 0xff +; GFX11-NEXT: v_readlane_b32 s7, v37, 15 +; GFX11-NEXT: s_or_b32 s0, s0, s4 +; GFX11-NEXT: s_or_b32 s4, s5, s6 ; GFX11-NEXT: s_lshl_b32 s5, s103, 8 ; GFX11-NEXT: s_and_b32 s6, s102, 0xff ; GFX11-NEXT: s_lshl_b32 s7, s101, 8 -; GFX11-NEXT: s_or_b32 s4, s4, s5 +; GFX11-NEXT: s_or_b32 s1, s1, s5 ; GFX11-NEXT: s_or_b32 s5, s6, s7 -; GFX11-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-NEXT: s_and_b32 s4, s4, 0xffff +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_lshl_b32 s4, s4, 16 +; GFX11-NEXT: s_and_b32 s1, s1, 0xffff ; GFX11-NEXT: s_lshl_b32 s5, s5, 16 -; GFX11-NEXT: s_or_b32 s2, s2, s3 -; GFX11-NEXT: s_or_b32 s3, s4, s5 +; GFX11-NEXT: s_or_b32 s0, s0, s4 +; GFX11-NEXT: s_or_b32 s1, s1, s5 ; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:64 -; GFX11-NEXT: v_dual_mov_b32 v5, s0 :: v_dual_mov_b32 v6, s1 -; GFX11-NEXT: v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v8, s3 -; GFX11-NEXT: v_readlane_b32 s17, v19, 5 -; GFX11-NEXT: v_readlane_b32 s13, v19, 9 -; GFX11-NEXT: v_readlane_b32 s9, v19, 13 +; GFX11-NEXT: v_dual_mov_b32 v5, s2 :: v_dual_mov_b32 v6, s3 +; GFX11-NEXT: v_dual_mov_b32 v7, s0 :: v_dual_mov_b32 v8, s1 ; GFX11-NEXT: s_clause 0x2 ; GFX11-NEXT: scratch_store_b128 v0, v[9:12], off offset:80 ; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:96 ; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:112 -; GFX11-NEXT: v_readlane_b32 s104, v17, 8 -; GFX11-NEXT: v_readlane_b32 s103, v17, 7 -; GFX11-NEXT: v_readlane_b32 s102, v17, 6 -; GFX11-NEXT: v_readlane_b32 s101, v17, 5 -; GFX11-NEXT: v_readlane_b32 s96, v17, 0 -; GFX11-NEXT: v_readlane_b32 s87, v16, 31 -; GFX11-NEXT: v_readlane_b32 s85, v16, 29 -; GFX11-NEXT: v_readlane_b32 s84, v16, 28 -; GFX11-NEXT: v_readlane_b32 s83, v16, 27 -; GFX11-NEXT: v_readlane_b32 s82, v16, 26 -; GFX11-NEXT: v_readlane_b32 s81, v16, 25 -; GFX11-NEXT: v_readlane_b32 s80, v16, 24 -; GFX11-NEXT: v_readlane_b32 s71, v16, 23 -; GFX11-NEXT: v_readlane_b32 s70, v16, 22 -; GFX11-NEXT: v_readlane_b32 s68, v16, 20 -; GFX11-NEXT: v_readlane_b32 s67, v16, 19 -; GFX11-NEXT: v_readlane_b32 s66, v16, 18 -; GFX11-NEXT: v_readlane_b32 s65, v16, 17 -; GFX11-NEXT: v_readlane_b32 s64, v16, 16 -; GFX11-NEXT: v_readlane_b32 s55, v16, 15 -; GFX11-NEXT: v_readlane_b32 s54, v16, 14 -; GFX11-NEXT: v_readlane_b32 s53, v16, 13 -; GFX11-NEXT: v_readlane_b32 s52, v16, 12 -; GFX11-NEXT: v_readlane_b32 s51, v16, 11 -; GFX11-NEXT: v_readlane_b32 s50, v16, 10 -; GFX11-NEXT: v_readlane_b32 s49, v16, 9 -; GFX11-NEXT: v_readlane_b32 s48, v16, 8 -; GFX11-NEXT: v_readlane_b32 s39, v16, 7 -; GFX11-NEXT: v_readlane_b32 s38, v16, 6 -; GFX11-NEXT: v_readlane_b32 s37, v16, 5 -; GFX11-NEXT: v_readlane_b32 s36, v16, 4 -; GFX11-NEXT: v_readlane_b32 s35, v16, 3 -; GFX11-NEXT: v_readlane_b32 s34, v16, 2 +; GFX11-NEXT: v_readlane_b32 s104, v35, 8 +; GFX11-NEXT: v_readlane_b32 s103, v35, 7 +; GFX11-NEXT: v_readlane_b32 s102, v35, 6 +; GFX11-NEXT: v_readlane_b32 s101, v35, 5 +; GFX11-NEXT: v_readlane_b32 s96, v35, 0 +; GFX11-NEXT: v_readlane_b32 s87, v34, 31 +; GFX11-NEXT: v_readlane_b32 s86, v34, 30 +; GFX11-NEXT: v_readlane_b32 s85, v34, 29 +; GFX11-NEXT: v_readlane_b32 s84, v34, 28 +; GFX11-NEXT: v_readlane_b32 s83, v34, 27 +; GFX11-NEXT: v_readlane_b32 s82, v34, 26 +; GFX11-NEXT: v_readlane_b32 s81, v34, 25 +; GFX11-NEXT: v_readlane_b32 s80, v34, 24 +; GFX11-NEXT: v_readlane_b32 s71, v34, 23 +; GFX11-NEXT: v_readlane_b32 s70, v34, 22 +; GFX11-NEXT: v_readlane_b32 s68, v34, 20 +; GFX11-NEXT: v_readlane_b32 s67, v34, 19 +; GFX11-NEXT: v_readlane_b32 s66, v34, 18 +; GFX11-NEXT: v_readlane_b32 s65, v34, 17 +; GFX11-NEXT: v_readlane_b32 s64, v34, 16 +; GFX11-NEXT: v_readlane_b32 s55, v34, 15 +; GFX11-NEXT: v_readlane_b32 s54, v34, 14 +; GFX11-NEXT: v_readlane_b32 s53, v34, 13 +; GFX11-NEXT: v_readlane_b32 s52, v34, 12 +; GFX11-NEXT: v_readlane_b32 s51, v34, 11 +; GFX11-NEXT: v_readlane_b32 s50, v34, 10 +; GFX11-NEXT: v_readlane_b32 s49, v34, 9 +; GFX11-NEXT: v_readlane_b32 s48, v34, 8 +; GFX11-NEXT: v_readlane_b32 s39, v34, 7 +; GFX11-NEXT: v_readlane_b32 s38, v34, 6 +; GFX11-NEXT: v_readlane_b32 s37, v34, 5 +; GFX11-NEXT: v_readlane_b32 s36, v34, 4 +; GFX11-NEXT: v_readlane_b32 s35, v34, 3 +; GFX11-NEXT: v_readlane_b32 s34, v34, 2 ; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 ; GFX11-NEXT: s_clause 0x3 ; 16-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v16, off, s32 -; GFX11-NEXT: scratch_load_b32 v17, off, s32 offset:4 -; GFX11-NEXT: scratch_load_b32 v18, off, s32 offset:8 -; GFX11-NEXT: scratch_load_b32 v19, off, s32 offset:12 +; GFX11-NEXT: scratch_load_b32 v34, off, s32 +; GFX11-NEXT: scratch_load_b32 v35, off, s32 offset:4 +; GFX11-NEXT: scratch_load_b32 v36, off, s32 offset:8 +; GFX11-NEXT: scratch_load_b32 v37, off, s32 offset:12 ; GFX11-NEXT: s_mov_b32 exec_lo, s0 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] @@ -97390,47 +96463,75 @@ define inreg <64 x bfloat> @bitcast_v16i64_to_v64bf16_scalar(<16 x i64> inreg %a ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_writelane_b32 v20, s30, 0 -; SI-NEXT: v_writelane_b32 v20, s31, 1 -; SI-NEXT: v_writelane_b32 v20, s34, 2 -; SI-NEXT: v_writelane_b32 v20, s35, 3 -; SI-NEXT: v_writelane_b32 v20, s36, 4 -; SI-NEXT: v_writelane_b32 v20, s37, 5 -; SI-NEXT: v_writelane_b32 v20, s38, 6 -; SI-NEXT: v_writelane_b32 v20, s39, 7 -; SI-NEXT: v_writelane_b32 v20, s48, 8 -; SI-NEXT: v_writelane_b32 v20, s49, 9 -; SI-NEXT: v_writelane_b32 v20, s50, 10 -; SI-NEXT: v_writelane_b32 v20, s51, 11 -; SI-NEXT: v_writelane_b32 v20, s52, 12 -; SI-NEXT: v_writelane_b32 v20, s53, 13 -; SI-NEXT: v_writelane_b32 v20, s54, 14 -; SI-NEXT: v_writelane_b32 v20, s55, 15 -; SI-NEXT: v_writelane_b32 v20, s64, 16 -; SI-NEXT: v_writelane_b32 v20, s65, 17 -; SI-NEXT: v_writelane_b32 v20, s66, 18 -; SI-NEXT: v_writelane_b32 v20, s67, 19 -; SI-NEXT: v_writelane_b32 v20, s68, 20 -; SI-NEXT: v_writelane_b32 v20, s69, 21 -; SI-NEXT: v_writelane_b32 v20, s70, 22 -; SI-NEXT: v_writelane_b32 v20, s71, 23 -; SI-NEXT: v_writelane_b32 v20, s80, 24 -; SI-NEXT: v_writelane_b32 v20, s81, 25 -; SI-NEXT: v_writelane_b32 v20, s82, 26 -; SI-NEXT: v_writelane_b32 v20, s83, 27 -; SI-NEXT: v_writelane_b32 v20, s84, 28 -; SI-NEXT: v_writelane_b32 v20, s85, 29 -; SI-NEXT: v_writelane_b32 v20, s86, 30 -; SI-NEXT: v_writelane_b32 v20, s87, 31 -; SI-NEXT: v_writelane_b32 v20, s96, 32 -; SI-NEXT: v_writelane_b32 v20, s97, 33 -; SI-NEXT: v_writelane_b32 v20, s98, 34 +; SI-NEXT: v_writelane_b32 v21, s30, 0 +; SI-NEXT: v_writelane_b32 v21, s31, 1 +; SI-NEXT: v_writelane_b32 v21, s34, 2 +; SI-NEXT: v_writelane_b32 v21, s35, 3 +; SI-NEXT: v_writelane_b32 v21, s36, 4 +; SI-NEXT: v_writelane_b32 v21, s37, 5 +; SI-NEXT: v_writelane_b32 v21, s38, 6 +; SI-NEXT: v_writelane_b32 v21, s39, 7 +; SI-NEXT: v_writelane_b32 v21, s48, 8 +; SI-NEXT: v_writelane_b32 v21, s49, 9 +; SI-NEXT: v_writelane_b32 v21, s50, 10 +; SI-NEXT: v_writelane_b32 v21, s51, 11 +; SI-NEXT: v_writelane_b32 v21, s52, 12 +; SI-NEXT: v_writelane_b32 v21, s53, 13 +; SI-NEXT: v_writelane_b32 v21, s54, 14 +; SI-NEXT: v_writelane_b32 v21, s55, 15 +; SI-NEXT: v_writelane_b32 v21, s64, 16 +; SI-NEXT: v_writelane_b32 v21, s65, 17 +; SI-NEXT: v_writelane_b32 v21, s66, 18 +; SI-NEXT: v_writelane_b32 v21, s67, 19 +; SI-NEXT: v_writelane_b32 v21, s68, 20 +; SI-NEXT: v_writelane_b32 v21, s69, 21 +; SI-NEXT: v_mov_b32_e32 v20, s16 +; SI-NEXT: v_writelane_b32 v21, s70, 22 +; SI-NEXT: v_readfirstlane_b32 s48, v20 +; SI-NEXT: v_mov_b32_e32 v20, s17 +; SI-NEXT: v_writelane_b32 v21, s71, 23 +; SI-NEXT: v_readfirstlane_b32 s49, v20 +; SI-NEXT: v_mov_b32_e32 v20, s18 +; SI-NEXT: v_writelane_b32 v21, s80, 24 +; SI-NEXT: v_readfirstlane_b32 s50, v20 +; SI-NEXT: v_mov_b32_e32 v20, s19 +; SI-NEXT: v_writelane_b32 v21, s81, 25 +; SI-NEXT: v_readfirstlane_b32 s51, v20 +; SI-NEXT: v_mov_b32_e32 v20, s20 +; SI-NEXT: v_writelane_b32 v21, s82, 26 +; SI-NEXT: v_readfirstlane_b32 s52, v20 +; SI-NEXT: v_mov_b32_e32 v20, s21 +; SI-NEXT: v_writelane_b32 v21, s83, 27 +; SI-NEXT: v_readfirstlane_b32 s53, v20 +; SI-NEXT: v_mov_b32_e32 v20, s22 +; SI-NEXT: v_writelane_b32 v21, s84, 28 +; SI-NEXT: v_readfirstlane_b32 s54, v20 +; SI-NEXT: v_mov_b32_e32 v20, s23 +; SI-NEXT: v_writelane_b32 v21, s85, 29 +; SI-NEXT: v_readfirstlane_b32 s55, v20 +; SI-NEXT: v_mov_b32_e32 v20, s24 +; SI-NEXT: v_writelane_b32 v21, s86, 30 +; SI-NEXT: v_readfirstlane_b32 s64, v20 +; SI-NEXT: v_mov_b32_e32 v20, s25 +; SI-NEXT: v_writelane_b32 v21, s87, 31 +; SI-NEXT: v_readfirstlane_b32 s65, v20 +; SI-NEXT: v_mov_b32_e32 v20, s26 +; SI-NEXT: v_writelane_b32 v21, s96, 32 +; SI-NEXT: v_readfirstlane_b32 s66, v20 +; SI-NEXT: v_mov_b32_e32 v20, s27 +; SI-NEXT: v_writelane_b32 v21, s97, 33 +; SI-NEXT: v_readfirstlane_b32 s67, v20 +; SI-NEXT: v_mov_b32_e32 v20, s28 +; SI-NEXT: v_writelane_b32 v21, s98, 34 +; SI-NEXT: v_readfirstlane_b32 s68, v20 +; SI-NEXT: v_mov_b32_e32 v20, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_writelane_b32 v20, s99, 35 +; SI-NEXT: v_writelane_b32 v21, s99, 35 +; SI-NEXT: v_readfirstlane_b32 s69, v20 ; SI-NEXT: v_readfirstlane_b32 s70, v1 ; SI-NEXT: v_readfirstlane_b32 s71, v2 ; SI-NEXT: v_readfirstlane_b32 s80, v3 @@ -97450,107 +96551,107 @@ define inreg <64 x bfloat> @bitcast_v16i64_to_v64bf16_scalar(<16 x i64> inreg %a ; SI-NEXT: v_readfirstlane_b32 s8, v17 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s9, v18 -; SI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane +; SI-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane ; SI-NEXT: s_cbranch_scc0 .LBB61_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_and_b32 s4, s9, 0xffff0000 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v21, s4, 0 +; SI-NEXT: v_writelane_b32 v22, s4, 0 ; SI-NEXT: s_lshl_b32 s4, s9, 16 -; SI-NEXT: v_writelane_b32 v21, s4, 1 +; SI-NEXT: v_writelane_b32 v22, s4, 1 ; SI-NEXT: s_and_b32 s4, s8, 0xffff0000 -; SI-NEXT: v_writelane_b32 v21, s4, 2 +; SI-NEXT: v_writelane_b32 v22, s4, 2 ; SI-NEXT: s_lshl_b32 s4, s8, 16 -; SI-NEXT: v_writelane_b32 v21, s4, 3 +; SI-NEXT: v_writelane_b32 v22, s4, 3 ; SI-NEXT: s_and_b32 s11, s7, 0xffff0000 ; SI-NEXT: s_lshl_b32 s10, s7, 16 ; SI-NEXT: s_and_b32 s13, s6, 0xffff0000 ; SI-NEXT: s_lshl_b32 s12, s6, 16 ; SI-NEXT: s_and_b32 s15, s99, 0xffff0000 ; SI-NEXT: s_lshl_b32 s14, s99, 16 -; SI-NEXT: s_and_b32 s41, s98, 0xffff0000 -; SI-NEXT: s_lshl_b32 s40, s98, 16 -; SI-NEXT: s_and_b32 s43, s97, 0xffff0000 -; SI-NEXT: s_lshl_b32 s42, s97, 16 -; SI-NEXT: s_and_b32 s45, s96, 0xffff0000 -; SI-NEXT: s_lshl_b32 s44, s96, 16 -; SI-NEXT: s_and_b32 s47, s87, 0xffff0000 -; SI-NEXT: s_lshl_b32 s46, s87, 16 -; SI-NEXT: s_and_b32 s57, s86, 0xffff0000 -; SI-NEXT: s_lshl_b32 s56, s86, 16 -; SI-NEXT: s_and_b32 s59, s85, 0xffff0000 -; SI-NEXT: s_lshl_b32 s58, s85, 16 -; SI-NEXT: s_and_b32 s61, s84, 0xffff0000 -; SI-NEXT: s_lshl_b32 s60, s84, 16 -; SI-NEXT: s_and_b32 s63, s83, 0xffff0000 -; SI-NEXT: s_lshl_b32 s62, s83, 16 -; SI-NEXT: s_and_b32 s73, s82, 0xffff0000 -; SI-NEXT: s_lshl_b32 s72, s82, 16 -; SI-NEXT: s_and_b32 s75, s81, 0xffff0000 -; SI-NEXT: s_lshl_b32 s74, s81, 16 -; SI-NEXT: s_and_b32 s77, s80, 0xffff0000 -; SI-NEXT: s_lshl_b32 s76, s80, 16 -; SI-NEXT: s_and_b32 s79, s71, 0xffff0000 -; SI-NEXT: s_lshl_b32 s78, s71, 16 -; SI-NEXT: s_and_b32 s89, s70, 0xffff0000 -; SI-NEXT: s_lshl_b32 s88, s70, 16 -; SI-NEXT: s_and_b32 s91, s29, 0xffff0000 -; SI-NEXT: s_lshl_b32 s90, s29, 16 -; SI-NEXT: s_and_b32 s93, s28, 0xffff0000 -; SI-NEXT: s_lshl_b32 s92, s28, 16 -; SI-NEXT: s_and_b32 s95, s27, 0xffff0000 -; SI-NEXT: s_lshl_b32 s94, s27, 16 -; SI-NEXT: s_and_b32 s31, s26, 0xffff0000 -; SI-NEXT: s_lshl_b32 s30, s26, 16 -; SI-NEXT: s_and_b32 s35, s25, 0xffff0000 -; SI-NEXT: s_lshl_b32 s34, s25, 16 -; SI-NEXT: s_and_b32 s37, s24, 0xffff0000 -; SI-NEXT: s_lshl_b32 s36, s24, 16 -; SI-NEXT: s_and_b32 s39, s23, 0xffff0000 -; SI-NEXT: s_lshl_b32 s38, s23, 16 -; SI-NEXT: s_and_b32 s49, s22, 0xffff0000 -; SI-NEXT: s_lshl_b32 s48, s22, 16 -; SI-NEXT: s_and_b32 s51, s21, 0xffff0000 -; SI-NEXT: s_lshl_b32 s50, s21, 16 -; SI-NEXT: s_and_b32 s53, s20, 0xffff0000 -; SI-NEXT: s_lshl_b32 s52, s20, 16 -; SI-NEXT: s_and_b32 s55, s19, 0xffff0000 -; SI-NEXT: s_lshl_b32 s54, s19, 16 -; SI-NEXT: s_and_b32 s65, s18, 0xffff0000 -; SI-NEXT: s_lshl_b32 s64, s18, 16 -; SI-NEXT: s_and_b32 s67, s17, 0xffff0000 -; SI-NEXT: s_lshl_b32 s66, s17, 16 -; SI-NEXT: s_and_b32 s69, s16, 0xffff0000 -; SI-NEXT: s_lshl_b32 s68, s16, 16 +; SI-NEXT: s_and_b32 s17, s98, 0xffff0000 +; SI-NEXT: s_lshl_b32 s16, s98, 16 +; SI-NEXT: s_and_b32 s19, s97, 0xffff0000 +; SI-NEXT: s_lshl_b32 s18, s97, 16 +; SI-NEXT: s_and_b32 s21, s96, 0xffff0000 +; SI-NEXT: s_lshl_b32 s20, s96, 16 +; SI-NEXT: s_and_b32 s23, s87, 0xffff0000 +; SI-NEXT: s_lshl_b32 s22, s87, 16 +; SI-NEXT: s_and_b32 s25, s86, 0xffff0000 +; SI-NEXT: s_lshl_b32 s24, s86, 16 +; SI-NEXT: s_and_b32 s27, s85, 0xffff0000 +; SI-NEXT: s_lshl_b32 s26, s85, 16 +; SI-NEXT: s_and_b32 s29, s84, 0xffff0000 +; SI-NEXT: s_lshl_b32 s28, s84, 16 +; SI-NEXT: s_and_b32 s41, s83, 0xffff0000 +; SI-NEXT: s_lshl_b32 s40, s83, 16 +; SI-NEXT: s_and_b32 s43, s82, 0xffff0000 +; SI-NEXT: s_lshl_b32 s42, s82, 16 +; SI-NEXT: s_and_b32 s45, s81, 0xffff0000 +; SI-NEXT: s_lshl_b32 s44, s81, 16 +; SI-NEXT: s_and_b32 s47, s80, 0xffff0000 +; SI-NEXT: s_lshl_b32 s46, s80, 16 +; SI-NEXT: s_and_b32 s57, s71, 0xffff0000 +; SI-NEXT: s_lshl_b32 s56, s71, 16 +; SI-NEXT: s_and_b32 s59, s70, 0xffff0000 +; SI-NEXT: s_lshl_b32 s58, s70, 16 +; SI-NEXT: s_and_b32 s61, s69, 0xffff0000 +; SI-NEXT: s_lshl_b32 s60, s69, 16 +; SI-NEXT: s_and_b32 s63, s68, 0xffff0000 +; SI-NEXT: s_lshl_b32 s62, s68, 16 +; SI-NEXT: s_and_b32 s73, s67, 0xffff0000 +; SI-NEXT: s_lshl_b32 s72, s67, 16 +; SI-NEXT: s_and_b32 s75, s66, 0xffff0000 +; SI-NEXT: s_lshl_b32 s74, s66, 16 +; SI-NEXT: s_and_b32 s77, s65, 0xffff0000 +; SI-NEXT: s_lshl_b32 s76, s65, 16 +; SI-NEXT: s_and_b32 s79, s64, 0xffff0000 +; SI-NEXT: s_lshl_b32 s78, s64, 16 +; SI-NEXT: s_and_b32 s89, s55, 0xffff0000 +; SI-NEXT: s_lshl_b32 s88, s55, 16 +; SI-NEXT: s_and_b32 s91, s54, 0xffff0000 +; SI-NEXT: s_lshl_b32 s90, s54, 16 +; SI-NEXT: s_and_b32 s93, s53, 0xffff0000 +; SI-NEXT: s_lshl_b32 s92, s53, 16 +; SI-NEXT: s_and_b32 s95, s52, 0xffff0000 +; SI-NEXT: s_lshl_b32 s94, s52, 16 +; SI-NEXT: s_and_b32 s31, s51, 0xffff0000 +; SI-NEXT: s_lshl_b32 s30, s51, 16 +; SI-NEXT: s_and_b32 s35, s50, 0xffff0000 +; SI-NEXT: s_lshl_b32 s34, s50, 16 +; SI-NEXT: s_and_b32 s37, s49, 0xffff0000 +; SI-NEXT: s_lshl_b32 s36, s49, 16 +; SI-NEXT: s_and_b32 s39, s48, 0xffff0000 +; SI-NEXT: s_lshl_b32 s38, s48, 16 ; SI-NEXT: s_cbranch_execnz .LBB61_3 ; SI-NEXT: .LBB61_2: ; %cmp.true -; SI-NEXT: s_add_u32 s4, s16, 3 -; SI-NEXT: s_addc_u32 s5, s17, 0 -; SI-NEXT: s_add_u32 s16, s18, 3 -; SI-NEXT: s_addc_u32 s17, s19, 0 -; SI-NEXT: s_add_u32 s18, s20, 3 -; SI-NEXT: s_addc_u32 s19, s21, 0 -; SI-NEXT: s_add_u32 s20, s22, 3 -; SI-NEXT: s_addc_u32 s21, s23, 0 -; SI-NEXT: s_add_u32 s22, s24, 3 -; SI-NEXT: s_addc_u32 s23, s25, 0 -; SI-NEXT: s_add_u32 s24, s26, 3 -; SI-NEXT: s_addc_u32 s25, s27, 0 -; SI-NEXT: s_add_u32 s26, s28, 3 -; SI-NEXT: s_addc_u32 s27, s29, 0 -; SI-NEXT: s_add_u32 s28, s70, 3 -; SI-NEXT: s_addc_u32 s29, s71, 0 -; SI-NEXT: s_add_u32 s76, s80, 3 -; SI-NEXT: s_addc_u32 s74, s81, 0 -; SI-NEXT: s_add_u32 s72, s82, 3 -; SI-NEXT: s_addc_u32 s62, s83, 0 -; SI-NEXT: s_add_u32 s60, s84, 3 -; SI-NEXT: s_addc_u32 s58, s85, 0 -; SI-NEXT: s_add_u32 s56, s86, 3 -; SI-NEXT: s_addc_u32 s46, s87, 0 -; SI-NEXT: s_add_u32 s44, s96, 3 -; SI-NEXT: s_addc_u32 s42, s97, 0 -; SI-NEXT: s_add_u32 s40, s98, 3 +; SI-NEXT: s_add_u32 s4, s48, 3 +; SI-NEXT: s_addc_u32 s5, s49, 0 +; SI-NEXT: s_add_u32 vcc_lo, s50, 3 +; SI-NEXT: s_addc_u32 vcc_hi, s51, 0 +; SI-NEXT: s_add_u32 s94, s52, 3 +; SI-NEXT: s_addc_u32 s92, s53, 0 +; SI-NEXT: s_add_u32 s90, s54, 3 +; SI-NEXT: s_addc_u32 s88, s55, 0 +; SI-NEXT: s_add_u32 s78, s64, 3 +; SI-NEXT: s_addc_u32 s76, s65, 0 +; SI-NEXT: s_add_u32 s74, s66, 3 +; SI-NEXT: s_addc_u32 s72, s67, 0 +; SI-NEXT: s_add_u32 s62, s68, 3 +; SI-NEXT: s_addc_u32 s60, s69, 0 +; SI-NEXT: s_add_u32 s58, s70, 3 +; SI-NEXT: s_addc_u32 s56, s71, 0 +; SI-NEXT: s_add_u32 s46, s80, 3 +; SI-NEXT: s_addc_u32 s44, s81, 0 +; SI-NEXT: s_add_u32 s42, s82, 3 +; SI-NEXT: s_addc_u32 s40, s83, 0 +; SI-NEXT: s_add_u32 s28, s84, 3 +; SI-NEXT: s_addc_u32 s26, s85, 0 +; SI-NEXT: s_add_u32 s24, s86, 3 +; SI-NEXT: s_addc_u32 s22, s87, 0 +; SI-NEXT: s_add_u32 s20, s96, 3 +; SI-NEXT: s_addc_u32 s18, s97, 0 +; SI-NEXT: s_add_u32 s16, s98, 3 ; SI-NEXT: s_addc_u32 s14, s99, 0 ; SI-NEXT: s_add_u32 s6, s6, 3 ; SI-NEXT: s_addc_u32 s7, s7, 0 @@ -97558,11 +96659,11 @@ define inreg <64 x bfloat> @bitcast_v16i64_to_v64bf16_scalar(<16 x i64> inreg %a ; SI-NEXT: s_addc_u32 s9, s9, 0 ; SI-NEXT: s_and_b32 s10, s9, 0xffff0000 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v21, s10, 0 +; SI-NEXT: v_writelane_b32 v22, s10, 0 ; SI-NEXT: s_lshl_b32 s9, s9, 16 -; SI-NEXT: v_writelane_b32 v21, s9, 1 +; SI-NEXT: v_writelane_b32 v22, s9, 1 ; SI-NEXT: s_and_b32 s9, s8, 0xffff0000 -; SI-NEXT: v_writelane_b32 v21, s9, 2 +; SI-NEXT: v_writelane_b32 v22, s9, 2 ; SI-NEXT: s_lshl_b32 s8, s8, 16 ; SI-NEXT: s_and_b32 s11, s7, 0xffff0000 ; SI-NEXT: s_lshl_b32 s10, s7, 16 @@ -97570,6 +96671,20 @@ define inreg <64 x bfloat> @bitcast_v16i64_to_v64bf16_scalar(<16 x i64> inreg %a ; SI-NEXT: s_lshl_b32 s12, s6, 16 ; SI-NEXT: s_and_b32 s15, s14, 0xffff0000 ; SI-NEXT: s_lshl_b32 s14, s14, 16 +; SI-NEXT: s_and_b32 s17, s16, 0xffff0000 +; SI-NEXT: s_lshl_b32 s16, s16, 16 +; SI-NEXT: s_and_b32 s19, s18, 0xffff0000 +; SI-NEXT: s_lshl_b32 s18, s18, 16 +; SI-NEXT: s_and_b32 s21, s20, 0xffff0000 +; SI-NEXT: s_lshl_b32 s20, s20, 16 +; SI-NEXT: s_and_b32 s23, s22, 0xffff0000 +; SI-NEXT: s_lshl_b32 s22, s22, 16 +; SI-NEXT: s_and_b32 s25, s24, 0xffff0000 +; SI-NEXT: s_lshl_b32 s24, s24, 16 +; SI-NEXT: s_and_b32 s27, s26, 0xffff0000 +; SI-NEXT: s_lshl_b32 s26, s26, 16 +; SI-NEXT: s_and_b32 s29, s28, 0xffff0000 +; SI-NEXT: s_lshl_b32 s28, s28, 16 ; SI-NEXT: s_and_b32 s41, s40, 0xffff0000 ; SI-NEXT: s_lshl_b32 s40, s40, 16 ; SI-NEXT: s_and_b32 s43, s42, 0xffff0000 @@ -97592,325 +96707,297 @@ define inreg <64 x bfloat> @bitcast_v16i64_to_v64bf16_scalar(<16 x i64> inreg %a ; SI-NEXT: s_lshl_b32 s74, s74, 16 ; SI-NEXT: s_and_b32 s77, s76, 0xffff0000 ; SI-NEXT: s_lshl_b32 s76, s76, 16 -; SI-NEXT: s_and_b32 s79, s29, 0xffff0000 -; SI-NEXT: s_lshl_b32 s78, s29, 16 -; SI-NEXT: s_and_b32 s89, s28, 0xffff0000 -; SI-NEXT: s_lshl_b32 s88, s28, 16 -; SI-NEXT: s_and_b32 s91, s27, 0xffff0000 -; SI-NEXT: s_lshl_b32 s90, s27, 16 -; SI-NEXT: s_and_b32 s93, s26, 0xffff0000 -; SI-NEXT: s_lshl_b32 s92, s26, 16 -; SI-NEXT: s_and_b32 s95, s25, 0xffff0000 -; SI-NEXT: s_lshl_b32 s94, s25, 16 -; SI-NEXT: s_and_b32 s31, s24, 0xffff0000 -; SI-NEXT: s_lshl_b32 s30, s24, 16 -; SI-NEXT: s_and_b32 s35, s23, 0xffff0000 -; SI-NEXT: s_lshl_b32 s34, s23, 16 -; SI-NEXT: s_and_b32 s37, s22, 0xffff0000 -; SI-NEXT: s_lshl_b32 s36, s22, 16 -; SI-NEXT: s_and_b32 s39, s21, 0xffff0000 -; SI-NEXT: s_lshl_b32 s38, s21, 16 -; SI-NEXT: s_and_b32 s49, s20, 0xffff0000 -; SI-NEXT: s_lshl_b32 s48, s20, 16 -; SI-NEXT: s_and_b32 s51, s19, 0xffff0000 -; SI-NEXT: s_lshl_b32 s50, s19, 16 -; SI-NEXT: s_and_b32 s53, s18, 0xffff0000 -; SI-NEXT: s_lshl_b32 s52, s18, 16 -; SI-NEXT: s_and_b32 s55, s17, 0xffff0000 -; SI-NEXT: s_lshl_b32 s54, s17, 16 -; SI-NEXT: s_and_b32 s65, s16, 0xffff0000 -; SI-NEXT: s_lshl_b32 s64, s16, 16 -; SI-NEXT: s_and_b32 s67, s5, 0xffff0000 -; SI-NEXT: s_lshl_b32 s66, s5, 16 -; SI-NEXT: s_and_b32 s69, s4, 0xffff0000 -; SI-NEXT: s_lshl_b32 s68, s4, 16 -; SI-NEXT: v_writelane_b32 v21, s8, 3 +; SI-NEXT: s_and_b32 s79, s78, 0xffff0000 +; SI-NEXT: s_lshl_b32 s78, s78, 16 +; SI-NEXT: s_and_b32 s89, s88, 0xffff0000 +; SI-NEXT: s_lshl_b32 s88, s88, 16 +; SI-NEXT: s_and_b32 s91, s90, 0xffff0000 +; SI-NEXT: s_lshl_b32 s90, s90, 16 +; SI-NEXT: s_and_b32 s93, s92, 0xffff0000 +; SI-NEXT: s_lshl_b32 s92, s92, 16 +; SI-NEXT: s_and_b32 s95, s94, 0xffff0000 +; SI-NEXT: s_lshl_b32 s94, s94, 16 +; SI-NEXT: s_and_b32 s31, vcc_hi, 0xffff0000 +; SI-NEXT: s_lshl_b32 s30, vcc_hi, 16 +; SI-NEXT: s_and_b32 s35, vcc_lo, 0xffff0000 +; SI-NEXT: s_lshl_b32 s34, vcc_lo, 16 +; SI-NEXT: s_and_b32 s37, s5, 0xffff0000 +; SI-NEXT: s_lshl_b32 s36, s5, 16 +; SI-NEXT: s_and_b32 s39, s4, 0xffff0000 +; SI-NEXT: s_lshl_b32 s38, s4, 16 +; SI-NEXT: v_writelane_b32 v22, s8, 3 ; SI-NEXT: .LBB61_3: ; %end -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s69 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s68 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s39 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s38 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_readlane_b32 s4, v22, 2 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s67 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s66 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s37 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s36 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s65 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s64 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s35 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s34 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s55 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s54 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s31 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s30 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s53 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s52 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s95 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s94 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s51 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s50 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s93 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s92 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s49 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s48 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s91 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s90 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s39 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s38 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s89 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s88 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s37 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s36 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s79 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s78 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s35 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s34 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s77 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s76 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s31 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s30 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s75 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s74 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s95 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s94 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s73 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s72 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s93 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s92 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s63 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s62 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s91 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s90 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s61 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s60 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s89 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s88 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s59 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s58 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s79 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s78 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s57 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s56 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s77 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s76 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s47 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s46 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 64, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s75 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s74 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s45 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s44 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s73 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s72 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s43 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s42 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x48, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s63 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s62 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s41 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s40 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s61 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s60 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s29 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s28 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x50, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s59 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s58 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s27 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s26 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s57 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s56 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s25 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s24 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x58, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s47 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s46 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s23 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s22 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s45 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s44 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s21 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s20 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x60, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s43 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s42 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s19 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s18 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x64, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s41 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s40 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s17 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s16 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x68, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s15 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s14 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s14 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s13 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s12 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s12 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x70, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s11 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s10 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s10 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0 -; SI-NEXT: v_readlane_b32 s4, v21, 2 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4 -; SI-NEXT: v_readlane_b32 s4, v21, 3 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_readlane_b32 s4, v22, 3 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0 -; SI-NEXT: v_readlane_b32 s4, v21, 0 +; SI-NEXT: v_readlane_b32 s4, v22, 0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4 -; SI-NEXT: v_readlane_b32 s4, v21, 1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_readlane_b32 s4, v22, 1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s99, v20, 35 -; SI-NEXT: v_readlane_b32 s98, v20, 34 -; SI-NEXT: v_readlane_b32 s97, v20, 33 -; SI-NEXT: v_readlane_b32 s96, v20, 32 -; SI-NEXT: v_readlane_b32 s87, v20, 31 -; SI-NEXT: v_readlane_b32 s86, v20, 30 -; SI-NEXT: v_readlane_b32 s85, v20, 29 -; SI-NEXT: v_readlane_b32 s84, v20, 28 -; SI-NEXT: v_readlane_b32 s83, v20, 27 -; SI-NEXT: v_readlane_b32 s82, v20, 26 -; SI-NEXT: v_readlane_b32 s81, v20, 25 -; SI-NEXT: v_readlane_b32 s80, v20, 24 -; SI-NEXT: v_readlane_b32 s71, v20, 23 -; SI-NEXT: v_readlane_b32 s70, v20, 22 -; SI-NEXT: v_readlane_b32 s69, v20, 21 -; SI-NEXT: v_readlane_b32 s68, v20, 20 -; SI-NEXT: v_readlane_b32 s67, v20, 19 -; SI-NEXT: v_readlane_b32 s66, v20, 18 -; SI-NEXT: v_readlane_b32 s65, v20, 17 -; SI-NEXT: v_readlane_b32 s64, v20, 16 -; SI-NEXT: v_readlane_b32 s55, v20, 15 -; SI-NEXT: v_readlane_b32 s54, v20, 14 -; SI-NEXT: v_readlane_b32 s53, v20, 13 -; SI-NEXT: v_readlane_b32 s52, v20, 12 -; SI-NEXT: v_readlane_b32 s51, v20, 11 -; SI-NEXT: v_readlane_b32 s50, v20, 10 -; SI-NEXT: v_readlane_b32 s49, v20, 9 -; SI-NEXT: v_readlane_b32 s48, v20, 8 -; SI-NEXT: v_readlane_b32 s39, v20, 7 -; SI-NEXT: v_readlane_b32 s38, v20, 6 -; SI-NEXT: v_readlane_b32 s37, v20, 5 -; SI-NEXT: v_readlane_b32 s36, v20, 4 -; SI-NEXT: v_readlane_b32 s35, v20, 3 -; SI-NEXT: v_readlane_b32 s34, v20, 2 -; SI-NEXT: v_readlane_b32 s31, v20, 1 -; SI-NEXT: v_readlane_b32 s30, v20, 0 +; SI-NEXT: v_readlane_b32 s99, v21, 35 +; SI-NEXT: v_readlane_b32 s98, v21, 34 +; SI-NEXT: v_readlane_b32 s97, v21, 33 +; SI-NEXT: v_readlane_b32 s96, v21, 32 +; SI-NEXT: v_readlane_b32 s87, v21, 31 +; SI-NEXT: v_readlane_b32 s86, v21, 30 +; SI-NEXT: v_readlane_b32 s85, v21, 29 +; SI-NEXT: v_readlane_b32 s84, v21, 28 +; SI-NEXT: v_readlane_b32 s83, v21, 27 +; SI-NEXT: v_readlane_b32 s82, v21, 26 +; SI-NEXT: v_readlane_b32 s81, v21, 25 +; SI-NEXT: v_readlane_b32 s80, v21, 24 +; SI-NEXT: v_readlane_b32 s71, v21, 23 +; SI-NEXT: v_readlane_b32 s70, v21, 22 +; SI-NEXT: v_readlane_b32 s69, v21, 21 +; SI-NEXT: v_readlane_b32 s68, v21, 20 +; SI-NEXT: v_readlane_b32 s67, v21, 19 +; SI-NEXT: v_readlane_b32 s66, v21, 18 +; SI-NEXT: v_readlane_b32 s65, v21, 17 +; SI-NEXT: v_readlane_b32 s64, v21, 16 +; SI-NEXT: v_readlane_b32 s55, v21, 15 +; SI-NEXT: v_readlane_b32 s54, v21, 14 +; SI-NEXT: v_readlane_b32 s53, v21, 13 +; SI-NEXT: v_readlane_b32 s52, v21, 12 +; SI-NEXT: v_readlane_b32 s51, v21, 11 +; SI-NEXT: v_readlane_b32 s50, v21, 10 +; SI-NEXT: v_readlane_b32 s49, v21, 9 +; SI-NEXT: v_readlane_b32 s48, v21, 8 +; SI-NEXT: v_readlane_b32 s39, v21, 7 +; SI-NEXT: v_readlane_b32 s38, v21, 6 +; SI-NEXT: v_readlane_b32 s37, v21, 5 +; SI-NEXT: v_readlane_b32 s36, v21, 4 +; SI-NEXT: v_readlane_b32 s35, v21, 3 +; SI-NEXT: v_readlane_b32 s34, v21, 2 +; SI-NEXT: v_readlane_b32 s31, v21, 1 +; SI-NEXT: v_readlane_b32 s30, v21, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] ; SI-NEXT: .LBB61_4: ; SI-NEXT: ; implicit-def: $sgpr4 ; SI-NEXT: ; kill: killed $sgpr4 -; SI-NEXT: ; implicit-def: $sgpr68 -; SI-NEXT: ; implicit-def: $sgpr69 -; SI-NEXT: ; implicit-def: $sgpr66 -; SI-NEXT: ; implicit-def: $sgpr67 -; SI-NEXT: ; implicit-def: $sgpr64 -; SI-NEXT: ; implicit-def: $sgpr65 -; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; implicit-def: $sgpr55 -; SI-NEXT: ; implicit-def: $sgpr52 -; SI-NEXT: ; implicit-def: $sgpr53 -; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; implicit-def: $sgpr51 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr49 ; SI-NEXT: ; implicit-def: $sgpr38 ; SI-NEXT: ; implicit-def: $sgpr39 ; SI-NEXT: ; implicit-def: $sgpr36 @@ -97951,6 +97038,20 @@ define inreg <64 x bfloat> @bitcast_v16i64_to_v64bf16_scalar(<16 x i64> inreg %a ; SI-NEXT: ; implicit-def: $sgpr43 ; SI-NEXT: ; implicit-def: $sgpr40 ; SI-NEXT: ; implicit-def: $sgpr41 +; SI-NEXT: ; implicit-def: $sgpr28 +; SI-NEXT: ; implicit-def: $sgpr29 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr27 +; SI-NEXT: ; implicit-def: $sgpr24 +; SI-NEXT: ; implicit-def: $sgpr25 +; SI-NEXT: ; implicit-def: $sgpr22 +; SI-NEXT: ; implicit-def: $sgpr23 +; SI-NEXT: ; implicit-def: $sgpr20 +; SI-NEXT: ; implicit-def: $sgpr21 +; SI-NEXT: ; implicit-def: $sgpr18 +; SI-NEXT: ; implicit-def: $sgpr19 +; SI-NEXT: ; implicit-def: $sgpr16 +; SI-NEXT: ; implicit-def: $sgpr17 ; SI-NEXT: ; implicit-def: $sgpr14 ; SI-NEXT: ; implicit-def: $sgpr15 ; SI-NEXT: ; implicit-def: $sgpr12 @@ -101207,562 +100308,737 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v52, v30 -; SI-NEXT: v_mov_b32_e32 v53, v28 -; SI-NEXT: v_mov_b32_e32 v40, v12 -; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:76 -; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 -; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:8 -; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:4 -; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:16 -; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:12 -; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:24 -; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:20 -; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:32 -; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:28 -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:40 -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:36 -; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:44 +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76 +; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 +; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:16 +; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:24 +; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:32 +; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:40 +; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48 +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:56 +; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:64 +; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:72 +; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:4 +; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:12 +; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:20 +; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28 +; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:36 +; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:44 +; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:52 +; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:60 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:68 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:56 -; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:52 -; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:64 -; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:60 -; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72 -; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:68 -; SI-NEXT: v_mov_b32_e32 v55, v14 -; SI-NEXT: v_mul_f32_e32 v14, 1.0, v0 -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v6 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v63, 1.0, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v8 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v7 +; SI-NEXT: v_mov_b32_e32 v43, v21 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v10 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11 +; SI-NEXT: v_mov_b32_e32 v54, v29 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v43 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v16 -; SI-NEXT: v_mul_f32_e32 v58, 1.0, v1 -; SI-NEXT: v_mul_f32_e32 v56, 1.0, v3 -; SI-NEXT: v_mul_f32_e32 v54, 1.0, v2 -; SI-NEXT: v_mul_f32_e32 v44, 1.0, v5 -; SI-NEXT: v_mul_f32_e32 v46, 1.0, v4 -; SI-NEXT: v_mul_f32_e32 v61, 1.0, v7 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v54 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v41, v23 +; SI-NEXT: v_mov_b32_e32 v29, v20 +; SI-NEXT: v_mul_f32_e32 v57, 1.0, v3 ; SI-NEXT: v_mul_f32_e32 v59, 1.0, v9 -; SI-NEXT: v_mul_f32_e32 v57, 1.0, v11 -; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13 -; SI-NEXT: v_mul_f32_e32 v47, 1.0, v40 -; SI-NEXT: v_mul_f32_e32 v45, 1.0, v15 -; SI-NEXT: v_mul_f32_e32 v15, 1.0, v17 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; SI-NEXT: v_mul_f32_e32 v16, 1.0, v19 -; SI-NEXT: v_mul_f32_e32 v43, 1.0, v18 -; SI-NEXT: v_mul_f32_e32 v17, 1.0, v21 -; SI-NEXT: v_mul_f32_e32 v41, 1.0, v20 -; SI-NEXT: v_mul_f32_e32 v18, 1.0, v23 -; SI-NEXT: v_mul_f32_e32 v40, 1.0, v22 -; SI-NEXT: v_mul_f32_e32 v19, 1.0, v25 -; SI-NEXT: v_mul_f32_e32 v55, 1.0, v24 -; SI-NEXT: v_mul_f32_e32 v20, 1.0, v27 -; SI-NEXT: v_mul_f32_e32 v21, 1.0, v29 -; SI-NEXT: v_mul_f32_e32 v53, 1.0, v53 -; SI-NEXT: v_mul_f32_e32 v52, 1.0, v52 +; SI-NEXT: v_mul_f32_e32 v61, 1.0, v13 +; SI-NEXT: v_mul_f32_e32 v23, 1.0, v15 +; SI-NEXT: v_mul_f32_e32 v44, 1.0, v17 +; SI-NEXT: v_mul_f32_e32 v21, 1.0, v19 +; SI-NEXT: v_mul_f32_e32 v20, 1.0, v41 +; SI-NEXT: v_mul_f32_e32 v17, 1.0, v25 +; SI-NEXT: v_mul_f32_e32 v15, 1.0, v27 +; SI-NEXT: v_mul_f32_e64 v25, 1.0, s17 +; SI-NEXT: v_mul_f32_e64 v3, 1.0, s21 +; SI-NEXT: v_mul_f32_e64 v5, 1.0, s25 +; SI-NEXT: v_mul_f32_e64 v7, 1.0, s29 +; SI-NEXT: v_mul_f32_e32 v9, 1.0, v2 +; SI-NEXT: v_mul_f32_e32 v54, 1.0, v4 +; SI-NEXT: v_mul_f32_e32 v11, 1.0, v6 +; SI-NEXT: v_mul_f32_e32 v56, 1.0, v8 +; SI-NEXT: v_mul_f32_e32 v13, 1.0, v10 +; SI-NEXT: v_mul_f32_e32 v58, 1.0, v12 +; SI-NEXT: v_mul_f32_e32 v60, 1.0, v14 +; SI-NEXT: v_mul_f32_e32 v62, 1.0, v16 +; SI-NEXT: v_mul_f32_e32 v47, 1.0, v22 +; SI-NEXT: v_mul_f32_e32 v22, 1.0, v28 +; SI-NEXT: v_mul_f32_e64 v19, 1.0, s16 +; SI-NEXT: v_mul_f32_e64 v14, 1.0, s20 +; SI-NEXT: v_mul_f32_e64 v16, 1.0, s22 +; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v32 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v33 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v34 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v35 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v37 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v38 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v39 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v48 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v49 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v0, 1.0, s17 -; SI-NEXT: v_mul_f32_e64 v3, 1.0, s16 ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s19 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s18 -; SI-NEXT: v_mul_f32_e64 v4, 1.0, s21 -; SI-NEXT: v_mul_f32_e64 v8, 1.0, s20 -; SI-NEXT: v_mul_f32_e64 v10, 1.0, s23 -; SI-NEXT: v_mul_f32_e64 v9, 1.0, s22 -; SI-NEXT: v_mul_f32_e64 v5, 1.0, s27 -; SI-NEXT: v_mul_f32_e64 v11, 1.0, s26 -; SI-NEXT: v_mul_f32_e64 v6, 1.0, s29 -; SI-NEXT: v_mul_f32_e64 v7, 1.0, s28 +; SI-NEXT: v_mul_f32_e32 v39, 1.0, v0 ; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v48 -; SI-NEXT: v_mul_f32_e32 v48, 1.0, v26 -; SI-NEXT: v_mul_f32_e32 v22, 1.0, v51 +; SI-NEXT: v_mul_f32_e32 v0, 1.0, v45 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill ; SI-NEXT: s_and_b64 s[4:5], vcc, exec -; SI-NEXT: v_mul_f32_e32 v23, 1.0, v37 -; SI-NEXT: v_mul_f32_e32 v51, 1.0, v50 -; SI-NEXT: v_mul_f32_e32 v24, 1.0, v38 -; SI-NEXT: v_mul_f32_e32 v50, 1.0, v49 -; SI-NEXT: v_mul_f32_e32 v25, 1.0, v39 -; SI-NEXT: v_mul_f32_e32 v49, 1.0, v30 -; SI-NEXT: v_mul_f32_e32 v26, 1.0, v28 -; SI-NEXT: v_mul_f32_e32 v39, 1.0, v12 -; SI-NEXT: v_mul_f32_e32 v27, 1.0, v31 -; SI-NEXT: s_waitcnt vmcnt(13) -; SI-NEXT: v_mul_f32_e32 v38, 1.0, v60 -; SI-NEXT: s_waitcnt vmcnt(12) +; SI-NEXT: v_mul_f32_e64 v35, 1.0, s23 +; SI-NEXT: v_mul_f32_e64 v33, 1.0, s27 +; SI-NEXT: v_mul_f32_e32 v32, 1.0, v18 +; SI-NEXT: v_mul_f32_e32 v34, 1.0, v29 +; SI-NEXT: v_mul_f32_e32 v36, 1.0, v24 +; SI-NEXT: v_mul_f32_e32 v38, 1.0, v26 +; SI-NEXT: v_mul_f32_e32 v31, 1.0, v30 +; SI-NEXT: v_mul_f32_e32 v24, 1.0, v51 +; SI-NEXT: v_mul_f32_e32 v41, 1.0, v53 +; SI-NEXT: v_mul_f32_e32 v26, 1.0, v55 +; SI-NEXT: v_mul_f32_e32 v43, 1.0, v40 ; SI-NEXT: v_mul_f32_e32 v28, 1.0, v42 -; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_mul_f32_e32 v37, 1.0, v62 -; SI-NEXT: s_waitcnt vmcnt(10) -; SI-NEXT: v_mul_f32_e32 v29, 1.0, v63 -; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_mul_f32_e32 v32, 1.0, v32 -; SI-NEXT: s_waitcnt vmcnt(8) -; SI-NEXT: v_mul_f32_e32 v30, 1.0, v33 -; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_mul_f32_e32 v31, 1.0, v34 -; SI-NEXT: s_waitcnt vmcnt(6) -; SI-NEXT: v_mul_f32_e32 v33, 1.0, v35 -; SI-NEXT: s_waitcnt vmcnt(5) -; SI-NEXT: v_mul_f32_e32 v42, 1.0, v36 -; SI-NEXT: v_mul_f32_e64 v12, 1.0, s25 -; SI-NEXT: v_mul_f32_e64 v34, 1.0, s24 -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v51, 1.0, v50 +; SI-NEXT: v_mul_f32_e32 v53, 1.0, v52 +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_mul_f32_e32 v0, 1.0, v46 +; SI-NEXT: v_mul_f32_e64 v48, 1.0, s18 +; SI-NEXT: v_mul_f32_e64 v18, 1.0, s24 +; SI-NEXT: v_mul_f32_e64 v29, 1.0, s26 +; SI-NEXT: v_mul_f32_e64 v45, 1.0, s28 +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB63_2 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; SI-NEXT: s_waitcnt expcnt(6) -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_alignbit_b32 v0, v0, v3, 16 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4 -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v10 -; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; SI-NEXT: v_alignbit_b32 v2, v2, v8, 16 -; SI-NEXT: v_alignbit_b32 v3, v3, v9, 16 -; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16 -; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v58 -; SI-NEXT: s_waitcnt expcnt(5) -; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v56 -; SI-NEXT: s_waitcnt expcnt(4) -; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v44 -; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; SI-NEXT: v_alignbit_b32 v5, v5, v11, 16 -; SI-NEXT: v_alignbit_b32 v7, v7, v14, 16 -; SI-NEXT: v_alignbit_b32 v8, v8, v54, 16 -; SI-NEXT: v_alignbit_b32 v9, v9, v46, 16 -; SI-NEXT: v_mov_b32_e32 v62, v61 -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v61 -; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; SI-NEXT: v_mov_b32_e32 v60, v59 -; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v59 -; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; SI-NEXT: v_mov_b32_e32 v56, v47 -; SI-NEXT: v_alignbit_b32 v13, v13, v47, 16 -; SI-NEXT: v_mov_b32_e32 v46, v45 -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v45 -; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v12 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v57 -; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22 -; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23 -; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 -; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26 -; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28 -; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29 -; SI-NEXT: v_alignbit_b32 v30, v30, v31, 16 -; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v33 -; SI-NEXT: v_alignbit_b32 v4, v4, v34, 16 -; SI-NEXT: v_mov_b32_e32 v63, v44 -; SI-NEXT: v_mov_b32_e32 v58, v57 -; SI-NEXT: v_mov_b32_e32 v44, v43 -; SI-NEXT: v_alignbit_b32 v16, v16, v43, 16 -; SI-NEXT: v_mov_b32_e32 v43, v41 -; SI-NEXT: v_alignbit_b32 v17, v17, v41, 16 -; SI-NEXT: v_alignbit_b32 v18, v18, v40, 16 -; SI-NEXT: v_mov_b32_e32 v40, v55 -; SI-NEXT: v_alignbit_b32 v19, v19, v55, 16 -; SI-NEXT: v_alignbit_b32 v20, v20, v48, 16 -; SI-NEXT: v_mov_b32_e32 v48, v53 -; SI-NEXT: v_alignbit_b32 v21, v21, v53, 16 -; SI-NEXT: v_alignbit_b32 v22, v22, v52, 16 -; SI-NEXT: v_mov_b32_e32 v52, v51 -; SI-NEXT: v_alignbit_b32 v23, v23, v51, 16 -; SI-NEXT: v_alignbit_b32 v24, v24, v50, 16 -; SI-NEXT: v_mov_b32_e32 v50, v49 -; SI-NEXT: v_alignbit_b32 v25, v25, v49, 16 -; SI-NEXT: v_mov_b32_e32 v36, v39 -; SI-NEXT: v_alignbit_b32 v26, v26, v39, 16 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v34, v38 -; SI-NEXT: v_alignbit_b32 v27, v27, v38, 16 -; SI-NEXT: v_mov_b32_e32 v35, v37 -; SI-NEXT: v_alignbit_b32 v28, v28, v37, 16 -; SI-NEXT: v_mov_b32_e32 v37, v32 -; SI-NEXT: v_alignbit_b32 v29, v29, v32, 16 -; SI-NEXT: v_alignbit_b32 v31, v31, v42, 16 +; SI-NEXT: v_mov_b32_e32 v0, v19 +; SI-NEXT: v_mov_b32_e32 v37, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v25 +; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v33 +; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v7 +; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v63 +; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v57 +; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v61 +; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v23 +; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v44 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v21 +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 s[4:5], 0 -; SI-NEXT: v_mov_b32_e32 v32, v33 -; SI-NEXT: v_mov_b32_e32 v33, v42 -; SI-NEXT: s_waitcnt vmcnt(4) -; SI-NEXT: v_alignbit_b32 v10, v10, v61, 16 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_alignbit_b32 v12, v12, v54, 16 -; SI-NEXT: v_mov_b32_e32 v41, v61 +; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v1 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[0:1], v[19:20], 16 +; SI-NEXT: v_mov_b32_e32 v1, v48 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[1:2], v[48:49], 16 +; SI-NEXT: v_mov_b32_e32 v2, v14 +; SI-NEXT: v_mov_b32_e32 v49, v15 +; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v3 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[2:3], v[14:15], 16 +; SI-NEXT: v_mov_b32_e32 v3, v16 +; SI-NEXT: v_mov_b32_e32 v20, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v35 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[3:4], v[16:17], 16 +; SI-NEXT: v_mov_b32_e32 v4, v18 +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v5 +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[4:5], v[18:19], 16 +; SI-NEXT: v_mov_b32_e32 v5, v29 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[5:6], v[29:30], 16 +; SI-NEXT: v_mov_b32_e32 v6, v45 +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[6:7], v[45:46], 16 +; SI-NEXT: v_mov_b32_e32 v7, v39 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[7:8], v[39:40], 16 +; SI-NEXT: v_mov_b32_e32 v8, v9 +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v37 +; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v20 +; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v49 +; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[8:9], v[9:10], 16 +; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v9 +; SI-NEXT: v_mov_b32_e32 v9, v54 +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[9:10], v[54:55], 16 +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v55, v13 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v10 +; SI-NEXT: v_mov_b32_e32 v10, v11 +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[10:11], v[11:12], 16 +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v11 +; SI-NEXT: v_mov_b32_e32 v11, v56 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[11:12], v[56:57], 16 +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v56, v44 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v12 +; SI-NEXT: v_lshr_b64 v[12:13], v[13:14], 16 +; SI-NEXT: v_mov_b32_e32 v13, v58 +; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[13:14], v[58:59], 16 +; SI-NEXT: v_mov_b32_e32 v14, v60 +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[14:15], v[60:61], 16 +; SI-NEXT: v_mov_b32_e32 v15, v62 +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[15:16], v[62:63], 16 +; SI-NEXT: v_mov_b32_e32 v16, v32 +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[16:17], v[32:33], 16 +; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v27 +; SI-NEXT: v_mov_b32_e32 v33, v34 +; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_alignbit_b32 v11, v11, v59, 16 -; SI-NEXT: v_mov_b32_e32 v55, v59 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_alignbit_b32 v14, v14, v45, 16 +; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v17 +; SI-NEXT: v_mov_b32_e32 v40, v17 +; SI-NEXT: v_lshr_b64 v[17:18], v[34:35], 16 +; SI-NEXT: v_lshr_b64 v[18:19], v[47:48], 16 +; SI-NEXT: v_lshr_b64 v[19:20], v[36:37], 16 +; SI-NEXT: v_mov_b32_e32 v20, v38 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[20:21], v[38:39], 16 +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; SI-NEXT: v_mov_b32_e32 v34, v47 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v21 +; SI-NEXT: v_mov_b32_e32 v21, v22 +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[21:22], v[22:23], 16 +; SI-NEXT: v_mov_b32_e32 v22, v31 +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[22:23], v[31:32], 16 +; SI-NEXT: v_mov_b32_e32 v23, v24 +; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[23:24], v[24:25], 16 +; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v52 +; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v30 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v24 +; SI-NEXT: v_mov_b32_e32 v24, v41 +; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[24:25], v[41:42], 16 +; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v41, v26 +; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v50 +; SI-NEXT: v_mov_b32_e32 v42, v51 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v25 +; SI-NEXT: v_lshr_b64 v[25:26], v[26:27], 16 +; SI-NEXT: v_mov_b32_e32 v26, v43 +; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[26:27], v[43:44], 16 +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v43, v28 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v27 +; SI-NEXT: v_lshr_b64 v[27:28], v[28:29], 16 +; SI-NEXT: v_lshr_b64 v[28:29], v[51:52], 16 +; SI-NEXT: v_lshr_b64 v[29:30], v[53:54], 16 +; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v52, v53 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v30 +; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshr_b64 v[30:31], v[31:32], 16 +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_alignbit_b32 v15, v15, v47, 16 -; SI-NEXT: v_mov_b32_e32 v51, v47 -; SI-NEXT: v_mov_b32_e32 v53, v45 +; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v57 +; SI-NEXT: v_mov_b32_e32 v53, v31 +; SI-NEXT: v_lshr_b64 v[31:32], v[31:32], 16 ; SI-NEXT: s_branch .LBB63_3 ; SI-NEXT: .LBB63_2: -; SI-NEXT: v_mov_b32_e32 v63, v44 -; SI-NEXT: v_mov_b32_e32 v44, v43 -; SI-NEXT: v_mov_b32_e32 v43, v41 -; SI-NEXT: v_mov_b32_e32 v40, v55 -; SI-NEXT: v_mov_b32_e32 v48, v53 -; SI-NEXT: v_mov_b32_e32 v52, v51 -; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload -; SI-NEXT: v_mov_b32_e32 v62, v61 -; SI-NEXT: v_mov_b32_e32 v60, v59 -; SI-NEXT: v_mov_b32_e32 v58, v57 -; SI-NEXT: v_mov_b32_e32 v56, v47 -; SI-NEXT: v_mov_b32_e32 v46, v45 -; SI-NEXT: v_mov_b32_e32 v50, v49 -; SI-NEXT: v_mov_b32_e32 v36, v39 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v34, v38 -; SI-NEXT: v_mov_b32_e32 v35, v37 -; SI-NEXT: v_mov_b32_e32 v37, v32 +; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill +; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v56, v44 +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v55, v13 +; SI-NEXT: s_waitcnt expcnt(2) +; SI-NEXT: v_mov_b32_e32 v33, v34 +; SI-NEXT: v_mov_b32_e32 v34, v47 +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_mov_b32_e32 v43, v28 +; SI-NEXT: v_mov_b32_e32 v52, v53 +; SI-NEXT: v_mov_b32_e32 v53, v0 ; SI-NEXT: s_mov_b64 s[4:5], -1 -; SI-NEXT: v_mov_b32_e32 v32, v33 -; SI-NEXT: v_mov_b32_e32 v33, v42 +; SI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_mov_b32_e32 v41, v26 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v42, v51 ; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; SI-NEXT: .LBB63_3: ; %Flow -; SI-NEXT: v_mov_b32_e32 v38, v50 -; SI-NEXT: v_mov_b32_e32 v39, v52 -; SI-NEXT: v_mov_b32_e32 v49, v40 -; SI-NEXT: v_mov_b32_e32 v50, v43 -; SI-NEXT: v_mov_b32_e32 v43, v44 -; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v37, v34 +; SI-NEXT: v_mov_b32_e32 v34, v33 +; SI-NEXT: v_mov_b32_e32 v35, v56 +; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: v_mov_b32_e32 v32, v40 +; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload ; SI-NEXT: s_andn2_b64 vcc, exec, s[4:5] +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_mov_b32_e32 v33, v38 +; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v51, v46 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v54, v46 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v44, v46 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v45, v56 +; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v47, v56 +; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v58, v60 +; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload ; SI-NEXT: s_cbranch_vccnz .LBB63_5 ; SI-NEXT: ; %bb.4: ; %cmp.true -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v44 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v57 +; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v61 +; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v49 ; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8 ; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v40 +; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v39 ; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 ; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v63 -; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 -; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v62 -; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 -; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v60 +; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v59 ; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 ; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v58 -; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 -; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v46 -; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 -; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32 +; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v40 +; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 +; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v35 +; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 +; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v32 +; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 +; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v53 ; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32 -; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 ; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 +; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16 -; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 -; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16 +; SI-NEXT: v_lshr_b64 v[1:2], v[2:3], 16 +; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v60 +; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 ; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 ; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 -; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; SI-NEXT: s_waitcnt vmcnt(13) ; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 ; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 ; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 -; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; SI-NEXT: s_waitcnt vmcnt(12) +; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 +; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; SI-NEXT: s_waitcnt vmcnt(8) +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; SI-NEXT: s_waitcnt vmcnt(7) +; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15 ; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 ; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 ; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; SI-NEXT: s_waitcnt vmcnt(13) ; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 ; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 ; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; SI-NEXT: s_waitcnt vmcnt(12) -; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 -; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 -; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22 -; SI-NEXT: s_waitcnt vmcnt(10) -; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 -; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23 -; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 -; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; SI-NEXT: s_waitcnt vmcnt(8) -; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 -; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 -; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26 -; SI-NEXT: s_waitcnt vmcnt(6) -; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 -; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; SI-NEXT: s_waitcnt vmcnt(5) +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 +; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 +; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 ; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 ; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28 -; SI-NEXT: s_waitcnt vmcnt(4) +; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 ; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 ; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 +; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26 ; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 -; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 -; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 -; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16 -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v58 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16 +; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v56 ; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 -; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16 -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16 +; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v47 ; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 -; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16 -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16 +; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v45 ; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 -; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16 -; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v45 +; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16 +; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v46 ; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 -; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16 -; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v42 +; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16 +; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v44 ; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8 -; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16 -; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v52 +; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16 +; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v54 ; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 -; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16 -; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v41 +; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16 +; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v51 ; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 -; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16 -; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v55 +; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16 +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v50 ; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 -; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16 -; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v54 +; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16 +; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v55 ; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 -; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16 -; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v56 +; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16 +; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v48 ; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 -; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16 -; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v53 +; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16 +; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v38 ; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 -; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16 -; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v51 +; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16 +; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v33 ; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 -; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16 -; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v43 +; SI-NEXT: v_lshr_b64 v[15:16], v[15:16], 16 +; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 +; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 ; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; SI-NEXT: v_alignbit_b32 v16, v17, v16, 16 -; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v50 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 ; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 -; SI-NEXT: v_alignbit_b32 v17, v18, v17, 16 -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; SI-NEXT: v_lshr_b64 v[16:17], v[16:17], 16 +; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v34 +; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 +; SI-NEXT: v_lshr_b64 v[17:18], v[17:18], 16 +; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v37 ; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; SI-NEXT: v_alignbit_b32 v18, v19, v18, 16 -; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v49 +; SI-NEXT: v_lshr_b64 v[18:19], v[18:19], 16 +; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v36 ; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 -; SI-NEXT: v_alignbit_b32 v19, v20, v19, 16 -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshr_b64 v[19:20], v[19:20], 16 +; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v33 +; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; SI-NEXT: v_lshr_b64 v[32:33], v[32:33], 16 +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 ; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 -; SI-NEXT: v_alignbit_b32 v20, v21, v20, 16 -; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v48 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 +; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; SI-NEXT: v_lshr_b64 v[20:21], v[20:21], 16 +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 ; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 -; SI-NEXT: v_alignbit_b32 v21, v22, v21, 16 -; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 ; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 -; SI-NEXT: v_alignbit_b32 v22, v23, v22, 16 -; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v39 +; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; SI-NEXT: v_lshr_b64 v[21:22], v[21:22], 16 +; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; SI-NEXT: v_lshr_b64 v[22:23], v[22:23], 16 +; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 ; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 -; SI-NEXT: v_alignbit_b32 v23, v24, v23, 16 -; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 ; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 -; SI-NEXT: v_alignbit_b32 v24, v25, v24, 16 -; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v38 +; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; SI-NEXT: v_lshr_b64 v[23:24], v[23:24], 16 +; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 ; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 -; SI-NEXT: v_alignbit_b32 v25, v26, v25, 16 -; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v36 +; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; SI-NEXT: v_lshr_b64 v[24:25], v[24:25], 16 +; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v41 +; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 +; SI-NEXT: v_lshr_b64 v[25:26], v[25:26], 16 +; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 ; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 -; SI-NEXT: v_alignbit_b32 v26, v27, v26, 16 -; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v34 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 ; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 -; SI-NEXT: v_alignbit_b32 v27, v28, v27, 16 -; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v35 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; SI-NEXT: v_lshr_b64 v[26:27], v[26:27], 16 +; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v43 +; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 +; SI-NEXT: v_lshr_b64 v[27:28], v[27:28], 16 +; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v42 ; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 -; SI-NEXT: v_alignbit_b32 v28, v29, v28, 16 -; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v37 +; SI-NEXT: v_lshr_b64 v[28:29], v[28:29], 16 +; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v52 ; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 -; SI-NEXT: v_alignbit_b32 v29, v30, v29, 16 -; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshr_b64 v[29:30], v[29:30], 16 +; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 ; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 -; SI-NEXT: v_alignbit_b32 v30, v31, v30, 16 -; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v33 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 ; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 -; SI-NEXT: v_alignbit_b32 v31, v32, v31, 16 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31 +; SI-NEXT: v_lshr_b64 v[30:31], v[30:31], 16 +; SI-NEXT: v_mov_b32_e32 v31, v32 ; SI-NEXT: .LBB63_5: ; %end ; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload @@ -101790,36 +101066,39 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a ; VI-NEXT: v_mov_b32_e32 v31, v17 ; VI-NEXT: v_mov_b32_e32 v30, v16 ; VI-NEXT: v_mov_b32_e32 v29, v15 -; VI-NEXT: v_mov_b32_e32 v28, v14 ; VI-NEXT: v_mov_b32_e32 v27, v13 -; VI-NEXT: v_mov_b32_e32 v26, v12 ; VI-NEXT: v_mov_b32_e32 v25, v11 -; VI-NEXT: v_mov_b32_e32 v24, v10 ; VI-NEXT: v_mov_b32_e32 v23, v9 -; VI-NEXT: v_mov_b32_e32 v22, v8 ; VI-NEXT: v_mov_b32_e32 v21, v7 -; VI-NEXT: v_mov_b32_e32 v20, v6 ; VI-NEXT: v_mov_b32_e32 v19, v5 -; VI-NEXT: v_mov_b32_e32 v32, v4 ; VI-NEXT: v_mov_b32_e32 v17, v3 -; VI-NEXT: v_mov_b32_e32 v16, v2 ; VI-NEXT: v_mov_b32_e32 v15, v1 +; VI-NEXT: v_mov_b32_e32 v28, v14 +; VI-NEXT: v_mov_b32_e32 v26, v12 +; VI-NEXT: v_mov_b32_e32 v24, v10 +; VI-NEXT: v_mov_b32_e32 v22, v8 +; VI-NEXT: v_mov_b32_e32 v20, v6 +; VI-NEXT: v_mov_b32_e32 v32, v4 +; VI-NEXT: v_mov_b32_e32 v16, v2 ; VI-NEXT: v_mov_b32_e32 v14, v0 -; VI-NEXT: v_mov_b32_e32 v0, s16 -; VI-NEXT: v_mov_b32_e32 v1, s17 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec -; VI-NEXT: v_mov_b32_e32 v2, s18 +; VI-NEXT: v_mov_b32_e32 v1, s17 ; VI-NEXT: v_mov_b32_e32 v3, s19 -; VI-NEXT: v_mov_b32_e32 v4, s20 ; VI-NEXT: v_mov_b32_e32 v5, s21 -; VI-NEXT: v_mov_b32_e32 v6, s22 ; VI-NEXT: v_mov_b32_e32 v7, s23 -; VI-NEXT: v_mov_b32_e32 v8, s24 ; VI-NEXT: v_mov_b32_e32 v9, s25 -; VI-NEXT: v_mov_b32_e32 v10, s26 ; VI-NEXT: v_mov_b32_e32 v11, s27 -; VI-NEXT: v_mov_b32_e32 v12, s28 ; VI-NEXT: v_mov_b32_e32 v13, s29 +; VI-NEXT: v_mov_b32_e32 v0, s16 +; VI-NEXT: v_mov_b32_e32 v2, s18 +; VI-NEXT: v_mov_b32_e32 v4, s20 +; VI-NEXT: v_mov_b32_e32 v6, s22 +; VI-NEXT: v_mov_b32_e32 v8, s24 +; VI-NEXT: v_mov_b32_e32 v10, s26 +; VI-NEXT: v_mov_b32_e32 v12, s28 +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB63_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_cbranch_execnz .LBB63_3 @@ -101828,580 +101107,600 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a ; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 ; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 ; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 ; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 ; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v15, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v15 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_bfe_u32 v18, v15, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc +; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15 +; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18 ; VI-NEXT: v_or_b32_e32 v34, 0x400000, v15 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 -; VI-NEXT: v_cndmask_b32_e32 v15, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; VI-NEXT: v_alignbit_b32 v15, v15, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v14 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v15, v18, v34, vcc +; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v15 +; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v14 +; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; VI-NEXT: v_bfe_u32 v18, v15, 16, 1 +; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15 ; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18 ; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v14, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v14 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v14 +; VI-NEXT: v_lshrrev_b64 v[34:35], 16, v[33:34] +; VI-NEXT: v_or_b32_e32 v33, 0x400000, v15 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 +; VI-NEXT: v_bfe_u32 v15, v14, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v35, v18, v33, vcc +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v14 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 +; VI-NEXT: v_or_b32_e32 v18, 0x400000, v14 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 -; VI-NEXT: v_cndmask_b32_e32 v14, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; VI-NEXT: v_alignbit_b32 v14, v14, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v13 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v14, v15, v18, vcc +; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v14 +; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[35:36] +; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v13 +; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; VI-NEXT: v_bfe_u32 v18, v15, 16, 1 +; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15 ; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18 ; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v13, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v13 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v13 +; VI-NEXT: v_or_b32_e32 v33, 0x400000, v15 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 +; VI-NEXT: v_bfe_u32 v15, v13, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v35, v18, v33, vcc +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 +; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 -; VI-NEXT: v_cndmask_b32_e32 v13, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; VI-NEXT: v_alignbit_b32 v13, v13, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v12 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v13, v15, v18, vcc +; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v13 +; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v12 +; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; VI-NEXT: v_bfe_u32 v15, v13, 16, 1 +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13 ; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 ; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v12, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v12 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v12 +; VI-NEXT: v_lshrrev_b64 v[35:36], 16, v[35:36] +; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 +; VI-NEXT: v_bfe_u32 v13, v12, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v36, v15, v18, vcc +; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v12 +; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 +; VI-NEXT: v_or_b32_e32 v15, 0x400000, v12 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 -; VI-NEXT: v_cndmask_b32_e32 v12, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; VI-NEXT: v_alignbit_b32 v12, v12, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v11 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v12, v13, v15, vcc +; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v12 +; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[36:37] +; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v11 +; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; VI-NEXT: v_bfe_u32 v15, v13, 16, 1 +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13 ; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 ; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v11, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v11 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v11 +; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 +; VI-NEXT: v_bfe_u32 v13, v11, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v36, v15, v18, vcc +; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11 +; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 +; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 -; VI-NEXT: v_cndmask_b32_e32 v11, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; VI-NEXT: v_alignbit_b32 v11, v11, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v10 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v11, v13, v15, vcc +; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v11 +; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; VI-NEXT: v_bfe_u32 v13, v11, 16, 1 +; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11 ; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 ; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v10, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v10 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v10 +; VI-NEXT: v_lshrrev_b64 v[36:37], 16, v[36:37] +; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 +; VI-NEXT: v_bfe_u32 v11, v10, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v37, v13, v15, vcc +; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v10 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 +; VI-NEXT: v_or_b32_e32 v13, 0x400000, v10 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 -; VI-NEXT: v_cndmask_b32_e32 v10, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; VI-NEXT: v_alignbit_b32 v10, v10, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v9 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v10, v11, v13, vcc +; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v10 +; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[37:38] +; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v9 +; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; VI-NEXT: v_bfe_u32 v13, v11, 16, 1 +; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11 ; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 ; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v9, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v9 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v9 +; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 +; VI-NEXT: v_bfe_u32 v11, v9, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v37, v13, v15, vcc +; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 +; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 -; VI-NEXT: v_cndmask_b32_e32 v9, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; VI-NEXT: v_alignbit_b32 v9, v9, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v8 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc +; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9 +; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v8 +; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 +; VI-NEXT: v_bfe_u32 v11, v9, 16, 1 +; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9 ; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 ; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v8, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v8 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v8 +; VI-NEXT: v_lshrrev_b64 v[37:38], 16, v[37:38] +; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 +; VI-NEXT: v_bfe_u32 v9, v8, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v38, v11, v13, vcc +; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9 +; VI-NEXT: v_or_b32_e32 v11, 0x400000, v8 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8 -; VI-NEXT: v_cndmask_b32_e32 v8, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; VI-NEXT: v_alignbit_b32 v8, v8, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v7 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v8, v9, v11, vcc +; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8 +; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[38:39] +; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v7 +; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 +; VI-NEXT: v_bfe_u32 v11, v9, 16, 1 +; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9 ; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 ; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v7, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v7 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v7 +; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 +; VI-NEXT: v_bfe_u32 v9, v7, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v38, v11, v13, vcc +; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9 +; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 -; VI-NEXT: v_cndmask_b32_e32 v7, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; VI-NEXT: v_alignbit_b32 v7, v7, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v6 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v7, v9, v11, vcc +; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v7 +; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v6 +; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 +; VI-NEXT: v_bfe_u32 v9, v7, 16, 1 +; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7 ; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9 ; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v6, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v6 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v6 +; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 +; VI-NEXT: v_bfe_u32 v7, v6, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v48, v9, v11, vcc +; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v6 +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7 +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v6 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; VI-NEXT: v_cndmask_b32_e32 v6, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; VI-NEXT: v_alignbit_b32 v6, v6, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v5 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v6, v7, v9, vcc +; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6 +; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[48:49] +; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v5 +; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 +; VI-NEXT: v_bfe_u32 v9, v7, 16, 1 +; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7 ; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9 ; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v5, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v5 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v5 +; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 +; VI-NEXT: v_bfe_u32 v7, v5, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v48, v9, v11, vcc +; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5 +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7 +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; VI-NEXT: v_cndmask_b32_e32 v5, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; VI-NEXT: v_alignbit_b32 v5, v5, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v4 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc +; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v5 +; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v4 +; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 +; VI-NEXT: v_bfe_u32 v7, v5, 16, 1 +; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5 ; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7 ; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v4, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v4 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v4 +; VI-NEXT: v_lshrrev_b64 v[48:49], 16, v[48:49] +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 +; VI-NEXT: v_bfe_u32 v5, v4, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v49, v7, v9, vcc +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v4 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; VI-NEXT: v_cndmask_b32_e32 v4, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; VI-NEXT: v_alignbit_b32 v4, v4, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v3 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc +; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v4 +; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[49:50] +; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v3 +; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 +; VI-NEXT: v_bfe_u32 v7, v5, 16, 1 +; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5 ; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7 ; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v3, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v3 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v3 +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v49, v7, v9, vcc +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; VI-NEXT: v_cndmask_b32_e32 v3, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; VI-NEXT: v_alignbit_b32 v3, v3, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v2 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v3 +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 ; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 ; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v2 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v2 +; VI-NEXT: v_lshrrev_b64 v[49:50], 16, v[49:50] +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v50, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: v_alignbit_b32 v2, v2, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v1 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v2 +; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[50:51] +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v1 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 ; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 ; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v1 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v50, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; VI-NEXT: v_alignbit_b32 v1, v1, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v0 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 ; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v0, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v0 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v0 +; VI-NEXT: v_lshrrev_b64 v[50:51], 16, v[50:51] +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_bfe_u32 v1, v0, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v51, v3, v5, vcc +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1 +; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; VI-NEXT: v_cndmask_b32_e32 v0, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; VI-NEXT: v_alignbit_b32 v0, v0, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v31 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v31, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v31 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v31 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31 -; VI-NEXT: v_cndmask_b32_e32 v31, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; VI-NEXT: v_alignbit_b32 v31, v31, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v30 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v30, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v30 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v30 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 -; VI-NEXT: v_cndmask_b32_e32 v30, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; VI-NEXT: v_alignbit_b32 v30, v30, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v29 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v29, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v29 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v29 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 -; VI-NEXT: v_cndmask_b32_e32 v29, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v29 -; VI-NEXT: v_alignbit_b32 v29, v29, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v28 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v28, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v28 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v28 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 -; VI-NEXT: v_cndmask_b32_e32 v28, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v28 -; VI-NEXT: v_alignbit_b32 v28, v28, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v27 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v27, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v27 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v27 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 -; VI-NEXT: v_cndmask_b32_e32 v27, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; VI-NEXT: v_alignbit_b32 v27, v27, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v26 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v26, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v26 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v26 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 -; VI-NEXT: v_cndmask_b32_e32 v26, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v26 -; VI-NEXT: v_alignbit_b32 v26, v26, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v25 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v25, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v25 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v25 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 -; VI-NEXT: v_cndmask_b32_e32 v25, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 -; VI-NEXT: v_alignbit_b32 v25, v25, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v24 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v24, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v24 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v24 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; VI-NEXT: v_cndmask_b32_e32 v24, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; VI-NEXT: v_alignbit_b32 v24, v24, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v23 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v23, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v23 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v23 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 -; VI-NEXT: v_cndmask_b32_e32 v23, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v23 -; VI-NEXT: v_alignbit_b32 v23, v23, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v22 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v22, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v22 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v22 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 -; VI-NEXT: v_cndmask_b32_e32 v22, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v22 -; VI-NEXT: v_alignbit_b32 v22, v22, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v21 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v21, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v21 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v21 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 -; VI-NEXT: v_cndmask_b32_e32 v21, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; VI-NEXT: v_alignbit_b32 v21, v21, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v20 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v20, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v20 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v20 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 -; VI-NEXT: v_cndmask_b32_e32 v20, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; VI-NEXT: v_alignbit_b32 v20, v20, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v19 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v19, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v19 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v19 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 -; VI-NEXT: v_cndmask_b32_e32 v19, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; VI-NEXT: v_alignbit_b32 v19, v19, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v32 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v32, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 -; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; VI-NEXT: v_alignbit_b32 v32, v32, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v17 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v17, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v17 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v17 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 -; VI-NEXT: v_cndmask_b32_e32 v17, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; VI-NEXT: v_alignbit_b32 v17, v17, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v16 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v16, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v16 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v16 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16 -; VI-NEXT: v_cndmask_b32_e32 v16, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; VI-NEXT: v_alignbit_b32 v16, v16, v18, 16 +; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc +; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v0 +; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[51:52] +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v31 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v31 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v51, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v30 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v30 +; VI-NEXT: v_lshrrev_b64 v[51:52], 16, v[51:52] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v52, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v29 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v29 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[30:31], 16, v[52:53] +; VI-NEXT: v_cndmask_b32_e32 v52, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v28 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v28 +; VI-NEXT: v_lshrrev_b64 v[52:53], 16, v[52:53] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v53, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v27 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v27 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[28:29], 16, v[53:54] +; VI-NEXT: v_cndmask_b32_e32 v53, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v26 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v26 +; VI-NEXT: v_lshrrev_b64 v[53:54], 16, v[53:54] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v54, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v25 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v25 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[26:27], 16, v[54:55] +; VI-NEXT: v_cndmask_b32_e32 v54, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v24 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v24 +; VI-NEXT: v_lshrrev_b64 v[38:39], 16, v[38:39] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v39, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v23 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v23 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[24:25], 16, v[39:40] +; VI-NEXT: v_cndmask_b32_e32 v39, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v22 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v22 +; VI-NEXT: v_lshrrev_b64 v[39:40], 16, v[39:40] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v40, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v21 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v21 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[22:23], 16, v[40:41] +; VI-NEXT: v_cndmask_b32_e32 v40, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v20 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v20 +; VI-NEXT: v_lshrrev_b64 v[40:41], 16, v[40:41] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v41, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v19 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v19 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v18, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v32 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v32 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v31, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v17 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v17 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[20:21], 16, v[41:42] +; VI-NEXT: v_cndmask_b32_e32 v41, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v16 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v16 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v15, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b64 v[54:55], 16, v[54:55] +; VI-NEXT: v_lshrrev_b64 v[18:19], 16, v[18:19] +; VI-NEXT: v_lshrrev_b64 v[41:42], 16, v[41:42] +; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v1 +; VI-NEXT: v_lshrrev_b64 v[32:33], 16, v[31:32] +; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[15:16] +; VI-NEXT: v_mov_b32_e32 v1, v50 +; VI-NEXT: v_mov_b32_e32 v3, v49 +; VI-NEXT: v_mov_b32_e32 v5, v48 +; VI-NEXT: v_mov_b32_e32 v7, v38 +; VI-NEXT: v_mov_b32_e32 v9, v37 +; VI-NEXT: v_mov_b32_e32 v11, v36 +; VI-NEXT: v_mov_b32_e32 v13, v35 +; VI-NEXT: v_mov_b32_e32 v15, v34 +; VI-NEXT: v_mov_b32_e32 v17, v41 +; VI-NEXT: v_mov_b32_e32 v19, v18 +; VI-NEXT: v_mov_b32_e32 v21, v40 +; VI-NEXT: v_mov_b32_e32 v23, v39 +; VI-NEXT: v_mov_b32_e32 v25, v54 +; VI-NEXT: v_mov_b32_e32 v27, v53 +; VI-NEXT: v_mov_b32_e32 v29, v52 +; VI-NEXT: v_mov_b32_e32 v31, v51 ; VI-NEXT: .LBB63_3: ; %end +; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload ; VI-NEXT: v_mov_b32_e32 v18, v32 +; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_setpc_b64 s[30:31] ; VI-NEXT: .LBB63_4: ; VI-NEXT: s_branch .LBB63_2 @@ -103066,100 +102365,26 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 -; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:156 -; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:28 -; GFX11-TRUE16-NEXT: s_clause 0x6 ; 28-byte Folded Spill -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v167, v13 :: v_dual_mov_b32 v176, v12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v177, v11 :: v_dual_mov_b32 v178, v10 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v179, v9 :: v_dual_mov_b32 v180, v8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v181, v7 :: v_dual_mov_b32 v182, v6 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v183, v5 :: v_dual_mov_b32 v168, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v169, v3 :: v_dual_mov_b32 v170, v2 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v171, v1 :: v_dual_mov_b32 v172, v0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v174, s28 :: v_dual_mov_b32 v173, s29 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, v13 :: v_dual_mov_b32 v30, v12 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, 0 ; GFX11-TRUE16-NEXT: s_and_b32 s5, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB63_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v135, s0 :: v_dual_mov_b32 v134, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v132, s2 :: v_dual_mov_b32 v129, s3 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v125, s16 :: v_dual_mov_b32 v120, s17 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v114, s18 :: v_dual_mov_b32 v107, s19 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v99, s20 :: v_dual_mov_b32 v90, s21 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v80, s22 :: v_dual_mov_b32 v69, s23 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v57, s24 :: v_dual_mov_b32 v44, s25 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, s26 :: v_dual_mov_b32 v15, s27 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 ; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB63_3 ; GFX11-TRUE16-NEXT: .LBB63_2: ; %cmp.true @@ -103170,972 +102395,674 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a ; GFX11-TRUE16-NEXT: s_and_b32 s4, s26, 0xffff0000 ; GFX11-TRUE16-NEXT: s_lshl_b32 s6, s26, 16 ; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1 +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1 ; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v1 +; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s6 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3 ; GFX11-TRUE16-NEXT: s_and_b32 s5, s25, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s7, s25, 16 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s6 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0 ; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s5 -; GFX11-TRUE16-NEXT: s_and_b32 s4, s24, 0xffff0000 +; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s25, 16 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v8 :: v_dual_add_nc_u32 v7, v7, v3 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v7, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v3 -; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s7 -; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v9, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v3 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v6, 16, 1 ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v4 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7 -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s24, 16 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v7, v2 :: v_dual_add_nc_u32 v7, v8, v5 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v9, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v4 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v7 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v6 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v6 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: s_and_b32 s4, s24, 0xffff0000 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v10, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc_lo +; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v6 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v3 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1 +; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s24, 16 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v7, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v9, v5 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v7 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v7 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v6 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v3 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v1.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 16, v2 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.h, v4.l -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s23, 0xffff0000 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v57.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s23, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s22, 0xffff0000 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v1.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s22, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v9 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v0.l +; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s21, 0xffff0000 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s21, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s21, 16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3 +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v6 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s20, 0xffff0000 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v90, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v90.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s20, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s19, 0xffff0000 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v1.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8 ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v32 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v32, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s19, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v32 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v0.l +; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s18, 0xffff0000 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v107, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v107.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s18, 16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3 +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v6 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s17, 0xffff0000 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s17, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: s_and_b32 s4, s16, 0xffff0000 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v32, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v32 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v1.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v32 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v3, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX11-TRUE16-NEXT: s_and_b32 s4, s16, 0xffff0000 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v33, v3 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v120, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v120.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v34, 16, 1 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s16, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s3, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v125, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v125.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s3 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v32, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16 +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v33, 16, 1 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s3 ; GFX11-TRUE16-NEXT: s_and_b32 s3, s2, 0xffff0000 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v35, v32 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v35, 0x40c00000, s3 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v32 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v33 +; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v35, 16, 1 ; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v34 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v1.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v32, v35 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s2 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v34 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s3 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s2 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 ; GFX11-TRUE16-NEXT: s_and_b32 s2, s1, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s2 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1 -; GFX11-TRUE16-NEXT: s_and_b32 s1, s0, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v134.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v167 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v167 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v167.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v176 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v176 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v176.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v177 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v177 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v177.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v178 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v178 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v178, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v179 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v179 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v179.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v180 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v180 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v180.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v181 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v181 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v181.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v182 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v182 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v182.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v183 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v183 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_add_f32_e64 v37, 0x40c00000, s2 +; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v32, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v183.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v168 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v168 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v168, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v168.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v169 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v169 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v169, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v169.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v170 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v170 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v170, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v170.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v171 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v171 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v171, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v171.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v172 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v172 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v172, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v172.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v173 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v173 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v37, 16, 1 +; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v33, vcc_lo +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, v36, v32 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v34, v37 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s1 +; GFX11-TRUE16-NEXT: s_and_b32 s1, s0, 0xffff0000 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v0.l +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v32 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v35, 0x40c00000, s1 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v173, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v173.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v174 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v33, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v2, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, v38, v34 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v32, v35 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v31 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v36 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v36, 0x40c00000, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v33, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v36 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v37 :: v_dual_add_nc_u32 v33, v33, v36 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v32.l +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v30 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v0 +; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v33, v33, v35 :: v_dual_add_nc_u32 v0, v0, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v33 +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v32.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v36, v37 :: v_dual_add_f32 v31, 0x40c00000, v31 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v33, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v31, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, v38, v31 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v29 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v36 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v31 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v30, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v30 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v34, v30 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_and_b32 v37, 0xffff0000, v28 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v33.l +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v30, v34, v36 :: v_dual_add_nc_u32 v33, v33, v35 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v29, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_dual_add_f32 v28, 0x40c00000, v28 :: v_dual_add_nc_u32 v35, v37, v29 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v32.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v33, v33, v36 :: v_dual_add_nc_u32 v32, v38, v34 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v29 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v27 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v35, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v28, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v28 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_add_nc_u32 v35, v35, v28 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v26 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v33.l +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX11-TRUE16-NEXT: v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_add_f32 v27, 0x40c00000, v27 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, v33, v34 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v28, v35, v36 :: v_dual_add_f32 v35, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v27, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v37, v27 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v27 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v38, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v25 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v26, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v26 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v34, v26 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_and_b32 v37, 0xffff0000, v24 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v33.l +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_add_f32 v25, 0x40c00000, v25 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v32.l +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v25, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v38, v34 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v23 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, v33, v35 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, v37, v25 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v25 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v35, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v24, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v24 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v33.l +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_and_b32 v37, 0xffff0000, v22 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, v35, v24 +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v174 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v24, v35, v36 :: v_dual_add_nc_u32 v33, v33, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v23, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v37, v23 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v23 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v38, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v21 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v22, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v22 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v34, v22 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_and_b32 v37, 0xffff0000, v20 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v33.l +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, v33, v35 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v32.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v38, v34 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v19 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v21, 16, 1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v21 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, v37, v21 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v174, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v174.h, v0.l +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v35, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v20, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v20 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_add_nc_u32 v35, v35, v20 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v33.l +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v18 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, v33, v34 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v20, v35, v36 :: v_dual_add_f32 v35, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v19, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v37, v19 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v19 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v32.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v38, v35 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v17 +; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v18, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, v39, v18 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v33.l +; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v34, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v38 :: v_dual_add_nc_u32 v33, 0x7fff, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v18 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v16 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, v36, v34 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_lshlrev_b32 v16, 16, v16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v33, v35 :: v_dual_add_f32 v33, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v36 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v17, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v33, 16, 1 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v17 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v35, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, v37, v17 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, v38, v33 +; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v16, 16, 1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v33 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 0x7fff, v37 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, v35, v16 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v48, 0x400000, v16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v32.l +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v37, v38, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v36, v39, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v35, v48, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v34.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v33.l ; GFX11-TRUE16-NEXT: .LBB63_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v125 :: v_dual_mov_b32 v5, v120 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v114 :: v_dual_mov_b32 v7, v107 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v99 :: v_dual_mov_b32 v9, v90 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v57 :: v_dual_mov_b32 v13, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v30 :: v_dual_mov_b32 v17, v173 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, v174 :: v_dual_mov_b32 v19, v171 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v172 :: v_dual_mov_b32 v21, v169 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, v170 :: v_dual_mov_b32 v23, v183 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, v168 :: v_dual_mov_b32 v25, v181 -; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0x6 ; 28-byte Folded Reload -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:280 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v135 :: v_dual_mov_b32 v1, v134 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v132 :: v_dual_mov_b32 v3, v129 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v80 :: v_dual_mov_b32 v11, v69 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v24, v182 :: v_dual_mov_b32 v27, v179 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v180 :: v_dual_mov_b32 v29, v177 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v178 :: v_dual_mov_b32 v31, v167 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v30, v176 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB63_4: -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 ; GFX11-TRUE16-NEXT: s_branch .LBB63_2 ; ; GFX11-FAKE16-LABEL: bitcast_v64bf16_to_v16i64_scalar: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 -; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:288 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:284 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:280 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:276 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:272 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:268 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:264 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:260 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:256 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:252 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:248 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:244 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:240 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:236 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:232 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:228 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:224 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:220 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:216 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:212 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:208 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:204 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:200 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:196 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:192 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:188 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:184 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:180 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:176 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:172 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:168 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:164 -; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:160 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:156 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:152 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:148 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:144 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:140 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:136 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:132 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:128 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:124 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:120 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:116 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:112 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:108 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:104 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:100 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:96 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:92 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:88 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v139, s32 offset:84 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v140, s32 offset:80 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v141, s32 offset:76 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v142, s32 offset:72 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v143, s32 offset:68 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v152, s32 offset:64 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v153, s32 offset:60 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v154, s32 offset:56 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v155, s32 offset:52 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v156, s32 offset:48 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v157, s32 offset:44 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v158, s32 offset:40 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v159, s32 offset:36 -; GFX11-FAKE16-NEXT: s_clause 0x8 ; 36-byte Folded Spill -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v168, s32 offset:32 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v169, s32 offset:28 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v170, s32 offset:24 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v171, s32 offset:20 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v172, s32 offset:16 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v173, s32 offset:12 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v174, s32 offset:8 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v175, s32 offset:4 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v184, s32 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v178, v13 :: v_dual_mov_b32 v179, v12 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v180, v11 :: v_dual_mov_b32 v181, v9 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v182, v10 :: v_dual_mov_b32 v169, v7 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v170, v8 :: v_dual_mov_b32 v177, v3 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v176, v6 :: v_dual_mov_b32 v171, v4 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v174, v5 :: v_dual_mov_b32 v173, v0 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v184, v2 :: v_dual_mov_b32 v175, v1 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v183, s28 :: v_dual_mov_b32 v172, s29 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v13 :: v_dual_mov_b32 v30, v12 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 ; GFX11-FAKE16-NEXT: s_mov_b32 s4, 0 ; GFX11-FAKE16-NEXT: s_and_b32 s5, vcc_lo, exec_lo ; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB63_4 ; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, s0 :: v_dual_mov_b32 v37, s2 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, s1 :: v_dual_mov_b32 v41, s3 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v46, s16 :: v_dual_mov_b32 v59, s18 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, s17 :: v_dual_mov_b32 v67, s19 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v76, s20 :: v_dual_mov_b32 v97, s22 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v86, s21 :: v_dual_mov_b32 v109, s23 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v122, s24 :: v_dual_mov_b32 v151, s26 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v136, s25 :: v_dual_mov_b32 v15, s27 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 ; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4 ; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB63_3 ; GFX11-FAKE16-NEXT: .LBB63_2: ; %cmp.true @@ -104143,762 +103070,674 @@ define inreg <16 x i64> @bitcast_v64bf16_to_v16i64_scalar(<64 x bfloat> inreg %a ; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s27, 16 ; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s5 ; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s26, 16 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s26, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s6 +; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s26, 16 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 ; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1 ; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s6 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1 +; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1 ; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1 -; GFX11-FAKE16-NEXT: s_lshl_b32 s7, s25, 16 +; GFX11-FAKE16-NEXT: s_and_b32 s5, s25, 0xffff0000 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0 -; GFX11-FAKE16-NEXT: s_and_b32 s5, s25, 0xffff0000 -; GFX11-FAKE16-NEXT: s_and_b32 s4, s24, 0xffff0000 ; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s5 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v183 +; GFX11-FAKE16-NEXT: s_lshl_b32 s7, s25, 16 +; GFX11-FAKE16-NEXT: s_and_b32 s4, s24, 0xffff0000 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s24, 16 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v9, v3 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v5 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v9, v3 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v6, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v7, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v7 :: v_dual_add_nc_u32 v2, 0x7fff, v2 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v5 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s7 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v3 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 +; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v6, 16, 1 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v8, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v1, 16, v0 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v3, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v10, v6 +; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v1, 16, v0 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v5, v6 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v7, v9, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s23, 16 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v0, 16, v1 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 ; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s24, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v6 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v8 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s23, 0xffff0000 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo ; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v5 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v9 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v1, v7 :: v_dual_and_b32 v1, 0xffff, v2 -; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v9, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v6 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v7, v9 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s23, 16 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v151, v0, 16, v1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6 -; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v4, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: s_and_b32 s4, s22, 0xffff0000 -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v12, 16, 1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v11, v7 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v3 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s22, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v5 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v6 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v8 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v9, v12 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v10, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v12 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s22, 16 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1 +; GFX11-FAKE16-NEXT: s_and_b32 s4, s22, 0xffff0000 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6 +; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s21, 0xffff0000 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v6, v9, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v11, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v14, v10 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v5 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v7 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v13 :: v_dual_add_nc_u32 v7, v9, v11 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v12 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v10 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s21, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v11 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v13, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v16, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s21, 16 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 +; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s20, 0xffff0000 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v7, v14 :: v_dual_add_nc_u32 v10, v10, v13 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v8 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v13 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v11 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v12, v16 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s20, 16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11 -; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v12, 16, 1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v10, v14, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s20, 16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6 +; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s19, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, v18, v12 -; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v17, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s19, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v13 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v14 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, v16, v19 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v12 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v14 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s19, 16 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 +; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s18, 0xffff0000 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v16, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, v21, v17 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v11 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v13 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v20 :: v_dual_add_nc_u32 v13, v16, v18 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v19 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v17 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s18, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v18 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v19, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v20, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v22, 16, 1 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s18, 16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v6 +; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s17, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, v17, v20 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v13, v21 :: v_dual_and_b32 v13, 0xffff, v14 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v20 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v19, v22 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s17, 16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v22 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18 -; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v19, 16, 1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v17, v21, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s17, 16 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v32, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s5 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s16, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, v24, v19 -; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v25, 16, 1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v18, v23 :: v_dual_and_b32 v17, 0xffff, v16 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s16, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v20 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v21 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, v22, v25 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v19 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v24, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_bfe_u32 v27, v23, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x7fff, v21 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v25 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s16, 16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1 +; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v32, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v6 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v33 :: v_dual_add_nc_u32 v5, v7, v32 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v0, 16, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v32 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s5 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s3, 0xffff0000 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v22, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v24, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v25, v27, v23 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v18 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v20 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v21, v26 :: v_dual_add_nc_u32 v20, v22, v24 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, 0x7fff, v25 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v23 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v26, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 ; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v24 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v28, 0x40c00000, s3 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v25, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v26, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; GFX11-FAKE16-NEXT: v_bfe_u32 v25, v28, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v33, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v5 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v34, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s3 ; GFX11-FAKE16-NEXT: s_and_b32 s3, s2, 0xffff0000 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v24, v20, v27 :: v_dual_add_nc_u32 v23, v23, v26 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v21 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v22 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v26 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, 0x7fff, v23 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v24 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, v25, v28 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s3 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v33 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v32, v33 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v34, 16, 1 ; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, 0x400000, v28 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, 0x7fff, v24 -; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v25, 16, 1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v31, 0x40c00000, s2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v23, v27, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v33, v34 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v32, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v32 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v32 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v35, vcc_lo +; GFX11-FAKE16-NEXT: v_add_f32_e64 v35, 0x40c00000, s2 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v33 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v34 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s3 +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s2, s1, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, v30, v25 -; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v31, 16, 1 ; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v29, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e64 v29, 0x40c00000, s2 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v22 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v26 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v26, 0x7fff, v27 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, v28, v31 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v25 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v30, 0x40c00000, s1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v29, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, 0x7fff, v27 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v31 -; GFX11-FAKE16-NEXT: s_and_b32 s1, s0, 0xffff0000 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v26, v28, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v30, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, v33, v29 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v24 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v26 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v27, v27, v32 :: v_dual_add_nc_u32 v26, v28, v30 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v33, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v35 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v33 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v28, 0x7fff, v31 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, 0x400000, v29 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v4, v33 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v36, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v36, 0x40c00000, s1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v34 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s2 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v36, 16, 1 +; GFX11-FAKE16-NEXT: s_and_b32 s1, s0, 0xffff0000 ; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v26, 0x7fff, v26 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v30 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v28, v31, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v29, v32, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v32 -; GFX11-FAKE16-NEXT: v_bfe_u32 v31, v34, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v26, v33, vcc_lo -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v28 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v28, v29, v32 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v178 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v30 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v30, v31, v34 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v178 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v28, 0x7fff, v28 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v33, 0x40c00000, v33 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v109, v5, 16, v7 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v30, 0x7fff, v30 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v28, v35, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v32, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v36 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v38, 0x40c00000, s0 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v32, v34 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v33 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v36 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v35 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v35, 0x40c00000, s1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v34 +; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v38, 16, 1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v33, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v29 +; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v2, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v0, 16, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v33, v35 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v36, v38 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v38 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v34 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v31 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v32 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v31, 0x40c00000, v31 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v34, 16, 1 ; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v31, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v37, v33 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v30, v36, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v179 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v35, v31 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v33 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v179 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v31 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v1, 16, v32 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v36, v34 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v31 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v30 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v31 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 ; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v180 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v36 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v34, v38, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v36, 16, 1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v35, 16, 1 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v38, 16, v180 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_add_f32 v37, 0x40c00000, v37 :: v_dual_add_nc_u32 v34, v34, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v33, v35 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v38 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v33 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v34 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v31, v35, v37 :: v_dual_add_nc_u32 v32, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v30, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v33 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v35, v36 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v29 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v30 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v38 :: v_dual_lshlrev_b32 v29, 16, v29 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v30 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v36 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v32 -; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v37, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v34, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v29, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v32, 16, v31 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v178, v31, 16, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, v36, v37 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v33, v48 :: v_dual_lshlrev_b32 v36, 16, v182 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v38 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v33, v38 :: v_dual_add_nc_u32 v32, v34, v35 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v35, v38 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v182 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v34 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v37 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, 0x7fff, v31 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v179, v32, 16, v34 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v30 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v136, v2, 16, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v36, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v36 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v36, v29 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v28 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v29 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v31, v31, v48 :: v_dual_add_nc_u32 v38, v38, v35 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v37, v36 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v181 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v38 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v38, 16, v181 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v37, 0x40c00000, v37 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v38 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v39, vcc_lo +; GFX11-FAKE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v30 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v34, v37, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v33 -; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v37, 16, 1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v48, vcc_lo -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v180, v31, 16, v33 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v35, v37 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v170 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v38 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v36, v38 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_lshlrev_b32 v36, 16, v170 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v28, 16, 1 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v33, 16, v30 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v28 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v38 :: v_dual_add_nc_u32 v33, v35, v28 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v36 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v27 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v37 -; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v36, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v182, v31, 16, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, v38, v35 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, v39, v36 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v48, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v36 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v27, 0x40c00000, v27 :: v_dual_cndmask_b32 v28, v33, v37 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, 0x7fff, v31 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff, v29 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v27, 16, 1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v34, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v32, 16, v29 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v27 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v37 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v169 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v31, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v34, v35 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v36, v27 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v26 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v28 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v32, 16, v28 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v34, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v26, 16, 1 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v39, 16, v169 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v181, v32, 16, v33 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v37, 0x40c00000, v37 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v176 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v48, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v39 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v37, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v37 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v34 -; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v36, 16, 1 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v38 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v35, v37 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v176 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v32, v36 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v25 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v36 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v37, v26 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v26 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v36 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 -; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v49, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v36 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v32, v37, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v27 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v170, v33, 16, v31 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v49, v35 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v48 :: v_dual_add_nc_u32 v33, v37, v38 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v174 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v25, 0x40c00000, v25 :: v_dual_lshlrev_b32 v36, 16, v24 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v34, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v33, 16, v27 +; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v25, 16, 1 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v35 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v36 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v33, v25 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v25 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v36, 16, 1 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v26 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v24, 16, 1 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v23 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v33, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v39, v36 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v32, 16, v26 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v35, v24 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v36 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v38 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_cndmask_b32 v34, v34, v36 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v174 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v32 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v35, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_cndmask_b32 v33, v33, v39 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v169, v31, 16, v32 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, v37, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v34 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v31, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v24 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v35, vcc_lo +; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v22 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v171 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v34, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v32, 16, v25 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v33 +; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v23, 16, 1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v35 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v38, 16, v177 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, v31, v36 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v176, v33, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v37 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v32, v23 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v24, 16, v33 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v34 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v32, 0x40c00000, v32 :: v_dual_lshlrev_b32 v37, 16, v171 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, 0x7fff, v31 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v38 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v36 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v36 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37 -; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v32, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v32 -; GFX11-FAKE16-NEXT: v_bfe_u32 v50, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v31, v31, v34 :: v_dual_add_nc_u32 v36, v37, v32 -; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v177 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v37, 0x40c00000, v37 :: v_dual_add_nc_u32 v34, v34, v35 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v23 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v22 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v36, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v32, v34 :: v_dual_add_nc_u32 v34, v35, v36 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v21 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v22, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 -; GFX11-FAKE16-NEXT: v_bfe_u32 v49, v37, 16, 1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v50, v38 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v38 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v184 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_add_f32 v21, 0x40c00000, v21 :: v_dual_add_nc_u32 v32, v32, v22 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v34, v34, v48 :: v_dual_add_nc_u32 v35, v49, v37 +; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v21, 16, 1 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v21 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v23 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v48, v21 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v32, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v39, v35 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v20 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v184 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_cndmask_b32 v21, v36, v37 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v38 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v37 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v37, 0x40c00000, v50 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31 +; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v20, 16, 1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v39, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v33, 16, v23 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v34, 16, v22 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v36 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v38, 0x40c00000, v48 :: v_dual_cndmask_b32 v35, v35, v49 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v36 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v34 -; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v37, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff, v36 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v174, v33, 16, v31 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v171, v32, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, v48, v37 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v175 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v175 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v39, v39, v38 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v177, v35, 16, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, 0x7fff, v31 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v37 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v34, 0x40c00000, v34 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v39 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v38 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v37, v20 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v19 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v32, 16, v21 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v35 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v20 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v34, 0x40c00000, v34 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v36 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v33, v35 :: v_dual_and_b32 v33, 0xffff0000, v18 +; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v19, 16, 1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v34, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_lshlrev_b32 v18, 16, v18 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v38, v19 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_add_nc_u32 v35, v35, v34 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v19 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v34, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v31, v35, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v173 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v173 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v33 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_cndmask_b32 v32, v32, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v37, v33 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, v39, v34 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v34 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_nc_u32 v37, v37, v33 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v36, v38, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, 0x7fff, v37 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v38, v38, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v122, v3, 16, v6 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v37, v39, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v37 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v33 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v18 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v35, v39, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v18, 16, 1 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, 0x7fff, v38 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v48 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v36, v49 :: v_dual_lshlrev_b32 v48, 16, v183 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v38 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v48, 0x40c00000, v48 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v37, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v172 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v39, 16, v172 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v36, v38 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v55, 0x400000, v48 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v18 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v36, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v17 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v16 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v17, 0x40c00000, v17 ; GFX11-FAKE16-NEXT: v_add_f32_e32 v37, 0x40c00000, v37 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v39, 0x40c00000, v39 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v34 -; GFX11-FAKE16-NEXT: v_bfe_u32 v50, v37, 16, 1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v39, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v49, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v39 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v50, 0x40c00000, v51 :: v_dual_add_nc_u32 v49, v50, v37 -; GFX11-FAKE16-NEXT: v_bfe_u32 v51, v48, 16, 1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v38, v38, v39 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v53, 0x400000, v37 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v35, v38, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v49, 0x7fff, v49 -; GFX11-FAKE16-NEXT: v_bfe_u32 v52, v50, 16, 1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v51, v51, v48 +; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v17, 16, 1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v17 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v38, v39, v36 +; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v37, 16, 1 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v17 +; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v16, 16, 1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v51, 0x400000, v37 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v38, 0x7fff, v38 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v36 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v35 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v52, v52, v50 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v38, v38, v54 :: v_dual_add_nc_u32 v51, 0x7fff, v51 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v39, 0x7fff, v52 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v52, 0x400000, v50 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v38 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v51, v55, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v39, v39, v37 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v36 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v48, v48, v16 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v39, 0x7fff, v39 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v35, v50, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v184, v32, 16, v31 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v175, v33, 16, v34 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff, v38 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v48 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v49, v53, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v173, v35, 16, v36 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v97, v8, 16, v10 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff, v48 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v37 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v39, v52, vcc_lo -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v86, v9, 16, v12 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v76, v11, 16, v13 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v67, v14, 16, v17 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v172, v37, 16, v38 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v39 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v59, v16, 16, v19 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v52, v18, 16, v20 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v46, v21, 16, v23 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v41, v22, 16, v25 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v183, v39, 16, v48 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v37, v24, 16, v27 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v34, v26, 16, v28 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v32, v29, 16, v30 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v48 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v16 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v39, v51, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v18 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v38, v49, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v32, 16, v20 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v34, 16, v19 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v33, 16, v18 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v36 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v35, v48, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v37 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v36, 16, v17 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff, v35 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v16, 16, v35 ; GFX11-FAKE16-NEXT: .LBB63_3: ; %end -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, v41 :: v_dual_mov_b32 v4, v46 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, v59 :: v_dual_mov_b32 v9, v86 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v7, v67 :: v_dual_mov_b32 v8, v76 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, v97 :: v_dual_mov_b32 v13, v136 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v11, v109 :: v_dual_mov_b32 v12, v122 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, v151 :: v_dual_mov_b32 v17, v172 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, v173 :: v_dual_mov_b32 v19, v175 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v20, v184 :: v_dual_mov_b32 v23, v174 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v22, v171 :: v_dual_mov_b32 v25, v169 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v26, v170 :: v_dual_mov_b32 v29, v180 -; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-FAKE16-NEXT: scratch_load_b32 v184, off, s32 -; GFX11-FAKE16-NEXT: scratch_load_b32 v175, off, s32 offset:4 -; GFX11-FAKE16-NEXT: scratch_load_b32 v174, off, s32 offset:8 -; GFX11-FAKE16-NEXT: scratch_load_b32 v173, off, s32 offset:12 -; GFX11-FAKE16-NEXT: scratch_load_b32 v172, off, s32 offset:16 -; GFX11-FAKE16-NEXT: scratch_load_b32 v171, off, s32 offset:20 -; GFX11-FAKE16-NEXT: scratch_load_b32 v170, off, s32 offset:24 -; GFX11-FAKE16-NEXT: scratch_load_b32 v169, off, s32 offset:28 -; GFX11-FAKE16-NEXT: scratch_load_b32 v168, off, s32 offset:32 -; GFX11-FAKE16-NEXT: scratch_load_b32 v159, off, s32 offset:36 -; GFX11-FAKE16-NEXT: scratch_load_b32 v158, off, s32 offset:40 -; GFX11-FAKE16-NEXT: scratch_load_b32 v157, off, s32 offset:44 -; GFX11-FAKE16-NEXT: scratch_load_b32 v156, off, s32 offset:48 -; GFX11-FAKE16-NEXT: scratch_load_b32 v155, off, s32 offset:52 -; GFX11-FAKE16-NEXT: scratch_load_b32 v154, off, s32 offset:56 -; GFX11-FAKE16-NEXT: scratch_load_b32 v153, off, s32 offset:60 -; GFX11-FAKE16-NEXT: scratch_load_b32 v152, off, s32 offset:64 -; GFX11-FAKE16-NEXT: scratch_load_b32 v143, off, s32 offset:68 -; GFX11-FAKE16-NEXT: scratch_load_b32 v142, off, s32 offset:72 -; GFX11-FAKE16-NEXT: scratch_load_b32 v141, off, s32 offset:76 -; GFX11-FAKE16-NEXT: scratch_load_b32 v140, off, s32 offset:80 -; GFX11-FAKE16-NEXT: scratch_load_b32 v139, off, s32 offset:84 -; GFX11-FAKE16-NEXT: scratch_load_b32 v138, off, s32 offset:88 -; GFX11-FAKE16-NEXT: scratch_load_b32 v137, off, s32 offset:92 -; GFX11-FAKE16-NEXT: scratch_load_b32 v136, off, s32 offset:96 -; GFX11-FAKE16-NEXT: scratch_load_b32 v127, off, s32 offset:100 -; GFX11-FAKE16-NEXT: scratch_load_b32 v126, off, s32 offset:104 -; GFX11-FAKE16-NEXT: scratch_load_b32 v125, off, s32 offset:108 -; GFX11-FAKE16-NEXT: scratch_load_b32 v124, off, s32 offset:112 -; GFX11-FAKE16-NEXT: scratch_load_b32 v123, off, s32 offset:116 -; GFX11-FAKE16-NEXT: scratch_load_b32 v122, off, s32 offset:120 -; GFX11-FAKE16-NEXT: scratch_load_b32 v121, off, s32 offset:124 -; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-FAKE16-NEXT: scratch_load_b32 v120, off, s32 offset:128 -; GFX11-FAKE16-NEXT: scratch_load_b32 v111, off, s32 offset:132 -; GFX11-FAKE16-NEXT: scratch_load_b32 v110, off, s32 offset:136 -; GFX11-FAKE16-NEXT: scratch_load_b32 v109, off, s32 offset:140 -; GFX11-FAKE16-NEXT: scratch_load_b32 v108, off, s32 offset:144 -; GFX11-FAKE16-NEXT: scratch_load_b32 v107, off, s32 offset:148 -; GFX11-FAKE16-NEXT: scratch_load_b32 v106, off, s32 offset:152 -; GFX11-FAKE16-NEXT: scratch_load_b32 v105, off, s32 offset:156 -; GFX11-FAKE16-NEXT: scratch_load_b32 v104, off, s32 offset:160 -; GFX11-FAKE16-NEXT: scratch_load_b32 v95, off, s32 offset:164 -; GFX11-FAKE16-NEXT: scratch_load_b32 v94, off, s32 offset:168 -; GFX11-FAKE16-NEXT: scratch_load_b32 v93, off, s32 offset:172 -; GFX11-FAKE16-NEXT: scratch_load_b32 v92, off, s32 offset:176 -; GFX11-FAKE16-NEXT: scratch_load_b32 v91, off, s32 offset:180 -; GFX11-FAKE16-NEXT: scratch_load_b32 v90, off, s32 offset:184 -; GFX11-FAKE16-NEXT: scratch_load_b32 v89, off, s32 offset:188 -; GFX11-FAKE16-NEXT: scratch_load_b32 v88, off, s32 offset:192 -; GFX11-FAKE16-NEXT: scratch_load_b32 v79, off, s32 offset:196 -; GFX11-FAKE16-NEXT: scratch_load_b32 v78, off, s32 offset:200 -; GFX11-FAKE16-NEXT: scratch_load_b32 v77, off, s32 offset:204 -; GFX11-FAKE16-NEXT: scratch_load_b32 v76, off, s32 offset:208 -; GFX11-FAKE16-NEXT: scratch_load_b32 v75, off, s32 offset:212 -; GFX11-FAKE16-NEXT: scratch_load_b32 v74, off, s32 offset:216 -; GFX11-FAKE16-NEXT: scratch_load_b32 v73, off, s32 offset:220 -; GFX11-FAKE16-NEXT: scratch_load_b32 v72, off, s32 offset:224 -; GFX11-FAKE16-NEXT: scratch_load_b32 v63, off, s32 offset:228 -; GFX11-FAKE16-NEXT: scratch_load_b32 v62, off, s32 offset:232 -; GFX11-FAKE16-NEXT: scratch_load_b32 v61, off, s32 offset:236 -; GFX11-FAKE16-NEXT: scratch_load_b32 v60, off, s32 offset:240 -; GFX11-FAKE16-NEXT: scratch_load_b32 v59, off, s32 offset:244 -; GFX11-FAKE16-NEXT: scratch_load_b32 v58, off, s32 offset:248 -; GFX11-FAKE16-NEXT: scratch_load_b32 v57, off, s32 offset:252 -; GFX11-FAKE16-NEXT: s_clause 0x8 ; 36-byte Folded Reload -; GFX11-FAKE16-NEXT: scratch_load_b32 v56, off, s32 offset:256 -; GFX11-FAKE16-NEXT: scratch_load_b32 v47, off, s32 offset:260 -; GFX11-FAKE16-NEXT: scratch_load_b32 v46, off, s32 offset:264 -; GFX11-FAKE16-NEXT: scratch_load_b32 v45, off, s32 offset:268 -; GFX11-FAKE16-NEXT: scratch_load_b32 v44, off, s32 offset:272 -; GFX11-FAKE16-NEXT: scratch_load_b32 v43, off, s32 offset:276 -; GFX11-FAKE16-NEXT: scratch_load_b32 v42, off, s32 offset:280 -; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s32 offset:284 -; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 offset:288 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, v32 :: v_dual_mov_b32 v1, v34 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, v37 :: v_dual_mov_b32 v5, v52 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, v183 :: v_dual_mov_b32 v21, v177 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v24, v176 :: v_dual_mov_b32 v27, v181 -; GFX11-FAKE16-NEXT: v_mov_b32_e32 v28, v182 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v30, v179 :: v_dual_mov_b32 v31, v178 -; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-FAKE16-NEXT: .LBB63_4: -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr15 ; GFX11-FAKE16-NEXT: s_branch .LBB63_2 %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -105891,20 +104730,48 @@ define inreg <64 x half> @bitcast_v16i64_to_v64f16_scalar(<16 x i64> inreg %a, i ; SI-NEXT: s_or_saveexec_b64 s[4:5], -1 ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] +; SI-NEXT: v_mov_b32_e32 v20, s16 +; SI-NEXT: v_readfirstlane_b32 s40, v20 +; SI-NEXT: v_mov_b32_e32 v20, s17 +; SI-NEXT: v_readfirstlane_b32 s44, v20 +; SI-NEXT: v_mov_b32_e32 v20, s18 +; SI-NEXT: v_readfirstlane_b32 s41, v20 +; SI-NEXT: v_mov_b32_e32 v20, s19 +; SI-NEXT: v_readfirstlane_b32 s45, v20 +; SI-NEXT: v_mov_b32_e32 v20, s20 +; SI-NEXT: v_readfirstlane_b32 s42, v20 +; SI-NEXT: v_mov_b32_e32 v20, s21 +; SI-NEXT: v_readfirstlane_b32 s46, v20 +; SI-NEXT: v_mov_b32_e32 v20, s22 +; SI-NEXT: v_readfirstlane_b32 s43, v20 +; SI-NEXT: v_mov_b32_e32 v20, s23 +; SI-NEXT: v_readfirstlane_b32 s47, v20 +; SI-NEXT: v_mov_b32_e32 v20, s24 +; SI-NEXT: v_readfirstlane_b32 s24, v20 +; SI-NEXT: v_mov_b32_e32 v20, s25 +; SI-NEXT: v_readfirstlane_b32 s56, v20 +; SI-NEXT: v_mov_b32_e32 v20, s26 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_writelane_b32 v63, s30, 0 +; SI-NEXT: v_readfirstlane_b32 s25, v20 +; SI-NEXT: v_mov_b32_e32 v20, s27 ; SI-NEXT: v_writelane_b32 v63, s31, 1 +; SI-NEXT: v_readfirstlane_b32 s27, v20 +; SI-NEXT: v_mov_b32_e32 v20, s28 ; SI-NEXT: v_writelane_b32 v63, s34, 2 +; SI-NEXT: v_readfirstlane_b32 s26, v20 +; SI-NEXT: v_mov_b32_e32 v20, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; SI-NEXT: v_writelane_b32 v63, s35, 3 -; SI-NEXT: v_readfirstlane_b32 s46, v1 -; SI-NEXT: v_readfirstlane_b32 s47, v2 -; SI-NEXT: v_readfirstlane_b32 s44, v3 -; SI-NEXT: v_readfirstlane_b32 s45, v4 -; SI-NEXT: v_readfirstlane_b32 s42, v5 -; SI-NEXT: v_readfirstlane_b32 s43, v6 -; SI-NEXT: v_readfirstlane_b32 s40, v7 -; SI-NEXT: v_readfirstlane_b32 s41, v8 +; SI-NEXT: v_readfirstlane_b32 s28, v20 +; SI-NEXT: v_readfirstlane_b32 s22, v1 +; SI-NEXT: v_readfirstlane_b32 s23, v2 +; SI-NEXT: v_readfirstlane_b32 s20, v3 +; SI-NEXT: v_readfirstlane_b32 s21, v4 +; SI-NEXT: v_readfirstlane_b32 s18, v5 +; SI-NEXT: v_readfirstlane_b32 s19, v6 +; SI-NEXT: v_readfirstlane_b32 s16, v7 +; SI-NEXT: v_readfirstlane_b32 s17, v8 ; SI-NEXT: v_readfirstlane_b32 s14, v9 ; SI-NEXT: v_readfirstlane_b32 s15, v10 ; SI-NEXT: v_readfirstlane_b32 s12, v11 @@ -105957,49 +104824,49 @@ define inreg <64 x half> @bitcast_v16i64_to_v64f16_scalar(<16 x i64> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v15, s4 ; SI-NEXT: s_lshr_b32 s4, s14, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v17, s4 -; SI-NEXT: s_lshr_b32 s4, s41, 16 +; SI-NEXT: s_lshr_b32 s4, s17, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v19, s4 -; SI-NEXT: s_lshr_b32 s4, s40, 16 +; SI-NEXT: s_lshr_b32 s4, s16, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v21, s4 -; SI-NEXT: s_lshr_b32 s4, s43, 16 +; SI-NEXT: s_lshr_b32 s4, s19, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v23, s4 -; SI-NEXT: s_lshr_b32 s4, s42, 16 +; SI-NEXT: s_lshr_b32 s4, s18, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v26, s4 -; SI-NEXT: s_lshr_b32 s4, s45, 16 +; SI-NEXT: s_lshr_b32 s4, s21, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v28, s4 -; SI-NEXT: s_lshr_b32 s4, s44, 16 +; SI-NEXT: s_lshr_b32 s4, s20, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v30, s4 -; SI-NEXT: s_lshr_b32 s4, s47, 16 +; SI-NEXT: s_lshr_b32 s4, s23, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v32, s4 -; SI-NEXT: s_lshr_b32 s4, s46, 16 +; SI-NEXT: s_lshr_b32 s4, s22, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v34, s4 -; SI-NEXT: s_lshr_b32 s4, s29, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v36, s4 ; SI-NEXT: s_lshr_b32 s4, s28, 16 +; SI-NEXT: v_cvt_f32_f16_e32 v36, s4 +; SI-NEXT: s_lshr_b32 s4, s26, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v38, s4 ; SI-NEXT: s_lshr_b32 s4, s27, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v48, s4 -; SI-NEXT: s_lshr_b32 s4, s26, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v51, s4 ; SI-NEXT: s_lshr_b32 s4, s25, 16 +; SI-NEXT: v_cvt_f32_f16_e32 v51, s4 +; SI-NEXT: s_lshr_b32 s4, s56, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v53, s4 ; SI-NEXT: s_lshr_b32 s4, s24, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v55, s4 -; SI-NEXT: s_lshr_b32 s4, s23, 16 +; SI-NEXT: s_lshr_b32 s4, s47, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v41, s4 -; SI-NEXT: s_lshr_b32 s4, s22, 16 +; SI-NEXT: s_lshr_b32 s4, s43, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v43, s4 -; SI-NEXT: s_lshr_b32 s4, s21, 16 +; SI-NEXT: s_lshr_b32 s4, s46, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v45, s4 -; SI-NEXT: s_lshr_b32 s4, s20, 16 +; SI-NEXT: s_lshr_b32 s4, s42, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v47, s4 -; SI-NEXT: s_lshr_b32 s4, s19, 16 +; SI-NEXT: s_lshr_b32 s4, s45, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v57, s4 -; SI-NEXT: s_lshr_b32 s4, s18, 16 +; SI-NEXT: s_lshr_b32 s4, s41, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v58, s4 -; SI-NEXT: s_lshr_b32 s4, s17, 16 +; SI-NEXT: s_lshr_b32 s4, s44, 16 ; SI-NEXT: v_cvt_f32_f16_e32 v59, s4 -; SI-NEXT: s_lshr_b32 s4, s16, 16 +; SI-NEXT: s_lshr_b32 s4, s40, 16 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; SI-NEXT: v_cvt_f32_f16_e32 v61, s4 ; SI-NEXT: v_cvt_f32_f16_e32 v8, s8 @@ -106010,75 +104877,75 @@ define inreg <64 x half> @bitcast_v16i64_to_v64f16_scalar(<16 x i64> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v18, s12 ; SI-NEXT: v_cvt_f32_f16_e32 v20, s15 ; SI-NEXT: v_cvt_f32_f16_e32 v22, s14 -; SI-NEXT: v_cvt_f32_f16_e32 v24, s41 -; SI-NEXT: v_cvt_f32_f16_e32 v25, s40 -; SI-NEXT: v_cvt_f32_f16_e32 v27, s43 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s42 -; SI-NEXT: v_cvt_f32_f16_e32 v31, s45 -; SI-NEXT: v_cvt_f32_f16_e32 v33, s44 -; SI-NEXT: v_cvt_f32_f16_e32 v35, s47 -; SI-NEXT: v_cvt_f32_f16_e32 v37, s46 -; SI-NEXT: v_cvt_f32_f16_e32 v39, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v49, s28 +; SI-NEXT: v_cvt_f32_f16_e32 v24, s17 +; SI-NEXT: v_cvt_f32_f16_e32 v25, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v27, s19 +; SI-NEXT: v_cvt_f32_f16_e32 v29, s18 +; SI-NEXT: v_cvt_f32_f16_e32 v31, s21 +; SI-NEXT: v_cvt_f32_f16_e32 v33, s20 +; SI-NEXT: v_cvt_f32_f16_e32 v35, s23 +; SI-NEXT: v_cvt_f32_f16_e32 v37, s22 +; SI-NEXT: v_cvt_f32_f16_e32 v39, s28 +; SI-NEXT: v_cvt_f32_f16_e32 v49, s26 ; SI-NEXT: v_cvt_f32_f16_e32 v50, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v52, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v54, s25 +; SI-NEXT: v_cvt_f32_f16_e32 v52, s25 +; SI-NEXT: v_cvt_f32_f16_e32 v54, s56 ; SI-NEXT: v_cvt_f32_f16_e32 v40, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v42, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v44, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v46, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v56, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v60, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v62, s18 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v1, s17 -; SI-NEXT: v_cvt_f32_f16_e32 v2, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v42, s47 +; SI-NEXT: v_cvt_f32_f16_e32 v44, s43 +; SI-NEXT: v_cvt_f32_f16_e32 v46, s46 +; SI-NEXT: v_cvt_f32_f16_e32 v56, s42 +; SI-NEXT: v_cvt_f32_f16_e32 v60, s45 +; SI-NEXT: v_cvt_f32_f16_e32 v62, s41 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, s44 +; SI-NEXT: v_cvt_f32_f16_e32 v2, s40 ; SI-NEXT: s_cbranch_execnz .LBB65_3 ; SI-NEXT: .LBB65_2: ; %cmp.true -; SI-NEXT: s_add_u32 s4, s16, 3 -; SI-NEXT: s_addc_u32 s5, s17, 0 -; SI-NEXT: s_lshr_b32 s16, s4, 16 -; SI-NEXT: s_lshr_b32 s17, s5, 16 -; SI-NEXT: s_add_u32 s18, s18, 3 -; SI-NEXT: s_addc_u32 s19, s19, 0 -; SI-NEXT: s_lshr_b32 s56, s18, 16 -; SI-NEXT: s_lshr_b32 s57, s19, 16 -; SI-NEXT: s_add_u32 s20, s20, 3 -; SI-NEXT: s_addc_u32 s21, s21, 0 -; SI-NEXT: s_lshr_b32 s58, s20, 16 -; SI-NEXT: s_lshr_b32 s59, s21, 16 -; SI-NEXT: s_add_u32 s22, s22, 3 -; SI-NEXT: s_addc_u32 s23, s23, 0 -; SI-NEXT: s_lshr_b32 s60, s22, 16 -; SI-NEXT: s_lshr_b32 s61, s23, 16 +; SI-NEXT: s_add_u32 s4, s40, 3 +; SI-NEXT: s_addc_u32 s5, s44, 0 +; SI-NEXT: s_lshr_b32 s29, s4, 16 +; SI-NEXT: s_lshr_b32 s40, s5, 16 +; SI-NEXT: s_add_u32 s41, s41, 3 +; SI-NEXT: s_addc_u32 s44, s45, 0 +; SI-NEXT: s_lshr_b32 s45, s41, 16 +; SI-NEXT: s_lshr_b32 s57, s44, 16 +; SI-NEXT: s_add_u32 s42, s42, 3 +; SI-NEXT: s_addc_u32 s46, s46, 0 +; SI-NEXT: s_lshr_b32 s58, s42, 16 +; SI-NEXT: s_lshr_b32 s59, s46, 16 +; SI-NEXT: s_add_u32 s43, s43, 3 +; SI-NEXT: s_addc_u32 s47, s47, 0 +; SI-NEXT: s_lshr_b32 s60, s43, 16 +; SI-NEXT: s_lshr_b32 s61, s47, 16 ; SI-NEXT: s_add_u32 s24, s24, 3 -; SI-NEXT: s_addc_u32 s25, s25, 0 +; SI-NEXT: s_addc_u32 s56, s56, 0 ; SI-NEXT: s_lshr_b32 s62, s24, 16 -; SI-NEXT: s_lshr_b32 s63, s25, 16 -; SI-NEXT: s_add_u32 s26, s26, 3 +; SI-NEXT: s_lshr_b32 s63, s56, 16 +; SI-NEXT: s_add_u32 s25, s25, 3 ; SI-NEXT: s_addc_u32 s27, s27, 0 -; SI-NEXT: s_lshr_b32 s72, s26, 16 +; SI-NEXT: s_lshr_b32 s72, s25, 16 ; SI-NEXT: s_lshr_b32 s73, s27, 16 -; SI-NEXT: s_add_u32 s28, s28, 3 -; SI-NEXT: s_addc_u32 s29, s29, 0 -; SI-NEXT: s_lshr_b32 s74, s28, 16 -; SI-NEXT: s_lshr_b32 s75, s29, 16 -; SI-NEXT: s_add_u32 s46, s46, 3 -; SI-NEXT: s_addc_u32 s47, s47, 0 -; SI-NEXT: s_lshr_b32 s76, s46, 16 -; SI-NEXT: s_lshr_b32 s77, s47, 16 -; SI-NEXT: s_add_u32 s44, s44, 3 -; SI-NEXT: s_addc_u32 s45, s45, 0 -; SI-NEXT: s_lshr_b32 s78, s44, 16 -; SI-NEXT: s_lshr_b32 s79, s45, 16 -; SI-NEXT: s_add_u32 s42, s42, 3 -; SI-NEXT: s_addc_u32 s43, s43, 0 -; SI-NEXT: s_lshr_b32 s88, s42, 16 -; SI-NEXT: s_lshr_b32 s89, s43, 16 -; SI-NEXT: s_add_u32 s40, s40, 3 -; SI-NEXT: s_addc_u32 s41, s41, 0 -; SI-NEXT: s_lshr_b32 s90, s40, 16 -; SI-NEXT: s_lshr_b32 s91, s41, 16 +; SI-NEXT: s_add_u32 s26, s26, 3 +; SI-NEXT: s_addc_u32 s28, s28, 0 +; SI-NEXT: s_lshr_b32 s74, s26, 16 +; SI-NEXT: s_lshr_b32 s75, s28, 16 +; SI-NEXT: s_add_u32 s22, s22, 3 +; SI-NEXT: s_addc_u32 s23, s23, 0 +; SI-NEXT: s_lshr_b32 s76, s22, 16 +; SI-NEXT: s_lshr_b32 s77, s23, 16 +; SI-NEXT: s_add_u32 s20, s20, 3 +; SI-NEXT: s_addc_u32 s21, s21, 0 +; SI-NEXT: s_lshr_b32 s78, s20, 16 +; SI-NEXT: s_lshr_b32 s79, s21, 16 +; SI-NEXT: s_add_u32 s18, s18, 3 +; SI-NEXT: s_addc_u32 s19, s19, 0 +; SI-NEXT: s_lshr_b32 s88, s18, 16 +; SI-NEXT: s_lshr_b32 s89, s19, 16 +; SI-NEXT: s_add_u32 s16, s16, 3 +; SI-NEXT: s_addc_u32 s17, s17, 0 +; SI-NEXT: s_lshr_b32 s90, s16, 16 +; SI-NEXT: s_lshr_b32 s91, s17, 16 ; SI-NEXT: s_add_u32 s14, s14, 3 ; SI-NEXT: s_addc_u32 s15, s15, 0 ; SI-NEXT: s_lshr_b32 s92, s14, 16 @@ -106113,26 +104980,26 @@ define inreg <64 x half> @bitcast_v16i64_to_v64f16_scalar(<16 x i64> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v18, s12 ; SI-NEXT: v_cvt_f32_f16_e32 v20, s15 ; SI-NEXT: v_cvt_f32_f16_e32 v22, s14 -; SI-NEXT: v_cvt_f32_f16_e32 v24, s41 -; SI-NEXT: v_cvt_f32_f16_e32 v25, s40 -; SI-NEXT: v_cvt_f32_f16_e32 v27, s43 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s42 -; SI-NEXT: v_cvt_f32_f16_e32 v31, s45 -; SI-NEXT: v_cvt_f32_f16_e32 v33, s44 -; SI-NEXT: v_cvt_f32_f16_e32 v35, s47 -; SI-NEXT: v_cvt_f32_f16_e32 v37, s46 -; SI-NEXT: v_cvt_f32_f16_e32 v39, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v49, s28 +; SI-NEXT: v_cvt_f32_f16_e32 v24, s17 +; SI-NEXT: v_cvt_f32_f16_e32 v25, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v27, s19 +; SI-NEXT: v_cvt_f32_f16_e32 v29, s18 +; SI-NEXT: v_cvt_f32_f16_e32 v31, s21 +; SI-NEXT: v_cvt_f32_f16_e32 v33, s20 +; SI-NEXT: v_cvt_f32_f16_e32 v35, s23 +; SI-NEXT: v_cvt_f32_f16_e32 v37, s22 +; SI-NEXT: v_cvt_f32_f16_e32 v39, s28 +; SI-NEXT: v_cvt_f32_f16_e32 v49, s26 ; SI-NEXT: v_cvt_f32_f16_e32 v50, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v52, s26 -; SI-NEXT: v_cvt_f32_f16_e32 v54, s25 +; SI-NEXT: v_cvt_f32_f16_e32 v52, s25 +; SI-NEXT: v_cvt_f32_f16_e32 v54, s56 ; SI-NEXT: v_cvt_f32_f16_e32 v40, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v42, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v44, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v46, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v56, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v60, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v62, s18 +; SI-NEXT: v_cvt_f32_f16_e32 v42, s47 +; SI-NEXT: v_cvt_f32_f16_e32 v44, s43 +; SI-NEXT: v_cvt_f32_f16_e32 v46, s46 +; SI-NEXT: v_cvt_f32_f16_e32 v56, s42 +; SI-NEXT: v_cvt_f32_f16_e32 v60, s44 +; SI-NEXT: v_cvt_f32_f16_e32 v62, s41 ; SI-NEXT: v_cvt_f32_f16_e32 v1, s5 ; SI-NEXT: v_cvt_f32_f16_e32 v2, s4 ; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill @@ -106164,9 +105031,9 @@ define inreg <64 x half> @bitcast_v16i64_to_v64f16_scalar(<16 x i64> inreg %a, i ; SI-NEXT: v_cvt_f32_f16_e32 v45, s59 ; SI-NEXT: v_cvt_f32_f16_e32 v47, s58 ; SI-NEXT: v_cvt_f32_f16_e32 v57, s57 -; SI-NEXT: v_cvt_f32_f16_e32 v58, s56 -; SI-NEXT: v_cvt_f32_f16_e32 v59, s17 -; SI-NEXT: v_cvt_f32_f16_e32 v61, s16 +; SI-NEXT: v_cvt_f32_f16_e32 v58, s45 +; SI-NEXT: v_cvt_f32_f16_e32 v59, s40 +; SI-NEXT: v_cvt_f32_f16_e32 v61, s29 ; SI-NEXT: .LBB65_3: ; %end ; SI-NEXT: s_waitcnt expcnt(1) ; SI-NEXT: v_cvt_f16_f32_e32 v61, v61 @@ -108630,252 +107497,80 @@ define inreg <16 x i64> @bitcast_v64f16_to_v16i64_scalar(<64 x half> inreg %a, i ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292 -; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288 -; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284 -; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280 -; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276 -; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272 -; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268 -; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264 -; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260 -; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256 -; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252 -; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248 -; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244 -; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240 -; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236 -; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232 -; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228 -; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224 -; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220 -; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216 -; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212 -; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208 -; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204 -; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200 -; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196 -; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192 -; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188 -; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184 -; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180 -; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176 -; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172 -; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164 -; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160 -; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156 -; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152 -; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148 -; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144 -; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140 -; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136 -; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132 -; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128 -; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124 -; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120 -; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116 -; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112 -; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108 -; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104 -; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100 -; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96 -; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92 -; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88 -; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84 -; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80 -; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76 -; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72 -; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68 -; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64 -; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60 -; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56 -; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52 -; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48 -; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44 -; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40 -; GFX11-NEXT: s_clause 0x9 ; 40-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36 -; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32 -; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28 -; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24 -; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20 -; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16 -; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12 -; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8 -; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4 -; GFX11-NEXT: scratch_store_b32 off, v185, s32 -; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12 -; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10 -; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8 -; GFX11-NEXT: v_dual_mov_b32 v182, v7 :: v_dual_mov_b32 v183, v6 -; GFX11-NEXT: v_dual_mov_b32 v170, v5 :: v_dual_mov_b32 v171, v4 -; GFX11-NEXT: v_dual_mov_b32 v172, v3 :: v_dual_mov_b32 v173, v2 -; GFX11-NEXT: v_dual_mov_b32 v174, v1 :: v_dual_mov_b32 v175, v0 -; GFX11-NEXT: v_dual_mov_b32 v184, s28 :: v_dual_mov_b32 v185, s29 +; GFX11-NEXT: v_dual_mov_b32 v31, v13 :: v_dual_mov_b32 v30, v12 +; GFX11-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 +; GFX11-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 ; GFX11-NEXT: s_mov_b32 s4, 0 ; GFX11-NEXT: s_and_b32 s5, vcc_lo, exec_lo ; GFX11-NEXT: s_cbranch_scc0 .LBB67_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: v_dual_mov_b32 v47, s0 :: v_dual_mov_b32 v52, s2 -; GFX11-NEXT: v_dual_mov_b32 v49, s1 :: v_dual_mov_b32 v56, s3 -; GFX11-NEXT: v_dual_mov_b32 v61, s16 :: v_dual_mov_b32 v74, s18 -; GFX11-NEXT: v_dual_mov_b32 v67, s17 :: v_dual_mov_b32 v82, s19 -; GFX11-NEXT: v_dual_mov_b32 v91, s20 :: v_dual_mov_b32 v112, s22 -; GFX11-NEXT: v_dual_mov_b32 v101, s21 :: v_dual_mov_b32 v124, s23 -; GFX11-NEXT: v_dual_mov_b32 v137, s24 :: v_dual_mov_b32 v14, s26 -; GFX11-NEXT: v_dual_mov_b32 v151, s25 :: v_dual_mov_b32 v30, s27 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 +; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 +; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 +; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 +; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 +; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4 ; GFX11-NEXT: s_cbranch_vccnz .LBB67_3 ; GFX11-NEXT: .LBB67_2: ; %cmp.true -; GFX11-NEXT: v_pk_add_f16 v30, 0x200, s27 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s27 op_sel_hi:[0,1] ; GFX11-NEXT: v_pk_add_f16 v14, 0x200, s26 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v176, 0x200, v176 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v177, 0x200, v177 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v178, 0x200, v178 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v179, 0x200, v179 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v180, 0x200, v180 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v181, 0x200, v181 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v182, 0x200, v182 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v183, 0x200, v183 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v170, 0x200, v170 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v171, 0x200, v171 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v172, 0x200, v172 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v173, 0x200, v173 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v174, 0x200, v174 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v175, 0x200, v175 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v185, 0x200, v185 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v184, 0x200, v184 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v151, 0x200, s25 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v137, 0x200, s24 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v124, 0x200, s23 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v112, 0x200, s22 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v101, 0x200, s21 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v91, 0x200, s20 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v82, 0x200, s19 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v74, 0x200, s18 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v67, 0x200, s17 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v61, 0x200, s16 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v56, 0x200, s3 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v52, 0x200, s2 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v49, 0x200, s1 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v47, 0x200, s0 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s25 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s24 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s23 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s22 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s21 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v31, 0x200, v31 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v30, 0x200, v30 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1] ; GFX11-NEXT: .LBB67_3: ; %end -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_dual_mov_b32 v0, v47 :: v_dual_mov_b32 v1, v49 -; GFX11-NEXT: v_dual_mov_b32 v3, v56 :: v_dual_mov_b32 v4, v61 -; GFX11-NEXT: v_dual_mov_b32 v6, v74 :: v_dual_mov_b32 v9, v101 -; GFX11-NEXT: v_dual_mov_b32 v7, v82 :: v_dual_mov_b32 v8, v91 -; GFX11-NEXT: v_dual_mov_b32 v11, v124 :: v_dual_mov_b32 v12, v137 -; GFX11-NEXT: v_dual_mov_b32 v15, v30 :: v_dual_mov_b32 v16, v184 -; GFX11-NEXT: v_dual_mov_b32 v17, v185 :: v_dual_mov_b32 v18, v175 -; GFX11-NEXT: v_dual_mov_b32 v19, v174 :: v_dual_mov_b32 v20, v173 -; GFX11-NEXT: v_dual_mov_b32 v21, v172 :: v_dual_mov_b32 v22, v171 -; GFX11-NEXT: v_dual_mov_b32 v23, v170 :: v_dual_mov_b32 v24, v183 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v185, off, s32 -; GFX11-NEXT: scratch_load_b32 v184, off, s32 offset:4 -; GFX11-NEXT: scratch_load_b32 v175, off, s32 offset:8 -; GFX11-NEXT: scratch_load_b32 v174, off, s32 offset:12 -; GFX11-NEXT: scratch_load_b32 v173, off, s32 offset:16 -; GFX11-NEXT: scratch_load_b32 v172, off, s32 offset:20 -; GFX11-NEXT: scratch_load_b32 v171, off, s32 offset:24 -; GFX11-NEXT: scratch_load_b32 v170, off, s32 offset:28 -; GFX11-NEXT: scratch_load_b32 v169, off, s32 offset:32 -; GFX11-NEXT: scratch_load_b32 v168, off, s32 offset:36 -; GFX11-NEXT: scratch_load_b32 v159, off, s32 offset:40 -; GFX11-NEXT: scratch_load_b32 v158, off, s32 offset:44 -; GFX11-NEXT: scratch_load_b32 v157, off, s32 offset:48 -; GFX11-NEXT: scratch_load_b32 v156, off, s32 offset:52 -; GFX11-NEXT: scratch_load_b32 v155, off, s32 offset:56 -; GFX11-NEXT: scratch_load_b32 v154, off, s32 offset:60 -; GFX11-NEXT: scratch_load_b32 v153, off, s32 offset:64 -; GFX11-NEXT: scratch_load_b32 v152, off, s32 offset:68 -; GFX11-NEXT: scratch_load_b32 v143, off, s32 offset:72 -; GFX11-NEXT: scratch_load_b32 v142, off, s32 offset:76 -; GFX11-NEXT: scratch_load_b32 v141, off, s32 offset:80 -; GFX11-NEXT: scratch_load_b32 v140, off, s32 offset:84 -; GFX11-NEXT: scratch_load_b32 v139, off, s32 offset:88 -; GFX11-NEXT: scratch_load_b32 v138, off, s32 offset:92 -; GFX11-NEXT: scratch_load_b32 v137, off, s32 offset:96 -; GFX11-NEXT: scratch_load_b32 v136, off, s32 offset:100 -; GFX11-NEXT: scratch_load_b32 v127, off, s32 offset:104 -; GFX11-NEXT: scratch_load_b32 v126, off, s32 offset:108 -; GFX11-NEXT: scratch_load_b32 v125, off, s32 offset:112 -; GFX11-NEXT: scratch_load_b32 v124, off, s32 offset:116 -; GFX11-NEXT: scratch_load_b32 v123, off, s32 offset:120 -; GFX11-NEXT: scratch_load_b32 v122, off, s32 offset:124 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v121, off, s32 offset:128 -; GFX11-NEXT: scratch_load_b32 v120, off, s32 offset:132 -; GFX11-NEXT: scratch_load_b32 v111, off, s32 offset:136 -; GFX11-NEXT: scratch_load_b32 v110, off, s32 offset:140 -; GFX11-NEXT: scratch_load_b32 v109, off, s32 offset:144 -; GFX11-NEXT: scratch_load_b32 v108, off, s32 offset:148 -; GFX11-NEXT: scratch_load_b32 v107, off, s32 offset:152 -; GFX11-NEXT: scratch_load_b32 v106, off, s32 offset:156 -; GFX11-NEXT: scratch_load_b32 v105, off, s32 offset:160 -; GFX11-NEXT: scratch_load_b32 v104, off, s32 offset:164 -; GFX11-NEXT: scratch_load_b32 v95, off, s32 offset:168 -; GFX11-NEXT: scratch_load_b32 v94, off, s32 offset:172 -; GFX11-NEXT: scratch_load_b32 v93, off, s32 offset:176 -; GFX11-NEXT: scratch_load_b32 v92, off, s32 offset:180 -; GFX11-NEXT: scratch_load_b32 v91, off, s32 offset:184 -; GFX11-NEXT: scratch_load_b32 v90, off, s32 offset:188 -; GFX11-NEXT: scratch_load_b32 v89, off, s32 offset:192 -; GFX11-NEXT: scratch_load_b32 v88, off, s32 offset:196 -; GFX11-NEXT: scratch_load_b32 v79, off, s32 offset:200 -; GFX11-NEXT: scratch_load_b32 v78, off, s32 offset:204 -; GFX11-NEXT: scratch_load_b32 v77, off, s32 offset:208 -; GFX11-NEXT: scratch_load_b32 v76, off, s32 offset:212 -; GFX11-NEXT: scratch_load_b32 v75, off, s32 offset:216 -; GFX11-NEXT: scratch_load_b32 v74, off, s32 offset:220 -; GFX11-NEXT: scratch_load_b32 v73, off, s32 offset:224 -; GFX11-NEXT: scratch_load_b32 v72, off, s32 offset:228 -; GFX11-NEXT: scratch_load_b32 v63, off, s32 offset:232 -; GFX11-NEXT: scratch_load_b32 v62, off, s32 offset:236 -; GFX11-NEXT: scratch_load_b32 v61, off, s32 offset:240 -; GFX11-NEXT: scratch_load_b32 v60, off, s32 offset:244 -; GFX11-NEXT: scratch_load_b32 v59, off, s32 offset:248 -; GFX11-NEXT: scratch_load_b32 v58, off, s32 offset:252 -; GFX11-NEXT: s_clause 0x9 ; 40-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v57, off, s32 offset:256 -; GFX11-NEXT: scratch_load_b32 v56, off, s32 offset:260 -; GFX11-NEXT: scratch_load_b32 v47, off, s32 offset:264 -; GFX11-NEXT: scratch_load_b32 v46, off, s32 offset:268 -; GFX11-NEXT: scratch_load_b32 v45, off, s32 offset:272 -; GFX11-NEXT: scratch_load_b32 v44, off, s32 offset:276 -; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:280 -; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:284 -; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:288 -; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:292 -; GFX11-NEXT: v_dual_mov_b32 v2, v52 :: v_dual_mov_b32 v5, v67 -; GFX11-NEXT: v_dual_mov_b32 v10, v112 :: v_dual_mov_b32 v13, v151 -; GFX11-NEXT: v_dual_mov_b32 v25, v182 :: v_dual_mov_b32 v26, v181 -; GFX11-NEXT: v_dual_mov_b32 v27, v180 :: v_dual_mov_b32 v28, v179 -; GFX11-NEXT: v_dual_mov_b32 v29, v178 :: v_dual_mov_b32 v30, v177 -; GFX11-NEXT: v_mov_b32_e32 v31, v176 -; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: .LBB67_4: -; GFX11-NEXT: ; implicit-def: $vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78 -; GFX11-NEXT: ; implicit-def: $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79 -; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-NEXT: ; implicit-def: $vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81 -; GFX11-NEXT: ; implicit-def: $vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84 -; GFX11-NEXT: ; implicit-def: $vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88 -; GFX11-NEXT: ; implicit-def: $vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93 -; GFX11-NEXT: ; implicit-def: $vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99 -; GFX11-NEXT: ; implicit-def: $vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106 -; GFX11-NEXT: ; implicit-def: $vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114 -; GFX11-NEXT: ; implicit-def: $vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123 -; GFX11-NEXT: ; implicit-def: $vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133 -; GFX11-NEXT: ; implicit-def: $vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144 -; GFX11-NEXT: ; implicit-def: $vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156 -; GFX11-NEXT: ; implicit-def: $vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169 +; GFX11-NEXT: ; implicit-def: $vgpr0 +; GFX11-NEXT: ; implicit-def: $vgpr1 +; GFX11-NEXT: ; implicit-def: $vgpr2 +; GFX11-NEXT: ; implicit-def: $vgpr3 +; GFX11-NEXT: ; implicit-def: $vgpr4 +; GFX11-NEXT: ; implicit-def: $vgpr5 +; GFX11-NEXT: ; implicit-def: $vgpr6 +; GFX11-NEXT: ; implicit-def: $vgpr7 +; GFX11-NEXT: ; implicit-def: $vgpr8 +; GFX11-NEXT: ; implicit-def: $vgpr9 +; GFX11-NEXT: ; implicit-def: $vgpr10 +; GFX11-NEXT: ; implicit-def: $vgpr11 +; GFX11-NEXT: ; implicit-def: $vgpr12 +; GFX11-NEXT: ; implicit-def: $vgpr13 +; GFX11-NEXT: ; implicit-def: $vgpr14 +; GFX11-NEXT: ; implicit-def: $vgpr15 ; GFX11-NEXT: s_branch .LBB67_2 %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -109463,37 +108158,65 @@ define inreg <64 x i16> @bitcast_v16i64_to_v64i16_scalar(<16 x i64> inreg %a, i3 ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v20, s30, 0 -; SI-NEXT: v_writelane_b32 v20, s31, 1 -; SI-NEXT: v_writelane_b32 v20, s34, 2 -; SI-NEXT: v_writelane_b32 v20, s35, 3 -; SI-NEXT: v_writelane_b32 v20, s36, 4 -; SI-NEXT: v_writelane_b32 v20, s37, 5 -; SI-NEXT: v_writelane_b32 v20, s38, 6 -; SI-NEXT: v_writelane_b32 v20, s39, 7 -; SI-NEXT: v_writelane_b32 v20, s48, 8 -; SI-NEXT: v_writelane_b32 v20, s49, 9 -; SI-NEXT: v_writelane_b32 v20, s50, 10 -; SI-NEXT: v_writelane_b32 v20, s51, 11 -; SI-NEXT: v_writelane_b32 v20, s52, 12 -; SI-NEXT: v_writelane_b32 v20, s53, 13 -; SI-NEXT: v_writelane_b32 v20, s54, 14 -; SI-NEXT: v_writelane_b32 v20, s55, 15 -; SI-NEXT: v_writelane_b32 v20, s64, 16 -; SI-NEXT: v_writelane_b32 v20, s65, 17 -; SI-NEXT: v_writelane_b32 v20, s66, 18 -; SI-NEXT: v_writelane_b32 v20, s67, 19 +; SI-NEXT: v_writelane_b32 v21, s30, 0 +; SI-NEXT: v_writelane_b32 v21, s31, 1 +; SI-NEXT: v_writelane_b32 v21, s34, 2 +; SI-NEXT: v_writelane_b32 v21, s35, 3 +; SI-NEXT: v_writelane_b32 v21, s36, 4 +; SI-NEXT: v_writelane_b32 v21, s37, 5 +; SI-NEXT: v_writelane_b32 v21, s38, 6 +; SI-NEXT: v_mov_b32_e32 v20, s16 +; SI-NEXT: v_writelane_b32 v21, s39, 7 +; SI-NEXT: v_readfirstlane_b32 s56, v20 +; SI-NEXT: v_mov_b32_e32 v20, s17 +; SI-NEXT: v_writelane_b32 v21, s48, 8 +; SI-NEXT: v_readfirstlane_b32 s57, v20 +; SI-NEXT: v_mov_b32_e32 v20, s18 +; SI-NEXT: v_writelane_b32 v21, s49, 9 +; SI-NEXT: v_readfirstlane_b32 s46, v20 +; SI-NEXT: v_mov_b32_e32 v20, s19 +; SI-NEXT: v_writelane_b32 v21, s50, 10 +; SI-NEXT: v_readfirstlane_b32 s47, v20 +; SI-NEXT: v_mov_b32_e32 v20, s20 +; SI-NEXT: v_writelane_b32 v21, s51, 11 +; SI-NEXT: v_readfirstlane_b32 s44, v20 +; SI-NEXT: v_mov_b32_e32 v20, s21 +; SI-NEXT: v_writelane_b32 v21, s52, 12 +; SI-NEXT: v_readfirstlane_b32 s45, v20 +; SI-NEXT: v_mov_b32_e32 v20, s22 +; SI-NEXT: v_writelane_b32 v21, s53, 13 +; SI-NEXT: v_readfirstlane_b32 s42, v20 +; SI-NEXT: v_mov_b32_e32 v20, s23 +; SI-NEXT: v_writelane_b32 v21, s54, 14 +; SI-NEXT: v_readfirstlane_b32 s43, v20 +; SI-NEXT: v_mov_b32_e32 v20, s24 +; SI-NEXT: v_writelane_b32 v21, s55, 15 +; SI-NEXT: v_readfirstlane_b32 s40, v20 +; SI-NEXT: v_mov_b32_e32 v20, s25 +; SI-NEXT: v_writelane_b32 v21, s64, 16 +; SI-NEXT: v_readfirstlane_b32 s41, v20 +; SI-NEXT: v_mov_b32_e32 v20, s26 +; SI-NEXT: v_writelane_b32 v21, s65, 17 +; SI-NEXT: v_readfirstlane_b32 s24, v20 +; SI-NEXT: v_mov_b32_e32 v20, s27 +; SI-NEXT: v_writelane_b32 v21, s66, 18 +; SI-NEXT: v_readfirstlane_b32 s25, v20 +; SI-NEXT: v_mov_b32_e32 v20, s28 +; SI-NEXT: v_writelane_b32 v21, s67, 19 +; SI-NEXT: v_readfirstlane_b32 s22, v20 +; SI-NEXT: v_mov_b32_e32 v20, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_writelane_b32 v20, s68, 20 -; SI-NEXT: v_readfirstlane_b32 s44, v1 -; SI-NEXT: v_readfirstlane_b32 s45, v2 -; SI-NEXT: v_readfirstlane_b32 s42, v3 -; SI-NEXT: v_readfirstlane_b32 s43, v4 -; SI-NEXT: v_readfirstlane_b32 s40, v5 -; SI-NEXT: v_readfirstlane_b32 s41, v6 +; SI-NEXT: v_writelane_b32 v21, s68, 20 +; SI-NEXT: v_readfirstlane_b32 s23, v20 +; SI-NEXT: v_readfirstlane_b32 s20, v1 +; SI-NEXT: v_readfirstlane_b32 s21, v2 +; SI-NEXT: v_readfirstlane_b32 s18, v3 +; SI-NEXT: v_readfirstlane_b32 s19, v4 +; SI-NEXT: v_readfirstlane_b32 s16, v5 +; SI-NEXT: v_readfirstlane_b32 s17, v6 ; SI-NEXT: v_readfirstlane_b32 s14, v7 ; SI-NEXT: v_readfirstlane_b32 s15, v8 ; SI-NEXT: v_readfirstlane_b32 s12, v9 @@ -109505,9 +108228,9 @@ define inreg <64 x i16> @bitcast_v16i64_to_v64i16_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: v_readfirstlane_b32 s6, v15 ; SI-NEXT: v_readfirstlane_b32 s7, v16 ; SI-NEXT: v_readfirstlane_b32 s4, v17 -; SI-NEXT: s_and_b64 s[46:47], vcc, exec +; SI-NEXT: s_and_b64 s[26:27], vcc, exec ; SI-NEXT: v_readfirstlane_b32 s5, v18 -; SI-NEXT: v_writelane_b32 v20, s69, 21 +; SI-NEXT: v_writelane_b32 v21, s69, 21 ; SI-NEXT: s_cbranch_scc0 .LBB69_4 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshr_b32 s38, s5, 16 @@ -109516,32 +108239,32 @@ define inreg <64 x i16> @bitcast_v16i64_to_v64i16_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: s_lshr_b32 s49, s11, 16 ; SI-NEXT: s_lshr_b32 s50, s13, 16 ; SI-NEXT: s_lshr_b32 s51, s15, 16 -; SI-NEXT: s_lshr_b32 s52, s41, 16 -; SI-NEXT: s_lshr_b32 s53, s43, 16 -; SI-NEXT: s_lshr_b32 s54, s45, 16 -; SI-NEXT: s_lshr_b32 s55, s29, 16 -; SI-NEXT: s_lshr_b32 s64, s27, 16 -; SI-NEXT: s_lshr_b32 s65, s25, 16 -; SI-NEXT: s_lshr_b32 s66, s23, 16 -; SI-NEXT: s_lshr_b32 s67, s21, 16 -; SI-NEXT: s_lshr_b32 s68, s19, 16 -; SI-NEXT: s_lshr_b32 s69, s17, 16 -; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[56:57], s[6:7], 16 +; SI-NEXT: s_lshr_b32 s52, s17, 16 +; SI-NEXT: s_lshr_b32 s53, s19, 16 +; SI-NEXT: s_lshr_b32 s54, s21, 16 +; SI-NEXT: s_lshr_b32 s55, s23, 16 +; SI-NEXT: s_lshr_b32 s64, s25, 16 +; SI-NEXT: s_lshr_b32 s65, s41, 16 +; SI-NEXT: s_lshr_b32 s66, s43, 16 +; SI-NEXT: s_lshr_b32 s67, s45, 16 +; SI-NEXT: s_lshr_b32 s68, s47, 16 +; SI-NEXT: s_lshr_b32 s69, s57, 16 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[6:7], 16 ; SI-NEXT: s_lshr_b64 s[58:59], s[8:9], 16 ; SI-NEXT: s_lshr_b64 s[60:61], s[10:11], 16 ; SI-NEXT: s_lshr_b64 s[62:63], s[12:13], 16 ; SI-NEXT: s_lshr_b64 s[72:73], s[14:15], 16 -; SI-NEXT: s_lshr_b64 s[74:75], s[40:41], 16 -; SI-NEXT: s_lshr_b64 s[76:77], s[42:43], 16 -; SI-NEXT: s_lshr_b64 s[78:79], s[44:45], 16 -; SI-NEXT: s_lshr_b64 s[88:89], s[28:29], 16 -; SI-NEXT: s_lshr_b64 s[90:91], s[26:27], 16 -; SI-NEXT: s_lshr_b64 s[92:93], s[24:25], 16 -; SI-NEXT: s_lshr_b64 s[94:95], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[30:31], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[34:35], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[36:37], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[74:75], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[76:77], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[78:79], s[20:21], 16 +; SI-NEXT: s_lshr_b64 s[88:89], s[22:23], 16 +; SI-NEXT: s_lshr_b64 s[90:91], s[24:25], 16 +; SI-NEXT: s_lshr_b64 s[92:93], s[40:41], 16 +; SI-NEXT: s_lshr_b64 s[94:95], s[42:43], 16 +; SI-NEXT: s_lshr_b64 s[30:31], s[44:45], 16 +; SI-NEXT: s_lshr_b64 s[34:35], s[46:47], 16 +; SI-NEXT: s_lshr_b64 s[36:37], s[56:57], 16 ; SI-NEXT: s_cbranch_execnz .LBB69_3 ; SI-NEXT: .LBB69_2: ; %cmp.true ; SI-NEXT: s_add_u32 s4, s4, 3 @@ -109556,186 +108279,186 @@ define inreg <64 x i16> @bitcast_v16i64_to_v64i16_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: s_addc_u32 s13, s13, 0 ; SI-NEXT: s_add_u32 s14, s14, 3 ; SI-NEXT: s_addc_u32 s15, s15, 0 +; SI-NEXT: s_add_u32 s16, s16, 3 +; SI-NEXT: s_addc_u32 s17, s17, 0 +; SI-NEXT: s_add_u32 s18, s18, 3 +; SI-NEXT: s_addc_u32 s19, s19, 0 +; SI-NEXT: s_add_u32 s20, s20, 3 +; SI-NEXT: s_addc_u32 s21, s21, 0 +; SI-NEXT: s_add_u32 s22, s22, 3 +; SI-NEXT: s_addc_u32 s23, s23, 0 +; SI-NEXT: s_add_u32 s24, s24, 3 +; SI-NEXT: s_addc_u32 s25, s25, 0 ; SI-NEXT: s_add_u32 s40, s40, 3 ; SI-NEXT: s_addc_u32 s41, s41, 0 ; SI-NEXT: s_add_u32 s42, s42, 3 ; SI-NEXT: s_addc_u32 s43, s43, 0 ; SI-NEXT: s_add_u32 s44, s44, 3 ; SI-NEXT: s_addc_u32 s45, s45, 0 -; SI-NEXT: s_add_u32 s28, s28, 3 -; SI-NEXT: s_addc_u32 s29, s29, 0 -; SI-NEXT: s_add_u32 s26, s26, 3 -; SI-NEXT: s_addc_u32 s27, s27, 0 -; SI-NEXT: s_add_u32 s24, s24, 3 -; SI-NEXT: s_addc_u32 s25, s25, 0 -; SI-NEXT: s_add_u32 s22, s22, 3 -; SI-NEXT: s_addc_u32 s23, s23, 0 -; SI-NEXT: s_add_u32 s20, s20, 3 -; SI-NEXT: s_addc_u32 s21, s21, 0 -; SI-NEXT: s_add_u32 s18, s18, 3 -; SI-NEXT: s_addc_u32 s19, s19, 0 -; SI-NEXT: s_add_u32 s16, s16, 3 -; SI-NEXT: s_addc_u32 s17, s17, 0 +; SI-NEXT: s_add_u32 s46, s46, 3 +; SI-NEXT: s_addc_u32 s47, s47, 0 +; SI-NEXT: s_add_u32 s56, s56, 3 +; SI-NEXT: s_addc_u32 s57, s57, 0 ; SI-NEXT: s_lshr_b32 s38, s5, 16 ; SI-NEXT: s_lshr_b32 s39, s7, 16 ; SI-NEXT: s_lshr_b32 s48, s9, 16 ; SI-NEXT: s_lshr_b32 s49, s11, 16 ; SI-NEXT: s_lshr_b32 s50, s13, 16 ; SI-NEXT: s_lshr_b32 s51, s15, 16 -; SI-NEXT: s_lshr_b32 s52, s41, 16 -; SI-NEXT: s_lshr_b32 s53, s43, 16 -; SI-NEXT: s_lshr_b32 s54, s45, 16 -; SI-NEXT: s_lshr_b32 s55, s29, 16 -; SI-NEXT: s_lshr_b32 s64, s27, 16 -; SI-NEXT: s_lshr_b32 s65, s25, 16 -; SI-NEXT: s_lshr_b32 s66, s23, 16 -; SI-NEXT: s_lshr_b32 s67, s21, 16 -; SI-NEXT: s_lshr_b32 s68, s19, 16 -; SI-NEXT: s_lshr_b32 s69, s17, 16 -; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[56:57], s[6:7], 16 +; SI-NEXT: s_lshr_b32 s52, s17, 16 +; SI-NEXT: s_lshr_b32 s53, s19, 16 +; SI-NEXT: s_lshr_b32 s54, s21, 16 +; SI-NEXT: s_lshr_b32 s55, s23, 16 +; SI-NEXT: s_lshr_b32 s64, s25, 16 +; SI-NEXT: s_lshr_b32 s65, s41, 16 +; SI-NEXT: s_lshr_b32 s66, s43, 16 +; SI-NEXT: s_lshr_b32 s67, s45, 16 +; SI-NEXT: s_lshr_b32 s68, s47, 16 +; SI-NEXT: s_lshr_b32 s69, s57, 16 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[6:7], 16 ; SI-NEXT: s_lshr_b64 s[58:59], s[8:9], 16 ; SI-NEXT: s_lshr_b64 s[60:61], s[10:11], 16 ; SI-NEXT: s_lshr_b64 s[62:63], s[12:13], 16 ; SI-NEXT: s_lshr_b64 s[72:73], s[14:15], 16 -; SI-NEXT: s_lshr_b64 s[74:75], s[40:41], 16 -; SI-NEXT: s_lshr_b64 s[76:77], s[42:43], 16 -; SI-NEXT: s_lshr_b64 s[78:79], s[44:45], 16 -; SI-NEXT: s_lshr_b64 s[88:89], s[28:29], 16 -; SI-NEXT: s_lshr_b64 s[90:91], s[26:27], 16 -; SI-NEXT: s_lshr_b64 s[92:93], s[24:25], 16 -; SI-NEXT: s_lshr_b64 s[94:95], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[30:31], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[34:35], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[36:37], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[74:75], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[76:77], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[78:79], s[20:21], 16 +; SI-NEXT: s_lshr_b64 s[88:89], s[22:23], 16 +; SI-NEXT: s_lshr_b64 s[90:91], s[24:25], 16 +; SI-NEXT: s_lshr_b64 s[92:93], s[40:41], 16 +; SI-NEXT: s_lshr_b64 s[94:95], s[42:43], 16 +; SI-NEXT: s_lshr_b64 s[30:31], s[44:45], 16 +; SI-NEXT: s_lshr_b64 s[34:35], s[46:47], 16 +; SI-NEXT: s_lshr_b64 s[36:37], s[56:57], 16 ; SI-NEXT: .LBB69_3: ; %end -; SI-NEXT: s_lshl_b32 s47, s36, 16 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_or_b32 s16, s16, s47 -; SI-NEXT: v_mov_b32_e32 v1, s16 -; SI-NEXT: s_and_b32 s16, s17, 0xffff -; SI-NEXT: s_lshl_b32 s17, s69, 16 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_lshl_b32 s16, s34, 16 -; SI-NEXT: s_and_b32 s17, s18, 0xffff -; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: v_mov_b32_e32 v3, s16 -; SI-NEXT: s_and_b32 s16, s19, 0xffff -; SI-NEXT: s_lshl_b32 s17, s68, 16 -; SI-NEXT: s_or_b32 s16, s16, s17 -; SI-NEXT: v_mov_b32_e32 v4, s16 -; SI-NEXT: s_lshl_b32 s16, s30, 16 -; SI-NEXT: s_and_b32 s17, s20, 0xffff -; SI-NEXT: s_or_b32 s16, s17, s16 +; SI-NEXT: s_lshl_b32 s27, s36, 16 +; SI-NEXT: s_and_b32 s29, s56, 0xffff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: v_mov_b32_e32 v1, s27 +; SI-NEXT: s_and_b32 s27, s57, 0xffff +; SI-NEXT: s_lshl_b32 s29, s69, 16 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_lshl_b32 s27, s34, 16 +; SI-NEXT: s_and_b32 s29, s46, 0xffff +; SI-NEXT: s_or_b32 s27, s29, s27 +; SI-NEXT: v_mov_b32_e32 v3, s27 +; SI-NEXT: s_and_b32 s27, s47, 0xffff +; SI-NEXT: s_lshl_b32 s29, s68, 16 +; SI-NEXT: s_or_b32 s27, s27, s29 +; SI-NEXT: v_mov_b32_e32 v4, s27 +; SI-NEXT: s_lshl_b32 s27, s30, 16 +; SI-NEXT: s_and_b32 s29, s44, 0xffff +; SI-NEXT: s_or_b32 s27, s29, s27 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0 -; SI-NEXT: v_mov_b32_e32 v5, s16 +; SI-NEXT: v_mov_b32_e32 v5, s27 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0 -; SI-NEXT: s_and_b32 s16, s21, 0xffff -; SI-NEXT: s_lshl_b32 s17, s67, 16 +; SI-NEXT: s_and_b32 s27, s45, 0xffff +; SI-NEXT: s_lshl_b32 s29, s67, 16 ; SI-NEXT: buffer_store_dword v3, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 12, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s27, s27, s29 ; SI-NEXT: buffer_store_dword v4, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0 ; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s22, 0xffff -; SI-NEXT: s_lshl_b32 s17, s94, 16 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_and_b32 s27, s42, 0xffff +; SI-NEXT: s_lshl_b32 s29, s94, 16 ; SI-NEXT: buffer_store_dword v5, v1, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v1, vcc, 20, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s27, s27, s29 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s23, 0xffff -; SI-NEXT: s_lshl_b32 s17, s66, 16 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_and_b32 s27, s43, 0xffff +; SI-NEXT: s_lshl_b32 s29, s66, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s27, s27, s29 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s24, 0xffff -; SI-NEXT: s_lshl_b32 s17, s92, 16 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_and_b32 s27, s40, 0xffff +; SI-NEXT: s_lshl_b32 s29, s92, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 28, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s27, s27, s29 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s25, 0xffff -; SI-NEXT: s_lshl_b32 s17, s65, 16 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_and_b32 s27, s41, 0xffff +; SI-NEXT: s_lshl_b32 s29, s65, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s27, s27, s29 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s26, 0xffff -; SI-NEXT: s_lshl_b32 s17, s90, 16 +; SI-NEXT: v_mov_b32_e32 v2, s27 +; SI-NEXT: s_and_b32 s24, s24, 0xffff +; SI-NEXT: s_lshl_b32 s27, s90, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 36, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s24, s24, s27 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s27, 0xffff -; SI-NEXT: s_lshl_b32 s17, s64, 16 +; SI-NEXT: v_mov_b32_e32 v2, s24 +; SI-NEXT: s_and_b32 s24, s25, 0xffff +; SI-NEXT: s_lshl_b32 s25, s64, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s24, s24, s25 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s28, 0xffff -; SI-NEXT: s_lshl_b32 s17, s88, 16 +; SI-NEXT: v_mov_b32_e32 v2, s24 +; SI-NEXT: s_and_b32 s22, s22, 0xffff +; SI-NEXT: s_lshl_b32 s24, s88, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 44, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s22, s22, s24 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s29, 0xffff -; SI-NEXT: s_lshl_b32 s17, s55, 16 +; SI-NEXT: v_mov_b32_e32 v2, s22 +; SI-NEXT: s_and_b32 s22, s23, 0xffff +; SI-NEXT: s_lshl_b32 s23, s55, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s22, s22, s23 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s44, 0xffff -; SI-NEXT: s_lshl_b32 s17, s78, 16 +; SI-NEXT: v_mov_b32_e32 v2, s22 +; SI-NEXT: s_and_b32 s20, s20, 0xffff +; SI-NEXT: s_lshl_b32 s22, s78, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 52, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s20, s20, s22 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s45, 0xffff -; SI-NEXT: s_lshl_b32 s17, s54, 16 +; SI-NEXT: v_mov_b32_e32 v2, s20 +; SI-NEXT: s_and_b32 s20, s21, 0xffff +; SI-NEXT: s_lshl_b32 s21, s54, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 56, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s20, s20, s21 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s42, 0xffff -; SI-NEXT: s_lshl_b32 s17, s76, 16 +; SI-NEXT: v_mov_b32_e32 v2, s20 +; SI-NEXT: s_and_b32 s18, s18, 0xffff +; SI-NEXT: s_lshl_b32 s20, s76, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 60, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s18, s18, s20 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s43, 0xffff -; SI-NEXT: s_lshl_b32 s17, s53, 16 +; SI-NEXT: v_mov_b32_e32 v2, s18 +; SI-NEXT: s_and_b32 s18, s19, 0xffff +; SI-NEXT: s_lshl_b32 s19, s53, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 64, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s18, s18, s19 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s40, 0xffff -; SI-NEXT: s_lshl_b32 s17, s74, 16 +; SI-NEXT: v_mov_b32_e32 v2, s18 +; SI-NEXT: s_and_b32 s16, s16, 0xffff +; SI-NEXT: s_lshl_b32 s18, s74, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x44, v0 -; SI-NEXT: s_or_b32 s16, s16, s17 +; SI-NEXT: s_or_b32 s16, s16, s18 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s16 -; SI-NEXT: s_and_b32 s16, s41, 0xffff +; SI-NEXT: s_and_b32 s16, s17, 0xffff ; SI-NEXT: s_lshl_b32 s17, s52, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x48, v0 ; SI-NEXT: s_or_b32 s16, s16, s17 @@ -109799,7 +108522,7 @@ define inreg <64 x i16> @bitcast_v16i64_to_v64i16_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s8 ; SI-NEXT: s_and_b32 s6, s6, 0xffff -; SI-NEXT: s_lshl_b32 s8, s56, 16 +; SI-NEXT: s_lshl_b32 s8, s28, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x6c, v0 ; SI-NEXT: s_or_b32 s6, s6, s8 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen @@ -109813,7 +108536,7 @@ define inreg <64 x i16> @bitcast_v16i64_to_v64i16_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mov_b32_e32 v2, s6 ; SI-NEXT: s_and_b32 s4, s4, 0xffff -; SI-NEXT: s_lshl_b32 s6, s46, 16 +; SI-NEXT: s_lshl_b32 s6, s26, 16 ; SI-NEXT: v_add_i32_e32 v1, vcc, 0x74, v0 ; SI-NEXT: s_or_b32 s4, s4, s6 ; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen @@ -109827,30 +108550,30 @@ define inreg <64 x i16> @bitcast_v16i64_to_v64i16_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 ; SI-NEXT: v_mov_b32_e32 v1, s4 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: v_readlane_b32 s69, v20, 21 -; SI-NEXT: v_readlane_b32 s68, v20, 20 -; SI-NEXT: v_readlane_b32 s67, v20, 19 -; SI-NEXT: v_readlane_b32 s66, v20, 18 -; SI-NEXT: v_readlane_b32 s65, v20, 17 -; SI-NEXT: v_readlane_b32 s64, v20, 16 -; SI-NEXT: v_readlane_b32 s55, v20, 15 -; SI-NEXT: v_readlane_b32 s54, v20, 14 -; SI-NEXT: v_readlane_b32 s53, v20, 13 -; SI-NEXT: v_readlane_b32 s52, v20, 12 -; SI-NEXT: v_readlane_b32 s51, v20, 11 -; SI-NEXT: v_readlane_b32 s50, v20, 10 -; SI-NEXT: v_readlane_b32 s49, v20, 9 -; SI-NEXT: v_readlane_b32 s48, v20, 8 -; SI-NEXT: v_readlane_b32 s39, v20, 7 -; SI-NEXT: v_readlane_b32 s38, v20, 6 -; SI-NEXT: v_readlane_b32 s37, v20, 5 -; SI-NEXT: v_readlane_b32 s36, v20, 4 -; SI-NEXT: v_readlane_b32 s35, v20, 3 -; SI-NEXT: v_readlane_b32 s34, v20, 2 -; SI-NEXT: v_readlane_b32 s31, v20, 1 -; SI-NEXT: v_readlane_b32 s30, v20, 0 +; SI-NEXT: v_readlane_b32 s69, v21, 21 +; SI-NEXT: v_readlane_b32 s68, v21, 20 +; SI-NEXT: v_readlane_b32 s67, v21, 19 +; SI-NEXT: v_readlane_b32 s66, v21, 18 +; SI-NEXT: v_readlane_b32 s65, v21, 17 +; SI-NEXT: v_readlane_b32 s64, v21, 16 +; SI-NEXT: v_readlane_b32 s55, v21, 15 +; SI-NEXT: v_readlane_b32 s54, v21, 14 +; SI-NEXT: v_readlane_b32 s53, v21, 13 +; SI-NEXT: v_readlane_b32 s52, v21, 12 +; SI-NEXT: v_readlane_b32 s51, v21, 11 +; SI-NEXT: v_readlane_b32 s50, v21, 10 +; SI-NEXT: v_readlane_b32 s49, v21, 9 +; SI-NEXT: v_readlane_b32 s48, v21, 8 +; SI-NEXT: v_readlane_b32 s39, v21, 7 +; SI-NEXT: v_readlane_b32 s38, v21, 6 +; SI-NEXT: v_readlane_b32 s37, v21, 5 +; SI-NEXT: v_readlane_b32 s36, v21, 4 +; SI-NEXT: v_readlane_b32 s35, v21, 3 +; SI-NEXT: v_readlane_b32 s34, v21, 2 +; SI-NEXT: v_readlane_b32 s31, v21, 1 +; SI-NEXT: v_readlane_b32 s30, v21, 0 ; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] @@ -109885,8 +108608,8 @@ define inreg <64 x i16> @bitcast_v16i64_to_v64i16_scalar(<16 x i64> inreg %a, i3 ; SI-NEXT: ; implicit-def: $sgpr39 ; SI-NEXT: ; implicit-def: $sgpr38 ; SI-NEXT: ; implicit-def: $sgpr58 -; SI-NEXT: ; implicit-def: $sgpr56 -; SI-NEXT: ; implicit-def: $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr28 +; SI-NEXT: ; implicit-def: $sgpr26 ; SI-NEXT: s_branch .LBB69_2 ; ; VI-LABEL: bitcast_v16i64_to_v64i16_scalar: @@ -111386,23 +110109,51 @@ define inreg <16 x i64> @bitcast_v64i16_to_v16i64_scalar(<64 x i16> inreg %a, i3 ; VI-LABEL: bitcast_v64i16_to_v16i64_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 +; VI-NEXT: v_mov_b32_e32 v19, s16 ; VI-NEXT: v_readfirstlane_b32 s6, v2 +; VI-NEXT: v_mov_b32_e32 v2, s17 ; VI-NEXT: v_readfirstlane_b32 s7, v3 +; VI-NEXT: v_mov_b32_e32 v3, s18 ; VI-NEXT: v_readfirstlane_b32 s8, v4 +; VI-NEXT: v_mov_b32_e32 v4, s19 ; VI-NEXT: v_readfirstlane_b32 s9, v5 +; VI-NEXT: v_mov_b32_e32 v5, s20 ; VI-NEXT: v_readfirstlane_b32 s10, v6 +; VI-NEXT: v_mov_b32_e32 v6, s21 ; VI-NEXT: v_readfirstlane_b32 s11, v7 +; VI-NEXT: v_mov_b32_e32 v7, s22 ; VI-NEXT: v_readfirstlane_b32 s12, v8 +; VI-NEXT: v_mov_b32_e32 v8, s23 ; VI-NEXT: v_readfirstlane_b32 s13, v9 +; VI-NEXT: v_mov_b32_e32 v9, s24 ; VI-NEXT: v_readfirstlane_b32 s14, v10 +; VI-NEXT: v_mov_b32_e32 v10, s25 ; VI-NEXT: v_readfirstlane_b32 s15, v11 -; VI-NEXT: v_readfirstlane_b32 s40, v12 -; VI-NEXT: v_readfirstlane_b32 s41, v13 -; VI-NEXT: v_readfirstlane_b32 s42, v14 -; VI-NEXT: v_readfirstlane_b32 s43, v15 -; VI-NEXT: v_readfirstlane_b32 s44, v16 -; VI-NEXT: v_readfirstlane_b32 s45, v17 +; VI-NEXT: v_mov_b32_e32 v11, s26 +; VI-NEXT: v_readfirstlane_b32 s16, v12 +; VI-NEXT: v_mov_b32_e32 v12, s27 +; VI-NEXT: v_readfirstlane_b32 s17, v13 +; VI-NEXT: v_mov_b32_e32 v13, s28 +; VI-NEXT: v_readfirstlane_b32 s18, v14 +; VI-NEXT: v_mov_b32_e32 v14, s29 +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 +; VI-NEXT: v_readfirstlane_b32 s19, v15 +; VI-NEXT: v_readfirstlane_b32 s20, v16 +; VI-NEXT: v_readfirstlane_b32 s21, v17 +; VI-NEXT: v_readfirstlane_b32 s22, v19 +; VI-NEXT: v_readfirstlane_b32 s23, v2 +; VI-NEXT: v_readfirstlane_b32 s24, v3 +; VI-NEXT: v_readfirstlane_b32 s25, v4 +; VI-NEXT: v_readfirstlane_b32 s26, v5 +; VI-NEXT: v_readfirstlane_b32 s27, v6 +; VI-NEXT: v_readfirstlane_b32 s28, v7 +; VI-NEXT: v_readfirstlane_b32 s29, v8 +; VI-NEXT: v_readfirstlane_b32 s40, v9 +; VI-NEXT: v_readfirstlane_b32 s41, v10 +; VI-NEXT: v_readfirstlane_b32 s42, v11 +; VI-NEXT: v_readfirstlane_b32 s43, v12 +; VI-NEXT: v_readfirstlane_b32 s44, v13 +; VI-NEXT: v_readfirstlane_b32 s45, v14 ; VI-NEXT: v_readfirstlane_b32 s46, v0 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s47, v1 @@ -111419,8 +110170,38 @@ define inreg <16 x i64> @bitcast_v64i16_to_v16i64_scalar(<64 x i16> inreg %a, i3 ; VI-NEXT: s_and_b32 s4, s46, 0xffff0000 ; VI-NEXT: s_and_b32 s5, s5, 0xffff ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s29, 3 +; VI-NEXT: s_add_i32 s5, s45, 3 ; VI-NEXT: s_add_i32 s46, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s45, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s44, 3 +; VI-NEXT: s_add_i32 s45, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s44, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s43, 3 +; VI-NEXT: s_add_i32 s44, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s43, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s42, 3 +; VI-NEXT: s_add_i32 s43, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s42, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s41, 3 +; VI-NEXT: s_add_i32 s42, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s41, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s40, 3 +; VI-NEXT: s_add_i32 s41, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s40, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s29, 3 +; VI-NEXT: s_add_i32 s40, s4, 0x30000 ; VI-NEXT: s_and_b32 s4, s29, 0xffff0000 ; VI-NEXT: s_and_b32 s5, s5, 0xffff ; VI-NEXT: s_or_b32 s4, s4, s5 @@ -111489,38 +110270,8 @@ define inreg <16 x i64> @bitcast_v64i16_to_v16i64_scalar(<64 x i16> inreg %a, i3 ; VI-NEXT: s_and_b32 s4, s16, 0xffff0000 ; VI-NEXT: s_and_b32 s5, s5, 0xffff ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s45, 3 -; VI-NEXT: s_add_i32 s16, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s45, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s44, 3 -; VI-NEXT: s_add_i32 s45, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s44, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s43, 3 -; VI-NEXT: s_add_i32 s44, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s43, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s42, 3 -; VI-NEXT: s_add_i32 s43, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s42, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s41, 3 -; VI-NEXT: s_add_i32 s42, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s41, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s40, 3 -; VI-NEXT: s_add_i32 s41, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s40, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 ; VI-NEXT: s_add_i32 s5, s15, 3 -; VI-NEXT: s_add_i32 s40, s4, 0x30000 +; VI-NEXT: s_add_i32 s16, s4, 0x30000 ; VI-NEXT: s_and_b32 s4, s15, 0xffff0000 ; VI-NEXT: s_and_b32 s5, s5, 0xffff ; VI-NEXT: s_or_b32 s4, s4, s5 @@ -111571,20 +110322,20 @@ define inreg <16 x i64> @bitcast_v64i16_to_v16i64_scalar(<64 x i16> inreg %a, i3 ; VI-NEXT: s_or_b32 s4, s4, s5 ; VI-NEXT: s_add_i32 s6, s4, 0x30000 ; VI-NEXT: .LBB71_3: ; %end -; VI-NEXT: v_mov_b32_e32 v0, s16 -; VI-NEXT: v_mov_b32_e32 v1, s17 -; VI-NEXT: v_mov_b32_e32 v2, s18 -; VI-NEXT: v_mov_b32_e32 v3, s19 -; VI-NEXT: v_mov_b32_e32 v4, s20 -; VI-NEXT: v_mov_b32_e32 v5, s21 -; VI-NEXT: v_mov_b32_e32 v6, s22 -; VI-NEXT: v_mov_b32_e32 v7, s23 -; VI-NEXT: v_mov_b32_e32 v8, s24 -; VI-NEXT: v_mov_b32_e32 v9, s25 -; VI-NEXT: v_mov_b32_e32 v10, s26 -; VI-NEXT: v_mov_b32_e32 v11, s27 -; VI-NEXT: v_mov_b32_e32 v12, s28 -; VI-NEXT: v_mov_b32_e32 v13, s29 +; VI-NEXT: v_mov_b32_e32 v0, s22 +; VI-NEXT: v_mov_b32_e32 v1, s23 +; VI-NEXT: v_mov_b32_e32 v2, s24 +; VI-NEXT: v_mov_b32_e32 v3, s25 +; VI-NEXT: v_mov_b32_e32 v4, s26 +; VI-NEXT: v_mov_b32_e32 v5, s27 +; VI-NEXT: v_mov_b32_e32 v6, s28 +; VI-NEXT: v_mov_b32_e32 v7, s29 +; VI-NEXT: v_mov_b32_e32 v8, s40 +; VI-NEXT: v_mov_b32_e32 v9, s41 +; VI-NEXT: v_mov_b32_e32 v10, s42 +; VI-NEXT: v_mov_b32_e32 v11, s43 +; VI-NEXT: v_mov_b32_e32 v12, s44 +; VI-NEXT: v_mov_b32_e32 v13, s45 ; VI-NEXT: v_mov_b32_e32 v14, s46 ; VI-NEXT: v_mov_b32_e32 v15, s47 ; VI-NEXT: v_mov_b32_e32 v16, s6 @@ -111597,12 +110348,12 @@ define inreg <16 x i64> @bitcast_v64i16_to_v16i64_scalar(<64 x i16> inreg %a, i3 ; VI-NEXT: v_mov_b32_e32 v23, s13 ; VI-NEXT: v_mov_b32_e32 v24, s14 ; VI-NEXT: v_mov_b32_e32 v25, s15 -; VI-NEXT: v_mov_b32_e32 v26, s40 -; VI-NEXT: v_mov_b32_e32 v27, s41 -; VI-NEXT: v_mov_b32_e32 v28, s42 -; VI-NEXT: v_mov_b32_e32 v29, s43 -; VI-NEXT: v_mov_b32_e32 v30, s44 -; VI-NEXT: v_mov_b32_e32 v31, s45 +; VI-NEXT: v_mov_b32_e32 v26, s16 +; VI-NEXT: v_mov_b32_e32 v27, s17 +; VI-NEXT: v_mov_b32_e32 v28, s18 +; VI-NEXT: v_mov_b32_e32 v29, s19 +; VI-NEXT: v_mov_b32_e32 v30, s20 +; VI-NEXT: v_mov_b32_e32 v31, s21 ; VI-NEXT: s_setpc_b64 s[30:31] ; VI-NEXT: .LBB71_4: ; VI-NEXT: s_branch .LBB71_2 @@ -111690,252 +110441,80 @@ define inreg <16 x i64> @bitcast_v64i16_to_v16i64_scalar(<64 x i16> inreg %a, i3 ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292 -; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288 -; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284 -; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280 -; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276 -; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272 -; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268 -; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264 -; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260 -; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256 -; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252 -; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248 -; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244 -; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240 -; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236 -; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232 -; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228 -; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224 -; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220 -; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216 -; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212 -; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208 -; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204 -; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200 -; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196 -; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192 -; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188 -; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184 -; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180 -; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176 -; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172 -; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164 -; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160 -; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156 -; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152 -; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148 -; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144 -; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140 -; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136 -; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132 -; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128 -; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124 -; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120 -; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116 -; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112 -; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108 -; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104 -; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100 -; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96 -; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92 -; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88 -; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84 -; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80 -; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76 -; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72 -; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68 -; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64 -; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60 -; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56 -; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52 -; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48 -; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44 -; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40 -; GFX11-NEXT: s_clause 0x9 ; 40-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36 -; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32 -; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28 -; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24 -; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20 -; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16 -; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12 -; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8 -; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4 -; GFX11-NEXT: scratch_store_b32 off, v185, s32 -; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12 -; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10 -; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8 -; GFX11-NEXT: v_dual_mov_b32 v182, v7 :: v_dual_mov_b32 v183, v6 -; GFX11-NEXT: v_dual_mov_b32 v170, v5 :: v_dual_mov_b32 v171, v4 -; GFX11-NEXT: v_dual_mov_b32 v172, v3 :: v_dual_mov_b32 v173, v2 -; GFX11-NEXT: v_dual_mov_b32 v174, v1 :: v_dual_mov_b32 v175, v0 -; GFX11-NEXT: v_dual_mov_b32 v184, s28 :: v_dual_mov_b32 v185, s29 +; GFX11-NEXT: v_dual_mov_b32 v31, v13 :: v_dual_mov_b32 v30, v12 +; GFX11-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 +; GFX11-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 ; GFX11-NEXT: s_mov_b32 s4, 0 ; GFX11-NEXT: s_and_b32 s5, vcc_lo, exec_lo ; GFX11-NEXT: s_cbranch_scc0 .LBB71_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: v_dual_mov_b32 v47, s0 :: v_dual_mov_b32 v52, s2 -; GFX11-NEXT: v_dual_mov_b32 v49, s1 :: v_dual_mov_b32 v56, s3 -; GFX11-NEXT: v_dual_mov_b32 v61, s16 :: v_dual_mov_b32 v74, s18 -; GFX11-NEXT: v_dual_mov_b32 v67, s17 :: v_dual_mov_b32 v82, s19 -; GFX11-NEXT: v_dual_mov_b32 v91, s20 :: v_dual_mov_b32 v112, s22 -; GFX11-NEXT: v_dual_mov_b32 v101, s21 :: v_dual_mov_b32 v124, s23 -; GFX11-NEXT: v_dual_mov_b32 v137, s24 :: v_dual_mov_b32 v14, s26 -; GFX11-NEXT: v_dual_mov_b32 v151, s25 :: v_dual_mov_b32 v30, s27 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 +; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 +; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 +; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 +; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 +; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4 ; GFX11-NEXT: s_cbranch_vccnz .LBB71_3 ; GFX11-NEXT: .LBB71_2: ; %cmp.true -; GFX11-NEXT: v_pk_add_u16 v30, s27, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v15, s27, 3 op_sel_hi:[1,0] ; GFX11-NEXT: v_pk_add_u16 v14, s26, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v176, v176, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v177, v177, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v178, v178, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v179, v179, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v180, v180, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v181, v181, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v182, v182, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v183, v183, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v170, v170, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v171, v171, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v172, v172, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v173, v173, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v174, v174, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v175, v175, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v185, v185, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v184, v184, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v151, s25, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v137, s24, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v124, s23, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v112, s22, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v101, s21, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v91, s20, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v82, s19, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v74, s18, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v67, s17, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v61, s16, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v56, s3, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v52, s2, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v49, s1, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v47, s0, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v13, s25, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v12, s24, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v11, s23, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v10, s22, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v31, v31, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v30, v30, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0] ; GFX11-NEXT: .LBB71_3: ; %end -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_dual_mov_b32 v0, v47 :: v_dual_mov_b32 v1, v49 -; GFX11-NEXT: v_dual_mov_b32 v3, v56 :: v_dual_mov_b32 v4, v61 -; GFX11-NEXT: v_dual_mov_b32 v6, v74 :: v_dual_mov_b32 v9, v101 -; GFX11-NEXT: v_dual_mov_b32 v7, v82 :: v_dual_mov_b32 v8, v91 -; GFX11-NEXT: v_dual_mov_b32 v11, v124 :: v_dual_mov_b32 v12, v137 -; GFX11-NEXT: v_dual_mov_b32 v15, v30 :: v_dual_mov_b32 v16, v184 -; GFX11-NEXT: v_dual_mov_b32 v17, v185 :: v_dual_mov_b32 v18, v175 -; GFX11-NEXT: v_dual_mov_b32 v19, v174 :: v_dual_mov_b32 v20, v173 -; GFX11-NEXT: v_dual_mov_b32 v21, v172 :: v_dual_mov_b32 v22, v171 -; GFX11-NEXT: v_dual_mov_b32 v23, v170 :: v_dual_mov_b32 v24, v183 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v185, off, s32 -; GFX11-NEXT: scratch_load_b32 v184, off, s32 offset:4 -; GFX11-NEXT: scratch_load_b32 v175, off, s32 offset:8 -; GFX11-NEXT: scratch_load_b32 v174, off, s32 offset:12 -; GFX11-NEXT: scratch_load_b32 v173, off, s32 offset:16 -; GFX11-NEXT: scratch_load_b32 v172, off, s32 offset:20 -; GFX11-NEXT: scratch_load_b32 v171, off, s32 offset:24 -; GFX11-NEXT: scratch_load_b32 v170, off, s32 offset:28 -; GFX11-NEXT: scratch_load_b32 v169, off, s32 offset:32 -; GFX11-NEXT: scratch_load_b32 v168, off, s32 offset:36 -; GFX11-NEXT: scratch_load_b32 v159, off, s32 offset:40 -; GFX11-NEXT: scratch_load_b32 v158, off, s32 offset:44 -; GFX11-NEXT: scratch_load_b32 v157, off, s32 offset:48 -; GFX11-NEXT: scratch_load_b32 v156, off, s32 offset:52 -; GFX11-NEXT: scratch_load_b32 v155, off, s32 offset:56 -; GFX11-NEXT: scratch_load_b32 v154, off, s32 offset:60 -; GFX11-NEXT: scratch_load_b32 v153, off, s32 offset:64 -; GFX11-NEXT: scratch_load_b32 v152, off, s32 offset:68 -; GFX11-NEXT: scratch_load_b32 v143, off, s32 offset:72 -; GFX11-NEXT: scratch_load_b32 v142, off, s32 offset:76 -; GFX11-NEXT: scratch_load_b32 v141, off, s32 offset:80 -; GFX11-NEXT: scratch_load_b32 v140, off, s32 offset:84 -; GFX11-NEXT: scratch_load_b32 v139, off, s32 offset:88 -; GFX11-NEXT: scratch_load_b32 v138, off, s32 offset:92 -; GFX11-NEXT: scratch_load_b32 v137, off, s32 offset:96 -; GFX11-NEXT: scratch_load_b32 v136, off, s32 offset:100 -; GFX11-NEXT: scratch_load_b32 v127, off, s32 offset:104 -; GFX11-NEXT: scratch_load_b32 v126, off, s32 offset:108 -; GFX11-NEXT: scratch_load_b32 v125, off, s32 offset:112 -; GFX11-NEXT: scratch_load_b32 v124, off, s32 offset:116 -; GFX11-NEXT: scratch_load_b32 v123, off, s32 offset:120 -; GFX11-NEXT: scratch_load_b32 v122, off, s32 offset:124 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v121, off, s32 offset:128 -; GFX11-NEXT: scratch_load_b32 v120, off, s32 offset:132 -; GFX11-NEXT: scratch_load_b32 v111, off, s32 offset:136 -; GFX11-NEXT: scratch_load_b32 v110, off, s32 offset:140 -; GFX11-NEXT: scratch_load_b32 v109, off, s32 offset:144 -; GFX11-NEXT: scratch_load_b32 v108, off, s32 offset:148 -; GFX11-NEXT: scratch_load_b32 v107, off, s32 offset:152 -; GFX11-NEXT: scratch_load_b32 v106, off, s32 offset:156 -; GFX11-NEXT: scratch_load_b32 v105, off, s32 offset:160 -; GFX11-NEXT: scratch_load_b32 v104, off, s32 offset:164 -; GFX11-NEXT: scratch_load_b32 v95, off, s32 offset:168 -; GFX11-NEXT: scratch_load_b32 v94, off, s32 offset:172 -; GFX11-NEXT: scratch_load_b32 v93, off, s32 offset:176 -; GFX11-NEXT: scratch_load_b32 v92, off, s32 offset:180 -; GFX11-NEXT: scratch_load_b32 v91, off, s32 offset:184 -; GFX11-NEXT: scratch_load_b32 v90, off, s32 offset:188 -; GFX11-NEXT: scratch_load_b32 v89, off, s32 offset:192 -; GFX11-NEXT: scratch_load_b32 v88, off, s32 offset:196 -; GFX11-NEXT: scratch_load_b32 v79, off, s32 offset:200 -; GFX11-NEXT: scratch_load_b32 v78, off, s32 offset:204 -; GFX11-NEXT: scratch_load_b32 v77, off, s32 offset:208 -; GFX11-NEXT: scratch_load_b32 v76, off, s32 offset:212 -; GFX11-NEXT: scratch_load_b32 v75, off, s32 offset:216 -; GFX11-NEXT: scratch_load_b32 v74, off, s32 offset:220 -; GFX11-NEXT: scratch_load_b32 v73, off, s32 offset:224 -; GFX11-NEXT: scratch_load_b32 v72, off, s32 offset:228 -; GFX11-NEXT: scratch_load_b32 v63, off, s32 offset:232 -; GFX11-NEXT: scratch_load_b32 v62, off, s32 offset:236 -; GFX11-NEXT: scratch_load_b32 v61, off, s32 offset:240 -; GFX11-NEXT: scratch_load_b32 v60, off, s32 offset:244 -; GFX11-NEXT: scratch_load_b32 v59, off, s32 offset:248 -; GFX11-NEXT: scratch_load_b32 v58, off, s32 offset:252 -; GFX11-NEXT: s_clause 0x9 ; 40-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v57, off, s32 offset:256 -; GFX11-NEXT: scratch_load_b32 v56, off, s32 offset:260 -; GFX11-NEXT: scratch_load_b32 v47, off, s32 offset:264 -; GFX11-NEXT: scratch_load_b32 v46, off, s32 offset:268 -; GFX11-NEXT: scratch_load_b32 v45, off, s32 offset:272 -; GFX11-NEXT: scratch_load_b32 v44, off, s32 offset:276 -; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:280 -; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:284 -; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:288 -; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:292 -; GFX11-NEXT: v_dual_mov_b32 v2, v52 :: v_dual_mov_b32 v5, v67 -; GFX11-NEXT: v_dual_mov_b32 v10, v112 :: v_dual_mov_b32 v13, v151 -; GFX11-NEXT: v_dual_mov_b32 v25, v182 :: v_dual_mov_b32 v26, v181 -; GFX11-NEXT: v_dual_mov_b32 v27, v180 :: v_dual_mov_b32 v28, v179 -; GFX11-NEXT: v_dual_mov_b32 v29, v178 :: v_dual_mov_b32 v30, v177 -; GFX11-NEXT: v_mov_b32_e32 v31, v176 -; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: .LBB71_4: -; GFX11-NEXT: ; implicit-def: $vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78 -; GFX11-NEXT: ; implicit-def: $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79 -; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-NEXT: ; implicit-def: $vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81 -; GFX11-NEXT: ; implicit-def: $vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84 -; GFX11-NEXT: ; implicit-def: $vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88 -; GFX11-NEXT: ; implicit-def: $vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93 -; GFX11-NEXT: ; implicit-def: $vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99 -; GFX11-NEXT: ; implicit-def: $vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106 -; GFX11-NEXT: ; implicit-def: $vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114 -; GFX11-NEXT: ; implicit-def: $vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123 -; GFX11-NEXT: ; implicit-def: $vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133 -; GFX11-NEXT: ; implicit-def: $vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144 -; GFX11-NEXT: ; implicit-def: $vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156 -; GFX11-NEXT: ; implicit-def: $vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169 +; GFX11-NEXT: ; implicit-def: $vgpr0 +; GFX11-NEXT: ; implicit-def: $vgpr1 +; GFX11-NEXT: ; implicit-def: $vgpr2 +; GFX11-NEXT: ; implicit-def: $vgpr3 +; GFX11-NEXT: ; implicit-def: $vgpr4 +; GFX11-NEXT: ; implicit-def: $vgpr5 +; GFX11-NEXT: ; implicit-def: $vgpr6 +; GFX11-NEXT: ; implicit-def: $vgpr7 +; GFX11-NEXT: ; implicit-def: $vgpr8 +; GFX11-NEXT: ; implicit-def: $vgpr9 +; GFX11-NEXT: ; implicit-def: $vgpr10 +; GFX11-NEXT: ; implicit-def: $vgpr11 +; GFX11-NEXT: ; implicit-def: $vgpr12 +; GFX11-NEXT: ; implicit-def: $vgpr13 +; GFX11-NEXT: ; implicit-def: $vgpr14 +; GFX11-NEXT: ; implicit-def: $vgpr15 ; GFX11-NEXT: s_branch .LBB71_2 %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -116241,9 +114820,9 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: s_or_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt expcnt(2) ; SI-NEXT: v_writelane_b32 v63, s30, 0 @@ -116268,40 +114847,68 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; SI-NEXT: v_writelane_b32 v63, s67, 19 ; SI-NEXT: v_writelane_b32 v63, s68, 20 ; SI-NEXT: v_writelane_b32 v63, s69, 21 +; SI-NEXT: v_mov_b32_e32 v20, s16 ; SI-NEXT: v_writelane_b32 v63, s70, 22 +; SI-NEXT: v_readfirstlane_b32 s56, v20 +; SI-NEXT: v_mov_b32_e32 v20, s17 ; SI-NEXT: v_writelane_b32 v63, s71, 23 +; SI-NEXT: v_readfirstlane_b32 s57, v20 +; SI-NEXT: v_mov_b32_e32 v20, s18 ; SI-NEXT: v_writelane_b32 v63, s80, 24 +; SI-NEXT: v_readfirstlane_b32 s46, v20 +; SI-NEXT: v_mov_b32_e32 v20, s19 ; SI-NEXT: v_writelane_b32 v63, s81, 25 +; SI-NEXT: v_readfirstlane_b32 s47, v20 +; SI-NEXT: v_mov_b32_e32 v20, s20 ; SI-NEXT: v_writelane_b32 v63, s82, 26 +; SI-NEXT: v_readfirstlane_b32 s44, v20 +; SI-NEXT: v_mov_b32_e32 v20, s21 ; SI-NEXT: v_writelane_b32 v63, s83, 27 +; SI-NEXT: v_readfirstlane_b32 s45, v20 +; SI-NEXT: v_mov_b32_e32 v20, s22 ; SI-NEXT: v_writelane_b32 v63, s84, 28 +; SI-NEXT: v_readfirstlane_b32 s42, v20 +; SI-NEXT: v_mov_b32_e32 v20, s23 ; SI-NEXT: v_writelane_b32 v63, s85, 29 +; SI-NEXT: v_readfirstlane_b32 s43, v20 +; SI-NEXT: v_mov_b32_e32 v20, s24 ; SI-NEXT: v_writelane_b32 v63, s86, 30 +; SI-NEXT: v_readfirstlane_b32 s40, v20 +; SI-NEXT: v_mov_b32_e32 v20, s25 ; SI-NEXT: v_writelane_b32 v63, s87, 31 +; SI-NEXT: v_readfirstlane_b32 s41, v20 +; SI-NEXT: v_mov_b32_e32 v20, s26 ; SI-NEXT: v_writelane_b32 v63, s96, 32 +; SI-NEXT: v_readfirstlane_b32 s24, v20 +; SI-NEXT: v_mov_b32_e32 v20, s27 ; SI-NEXT: v_writelane_b32 v63, s97, 33 +; SI-NEXT: v_readfirstlane_b32 s25, v20 +; SI-NEXT: v_mov_b32_e32 v20, s28 ; SI-NEXT: v_writelane_b32 v63, s98, 34 +; SI-NEXT: v_readfirstlane_b32 s22, v20 +; SI-NEXT: v_mov_b32_e32 v20, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; SI-NEXT: v_writelane_b32 v63, s99, 35 -; SI-NEXT: v_readfirstlane_b32 s4, v1 -; SI-NEXT: v_readfirstlane_b32 s5, v2 -; SI-NEXT: v_readfirstlane_b32 s6, v3 -; SI-NEXT: v_readfirstlane_b32 s7, v4 -; SI-NEXT: v_readfirstlane_b32 s8, v5 -; SI-NEXT: v_readfirstlane_b32 s9, v6 -; SI-NEXT: v_readfirstlane_b32 s10, v7 -; SI-NEXT: v_readfirstlane_b32 s11, v8 +; SI-NEXT: v_readfirstlane_b32 s23, v20 +; SI-NEXT: v_readfirstlane_b32 s20, v1 +; SI-NEXT: v_readfirstlane_b32 s21, v2 +; SI-NEXT: v_readfirstlane_b32 s18, v3 +; SI-NEXT: v_readfirstlane_b32 s19, v4 +; SI-NEXT: v_readfirstlane_b32 s16, v5 +; SI-NEXT: v_readfirstlane_b32 s17, v6 +; SI-NEXT: v_readfirstlane_b32 s14, v7 +; SI-NEXT: v_readfirstlane_b32 s15, v8 ; SI-NEXT: v_readfirstlane_b32 s12, v9 ; SI-NEXT: v_readfirstlane_b32 s13, v10 -; SI-NEXT: v_readfirstlane_b32 s14, v11 -; SI-NEXT: v_readfirstlane_b32 s15, v12 -; SI-NEXT: v_readfirstlane_b32 s40, v13 -; SI-NEXT: v_readfirstlane_b32 s41, v14 -; SI-NEXT: v_readfirstlane_b32 s42, v15 -; SI-NEXT: v_readfirstlane_b32 s43, v16 -; SI-NEXT: v_readfirstlane_b32 s44, v17 -; SI-NEXT: s_and_b64 s[46:47], vcc, exec -; SI-NEXT: v_readfirstlane_b32 s45, v18 +; SI-NEXT: v_readfirstlane_b32 s10, v11 +; SI-NEXT: v_readfirstlane_b32 s11, v12 +; SI-NEXT: v_readfirstlane_b32 s8, v13 +; SI-NEXT: v_readfirstlane_b32 s9, v14 +; SI-NEXT: v_readfirstlane_b32 s6, v15 +; SI-NEXT: v_readfirstlane_b32 s7, v16 +; SI-NEXT: v_readfirstlane_b32 s4, v17 +; SI-NEXT: s_and_b64 s[26:27], vcc, exec +; SI-NEXT: v_readfirstlane_b32 s5, v18 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill @@ -116315,488 +114922,463 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 ; 4-byte Folded Spill -; SI-NEXT: ; implicit-def: $vgpr61 : SGPR spill to VGPR lane ; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane +; SI-NEXT: ; implicit-def: $vgpr61 : SGPR spill to VGPR lane ; SI-NEXT: s_cbranch_scc0 .LBB73_3 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: s_lshr_b32 s46, s45, 24 -; SI-NEXT: v_writelane_b32 v61, s46, 34 -; SI-NEXT: s_lshr_b32 s46, s45, 16 -; SI-NEXT: v_writelane_b32 v61, s46, 35 -; SI-NEXT: s_lshr_b32 s46, s45, 8 -; SI-NEXT: v_writelane_b32 v61, s46, 36 -; SI-NEXT: s_lshr_b32 s46, s43, 24 -; SI-NEXT: v_writelane_b32 v61, s46, 37 -; SI-NEXT: s_lshr_b32 s46, s43, 16 -; SI-NEXT: v_writelane_b32 v61, s46, 38 -; SI-NEXT: s_lshr_b32 s46, s43, 8 -; SI-NEXT: v_writelane_b32 v61, s46, 39 -; SI-NEXT: s_lshr_b32 s46, s41, 24 -; SI-NEXT: v_writelane_b32 v61, s46, 40 -; SI-NEXT: s_lshr_b32 s46, s41, 16 -; SI-NEXT: v_writelane_b32 v61, s46, 41 -; SI-NEXT: s_lshr_b32 s46, s41, 8 -; SI-NEXT: v_writelane_b32 v61, s46, 42 -; SI-NEXT: s_lshr_b32 s46, s15, 24 -; SI-NEXT: v_writelane_b32 v61, s46, 43 -; SI-NEXT: s_lshr_b32 s46, s15, 16 -; SI-NEXT: v_writelane_b32 v61, s46, 44 -; SI-NEXT: s_lshr_b32 s46, s15, 8 -; SI-NEXT: v_writelane_b32 v61, s46, 45 -; SI-NEXT: s_lshr_b32 s46, s13, 24 -; SI-NEXT: v_writelane_b32 v61, s46, 46 -; SI-NEXT: s_lshr_b32 s46, s13, 16 -; SI-NEXT: v_writelane_b32 v61, s46, 47 -; SI-NEXT: s_lshr_b32 s46, s13, 8 -; SI-NEXT: v_writelane_b32 v61, s46, 48 -; SI-NEXT: s_lshr_b32 s46, s11, 24 -; SI-NEXT: v_writelane_b32 v61, s46, 49 -; SI-NEXT: s_lshr_b32 s46, s11, 16 -; SI-NEXT: v_writelane_b32 v61, s46, 50 -; SI-NEXT: s_lshr_b32 s46, s11, 8 -; SI-NEXT: v_writelane_b32 v61, s46, 51 -; SI-NEXT: s_lshr_b32 s46, s9, 24 -; SI-NEXT: v_writelane_b32 v61, s46, 52 -; SI-NEXT: s_lshr_b32 s46, s9, 16 -; SI-NEXT: v_writelane_b32 v61, s46, 53 -; SI-NEXT: s_lshr_b32 s46, s9, 8 -; SI-NEXT: v_writelane_b32 v61, s46, 54 -; SI-NEXT: s_lshr_b32 s46, s7, 24 -; SI-NEXT: v_writelane_b32 v61, s46, 55 -; SI-NEXT: s_lshr_b32 s46, s7, 16 -; SI-NEXT: v_writelane_b32 v61, s46, 56 -; SI-NEXT: s_lshr_b32 s46, s7, 8 -; SI-NEXT: v_writelane_b32 v61, s46, 57 -; SI-NEXT: s_lshr_b32 s46, s5, 24 -; SI-NEXT: v_writelane_b32 v61, s46, 58 -; SI-NEXT: s_lshr_b32 s46, s5, 16 -; SI-NEXT: v_writelane_b32 v61, s46, 59 -; SI-NEXT: s_lshr_b32 s46, s5, 8 -; SI-NEXT: v_writelane_b32 v61, s46, 60 -; SI-NEXT: s_lshr_b32 s46, s29, 24 -; SI-NEXT: v_writelane_b32 v61, s46, 61 -; SI-NEXT: s_lshr_b32 s46, s29, 16 -; SI-NEXT: v_writelane_b32 v61, s46, 62 -; SI-NEXT: s_lshr_b32 s46, s29, 8 -; SI-NEXT: v_writelane_b32 v61, s46, 63 -; SI-NEXT: s_lshr_b32 s46, s27, 24 -; SI-NEXT: v_writelane_b32 v62, s46, 0 -; SI-NEXT: s_lshr_b32 s46, s27, 16 -; SI-NEXT: v_writelane_b32 v62, s46, 1 -; SI-NEXT: s_lshr_b32 s46, s27, 8 -; SI-NEXT: v_writelane_b32 v62, s46, 2 -; SI-NEXT: s_lshr_b32 s46, s25, 24 -; SI-NEXT: v_writelane_b32 v62, s46, 3 -; SI-NEXT: s_lshr_b32 s46, s25, 16 -; SI-NEXT: v_writelane_b32 v62, s46, 4 -; SI-NEXT: s_lshr_b32 s46, s25, 8 -; SI-NEXT: v_writelane_b32 v62, s46, 5 -; SI-NEXT: s_lshr_b32 s46, s23, 24 -; SI-NEXT: v_writelane_b32 v62, s46, 6 -; SI-NEXT: s_lshr_b32 s46, s23, 16 -; SI-NEXT: v_writelane_b32 v62, s46, 7 -; SI-NEXT: s_lshr_b32 s46, s23, 8 -; SI-NEXT: v_writelane_b32 v62, s46, 8 -; SI-NEXT: s_lshr_b32 s46, s21, 24 -; SI-NEXT: v_writelane_b32 v62, s46, 9 -; SI-NEXT: s_lshr_b32 s46, s21, 16 -; SI-NEXT: v_writelane_b32 v62, s46, 10 -; SI-NEXT: s_lshr_b32 s46, s21, 8 -; SI-NEXT: v_writelane_b32 v62, s46, 11 -; SI-NEXT: s_lshr_b32 s46, s19, 24 -; SI-NEXT: v_writelane_b32 v62, s46, 12 -; SI-NEXT: s_lshr_b32 s46, s19, 16 -; SI-NEXT: v_writelane_b32 v62, s46, 13 -; SI-NEXT: s_lshr_b32 s46, s19, 8 -; SI-NEXT: v_writelane_b32 v62, s46, 14 -; SI-NEXT: s_lshr_b32 s46, s17, 24 -; SI-NEXT: v_writelane_b32 v62, s46, 15 -; SI-NEXT: s_lshr_b32 s46, s17, 16 -; SI-NEXT: v_writelane_b32 v62, s46, 16 -; SI-NEXT: s_lshr_b32 s46, s17, 8 -; SI-NEXT: v_writelane_b32 v62, s46, 17 -; SI-NEXT: s_lshr_b64 s[46:47], s[44:45], 24 -; SI-NEXT: v_writelane_b32 v61, s46, 32 -; SI-NEXT: v_writelane_b32 v61, s47, 33 -; SI-NEXT: s_lshr_b64 s[46:47], s[44:45], 8 -; SI-NEXT: v_writelane_b32 v61, s46, 30 -; SI-NEXT: v_writelane_b32 v61, s47, 31 -; SI-NEXT: s_lshr_b64 s[46:47], s[42:43], 24 -; SI-NEXT: v_writelane_b32 v61, s46, 28 -; SI-NEXT: v_writelane_b32 v61, s47, 29 -; SI-NEXT: s_lshr_b64 s[46:47], s[42:43], 16 -; SI-NEXT: v_writelane_b32 v61, s46, 26 -; SI-NEXT: v_writelane_b32 v61, s47, 27 -; SI-NEXT: s_lshr_b64 s[46:47], s[42:43], 8 -; SI-NEXT: v_writelane_b32 v61, s46, 24 -; SI-NEXT: v_writelane_b32 v61, s47, 25 -; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 24 -; SI-NEXT: v_writelane_b32 v61, s46, 22 -; SI-NEXT: v_writelane_b32 v61, s47, 23 -; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 16 -; SI-NEXT: v_writelane_b32 v61, s46, 20 -; SI-NEXT: v_writelane_b32 v61, s47, 21 -; SI-NEXT: s_lshr_b64 s[46:47], s[40:41], 8 -; SI-NEXT: v_writelane_b32 v61, s46, 18 -; SI-NEXT: v_writelane_b32 v61, s47, 19 -; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 24 -; SI-NEXT: v_writelane_b32 v61, s46, 16 -; SI-NEXT: v_writelane_b32 v61, s47, 17 -; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 16 -; SI-NEXT: v_writelane_b32 v61, s46, 14 -; SI-NEXT: v_writelane_b32 v61, s47, 15 -; SI-NEXT: s_lshr_b64 s[46:47], s[14:15], 8 -; SI-NEXT: v_writelane_b32 v61, s46, 12 -; SI-NEXT: v_writelane_b32 v61, s47, 13 -; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 24 -; SI-NEXT: v_writelane_b32 v61, s46, 10 -; SI-NEXT: v_writelane_b32 v61, s47, 11 -; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 16 -; SI-NEXT: v_writelane_b32 v61, s46, 8 -; SI-NEXT: v_writelane_b32 v61, s47, 9 -; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 8 -; SI-NEXT: v_writelane_b32 v61, s46, 6 -; SI-NEXT: v_writelane_b32 v61, s47, 7 -; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 24 -; SI-NEXT: v_writelane_b32 v61, s46, 4 -; SI-NEXT: v_writelane_b32 v61, s47, 5 -; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 16 -; SI-NEXT: v_writelane_b32 v61, s46, 2 -; SI-NEXT: v_writelane_b32 v61, s47, 3 -; SI-NEXT: s_lshr_b64 s[46:47], s[10:11], 8 -; SI-NEXT: v_writelane_b32 v61, s46, 0 -; SI-NEXT: s_lshr_b64 s[48:49], s[44:45], 16 -; SI-NEXT: v_writelane_b32 v61, s47, 1 -; SI-NEXT: s_lshr_b64 s[50:51], s[8:9], 24 -; SI-NEXT: s_lshr_b64 s[52:53], s[8:9], 16 -; SI-NEXT: s_lshr_b64 s[54:55], s[8:9], 8 -; SI-NEXT: s_lshr_b64 s[64:65], s[6:7], 24 -; SI-NEXT: s_lshr_b64 s[66:67], s[6:7], 16 -; SI-NEXT: s_lshr_b64 s[68:69], s[6:7], 8 -; SI-NEXT: s_lshr_b64 s[70:71], s[4:5], 24 -; SI-NEXT: s_lshr_b64 s[80:81], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[82:83], s[4:5], 8 -; SI-NEXT: s_lshr_b64 s[84:85], s[28:29], 24 -; SI-NEXT: s_lshr_b64 s[86:87], s[28:29], 16 -; SI-NEXT: s_lshr_b64 s[96:97], s[28:29], 8 -; SI-NEXT: s_lshr_b64 s[98:99], s[26:27], 24 -; SI-NEXT: s_lshr_b64 s[46:47], s[26:27], 16 -; SI-NEXT: s_lshr_b64 s[56:57], s[26:27], 8 -; SI-NEXT: s_lshr_b64 s[58:59], s[24:25], 24 -; SI-NEXT: s_lshr_b64 s[60:61], s[24:25], 16 -; SI-NEXT: s_lshr_b64 s[62:63], s[24:25], 8 -; SI-NEXT: s_lshr_b64 s[72:73], s[22:23], 24 -; SI-NEXT: s_lshr_b64 s[74:75], s[22:23], 16 -; SI-NEXT: s_lshr_b64 s[76:77], s[22:23], 8 -; SI-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 -; SI-NEXT: s_lshr_b64 s[88:89], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[90:91], s[20:21], 8 -; SI-NEXT: s_lshr_b64 s[92:93], s[18:19], 24 -; SI-NEXT: s_lshr_b64 s[94:95], s[18:19], 16 -; SI-NEXT: s_lshr_b64 s[30:31], s[18:19], 8 -; SI-NEXT: s_lshr_b64 s[34:35], s[16:17], 24 -; SI-NEXT: s_lshr_b64 s[36:37], s[16:17], 16 -; SI-NEXT: s_lshr_b64 s[38:39], s[16:17], 8 +; SI-NEXT: s_lshr_b32 s26, s5, 24 +; SI-NEXT: v_writelane_b32 v62, s26, 34 +; SI-NEXT: s_lshr_b32 s26, s5, 16 +; SI-NEXT: v_writelane_b32 v62, s26, 35 +; SI-NEXT: s_lshr_b32 s26, s5, 8 +; SI-NEXT: v_writelane_b32 v62, s26, 36 +; SI-NEXT: s_lshr_b32 s26, s7, 24 +; SI-NEXT: v_writelane_b32 v62, s26, 37 +; SI-NEXT: s_lshr_b32 s26, s7, 16 +; SI-NEXT: v_writelane_b32 v62, s26, 38 +; SI-NEXT: s_lshr_b32 s26, s7, 8 +; SI-NEXT: v_writelane_b32 v62, s26, 39 +; SI-NEXT: s_lshr_b32 s26, s9, 24 +; SI-NEXT: v_writelane_b32 v62, s26, 40 +; SI-NEXT: s_lshr_b32 s26, s9, 16 +; SI-NEXT: v_writelane_b32 v62, s26, 41 +; SI-NEXT: s_lshr_b32 s26, s9, 8 +; SI-NEXT: v_writelane_b32 v62, s26, 42 +; SI-NEXT: s_lshr_b32 s26, s11, 24 +; SI-NEXT: v_writelane_b32 v62, s26, 43 +; SI-NEXT: s_lshr_b32 s26, s11, 16 +; SI-NEXT: v_writelane_b32 v62, s26, 44 +; SI-NEXT: s_lshr_b32 s26, s11, 8 +; SI-NEXT: v_writelane_b32 v62, s26, 45 +; SI-NEXT: s_lshr_b32 s26, s13, 24 +; SI-NEXT: v_writelane_b32 v62, s26, 46 +; SI-NEXT: s_lshr_b32 s26, s13, 16 +; SI-NEXT: v_writelane_b32 v62, s26, 47 +; SI-NEXT: s_lshr_b32 s26, s13, 8 +; SI-NEXT: v_writelane_b32 v62, s26, 48 +; SI-NEXT: s_lshr_b32 s26, s15, 24 +; SI-NEXT: v_writelane_b32 v62, s26, 49 +; SI-NEXT: s_lshr_b32 s26, s15, 16 +; SI-NEXT: v_writelane_b32 v62, s26, 50 +; SI-NEXT: s_lshr_b32 s26, s15, 8 +; SI-NEXT: v_writelane_b32 v62, s26, 51 +; SI-NEXT: s_lshr_b32 s26, s17, 24 +; SI-NEXT: v_writelane_b32 v62, s26, 52 +; SI-NEXT: s_lshr_b32 s26, s17, 16 +; SI-NEXT: v_writelane_b32 v62, s26, 53 +; SI-NEXT: s_lshr_b32 s26, s17, 8 +; SI-NEXT: v_writelane_b32 v62, s26, 54 +; SI-NEXT: s_lshr_b32 s26, s19, 24 +; SI-NEXT: v_writelane_b32 v62, s26, 55 +; SI-NEXT: s_lshr_b32 s26, s19, 16 +; SI-NEXT: v_writelane_b32 v62, s26, 56 +; SI-NEXT: s_lshr_b32 s26, s19, 8 +; SI-NEXT: v_writelane_b32 v62, s26, 57 +; SI-NEXT: s_lshr_b32 s26, s21, 24 +; SI-NEXT: v_writelane_b32 v62, s26, 58 +; SI-NEXT: s_lshr_b32 s26, s21, 16 +; SI-NEXT: v_writelane_b32 v62, s26, 59 +; SI-NEXT: s_lshr_b32 s26, s21, 8 +; SI-NEXT: v_writelane_b32 v62, s26, 60 +; SI-NEXT: s_lshr_b32 s26, s23, 24 +; SI-NEXT: v_writelane_b32 v62, s26, 61 +; SI-NEXT: s_lshr_b32 s26, s23, 16 +; SI-NEXT: v_writelane_b32 v62, s26, 62 +; SI-NEXT: s_lshr_b32 s26, s23, 8 +; SI-NEXT: v_writelane_b32 v62, s26, 63 +; SI-NEXT: s_lshr_b32 s26, s25, 24 +; SI-NEXT: v_writelane_b32 v61, s26, 0 +; SI-NEXT: s_lshr_b32 s26, s25, 16 +; SI-NEXT: v_writelane_b32 v61, s26, 1 +; SI-NEXT: s_lshr_b32 s26, s25, 8 +; SI-NEXT: v_writelane_b32 v61, s26, 2 +; SI-NEXT: s_lshr_b32 s26, s41, 24 +; SI-NEXT: v_writelane_b32 v61, s26, 3 +; SI-NEXT: s_lshr_b32 s26, s41, 16 +; SI-NEXT: v_writelane_b32 v61, s26, 4 +; SI-NEXT: s_lshr_b32 s26, s41, 8 +; SI-NEXT: v_writelane_b32 v61, s26, 5 +; SI-NEXT: s_lshr_b32 s26, s43, 24 +; SI-NEXT: v_writelane_b32 v61, s26, 6 +; SI-NEXT: s_lshr_b32 s26, s43, 16 +; SI-NEXT: v_writelane_b32 v61, s26, 7 +; SI-NEXT: s_lshr_b32 s26, s43, 8 +; SI-NEXT: v_writelane_b32 v61, s26, 8 +; SI-NEXT: s_lshr_b32 s26, s45, 24 +; SI-NEXT: v_writelane_b32 v61, s26, 9 +; SI-NEXT: s_lshr_b32 s26, s45, 16 +; SI-NEXT: v_writelane_b32 v61, s26, 10 +; SI-NEXT: s_lshr_b32 s26, s45, 8 +; SI-NEXT: v_writelane_b32 v61, s26, 11 +; SI-NEXT: s_lshr_b32 s26, s47, 24 +; SI-NEXT: v_writelane_b32 v61, s26, 12 +; SI-NEXT: s_lshr_b32 s26, s47, 16 +; SI-NEXT: v_writelane_b32 v61, s26, 13 +; SI-NEXT: s_lshr_b32 s26, s47, 8 +; SI-NEXT: v_writelane_b32 v61, s26, 14 +; SI-NEXT: s_lshr_b32 s26, s57, 24 +; SI-NEXT: v_writelane_b32 v61, s26, 15 +; SI-NEXT: s_lshr_b32 s26, s57, 16 +; SI-NEXT: v_writelane_b32 v61, s26, 16 +; SI-NEXT: s_lshr_b32 s26, s57, 8 +; SI-NEXT: v_writelane_b32 v61, s26, 17 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 24 +; SI-NEXT: v_writelane_b32 v62, s26, 32 +; SI-NEXT: v_writelane_b32 v62, s27, 33 +; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 8 +; SI-NEXT: v_writelane_b32 v62, s26, 30 +; SI-NEXT: v_writelane_b32 v62, s27, 31 +; SI-NEXT: s_lshr_b64 s[26:27], s[6:7], 24 +; SI-NEXT: v_writelane_b32 v62, s26, 28 +; SI-NEXT: v_writelane_b32 v62, s27, 29 +; SI-NEXT: s_lshr_b64 s[26:27], s[6:7], 16 +; SI-NEXT: v_writelane_b32 v62, s26, 26 +; SI-NEXT: v_writelane_b32 v62, s27, 27 +; SI-NEXT: s_lshr_b64 s[26:27], s[6:7], 8 +; SI-NEXT: v_writelane_b32 v62, s26, 24 +; SI-NEXT: v_writelane_b32 v62, s27, 25 +; SI-NEXT: s_lshr_b64 s[26:27], s[8:9], 24 +; SI-NEXT: v_writelane_b32 v62, s26, 22 +; SI-NEXT: v_writelane_b32 v62, s27, 23 +; SI-NEXT: s_lshr_b64 s[26:27], s[8:9], 16 +; SI-NEXT: v_writelane_b32 v62, s26, 20 +; SI-NEXT: v_writelane_b32 v62, s27, 21 +; SI-NEXT: s_lshr_b64 s[26:27], s[8:9], 8 +; SI-NEXT: v_writelane_b32 v62, s26, 18 +; SI-NEXT: v_writelane_b32 v62, s27, 19 +; SI-NEXT: s_lshr_b64 s[26:27], s[10:11], 24 +; SI-NEXT: v_writelane_b32 v62, s26, 16 +; SI-NEXT: v_writelane_b32 v62, s27, 17 +; SI-NEXT: s_lshr_b64 s[26:27], s[10:11], 16 +; SI-NEXT: v_writelane_b32 v62, s26, 14 +; SI-NEXT: v_writelane_b32 v62, s27, 15 +; SI-NEXT: s_lshr_b64 s[26:27], s[10:11], 8 +; SI-NEXT: v_writelane_b32 v62, s26, 12 +; SI-NEXT: v_writelane_b32 v62, s27, 13 +; SI-NEXT: s_lshr_b64 s[26:27], s[12:13], 24 +; SI-NEXT: v_writelane_b32 v62, s26, 10 +; SI-NEXT: v_writelane_b32 v62, s27, 11 +; SI-NEXT: s_lshr_b64 s[26:27], s[12:13], 16 +; SI-NEXT: v_writelane_b32 v62, s26, 8 +; SI-NEXT: v_writelane_b32 v62, s27, 9 +; SI-NEXT: s_lshr_b64 s[26:27], s[12:13], 8 +; SI-NEXT: v_writelane_b32 v62, s26, 6 +; SI-NEXT: v_writelane_b32 v62, s27, 7 +; SI-NEXT: s_lshr_b64 s[26:27], s[14:15], 24 +; SI-NEXT: v_writelane_b32 v62, s26, 4 +; SI-NEXT: v_writelane_b32 v62, s27, 5 +; SI-NEXT: s_lshr_b64 s[26:27], s[14:15], 16 +; SI-NEXT: v_writelane_b32 v62, s26, 2 +; SI-NEXT: v_writelane_b32 v62, s27, 3 +; SI-NEXT: s_lshr_b64 s[26:27], s[14:15], 8 +; SI-NEXT: v_writelane_b32 v62, s26, 0 +; SI-NEXT: s_lshr_b64 s[48:49], s[4:5], 16 +; SI-NEXT: v_writelane_b32 v62, s27, 1 +; SI-NEXT: s_lshr_b64 s[50:51], s[16:17], 24 +; SI-NEXT: s_lshr_b64 s[52:53], s[16:17], 16 +; SI-NEXT: s_lshr_b64 s[54:55], s[16:17], 8 +; SI-NEXT: s_lshr_b64 s[64:65], s[18:19], 24 +; SI-NEXT: s_lshr_b64 s[66:67], s[18:19], 16 +; SI-NEXT: s_lshr_b64 s[68:69], s[18:19], 8 +; SI-NEXT: s_lshr_b64 s[70:71], s[20:21], 24 +; SI-NEXT: s_lshr_b64 s[80:81], s[20:21], 16 +; SI-NEXT: s_lshr_b64 s[82:83], s[20:21], 8 +; SI-NEXT: s_lshr_b64 s[84:85], s[22:23], 24 +; SI-NEXT: s_lshr_b64 s[86:87], s[22:23], 16 +; SI-NEXT: s_lshr_b64 s[96:97], s[22:23], 8 +; SI-NEXT: s_lshr_b64 s[98:99], s[24:25], 24 +; SI-NEXT: s_lshr_b64 s[26:27], s[24:25], 16 +; SI-NEXT: s_lshr_b64 s[28:29], s[24:25], 8 +; SI-NEXT: s_lshr_b64 s[58:59], s[40:41], 24 +; SI-NEXT: s_lshr_b64 s[60:61], s[40:41], 16 +; SI-NEXT: s_lshr_b64 s[62:63], s[40:41], 8 +; SI-NEXT: s_lshr_b64 s[72:73], s[42:43], 24 +; SI-NEXT: s_lshr_b64 s[74:75], s[42:43], 16 +; SI-NEXT: s_lshr_b64 s[76:77], s[42:43], 8 +; SI-NEXT: s_lshr_b64 s[78:79], s[44:45], 24 +; SI-NEXT: s_lshr_b64 s[88:89], s[44:45], 16 +; SI-NEXT: s_lshr_b64 s[90:91], s[44:45], 8 +; SI-NEXT: s_lshr_b64 s[92:93], s[46:47], 24 +; SI-NEXT: s_lshr_b64 s[94:95], s[46:47], 16 +; SI-NEXT: s_lshr_b64 s[30:31], s[46:47], 8 +; SI-NEXT: s_lshr_b64 s[34:35], s[56:57], 24 +; SI-NEXT: s_lshr_b64 s[36:37], s[56:57], 16 +; SI-NEXT: s_lshr_b64 s[38:39], s[56:57], 8 ; SI-NEXT: s_cbranch_execnz .LBB73_4 ; SI-NEXT: .LBB73_2: ; %cmp.true -; SI-NEXT: v_add_f64 v[5:6], s[40:41], 1.0 -; SI-NEXT: v_add_f64 v[7:8], s[14:15], 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v6 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 8, v6 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 24, v8 -; SI-NEXT: v_add_f64 v[9:10], s[12:13], 1.0 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v8 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 8, v8 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 24, v10 -; SI-NEXT: v_add_f64 v[11:12], s[10:11], 1.0 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v10 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 8, v10 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 24, v12 -; SI-NEXT: v_add_f64 v[13:14], s[8:9], 1.0 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v12 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 8, v12 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 24, v14 -; SI-NEXT: v_add_f64 v[15:16], s[6:7], 1.0 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v14 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 8, v14 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 24, v16 -; SI-NEXT: v_add_f64 v[17:18], s[4:5], 1.0 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v16 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 8, v16 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 24, v18 -; SI-NEXT: v_add_f64 v[19:20], s[28:29], 1.0 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v18 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 8, v18 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 24, v20 -; SI-NEXT: v_add_f64 v[21:22], s[26:27], 1.0 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v20 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 8, v20 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 24, v22 -; SI-NEXT: v_add_f64 v[23:24], s[24:25], 1.0 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v22 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 8, v22 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 24, v24 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v24 -; SI-NEXT: v_add_f64 v[38:39], s[22:23], 1.0 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 8, v24 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 24, v39 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v39 -; SI-NEXT: v_add_f64 v[52:53], s[20:21], 1.0 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 8, v39 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 24, v53 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v53 -; SI-NEXT: v_add_f64 v[44:45], s[18:19], 1.0 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 8, v53 -; SI-NEXT: v_add_f64 v[1:2], s[44:45], 1.0 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 24, v45 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v45 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[1:2], 24 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[1:2], 16 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[1:2], 8 -; SI-NEXT: v_add_f64 v[3:4], s[42:43], 1.0 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[3:4], 24 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[3:4], 16 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[3:4], 8 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[5:6], 24 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[5:6], 16 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[5:6], 8 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[7:8], 24 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[7:8], 16 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[7:8], 8 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[9:10], 24 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[9:10], 16 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[9:10], 8 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[11:12], 24 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[11:12], 16 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[11:12], 8 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[13:14], 24 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[13:14], 16 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[13:14], 8 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[15:16], 24 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; SI-NEXT: v_add_f64 v[30:31], s[22:23], 1.0 +; SI-NEXT: v_add_f64 v[7:8], s[24:25], 1.0 +; SI-NEXT: v_lshr_b64 v[9:10], v[30:31], 24 +; SI-NEXT: v_lshr_b64 v[10:11], v[7:8], 24 +; SI-NEXT: v_add_f64 v[54:55], s[40:41], 1.0 +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[10:11], v[54:55], 24 +; SI-NEXT: v_add_f64 v[42:43], s[42:43], 1.0 +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[10:11], v[54:55], 16 +; SI-NEXT: v_add_f64 v[37:38], s[4:5], 1.0 +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[10:11], v[42:43], 16 +; SI-NEXT: v_add_f64 v[56:57], s[44:45], 1.0 +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[10:11], v[42:43], 8 +; SI-NEXT: v_lshr_b64 v[1:2], v[37:38], 24 +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[10:11], v[56:57], 24 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(2) +; SI-NEXT: v_lshr_b64 v[1:2], v[37:38], 16 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[15:16], 16 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; SI-NEXT: v_lshr_b64 v[10:11], v[56:57], 16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(2) +; SI-NEXT: v_lshr_b64 v[1:2], v[37:38], 8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[15:16], 8 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; SI-NEXT: v_lshr_b64 v[10:11], v[56:57], 8 +; SI-NEXT: v_add_f64 v[35:36], s[6:7], 1.0 +; SI-NEXT: v_add_f64 v[19:20], s[46:47], 1.0 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(2) +; SI-NEXT: v_lshr_b64 v[1:2], v[35:36], 24 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[17:18], 24 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill +; SI-NEXT: v_lshr_b64 v[10:11], v[19:20], 24 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(2) +; SI-NEXT: v_lshr_b64 v[1:2], v[35:36], 16 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[17:18], 16 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill +; SI-NEXT: v_lshr_b64 v[10:11], v[19:20], 16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(2) +; SI-NEXT: v_lshr_b64 v[1:2], v[35:36], 8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[17:18], 8 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill +; SI-NEXT: v_lshr_b64 v[10:11], v[19:20], 8 +; SI-NEXT: v_add_f64 v[3:4], s[8:9], 1.0 +; SI-NEXT: v_add_f64 v[24:25], s[56:57], 1.0 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(2) +; SI-NEXT: v_lshr_b64 v[1:2], v[3:4], 24 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[19:20], 24 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill +; SI-NEXT: v_lshr_b64 v[10:11], v[24:25], 24 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(2) +; SI-NEXT: v_lshr_b64 v[1:2], v[3:4], 16 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[19:20], 16 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill +; SI-NEXT: v_lshr_b64 v[10:11], v[24:25], 16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(2) +; SI-NEXT: v_lshr_b64 v[1:2], v[3:4], 8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[19:20], 8 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill +; SI-NEXT: v_lshr_b64 v[10:11], v[24:25], 8 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[21:22], 24 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; SI-NEXT: v_add_f64 v[47:48], s[10:11], 1.0 +; SI-NEXT: v_add_f64 v[13:14], s[16:17], 1.0 +; SI-NEXT: v_lshr_b64 v[1:2], v[47:48], 24 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; SI-NEXT: v_add_f64 v[32:33], s[14:15], 1.0 +; SI-NEXT: v_add_f64 v[28:29], s[18:19], 1.0 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[21:22], 16 -; SI-NEXT: v_lshr_b64 v[47:48], v[23:24], 16 -; SI-NEXT: v_add_f64 v[58:59], s[16:17], 1.0 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill -; SI-NEXT: v_lshr_b64 v[35:36], v[21:22], 8 -; SI-NEXT: v_lshr_b64 v[48:49], v[23:24], 8 -; SI-NEXT: v_lshrrev_b32_e32 v27, 24, v2 -; SI-NEXT: v_lshr_b64 v[36:37], v[23:24], 24 -; SI-NEXT: v_lshr_b64 v[49:50], v[38:39], 24 -; SI-NEXT: v_lshr_b64 v[40:41], v[38:39], 8 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[25:26], v[44:45], 8 -; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v2 -; SI-NEXT: v_mov_b32_e32 v37, v27 -; SI-NEXT: v_lshr_b64 v[50:51], v[38:39], 16 -; SI-NEXT: v_lshr_b64 v[41:42], v[52:53], 24 -; SI-NEXT: v_lshr_b64 v[54:55], v[52:53], 8 -; SI-NEXT: v_lshr_b64 v[26:27], v[58:59], 24 -; SI-NEXT: v_lshrrev_b32_e32 v29, 8, v2 -; SI-NEXT: v_mov_b32_e32 v51, v28 -; SI-NEXT: v_lshr_b64 v[42:43], v[52:53], 16 -; SI-NEXT: v_lshr_b64 v[55:56], v[44:45], 24 -; SI-NEXT: v_lshr_b64 v[27:28], v[58:59], 16 -; SI-NEXT: v_mov_b32_e32 v43, v29 -; SI-NEXT: v_lshr_b64 v[56:57], v[44:45], 16 -; SI-NEXT: v_lshr_b64 v[28:29], v[58:59], 8 -; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v4 -; SI-NEXT: v_lshrrev_b32_e32 v30, 8, v4 -; SI-NEXT: v_lshrrev_b32_e32 v34, 24, v6 -; SI-NEXT: v_lshrrev_b32_e32 v60, 8, v45 -; SI-NEXT: v_lshrrev_b32_e32 v31, 24, v59 -; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v59 -; SI-NEXT: v_lshrrev_b32_e32 v46, 8, v59 -; SI-NEXT: v_lshrrev_b32_e32 v57, 24, v4 +; SI-NEXT: v_lshr_b64 v[1:2], v[47:48], 8 +; SI-NEXT: v_lshr_b64 v[17:18], v[13:14], 16 +; SI-NEXT: v_add_f64 v[21:22], s[20:21], 1.0 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: v_lshr_b64 v[15:16], v[32:33], 8 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; SI-NEXT: v_lshr_b64 v[26:27], v[28:29], 8 +; SI-NEXT: v_readfirstlane_b32 s11, v48 +; SI-NEXT: v_lshr_b64 v[51:52], v[47:48], 16 +; SI-NEXT: s_waitcnt expcnt(2) +; SI-NEXT: v_lshr_b64 v[1:2], v[28:29], 24 +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshr_b64 v[16:17], v[28:29], 16 +; SI-NEXT: v_mov_b32_e32 v48, v28 +; SI-NEXT: v_lshr_b64 v[27:28], v[21:22], 8 +; SI-NEXT: v_readfirstlane_b32 s19, v29 +; SI-NEXT: v_lshr_b64 v[28:29], v[30:31], 16 +; SI-NEXT: v_readfirstlane_b32 s23, v31 +; SI-NEXT: v_lshr_b64 v[52:53], v[30:31], 8 +; SI-NEXT: v_readfirstlane_b32 s47, v20 +; SI-NEXT: v_readfirstlane_b32 s43, v43 +; SI-NEXT: v_readfirstlane_b32 s5, v38 +; SI-NEXT: v_lshr_b64 v[38:39], v[42:43], 24 +; SI-NEXT: v_add_f64 v[44:45], s[12:13], 1.0 +; SI-NEXT: v_readfirstlane_b32 s9, v4 +; SI-NEXT: v_lshr_b64 v[58:59], v[44:45], 24 +; SI-NEXT: v_lshr_b64 v[4:5], v[32:33], 16 +; SI-NEXT: v_readfirstlane_b32 s15, v33 +; SI-NEXT: v_readfirstlane_b32 s13, v45 +; SI-NEXT: v_readfirstlane_b32 s7, v36 +; SI-NEXT: v_lshr_b64 v[40:41], v[44:45], 16 +; SI-NEXT: v_lshr_b64 v[59:60], v[44:45], 8 +; SI-NEXT: v_lshr_b64 v[45:46], v[32:33], 24 +; SI-NEXT: v_lshr_b64 v[33:34], v[13:14], 24 +; SI-NEXT: v_lshr_b64 v[5:6], v[13:14], 8 +; SI-NEXT: v_mov_b32_e32 v36, v13 +; SI-NEXT: v_lshr_b64 v[12:13], v[21:22], 24 +; SI-NEXT: v_readfirstlane_b32 s17, v14 +; SI-NEXT: v_lshr_b64 v[13:14], v[7:8], 16 +; SI-NEXT: v_lshr_b64 v[49:50], v[54:55], 8 +; SI-NEXT: v_mov_b32_e32 v14, v9 +; SI-NEXT: v_readfirstlane_b32 s57, v25 +; SI-NEXT: v_mov_b32_e32 v25, v12 +; SI-NEXT: v_mov_b32_e32 v12, v5 +; SI-NEXT: v_mov_b32_e32 v5, v16 +; SI-NEXT: v_readfirstlane_b32 s25, v8 +; SI-NEXT: v_readfirstlane_b32 s21, v22 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[17:18], v[21:22], 16 +; SI-NEXT: v_lshr_b64 v[22:23], v[7:8], 8 +; SI-NEXT: v_mov_b32_e32 v23, v27 +; SI-NEXT: v_mov_b32_e32 v27, v17 +; SI-NEXT: v_mov_b32_e32 v17, v15 +; SI-NEXT: v_readfirstlane_b32 s45, v57 +; SI-NEXT: v_readfirstlane_b32 s41, v55 +; SI-NEXT: s_lshr_b32 s10, s5, 24 +; SI-NEXT: s_lshr_b32 s12, s5, 16 +; SI-NEXT: s_lshr_b32 s14, s5, 8 +; SI-NEXT: s_lshr_b32 s16, s7, 24 +; SI-NEXT: s_lshr_b32 s18, s7, 16 +; SI-NEXT: s_lshr_b32 s20, s7, 8 +; SI-NEXT: s_lshr_b32 s22, s9, 24 +; SI-NEXT: s_lshr_b32 s24, s9, 16 +; SI-NEXT: s_lshr_b32 s26, s9, 8 +; SI-NEXT: s_lshr_b32 s27, s11, 24 +; SI-NEXT: s_lshr_b32 s28, s11, 16 +; SI-NEXT: s_lshr_b32 s29, s11, 8 +; SI-NEXT: s_lshr_b32 s40, s13, 24 +; SI-NEXT: s_lshr_b32 s42, s13, 16 +; SI-NEXT: s_lshr_b32 s44, s13, 8 +; SI-NEXT: s_lshr_b32 s46, s15, 24 +; SI-NEXT: s_lshr_b32 s56, s15, 16 +; SI-NEXT: s_lshr_b32 s58, s15, 8 +; SI-NEXT: s_lshr_b32 s59, s17, 24 +; SI-NEXT: s_waitcnt vmcnt(7) +; SI-NEXT: v_mov_b32_e32 v29, v10 +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; SI-NEXT: s_lshr_b32 s60, s17, 16 +; SI-NEXT: s_lshr_b32 s61, s17, 8 +; SI-NEXT: s_lshr_b32 s62, s19, 24 +; SI-NEXT: s_lshr_b32 s63, s19, 16 +; SI-NEXT: s_lshr_b32 s72, s19, 8 +; SI-NEXT: s_lshr_b32 s73, s21, 24 +; SI-NEXT: s_lshr_b32 s74, s21, 16 +; SI-NEXT: s_lshr_b32 s75, s21, 8 +; SI-NEXT: s_lshr_b32 s76, s23, 24 +; SI-NEXT: s_lshr_b32 s77, s23, 16 +; SI-NEXT: s_lshr_b32 s78, s23, 8 +; SI-NEXT: s_lshr_b32 s79, s25, 24 +; SI-NEXT: s_lshr_b32 s88, s25, 16 +; SI-NEXT: s_lshr_b32 s89, s25, 8 +; SI-NEXT: s_lshr_b32 s90, s41, 24 +; SI-NEXT: s_lshr_b32 s91, s41, 16 +; SI-NEXT: s_lshr_b32 s92, s41, 8 +; SI-NEXT: s_lshr_b32 s93, s43, 24 +; SI-NEXT: s_lshr_b32 s94, s43, 16 +; SI-NEXT: s_lshr_b32 s95, s43, 8 +; SI-NEXT: s_lshr_b32 s30, s45, 24 +; SI-NEXT: s_lshr_b32 s31, s45, 16 +; SI-NEXT: s_lshr_b32 s34, s45, 8 +; SI-NEXT: s_lshr_b32 s35, s47, 24 +; SI-NEXT: s_lshr_b32 s36, s47, 16 +; SI-NEXT: s_lshr_b32 s37, s47, 8 +; SI-NEXT: s_lshr_b32 s8, s57, 24 +; SI-NEXT: s_lshr_b32 vcc_lo, s57, 16 +; SI-NEXT: s_lshr_b32 s6, s57, 8 +; SI-NEXT: v_mov_b32_e32 v34, v4 +; SI-NEXT: v_mov_b32_e32 v53, v51 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v31, v10 +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v20, v10 +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v43, v10 +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v50, v10 +; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v46, v10 +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v16, v10 +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v8, v10 +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v15, v10 +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v51, v10 ; SI-NEXT: s_branch .LBB73_5 ; SI-NEXT: .LBB73_3: -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 0 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 1 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s48, 0 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s49, 1 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr48 ; SI-NEXT: ; implicit-def: $sgpr38 ; SI-NEXT: ; implicit-def: $sgpr36 @@ -116813,7 +115395,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; SI-NEXT: ; implicit-def: $sgpr62 ; SI-NEXT: ; implicit-def: $sgpr60 ; SI-NEXT: ; implicit-def: $sgpr58 -; SI-NEXT: ; implicit-def: $sgpr56 +; SI-NEXT: ; implicit-def: $sgpr28 ; SI-NEXT: ; implicit-def: $sgpr98 ; SI-NEXT: ; implicit-def: $sgpr96 ; SI-NEXT: ; implicit-def: $sgpr86 @@ -116827,580 +115409,351 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; SI-NEXT: ; implicit-def: $sgpr54 ; SI-NEXT: ; implicit-def: $sgpr52 ; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 2 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 3 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s48, 2 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s49, 3 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 4 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 5 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s48, 4 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s49, 5 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 6 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 7 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s48, 6 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s49, 7 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 8 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 9 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s48, 8 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s49, 9 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 10 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 11 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s48, 10 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s49, 11 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 12 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 13 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s48, 12 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s49, 13 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 14 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 15 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s48, 14 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s49, 15 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 16 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 17 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s48, 16 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s49, 17 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 18 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 19 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s48, 18 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s49, 19 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 20 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 21 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s48, 20 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s49, 21 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 22 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 23 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s48, 22 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s49, 23 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 24 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 25 -; SI-NEXT: ; implicit-def: $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s48, 24 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s49, 25 +; SI-NEXT: ; implicit-def: $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 26 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s49, 27 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s48, 26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s49, 27 ; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 28 -; SI-NEXT: v_writelane_b32 v61, s49, 29 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s48, 28 +; SI-NEXT: v_writelane_b32 v62, s49, 29 ; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 30 -; SI-NEXT: v_writelane_b32 v61, s49, 31 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s48, 30 +; SI-NEXT: v_writelane_b32 v62, s49, 31 ; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: v_writelane_b32 v61, s48, 32 -; SI-NEXT: v_writelane_b32 v61, s49, 33 -; SI-NEXT: ; kill: killed $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr46 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: v_writelane_b32 v62, s48, 32 +; SI-NEXT: v_writelane_b32 v62, s49, 33 +; SI-NEXT: ; kill: killed $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr48 ; SI-NEXT: s_branch .LBB73_2 ; SI-NEXT: .LBB73_4: -; SI-NEXT: v_mov_b32_e32 v17, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 34 -; SI-NEXT: v_mov_b32_e32 v37, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 35 -; SI-NEXT: v_mov_b32_e32 v51, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 36 -; SI-NEXT: v_mov_b32_e32 v43, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 37 -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_mov_b32_e32 v57, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 38 -; SI-NEXT: v_mov_b32_e32 v33, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 39 -; SI-NEXT: v_mov_b32_e32 v30, s4 -; SI-NEXT: v_mov_b32_e32 v29, s46 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s98 -; SI-NEXT: v_readlane_b32 s4, v61, 40 -; SI-NEXT: v_mov_b32_e32 v34, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 41 -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 42 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 43 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 44 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 45 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 46 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 47 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 48 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 49 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 50 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 51 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 52 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 53 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 54 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 55 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 56 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 57 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 58 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 59 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 60 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 61 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 62 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 63 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s96 -; SI-NEXT: v_readlane_b32 s4, v62, 0 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 1 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 2 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 3 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 4 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 5 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 6 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 7 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 8 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 9 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 10 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 11 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 12 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 13 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 14 -; SI-NEXT: v_mov_b32_e32 v60, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 15 -; SI-NEXT: v_mov_b32_e32 v31, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 16 -; SI-NEXT: v_mov_b32_e32 v32, s4 -; SI-NEXT: v_readlane_b32 s4, v62, 17 -; SI-NEXT: v_mov_b32_e32 v18, s5 -; SI-NEXT: v_mov_b32_e32 v46, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 0 -; SI-NEXT: v_readlane_b32 s5, v61, 1 -; SI-NEXT: v_mov_b32_e32 v59, s17 -; SI-NEXT: v_mov_b32_e32 v58, s16 -; SI-NEXT: v_mov_b32_e32 v45, s19 -; SI-NEXT: v_mov_b32_e32 v44, s18 -; SI-NEXT: v_mov_b32_e32 v53, s21 -; SI-NEXT: v_mov_b32_e32 v52, s20 -; SI-NEXT: v_mov_b32_e32 v39, s23 -; SI-NEXT: v_mov_b32_e32 v38, s22 -; SI-NEXT: v_mov_b32_e32 v24, s25 -; SI-NEXT: v_mov_b32_e32 v23, s24 -; SI-NEXT: v_mov_b32_e32 v22, s27 -; SI-NEXT: v_mov_b32_e32 v21, s26 -; SI-NEXT: v_mov_b32_e32 v20, s29 -; SI-NEXT: v_mov_b32_e32 v19, s28 -; SI-NEXT: v_mov_b32_e32 v16, s7 -; SI-NEXT: v_mov_b32_e32 v15, s6 -; SI-NEXT: v_mov_b32_e32 v14, s9 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s86 -; SI-NEXT: v_mov_b32_e32 v13, s8 -; SI-NEXT: v_mov_b32_e32 v12, s11 -; SI-NEXT: v_mov_b32_e32 v11, s10 -; SI-NEXT: v_mov_b32_e32 v10, s13 -; SI-NEXT: v_mov_b32_e32 v9, s12 -; SI-NEXT: v_mov_b32_e32 v8, s15 -; SI-NEXT: v_mov_b32_e32 v7, s14 -; SI-NEXT: v_mov_b32_e32 v6, s41 -; SI-NEXT: v_mov_b32_e32 v5, s40 -; SI-NEXT: v_mov_b32_e32 v4, s43 -; SI-NEXT: v_mov_b32_e32 v3, s42 -; SI-NEXT: v_mov_b32_e32 v2, s45 -; SI-NEXT: v_mov_b32_e32 v1, s44 -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v28, s38 -; SI-NEXT: v_mov_b32_e32 v27, s36 -; SI-NEXT: v_mov_b32_e32 v26, s34 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v25, s30 -; SI-NEXT: v_mov_b32_e32 v56, s94 -; SI-NEXT: v_mov_b32_e32 v55, s92 -; SI-NEXT: v_mov_b32_e32 v54, s90 -; SI-NEXT: v_mov_b32_e32 v42, s88 -; SI-NEXT: v_mov_b32_e32 v41, s78 -; SI-NEXT: v_mov_b32_e32 v40, s76 -; SI-NEXT: v_mov_b32_e32 v50, s74 -; SI-NEXT: v_mov_b32_e32 v49, s72 -; SI-NEXT: v_mov_b32_e32 v48, s62 -; SI-NEXT: v_mov_b32_e32 v47, s60 -; SI-NEXT: v_mov_b32_e32 v36, s58 -; SI-NEXT: v_mov_b32_e32 v35, s56 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s84 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s82 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s80 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s70 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s68 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s66 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s64 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s54 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s52 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s50 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 2 -; SI-NEXT: v_readlane_b32 s5, v61, 3 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 4 -; SI-NEXT: v_readlane_b32 s5, v61, 5 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 6 -; SI-NEXT: v_readlane_b32 s5, v61, 7 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 8 -; SI-NEXT: v_readlane_b32 s5, v61, 9 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 10 -; SI-NEXT: v_readlane_b32 s5, v61, 11 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v1, s38 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 12 -; SI-NEXT: v_readlane_b32 s5, v61, 13 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v1, s36 +; SI-NEXT: v_mov_b32_e32 v13, s26 +; SI-NEXT: v_readlane_b32 s26, v62, 0 +; SI-NEXT: v_readlane_b32 s27, v62, 1 +; SI-NEXT: v_mov_b32_e32 v17, s26 +; SI-NEXT: v_readlane_b32 s26, v62, 2 +; SI-NEXT: v_readlane_b32 s27, v62, 3 +; SI-NEXT: v_mov_b32_e32 v34, s26 +; SI-NEXT: v_readlane_b32 s26, v62, 4 +; SI-NEXT: v_readlane_b32 s27, v62, 5 +; SI-NEXT: v_mov_b32_e32 v45, s26 +; SI-NEXT: v_readlane_b32 s26, v62, 6 +; SI-NEXT: v_readlane_b32 s27, v62, 7 +; SI-NEXT: v_mov_b32_e32 v59, s26 +; SI-NEXT: v_readlane_b32 s26, v62, 8 +; SI-NEXT: v_readlane_b32 s27, v62, 9 +; SI-NEXT: v_mov_b32_e32 v40, s26 +; SI-NEXT: v_readlane_b32 s26, v62, 10 +; SI-NEXT: v_readlane_b32 s27, v62, 11 +; SI-NEXT: v_mov_b32_e32 v58, s26 +; SI-NEXT: v_readlane_b32 s26, v62, 12 +; SI-NEXT: v_readlane_b32 s27, v62, 13 +; SI-NEXT: v_mov_b32_e32 v9, s26 +; SI-NEXT: v_readlane_b32 s26, v62, 14 +; SI-NEXT: v_readlane_b32 s27, v62, 15 +; SI-NEXT: v_mov_b32_e32 v53, s26 +; SI-NEXT: v_readlane_b32 s26, v62, 16 +; SI-NEXT: v_readlane_b32 s27, v62, 17 +; SI-NEXT: v_mov_b32_e32 v50, s26 +; SI-NEXT: v_readlane_b32 s26, v62, 18 +; SI-NEXT: v_readlane_b32 s27, v62, 19 +; SI-NEXT: v_mov_b32_e32 v29, s26 +; SI-NEXT: v_readlane_b32 s26, v62, 20 +; SI-NEXT: v_readlane_b32 s27, v62, 21 +; SI-NEXT: v_mov_b32_e32 v31, s26 +; SI-NEXT: v_readlane_b32 s26, v62, 22 +; SI-NEXT: v_readlane_b32 s27, v62, 23 +; SI-NEXT: v_mov_b32_e32 v20, s26 +; SI-NEXT: v_readlane_b32 s26, v62, 24 +; SI-NEXT: v_readlane_b32 s27, v62, 25 +; SI-NEXT: v_mov_b32_e32 v43, s26 +; SI-NEXT: v_readlane_b32 s26, v62, 26 +; SI-NEXT: v_readlane_b32 s27, v62, 27 +; SI-NEXT: v_mov_b32_e32 v46, s26 +; SI-NEXT: v_readlane_b32 s26, v62, 28 +; SI-NEXT: v_readlane_b32 s27, v62, 29 +; SI-NEXT: v_mov_b32_e32 v16, s26 +; SI-NEXT: v_readlane_b32 s26, v62, 30 +; SI-NEXT: v_readlane_b32 s27, v62, 31 +; SI-NEXT: v_mov_b32_e32 v51, s26 +; SI-NEXT: v_readlane_b32 s26, v62, 32 +; SI-NEXT: v_mov_b32_e32 v3, s8 +; SI-NEXT: v_readlane_b32 s27, v62, 33 +; SI-NEXT: v_mov_b32_e32 v38, s72 +; SI-NEXT: v_mov_b32_e32 v49, s62 +; SI-NEXT: v_mov_b32_e32 v22, s28 +; SI-NEXT: v_mov_b32_e32 v24, s56 +; SI-NEXT: v_mov_b32_e32 v19, s46 +; SI-NEXT: v_mov_b32_e32 v56, s44 +; SI-NEXT: v_mov_b32_e32 v42, s42 +; SI-NEXT: v_mov_b32_e32 v54, s40 +; SI-NEXT: v_mov_b32_e32 v7, s24 +; SI-NEXT: v_mov_b32_e32 v30, s22 +; SI-NEXT: v_mov_b32_e32 v21, s20 +; SI-NEXT: v_mov_b32_e32 v48, s18 +; SI-NEXT: v_mov_b32_e32 v36, s16 +; SI-NEXT: v_mov_b32_e32 v32, s14 +; SI-NEXT: v_mov_b32_e32 v44, s12 +; SI-NEXT: v_mov_b32_e32 v47, s10 +; SI-NEXT: v_mov_b32_e32 v35, s6 +; SI-NEXT: v_mov_b32_e32 v37, s4 +; SI-NEXT: v_mov_b32_e32 v52, s96 +; SI-NEXT: v_mov_b32_e32 v28, s86 +; SI-NEXT: v_mov_b32_e32 v14, s84 +; SI-NEXT: v_mov_b32_e32 v23, s82 +; SI-NEXT: v_mov_b32_e32 v27, s80 +; SI-NEXT: v_mov_b32_e32 v25, s70 +; SI-NEXT: v_mov_b32_e32 v26, s68 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 14 -; SI-NEXT: v_readlane_b32 s5, v61, 15 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v1, s34 +; SI-NEXT: v_mov_b32_e32 v5, s66 +; SI-NEXT: v_mov_b32_e32 v12, s54 +; SI-NEXT: v_mov_b32_e32 v33, s50 +; SI-NEXT: v_mov_b32_e32 v8, s48 +; SI-NEXT: v_mov_b32_e32 v15, s26 +; SI-NEXT: v_readlane_b32 s10, v62, 34 +; SI-NEXT: v_readlane_b32 s12, v62, 35 +; SI-NEXT: v_readlane_b32 s14, v62, 36 +; SI-NEXT: v_readlane_b32 s16, v62, 37 +; SI-NEXT: v_readlane_b32 s18, v62, 38 +; SI-NEXT: v_readlane_b32 s20, v62, 39 +; SI-NEXT: v_readlane_b32 s22, v62, 40 +; SI-NEXT: v_readlane_b32 s24, v62, 41 +; SI-NEXT: v_readlane_b32 s26, v62, 42 +; SI-NEXT: v_readlane_b32 s27, v62, 43 +; SI-NEXT: v_readlane_b32 s28, v62, 44 +; SI-NEXT: v_readlane_b32 s29, v62, 45 +; SI-NEXT: v_readlane_b32 s40, v62, 46 +; SI-NEXT: v_readlane_b32 s42, v62, 47 +; SI-NEXT: v_readlane_b32 s44, v62, 48 +; SI-NEXT: v_readlane_b32 s46, v62, 49 +; SI-NEXT: v_readlane_b32 s56, v62, 50 +; SI-NEXT: v_readlane_b32 s59, v62, 52 +; SI-NEXT: v_readlane_b32 s61, v62, 54 +; SI-NEXT: v_readlane_b32 s62, v62, 55 +; SI-NEXT: v_readlane_b32 s63, v62, 56 +; SI-NEXT: v_readlane_b32 s72, v62, 57 +; SI-NEXT: v_readlane_b32 s73, v62, 58 +; SI-NEXT: v_readlane_b32 s75, v62, 60 +; SI-NEXT: v_readlane_b32 s77, v62, 62 +; SI-NEXT: v_readlane_b32 s79, v61, 0 +; SI-NEXT: v_readlane_b32 s89, v61, 2 +; SI-NEXT: v_readlane_b32 s91, v61, 4 +; SI-NEXT: v_readlane_b32 s93, v61, 6 +; SI-NEXT: v_readlane_b32 s95, v61, 8 +; SI-NEXT: v_readlane_b32 s31, v61, 10 +; SI-NEXT: v_readlane_b32 s34, v61, 11 +; SI-NEXT: v_readlane_b32 s35, v61, 12 +; SI-NEXT: v_readlane_b32 s36, v61, 13 +; SI-NEXT: v_readlane_b32 s37, v61, 14 +; SI-NEXT: v_readlane_b32 s8, v61, 15 +; SI-NEXT: v_readlane_b32 vcc_lo, v61, 16 +; SI-NEXT: v_readlane_b32 s6, v61, 17 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 16 -; SI-NEXT: v_readlane_b32 s5, v61, 17 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v1, s30 +; SI-NEXT: v_readlane_b32 s30, v61, 9 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 18 -; SI-NEXT: v_readlane_b32 s5, v61, 19 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v1, s94 +; SI-NEXT: v_readlane_b32 s94, v61, 7 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 20 -; SI-NEXT: v_readlane_b32 s5, v61, 21 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v1, s92 +; SI-NEXT: v_readlane_b32 s92, v61, 5 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 22 -; SI-NEXT: v_readlane_b32 s5, v61, 23 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v1, s90 +; SI-NEXT: v_readlane_b32 s90, v61, 3 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 24 -; SI-NEXT: v_readlane_b32 s5, v61, 25 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v1, s88 +; SI-NEXT: v_readlane_b32 s88, v61, 1 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 26 -; SI-NEXT: v_readlane_b32 s5, v61, 27 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v1, s78 +; SI-NEXT: v_readlane_b32 s78, v62, 63 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 28 -; SI-NEXT: v_readlane_b32 s5, v61, 29 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v1, s76 +; SI-NEXT: v_readlane_b32 s76, v62, 61 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 30 -; SI-NEXT: v_readlane_b32 s5, v61, 31 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v1, s74 +; SI-NEXT: v_readlane_b32 s74, v62, 59 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s4 -; SI-NEXT: v_readlane_b32 s4, v61, 32 -; SI-NEXT: v_readlane_b32 s5, v61, 33 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v1, s60 +; SI-NEXT: v_readlane_b32 s60, v62, 53 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s48 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v1, s58 +; SI-NEXT: v_readlane_b32 s58, v62, 51 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_mov_b32_e32 v29, s4 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v1, s98 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v2, s52 +; SI-NEXT: v_mov_b32_e32 v1, s64 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: .LBB73_5: ; %end -; SI-NEXT: v_lshlrev_b32_e32 v28, 8, v28 +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_and_b32_e32 v29, 0xff, v58 -; SI-NEXT: v_and_b32_e32 v27, 0xff, v27 -; SI-NEXT: v_or_b32_e32 v28, v29, v28 -; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v26 -; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27 -; SI-NEXT: v_or_b32_e32 v26, v26, v27 -; SI-NEXT: v_and_b32_e32 v27, 0xffff, v28 -; SI-NEXT: v_or_b32_e32 v26, v27, v26 -; SI-NEXT: buffer_store_dword v26, v0, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v26, 0xff, v59 -; SI-NEXT: v_lshlrev_b32_e32 v27, 8, v46 -; SI-NEXT: v_or_b32_e32 v26, v26, v27 -; SI-NEXT: v_and_b32_e32 v27, 0xff, v32 -; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27 -; SI-NEXT: v_lshlrev_b32_e32 v28, 24, v31 -; SI-NEXT: v_or_b32_e32 v27, v28, v27 -; SI-NEXT: v_and_b32_e32 v26, 0xffff, v26 -; SI-NEXT: v_or_b32_e32 v26, v26, v27 -; SI-NEXT: v_add_i32_e32 v27, vcc, 4, v0 -; SI-NEXT: buffer_store_dword v26, v27, s[0:3], 0 offen -; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v25 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v26, 0xff, v44 -; SI-NEXT: v_or_b32_e32 v25, v26, v25 -; SI-NEXT: v_and_b32_e32 v26, 0xff, v56 -; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v55 -; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; SI-NEXT: v_or_b32_e32 v26, v27, v26 -; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25 -; SI-NEXT: v_or_b32_e32 v25, v25, v26 -; SI-NEXT: v_add_i32_e32 v26, vcc, 8, v0 -; SI-NEXT: buffer_store_dword v25, v26, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v25, 0xff, v45 -; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v60 -; SI-NEXT: v_or_b32_e32 v25, v25, v26 -; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25 -; SI-NEXT: v_and_b32_e32 v23, 0xff, v23 -; SI-NEXT: v_and_b32_e32 v21, 0xff, v21 -; SI-NEXT: v_and_b32_e32 v19, 0xff, v19 -; SI-NEXT: v_and_b32_e32 v17, 0xff, v17 -; SI-NEXT: v_and_b32_e32 v15, 0xff, v15 -; SI-NEXT: v_and_b32_e32 v13, 0xff, v13 -; SI-NEXT: v_and_b32_e32 v11, 0xff, v11 -; SI-NEXT: v_and_b32_e32 v9, 0xff, v9 -; SI-NEXT: v_and_b32_e32 v7, 0xff, v7 -; SI-NEXT: v_and_b32_e32 v5, 0xff, v5 -; SI-NEXT: v_and_b32_e32 v3, 0xff, v3 -; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 +; SI-NEXT: v_and_b32_e32 v2, 0xff, v24 +; SI-NEXT: s_and_b32 s4, s57, 0xff +; SI-NEXT: s_lshl_b32 s6, s6, 8 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_and_b32 s6, vcc_lo, 0xff +; SI-NEXT: s_lshl_b32 s6, s6, 16 +; SI-NEXT: s_lshl_b32 s8, s8, 24 +; SI-NEXT: s_and_b32 s4, s4, 0xffff +; SI-NEXT: s_or_b32 s6, s8, s6 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_lshl_b32 s6, s37, 8 +; SI-NEXT: s_lshl_b32 s8, s35, 24 ; SI-NEXT: v_readlane_b32 s99, v63, 35 ; SI-NEXT: v_readlane_b32 s98, v63, 34 ; SI-NEXT: v_readlane_b32 s97, v63, 33 @@ -117432,509 +115785,436 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; SI-NEXT: v_readlane_b32 s39, v63, 7 ; SI-NEXT: v_readlane_b32 s38, v63, 6 ; SI-NEXT: v_readlane_b32 s37, v63, 5 -; SI-NEXT: v_readlane_b32 s36, v63, 4 ; SI-NEXT: v_readlane_b32 s35, v63, 3 -; SI-NEXT: v_readlane_b32 s34, v63, 2 -; SI-NEXT: v_readlane_b32 s31, v63, 1 -; SI-NEXT: v_readlane_b32 s30, v63, 0 ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v26, 0xff, v26 -; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v27 -; SI-NEXT: v_or_b32_e32 v26, v27, v26 -; SI-NEXT: v_or_b32_e32 v25, v25, v26 -; SI-NEXT: v_add_i32_e32 v26, vcc, 12, v0 -; SI-NEXT: buffer_store_dword v25, v26, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v54 -; SI-NEXT: v_and_b32_e32 v26, 0xff, v52 -; SI-NEXT: v_or_b32_e32 v25, v26, v25 -; SI-NEXT: v_and_b32_e32 v26, 0xff, v42 -; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v41 -; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; SI-NEXT: v_or_b32_e32 v26, v27, v26 -; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25 -; SI-NEXT: v_or_b32_e32 v25, v25, v26 -; SI-NEXT: v_add_i32_e32 v26, vcc, 16, v0 -; SI-NEXT: buffer_store_dword v25, v26, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v25, 0xff, v53 -; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v10 +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26 -; SI-NEXT: v_or_b32_e32 v25, v25, v26 -; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25 +; SI-NEXT: v_and_b32_e32 v4, 0xff, v10 +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v27 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v26, 0xff, v26 -; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; SI-NEXT: v_or_b32_e32 v26, v27, v26 -; SI-NEXT: v_or_b32_e32 v25, v25, v26 -; SI-NEXT: v_add_i32_e32 v26, vcc, 20, v0 -; SI-NEXT: buffer_store_dword v25, v26, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v40 -; SI-NEXT: v_and_b32_e32 v26, 0xff, v38 -; SI-NEXT: v_or_b32_e32 v25, v26, v25 -; SI-NEXT: v_and_b32_e32 v26, 0xff, v50 -; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v49 -; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; SI-NEXT: v_or_b32_e32 v26, v27, v26 -; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25 -; SI-NEXT: v_or_b32_e32 v25, v25, v26 -; SI-NEXT: v_add_i32_e32 v26, vcc, 24, v0 -; SI-NEXT: buffer_store_dword v25, v26, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v10 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v25, 0xff, v39 -; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0 +; SI-NEXT: v_mov_b32_e32 v4, s4 +; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v2, 0xff, v19 +; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; SI-NEXT: s_and_b32 s4, s47, 0xff +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_and_b32 s6, s36, 0xff +; SI-NEXT: s_lshl_b32 s6, s6, 16 +; SI-NEXT: s_and_b32 s4, s4, 0xffff +; SI-NEXT: s_or_b32 s6, s8, s6 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_lshl_b32 s6, s34, 8 +; SI-NEXT: s_lshl_b32 s8, s30, 24 +; SI-NEXT: v_readlane_b32 s36, v63, 4 +; SI-NEXT: v_readlane_b32 s34, v63, 2 +; SI-NEXT: v_readlane_b32 s30, v63, 0 +; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v18 +; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v26 -; SI-NEXT: v_or_b32_e32 v25, v25, v26 -; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v25, 0xffff, v25 +; SI-NEXT: v_and_b32_e32 v4, 0xff, v18 +; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v27 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v26, 0xff, v26 -; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26 -; SI-NEXT: v_or_b32_e32 v26, v27, v26 -; SI-NEXT: v_or_b32_e32 v25, v25, v26 -; SI-NEXT: v_add_i32_e32 v26, vcc, 28, v0 -; SI-NEXT: buffer_store_dword v25, v26, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v48 -; SI-NEXT: v_or_b32_e32 v23, v23, v25 -; SI-NEXT: v_and_b32_e32 v25, 0xff, v47 -; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v36 -; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25 -; SI-NEXT: v_or_b32_e32 v25, v26, v25 -; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23 -; SI-NEXT: v_or_b32_e32 v23, v23, v25 -; SI-NEXT: v_add_i32_e32 v25, vcc, 32, v0 -; SI-NEXT: buffer_store_dword v23, v25, s[0:3], 0 offen +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v18 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 8, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v23, 0xff, v24 -; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0 +; SI-NEXT: v_mov_b32_e32 v4, s4 +; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v2, 0xff, v56 +; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload +; SI-NEXT: s_and_b32 s4, s45, 0xff +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_and_b32 s6, s31, 0xff +; SI-NEXT: s_lshl_b32 s6, s6, 16 +; SI-NEXT: s_and_b32 s4, s4, 0xffff +; SI-NEXT: s_or_b32 s6, s8, s6 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_lshl_b32 s6, s95, 8 +; SI-NEXT: s_lshl_b32 s8, s93, 24 +; SI-NEXT: v_readlane_b32 s31, v63, 1 +; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v55 +; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v24 -; SI-NEXT: v_or_b32_e32 v23, v23, v24 -; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23 +; SI-NEXT: v_and_b32_e32 v4, 0xff, v55 +; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v25 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v24, 0xff, v24 -; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; SI-NEXT: v_or_b32_e32 v24, v25, v24 -; SI-NEXT: v_or_b32_e32 v23, v23, v24 -; SI-NEXT: v_add_i32_e32 v24, vcc, 36, v0 -; SI-NEXT: buffer_store_dword v23, v24, s[0:3], 0 offen +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v55 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 16, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v23, 8, v35 -; SI-NEXT: v_or_b32_e32 v21, v21, v23 -; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v23, 0xff, v23 +; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0 +; SI-NEXT: v_mov_b32_e32 v4, s4 +; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v2, 0xff, v42 +; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; SI-NEXT: s_and_b32 s4, s43, 0xff +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_and_b32 s6, s94, 0xff +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v38 +; SI-NEXT: s_lshl_b32 s6, s6, 16 +; SI-NEXT: s_and_b32 s4, s4, 0xffff +; SI-NEXT: s_or_b32 s6, s8, s6 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_lshl_b32 s6, s92, 8 +; SI-NEXT: s_lshl_b32 s8, s90, 24 +; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v41 +; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v24 -; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; SI-NEXT: v_or_b32_e32 v23, v24, v23 -; SI-NEXT: v_or_b32_e32 v21, v21, v23 -; SI-NEXT: v_add_i32_e32 v23, vcc, 40, v0 -; SI-NEXT: buffer_store_dword v21, v23, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v4, 0xff, v41 +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 24, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v21, 0xff, v22 -; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v22 -; SI-NEXT: v_or_b32_e32 v21, v21, v22 -; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v23, 24, v23 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v22, 0xff, v22 -; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; SI-NEXT: v_or_b32_e32 v22, v23, v22 -; SI-NEXT: v_or_b32_e32 v21, v21, v22 -; SI-NEXT: v_add_i32_e32 v22, vcc, 44, v0 -; SI-NEXT: buffer_store_dword v21, v22, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0 +; SI-NEXT: v_mov_b32_e32 v4, s4 +; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v2, 0xff, v54 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v49 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: s_and_b32 s4, s41, 0xff +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_and_b32 s6, s91, 0xff +; SI-NEXT: s_lshl_b32 s6, s6, 16 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: s_and_b32 s4, s4, 0xffff +; SI-NEXT: s_or_b32 s6, s8, s6 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_lshl_b32 s6, s89, 8 +; SI-NEXT: s_lshl_b32 s8, s79, 24 ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v21 -; SI-NEXT: v_or_b32_e32 v19, v19, v21 -; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v21, 0xff, v21 +; SI-NEXT: v_and_b32_e32 v4, 0xff, v38 +; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v22 -; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; SI-NEXT: v_or_b32_e32 v21, v22, v21 -; SI-NEXT: v_or_b32_e32 v19, v19, v21 -; SI-NEXT: v_add_i32_e32 v21, vcc, 48, v0 -; SI-NEXT: buffer_store_dword v19, v21, s[0:3], 0 offen +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v38 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 32, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v19, 0xff, v20 -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v20, 8, v20 -; SI-NEXT: v_or_b32_e32 v19, v19, v20 -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v21 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v20, 0xff, v20 -; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; SI-NEXT: v_or_b32_e32 v20, v21, v20 -; SI-NEXT: v_or_b32_e32 v19, v19, v20 -; SI-NEXT: v_add_i32_e32 v20, vcc, 52, v0 -; SI-NEXT: buffer_store_dword v19, v20, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0 +; SI-NEXT: v_mov_b32_e32 v4, s4 +; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v2, 0xff, v7 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v19 -; SI-NEXT: v_or_b32_e32 v17, v17, v19 -; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v19, 0xff, v19 +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v22 +; SI-NEXT: s_and_b32 s4, s25, 0xff +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_and_b32_e32 v4, 0xff, v13 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_and_b32 s6, s88, 0xff +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; SI-NEXT: s_lshl_b32 s6, s6, 16 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: s_and_b32 s4, s4, 0xffff +; SI-NEXT: s_or_b32 s6, s8, s6 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_lshl_b32 s6, s78, 8 +; SI-NEXT: s_lshl_b32 s8, s76, 24 ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v20 -; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; SI-NEXT: v_or_b32_e32 v19, v20, v19 -; SI-NEXT: v_or_b32_e32 v17, v17, v19 -; SI-NEXT: v_add_i32_e32 v19, vcc, 56, v0 -; SI-NEXT: buffer_store_dword v17, v19, s[0:3], 0 offen +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 40, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v17, 0xff, v18 -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18 -; SI-NEXT: v_or_b32_e32 v17, v17, v18 -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v19, 24, v19 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v18, 0xff, v18 -; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18 -; SI-NEXT: v_or_b32_e32 v18, v19, v18 -; SI-NEXT: v_or_b32_e32 v17, v17, v18 -; SI-NEXT: v_add_i32_e32 v18, vcc, 60, v0 -; SI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; SI-NEXT: v_or_b32_e32 v15, v15, v17 -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v17, 0xff, v17 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v18 -; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; SI-NEXT: v_or_b32_e32 v17, v18, v17 -; SI-NEXT: v_or_b32_e32 v15, v15, v17 -; SI-NEXT: v_add_i32_e32 v17, vcc, 64, v0 -; SI-NEXT: buffer_store_dword v15, v17, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0 +; SI-NEXT: v_mov_b32_e32 v4, s4 +; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v2, 0xff, v30 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v15, 0xff, v16 -; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16 -; SI-NEXT: v_or_b32_e32 v15, v15, v16 -; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17 -; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v16, 0xff, v16 -; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; SI-NEXT: v_or_b32_e32 v16, v17, v16 -; SI-NEXT: v_or_b32_e32 v15, v15, v16 -; SI-NEXT: v_add_i32_e32 v16, vcc, 0x44, v0 -; SI-NEXT: buffer_store_dword v15, v16, s[0:3], 0 offen +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v52 +; SI-NEXT: s_and_b32 s4, s23, 0xff +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_and_b32_e32 v4, 0xff, v28 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_and_b32 s6, s77, 0xff +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v14 +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; SI-NEXT: s_lshl_b32 s6, s6, 16 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: s_and_b32 s4, s4, 0xffff +; SI-NEXT: s_or_b32 s6, s8, s6 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 48, v0 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15 -; SI-NEXT: v_or_b32_e32 v13, v13, v15 -; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v15, 0xff, v15 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16 -; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; SI-NEXT: v_or_b32_e32 v15, v16, v15 -; SI-NEXT: v_or_b32_e32 v13, v13, v15 -; SI-NEXT: v_add_i32_e32 v15, vcc, 0x48, v0 -; SI-NEXT: buffer_store_dword v13, v15, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0 +; SI-NEXT: v_mov_b32_e32 v4, s4 +; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v2, 0xff, v21 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v13, 0xff, v14 -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14 -; SI-NEXT: v_or_b32_e32 v13, v13, v14 -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15 -; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v14, 0xff, v14 -; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; SI-NEXT: v_or_b32_e32 v14, v15, v14 -; SI-NEXT: v_or_b32_e32 v13, v13, v14 -; SI-NEXT: v_add_i32_e32 v14, vcc, 0x4c, v0 -; SI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v23 +; SI-NEXT: s_and_b32 s4, s21, 0xff +; SI-NEXT: s_lshl_b32 s6, s75, 8 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_and_b32_e32 v4, 0xff, v27 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_and_b32 s6, s74, 0xff +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v25 +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; SI-NEXT: s_lshl_b32 s6, s6, 16 +; SI-NEXT: s_lshl_b32 s8, s73, 24 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: s_and_b32 s4, s4, 0xffff +; SI-NEXT: s_or_b32 s6, s8, s6 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 56, v0 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13 -; SI-NEXT: v_or_b32_e32 v11, v11, v13 -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v13, 0xff, v13 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14 -; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; SI-NEXT: v_or_b32_e32 v13, v14, v13 -; SI-NEXT: v_or_b32_e32 v11, v11, v13 -; SI-NEXT: v_add_i32_e32 v13, vcc, 0x50, v0 -; SI-NEXT: buffer_store_dword v11, v13, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v0 +; SI-NEXT: v_mov_b32_e32 v4, s4 +; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v2, 0xff, v48 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v11, 0xff, v12 -; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v12 -; SI-NEXT: v_or_b32_e32 v11, v11, v12 -; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13 -; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v12, 0xff, v12 -; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; SI-NEXT: v_or_b32_e32 v12, v13, v12 -; SI-NEXT: v_or_b32_e32 v11, v11, v12 -; SI-NEXT: v_add_i32_e32 v12, vcc, 0x54, v0 -; SI-NEXT: buffer_store_dword v11, v12, s[0:3], 0 offen +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v26 +; SI-NEXT: s_and_b32 s4, s19, 0xff +; SI-NEXT: s_lshl_b32 s6, s72, 8 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_and_b32_e32 v4, 0xff, v5 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_and_b32 s6, s63, 0xff +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v1 +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; SI-NEXT: s_lshl_b32 s6, s6, 16 +; SI-NEXT: s_lshl_b32 s8, s62, 24 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: s_and_b32 s4, s4, 0xffff +; SI-NEXT: s_or_b32 s6, s8, s6 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 64, v0 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v11, 8, v11 -; SI-NEXT: v_or_b32_e32 v9, v9, v11 -; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v11, 0xff, v11 -; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12 -; SI-NEXT: v_or_b32_e32 v11, v12, v11 -; SI-NEXT: v_or_b32_e32 v9, v9, v11 -; SI-NEXT: v_add_i32_e32 v11, vcc, 0x58, v0 -; SI-NEXT: buffer_store_dword v9, v11, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v0 +; SI-NEXT: v_mov_b32_e32 v4, s4 +; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v9, 0xff, v10 -; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v10 -; SI-NEXT: v_or_b32_e32 v9, v9, v10 -; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v12 +; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v2, 0xff, v36 +; SI-NEXT: s_and_b32 s4, s17, 0xff +; SI-NEXT: s_lshl_b32 s6, s61, 8 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_and_b32 s6, s60, 0xff +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v33 +; SI-NEXT: s_lshl_b32 s6, s6, 16 +; SI-NEXT: s_lshl_b32 s8, s59, 24 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: s_and_b32 s4, s4, 0xffff +; SI-NEXT: s_or_b32 s6, s8, s6 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_lshl_b32 s6, s58, 8 +; SI-NEXT: s_lshl_b32 s8, s46, 24 +; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v20 +; SI-NEXT: v_and_b32_e32 v1, 0xff, v37 ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v11 -; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v10, 0xff, v10 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_or_b32_e32 v10, v11, v10 -; SI-NEXT: v_or_b32_e32 v9, v9, v10 -; SI-NEXT: v_add_i32_e32 v10, vcc, 0x5c, v0 -; SI-NEXT: buffer_store_dword v9, v10, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v4, 0xff, v12 +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 0x48, v0 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9 -; SI-NEXT: v_or_b32_e32 v7, v7, v9 -; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v9, 0xff, v9 -; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v10, 24, v10 -; SI-NEXT: v_or_b32_e32 v9, v10, v9 -; SI-NEXT: v_or_b32_e32 v7, v7, v9 -; SI-NEXT: v_add_i32_e32 v9, vcc, 0x60, v0 -; SI-NEXT: buffer_store_dword v7, v9, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v0 +; SI-NEXT: v_mov_b32_e32 v4, s4 +; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v2, 0xff, v32 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v7, 0xff, v8 -; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8 -; SI-NEXT: v_or_b32_e32 v7, v7, v8 -; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v9 -; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v8, 0xff, v8 -; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; SI-NEXT: v_or_b32_e32 v8, v9, v8 -; SI-NEXT: v_or_b32_e32 v7, v7, v8 -; SI-NEXT: v_add_i32_e32 v8, vcc, 0x64, v0 -; SI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v17 +; SI-NEXT: s_and_b32 s4, s15, 0xff +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_and_b32_e32 v4, 0xff, v34 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_and_b32 s6, s56, 0xff +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v45 +; SI-NEXT: s_lshl_b32 s6, s6, 16 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: s_and_b32 s4, s4, 0xffff +; SI-NEXT: s_or_b32 s6, s8, s6 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 0x50, v0 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v7 -; SI-NEXT: v_or_b32_e32 v5, v5, v7 -; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v7, 0xff, v7 -; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v8 -; SI-NEXT: v_or_b32_e32 v7, v8, v7 -; SI-NEXT: v_or_b32_e32 v5, v5, v7 -; SI-NEXT: v_add_i32_e32 v7, vcc, 0x68, v0 -; SI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v0 +; SI-NEXT: v_mov_b32_e32 v4, s4 +; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v2, 0xff, v44 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v5, 0xff, v6 -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v34 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6 -; SI-NEXT: v_or_b32_e32 v5, v5, v6 -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v6, 0xff, v6 -; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; SI-NEXT: v_or_b32_e32 v6, v7, v6 -; SI-NEXT: v_or_b32_e32 v5, v5, v6 -; SI-NEXT: v_add_i32_e32 v6, vcc, 0x6c, v0 -; SI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v59 +; SI-NEXT: s_and_b32 s4, s13, 0xff +; SI-NEXT: s_lshl_b32 s6, s44, 8 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_and_b32_e32 v4, 0xff, v40 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_and_b32 s6, s42, 0xff +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v58 +; SI-NEXT: s_lshl_b32 s6, s6, 16 +; SI-NEXT: s_lshl_b32 s8, s40, 24 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: s_and_b32 s4, s4, 0xffff +; SI-NEXT: s_or_b32 s6, s8, s6 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 0x58, v0 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5 -; SI-NEXT: v_or_b32_e32 v3, v3, v5 -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v5, 0xff, v5 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v6 -; SI-NEXT: v_or_b32_e32 v5, v6, v5 -; SI-NEXT: v_or_b32_e32 v3, v3, v5 -; SI-NEXT: v_add_i32_e32 v5, vcc, 0x70, v0 -; SI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v0 +; SI-NEXT: v_mov_b32_e32 v4, s4 +; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v2, 0xff, v47 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v3, 0xff, v4 -; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v30 -; SI-NEXT: v_or_b32_e32 v3, v3, v4 -; SI-NEXT: v_and_b32_e32 v4, 0xff, v33 +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v9 +; SI-NEXT: s_and_b32 s4, s11, 0xff +; SI-NEXT: s_lshl_b32 s6, s29, 8 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_and_b32_e32 v4, 0xff, v53 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_and_b32 s6, s28, 0xff ; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v57 -; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3 +; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v50 +; SI-NEXT: s_lshl_b32 s6, s6, 16 +; SI-NEXT: s_lshl_b32 s8, s27, 24 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; SI-NEXT: v_or_b32_e32 v4, v6, v4 +; SI-NEXT: s_and_b32 s4, s4, 0xffff +; SI-NEXT: s_or_b32 s6, s8, s6 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 0x60, v0 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x64, v0 +; SI-NEXT: v_mov_b32_e32 v4, s4 +; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v2, 0xff, v3 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v29 +; SI-NEXT: s_and_b32 s4, s9, 0xff +; SI-NEXT: s_lshl_b32 s6, s26, 8 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_and_b32_e32 v4, 0xff, v31 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_and_b32 s6, s24, 0xff +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; SI-NEXT: s_lshl_b32 s6, s6, 16 +; SI-NEXT: s_lshl_b32 s8, s22, 24 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; SI-NEXT: v_or_b32_e32 v4, v5, v4 -; SI-NEXT: v_or_b32_e32 v3, v3, v4 -; SI-NEXT: v_add_i32_e32 v4, vcc, 0x74, v0 -; SI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen +; SI-NEXT: s_and_b32 s4, s4, 0xffff +; SI-NEXT: s_or_b32 s6, s8, s6 +; SI-NEXT: v_or_b32_e32 v2, v2, v4 +; SI-NEXT: v_add_i32_e32 v4, vcc, 0x68, v0 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3 -; SI-NEXT: v_or_b32_e32 v1, v1, v3 -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v3, 0xff, v3 +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0 +; SI-NEXT: v_mov_b32_e32 v4, s4 +; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen +; SI-NEXT: v_and_b32_e32 v2, 0xff, v35 +; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v43 +; SI-NEXT: s_and_b32 s4, s7, 0xff +; SI-NEXT: s_lshl_b32 s6, s20, 8 +; SI-NEXT: v_or_b32_e32 v2, v2, v3 +; SI-NEXT: v_and_b32_e32 v3, 0xff, v46 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: s_and_b32 s6, s18, 0xff ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v16 +; SI-NEXT: s_lshl_b32 s6, s6, 16 +; SI-NEXT: s_lshl_b32 s7, s16, 24 +; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; SI-NEXT: v_or_b32_e32 v3, v4, v3 -; SI-NEXT: v_or_b32_e32 v1, v1, v3 -; SI-NEXT: v_add_i32_e32 v3, vcc, 0x78, v0 -; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: s_and_b32 s4, s4, 0xffff +; SI-NEXT: s_or_b32 s6, s7, s6 +; SI-NEXT: v_or_b32_e32 v2, v2, v3 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x70, v0 +; SI-NEXT: s_or_b32 s4, s4, s6 +; SI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v2 -; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v43 +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0 +; SI-NEXT: v_mov_b32_e32 v3, s4 +; SI-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen +; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v51 +; SI-NEXT: s_and_b32 s4, s5, 0xff +; SI-NEXT: s_lshl_b32 s5, s14, 8 ; SI-NEXT: v_or_b32_e32 v1, v1, v2 -; SI-NEXT: v_and_b32_e32 v2, 0xff, v51 +; SI-NEXT: v_and_b32_e32 v2, 0xff, v8 +; SI-NEXT: s_or_b32 s4, s4, s5 +; SI-NEXT: s_and_b32 s5, s12, 0xff ; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v37 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v15 +; SI-NEXT: s_lshl_b32 s5, s5, 16 +; SI-NEXT: s_lshl_b32 s6, s10, 24 ; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; SI-NEXT: v_or_b32_e32 v2, v3, v2 +; SI-NEXT: s_and_b32 s4, s4, 0xffff +; SI-NEXT: s_or_b32 s5, s6, s5 ; SI-NEXT: v_or_b32_e32 v1, v1, v2 +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0 +; SI-NEXT: s_or_b32 s4, s4, s5 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v1, s4 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload @@ -117950,9 +116230,9 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload ; SI-NEXT: s_or_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] @@ -117961,8 +116241,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-NEXT: s_or_saveexec_b64 s[4:5], -1 -; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] ; VI-NEXT: v_writelane_b32 v63, s30, 0 ; VI-NEXT: v_writelane_b32 v63, s31, 1 @@ -117982,40 +116262,68 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; VI-NEXT: v_writelane_b32 v63, s55, 15 ; VI-NEXT: v_writelane_b32 v63, s64, 16 ; VI-NEXT: v_writelane_b32 v63, s65, 17 +; VI-NEXT: v_mov_b32_e32 v20, s16 ; VI-NEXT: v_writelane_b32 v63, s66, 18 +; VI-NEXT: v_readfirstlane_b32 s56, v20 +; VI-NEXT: v_mov_b32_e32 v20, s17 ; VI-NEXT: v_writelane_b32 v63, s67, 19 +; VI-NEXT: v_readfirstlane_b32 s57, v20 +; VI-NEXT: v_mov_b32_e32 v20, s18 ; VI-NEXT: v_writelane_b32 v63, s68, 20 +; VI-NEXT: v_readfirstlane_b32 s46, v20 +; VI-NEXT: v_mov_b32_e32 v20, s19 ; VI-NEXT: v_writelane_b32 v63, s69, 21 +; VI-NEXT: v_readfirstlane_b32 s47, v20 +; VI-NEXT: v_mov_b32_e32 v20, s20 ; VI-NEXT: v_writelane_b32 v63, s70, 22 +; VI-NEXT: v_readfirstlane_b32 s44, v20 +; VI-NEXT: v_mov_b32_e32 v20, s21 ; VI-NEXT: v_writelane_b32 v63, s71, 23 +; VI-NEXT: v_readfirstlane_b32 s45, v20 +; VI-NEXT: v_mov_b32_e32 v20, s22 ; VI-NEXT: v_writelane_b32 v63, s80, 24 +; VI-NEXT: v_readfirstlane_b32 s42, v20 +; VI-NEXT: v_mov_b32_e32 v20, s23 ; VI-NEXT: v_writelane_b32 v63, s81, 25 +; VI-NEXT: v_readfirstlane_b32 s43, v20 +; VI-NEXT: v_mov_b32_e32 v20, s24 ; VI-NEXT: v_writelane_b32 v63, s82, 26 +; VI-NEXT: v_readfirstlane_b32 s40, v20 +; VI-NEXT: v_mov_b32_e32 v20, s25 ; VI-NEXT: v_writelane_b32 v63, s83, 27 +; VI-NEXT: v_readfirstlane_b32 s41, v20 +; VI-NEXT: v_mov_b32_e32 v20, s26 ; VI-NEXT: v_writelane_b32 v63, s84, 28 +; VI-NEXT: v_readfirstlane_b32 s24, v20 +; VI-NEXT: v_mov_b32_e32 v20, s27 ; VI-NEXT: v_writelane_b32 v63, s85, 29 +; VI-NEXT: v_readfirstlane_b32 s25, v20 +; VI-NEXT: v_mov_b32_e32 v20, s28 ; VI-NEXT: v_writelane_b32 v63, s86, 30 +; VI-NEXT: v_readfirstlane_b32 s20, v20 +; VI-NEXT: v_mov_b32_e32 v20, s29 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; VI-NEXT: v_writelane_b32 v63, s87, 31 -; VI-NEXT: v_readfirstlane_b32 s6, v1 -; VI-NEXT: v_readfirstlane_b32 s7, v2 -; VI-NEXT: v_readfirstlane_b32 s8, v3 -; VI-NEXT: v_readfirstlane_b32 s9, v4 -; VI-NEXT: v_readfirstlane_b32 s10, v5 -; VI-NEXT: v_readfirstlane_b32 s11, v6 -; VI-NEXT: v_readfirstlane_b32 s12, v7 -; VI-NEXT: v_readfirstlane_b32 s13, v8 -; VI-NEXT: v_readfirstlane_b32 s14, v9 -; VI-NEXT: v_readfirstlane_b32 s15, v10 -; VI-NEXT: v_readfirstlane_b32 s40, v11 -; VI-NEXT: v_readfirstlane_b32 s41, v12 -; VI-NEXT: v_readfirstlane_b32 s42, v13 -; VI-NEXT: v_readfirstlane_b32 s43, v14 -; VI-NEXT: v_readfirstlane_b32 s44, v15 -; VI-NEXT: v_readfirstlane_b32 s45, v16 -; VI-NEXT: v_readfirstlane_b32 s4, v17 -; VI-NEXT: s_and_b64 s[46:47], vcc, exec -; VI-NEXT: v_readfirstlane_b32 s5, v18 +; VI-NEXT: v_readfirstlane_b32 s21, v20 +; VI-NEXT: v_readfirstlane_b32 s22, v1 +; VI-NEXT: v_readfirstlane_b32 s23, v2 +; VI-NEXT: v_readfirstlane_b32 s18, v3 +; VI-NEXT: v_readfirstlane_b32 s19, v4 +; VI-NEXT: v_readfirstlane_b32 s16, v5 +; VI-NEXT: v_readfirstlane_b32 s17, v6 +; VI-NEXT: v_readfirstlane_b32 s14, v7 +; VI-NEXT: v_readfirstlane_b32 s15, v8 +; VI-NEXT: v_readfirstlane_b32 s12, v9 +; VI-NEXT: v_readfirstlane_b32 s13, v10 +; VI-NEXT: v_readfirstlane_b32 s10, v11 +; VI-NEXT: v_readfirstlane_b32 s11, v12 +; VI-NEXT: v_readfirstlane_b32 s8, v13 +; VI-NEXT: v_readfirstlane_b32 s9, v14 +; VI-NEXT: v_readfirstlane_b32 s4, v15 +; VI-NEXT: v_readfirstlane_b32 s5, v16 +; VI-NEXT: v_readfirstlane_b32 s6, v17 +; VI-NEXT: s_and_b64 s[26:27], vcc, exec +; VI-NEXT: v_readfirstlane_b32 s7, v18 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill @@ -118033,387 +116341,326 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; VI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; VI-NEXT: s_cbranch_scc0 .LBB73_3 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_lshr_b32 s46, s5, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 10 -; VI-NEXT: s_lshr_b32 s46, s5, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 11 -; VI-NEXT: s_lshr_b32 s46, s5, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 12 -; VI-NEXT: s_lshr_b32 s46, s4, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 8 -; VI-NEXT: s_lshr_b32 s46, s4, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 9 -; VI-NEXT: s_lshr_b32 s46, s45, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 13 -; VI-NEXT: s_lshr_b32 s46, s45, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 14 -; VI-NEXT: s_lshr_b32 s46, s45, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 15 -; VI-NEXT: s_lshr_b32 s46, s44, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 6 -; VI-NEXT: s_lshr_b32 s46, s44, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 7 -; VI-NEXT: s_lshr_b32 s46, s43, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 16 -; VI-NEXT: s_lshr_b32 s46, s43, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 17 -; VI-NEXT: s_lshr_b32 s46, s43, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 18 -; VI-NEXT: s_lshr_b32 s46, s42, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 4 -; VI-NEXT: s_lshr_b32 s46, s42, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 5 -; VI-NEXT: s_lshr_b32 s46, s41, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 19 -; VI-NEXT: s_lshr_b32 s46, s41, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 20 -; VI-NEXT: s_lshr_b32 s46, s41, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 21 -; VI-NEXT: s_lshr_b32 s46, s40, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 2 -; VI-NEXT: s_lshr_b32 s46, s40, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 3 -; VI-NEXT: s_lshr_b32 s46, s15, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 22 -; VI-NEXT: s_lshr_b32 s46, s15, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 23 -; VI-NEXT: s_lshr_b32 s46, s15, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 24 -; VI-NEXT: s_lshr_b32 s46, s14, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 0 -; VI-NEXT: s_lshr_b32 s46, s14, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 1 -; VI-NEXT: s_lshr_b32 s46, s13, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 25 -; VI-NEXT: s_lshr_b32 s46, s13, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 26 -; VI-NEXT: s_lshr_b32 s46, s13, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 27 -; VI-NEXT: s_lshr_b32 s46, s11, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 28 -; VI-NEXT: s_lshr_b32 s46, s11, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 29 -; VI-NEXT: s_lshr_b32 s46, s11, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 30 -; VI-NEXT: s_lshr_b32 s46, s9, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 31 -; VI-NEXT: s_lshr_b32 s46, s9, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 32 -; VI-NEXT: s_lshr_b32 s46, s9, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 33 -; VI-NEXT: s_lshr_b32 s46, s7, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 34 -; VI-NEXT: s_lshr_b32 s46, s7, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 35 -; VI-NEXT: s_lshr_b32 s46, s7, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 36 -; VI-NEXT: s_lshr_b32 s46, s29, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 37 -; VI-NEXT: s_lshr_b32 s46, s29, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 38 -; VI-NEXT: s_lshr_b32 s46, s29, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 39 -; VI-NEXT: s_lshr_b32 s46, s27, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 40 -; VI-NEXT: s_lshr_b32 s46, s27, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 41 -; VI-NEXT: s_lshr_b32 s46, s27, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 42 -; VI-NEXT: s_lshr_b32 s46, s25, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 43 -; VI-NEXT: s_lshr_b32 s46, s25, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 44 -; VI-NEXT: s_lshr_b32 s46, s25, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 45 -; VI-NEXT: s_lshr_b32 s46, s23, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 46 -; VI-NEXT: s_lshr_b32 s46, s23, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 47 -; VI-NEXT: s_lshr_b32 s46, s23, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 48 -; VI-NEXT: s_lshr_b32 s46, s21, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 49 -; VI-NEXT: s_lshr_b32 s46, s21, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 50 -; VI-NEXT: s_lshr_b32 s46, s21, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 51 -; VI-NEXT: s_lshr_b32 s46, s19, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 52 -; VI-NEXT: s_lshr_b32 s46, s19, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 53 -; VI-NEXT: s_lshr_b32 s46, s19, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 54 -; VI-NEXT: s_lshr_b32 s46, s17, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 55 -; VI-NEXT: s_lshr_b32 s46, s17, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 56 -; VI-NEXT: s_lshr_b32 s46, s17, 8 -; VI-NEXT: s_lshr_b32 s81, s12, 16 -; VI-NEXT: s_lshr_b32 s80, s12, 8 -; VI-NEXT: s_lshr_b32 s83, s10, 16 -; VI-NEXT: s_lshr_b32 s82, s10, 8 -; VI-NEXT: s_lshr_b32 s85, s8, 16 -; VI-NEXT: s_lshr_b32 s84, s8, 8 -; VI-NEXT: s_lshr_b32 s51, s6, 16 -; VI-NEXT: s_lshr_b32 s50, s6, 8 -; VI-NEXT: s_lshr_b32 s52, s28, 16 -; VI-NEXT: s_lshr_b32 s86, s28, 8 -; VI-NEXT: s_lshr_b32 s87, s26, 16 -; VI-NEXT: s_lshr_b32 s53, s26, 8 -; VI-NEXT: s_lshr_b32 s55, s24, 16 -; VI-NEXT: s_lshr_b32 s54, s24, 8 +; VI-NEXT: s_lshr_b32 s26, s7, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 13 +; VI-NEXT: s_lshr_b32 s26, s7, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 14 +; VI-NEXT: s_lshr_b32 s26, s7, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 15 +; VI-NEXT: s_lshr_b32 s26, s6, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 11 +; VI-NEXT: s_lshr_b32 s26, s6, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 12 +; VI-NEXT: s_lshr_b32 s26, s5, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 16 +; VI-NEXT: s_lshr_b32 s26, s5, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 17 +; VI-NEXT: s_lshr_b32 s26, s5, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 18 +; VI-NEXT: s_lshr_b32 s26, s4, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 9 +; VI-NEXT: s_lshr_b32 s26, s4, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 10 +; VI-NEXT: s_lshr_b32 s26, s9, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 19 +; VI-NEXT: s_lshr_b32 s26, s9, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 20 +; VI-NEXT: s_lshr_b32 s26, s9, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 21 +; VI-NEXT: s_lshr_b32 s26, s8, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 7 +; VI-NEXT: s_lshr_b32 s26, s8, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 8 +; VI-NEXT: s_lshr_b32 s26, s11, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 22 +; VI-NEXT: s_lshr_b32 s26, s11, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 23 +; VI-NEXT: s_lshr_b32 s26, s11, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 24 +; VI-NEXT: s_lshr_b32 s26, s10, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 5 +; VI-NEXT: s_lshr_b32 s26, s10, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 6 +; VI-NEXT: s_lshr_b32 s26, s13, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 25 +; VI-NEXT: s_lshr_b32 s26, s13, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 26 +; VI-NEXT: s_lshr_b32 s26, s13, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 27 +; VI-NEXT: s_lshr_b32 s26, s12, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 3 +; VI-NEXT: s_lshr_b32 s26, s12, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 4 +; VI-NEXT: s_lshr_b32 s26, s15, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 28 +; VI-NEXT: s_lshr_b32 s26, s15, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 29 +; VI-NEXT: s_lshr_b32 s26, s15, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 30 +; VI-NEXT: s_lshr_b32 s26, s14, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 1 +; VI-NEXT: s_lshr_b32 s26, s14, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 2 +; VI-NEXT: s_lshr_b32 s26, s17, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 31 +; VI-NEXT: s_lshr_b32 s26, s17, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 32 +; VI-NEXT: s_lshr_b32 s26, s17, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 33 +; VI-NEXT: s_lshr_b32 s26, s16, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 0 +; VI-NEXT: s_lshr_b32 s26, s19, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 34 +; VI-NEXT: s_lshr_b32 s26, s19, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 35 +; VI-NEXT: s_lshr_b32 s26, s19, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 36 +; VI-NEXT: s_lshr_b32 s26, s23, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 37 +; VI-NEXT: s_lshr_b32 s26, s23, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 38 +; VI-NEXT: s_lshr_b32 s26, s23, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 39 +; VI-NEXT: s_lshr_b32 s26, s21, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 40 +; VI-NEXT: s_lshr_b32 s26, s21, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 41 +; VI-NEXT: s_lshr_b32 s26, s21, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 42 +; VI-NEXT: s_lshr_b32 s26, s25, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 43 +; VI-NEXT: s_lshr_b32 s26, s25, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 44 +; VI-NEXT: s_lshr_b32 s26, s25, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 45 +; VI-NEXT: s_lshr_b32 s26, s41, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 46 +; VI-NEXT: s_lshr_b32 s26, s41, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 47 +; VI-NEXT: s_lshr_b32 s26, s41, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 48 +; VI-NEXT: s_lshr_b32 s26, s43, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 49 +; VI-NEXT: s_lshr_b32 s26, s43, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 50 +; VI-NEXT: s_lshr_b32 s26, s43, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 51 +; VI-NEXT: s_lshr_b32 s26, s45, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 52 +; VI-NEXT: s_lshr_b32 s26, s45, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 53 +; VI-NEXT: s_lshr_b32 s26, s45, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 54 +; VI-NEXT: s_lshr_b32 s26, s47, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 55 +; VI-NEXT: s_lshr_b32 s26, s47, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 56 +; VI-NEXT: s_lshr_b32 s26, s47, 8 +; VI-NEXT: s_lshr_b32 s82, s16, 8 +; VI-NEXT: s_lshr_b32 s83, s18, 16 +; VI-NEXT: s_lshr_b32 s55, s18, 8 ; VI-NEXT: s_lshr_b32 s65, s22, 16 ; VI-NEXT: s_lshr_b32 s64, s22, 8 -; VI-NEXT: s_lshr_b32 s67, s20, 16 -; VI-NEXT: s_lshr_b32 s66, s20, 8 -; VI-NEXT: s_lshr_b32 s69, s18, 16 -; VI-NEXT: s_lshr_b32 s68, s18, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 57 -; VI-NEXT: s_lshr_b32 s71, s16, 16 -; VI-NEXT: s_lshr_b32 s70, s16, 8 -; VI-NEXT: s_lshr_b64 s[46:47], s[4:5], 24 -; VI-NEXT: s_lshr_b64 s[56:57], s[44:45], 24 -; VI-NEXT: s_lshr_b64 s[58:59], s[42:43], 24 -; VI-NEXT: s_lshr_b64 s[60:61], s[40:41], 24 -; VI-NEXT: s_lshr_b64 s[62:63], s[14:15], 24 -; VI-NEXT: s_lshr_b64 s[72:73], s[12:13], 24 -; VI-NEXT: s_lshr_b64 s[74:75], s[10:11], 24 -; VI-NEXT: s_lshr_b64 s[76:77], s[8:9], 24 -; VI-NEXT: s_lshr_b64 s[78:79], s[6:7], 24 -; VI-NEXT: s_lshr_b64 s[88:89], s[28:29], 24 -; VI-NEXT: s_lshr_b64 s[90:91], s[26:27], 24 -; VI-NEXT: s_lshr_b64 s[30:31], s[24:25], 24 -; VI-NEXT: s_lshr_b64 s[34:35], s[22:23], 24 -; VI-NEXT: s_lshr_b64 s[36:37], s[20:21], 24 -; VI-NEXT: s_lshr_b64 s[38:39], s[18:19], 24 -; VI-NEXT: s_lshr_b64 s[48:49], s[16:17], 24 +; VI-NEXT: s_lshr_b32 s85, s20, 16 +; VI-NEXT: s_lshr_b32 s84, s20, 8 +; VI-NEXT: s_lshr_b32 s67, s24, 16 +; VI-NEXT: s_lshr_b32 s66, s24, 8 +; VI-NEXT: s_lshr_b32 s69, s40, 16 +; VI-NEXT: s_lshr_b32 s68, s40, 8 +; VI-NEXT: s_lshr_b32 s71, s42, 16 +; VI-NEXT: s_lshr_b32 s70, s42, 8 +; VI-NEXT: s_lshr_b32 s87, s44, 16 +; VI-NEXT: s_lshr_b32 s86, s44, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 57 +; VI-NEXT: s_lshr_b32 s81, s46, 16 +; VI-NEXT: s_lshr_b32 s80, s46, 8 +; VI-NEXT: s_lshr_b32 s51, s57, 24 +; VI-NEXT: s_lshr_b32 s52, s57, 16 +; VI-NEXT: s_lshr_b32 s53, s57, 8 +; VI-NEXT: s_lshr_b32 s54, s56, 16 +; VI-NEXT: s_lshr_b32 s50, s56, 8 +; VI-NEXT: s_lshr_b64 s[26:27], s[6:7], 24 +; VI-NEXT: s_lshr_b64 s[28:29], s[4:5], 24 +; VI-NEXT: s_lshr_b64 s[58:59], s[8:9], 24 +; VI-NEXT: s_lshr_b64 s[60:61], s[10:11], 24 +; VI-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 +; VI-NEXT: s_lshr_b64 s[72:73], s[14:15], 24 +; VI-NEXT: s_lshr_b64 s[74:75], s[16:17], 24 +; VI-NEXT: s_lshr_b64 s[76:77], s[18:19], 24 +; VI-NEXT: s_lshr_b64 s[78:79], s[22:23], 24 +; VI-NEXT: s_lshr_b64 s[88:89], s[20:21], 24 +; VI-NEXT: s_lshr_b64 s[90:91], s[24:25], 24 +; VI-NEXT: s_lshr_b64 s[30:31], s[40:41], 24 +; VI-NEXT: s_lshr_b64 s[34:35], s[42:43], 24 +; VI-NEXT: s_lshr_b64 s[36:37], s[44:45], 24 +; VI-NEXT: s_lshr_b64 s[38:39], s[46:47], 24 +; VI-NEXT: s_lshr_b64 s[48:49], s[56:57], 24 ; VI-NEXT: s_cbranch_execnz .LBB73_4 ; VI-NEXT: .LBB73_2: ; %cmp.true -; VI-NEXT: v_add_f64 v[11:12], s[4:5], 1.0 -; VI-NEXT: v_add_f64 v[1:2], s[44:45], 1.0 -; VI-NEXT: v_add_f64 v[3:4], s[42:43], 1.0 -; VI-NEXT: v_add_f64 v[5:6], s[40:41], 1.0 -; VI-NEXT: v_add_f64 v[7:8], s[14:15], 1.0 -; VI-NEXT: v_add_f64 v[9:10], s[12:13], 1.0 -; VI-NEXT: v_add_f64 v[13:14], s[10:11], 1.0 -; VI-NEXT: v_add_f64 v[15:16], s[8:9], 1.0 -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[11:12] -; VI-NEXT: v_add_f64 v[17:18], s[6:7], 1.0 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[1:2] -; VI-NEXT: v_add_f64 v[19:20], s[28:29], 1.0 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[3:4] -; VI-NEXT: v_add_f64 v[21:22], s[26:27], 1.0 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[5:6] -; VI-NEXT: v_add_f64 v[23:24], s[24:25], 1.0 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[7:8] -; VI-NEXT: v_add_f64 v[25:26], s[22:23], 1.0 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[9:10] -; VI-NEXT: v_add_f64 v[27:28], s[20:21], 1.0 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[13:14] -; VI-NEXT: v_add_f64 v[29:30], s[18:19], 1.0 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[15:16] -; VI-NEXT: v_add_f64 v[31:32], s[16:17], 1.0 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[17:18] -; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v12 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[19:20] -; VI-NEXT: v_lshrrev_b32_e32 v44, 24, v2 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[21:22] -; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v2 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[23:24] -; VI-NEXT: v_lshrrev_b32_e32 v45, 8, v2 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[25:26] -; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v1 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[27:28] -; VI-NEXT: v_lshrrev_b32_e32 v47, 24, v4 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[29:30] -; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v3 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[31:32] -; VI-NEXT: v_lshrrev_b32_e32 v46, 16, v5 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v4 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v4 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v3 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 24, v6 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v6 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v6 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 24, v8 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v8 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v8 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v7 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 24, v10 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v10 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v10 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v9 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v9 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 24, v14 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v14 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v14 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v13 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 24, v16 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v16 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v16 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v15 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v15 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 24, v18 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v18 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v18 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v17 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v17 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 24, v20 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v20 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v20 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; VI-NEXT: v_add_f64 v[1:2], s[6:7], 1.0 +; VI-NEXT: v_add_f64 v[3:4], s[4:5], 1.0 +; VI-NEXT: v_add_f64 v[23:24], s[18:19], 1.0 +; VI-NEXT: v_add_f64 v[25:26], s[20:21], 1.0 +; VI-NEXT: v_add_f64 v[5:6], s[8:9], 1.0 +; VI-NEXT: v_add_f64 v[27:28], s[24:25], 1.0 +; VI-NEXT: v_add_f64 v[31:32], s[40:41], 1.0 +; VI-NEXT: v_add_f64 v[33:34], s[42:43], 1.0 +; VI-NEXT: v_lshrrev_b64 v[9:10], 24, v[1:2] +; VI-NEXT: v_add_f64 v[19:20], s[22:23], 1.0 +; VI-NEXT: v_add_f64 v[7:8], s[10:11], 1.0 +; VI-NEXT: v_add_f64 v[37:38], s[44:45], 1.0 +; VI-NEXT: v_add_f64 v[17:18], s[16:17], 1.0 +; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; VI-NEXT: v_add_f64 v[52:53], s[56:57], 1.0 +; VI-NEXT: v_add_f64 v[50:51], s[46:47], 1.0 +; VI-NEXT: v_add_f64 v[13:14], s[14:15], 1.0 +; VI-NEXT: v_add_f64 v[11:12], s[12:13], 1.0 +; VI-NEXT: v_lshrrev_b64 v[9:10], 24, v[3:4] +; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b64 v[40:41], 24, v[23:24] +; VI-NEXT: v_lshrrev_b64 v[9:10], 24, v[5:6] +; VI-NEXT: v_lshrrev_b64 v[41:42], 24, v[25:26] +; VI-NEXT: v_lshrrev_b64 v[42:43], 24, v[27:28] +; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b64 v[43:44], 24, v[31:32] +; VI-NEXT: v_readfirstlane_b32 s11, v8 +; VI-NEXT: v_lshrrev_b64 v[29:30], 24, v[7:8] +; VI-NEXT: v_lshrrev_b64 v[8:9], 24, v[19:20] +; VI-NEXT: v_lshrrev_b64 v[44:45], 24, v[33:34] +; VI-NEXT: v_lshrrev_b64 v[54:55], 24, v[17:18] +; VI-NEXT: v_lshrrev_b64 v[45:46], 24, v[37:38] +; VI-NEXT: v_readfirstlane_b32 s57, v53 +; VI-NEXT: v_readfirstlane_b32 s47, v51 +; VI-NEXT: v_readfirstlane_b32 s45, v38 +; VI-NEXT: v_readfirstlane_b32 s43, v34 +; VI-NEXT: v_readfirstlane_b32 s41, v32 +; VI-NEXT: v_readfirstlane_b32 s25, v28 +; VI-NEXT: v_readfirstlane_b32 s21, v26 +; VI-NEXT: v_readfirstlane_b32 s23, v20 +; VI-NEXT: v_readfirstlane_b32 s19, v24 +; VI-NEXT: v_readfirstlane_b32 s17, v18 +; VI-NEXT: v_readfirstlane_b32 s15, v14 +; VI-NEXT: v_readfirstlane_b32 s13, v12 +; VI-NEXT: v_readfirstlane_b32 s9, v6 +; VI-NEXT: v_readfirstlane_b32 s5, v4 +; VI-NEXT: v_readfirstlane_b32 s7, v2 +; VI-NEXT: v_lshrrev_b64 v[35:36], 24, v[11:12] +; VI-NEXT: v_lshrrev_b64 v[48:49], 24, v[13:14] +; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b64 v[46:47], 24, v[50:51] +; VI-NEXT: v_lshrrev_b64 v[55:56], 24, v[52:53] +; VI-NEXT: s_lshr_b32 s10, s7, 24 +; VI-NEXT: s_lshr_b32 s12, s7, 16 +; VI-NEXT: s_lshr_b32 s14, s7, 8 +; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; VI-NEXT: v_lshrrev_b32_e32 v4, 8, v1 +; VI-NEXT: s_lshr_b32 s16, s5, 24 +; VI-NEXT: s_lshr_b32 s18, s5, 16 +; VI-NEXT: s_lshr_b32 s20, s5, 8 +; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v3 +; VI-NEXT: v_lshrrev_b32_e32 v8, 8, v3 +; VI-NEXT: s_lshr_b32 s22, s9, 24 +; VI-NEXT: s_lshr_b32 s24, s9, 16 +; VI-NEXT: s_lshr_b32 s26, s9, 8 +; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v5 +; VI-NEXT: v_lshrrev_b32_e32 v12, 8, v5 +; VI-NEXT: s_lshr_b32 s27, s11, 24 +; VI-NEXT: s_lshr_b32 s28, s11, 16 +; VI-NEXT: s_lshr_b32 s29, s11, 8 +; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v7 +; VI-NEXT: v_lshrrev_b32_e32 v16, 8, v7 +; VI-NEXT: s_lshr_b32 s40, s13, 24 +; VI-NEXT: s_lshr_b32 s42, s13, 16 +; VI-NEXT: s_lshr_b32 s44, s13, 8 +; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v11 +; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v11 +; VI-NEXT: s_lshr_b32 s46, s15, 24 +; VI-NEXT: s_lshr_b32 s56, s15, 16 +; VI-NEXT: s_lshr_b32 s58, s15, 8 +; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v13 +; VI-NEXT: v_lshrrev_b32_e32 v24, 8, v13 +; VI-NEXT: s_lshr_b32 s59, s17, 24 +; VI-NEXT: s_lshr_b32 s60, s17, 16 +; VI-NEXT: s_lshr_b32 s61, s17, 8 +; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v17 +; VI-NEXT: v_lshrrev_b32_e32 v28, 8, v17 +; VI-NEXT: s_lshr_b32 s62, s19, 24 +; VI-NEXT: s_lshr_b32 s63, s19, 16 +; VI-NEXT: s_lshr_b32 s72, s19, 8 +; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v23 +; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v23 +; VI-NEXT: s_lshr_b32 s73, s23, 24 +; VI-NEXT: s_lshr_b32 s74, s23, 16 +; VI-NEXT: s_lshr_b32 s75, s23, 8 ; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v19 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v19 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 24, v22 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v22 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v22 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v21 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v21 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v23 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v23 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v25 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v25 -; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v12 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v27 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v12 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v27 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v11 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v29 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v11 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v29 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v1 -; VI-NEXT: v_lshrrev_b32_e32 v52, 8, v5 -; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v7 -; VI-NEXT: v_lshrrev_b32_e32 v53, 24, v24 -; VI-NEXT: v_lshrrev_b32_e32 v56, 16, v24 -; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v24 -; VI-NEXT: v_lshrrev_b32_e32 v58, 24, v26 -; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v26 -; VI-NEXT: v_lshrrev_b32_e32 v54, 8, v26 -; VI-NEXT: v_lshrrev_b32_e32 v48, 24, v28 -; VI-NEXT: v_lshrrev_b32_e32 v59, 16, v28 -; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v28 -; VI-NEXT: v_lshrrev_b32_e32 v39, 24, v30 -; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v30 -; VI-NEXT: v_lshrrev_b32_e32 v61, 8, v30 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v36, 24, v32 -; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v32 -; VI-NEXT: v_lshrrev_b32_e32 v50, 8, v32 -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v31 -; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v31 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v36, 8, v19 +; VI-NEXT: s_lshr_b32 s76, s21, 24 +; VI-NEXT: s_lshr_b32 s77, s21, 16 +; VI-NEXT: s_lshr_b32 s78, s21, 8 +; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v25 +; VI-NEXT: v_lshrrev_b32_e32 v49, 8, v25 +; VI-NEXT: s_lshr_b32 s79, s25, 24 +; VI-NEXT: s_lshr_b32 s88, s25, 16 +; VI-NEXT: s_lshr_b32 s89, s25, 8 +; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v27 +; VI-NEXT: v_lshrrev_b32_e32 v53, 8, v27 +; VI-NEXT: s_lshr_b32 s90, s41, 24 +; VI-NEXT: s_lshr_b32 s91, s41, 16 +; VI-NEXT: s_lshr_b32 s30, s41, 8 +; VI-NEXT: v_lshrrev_b32_e32 v47, 16, v31 +; VI-NEXT: v_lshrrev_b32_e32 v56, 8, v31 +; VI-NEXT: s_lshr_b32 s31, s43, 24 +; VI-NEXT: s_lshr_b32 s34, s43, 16 +; VI-NEXT: s_lshr_b32 s35, s43, 8 +; VI-NEXT: v_lshrrev_b32_e32 v57, 16, v33 +; VI-NEXT: v_lshrrev_b32_e32 v58, 8, v33 +; VI-NEXT: s_lshr_b32 s36, s45, 24 +; VI-NEXT: s_lshr_b32 s37, s45, 16 +; VI-NEXT: s_lshr_b32 s38, s45, 8 +; VI-NEXT: v_lshrrev_b32_e32 v59, 16, v37 +; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v37 +; VI-NEXT: s_lshr_b32 s39, s47, 24 +; VI-NEXT: s_lshr_b32 s48, s47, 16 +; VI-NEXT: s_lshr_b32 s49, s47, 8 +; VI-NEXT: v_lshrrev_b32_e32 v61, 16, v50 +; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v50 +; VI-NEXT: s_lshr_b32 s51, s57, 24 +; VI-NEXT: s_lshr_b32 s52, s57, 16 +; VI-NEXT: s_lshr_b32 s53, s57, 8 +; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v52 +; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v52 ; VI-NEXT: s_branch .LBB73_5 ; VI-NEXT: .LBB73_3: -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr50 +; VI-NEXT: ; implicit-def: $sgpr54 +; VI-NEXT: ; implicit-def: $sgpr53 +; VI-NEXT: ; implicit-def: $sgpr52 +; VI-NEXT: ; implicit-def: $sgpr51 +; VI-NEXT: ; implicit-def: $sgpr80 +; VI-NEXT: ; implicit-def: $sgpr81 +; VI-NEXT: ; implicit-def: $sgpr86 +; VI-NEXT: ; implicit-def: $sgpr87 ; VI-NEXT: ; implicit-def: $sgpr70 ; VI-NEXT: ; implicit-def: $sgpr71 ; VI-NEXT: ; implicit-def: $sgpr68 ; VI-NEXT: ; implicit-def: $sgpr69 ; VI-NEXT: ; implicit-def: $sgpr66 ; VI-NEXT: ; implicit-def: $sgpr67 +; VI-NEXT: ; implicit-def: $sgpr84 +; VI-NEXT: ; implicit-def: $sgpr85 ; VI-NEXT: ; implicit-def: $sgpr64 ; VI-NEXT: ; implicit-def: $sgpr65 -; VI-NEXT: ; implicit-def: $sgpr54 ; VI-NEXT: ; implicit-def: $sgpr55 -; VI-NEXT: ; implicit-def: $sgpr53 -; VI-NEXT: ; implicit-def: $sgpr87 -; VI-NEXT: ; implicit-def: $sgpr86 -; VI-NEXT: ; implicit-def: $sgpr52 -; VI-NEXT: ; implicit-def: $sgpr50 -; VI-NEXT: ; implicit-def: $sgpr51 -; VI-NEXT: ; implicit-def: $sgpr84 -; VI-NEXT: ; implicit-def: $sgpr85 -; VI-NEXT: ; implicit-def: $sgpr82 ; VI-NEXT: ; implicit-def: $sgpr83 -; VI-NEXT: ; implicit-def: $sgpr80 -; VI-NEXT: ; implicit-def: $sgpr81 +; VI-NEXT: ; implicit-def: $sgpr82 ; VI-NEXT: ; implicit-def: $sgpr48 ; VI-NEXT: ; implicit-def: $sgpr38 ; VI-NEXT: ; implicit-def: $sgpr36 @@ -118428,404 +116675,400 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; VI-NEXT: ; implicit-def: $sgpr62 ; VI-NEXT: ; implicit-def: $sgpr60 ; VI-NEXT: ; implicit-def: $sgpr58 -; VI-NEXT: ; implicit-def: $sgpr56 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 +; VI-NEXT: ; implicit-def: $sgpr28 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 ; VI-NEXT: s_branch .LBB73_2 ; VI-NEXT: .LBB73_4: -; VI-NEXT: v_mov_b32_e32 v33, s71 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s69 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s68 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s67 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s66 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s65 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s64 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s55 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s54 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s87 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s53 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s52 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s86 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s51 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s50 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s85 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s84 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s83 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s82 -; VI-NEXT: v_mov_b32_e32 v11, s4 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s81 -; VI-NEXT: v_readlane_b32 s4, v62, 0 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s80 -; VI-NEXT: v_mov_b32_e32 v34, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 1 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 2 -; VI-NEXT: v_mov_b32_e32 v38, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 3 -; VI-NEXT: v_mov_b32_e32 v52, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 4 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 5 -; VI-NEXT: v_mov_b32_e32 v37, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 6 -; VI-NEXT: v_mov_b32_e32 v43, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 7 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 8 -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 9 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 10 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 11 -; VI-NEXT: v_mov_b32_e32 v41, s4 -; VI-NEXT: v_mov_b32_e32 v40, s48 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v40, s38 -; VI-NEXT: v_readlane_b32 s4, v62, 12 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 13 -; VI-NEXT: v_mov_b32_e32 v44, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 14 -; VI-NEXT: v_mov_b32_e32 v51, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 15 -; VI-NEXT: v_mov_b32_e32 v45, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 16 -; VI-NEXT: v_mov_b32_e32 v47, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 17 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 18 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 19 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 20 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 21 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 22 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 23 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 24 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 25 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v40, s36 -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 26 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 27 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 28 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 29 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 30 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 31 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 32 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 33 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 34 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 35 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 36 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 37 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v40, s34 -; VI-NEXT: v_readlane_b32 s4, v62, 38 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 39 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 40 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 41 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 42 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 43 -; VI-NEXT: v_mov_b32_e32 v53, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 44 -; VI-NEXT: v_mov_b32_e32 v56, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 45 -; VI-NEXT: v_mov_b32_e32 v57, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 46 -; VI-NEXT: v_mov_b32_e32 v58, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 47 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 48 -; VI-NEXT: v_mov_b32_e32 v54, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 49 -; VI-NEXT: v_mov_b32_e32 v48, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 50 -; VI-NEXT: v_mov_b32_e32 v59, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 51 -; VI-NEXT: v_mov_b32_e32 v60, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 52 -; VI-NEXT: v_mov_b32_e32 v39, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 53 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v40, s30 -; VI-NEXT: v_mov_b32_e32 v49, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 54 -; VI-NEXT: v_mov_b32_e32 v61, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 55 -; VI-NEXT: v_mov_b32_e32 v36, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 56 -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 57 -; VI-NEXT: v_mov_b32_e32 v12, s5 -; VI-NEXT: v_mov_b32_e32 v1, s44 -; VI-NEXT: v_mov_b32_e32 v2, s45 -; VI-NEXT: v_mov_b32_e32 v3, s42 -; VI-NEXT: v_mov_b32_e32 v4, s43 -; VI-NEXT: v_mov_b32_e32 v5, s40 -; VI-NEXT: v_mov_b32_e32 v6, s41 -; VI-NEXT: v_mov_b32_e32 v7, s14 -; VI-NEXT: v_mov_b32_e32 v8, s15 -; VI-NEXT: v_mov_b32_e32 v9, s12 -; VI-NEXT: v_mov_b32_e32 v10, s13 -; VI-NEXT: v_mov_b32_e32 v13, s10 -; VI-NEXT: v_mov_b32_e32 v14, s11 -; VI-NEXT: v_mov_b32_e32 v15, s8 -; VI-NEXT: v_mov_b32_e32 v16, s9 -; VI-NEXT: v_mov_b32_e32 v17, s6 -; VI-NEXT: v_mov_b32_e32 v18, s7 -; VI-NEXT: v_mov_b32_e32 v19, s28 -; VI-NEXT: v_mov_b32_e32 v20, s29 -; VI-NEXT: v_mov_b32_e32 v21, s26 -; VI-NEXT: v_mov_b32_e32 v22, s27 -; VI-NEXT: v_mov_b32_e32 v23, s24 -; VI-NEXT: v_mov_b32_e32 v24, s25 -; VI-NEXT: v_mov_b32_e32 v25, s22 -; VI-NEXT: v_mov_b32_e32 v26, s23 -; VI-NEXT: v_mov_b32_e32 v27, s20 -; VI-NEXT: v_mov_b32_e32 v28, s21 -; VI-NEXT: v_mov_b32_e32 v29, s18 -; VI-NEXT: v_mov_b32_e32 v30, s19 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v40, s90 -; VI-NEXT: v_mov_b32_e32 v31, s16 -; VI-NEXT: v_mov_b32_e32 v32, s17 -; VI-NEXT: v_mov_b32_e32 v42, s70 -; VI-NEXT: v_mov_b32_e32 v50, s4 -; VI-NEXT: v_mov_b32_e32 v46, v38 -; VI-NEXT: v_mov_b32_e32 v38, v34 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v40, s88 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v40, s78 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v40, s76 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v40, s74 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v40, s72 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v40, s62 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v40, s60 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v40, s58 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v40, s56 +; VI-NEXT: v_mov_b32_e32 v39, s58 +; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v40, s46 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v40, v43 +; VI-NEXT: v_mov_b32_e32 v39, s28 +; VI-NEXT: v_readlane_b32 s27, v62, 0 +; VI-NEXT: v_mov_b32_e32 v26, s27 +; VI-NEXT: v_readlane_b32 s27, v62, 1 +; VI-NEXT: v_mov_b32_e32 v22, s27 +; VI-NEXT: v_readlane_b32 s27, v62, 2 +; VI-NEXT: v_mov_b32_e32 v24, s27 +; VI-NEXT: v_readlane_b32 s27, v62, 3 +; VI-NEXT: v_mov_b32_e32 v18, s27 +; VI-NEXT: v_readlane_b32 s27, v62, 4 +; VI-NEXT: v_mov_b32_e32 v20, s27 +; VI-NEXT: v_readlane_b32 s27, v62, 5 +; VI-NEXT: v_mov_b32_e32 v14, s27 +; VI-NEXT: v_readlane_b32 s27, v62, 6 +; VI-NEXT: v_mov_b32_e32 v16, s27 +; VI-NEXT: v_readlane_b32 s27, v62, 7 +; VI-NEXT: v_mov_b32_e32 v10, s27 +; VI-NEXT: v_readlane_b32 s27, v62, 8 +; VI-NEXT: v_mov_b32_e32 v12, s27 +; VI-NEXT: v_readlane_b32 s27, v62, 9 +; VI-NEXT: v_mov_b32_e32 v6, s27 +; VI-NEXT: v_readlane_b32 s27, v62, 10 +; VI-NEXT: v_mov_b32_e32 v30, s83 +; VI-NEXT: v_mov_b32_e32 v8, s27 +; VI-NEXT: v_readlane_b32 s27, v62, 11 +; VI-NEXT: v_mov_b32_e32 v29, s78 +; VI-NEXT: v_mov_b32_e32 v2, s27 +; VI-NEXT: v_readlane_b32 s27, v62, 12 +; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v15, s54 +; VI-NEXT: v_mov_b32_e32 v21, s50 +; VI-NEXT: v_mov_b32_e32 v61, s81 +; VI-NEXT: v_mov_b32_e32 v9, s80 +; VI-NEXT: v_mov_b32_e32 v59, s87 +; VI-NEXT: v_mov_b32_e32 v60, s86 +; VI-NEXT: v_mov_b32_e32 v57, s71 +; VI-NEXT: v_mov_b32_e32 v58, s70 +; VI-NEXT: v_mov_b32_e32 v47, s69 +; VI-NEXT: v_mov_b32_e32 v56, s68 +; VI-NEXT: v_mov_b32_e32 v51, s67 +; VI-NEXT: v_mov_b32_e32 v53, s66 +; VI-NEXT: v_mov_b32_e32 v38, s85 +; VI-NEXT: v_mov_b32_e32 v49, s84 +; VI-NEXT: v_mov_b32_e32 v34, s65 +; VI-NEXT: v_mov_b32_e32 v36, s64 +; VI-NEXT: v_mov_b32_e32 v32, s55 +; VI-NEXT: v_mov_b32_e32 v28, s82 +; VI-NEXT: v_mov_b32_e32 v4, s27 +; VI-NEXT: v_mov_b32_e32 v52, s56 +; VI-NEXT: v_mov_b32_e32 v50, s46 +; VI-NEXT: v_mov_b32_e32 v37, s44 +; VI-NEXT: v_mov_b32_e32 v33, s42 +; VI-NEXT: v_mov_b32_e32 v31, s40 +; VI-NEXT: v_mov_b32_e32 v27, s24 +; VI-NEXT: v_mov_b32_e32 v25, s20 +; VI-NEXT: v_mov_b32_e32 v19, s22 +; VI-NEXT: v_mov_b32_e32 v23, s18 +; VI-NEXT: v_mov_b32_e32 v17, s16 +; VI-NEXT: v_mov_b32_e32 v13, s14 +; VI-NEXT: v_mov_b32_e32 v11, s12 +; VI-NEXT: v_mov_b32_e32 v7, s10 +; VI-NEXT: v_mov_b32_e32 v5, s8 +; VI-NEXT: v_mov_b32_e32 v3, s4 +; VI-NEXT: v_mov_b32_e32 v1, s6 +; VI-NEXT: v_mov_b32_e32 v55, s48 +; VI-NEXT: v_mov_b32_e32 v46, s38 +; VI-NEXT: v_mov_b32_e32 v45, s36 +; VI-NEXT: v_mov_b32_e32 v44, s34 +; VI-NEXT: v_mov_b32_e32 v43, s30 +; VI-NEXT: v_mov_b32_e32 v42, s90 +; VI-NEXT: v_mov_b32_e32 v41, s88 +; VI-NEXT: v_mov_b32_e32 v54, s74 +; VI-NEXT: v_mov_b32_e32 v48, s72 +; VI-NEXT: v_mov_b32_e32 v35, s62 +; VI-NEXT: v_mov_b32_e32 v29, s60 +; VI-NEXT: v_readlane_b32 s10, v62, 13 +; VI-NEXT: v_readlane_b32 s12, v62, 14 +; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v39, s26 +; VI-NEXT: v_readlane_b32 s14, v62, 15 +; VI-NEXT: v_readlane_b32 s16, v62, 16 +; VI-NEXT: v_readlane_b32 s18, v62, 17 +; VI-NEXT: v_readlane_b32 s20, v62, 18 +; VI-NEXT: v_readlane_b32 s22, v62, 19 +; VI-NEXT: v_readlane_b32 s24, v62, 20 +; VI-NEXT: v_readlane_b32 s26, v62, 21 +; VI-NEXT: v_readlane_b32 s27, v62, 22 +; VI-NEXT: v_readlane_b32 s28, v62, 23 +; VI-NEXT: v_readlane_b32 s29, v62, 24 +; VI-NEXT: v_readlane_b32 s40, v62, 25 +; VI-NEXT: v_readlane_b32 s42, v62, 26 +; VI-NEXT: v_readlane_b32 s44, v62, 27 +; VI-NEXT: v_readlane_b32 s46, v62, 28 +; VI-NEXT: v_readlane_b32 s56, v62, 29 +; VI-NEXT: v_readlane_b32 s58, v62, 30 +; VI-NEXT: v_readlane_b32 s59, v62, 31 +; VI-NEXT: v_readlane_b32 s60, v62, 32 +; VI-NEXT: v_readlane_b32 s61, v62, 33 +; VI-NEXT: v_readlane_b32 s62, v62, 34 +; VI-NEXT: v_readlane_b32 s63, v62, 35 +; VI-NEXT: v_readlane_b32 s72, v62, 36 +; VI-NEXT: v_readlane_b32 s73, v62, 37 +; VI-NEXT: v_readlane_b32 s74, v62, 38 +; VI-NEXT: v_readlane_b32 s75, v62, 39 +; VI-NEXT: v_readlane_b32 s76, v62, 40 +; VI-NEXT: v_readlane_b32 s77, v62, 41 +; VI-NEXT: v_readlane_b32 s78, v62, 42 +; VI-NEXT: v_readlane_b32 s79, v62, 43 +; VI-NEXT: v_readlane_b32 s88, v62, 44 +; VI-NEXT: v_readlane_b32 s89, v62, 45 +; VI-NEXT: v_readlane_b32 s90, v62, 46 +; VI-NEXT: v_readlane_b32 s91, v62, 47 +; VI-NEXT: v_readlane_b32 s30, v62, 48 +; VI-NEXT: v_readlane_b32 s31, v62, 49 +; VI-NEXT: v_readlane_b32 s34, v62, 50 +; VI-NEXT: v_readlane_b32 s35, v62, 51 +; VI-NEXT: v_readlane_b32 s36, v62, 52 +; VI-NEXT: v_readlane_b32 s37, v62, 53 +; VI-NEXT: v_readlane_b32 s38, v62, 54 +; VI-NEXT: v_readlane_b32 s39, v62, 55 +; VI-NEXT: v_readlane_b32 s48, v62, 56 +; VI-NEXT: v_readlane_b32 s49, v62, 57 +; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; VI-NEXT: .LBB73_5: ; %end -; VI-NEXT: v_lshlrev_b32_e32 v34, 8, v42 -; VI-NEXT: v_or_b32_sdwa v31, v31, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v34, 8, v50 -; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload -; VI-NEXT: v_or_b32_sdwa v32, v32, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: s_and_b32 s4, s57, 0xff +; VI-NEXT: s_lshl_b32 s6, s53, 8 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: s_and_b32 s6, s52, 0xff +; VI-NEXT: s_lshl_b32 s8, s51, 8 +; VI-NEXT: v_lshlrev_b32_e32 v21, 8, v21 +; VI-NEXT: s_or_b32 s6, s6, s8 +; VI-NEXT: v_or_b32_sdwa v21, v52, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v52, 8, v55 +; VI-NEXT: s_and_b32 s4, s4, 0xffff +; VI-NEXT: s_lshl_b32 s6, s6, 16 +; VI-NEXT: v_or_b32_sdwa v15, v15, v52 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: v_or_b32_sdwa v15, v21, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_mov_b32_e32 v21, s4 +; VI-NEXT: s_and_b32 s4, s47, 0xff +; VI-NEXT: s_lshl_b32 s6, s49, 8 +; VI-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v15, vcc, 4, v0 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: s_and_b32 s6, s48, 0xff +; VI-NEXT: s_lshl_b32 s8, s39, 8 +; VI-NEXT: buffer_store_dword v21, v15, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v9, 8, v9 +; VI-NEXT: v_lshlrev_b32_e32 v15, 8, v46 +; VI-NEXT: s_or_b32 s6, s6, s8 +; VI-NEXT: v_or_b32_sdwa v9, v50, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v15, v61, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: s_and_b32 s4, s4, 0xffff +; VI-NEXT: s_lshl_b32 s6, s6, 16 +; VI-NEXT: v_or_b32_sdwa v9, v9, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v15, vcc, 8, v0 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: buffer_store_dword v9, v15, s[0:3], 0 offen +; VI-NEXT: v_mov_b32_e32 v15, s4 +; VI-NEXT: s_and_b32 s4, s45, 0xff +; VI-NEXT: s_lshl_b32 s6, s38, 8 +; VI-NEXT: v_add_u32_e32 v9, vcc, 12, v0 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: s_and_b32 s6, s37, 0xff +; VI-NEXT: s_lshl_b32 s8, s36, 8 +; VI-NEXT: buffer_store_dword v15, v9, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v9, 8, v60 +; VI-NEXT: v_lshlrev_b32_e32 v15, 8, v45 +; VI-NEXT: s_or_b32 s6, s6, s8 +; VI-NEXT: v_or_b32_sdwa v9, v37, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v15, v59, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: s_and_b32 s4, s4, 0xffff +; VI-NEXT: s_lshl_b32 s6, s6, 16 +; VI-NEXT: v_or_b32_sdwa v9, v9, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v15, vcc, 16, v0 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: buffer_store_dword v9, v15, s[0:3], 0 offen +; VI-NEXT: v_mov_b32_e32 v15, s4 +; VI-NEXT: s_and_b32 s4, s43, 0xff +; VI-NEXT: s_lshl_b32 s6, s35, 8 +; VI-NEXT: v_add_u32_e32 v9, vcc, 20, v0 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: s_and_b32 s6, s34, 0xff +; VI-NEXT: s_lshl_b32 s8, s31, 8 +; VI-NEXT: buffer_store_dword v15, v9, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v9, 8, v58 +; VI-NEXT: v_lshlrev_b32_e32 v15, 8, v44 +; VI-NEXT: s_or_b32 s6, s6, s8 +; VI-NEXT: v_or_b32_sdwa v9, v33, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v15, v57, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: s_and_b32 s4, s4, 0xffff +; VI-NEXT: s_lshl_b32 s6, s6, 16 +; VI-NEXT: v_or_b32_sdwa v9, v9, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v15, vcc, 24, v0 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: buffer_store_dword v9, v15, s[0:3], 0 offen +; VI-NEXT: v_mov_b32_e32 v15, s4 +; VI-NEXT: s_and_b32 s4, s41, 0xff +; VI-NEXT: s_lshl_b32 s6, s30, 8 +; VI-NEXT: v_add_u32_e32 v9, vcc, 28, v0 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: s_and_b32 s6, s91, 0xff +; VI-NEXT: s_lshl_b32 s8, s90, 8 +; VI-NEXT: buffer_store_dword v15, v9, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v9, 8, v56 +; VI-NEXT: v_lshlrev_b32_e32 v15, 8, v43 +; VI-NEXT: s_or_b32 s6, s6, s8 +; VI-NEXT: v_or_b32_sdwa v9, v31, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v15, v47, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: s_and_b32 s4, s4, 0xffff +; VI-NEXT: s_lshl_b32 s6, s6, 16 +; VI-NEXT: v_or_b32_sdwa v9, v9, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v15, vcc, 32, v0 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: buffer_store_dword v9, v15, s[0:3], 0 offen +; VI-NEXT: v_mov_b32_e32 v15, s4 +; VI-NEXT: s_and_b32 s4, s25, 0xff +; VI-NEXT: s_lshl_b32 s6, s89, 8 +; VI-NEXT: v_add_u32_e32 v9, vcc, 36, v0 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: s_and_b32 s6, s88, 0xff +; VI-NEXT: s_lshl_b32 s8, s79, 8 +; VI-NEXT: buffer_store_dword v15, v9, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v9, 8, v53 +; VI-NEXT: v_lshlrev_b32_e32 v15, 8, v42 +; VI-NEXT: s_or_b32 s6, s6, s8 +; VI-NEXT: v_or_b32_sdwa v9, v27, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v15, v51, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: s_and_b32 s4, s4, 0xffff +; VI-NEXT: s_lshl_b32 s6, s6, 16 +; VI-NEXT: v_or_b32_sdwa v9, v9, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v15, vcc, 40, v0 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: buffer_store_dword v9, v15, s[0:3], 0 offen +; VI-NEXT: v_mov_b32_e32 v15, s4 +; VI-NEXT: s_and_b32 s4, s21, 0xff +; VI-NEXT: s_lshl_b32 s6, s78, 8 +; VI-NEXT: v_add_u32_e32 v9, vcc, 44, v0 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: s_and_b32 s6, s77, 0xff +; VI-NEXT: s_lshl_b32 s8, s76, 8 +; VI-NEXT: buffer_store_dword v15, v9, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v9, 8, v49 +; VI-NEXT: v_lshlrev_b32_e32 v15, 8, v41 +; VI-NEXT: s_or_b32 s6, s6, s8 +; VI-NEXT: v_or_b32_sdwa v9, v25, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v15, v38, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: s_and_b32 s4, s4, 0xffff +; VI-NEXT: s_lshl_b32 s6, s6, 16 +; VI-NEXT: v_or_b32_sdwa v9, v9, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v15, vcc, 48, v0 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: buffer_store_dword v9, v15, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v9, vcc, 52, v0 +; VI-NEXT: v_mov_b32_e32 v15, s4 +; VI-NEXT: buffer_store_dword v15, v9, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v9, 8, v36 +; VI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; VI-NEXT: s_and_b32 s4, s23, 0xff +; VI-NEXT: s_lshl_b32 s6, s75, 8 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: s_and_b32 s6, s74, 0xff +; VI-NEXT: s_lshl_b32 s8, s73, 8 +; VI-NEXT: s_or_b32 s6, s6, s8 +; VI-NEXT: v_or_b32_sdwa v9, v19, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: s_and_b32 s4, s4, 0xffff +; VI-NEXT: s_lshl_b32 s6, s6, 16 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: s_lshl_b32 s6, s72, 8 +; VI-NEXT: s_lshl_b32 s8, s62, 8 ; VI-NEXT: v_readlane_b32 s87, v63, 31 ; VI-NEXT: v_readlane_b32 s86, v63, 30 ; VI-NEXT: v_readlane_b32 s85, v63, 29 @@ -118858,367 +117101,173 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; VI-NEXT: v_readlane_b32 s34, v63, 2 ; VI-NEXT: v_readlane_b32 s31, v63, 1 ; VI-NEXT: v_readlane_b32 s30, v63, 0 -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v34, 8, v42 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v34, v50, v34 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v31, v31, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: buffer_store_dword v31, v0, s[0:3], 0 offen -; VI-NEXT: v_lshlrev_b32_e32 v31, 8, v36 -; VI-NEXT: v_or_b32_sdwa v31, v55, v31 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v31, v32, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v32, vcc, 4, v0 -; VI-NEXT: buffer_store_dword v31, v32, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v31, 8, v31 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v31, v32, v31 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v32, 8, v32 -; VI-NEXT: v_or_b32_sdwa v29, v29, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v29, v29, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v31, vcc, 8, v0 -; VI-NEXT: buffer_store_dword v29, v31, s[0:3], 0 offen -; VI-NEXT: v_lshlrev_b32_e32 v29, 8, v61 -; VI-NEXT: v_or_b32_sdwa v29, v30, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v30, 8, v39 -; VI-NEXT: v_or_b32_sdwa v30, v49, v30 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v29, v29, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v30, vcc, 12, v0 -; VI-NEXT: buffer_store_dword v29, v30, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v29, 8, v29 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v29, v30, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v30, 8, v30 -; VI-NEXT: v_or_b32_sdwa v27, v27, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v27, v27, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v29, vcc, 16, v0 -; VI-NEXT: buffer_store_dword v27, v29, s[0:3], 0 offen -; VI-NEXT: v_lshlrev_b32_e32 v27, 8, v60 -; VI-NEXT: v_or_b32_sdwa v27, v28, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v28, 8, v48 -; VI-NEXT: v_or_b32_sdwa v28, v59, v28 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v27, v27, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v28, vcc, 20, v0 -; VI-NEXT: buffer_store_dword v27, v28, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v27, 8, v27 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v27, v28, v27 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v28, 8, v28 -; VI-NEXT: v_or_b32_sdwa v25, v25, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v25, v25, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v27, vcc, 24, v0 -; VI-NEXT: buffer_store_dword v25, v27, s[0:3], 0 offen -; VI-NEXT: v_lshlrev_b32_e32 v25, 8, v54 -; VI-NEXT: v_or_b32_sdwa v25, v26, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v26, 8, v58 -; VI-NEXT: v_or_b32_sdwa v26, v35, v26 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v25, v25, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v26, vcc, 28, v0 -; VI-NEXT: buffer_store_dword v25, v26, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v25, 8, v25 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v25, v26, v25 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v26, 8, v26 -; VI-NEXT: v_or_b32_sdwa v23, v23, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v23, v23, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v25, vcc, 32, v0 -; VI-NEXT: buffer_store_dword v23, v25, s[0:3], 0 offen -; VI-NEXT: v_lshlrev_b32_e32 v23, 8, v57 -; VI-NEXT: v_or_b32_sdwa v23, v24, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v24, 8, v53 -; VI-NEXT: v_or_b32_sdwa v24, v56, v24 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v24, vcc, 36, v0 -; VI-NEXT: buffer_store_dword v23, v24, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v23, 8, v23 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v23, v24, v23 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v24, 8, v24 -; VI-NEXT: v_or_b32_sdwa v21, v21, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v21, v21, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v23, vcc, 40, v0 -; VI-NEXT: buffer_store_dword v21, v23, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload ; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v21, 8, v21 -; VI-NEXT: v_or_b32_sdwa v21, v22, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v22, 8, v22 -; VI-NEXT: v_or_b32_sdwa v22, v23, v22 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v21, v21, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v22, vcc, 44, v0 -; VI-NEXT: buffer_store_dword v21, v22, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v21, 8, v21 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v21, v22, v21 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v22, 8, v22 -; VI-NEXT: v_or_b32_sdwa v19, v19, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v19, v19, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v21, vcc, 48, v0 -; VI-NEXT: buffer_store_dword v19, v21, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v19, 8, v19 -; VI-NEXT: v_or_b32_sdwa v19, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v20, 8, v20 -; VI-NEXT: v_or_b32_sdwa v20, v21, v20 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v19, v19, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v20, vcc, 52, v0 -; VI-NEXT: buffer_store_dword v19, v20, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v19, 8, v19 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v19, v20, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v20, 8, v20 -; VI-NEXT: v_or_b32_sdwa v17, v17, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v17, v17, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v19, vcc, 56, v0 -; VI-NEXT: buffer_store_dword v17, v19, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18 -; VI-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v17, v17, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v18, vcc, 60, v0 -; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18 -; VI-NEXT: v_or_b32_sdwa v15, v15, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v15, v15, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v17, vcc, 64, v0 -; VI-NEXT: buffer_store_dword v15, v17, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v15, 8, v15 -; VI-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v16, 8, v16 -; VI-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v15, v15, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v16, vcc, 0x44, v0 -; VI-NEXT: buffer_store_dword v15, v16, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v15, 8, v15 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v16, 8, v16 -; VI-NEXT: v_or_b32_sdwa v13, v13, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v13, v13, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v15, 8, v36 +; VI-NEXT: v_or_b32_sdwa v15, v34, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v9, v9, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v15, vcc, 56, v0 +; VI-NEXT: buffer_store_dword v9, v15, s[0:3], 0 offen +; VI-NEXT: v_mov_b32_e32 v15, s4 +; VI-NEXT: s_and_b32 s4, s19, 0xff +; VI-NEXT: v_add_u32_e32 v9, vcc, 60, v0 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: s_and_b32 s6, s63, 0xff +; VI-NEXT: buffer_store_dword v15, v9, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v9, 8, v32 +; VI-NEXT: v_lshlrev_b32_e32 v15, 8, v40 +; VI-NEXT: s_or_b32 s6, s6, s8 +; VI-NEXT: v_or_b32_sdwa v9, v23, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v15, v30, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: s_and_b32 s4, s4, 0xffff +; VI-NEXT: s_lshl_b32 s6, s6, 16 +; VI-NEXT: v_or_b32_sdwa v9, v9, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v15, vcc, 64, v0 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: buffer_store_dword v9, v15, s[0:3], 0 offen +; VI-NEXT: v_mov_b32_e32 v15, s4 +; VI-NEXT: s_and_b32 s4, s17, 0xff +; VI-NEXT: s_lshl_b32 s6, s61, 8 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x44, v0 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: s_and_b32 s6, s60, 0xff +; VI-NEXT: s_lshl_b32 s8, s59, 8 +; VI-NEXT: buffer_store_dword v15, v9, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v9, 8, v28 +; VI-NEXT: v_lshlrev_b32_e32 v15, 8, v54 +; VI-NEXT: s_or_b32 s6, s6, s8 +; VI-NEXT: v_or_b32_sdwa v9, v17, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v15, v26, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: s_and_b32 s4, s4, 0xffff +; VI-NEXT: s_lshl_b32 s6, s6, 16 +; VI-NEXT: v_or_b32_sdwa v9, v9, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_add_u32_e32 v15, vcc, 0x48, v0 -; VI-NEXT: buffer_store_dword v13, v15, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v13, 8, v13 -; VI-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v14, 8, v14 -; VI-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v13, v13, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v14, vcc, 0x4c, v0 -; VI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v13, 8, v13 -; VI-NEXT: v_or_b32_sdwa v9, v9, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v13, 8, v13 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: buffer_store_dword v9, v15, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x4c, v0 +; VI-NEXT: v_mov_b32_e32 v15, s4 +; VI-NEXT: s_and_b32 s4, s15, 0xff +; VI-NEXT: s_lshl_b32 s6, s58, 8 +; VI-NEXT: buffer_store_dword v15, v9, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v9, 8, v24 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: s_and_b32 s6, s56, 0xff +; VI-NEXT: s_lshl_b32 s8, s46, 8 +; VI-NEXT: v_or_b32_sdwa v9, v13, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v13, 8, v48 +; VI-NEXT: s_or_b32 s6, s6, s8 +; VI-NEXT: v_or_b32_sdwa v13, v22, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: s_and_b32 s4, s4, 0xffff +; VI-NEXT: s_lshl_b32 s6, s6, 16 ; VI-NEXT: v_or_b32_sdwa v9, v9, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_add_u32_e32 v13, vcc, 0x50, v0 +; VI-NEXT: s_or_b32 s4, s4, s6 ; VI-NEXT: buffer_store_dword v9, v13, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v9, 8, v9 -; VI-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v10, 8, v10 -; VI-NEXT: v_or_b32_sdwa v10, v13, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v10, vcc, 0x54, v0 -; VI-NEXT: buffer_store_dword v9, v10, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v9, 8, v9 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x54, v0 +; VI-NEXT: v_mov_b32_e32 v13, s4 +; VI-NEXT: s_and_b32 s4, s13, 0xff +; VI-NEXT: s_lshl_b32 s6, s44, 8 +; VI-NEXT: buffer_store_dword v13, v9, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v9, 8, v20 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: s_and_b32 s6, s42, 0xff +; VI-NEXT: s_lshl_b32 s8, s40, 8 +; VI-NEXT: v_or_b32_sdwa v9, v11, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v11, 8, v35 +; VI-NEXT: s_or_b32 s6, s6, s8 +; VI-NEXT: v_or_b32_sdwa v11, v18, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: s_and_b32 s4, s4, 0xffff +; VI-NEXT: s_lshl_b32 s6, s6, 16 +; VI-NEXT: v_or_b32_sdwa v9, v9, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x58, v0 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: buffer_store_dword v9, v11, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x5c, v0 +; VI-NEXT: v_mov_b32_e32 v11, s4 +; VI-NEXT: s_and_b32 s4, s11, 0xff +; VI-NEXT: s_lshl_b32 s6, s29, 8 +; VI-NEXT: buffer_store_dword v11, v9, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v9, 8, v16 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: s_and_b32 s6, s28, 0xff +; VI-NEXT: s_lshl_b32 s8, s27, 8 ; VI-NEXT: v_or_b32_sdwa v7, v7, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v9, 8, v9 -; VI-NEXT: v_or_b32_sdwa v9, v38, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v9, 8, v29 +; VI-NEXT: s_or_b32 s6, s6, s8 +; VI-NEXT: v_or_b32_sdwa v9, v14, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: s_and_b32 s4, s4, 0xffff +; VI-NEXT: s_lshl_b32 s6, s6, 16 ; VI-NEXT: v_or_b32_sdwa v7, v7, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v9, vcc, 0x58, v0 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x60, v0 +; VI-NEXT: s_or_b32 s4, s4, s6 ; VI-NEXT: buffer_store_dword v7, v9, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v7, 8, v7 -; VI-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v8, 8, v8 -; VI-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v8, vcc, 0x5c, v0 -; VI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen -; VI-NEXT: v_lshlrev_b32_e32 v7, 8, v52 +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x64, v0 +; VI-NEXT: v_mov_b32_e32 v9, s4 +; VI-NEXT: buffer_store_dword v9, v7, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v7, 8, v12 +; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; VI-NEXT: s_and_b32 s4, s9, 0xff +; VI-NEXT: s_lshl_b32 s6, s26, 8 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: s_and_b32 s6, s24, 0xff +; VI-NEXT: s_lshl_b32 s8, s22, 8 ; VI-NEXT: v_or_b32_sdwa v5, v5, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; VI-NEXT: s_or_b32 s6, s6, s8 +; VI-NEXT: s_and_b32 s4, s4, 0xffff +; VI-NEXT: s_lshl_b32 s6, s6, 16 +; VI-NEXT: s_or_b32 s4, s4, s6 +; VI-NEXT: s_lshl_b32 s6, s16, 8 ; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v7, 8, v7 -; VI-NEXT: v_or_b32_sdwa v7, v46, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v7, 8, v11 +; VI-NEXT: v_or_b32_sdwa v7, v10, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v5, v5, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v7, vcc, 0x60, v0 +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x68, v0 ; VI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v5 -; VI-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v6, 8, v6 -; VI-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v6, vcc, 0x64, v0 -; VI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen -; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v37 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x6c, v0 +; VI-NEXT: v_mov_b32_e32 v7, s4 +; VI-NEXT: buffer_store_dword v7, v5, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v8 +; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; VI-NEXT: s_and_b32 s4, s5, 0xff +; VI-NEXT: s_lshl_b32 s5, s20, 8 +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_and_b32 s5, s18, 0xff ; VI-NEXT: v_or_b32_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v5 -; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_or_b32 s5, s5, s6 +; VI-NEXT: s_and_b32 s4, s4, 0xffff +; VI-NEXT: s_lshl_b32 s5, s5, 16 +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_lshl_b32 s5, s14, 8 +; VI-NEXT: s_lshl_b32 s6, s10, 8 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v7 ; VI-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v5, vcc, 0x68, v0 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x70, v0 ; VI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v3 -; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v4, 8, v47 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v4, vcc, 0x6c, v0 -; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen -; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v33 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x74, v0 +; VI-NEXT: v_mov_b32_e32 v5, s4 +; VI-NEXT: buffer_store_dword v5, v3, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v4 ; VI-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; VI-NEXT: s_and_b32 s4, s7, 0xff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_and_b32 s5, s12, 0xff +; VI-NEXT: s_or_b32 s5, s5, s6 +; VI-NEXT: s_and_b32 s4, s4, 0xffff +; VI-NEXT: s_lshl_b32 s5, s5, 16 +; VI-NEXT: s_or_b32 s4, s4, s5 ; VI-NEXT: s_waitcnt vmcnt(1) ; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v3 -; VI-NEXT: v_or_b32_sdwa v3, v40, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v3, vcc, 0x70, v0 -; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v45 -; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v44 -; VI-NEXT: v_or_b32_sdwa v2, v51, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(3) -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; VI-NEXT: v_or_b32_sdwa v1, v11, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0 ; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload ; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0 -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; VI-NEXT: v_or_b32_sdwa v1, v12, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v2, v41, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_mov_b32_e32 v1, s4 ; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload @@ -119235,8 +117284,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload ; VI-NEXT: s_or_saveexec_b64 s[4:5], -1 -; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_setpc_b64 s[30:31] @@ -119245,8 +117294,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 -; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: v_writelane_b32 v63, s30, 0 ; GFX9-NEXT: v_writelane_b32 v63, s31, 1 @@ -119270,40 +117319,68 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; GFX9-NEXT: v_writelane_b32 v63, s67, 19 ; GFX9-NEXT: v_writelane_b32 v63, s68, 20 ; GFX9-NEXT: v_writelane_b32 v63, s69, 21 +; GFX9-NEXT: v_mov_b32_e32 v20, s16 ; GFX9-NEXT: v_writelane_b32 v63, s70, 22 +; GFX9-NEXT: v_readfirstlane_b32 s56, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s17 ; GFX9-NEXT: v_writelane_b32 v63, s71, 23 +; GFX9-NEXT: v_readfirstlane_b32 s57, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s18 ; GFX9-NEXT: v_writelane_b32 v63, s80, 24 +; GFX9-NEXT: v_readfirstlane_b32 s46, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s19 ; GFX9-NEXT: v_writelane_b32 v63, s81, 25 +; GFX9-NEXT: v_readfirstlane_b32 s47, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s20 ; GFX9-NEXT: v_writelane_b32 v63, s82, 26 +; GFX9-NEXT: v_readfirstlane_b32 s44, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s21 ; GFX9-NEXT: v_writelane_b32 v63, s83, 27 +; GFX9-NEXT: v_readfirstlane_b32 s45, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s22 ; GFX9-NEXT: v_writelane_b32 v63, s84, 28 +; GFX9-NEXT: v_readfirstlane_b32 s42, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s23 ; GFX9-NEXT: v_writelane_b32 v63, s85, 29 +; GFX9-NEXT: v_readfirstlane_b32 s43, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s24 ; GFX9-NEXT: v_writelane_b32 v63, s86, 30 +; GFX9-NEXT: v_readfirstlane_b32 s40, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s25 ; GFX9-NEXT: v_writelane_b32 v63, s87, 31 +; GFX9-NEXT: v_readfirstlane_b32 s41, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s26 ; GFX9-NEXT: v_writelane_b32 v63, s96, 32 +; GFX9-NEXT: v_readfirstlane_b32 s24, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s27 ; GFX9-NEXT: v_writelane_b32 v63, s97, 33 +; GFX9-NEXT: v_readfirstlane_b32 s25, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s28 ; GFX9-NEXT: v_writelane_b32 v63, s98, 34 +; GFX9-NEXT: v_readfirstlane_b32 s22, v20 +; GFX9-NEXT: v_mov_b32_e32 v20, s29 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; GFX9-NEXT: v_writelane_b32 v63, s99, 35 -; GFX9-NEXT: v_readfirstlane_b32 s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s7, v2 -; GFX9-NEXT: v_readfirstlane_b32 s8, v3 -; GFX9-NEXT: v_readfirstlane_b32 s9, v4 -; GFX9-NEXT: v_readfirstlane_b32 s10, v5 -; GFX9-NEXT: v_readfirstlane_b32 s11, v6 -; GFX9-NEXT: v_readfirstlane_b32 s12, v7 -; GFX9-NEXT: v_readfirstlane_b32 s13, v8 -; GFX9-NEXT: v_readfirstlane_b32 s14, v9 -; GFX9-NEXT: v_readfirstlane_b32 s15, v10 -; GFX9-NEXT: v_readfirstlane_b32 s40, v11 -; GFX9-NEXT: v_readfirstlane_b32 s41, v12 -; GFX9-NEXT: v_readfirstlane_b32 s42, v13 -; GFX9-NEXT: v_readfirstlane_b32 s43, v14 -; GFX9-NEXT: v_readfirstlane_b32 s44, v15 -; GFX9-NEXT: v_readfirstlane_b32 s45, v16 -; GFX9-NEXT: v_readfirstlane_b32 s4, v17 -; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec -; GFX9-NEXT: v_readfirstlane_b32 s5, v18 +; GFX9-NEXT: v_readfirstlane_b32 s23, v20 +; GFX9-NEXT: v_readfirstlane_b32 s20, v1 +; GFX9-NEXT: v_readfirstlane_b32 s21, v2 +; GFX9-NEXT: v_readfirstlane_b32 s18, v3 +; GFX9-NEXT: v_readfirstlane_b32 s19, v4 +; GFX9-NEXT: v_readfirstlane_b32 s16, v5 +; GFX9-NEXT: v_readfirstlane_b32 s17, v6 +; GFX9-NEXT: v_readfirstlane_b32 s14, v7 +; GFX9-NEXT: v_readfirstlane_b32 s15, v8 +; GFX9-NEXT: v_readfirstlane_b32 s12, v9 +; GFX9-NEXT: v_readfirstlane_b32 s13, v10 +; GFX9-NEXT: v_readfirstlane_b32 s10, v11 +; GFX9-NEXT: v_readfirstlane_b32 s11, v12 +; GFX9-NEXT: v_readfirstlane_b32 s8, v13 +; GFX9-NEXT: v_readfirstlane_b32 s9, v14 +; GFX9-NEXT: v_readfirstlane_b32 s4, v15 +; GFX9-NEXT: v_readfirstlane_b32 s5, v16 +; GFX9-NEXT: v_readfirstlane_b32 s6, v17 +; GFX9-NEXT: s_and_b64 s[26:27], vcc, exec +; GFX9-NEXT: v_readfirstlane_b32 s7, v18 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill @@ -119321,372 +117398,300 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; GFX9-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; GFX9-NEXT: s_cbranch_scc0 .LBB73_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false -; GFX9-NEXT: s_lshr_b32 s46, s5, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 2 -; GFX9-NEXT: s_lshr_b32 s46, s5, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 3 -; GFX9-NEXT: s_lshr_b32 s46, s5, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 4 -; GFX9-NEXT: s_lshr_b32 s46, s4, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 0 -; GFX9-NEXT: s_lshr_b32 s46, s4, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 1 -; GFX9-NEXT: s_lshr_b32 s46, s45, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 5 -; GFX9-NEXT: s_lshr_b32 s46, s45, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 6 -; GFX9-NEXT: s_lshr_b32 s46, s45, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 7 -; GFX9-NEXT: s_lshr_b32 s46, s43, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 8 -; GFX9-NEXT: s_lshr_b32 s46, s43, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 9 -; GFX9-NEXT: s_lshr_b32 s46, s43, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 10 -; GFX9-NEXT: s_lshr_b32 s46, s41, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 11 -; GFX9-NEXT: s_lshr_b32 s46, s41, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 12 -; GFX9-NEXT: s_lshr_b32 s46, s41, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 13 -; GFX9-NEXT: s_lshr_b32 s46, s15, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 14 -; GFX9-NEXT: s_lshr_b32 s46, s15, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 15 -; GFX9-NEXT: s_lshr_b32 s46, s15, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 16 -; GFX9-NEXT: s_lshr_b32 s46, s13, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 17 -; GFX9-NEXT: s_lshr_b32 s46, s13, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 18 -; GFX9-NEXT: s_lshr_b32 s46, s13, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 19 -; GFX9-NEXT: s_lshr_b32 s46, s11, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 20 -; GFX9-NEXT: s_lshr_b32 s46, s11, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 21 -; GFX9-NEXT: s_lshr_b32 s46, s11, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 22 -; GFX9-NEXT: s_lshr_b32 s46, s9, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 23 -; GFX9-NEXT: s_lshr_b32 s46, s9, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 24 -; GFX9-NEXT: s_lshr_b32 s46, s9, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 25 -; GFX9-NEXT: s_lshr_b32 s46, s7, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 26 -; GFX9-NEXT: s_lshr_b32 s46, s7, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 27 -; GFX9-NEXT: s_lshr_b32 s46, s7, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 28 -; GFX9-NEXT: s_lshr_b32 s46, s29, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 29 -; GFX9-NEXT: s_lshr_b32 s46, s29, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 30 -; GFX9-NEXT: s_lshr_b32 s46, s29, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 31 -; GFX9-NEXT: s_lshr_b32 s46, s27, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 32 -; GFX9-NEXT: s_lshr_b32 s46, s27, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 33 -; GFX9-NEXT: s_lshr_b32 s46, s27, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 34 -; GFX9-NEXT: s_lshr_b32 s46, s25, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 35 -; GFX9-NEXT: s_lshr_b32 s46, s25, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 36 -; GFX9-NEXT: s_lshr_b32 s46, s25, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 37 -; GFX9-NEXT: s_lshr_b32 s46, s23, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 38 -; GFX9-NEXT: s_lshr_b32 s46, s23, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 39 -; GFX9-NEXT: s_lshr_b32 s46, s23, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 40 -; GFX9-NEXT: s_lshr_b32 s46, s21, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 41 -; GFX9-NEXT: s_lshr_b32 s46, s21, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 42 -; GFX9-NEXT: s_lshr_b32 s46, s21, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 43 -; GFX9-NEXT: s_lshr_b32 s46, s19, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 44 -; GFX9-NEXT: s_lshr_b32 s46, s19, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 45 -; GFX9-NEXT: s_lshr_b32 s46, s19, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 46 -; GFX9-NEXT: s_lshr_b32 s46, s17, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 47 -; GFX9-NEXT: s_lshr_b32 s46, s17, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 48 -; GFX9-NEXT: s_lshr_b32 s46, s17, 8 -; GFX9-NEXT: s_lshr_b32 s83, s44, 16 -; GFX9-NEXT: s_lshr_b32 s82, s44, 8 -; GFX9-NEXT: s_lshr_b32 s85, s42, 16 -; GFX9-NEXT: s_lshr_b32 s84, s42, 8 -; GFX9-NEXT: s_lshr_b32 s87, s40, 16 -; GFX9-NEXT: s_lshr_b32 s86, s40, 8 -; GFX9-NEXT: s_lshr_b32 s97, s14, 16 -; GFX9-NEXT: s_lshr_b32 s96, s14, 8 -; GFX9-NEXT: s_lshr_b32 s99, s12, 16 -; GFX9-NEXT: s_lshr_b32 s98, s12, 8 -; GFX9-NEXT: s_lshr_b32 s39, s10, 16 -; GFX9-NEXT: s_lshr_b32 s38, s10, 8 -; GFX9-NEXT: s_lshr_b32 s49, s8, 16 -; GFX9-NEXT: s_lshr_b32 s48, s8, 8 -; GFX9-NEXT: s_lshr_b32 s51, s6, 16 -; GFX9-NEXT: s_lshr_b32 s50, s6, 8 -; GFX9-NEXT: s_lshr_b32 s53, s28, 16 -; GFX9-NEXT: s_lshr_b32 s52, s28, 8 -; GFX9-NEXT: s_lshr_b32 s55, s26, 16 -; GFX9-NEXT: s_lshr_b32 s54, s26, 8 -; GFX9-NEXT: s_lshr_b32 s65, s24, 16 -; GFX9-NEXT: s_lshr_b32 s64, s24, 8 -; GFX9-NEXT: s_lshr_b32 s67, s22, 16 -; GFX9-NEXT: s_lshr_b32 s66, s22, 8 -; GFX9-NEXT: s_lshr_b32 s69, s20, 16 -; GFX9-NEXT: s_lshr_b32 s68, s20, 8 -; GFX9-NEXT: s_lshr_b32 s71, s18, 16 -; GFX9-NEXT: s_lshr_b32 s70, s18, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 49 -; GFX9-NEXT: s_lshr_b32 s81, s16, 16 -; GFX9-NEXT: s_lshr_b32 s80, s16, 8 -; GFX9-NEXT: s_lshr_b64 s[46:47], s[4:5], 24 -; GFX9-NEXT: s_lshr_b64 s[56:57], s[44:45], 24 -; GFX9-NEXT: s_lshr_b64 s[58:59], s[42:43], 24 -; GFX9-NEXT: s_lshr_b64 s[60:61], s[40:41], 24 -; GFX9-NEXT: s_lshr_b64 s[62:63], s[14:15], 24 -; GFX9-NEXT: s_lshr_b64 s[72:73], s[12:13], 24 -; GFX9-NEXT: s_lshr_b64 s[74:75], s[10:11], 24 -; GFX9-NEXT: s_lshr_b64 s[76:77], s[8:9], 24 -; GFX9-NEXT: s_lshr_b64 s[78:79], s[6:7], 24 -; GFX9-NEXT: s_lshr_b64 s[88:89], s[28:29], 24 -; GFX9-NEXT: s_lshr_b64 s[90:91], s[26:27], 24 -; GFX9-NEXT: s_lshr_b64 s[92:93], s[24:25], 24 -; GFX9-NEXT: s_lshr_b64 s[94:95], s[22:23], 24 -; GFX9-NEXT: s_lshr_b64 s[30:31], s[20:21], 24 -; GFX9-NEXT: s_lshr_b64 s[34:35], s[18:19], 24 -; GFX9-NEXT: s_lshr_b64 s[36:37], s[16:17], 24 +; GFX9-NEXT: s_lshr_b32 s26, s7, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 2 +; GFX9-NEXT: s_lshr_b32 s26, s7, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 3 +; GFX9-NEXT: s_lshr_b32 s26, s7, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 4 +; GFX9-NEXT: s_lshr_b32 s26, s6, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 0 +; GFX9-NEXT: s_lshr_b32 s26, s6, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 1 +; GFX9-NEXT: s_lshr_b32 s26, s5, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 5 +; GFX9-NEXT: s_lshr_b32 s26, s5, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 6 +; GFX9-NEXT: s_lshr_b32 s26, s5, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 7 +; GFX9-NEXT: s_lshr_b32 s26, s9, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 8 +; GFX9-NEXT: s_lshr_b32 s26, s9, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 9 +; GFX9-NEXT: s_lshr_b32 s26, s9, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 10 +; GFX9-NEXT: s_lshr_b32 s26, s11, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 11 +; GFX9-NEXT: s_lshr_b32 s26, s11, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 12 +; GFX9-NEXT: s_lshr_b32 s26, s11, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 13 +; GFX9-NEXT: s_lshr_b32 s26, s13, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 14 +; GFX9-NEXT: s_lshr_b32 s26, s13, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 15 +; GFX9-NEXT: s_lshr_b32 s26, s13, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 16 +; GFX9-NEXT: s_lshr_b32 s26, s15, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 17 +; GFX9-NEXT: s_lshr_b32 s26, s15, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 18 +; GFX9-NEXT: s_lshr_b32 s26, s15, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 19 +; GFX9-NEXT: s_lshr_b32 s26, s17, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 20 +; GFX9-NEXT: s_lshr_b32 s26, s17, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 21 +; GFX9-NEXT: s_lshr_b32 s26, s17, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 22 +; GFX9-NEXT: s_lshr_b32 s26, s19, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 23 +; GFX9-NEXT: s_lshr_b32 s26, s19, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 24 +; GFX9-NEXT: s_lshr_b32 s26, s19, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 25 +; GFX9-NEXT: s_lshr_b32 s26, s21, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 26 +; GFX9-NEXT: s_lshr_b32 s26, s21, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 27 +; GFX9-NEXT: s_lshr_b32 s26, s21, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 28 +; GFX9-NEXT: s_lshr_b32 s26, s23, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 29 +; GFX9-NEXT: s_lshr_b32 s26, s23, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 30 +; GFX9-NEXT: s_lshr_b32 s26, s23, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 31 +; GFX9-NEXT: s_lshr_b32 s26, s25, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 32 +; GFX9-NEXT: s_lshr_b32 s26, s25, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 33 +; GFX9-NEXT: s_lshr_b32 s26, s25, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 34 +; GFX9-NEXT: s_lshr_b32 s26, s41, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 35 +; GFX9-NEXT: s_lshr_b32 s26, s41, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 36 +; GFX9-NEXT: s_lshr_b32 s26, s41, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 37 +; GFX9-NEXT: s_lshr_b32 s26, s43, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 38 +; GFX9-NEXT: s_lshr_b32 s26, s43, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 39 +; GFX9-NEXT: s_lshr_b32 s26, s43, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 40 +; GFX9-NEXT: s_lshr_b32 s26, s45, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 41 +; GFX9-NEXT: s_lshr_b32 s26, s45, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 42 +; GFX9-NEXT: s_lshr_b32 s26, s45, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 43 +; GFX9-NEXT: s_lshr_b32 s26, s47, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 44 +; GFX9-NEXT: s_lshr_b32 s26, s47, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 45 +; GFX9-NEXT: s_lshr_b32 s26, s47, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 46 +; GFX9-NEXT: s_lshr_b32 s26, s57, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 47 +; GFX9-NEXT: s_lshr_b32 s26, s57, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 48 +; GFX9-NEXT: s_lshr_b32 s26, s57, 8 +; GFX9-NEXT: s_lshr_b32 s83, s4, 16 +; GFX9-NEXT: s_lshr_b32 s82, s4, 8 +; GFX9-NEXT: s_lshr_b32 s85, s8, 16 +; GFX9-NEXT: s_lshr_b32 s84, s8, 8 +; GFX9-NEXT: s_lshr_b32 s87, s10, 16 +; GFX9-NEXT: s_lshr_b32 s86, s10, 8 +; GFX9-NEXT: s_lshr_b32 s97, s12, 16 +; GFX9-NEXT: s_lshr_b32 s96, s12, 8 +; GFX9-NEXT: s_lshr_b32 s99, s14, 16 +; GFX9-NEXT: s_lshr_b32 s98, s14, 8 +; GFX9-NEXT: s_lshr_b32 s39, s16, 16 +; GFX9-NEXT: s_lshr_b32 s38, s16, 8 +; GFX9-NEXT: s_lshr_b32 s49, s18, 16 +; GFX9-NEXT: s_lshr_b32 s48, s18, 8 +; GFX9-NEXT: s_lshr_b32 s51, s20, 16 +; GFX9-NEXT: s_lshr_b32 s50, s20, 8 +; GFX9-NEXT: s_lshr_b32 s53, s22, 16 +; GFX9-NEXT: s_lshr_b32 s52, s22, 8 +; GFX9-NEXT: s_lshr_b32 s55, s24, 16 +; GFX9-NEXT: s_lshr_b32 s54, s24, 8 +; GFX9-NEXT: s_lshr_b32 s65, s40, 16 +; GFX9-NEXT: s_lshr_b32 s64, s40, 8 +; GFX9-NEXT: s_lshr_b32 s67, s42, 16 +; GFX9-NEXT: s_lshr_b32 s66, s42, 8 +; GFX9-NEXT: s_lshr_b32 s69, s44, 16 +; GFX9-NEXT: s_lshr_b32 s68, s44, 8 +; GFX9-NEXT: s_lshr_b32 s71, s46, 16 +; GFX9-NEXT: s_lshr_b32 s70, s46, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 49 +; GFX9-NEXT: s_lshr_b32 s81, s56, 16 +; GFX9-NEXT: s_lshr_b32 s80, s56, 8 +; GFX9-NEXT: s_lshr_b64 s[26:27], s[6:7], 24 +; GFX9-NEXT: s_lshr_b64 s[28:29], s[4:5], 24 +; GFX9-NEXT: s_lshr_b64 s[58:59], s[8:9], 24 +; GFX9-NEXT: s_lshr_b64 s[60:61], s[10:11], 24 +; GFX9-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 +; GFX9-NEXT: s_lshr_b64 s[72:73], s[14:15], 24 +; GFX9-NEXT: s_lshr_b64 s[74:75], s[16:17], 24 +; GFX9-NEXT: s_lshr_b64 s[76:77], s[18:19], 24 +; GFX9-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 +; GFX9-NEXT: s_lshr_b64 s[88:89], s[22:23], 24 +; GFX9-NEXT: s_lshr_b64 s[90:91], s[24:25], 24 +; GFX9-NEXT: s_lshr_b64 s[92:93], s[40:41], 24 +; GFX9-NEXT: s_lshr_b64 s[94:95], s[42:43], 24 +; GFX9-NEXT: s_lshr_b64 s[30:31], s[44:45], 24 +; GFX9-NEXT: s_lshr_b64 s[34:35], s[46:47], 24 +; GFX9-NEXT: s_lshr_b64 s[36:37], s[56:57], 24 ; GFX9-NEXT: s_cbranch_execnz .LBB73_4 ; GFX9-NEXT: .LBB73_2: ; %cmp.true -; GFX9-NEXT: v_add_f64 v[11:12], s[4:5], 1.0 -; GFX9-NEXT: v_add_f64 v[1:2], s[44:45], 1.0 -; GFX9-NEXT: v_add_f64 v[3:4], s[42:43], 1.0 -; GFX9-NEXT: v_add_f64 v[5:6], s[40:41], 1.0 -; GFX9-NEXT: v_add_f64 v[7:8], s[14:15], 1.0 +; GFX9-NEXT: v_add_f64 v[1:2], s[6:7], 1.0 +; GFX9-NEXT: v_add_f64 v[3:4], s[4:5], 1.0 +; GFX9-NEXT: v_add_f64 v[5:6], s[8:9], 1.0 +; GFX9-NEXT: v_add_f64 v[35:36], s[40:41], 1.0 +; GFX9-NEXT: v_add_f64 v[37:38], s[42:43], 1.0 +; GFX9-NEXT: v_add_f64 v[7:8], s[10:11], 1.0 +; GFX9-NEXT: v_add_f64 v[48:49], s[44:45], 1.0 +; GFX9-NEXT: v_add_f64 v[13:14], s[14:15], 1.0 +; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[1:2] ; GFX9-NEXT: v_add_f64 v[9:10], s[12:13], 1.0 -; GFX9-NEXT: v_add_f64 v[13:14], s[10:11], 1.0 -; GFX9-NEXT: v_add_f64 v[19:20], s[8:9], 1.0 -; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[11:12] -; GFX9-NEXT: v_add_f64 v[23:24], s[6:7], 1.0 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2] -; GFX9-NEXT: v_add_f64 v[27:28], s[28:29], 1.0 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[3:4] -; GFX9-NEXT: v_add_f64 v[31:32], s[26:27], 1.0 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; GFX9-NEXT: v_add_f64 v[52:53], s[46:47], 1.0 +; GFX9-NEXT: v_add_f64 v[15:16], s[16:17], 1.0 +; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[5:6] +; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: v_add_f64 v[39:40], s[56:57], 1.0 ; GFX9-NEXT: v_add_f64 v[33:34], s[24:25], 1.0 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[7:8] -; GFX9-NEXT: v_add_f64 v[35:36], s[22:23], 1.0 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[9:10] -; GFX9-NEXT: v_add_f64 v[37:38], s[20:21], 1.0 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[13:14] -; GFX9-NEXT: v_add_f64 v[48:49], s[18:19], 1.0 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[19:20] -; GFX9-NEXT: v_add_f64 v[50:51], s[16:17], 1.0 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[23:24] -; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v37 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[27:28] -; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v48 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[31:32] -; GFX9-NEXT: v_lshrrev_b32_e32 v30, 8, v20 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[33:34] -; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v24 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[35:36] -; GFX9-NEXT: v_lshrrev_b32_e32 v44, 8, v28 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[37:38] -; GFX9-NEXT: v_lshrrev_b32_e32 v26, 24, v32 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[48:49] -; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v32 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[50:51] -; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v32 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v12 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v12 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v12 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v11 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v11 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v2 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v2 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v2 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v1 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v1 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v4 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v4 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v4 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v3 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v3 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v6 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v6 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v6 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v5 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v5 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v8 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v8 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v8 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v7 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v7 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v10 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v10 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v10 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v9 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v9 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v14 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v14 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v14 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v13 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v13 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v20 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v20 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v19 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v19 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v24 -; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v27 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v24 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v16, 8, v27 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v23 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v31 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v23 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v33 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v28 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v35 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v28 -; GFX9-NEXT: v_lshrrev_b32_e32 v52, 8, v31 -; GFX9-NEXT: v_lshrrev_b32_e32 v39, 24, v34 -; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v34 -; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v34 -; GFX9-NEXT: v_lshrrev_b32_e32 v54, 8, v33 -; GFX9-NEXT: v_lshrrev_b32_e32 v42, 24, v36 -; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v36 -; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v36 -; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v41, 8, v35 -; GFX9-NEXT: v_lshrrev_b32_e32 v47, 24, v38 -; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v38 -; GFX9-NEXT: v_lshrrev_b32_e32 v18, 8, v38 -; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v43, 8, v37 -; GFX9-NEXT: v_lshrrev_b32_e32 v17, 24, v49 -; GFX9-NEXT: v_lshrrev_b32_e32 v58, 16, v49 -; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v49 -; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill -; GFX9-NEXT: v_lshrrev_b32_e32 v45, 8, v48 -; GFX9-NEXT: v_lshrrev_b32_e32 v59, 24, v51 -; GFX9-NEXT: v_lshrrev_b32_e32 v60, 16, v51 -; GFX9-NEXT: v_lshrrev_b32_e32 v25, 8, v51 -; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v50 -; GFX9-NEXT: v_lshrrev_b32_e32 v56, 8, v50 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill +; GFX9-NEXT: v_add_f64 v[31:32], s[22:23], 1.0 +; GFX9-NEXT: v_add_f64 v[28:29], s[20:21], 1.0 +; GFX9-NEXT: v_add_f64 v[19:20], s[18:19], 1.0 +; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[3:4] +; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[5:6] +; GFX9-NEXT: v_lshrrev_b64 v[41:42], 24, v[35:36] +; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[7:8] +; GFX9-NEXT: v_lshrrev_b64 v[42:43], 24, v[37:38] +; GFX9-NEXT: v_readfirstlane_b32 s13, v10 +; GFX9-NEXT: v_lshrrev_b64 v[10:11], 24, v[9:10] +; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[13:14] +; GFX9-NEXT: v_lshrrev_b64 v[43:44], 24, v[48:49] +; GFX9-NEXT: v_lshrrev_b64 v[25:26], 24, v[15:16] +; GFX9-NEXT: v_lshrrev_b64 v[44:45], 24, v[52:53] +; GFX9-NEXT: v_readfirstlane_b32 s57, v40 +; GFX9-NEXT: v_readfirstlane_b32 s47, v53 +; GFX9-NEXT: v_readfirstlane_b32 s45, v49 +; GFX9-NEXT: v_readfirstlane_b32 s43, v38 +; GFX9-NEXT: v_readfirstlane_b32 s41, v36 +; GFX9-NEXT: v_readfirstlane_b32 s25, v34 +; GFX9-NEXT: v_readfirstlane_b32 s23, v32 +; GFX9-NEXT: v_readfirstlane_b32 s21, v29 +; GFX9-NEXT: v_readfirstlane_b32 s19, v20 +; GFX9-NEXT: v_readfirstlane_b32 s17, v16 +; GFX9-NEXT: v_readfirstlane_b32 s15, v14 +; GFX9-NEXT: v_readfirstlane_b32 s11, v8 +; GFX9-NEXT: v_readfirstlane_b32 s9, v6 +; GFX9-NEXT: v_readfirstlane_b32 s5, v4 +; GFX9-NEXT: v_readfirstlane_b32 s7, v2 +; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GFX9-NEXT: v_lshrrev_b64 v[26:27], 24, v[19:20] +; GFX9-NEXT: v_lshrrev_b64 v[29:30], 24, v[28:29] +; GFX9-NEXT: v_lshrrev_b64 v[50:51], 24, v[31:32] +; GFX9-NEXT: v_lshrrev_b64 v[54:55], 24, v[33:34] +; GFX9-NEXT: v_lshrrev_b64 v[45:46], 24, v[39:40] +; GFX9-NEXT: s_lshr_b32 s10, s7, 24 +; GFX9-NEXT: s_lshr_b32 s12, s7, 16 +; GFX9-NEXT: s_lshr_b32 s14, s7, 8 +; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; GFX9-NEXT: v_lshrrev_b32_e32 v4, 8, v1 +; GFX9-NEXT: s_lshr_b32 s16, s5, 24 +; GFX9-NEXT: s_lshr_b32 s18, s5, 16 +; GFX9-NEXT: s_lshr_b32 s20, s5, 8 +; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v3 +; GFX9-NEXT: v_lshrrev_b32_e32 v8, 8, v3 +; GFX9-NEXT: s_lshr_b32 s22, s9, 24 +; GFX9-NEXT: s_lshr_b32 s24, s9, 16 +; GFX9-NEXT: s_lshr_b32 s26, s9, 8 +; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v5 +; GFX9-NEXT: v_lshrrev_b32_e32 v12, 8, v5 +; GFX9-NEXT: s_lshr_b32 s27, s11, 24 +; GFX9-NEXT: s_lshr_b32 s28, s11, 16 +; GFX9-NEXT: s_lshr_b32 s29, s11, 8 +; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v7 +; GFX9-NEXT: v_lshrrev_b32_e32 v16, 8, v7 +; GFX9-NEXT: s_lshr_b32 s40, s13, 24 +; GFX9-NEXT: s_lshr_b32 s42, s13, 16 +; GFX9-NEXT: s_lshr_b32 s44, s13, 8 +; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v9 +; GFX9-NEXT: v_lshrrev_b32_e32 v20, 8, v9 +; GFX9-NEXT: s_lshr_b32 s46, s15, 24 +; GFX9-NEXT: s_lshr_b32 s56, s15, 16 +; GFX9-NEXT: s_lshr_b32 s58, s15, 8 +; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v13 +; GFX9-NEXT: v_lshrrev_b32_e32 v30, 8, v13 +; GFX9-NEXT: s_lshr_b32 s59, s17, 24 +; GFX9-NEXT: s_lshr_b32 s60, s17, 16 +; GFX9-NEXT: s_lshr_b32 s61, s17, 8 +; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v15 +; GFX9-NEXT: v_lshrrev_b32_e32 v34, 8, v15 +; GFX9-NEXT: s_lshr_b32 s62, s19, 24 +; GFX9-NEXT: s_lshr_b32 s63, s19, 16 +; GFX9-NEXT: s_lshr_b32 s72, s19, 8 +; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v19 +; GFX9-NEXT: v_lshrrev_b32_e32 v38, 8, v19 +; GFX9-NEXT: s_lshr_b32 s73, s21, 24 +; GFX9-NEXT: s_lshr_b32 s74, s21, 16 +; GFX9-NEXT: s_lshr_b32 s75, s21, 8 +; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v28 +; GFX9-NEXT: v_lshrrev_b32_e32 v51, 8, v28 +; GFX9-NEXT: s_lshr_b32 s76, s23, 24 +; GFX9-NEXT: s_lshr_b32 s77, s23, 16 +; GFX9-NEXT: s_lshr_b32 s78, s23, 8 +; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v31 +; GFX9-NEXT: v_lshrrev_b32_e32 v56, 8, v31 +; GFX9-NEXT: s_lshr_b32 s79, s25, 24 +; GFX9-NEXT: s_lshr_b32 s88, s25, 16 +; GFX9-NEXT: s_lshr_b32 s89, s25, 8 +; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v33 +; GFX9-NEXT: v_lshrrev_b32_e32 v58, 8, v33 +; GFX9-NEXT: s_lshr_b32 s90, s41, 24 +; GFX9-NEXT: s_lshr_b32 s91, s41, 16 +; GFX9-NEXT: s_lshr_b32 s92, s41, 8 +; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v35 +; GFX9-NEXT: v_lshrrev_b32_e32 v59, 8, v35 +; GFX9-NEXT: s_lshr_b32 s93, s43, 24 +; GFX9-NEXT: s_lshr_b32 s94, s43, 16 +; GFX9-NEXT: s_lshr_b32 s95, s43, 8 +; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v37 +; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v37 +; GFX9-NEXT: s_lshr_b32 vcc_lo, s45, 24 +; GFX9-NEXT: s_lshr_b32 vcc_hi, s45, 16 +; GFX9-NEXT: s_lshr_b32 s30, s45, 8 +; GFX9-NEXT: v_lshrrev_b32_e32 v47, 16, v48 +; GFX9-NEXT: v_lshrrev_b32_e32 v11, 8, v48 +; GFX9-NEXT: s_lshr_b32 s31, s47, 24 +; GFX9-NEXT: s_lshr_b32 s34, s47, 16 +; GFX9-NEXT: s_lshr_b32 s35, s47, 8 +; GFX9-NEXT: v_lshrrev_b32_e32 v57, 16, v52 +; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v52 +; GFX9-NEXT: s_lshr_b32 s8, s57, 24 +; GFX9-NEXT: s_lshr_b32 s36, s57, 16 +; GFX9-NEXT: s_lshr_b32 s6, s57, 8 +; GFX9-NEXT: v_lshrrev_b32_e32 v60, 16, v39 +; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v39 ; GFX9-NEXT: s_branch .LBB73_5 ; GFX9-NEXT: .LBB73_3: -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 ; GFX9-NEXT: ; implicit-def: $sgpr80 ; GFX9-NEXT: ; implicit-def: $sgpr81 ; GFX9-NEXT: ; implicit-def: $sgpr70 @@ -119731,417 +117736,435 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; GFX9-NEXT: ; implicit-def: $sgpr62 ; GFX9-NEXT: ; implicit-def: $sgpr60 ; GFX9-NEXT: ; implicit-def: $sgpr58 -; GFX9-NEXT: ; implicit-def: $sgpr56 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr28 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 ; GFX9-NEXT: s_branch .LBB73_2 ; GFX9-NEXT: .LBB73_4: -; GFX9-NEXT: v_mov_b32_e32 v41, s66 -; GFX9-NEXT: v_mov_b32_e32 v40, s36 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v40, s34 -; GFX9-NEXT: v_mov_b32_e32 v15, s81 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s71 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s69 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s67 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s65 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s55 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s53 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s52 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s51 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s50 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s49 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s48 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s39 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s38 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s99 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s98 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s97 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s96 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s87 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s86 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s85 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s84 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s83 -; GFX9-NEXT: v_mov_b32_e32 v11, s4 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s82 -; GFX9-NEXT: v_readlane_b32 s4, v62, 0 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 1 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 2 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 3 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 4 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 5 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 6 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 7 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 8 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 9 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v40, s30 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 10 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 11 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 12 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 13 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 14 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 15 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 16 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 17 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 18 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 19 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 20 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 21 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 22 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 23 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 24 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 25 -; GFX9-NEXT: v_mov_b32_e32 v30, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 26 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 27 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 28 -; GFX9-NEXT: v_mov_b32_e32 v29, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 29 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 30 -; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v15, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 31 -; GFX9-NEXT: v_mov_b32_e32 v44, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 32 -; GFX9-NEXT: v_mov_b32_e32 v26, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 33 -; GFX9-NEXT: v_mov_b32_e32 v53, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 34 -; GFX9-NEXT: v_mov_b32_e32 v57, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 35 -; GFX9-NEXT: v_mov_b32_e32 v39, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 36 -; GFX9-NEXT: v_mov_b32_e32 v55, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 37 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v40, s94 -; GFX9-NEXT: v_mov_b32_e32 v61, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 38 -; GFX9-NEXT: v_mov_b32_e32 v42, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 39 -; GFX9-NEXT: v_mov_b32_e32 v46, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 40 -; GFX9-NEXT: v_mov_b32_e32 v21, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 41 -; GFX9-NEXT: v_mov_b32_e32 v47, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 42 -; GFX9-NEXT: v_mov_b32_e32 v16, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 43 -; GFX9-NEXT: v_mov_b32_e32 v18, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 44 -; GFX9-NEXT: v_mov_b32_e32 v17, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 45 -; GFX9-NEXT: v_mov_b32_e32 v58, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 46 -; GFX9-NEXT: v_mov_b32_e32 v22, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 47 -; GFX9-NEXT: v_mov_b32_e32 v59, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 48 -; GFX9-NEXT: v_mov_b32_e32 v60, s4 -; GFX9-NEXT: v_readlane_b32 s4, v62, 49 -; GFX9-NEXT: v_mov_b32_e32 v12, s5 -; GFX9-NEXT: v_mov_b32_e32 v1, s44 -; GFX9-NEXT: v_mov_b32_e32 v2, s45 -; GFX9-NEXT: v_mov_b32_e32 v3, s42 -; GFX9-NEXT: v_mov_b32_e32 v4, s43 -; GFX9-NEXT: v_mov_b32_e32 v5, s40 -; GFX9-NEXT: v_mov_b32_e32 v6, s41 -; GFX9-NEXT: v_mov_b32_e32 v7, s14 -; GFX9-NEXT: v_mov_b32_e32 v8, s15 -; GFX9-NEXT: v_mov_b32_e32 v9, s12 -; GFX9-NEXT: v_mov_b32_e32 v10, s13 -; GFX9-NEXT: v_mov_b32_e32 v13, s10 -; GFX9-NEXT: v_mov_b32_e32 v14, s11 -; GFX9-NEXT: v_mov_b32_e32 v19, s8 -; GFX9-NEXT: v_mov_b32_e32 v20, s9 -; GFX9-NEXT: v_mov_b32_e32 v23, s6 -; GFX9-NEXT: v_mov_b32_e32 v24, s7 -; GFX9-NEXT: v_mov_b32_e32 v27, s28 -; GFX9-NEXT: v_mov_b32_e32 v28, s29 -; GFX9-NEXT: v_mov_b32_e32 v31, s26 -; GFX9-NEXT: v_mov_b32_e32 v32, s27 +; GFX9-NEXT: v_mov_b32_e32 v22, s62 +; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v23, s60 +; GFX9-NEXT: v_mov_b32_e32 v22, s58 +; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v22, s28 +; GFX9-NEXT: v_readlane_b32 s27, v62, 0 +; GFX9-NEXT: v_mov_b32_e32 v2, s27 +; GFX9-NEXT: v_readlane_b32 s27, v62, 1 +; GFX9-NEXT: v_mov_b32_e32 v60, s81 +; GFX9-NEXT: v_mov_b32_e32 v21, s80 +; GFX9-NEXT: v_mov_b32_e32 v57, s71 +; GFX9-NEXT: v_mov_b32_e32 v17, s70 +; GFX9-NEXT: v_mov_b32_e32 v47, s69 +; GFX9-NEXT: v_mov_b32_e32 v11, s68 +; GFX9-NEXT: v_mov_b32_e32 v46, s67 +; GFX9-NEXT: v_mov_b32_e32 v61, s66 +; GFX9-NEXT: v_mov_b32_e32 v40, s65 +; GFX9-NEXT: v_mov_b32_e32 v59, s64 +; GFX9-NEXT: v_mov_b32_e32 v55, s55 +; GFX9-NEXT: v_mov_b32_e32 v58, s54 +; GFX9-NEXT: v_mov_b32_e32 v53, s53 +; GFX9-NEXT: v_mov_b32_e32 v56, s52 +; GFX9-NEXT: v_mov_b32_e32 v49, s51 +; GFX9-NEXT: v_mov_b32_e32 v51, s50 +; GFX9-NEXT: v_mov_b32_e32 v36, s49 +; GFX9-NEXT: v_mov_b32_e32 v38, s48 +; GFX9-NEXT: v_mov_b32_e32 v32, s39 +; GFX9-NEXT: v_mov_b32_e32 v34, s38 +; GFX9-NEXT: v_mov_b32_e32 v27, s99 +; GFX9-NEXT: v_mov_b32_e32 v30, s98 +; GFX9-NEXT: v_mov_b32_e32 v18, s97 +; GFX9-NEXT: v_mov_b32_e32 v20, s96 +; GFX9-NEXT: v_mov_b32_e32 v14, s87 +; GFX9-NEXT: v_mov_b32_e32 v16, s86 +; GFX9-NEXT: v_mov_b32_e32 v10, s85 +; GFX9-NEXT: v_mov_b32_e32 v12, s84 +; GFX9-NEXT: v_mov_b32_e32 v6, s83 +; GFX9-NEXT: v_mov_b32_e32 v8, s82 +; GFX9-NEXT: v_mov_b32_e32 v4, s27 +; GFX9-NEXT: v_mov_b32_e32 v39, s56 +; GFX9-NEXT: v_mov_b32_e32 v52, s46 +; GFX9-NEXT: v_mov_b32_e32 v48, s44 +; GFX9-NEXT: v_mov_b32_e32 v37, s42 +; GFX9-NEXT: v_mov_b32_e32 v35, s40 ; GFX9-NEXT: v_mov_b32_e32 v33, s24 -; GFX9-NEXT: v_mov_b32_e32 v34, s25 -; GFX9-NEXT: v_mov_b32_e32 v35, s22 -; GFX9-NEXT: v_mov_b32_e32 v36, s23 -; GFX9-NEXT: v_mov_b32_e32 v37, s20 -; GFX9-NEXT: v_mov_b32_e32 v38, s21 -; GFX9-NEXT: v_mov_b32_e32 v48, s18 -; GFX9-NEXT: v_mov_b32_e32 v49, s19 -; GFX9-NEXT: v_mov_b32_e32 v50, s16 -; GFX9-NEXT: v_mov_b32_e32 v51, s17 -; GFX9-NEXT: v_mov_b32_e32 v56, s80 -; GFX9-NEXT: v_mov_b32_e32 v45, s70 -; GFX9-NEXT: v_mov_b32_e32 v43, s68 -; GFX9-NEXT: v_mov_b32_e32 v54, s64 -; GFX9-NEXT: v_mov_b32_e32 v52, s54 -; GFX9-NEXT: v_mov_b32_e32 v25, s4 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v40, s92 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v40, s90 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v40, s88 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v40, s78 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v40, s76 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v40, s74 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v40, s72 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v40, s62 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v40, s60 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v40, s58 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v40, s56 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v40, s46 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v31, s22 +; GFX9-NEXT: v_mov_b32_e32 v28, s20 +; GFX9-NEXT: v_mov_b32_e32 v19, s18 +; GFX9-NEXT: v_mov_b32_e32 v15, s16 +; GFX9-NEXT: v_mov_b32_e32 v13, s14 +; GFX9-NEXT: v_mov_b32_e32 v9, s12 +; GFX9-NEXT: v_mov_b32_e32 v7, s10 +; GFX9-NEXT: v_mov_b32_e32 v5, s8 +; GFX9-NEXT: v_mov_b32_e32 v3, s4 +; GFX9-NEXT: v_mov_b32_e32 v1, s6 +; GFX9-NEXT: v_mov_b32_e32 v45, s36 +; GFX9-NEXT: v_mov_b32_e32 v44, s34 +; GFX9-NEXT: v_mov_b32_e32 v43, s30 +; GFX9-NEXT: v_mov_b32_e32 v42, s94 +; GFX9-NEXT: v_mov_b32_e32 v41, s92 +; GFX9-NEXT: v_mov_b32_e32 v54, s90 +; GFX9-NEXT: v_mov_b32_e32 v50, s88 +; GFX9-NEXT: v_mov_b32_e32 v29, s78 +; GFX9-NEXT: v_mov_b32_e32 v26, s76 +; GFX9-NEXT: v_mov_b32_e32 v25, s74 +; GFX9-NEXT: v_mov_b32_e32 v24, s72 +; GFX9-NEXT: v_readlane_b32 s10, v62, 2 +; GFX9-NEXT: v_readlane_b32 s12, v62, 3 +; GFX9-NEXT: v_readlane_b32 s14, v62, 4 +; GFX9-NEXT: v_readlane_b32 s16, v62, 5 +; GFX9-NEXT: v_readlane_b32 s18, v62, 6 +; GFX9-NEXT: v_readlane_b32 s20, v62, 7 +; GFX9-NEXT: v_readlane_b32 s22, v62, 8 +; GFX9-NEXT: v_readlane_b32 s24, v62, 9 +; GFX9-NEXT: v_readlane_b32 s27, v62, 11 +; GFX9-NEXT: v_readlane_b32 s28, v62, 12 +; GFX9-NEXT: v_readlane_b32 s29, v62, 13 +; GFX9-NEXT: v_readlane_b32 s40, v62, 14 +; GFX9-NEXT: v_readlane_b32 s42, v62, 15 +; GFX9-NEXT: v_readlane_b32 s44, v62, 16 +; GFX9-NEXT: v_readlane_b32 s46, v62, 17 +; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-NEXT: v_mov_b32_e32 v22, s26 +; GFX9-NEXT: v_readlane_b32 s26, v62, 10 +; GFX9-NEXT: v_readlane_b32 s56, v62, 18 +; GFX9-NEXT: v_readlane_b32 s58, v62, 19 +; GFX9-NEXT: v_readlane_b32 s59, v62, 20 +; GFX9-NEXT: v_readlane_b32 s60, v62, 21 +; GFX9-NEXT: v_readlane_b32 s61, v62, 22 +; GFX9-NEXT: v_readlane_b32 s62, v62, 23 +; GFX9-NEXT: v_readlane_b32 s63, v62, 24 +; GFX9-NEXT: v_readlane_b32 s72, v62, 25 +; GFX9-NEXT: v_readlane_b32 s73, v62, 26 +; GFX9-NEXT: v_readlane_b32 s74, v62, 27 +; GFX9-NEXT: v_readlane_b32 s75, v62, 28 +; GFX9-NEXT: v_readlane_b32 s76, v62, 29 +; GFX9-NEXT: v_readlane_b32 s77, v62, 30 +; GFX9-NEXT: v_readlane_b32 s78, v62, 31 +; GFX9-NEXT: v_readlane_b32 s79, v62, 32 +; GFX9-NEXT: v_readlane_b32 s88, v62, 33 +; GFX9-NEXT: v_readlane_b32 s89, v62, 34 +; GFX9-NEXT: v_readlane_b32 s90, v62, 35 +; GFX9-NEXT: v_readlane_b32 s91, v62, 36 +; GFX9-NEXT: v_readlane_b32 s92, v62, 37 +; GFX9-NEXT: v_readlane_b32 s93, v62, 38 +; GFX9-NEXT: v_readlane_b32 s94, v62, 39 +; GFX9-NEXT: v_readlane_b32 s95, v62, 40 +; GFX9-NEXT: v_readlane_b32 vcc_lo, v62, 41 +; GFX9-NEXT: v_readlane_b32 vcc_hi, v62, 42 +; GFX9-NEXT: v_readlane_b32 s30, v62, 43 +; GFX9-NEXT: v_readlane_b32 s31, v62, 44 +; GFX9-NEXT: v_readlane_b32 s34, v62, 45 +; GFX9-NEXT: v_readlane_b32 s35, v62, 46 +; GFX9-NEXT: v_readlane_b32 s8, v62, 47 +; GFX9-NEXT: v_readlane_b32 s36, v62, 48 +; GFX9-NEXT: v_readlane_b32 s6, v62, 49 +; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-NEXT: .LBB73_5: ; %end ; GFX9-NEXT: v_lshlrev_b32_e32 v21, 8, v21 -; GFX9-NEXT: v_or_b32_sdwa v21, v36, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b32_e32 v36, 8, v54 -; GFX9-NEXT: v_or_b32_sdwa v33, v33, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b32_e32 v36, 8, v61 -; GFX9-NEXT: v_or_b32_sdwa v34, v34, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b32_e32 v36, 8, v52 -; GFX9-NEXT: v_or_b32_sdwa v31, v31, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b32_e32 v36, 8, v57 -; GFX9-NEXT: v_or_b32_sdwa v32, v32, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload -; GFX9-NEXT: v_lshlrev_b32_e32 v29, 8, v29 -; GFX9-NEXT: v_or_b32_sdwa v24, v24, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b32_e32 v25, 8, v25 -; GFX9-NEXT: v_or_b32_sdwa v25, v51, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b32_e32 v51, 8, v45 -; GFX9-NEXT: v_or_b32_sdwa v48, v48, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload -; GFX9-NEXT: v_lshlrev_b32_e32 v40, 8, v56 -; GFX9-NEXT: v_or_b32_sdwa v50, v50, v40 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b32_e32 v22, 8, v22 -; GFX9-NEXT: v_or_b32_sdwa v22, v49, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b32_e32 v49, 8, v43 -; GFX9-NEXT: v_or_b32_sdwa v37, v37, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v21, v39, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b32_e32 v39, 8, v61 +; GFX9-NEXT: v_or_b32_sdwa v37, v37, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b32_e32 v39, 8, v59 +; GFX9-NEXT: v_or_b32_sdwa v35, v35, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b32_e32 v39, 8, v58 +; GFX9-NEXT: s_and_b32 s4, s57, 0xff +; GFX9-NEXT: s_lshl_b32 s6, s6, 8 +; GFX9-NEXT: v_or_b32_sdwa v33, v33, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b32_e32 v39, 8, v56 +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: s_and_b32 s6, s36, 0xff +; GFX9-NEXT: s_lshl_b32 s8, s8, 8 +; GFX9-NEXT: v_or_b32_sdwa v31, v31, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b32_e32 v39, 8, v45 +; GFX9-NEXT: s_or_b32 s6, s6, s8 +; GFX9-NEXT: v_or_b32_sdwa v39, v60, v39 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: s_and_b32 s4, s4, 0xffff +; GFX9-NEXT: s_lshl_b32 s6, s6, 16 +; GFX9-NEXT: v_or_b32_sdwa v21, v21, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: buffer_store_dword v21, v0, s[0:3], 0 offen +; GFX9-NEXT: v_mov_b32_e32 v21, s4 +; GFX9-NEXT: s_and_b32 s4, s47, 0xff +; GFX9-NEXT: s_lshl_b32 s6, s35, 8 +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: s_and_b32 s6, s34, 0xff +; GFX9-NEXT: s_lshl_b32 s8, s31, 8 ; GFX9-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; GFX9-NEXT: v_or_b32_sdwa v17, v58, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v17, v22, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b32_e32 v18, 8, v18 -; GFX9-NEXT: v_or_b32_sdwa v18, v38, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b32_e32 v38, 8, v41 -; GFX9-NEXT: v_or_b32_sdwa v35, v35, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: buffer_store_dword v21, v0, s[0:3], 0 offen offset:4 +; GFX9-NEXT: v_lshlrev_b32_e32 v21, 8, v44 +; GFX9-NEXT: s_or_b32 s6, s6, s8 +; GFX9-NEXT: v_or_b32_sdwa v17, v52, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v21, v57, v21 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: s_and_b32 s4, s4, 0xffff +; GFX9-NEXT: s_lshl_b32 s6, s6, 16 +; GFX9-NEXT: v_or_b32_sdwa v17, v17, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:8 +; GFX9-NEXT: v_mov_b32_e32 v17, s4 +; GFX9-NEXT: s_and_b32 s4, s45, 0xff +; GFX9-NEXT: s_lshl_b32 s6, s30, 8 +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: s_and_b32 s6, vcc_hi, 0xff +; GFX9-NEXT: s_lshl_b32 s8, vcc_lo, 8 +; GFX9-NEXT: v_lshlrev_b32_e32 v11, 8, v11 +; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:12 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 8, v43 +; GFX9-NEXT: s_or_b32 s6, s6, s8 +; GFX9-NEXT: v_or_b32_sdwa v11, v48, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v17, v47, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: s_and_b32 s4, s4, 0xffff +; GFX9-NEXT: s_lshl_b32 s6, s6, 16 +; GFX9-NEXT: v_or_b32_sdwa v11, v11, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:16 +; GFX9-NEXT: v_mov_b32_e32 v11, s4 +; GFX9-NEXT: s_and_b32 s4, s43, 0xff +; GFX9-NEXT: s_lshl_b32 s6, s95, 8 +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: s_and_b32 s6, s94, 0xff +; GFX9-NEXT: s_lshl_b32 s8, s93, 8 +; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:20 +; GFX9-NEXT: v_lshlrev_b32_e32 v11, 8, v42 +; GFX9-NEXT: s_or_b32 s6, s6, s8 +; GFX9-NEXT: v_or_b32_sdwa v11, v46, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: s_and_b32 s4, s4, 0xffff +; GFX9-NEXT: s_lshl_b32 s6, s6, 16 +; GFX9-NEXT: v_or_b32_sdwa v11, v37, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:24 +; GFX9-NEXT: v_mov_b32_e32 v11, s4 +; GFX9-NEXT: s_and_b32 s4, s41, 0xff +; GFX9-NEXT: s_lshl_b32 s6, s92, 8 +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: s_and_b32 s6, s91, 0xff +; GFX9-NEXT: s_lshl_b32 s8, s90, 8 +; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:28 +; GFX9-NEXT: v_lshlrev_b32_e32 v11, 8, v41 +; GFX9-NEXT: s_or_b32 s6, s6, s8 +; GFX9-NEXT: v_or_b32_sdwa v11, v40, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: s_and_b32 s4, s4, 0xffff +; GFX9-NEXT: s_lshl_b32 s6, s6, 16 +; GFX9-NEXT: v_or_b32_sdwa v11, v35, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:32 +; GFX9-NEXT: v_mov_b32_e32 v11, s4 +; GFX9-NEXT: s_and_b32 s4, s25, 0xff +; GFX9-NEXT: s_lshl_b32 s6, s89, 8 +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: s_and_b32 s6, s88, 0xff +; GFX9-NEXT: s_lshl_b32 s8, s79, 8 +; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:36 +; GFX9-NEXT: v_lshlrev_b32_e32 v11, 8, v54 +; GFX9-NEXT: s_or_b32 s6, s6, s8 +; GFX9-NEXT: v_or_b32_sdwa v11, v55, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: s_and_b32 s4, s4, 0xffff +; GFX9-NEXT: s_lshl_b32 s6, s6, 16 +; GFX9-NEXT: v_or_b32_sdwa v11, v33, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:40 +; GFX9-NEXT: v_mov_b32_e32 v11, s4 +; GFX9-NEXT: s_and_b32 s4, s23, 0xff +; GFX9-NEXT: s_lshl_b32 s6, s78, 8 +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: s_and_b32 s6, s77, 0xff +; GFX9-NEXT: s_lshl_b32 s8, s76, 8 +; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:44 +; GFX9-NEXT: v_lshlrev_b32_e32 v11, 8, v50 +; GFX9-NEXT: s_or_b32 s6, s6, s8 +; GFX9-NEXT: v_or_b32_sdwa v11, v53, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: s_and_b32 s4, s4, 0xffff +; GFX9-NEXT: s_lshl_b32 s6, s6, 16 +; GFX9-NEXT: v_or_b32_sdwa v11, v31, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:48 +; GFX9-NEXT: v_mov_b32_e32 v11, s4 +; GFX9-NEXT: s_and_b32 s4, s21, 0xff +; GFX9-NEXT: s_lshl_b32 s6, s75, 8 +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: s_and_b32 s6, s74, 0xff +; GFX9-NEXT: s_lshl_b32 s8, s73, 8 +; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:52 +; GFX9-NEXT: v_lshlrev_b32_e32 v11, 8, v51 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 8, v29 +; GFX9-NEXT: s_or_b32 s6, s6, s8 +; GFX9-NEXT: v_or_b32_sdwa v11, v28, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v17, v49, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: s_and_b32 s4, s4, 0xffff +; GFX9-NEXT: s_lshl_b32 s6, s6, 16 +; GFX9-NEXT: v_or_b32_sdwa v11, v11, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:56 +; GFX9-NEXT: v_mov_b32_e32 v11, s4 +; GFX9-NEXT: s_and_b32 s4, s19, 0xff +; GFX9-NEXT: s_lshl_b32 s6, s72, 8 +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: s_and_b32 s6, s63, 0xff +; GFX9-NEXT: s_lshl_b32 s8, s62, 8 +; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:60 +; GFX9-NEXT: v_lshlrev_b32_e32 v11, 8, v38 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 8, v26 +; GFX9-NEXT: s_or_b32 s6, s6, s8 +; GFX9-NEXT: v_or_b32_sdwa v11, v19, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v17, v36, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: s_and_b32 s4, s4, 0xffff +; GFX9-NEXT: s_lshl_b32 s6, s6, 16 +; GFX9-NEXT: v_or_b32_sdwa v11, v11, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:64 +; GFX9-NEXT: v_mov_b32_e32 v11, s4 +; GFX9-NEXT: s_and_b32 s4, s17, 0xff +; GFX9-NEXT: s_lshl_b32 s6, s61, 8 +; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:68 +; GFX9-NEXT: v_lshlrev_b32_e32 v11, 8, v34 +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: s_and_b32 s6, s60, 0xff +; GFX9-NEXT: s_lshl_b32 s8, s59, 8 +; GFX9-NEXT: v_or_b32_sdwa v11, v15, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b32_e32 v15, 8, v25 +; GFX9-NEXT: s_or_b32 s6, s6, s8 +; GFX9-NEXT: v_or_b32_sdwa v15, v32, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: s_and_b32 s4, s4, 0xffff +; GFX9-NEXT: s_lshl_b32 s6, s6, 16 +; GFX9-NEXT: v_or_b32_sdwa v11, v11, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:72 +; GFX9-NEXT: v_mov_b32_e32 v11, s4 +; GFX9-NEXT: s_and_b32 s4, s15, 0xff +; GFX9-NEXT: s_lshl_b32 s6, s58, 8 +; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:76 +; GFX9-NEXT: v_lshlrev_b32_e32 v11, 8, v30 +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: s_and_b32 s6, s56, 0xff +; GFX9-NEXT: s_lshl_b32 s8, s46, 8 +; GFX9-NEXT: v_or_b32_sdwa v11, v13, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b32_e32 v13, 8, v24 +; GFX9-NEXT: s_or_b32 s6, s6, s8 +; GFX9-NEXT: v_or_b32_sdwa v13, v27, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: s_and_b32 s4, s4, 0xffff +; GFX9-NEXT: s_lshl_b32 s6, s6, 16 +; GFX9-NEXT: v_or_b32_sdwa v11, v11, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:80 +; GFX9-NEXT: v_mov_b32_e32 v11, s4 +; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:84 +; GFX9-NEXT: v_lshlrev_b32_e32 v11, 8, v20 +; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-NEXT: s_and_b32 s4, s13, 0xff +; GFX9-NEXT: s_lshl_b32 s6, s44, 8 +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: s_and_b32 s6, s42, 0xff +; GFX9-NEXT: s_lshl_b32 s8, s40, 8 +; GFX9-NEXT: v_or_b32_sdwa v9, v9, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: s_or_b32 s6, s6, s8 +; GFX9-NEXT: s_and_b32 s4, s4, 0xffff +; GFX9-NEXT: s_lshl_b32 s6, s6, 16 +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: s_lshl_b32 s6, s29, 8 +; GFX9-NEXT: s_lshl_b32 s8, s27, 8 ; GFX9-NEXT: v_readlane_b32 s99, v63, 35 ; GFX9-NEXT: v_readlane_b32 s98, v63, 34 ; GFX9-NEXT: v_readlane_b32 s97, v63, 33 @@ -120178,326 +118201,87 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; GFX9-NEXT: v_readlane_b32 s34, v63, 2 ; GFX9-NEXT: v_readlane_b32 s31, v63, 1 ; GFX9-NEXT: v_readlane_b32 s30, v63, 0 -; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(3) -; GFX9-NEXT: v_lshlrev_b32_e32 v36, 8, v36 -; GFX9-NEXT: v_or_b32_sdwa v27, v27, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b32_e32 v36, 8, v44 -; GFX9-NEXT: v_or_b32_sdwa v28, v28, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_lshlrev_b32_e32 v29, 8, v29 -; GFX9-NEXT: v_or_b32_sdwa v29, v19, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b32_e32 v19, 8, v30 -; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload -; GFX9-NEXT: v_or_b32_sdwa v20, v20, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b32_e32 v19, 8, v51 -; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_lshlrev_b32_e32 v36, 8, v36 -; GFX9-NEXT: v_or_b32_sdwa v23, v23, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v19, v30, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v19, v50, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v19, v0, s[0:3], 0 offen -; GFX9-NEXT: v_lshlrev_b32_e32 v19, 8, v59 -; GFX9-NEXT: v_or_b32_sdwa v19, v60, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v19, v25, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v19, v0, s[0:3], 0 offen offset:4 -; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(2) -; GFX9-NEXT: v_lshlrev_b32_e32 v19, 8, v49 -; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:12 -; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_or_b32_sdwa v19, v25, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v19, v48, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v19, v0, s[0:3], 0 offen offset:8 -; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 8, v48 -; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v17, v19, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v17, v37, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:16 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 8, v47 -; GFX9-NEXT: v_or_b32_sdwa v16, v16, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v16, v18, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:20 -; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(2) -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 8, v16 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v16, v35, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:24 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 8, v42 -; GFX9-NEXT: v_or_b32_sdwa v16, v46, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v16, v21, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:28 -; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(2) -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 8, v16 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v16, v33, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:32 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 8, v39 -; GFX9-NEXT: v_or_b32_sdwa v16, v55, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v16, v34, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:36 -; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(2) -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 8, v16 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v16, v31, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:40 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 8, v26 -; GFX9-NEXT: v_or_b32_sdwa v16, v53, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v16, v32, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:44 -; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(2) -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 8, v18 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v16, v27, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:48 -; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 8, v16 -; GFX9-NEXT: v_or_b32_sdwa v15, v15, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v15, v28, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:52 -; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(2) -; GFX9-NEXT: v_lshlrev_b32_e32 v15, 8, v15 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v15, v23, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:56 -; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_lshlrev_b32_e32 v15, 8, v15 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v15, v24, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:60 -; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(2) -; GFX9-NEXT: v_lshlrev_b32_e32 v15, 8, v15 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v15, v29, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:64 -; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_lshlrev_b32_e32 v15, 8, v15 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v15, v20, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:68 -; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(2) -; GFX9-NEXT: v_lshlrev_b32_e32 v15, 8, v15 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 8, v16 -; GFX9-NEXT: v_or_b32_sdwa v13, v13, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v13, v13, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:72 -; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v13, 8, v13 -; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_lshlrev_b32_e32 v14, 8, v14 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v13, v13, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:76 -; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v13, 8, v13 -; GFX9-NEXT: v_or_b32_sdwa v9, v9, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(2) -; GFX9-NEXT: v_lshlrev_b32_e32 v13, 8, v13 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v9, v9, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:80 -; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v9 -; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload ; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v10 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v10, v13, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:84 -; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v9 +; GFX9-NEXT: v_lshlrev_b32_e32 v11, 8, v19 +; GFX9-NEXT: v_or_b32_sdwa v11, v18, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v9, v9, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:88 +; GFX9-NEXT: v_mov_b32_e32 v9, s4 +; GFX9-NEXT: s_and_b32 s4, s11, 0xff +; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:92 +; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v16 +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: s_and_b32 s6, s28, 0xff ; GFX9-NEXT: v_or_b32_sdwa v7, v7, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(2) -; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v9 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v23 +; GFX9-NEXT: s_or_b32 s6, s6, s8 +; GFX9-NEXT: v_or_b32_sdwa v9, v14, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: s_and_b32 s4, s4, 0xffff +; GFX9-NEXT: s_lshl_b32 s6, s6, 16 ; GFX9-NEXT: v_or_b32_sdwa v7, v7, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:88 -; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v7, 8, v7 -; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_lshlrev_b32_e32 v8, 8, v8 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:92 -; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v7, 8, v7 +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:96 +; GFX9-NEXT: v_mov_b32_e32 v7, s4 +; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:100 +; GFX9-NEXT: v_lshlrev_b32_e32 v7, 8, v12 +; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; GFX9-NEXT: s_and_b32 s4, s9, 0xff +; GFX9-NEXT: s_lshl_b32 s6, s26, 8 +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: s_and_b32 s6, s24, 0xff +; GFX9-NEXT: s_lshl_b32 s8, s22, 8 ; GFX9-NEXT: v_or_b32_sdwa v5, v5, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(2) -; GFX9-NEXT: v_lshlrev_b32_e32 v7, 8, v7 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v5, v5, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:96 -; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5 -; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; GFX9-NEXT: s_or_b32 s6, s6, s8 +; GFX9-NEXT: s_and_b32 s4, s4, 0xffff +; GFX9-NEXT: s_lshl_b32 s6, s6, 16 +; GFX9-NEXT: s_or_b32 s4, s4, s6 +; GFX9-NEXT: s_lshl_b32 s6, s16, 8 ; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_lshlrev_b32_e32 v6, 8, v6 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:100 -; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5 +; GFX9-NEXT: v_lshlrev_b32_e32 v7, 8, v11 +; GFX9-NEXT: v_or_b32_sdwa v7, v10, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v5, v5, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:104 +; GFX9-NEXT: v_mov_b32_e32 v5, s4 +; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:108 +; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v8 +; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-NEXT: s_and_b32 s4, s5, 0xff +; GFX9-NEXT: s_lshl_b32 s5, s20, 8 +; GFX9-NEXT: s_or_b32 s4, s4, s5 +; GFX9-NEXT: s_and_b32 s5, s18, 0xff ; GFX9-NEXT: v_or_b32_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(2) -; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5 -; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_or_b32 s5, s5, s6 +; GFX9-NEXT: s_and_b32 s4, s4, 0xffff +; GFX9-NEXT: s_lshl_b32 s5, s5, 16 +; GFX9-NEXT: s_or_b32 s4, s4, s5 +; GFX9-NEXT: s_lshl_b32 s5, s14, 8 +; GFX9-NEXT: s_lshl_b32 s6, s10, 8 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v7 ; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:104 -; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3 -; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_lshlrev_b32_e32 v4, 8, v4 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:108 -; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3 +; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:112 +; GFX9-NEXT: v_mov_b32_e32 v3, s4 +; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:116 +; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v4 ; GFX9-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(2) -; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:112 -; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GFX9-NEXT: s_and_b32 s4, s7, 0xff +; GFX9-NEXT: s_or_b32 s4, s4, s5 +; GFX9-NEXT: s_and_b32 s5, s12, 0xff +; GFX9-NEXT: s_or_b32 s5, s5, s6 +; GFX9-NEXT: s_and_b32 s4, s4, 0xffff +; GFX9-NEXT: s_lshl_b32 s5, s5, 16 +; GFX9-NEXT: s_or_b32 s4, s4, s5 ; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:116 -; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(3) -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; GFX9-NEXT: s_waitcnt vmcnt(2) -; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; GFX9-NEXT: v_or_b32_sdwa v1, v11, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3 +; GFX9-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120 -; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload -; GFX9-NEXT: s_nop 0 -; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(2) -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; GFX9-NEXT: v_or_b32_sdwa v1, v12, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: v_mov_b32_e32 v1, s4 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124 ; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload @@ -120514,8 +118298,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 -; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] @@ -120525,408 +118309,431 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_or_saveexec_b32 s4, -1 ; GFX11-NEXT: s_clause 0x3 ; 16-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:80 -; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:84 -; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:88 -; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:92 +; GFX11-NEXT: scratch_store_b32 off, v40, s32 +; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:4 +; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:8 +; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:12 ; GFX11-NEXT: s_mov_b32 exec_lo, s4 -; GFX11-NEXT: v_writelane_b32 v76, s30, 0 -; GFX11-NEXT: v_writelane_b32 v77, s96, 0 +; GFX11-NEXT: v_writelane_b32 v40, s30, 0 +; GFX11-NEXT: v_writelane_b32 v41, s96, 0 +; GFX11-NEXT: v_dual_mov_b32 v16, s0 :: v_dual_mov_b32 v17, s1 +; GFX11-NEXT: v_dual_mov_b32 v18, s2 :: v_dual_mov_b32 v19, s3 +; GFX11-NEXT: v_writelane_b32 v40, s31, 1 +; GFX11-NEXT: v_writelane_b32 v41, s97, 1 +; GFX11-NEXT: v_dual_mov_b32 v20, s16 :: v_dual_mov_b32 v21, s17 +; GFX11-NEXT: v_dual_mov_b32 v22, s18 :: v_dual_mov_b32 v23, s19 +; GFX11-NEXT: v_writelane_b32 v40, s34, 2 +; GFX11-NEXT: v_writelane_b32 v41, s98, 2 +; GFX11-NEXT: v_dual_mov_b32 v24, s20 :: v_dual_mov_b32 v25, s21 +; GFX11-NEXT: v_dual_mov_b32 v26, s22 :: v_dual_mov_b32 v27, s23 +; GFX11-NEXT: v_writelane_b32 v40, s35, 3 +; GFX11-NEXT: v_writelane_b32 v41, s99, 3 +; GFX11-NEXT: v_dual_mov_b32 v28, s24 :: v_dual_mov_b32 v29, s25 +; GFX11-NEXT: v_dual_mov_b32 v30, s26 :: v_dual_mov_b32 v31, s27 +; GFX11-NEXT: v_writelane_b32 v40, s36, 4 +; GFX11-NEXT: v_writelane_b32 v41, s100, 4 +; GFX11-NEXT: v_dual_mov_b32 v32, s28 :: v_dual_mov_b32 v33, s29 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 -; GFX11-NEXT: v_readfirstlane_b32 s4, v1 -; GFX11-NEXT: v_readfirstlane_b32 s5, v2 -; GFX11-NEXT: v_writelane_b32 v76, s31, 1 -; GFX11-NEXT: v_writelane_b32 v77, s97, 1 -; GFX11-NEXT: v_readfirstlane_b32 s6, v3 -; GFX11-NEXT: v_readfirstlane_b32 s7, v4 +; GFX11-NEXT: v_writelane_b32 v40, s37, 5 +; GFX11-NEXT: v_writelane_b32 v41, s101, 5 +; GFX11-NEXT: v_readfirstlane_b32 s40, v16 +; GFX11-NEXT: v_readfirstlane_b32 s41, v17 +; GFX11-NEXT: v_readfirstlane_b32 s28, v18 +; GFX11-NEXT: v_writelane_b32 v40, s38, 6 +; GFX11-NEXT: v_writelane_b32 v41, s102, 6 +; GFX11-NEXT: v_readfirstlane_b32 s29, v19 +; GFX11-NEXT: v_readfirstlane_b32 s26, v20 +; GFX11-NEXT: v_readfirstlane_b32 s27, v21 +; GFX11-NEXT: v_writelane_b32 v40, s39, 7 +; GFX11-NEXT: v_writelane_b32 v41, s103, 7 +; GFX11-NEXT: v_readfirstlane_b32 s24, v22 +; GFX11-NEXT: v_readfirstlane_b32 s25, v23 +; GFX11-NEXT: v_readfirstlane_b32 s22, v24 +; GFX11-NEXT: v_writelane_b32 v40, s48, 8 +; GFX11-NEXT: v_readfirstlane_b32 s23, v25 +; GFX11-NEXT: v_readfirstlane_b32 s20, v26 +; GFX11-NEXT: v_readfirstlane_b32 s21, v27 +; GFX11-NEXT: v_readfirstlane_b32 s18, v28 +; GFX11-NEXT: v_writelane_b32 v40, s49, 9 +; GFX11-NEXT: v_readfirstlane_b32 s19, v29 +; GFX11-NEXT: v_readfirstlane_b32 s16, v30 +; GFX11-NEXT: v_readfirstlane_b32 s17, v31 +; GFX11-NEXT: v_readfirstlane_b32 s14, v32 +; GFX11-NEXT: v_writelane_b32 v40, s50, 10 +; GFX11-NEXT: v_readfirstlane_b32 s15, v33 +; GFX11-NEXT: v_readfirstlane_b32 s12, v1 +; GFX11-NEXT: v_readfirstlane_b32 s13, v2 +; GFX11-NEXT: v_readfirstlane_b32 s10, v3 +; GFX11-NEXT: v_writelane_b32 v40, s51, 11 +; GFX11-NEXT: v_readfirstlane_b32 s11, v4 ; GFX11-NEXT: v_readfirstlane_b32 s8, v5 -; GFX11-NEXT: v_writelane_b32 v76, s34, 2 -; GFX11-NEXT: v_writelane_b32 v77, s98, 2 ; GFX11-NEXT: v_readfirstlane_b32 s9, v6 -; GFX11-NEXT: v_readfirstlane_b32 s10, v7 -; GFX11-NEXT: v_readfirstlane_b32 s11, v8 -; GFX11-NEXT: v_writelane_b32 v76, s35, 3 -; GFX11-NEXT: v_writelane_b32 v77, s99, 3 -; GFX11-NEXT: v_readfirstlane_b32 s12, v9 -; GFX11-NEXT: v_readfirstlane_b32 s13, v10 -; GFX11-NEXT: v_readfirstlane_b32 s14, v11 -; GFX11-NEXT: v_writelane_b32 v76, s36, 4 -; GFX11-NEXT: v_writelane_b32 v77, s100, 4 -; GFX11-NEXT: v_readfirstlane_b32 s15, v12 -; GFX11-NEXT: v_readfirstlane_b32 s40, v13 -; GFX11-NEXT: v_readfirstlane_b32 s41, v14 -; GFX11-NEXT: v_writelane_b32 v76, s37, 5 -; GFX11-NEXT: v_writelane_b32 v77, s101, 5 -; GFX11-NEXT: s_mov_b32 vcc_hi, 0 +; GFX11-NEXT: v_readfirstlane_b32 s6, v7 +; GFX11-NEXT: v_writelane_b32 v40, s52, 12 +; GFX11-NEXT: v_readfirstlane_b32 s7, v8 +; GFX11-NEXT: v_readfirstlane_b32 s4, v9 +; GFX11-NEXT: v_readfirstlane_b32 s5, v10 +; GFX11-NEXT: v_readfirstlane_b32 s2, v11 +; GFX11-NEXT: v_writelane_b32 v40, s53, 13 +; GFX11-NEXT: v_readfirstlane_b32 s3, v12 +; GFX11-NEXT: v_readfirstlane_b32 s0, v13 +; GFX11-NEXT: v_readfirstlane_b32 s1, v14 +; GFX11-NEXT: s_mov_b32 s49, 0 +; GFX11-NEXT: v_writelane_b32 v40, s54, 14 ; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo -; GFX11-NEXT: s_clause 0x13 ; 80-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:76 -; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:72 -; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:68 -; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:64 -; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:60 -; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:56 -; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:52 -; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:48 -; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:44 -; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:40 -; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:36 -; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:32 -; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:28 -; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:24 -; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:20 -; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:16 -; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:12 -; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:8 -; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:4 -; GFX11-NEXT: scratch_store_b32 off, v75, s32 -; GFX11-NEXT: v_writelane_b32 v76, s38, 6 -; GFX11-NEXT: v_writelane_b32 v77, s102, 6 -; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane -; GFX11-NEXT: ; implicit-def: $vgpr79 : SGPR spill to VGPR lane -; GFX11-NEXT: v_writelane_b32 v76, s39, 7 -; GFX11-NEXT: v_writelane_b32 v77, s103, 7 -; GFX11-NEXT: v_writelane_b32 v76, s48, 8 -; GFX11-NEXT: v_writelane_b32 v77, s104, 8 -; GFX11-NEXT: v_writelane_b32 v76, s49, 9 -; GFX11-NEXT: v_writelane_b32 v76, s50, 10 -; GFX11-NEXT: v_writelane_b32 v76, s51, 11 -; GFX11-NEXT: v_writelane_b32 v76, s52, 12 -; GFX11-NEXT: v_writelane_b32 v76, s53, 13 -; GFX11-NEXT: v_writelane_b32 v76, s54, 14 -; GFX11-NEXT: v_writelane_b32 v76, s55, 15 -; GFX11-NEXT: v_writelane_b32 v76, s64, 16 -; GFX11-NEXT: v_writelane_b32 v76, s65, 17 -; GFX11-NEXT: v_writelane_b32 v76, s66, 18 -; GFX11-NEXT: v_writelane_b32 v76, s67, 19 -; GFX11-NEXT: v_writelane_b32 v76, s68, 20 -; GFX11-NEXT: v_writelane_b32 v76, s69, 21 -; GFX11-NEXT: v_writelane_b32 v76, s70, 22 -; GFX11-NEXT: v_writelane_b32 v76, s71, 23 -; GFX11-NEXT: v_writelane_b32 v76, s80, 24 -; GFX11-NEXT: v_writelane_b32 v76, s81, 25 -; GFX11-NEXT: v_writelane_b32 v76, s82, 26 -; GFX11-NEXT: v_writelane_b32 v76, s83, 27 -; GFX11-NEXT: v_writelane_b32 v76, s84, 28 -; GFX11-NEXT: v_writelane_b32 v76, s85, 29 -; GFX11-NEXT: v_writelane_b32 v76, s86, 30 -; GFX11-NEXT: v_writelane_b32 v76, s87, 31 +; GFX11-NEXT: v_writelane_b32 v41, s104, 8 +; GFX11-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane +; GFX11-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane +; GFX11-NEXT: v_writelane_b32 v40, s55, 15 +; GFX11-NEXT: v_writelane_b32 v40, s64, 16 +; GFX11-NEXT: v_writelane_b32 v40, s65, 17 +; GFX11-NEXT: v_writelane_b32 v40, s66, 18 +; GFX11-NEXT: v_writelane_b32 v40, s67, 19 +; GFX11-NEXT: v_writelane_b32 v40, s68, 20 +; GFX11-NEXT: v_writelane_b32 v40, s69, 21 +; GFX11-NEXT: v_writelane_b32 v40, s70, 22 +; GFX11-NEXT: v_writelane_b32 v40, s71, 23 +; GFX11-NEXT: v_writelane_b32 v40, s80, 24 +; GFX11-NEXT: v_writelane_b32 v40, s81, 25 +; GFX11-NEXT: v_writelane_b32 v40, s82, 26 +; GFX11-NEXT: v_writelane_b32 v40, s83, 27 +; GFX11-NEXT: v_writelane_b32 v40, s84, 28 +; GFX11-NEXT: v_writelane_b32 v40, s85, 29 +; GFX11-NEXT: v_writelane_b32 v40, s86, 30 +; GFX11-NEXT: v_writelane_b32 v40, s87, 31 ; GFX11-NEXT: s_cbranch_scc0 .LBB73_3 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: s_lshr_b32 s42, s13, 16 -; GFX11-NEXT: s_lshr_b32 s50, s41, 24 -; GFX11-NEXT: v_writelane_b32 v78, s42, 0 -; GFX11-NEXT: s_lshr_b32 s42, s13, 8 -; GFX11-NEXT: s_lshr_b32 s49, s41, 16 +; GFX11-NEXT: s_lshr_b32 s42, s1, 24 +; GFX11-NEXT: s_lshr_b32 s53, s2, 16 +; GFX11-NEXT: v_writelane_b32 v42, s42, 2 +; GFX11-NEXT: s_lshr_b32 s42, s1, 16 +; GFX11-NEXT: s_lshr_b32 s52, s2, 8 +; GFX11-NEXT: s_lshr_b32 s55, s4, 16 +; GFX11-NEXT: s_lshr_b32 s54, s4, 8 +; GFX11-NEXT: v_writelane_b32 v42, s42, 3 +; GFX11-NEXT: s_lshr_b32 s42, s1, 8 +; GFX11-NEXT: s_lshr_b32 s65, s6, 16 +; GFX11-NEXT: s_lshr_b32 s64, s6, 8 +; GFX11-NEXT: s_lshr_b32 s67, s8, 16 +; GFX11-NEXT: v_writelane_b32 v42, s42, 4 +; GFX11-NEXT: s_lshr_b32 s42, s0, 16 +; GFX11-NEXT: s_lshr_b32 s66, s8, 8 +; GFX11-NEXT: s_lshr_b32 s69, s10, 16 +; GFX11-NEXT: s_lshr_b32 s68, s10, 8 +; GFX11-NEXT: v_writelane_b32 v42, s42, 0 +; GFX11-NEXT: s_lshr_b32 s42, s0, 8 +; GFX11-NEXT: s_lshr_b32 s71, s12, 16 +; GFX11-NEXT: s_lshr_b32 s70, s12, 8 +; GFX11-NEXT: s_lshr_b32 s81, s14, 16 +; GFX11-NEXT: v_writelane_b32 v42, s42, 1 +; GFX11-NEXT: s_lshr_b32 s42, s3, 24 +; GFX11-NEXT: s_lshr_b32 s80, s14, 8 +; GFX11-NEXT: s_lshr_b32 s83, s16, 16 +; GFX11-NEXT: s_lshr_b32 s82, s16, 8 +; GFX11-NEXT: v_writelane_b32 v42, s42, 5 +; GFX11-NEXT: s_lshr_b32 s42, s3, 16 +; GFX11-NEXT: s_lshr_b32 s85, s18, 16 +; GFX11-NEXT: s_lshr_b32 s84, s18, 8 +; GFX11-NEXT: s_lshr_b32 s87, s20, 16 +; GFX11-NEXT: v_writelane_b32 v42, s42, 6 +; GFX11-NEXT: s_lshr_b32 s42, s3, 8 +; GFX11-NEXT: s_lshr_b32 s86, s20, 8 +; GFX11-NEXT: s_lshr_b32 s97, s22, 16 +; GFX11-NEXT: s_lshr_b32 s96, s22, 8 +; GFX11-NEXT: v_writelane_b32 v42, s42, 7 +; GFX11-NEXT: s_lshr_b32 s42, s5, 24 +; GFX11-NEXT: s_lshr_b32 s99, s24, 16 +; GFX11-NEXT: s_lshr_b32 s98, s24, 8 +; GFX11-NEXT: s_lshr_b32 s104, s27, 24 +; GFX11-NEXT: v_writelane_b32 v42, s42, 8 +; GFX11-NEXT: s_lshr_b32 s42, s5, 16 +; GFX11-NEXT: s_lshr_b32 vcc_hi, s27, 16 +; GFX11-NEXT: s_lshr_b32 s34, s27, 8 +; GFX11-NEXT: s_lshr_b32 s101, s26, 16 +; GFX11-NEXT: v_writelane_b32 v42, s42, 9 +; GFX11-NEXT: s_lshr_b32 s42, s5, 8 +; GFX11-NEXT: s_lshr_b32 s100, s26, 8 +; GFX11-NEXT: s_lshr_b32 s35, s29, 24 +; GFX11-NEXT: s_lshr_b32 s36, s29, 16 +; GFX11-NEXT: v_writelane_b32 v42, s42, 10 +; GFX11-NEXT: s_lshr_b32 s42, s7, 24 +; GFX11-NEXT: s_lshr_b32 s37, s29, 8 +; GFX11-NEXT: s_lshr_b32 s50, s28, 16 +; GFX11-NEXT: s_lshr_b32 s102, s28, 8 +; GFX11-NEXT: v_writelane_b32 v42, s42, 11 +; GFX11-NEXT: s_lshr_b32 s42, s7, 16 +; GFX11-NEXT: s_lshr_b32 s38, s41, 24 +; GFX11-NEXT: s_lshr_b32 s39, s41, 16 ; GFX11-NEXT: s_lshr_b32 s48, s41, 8 -; GFX11-NEXT: s_lshr_b32 s52, s40, 16 -; GFX11-NEXT: v_writelane_b32 v78, s42, 1 -; GFX11-NEXT: s_lshr_b32 s42, s11, 24 +; GFX11-NEXT: v_writelane_b32 v42, s42, 12 +; GFX11-NEXT: s_lshr_b32 s42, s7, 8 +; GFX11-NEXT: s_lshr_b32 s103, s40, 16 ; GFX11-NEXT: s_lshr_b32 s51, s40, 8 -; GFX11-NEXT: s_lshr_b32 s39, s15, 24 -; GFX11-NEXT: s_lshr_b32 s38, s15, 16 -; GFX11-NEXT: v_writelane_b32 v78, s42, 2 -; GFX11-NEXT: s_lshr_b32 s42, s11, 16 -; GFX11-NEXT: s_lshr_b32 s37, s15, 8 -; GFX11-NEXT: s_lshr_b32 s54, s14, 16 -; GFX11-NEXT: s_lshr_b32 s53, s14, 8 -; GFX11-NEXT: v_writelane_b32 v78, s42, 3 -; GFX11-NEXT: s_lshr_b32 s42, s11, 8 -; GFX11-NEXT: s_lshr_b32 s36, s13, 24 -; GFX11-NEXT: s_lshr_b32 s64, s12, 16 -; GFX11-NEXT: s_lshr_b32 s55, s12, 8 -; GFX11-NEXT: v_writelane_b32 v78, s42, 4 +; GFX11-NEXT: s_lshr_b64 s[62:63], s[0:1], 24 +; GFX11-NEXT: v_writelane_b32 v42, s42, 13 ; GFX11-NEXT: s_lshr_b32 s42, s9, 24 -; GFX11-NEXT: s_lshr_b32 s66, s10, 16 -; GFX11-NEXT: s_lshr_b32 s65, s10, 8 -; GFX11-NEXT: s_lshr_b32 s68, s8, 16 -; GFX11-NEXT: v_writelane_b32 v78, s42, 5 +; GFX11-NEXT: s_lshr_b64 s[72:73], s[2:3], 24 +; GFX11-NEXT: s_lshr_b64 s[74:75], s[4:5], 24 +; GFX11-NEXT: s_lshr_b64 s[76:77], s[6:7], 24 +; GFX11-NEXT: v_writelane_b32 v42, s42, 14 ; GFX11-NEXT: s_lshr_b32 s42, s9, 16 -; GFX11-NEXT: s_lshr_b32 s67, s8, 8 -; GFX11-NEXT: s_lshr_b32 s70, s6, 16 -; GFX11-NEXT: s_lshr_b32 s69, s6, 8 -; GFX11-NEXT: v_writelane_b32 v78, s42, 6 -; GFX11-NEXT: s_lshr_b32 s42, s9, 8 -; GFX11-NEXT: s_lshr_b32 s80, s4, 16 -; GFX11-NEXT: s_lshr_b32 s71, s4, 8 -; GFX11-NEXT: s_lshr_b32 s82, s28, 16 -; GFX11-NEXT: v_writelane_b32 v78, s42, 7 -; GFX11-NEXT: s_lshr_b32 s42, s7, 24 -; GFX11-NEXT: s_lshr_b32 s81, s28, 8 -; GFX11-NEXT: s_lshr_b32 s84, s26, 16 -; GFX11-NEXT: s_lshr_b32 s83, s26, 8 -; GFX11-NEXT: v_writelane_b32 v78, s42, 8 -; GFX11-NEXT: s_lshr_b32 s42, s7, 16 -; GFX11-NEXT: s_lshr_b32 s86, s24, 16 -; GFX11-NEXT: s_lshr_b32 s85, s24, 8 -; GFX11-NEXT: s_lshr_b32 s96, s22, 16 -; GFX11-NEXT: v_writelane_b32 v78, s42, 9 -; GFX11-NEXT: s_lshr_b32 s42, s7, 8 -; GFX11-NEXT: s_lshr_b32 s87, s22, 8 -; GFX11-NEXT: s_lshr_b32 s98, s20, 16 -; GFX11-NEXT: s_lshr_b32 s97, s20, 8 -; GFX11-NEXT: v_writelane_b32 v78, s42, 10 -; GFX11-NEXT: s_lshr_b32 s42, s5, 24 -; GFX11-NEXT: s_lshr_b32 s100, s18, 16 -; GFX11-NEXT: s_lshr_b32 s99, s18, 8 -; GFX11-NEXT: s_lshr_b32 s102, s16, 16 -; GFX11-NEXT: v_writelane_b32 v78, s42, 11 -; GFX11-NEXT: s_lshr_b32 s42, s5, 16 -; GFX11-NEXT: s_lshr_b32 s101, s16, 8 -; GFX11-NEXT: s_lshr_b32 s104, s2, 16 -; GFX11-NEXT: s_lshr_b32 s103, s2, 8 -; GFX11-NEXT: v_writelane_b32 v78, s42, 12 -; GFX11-NEXT: s_lshr_b32 s42, s5, 8 -; GFX11-NEXT: s_lshr_b32 s35, s0, 16 -; GFX11-NEXT: s_lshr_b32 s34, s0, 8 -; GFX11-NEXT: s_lshr_b64 s[62:63], s[40:41], 24 -; GFX11-NEXT: v_writelane_b32 v78, s42, 13 -; GFX11-NEXT: s_lshr_b32 s42, s29, 24 -; GFX11-NEXT: s_lshr_b64 s[72:73], s[14:15], 24 -; GFX11-NEXT: s_lshr_b64 s[74:75], s[12:13], 24 -; GFX11-NEXT: s_lshr_b64 s[76:77], s[10:11], 24 -; GFX11-NEXT: v_writelane_b32 v78, s42, 14 -; GFX11-NEXT: s_lshr_b32 s42, s29, 16 ; GFX11-NEXT: s_lshr_b64 s[78:79], s[8:9], 24 -; GFX11-NEXT: s_lshr_b64 s[88:89], s[6:7], 24 -; GFX11-NEXT: s_lshr_b64 s[90:91], s[4:5], 24 -; GFX11-NEXT: v_writelane_b32 v78, s42, 15 -; GFX11-NEXT: s_lshr_b32 s42, s29, 8 -; GFX11-NEXT: s_lshr_b64 s[92:93], s[28:29], 24 -; GFX11-NEXT: s_lshr_b64 s[94:95], s[26:27], 24 -; GFX11-NEXT: s_lshr_b64 s[30:31], s[24:25], 24 -; GFX11-NEXT: v_writelane_b32 v78, s42, 16 -; GFX11-NEXT: s_lshr_b32 s42, s27, 24 -; GFX11-NEXT: s_lshr_b64 s[60:61], s[22:23], 24 -; GFX11-NEXT: s_lshr_b64 s[58:59], s[20:21], 24 -; GFX11-NEXT: s_lshr_b64 s[56:57], s[18:19], 24 -; GFX11-NEXT: v_writelane_b32 v78, s42, 17 -; GFX11-NEXT: s_lshr_b32 s42, s27, 16 -; GFX11-NEXT: s_lshr_b64 s[46:47], s[16:17], 24 -; GFX11-NEXT: s_lshr_b64 s[44:45], s[2:3], 24 -; GFX11-NEXT: v_writelane_b32 v78, s42, 18 -; GFX11-NEXT: s_lshr_b32 s42, s27, 8 +; GFX11-NEXT: s_lshr_b64 s[88:89], s[10:11], 24 +; GFX11-NEXT: s_lshr_b64 s[90:91], s[12:13], 24 +; GFX11-NEXT: v_writelane_b32 v42, s42, 15 +; GFX11-NEXT: s_lshr_b32 s42, s9, 8 +; GFX11-NEXT: s_lshr_b64 s[92:93], s[14:15], 24 +; GFX11-NEXT: s_lshr_b64 s[94:95], s[16:17], 24 +; GFX11-NEXT: s_lshr_b64 s[30:31], s[18:19], 24 +; GFX11-NEXT: v_writelane_b32 v42, s42, 16 +; GFX11-NEXT: s_lshr_b32 s42, s11, 24 +; GFX11-NEXT: s_lshr_b64 s[60:61], s[20:21], 24 +; GFX11-NEXT: s_lshr_b64 s[58:59], s[22:23], 24 +; GFX11-NEXT: s_lshr_b64 s[56:57], s[24:25], 24 +; GFX11-NEXT: v_writelane_b32 v42, s42, 17 +; GFX11-NEXT: s_lshr_b32 s42, s11, 16 +; GFX11-NEXT: s_lshr_b64 s[46:47], s[26:27], 24 +; GFX11-NEXT: s_lshr_b64 s[44:45], s[28:29], 24 +; GFX11-NEXT: v_writelane_b32 v42, s42, 18 +; GFX11-NEXT: s_lshr_b32 s42, s11, 8 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_writelane_b32 v78, s42, 19 -; GFX11-NEXT: s_lshr_b32 s42, s25, 24 -; GFX11-NEXT: v_writelane_b32 v78, s42, 20 -; GFX11-NEXT: s_lshr_b32 s42, s25, 16 +; GFX11-NEXT: v_writelane_b32 v42, s42, 19 +; GFX11-NEXT: s_lshr_b32 s42, s13, 24 +; GFX11-NEXT: v_writelane_b32 v42, s42, 20 +; GFX11-NEXT: s_lshr_b32 s42, s13, 16 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_writelane_b32 v78, s42, 21 -; GFX11-NEXT: s_lshr_b32 s42, s25, 8 -; GFX11-NEXT: v_writelane_b32 v78, s42, 22 -; GFX11-NEXT: s_lshr_b32 s42, s23, 24 +; GFX11-NEXT: v_writelane_b32 v42, s42, 21 +; GFX11-NEXT: s_lshr_b32 s42, s13, 8 +; GFX11-NEXT: v_writelane_b32 v42, s42, 22 +; GFX11-NEXT: s_lshr_b32 s42, s15, 24 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_writelane_b32 v78, s42, 23 -; GFX11-NEXT: s_lshr_b32 s42, s23, 16 -; GFX11-NEXT: v_writelane_b32 v78, s42, 24 -; GFX11-NEXT: s_lshr_b32 s42, s23, 8 +; GFX11-NEXT: v_writelane_b32 v42, s42, 23 +; GFX11-NEXT: s_lshr_b32 s42, s15, 16 +; GFX11-NEXT: v_writelane_b32 v42, s42, 24 +; GFX11-NEXT: s_lshr_b32 s42, s15, 8 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_writelane_b32 v78, s42, 25 -; GFX11-NEXT: s_lshr_b32 s42, s21, 24 -; GFX11-NEXT: v_writelane_b32 v78, s42, 26 -; GFX11-NEXT: s_lshr_b32 s42, s21, 16 +; GFX11-NEXT: v_writelane_b32 v42, s42, 25 +; GFX11-NEXT: s_lshr_b32 s42, s17, 24 +; GFX11-NEXT: v_writelane_b32 v42, s42, 26 +; GFX11-NEXT: s_lshr_b32 s42, s17, 16 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_writelane_b32 v78, s42, 27 -; GFX11-NEXT: s_lshr_b32 s42, s21, 8 -; GFX11-NEXT: v_writelane_b32 v78, s42, 28 +; GFX11-NEXT: v_writelane_b32 v42, s42, 27 +; GFX11-NEXT: s_lshr_b32 s42, s17, 8 +; GFX11-NEXT: v_writelane_b32 v42, s42, 28 ; GFX11-NEXT: s_lshr_b32 s42, s19, 24 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_writelane_b32 v78, s42, 29 +; GFX11-NEXT: v_writelane_b32 v42, s42, 29 ; GFX11-NEXT: s_lshr_b32 s42, s19, 16 -; GFX11-NEXT: v_writelane_b32 v78, s42, 30 +; GFX11-NEXT: v_writelane_b32 v42, s42, 30 ; GFX11-NEXT: s_lshr_b32 s42, s19, 8 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_writelane_b32 v78, s42, 31 -; GFX11-NEXT: s_lshr_b32 s42, s17, 24 -; GFX11-NEXT: v_writelane_b32 v79, s42, 0 -; GFX11-NEXT: s_lshr_b32 s42, s17, 16 +; GFX11-NEXT: v_writelane_b32 v42, s42, 31 +; GFX11-NEXT: s_lshr_b32 s42, s21, 24 +; GFX11-NEXT: v_writelane_b32 v43, s42, 0 +; GFX11-NEXT: s_lshr_b32 s42, s21, 16 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_writelane_b32 v79, s42, 1 -; GFX11-NEXT: s_lshr_b32 s42, s17, 8 -; GFX11-NEXT: v_writelane_b32 v79, s42, 2 -; GFX11-NEXT: s_lshr_b32 s42, s3, 24 +; GFX11-NEXT: v_writelane_b32 v43, s42, 1 +; GFX11-NEXT: s_lshr_b32 s42, s21, 8 +; GFX11-NEXT: v_writelane_b32 v43, s42, 2 +; GFX11-NEXT: s_lshr_b32 s42, s23, 24 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_writelane_b32 v79, s42, 3 -; GFX11-NEXT: s_lshr_b32 s42, s3, 16 -; GFX11-NEXT: v_writelane_b32 v79, s42, 4 -; GFX11-NEXT: s_lshr_b32 s42, s3, 8 +; GFX11-NEXT: v_writelane_b32 v43, s42, 3 +; GFX11-NEXT: s_lshr_b32 s42, s23, 16 +; GFX11-NEXT: v_writelane_b32 v43, s42, 4 +; GFX11-NEXT: s_lshr_b32 s42, s23, 8 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_writelane_b32 v79, s42, 5 -; GFX11-NEXT: s_lshr_b32 s42, s1, 24 -; GFX11-NEXT: v_writelane_b32 v79, s42, 6 -; GFX11-NEXT: s_lshr_b32 s42, s1, 16 +; GFX11-NEXT: v_writelane_b32 v43, s42, 5 +; GFX11-NEXT: s_lshr_b32 s42, s25, 24 +; GFX11-NEXT: v_writelane_b32 v43, s42, 6 +; GFX11-NEXT: s_lshr_b32 s42, s25, 16 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_writelane_b32 v79, s42, 7 -; GFX11-NEXT: s_lshr_b32 s42, s1, 8 -; GFX11-NEXT: v_writelane_b32 v79, s42, 8 -; GFX11-NEXT: s_lshr_b64 s[42:43], s[0:1], 24 -; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, vcc_hi +; GFX11-NEXT: v_writelane_b32 v43, s42, 7 +; GFX11-NEXT: s_lshr_b32 s42, s25, 8 +; GFX11-NEXT: v_writelane_b32 v43, s42, 8 +; GFX11-NEXT: s_lshr_b64 s[42:43], s[40:41], 24 +; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s49 ; GFX11-NEXT: s_cbranch_vccnz .LBB73_4 ; GFX11-NEXT: .LBB73_2: ; %cmp.true -; GFX11-NEXT: v_add_f64 v[23:24], s[24:25], 1.0 -; GFX11-NEXT: v_add_f64 v[28:29], s[22:23], 1.0 -; GFX11-NEXT: v_add_f64 v[32:33], s[20:21], 1.0 -; GFX11-NEXT: v_add_f64 v[5:6], s[12:13], 1.0 -; GFX11-NEXT: v_add_f64 v[36:37], s[18:19], 1.0 -; GFX11-NEXT: v_add_f64 v[52:53], s[2:3], 1.0 -; GFX11-NEXT: v_add_f64 v[1:2], s[40:41], 1.0 -; GFX11-NEXT: v_add_f64 v[3:4], s[14:15], 1.0 -; GFX11-NEXT: v_add_f64 v[7:8], s[10:11], 1.0 -; GFX11-NEXT: v_add_f64 v[9:10], s[8:9], 1.0 +; GFX11-NEXT: v_add_f64 v[50:51], s[24:25], 1.0 +; GFX11-NEXT: v_add_f64 v[52:53], s[26:27], 1.0 +; GFX11-NEXT: v_add_f64 v[68:69], s[40:41], 1.0 +; GFX11-NEXT: v_add_f64 v[64:65], s[28:29], 1.0 +; GFX11-NEXT: v_add_f64 v[48:49], s[22:23], 1.0 +; GFX11-NEXT: v_add_f64 v[35:36], s[20:21], 1.0 +; GFX11-NEXT: v_add_f64 v[31:32], s[18:19], 1.0 +; GFX11-NEXT: v_add_f64 v[29:30], s[16:17], 1.0 +; GFX11-NEXT: v_add_f64 v[25:26], s[14:15], 1.0 +; GFX11-NEXT: v_add_f64 v[21:22], s[12:13], 1.0 +; GFX11-NEXT: v_add_f64 v[17:18], s[10:11], 1.0 +; GFX11-NEXT: v_add_f64 v[13:14], s[8:9], 1.0 ; GFX11-NEXT: v_add_f64 v[11:12], s[6:7], 1.0 -; GFX11-NEXT: v_add_f64 v[13:14], s[4:5], 1.0 -; GFX11-NEXT: v_add_f64 v[15:16], s[28:29], 1.0 -; GFX11-NEXT: v_add_f64 v[19:20], s[26:27], 1.0 -; GFX11-NEXT: v_add_f64 v[48:49], s[16:17], 1.0 -; GFX11-NEXT: v_add_f64 v[64:65], s[0:1], 1.0 -; GFX11-NEXT: v_lshrrev_b64 v[66:67], 24, v[23:24] -; GFX11-NEXT: v_lshrrev_b64 v[67:68], 24, v[28:29] -; GFX11-NEXT: v_lshrrev_b64 v[68:69], 24, v[32:33] -; GFX11-NEXT: v_lshrrev_b64 v[25:26], 24, v[5:6] -; GFX11-NEXT: v_lshrrev_b64 v[69:70], 24, v[36:37] -; GFX11-NEXT: v_lshrrev_b64 v[80:81], 24, v[52:53] -; GFX11-NEXT: v_lshrrev_b64 v[17:18], 24, v[1:2] -; GFX11-NEXT: v_lshrrev_b64 v[21:22], 24, v[3:4] -; GFX11-NEXT: v_lshrrev_b64 v[26:27], 24, v[7:8] -; GFX11-NEXT: v_lshrrev_b64 v[30:31], 24, v[9:10] -; GFX11-NEXT: v_lshrrev_b64 v[34:35], 24, v[11:12] -; GFX11-NEXT: v_lshrrev_b64 v[38:39], 24, v[13:14] -; GFX11-NEXT: v_lshrrev_b64 v[50:51], 24, v[15:16] -; GFX11-NEXT: v_lshrrev_b64 v[54:55], 24, v[19:20] +; GFX11-NEXT: v_add_f64 v[7:8], s[4:5], 1.0 +; GFX11-NEXT: v_add_f64 v[3:4], s[2:3], 1.0 +; GFX11-NEXT: v_add_f64 v[1:2], s[0:1], 1.0 +; GFX11-NEXT: v_lshrrev_b64 v[80:81], 24, v[50:51] +; GFX11-NEXT: v_lshrrev_b64 v[81:82], 24, v[52:53] +; GFX11-NEXT: v_readfirstlane_b32 s41, v69 +; GFX11-NEXT: v_readfirstlane_b32 s29, v65 +; GFX11-NEXT: v_readfirstlane_b32 s27, v53 +; GFX11-NEXT: v_readfirstlane_b32 s25, v51 +; GFX11-NEXT: v_readfirstlane_b32 s23, v49 +; GFX11-NEXT: v_readfirstlane_b32 s21, v36 +; GFX11-NEXT: v_readfirstlane_b32 s19, v32 +; GFX11-NEXT: v_readfirstlane_b32 s17, v30 +; GFX11-NEXT: v_readfirstlane_b32 s15, v26 +; GFX11-NEXT: v_readfirstlane_b32 s13, v22 +; GFX11-NEXT: v_readfirstlane_b32 s11, v18 +; GFX11-NEXT: v_readfirstlane_b32 s9, v14 +; GFX11-NEXT: v_readfirstlane_b32 s7, v12 +; GFX11-NEXT: v_readfirstlane_b32 s5, v8 +; GFX11-NEXT: v_readfirstlane_b32 s3, v4 +; GFX11-NEXT: v_readfirstlane_b32 s1, v2 +; GFX11-NEXT: v_lshrrev_b64 v[37:38], 24, v[25:26] +; GFX11-NEXT: v_lshrrev_b64 v[82:83], 24, v[64:65] +; GFX11-NEXT: v_lshrrev_b64 v[5:6], 24, v[1:2] +; GFX11-NEXT: v_lshrrev_b64 v[9:10], 24, v[3:4] +; GFX11-NEXT: v_lshrrev_b64 v[15:16], 24, v[7:8] +; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12] +; GFX11-NEXT: v_lshrrev_b64 v[23:24], 24, v[13:14] +; GFX11-NEXT: v_lshrrev_b64 v[27:28], 24, v[17:18] +; GFX11-NEXT: v_lshrrev_b64 v[33:34], 24, v[21:22] +; GFX11-NEXT: v_lshrrev_b64 v[38:39], 24, v[29:30] +; GFX11-NEXT: v_lshrrev_b64 v[54:55], 24, v[31:32] +; GFX11-NEXT: v_lshrrev_b64 v[66:67], 24, v[35:36] ; GFX11-NEXT: v_lshrrev_b64 v[70:71], 24, v[48:49] -; GFX11-NEXT: v_lshrrev_b64 v[81:82], 24, v[64:65] -; GFX11-NEXT: v_lshrrev_b32_e32 v22, 24, v2 -; GFX11-NEXT: v_lshrrev_b32_e32 v31, 16, v2 -; GFX11-NEXT: v_lshrrev_b32_e32 v35, 8, v2 -; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v1 -; GFX11-NEXT: v_lshrrev_b32_e32 v27, 8, v1 -; GFX11-NEXT: v_lshrrev_b32_e32 v51, 24, v4 -; GFX11-NEXT: v_lshrrev_b32_e32 v71, 16, v4 -; GFX11-NEXT: v_lshrrev_b32_e32 v83, 8, v4 -; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v3 -; GFX11-NEXT: v_lshrrev_b32_e32 v55, 8, v3 -; GFX11-NEXT: v_lshrrev_b32_e32 v85, 24, v6 -; GFX11-NEXT: v_lshrrev_b32_e32 v87, 16, v6 -; GFX11-NEXT: v_lshrrev_b32_e32 v96, 8, v6 -; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v5 -; GFX11-NEXT: v_lshrrev_b32_e32 v86, 8, v5 -; GFX11-NEXT: v_lshrrev_b32_e32 v99, 24, v8 -; GFX11-NEXT: v_lshrrev_b32_e32 v100, 16, v8 -; GFX11-NEXT: v_lshrrev_b32_e32 v101, 8, v8 -; GFX11-NEXT: v_lshrrev_b32_e32 v97, 16, v7 -; GFX11-NEXT: v_lshrrev_b32_e32 v98, 8, v7 -; GFX11-NEXT: v_lshrrev_b32_e32 v112, 24, v10 -; GFX11-NEXT: v_lshrrev_b32_e32 v114, 16, v10 -; GFX11-NEXT: v_lshrrev_b32_e32 v116, 8, v10 -; GFX11-NEXT: v_lshrrev_b32_e32 v102, 16, v9 -; GFX11-NEXT: v_lshrrev_b32_e32 v103, 8, v9 -; GFX11-NEXT: v_lshrrev_b32_e32 v119, 24, v12 -; GFX11-NEXT: v_lshrrev_b32_e32 v128, 16, v12 -; GFX11-NEXT: v_lshrrev_b32_e32 v129, 8, v12 -; GFX11-NEXT: v_lshrrev_b32_e32 v113, 16, v11 -; GFX11-NEXT: v_lshrrev_b32_e32 v115, 8, v11 -; GFX11-NEXT: v_lshrrev_b32_e32 v132, 24, v14 -; GFX11-NEXT: v_lshrrev_b32_e32 v133, 16, v14 -; GFX11-NEXT: v_lshrrev_b32_e32 v134, 8, v14 -; GFX11-NEXT: v_lshrrev_b32_e32 v117, 16, v13 -; GFX11-NEXT: v_lshrrev_b32_e32 v118, 8, v13 -; GFX11-NEXT: v_lshrrev_b32_e32 v145, 24, v16 -; GFX11-NEXT: v_lshrrev_b32_e32 v146, 16, v16 -; GFX11-NEXT: v_lshrrev_b32_e32 v147, 8, v16 -; GFX11-NEXT: v_lshrrev_b32_e32 v130, 16, v15 -; GFX11-NEXT: v_lshrrev_b32_e32 v131, 8, v15 -; GFX11-NEXT: v_lshrrev_b32_e32 v150, 24, v20 -; GFX11-NEXT: v_lshrrev_b32_e32 v151, 16, v20 -; GFX11-NEXT: v_lshrrev_b32_e32 v162, 8, v20 -; GFX11-NEXT: v_lshrrev_b32_e32 v135, 16, v19 -; GFX11-NEXT: v_lshrrev_b32_e32 v144, 8, v19 -; GFX11-NEXT: v_lshrrev_b32_e32 v164, 24, v24 -; GFX11-NEXT: v_lshrrev_b32_e32 v166, 16, v24 -; GFX11-NEXT: v_lshrrev_b32_e32 v167, 8, v24 -; GFX11-NEXT: v_lshrrev_b32_e32 v148, 16, v23 -; GFX11-NEXT: v_lshrrev_b32_e32 v149, 8, v23 -; GFX11-NEXT: v_lshrrev_b32_e32 v178, 24, v29 -; GFX11-NEXT: v_lshrrev_b32_e32 v179, 16, v29 -; GFX11-NEXT: v_lshrrev_b32_e32 v180, 8, v29 -; GFX11-NEXT: v_lshrrev_b32_e32 v160, 16, v28 -; GFX11-NEXT: v_lshrrev_b32_e32 v161, 8, v28 -; GFX11-NEXT: v_lshrrev_b32_e32 v183, 24, v33 -; GFX11-NEXT: v_lshrrev_b32_e32 v40, 16, v33 -; GFX11-NEXT: v_lshrrev_b32_e32 v42, 8, v33 -; GFX11-NEXT: v_lshrrev_b32_e32 v163, 16, v32 -; GFX11-NEXT: v_lshrrev_b32_e32 v165, 8, v32 -; GFX11-NEXT: v_lshrrev_b32_e32 v45, 24, v37 -; GFX11-NEXT: v_lshrrev_b32_e32 v47, 16, v37 -; GFX11-NEXT: v_lshrrev_b32_e32 v56, 8, v37 -; GFX11-NEXT: v_lshrrev_b32_e32 v176, 16, v36 -; GFX11-NEXT: v_lshrrev_b32_e32 v177, 8, v36 -; GFX11-NEXT: v_lshrrev_b32_e32 v57, 24, v49 -; GFX11-NEXT: v_lshrrev_b32_e32 v58, 16, v49 -; GFX11-NEXT: v_lshrrev_b32_e32 v59, 8, v49 -; GFX11-NEXT: v_lshrrev_b32_e32 v181, 16, v48 -; GFX11-NEXT: v_lshrrev_b32_e32 v182, 8, v48 -; GFX11-NEXT: v_lshrrev_b32_e32 v60, 24, v53 -; GFX11-NEXT: v_lshrrev_b32_e32 v61, 16, v53 -; GFX11-NEXT: v_lshrrev_b32_e32 v62, 8, v53 -; GFX11-NEXT: v_lshrrev_b32_e32 v41, 16, v52 -; GFX11-NEXT: v_lshrrev_b32_e32 v43, 8, v52 -; GFX11-NEXT: v_lshrrev_b32_e32 v63, 24, v65 -; GFX11-NEXT: v_lshrrev_b32_e32 v72, 16, v65 -; GFX11-NEXT: v_lshrrev_b32_e32 v73, 8, v65 -; GFX11-NEXT: v_lshrrev_b32_e32 v44, 16, v64 -; GFX11-NEXT: v_lshrrev_b32_e32 v46, 8, v64 +; GFX11-NEXT: v_lshrrev_b64 v[83:84], 24, v[68:69] +; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; GFX11-NEXT: v_lshrrev_b32_e32 v4, 8, v1 +; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v3 +; GFX11-NEXT: v_lshrrev_b32_e32 v8, 8, v3 +; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v7 +; GFX11-NEXT: v_lshrrev_b32_e32 v12, 8, v7 +; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v11 +; GFX11-NEXT: v_lshrrev_b32_e32 v16, 8, v11 +; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v13 +; GFX11-NEXT: v_lshrrev_b32_e32 v20, 8, v13 +; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v17 +; GFX11-NEXT: v_lshrrev_b32_e32 v24, 8, v17 +; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v21 +; GFX11-NEXT: v_lshrrev_b32_e32 v28, 8, v21 +; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v25 +; GFX11-NEXT: v_lshrrev_b32_e32 v32, 8, v25 +; GFX11-NEXT: v_lshrrev_b32_e32 v34, 16, v29 +; GFX11-NEXT: v_lshrrev_b32_e32 v36, 8, v29 +; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v31 +; GFX11-NEXT: v_lshrrev_b32_e32 v49, 8, v31 +; GFX11-NEXT: v_lshrrev_b32_e32 v51, 16, v35 +; GFX11-NEXT: v_lshrrev_b32_e32 v53, 8, v35 +; GFX11-NEXT: v_lshrrev_b32_e32 v55, 16, v48 +; GFX11-NEXT: v_lshrrev_b32_e32 v67, 8, v48 +; GFX11-NEXT: v_lshrrev_b32_e32 v71, 16, v50 +; GFX11-NEXT: v_lshrrev_b32_e32 v85, 8, v50 +; GFX11-NEXT: v_lshrrev_b32_e32 v86, 16, v52 +; GFX11-NEXT: v_lshrrev_b32_e32 v87, 8, v52 +; GFX11-NEXT: v_lshrrev_b32_e32 v96, 16, v64 +; GFX11-NEXT: v_lshrrev_b32_e32 v97, 8, v64 +; GFX11-NEXT: v_lshrrev_b32_e32 v98, 16, v68 +; GFX11-NEXT: v_lshrrev_b32_e32 v99, 8, v68 +; GFX11-NEXT: s_lshr_b32 s8, s1, 24 +; GFX11-NEXT: s_lshr_b32 s10, s1, 16 +; GFX11-NEXT: s_lshr_b32 s12, s1, 8 +; GFX11-NEXT: s_lshr_b32 s14, s3, 24 +; GFX11-NEXT: s_lshr_b32 s16, s3, 16 +; GFX11-NEXT: s_lshr_b32 s18, s3, 8 +; GFX11-NEXT: s_lshr_b32 s20, s5, 24 +; GFX11-NEXT: s_lshr_b32 s22, s5, 16 +; GFX11-NEXT: s_lshr_b32 s24, s5, 8 +; GFX11-NEXT: s_lshr_b32 s26, s7, 24 +; GFX11-NEXT: s_lshr_b32 s28, s7, 16 +; GFX11-NEXT: s_lshr_b32 s40, s7, 8 +; GFX11-NEXT: s_lshr_b32 s42, s9, 24 +; GFX11-NEXT: s_lshr_b32 s43, s9, 16 +; GFX11-NEXT: s_lshr_b32 s44, s9, 8 +; GFX11-NEXT: s_lshr_b32 s45, s11, 24 +; GFX11-NEXT: s_lshr_b32 s46, s11, 16 +; GFX11-NEXT: s_lshr_b32 s47, s11, 8 +; GFX11-NEXT: s_lshr_b32 s56, s13, 24 +; GFX11-NEXT: s_lshr_b32 s57, s13, 16 +; GFX11-NEXT: s_lshr_b32 s58, s13, 8 +; GFX11-NEXT: s_lshr_b32 s59, s15, 24 +; GFX11-NEXT: s_lshr_b32 s60, s15, 16 +; GFX11-NEXT: s_lshr_b32 s61, s15, 8 +; GFX11-NEXT: s_lshr_b32 s62, s17, 24 +; GFX11-NEXT: s_lshr_b32 s63, s17, 16 +; GFX11-NEXT: s_lshr_b32 s72, s17, 8 +; GFX11-NEXT: s_lshr_b32 s73, s19, 24 +; GFX11-NEXT: s_lshr_b32 s74, s19, 16 +; GFX11-NEXT: s_lshr_b32 s75, s19, 8 +; GFX11-NEXT: s_lshr_b32 s76, s21, 24 +; GFX11-NEXT: s_lshr_b32 s77, s21, 16 +; GFX11-NEXT: s_lshr_b32 s78, s21, 8 +; GFX11-NEXT: s_lshr_b32 s79, s23, 24 +; GFX11-NEXT: s_lshr_b32 s88, s23, 16 +; GFX11-NEXT: s_lshr_b32 s89, s23, 8 +; GFX11-NEXT: s_lshr_b32 s90, s25, 24 +; GFX11-NEXT: s_lshr_b32 s91, s25, 16 +; GFX11-NEXT: s_lshr_b32 s92, s25, 8 +; GFX11-NEXT: s_lshr_b32 s104, s27, 24 +; GFX11-NEXT: s_lshr_b32 vcc_hi, s27, 16 +; GFX11-NEXT: s_lshr_b32 s34, s27, 8 +; GFX11-NEXT: s_lshr_b32 s35, s29, 24 +; GFX11-NEXT: s_lshr_b32 s36, s29, 16 +; GFX11-NEXT: s_lshr_b32 s37, s29, 8 +; GFX11-NEXT: s_lshr_b32 s38, s41, 24 +; GFX11-NEXT: s_lshr_b32 s39, s41, 16 +; GFX11-NEXT: s_lshr_b32 s48, s41, 8 ; GFX11-NEXT: s_branch .LBB73_5 ; GFX11-NEXT: .LBB73_3: ; GFX11-NEXT: ; implicit-def: $sgpr43 ; GFX11-NEXT: ; kill: killed $sgpr43 +; GFX11-NEXT: s_mov_b32 s49, -1 ; GFX11-NEXT: ; implicit-def: $sgpr43 ; GFX11-NEXT: ; kill: killed $sgpr43 -; GFX11-NEXT: ; implicit-def: $sgpr34 -; GFX11-NEXT: ; implicit-def: $sgpr35 -; GFX11-NEXT: ; implicit-def: $sgpr42 +; GFX11-NEXT: ; implicit-def: $sgpr51 ; GFX11-NEXT: ; implicit-def: $sgpr103 -; GFX11-NEXT: ; implicit-def: $sgpr104 +; GFX11-NEXT: ; implicit-def: $sgpr42 +; GFX11-NEXT: ; implicit-def: $sgpr48 +; GFX11-NEXT: ; implicit-def: $sgpr39 +; GFX11-NEXT: ; implicit-def: $sgpr38 +; GFX11-NEXT: ; implicit-def: $sgpr102 +; GFX11-NEXT: ; implicit-def: $sgpr50 ; GFX11-NEXT: ; implicit-def: $sgpr44 +; GFX11-NEXT: ; implicit-def: $sgpr37 +; GFX11-NEXT: ; implicit-def: $sgpr36 +; GFX11-NEXT: ; implicit-def: $sgpr35 +; GFX11-NEXT: ; implicit-def: $sgpr100 ; GFX11-NEXT: ; implicit-def: $sgpr101 -; GFX11-NEXT: ; implicit-def: $sgpr102 ; GFX11-NEXT: ; implicit-def: $sgpr46 +; GFX11-NEXT: ; implicit-def: $sgpr34 +; GFX11-NEXT: ; implicit-def: $vcc_hi +; GFX11-NEXT: ; implicit-def: $sgpr104 +; GFX11-NEXT: ; implicit-def: $sgpr98 ; GFX11-NEXT: ; implicit-def: $sgpr99 -; GFX11-NEXT: ; implicit-def: $sgpr100 ; GFX11-NEXT: ; implicit-def: $sgpr56 +; GFX11-NEXT: ; implicit-def: $sgpr96 ; GFX11-NEXT: ; implicit-def: $sgpr97 -; GFX11-NEXT: ; implicit-def: $sgpr98 ; GFX11-NEXT: ; implicit-def: $sgpr58 +; GFX11-NEXT: ; implicit-def: $sgpr86 ; GFX11-NEXT: ; implicit-def: $sgpr87 -; GFX11-NEXT: ; implicit-def: $sgpr96 ; GFX11-NEXT: ; implicit-def: $sgpr60 -; GFX11-NEXT: ; implicit-def: $sgpr85 -; GFX11-NEXT: ; implicit-def: $sgpr86 -; GFX11-NEXT: ; implicit-def: $sgpr83 ; GFX11-NEXT: ; implicit-def: $sgpr84 -; GFX11-NEXT: ; implicit-def: $sgpr81 +; GFX11-NEXT: ; implicit-def: $sgpr85 ; GFX11-NEXT: ; implicit-def: $sgpr82 -; GFX11-NEXT: ; implicit-def: $sgpr71 +; GFX11-NEXT: ; implicit-def: $sgpr83 ; GFX11-NEXT: ; implicit-def: $sgpr80 -; GFX11-NEXT: ; implicit-def: $sgpr69 +; GFX11-NEXT: ; implicit-def: $sgpr81 ; GFX11-NEXT: ; implicit-def: $sgpr70 -; GFX11-NEXT: ; implicit-def: $sgpr67 +; GFX11-NEXT: ; implicit-def: $sgpr71 ; GFX11-NEXT: ; implicit-def: $sgpr68 -; GFX11-NEXT: ; implicit-def: $sgpr65 +; GFX11-NEXT: ; implicit-def: $sgpr69 ; GFX11-NEXT: ; implicit-def: $sgpr66 -; GFX11-NEXT: ; implicit-def: $sgpr55 +; GFX11-NEXT: ; implicit-def: $sgpr67 ; GFX11-NEXT: ; implicit-def: $sgpr64 -; GFX11-NEXT: ; implicit-def: $sgpr36 -; GFX11-NEXT: ; implicit-def: $sgpr53 +; GFX11-NEXT: ; implicit-def: $sgpr65 ; GFX11-NEXT: ; implicit-def: $sgpr54 -; GFX11-NEXT: ; implicit-def: $sgpr37 -; GFX11-NEXT: ; implicit-def: $sgpr38 -; GFX11-NEXT: ; implicit-def: $sgpr39 -; GFX11-NEXT: ; implicit-def: $sgpr51 +; GFX11-NEXT: ; implicit-def: $sgpr55 ; GFX11-NEXT: ; implicit-def: $sgpr52 -; GFX11-NEXT: ; implicit-def: $sgpr48 -; GFX11-NEXT: ; implicit-def: $sgpr49 -; GFX11-NEXT: ; implicit-def: $sgpr50 +; GFX11-NEXT: ; implicit-def: $sgpr53 ; GFX11-NEXT: ; implicit-def: $sgpr30 ; GFX11-NEXT: ; implicit-def: $sgpr94 ; GFX11-NEXT: ; implicit-def: $sgpr92 @@ -121017,524 +118824,441 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a, ; GFX11-NEXT: ; kill: killed $sgpr43 ; GFX11-NEXT: s_branch .LBB73_2 ; GFX11-NEXT: .LBB73_4: -; GFX11-NEXT: v_dual_mov_b32 v64, s0 :: v_dual_mov_b32 v65, s1 -; GFX11-NEXT: v_readlane_b32 s0, v78, 0 -; GFX11-NEXT: v_dual_mov_b32 v1, s40 :: v_dual_mov_b32 v2, s41 -; GFX11-NEXT: v_dual_mov_b32 v3, s14 :: v_dual_mov_b32 v4, s15 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_mov_b32_e32 v87, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 1 -; GFX11-NEXT: v_mov_b32_e32 v39, s54 -; GFX11-NEXT: v_dual_mov_b32 v5, s12 :: v_dual_mov_b32 v6, s13 -; GFX11-NEXT: v_dual_mov_b32 v7, s10 :: v_dual_mov_b32 v8, s11 -; GFX11-NEXT: v_mov_b32_e32 v96, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 2 -; GFX11-NEXT: v_dual_mov_b32 v9, s8 :: v_dual_mov_b32 v10, s9 -; GFX11-NEXT: v_dual_mov_b32 v11, s6 :: v_dual_mov_b32 v12, s7 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_mov_b32_e32 v99, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 3 -; GFX11-NEXT: v_mov_b32_e32 v55, s53 -; GFX11-NEXT: v_dual_mov_b32 v13, s4 :: v_dual_mov_b32 v14, s5 -; GFX11-NEXT: v_dual_mov_b32 v15, s28 :: v_dual_mov_b32 v16, s29 -; GFX11-NEXT: v_mov_b32_e32 v100, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 4 -; GFX11-NEXT: v_dual_mov_b32 v19, s26 :: v_dual_mov_b32 v20, s27 -; GFX11-NEXT: v_dual_mov_b32 v23, s24 :: v_dual_mov_b32 v24, s25 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_mov_b32_e32 v101, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 5 -; GFX11-NEXT: v_dual_mov_b32 v27, s51 :: v_dual_mov_b32 v28, s22 -; GFX11-NEXT: v_dual_mov_b32 v29, s23 :: v_dual_mov_b32 v32, s20 -; GFX11-NEXT: v_dual_mov_b32 v33, s21 :: v_dual_mov_b32 v112, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 6 -; GFX11-NEXT: v_dual_mov_b32 v31, s49 :: v_dual_mov_b32 v36, s18 -; GFX11-NEXT: v_dual_mov_b32 v37, s19 :: v_dual_mov_b32 v48, s16 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_dual_mov_b32 v49, s17 :: v_dual_mov_b32 v114, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 7 -; GFX11-NEXT: v_dual_mov_b32 v35, s48 :: v_dual_mov_b32 v52, s2 -; GFX11-NEXT: v_dual_mov_b32 v53, s3 :: v_dual_mov_b32 v44, s35 -; GFX11-NEXT: v_dual_mov_b32 v41, s104 :: v_dual_mov_b32 v116, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 8 -; GFX11-NEXT: v_dual_mov_b32 v46, s34 :: v_dual_mov_b32 v43, s103 -; GFX11-NEXT: v_dual_mov_b32 v181, s102 :: v_dual_mov_b32 v182, s101 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_mov_b32_e32 v119, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 9 -; GFX11-NEXT: v_dual_mov_b32 v51, s39 :: v_dual_mov_b32 v176, s100 -; GFX11-NEXT: v_mov_b32_e32 v177, s99 -; GFX11-NEXT: v_dual_mov_b32 v163, s98 :: v_dual_mov_b32 v160, s96 -; GFX11-NEXT: v_mov_b32_e32 v128, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 10 -; GFX11-NEXT: v_dual_mov_b32 v165, s97 :: v_dual_mov_b32 v148, s86 -; GFX11-NEXT: v_dual_mov_b32 v161, s87 :: v_dual_mov_b32 v144, s83 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_mov_b32_e32 v129, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 11 -; GFX11-NEXT: v_mov_b32_e32 v71, s38 -; GFX11-NEXT: v_dual_mov_b32 v149, s85 :: v_dual_mov_b32 v130, s82 -; GFX11-NEXT: v_dual_mov_b32 v135, s84 :: v_dual_mov_b32 v118, s71 -; GFX11-NEXT: v_mov_b32_e32 v132, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 12 -; GFX11-NEXT: v_dual_mov_b32 v131, s81 :: v_dual_mov_b32 v102, s68 -; GFX11-NEXT: v_dual_mov_b32 v117, s80 :: v_dual_mov_b32 v98, s65 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_mov_b32_e32 v133, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 13 -; GFX11-NEXT: v_mov_b32_e32 v83, s37 -; GFX11-NEXT: v_dual_mov_b32 v113, s70 :: v_dual_mov_b32 v84, s64 -; GFX11-NEXT: v_dual_mov_b32 v115, s69 :: v_dual_mov_b32 v86, s55 -; GFX11-NEXT: v_mov_b32_e32 v134, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 14 -; GFX11-NEXT: v_dual_mov_b32 v103, s67 :: v_dual_mov_b32 v18, s52 -; GFX11-NEXT: v_dual_mov_b32 v97, s66 :: v_dual_mov_b32 v22, s50 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_mov_b32_e32 v145, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 15 -; GFX11-NEXT: v_mov_b32_e32 v85, s36 -; GFX11-NEXT: v_dual_mov_b32 v81, s42 :: v_dual_mov_b32 v38, s90 -; GFX11-NEXT: v_dual_mov_b32 v69, s56 :: v_dual_mov_b32 v34, s88 -; GFX11-NEXT: v_mov_b32_e32 v146, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 16 -; GFX11-NEXT: v_dual_mov_b32 v67, s60 :: v_dual_mov_b32 v30, s78 -; GFX11-NEXT: v_dual_mov_b32 v26, s76 :: v_dual_mov_b32 v25, s74 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_mov_b32_e32 v147, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 17 -; GFX11-NEXT: v_mov_b32_e32 v21, s72 -; GFX11-NEXT: v_dual_mov_b32 v17, s62 :: v_dual_mov_b32 v80, s44 -; GFX11-NEXT: v_mov_b32_e32 v70, s46 -; GFX11-NEXT: v_mov_b32_e32 v150, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 18 -; GFX11-NEXT: v_mov_b32_e32 v68, s58 -; GFX11-NEXT: v_mov_b32_e32 v66, s30 -; GFX11-NEXT: v_mov_b32_e32 v54, s94 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_dual_mov_b32 v50, s92 :: v_dual_mov_b32 v151, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 19 -; GFX11-NEXT: v_mov_b32_e32 v162, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 20 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_mov_b32_e32 v164, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 21 -; GFX11-NEXT: v_mov_b32_e32 v166, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 22 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_mov_b32_e32 v167, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 23 -; GFX11-NEXT: v_mov_b32_e32 v178, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 24 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_mov_b32_e32 v179, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 25 -; GFX11-NEXT: v_mov_b32_e32 v180, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 26 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_mov_b32_e32 v183, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 27 -; GFX11-NEXT: v_mov_b32_e32 v40, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 28 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_mov_b32_e32 v42, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 29 -; GFX11-NEXT: v_mov_b32_e32 v45, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 30 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_mov_b32_e32 v47, s0 -; GFX11-NEXT: v_readlane_b32 s0, v78, 31 -; GFX11-NEXT: v_mov_b32_e32 v56, s0 -; GFX11-NEXT: v_readlane_b32 s0, v79, 0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_mov_b32_e32 v57, s0 -; GFX11-NEXT: v_readlane_b32 s0, v79, 1 -; GFX11-NEXT: v_mov_b32_e32 v58, s0 -; GFX11-NEXT: v_readlane_b32 s0, v79, 2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_mov_b32_e32 v59, s0 -; GFX11-NEXT: v_readlane_b32 s0, v79, 3 -; GFX11-NEXT: v_mov_b32_e32 v60, s0 -; GFX11-NEXT: v_readlane_b32 s0, v79, 4 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_mov_b32_e32 v61, s0 -; GFX11-NEXT: v_readlane_b32 s0, v79, 5 -; GFX11-NEXT: v_mov_b32_e32 v62, s0 -; GFX11-NEXT: v_readlane_b32 s0, v79, 6 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_mov_b32_e32 v63, s0 -; GFX11-NEXT: v_readlane_b32 s0, v79, 7 -; GFX11-NEXT: v_mov_b32_e32 v72, s0 -; GFX11-NEXT: v_readlane_b32 s0, v79, 8 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_mov_b32_e32 v73, s0 +; GFX11-NEXT: v_readlane_b32 s43, v42, 0 +; GFX11-NEXT: v_dual_mov_b32 v98, s103 :: v_dual_mov_b32 v99, s51 +; GFX11-NEXT: v_dual_mov_b32 v96, s50 :: v_dual_mov_b32 v97, s102 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-NEXT: v_dual_mov_b32 v2, s43 :: v_dual_mov_b32 v7, s4 +; GFX11-NEXT: v_readlane_b32 s43, v42, 1 +; GFX11-NEXT: v_dual_mov_b32 v86, s101 :: v_dual_mov_b32 v87, s100 +; GFX11-NEXT: v_dual_mov_b32 v71, s99 :: v_dual_mov_b32 v34, s83 +; GFX11-NEXT: v_dual_mov_b32 v85, s98 :: v_dual_mov_b32 v36, s82 +; GFX11-NEXT: v_dual_mov_b32 v55, s97 :: v_dual_mov_b32 v30, s81 +; GFX11-NEXT: v_dual_mov_b32 v67, s96 :: v_dual_mov_b32 v32, s80 +; GFX11-NEXT: v_dual_mov_b32 v51, s87 :: v_dual_mov_b32 v26, s71 +; GFX11-NEXT: v_dual_mov_b32 v53, s86 :: v_dual_mov_b32 v28, s70 +; GFX11-NEXT: v_dual_mov_b32 v39, s85 :: v_dual_mov_b32 v22, s69 +; GFX11-NEXT: v_dual_mov_b32 v49, s84 :: v_dual_mov_b32 v24, s68 +; GFX11-NEXT: v_dual_mov_b32 v18, s67 :: v_dual_mov_b32 v35, s20 +; GFX11-NEXT: v_dual_mov_b32 v20, s66 :: v_dual_mov_b32 v31, s18 +; GFX11-NEXT: v_dual_mov_b32 v14, s65 :: v_dual_mov_b32 v29, s16 +; GFX11-NEXT: v_dual_mov_b32 v16, s64 :: v_dual_mov_b32 v25, s14 +; GFX11-NEXT: v_dual_mov_b32 v10, s55 :: v_dual_mov_b32 v21, s12 +; GFX11-NEXT: v_dual_mov_b32 v12, s54 :: v_dual_mov_b32 v17, s10 +; GFX11-NEXT: v_dual_mov_b32 v6, s53 :: v_dual_mov_b32 v13, s8 +; GFX11-NEXT: v_dual_mov_b32 v8, s52 :: v_dual_mov_b32 v11, s6 +; GFX11-NEXT: v_dual_mov_b32 v4, s43 :: v_dual_mov_b32 v3, s2 +; GFX11-NEXT: v_dual_mov_b32 v68, s40 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v64, s28 :: v_dual_mov_b32 v83, s42 +; GFX11-NEXT: v_dual_mov_b32 v52, s26 :: v_dual_mov_b32 v81, s46 +; GFX11-NEXT: v_dual_mov_b32 v50, s24 :: v_dual_mov_b32 v37, s92 +; GFX11-NEXT: v_dual_mov_b32 v48, s22 :: v_dual_mov_b32 v33, s90 +; GFX11-NEXT: v_dual_mov_b32 v82, s44 :: v_dual_mov_b32 v27, s88 +; GFX11-NEXT: v_dual_mov_b32 v80, s56 :: v_dual_mov_b32 v23, s78 +; GFX11-NEXT: v_dual_mov_b32 v70, s58 :: v_dual_mov_b32 v19, s76 +; GFX11-NEXT: v_dual_mov_b32 v66, s60 :: v_dual_mov_b32 v15, s74 +; GFX11-NEXT: v_dual_mov_b32 v54, s30 :: v_dual_mov_b32 v9, s72 +; GFX11-NEXT: v_dual_mov_b32 v38, s94 :: v_dual_mov_b32 v5, s62 +; GFX11-NEXT: v_readlane_b32 s8, v42, 2 +; GFX11-NEXT: v_readlane_b32 s10, v42, 3 +; GFX11-NEXT: v_readlane_b32 s12, v42, 4 +; GFX11-NEXT: v_readlane_b32 s14, v42, 5 +; GFX11-NEXT: v_readlane_b32 s16, v42, 6 +; GFX11-NEXT: v_readlane_b32 s18, v42, 7 +; GFX11-NEXT: v_readlane_b32 s20, v42, 8 +; GFX11-NEXT: v_readlane_b32 s22, v42, 9 +; GFX11-NEXT: v_readlane_b32 s24, v42, 10 +; GFX11-NEXT: v_readlane_b32 s26, v42, 11 +; GFX11-NEXT: v_readlane_b32 s28, v42, 12 +; GFX11-NEXT: v_readlane_b32 s40, v42, 13 +; GFX11-NEXT: v_readlane_b32 s42, v42, 14 +; GFX11-NEXT: v_readlane_b32 s43, v42, 15 +; GFX11-NEXT: v_readlane_b32 s44, v42, 16 +; GFX11-NEXT: v_readlane_b32 s45, v42, 17 +; GFX11-NEXT: v_readlane_b32 s46, v42, 18 +; GFX11-NEXT: v_readlane_b32 s47, v42, 19 +; GFX11-NEXT: v_readlane_b32 s56, v42, 20 +; GFX11-NEXT: v_readlane_b32 s57, v42, 21 +; GFX11-NEXT: v_readlane_b32 s58, v42, 22 +; GFX11-NEXT: v_readlane_b32 s59, v42, 23 +; GFX11-NEXT: v_readlane_b32 s60, v42, 24 +; GFX11-NEXT: v_readlane_b32 s61, v42, 25 +; GFX11-NEXT: v_readlane_b32 s62, v42, 26 +; GFX11-NEXT: v_readlane_b32 s63, v42, 27 +; GFX11-NEXT: v_readlane_b32 s72, v42, 28 +; GFX11-NEXT: v_readlane_b32 s73, v42, 29 +; GFX11-NEXT: v_readlane_b32 s74, v42, 30 +; GFX11-NEXT: v_readlane_b32 s75, v42, 31 +; GFX11-NEXT: v_readlane_b32 s76, v43, 0 +; GFX11-NEXT: v_readlane_b32 s77, v43, 1 +; GFX11-NEXT: v_readlane_b32 s78, v43, 2 +; GFX11-NEXT: v_readlane_b32 s79, v43, 3 +; GFX11-NEXT: v_readlane_b32 s88, v43, 4 +; GFX11-NEXT: v_readlane_b32 s89, v43, 5 +; GFX11-NEXT: v_readlane_b32 s90, v43, 6 +; GFX11-NEXT: v_readlane_b32 s91, v43, 7 +; GFX11-NEXT: v_readlane_b32 s92, v43, 8 ; GFX11-NEXT: .LBB73_5: ; %end -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_lshlrev_b32_e32 v82, 8, v46 -; GFX11-NEXT: v_and_b32_e32 v64, 0xff, v64 -; GFX11-NEXT: v_lshlrev_b32_e32 v81, 8, v81 -; GFX11-NEXT: v_and_b32_e32 v65, 0xff, v65 -; GFX11-NEXT: v_lshlrev_b32_e32 v80, 8, v80 -; GFX11-NEXT: v_and_b32_e32 v52, 0xff, v52 -; GFX11-NEXT: v_or_b32_e32 v64, v64, v82 -; GFX11-NEXT: v_and_b32_e32 v82, 0xff, v44 -; GFX11-NEXT: v_lshlrev_b32_e32 v44, 8, v63 -; GFX11-NEXT: v_lshlrev_b32_e32 v43, 8, v43 -; GFX11-NEXT: v_and_b32_e32 v41, 0xff, v41 +; GFX11-NEXT: s_and_b32 s0, s41, 0xff +; GFX11-NEXT: s_lshl_b32 s2, s48, 8 +; GFX11-NEXT: s_lshl_b32 s4, s38, 8 +; GFX11-NEXT: s_or_b32 s0, s0, s2 +; GFX11-NEXT: s_and_b32 s2, s39, 0xff +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: v_and_b32_e32 v65, 0xff, v68 +; GFX11-NEXT: s_lshl_b32 s2, s2, 16 +; GFX11-NEXT: v_lshlrev_b32_e32 v69, 8, v99 +; GFX11-NEXT: s_or_b32 s0, s0, s2 +; GFX11-NEXT: s_and_b32 s2, s29, 0xff +; GFX11-NEXT: s_lshl_b32 s4, s37, 8 +; GFX11-NEXT: s_lshl_b32 s6, s35, 8 +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: s_and_b32 s4, s36, 0xff +; GFX11-NEXT: v_lshlrev_b32_e32 v68, 8, v83 +; GFX11-NEXT: s_or_b32 s4, s4, s6 +; GFX11-NEXT: v_or_b32_e32 v65, v65, v69 +; GFX11-NEXT: v_and_b32_e32 v69, 0xff, v98 +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_lshl_b32 s4, s4, 16 +; GFX11-NEXT: s_lshl_b32 s6, s90, 8 +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: v_or_b32_e32 v68, v69, v68 +; GFX11-NEXT: v_dual_mov_b32 v99, s2 :: v_dual_and_b32 v64, 0xff, v64 +; GFX11-NEXT: v_lshlrev_b32_e32 v69, 8, v97 +; GFX11-NEXT: v_mov_b32_e32 v97, s0 +; GFX11-NEXT: s_and_b32 s0, s27, 0xff +; GFX11-NEXT: s_lshl_b32 s2, s34, 8 +; GFX11-NEXT: s_lshl_b32 s4, s104, 8 +; GFX11-NEXT: s_or_b32 s0, s0, s2 +; GFX11-NEXT: s_and_b32 s2, vcc_hi, 0xff +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: s_lshl_b32 s4, s92, 8 +; GFX11-NEXT: s_lshl_b32 s2, s2, 16 +; GFX11-NEXT: v_and_b32_e32 v65, 0xffff, v65 +; GFX11-NEXT: s_or_b32 s0, s0, s2 +; GFX11-NEXT: s_and_b32 s2, s25, 0xff +; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v68 +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: s_and_b32 s4, s91, 0xff +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_or_b32 s4, s4, s6 +; GFX11-NEXT: v_and_b32_e32 v83, 0xff, v96 +; GFX11-NEXT: s_lshl_b32 s4, s4, 16 +; GFX11-NEXT: v_or_b32_e32 v64, v64, v69 +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: v_lshlrev_b32_e32 v82, 8, v82 +; GFX11-NEXT: v_or_b32_e32 v96, v65, v68 +; GFX11-NEXT: v_dual_mov_b32 v81, s0 :: v_dual_lshlrev_b32 v68, 8, v81 +; GFX11-NEXT: s_and_b32 s0, s23, 0xff +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-NEXT: v_or_b32_e32 v69, v83, v82 +; GFX11-NEXT: v_mov_b32_e32 v83, s2 +; GFX11-NEXT: s_lshl_b32 s2, s89, 8 +; GFX11-NEXT: s_lshl_b32 s4, s79, 8 +; GFX11-NEXT: s_or_b32 s0, s0, s2 +; GFX11-NEXT: s_and_b32 s2, s88, 0xff +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: s_and_b32 s4, s21, 0xff +; GFX11-NEXT: s_lshl_b32 s2, s2, 16 +; GFX11-NEXT: s_lshl_b32 s6, s78, 8 +; GFX11-NEXT: s_or_b32 s0, s0, s2 +; GFX11-NEXT: s_or_b32 s2, s4, s6 +; GFX11-NEXT: s_and_b32 s4, s77, 0xff +; GFX11-NEXT: s_lshl_b32 s6, s76, 8 ; GFX11-NEXT: v_and_b32_e32 v64, 0xffff, v64 -; GFX11-NEXT: v_or_b32_e32 v81, v82, v81 -; GFX11-NEXT: v_lshlrev_b32_e32 v82, 8, v73 -; GFX11-NEXT: v_or_b32_e32 v52, v52, v43 -; GFX11-NEXT: v_or_b32_e32 v80, v41, v80 -; GFX11-NEXT: v_and_b32_e32 v53, 0xff, v53 -; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v81 -; GFX11-NEXT: v_or_b32_e32 v65, v65, v82 -; GFX11-NEXT: v_and_b32_e32 v82, 0xff, v72 -; GFX11-NEXT: v_lshlrev_b32_e32 v41, 8, v60 -; GFX11-NEXT: v_and_b32_e32 v52, 0xffff, v52 -; GFX11-NEXT: v_or_b32_e32 v72, v64, v81 -; GFX11-NEXT: v_and_b32_e32 v64, 0xffff, v65 -; GFX11-NEXT: v_or_b32_e32 v82, v82, v44 -; GFX11-NEXT: v_lshlrev_b32_e32 v81, 8, v62 +; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v69 +; GFX11-NEXT: s_or_b32 s4, s4, s6 +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_lshl_b32 s4, s4, 16 +; GFX11-NEXT: v_and_b32_e32 v65, 0xff, v86 +; GFX11-NEXT: v_or_b32_e32 v98, v64, v69 +; GFX11-NEXT: v_lshlrev_b32_e32 v64, 8, v87 +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: v_and_b32_e32 v52, 0xff, v52 +; GFX11-NEXT: v_and_b32_e32 v50, 0xff, v50 +; GFX11-NEXT: v_lshlrev_b32_e32 v69, 8, v80 ; GFX11-NEXT: v_and_b32_e32 v48, 0xff, v48 -; GFX11-NEXT: v_lshlrev_b32_e32 v70, 8, v70 -; GFX11-NEXT: v_and_b32_e32 v49, 0xff, v49 -; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v82 -; GFX11-NEXT: v_and_b32_e32 v82, 0xff, v61 -; GFX11-NEXT: v_or_b32_e32 v53, v53, v81 -; GFX11-NEXT: v_and_b32_e32 v81, 0xff, v181 -; GFX11-NEXT: v_and_b32_e32 v36, 0xff, v36 -; GFX11-NEXT: v_or_b32_e32 v73, v64, v65 -; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v80 -; GFX11-NEXT: v_or_b32_e32 v65, v82, v41 -; GFX11-NEXT: v_lshlrev_b32_e32 v80, 8, v182 -; GFX11-NEXT: v_lshlrev_b32_e32 v69, 8, v69 -; GFX11-NEXT: v_and_b32_e32 v37, 0xff, v37 -; GFX11-NEXT: v_or_b32_e32 v74, v52, v64 -; GFX11-NEXT: v_and_b32_e32 v52, 0xffff, v53 -; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v65 -; GFX11-NEXT: v_or_b32_e32 v48, v48, v80 -; GFX11-NEXT: v_or_b32_e32 v64, v81, v70 -; GFX11-NEXT: v_lshlrev_b32_e32 v65, 8, v59 -; GFX11-NEXT: v_and_b32_e32 v70, 0xff, v58 -; GFX11-NEXT: v_lshlrev_b32_e32 v80, 8, v57 -; GFX11-NEXT: v_or_b32_e32 v75, v52, v53 -; GFX11-NEXT: v_and_b32_e32 v48, 0xffff, v48 -; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v64 -; GFX11-NEXT: v_or_b32_e32 v49, v49, v65 -; GFX11-NEXT: v_or_b32_e32 v53, v70, v80 -; GFX11-NEXT: v_lshlrev_b32_e32 v64, 8, v177 -; GFX11-NEXT: v_and_b32_e32 v65, 0xff, v176 -; GFX11-NEXT: v_or_b32_e32 v43, v48, v52 -; GFX11-NEXT: v_and_b32_e32 v48, 0xffff, v49 -; GFX11-NEXT: v_lshlrev_b32_e32 v49, 16, v53 -; GFX11-NEXT: v_or_b32_e32 v36, v36, v64 -; GFX11-NEXT: v_or_b32_e32 v52, v65, v69 -; GFX11-NEXT: v_lshlrev_b32_e32 v53, 8, v56 -; GFX11-NEXT: v_and_b32_e32 v64, 0xff, v47 -; GFX11-NEXT: v_lshlrev_b32_e32 v65, 8, v45 -; GFX11-NEXT: v_or_b32_e32 v44, v48, v49 -; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v52 -; GFX11-NEXT: v_or_b32_e32 v37, v37, v53 -; GFX11-NEXT: v_and_b32_e32 v32, 0xff, v32 -; GFX11-NEXT: v_or_b32_e32 v49, v64, v65 -; GFX11-NEXT: v_lshlrev_b32_e32 v52, 8, v165 -; GFX11-NEXT: v_and_b32_e32 v53, 0xff, v163 -; GFX11-NEXT: v_lshlrev_b32_e32 v64, 8, v68 -; GFX11-NEXT: v_and_b32_e32 v36, 0xffff, v36 -; GFX11-NEXT: v_and_b32_e32 v33, 0xff, v33 -; GFX11-NEXT: v_lshlrev_b32_e32 v65, 8, v42 -; GFX11-NEXT: v_and_b32_e32 v37, 0xffff, v37 -; GFX11-NEXT: v_lshlrev_b32_e32 v49, 16, v49 -; GFX11-NEXT: v_or_b32_e32 v32, v32, v52 -; GFX11-NEXT: v_or_b32_e32 v52, v53, v64 -; GFX11-NEXT: v_or_b32_e32 v33, v33, v65 -; GFX11-NEXT: v_or_b32_e32 v45, v36, v48 -; GFX11-NEXT: v_or_b32_e32 v46, v37, v49 -; GFX11-NEXT: v_and_b32_e32 v37, 0xff, v40 -; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v52 -; GFX11-NEXT: v_lshlrev_b32_e32 v48, 8, v183 -; GFX11-NEXT: v_and_b32_e32 v28, 0xff, v28 -; GFX11-NEXT: v_lshlrev_b32_e32 v49, 8, v161 -; GFX11-NEXT: v_and_b32_e32 v52, 0xff, v160 -; GFX11-NEXT: v_lshlrev_b32_e32 v53, 8, v67 +; GFX11-NEXT: v_and_b32_e32 v35, 0xff, v35 +; GFX11-NEXT: v_or_b32_e32 v52, v52, v64 +; GFX11-NEXT: v_or_b32_e32 v64, v65, v68 +; GFX11-NEXT: v_lshlrev_b32_e32 v65, 8, v85 +; GFX11-NEXT: v_and_b32_e32 v68, 0xff, v71 +; GFX11-NEXT: v_and_b32_e32 v51, 0xff, v51 +; GFX11-NEXT: v_and_b32_e32 v52, 0xffff, v52 +; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v64 +; GFX11-NEXT: v_or_b32_e32 v50, v50, v65 +; GFX11-NEXT: v_or_b32_e32 v65, v68, v69 +; GFX11-NEXT: v_and_b32_e32 v31, 0xff, v31 +; GFX11-NEXT: v_and_b32_e32 v39, 0xff, v39 +; GFX11-NEXT: v_or_b32_e32 v80, v52, v64 +; GFX11-NEXT: v_and_b32_e32 v50, 0xffff, v50 +; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v65 +; GFX11-NEXT: v_and_b32_e32 v52, 0xff, v55 +; GFX11-NEXT: v_lshlrev_b32_e32 v55, 8, v70 ; GFX11-NEXT: v_and_b32_e32 v29, 0xff, v29 -; GFX11-NEXT: v_lshlrev_b32_e32 v64, 8, v180 -; GFX11-NEXT: v_and_b32_e32 v65, 0xff, v179 -; GFX11-NEXT: v_lshlrev_b32_e32 v67, 8, v178 -; GFX11-NEXT: v_or_b32_e32 v37, v37, v48 -; GFX11-NEXT: v_or_b32_e32 v28, v28, v49 -; GFX11-NEXT: v_or_b32_e32 v48, v52, v53 -; GFX11-NEXT: v_or_b32_e32 v29, v29, v64 -; GFX11-NEXT: v_or_b32_e32 v49, v65, v67 -; GFX11-NEXT: v_and_b32_e32 v32, 0xffff, v32 -; GFX11-NEXT: v_and_b32_e32 v33, 0xffff, v33 -; GFX11-NEXT: v_lshlrev_b32_e32 v37, 16, v37 -; GFX11-NEXT: v_and_b32_e32 v28, 0xffff, v28 -; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v48 -; GFX11-NEXT: v_and_b32_e32 v29, 0xffff, v29 -; GFX11-NEXT: v_lshlrev_b32_e32 v49, 16, v49 -; GFX11-NEXT: v_or_b32_e32 v67, v32, v36 -; GFX11-NEXT: v_or_b32_e32 v68, v33, v37 -; GFX11-NEXT: v_or_b32_e32 v69, v28, v48 -; GFX11-NEXT: v_and_b32_e32 v23, 0xff, v23 -; GFX11-NEXT: v_or_b32_e32 v70, v29, v49 -; GFX11-NEXT: v_lshlrev_b32_e32 v28, 8, v149 -; GFX11-NEXT: v_and_b32_e32 v29, 0xff, v148 -; GFX11-NEXT: v_lshlrev_b32_e32 v32, 8, v66 -; GFX11-NEXT: v_and_b32_e32 v24, 0xff, v24 -; GFX11-NEXT: v_lshlrev_b32_e32 v33, 8, v167 -; GFX11-NEXT: v_and_b32_e32 v36, 0xff, v166 -; GFX11-NEXT: v_lshlrev_b32_e32 v37, 8, v164 -; GFX11-NEXT: v_and_b32_e32 v19, 0xff, v19 -; GFX11-NEXT: v_lshlrev_b32_e32 v48, 8, v144 -; GFX11-NEXT: v_or_b32_e32 v23, v23, v28 -; GFX11-NEXT: v_or_b32_e32 v28, v29, v32 -; GFX11-NEXT: v_or_b32_e32 v24, v24, v33 -; GFX11-NEXT: v_or_b32_e32 v29, v36, v37 -; GFX11-NEXT: v_or_b32_e32 v19, v19, v48 -; GFX11-NEXT: v_and_b32_e32 v32, 0xff, v135 -; GFX11-NEXT: v_lshlrev_b32_e32 v33, 8, v54 -; GFX11-NEXT: v_and_b32_e32 v20, 0xff, v20 -; GFX11-NEXT: v_lshlrev_b32_e32 v36, 8, v162 -; GFX11-NEXT: v_and_b32_e32 v37, 0xff, v151 -; GFX11-NEXT: v_lshlrev_b32_e32 v48, 8, v150 -; GFX11-NEXT: v_and_b32_e32 v15, 0xff, v15 -; GFX11-NEXT: v_lshlrev_b32_e32 v49, 8, v131 -; GFX11-NEXT: v_and_b32_e32 v52, 0xff, v130 -; GFX11-NEXT: v_lshlrev_b32_e32 v50, 8, v50 -; GFX11-NEXT: v_or_b32_e32 v32, v32, v33 -; GFX11-NEXT: v_or_b32_e32 v20, v20, v36 -; GFX11-NEXT: v_or_b32_e32 v33, v37, v48 -; GFX11-NEXT: v_or_b32_e32 v15, v15, v49 -; GFX11-NEXT: v_or_b32_e32 v36, v52, v50 -; GFX11-NEXT: v_and_b32_e32 v23, 0xffff, v23 -; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v28 -; GFX11-NEXT: v_and_b32_e32 v19, 0xffff, v19 -; GFX11-NEXT: v_lshlrev_b32_e32 v32, 16, v32 -; GFX11-NEXT: v_and_b32_e32 v20, 0xffff, v20 -; GFX11-NEXT: v_lshlrev_b32_e32 v33, 16, v33 -; GFX11-NEXT: v_and_b32_e32 v15, 0xffff, v15 -; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v36 -; GFX11-NEXT: v_and_b32_e32 v24, 0xffff, v24 -; GFX11-NEXT: v_lshlrev_b32_e32 v29, 16, v29 -; GFX11-NEXT: v_or_b32_e32 v148, v23, v28 -; GFX11-NEXT: v_or_b32_e32 v150, v19, v32 -; GFX11-NEXT: v_or_b32_e32 v151, v20, v33 -; GFX11-NEXT: v_or_b32_e32 v130, v15, v36 -; GFX11-NEXT: v_and_b32_e32 v15, 0xff, v16 -; GFX11-NEXT: v_lshlrev_b32_e32 v16, 8, v147 -; GFX11-NEXT: v_and_b32_e32 v19, 0xff, v146 -; GFX11-NEXT: v_lshlrev_b32_e32 v20, 8, v145 +; GFX11-NEXT: v_lshlrev_b32_e32 v36, 8, v36 +; GFX11-NEXT: v_or_b32_e32 v82, v50, v65 +; GFX11-NEXT: v_lshlrev_b32_e32 v50, 8, v67 +; GFX11-NEXT: v_and_b32_e32 v34, 0xff, v34 +; GFX11-NEXT: v_lshlrev_b32_e32 v38, 8, v38 +; GFX11-NEXT: v_or_b32_e32 v36, v29, v36 +; GFX11-NEXT: v_and_b32_e32 v25, 0xff, v25 +; GFX11-NEXT: v_or_b32_e32 v48, v48, v50 +; GFX11-NEXT: v_or_b32_e32 v50, v52, v55 +; GFX11-NEXT: v_lshlrev_b32_e32 v52, 8, v66 +; GFX11-NEXT: v_lshlrev_b32_e32 v32, 8, v32 +; GFX11-NEXT: v_and_b32_e32 v30, 0xff, v30 +; GFX11-NEXT: v_and_b32_e32 v48, 0xffff, v48 +; GFX11-NEXT: v_lshlrev_b32_e32 v50, 16, v50 +; GFX11-NEXT: s_lshl_b32 s4, s73, 8 +; GFX11-NEXT: v_or_b32_e32 v34, v34, v38 +; GFX11-NEXT: v_or_b32_e32 v25, v25, v32 +; GFX11-NEXT: s_lshl_b32 s6, s62, 8 +; GFX11-NEXT: v_or_b32_e32 v48, v48, v50 +; GFX11-NEXT: v_lshlrev_b32_e32 v50, 8, v53 +; GFX11-NEXT: v_lshlrev_b32_e32 v34, 16, v34 +; GFX11-NEXT: v_and_b32_e32 v25, 0xffff, v25 +; GFX11-NEXT: v_and_b32_e32 v21, 0xff, v21 +; GFX11-NEXT: v_and_b32_e32 v26, 0xff, v26 +; GFX11-NEXT: v_or_b32_e32 v35, v35, v50 +; GFX11-NEXT: v_or_b32_e32 v50, v51, v52 +; GFX11-NEXT: v_lshlrev_b32_e32 v51, 8, v54 +; GFX11-NEXT: v_and_b32_e32 v17, 0xff, v17 +; GFX11-NEXT: v_and_b32_e32 v22, 0xff, v22 +; GFX11-NEXT: v_and_b32_e32 v35, 0xffff, v35 +; GFX11-NEXT: v_lshlrev_b32_e32 v50, 16, v50 ; GFX11-NEXT: v_and_b32_e32 v13, 0xff, v13 -; GFX11-NEXT: v_lshlrev_b32_e32 v23, 8, v118 -; GFX11-NEXT: v_or_b32_e32 v149, v24, v29 -; GFX11-NEXT: v_and_b32_e32 v24, 0xff, v117 -; GFX11-NEXT: v_lshlrev_b32_e32 v28, 8, v38 +; GFX11-NEXT: v_lshlrev_b32_e32 v20, 8, v20 +; GFX11-NEXT: v_and_b32_e32 v18, 0xff, v18 ; GFX11-NEXT: v_and_b32_e32 v14, 0xff, v14 -; GFX11-NEXT: v_lshlrev_b32_e32 v29, 8, v134 -; GFX11-NEXT: v_or_b32_e32 v15, v15, v16 -; GFX11-NEXT: v_or_b32_e32 v16, v19, v20 -; GFX11-NEXT: v_or_b32_e32 v13, v13, v23 -; GFX11-NEXT: v_and_b32_e32 v20, 0xff, v133 -; GFX11-NEXT: v_lshlrev_b32_e32 v23, 8, v132 -; GFX11-NEXT: v_or_b32_e32 v19, v24, v28 -; GFX11-NEXT: v_or_b32_e32 v14, v14, v29 -; GFX11-NEXT: v_and_b32_e32 v11, 0xff, v11 -; GFX11-NEXT: v_lshlrev_b32_e32 v24, 8, v115 -; GFX11-NEXT: v_and_b32_e32 v28, 0xff, v113 -; GFX11-NEXT: v_lshlrev_b32_e32 v29, 8, v34 -; GFX11-NEXT: v_and_b32_e32 v12, 0xff, v12 -; GFX11-NEXT: v_lshlrev_b32_e32 v32, 8, v129 -; GFX11-NEXT: v_and_b32_e32 v33, 0xff, v128 -; GFX11-NEXT: v_lshlrev_b32_e32 v34, 8, v119 -; GFX11-NEXT: v_or_b32_e32 v20, v20, v23 -; GFX11-NEXT: v_and_b32_e32 v15, 0xffff, v15 -; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v16 +; GFX11-NEXT: v_or_b32_e32 v50, v35, v50 +; GFX11-NEXT: v_lshlrev_b32_e32 v35, 8, v49 +; GFX11-NEXT: v_mov_b32_e32 v49, s0 +; GFX11-NEXT: s_and_b32 s0, s19, 0xff +; GFX11-NEXT: v_or_b32_e32 v13, v13, v20 +; GFX11-NEXT: v_lshlrev_b32_e32 v19, 8, v19 +; GFX11-NEXT: v_or_b32_e32 v31, v31, v35 +; GFX11-NEXT: v_or_b32_e32 v35, v39, v51 +; GFX11-NEXT: v_mov_b32_e32 v51, s2 +; GFX11-NEXT: s_lshl_b32 s2, s75, 8 ; GFX11-NEXT: v_and_b32_e32 v13, 0xffff, v13 -; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX11-NEXT: v_and_b32_e32 v14, 0xffff, v14 -; GFX11-NEXT: v_or_b32_e32 v11, v11, v24 -; GFX11-NEXT: v_or_b32_e32 v23, v28, v29 -; GFX11-NEXT: v_or_b32_e32 v12, v12, v32 -; GFX11-NEXT: v_or_b32_e32 v24, v33, v34 -; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX11-NEXT: v_and_b32_e32 v11, 0xffff, v11 -; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23 -; GFX11-NEXT: v_and_b32_e32 v12, 0xffff, v12 -; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX11-NEXT: v_or_b32_e32 v131, v15, v16 -; GFX11-NEXT: v_or_b32_e32 v132, v13, v19 -; GFX11-NEXT: v_or_b32_e32 v133, v14, v20 -; GFX11-NEXT: v_and_b32_e32 v9, 0xff, v9 -; GFX11-NEXT: v_lshlrev_b32_e32 v13, 8, v103 -; GFX11-NEXT: v_and_b32_e32 v14, 0xff, v102 -; GFX11-NEXT: v_lshlrev_b32_e32 v15, 8, v30 -; GFX11-NEXT: v_and_b32_e32 v10, 0xff, v10 -; GFX11-NEXT: v_lshlrev_b32_e32 v16, 8, v116 -; GFX11-NEXT: v_and_b32_e32 v19, 0xff, v114 -; GFX11-NEXT: v_lshlrev_b32_e32 v20, 8, v112 -; GFX11-NEXT: v_or_b32_e32 v11, v11, v23 -; GFX11-NEXT: v_or_b32_e32 v12, v12, v24 +; GFX11-NEXT: v_and_b32_e32 v31, 0xffff, v31 +; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v35 +; GFX11-NEXT: s_or_b32 s0, s0, s2 +; GFX11-NEXT: s_and_b32 s2, s74, 0xff +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: v_or_b32_e32 v29, v31, v35 +; GFX11-NEXT: v_lshlrev_b32_e32 v35, 8, v37 +; GFX11-NEXT: s_lshl_b32 s2, s2, 16 +; GFX11-NEXT: s_lshl_b32 s4, s72, 8 +; GFX11-NEXT: s_or_b32 s0, s0, s2 +; GFX11-NEXT: s_and_b32 s2, s17, 0xff +; GFX11-NEXT: v_or_b32_e32 v30, v30, v35 +; GFX11-NEXT: v_and_b32_e32 v31, 0xffff, v36 +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: s_and_b32 s4, s63, 0xff +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v30 +; GFX11-NEXT: s_or_b32 s4, s4, s6 +; GFX11-NEXT: v_or_b32_e32 v31, v31, v34 +; GFX11-NEXT: s_lshl_b32 s4, s4, 16 +; GFX11-NEXT: v_mov_b32_e32 v30, s0 +; GFX11-NEXT: v_or_b32_e32 v34, v25, v35 +; GFX11-NEXT: v_lshlrev_b32_e32 v25, 8, v28 +; GFX11-NEXT: v_lshlrev_b32_e32 v28, 8, v33 +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: s_and_b32 s0, s15, 0xff +; GFX11-NEXT: v_mov_b32_e32 v32, s2 +; GFX11-NEXT: s_lshl_b32 s2, s61, 8 +; GFX11-NEXT: v_or_b32_e32 v21, v21, v25 +; GFX11-NEXT: v_or_b32_e32 v25, v26, v28 +; GFX11-NEXT: s_or_b32 s0, s0, s2 +; GFX11-NEXT: s_and_b32 s2, s60, 0xff +; GFX11-NEXT: s_lshl_b32 s4, s59, 8 +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: v_and_b32_e32 v21, 0xffff, v21 +; GFX11-NEXT: s_lshl_b32 s2, s2, 16 +; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GFX11-NEXT: s_and_b32 s4, s13, 0xff +; GFX11-NEXT: s_lshl_b32 s6, s58, 8 +; GFX11-NEXT: s_or_b32 s0, s0, s2 +; GFX11-NEXT: s_or_b32 s2, s4, s6 +; GFX11-NEXT: s_and_b32 s4, s57, 0xff +; GFX11-NEXT: s_lshl_b32 s6, s56, 8 +; GFX11-NEXT: v_or_b32_e32 v36, v21, v25 +; GFX11-NEXT: s_or_b32 s4, s4, s6 +; GFX11-NEXT: v_lshlrev_b32_e32 v21, 8, v24 +; GFX11-NEXT: v_lshlrev_b32_e32 v24, 8, v27 +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_lshl_b32 s4, s4, 16 +; GFX11-NEXT: v_mov_b32_e32 v35, s0 +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: v_or_b32_e32 v17, v17, v21 +; GFX11-NEXT: v_or_b32_e32 v21, v22, v24 +; GFX11-NEXT: v_mov_b32_e32 v37, s2 +; GFX11-NEXT: s_and_b32 s0, s11, 0xff +; GFX11-NEXT: s_lshl_b32 s2, s47, 8 +; GFX11-NEXT: v_lshlrev_b32_e32 v22, 8, v23 +; GFX11-NEXT: s_or_b32 s0, s0, s2 +; GFX11-NEXT: s_and_b32 s2, s46, 0xff +; GFX11-NEXT: s_lshl_b32 s4, s45, 8 +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: v_or_b32_e32 v18, v18, v22 +; GFX11-NEXT: s_lshl_b32 s2, s2, 16 +; GFX11-NEXT: s_lshl_b32 s4, s44, 8 +; GFX11-NEXT: s_or_b32 s0, s0, s2 +; GFX11-NEXT: s_and_b32 s2, s9, 0xff +; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: s_and_b32 s4, s43, 0xff +; GFX11-NEXT: s_lshl_b32 s6, s42, 8 +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_or_b32 s4, s4, s6 +; GFX11-NEXT: v_or_b32_e32 v14, v14, v19 +; GFX11-NEXT: s_lshl_b32 s4, s4, 16 +; GFX11-NEXT: v_or_b32_e32 v19, v13, v18 ; GFX11-NEXT: v_and_b32_e32 v7, 0xff, v7 -; GFX11-NEXT: v_lshlrev_b32_e32 v23, 8, v98 -; GFX11-NEXT: v_or_b32_e32 v9, v9, v13 -; GFX11-NEXT: v_or_b32_e32 v13, v14, v15 -; GFX11-NEXT: v_or_b32_e32 v10, v10, v16 -; GFX11-NEXT: v_or_b32_e32 v14, v19, v20 -; GFX11-NEXT: v_and_b32_e32 v15, 0xff, v97 -; GFX11-NEXT: v_lshlrev_b32_e32 v16, 8, v26 -; GFX11-NEXT: v_and_b32_e32 v8, 0xff, v8 -; GFX11-NEXT: v_lshlrev_b32_e32 v19, 8, v101 -; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v5 -; GFX11-NEXT: v_lshlrev_b32_e32 v24, 8, v86 -; GFX11-NEXT: v_and_b32_e32 v26, 0xff, v84 -; GFX11-NEXT: v_lshlrev_b32_e32 v25, 8, v25 -; GFX11-NEXT: v_or_b32_e32 v7, v7, v23 -; GFX11-NEXT: v_and_b32_e32 v20, 0xff, v100 -; GFX11-NEXT: v_lshlrev_b32_e32 v23, 8, v99 -; GFX11-NEXT: v_or_b32_e32 v15, v15, v16 -; GFX11-NEXT: v_or_b32_e32 v8, v8, v19 -; GFX11-NEXT: v_or_b32_e32 v5, v5, v24 -; GFX11-NEXT: v_or_b32_e32 v19, v26, v25 -; GFX11-NEXT: v_and_b32_e32 v9, 0xffff, v9 -; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX11-NEXT: v_and_b32_e32 v10, 0xffff, v10 -; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14 +; GFX11-NEXT: v_lshlrev_b32_e32 v12, 8, v12 +; GFX11-NEXT: v_and_b32_e32 v10, 0xff, v10 +; GFX11-NEXT: v_lshlrev_b32_e32 v13, 8, v15 +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: v_mov_b32_e32 v18, s0 +; GFX11-NEXT: v_mov_b32_e32 v20, s2 +; GFX11-NEXT: s_and_b32 s0, s7, 0xff +; GFX11-NEXT: s_lshl_b32 s2, s40, 8 +; GFX11-NEXT: v_and_b32_e32 v11, 0xff, v11 +; GFX11-NEXT: v_lshlrev_b32_e32 v16, 8, v16 +; GFX11-NEXT: s_or_b32 s0, s0, s2 +; GFX11-NEXT: s_and_b32 s2, s28, 0xff +; GFX11-NEXT: s_lshl_b32 s4, s26, 8 +; GFX11-NEXT: v_or_b32_e32 v7, v7, v12 +; GFX11-NEXT: v_or_b32_e32 v10, v10, v13 +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: v_or_b32_e32 v11, v11, v16 +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_lshl_b32 s2, s2, 16 +; GFX11-NEXT: s_and_b32 s4, s5, 0xff +; GFX11-NEXT: s_lshl_b32 s5, s24, 8 ; GFX11-NEXT: v_and_b32_e32 v7, 0xffff, v7 -; GFX11-NEXT: v_or_b32_e32 v16, v20, v23 -; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5 -; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v19 -; GFX11-NEXT: v_and_b32_e32 v8, 0xffff, v8 -; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX11-NEXT: v_or_b32_e32 v13, v9, v13 -; GFX11-NEXT: v_or_b32_e32 v14, v10, v14 -; GFX11-NEXT: v_or_b32_e32 v7, v7, v15 -; GFX11-NEXT: v_or_b32_e32 v9, v5, v19 -; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v6 -; GFX11-NEXT: v_lshlrev_b32_e32 v6, 8, v96 -; GFX11-NEXT: v_and_b32_e32 v10, 0xff, v87 -; GFX11-NEXT: v_lshlrev_b32_e32 v15, 8, v85 -; GFX11-NEXT: v_and_b32_e32 v19, 0xff, v39 -; GFX11-NEXT: v_lshlrev_b32_e32 v20, 8, v21 -; GFX11-NEXT: v_or_b32_e32 v8, v8, v16 +; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX11-NEXT: s_or_b32 s0, s0, s2 +; GFX11-NEXT: s_or_b32 s2, s4, s5 +; GFX11-NEXT: s_and_b32 s4, s22, 0xff +; GFX11-NEXT: s_lshl_b32 s5, s20, 8 +; GFX11-NEXT: v_and_b32_e32 v11, 0xffff, v11 +; GFX11-NEXT: s_or_b32 s4, s4, s5 +; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14 +; GFX11-NEXT: v_or_b32_e32 v13, v7, v10 +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff ; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3 -; GFX11-NEXT: v_lshlrev_b32_e32 v16, 8, v55 -; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v4 -; GFX11-NEXT: v_lshlrev_b32_e32 v21, 8, v83 -; GFX11-NEXT: v_or_b32_e32 v5, v5, v6 -; GFX11-NEXT: v_or_b32_e32 v6, v10, v15 -; GFX11-NEXT: v_or_b32_e32 v10, v19, v20 -; GFX11-NEXT: v_or_b32_e32 v3, v3, v16 -; GFX11-NEXT: v_or_b32_e32 v4, v4, v21 -; GFX11-NEXT: v_lshlrev_b32_e32 v16, 8, v51 +; GFX11-NEXT: v_lshlrev_b32_e32 v7, 8, v8 +; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v6 +; GFX11-NEXT: v_lshlrev_b32_e32 v8, 8, v9 +; GFX11-NEXT: s_lshl_b32 s4, s4, 16 +; GFX11-NEXT: v_or_b32_e32 v11, v11, v14 +; GFX11-NEXT: s_or_b32 s2, s2, s4 +; GFX11-NEXT: v_mov_b32_e32 v12, s0 +; GFX11-NEXT: v_mov_b32_e32 v14, s2 +; GFX11-NEXT: s_and_b32 s0, s3, 0xff +; GFX11-NEXT: s_lshl_b32 s2, s18, 8 +; GFX11-NEXT: v_or_b32_e32 v3, v3, v7 +; GFX11-NEXT: v_or_b32_e32 v6, v6, v8 ; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1 -; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v10 -; GFX11-NEXT: v_and_b32_e32 v10, 0xff, v71 -; GFX11-NEXT: v_lshlrev_b32_e32 v19, 8, v27 -; GFX11-NEXT: v_and_b32_e32 v18, 0xff, v18 -; GFX11-NEXT: v_lshlrev_b32_e32 v17, 8, v17 +; GFX11-NEXT: v_lshlrev_b32_e32 v4, 8, v4 ; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2 -; GFX11-NEXT: v_lshlrev_b32_e32 v20, 8, v35 -; GFX11-NEXT: v_and_b32_e32 v21, 0xff, v31 -; GFX11-NEXT: v_lshlrev_b32_e32 v22, 8, v22 -; GFX11-NEXT: v_or_b32_e32 v10, v10, v16 -; GFX11-NEXT: v_or_b32_e32 v1, v1, v19 -; GFX11-NEXT: v_or_b32_e32 v16, v18, v17 -; GFX11-NEXT: v_or_b32_e32 v2, v2, v20 -; GFX11-NEXT: v_or_b32_e32 v17, v21, v22 -; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5 -; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GFX11-NEXT: v_lshlrev_b32_e32 v5, 8, v5 +; GFX11-NEXT: s_or_b32 s0, s0, s2 +; GFX11-NEXT: s_and_b32 s2, s16, 0xff +; GFX11-NEXT: s_lshl_b32 s3, s14, 8 ; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v4 -; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v10 -; GFX11-NEXT: v_and_b32_e32 v19, 0xffff, v1 -; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX11-NEXT: v_and_b32_e32 v20, 0xffff, v2 -; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; GFX11-NEXT: v_or_b32_e32 v10, v5, v6 +; GFX11-NEXT: s_or_b32 s2, s2, s3 +; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: v_or_b32_e32 v4, v1, v4 +; GFX11-NEXT: v_or_b32_e32 v2, v2, v5 +; GFX11-NEXT: s_lshl_b32 s2, s2, 16 +; GFX11-NEXT: s_and_b32 s1, s1, 0xff +; GFX11-NEXT: s_or_b32 s0, s0, s2 +; GFX11-NEXT: s_lshl_b32 s2, s12, 8 +; GFX11-NEXT: s_and_b32 s3, s10, 0xff +; GFX11-NEXT: s_lshl_b32 s4, s8, 8 +; GFX11-NEXT: v_and_b32_e32 v17, 0xffff, v17 +; GFX11-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX11-NEXT: s_or_b32 s1, s1, s2 +; GFX11-NEXT: s_or_b32 s2, s3, s4 +; GFX11-NEXT: v_or_b32_e32 v1, v3, v6 +; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v4 +; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX11-NEXT: s_and_b32 s1, s1, 0xffff +; GFX11-NEXT: s_lshl_b32 s2, s2, 16 +; GFX11-NEXT: v_or_b32_e32 v17, v17, v21 +; GFX11-NEXT: s_or_b32 s1, s1, s2 ; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: scratch_store_b128 v0, v[72:75], off -; GFX11-NEXT: scratch_store_b128 v0, v[43:46], off offset:16 -; GFX11-NEXT: v_or_b32_e32 v1, v3, v15 -; GFX11-NEXT: v_or_b32_e32 v2, v4, v18 -; GFX11-NEXT: v_or_b32_e32 v3, v19, v16 -; GFX11-NEXT: v_or_b32_e32 v4, v20, v17 +; GFX11-NEXT: scratch_store_b128 v0, v[96:99], off +; GFX11-NEXT: scratch_store_b128 v0, v[80:83], off offset:16 +; GFX11-NEXT: v_or_b32_e32 v3, v3, v2 +; GFX11-NEXT: v_mov_b32_e32 v2, s0 +; GFX11-NEXT: v_mov_b32_e32 v4, s1 ; GFX11-NEXT: s_clause 0x5 -; GFX11-NEXT: scratch_store_b128 v0, v[67:70], off offset:32 -; GFX11-NEXT: scratch_store_b128 v0, v[148:151], off offset:48 -; GFX11-NEXT: scratch_store_b128 v0, v[130:133], off offset:64 -; GFX11-NEXT: scratch_store_b128 v0, v[11:14], off offset:80 -; GFX11-NEXT: scratch_store_b128 v0, v[7:10], off offset:96 +; GFX11-NEXT: scratch_store_b128 v0, v[48:51], off offset:32 +; GFX11-NEXT: scratch_store_b128 v0, v[29:32], off offset:48 +; GFX11-NEXT: scratch_store_b128 v0, v[34:37], off offset:64 +; GFX11-NEXT: scratch_store_b128 v0, v[17:20], off offset:80 +; GFX11-NEXT: scratch_store_b128 v0, v[11:14], off offset:96 ; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:112 -; GFX11-NEXT: s_clause 0x13 ; 80-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v75, off, s32 -; GFX11-NEXT: scratch_load_b32 v74, off, s32 offset:4 -; GFX11-NEXT: scratch_load_b32 v73, off, s32 offset:8 -; GFX11-NEXT: scratch_load_b32 v72, off, s32 offset:12 -; GFX11-NEXT: scratch_load_b32 v63, off, s32 offset:16 -; GFX11-NEXT: scratch_load_b32 v62, off, s32 offset:20 -; GFX11-NEXT: scratch_load_b32 v61, off, s32 offset:24 -; GFX11-NEXT: scratch_load_b32 v60, off, s32 offset:28 -; GFX11-NEXT: scratch_load_b32 v59, off, s32 offset:32 -; GFX11-NEXT: scratch_load_b32 v58, off, s32 offset:36 -; GFX11-NEXT: scratch_load_b32 v57, off, s32 offset:40 -; GFX11-NEXT: scratch_load_b32 v56, off, s32 offset:44 -; GFX11-NEXT: scratch_load_b32 v47, off, s32 offset:48 -; GFX11-NEXT: scratch_load_b32 v46, off, s32 offset:52 -; GFX11-NEXT: scratch_load_b32 v45, off, s32 offset:56 -; GFX11-NEXT: scratch_load_b32 v44, off, s32 offset:60 -; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:64 -; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:68 -; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:72 -; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:76 -; GFX11-NEXT: v_readlane_b32 s104, v77, 8 -; GFX11-NEXT: v_readlane_b32 s103, v77, 7 -; GFX11-NEXT: v_readlane_b32 s102, v77, 6 -; GFX11-NEXT: v_readlane_b32 s101, v77, 5 -; GFX11-NEXT: v_readlane_b32 s100, v77, 4 -; GFX11-NEXT: v_readlane_b32 s99, v77, 3 -; GFX11-NEXT: v_readlane_b32 s98, v77, 2 -; GFX11-NEXT: v_readlane_b32 s97, v77, 1 -; GFX11-NEXT: v_readlane_b32 s96, v77, 0 -; GFX11-NEXT: v_readlane_b32 s87, v76, 31 -; GFX11-NEXT: v_readlane_b32 s86, v76, 30 -; GFX11-NEXT: v_readlane_b32 s85, v76, 29 -; GFX11-NEXT: v_readlane_b32 s84, v76, 28 -; GFX11-NEXT: v_readlane_b32 s83, v76, 27 -; GFX11-NEXT: v_readlane_b32 s82, v76, 26 -; GFX11-NEXT: v_readlane_b32 s81, v76, 25 -; GFX11-NEXT: v_readlane_b32 s80, v76, 24 -; GFX11-NEXT: v_readlane_b32 s71, v76, 23 -; GFX11-NEXT: v_readlane_b32 s70, v76, 22 -; GFX11-NEXT: v_readlane_b32 s69, v76, 21 -; GFX11-NEXT: v_readlane_b32 s68, v76, 20 -; GFX11-NEXT: v_readlane_b32 s67, v76, 19 -; GFX11-NEXT: v_readlane_b32 s66, v76, 18 -; GFX11-NEXT: v_readlane_b32 s65, v76, 17 -; GFX11-NEXT: v_readlane_b32 s64, v76, 16 -; GFX11-NEXT: v_readlane_b32 s55, v76, 15 -; GFX11-NEXT: v_readlane_b32 s54, v76, 14 -; GFX11-NEXT: v_readlane_b32 s53, v76, 13 -; GFX11-NEXT: v_readlane_b32 s52, v76, 12 -; GFX11-NEXT: v_readlane_b32 s51, v76, 11 -; GFX11-NEXT: v_readlane_b32 s50, v76, 10 -; GFX11-NEXT: v_readlane_b32 s49, v76, 9 -; GFX11-NEXT: v_readlane_b32 s48, v76, 8 -; GFX11-NEXT: v_readlane_b32 s39, v76, 7 -; GFX11-NEXT: v_readlane_b32 s38, v76, 6 -; GFX11-NEXT: v_readlane_b32 s37, v76, 5 -; GFX11-NEXT: v_readlane_b32 s36, v76, 4 -; GFX11-NEXT: v_readlane_b32 s35, v76, 3 -; GFX11-NEXT: v_readlane_b32 s34, v76, 2 -; GFX11-NEXT: v_readlane_b32 s31, v76, 1 -; GFX11-NEXT: v_readlane_b32 s30, v76, 0 +; GFX11-NEXT: v_readlane_b32 s104, v41, 8 +; GFX11-NEXT: v_readlane_b32 s103, v41, 7 +; GFX11-NEXT: v_readlane_b32 s102, v41, 6 +; GFX11-NEXT: v_readlane_b32 s101, v41, 5 +; GFX11-NEXT: v_readlane_b32 s100, v41, 4 +; GFX11-NEXT: v_readlane_b32 s99, v41, 3 +; GFX11-NEXT: v_readlane_b32 s98, v41, 2 +; GFX11-NEXT: v_readlane_b32 s97, v41, 1 +; GFX11-NEXT: v_readlane_b32 s96, v41, 0 +; GFX11-NEXT: v_readlane_b32 s87, v40, 31 +; GFX11-NEXT: v_readlane_b32 s86, v40, 30 +; GFX11-NEXT: v_readlane_b32 s85, v40, 29 +; GFX11-NEXT: v_readlane_b32 s84, v40, 28 +; GFX11-NEXT: v_readlane_b32 s83, v40, 27 +; GFX11-NEXT: v_readlane_b32 s82, v40, 26 +; GFX11-NEXT: v_readlane_b32 s81, v40, 25 +; GFX11-NEXT: v_readlane_b32 s80, v40, 24 +; GFX11-NEXT: v_readlane_b32 s71, v40, 23 +; GFX11-NEXT: v_readlane_b32 s70, v40, 22 +; GFX11-NEXT: v_readlane_b32 s69, v40, 21 +; GFX11-NEXT: v_readlane_b32 s68, v40, 20 +; GFX11-NEXT: v_readlane_b32 s67, v40, 19 +; GFX11-NEXT: v_readlane_b32 s66, v40, 18 +; GFX11-NEXT: v_readlane_b32 s65, v40, 17 +; GFX11-NEXT: v_readlane_b32 s64, v40, 16 +; GFX11-NEXT: v_readlane_b32 s55, v40, 15 +; GFX11-NEXT: v_readlane_b32 s54, v40, 14 +; GFX11-NEXT: v_readlane_b32 s53, v40, 13 +; GFX11-NEXT: v_readlane_b32 s52, v40, 12 +; GFX11-NEXT: v_readlane_b32 s51, v40, 11 +; GFX11-NEXT: v_readlane_b32 s50, v40, 10 +; GFX11-NEXT: v_readlane_b32 s49, v40, 9 +; GFX11-NEXT: v_readlane_b32 s48, v40, 8 +; GFX11-NEXT: v_readlane_b32 s39, v40, 7 +; GFX11-NEXT: v_readlane_b32 s38, v40, 6 +; GFX11-NEXT: v_readlane_b32 s37, v40, 5 +; GFX11-NEXT: v_readlane_b32 s36, v40, 4 +; GFX11-NEXT: v_readlane_b32 s35, v40, 3 +; GFX11-NEXT: v_readlane_b32 s34, v40, 2 +; GFX11-NEXT: v_readlane_b32 s31, v40, 1 +; GFX11-NEXT: v_readlane_b32 s30, v40, 0 ; GFX11-NEXT: s_or_saveexec_b32 s0, -1 ; GFX11-NEXT: s_clause 0x3 ; 16-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v76, off, s32 offset:80 -; GFX11-NEXT: scratch_load_b32 v77, off, s32 offset:84 -; GFX11-NEXT: scratch_load_b32 v78, off, s32 offset:88 -; GFX11-NEXT: scratch_load_b32 v79, off, s32 offset:92 +; GFX11-NEXT: scratch_load_b32 v40, off, s32 +; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:4 +; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:8 +; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:12 ; GFX11-NEXT: s_mov_b32 exec_lo, s0 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] @@ -133339,40 +131063,68 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg ; SI-NEXT: v_writelane_b32 v63, s67, 19 ; SI-NEXT: v_writelane_b32 v63, s68, 20 ; SI-NEXT: v_writelane_b32 v63, s69, 21 +; SI-NEXT: v_mov_b32_e32 v20, s16 ; SI-NEXT: v_writelane_b32 v63, s70, 22 +; SI-NEXT: v_readfirstlane_b32 s4, v20 +; SI-NEXT: v_mov_b32_e32 v20, s17 ; SI-NEXT: v_writelane_b32 v63, s71, 23 +; SI-NEXT: v_readfirstlane_b32 s5, v20 +; SI-NEXT: v_mov_b32_e32 v20, s18 ; SI-NEXT: v_writelane_b32 v63, s80, 24 +; SI-NEXT: v_readfirstlane_b32 s6, v20 +; SI-NEXT: v_mov_b32_e32 v20, s19 ; SI-NEXT: v_writelane_b32 v63, s81, 25 +; SI-NEXT: v_readfirstlane_b32 s7, v20 +; SI-NEXT: v_mov_b32_e32 v20, s20 ; SI-NEXT: v_writelane_b32 v63, s82, 26 +; SI-NEXT: v_readfirstlane_b32 s8, v20 +; SI-NEXT: v_mov_b32_e32 v20, s21 ; SI-NEXT: v_writelane_b32 v63, s83, 27 +; SI-NEXT: v_readfirstlane_b32 s9, v20 +; SI-NEXT: v_mov_b32_e32 v20, s22 ; SI-NEXT: v_writelane_b32 v63, s84, 28 +; SI-NEXT: v_readfirstlane_b32 s20, v20 +; SI-NEXT: v_mov_b32_e32 v20, s23 ; SI-NEXT: v_writelane_b32 v63, s85, 29 +; SI-NEXT: v_readfirstlane_b32 s21, v20 +; SI-NEXT: v_mov_b32_e32 v20, s24 ; SI-NEXT: v_writelane_b32 v63, s86, 30 +; SI-NEXT: v_readfirstlane_b32 s24, v20 +; SI-NEXT: v_mov_b32_e32 v20, s25 ; SI-NEXT: v_writelane_b32 v63, s87, 31 +; SI-NEXT: v_readfirstlane_b32 s25, v20 +; SI-NEXT: v_mov_b32_e32 v20, s26 ; SI-NEXT: v_writelane_b32 v63, s96, 32 +; SI-NEXT: v_readfirstlane_b32 s40, v20 +; SI-NEXT: v_mov_b32_e32 v20, s27 ; SI-NEXT: v_writelane_b32 v63, s97, 33 +; SI-NEXT: v_readfirstlane_b32 s41, v20 +; SI-NEXT: v_mov_b32_e32 v20, s28 ; SI-NEXT: v_writelane_b32 v63, s98, 34 +; SI-NEXT: v_readfirstlane_b32 s42, v20 +; SI-NEXT: v_mov_b32_e32 v20, s29 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; SI-NEXT: v_writelane_b32 v63, s99, 35 +; SI-NEXT: v_readfirstlane_b32 s43, v20 ; SI-NEXT: v_readfirstlane_b32 s44, v1 ; SI-NEXT: v_readfirstlane_b32 s45, v2 -; SI-NEXT: v_readfirstlane_b32 s42, v3 -; SI-NEXT: v_readfirstlane_b32 s43, v4 -; SI-NEXT: v_readfirstlane_b32 s40, v5 -; SI-NEXT: v_readfirstlane_b32 s41, v6 -; SI-NEXT: v_readfirstlane_b32 s14, v7 -; SI-NEXT: v_readfirstlane_b32 s15, v8 -; SI-NEXT: v_readfirstlane_b32 s12, v9 -; SI-NEXT: v_readfirstlane_b32 s13, v10 -; SI-NEXT: v_readfirstlane_b32 s10, v11 -; SI-NEXT: v_readfirstlane_b32 s11, v12 -; SI-NEXT: v_readfirstlane_b32 s8, v13 -; SI-NEXT: v_readfirstlane_b32 s9, v14 -; SI-NEXT: v_readfirstlane_b32 s4, v15 -; SI-NEXT: v_readfirstlane_b32 s5, v16 -; SI-NEXT: v_readfirstlane_b32 s6, v17 +; SI-NEXT: v_readfirstlane_b32 s28, v3 +; SI-NEXT: v_readfirstlane_b32 s29, v4 +; SI-NEXT: v_readfirstlane_b32 s26, v5 +; SI-NEXT: v_readfirstlane_b32 s27, v6 +; SI-NEXT: v_readfirstlane_b32 s22, v7 +; SI-NEXT: v_readfirstlane_b32 s23, v8 +; SI-NEXT: v_readfirstlane_b32 s18, v9 +; SI-NEXT: v_readfirstlane_b32 s19, v10 +; SI-NEXT: v_readfirstlane_b32 s16, v11 +; SI-NEXT: v_readfirstlane_b32 s17, v12 +; SI-NEXT: v_readfirstlane_b32 s14, v13 +; SI-NEXT: v_readfirstlane_b32 s15, v14 +; SI-NEXT: v_readfirstlane_b32 s10, v15 +; SI-NEXT: v_readfirstlane_b32 s11, v16 +; SI-NEXT: v_readfirstlane_b32 s12, v17 ; SI-NEXT: s_and_b64 s[46:47], vcc, exec -; SI-NEXT: v_readfirstlane_b32 s7, v18 +; SI-NEXT: v_readfirstlane_b32 s13, v18 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill @@ -133390,164 +131142,162 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg ; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; SI-NEXT: s_cbranch_scc0 .LBB77_3 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: s_and_b32 s46, s17, 0xffff0000 +; SI-NEXT: s_and_b32 s46, s5, 0xffff0000 ; SI-NEXT: v_writelane_b32 v62, s46, 0 -; SI-NEXT: s_lshl_b32 s46, s17, 16 +; SI-NEXT: s_lshl_b32 s46, s5, 16 ; SI-NEXT: v_writelane_b32 v62, s46, 1 -; SI-NEXT: s_and_b32 s46, s16, 0xffff0000 +; SI-NEXT: s_and_b32 s46, s4, 0xffff0000 ; SI-NEXT: v_writelane_b32 v62, s46, 2 -; SI-NEXT: s_lshl_b32 s46, s16, 16 -; SI-NEXT: s_and_b32 s59, s7, 0xffff0000 -; SI-NEXT: s_lshl_b32 s58, s7, 16 -; SI-NEXT: s_and_b32 s57, s6, 0xffff0000 -; SI-NEXT: s_lshl_b32 s56, s6, 16 -; SI-NEXT: s_and_b32 s99, s5, 0xffff0000 -; SI-NEXT: s_lshl_b32 s98, s5, 16 -; SI-NEXT: s_and_b32 s97, s4, 0xffff0000 -; SI-NEXT: s_lshl_b32 s96, s4, 16 -; SI-NEXT: s_and_b32 s87, s9, 0xffff0000 -; SI-NEXT: s_lshl_b32 s86, s9, 16 -; SI-NEXT: s_and_b32 s85, s8, 0xffff0000 -; SI-NEXT: s_lshl_b32 s84, s8, 16 -; SI-NEXT: s_and_b32 s83, s11, 0xffff0000 -; SI-NEXT: s_lshl_b32 s82, s11, 16 -; SI-NEXT: s_and_b32 s81, s10, 0xffff0000 -; SI-NEXT: s_lshl_b32 s80, s10, 16 -; SI-NEXT: s_and_b32 s71, s13, 0xffff0000 -; SI-NEXT: s_lshl_b32 s70, s13, 16 -; SI-NEXT: s_and_b32 s69, s12, 0xffff0000 -; SI-NEXT: s_lshl_b32 s68, s12, 16 -; SI-NEXT: s_and_b32 s67, s15, 0xffff0000 -; SI-NEXT: s_lshl_b32 s66, s15, 16 -; SI-NEXT: s_and_b32 s65, s14, 0xffff0000 -; SI-NEXT: s_lshl_b32 s64, s14, 16 -; SI-NEXT: s_and_b32 s55, s41, 0xffff0000 -; SI-NEXT: s_lshl_b32 s54, s41, 16 -; SI-NEXT: s_and_b32 s53, s40, 0xffff0000 -; SI-NEXT: s_lshl_b32 s52, s40, 16 -; SI-NEXT: s_and_b32 s51, s43, 0xffff0000 -; SI-NEXT: s_lshl_b32 s50, s43, 16 -; SI-NEXT: s_and_b32 s49, s42, 0xffff0000 -; SI-NEXT: s_lshl_b32 s48, s42, 16 +; SI-NEXT: s_lshl_b32 s46, s4, 16 +; SI-NEXT: s_and_b32 s59, s13, 0xffff0000 +; SI-NEXT: s_lshl_b32 s58, s13, 16 +; SI-NEXT: s_and_b32 s57, s12, 0xffff0000 +; SI-NEXT: s_lshl_b32 s56, s12, 16 +; SI-NEXT: s_and_b32 s99, s11, 0xffff0000 +; SI-NEXT: s_lshl_b32 s98, s11, 16 +; SI-NEXT: s_and_b32 s97, s10, 0xffff0000 +; SI-NEXT: s_lshl_b32 s96, s10, 16 +; SI-NEXT: s_and_b32 s87, s15, 0xffff0000 +; SI-NEXT: s_lshl_b32 s86, s15, 16 +; SI-NEXT: s_and_b32 s85, s14, 0xffff0000 +; SI-NEXT: s_lshl_b32 s84, s14, 16 +; SI-NEXT: s_and_b32 s83, s17, 0xffff0000 +; SI-NEXT: s_lshl_b32 s82, s17, 16 +; SI-NEXT: s_and_b32 s81, s16, 0xffff0000 +; SI-NEXT: s_lshl_b32 s80, s16, 16 +; SI-NEXT: s_and_b32 s71, s19, 0xffff0000 +; SI-NEXT: s_lshl_b32 s70, s19, 16 +; SI-NEXT: s_and_b32 s69, s18, 0xffff0000 +; SI-NEXT: s_lshl_b32 s68, s18, 16 +; SI-NEXT: s_and_b32 s67, s23, 0xffff0000 +; SI-NEXT: s_lshl_b32 s66, s23, 16 +; SI-NEXT: s_and_b32 s65, s22, 0xffff0000 +; SI-NEXT: s_lshl_b32 s64, s22, 16 +; SI-NEXT: s_and_b32 s55, s27, 0xffff0000 +; SI-NEXT: s_lshl_b32 s54, s27, 16 +; SI-NEXT: s_and_b32 s53, s26, 0xffff0000 +; SI-NEXT: s_lshl_b32 s52, s26, 16 +; SI-NEXT: s_and_b32 s51, s29, 0xffff0000 +; SI-NEXT: s_lshl_b32 s50, s29, 16 +; SI-NEXT: s_and_b32 s49, s28, 0xffff0000 +; SI-NEXT: s_lshl_b32 s48, s28, 16 ; SI-NEXT: s_and_b32 s39, s45, 0xffff0000 ; SI-NEXT: s_lshl_b32 s38, s45, 16 ; SI-NEXT: s_and_b32 s37, s44, 0xffff0000 ; SI-NEXT: s_lshl_b32 s36, s44, 16 -; SI-NEXT: s_and_b32 s35, s29, 0xffff0000 -; SI-NEXT: s_lshl_b32 s34, s29, 16 -; SI-NEXT: s_and_b32 s31, s28, 0xffff0000 -; SI-NEXT: s_lshl_b32 s30, s28, 16 -; SI-NEXT: s_and_b32 s95, s27, 0xffff0000 -; SI-NEXT: s_lshl_b32 s94, s27, 16 -; SI-NEXT: s_and_b32 s93, s26, 0xffff0000 -; SI-NEXT: s_lshl_b32 s92, s26, 16 +; SI-NEXT: s_and_b32 s35, s43, 0xffff0000 +; SI-NEXT: s_lshl_b32 s34, s43, 16 +; SI-NEXT: s_and_b32 s31, s42, 0xffff0000 +; SI-NEXT: s_lshl_b32 s30, s42, 16 +; SI-NEXT: s_and_b32 s95, s41, 0xffff0000 +; SI-NEXT: s_lshl_b32 s94, s41, 16 +; SI-NEXT: s_and_b32 s93, s40, 0xffff0000 +; SI-NEXT: s_lshl_b32 s92, s40, 16 ; SI-NEXT: s_and_b32 s91, s25, 0xffff0000 ; SI-NEXT: s_lshl_b32 s90, s25, 16 ; SI-NEXT: s_and_b32 s89, s24, 0xffff0000 ; SI-NEXT: s_lshl_b32 s88, s24, 16 -; SI-NEXT: s_and_b32 s79, s23, 0xffff0000 -; SI-NEXT: s_lshl_b32 s78, s23, 16 -; SI-NEXT: s_and_b32 s77, s22, 0xffff0000 -; SI-NEXT: s_lshl_b32 s76, s22, 16 -; SI-NEXT: s_and_b32 s75, s21, 0xffff0000 -; SI-NEXT: s_lshl_b32 s74, s21, 16 -; SI-NEXT: s_and_b32 s73, s20, 0xffff0000 -; SI-NEXT: s_lshl_b32 s72, s20, 16 -; SI-NEXT: s_and_b32 s63, s19, 0xffff0000 -; SI-NEXT: s_lshl_b32 s62, s19, 16 -; SI-NEXT: s_and_b32 s61, s18, 0xffff0000 -; SI-NEXT: s_lshl_b32 s60, s18, 16 +; SI-NEXT: s_and_b32 s79, s21, 0xffff0000 +; SI-NEXT: s_lshl_b32 s78, s21, 16 +; SI-NEXT: s_and_b32 s77, s20, 0xffff0000 +; SI-NEXT: s_lshl_b32 s76, s20, 16 +; SI-NEXT: s_and_b32 s75, s9, 0xffff0000 +; SI-NEXT: s_lshl_b32 s74, s9, 16 +; SI-NEXT: s_and_b32 s73, s8, 0xffff0000 +; SI-NEXT: s_lshl_b32 s72, s8, 16 +; SI-NEXT: s_and_b32 s63, s7, 0xffff0000 +; SI-NEXT: s_lshl_b32 s62, s7, 16 +; SI-NEXT: s_and_b32 s61, s6, 0xffff0000 +; SI-NEXT: s_lshl_b32 s60, s6, 16 ; SI-NEXT: v_writelane_b32 v62, s46, 3 ; SI-NEXT: s_cbranch_execnz .LBB77_4 ; SI-NEXT: .LBB77_2: ; %cmp.true -; SI-NEXT: v_add_f64 v[35:36], s[44:45], 1.0 -; SI-NEXT: v_add_f64 v[3:4], s[6:7], 1.0 -; SI-NEXT: v_add_f64 v[49:50], s[28:29], 1.0 -; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v3 -; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v3 -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v35 -; SI-NEXT: v_add_f64 v[1:2], s[22:23], 1.0 +; SI-NEXT: v_add_f64 v[3:4], s[12:13], 1.0 +; SI-NEXT: v_add_f64 v[1:2], s[20:21], 1.0 ; SI-NEXT: v_add_f64 v[41:42], s[24:25], 1.0 -; SI-NEXT: v_add_f64 v[27:28], s[40:41], 1.0 -; SI-NEXT: v_add_f64 v[15:16], s[10:11], 1.0 -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v35 -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v4 +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v50 -; SI-NEXT: v_add_f64 v[31:32], s[42:43], 1.0 -; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v16 -; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v16 -; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v15 -; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v15 -; SI-NEXT: v_and_b32_e32 v43, 0xffff0000, v28 -; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v28 -; SI-NEXT: v_and_b32_e32 v45, 0xffff0000, v27 -; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v27 +; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v3 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v42 -; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v42 -; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v41 -; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v41 +; SI-NEXT: v_and_b32_e32 v54, 0xffff0000, v42 +; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v42 +; SI-NEXT: v_and_b32_e32 v40, 0xffff0000, v41 +; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v41 ; SI-NEXT: v_and_b32_e32 v42, 0xffff0000, v2 ; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v2 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_f64 v[2:3], s[20:21], 1.0 -; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v4 -; SI-NEXT: v_add_f64 v[11:12], s[8:9], 1.0 -; SI-NEXT: v_add_f64 v[7:8], s[4:5], 1.0 -; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; SI-NEXT: v_add_f64 v[2:3], s[8:9], 1.0 +; SI-NEXT: v_add_f64 v[51:52], s[40:41], 1.0 +; SI-NEXT: v_add_f64 v[49:50], s[42:43], 1.0 +; SI-NEXT: v_add_f64 v[35:36], s[44:45], 1.0 +; SI-NEXT: v_add_f64 v[31:32], s[28:29], 1.0 +; SI-NEXT: v_add_f64 v[27:28], s[26:27], 1.0 +; SI-NEXT: v_add_f64 v[23:24], s[22:23], 1.0 +; SI-NEXT: v_add_f64 v[19:20], s[18:19], 1.0 +; SI-NEXT: v_add_f64 v[15:16], s[16:17], 1.0 +; SI-NEXT: v_add_f64 v[11:12], s[14:15], 1.0 +; SI-NEXT: v_add_f64 v[7:8], s[10:11], 1.0 +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; SI-NEXT: v_and_b32_e32 v46, 0xffff0000, v3 +; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v3 +; SI-NEXT: v_add_f64 v[59:60], s[6:7], 1.0 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v4 -; SI-NEXT: v_and_b32_e32 v47, 0xffff0000, v32 -; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v32 -; SI-NEXT: v_and_b32_e32 v57, 0xffff0000, v31 -; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v31 -; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v3 -; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v3 -; SI-NEXT: v_add_f64 v[3:4], s[16:17], 1.0 -; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v7 -; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v7 -; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v12 -; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v12 -; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v11 -; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v11 -; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v1 -; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v1 -; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v4 -; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v4 -; SI-NEXT: v_mov_b32_e32 v4, v5 -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; SI-NEXT: v_add_f64 v[51:52], s[26:27], 1.0 -; SI-NEXT: v_add_f64 v[23:24], s[14:15], 1.0 -; SI-NEXT: v_add_f64 v[19:20], s[12:13], 1.0 -; SI-NEXT: v_add_f64 v[59:60], s[18:19], 1.0 -; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v8 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v8 -; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v20 -; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v20 -; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v19 -; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v19 -; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v24 -; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v24 -; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v23 -; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v23 -; SI-NEXT: v_and_b32_e32 v61, 0xffff0000, v36 -; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v36 -; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v50 -; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v49 -; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v49 +; SI-NEXT: v_add_f64 v[3:4], s[4:5], 1.0 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v8 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v8 +; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v7 +; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v12 +; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v12 +; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v11 +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v16 +; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v16 +; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v15 +; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15 +; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v20 +; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v20 +; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v19 +; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v24 +; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v24 +; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v23 +; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v28 +; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v28 +; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v27 +; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27 +; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v32 +; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v32 +; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v31 +; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31 +; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v36 +; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v36 +; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v35 +; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v35 +; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v50 +; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v50 +; SI-NEXT: v_and_b32_e32 v48, 0xffff0000, v49 +; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v49 ; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v52 ; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v52 ; SI-NEXT: v_and_b32_e32 v52, 0xffff0000, v51 ; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v51 -; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v2 -; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v2 -; SI-NEXT: v_and_b32_e32 v36, 0xffff0000, v60 -; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v60 +; SI-NEXT: v_and_b32_e32 v43, 0xffff0000, v1 +; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v1 +; SI-NEXT: v_and_b32_e32 v47, 0xffff0000, v2 +; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v2 +; SI-NEXT: v_and_b32_e32 v58, 0xffff0000, v60 +; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v60 ; SI-NEXT: v_and_b32_e32 v60, 0xffff0000, v59 ; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v59 +; SI-NEXT: v_and_b32_e32 v61, 0xffff0000, v4 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v4 ; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; SI-NEXT: s_branch .LBB77_5 @@ -133622,15 +131372,18 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg ; SI-NEXT: ; kill: killed $sgpr46 ; SI-NEXT: s_branch .LBB77_2 ; SI-NEXT: .LBB77_4: -; SI-NEXT: v_mov_b32_e32 v1, s37 +; SI-NEXT: v_mov_b32_e32 v1, s59 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v1, s36 -; SI-NEXT: v_readlane_b32 s4, v62, 0 +; SI-NEXT: v_mov_b32_e32 v1, s58 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v1, s34 -; SI-NEXT: v_mov_b32_e32 v7, s4 +; SI-NEXT: v_mov_b32_e32 v1, s57 +; SI-NEXT: v_readlane_b32 s4, v62, 0 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v1, s56 +; SI-NEXT: v_mov_b32_e32 v61, s4 ; SI-NEXT: v_readlane_b32 s4, v62, 1 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) @@ -133638,328 +131391,329 @@ define inreg <64 x bfloat> @bitcast_v16f64_to_v64bf16_scalar(<16 x double> inreg ; SI-NEXT: v_readlane_b32 s4, v62, 2 ; SI-NEXT: v_mov_b32_e32 v2, s4 ; SI-NEXT: v_readlane_b32 s4, v62, 3 -; SI-NEXT: v_mov_b32_e32 v5, s59 -; SI-NEXT: v_mov_b32_e32 v4, s58 -; SI-NEXT: v_mov_b32_e32 v9, s57 -; SI-NEXT: v_mov_b32_e32 v6, s56 -; SI-NEXT: v_mov_b32_e32 v13, s99 -; SI-NEXT: v_mov_b32_e32 v10, s98 -; SI-NEXT: v_mov_b32_e32 v17, s97 -; SI-NEXT: v_mov_b32_e32 v14, s96 -; SI-NEXT: v_mov_b32_e32 v21, s87 -; SI-NEXT: v_mov_b32_e32 v18, s86 -; SI-NEXT: v_mov_b32_e32 v25, s85 -; SI-NEXT: v_mov_b32_e32 v22, s84 -; SI-NEXT: v_mov_b32_e32 v29, s83 -; SI-NEXT: v_mov_b32_e32 v26, s82 -; SI-NEXT: v_mov_b32_e32 v33, s81 -; SI-NEXT: v_mov_b32_e32 v30, s80 -; SI-NEXT: v_mov_b32_e32 v37, s71 -; SI-NEXT: v_mov_b32_e32 v34, s70 -; SI-NEXT: v_mov_b32_e32 v39, s69 -; SI-NEXT: v_mov_b32_e32 v38, s68 -; SI-NEXT: v_mov_b32_e32 v53, s67 -; SI-NEXT: v_mov_b32_e32 v48, s66 -; SI-NEXT: v_mov_b32_e32 v55, s65 -; SI-NEXT: v_mov_b32_e32 v54, s64 -; SI-NEXT: v_mov_b32_e32 v43, s55 -; SI-NEXT: v_mov_b32_e32 v40, s54 -; SI-NEXT: v_mov_b32_e32 v45, s53 -; SI-NEXT: v_mov_b32_e32 v44, s52 -; SI-NEXT: v_mov_b32_e32 v47, s51 -; SI-NEXT: v_mov_b32_e32 v46, s50 -; SI-NEXT: v_mov_b32_e32 v57, s49 -; SI-NEXT: v_mov_b32_e32 v56, s48 -; SI-NEXT: v_mov_b32_e32 v61, s39 -; SI-NEXT: v_mov_b32_e32 v58, s38 -; SI-NEXT: v_mov_b32_e32 v8, s35 -; SI-NEXT: v_mov_b32_e32 v24, s31 -; SI-NEXT: v_mov_b32_e32 v23, s30 +; SI-NEXT: v_mov_b32_e32 v6, s99 +; SI-NEXT: v_mov_b32_e32 v5, s98 +; SI-NEXT: v_mov_b32_e32 v8, s97 +; SI-NEXT: v_mov_b32_e32 v7, s96 +; SI-NEXT: v_mov_b32_e32 v10, s87 +; SI-NEXT: v_mov_b32_e32 v9, s86 +; SI-NEXT: v_mov_b32_e32 v12, s85 +; SI-NEXT: v_mov_b32_e32 v11, s84 +; SI-NEXT: v_mov_b32_e32 v14, s83 +; SI-NEXT: v_mov_b32_e32 v13, s82 +; SI-NEXT: v_mov_b32_e32 v16, s81 +; SI-NEXT: v_mov_b32_e32 v15, s80 +; SI-NEXT: v_mov_b32_e32 v18, s71 +; SI-NEXT: v_mov_b32_e32 v17, s70 +; SI-NEXT: v_mov_b32_e32 v20, s69 +; SI-NEXT: v_mov_b32_e32 v19, s68 +; SI-NEXT: v_mov_b32_e32 v22, s67 +; SI-NEXT: v_mov_b32_e32 v21, s66 +; SI-NEXT: v_mov_b32_e32 v24, s65 +; SI-NEXT: v_mov_b32_e32 v23, s64 +; SI-NEXT: v_mov_b32_e32 v26, s55 +; SI-NEXT: v_mov_b32_e32 v25, s54 +; SI-NEXT: v_mov_b32_e32 v28, s53 +; SI-NEXT: v_mov_b32_e32 v27, s52 +; SI-NEXT: v_mov_b32_e32 v30, s51 +; SI-NEXT: v_mov_b32_e32 v29, s50 +; SI-NEXT: v_mov_b32_e32 v32, s49 +; SI-NEXT: v_mov_b32_e32 v31, s48 +; SI-NEXT: v_mov_b32_e32 v34, s39 +; SI-NEXT: v_mov_b32_e32 v33, s38 +; SI-NEXT: v_mov_b32_e32 v36, s37 +; SI-NEXT: v_mov_b32_e32 v35, s36 +; SI-NEXT: v_mov_b32_e32 v38, s35 +; SI-NEXT: v_mov_b32_e32 v37, s34 +; SI-NEXT: v_mov_b32_e32 v48, s31 +; SI-NEXT: v_mov_b32_e32 v39, s30 ; SI-NEXT: v_mov_b32_e32 v50, s95 ; SI-NEXT: v_mov_b32_e32 v49, s94 ; SI-NEXT: v_mov_b32_e32 v52, s93 ; SI-NEXT: v_mov_b32_e32 v51, s92 -; SI-NEXT: v_mov_b32_e32 v16, s91 -; SI-NEXT: v_mov_b32_e32 v15, s90 -; SI-NEXT: v_mov_b32_e32 v28, s89 -; SI-NEXT: v_mov_b32_e32 v27, s88 +; SI-NEXT: v_mov_b32_e32 v54, s91 +; SI-NEXT: v_mov_b32_e32 v53, s90 +; SI-NEXT: v_mov_b32_e32 v40, s89 +; SI-NEXT: v_mov_b32_e32 v55, s88 ; SI-NEXT: v_mov_b32_e32 v42, s79 ; SI-NEXT: v_mov_b32_e32 v41, s78 -; SI-NEXT: v_mov_b32_e32 v11, s77 -; SI-NEXT: v_mov_b32_e32 v12, s76 -; SI-NEXT: v_mov_b32_e32 v32, s75 -; SI-NEXT: v_mov_b32_e32 v31, s74 -; SI-NEXT: v_mov_b32_e32 v19, s73 -; SI-NEXT: v_mov_b32_e32 v20, s72 -; SI-NEXT: v_mov_b32_e32 v36, s63 -; SI-NEXT: v_mov_b32_e32 v35, s62 +; SI-NEXT: v_mov_b32_e32 v43, s77 +; SI-NEXT: v_mov_b32_e32 v44, s76 +; SI-NEXT: v_mov_b32_e32 v46, s75 +; SI-NEXT: v_mov_b32_e32 v45, s74 +; SI-NEXT: v_mov_b32_e32 v47, s73 +; SI-NEXT: v_mov_b32_e32 v56, s72 +; SI-NEXT: v_mov_b32_e32 v58, s63 +; SI-NEXT: v_mov_b32_e32 v57, s62 ; SI-NEXT: v_mov_b32_e32 v60, s61 ; SI-NEXT: v_mov_b32_e32 v59, s60 ; SI-NEXT: v_mov_b32_e32 v3, s4 ; SI-NEXT: .LBB77_5: ; %end ; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 +; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v2 ; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3 -; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16 +; SI-NEXT: v_lshr_b64 v[2:3], v[3:4], 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 ; SI-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v7 +; SI-NEXT: v_mul_f32_e32 v2, 1.0, v61 ; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v60 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v59 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v59 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v35 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v58 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v57 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v19 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v20 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v47 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v56 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v32 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v31 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v46 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v45 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v12 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v43 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v44 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v42 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v41 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v41 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v28 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v27 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v40 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v55 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v16 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v15 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v54 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v53 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v52 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v51 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v51 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v50 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v49 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v49 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v24 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v23 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v48 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v39 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_readlane_b32 s99, v63, 35 -; SI-NEXT: v_readlane_b32 s98, v63, 34 -; SI-NEXT: v_readlane_b32 s97, v63, 33 -; SI-NEXT: v_readlane_b32 s96, v63, 32 -; SI-NEXT: v_readlane_b32 s87, v63, 31 -; SI-NEXT: v_readlane_b32 s86, v63, 30 -; SI-NEXT: v_readlane_b32 s85, v63, 29 -; SI-NEXT: v_readlane_b32 s84, v63, 28 -; SI-NEXT: v_readlane_b32 s83, v63, 27 -; SI-NEXT: v_readlane_b32 s82, v63, 26 -; SI-NEXT: v_readlane_b32 s81, v63, 25 -; SI-NEXT: v_readlane_b32 s80, v63, 24 -; SI-NEXT: v_readlane_b32 s71, v63, 23 -; SI-NEXT: v_readlane_b32 s70, v63, 22 -; SI-NEXT: v_readlane_b32 s69, v63, 21 -; SI-NEXT: v_readlane_b32 s68, v63, 20 -; SI-NEXT: v_readlane_b32 s67, v63, 19 -; SI-NEXT: v_readlane_b32 s66, v63, 18 -; SI-NEXT: v_readlane_b32 s65, v63, 17 -; SI-NEXT: v_readlane_b32 s64, v63, 16 -; SI-NEXT: v_readlane_b32 s55, v63, 15 -; SI-NEXT: v_readlane_b32 s54, v63, 14 -; SI-NEXT: v_readlane_b32 s53, v63, 13 -; SI-NEXT: v_readlane_b32 s52, v63, 12 -; SI-NEXT: v_readlane_b32 s51, v63, 11 -; SI-NEXT: v_readlane_b32 s50, v63, 10 -; SI-NEXT: v_readlane_b32 s49, v63, 9 -; SI-NEXT: v_readlane_b32 s48, v63, 8 -; SI-NEXT: v_readlane_b32 s39, v63, 7 -; SI-NEXT: v_readlane_b32 s38, v63, 6 -; SI-NEXT: v_readlane_b32 s37, v63, 5 -; SI-NEXT: v_readlane_b32 s36, v63, 4 -; SI-NEXT: v_readlane_b32 s35, v63, 3 -; SI-NEXT: v_readlane_b32 s34, v63, 2 -; SI-NEXT: v_readlane_b32 s31, v63, 1 -; SI-NEXT: v_readlane_b32 s30, v63, 0 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v38 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v37 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v35 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v61 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v58 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v34 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v33 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v57 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v56 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v32 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v31 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 64, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v47 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v46 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v30 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v29 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v45 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v44 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v28 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v27 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x48, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v43 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v40 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v26 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v25 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v55 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v54 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v24 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v23 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x50, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v53 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v48 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v22 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v21 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v39 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v38 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v20 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v19 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x58, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v37 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v34 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v18 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v17 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v33 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v30 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v15 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x60, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v29 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v26 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v14 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v13 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x64, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v25 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v22 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v12 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x68, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v21 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v18 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v10 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v17 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v14 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v7 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x70, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v13 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v10 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v6 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v6 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; SI-NEXT: v_readlane_b32 s99, v63, 35 +; SI-NEXT: v_readlane_b32 s98, v63, 34 +; SI-NEXT: v_readlane_b32 s97, v63, 33 +; SI-NEXT: v_readlane_b32 s96, v63, 32 +; SI-NEXT: v_readlane_b32 s87, v63, 31 +; SI-NEXT: v_readlane_b32 s86, v63, 30 +; SI-NEXT: v_readlane_b32 s85, v63, 29 +; SI-NEXT: v_readlane_b32 s84, v63, 28 +; SI-NEXT: v_readlane_b32 s83, v63, 27 +; SI-NEXT: v_readlane_b32 s82, v63, 26 +; SI-NEXT: v_readlane_b32 s81, v63, 25 +; SI-NEXT: v_readlane_b32 s80, v63, 24 +; SI-NEXT: v_readlane_b32 s71, v63, 23 +; SI-NEXT: v_readlane_b32 s70, v63, 22 +; SI-NEXT: v_readlane_b32 s69, v63, 21 +; SI-NEXT: v_readlane_b32 s68, v63, 20 +; SI-NEXT: v_readlane_b32 s67, v63, 19 +; SI-NEXT: v_readlane_b32 s66, v63, 18 +; SI-NEXT: v_readlane_b32 s65, v63, 17 +; SI-NEXT: v_readlane_b32 s64, v63, 16 +; SI-NEXT: v_readlane_b32 s55, v63, 15 +; SI-NEXT: v_readlane_b32 s54, v63, 14 +; SI-NEXT: v_readlane_b32 s53, v63, 13 +; SI-NEXT: v_readlane_b32 s52, v63, 12 +; SI-NEXT: v_readlane_b32 s51, v63, 11 +; SI-NEXT: v_readlane_b32 s50, v63, 10 +; SI-NEXT: v_readlane_b32 s49, v63, 9 +; SI-NEXT: v_readlane_b32 s48, v63, 8 +; SI-NEXT: v_readlane_b32 s39, v63, 7 +; SI-NEXT: v_readlane_b32 s38, v63, 6 +; SI-NEXT: v_readlane_b32 s37, v63, 5 +; SI-NEXT: v_readlane_b32 s36, v63, 4 +; SI-NEXT: v_readlane_b32 s35, v63, 3 +; SI-NEXT: v_readlane_b32 s34, v63, 2 +; SI-NEXT: v_readlane_b32 s31, v63, 1 +; SI-NEXT: v_readlane_b32 s30, v63, 0 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v4 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload @@ -137170,562 +134924,737 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v52, v30 -; SI-NEXT: v_mov_b32_e32 v53, v28 -; SI-NEXT: v_mov_b32_e32 v40, v12 -; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:76 -; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 -; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:8 -; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:4 -; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:16 -; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:12 -; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:24 -; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:20 -; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:32 -; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:28 -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:40 -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:36 -; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:44 +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76 +; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 +; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:16 +; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:24 +; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:32 +; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:40 +; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:48 +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:56 +; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:64 +; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:72 +; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:4 +; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:12 +; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:20 +; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:28 +; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:36 +; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:44 +; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:52 +; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:60 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:68 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:56 -; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:52 -; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:64 -; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:60 -; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72 -; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:68 -; SI-NEXT: v_mov_b32_e32 v55, v14 -; SI-NEXT: v_mul_f32_e32 v14, 1.0, v0 -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v6 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v63, 1.0, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v8 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v7 +; SI-NEXT: v_mov_b32_e32 v43, v21 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v10 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v11 +; SI-NEXT: v_mov_b32_e32 v54, v29 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v43 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v16 -; SI-NEXT: v_mul_f32_e32 v58, 1.0, v1 -; SI-NEXT: v_mul_f32_e32 v56, 1.0, v3 -; SI-NEXT: v_mul_f32_e32 v54, 1.0, v2 -; SI-NEXT: v_mul_f32_e32 v44, 1.0, v5 -; SI-NEXT: v_mul_f32_e32 v46, 1.0, v4 -; SI-NEXT: v_mul_f32_e32 v61, 1.0, v7 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v54 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v41, v23 +; SI-NEXT: v_mov_b32_e32 v29, v20 +; SI-NEXT: v_mul_f32_e32 v57, 1.0, v3 ; SI-NEXT: v_mul_f32_e32 v59, 1.0, v9 -; SI-NEXT: v_mul_f32_e32 v57, 1.0, v11 -; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13 -; SI-NEXT: v_mul_f32_e32 v47, 1.0, v40 -; SI-NEXT: v_mul_f32_e32 v45, 1.0, v15 -; SI-NEXT: v_mul_f32_e32 v15, 1.0, v17 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; SI-NEXT: v_mul_f32_e32 v16, 1.0, v19 -; SI-NEXT: v_mul_f32_e32 v43, 1.0, v18 -; SI-NEXT: v_mul_f32_e32 v17, 1.0, v21 -; SI-NEXT: v_mul_f32_e32 v41, 1.0, v20 -; SI-NEXT: v_mul_f32_e32 v18, 1.0, v23 -; SI-NEXT: v_mul_f32_e32 v40, 1.0, v22 -; SI-NEXT: v_mul_f32_e32 v19, 1.0, v25 -; SI-NEXT: v_mul_f32_e32 v55, 1.0, v24 -; SI-NEXT: v_mul_f32_e32 v20, 1.0, v27 -; SI-NEXT: v_mul_f32_e32 v21, 1.0, v29 -; SI-NEXT: v_mul_f32_e32 v53, 1.0, v53 -; SI-NEXT: v_mul_f32_e32 v52, 1.0, v52 +; SI-NEXT: v_mul_f32_e32 v61, 1.0, v13 +; SI-NEXT: v_mul_f32_e32 v23, 1.0, v15 +; SI-NEXT: v_mul_f32_e32 v44, 1.0, v17 +; SI-NEXT: v_mul_f32_e32 v21, 1.0, v19 +; SI-NEXT: v_mul_f32_e32 v20, 1.0, v41 +; SI-NEXT: v_mul_f32_e32 v17, 1.0, v25 +; SI-NEXT: v_mul_f32_e32 v15, 1.0, v27 +; SI-NEXT: v_mul_f32_e64 v25, 1.0, s17 +; SI-NEXT: v_mul_f32_e64 v3, 1.0, s21 +; SI-NEXT: v_mul_f32_e64 v5, 1.0, s25 +; SI-NEXT: v_mul_f32_e64 v7, 1.0, s29 +; SI-NEXT: v_mul_f32_e32 v9, 1.0, v2 +; SI-NEXT: v_mul_f32_e32 v54, 1.0, v4 +; SI-NEXT: v_mul_f32_e32 v11, 1.0, v6 +; SI-NEXT: v_mul_f32_e32 v56, 1.0, v8 +; SI-NEXT: v_mul_f32_e32 v13, 1.0, v10 +; SI-NEXT: v_mul_f32_e32 v58, 1.0, v12 +; SI-NEXT: v_mul_f32_e32 v60, 1.0, v14 +; SI-NEXT: v_mul_f32_e32 v62, 1.0, v16 +; SI-NEXT: v_mul_f32_e32 v47, 1.0, v22 +; SI-NEXT: v_mul_f32_e32 v22, 1.0, v28 +; SI-NEXT: v_mul_f32_e64 v19, 1.0, s16 +; SI-NEXT: v_mul_f32_e64 v14, 1.0, s20 +; SI-NEXT: v_mul_f32_e64 v16, 1.0, s22 +; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v32 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v33 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v34 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v35 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v37 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v38 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v39 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v48 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v49 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v0, 1.0, s17 -; SI-NEXT: v_mul_f32_e64 v3, 1.0, s16 ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s19 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s18 -; SI-NEXT: v_mul_f32_e64 v4, 1.0, s21 -; SI-NEXT: v_mul_f32_e64 v8, 1.0, s20 -; SI-NEXT: v_mul_f32_e64 v10, 1.0, s23 -; SI-NEXT: v_mul_f32_e64 v9, 1.0, s22 -; SI-NEXT: v_mul_f32_e64 v5, 1.0, s27 -; SI-NEXT: v_mul_f32_e64 v11, 1.0, s26 -; SI-NEXT: v_mul_f32_e64 v6, 1.0, s29 -; SI-NEXT: v_mul_f32_e64 v7, 1.0, s28 +; SI-NEXT: v_mul_f32_e32 v39, 1.0, v0 ; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v48 -; SI-NEXT: v_mul_f32_e32 v48, 1.0, v26 -; SI-NEXT: v_mul_f32_e32 v22, 1.0, v51 +; SI-NEXT: v_mul_f32_e32 v0, 1.0, v45 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill ; SI-NEXT: s_and_b64 s[4:5], vcc, exec -; SI-NEXT: v_mul_f32_e32 v23, 1.0, v37 -; SI-NEXT: v_mul_f32_e32 v51, 1.0, v50 -; SI-NEXT: v_mul_f32_e32 v24, 1.0, v38 -; SI-NEXT: v_mul_f32_e32 v50, 1.0, v49 -; SI-NEXT: v_mul_f32_e32 v25, 1.0, v39 -; SI-NEXT: v_mul_f32_e32 v49, 1.0, v30 -; SI-NEXT: v_mul_f32_e32 v26, 1.0, v28 -; SI-NEXT: v_mul_f32_e32 v39, 1.0, v12 -; SI-NEXT: v_mul_f32_e32 v27, 1.0, v31 -; SI-NEXT: s_waitcnt vmcnt(13) -; SI-NEXT: v_mul_f32_e32 v38, 1.0, v60 -; SI-NEXT: s_waitcnt vmcnt(12) +; SI-NEXT: v_mul_f32_e64 v35, 1.0, s23 +; SI-NEXT: v_mul_f32_e64 v33, 1.0, s27 +; SI-NEXT: v_mul_f32_e32 v32, 1.0, v18 +; SI-NEXT: v_mul_f32_e32 v34, 1.0, v29 +; SI-NEXT: v_mul_f32_e32 v36, 1.0, v24 +; SI-NEXT: v_mul_f32_e32 v38, 1.0, v26 +; SI-NEXT: v_mul_f32_e32 v31, 1.0, v30 +; SI-NEXT: v_mul_f32_e32 v24, 1.0, v51 +; SI-NEXT: v_mul_f32_e32 v41, 1.0, v53 +; SI-NEXT: v_mul_f32_e32 v26, 1.0, v55 +; SI-NEXT: v_mul_f32_e32 v43, 1.0, v40 ; SI-NEXT: v_mul_f32_e32 v28, 1.0, v42 -; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_mul_f32_e32 v37, 1.0, v62 -; SI-NEXT: s_waitcnt vmcnt(10) -; SI-NEXT: v_mul_f32_e32 v29, 1.0, v63 -; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_mul_f32_e32 v32, 1.0, v32 -; SI-NEXT: s_waitcnt vmcnt(8) -; SI-NEXT: v_mul_f32_e32 v30, 1.0, v33 -; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_mul_f32_e32 v31, 1.0, v34 -; SI-NEXT: s_waitcnt vmcnt(6) -; SI-NEXT: v_mul_f32_e32 v33, 1.0, v35 -; SI-NEXT: s_waitcnt vmcnt(5) -; SI-NEXT: v_mul_f32_e32 v42, 1.0, v36 -; SI-NEXT: v_mul_f32_e64 v12, 1.0, s25 -; SI-NEXT: v_mul_f32_e64 v34, 1.0, s24 -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v51, 1.0, v50 +; SI-NEXT: v_mul_f32_e32 v53, 1.0, v52 +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_mul_f32_e32 v0, 1.0, v46 +; SI-NEXT: v_mul_f32_e64 v48, 1.0, s18 +; SI-NEXT: v_mul_f32_e64 v18, 1.0, s24 +; SI-NEXT: v_mul_f32_e64 v29, 1.0, s26 +; SI-NEXT: v_mul_f32_e64 v45, 1.0, s28 +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB79_2 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; SI-NEXT: s_waitcnt expcnt(6) -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_alignbit_b32 v0, v0, v3, 16 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4 -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v10 -; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; SI-NEXT: v_alignbit_b32 v2, v2, v8, 16 -; SI-NEXT: v_alignbit_b32 v3, v3, v9, 16 -; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16 -; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v58 -; SI-NEXT: s_waitcnt expcnt(5) -; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v56 -; SI-NEXT: s_waitcnt expcnt(4) -; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v44 -; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; SI-NEXT: v_alignbit_b32 v5, v5, v11, 16 -; SI-NEXT: v_alignbit_b32 v7, v7, v14, 16 -; SI-NEXT: v_alignbit_b32 v8, v8, v54, 16 -; SI-NEXT: v_alignbit_b32 v9, v9, v46, 16 -; SI-NEXT: v_mov_b32_e32 v62, v61 -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v61 -; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; SI-NEXT: v_mov_b32_e32 v60, v59 -; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v59 -; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; SI-NEXT: v_mov_b32_e32 v56, v47 -; SI-NEXT: v_alignbit_b32 v13, v13, v47, 16 -; SI-NEXT: v_mov_b32_e32 v46, v45 -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v45 -; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v12 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v57 -; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22 -; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23 -; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 -; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26 -; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28 -; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29 -; SI-NEXT: v_alignbit_b32 v30, v30, v31, 16 -; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v33 -; SI-NEXT: v_alignbit_b32 v4, v4, v34, 16 -; SI-NEXT: v_mov_b32_e32 v63, v44 -; SI-NEXT: v_mov_b32_e32 v58, v57 -; SI-NEXT: v_mov_b32_e32 v44, v43 -; SI-NEXT: v_alignbit_b32 v16, v16, v43, 16 -; SI-NEXT: v_mov_b32_e32 v43, v41 -; SI-NEXT: v_alignbit_b32 v17, v17, v41, 16 -; SI-NEXT: v_alignbit_b32 v18, v18, v40, 16 -; SI-NEXT: v_mov_b32_e32 v40, v55 -; SI-NEXT: v_alignbit_b32 v19, v19, v55, 16 -; SI-NEXT: v_alignbit_b32 v20, v20, v48, 16 -; SI-NEXT: v_mov_b32_e32 v48, v53 -; SI-NEXT: v_alignbit_b32 v21, v21, v53, 16 -; SI-NEXT: v_alignbit_b32 v22, v22, v52, 16 -; SI-NEXT: v_mov_b32_e32 v52, v51 -; SI-NEXT: v_alignbit_b32 v23, v23, v51, 16 -; SI-NEXT: v_alignbit_b32 v24, v24, v50, 16 -; SI-NEXT: v_mov_b32_e32 v50, v49 -; SI-NEXT: v_alignbit_b32 v25, v25, v49, 16 -; SI-NEXT: v_mov_b32_e32 v36, v39 -; SI-NEXT: v_alignbit_b32 v26, v26, v39, 16 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v34, v38 -; SI-NEXT: v_alignbit_b32 v27, v27, v38, 16 -; SI-NEXT: v_mov_b32_e32 v35, v37 -; SI-NEXT: v_alignbit_b32 v28, v28, v37, 16 -; SI-NEXT: v_mov_b32_e32 v37, v32 -; SI-NEXT: v_alignbit_b32 v29, v29, v32, 16 -; SI-NEXT: v_alignbit_b32 v31, v31, v42, 16 +; SI-NEXT: v_mov_b32_e32 v0, v19 +; SI-NEXT: v_mov_b32_e32 v37, v20 +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v25 +; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v33 +; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v7 +; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v63 +; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v57 +; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v61 +; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v23 +; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v44 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v21 +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 s[4:5], 0 -; SI-NEXT: v_mov_b32_e32 v32, v33 -; SI-NEXT: v_mov_b32_e32 v33, v42 -; SI-NEXT: s_waitcnt vmcnt(4) -; SI-NEXT: v_alignbit_b32 v10, v10, v61, 16 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_alignbit_b32 v12, v12, v54, 16 -; SI-NEXT: v_mov_b32_e32 v41, v61 +; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v1 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[0:1], v[19:20], 16 +; SI-NEXT: v_mov_b32_e32 v1, v48 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[1:2], v[48:49], 16 +; SI-NEXT: v_mov_b32_e32 v2, v14 +; SI-NEXT: v_mov_b32_e32 v49, v15 +; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v3 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[2:3], v[14:15], 16 +; SI-NEXT: v_mov_b32_e32 v3, v16 +; SI-NEXT: v_mov_b32_e32 v20, v17 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v35 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[3:4], v[16:17], 16 +; SI-NEXT: v_mov_b32_e32 v4, v18 +; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v5 +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[4:5], v[18:19], 16 +; SI-NEXT: v_mov_b32_e32 v5, v29 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[5:6], v[29:30], 16 +; SI-NEXT: v_mov_b32_e32 v6, v45 +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[6:7], v[45:46], 16 +; SI-NEXT: v_mov_b32_e32 v7, v39 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[7:8], v[39:40], 16 +; SI-NEXT: v_mov_b32_e32 v8, v9 +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v37 +; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v20 +; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v49 +; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[8:9], v[9:10], 16 +; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v9 +; SI-NEXT: v_mov_b32_e32 v9, v54 +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[9:10], v[54:55], 16 +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v55, v13 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v10 +; SI-NEXT: v_mov_b32_e32 v10, v11 +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[10:11], v[11:12], 16 +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v11 +; SI-NEXT: v_mov_b32_e32 v11, v56 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[11:12], v[56:57], 16 +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v56, v44 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v12 +; SI-NEXT: v_lshr_b64 v[12:13], v[13:14], 16 +; SI-NEXT: v_mov_b32_e32 v13, v58 +; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[13:14], v[58:59], 16 +; SI-NEXT: v_mov_b32_e32 v14, v60 +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[14:15], v[60:61], 16 +; SI-NEXT: v_mov_b32_e32 v15, v62 +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[15:16], v[62:63], 16 +; SI-NEXT: v_mov_b32_e32 v16, v32 +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[16:17], v[32:33], 16 +; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v27 +; SI-NEXT: v_mov_b32_e32 v33, v34 +; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_alignbit_b32 v11, v11, v59, 16 -; SI-NEXT: v_mov_b32_e32 v55, v59 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_alignbit_b32 v14, v14, v45, 16 +; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v17 +; SI-NEXT: v_mov_b32_e32 v40, v17 +; SI-NEXT: v_lshr_b64 v[17:18], v[34:35], 16 +; SI-NEXT: v_lshr_b64 v[18:19], v[47:48], 16 +; SI-NEXT: v_lshr_b64 v[19:20], v[36:37], 16 +; SI-NEXT: v_mov_b32_e32 v20, v38 +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[20:21], v[38:39], 16 +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; SI-NEXT: v_mov_b32_e32 v34, v47 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v21 +; SI-NEXT: v_mov_b32_e32 v21, v22 +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[21:22], v[22:23], 16 +; SI-NEXT: v_mov_b32_e32 v22, v31 +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[22:23], v[31:32], 16 +; SI-NEXT: v_mov_b32_e32 v23, v24 +; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[23:24], v[24:25], 16 +; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v52 +; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v30 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v24 +; SI-NEXT: v_mov_b32_e32 v24, v41 +; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[24:25], v[41:42], 16 +; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v41, v26 +; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v50 +; SI-NEXT: v_mov_b32_e32 v42, v51 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v25 +; SI-NEXT: v_lshr_b64 v[25:26], v[26:27], 16 +; SI-NEXT: v_mov_b32_e32 v26, v43 +; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[26:27], v[43:44], 16 +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v43, v28 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v27 +; SI-NEXT: v_lshr_b64 v[27:28], v[28:29], 16 +; SI-NEXT: v_lshr_b64 v[28:29], v[51:52], 16 +; SI-NEXT: v_lshr_b64 v[29:30], v[53:54], 16 +; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v52, v53 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v30 +; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshr_b64 v[30:31], v[31:32], 16 +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_alignbit_b32 v15, v15, v47, 16 -; SI-NEXT: v_mov_b32_e32 v51, v47 -; SI-NEXT: v_mov_b32_e32 v53, v45 +; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v57 +; SI-NEXT: v_mov_b32_e32 v53, v31 +; SI-NEXT: v_lshr_b64 v[31:32], v[31:32], 16 ; SI-NEXT: s_branch .LBB79_3 ; SI-NEXT: .LBB79_2: -; SI-NEXT: v_mov_b32_e32 v63, v44 -; SI-NEXT: v_mov_b32_e32 v44, v43 -; SI-NEXT: v_mov_b32_e32 v43, v41 -; SI-NEXT: v_mov_b32_e32 v40, v55 -; SI-NEXT: v_mov_b32_e32 v48, v53 -; SI-NEXT: v_mov_b32_e32 v52, v51 -; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload -; SI-NEXT: v_mov_b32_e32 v62, v61 -; SI-NEXT: v_mov_b32_e32 v60, v59 -; SI-NEXT: v_mov_b32_e32 v58, v57 -; SI-NEXT: v_mov_b32_e32 v56, v47 -; SI-NEXT: v_mov_b32_e32 v46, v45 -; SI-NEXT: v_mov_b32_e32 v50, v49 -; SI-NEXT: v_mov_b32_e32 v36, v39 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v34, v38 -; SI-NEXT: v_mov_b32_e32 v35, v37 -; SI-NEXT: v_mov_b32_e32 v37, v32 +; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill +; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v56, v44 +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v55, v13 +; SI-NEXT: s_waitcnt expcnt(2) +; SI-NEXT: v_mov_b32_e32 v33, v34 +; SI-NEXT: v_mov_b32_e32 v34, v47 +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_mov_b32_e32 v43, v28 +; SI-NEXT: v_mov_b32_e32 v52, v53 +; SI-NEXT: v_mov_b32_e32 v53, v0 ; SI-NEXT: s_mov_b64 s[4:5], -1 -; SI-NEXT: v_mov_b32_e32 v32, v33 -; SI-NEXT: v_mov_b32_e32 v33, v42 +; SI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_mov_b32_e32 v41, v26 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v42, v51 ; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 ; SI-NEXT: .LBB79_3: ; %Flow -; SI-NEXT: v_mov_b32_e32 v38, v50 -; SI-NEXT: v_mov_b32_e32 v39, v52 -; SI-NEXT: v_mov_b32_e32 v49, v40 -; SI-NEXT: v_mov_b32_e32 v50, v43 -; SI-NEXT: v_mov_b32_e32 v43, v44 -; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v37, v34 +; SI-NEXT: v_mov_b32_e32 v34, v33 +; SI-NEXT: v_mov_b32_e32 v35, v56 +; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: v_mov_b32_e32 v32, v40 +; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload ; SI-NEXT: s_andn2_b64 vcc, exec, s[4:5] +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_mov_b32_e32 v33, v38 +; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v51, v46 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v54, v46 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v44, v46 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v45, v56 +; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v47, v56 +; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_mov_b32_e32 v58, v60 +; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload ; SI-NEXT: s_cbranch_vccnz .LBB79_5 ; SI-NEXT: ; %bb.4: ; %cmp.true -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v44 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v57 +; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v61 +; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v49 ; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8 ; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v40 +; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v39 ; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 ; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v63 -; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 -; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v62 -; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 -; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v60 +; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v59 ; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 ; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v58 -; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 -; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v46 -; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 -; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32 +; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v40 +; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 +; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v35 +; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 +; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v32 +; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 +; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v53 ; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32 -; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 ; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 +; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16 -; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 -; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16 +; SI-NEXT: v_lshr_b64 v[1:2], v[2:3], 16 +; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v60 +; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 +; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 ; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 ; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 -; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; SI-NEXT: s_waitcnt vmcnt(13) ; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 ; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 ; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 -; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; SI-NEXT: s_waitcnt vmcnt(12) +; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 +; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; SI-NEXT: s_waitcnt vmcnt(8) +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; SI-NEXT: s_waitcnt vmcnt(7) +; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13 +; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15 ; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 ; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 ; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; SI-NEXT: s_waitcnt vmcnt(13) ; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 ; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 ; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; SI-NEXT: s_waitcnt vmcnt(12) -; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 -; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 -; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22 -; SI-NEXT: s_waitcnt vmcnt(10) -; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 -; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23 -; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 -; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; SI-NEXT: s_waitcnt vmcnt(8) -; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 -; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 -; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 -; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26 -; SI-NEXT: s_waitcnt vmcnt(6) -; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 -; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; SI-NEXT: s_waitcnt vmcnt(5) +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 +; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4 +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 +; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5 +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 ; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 ; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28 -; SI-NEXT: s_waitcnt vmcnt(4) +; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 ; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 +; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 ; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 +; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v26 ; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 -; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 -; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 -; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16 -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v58 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16 +; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v56 ; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 -; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16 -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16 +; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v47 ; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 -; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16 -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16 +; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v45 ; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 -; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16 -; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v45 +; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16 +; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v46 ; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 -; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16 -; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v42 +; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16 +; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v44 ; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8 -; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16 -; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v52 +; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16 +; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v54 ; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 -; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16 -; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v41 +; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16 +; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v51 ; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 -; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16 -; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v55 +; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16 +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v50 ; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 -; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16 -; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v54 +; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16 +; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v55 ; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 -; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16 -; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v56 +; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16 +; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v48 ; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 -; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16 -; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v53 +; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16 +; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v38 ; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 -; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16 -; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v51 +; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16 +; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v33 ; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 -; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16 -; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v43 +; SI-NEXT: v_lshr_b64 v[15:16], v[15:16], 16 +; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 +; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 ; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; SI-NEXT: v_alignbit_b32 v16, v17, v16, 16 -; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v50 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 ; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 -; SI-NEXT: v_alignbit_b32 v17, v18, v17, 16 -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 +; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; SI-NEXT: v_lshr_b64 v[16:17], v[16:17], 16 +; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v34 +; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 +; SI-NEXT: v_lshr_b64 v[17:18], v[17:18], 16 +; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v37 ; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; SI-NEXT: v_alignbit_b32 v18, v19, v18, 16 -; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v49 +; SI-NEXT: v_lshr_b64 v[18:19], v[18:19], 16 +; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v36 ; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 -; SI-NEXT: v_alignbit_b32 v19, v20, v19, 16 -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshr_b64 v[19:20], v[19:20], 16 +; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v33 +; SI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; SI-NEXT: v_lshr_b64 v[32:33], v[32:33], 16 +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 ; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 -; SI-NEXT: v_alignbit_b32 v20, v21, v20, 16 -; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v48 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 +; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 +; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; SI-NEXT: v_lshr_b64 v[20:21], v[20:21], 16 +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 ; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 -; SI-NEXT: v_alignbit_b32 v21, v22, v21, 16 -; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 ; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 -; SI-NEXT: v_alignbit_b32 v22, v23, v22, 16 -; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v39 +; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; SI-NEXT: v_lshr_b64 v[21:22], v[21:22], 16 +; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 +; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 +; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 +; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; SI-NEXT: v_lshr_b64 v[22:23], v[22:23], 16 +; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 ; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 -; SI-NEXT: v_alignbit_b32 v23, v24, v23, 16 -; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 ; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 -; SI-NEXT: v_alignbit_b32 v24, v25, v24, 16 -; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v38 +; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; SI-NEXT: v_lshr_b64 v[23:24], v[23:24], 16 +; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 ; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 -; SI-NEXT: v_alignbit_b32 v25, v26, v25, 16 -; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v36 +; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; SI-NEXT: v_lshr_b64 v[24:25], v[24:25], 16 +; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v41 +; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 +; SI-NEXT: v_lshr_b64 v[25:26], v[25:26], 16 +; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 ; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 -; SI-NEXT: v_alignbit_b32 v26, v27, v26, 16 -; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v34 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 ; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 -; SI-NEXT: v_alignbit_b32 v27, v28, v27, 16 -; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v35 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; SI-NEXT: v_lshr_b64 v[26:27], v[26:27], 16 +; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v43 +; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 +; SI-NEXT: v_lshr_b64 v[27:28], v[27:28], 16 +; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v42 ; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 -; SI-NEXT: v_alignbit_b32 v28, v29, v28, 16 -; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v37 +; SI-NEXT: v_lshr_b64 v[28:29], v[28:29], 16 +; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v52 ; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 -; SI-NEXT: v_alignbit_b32 v29, v30, v29, 16 -; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshr_b64 v[29:30], v[29:30], 16 +; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 ; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 -; SI-NEXT: v_alignbit_b32 v30, v31, v30, 16 -; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v33 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 ; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 -; SI-NEXT: v_alignbit_b32 v31, v32, v31, 16 +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31 +; SI-NEXT: v_lshr_b64 v[30:31], v[30:31], 16 +; SI-NEXT: v_mov_b32_e32 v31, v32 ; SI-NEXT: .LBB79_5: ; %end ; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload @@ -137753,36 +135682,39 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg ; VI-NEXT: v_mov_b32_e32 v31, v17 ; VI-NEXT: v_mov_b32_e32 v30, v16 ; VI-NEXT: v_mov_b32_e32 v29, v15 -; VI-NEXT: v_mov_b32_e32 v28, v14 ; VI-NEXT: v_mov_b32_e32 v27, v13 -; VI-NEXT: v_mov_b32_e32 v26, v12 ; VI-NEXT: v_mov_b32_e32 v25, v11 -; VI-NEXT: v_mov_b32_e32 v24, v10 ; VI-NEXT: v_mov_b32_e32 v23, v9 -; VI-NEXT: v_mov_b32_e32 v22, v8 ; VI-NEXT: v_mov_b32_e32 v21, v7 -; VI-NEXT: v_mov_b32_e32 v20, v6 ; VI-NEXT: v_mov_b32_e32 v19, v5 -; VI-NEXT: v_mov_b32_e32 v32, v4 ; VI-NEXT: v_mov_b32_e32 v17, v3 -; VI-NEXT: v_mov_b32_e32 v16, v2 ; VI-NEXT: v_mov_b32_e32 v15, v1 +; VI-NEXT: v_mov_b32_e32 v28, v14 +; VI-NEXT: v_mov_b32_e32 v26, v12 +; VI-NEXT: v_mov_b32_e32 v24, v10 +; VI-NEXT: v_mov_b32_e32 v22, v8 +; VI-NEXT: v_mov_b32_e32 v20, v6 +; VI-NEXT: v_mov_b32_e32 v32, v4 +; VI-NEXT: v_mov_b32_e32 v16, v2 ; VI-NEXT: v_mov_b32_e32 v14, v0 -; VI-NEXT: v_mov_b32_e32 v0, s16 -; VI-NEXT: v_mov_b32_e32 v1, s17 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec -; VI-NEXT: v_mov_b32_e32 v2, s18 +; VI-NEXT: v_mov_b32_e32 v1, s17 ; VI-NEXT: v_mov_b32_e32 v3, s19 -; VI-NEXT: v_mov_b32_e32 v4, s20 ; VI-NEXT: v_mov_b32_e32 v5, s21 -; VI-NEXT: v_mov_b32_e32 v6, s22 ; VI-NEXT: v_mov_b32_e32 v7, s23 -; VI-NEXT: v_mov_b32_e32 v8, s24 ; VI-NEXT: v_mov_b32_e32 v9, s25 -; VI-NEXT: v_mov_b32_e32 v10, s26 ; VI-NEXT: v_mov_b32_e32 v11, s27 -; VI-NEXT: v_mov_b32_e32 v12, s28 ; VI-NEXT: v_mov_b32_e32 v13, s29 +; VI-NEXT: v_mov_b32_e32 v0, s16 +; VI-NEXT: v_mov_b32_e32 v2, s18 +; VI-NEXT: v_mov_b32_e32 v4, s20 +; VI-NEXT: v_mov_b32_e32 v6, s22 +; VI-NEXT: v_mov_b32_e32 v8, s24 +; VI-NEXT: v_mov_b32_e32 v10, s26 +; VI-NEXT: v_mov_b32_e32 v12, s28 +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: s_cbranch_scc0 .LBB79_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_cbranch_execnz .LBB79_3 @@ -137791,580 +135723,600 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg ; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 ; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 ; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 ; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 ; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v15, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v15 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_bfe_u32 v18, v15, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc +; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15 +; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18 ; VI-NEXT: v_or_b32_e32 v34, 0x400000, v15 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 -; VI-NEXT: v_cndmask_b32_e32 v15, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; VI-NEXT: v_alignbit_b32 v15, v15, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v14 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v15, v18, v34, vcc +; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v15 +; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v14 +; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; VI-NEXT: v_bfe_u32 v18, v15, 16, 1 +; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15 ; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18 ; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v14, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v14 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v14 +; VI-NEXT: v_lshrrev_b64 v[34:35], 16, v[33:34] +; VI-NEXT: v_or_b32_e32 v33, 0x400000, v15 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 +; VI-NEXT: v_bfe_u32 v15, v14, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v35, v18, v33, vcc +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v14 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 +; VI-NEXT: v_or_b32_e32 v18, 0x400000, v14 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 -; VI-NEXT: v_cndmask_b32_e32 v14, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; VI-NEXT: v_alignbit_b32 v14, v14, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v13 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v14, v15, v18, vcc +; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v14 +; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[35:36] +; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v13 +; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; VI-NEXT: v_bfe_u32 v18, v15, 16, 1 +; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15 ; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18 ; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v13, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v13 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v13 +; VI-NEXT: v_or_b32_e32 v33, 0x400000, v15 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 +; VI-NEXT: v_bfe_u32 v15, v13, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v35, v18, v33, vcc +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 +; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 -; VI-NEXT: v_cndmask_b32_e32 v13, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; VI-NEXT: v_alignbit_b32 v13, v13, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v12 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v13, v15, v18, vcc +; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v13 +; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v12 +; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; VI-NEXT: v_bfe_u32 v15, v13, 16, 1 +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13 ; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 ; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v12, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v12 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v12 +; VI-NEXT: v_lshrrev_b64 v[35:36], 16, v[35:36] +; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 +; VI-NEXT: v_bfe_u32 v13, v12, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v36, v15, v18, vcc +; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v12 +; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 +; VI-NEXT: v_or_b32_e32 v15, 0x400000, v12 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 -; VI-NEXT: v_cndmask_b32_e32 v12, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; VI-NEXT: v_alignbit_b32 v12, v12, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v11 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v12, v13, v15, vcc +; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v12 +; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[36:37] +; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v11 +; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; VI-NEXT: v_bfe_u32 v15, v13, 16, 1 +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13 ; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 ; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v11, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v11 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v11 +; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 +; VI-NEXT: v_bfe_u32 v13, v11, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v36, v15, v18, vcc +; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11 +; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 +; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 -; VI-NEXT: v_cndmask_b32_e32 v11, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; VI-NEXT: v_alignbit_b32 v11, v11, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v10 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v11, v13, v15, vcc +; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v11 +; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; VI-NEXT: v_bfe_u32 v13, v11, 16, 1 +; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11 ; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 ; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v10, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v10 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v10 +; VI-NEXT: v_lshrrev_b64 v[36:37], 16, v[36:37] +; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 +; VI-NEXT: v_bfe_u32 v11, v10, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v37, v13, v15, vcc +; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v10 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 +; VI-NEXT: v_or_b32_e32 v13, 0x400000, v10 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 -; VI-NEXT: v_cndmask_b32_e32 v10, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; VI-NEXT: v_alignbit_b32 v10, v10, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v9 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v10, v11, v13, vcc +; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v10 +; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[37:38] +; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v9 +; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; VI-NEXT: v_bfe_u32 v13, v11, 16, 1 +; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11 ; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 ; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v9, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v9 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v9 +; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 +; VI-NEXT: v_bfe_u32 v11, v9, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v37, v13, v15, vcc +; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 +; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 -; VI-NEXT: v_cndmask_b32_e32 v9, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; VI-NEXT: v_alignbit_b32 v9, v9, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v8 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc +; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9 +; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v8 +; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 +; VI-NEXT: v_bfe_u32 v11, v9, 16, 1 +; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9 ; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 ; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v8, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v8 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v8 +; VI-NEXT: v_lshrrev_b64 v[37:38], 16, v[37:38] +; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 +; VI-NEXT: v_bfe_u32 v9, v8, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v38, v11, v13, vcc +; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9 +; VI-NEXT: v_or_b32_e32 v11, 0x400000, v8 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8 -; VI-NEXT: v_cndmask_b32_e32 v8, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; VI-NEXT: v_alignbit_b32 v8, v8, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v7 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v8, v9, v11, vcc +; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v8 +; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[38:39] +; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v7 +; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 +; VI-NEXT: v_bfe_u32 v11, v9, 16, 1 +; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9 ; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 ; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v7, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v7 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v7 +; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 +; VI-NEXT: v_bfe_u32 v9, v7, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v38, v11, v13, vcc +; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9 +; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 -; VI-NEXT: v_cndmask_b32_e32 v7, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; VI-NEXT: v_alignbit_b32 v7, v7, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v6 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v7, v9, v11, vcc +; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v7 +; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v6 +; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 +; VI-NEXT: v_bfe_u32 v9, v7, 16, 1 +; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7 ; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9 ; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v6, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v6 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v6 +; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 +; VI-NEXT: v_bfe_u32 v7, v6, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v48, v9, v11, vcc +; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v6 +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7 +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v6 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; VI-NEXT: v_cndmask_b32_e32 v6, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; VI-NEXT: v_alignbit_b32 v6, v6, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v5 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v6, v7, v9, vcc +; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v6 +; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[48:49] +; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v5 +; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 +; VI-NEXT: v_bfe_u32 v9, v7, 16, 1 +; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7 ; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9 ; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v5, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v5 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v5 +; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 +; VI-NEXT: v_bfe_u32 v7, v5, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v48, v9, v11, vcc +; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5 +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7 +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; VI-NEXT: v_cndmask_b32_e32 v5, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; VI-NEXT: v_alignbit_b32 v5, v5, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v4 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v5, v7, v9, vcc +; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v5 +; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v4 +; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 +; VI-NEXT: v_bfe_u32 v7, v5, 16, 1 +; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5 ; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7 ; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v4, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v4 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v4 +; VI-NEXT: v_lshrrev_b64 v[48:49], 16, v[48:49] +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 +; VI-NEXT: v_bfe_u32 v5, v4, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v49, v7, v9, vcc +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v4 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; VI-NEXT: v_cndmask_b32_e32 v4, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; VI-NEXT: v_alignbit_b32 v4, v4, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v3 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc +; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v4 +; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[49:50] +; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v3 +; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 +; VI-NEXT: v_bfe_u32 v7, v5, 16, 1 +; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5 ; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7 ; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v3, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v3 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v3 +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v49, v7, v9, vcc +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; VI-NEXT: v_cndmask_b32_e32 v3, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; VI-NEXT: v_alignbit_b32 v3, v3, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v2 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v3 +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 ; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 ; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v2 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v2 +; VI-NEXT: v_lshrrev_b64 v[49:50], 16, v[49:50] +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v50, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: v_alignbit_b32 v2, v2, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v1 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v2 +; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[50:51] +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v1 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 ; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 ; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v1 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v50, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; VI-NEXT: v_alignbit_b32 v1, v1, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v0 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 ; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v0, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v0 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v0 +; VI-NEXT: v_lshrrev_b64 v[50:51], 16, v[50:51] +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_bfe_u32 v1, v0, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v51, v3, v5, vcc +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1 +; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; VI-NEXT: v_cndmask_b32_e32 v0, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; VI-NEXT: v_alignbit_b32 v0, v0, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v31 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v31, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v31 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v31 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31 -; VI-NEXT: v_cndmask_b32_e32 v31, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; VI-NEXT: v_alignbit_b32 v31, v31, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v30 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v30, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v30 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v30 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 -; VI-NEXT: v_cndmask_b32_e32 v30, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; VI-NEXT: v_alignbit_b32 v30, v30, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v29 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v29, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v29 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v29 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 -; VI-NEXT: v_cndmask_b32_e32 v29, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v29 -; VI-NEXT: v_alignbit_b32 v29, v29, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v28 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v28, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v28 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v28 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 -; VI-NEXT: v_cndmask_b32_e32 v28, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v28 -; VI-NEXT: v_alignbit_b32 v28, v28, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v27 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v27, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v27 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v27 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 -; VI-NEXT: v_cndmask_b32_e32 v27, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; VI-NEXT: v_alignbit_b32 v27, v27, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v26 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v26, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v26 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v26 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 -; VI-NEXT: v_cndmask_b32_e32 v26, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v26 -; VI-NEXT: v_alignbit_b32 v26, v26, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v25 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v25, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v25 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v25 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 -; VI-NEXT: v_cndmask_b32_e32 v25, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 -; VI-NEXT: v_alignbit_b32 v25, v25, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v24 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v24, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v24 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v24 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; VI-NEXT: v_cndmask_b32_e32 v24, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; VI-NEXT: v_alignbit_b32 v24, v24, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v23 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v23, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v23 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v23 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 -; VI-NEXT: v_cndmask_b32_e32 v23, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v23 -; VI-NEXT: v_alignbit_b32 v23, v23, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v22 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v22, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v22 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v22 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 -; VI-NEXT: v_cndmask_b32_e32 v22, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v22 -; VI-NEXT: v_alignbit_b32 v22, v22, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v21 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v21, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v21 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v21 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 -; VI-NEXT: v_cndmask_b32_e32 v21, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; VI-NEXT: v_alignbit_b32 v21, v21, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v20 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v20, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v20 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v20 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 -; VI-NEXT: v_cndmask_b32_e32 v20, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; VI-NEXT: v_alignbit_b32 v20, v20, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v19 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v19, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v19 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v19 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 -; VI-NEXT: v_cndmask_b32_e32 v19, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; VI-NEXT: v_alignbit_b32 v19, v19, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v32 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v32, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 -; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; VI-NEXT: v_alignbit_b32 v32, v32, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v17 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v17, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v17 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v17 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 -; VI-NEXT: v_cndmask_b32_e32 v17, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; VI-NEXT: v_alignbit_b32 v17, v17, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v16 -; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v16, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v16 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v16 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16 -; VI-NEXT: v_cndmask_b32_e32 v16, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; VI-NEXT: v_alignbit_b32 v16, v16, v18, 16 +; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc +; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v0 +; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[51:52] +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v31 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v31 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v51, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v30 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v30 +; VI-NEXT: v_lshrrev_b64 v[51:52], 16, v[51:52] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v52, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v29 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v29 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[30:31], 16, v[52:53] +; VI-NEXT: v_cndmask_b32_e32 v52, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v28 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v28 +; VI-NEXT: v_lshrrev_b64 v[52:53], 16, v[52:53] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v53, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v27 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v27 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[28:29], 16, v[53:54] +; VI-NEXT: v_cndmask_b32_e32 v53, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v26 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v26 +; VI-NEXT: v_lshrrev_b64 v[53:54], 16, v[53:54] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v54, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v25 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v25 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[26:27], 16, v[54:55] +; VI-NEXT: v_cndmask_b32_e32 v54, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v24 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v24 +; VI-NEXT: v_lshrrev_b64 v[38:39], 16, v[38:39] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v39, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v23 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v23 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[24:25], 16, v[39:40] +; VI-NEXT: v_cndmask_b32_e32 v39, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v22 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v22 +; VI-NEXT: v_lshrrev_b64 v[39:40], 16, v[39:40] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v40, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v21 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v21 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[22:23], 16, v[40:41] +; VI-NEXT: v_cndmask_b32_e32 v40, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v20 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v20 +; VI-NEXT: v_lshrrev_b64 v[40:41], 16, v[40:41] +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v41, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v19 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v19 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v18, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v32 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v32 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v31, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v17 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v17 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b64 v[20:21], 16, v[41:42] +; VI-NEXT: v_cndmask_b32_e32 v41, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v16 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v16 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v15, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshrrev_b64 v[54:55], 16, v[54:55] +; VI-NEXT: v_lshrrev_b64 v[18:19], 16, v[18:19] +; VI-NEXT: v_lshrrev_b64 v[41:42], 16, v[41:42] +; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v1 +; VI-NEXT: v_lshrrev_b64 v[32:33], 16, v[31:32] +; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[15:16] +; VI-NEXT: v_mov_b32_e32 v1, v50 +; VI-NEXT: v_mov_b32_e32 v3, v49 +; VI-NEXT: v_mov_b32_e32 v5, v48 +; VI-NEXT: v_mov_b32_e32 v7, v38 +; VI-NEXT: v_mov_b32_e32 v9, v37 +; VI-NEXT: v_mov_b32_e32 v11, v36 +; VI-NEXT: v_mov_b32_e32 v13, v35 +; VI-NEXT: v_mov_b32_e32 v15, v34 +; VI-NEXT: v_mov_b32_e32 v17, v41 +; VI-NEXT: v_mov_b32_e32 v19, v18 +; VI-NEXT: v_mov_b32_e32 v21, v40 +; VI-NEXT: v_mov_b32_e32 v23, v39 +; VI-NEXT: v_mov_b32_e32 v25, v54 +; VI-NEXT: v_mov_b32_e32 v27, v53 +; VI-NEXT: v_mov_b32_e32 v29, v52 +; VI-NEXT: v_mov_b32_e32 v31, v51 ; VI-NEXT: .LBB79_3: ; %end +; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload ; VI-NEXT: v_mov_b32_e32 v18, v32 +; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_setpc_b64 s[30:31] ; VI-NEXT: .LBB79_4: ; VI-NEXT: s_branch .LBB79_2 @@ -139029,100 +136981,26 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 -; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:280 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:252 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:156 -; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v156, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v157, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v158, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v159, s32 offset:28 -; GFX11-TRUE16-NEXT: s_clause 0x6 ; 28-byte Folded Spill -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v168, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v169, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v170, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v171, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v172, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v173, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v174, s32 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v167, v13 :: v_dual_mov_b32 v176, v12 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v177, v11 :: v_dual_mov_b32 v178, v10 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v179, v9 :: v_dual_mov_b32 v180, v8 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v181, v7 :: v_dual_mov_b32 v182, v6 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v183, v5 :: v_dual_mov_b32 v168, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v169, v3 :: v_dual_mov_b32 v170, v2 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v171, v1 :: v_dual_mov_b32 v172, v0 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v174, s28 :: v_dual_mov_b32 v173, s29 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, v13 :: v_dual_mov_b32 v30, v12 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 ; GFX11-TRUE16-NEXT: s_mov_b32 s4, 0 ; GFX11-TRUE16-NEXT: s_and_b32 s5, vcc_lo, exec_lo ; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB79_4 ; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v135, s0 :: v_dual_mov_b32 v134, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v132, s2 :: v_dual_mov_b32 v129, s3 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v125, s16 :: v_dual_mov_b32 v120, s17 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v114, s18 :: v_dual_mov_b32 v107, s19 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v99, s20 :: v_dual_mov_b32 v90, s21 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v80, s22 :: v_dual_mov_b32 v69, s23 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v57, s24 :: v_dual_mov_b32 v44, s25 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, s26 :: v_dual_mov_b32 v15, s27 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 +; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 ; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4 ; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB79_3 ; GFX11-TRUE16-NEXT: .LBB79_2: ; %cmp.true @@ -139133,972 +137011,674 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg ; GFX11-TRUE16-NEXT: s_and_b32 s4, s26, 0xffff0000 ; GFX11-TRUE16-NEXT: s_lshl_b32 s6, s26, 16 ; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v1, 16, 1 +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1 ; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v1 +; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s6 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v3 ; GFX11-TRUE16-NEXT: s_and_b32 s5, s25, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s7, s25, 16 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s6 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0 ; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s5 -; GFX11-TRUE16-NEXT: s_and_b32 s4, s24, 0xffff0000 +; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s25, 16 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v8 :: v_dual_add_nc_u32 v7, v7, v3 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v7, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v3 -; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s7 -; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v9, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v3 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v6, 16, 1 ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v4 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7 -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s24, 16 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v7, v2 :: v_dual_add_nc_u32 v7, v8, v5 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v9, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v4 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v7 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v6 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v6 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: s_and_b32 s4, s24, 0xffff0000 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v10, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc_lo +; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v6 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v3 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1 +; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s24, 16 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v7, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v9, v5 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v7 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v7 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v6 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v3 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v1.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 16, v2 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v44.h, v4.l -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s23, 0xffff0000 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v57.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s23, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s22, 0xffff0000 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v1.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s22, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v9 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v0.l +; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s21, 0xffff0000 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s21, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s21, 16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3 +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v6 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s20, 0xffff0000 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v90, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v90.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s20, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s19, 0xffff0000 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v1.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8 ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v32 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v32, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s19, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v32 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v0.l +; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s18, 0xffff0000 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v107, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v107.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s18, 16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3 +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v6 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s17, 0xffff0000 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s17, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: s_and_b32 s4, s16, 0xffff0000 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v32, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v32 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v4 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v1.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v32 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v3, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 +; GFX11-TRUE16-NEXT: s_and_b32 s4, s16, 0xffff0000 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v33, v3 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v120, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v120.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v34, 16, 1 ; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s16, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 ; GFX11-TRUE16-NEXT: s_and_b32 s4, s3, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v125, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v125.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s3 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s4 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v32, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16 +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v33, 16, 1 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s3 ; GFX11-TRUE16-NEXT: s_and_b32 s3, s2, 0xffff0000 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v35, v32 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v35, 0x40c00000, s3 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v32 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v33 +; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v35, 16, 1 ; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v34 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v1.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v32, v35 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s2 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v34 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s3 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s2 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 ; GFX11-TRUE16-NEXT: s_and_b32 s2, s1, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s2 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1 -; GFX11-TRUE16-NEXT: s_and_b32 s1, s0, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v134.h, v0.l -; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v167 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v167 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 16, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v167.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v176 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v176 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v176.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v177 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v177 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v177.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v178 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v178 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v178, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v179 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v179 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v179.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v180 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v180 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v180.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v181 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v181 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v181.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v182 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v182 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v37, 0x40c00000, s2 +; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v32, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 ; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v182.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v183 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v183 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v183.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v168 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v168 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v168, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v168.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v169 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v169 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v169, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v169.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v170 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v170 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v170, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v170.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v171 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v171 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v171, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v171.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v172 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v172 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v172, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v172.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v173 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v173 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v37, 16, 1 +; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v33, vcc_lo +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, v36, v32 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v34, v37 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s1 +; GFX11-TRUE16-NEXT: s_and_b32 s1, s0, 0xffff0000 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v0.l +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v32 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v35, 0x40c00000, s1 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v173, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v173.h, v0.l -; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v174 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v33, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v2, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, v38, v34 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v32, v35 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v31 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v36 +; GFX11-TRUE16-NEXT: v_add_f32_e64 v36, 0x40c00000, s0 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v33, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v36, 16, 1 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v36 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v37 :: v_dual_add_nc_u32 v33, v33, v36 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v32.l +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v30 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v0 +; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v33, v33, v35 :: v_dual_add_nc_u32 v0, v0, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v0 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v33 +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v32.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v34, v36, v37 :: v_dual_add_f32 v31, 0x40c00000, v31 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v33, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v31, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, v38, v31 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v29 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v29 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v36 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v31 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v30, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v30 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v34, v30 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_and_b32 v37, 0xffff0000, v28 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v33.l +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v30, v34, v36 :: v_dual_add_nc_u32 v33, v33, v35 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v29, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v30 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_dual_add_f32 v28, 0x40c00000, v28 :: v_dual_add_nc_u32 v35, v37, v29 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v32.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v33, v33, v36 :: v_dual_add_nc_u32 v32, v38, v34 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v29 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v27 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v35, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v28, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v28 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_add_nc_u32 v35, v35, v28 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v26 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v33.l +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX11-TRUE16-NEXT: v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_add_f32 v27, 0x40c00000, v27 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, v33, v34 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v28, v35, v36 :: v_dual_add_f32 v35, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v27, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v37, v27 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v32.l +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v27 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v38, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v25 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v26, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v26 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v34, v26 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_and_b32 v37, 0xffff0000, v24 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v33.l +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_add_f32 v25, 0x40c00000, v25 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v32.l +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v25, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v38, v34 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v23 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, v33, v35 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, v37, v25 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v25 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v35, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v24, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v24 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v33.l +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_and_b32 v37, 0xffff0000, v22 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, v35, v24 +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v174 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v24, v35, v36 :: v_dual_add_nc_u32 v33, v33, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v23, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v37, v23 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v32.l +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v23 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v38, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v21 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v22, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v22 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v34, v22 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_and_b32 v37, 0xffff0000, v20 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v33.l +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, v33, v35 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v32.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v38, v34 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v19 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v21, 16, 1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v21 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, v37, v21 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v174, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v174.h, v0.l +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v35, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v20, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v38 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v20 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_add_nc_u32 v35, v35, v20 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v33.l +; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v34, 16, 1 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v18 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, v33, v34 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v20, v35, v36 :: v_dual_add_f32 v35, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v19, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v35, 16, 1 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v37, v19 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v19 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v32.l +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v38, v35 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v17 +; GFX11-TRUE16-NEXT: v_bfe_u32 v39, v18, 16, 1 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v34, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v35 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, v39, v18 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v33.l +; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v34, 16, 1 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v32, v32, v38 :: v_dual_add_nc_u32 v33, 0x7fff, v35 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v18 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v16 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, v36, v34 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_lshlrev_b32 v16, 16, v16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v33, v35 :: v_dual_add_f32 v33, 0x40c00000, v37 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v36 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v17, 16, 1 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v33, 16, 1 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v39, 0x400000, v17 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v35, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, v37, v17 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, v38, v33 +; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v16, 16, 1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v33 +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 0x7fff, v37 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, v35, v16 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v48, 0x400000, v16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v32.l +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v37, v38, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v36, v39, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v35, v48, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v34.l +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v33.l ; GFX11-TRUE16-NEXT: .LBB79_3: ; %end -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v125 :: v_dual_mov_b32 v5, v120 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v114 :: v_dual_mov_b32 v7, v107 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v99 :: v_dual_mov_b32 v9, v90 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v57 :: v_dual_mov_b32 v13, v44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v30 :: v_dual_mov_b32 v17, v173 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, v174 :: v_dual_mov_b32 v19, v171 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v172 :: v_dual_mov_b32 v21, v169 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, v170 :: v_dual_mov_b32 v23, v183 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, v168 :: v_dual_mov_b32 v25, v181 -; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-TRUE16-NEXT: scratch_load_b32 v174, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v173, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v172, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v171, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v170, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v169, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v168, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v159, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v158, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v157, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v156, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:252 -; GFX11-TRUE16-NEXT: s_clause 0x6 ; 28-byte Folded Reload -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:256 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:260 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:264 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:268 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:272 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:276 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:280 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v135 :: v_dual_mov_b32 v1, v134 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v132 :: v_dual_mov_b32 v3, v129 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v80 :: v_dual_mov_b32 v11, v69 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v24, v182 :: v_dual_mov_b32 v27, v179 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v180 :: v_dual_mov_b32 v29, v177 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v178 :: v_dual_mov_b32 v31, v167 -; GFX11-TRUE16-NEXT: v_mov_b32_e32 v30, v176 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-TRUE16-NEXT: .LBB79_4: -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0 ; GFX11-TRUE16-NEXT: s_branch .LBB79_2 ; ; GFX11-FAKE16-LABEL: bitcast_v64bf16_to_v16f64_scalar: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 -; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:288 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:284 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:280 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:276 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v44, s32 offset:272 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v45, s32 offset:268 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v46, s32 offset:264 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v47, s32 offset:260 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v56, s32 offset:256 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v57, s32 offset:252 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v58, s32 offset:248 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v59, s32 offset:244 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v60, s32 offset:240 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v61, s32 offset:236 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v62, s32 offset:232 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v63, s32 offset:228 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v72, s32 offset:224 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v73, s32 offset:220 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v74, s32 offset:216 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v75, s32 offset:212 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v76, s32 offset:208 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v77, s32 offset:204 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v78, s32 offset:200 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v79, s32 offset:196 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v88, s32 offset:192 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v89, s32 offset:188 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v90, s32 offset:184 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v91, s32 offset:180 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v92, s32 offset:176 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v93, s32 offset:172 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v94, s32 offset:168 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v95, s32 offset:164 -; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v104, s32 offset:160 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v105, s32 offset:156 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v106, s32 offset:152 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v107, s32 offset:148 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v108, s32 offset:144 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v109, s32 offset:140 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v110, s32 offset:136 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v111, s32 offset:132 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v120, s32 offset:128 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v121, s32 offset:124 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v122, s32 offset:120 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v123, s32 offset:116 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v124, s32 offset:112 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v125, s32 offset:108 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v126, s32 offset:104 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v127, s32 offset:100 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v136, s32 offset:96 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v137, s32 offset:92 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v138, s32 offset:88 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v139, s32 offset:84 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v140, s32 offset:80 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v141, s32 offset:76 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v142, s32 offset:72 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v143, s32 offset:68 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v152, s32 offset:64 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v153, s32 offset:60 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v154, s32 offset:56 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v155, s32 offset:52 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v156, s32 offset:48 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v157, s32 offset:44 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v158, s32 offset:40 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v159, s32 offset:36 -; GFX11-FAKE16-NEXT: s_clause 0x8 ; 36-byte Folded Spill -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v168, s32 offset:32 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v169, s32 offset:28 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v170, s32 offset:24 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v171, s32 offset:20 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v172, s32 offset:16 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v173, s32 offset:12 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v174, s32 offset:8 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v175, s32 offset:4 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v184, s32 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v178, v13 :: v_dual_mov_b32 v179, v12 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v180, v11 :: v_dual_mov_b32 v181, v9 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v182, v10 :: v_dual_mov_b32 v169, v7 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v170, v8 :: v_dual_mov_b32 v177, v3 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v176, v6 :: v_dual_mov_b32 v171, v4 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v174, v5 :: v_dual_mov_b32 v173, v0 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v184, v2 :: v_dual_mov_b32 v175, v1 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v183, s28 :: v_dual_mov_b32 v172, s29 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v13 :: v_dual_mov_b32 v30, v12 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 ; GFX11-FAKE16-NEXT: s_mov_b32 s4, 0 ; GFX11-FAKE16-NEXT: s_and_b32 s5, vcc_lo, exec_lo ; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB79_4 ; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, s0 :: v_dual_mov_b32 v37, s2 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, s1 :: v_dual_mov_b32 v41, s3 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v46, s16 :: v_dual_mov_b32 v59, s18 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, s17 :: v_dual_mov_b32 v67, s19 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v76, s20 :: v_dual_mov_b32 v97, s22 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v86, s21 :: v_dual_mov_b32 v109, s23 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v122, s24 :: v_dual_mov_b32 v151, s26 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v136, s25 :: v_dual_mov_b32 v15, s27 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 ; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4 ; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB79_3 ; GFX11-FAKE16-NEXT: .LBB79_2: ; %cmp.true @@ -140106,762 +137686,674 @@ define inreg <16 x double> @bitcast_v64bf16_to_v16f64_scalar(<64 x bfloat> inreg ; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s27, 16 ; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s5 ; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s26, 16 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s26, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s6 +; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s26, 16 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 ; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1 ; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s6 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s4 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1 +; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1 ; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0 -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1 -; GFX11-FAKE16-NEXT: s_lshl_b32 s7, s25, 16 +; GFX11-FAKE16-NEXT: s_and_b32 s5, s25, 0xffff0000 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0 -; GFX11-FAKE16-NEXT: s_and_b32 s5, s25, 0xffff0000 -; GFX11-FAKE16-NEXT: s_and_b32 s4, s24, 0xffff0000 ; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s5 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v183 +; GFX11-FAKE16-NEXT: s_lshl_b32 s7, s25, 16 +; GFX11-FAKE16-NEXT: s_and_b32 s4, s24, 0xffff0000 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s24, 16 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v9, v3 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v5 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v9, v3 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v6, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v7, vcc_lo +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v7 :: v_dual_add_nc_u32 v2, 0x7fff, v2 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v5 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s7 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v3 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 +; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v6, 16, 1 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v8, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v1, 16, v0 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v3, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v10, v6 +; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v1, 16, v0 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v5, v6 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v7, v9, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s23, 16 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v0, 16, v1 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 ; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s24, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v4 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v6 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v8 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s23, 0xffff0000 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo ; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v5 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v9 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v1, v7 :: v_dual_and_b32 v1, 0xffff, v2 -; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v9, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v6 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v7, v9 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s23, 16 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v151, v0, 16, v1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6 -; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v7, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v4, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: s_and_b32 s4, s22, 0xffff0000 -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v12, 16, 1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v11, v7 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v3 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s22, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v5 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v6 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v8 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v9, v12 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v10, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v12 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s22, 16 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1 +; GFX11-FAKE16-NEXT: s_and_b32 s4, s22, 0xffff0000 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6 +; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s21, 0xffff0000 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v6, v9, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v11, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v14, v10 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v5 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v7 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v8, v13 :: v_dual_add_nc_u32 v7, v9, v11 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v12 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v10 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s21, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v11 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v13, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v16, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s21, 16 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 +; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s20, 0xffff0000 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v7, v14 :: v_dual_add_nc_u32 v10, v10, v13 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v8 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v13 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v11 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v12, v16 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s20, 16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11 -; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v12, 16, 1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v10, v14, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s20, 16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6 +; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s19, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, v18, v12 -; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v17, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s19, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v13 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v14 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, v16, v19 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v12 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v14 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s19, 16 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 +; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s18, 0xffff0000 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v16, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, v21, v17 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v11 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v13 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v20 :: v_dual_add_nc_u32 v13, v16, v18 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v19 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v17 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s18, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v18 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v19, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v20, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v22, 16, 1 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s18, 16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v6 +; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s17, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, v17, v20 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v13, v21 :: v_dual_and_b32 v13, 0xffff, v14 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v20 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v18 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v19, v22 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s17, 16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v22 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18 -; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v19, 16, 1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v17, v21, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s17, 16 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v32, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s5 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s16, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, v24, v19 -; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v25, 16, 1 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v18, v23 :: v_dual_and_b32 v17, 0xffff, v16 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s16, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v20 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v21 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, v22, v25 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v19 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v24, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_bfe_u32 v27, v23, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x7fff, v21 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v25 +; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s16, 16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1 +; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v32, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v6 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v2, v33 :: v_dual_add_nc_u32 v5, v7, v32 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v0, 16, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v32 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s5 ; GFX11-FAKE16-NEXT: s_and_b32 s4, s3, 0xffff0000 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v22, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v24, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v25, v27, v23 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v18 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v20 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v21, v26 :: v_dual_add_nc_u32 v20, v22, v24 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, 0x7fff, v25 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v23 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v26, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 ; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v24 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v28, 0x40c00000, s3 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v25, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v26, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; GFX11-FAKE16-NEXT: v_bfe_u32 v25, v28, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v33, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v5 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v34, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s3 ; GFX11-FAKE16-NEXT: s_and_b32 s3, s2, 0xffff0000 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v24, v20, v27 :: v_dual_add_nc_u32 v23, v23, v26 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v21 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v22 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v26 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, 0x7fff, v23 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v24 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, v25, v28 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s3 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v33 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v32, v33 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v34, 16, 1 ; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, 0x400000, v28 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, 0x7fff, v24 -; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v25, 16, 1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v31, 0x40c00000, s2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v23, v27, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s4 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v33, v34 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v32, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v32 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v32 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v35, vcc_lo +; GFX11-FAKE16-NEXT: v_add_f32_e64 v35, 0x40c00000, s2 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v33 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v34 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s3 +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 ; GFX11-FAKE16-NEXT: s_and_b32 s2, s1, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, v30, v25 -; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v31, 16, 1 ; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v29, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e64 v29, 0x40c00000, s2 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v22 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v26 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v26, 0x7fff, v27 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, v28, v31 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v25 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v30, 0x40c00000, s1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v29, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, 0x7fff, v27 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v31 -; GFX11-FAKE16-NEXT: s_and_b32 s1, s0, 0xffff0000 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v26, v28, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v30, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, v33, v29 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v24 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v26 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v27, v27, v32 :: v_dual_add_nc_u32 v26, v28, v30 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v33, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v35 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v33 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v28, 0x7fff, v31 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, 0x400000, v29 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v4, v33 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v36, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v36, 0x40c00000, s1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v34 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s2 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v36, 16, 1 +; GFX11-FAKE16-NEXT: s_and_b32 s1, s0, 0xffff0000 ; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v26, 0x7fff, v26 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v30 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v34, 0x40c00000, s0 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v28, v31, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v29, v32, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v32 -; GFX11-FAKE16-NEXT: v_bfe_u32 v31, v34, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v34 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v26, v33, vcc_lo -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v28 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v28, v29, v32 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v178 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v30 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v30, v31, v34 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff0000, v178 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v28, 0x7fff, v28 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v33, 0x40c00000, v33 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v109, v5, 16, v7 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v30, 0x7fff, v30 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v28, v35, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v32, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v34, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v36 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v38, 0x40c00000, s0 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v3 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v32, v34 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v0, 16, v1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v33 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v36 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v35 +; GFX11-FAKE16-NEXT: v_add_f32_e64 v35, 0x40c00000, s1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v34 +; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v38, 16, 1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v33, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v29 +; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v2, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v0, 16, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v33, v35 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v36, v38 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v38 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v34 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v31 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v32 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v34 :: v_dual_add_f32 v31, 0x40c00000, v31 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v36, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v34, 16, 1 ; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v31, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v37, v33 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v30, v36, vcc_lo -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v179 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v35, v31 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v33 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v179 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v31 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v1, 16, v32 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v36, v34 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v31 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v30 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v31 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 ; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v180 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v36 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v34, v38, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v36, 16, 1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v35, 16, 1 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v38, 16, v180 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_add_f32 v37, 0x40c00000, v37 :: v_dual_add_nc_u32 v34, v34, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v33, v35 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v38 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v33 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v34 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v31, v35, v37 :: v_dual_add_nc_u32 v32, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v30, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v33 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v35, v36 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v29 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v30 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v38 :: v_dual_lshlrev_b32 v29, 16, v29 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v30 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v36 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v32 -; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v37, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v34, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v29, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v32, 16, v31 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v178, v31, 16, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, v36, v37 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v33, v48 :: v_dual_lshlrev_b32 v36, 16, v182 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v38 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v33, v38 :: v_dual_add_nc_u32 v32, v34, v35 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v35, v38 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v182 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v34 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v37 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, 0x7fff, v31 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v179, v32, 16, v34 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v30 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v136, v2, 16, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v36, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v36 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v36, v29 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v28 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v29 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v31, v31, v48 :: v_dual_add_nc_u32 v38, v38, v35 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v37, v36 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v181 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v38 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v38, 16, v181 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v37, 0x40c00000, v37 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v38 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v39, vcc_lo +; GFX11-FAKE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v30 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v34, v37, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v33 -; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v37, 16, 1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v48, vcc_lo -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v180, v31, 16, v33 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v35, v37 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v170 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v38 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v36, v38 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_lshlrev_b32 v36, 16, v170 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v28, 16, 1 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v33, 16, v30 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v28 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v38 :: v_dual_add_nc_u32 v33, v35, v28 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v36 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v27 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v37 -; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v36, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v182, v31, 16, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, v38, v35 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, v39, v36 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v48, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v36 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v27, 0x40c00000, v27 :: v_dual_cndmask_b32 v28, v33, v37 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, 0x7fff, v31 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff, v29 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v27, 16, 1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v34, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v32, 16, v29 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v27 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v33 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v37 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v169 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v31, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v34, v35 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v36, v27 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v26 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v28 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v32, 16, v28 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v34, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v26, 16, 1 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v39, 16, v169 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v181, v32, 16, v33 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v37, 0x40c00000, v37 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v176 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v48, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v39 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v37, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v37 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v34 -; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v36, 16, 1 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v38 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v35, v37 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v176 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v32, v36 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v25 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v36 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v37, v26 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v26 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v36 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 -; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v49, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v36 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v32, v37, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v27 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v170, v33, 16, v31 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v49, v35 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v48 :: v_dual_add_nc_u32 v33, v37, v38 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v174 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v25, 0x40c00000, v25 :: v_dual_lshlrev_b32 v36, 16, v24 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v34, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v33, 16, v27 +; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v25, 16, 1 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v35 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v36 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v33, v25 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v25 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v36, 16, 1 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v26 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v24, 16, 1 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v23 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v33, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v39, v36 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v32, 16, v26 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v34 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v35, v24 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v36 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v38 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v37 :: v_dual_cndmask_b32 v34, v34, v36 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v174 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v32 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v35, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_cndmask_b32 v33, v33, v39 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v169, v31, 16, v32 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, v37, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v34 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v31, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v25 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v24 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v35, vcc_lo +; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v22 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v171 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v34, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v32, 16, v25 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v33 +; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v23, 16, 1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v24 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v35 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v38, 16, v177 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, v31, v36 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v176, v33, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v37 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v32, v23 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v24, 16, v33 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v34 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v32, 0x40c00000, v32 :: v_dual_lshlrev_b32 v37, 16, v171 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, 0x7fff, v31 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v38 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v36 ; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v33, v34, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v36 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v37 -; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v32, 16, 1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v32 -; GFX11-FAKE16-NEXT: v_bfe_u32 v50, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v31, v31, v34 :: v_dual_add_nc_u32 v36, v37, v32 -; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v35, 16, 1 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v177 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v37, 0x40c00000, v37 :: v_dual_add_nc_u32 v34, v34, v35 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v23 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v22 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v36, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v23, v32, v34 :: v_dual_add_nc_u32 v34, v35, v36 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v21 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v22, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34 -; GFX11-FAKE16-NEXT: v_bfe_u32 v49, v37, 16, 1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v50, v38 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v38 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v50, 16, v184 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_add_f32 v21, 0x40c00000, v21 :: v_dual_add_nc_u32 v32, v32, v22 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v23 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v37, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v34, v34, v48 :: v_dual_add_nc_u32 v35, v49, v37 +; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v21, 16, 1 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v21 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v23 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v48, v21 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v32, v38, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v39, v35 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v20 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v184 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v22 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v35 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_cndmask_b32 v21, v36, v37 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v36, 0x40c00000, v38 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v37 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v37, 0x40c00000, v50 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31 +; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v20, 16, 1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v21 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v39, vcc_lo +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v33, 16, v23 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v34, 16, v22 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v36 ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v38, 0x40c00000, v48 :: v_dual_cndmask_b32 v35, v35, v49 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v36 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v34 -; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v37, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff, v36 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v174, v33, 16, v31 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v171, v32, 16, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, v48, v37 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v175 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v175 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v39, v39, v38 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v177, v35, 16, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, 0x7fff, v31 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v37 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_add_f32 v34, 0x40c00000, v34 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v39 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v38 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, v37, v20 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v19 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v32, 16, v21 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v35 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v33, 0x7fff, v33 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v20 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v34, 0x40c00000, v34 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v36 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v33, v35 :: v_dual_and_b32 v33, 0xffff0000, v18 +; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v19, 16, 1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v34, 16, 1 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v33, 0x40c00000, v33 :: v_dual_lshlrev_b32 v18, 16, v18 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v38, v19 +; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v32, v32, v37 :: v_dual_add_nc_u32 v35, v35, v34 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v19 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v33, 16, 1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v34, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v31, v35, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v173 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v48, 16, v173 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v33 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v35, 0x40c00000, v35 :: v_dual_cndmask_b32 v32, v32, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v37, v33 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, v39, v34 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v34 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v35, 16, 1 +; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_nc_u32 v37, v37, v33 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v36, v38, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, 0x7fff, v37 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v38, v38, v35 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v122, v3, 16, v6 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v37, v39, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v37 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v33 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v18 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v35, v39, vcc_lo +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v18, 16, 1 ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, 0x7fff, v38 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v38, 0x40c00000, v48 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v35 -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v36, v49 :: v_dual_lshlrev_b32 v48, 16, v183 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v38, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v38 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v48, 0x40c00000, v48 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v37, v39, vcc_lo -; GFX11-FAKE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v172 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v39, 16, v172 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, v36, v38 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v38, v38 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v55, 0x400000, v48 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v32 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v18 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v36, v37, vcc_lo +; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff0000, v17 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v16 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v36 :: v_dual_add_f32 v17, 0x40c00000, v17 ; GFX11-FAKE16-NEXT: v_add_f32_e32 v37, 0x40c00000, v37 -; GFX11-FAKE16-NEXT: v_add_f32_e32 v39, 0x40c00000, v39 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v36, 0x7fff, v36 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v34 -; GFX11-FAKE16-NEXT: v_bfe_u32 v50, v37, 16, 1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v39, 16, 1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v36, v49, vcc_lo -; GFX11-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v39 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39 -; GFX11-FAKE16-NEXT: v_dual_add_f32 v50, 0x40c00000, v51 :: v_dual_add_nc_u32 v49, v50, v37 -; GFX11-FAKE16-NEXT: v_bfe_u32 v51, v48, 16, 1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v38, v38, v39 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v53, 0x400000, v37 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v35, v38, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v49, 0x7fff, v49 -; GFX11-FAKE16-NEXT: v_bfe_u32 v52, v50, 16, 1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v51, v51, v48 +; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v36, 16, 1 +; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v17, 16, 1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v17 +; GFX11-FAKE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v38, v39, v36 +; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v37, 16, 1 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v17 +; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v16, 16, 1 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v51, 0x400000, v37 ; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v38, 0x7fff, v38 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v36 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v35 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v52, v52, v50 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v38, v38, v54 :: v_dual_add_nc_u32 v51, 0x7fff, v51 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v36, 0xffff, v36 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v39, 0x7fff, v52 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v52, 0x400000, v50 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v38 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v48, v51, v55, vcc_lo +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v39, v39, v37 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v36 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v48, v48, v16 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v39, 0x7fff, v39 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v35, v50, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v184, v32, 16, v31 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v175, v33, 16, v34 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v38, 0xffff, v38 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v48 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v49, v53, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v50, v50 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v173, v35, 16, v36 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v97, v8, 16, v10 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v48, 0xffff, v48 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v37 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v39, v39, v52, vcc_lo -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v86, v9, 16, v12 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v76, v11, 16, v13 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v67, v14, 16, v17 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v172, v37, 16, v38 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v39 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v59, v16, 16, v19 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v52, v18, 16, v20 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v46, v21, 16, v23 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v41, v22, 16, v25 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v183, v39, 16, v48 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v37, v24, 16, v27 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v34, v26, 16, v28 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v32, v29, 16, v30 +; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v48 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v16 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v34 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v39, v51, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v18 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v38, v49, vcc_lo +; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v32, 16, v20 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v34, 16, v19 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v33, 16, v18 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v36 +; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v35, v48, vcc_lo +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v37 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v36, 16, v17 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_and_b32_e32 v35, 0xffff, v35 +; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v16, 16, v35 ; GFX11-FAKE16-NEXT: .LBB79_3: ; %end -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, v41 :: v_dual_mov_b32 v4, v46 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, v59 :: v_dual_mov_b32 v9, v86 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v7, v67 :: v_dual_mov_b32 v8, v76 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, v97 :: v_dual_mov_b32 v13, v136 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v11, v109 :: v_dual_mov_b32 v12, v122 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, v151 :: v_dual_mov_b32 v17, v172 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, v173 :: v_dual_mov_b32 v19, v175 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v20, v184 :: v_dual_mov_b32 v23, v174 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v22, v171 :: v_dual_mov_b32 v25, v169 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v26, v170 :: v_dual_mov_b32 v29, v180 -; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-FAKE16-NEXT: scratch_load_b32 v184, off, s32 -; GFX11-FAKE16-NEXT: scratch_load_b32 v175, off, s32 offset:4 -; GFX11-FAKE16-NEXT: scratch_load_b32 v174, off, s32 offset:8 -; GFX11-FAKE16-NEXT: scratch_load_b32 v173, off, s32 offset:12 -; GFX11-FAKE16-NEXT: scratch_load_b32 v172, off, s32 offset:16 -; GFX11-FAKE16-NEXT: scratch_load_b32 v171, off, s32 offset:20 -; GFX11-FAKE16-NEXT: scratch_load_b32 v170, off, s32 offset:24 -; GFX11-FAKE16-NEXT: scratch_load_b32 v169, off, s32 offset:28 -; GFX11-FAKE16-NEXT: scratch_load_b32 v168, off, s32 offset:32 -; GFX11-FAKE16-NEXT: scratch_load_b32 v159, off, s32 offset:36 -; GFX11-FAKE16-NEXT: scratch_load_b32 v158, off, s32 offset:40 -; GFX11-FAKE16-NEXT: scratch_load_b32 v157, off, s32 offset:44 -; GFX11-FAKE16-NEXT: scratch_load_b32 v156, off, s32 offset:48 -; GFX11-FAKE16-NEXT: scratch_load_b32 v155, off, s32 offset:52 -; GFX11-FAKE16-NEXT: scratch_load_b32 v154, off, s32 offset:56 -; GFX11-FAKE16-NEXT: scratch_load_b32 v153, off, s32 offset:60 -; GFX11-FAKE16-NEXT: scratch_load_b32 v152, off, s32 offset:64 -; GFX11-FAKE16-NEXT: scratch_load_b32 v143, off, s32 offset:68 -; GFX11-FAKE16-NEXT: scratch_load_b32 v142, off, s32 offset:72 -; GFX11-FAKE16-NEXT: scratch_load_b32 v141, off, s32 offset:76 -; GFX11-FAKE16-NEXT: scratch_load_b32 v140, off, s32 offset:80 -; GFX11-FAKE16-NEXT: scratch_load_b32 v139, off, s32 offset:84 -; GFX11-FAKE16-NEXT: scratch_load_b32 v138, off, s32 offset:88 -; GFX11-FAKE16-NEXT: scratch_load_b32 v137, off, s32 offset:92 -; GFX11-FAKE16-NEXT: scratch_load_b32 v136, off, s32 offset:96 -; GFX11-FAKE16-NEXT: scratch_load_b32 v127, off, s32 offset:100 -; GFX11-FAKE16-NEXT: scratch_load_b32 v126, off, s32 offset:104 -; GFX11-FAKE16-NEXT: scratch_load_b32 v125, off, s32 offset:108 -; GFX11-FAKE16-NEXT: scratch_load_b32 v124, off, s32 offset:112 -; GFX11-FAKE16-NEXT: scratch_load_b32 v123, off, s32 offset:116 -; GFX11-FAKE16-NEXT: scratch_load_b32 v122, off, s32 offset:120 -; GFX11-FAKE16-NEXT: scratch_load_b32 v121, off, s32 offset:124 -; GFX11-FAKE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-FAKE16-NEXT: scratch_load_b32 v120, off, s32 offset:128 -; GFX11-FAKE16-NEXT: scratch_load_b32 v111, off, s32 offset:132 -; GFX11-FAKE16-NEXT: scratch_load_b32 v110, off, s32 offset:136 -; GFX11-FAKE16-NEXT: scratch_load_b32 v109, off, s32 offset:140 -; GFX11-FAKE16-NEXT: scratch_load_b32 v108, off, s32 offset:144 -; GFX11-FAKE16-NEXT: scratch_load_b32 v107, off, s32 offset:148 -; GFX11-FAKE16-NEXT: scratch_load_b32 v106, off, s32 offset:152 -; GFX11-FAKE16-NEXT: scratch_load_b32 v105, off, s32 offset:156 -; GFX11-FAKE16-NEXT: scratch_load_b32 v104, off, s32 offset:160 -; GFX11-FAKE16-NEXT: scratch_load_b32 v95, off, s32 offset:164 -; GFX11-FAKE16-NEXT: scratch_load_b32 v94, off, s32 offset:168 -; GFX11-FAKE16-NEXT: scratch_load_b32 v93, off, s32 offset:172 -; GFX11-FAKE16-NEXT: scratch_load_b32 v92, off, s32 offset:176 -; GFX11-FAKE16-NEXT: scratch_load_b32 v91, off, s32 offset:180 -; GFX11-FAKE16-NEXT: scratch_load_b32 v90, off, s32 offset:184 -; GFX11-FAKE16-NEXT: scratch_load_b32 v89, off, s32 offset:188 -; GFX11-FAKE16-NEXT: scratch_load_b32 v88, off, s32 offset:192 -; GFX11-FAKE16-NEXT: scratch_load_b32 v79, off, s32 offset:196 -; GFX11-FAKE16-NEXT: scratch_load_b32 v78, off, s32 offset:200 -; GFX11-FAKE16-NEXT: scratch_load_b32 v77, off, s32 offset:204 -; GFX11-FAKE16-NEXT: scratch_load_b32 v76, off, s32 offset:208 -; GFX11-FAKE16-NEXT: scratch_load_b32 v75, off, s32 offset:212 -; GFX11-FAKE16-NEXT: scratch_load_b32 v74, off, s32 offset:216 -; GFX11-FAKE16-NEXT: scratch_load_b32 v73, off, s32 offset:220 -; GFX11-FAKE16-NEXT: scratch_load_b32 v72, off, s32 offset:224 -; GFX11-FAKE16-NEXT: scratch_load_b32 v63, off, s32 offset:228 -; GFX11-FAKE16-NEXT: scratch_load_b32 v62, off, s32 offset:232 -; GFX11-FAKE16-NEXT: scratch_load_b32 v61, off, s32 offset:236 -; GFX11-FAKE16-NEXT: scratch_load_b32 v60, off, s32 offset:240 -; GFX11-FAKE16-NEXT: scratch_load_b32 v59, off, s32 offset:244 -; GFX11-FAKE16-NEXT: scratch_load_b32 v58, off, s32 offset:248 -; GFX11-FAKE16-NEXT: scratch_load_b32 v57, off, s32 offset:252 -; GFX11-FAKE16-NEXT: s_clause 0x8 ; 36-byte Folded Reload -; GFX11-FAKE16-NEXT: scratch_load_b32 v56, off, s32 offset:256 -; GFX11-FAKE16-NEXT: scratch_load_b32 v47, off, s32 offset:260 -; GFX11-FAKE16-NEXT: scratch_load_b32 v46, off, s32 offset:264 -; GFX11-FAKE16-NEXT: scratch_load_b32 v45, off, s32 offset:268 -; GFX11-FAKE16-NEXT: scratch_load_b32 v44, off, s32 offset:272 -; GFX11-FAKE16-NEXT: scratch_load_b32 v43, off, s32 offset:276 -; GFX11-FAKE16-NEXT: scratch_load_b32 v42, off, s32 offset:280 -; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s32 offset:284 -; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 offset:288 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, v32 :: v_dual_mov_b32 v1, v34 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, v37 :: v_dual_mov_b32 v5, v52 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, v183 :: v_dual_mov_b32 v21, v177 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v24, v176 :: v_dual_mov_b32 v27, v181 -; GFX11-FAKE16-NEXT: v_mov_b32_e32 v28, v182 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v30, v179 :: v_dual_mov_b32 v31, v178 -; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] ; GFX11-FAKE16-NEXT: .LBB79_4: -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154 -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr1 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr2 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr3 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr4 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr5 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr6 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr7 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr8 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr9 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr10 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr11 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr12 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr13 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr14 +; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr15 ; GFX11-FAKE16-NEXT: s_branch .LBB79_2 %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -141760,25 +139252,21 @@ define inreg <64 x half> @bitcast_v16f64_to_v64f16_scalar(<16 x double> inreg %a ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; SI-NEXT: v_readfirstlane_b32 s44, v1 -; SI-NEXT: v_readfirstlane_b32 s45, v2 -; SI-NEXT: v_readfirstlane_b32 s42, v3 -; SI-NEXT: v_readfirstlane_b32 s43, v4 -; SI-NEXT: v_readfirstlane_b32 s40, v5 -; SI-NEXT: v_readfirstlane_b32 s41, v6 -; SI-NEXT: v_readfirstlane_b32 s14, v7 -; SI-NEXT: v_readfirstlane_b32 s15, v8 -; SI-NEXT: v_readfirstlane_b32 s12, v9 -; SI-NEXT: v_readfirstlane_b32 s13, v10 -; SI-NEXT: v_readfirstlane_b32 s10, v11 -; SI-NEXT: v_readfirstlane_b32 s11, v12 -; SI-NEXT: v_readfirstlane_b32 s8, v13 -; SI-NEXT: v_readfirstlane_b32 s9, v14 -; SI-NEXT: v_readfirstlane_b32 s6, v15 -; SI-NEXT: v_readfirstlane_b32 s7, v16 -; SI-NEXT: v_readfirstlane_b32 s4, v17 -; SI-NEXT: s_and_b64 s[46:47], vcc, exec -; SI-NEXT: v_readfirstlane_b32 s5, v18 +; SI-NEXT: v_mov_b32_e32 v19, s16 +; SI-NEXT: v_mov_b32_e32 v20, s17 +; SI-NEXT: v_mov_b32_e32 v21, s18 +; SI-NEXT: v_mov_b32_e32 v22, s19 +; SI-NEXT: v_mov_b32_e32 v27, s20 +; SI-NEXT: v_mov_b32_e32 v28, s21 +; SI-NEXT: v_mov_b32_e32 v31, s22 +; SI-NEXT: v_mov_b32_e32 v32, s23 +; SI-NEXT: v_mov_b32_e32 v29, s24 +; SI-NEXT: v_mov_b32_e32 v30, s25 +; SI-NEXT: v_mov_b32_e32 v25, s26 +; SI-NEXT: v_mov_b32_e32 v26, s27 +; SI-NEXT: s_and_b64 s[4:5], vcc, exec +; SI-NEXT: v_mov_b32_e32 v23, s28 +; SI-NEXT: v_mov_b32_e32 v24, s29 ; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill @@ -141797,500 +139285,622 @@ define inreg <64 x half> @bitcast_v16f64_to_v64f16_scalar(<16 x double> inreg %a ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB81_4 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: s_lshr_b32 s46, s5, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v10, s46 -; SI-NEXT: s_lshr_b32 s46, s4, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v51, s46 -; SI-NEXT: s_lshr_b32 s46, s7, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v43, s46 -; SI-NEXT: s_lshr_b32 s46, s6, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v40, s46 -; SI-NEXT: s_lshr_b32 s46, s9, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v42, s46 -; SI-NEXT: s_lshr_b32 s46, s8, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v44, s46 -; SI-NEXT: s_lshr_b32 s46, s11, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v8, s46 -; SI-NEXT: s_lshr_b32 s46, s10, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v9, s46 -; SI-NEXT: s_lshr_b32 s46, s13, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v16, s46 -; SI-NEXT: s_lshr_b32 s46, s12, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v23, s46 -; SI-NEXT: s_lshr_b32 s46, s15, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v27, s46 -; SI-NEXT: s_lshr_b32 s46, s14, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v31, s46 -; SI-NEXT: s_lshr_b32 s46, s41, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v38, s46 -; SI-NEXT: s_lshr_b32 s46, s40, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v50, s46 -; SI-NEXT: s_lshr_b32 s46, s43, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v32, s46 -; SI-NEXT: s_lshr_b32 s46, s42, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v22, s46 -; SI-NEXT: s_lshr_b32 s46, s45, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v30, s46 -; SI-NEXT: s_lshr_b32 s46, s44, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v25, s46 -; SI-NEXT: s_lshr_b32 s46, s29, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v12, s46 -; SI-NEXT: s_lshr_b32 s46, s28, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v37, s46 -; SI-NEXT: s_lshr_b32 s46, s27, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v1, s25 -; SI-NEXT: v_cvt_f32_f16_e32 v34, s46 -; SI-NEXT: s_lshr_b32 s46, s26, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v13, s46 -; SI-NEXT: s_lshr_b32 s46, s25, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v35, s46 -; SI-NEXT: s_lshr_b32 s46, s24, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v24, s46 -; SI-NEXT: s_lshr_b32 s46, s23, 16 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v18 +; SI-NEXT: v_cvt_f32_f16_e32 v47, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v17 +; SI-NEXT: v_cvt_f32_f16_e32 v45, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v16 +; SI-NEXT: v_cvt_f32_f16_e32 v43, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v15 +; SI-NEXT: v_cvt_f32_f16_e32 v41, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v14 +; SI-NEXT: v_cvt_f32_f16_e32 v55, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v13 +; SI-NEXT: v_cvt_f32_f16_e32 v53, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v12 +; SI-NEXT: v_cvt_f32_f16_e32 v51, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v11 +; SI-NEXT: v_cvt_f32_f16_e32 v49, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v10 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v33 +; SI-NEXT: v_cvt_f32_f16_e32 v36, v18 +; SI-NEXT: v_cvt_f32_f16_e32 v38, v17 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v1, s24 -; SI-NEXT: v_cvt_f32_f16_e32 v28, s46 -; SI-NEXT: s_lshr_b32 s46, s22, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v17, s46 -; SI-NEXT: s_lshr_b32 s46, s21, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v46, s46 -; SI-NEXT: s_lshr_b32 s46, s20, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v56, s46 -; SI-NEXT: s_lshr_b32 s46, s19, 16 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v9 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v33 +; SI-NEXT: v_cvt_f32_f16_e32 v48, v16 +; SI-NEXT: v_cvt_f32_f16_e32 v57, v28 +; SI-NEXT: v_cvt_f32_f16_e32 v59, v27 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v1, s23 -; SI-NEXT: v_cvt_f32_f16_e32 v57, s46 -; SI-NEXT: s_lshr_b32 s46, s18, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v58, s46 -; SI-NEXT: s_lshr_b32 s46, s17, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v60, s46 -; SI-NEXT: s_lshr_b32 s46, s16, 16 -; SI-NEXT: v_cvt_f32_f16_e32 v62, s46 -; SI-NEXT: v_cvt_f32_f16_e32 v7, s5 -; SI-NEXT: v_cvt_f32_f16_e32 v5, s4 -; SI-NEXT: v_cvt_f32_f16_e32 v14, s7 -; SI-NEXT: v_cvt_f32_f16_e32 v15, s6 -; SI-NEXT: v_cvt_f32_f16_e32 v6, s9 -; SI-NEXT: v_cvt_f32_f16_e32 v18, s8 -; SI-NEXT: v_cvt_f32_f16_e32 v11, s11 -; SI-NEXT: v_cvt_f32_f16_e32 v19, s10 -; SI-NEXT: v_cvt_f32_f16_e32 v39, s13 -; SI-NEXT: v_cvt_f32_f16_e32 v55, s12 -; SI-NEXT: v_cvt_f32_f16_e32 v41, s15 -; SI-NEXT: v_cvt_f32_f16_e32 v45, s14 -; SI-NEXT: v_cvt_f32_f16_e32 v59, s41 -; SI-NEXT: v_cvt_f32_f16_e32 v54, s40 -; SI-NEXT: v_cvt_f32_f16_e32 v36, s43 -; SI-NEXT: v_cvt_f32_f16_e32 v26, s42 -; SI-NEXT: v_cvt_f32_f16_e32 v21, s45 -; SI-NEXT: v_cvt_f32_f16_e32 v61, s44 -; SI-NEXT: v_cvt_f32_f16_e32 v63, s29 -; SI-NEXT: v_cvt_f32_f16_e32 v20, s28 -; SI-NEXT: v_cvt_f32_f16_e32 v33, s27 -; SI-NEXT: v_cvt_f32_f16_e32 v29, s26 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill -; SI-NEXT: v_cvt_f32_f16_e32 v49, s22 -; SI-NEXT: v_cvt_f32_f16_e32 v53, s21 -; SI-NEXT: v_cvt_f32_f16_e32 v47, s20 -; SI-NEXT: v_cvt_f32_f16_e32 v52, s19 -; SI-NEXT: v_cvt_f32_f16_e32 v48, s18 -; SI-NEXT: v_cvt_f32_f16_e32 v2, s17 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v1, s16 -; SI-NEXT: s_cbranch_execnz .LBB81_3 -; SI-NEXT: .LBB81_2: ; %cmp.true -; SI-NEXT: v_add_f64 v[1:2], s[22:23], 1.0 -; SI-NEXT: v_add_f64 v[52:53], s[24:25], 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1 -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v8 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v33 +; SI-NEXT: v_cvt_f32_f16_e32 v62, v22 +; SI-NEXT: v_cvt_f32_f16_e32 v63, v21 +; SI-NEXT: v_cvt_f32_f16_e32 v34, v19 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v52 -; SI-NEXT: v_add_f64 v[48:49], s[26:27], 1.0 -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v53 -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v48 -; SI-NEXT: v_add_f64 v[36:37], s[28:29], 1.0 -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v49 -; SI-NEXT: v_add_f64 v[14:15], s[10:11], 1.0 -; SI-NEXT: v_add_f64 v[10:11], s[8:9], 1.0 -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v36 -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill -; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v15 -; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v10 -; SI-NEXT: v_cvt_f32_f16_e32 v44, v17 -; SI-NEXT: v_cvt_f32_f16_e32 v8, v13 -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload -; SI-NEXT: v_add_f64 v[4:5], s[4:5], 1.0 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v7 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v33 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v3, v10 -; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v5 -; SI-NEXT: v_cvt_f32_f16_e32 v10, v35 -; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v4 -; SI-NEXT: v_cvt_f32_f16_e32 v40, v4 -; SI-NEXT: v_cvt_f32_f16_e32 v4, v14 -; SI-NEXT: v_add_f64 v[29:30], s[42:43], 1.0 -; SI-NEXT: v_add_f64 v[6:7], s[6:7], 1.0 -; SI-NEXT: v_add_f64 v[21:22], s[14:15], 1.0 -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v6 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v33 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v4, v30 -; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v37 -; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v29 -; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v6 -; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v21 -; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v22 -; SI-NEXT: v_cvt_f32_f16_e32 v42, v5 -; SI-NEXT: v_cvt_f32_f16_e32 v5, v7 -; SI-NEXT: v_cvt_f32_f16_e32 v12, v6 -; SI-NEXT: v_cvt_f32_f16_e32 v41, v22 -; SI-NEXT: v_cvt_f32_f16_e32 v45, v21 -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v33 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v4, v29 -; SI-NEXT: v_cvt_f32_f16_e32 v21, v36 -; SI-NEXT: v_cvt_f32_f16_e32 v36, v24 -; SI-NEXT: v_cvt_f32_f16_e32 v22, v56 -; SI-NEXT: v_cvt_f32_f16_e32 v56, v57 -; SI-NEXT: v_add_f64 v[46:47], s[20:21], 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v14 -; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v11 -; SI-NEXT: v_cvt_f32_f16_e32 v6, v11 -; SI-NEXT: v_cvt_f32_f16_e32 v11, v15 -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v46 -; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v47 -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill -; SI-NEXT: v_cvt_f32_f16_e32 v63, v37 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v4, v53 -; SI-NEXT: v_cvt_f32_f16_e32 v53, v47 -; SI-NEXT: v_cvt_f32_f16_e32 v47, v46 -; SI-NEXT: v_cvt_f32_f16_e32 v46, v15 -; SI-NEXT: v_mov_b32_e32 v15, v12 -; SI-NEXT: v_mov_b32_e32 v12, v56 -; SI-NEXT: v_cvt_f32_f16_e32 v56, v14 -; SI-NEXT: v_mov_b32_e32 v14, v5 -; SI-NEXT: v_mov_b32_e32 v5, v40 -; SI-NEXT: v_mov_b32_e32 v40, v36 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 -; SI-NEXT: v_add_f64 v[33:34], s[44:45], 1.0 -; SI-NEXT: v_add_f64 v[25:26], s[40:41], 1.0 -; SI-NEXT: v_cvt_f32_f16_e32 v20, v20 -; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v26 -; SI-NEXT: v_cvt_f32_f16_e32 v59, v26 -; SI-NEXT: v_cvt_f32_f16_e32 v26, v34 -; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v33 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v33 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v33 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v33 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v24 +; SI-NEXT: v_cvt_f32_f16_e32 v35, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v23 +; SI-NEXT: v_cvt_f32_f16_e32 v37, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v26 +; SI-NEXT: v_cvt_f32_f16_e32 v39, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v25 +; SI-NEXT: v_cvt_f32_f16_e32 v50, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v30 +; SI-NEXT: v_cvt_f32_f16_e32 v52, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v29 +; SI-NEXT: v_cvt_f32_f16_e32 v54, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v32 +; SI-NEXT: v_cvt_f32_f16_e32 v40, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v31 +; SI-NEXT: v_cvt_f32_f16_e32 v42, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v28 +; SI-NEXT: v_cvt_f32_f16_e32 v44, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v27 +; SI-NEXT: v_cvt_f32_f16_e32 v46, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v22 +; SI-NEXT: v_cvt_f32_f16_e32 v56, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v21 +; SI-NEXT: v_cvt_f32_f16_e32 v58, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v20 +; SI-NEXT: v_cvt_f32_f16_e32 v60, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v19 ; SI-NEXT: v_cvt_f32_f16_e32 v61, v33 -; SI-NEXT: v_cvt_f32_f16_e32 v33, v49 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill -; SI-NEXT: v_cvt_f32_f16_e32 v49, v1 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_f64 v[1:2], s[18:19], 1.0 -; SI-NEXT: v_add_f64 v[18:19], s[12:13], 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v7 -; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v1 -; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v34 -; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload -; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v25 -; SI-NEXT: v_cvt_f32_f16_e32 v54, v25 -; SI-NEXT: v_cvt_f32_f16_e32 v43, v28 -; SI-NEXT: v_cvt_f32_f16_e32 v25, v58 -; SI-NEXT: v_cvt_f32_f16_e32 v58, v7 -; SI-NEXT: v_mov_b32_e32 v7, v42 -; SI-NEXT: v_mov_b32_e32 v42, v20 -; SI-NEXT: v_mov_b32_e32 v20, v21 -; SI-NEXT: v_mov_b32_e32 v21, v26 -; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v18 -; SI-NEXT: v_cvt_f32_f16_e32 v55, v18 -; SI-NEXT: v_cvt_f32_f16_e32 v29, v48 -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_cvt_f32_f16_e32 v37, v13 -; SI-NEXT: s_waitcnt vmcnt(6) -; SI-NEXT: v_cvt_f32_f16_e32 v35, v17 -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; SI-NEXT: v_cvt_f32_f16_e32 v33, v15 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v4, v52 -; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v52, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v48, v1 -; SI-NEXT: v_add_f64 v[1:2], s[16:17], 1.0 -; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v30 -; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v19 -; SI-NEXT: v_cvt_f32_f16_e32 v39, v19 -; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v1 -; SI-NEXT: v_cvt_f32_f16_e32 v51, v32 -; SI-NEXT: v_cvt_f32_f16_e32 v32, v62 -; SI-NEXT: v_cvt_f32_f16_e32 v62, v19 -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f32_f16_e32 v33, v14 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v13 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v12 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v11 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v10 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v9 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v8 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v7 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v6 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v5 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v4 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v3 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v2 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v1 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v24 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v23 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v26 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v25 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v30 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v29 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v32 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v31 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v20 +; SI-NEXT: s_cbranch_execnz .LBB81_3 +; SI-NEXT: .LBB81_2: ; %cmp.true +; SI-NEXT: v_add_f64 v[1:2], v[1:2], 1.0 +; SI-NEXT: v_add_f64 v[23:24], v[23:24], 1.0 +; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v1 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 -; SI-NEXT: v_cvt_f32_f16_e32 v9, v9 +; SI-NEXT: v_add_f64 v[33:34], v[25:26], 1.0 +; SI-NEXT: v_add_f64 v[29:30], v[29:30], 1.0 +; SI-NEXT: v_add_f64 v[31:32], v[31:32], 1.0 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v24 +; SI-NEXT: v_add_f64 v[3:4], v[3:4], 1.0 +; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v2 +; SI-NEXT: v_add_f64 v[5:6], v[5:6], 1.0 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v23 +; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 +; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v4 +; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v5 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v34 +; SI-NEXT: v_cvt_f32_f16_e32 v5, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v4, v4 +; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v6 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v33 +; SI-NEXT: v_cvt_f32_f16_e32 v6, v6 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: v_add_f64 v[9:10], v[9:10], 1.0 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v30 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v10 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v29 +; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v34 +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v9 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v32 +; SI-NEXT: v_add_f64 v[7:8], v[7:8], 1.0 +; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v3 +; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v8 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v31 +; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v7 +; SI-NEXT: v_cvt_f32_f16_e32 v7, v7 +; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_add_f64 v[1:2], v[21:22], 1.0 +; SI-NEXT: v_add_f64 v[27:28], v[27:28], 1.0 +; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1 +; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v62, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v63, v1 +; SI-NEXT: v_add_f64 v[1:2], v[19:20], 1.0 +; SI-NEXT: v_add_f64 v[11:12], v[11:12], 1.0 +; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v34, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v1, v48 +; SI-NEXT: v_add_f64 v[13:14], v[13:14], 1.0 +; SI-NEXT: v_add_f64 v[15:16], v[15:16], 1.0 +; SI-NEXT: v_add_f64 v[17:18], v[17:18], 1.0 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v38 +; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v27 +; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v31 +; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v32 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v36 +; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v29 +; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v30 +; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v33 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v61 +; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v23 +; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v24 +; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v11 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v60 +; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v12 +; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v13 +; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v14 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v58 +; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v15 +; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v16 +; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v17 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v56 +; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v18 +; SI-NEXT: v_cvt_f32_f16_e32 v18, v18 +; SI-NEXT: v_cvt_f32_f16_e32 v17, v17 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v44 ; SI-NEXT: v_cvt_f32_f16_e32 v16, v16 -; SI-NEXT: v_cvt_f32_f16_e32 v23, v23 -; SI-NEXT: v_cvt_f32_f16_e32 v27, v27 -; SI-NEXT: v_cvt_f32_f16_e32 v31, v31 -; SI-NEXT: v_cvt_f32_f16_e32 v38, v38 -; SI-NEXT: v_cvt_f32_f16_e32 v50, v50 -; SI-NEXT: v_cvt_f32_f16_e32 v30, v60 -; SI-NEXT: v_cvt_f32_f16_e32 v57, v18 -; SI-NEXT: v_cvt_f32_f16_e32 v60, v4 -; SI-NEXT: v_mov_b32_e32 v18, v3 -; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(4) -; SI-NEXT: v_cvt_f32_f16_e32 v24, v17 -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(4) -; SI-NEXT: v_cvt_f32_f16_e32 v34, v13 -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_cvt_f32_f16_e32 v28, v17 -; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v52 +; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v28 +; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v15, v15 +; SI-NEXT: v_cvt_f32_f16_e32 v14, v14 ; SI-NEXT: v_cvt_f32_f16_e32 v13, v13 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v17, v17 +; SI-NEXT: v_cvt_f32_f16_e32 v12, v12 +; SI-NEXT: v_cvt_f32_f16_e32 v11, v11 +; SI-NEXT: v_cvt_f32_f16_e32 v10, v10 +; SI-NEXT: v_cvt_f32_f16_e32 v9, v9 +; SI-NEXT: v_cvt_f32_f16_e32 v8, v8 +; SI-NEXT: v_cvt_f32_f16_e32 v57, v28 +; SI-NEXT: v_cvt_f32_f16_e32 v59, v27 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v2 +; SI-NEXT: v_cvt_f32_f16_e32 v47, v47 +; SI-NEXT: v_cvt_f32_f16_e32 v45, v45 +; SI-NEXT: v_cvt_f32_f16_e32 v43, v43 +; SI-NEXT: v_cvt_f32_f16_e32 v41, v41 +; SI-NEXT: v_cvt_f32_f16_e32 v55, v55 +; SI-NEXT: v_cvt_f32_f16_e32 v53, v53 +; SI-NEXT: v_cvt_f32_f16_e32 v51, v51 +; SI-NEXT: v_cvt_f32_f16_e32 v49, v49 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f32_f16_e32 v1, v50 +; SI-NEXT: v_cvt_f32_f16_e32 v35, v35 +; SI-NEXT: v_cvt_f32_f16_e32 v37, v37 +; SI-NEXT: v_cvt_f32_f16_e32 v39, v39 +; SI-NEXT: v_cvt_f32_f16_e32 v50, v26 +; SI-NEXT: v_cvt_f32_f16_e32 v52, v25 +; SI-NEXT: v_cvt_f32_f16_e32 v54, v54 +; SI-NEXT: v_cvt_f32_f16_e32 v40, v40 +; SI-NEXT: v_cvt_f32_f16_e32 v42, v42 +; SI-NEXT: v_cvt_f32_f16_e32 v44, v3 +; SI-NEXT: v_cvt_f32_f16_e32 v46, v46 +; SI-NEXT: v_cvt_f32_f16_e32 v56, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v58, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v60, v7 +; SI-NEXT: v_cvt_f32_f16_e32 v61, v6 +; SI-NEXT: v_mov_b32_e32 v48, v16 +; SI-NEXT: v_mov_b32_e32 v38, v17 +; SI-NEXT: v_mov_b32_e32 v36, v18 +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill ; SI-NEXT: .LBB81_3: ; %end -; SI-NEXT: v_cvt_f16_f32_e32 v3, v62 -; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 -; SI-NEXT: v_add_i32_e32 v4, vcc, 12, v0 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_or_b32_e32 v1, v1, v3 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v61 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v34 +; SI-NEXT: v_add_i32_e32 v3, vcc, 12, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v1, v60 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v2 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v33 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: v_add_i32_e32 v3, vcc, 4, v0 -; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v1, v58 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v48 -; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: v_add_i32_e32 v3, vcc, 8, v0 -; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v57 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v52 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v63 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v1, v56 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v47 -; SI-NEXT: v_add_i32_e32 v4, vcc, 16, v0 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v62 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v1, v46 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v53 -; SI-NEXT: v_add_i32_e32 v4, vcc, 20, v0 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v59 +; SI-NEXT: v_add_i32_e32 v3, vcc, 16, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v17 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v49 -; SI-NEXT: v_add_i32_e32 v4, vcc, 24, v0 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v44 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v57 +; SI-NEXT: v_add_i32_e32 v3, vcc, 20, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v28 -; SI-NEXT: v_add_i32_e32 v4, vcc, 28, v0 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v42 +; SI-NEXT: v_add_i32_e32 v3, vcc, 24, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v2 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v24 -; SI-NEXT: v_add_i32_e32 v4, vcc, 32, v0 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v40 +; SI-NEXT: v_add_i32_e32 v3, vcc, 28, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v2 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v35 -; SI-NEXT: v_add_i32_e32 v4, vcc, 36, v0 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v54 +; SI-NEXT: v_add_i32_e32 v3, vcc, 32, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v2 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v6 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v13 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v29 -; SI-NEXT: v_add_i32_e32 v4, vcc, 40, v0 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v52 +; SI-NEXT: v_add_i32_e32 v3, vcc, 36, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v34 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v33 -; SI-NEXT: v_add_i32_e32 v4, vcc, 44, v0 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v50 +; SI-NEXT: v_add_i32_e32 v3, vcc, 40, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v39 +; SI-NEXT: v_add_i32_e32 v3, vcc, 44, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v1, v37 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v20 -; SI-NEXT: v_add_i32_e32 v4, vcc, 48, v0 +; SI-NEXT: v_add_i32_e32 v3, vcc, 48, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v12 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v63 -; SI-NEXT: v_add_i32_e32 v4, vcc, 52, v0 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v35 +; SI-NEXT: v_add_i32_e32 v3, vcc, 52, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v25 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v61 -; SI-NEXT: v_add_i32_e32 v4, vcc, 56, v0 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 56, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v30 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v21 -; SI-NEXT: v_add_i32_e32 v4, vcc, 60, v0 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 60, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v22 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v26 -; SI-NEXT: v_add_i32_e32 v4, vcc, 64, v0 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 64, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v32 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v36 -; SI-NEXT: v_add_i32_e32 v4, vcc, 0x44, v0 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x44, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v50 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v54 -; SI-NEXT: v_add_i32_e32 v4, vcc, 0x48, v0 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x48, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v38 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v59 -; SI-NEXT: v_add_i32_e32 v4, vcc, 0x4c, v0 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x4c, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v31 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v45 -; SI-NEXT: v_add_i32_e32 v4, vcc, 0x50, v0 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x50, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v27 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v41 -; SI-NEXT: v_add_i32_e32 v4, vcc, 0x54, v0 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x54, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v23 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v55 -; SI-NEXT: v_add_i32_e32 v4, vcc, 0x58, v0 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x58, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v16 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v39 -; SI-NEXT: v_add_i32_e32 v4, vcc, 0x5c, v0 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x5c, v0 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v9 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v19 -; SI-NEXT: v_add_i32_e32 v4, vcc, 0x60, v0 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v49 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x60, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v8 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v11 -; SI-NEXT: v_add_i32_e32 v4, vcc, 0x64, v0 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v51 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x64, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v44 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v18 -; SI-NEXT: v_add_i32_e32 v4, vcc, 0x68, v0 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v53 +; SI-NEXT: v_add_i32_e32 v3, vcc, 0x68, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SI-NEXT: v_or_b32_e32 v1, v2, v1 +; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v42 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v55 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x6c, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v40 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v15 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v41 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x70, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_cvt_f16_f32_e32 v1, v43 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v14 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v48 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x74, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v51 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v5 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v45 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v38 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x78, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v10 -; SI-NEXT: v_cvt_f16_f32_e32 v2, v7 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v47 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v36 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; SI-NEXT: v_or_b32_e32 v1, v2, v1 @@ -142314,73 +139924,103 @@ define inreg <64 x half> @bitcast_v16f64_to_v64f16_scalar(<16 x double> inreg %a ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] ; SI-NEXT: .LBB81_4: -; SI-NEXT: ; implicit-def: $vgpr3 -; SI-NEXT: ; kill: killed $vgpr3 -; SI-NEXT: ; implicit-def: $vgpr3 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr62 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr60 -; SI-NEXT: ; implicit-def: $vgpr48 -; SI-NEXT: ; implicit-def: $vgpr58 -; SI-NEXT: ; implicit-def: $vgpr52 -; SI-NEXT: ; implicit-def: $vgpr57 -; SI-NEXT: ; implicit-def: $vgpr47 -; SI-NEXT: ; implicit-def: $vgpr56 -; SI-NEXT: ; implicit-def: $vgpr53 -; SI-NEXT: ; implicit-def: $vgpr46 -; SI-NEXT: ; implicit-def: $vgpr49 -; SI-NEXT: ; implicit-def: $vgpr17 -; SI-NEXT: ; implicit-def: $vgpr28 -; SI-NEXT: ; kill: killed $vgpr3 -; SI-NEXT: ; implicit-def: $vgpr24 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 ; SI-NEXT: ; implicit-def: $vgpr35 -; SI-NEXT: ; implicit-def: $vgpr29 -; SI-NEXT: ; implicit-def: $vgpr13 -; SI-NEXT: ; implicit-def: $vgpr33 +; SI-NEXT: ; kill: killed $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; kill: killed $vgpr35 ; SI-NEXT: ; implicit-def: $vgpr34 -; SI-NEXT: ; implicit-def: $vgpr20 -; SI-NEXT: ; implicit-def: $vgpr37 -; SI-NEXT: ; implicit-def: $vgpr63 -; SI-NEXT: ; implicit-def: $vgpr12 ; SI-NEXT: ; implicit-def: $vgpr61 -; SI-NEXT: ; implicit-def: $vgpr25 -; SI-NEXT: ; implicit-def: $vgpr21 -; SI-NEXT: ; implicit-def: $vgpr30 -; SI-NEXT: ; implicit-def: $vgpr26 -; SI-NEXT: ; implicit-def: $vgpr22 -; SI-NEXT: ; implicit-def: $vgpr36 -; SI-NEXT: ; implicit-def: $vgpr32 -; SI-NEXT: ; implicit-def: $vgpr54 -; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; implicit-def: $vgpr33 +; SI-NEXT: ; implicit-def: $vgpr60 +; SI-NEXT: ; implicit-def: $vgpr63 +; SI-NEXT: ; implicit-def: $vgpr58 +; SI-NEXT: ; implicit-def: $vgpr62 +; SI-NEXT: ; implicit-def: $vgpr56 ; SI-NEXT: ; implicit-def: $vgpr59 -; SI-NEXT: ; implicit-def: $vgpr38 -; SI-NEXT: ; implicit-def: $vgpr45 -; SI-NEXT: ; implicit-def: $vgpr31 -; SI-NEXT: ; implicit-def: $vgpr41 -; SI-NEXT: ; implicit-def: $vgpr27 -; SI-NEXT: ; implicit-def: $vgpr55 -; SI-NEXT: ; implicit-def: $vgpr23 -; SI-NEXT: ; implicit-def: $vgpr39 -; SI-NEXT: ; implicit-def: $vgpr16 -; SI-NEXT: ; implicit-def: $vgpr19 -; SI-NEXT: ; implicit-def: $vgpr9 -; SI-NEXT: ; implicit-def: $vgpr11 -; SI-NEXT: ; implicit-def: $vgpr8 -; SI-NEXT: ; implicit-def: $vgpr18 +; SI-NEXT: ; implicit-def: $vgpr46 +; SI-NEXT: ; implicit-def: $vgpr57 ; SI-NEXT: ; implicit-def: $vgpr44 -; SI-NEXT: ; implicit-def: $vgpr6 ; SI-NEXT: ; implicit-def: $vgpr42 -; SI-NEXT: ; implicit-def: $vgpr15 ; SI-NEXT: ; implicit-def: $vgpr40 -; SI-NEXT: ; implicit-def: $vgpr14 -; SI-NEXT: ; implicit-def: $vgpr43 -; SI-NEXT: ; implicit-def: $vgpr5 +; SI-NEXT: ; implicit-def: $vgpr54 +; SI-NEXT: ; implicit-def: $vgpr52 +; SI-NEXT: ; implicit-def: $vgpr50 +; SI-NEXT: ; implicit-def: $vgpr39 +; SI-NEXT: ; implicit-def: $vgpr37 +; SI-NEXT: ; implicit-def: $vgpr49 ; SI-NEXT: ; implicit-def: $vgpr51 -; SI-NEXT: ; implicit-def: $vgpr7 -; SI-NEXT: ; implicit-def: $vgpr10 -; SI-NEXT: ; implicit-def: $vgpr3 -; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr53 +; SI-NEXT: ; implicit-def: $vgpr55 +; SI-NEXT: ; implicit-def: $vgpr41 +; SI-NEXT: ; implicit-def: $vgpr48 +; SI-NEXT: ; implicit-def: $vgpr43 +; SI-NEXT: ; implicit-def: $vgpr38 +; SI-NEXT: ; implicit-def: $vgpr45 +; SI-NEXT: ; implicit-def: $vgpr47 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; kill: killed $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; kill: killed $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; kill: killed $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; kill: killed $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; kill: killed $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; kill: killed $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; kill: killed $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr36 ; SI-NEXT: s_branch .LBB81_2 ; ; VI-LABEL: bitcast_v16f64_to_v64f16_scalar: @@ -144471,252 +142111,80 @@ define inreg <16 x double> @bitcast_v64f16_to_v16f64_scalar(<64 x half> inreg %a ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292 -; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288 -; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284 -; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280 -; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276 -; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272 -; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268 -; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264 -; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260 -; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256 -; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252 -; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248 -; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244 -; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240 -; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236 -; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232 -; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228 -; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224 -; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220 -; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216 -; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212 -; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208 -; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204 -; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200 -; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196 -; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192 -; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188 -; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184 -; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180 -; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176 -; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172 -; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164 -; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160 -; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156 -; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152 -; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148 -; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144 -; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140 -; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136 -; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132 -; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128 -; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124 -; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120 -; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116 -; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112 -; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108 -; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104 -; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100 -; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96 -; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92 -; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88 -; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84 -; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80 -; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76 -; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72 -; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68 -; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64 -; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60 -; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56 -; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52 -; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48 -; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44 -; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40 -; GFX11-NEXT: s_clause 0x9 ; 40-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36 -; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32 -; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28 -; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24 -; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20 -; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16 -; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12 -; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8 -; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4 -; GFX11-NEXT: scratch_store_b32 off, v185, s32 -; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12 -; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10 -; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8 -; GFX11-NEXT: v_dual_mov_b32 v182, v7 :: v_dual_mov_b32 v183, v6 -; GFX11-NEXT: v_dual_mov_b32 v170, v5 :: v_dual_mov_b32 v171, v4 -; GFX11-NEXT: v_dual_mov_b32 v172, v3 :: v_dual_mov_b32 v173, v2 -; GFX11-NEXT: v_dual_mov_b32 v174, v1 :: v_dual_mov_b32 v175, v0 -; GFX11-NEXT: v_dual_mov_b32 v184, s28 :: v_dual_mov_b32 v185, s29 +; GFX11-NEXT: v_dual_mov_b32 v31, v13 :: v_dual_mov_b32 v30, v12 +; GFX11-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 +; GFX11-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 ; GFX11-NEXT: s_mov_b32 s4, 0 ; GFX11-NEXT: s_and_b32 s5, vcc_lo, exec_lo ; GFX11-NEXT: s_cbranch_scc0 .LBB83_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: v_dual_mov_b32 v47, s0 :: v_dual_mov_b32 v52, s2 -; GFX11-NEXT: v_dual_mov_b32 v49, s1 :: v_dual_mov_b32 v56, s3 -; GFX11-NEXT: v_dual_mov_b32 v61, s16 :: v_dual_mov_b32 v74, s18 -; GFX11-NEXT: v_dual_mov_b32 v67, s17 :: v_dual_mov_b32 v82, s19 -; GFX11-NEXT: v_dual_mov_b32 v91, s20 :: v_dual_mov_b32 v112, s22 -; GFX11-NEXT: v_dual_mov_b32 v101, s21 :: v_dual_mov_b32 v124, s23 -; GFX11-NEXT: v_dual_mov_b32 v137, s24 :: v_dual_mov_b32 v14, s26 -; GFX11-NEXT: v_dual_mov_b32 v151, s25 :: v_dual_mov_b32 v30, s27 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 +; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 +; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 +; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 +; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 +; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4 ; GFX11-NEXT: s_cbranch_vccnz .LBB83_3 ; GFX11-NEXT: .LBB83_2: ; %cmp.true -; GFX11-NEXT: v_pk_add_f16 v30, 0x200, s27 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s27 op_sel_hi:[0,1] ; GFX11-NEXT: v_pk_add_f16 v14, 0x200, s26 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v176, 0x200, v176 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v177, 0x200, v177 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v178, 0x200, v178 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v179, 0x200, v179 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v180, 0x200, v180 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v181, 0x200, v181 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v182, 0x200, v182 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v183, 0x200, v183 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v170, 0x200, v170 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v171, 0x200, v171 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v172, 0x200, v172 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v173, 0x200, v173 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v174, 0x200, v174 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v175, 0x200, v175 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v185, 0x200, v185 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v184, 0x200, v184 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v151, 0x200, s25 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v137, 0x200, s24 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v124, 0x200, s23 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v112, 0x200, s22 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v101, 0x200, s21 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v91, 0x200, s20 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v82, 0x200, s19 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v74, 0x200, s18 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v67, 0x200, s17 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v61, 0x200, s16 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v56, 0x200, s3 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v52, 0x200, s2 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v49, 0x200, s1 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v47, 0x200, s0 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s25 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s24 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s23 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s22 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s21 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v31, 0x200, v31 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v30, 0x200, v30 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v29, 0x200, v29 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v28, 0x200, v28 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v27, 0x200, v27 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v26, 0x200, v26 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v25, 0x200, v25 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v24, 0x200, v24 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v23, 0x200, v23 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v22, 0x200, v22 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v21, 0x200, v21 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v20, 0x200, v20 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v19, 0x200, v19 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v18, 0x200, v18 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v17, 0x200, v17 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1] ; GFX11-NEXT: .LBB83_3: ; %end -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_dual_mov_b32 v0, v47 :: v_dual_mov_b32 v1, v49 -; GFX11-NEXT: v_dual_mov_b32 v3, v56 :: v_dual_mov_b32 v4, v61 -; GFX11-NEXT: v_dual_mov_b32 v6, v74 :: v_dual_mov_b32 v9, v101 -; GFX11-NEXT: v_dual_mov_b32 v7, v82 :: v_dual_mov_b32 v8, v91 -; GFX11-NEXT: v_dual_mov_b32 v11, v124 :: v_dual_mov_b32 v12, v137 -; GFX11-NEXT: v_dual_mov_b32 v15, v30 :: v_dual_mov_b32 v16, v184 -; GFX11-NEXT: v_dual_mov_b32 v17, v185 :: v_dual_mov_b32 v18, v175 -; GFX11-NEXT: v_dual_mov_b32 v19, v174 :: v_dual_mov_b32 v20, v173 -; GFX11-NEXT: v_dual_mov_b32 v21, v172 :: v_dual_mov_b32 v22, v171 -; GFX11-NEXT: v_dual_mov_b32 v23, v170 :: v_dual_mov_b32 v24, v183 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v185, off, s32 -; GFX11-NEXT: scratch_load_b32 v184, off, s32 offset:4 -; GFX11-NEXT: scratch_load_b32 v175, off, s32 offset:8 -; GFX11-NEXT: scratch_load_b32 v174, off, s32 offset:12 -; GFX11-NEXT: scratch_load_b32 v173, off, s32 offset:16 -; GFX11-NEXT: scratch_load_b32 v172, off, s32 offset:20 -; GFX11-NEXT: scratch_load_b32 v171, off, s32 offset:24 -; GFX11-NEXT: scratch_load_b32 v170, off, s32 offset:28 -; GFX11-NEXT: scratch_load_b32 v169, off, s32 offset:32 -; GFX11-NEXT: scratch_load_b32 v168, off, s32 offset:36 -; GFX11-NEXT: scratch_load_b32 v159, off, s32 offset:40 -; GFX11-NEXT: scratch_load_b32 v158, off, s32 offset:44 -; GFX11-NEXT: scratch_load_b32 v157, off, s32 offset:48 -; GFX11-NEXT: scratch_load_b32 v156, off, s32 offset:52 -; GFX11-NEXT: scratch_load_b32 v155, off, s32 offset:56 -; GFX11-NEXT: scratch_load_b32 v154, off, s32 offset:60 -; GFX11-NEXT: scratch_load_b32 v153, off, s32 offset:64 -; GFX11-NEXT: scratch_load_b32 v152, off, s32 offset:68 -; GFX11-NEXT: scratch_load_b32 v143, off, s32 offset:72 -; GFX11-NEXT: scratch_load_b32 v142, off, s32 offset:76 -; GFX11-NEXT: scratch_load_b32 v141, off, s32 offset:80 -; GFX11-NEXT: scratch_load_b32 v140, off, s32 offset:84 -; GFX11-NEXT: scratch_load_b32 v139, off, s32 offset:88 -; GFX11-NEXT: scratch_load_b32 v138, off, s32 offset:92 -; GFX11-NEXT: scratch_load_b32 v137, off, s32 offset:96 -; GFX11-NEXT: scratch_load_b32 v136, off, s32 offset:100 -; GFX11-NEXT: scratch_load_b32 v127, off, s32 offset:104 -; GFX11-NEXT: scratch_load_b32 v126, off, s32 offset:108 -; GFX11-NEXT: scratch_load_b32 v125, off, s32 offset:112 -; GFX11-NEXT: scratch_load_b32 v124, off, s32 offset:116 -; GFX11-NEXT: scratch_load_b32 v123, off, s32 offset:120 -; GFX11-NEXT: scratch_load_b32 v122, off, s32 offset:124 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v121, off, s32 offset:128 -; GFX11-NEXT: scratch_load_b32 v120, off, s32 offset:132 -; GFX11-NEXT: scratch_load_b32 v111, off, s32 offset:136 -; GFX11-NEXT: scratch_load_b32 v110, off, s32 offset:140 -; GFX11-NEXT: scratch_load_b32 v109, off, s32 offset:144 -; GFX11-NEXT: scratch_load_b32 v108, off, s32 offset:148 -; GFX11-NEXT: scratch_load_b32 v107, off, s32 offset:152 -; GFX11-NEXT: scratch_load_b32 v106, off, s32 offset:156 -; GFX11-NEXT: scratch_load_b32 v105, off, s32 offset:160 -; GFX11-NEXT: scratch_load_b32 v104, off, s32 offset:164 -; GFX11-NEXT: scratch_load_b32 v95, off, s32 offset:168 -; GFX11-NEXT: scratch_load_b32 v94, off, s32 offset:172 -; GFX11-NEXT: scratch_load_b32 v93, off, s32 offset:176 -; GFX11-NEXT: scratch_load_b32 v92, off, s32 offset:180 -; GFX11-NEXT: scratch_load_b32 v91, off, s32 offset:184 -; GFX11-NEXT: scratch_load_b32 v90, off, s32 offset:188 -; GFX11-NEXT: scratch_load_b32 v89, off, s32 offset:192 -; GFX11-NEXT: scratch_load_b32 v88, off, s32 offset:196 -; GFX11-NEXT: scratch_load_b32 v79, off, s32 offset:200 -; GFX11-NEXT: scratch_load_b32 v78, off, s32 offset:204 -; GFX11-NEXT: scratch_load_b32 v77, off, s32 offset:208 -; GFX11-NEXT: scratch_load_b32 v76, off, s32 offset:212 -; GFX11-NEXT: scratch_load_b32 v75, off, s32 offset:216 -; GFX11-NEXT: scratch_load_b32 v74, off, s32 offset:220 -; GFX11-NEXT: scratch_load_b32 v73, off, s32 offset:224 -; GFX11-NEXT: scratch_load_b32 v72, off, s32 offset:228 -; GFX11-NEXT: scratch_load_b32 v63, off, s32 offset:232 -; GFX11-NEXT: scratch_load_b32 v62, off, s32 offset:236 -; GFX11-NEXT: scratch_load_b32 v61, off, s32 offset:240 -; GFX11-NEXT: scratch_load_b32 v60, off, s32 offset:244 -; GFX11-NEXT: scratch_load_b32 v59, off, s32 offset:248 -; GFX11-NEXT: scratch_load_b32 v58, off, s32 offset:252 -; GFX11-NEXT: s_clause 0x9 ; 40-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v57, off, s32 offset:256 -; GFX11-NEXT: scratch_load_b32 v56, off, s32 offset:260 -; GFX11-NEXT: scratch_load_b32 v47, off, s32 offset:264 -; GFX11-NEXT: scratch_load_b32 v46, off, s32 offset:268 -; GFX11-NEXT: scratch_load_b32 v45, off, s32 offset:272 -; GFX11-NEXT: scratch_load_b32 v44, off, s32 offset:276 -; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:280 -; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:284 -; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:288 -; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:292 -; GFX11-NEXT: v_dual_mov_b32 v2, v52 :: v_dual_mov_b32 v5, v67 -; GFX11-NEXT: v_dual_mov_b32 v10, v112 :: v_dual_mov_b32 v13, v151 -; GFX11-NEXT: v_dual_mov_b32 v25, v182 :: v_dual_mov_b32 v26, v181 -; GFX11-NEXT: v_dual_mov_b32 v27, v180 :: v_dual_mov_b32 v28, v179 -; GFX11-NEXT: v_dual_mov_b32 v29, v178 :: v_dual_mov_b32 v30, v177 -; GFX11-NEXT: v_mov_b32_e32 v31, v176 -; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: .LBB83_4: -; GFX11-NEXT: ; implicit-def: $vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78 -; GFX11-NEXT: ; implicit-def: $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79 -; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-NEXT: ; implicit-def: $vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81 -; GFX11-NEXT: ; implicit-def: $vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84 -; GFX11-NEXT: ; implicit-def: $vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88 -; GFX11-NEXT: ; implicit-def: $vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93 -; GFX11-NEXT: ; implicit-def: $vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99 -; GFX11-NEXT: ; implicit-def: $vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106 -; GFX11-NEXT: ; implicit-def: $vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114 -; GFX11-NEXT: ; implicit-def: $vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123 -; GFX11-NEXT: ; implicit-def: $vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133 -; GFX11-NEXT: ; implicit-def: $vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144 -; GFX11-NEXT: ; implicit-def: $vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156 -; GFX11-NEXT: ; implicit-def: $vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169 +; GFX11-NEXT: ; implicit-def: $vgpr0 +; GFX11-NEXT: ; implicit-def: $vgpr1 +; GFX11-NEXT: ; implicit-def: $vgpr2 +; GFX11-NEXT: ; implicit-def: $vgpr3 +; GFX11-NEXT: ; implicit-def: $vgpr4 +; GFX11-NEXT: ; implicit-def: $vgpr5 +; GFX11-NEXT: ; implicit-def: $vgpr6 +; GFX11-NEXT: ; implicit-def: $vgpr7 +; GFX11-NEXT: ; implicit-def: $vgpr8 +; GFX11-NEXT: ; implicit-def: $vgpr9 +; GFX11-NEXT: ; implicit-def: $vgpr10 +; GFX11-NEXT: ; implicit-def: $vgpr11 +; GFX11-NEXT: ; implicit-def: $vgpr12 +; GFX11-NEXT: ; implicit-def: $vgpr13 +; GFX11-NEXT: ; implicit-def: $vgpr14 +; GFX11-NEXT: ; implicit-def: $vgpr15 ; GFX11-NEXT: s_branch .LBB83_2 %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -147071,23 +144539,51 @@ define inreg <16 x double> @bitcast_v64i16_to_v16f64_scalar(<64 x i16> inreg %a, ; VI-LABEL: bitcast_v64i16_to_v16f64_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 +; VI-NEXT: v_mov_b32_e32 v19, s16 ; VI-NEXT: v_readfirstlane_b32 s6, v2 +; VI-NEXT: v_mov_b32_e32 v2, s17 ; VI-NEXT: v_readfirstlane_b32 s7, v3 +; VI-NEXT: v_mov_b32_e32 v3, s18 ; VI-NEXT: v_readfirstlane_b32 s8, v4 +; VI-NEXT: v_mov_b32_e32 v4, s19 ; VI-NEXT: v_readfirstlane_b32 s9, v5 +; VI-NEXT: v_mov_b32_e32 v5, s20 ; VI-NEXT: v_readfirstlane_b32 s10, v6 +; VI-NEXT: v_mov_b32_e32 v6, s21 ; VI-NEXT: v_readfirstlane_b32 s11, v7 +; VI-NEXT: v_mov_b32_e32 v7, s22 ; VI-NEXT: v_readfirstlane_b32 s12, v8 +; VI-NEXT: v_mov_b32_e32 v8, s23 ; VI-NEXT: v_readfirstlane_b32 s13, v9 +; VI-NEXT: v_mov_b32_e32 v9, s24 ; VI-NEXT: v_readfirstlane_b32 s14, v10 +; VI-NEXT: v_mov_b32_e32 v10, s25 ; VI-NEXT: v_readfirstlane_b32 s15, v11 -; VI-NEXT: v_readfirstlane_b32 s40, v12 -; VI-NEXT: v_readfirstlane_b32 s41, v13 -; VI-NEXT: v_readfirstlane_b32 s42, v14 -; VI-NEXT: v_readfirstlane_b32 s43, v15 -; VI-NEXT: v_readfirstlane_b32 s44, v16 -; VI-NEXT: v_readfirstlane_b32 s45, v17 +; VI-NEXT: v_mov_b32_e32 v11, s26 +; VI-NEXT: v_readfirstlane_b32 s16, v12 +; VI-NEXT: v_mov_b32_e32 v12, s27 +; VI-NEXT: v_readfirstlane_b32 s17, v13 +; VI-NEXT: v_mov_b32_e32 v13, s28 +; VI-NEXT: v_readfirstlane_b32 s18, v14 +; VI-NEXT: v_mov_b32_e32 v14, s29 +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 +; VI-NEXT: v_readfirstlane_b32 s19, v15 +; VI-NEXT: v_readfirstlane_b32 s20, v16 +; VI-NEXT: v_readfirstlane_b32 s21, v17 +; VI-NEXT: v_readfirstlane_b32 s22, v19 +; VI-NEXT: v_readfirstlane_b32 s23, v2 +; VI-NEXT: v_readfirstlane_b32 s24, v3 +; VI-NEXT: v_readfirstlane_b32 s25, v4 +; VI-NEXT: v_readfirstlane_b32 s26, v5 +; VI-NEXT: v_readfirstlane_b32 s27, v6 +; VI-NEXT: v_readfirstlane_b32 s28, v7 +; VI-NEXT: v_readfirstlane_b32 s29, v8 +; VI-NEXT: v_readfirstlane_b32 s40, v9 +; VI-NEXT: v_readfirstlane_b32 s41, v10 +; VI-NEXT: v_readfirstlane_b32 s42, v11 +; VI-NEXT: v_readfirstlane_b32 s43, v12 +; VI-NEXT: v_readfirstlane_b32 s44, v13 +; VI-NEXT: v_readfirstlane_b32 s45, v14 ; VI-NEXT: v_readfirstlane_b32 s46, v0 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s47, v1 @@ -147104,8 +144600,38 @@ define inreg <16 x double> @bitcast_v64i16_to_v16f64_scalar(<64 x i16> inreg %a, ; VI-NEXT: s_and_b32 s4, s46, 0xffff0000 ; VI-NEXT: s_and_b32 s5, s5, 0xffff ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s29, 3 +; VI-NEXT: s_add_i32 s5, s45, 3 ; VI-NEXT: s_add_i32 s46, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s45, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s44, 3 +; VI-NEXT: s_add_i32 s45, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s44, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s43, 3 +; VI-NEXT: s_add_i32 s44, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s43, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s42, 3 +; VI-NEXT: s_add_i32 s43, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s42, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s41, 3 +; VI-NEXT: s_add_i32 s42, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s41, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s40, 3 +; VI-NEXT: s_add_i32 s41, s4, 0x30000 +; VI-NEXT: s_and_b32 s4, s40, 0xffff0000 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: s_add_i32 s5, s29, 3 +; VI-NEXT: s_add_i32 s40, s4, 0x30000 ; VI-NEXT: s_and_b32 s4, s29, 0xffff0000 ; VI-NEXT: s_and_b32 s5, s5, 0xffff ; VI-NEXT: s_or_b32 s4, s4, s5 @@ -147174,38 +144700,8 @@ define inreg <16 x double> @bitcast_v64i16_to_v16f64_scalar(<64 x i16> inreg %a, ; VI-NEXT: s_and_b32 s4, s16, 0xffff0000 ; VI-NEXT: s_and_b32 s5, s5, 0xffff ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s45, 3 -; VI-NEXT: s_add_i32 s16, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s45, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s44, 3 -; VI-NEXT: s_add_i32 s45, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s44, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s43, 3 -; VI-NEXT: s_add_i32 s44, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s43, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s42, 3 -; VI-NEXT: s_add_i32 s43, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s42, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s41, 3 -; VI-NEXT: s_add_i32 s42, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s41, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s5, s40, 3 -; VI-NEXT: s_add_i32 s41, s4, 0x30000 -; VI-NEXT: s_and_b32 s4, s40, 0xffff0000 -; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s4, s4, s5 ; VI-NEXT: s_add_i32 s5, s15, 3 -; VI-NEXT: s_add_i32 s40, s4, 0x30000 +; VI-NEXT: s_add_i32 s16, s4, 0x30000 ; VI-NEXT: s_and_b32 s4, s15, 0xffff0000 ; VI-NEXT: s_and_b32 s5, s5, 0xffff ; VI-NEXT: s_or_b32 s4, s4, s5 @@ -147256,20 +144752,20 @@ define inreg <16 x double> @bitcast_v64i16_to_v16f64_scalar(<64 x i16> inreg %a, ; VI-NEXT: s_or_b32 s4, s4, s5 ; VI-NEXT: s_add_i32 s6, s4, 0x30000 ; VI-NEXT: .LBB87_3: ; %end -; VI-NEXT: v_mov_b32_e32 v0, s16 -; VI-NEXT: v_mov_b32_e32 v1, s17 -; VI-NEXT: v_mov_b32_e32 v2, s18 -; VI-NEXT: v_mov_b32_e32 v3, s19 -; VI-NEXT: v_mov_b32_e32 v4, s20 -; VI-NEXT: v_mov_b32_e32 v5, s21 -; VI-NEXT: v_mov_b32_e32 v6, s22 -; VI-NEXT: v_mov_b32_e32 v7, s23 -; VI-NEXT: v_mov_b32_e32 v8, s24 -; VI-NEXT: v_mov_b32_e32 v9, s25 -; VI-NEXT: v_mov_b32_e32 v10, s26 -; VI-NEXT: v_mov_b32_e32 v11, s27 -; VI-NEXT: v_mov_b32_e32 v12, s28 -; VI-NEXT: v_mov_b32_e32 v13, s29 +; VI-NEXT: v_mov_b32_e32 v0, s22 +; VI-NEXT: v_mov_b32_e32 v1, s23 +; VI-NEXT: v_mov_b32_e32 v2, s24 +; VI-NEXT: v_mov_b32_e32 v3, s25 +; VI-NEXT: v_mov_b32_e32 v4, s26 +; VI-NEXT: v_mov_b32_e32 v5, s27 +; VI-NEXT: v_mov_b32_e32 v6, s28 +; VI-NEXT: v_mov_b32_e32 v7, s29 +; VI-NEXT: v_mov_b32_e32 v8, s40 +; VI-NEXT: v_mov_b32_e32 v9, s41 +; VI-NEXT: v_mov_b32_e32 v10, s42 +; VI-NEXT: v_mov_b32_e32 v11, s43 +; VI-NEXT: v_mov_b32_e32 v12, s44 +; VI-NEXT: v_mov_b32_e32 v13, s45 ; VI-NEXT: v_mov_b32_e32 v14, s46 ; VI-NEXT: v_mov_b32_e32 v15, s47 ; VI-NEXT: v_mov_b32_e32 v16, s6 @@ -147282,12 +144778,12 @@ define inreg <16 x double> @bitcast_v64i16_to_v16f64_scalar(<64 x i16> inreg %a, ; VI-NEXT: v_mov_b32_e32 v23, s13 ; VI-NEXT: v_mov_b32_e32 v24, s14 ; VI-NEXT: v_mov_b32_e32 v25, s15 -; VI-NEXT: v_mov_b32_e32 v26, s40 -; VI-NEXT: v_mov_b32_e32 v27, s41 -; VI-NEXT: v_mov_b32_e32 v28, s42 -; VI-NEXT: v_mov_b32_e32 v29, s43 -; VI-NEXT: v_mov_b32_e32 v30, s44 -; VI-NEXT: v_mov_b32_e32 v31, s45 +; VI-NEXT: v_mov_b32_e32 v26, s16 +; VI-NEXT: v_mov_b32_e32 v27, s17 +; VI-NEXT: v_mov_b32_e32 v28, s18 +; VI-NEXT: v_mov_b32_e32 v29, s19 +; VI-NEXT: v_mov_b32_e32 v30, s20 +; VI-NEXT: v_mov_b32_e32 v31, s21 ; VI-NEXT: s_setpc_b64 s[30:31] ; VI-NEXT: .LBB87_4: ; VI-NEXT: s_branch .LBB87_2 @@ -147375,252 +144871,80 @@ define inreg <16 x double> @bitcast_v64i16_to_v16f64_scalar(<64 x i16> inreg %a, ; GFX11: ; %bb.0: ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:292 -; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:288 -; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:284 -; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:280 -; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:276 -; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:272 -; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:268 -; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:264 -; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:260 -; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:256 -; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:252 -; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:248 -; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:244 -; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:240 -; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:236 -; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:232 -; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:228 -; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:224 -; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:220 -; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:216 -; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:212 -; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:208 -; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:204 -; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:200 -; GFX11-NEXT: scratch_store_b32 off, v88, s32 offset:196 -; GFX11-NEXT: scratch_store_b32 off, v89, s32 offset:192 -; GFX11-NEXT: scratch_store_b32 off, v90, s32 offset:188 -; GFX11-NEXT: scratch_store_b32 off, v91, s32 offset:184 -; GFX11-NEXT: scratch_store_b32 off, v92, s32 offset:180 -; GFX11-NEXT: scratch_store_b32 off, v93, s32 offset:176 -; GFX11-NEXT: scratch_store_b32 off, v94, s32 offset:172 -; GFX11-NEXT: scratch_store_b32 off, v95, s32 offset:168 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v104, s32 offset:164 -; GFX11-NEXT: scratch_store_b32 off, v105, s32 offset:160 -; GFX11-NEXT: scratch_store_b32 off, v106, s32 offset:156 -; GFX11-NEXT: scratch_store_b32 off, v107, s32 offset:152 -; GFX11-NEXT: scratch_store_b32 off, v108, s32 offset:148 -; GFX11-NEXT: scratch_store_b32 off, v109, s32 offset:144 -; GFX11-NEXT: scratch_store_b32 off, v110, s32 offset:140 -; GFX11-NEXT: scratch_store_b32 off, v111, s32 offset:136 -; GFX11-NEXT: scratch_store_b32 off, v120, s32 offset:132 -; GFX11-NEXT: scratch_store_b32 off, v121, s32 offset:128 -; GFX11-NEXT: scratch_store_b32 off, v122, s32 offset:124 -; GFX11-NEXT: scratch_store_b32 off, v123, s32 offset:120 -; GFX11-NEXT: scratch_store_b32 off, v124, s32 offset:116 -; GFX11-NEXT: scratch_store_b32 off, v125, s32 offset:112 -; GFX11-NEXT: scratch_store_b32 off, v126, s32 offset:108 -; GFX11-NEXT: scratch_store_b32 off, v127, s32 offset:104 -; GFX11-NEXT: scratch_store_b32 off, v136, s32 offset:100 -; GFX11-NEXT: scratch_store_b32 off, v137, s32 offset:96 -; GFX11-NEXT: scratch_store_b32 off, v138, s32 offset:92 -; GFX11-NEXT: scratch_store_b32 off, v139, s32 offset:88 -; GFX11-NEXT: scratch_store_b32 off, v140, s32 offset:84 -; GFX11-NEXT: scratch_store_b32 off, v141, s32 offset:80 -; GFX11-NEXT: scratch_store_b32 off, v142, s32 offset:76 -; GFX11-NEXT: scratch_store_b32 off, v143, s32 offset:72 -; GFX11-NEXT: scratch_store_b32 off, v152, s32 offset:68 -; GFX11-NEXT: scratch_store_b32 off, v153, s32 offset:64 -; GFX11-NEXT: scratch_store_b32 off, v154, s32 offset:60 -; GFX11-NEXT: scratch_store_b32 off, v155, s32 offset:56 -; GFX11-NEXT: scratch_store_b32 off, v156, s32 offset:52 -; GFX11-NEXT: scratch_store_b32 off, v157, s32 offset:48 -; GFX11-NEXT: scratch_store_b32 off, v158, s32 offset:44 -; GFX11-NEXT: scratch_store_b32 off, v159, s32 offset:40 -; GFX11-NEXT: s_clause 0x9 ; 40-byte Folded Spill -; GFX11-NEXT: scratch_store_b32 off, v168, s32 offset:36 -; GFX11-NEXT: scratch_store_b32 off, v169, s32 offset:32 -; GFX11-NEXT: scratch_store_b32 off, v170, s32 offset:28 -; GFX11-NEXT: scratch_store_b32 off, v171, s32 offset:24 -; GFX11-NEXT: scratch_store_b32 off, v172, s32 offset:20 -; GFX11-NEXT: scratch_store_b32 off, v173, s32 offset:16 -; GFX11-NEXT: scratch_store_b32 off, v174, s32 offset:12 -; GFX11-NEXT: scratch_store_b32 off, v175, s32 offset:8 -; GFX11-NEXT: scratch_store_b32 off, v184, s32 offset:4 -; GFX11-NEXT: scratch_store_b32 off, v185, s32 -; GFX11-NEXT: v_dual_mov_b32 v176, v13 :: v_dual_mov_b32 v177, v12 -; GFX11-NEXT: v_dual_mov_b32 v178, v11 :: v_dual_mov_b32 v179, v10 -; GFX11-NEXT: v_dual_mov_b32 v180, v9 :: v_dual_mov_b32 v181, v8 -; GFX11-NEXT: v_dual_mov_b32 v182, v7 :: v_dual_mov_b32 v183, v6 -; GFX11-NEXT: v_dual_mov_b32 v170, v5 :: v_dual_mov_b32 v171, v4 -; GFX11-NEXT: v_dual_mov_b32 v172, v3 :: v_dual_mov_b32 v173, v2 -; GFX11-NEXT: v_dual_mov_b32 v174, v1 :: v_dual_mov_b32 v175, v0 -; GFX11-NEXT: v_dual_mov_b32 v184, s28 :: v_dual_mov_b32 v185, s29 +; GFX11-NEXT: v_dual_mov_b32 v31, v13 :: v_dual_mov_b32 v30, v12 +; GFX11-NEXT: v_dual_mov_b32 v29, v11 :: v_dual_mov_b32 v28, v10 +; GFX11-NEXT: v_dual_mov_b32 v27, v9 :: v_dual_mov_b32 v26, v8 +; GFX11-NEXT: v_dual_mov_b32 v25, v7 :: v_dual_mov_b32 v24, v6 +; GFX11-NEXT: v_dual_mov_b32 v23, v5 :: v_dual_mov_b32 v22, v4 +; GFX11-NEXT: v_dual_mov_b32 v21, v3 :: v_dual_mov_b32 v20, v2 +; GFX11-NEXT: v_dual_mov_b32 v19, v1 :: v_dual_mov_b32 v18, v0 +; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 ; GFX11-NEXT: s_mov_b32 s4, 0 ; GFX11-NEXT: s_and_b32 s5, vcc_lo, exec_lo ; GFX11-NEXT: s_cbranch_scc0 .LBB87_4 ; GFX11-NEXT: ; %bb.1: ; %cmp.false -; GFX11-NEXT: v_dual_mov_b32 v47, s0 :: v_dual_mov_b32 v52, s2 -; GFX11-NEXT: v_dual_mov_b32 v49, s1 :: v_dual_mov_b32 v56, s3 -; GFX11-NEXT: v_dual_mov_b32 v61, s16 :: v_dual_mov_b32 v74, s18 -; GFX11-NEXT: v_dual_mov_b32 v67, s17 :: v_dual_mov_b32 v82, s19 -; GFX11-NEXT: v_dual_mov_b32 v91, s20 :: v_dual_mov_b32 v112, s22 -; GFX11-NEXT: v_dual_mov_b32 v101, s21 :: v_dual_mov_b32 v124, s23 -; GFX11-NEXT: v_dual_mov_b32 v137, s24 :: v_dual_mov_b32 v14, s26 -; GFX11-NEXT: v_dual_mov_b32 v151, s25 :: v_dual_mov_b32 v30, s27 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17 +; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19 +; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21 +; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23 +; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25 +; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27 ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4 ; GFX11-NEXT: s_cbranch_vccnz .LBB87_3 ; GFX11-NEXT: .LBB87_2: ; %cmp.true -; GFX11-NEXT: v_pk_add_u16 v30, s27, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v15, s27, 3 op_sel_hi:[1,0] ; GFX11-NEXT: v_pk_add_u16 v14, s26, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v176, v176, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v177, v177, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v178, v178, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v179, v179, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v180, v180, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v181, v181, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v182, v182, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v183, v183, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v170, v170, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v171, v171, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v172, v172, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v173, v173, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v174, v174, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v175, v175, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v185, v185, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v184, v184, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v151, s25, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v137, s24, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v124, s23, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v112, s22, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v101, s21, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v91, s20, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v82, s19, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v74, s18, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v67, s17, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v61, s16, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v56, s3, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v52, s2, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v49, s1, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v47, s0, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v13, s25, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v12, s24, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v11, s23, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v10, s22, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v31, v31, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v30, v30, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v29, v29, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v28, v28, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v27, v27, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v26, v26, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v25, v25, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v24, v24, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v23, v23, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v22, v22, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v21, v21, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v20, v20, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v19, v19, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v18, v18, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v17, v17, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0] ; GFX11-NEXT: .LBB87_3: ; %end -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_dual_mov_b32 v0, v47 :: v_dual_mov_b32 v1, v49 -; GFX11-NEXT: v_dual_mov_b32 v3, v56 :: v_dual_mov_b32 v4, v61 -; GFX11-NEXT: v_dual_mov_b32 v6, v74 :: v_dual_mov_b32 v9, v101 -; GFX11-NEXT: v_dual_mov_b32 v7, v82 :: v_dual_mov_b32 v8, v91 -; GFX11-NEXT: v_dual_mov_b32 v11, v124 :: v_dual_mov_b32 v12, v137 -; GFX11-NEXT: v_dual_mov_b32 v15, v30 :: v_dual_mov_b32 v16, v184 -; GFX11-NEXT: v_dual_mov_b32 v17, v185 :: v_dual_mov_b32 v18, v175 -; GFX11-NEXT: v_dual_mov_b32 v19, v174 :: v_dual_mov_b32 v20, v173 -; GFX11-NEXT: v_dual_mov_b32 v21, v172 :: v_dual_mov_b32 v22, v171 -; GFX11-NEXT: v_dual_mov_b32 v23, v170 :: v_dual_mov_b32 v24, v183 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v185, off, s32 -; GFX11-NEXT: scratch_load_b32 v184, off, s32 offset:4 -; GFX11-NEXT: scratch_load_b32 v175, off, s32 offset:8 -; GFX11-NEXT: scratch_load_b32 v174, off, s32 offset:12 -; GFX11-NEXT: scratch_load_b32 v173, off, s32 offset:16 -; GFX11-NEXT: scratch_load_b32 v172, off, s32 offset:20 -; GFX11-NEXT: scratch_load_b32 v171, off, s32 offset:24 -; GFX11-NEXT: scratch_load_b32 v170, off, s32 offset:28 -; GFX11-NEXT: scratch_load_b32 v169, off, s32 offset:32 -; GFX11-NEXT: scratch_load_b32 v168, off, s32 offset:36 -; GFX11-NEXT: scratch_load_b32 v159, off, s32 offset:40 -; GFX11-NEXT: scratch_load_b32 v158, off, s32 offset:44 -; GFX11-NEXT: scratch_load_b32 v157, off, s32 offset:48 -; GFX11-NEXT: scratch_load_b32 v156, off, s32 offset:52 -; GFX11-NEXT: scratch_load_b32 v155, off, s32 offset:56 -; GFX11-NEXT: scratch_load_b32 v154, off, s32 offset:60 -; GFX11-NEXT: scratch_load_b32 v153, off, s32 offset:64 -; GFX11-NEXT: scratch_load_b32 v152, off, s32 offset:68 -; GFX11-NEXT: scratch_load_b32 v143, off, s32 offset:72 -; GFX11-NEXT: scratch_load_b32 v142, off, s32 offset:76 -; GFX11-NEXT: scratch_load_b32 v141, off, s32 offset:80 -; GFX11-NEXT: scratch_load_b32 v140, off, s32 offset:84 -; GFX11-NEXT: scratch_load_b32 v139, off, s32 offset:88 -; GFX11-NEXT: scratch_load_b32 v138, off, s32 offset:92 -; GFX11-NEXT: scratch_load_b32 v137, off, s32 offset:96 -; GFX11-NEXT: scratch_load_b32 v136, off, s32 offset:100 -; GFX11-NEXT: scratch_load_b32 v127, off, s32 offset:104 -; GFX11-NEXT: scratch_load_b32 v126, off, s32 offset:108 -; GFX11-NEXT: scratch_load_b32 v125, off, s32 offset:112 -; GFX11-NEXT: scratch_load_b32 v124, off, s32 offset:116 -; GFX11-NEXT: scratch_load_b32 v123, off, s32 offset:120 -; GFX11-NEXT: scratch_load_b32 v122, off, s32 offset:124 -; GFX11-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v121, off, s32 offset:128 -; GFX11-NEXT: scratch_load_b32 v120, off, s32 offset:132 -; GFX11-NEXT: scratch_load_b32 v111, off, s32 offset:136 -; GFX11-NEXT: scratch_load_b32 v110, off, s32 offset:140 -; GFX11-NEXT: scratch_load_b32 v109, off, s32 offset:144 -; GFX11-NEXT: scratch_load_b32 v108, off, s32 offset:148 -; GFX11-NEXT: scratch_load_b32 v107, off, s32 offset:152 -; GFX11-NEXT: scratch_load_b32 v106, off, s32 offset:156 -; GFX11-NEXT: scratch_load_b32 v105, off, s32 offset:160 -; GFX11-NEXT: scratch_load_b32 v104, off, s32 offset:164 -; GFX11-NEXT: scratch_load_b32 v95, off, s32 offset:168 -; GFX11-NEXT: scratch_load_b32 v94, off, s32 offset:172 -; GFX11-NEXT: scratch_load_b32 v93, off, s32 offset:176 -; GFX11-NEXT: scratch_load_b32 v92, off, s32 offset:180 -; GFX11-NEXT: scratch_load_b32 v91, off, s32 offset:184 -; GFX11-NEXT: scratch_load_b32 v90, off, s32 offset:188 -; GFX11-NEXT: scratch_load_b32 v89, off, s32 offset:192 -; GFX11-NEXT: scratch_load_b32 v88, off, s32 offset:196 -; GFX11-NEXT: scratch_load_b32 v79, off, s32 offset:200 -; GFX11-NEXT: scratch_load_b32 v78, off, s32 offset:204 -; GFX11-NEXT: scratch_load_b32 v77, off, s32 offset:208 -; GFX11-NEXT: scratch_load_b32 v76, off, s32 offset:212 -; GFX11-NEXT: scratch_load_b32 v75, off, s32 offset:216 -; GFX11-NEXT: scratch_load_b32 v74, off, s32 offset:220 -; GFX11-NEXT: scratch_load_b32 v73, off, s32 offset:224 -; GFX11-NEXT: scratch_load_b32 v72, off, s32 offset:228 -; GFX11-NEXT: scratch_load_b32 v63, off, s32 offset:232 -; GFX11-NEXT: scratch_load_b32 v62, off, s32 offset:236 -; GFX11-NEXT: scratch_load_b32 v61, off, s32 offset:240 -; GFX11-NEXT: scratch_load_b32 v60, off, s32 offset:244 -; GFX11-NEXT: scratch_load_b32 v59, off, s32 offset:248 -; GFX11-NEXT: scratch_load_b32 v58, off, s32 offset:252 -; GFX11-NEXT: s_clause 0x9 ; 40-byte Folded Reload -; GFX11-NEXT: scratch_load_b32 v57, off, s32 offset:256 -; GFX11-NEXT: scratch_load_b32 v56, off, s32 offset:260 -; GFX11-NEXT: scratch_load_b32 v47, off, s32 offset:264 -; GFX11-NEXT: scratch_load_b32 v46, off, s32 offset:268 -; GFX11-NEXT: scratch_load_b32 v45, off, s32 offset:272 -; GFX11-NEXT: scratch_load_b32 v44, off, s32 offset:276 -; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:280 -; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:284 -; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:288 -; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:292 -; GFX11-NEXT: v_dual_mov_b32 v2, v52 :: v_dual_mov_b32 v5, v67 -; GFX11-NEXT: v_dual_mov_b32 v10, v112 :: v_dual_mov_b32 v13, v151 -; GFX11-NEXT: v_dual_mov_b32 v25, v182 :: v_dual_mov_b32 v26, v181 -; GFX11-NEXT: v_dual_mov_b32 v27, v180 :: v_dual_mov_b32 v28, v179 -; GFX11-NEXT: v_dual_mov_b32 v29, v178 :: v_dual_mov_b32 v30, v177 -; GFX11-NEXT: v_mov_b32_e32 v31, v176 -; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: .LBB87_4: -; GFX11-NEXT: ; implicit-def: $vgpr47_vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78 -; GFX11-NEXT: ; implicit-def: $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79 -; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 -; GFX11-NEXT: ; implicit-def: $vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46 -; GFX11-NEXT: ; implicit-def: $vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81 -; GFX11-NEXT: ; implicit-def: $vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84 -; GFX11-NEXT: ; implicit-def: $vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88 -; GFX11-NEXT: ; implicit-def: $vgpr62_vgpr63_vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93 -; GFX11-NEXT: ; implicit-def: $vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99 -; GFX11-NEXT: ; implicit-def: $vgpr75_vgpr76_vgpr77_vgpr78_vgpr79_vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106 -; GFX11-NEXT: ; implicit-def: $vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114 -; GFX11-NEXT: ; implicit-def: $vgpr92_vgpr93_vgpr94_vgpr95_vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123 -; GFX11-NEXT: ; implicit-def: $vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111_vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133 -; GFX11-NEXT: ; implicit-def: $vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144 -; GFX11-NEXT: ; implicit-def: $vgpr125_vgpr126_vgpr127_vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156 -; GFX11-NEXT: ; implicit-def: $vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143_vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159_vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169 +; GFX11-NEXT: ; implicit-def: $vgpr0 +; GFX11-NEXT: ; implicit-def: $vgpr1 +; GFX11-NEXT: ; implicit-def: $vgpr2 +; GFX11-NEXT: ; implicit-def: $vgpr3 +; GFX11-NEXT: ; implicit-def: $vgpr4 +; GFX11-NEXT: ; implicit-def: $vgpr5 +; GFX11-NEXT: ; implicit-def: $vgpr6 +; GFX11-NEXT: ; implicit-def: $vgpr7 +; GFX11-NEXT: ; implicit-def: $vgpr8 +; GFX11-NEXT: ; implicit-def: $vgpr9 +; GFX11-NEXT: ; implicit-def: $vgpr10 +; GFX11-NEXT: ; implicit-def: $vgpr11 +; GFX11-NEXT: ; implicit-def: $vgpr12 +; GFX11-NEXT: ; implicit-def: $vgpr13 +; GFX11-NEXT: ; implicit-def: $vgpr14 +; GFX11-NEXT: ; implicit-def: $vgpr15 ; GFX11-NEXT: s_branch .LBB87_2 %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -153903,6 +151227,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:332 ; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:328 @@ -153912,14 +151237,13 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:312 ; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:308 ; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:304 -; SI-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane -; SI-NEXT: s_mov_b32 s72, s21 +; SI-NEXT: ; implicit-def: $vgpr44 : SGPR spill to VGPR lane +; SI-NEXT: s_mov_b32 s73, s21 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_writelane_b32 v43, s19, 0 -; SI-NEXT: v_writelane_b32 v43, s18, 1 -; SI-NEXT: v_writelane_b32 v43, s17, 2 -; SI-NEXT: v_writelane_b32 v43, s16, 3 -; SI-NEXT: s_mov_b32 s60, s24 +; SI-NEXT: v_writelane_b32 v44, s19, 0 +; SI-NEXT: v_writelane_b32 v44, s18, 1 +; SI-NEXT: v_writelane_b32 v44, s17, 2 +; SI-NEXT: v_writelane_b32 v44, s16, 3 ; SI-NEXT: v_writelane_b32 v41, s30, 0 ; SI-NEXT: v_writelane_b32 v41, s31, 1 ; SI-NEXT: v_writelane_b32 v41, s34, 2 @@ -153944,7 +151268,8 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: v_writelane_b32 v41, s69, 21 ; SI-NEXT: v_writelane_b32 v41, s70, 22 ; SI-NEXT: v_writelane_b32 v41, s71, 23 -; SI-NEXT: s_mov_b32 s77, s28 +; SI-NEXT: s_mov_b32 s74, s29 +; SI-NEXT: s_mov_b32 s78, s28 ; SI-NEXT: s_mov_b32 s76, s27 ; SI-NEXT: v_writelane_b32 v41, s80, 24 ; SI-NEXT: v_writelane_b32 v41, s81, 25 @@ -153955,7 +151280,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: v_writelane_b32 v41, s86, 30 ; SI-NEXT: v_writelane_b32 v41, s87, 31 ; SI-NEXT: v_writelane_b32 v41, s96, 32 -; SI-NEXT: s_mov_b32 s79, s26 +; SI-NEXT: s_mov_b32 s47, s26 ; SI-NEXT: v_writelane_b32 v41, s97, 33 ; SI-NEXT: v_writelane_b32 v41, s98, 34 ; SI-NEXT: v_writelane_b32 v41, s99, 35 @@ -153965,32 +151290,32 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:156 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:152 +; SI-NEXT: v_readfirstlane_b32 s37, v22 +; SI-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane ; SI-NEXT: v_readfirstlane_b32 s38, v20 -; SI-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane +; SI-NEXT: v_writelane_b32 v43, s37, 0 ; SI-NEXT: v_readfirstlane_b32 s39, v19 -; SI-NEXT: v_writelane_b32 v42, s38, 0 +; SI-NEXT: v_writelane_b32 v43, s38, 1 ; SI-NEXT: v_readfirstlane_b32 s48, v25 -; SI-NEXT: v_writelane_b32 v42, s39, 1 +; SI-NEXT: v_writelane_b32 v43, s39, 2 ; SI-NEXT: v_readfirstlane_b32 s49, v26 -; SI-NEXT: v_writelane_b32 v42, s48, 2 +; SI-NEXT: v_writelane_b32 v43, s48, 3 ; SI-NEXT: v_readfirstlane_b32 s50, v24 -; SI-NEXT: v_writelane_b32 v42, s49, 3 +; SI-NEXT: v_writelane_b32 v43, s49, 4 ; SI-NEXT: v_readfirstlane_b32 s51, v23 -; SI-NEXT: v_writelane_b32 v42, s50, 4 +; SI-NEXT: v_writelane_b32 v43, s50, 5 ; SI-NEXT: v_readfirstlane_b32 s52, v29 -; SI-NEXT: v_writelane_b32 v42, s51, 5 +; SI-NEXT: v_writelane_b32 v43, s51, 6 ; SI-NEXT: v_readfirstlane_b32 s53, v30 -; SI-NEXT: v_writelane_b32 v42, s52, 6 +; SI-NEXT: v_writelane_b32 v43, s52, 7 ; SI-NEXT: v_readfirstlane_b32 s54, v28 -; SI-NEXT: v_writelane_b32 v42, s53, 7 +; SI-NEXT: v_writelane_b32 v43, s53, 8 ; SI-NEXT: v_readfirstlane_b32 s55, v27 -; SI-NEXT: v_writelane_b32 v42, s54, 8 -; SI-NEXT: v_writelane_b32 v42, s55, 9 +; SI-NEXT: v_writelane_b32 v43, s54, 9 +; SI-NEXT: v_writelane_b32 v43, s55, 10 +; SI-NEXT: s_mov_b32 s57, s24 ; SI-NEXT: v_readfirstlane_b32 s16, v1 ; SI-NEXT: v_readfirstlane_b32 s17, v2 -; SI-NEXT: v_readfirstlane_b32 s18, v5 -; SI-NEXT: v_readfirstlane_b32 s19, v6 -; SI-NEXT: v_readfirstlane_b32 s88, v4 ; SI-NEXT: s_waitcnt vmcnt(12) ; SI-NEXT: v_readfirstlane_b32 s6, v31 ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:300 @@ -154001,27 +151326,30 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:280 ; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_readfirstlane_b32 s4, v32 -; SI-NEXT: v_writelane_b32 v43, s4, 4 +; SI-NEXT: v_writelane_b32 v44, s4, 4 ; SI-NEXT: v_readfirstlane_b32 s4, v33 ; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:276 ; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:272 -; SI-NEXT: v_writelane_b32 v43, s4, 5 +; SI-NEXT: v_writelane_b32 v44, s4, 5 ; SI-NEXT: v_readfirstlane_b32 s4, v34 -; SI-NEXT: v_writelane_b32 v43, s4, 6 +; SI-NEXT: v_writelane_b32 v44, s4, 6 ; SI-NEXT: v_readfirstlane_b32 s4, v35 -; SI-NEXT: v_writelane_b32 v43, s4, 7 +; SI-NEXT: v_writelane_b32 v44, s4, 7 ; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_readfirstlane_b32 s4, v36 -; SI-NEXT: v_writelane_b32 v43, s4, 8 +; SI-NEXT: v_writelane_b32 v44, s4, 8 ; SI-NEXT: v_readfirstlane_b32 s4, v37 ; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:268 ; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:264 ; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:260 ; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:256 -; SI-NEXT: v_writelane_b32 v43, s4, 9 +; SI-NEXT: v_writelane_b32 v44, s4, 9 ; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_readfirstlane_b32 s4, v38 -; SI-NEXT: v_writelane_b32 v43, s4, 10 +; SI-NEXT: v_writelane_b32 v44, s4, 10 +; SI-NEXT: v_readfirstlane_b32 s18, v5 +; SI-NEXT: v_readfirstlane_b32 s19, v6 +; SI-NEXT: v_readfirstlane_b32 s77, v4 ; SI-NEXT: v_readfirstlane_b32 s89, v3 ; SI-NEXT: v_readfirstlane_b32 s90, v9 ; SI-NEXT: v_readfirstlane_b32 s91, v10 @@ -154034,22 +151362,23 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: v_readfirstlane_b32 s34, v16 ; SI-NEXT: v_readfirstlane_b32 s35, v15 ; SI-NEXT: v_readfirstlane_b32 s36, v21 -; SI-NEXT: v_readfirstlane_b32 s37, v22 +; SI-NEXT: s_waitcnt vmcnt(12) +; SI-NEXT: v_readfirstlane_b32 s24, v40 ; SI-NEXT: s_waitcnt vmcnt(11) ; SI-NEXT: v_readfirstlane_b32 s4, v31 -; SI-NEXT: v_writelane_b32 v43, s4, 11 +; SI-NEXT: v_writelane_b32 v44, s4, 11 ; SI-NEXT: s_waitcnt vmcnt(10) ; SI-NEXT: v_readfirstlane_b32 s4, v39 -; SI-NEXT: v_writelane_b32 v43, s4, 12 +; SI-NEXT: v_writelane_b32 v44, s4, 12 ; SI-NEXT: s_waitcnt vmcnt(9) ; SI-NEXT: v_readfirstlane_b32 s4, v48 -; SI-NEXT: v_writelane_b32 v43, s4, 13 +; SI-NEXT: v_writelane_b32 v44, s4, 13 ; SI-NEXT: s_waitcnt vmcnt(8) ; SI-NEXT: v_readfirstlane_b32 s4, v49 -; SI-NEXT: v_writelane_b32 v43, s4, 14 +; SI-NEXT: v_writelane_b32 v44, s4, 14 ; SI-NEXT: s_waitcnt vmcnt(7) ; SI-NEXT: v_readfirstlane_b32 s4, v50 -; SI-NEXT: v_writelane_b32 v43, s4, 15 +; SI-NEXT: v_writelane_b32 v44, s4, 15 ; SI-NEXT: s_waitcnt vmcnt(6) ; SI-NEXT: v_readfirstlane_b32 s4, v51 ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:252 @@ -154062,33 +151391,33 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_waitcnt vmcnt(12) ; SI-NEXT: v_readfirstlane_b32 s75, v32 ; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_readfirstlane_b32 s61, v33 +; SI-NEXT: v_readfirstlane_b32 s21, v33 ; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:224 ; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:220 -; SI-NEXT: v_writelane_b32 v43, s4, 16 +; SI-NEXT: v_writelane_b32 v44, s4, 16 ; SI-NEXT: s_waitcnt vmcnt(12) -; SI-NEXT: v_readfirstlane_b32 s43, v34 +; SI-NEXT: v_readfirstlane_b32 s4, v34 ; SI-NEXT: s_waitcnt vmcnt(11) ; SI-NEXT: v_readfirstlane_b32 s40, v35 ; SI-NEXT: s_waitcnt vmcnt(10) -; SI-NEXT: v_readfirstlane_b32 s4, v36 +; SI-NEXT: v_readfirstlane_b32 s61, v36 ; SI-NEXT: s_waitcnt vmcnt(9) ; SI-NEXT: v_readfirstlane_b32 s63, v37 ; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:216 ; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:212 ; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:208 ; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:204 -; SI-NEXT: v_writelane_b32 v43, s4, 17 +; SI-NEXT: v_writelane_b32 v44, s4, 17 ; SI-NEXT: s_waitcnt vmcnt(12) ; SI-NEXT: v_readfirstlane_b32 s59, v31 ; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_readfirstlane_b32 s42, v38 +; SI-NEXT: v_readfirstlane_b32 s56, v38 ; SI-NEXT: s_waitcnt vmcnt(10) -; SI-NEXT: v_readfirstlane_b32 s73, v39 +; SI-NEXT: v_readfirstlane_b32 s43, v39 ; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_readfirstlane_b32 s21, v48 +; SI-NEXT: v_readfirstlane_b32 s46, v48 ; SI-NEXT: s_waitcnt vmcnt(8) -; SI-NEXT: v_readfirstlane_b32 s57, v49 +; SI-NEXT: v_readfirstlane_b32 s42, v49 ; SI-NEXT: s_waitcnt vmcnt(7) ; SI-NEXT: v_readfirstlane_b32 s13, v50 ; SI-NEXT: s_waitcnt vmcnt(6) @@ -154101,43 +151430,44 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:180 ; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:176 ; SI-NEXT: s_waitcnt vmcnt(12) -; SI-NEXT: v_readfirstlane_b32 s47, v32 +; SI-NEXT: v_readfirstlane_b32 s88, v32 ; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_readfirstlane_b32 s24, v33 +; SI-NEXT: v_readfirstlane_b32 s79, v33 ; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:172 ; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:168 ; SI-NEXT: s_waitcnt vmcnt(12) -; SI-NEXT: v_readfirstlane_b32 s78, v34 +; SI-NEXT: v_readfirstlane_b32 s4, v34 +; SI-NEXT: v_writelane_b32 v44, s4, 18 ; SI-NEXT: s_waitcnt vmcnt(11) ; SI-NEXT: v_readfirstlane_b32 s4, v35 -; SI-NEXT: v_writelane_b32 v43, s4, 18 +; SI-NEXT: v_writelane_b32 v44, s4, 19 ; SI-NEXT: s_waitcnt vmcnt(10) ; SI-NEXT: v_readfirstlane_b32 s4, v36 -; SI-NEXT: v_writelane_b32 v43, s4, 19 +; SI-NEXT: v_writelane_b32 v44, s4, 20 ; SI-NEXT: s_waitcnt vmcnt(9) ; SI-NEXT: v_readfirstlane_b32 s4, v37 -; SI-NEXT: v_writelane_b32 v43, s4, 20 +; SI-NEXT: v_writelane_b32 v44, s4, 21 ; SI-NEXT: s_waitcnt vmcnt(8) ; SI-NEXT: v_readfirstlane_b32 s4, v31 -; SI-NEXT: v_writelane_b32 v43, s4, 21 +; SI-NEXT: v_writelane_b32 v44, s4, 22 ; SI-NEXT: s_waitcnt vmcnt(7) ; SI-NEXT: v_readfirstlane_b32 s4, v38 -; SI-NEXT: v_writelane_b32 v43, s4, 22 +; SI-NEXT: v_writelane_b32 v44, s4, 23 ; SI-NEXT: s_waitcnt vmcnt(6) ; SI-NEXT: v_readfirstlane_b32 s4, v39 -; SI-NEXT: v_writelane_b32 v43, s4, 23 +; SI-NEXT: v_writelane_b32 v44, s4, 24 ; SI-NEXT: s_waitcnt vmcnt(5) ; SI-NEXT: v_readfirstlane_b32 s4, v48 -; SI-NEXT: v_writelane_b32 v43, s4, 24 +; SI-NEXT: v_writelane_b32 v44, s4, 25 ; SI-NEXT: s_waitcnt vmcnt(4) ; SI-NEXT: v_readfirstlane_b32 s4, v49 -; SI-NEXT: v_writelane_b32 v43, s4, 25 +; SI-NEXT: v_writelane_b32 v44, s4, 26 ; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_readfirstlane_b32 s4, v50 -; SI-NEXT: v_writelane_b32 v43, s4, 26 +; SI-NEXT: v_writelane_b32 v44, s4, 27 ; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_readfirstlane_b32 s4, v51 -; SI-NEXT: v_writelane_b32 v43, s4, 27 +; SI-NEXT: v_writelane_b32 v44, s4, 28 ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:148 ; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:144 ; SI-NEXT: s_waitcnt vmcnt(3) @@ -154153,42 +151483,41 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:112 ; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:108 ; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:104 -; SI-NEXT: v_writelane_b32 v43, s4, 28 +; SI-NEXT: v_writelane_b32 v44, s4, 29 ; SI-NEXT: s_waitcnt vmcnt(13) ; SI-NEXT: v_readfirstlane_b32 s4, v52 -; SI-NEXT: v_writelane_b32 v43, s4, 29 +; SI-NEXT: v_writelane_b32 v44, s4, 30 ; SI-NEXT: v_readfirstlane_b32 s4, v53 -; SI-NEXT: v_writelane_b32 v43, s4, 30 +; SI-NEXT: v_writelane_b32 v44, s4, 31 ; SI-NEXT: v_readfirstlane_b32 s4, v54 -; SI-NEXT: v_writelane_b32 v43, s4, 31 +; SI-NEXT: v_writelane_b32 v44, s4, 32 ; SI-NEXT: v_readfirstlane_b32 s4, v55 -; SI-NEXT: v_writelane_b32 v43, s4, 32 -; SI-NEXT: v_readfirstlane_b32 s4, v40 -; SI-NEXT: v_writelane_b32 v43, s4, 33 -; SI-NEXT: v_writelane_b32 v43, s22, 34 -; SI-NEXT: v_writelane_b32 v43, s23, 35 -; SI-NEXT: v_writelane_b32 v43, s72, 36 -; SI-NEXT: v_writelane_b32 v43, s20, 37 -; SI-NEXT: v_writelane_b32 v43, s79, 38 -; SI-NEXT: v_writelane_b32 v43, s76, 39 -; SI-NEXT: v_writelane_b32 v43, s25, 40 -; SI-NEXT: v_writelane_b32 v43, s60, 41 -; SI-NEXT: v_writelane_b32 v43, s29, 42 -; SI-NEXT: v_writelane_b32 v43, s77, 43 -; SI-NEXT: v_writelane_b32 v43, s16, 44 -; SI-NEXT: v_writelane_b32 v43, s17, 45 -; SI-NEXT: v_writelane_b32 v43, s18, 46 -; SI-NEXT: v_writelane_b32 v43, s19, 47 -; SI-NEXT: v_writelane_b32 v43, s88, 48 -; SI-NEXT: v_writelane_b32 v43, s89, 49 -; SI-NEXT: v_writelane_b32 v43, s90, 50 -; SI-NEXT: v_writelane_b32 v43, s91, 51 -; SI-NEXT: v_writelane_b32 v43, s92, 52 -; SI-NEXT: v_writelane_b32 v43, s93, 53 -; SI-NEXT: v_writelane_b32 v43, s94, 54 -; SI-NEXT: v_writelane_b32 v43, s95, 55 +; SI-NEXT: v_writelane_b32 v44, s4, 33 +; SI-NEXT: v_writelane_b32 v44, s22, 34 +; SI-NEXT: v_writelane_b32 v44, s23, 35 +; SI-NEXT: v_writelane_b32 v44, s73, 36 +; SI-NEXT: v_writelane_b32 v44, s20, 37 +; SI-NEXT: v_writelane_b32 v44, s47, 38 +; SI-NEXT: v_writelane_b32 v44, s76, 39 +; SI-NEXT: v_writelane_b32 v44, s25, 40 +; SI-NEXT: v_writelane_b32 v44, s57, 41 +; SI-NEXT: v_writelane_b32 v44, s74, 42 +; SI-NEXT: v_writelane_b32 v44, s78, 43 +; SI-NEXT: v_writelane_b32 v44, s24, 44 +; SI-NEXT: v_writelane_b32 v44, s16, 45 +; SI-NEXT: v_writelane_b32 v44, s17, 46 +; SI-NEXT: v_writelane_b32 v44, s18, 47 +; SI-NEXT: v_writelane_b32 v44, s19, 48 +; SI-NEXT: v_writelane_b32 v44, s77, 49 +; SI-NEXT: v_writelane_b32 v44, s89, 50 +; SI-NEXT: v_writelane_b32 v44, s90, 51 +; SI-NEXT: v_writelane_b32 v44, s91, 52 +; SI-NEXT: v_writelane_b32 v44, s92, 53 +; SI-NEXT: v_writelane_b32 v44, s93, 54 +; SI-NEXT: v_writelane_b32 v44, s94, 55 +; SI-NEXT: v_writelane_b32 v44, s95, 56 ; SI-NEXT: s_waitcnt vmcnt(10) -; SI-NEXT: v_readfirstlane_b32 s62, v33 +; SI-NEXT: v_readfirstlane_b32 s58, v33 ; SI-NEXT: s_waitcnt vmcnt(9) ; SI-NEXT: v_readfirstlane_b32 s10, v34 ; SI-NEXT: s_waitcnt vmcnt(8) @@ -154196,7 +151525,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: v_readfirstlane_b32 s28, v31 ; SI-NEXT: v_readfirstlane_b32 s27, v32 ; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_readfirstlane_b32 s58, v36 +; SI-NEXT: v_readfirstlane_b32 s29, v36 ; SI-NEXT: s_waitcnt vmcnt(6) ; SI-NEXT: v_readfirstlane_b32 s69, v37 ; SI-NEXT: s_waitcnt vmcnt(5) @@ -154227,32 +151556,31 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_and_b64 s[4:5], vcc, exec ; SI-NEXT: v_readfirstlane_b32 vcc_lo, v12 ; SI-NEXT: v_readfirstlane_b32 vcc_hi, v11 -; SI-NEXT: v_writelane_b32 v43, vcc_lo, 56 -; SI-NEXT: v_writelane_b32 v43, vcc_hi, 57 -; SI-NEXT: v_writelane_b32 v43, s30, 58 -; SI-NEXT: v_writelane_b32 v43, s31, 59 -; SI-NEXT: v_writelane_b32 v43, s34, 60 -; SI-NEXT: v_writelane_b32 v43, s35, 61 -; SI-NEXT: v_writelane_b32 v43, s36, 62 -; SI-NEXT: v_writelane_b32 v43, s37, 63 +; SI-NEXT: v_writelane_b32 v44, vcc_lo, 57 +; SI-NEXT: v_writelane_b32 v44, vcc_hi, 58 +; SI-NEXT: v_writelane_b32 v44, s30, 59 +; SI-NEXT: v_writelane_b32 v44, s31, 60 +; SI-NEXT: v_writelane_b32 v44, s34, 61 +; SI-NEXT: v_writelane_b32 v44, s35, 62 +; SI-NEXT: v_writelane_b32 v44, s36, 63 ; SI-NEXT: s_waitcnt vmcnt(12) -; SI-NEXT: v_readfirstlane_b32 s74, v31 +; SI-NEXT: v_readfirstlane_b32 s60, v31 ; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_readfirstlane_b32 s46, v32 +; SI-NEXT: v_readfirstlane_b32 s62, v32 ; SI-NEXT: s_waitcnt vmcnt(10) -; SI-NEXT: v_readfirstlane_b32 s96, v33 +; SI-NEXT: v_readfirstlane_b32 s83, v33 ; SI-NEXT: s_waitcnt vmcnt(9) ; SI-NEXT: v_readfirstlane_b32 s98, v34 ; SI-NEXT: s_waitcnt vmcnt(8) -; SI-NEXT: v_readfirstlane_b32 s41, v35 +; SI-NEXT: v_readfirstlane_b32 s81, v35 ; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_readfirstlane_b32 s56, v36 +; SI-NEXT: v_readfirstlane_b32 s72, v36 ; SI-NEXT: s_waitcnt vmcnt(6) ; SI-NEXT: v_readfirstlane_b32 s87, v37 ; SI-NEXT: s_waitcnt vmcnt(5) ; SI-NEXT: v_readfirstlane_b32 s99, v38 ; SI-NEXT: s_waitcnt vmcnt(4) -; SI-NEXT: v_readfirstlane_b32 s81, v39 +; SI-NEXT: v_readfirstlane_b32 s82, v39 ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:48 ; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:44 ; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:40 @@ -154264,9 +151592,9 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_waitcnt vmcnt(11) ; SI-NEXT: v_readfirstlane_b32 s26, v48 ; SI-NEXT: s_waitcnt vmcnt(10) -; SI-NEXT: v_readfirstlane_b32 s83, v49 +; SI-NEXT: v_readfirstlane_b32 s15, v49 ; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_readfirstlane_b32 s82, v50 +; SI-NEXT: v_readfirstlane_b32 s96, v50 ; SI-NEXT: s_waitcnt vmcnt(8) ; SI-NEXT: v_readfirstlane_b32 s7, v51 ; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:16 @@ -154275,7 +151603,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:4 ; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 ; SI-NEXT: s_waitcnt vmcnt(12) -; SI-NEXT: v_readfirstlane_b32 s15, v31 +; SI-NEXT: v_readfirstlane_b32 s41, v31 ; SI-NEXT: s_waitcnt vmcnt(11) ; SI-NEXT: v_readfirstlane_b32 s97, v32 ; SI-NEXT: s_waitcnt vmcnt(10) @@ -154296,144 +151624,146 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: v_readfirstlane_b32 s65, v48 ; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_readfirstlane_b32 s64, v49 -; SI-NEXT: v_writelane_b32 v42, s64, 10 +; SI-NEXT: v_writelane_b32 v43, s64, 11 ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_readfirstlane_b32 s67, v50 -; SI-NEXT: v_writelane_b32 v42, s65, 11 +; SI-NEXT: v_writelane_b32 v43, s65, 12 ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_readfirstlane_b32 s84, v51 -; SI-NEXT: v_writelane_b32 v42, s67, 12 -; SI-NEXT: v_writelane_b32 v42, s84, 13 -; SI-NEXT: v_writelane_b32 v42, s85, 14 -; SI-NEXT: v_writelane_b32 v42, s86, 15 -; SI-NEXT: v_writelane_b32 v42, s87, 16 -; SI-NEXT: v_writelane_b32 v42, s8, 17 -; SI-NEXT: v_writelane_b32 v42, s99, 18 -; SI-NEXT: v_writelane_b32 v42, s12, 19 -; SI-NEXT: v_writelane_b32 v42, s44, 20 -; SI-NEXT: v_writelane_b32 v42, s97, 21 -; SI-NEXT: v_writelane_b32 v42, s83, 22 -; SI-NEXT: v_writelane_b32 v42, s82, 23 -; SI-NEXT: v_writelane_b32 v42, s98, 24 -; SI-NEXT: v_writelane_b32 v42, s96, 25 -; SI-NEXT: v_writelane_b32 v42, s81, 26 -; SI-NEXT: v_writelane_b32 v42, s9, 27 -; SI-NEXT: v_writelane_b32 v42, s41, 28 -; SI-NEXT: v_writelane_b32 v42, s80, 29 -; SI-NEXT: v_writelane_b32 v42, s7, 30 -; SI-NEXT: v_writelane_b32 v42, s56, 31 -; SI-NEXT: v_writelane_b32 v42, s26, 32 -; SI-NEXT: v_writelane_b32 v42, s15, 33 -; SI-NEXT: v_writelane_b32 v42, s14, 34 -; SI-NEXT: v_writelane_b32 v42, s69, 35 -; SI-NEXT: v_writelane_b32 v42, s71, 36 -; SI-NEXT: v_writelane_b32 v42, s70, 37 -; SI-NEXT: v_writelane_b32 v42, s68, 38 -; SI-NEXT: v_writelane_b32 v42, s74, 39 -; SI-NEXT: v_writelane_b32 v42, s46, 40 -; SI-NEXT: v_writelane_b32 v42, s11, 41 -; SI-NEXT: v_writelane_b32 v42, s10, 42 -; SI-NEXT: v_writelane_b32 v42, s62, 43 -; SI-NEXT: v_writelane_b32 v42, s66, 44 -; SI-NEXT: v_writelane_b32 v42, s58, 45 -; SI-NEXT: v_writelane_b32 v42, s28, 46 -; SI-NEXT: v_writelane_b32 v42, s27, 47 -; SI-NEXT: v_writelane_b32 v42, s78, 48 -; SI-NEXT: v_writelane_b32 v42, s24, 49 +; SI-NEXT: v_writelane_b32 v43, s67, 13 +; SI-NEXT: v_writelane_b32 v43, s84, 14 +; SI-NEXT: v_writelane_b32 v43, s85, 15 +; SI-NEXT: v_writelane_b32 v43, s86, 16 +; SI-NEXT: v_writelane_b32 v43, s87, 17 +; SI-NEXT: v_writelane_b32 v43, s8, 18 +; SI-NEXT: v_writelane_b32 v43, s99, 19 +; SI-NEXT: v_writelane_b32 v43, s12, 20 +; SI-NEXT: v_writelane_b32 v43, s44, 21 +; SI-NEXT: v_writelane_b32 v43, s97, 22 +; SI-NEXT: v_writelane_b32 v43, s15, 23 +; SI-NEXT: v_writelane_b32 v43, s96, 24 +; SI-NEXT: v_writelane_b32 v43, s98, 25 +; SI-NEXT: v_writelane_b32 v43, s83, 26 +; SI-NEXT: v_writelane_b32 v43, s82, 27 +; SI-NEXT: v_writelane_b32 v43, s9, 28 +; SI-NEXT: v_writelane_b32 v43, s81, 29 +; SI-NEXT: v_writelane_b32 v43, s80, 30 +; SI-NEXT: v_writelane_b32 v43, s7, 31 +; SI-NEXT: v_writelane_b32 v43, s72, 32 +; SI-NEXT: v_writelane_b32 v43, s26, 33 +; SI-NEXT: v_writelane_b32 v43, s41, 34 +; SI-NEXT: v_writelane_b32 v43, s14, 35 +; SI-NEXT: v_writelane_b32 v43, s69, 36 +; SI-NEXT: v_writelane_b32 v43, s71, 37 +; SI-NEXT: v_writelane_b32 v43, s70, 38 +; SI-NEXT: v_writelane_b32 v43, s68, 39 +; SI-NEXT: v_writelane_b32 v43, s60, 40 +; SI-NEXT: v_writelane_b32 v43, s62, 41 +; SI-NEXT: v_writelane_b32 v43, s11, 42 +; SI-NEXT: v_writelane_b32 v43, s10, 43 +; SI-NEXT: v_writelane_b32 v43, s58, 44 +; SI-NEXT: v_writelane_b32 v43, s66, 45 +; SI-NEXT: v_writelane_b32 v43, s29, 46 +; SI-NEXT: v_writelane_b32 v43, s28, 47 +; SI-NEXT: v_writelane_b32 v43, s27, 48 ; SI-NEXT: s_cbranch_scc0 .LBB89_4 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: v_readlane_b32 s4, v43, 3 +; SI-NEXT: v_readlane_b32 s4, v44, 3 ; SI-NEXT: s_and_b32 s4, s4, 0xff -; SI-NEXT: v_readlane_b32 s5, v43, 2 +; SI-NEXT: v_readlane_b32 s5, v44, 2 ; SI-NEXT: s_lshl_b32 s4, s4, 16 ; SI-NEXT: s_lshl_b32 s5, s5, 24 ; SI-NEXT: s_or_b32 s4, s5, s4 -; SI-NEXT: v_writelane_b32 v42, s4, 56 -; SI-NEXT: v_readlane_b32 s4, v43, 1 +; SI-NEXT: v_writelane_b32 v43, s4, 58 +; SI-NEXT: v_readlane_b32 s4, v44, 1 ; SI-NEXT: s_and_b32 s4, s4, 0xff -; SI-NEXT: v_readlane_b32 s5, v43, 0 +; SI-NEXT: v_readlane_b32 s5, v44, 0 ; SI-NEXT: s_lshl_b32 s4, s4, 16 ; SI-NEXT: s_lshl_b32 s5, s5, 24 ; SI-NEXT: s_or_b32 s4, s5, s4 -; SI-NEXT: v_writelane_b32 v42, s4, 57 +; SI-NEXT: v_writelane_b32 v43, s4, 59 ; SI-NEXT: s_and_b32 s4, s20, 0xff -; SI-NEXT: s_lshl_b32 s5, s72, 8 +; SI-NEXT: s_lshl_b32 s5, s73, 8 ; SI-NEXT: s_or_b32 s4, s4, s5 ; SI-NEXT: s_and_b32 s5, s22, 0xff ; SI-NEXT: s_lshl_b32 s5, s5, 16 ; SI-NEXT: s_mov_b32 s22, s6 ; SI-NEXT: s_lshl_b32 s6, s23, 24 -; SI-NEXT: v_writelane_b32 v42, s4, 58 +; SI-NEXT: v_writelane_b32 v43, s4, 60 ; SI-NEXT: s_or_b32 s4, s6, s5 -; SI-NEXT: s_and_b32 s5, s60, 0xff +; SI-NEXT: s_and_b32 s5, s57, 0xff ; SI-NEXT: s_lshl_b32 s5, s5, 16 ; SI-NEXT: s_lshl_b32 s6, s25, 24 -; SI-NEXT: v_writelane_b32 v42, s4, 59 -; SI-NEXT: s_or_b32 s5, s6, s5 -; SI-NEXT: v_writelane_b32 v42, s5, 60 -; SI-NEXT: s_and_b32 s5, s79, 0xff +; SI-NEXT: v_writelane_b32 v43, s4, 61 +; SI-NEXT: s_or_b32 s4, s6, s5 +; SI-NEXT: s_and_b32 s5, s47, 0xff ; SI-NEXT: s_lshl_b32 s5, s5, 16 ; SI-NEXT: s_lshl_b32 s6, s76, 24 -; SI-NEXT: s_or_b32 s5, s6, s5 -; SI-NEXT: v_writelane_b32 v42, s5, 61 -; SI-NEXT: s_and_b32 s5, s77, 0xff -; SI-NEXT: s_lshl_b32 s6, s29, 8 +; SI-NEXT: v_writelane_b32 v43, s4, 62 +; SI-NEXT: s_or_b32 s4, s6, s5 +; SI-NEXT: s_and_b32 s5, s78, 0xff +; SI-NEXT: s_lshl_b32 s6, s74, 8 ; SI-NEXT: s_or_b32 s5, s5, s6 ; SI-NEXT: s_and_b32 s6, s16, 0xff ; SI-NEXT: s_lshl_b32 s6, s6, 16 ; SI-NEXT: s_lshl_b32 s16, s17, 24 -; SI-NEXT: s_or_b32 s6, s16, s6 -; SI-NEXT: v_writelane_b32 v42, s6, 62 +; SI-NEXT: v_writelane_b32 v43, s4, 63 +; SI-NEXT: s_or_b32 s4, s16, s6 ; SI-NEXT: s_and_b32 s6, s89, 0xff +; SI-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane ; SI-NEXT: s_lshl_b32 s6, s6, 16 -; SI-NEXT: s_lshl_b32 s16, s88, 24 -; SI-NEXT: s_mov_b32 s4, s47 -; SI-NEXT: s_or_b32 s47, s16, s6 +; SI-NEXT: s_lshl_b32 s16, s77, 24 +; SI-NEXT: v_writelane_b32 v42, s4, 0 +; SI-NEXT: s_or_b32 s6, s16, s6 +; SI-NEXT: v_writelane_b32 v42, s6, 1 ; SI-NEXT: s_and_b32 s6, s18, 0xff ; SI-NEXT: s_lshl_b32 s6, s6, 16 ; SI-NEXT: s_lshl_b32 s16, s19, 24 -; SI-NEXT: s_or_b32 s25, s16, s6 +; SI-NEXT: s_or_b32 s76, s16, s6 ; SI-NEXT: s_and_b32 s6, s93, 0xff ; SI-NEXT: s_lshl_b32 s16, s92, 8 ; SI-NEXT: s_or_b32 s6, s6, s16 ; SI-NEXT: s_and_b32 s16, s90, 0xff ; SI-NEXT: s_lshl_b32 s16, s16, 16 ; SI-NEXT: s_lshl_b32 s17, s91, 24 -; SI-NEXT: s_or_b32 s92, s17, s16 +; SI-NEXT: s_or_b32 s77, s17, s16 ; SI-NEXT: s_and_b32 s16, vcc_hi, 0xff ; SI-NEXT: s_lshl_b32 s16, s16, 16 ; SI-NEXT: s_lshl_b32 s17, vcc_lo, 24 -; SI-NEXT: s_or_b32 s76, s17, s16 +; SI-NEXT: s_or_b32 s25, s17, s16 ; SI-NEXT: s_and_b32 s16, s94, 0xff ; SI-NEXT: s_lshl_b32 s16, s16, 16 ; SI-NEXT: s_lshl_b32 s17, s95, 24 -; SI-NEXT: s_or_b32 s91, s17, s16 +; SI-NEXT: s_or_b32 s74, s17, s16 ; SI-NEXT: s_and_b32 s16, s35, 0xff ; SI-NEXT: s_lshl_b32 s17, s34, 8 ; SI-NEXT: s_or_b32 s16, s16, s17 ; SI-NEXT: s_and_b32 s17, s30, 0xff ; SI-NEXT: s_lshl_b32 s17, s17, 16 ; SI-NEXT: s_lshl_b32 s18, s31, 24 -; SI-NEXT: s_or_b32 s77, s18, s17 +; SI-NEXT: s_or_b32 s78, s18, s17 ; SI-NEXT: s_and_b32 s17, s39, 0xff ; SI-NEXT: s_lshl_b32 s17, s17, 16 ; SI-NEXT: s_lshl_b32 s18, s38, 24 -; SI-NEXT: s_or_b32 s79, s18, s17 +; SI-NEXT: s_mov_b32 s31, s88 +; SI-NEXT: s_or_b32 s88, s18, s17 ; SI-NEXT: s_and_b32 s17, s36, 0xff ; SI-NEXT: s_lshl_b32 s17, s17, 16 ; SI-NEXT: s_lshl_b32 s18, s37, 24 -; SI-NEXT: s_or_b32 s93, s18, s17 +; SI-NEXT: s_or_b32 s89, s18, s17 ; SI-NEXT: s_and_b32 s17, s51, 0xff ; SI-NEXT: s_lshl_b32 s18, s50, 8 ; SI-NEXT: s_or_b32 s17, s17, s18 ; SI-NEXT: s_and_b32 s18, s48, 0xff ; SI-NEXT: s_lshl_b32 s18, s18, 16 ; SI-NEXT: s_lshl_b32 s19, s49, 24 -; SI-NEXT: s_or_b32 s89, s19, s18 +; SI-NEXT: s_or_b32 s18, s19, s18 +; SI-NEXT: v_writelane_b32 v43, s18, 49 ; SI-NEXT: s_and_b32 s18, s55, 0xff ; SI-NEXT: s_lshl_b32 s18, s18, 16 ; SI-NEXT: s_lshl_b32 s19, s54, 24 -; SI-NEXT: s_or_b32 s31, s19, s18 +; SI-NEXT: s_mov_b32 s73, s79 +; SI-NEXT: s_or_b32 s79, s19, s18 ; SI-NEXT: s_and_b32 s18, s52, 0xff ; SI-NEXT: s_lshl_b32 s18, s18, 16 ; SI-NEXT: s_lshl_b32 s19, s53, 24 @@ -154444,7 +151774,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_and_b32 s19, s64, 0xff ; SI-NEXT: s_lshl_b32 s19, s19, 16 ; SI-NEXT: s_lshl_b32 s20, s65, 24 -; SI-NEXT: s_or_b32 s60, s20, s19 +; SI-NEXT: s_or_b32 s95, s20, s19 ; SI-NEXT: s_and_b32 s19, s12, 0xff ; SI-NEXT: s_lshl_b32 s19, s19, 16 ; SI-NEXT: s_lshl_b32 s20, s8, 24 @@ -154460,217 +151790,226 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_lshl_b32 s19, s19, 16 ; SI-NEXT: s_lshl_b32 s20, s97, 24 ; SI-NEXT: s_or_b32 s9, s20, s19 -; SI-NEXT: s_and_b32 s19, s15, 0xff +; SI-NEXT: s_and_b32 s19, s41, 0xff ; SI-NEXT: s_lshl_b32 s19, s19, 16 ; SI-NEXT: s_lshl_b32 s20, s7, 24 ; SI-NEXT: s_or_b32 s7, s20, s19 -; SI-NEXT: s_and_b32 s19, s82, 0xff +; SI-NEXT: s_and_b32 s19, s96, 0xff ; SI-NEXT: s_lshl_b32 s19, s19, 16 -; SI-NEXT: s_lshl_b32 s20, s83, 24 -; SI-NEXT: s_or_b32 s23, s20, s19 +; SI-NEXT: s_lshl_b32 s20, s15, 24 +; SI-NEXT: v_writelane_b32 v43, s12, 50 +; SI-NEXT: s_or_b32 s12, s20, s19 ; SI-NEXT: s_and_b32 s19, s26, 0xff -; SI-NEXT: s_lshl_b32 s20, s81, 8 +; SI-NEXT: s_lshl_b32 s20, s82, 8 ; SI-NEXT: s_or_b32 vcc_hi, s19, s20 ; SI-NEXT: s_and_b32 s19, s99, 0xff -; SI-NEXT: v_writelane_b32 v42, s9, 50 ; SI-NEXT: s_lshl_b32 s19, s19, 16 ; SI-NEXT: s_lshl_b32 s20, s87, 24 -; SI-NEXT: v_writelane_b32 v42, s7, 51 -; SI-NEXT: s_or_b32 s7, s20, s19 -; SI-NEXT: s_and_b32 s19, s56, 0xff +; SI-NEXT: v_writelane_b32 v43, s9, 51 +; SI-NEXT: s_or_b32 s9, s20, s19 +; SI-NEXT: s_and_b32 s19, s72, 0xff ; SI-NEXT: s_lshl_b32 s19, s19, 16 -; SI-NEXT: s_lshl_b32 s20, s41, 24 -; SI-NEXT: v_writelane_b32 v42, s7, 52 -; SI-NEXT: s_or_b32 s7, s20, s19 +; SI-NEXT: s_lshl_b32 s20, s81, 24 +; SI-NEXT: v_writelane_b32 v43, s9, 52 +; SI-NEXT: s_or_b32 s9, s20, s19 ; SI-NEXT: s_and_b32 s19, s98, 0xff ; SI-NEXT: s_lshl_b32 s19, s19, 16 -; SI-NEXT: s_lshl_b32 s20, s96, 24 -; SI-NEXT: v_writelane_b32 v42, s7, 54 -; SI-NEXT: s_or_b32 s7, s20, s19 -; SI-NEXT: s_and_b32 s19, s46, 0xff -; SI-NEXT: s_lshl_b32 s20, s74, 8 +; SI-NEXT: s_lshl_b32 s20, s83, 24 +; SI-NEXT: v_writelane_b32 v43, s9, 54 +; SI-NEXT: s_or_b32 s9, s20, s19 +; SI-NEXT: s_and_b32 s19, s62, 0xff +; SI-NEXT: s_lshl_b32 s20, s60, 8 ; SI-NEXT: s_or_b32 s84, s19, s20 ; SI-NEXT: s_and_b32 s19, s71, 0xff ; SI-NEXT: s_lshl_b32 s19, s19, 16 ; SI-NEXT: s_lshl_b32 s20, s70, 24 -; SI-NEXT: s_or_b32 s72, s20, s19 +; SI-NEXT: v_writelane_b32 v43, s9, 53 +; SI-NEXT: s_or_b32 s9, s20, s19 ; SI-NEXT: s_and_b32 s19, s11, 0xff ; SI-NEXT: s_lshl_b32 s19, s19, 16 ; SI-NEXT: s_lshl_b32 s20, s68, 24 -; SI-NEXT: v_writelane_b32 v42, s7, 53 -; SI-NEXT: s_or_b32 s7, s20, s19 +; SI-NEXT: s_or_b32 s57, s20, s19 ; SI-NEXT: s_and_b32 s19, s14, 0xff ; SI-NEXT: s_lshl_b32 s19, s19, 16 ; SI-NEXT: s_lshl_b32 s20, s69, 24 +; SI-NEXT: v_writelane_b32 v43, s9, 55 ; SI-NEXT: s_or_b32 s9, s20, s19 -; SI-NEXT: s_and_b32 s19, s58, 0xff +; SI-NEXT: s_and_b32 s19, s29, 0xff ; SI-NEXT: s_lshl_b32 s20, s66, 8 ; SI-NEXT: s_or_b32 s85, s19, s20 ; SI-NEXT: s_and_b32 s19, s10, 0xff ; SI-NEXT: s_lshl_b32 s19, s19, 16 -; SI-NEXT: s_lshl_b32 s20, s62, 24 -; SI-NEXT: s_or_b32 s49, s20, s19 +; SI-NEXT: s_lshl_b32 s20, s58, 24 +; SI-NEXT: v_writelane_b32 v43, s9, 56 +; SI-NEXT: s_or_b32 s9, s20, s19 ; SI-NEXT: s_and_b32 s19, s27, 0xff -; SI-NEXT: v_writelane_b32 v42, s9, 55 ; SI-NEXT: s_lshl_b32 s19, s19, 16 ; SI-NEXT: s_lshl_b32 s20, s28, 24 -; SI-NEXT: v_readlane_b32 s9, v43, 33 -; SI-NEXT: s_or_b32 s50, s20, s19 -; SI-NEXT: s_and_b32 s19, s9, 0xff -; SI-NEXT: v_readlane_b32 s9, v43, 32 +; SI-NEXT: v_writelane_b32 v43, s9, 57 +; SI-NEXT: s_or_b32 s23, s20, s19 +; SI-NEXT: s_and_b32 s19, s24, 0xff +; SI-NEXT: v_readlane_b32 s9, v44, 33 ; SI-NEXT: s_lshl_b32 s19, s19, 16 ; SI-NEXT: s_lshl_b32 s20, s9, 24 -; SI-NEXT: v_readlane_b32 s9, v43, 31 -; SI-NEXT: s_or_b32 s51, s20, s19 +; SI-NEXT: v_readlane_b32 s9, v44, 32 +; SI-NEXT: s_or_b32 s10, s20, s19 ; SI-NEXT: s_and_b32 s19, s9, 0xff -; SI-NEXT: v_readlane_b32 s9, v43, 30 +; SI-NEXT: v_readlane_b32 s9, v44, 31 ; SI-NEXT: s_lshl_b32 s20, s9, 8 -; SI-NEXT: v_readlane_b32 s9, v43, 29 +; SI-NEXT: v_readlane_b32 s9, v44, 30 ; SI-NEXT: s_or_b32 s86, s19, s20 ; SI-NEXT: s_and_b32 s19, s9, 0xff -; SI-NEXT: v_readlane_b32 s9, v43, 28 +; SI-NEXT: v_readlane_b32 s9, v44, 29 ; SI-NEXT: s_lshl_b32 s19, s19, 16 ; SI-NEXT: s_lshl_b32 s20, s9, 24 -; SI-NEXT: v_readlane_b32 s9, v43, 27 -; SI-NEXT: s_or_b32 s52, s20, s19 +; SI-NEXT: v_readlane_b32 s9, v44, 28 +; SI-NEXT: s_or_b32 s47, s20, s19 ; SI-NEXT: s_and_b32 s19, s9, 0xff -; SI-NEXT: v_readlane_b32 s9, v43, 26 +; SI-NEXT: v_readlane_b32 s9, v44, 27 ; SI-NEXT: s_lshl_b32 s19, s19, 16 ; SI-NEXT: s_lshl_b32 s20, s9, 24 -; SI-NEXT: v_readlane_b32 s9, v43, 25 -; SI-NEXT: s_or_b32 s53, s20, s19 -; SI-NEXT: s_and_b32 s19, s9, 0xff -; SI-NEXT: v_readlane_b32 s9, v43, 24 +; SI-NEXT: v_readlane_b32 s11, v44, 26 +; SI-NEXT: s_or_b32 s9, s20, s19 +; SI-NEXT: s_and_b32 s19, s11, 0xff +; SI-NEXT: v_readlane_b32 s11, v44, 25 ; SI-NEXT: s_lshl_b32 s19, s19, 16 -; SI-NEXT: s_lshl_b32 s20, s9, 24 -; SI-NEXT: v_readlane_b32 s9, v43, 23 -; SI-NEXT: s_or_b32 s54, s20, s19 -; SI-NEXT: s_and_b32 s19, s9, 0xff -; SI-NEXT: v_readlane_b32 s9, v43, 22 -; SI-NEXT: s_lshl_b32 s20, s9, 8 -; SI-NEXT: v_readlane_b32 s9, v43, 21 +; SI-NEXT: s_lshl_b32 s20, s11, 24 +; SI-NEXT: v_readlane_b32 s11, v44, 24 +; SI-NEXT: s_or_b32 s24, s20, s19 +; SI-NEXT: s_mov_b32 s92, s11 +; SI-NEXT: s_and_b32 s19, s11, 0xff +; SI-NEXT: v_readlane_b32 s11, v44, 23 +; SI-NEXT: s_mov_b32 s36, s11 +; SI-NEXT: s_lshl_b32 s20, s11, 8 +; SI-NEXT: v_readlane_b32 s11, v44, 22 ; SI-NEXT: s_or_b32 s87, s19, s20 -; SI-NEXT: s_and_b32 s19, s9, 0xff -; SI-NEXT: v_readlane_b32 s9, v43, 20 +; SI-NEXT: s_mov_b32 s62, s11 +; SI-NEXT: s_and_b32 s19, s11, 0xff +; SI-NEXT: v_readlane_b32 s11, v44, 21 ; SI-NEXT: s_lshl_b32 s19, s19, 16 -; SI-NEXT: s_lshl_b32 s20, s9, 24 -; SI-NEXT: v_readlane_b32 s9, v43, 19 -; SI-NEXT: s_or_b32 s55, s20, s19 -; SI-NEXT: s_mov_b32 s58, s9 -; SI-NEXT: s_and_b32 s19, s9, 0xff -; SI-NEXT: v_readlane_b32 s9, v43, 18 +; SI-NEXT: s_mov_b32 s30, s11 +; SI-NEXT: s_lshl_b32 s20, s11, 24 +; SI-NEXT: v_readlane_b32 s11, v44, 20 +; SI-NEXT: s_or_b32 s58, s20, s19 +; SI-NEXT: s_mov_b32 s91, s11 +; SI-NEXT: s_and_b32 s19, s11, 0xff +; SI-NEXT: v_readlane_b32 s11, v44, 19 ; SI-NEXT: s_lshl_b32 s19, s19, 16 -; SI-NEXT: s_lshl_b32 s20, s9, 24 -; SI-NEXT: s_or_b32 s64, s20, s19 -; SI-NEXT: s_and_b32 s19, s78, 0xff +; SI-NEXT: s_mov_b32 s35, s11 +; SI-NEXT: s_lshl_b32 s20, s11, 24 +; SI-NEXT: v_readlane_b32 s11, v44, 18 +; SI-NEXT: s_mov_b32 s4, s46 +; SI-NEXT: s_or_b32 s46, s20, s19 +; SI-NEXT: s_and_b32 s19, s11, 0xff ; SI-NEXT: s_lshl_b32 s19, s19, 16 -; SI-NEXT: s_lshl_b32 s20, s24, 24 -; SI-NEXT: s_or_b32 s65, s20, s19 -; SI-NEXT: s_and_b32 s19, s4, 0xff +; SI-NEXT: s_lshl_b32 s20, s73, 24 +; SI-NEXT: s_mov_b32 s52, s73 +; SI-NEXT: s_or_b32 s73, s20, s19 +; SI-NEXT: s_and_b32 s19, s31, 0xff ; SI-NEXT: s_lshl_b32 s20, s45, 8 ; SI-NEXT: s_or_b32 s26, s19, s20 ; SI-NEXT: s_and_b32 s19, s13, 0xff ; SI-NEXT: s_lshl_b32 s19, s19, 16 -; SI-NEXT: s_lshl_b32 s20, s57, 24 -; SI-NEXT: s_or_b32 s66, s20, s19 -; SI-NEXT: s_and_b32 s19, s21, 0xff -; SI-NEXT: s_lshl_b32 s19, s19, 16 -; SI-NEXT: s_lshl_b32 s20, s73, 24 +; SI-NEXT: s_lshl_b32 s20, s42, 24 ; SI-NEXT: s_or_b32 s67, s20, s19 -; SI-NEXT: s_and_b32 s19, s42, 0xff -; SI-NEXT: v_readlane_b32 s88, v43, 17 +; SI-NEXT: s_and_b32 s19, s4, 0xff +; SI-NEXT: s_lshl_b32 s19, s19, 16 +; SI-NEXT: s_lshl_b32 s20, s43, 24 +; SI-NEXT: s_mov_b32 s53, s42 +; SI-NEXT: s_or_b32 s42, s20, s19 +; SI-NEXT: s_and_b32 s19, s56, 0xff ; SI-NEXT: s_lshl_b32 s19, s19, 16 ; SI-NEXT: s_lshl_b32 s20, s59, 24 ; SI-NEXT: s_or_b32 s68, s20, s19 ; SI-NEXT: s_and_b32 s19, s63, 0xff -; SI-NEXT: s_lshl_b32 s20, s88, 8 +; SI-NEXT: s_lshl_b32 s20, s61, 8 +; SI-NEXT: v_readlane_b32 s93, v44, 17 ; SI-NEXT: s_or_b32 s27, s19, s20 ; SI-NEXT: s_and_b32 s19, s40, 0xff ; SI-NEXT: s_lshl_b32 s19, s19, 16 -; SI-NEXT: s_lshl_b32 s20, s43, 24 -; SI-NEXT: s_or_b32 s69, s20, s19 -; SI-NEXT: s_and_b32 s19, s61, 0xff -; SI-NEXT: s_mov_b32 s39, s57 -; SI-NEXT: s_mov_b32 s57, s7 +; SI-NEXT: s_lshl_b32 s20, s93, 24 +; SI-NEXT: s_or_b32 s70, s20, s19 +; SI-NEXT: s_and_b32 s19, s21, 0xff +; SI-NEXT: s_mov_b32 s51, s59 +; SI-NEXT: s_mov_b32 s59, s7 ; SI-NEXT: s_lshl_b32 s19, s19, 16 ; SI-NEXT: s_lshl_b32 s20, s75, 24 -; SI-NEXT: v_readlane_b32 s7, v43, 16 -; SI-NEXT: s_or_b32 s70, s20, s19 +; SI-NEXT: v_readlane_b32 s7, v44, 16 +; SI-NEXT: s_mov_b32 s48, s56 +; SI-NEXT: s_mov_b32 s56, s10 +; SI-NEXT: s_or_b32 s69, s20, s19 ; SI-NEXT: s_mov_b32 s10, s7 ; SI-NEXT: s_and_b32 s19, s7, 0xff -; SI-NEXT: v_readlane_b32 s7, v43, 15 +; SI-NEXT: v_readlane_b32 s7, v44, 15 ; SI-NEXT: s_lshl_b32 s19, s19, 16 ; SI-NEXT: s_mov_b32 s71, s7 ; SI-NEXT: s_lshl_b32 s20, s7, 24 -; SI-NEXT: v_readlane_b32 s7, v43, 14 -; SI-NEXT: s_or_b32 s62, s20, s19 -; SI-NEXT: s_mov_b32 s15, s7 -; SI-NEXT: s_and_b32 s19, s7, 0xff -; SI-NEXT: v_readlane_b32 s7, v43, 13 +; SI-NEXT: v_readlane_b32 s7, v44, 14 +; SI-NEXT: s_mov_b32 s39, s75 +; SI-NEXT: s_mov_b32 s75, s94 +; SI-NEXT: s_or_b32 s94, s20, s19 ; SI-NEXT: s_mov_b32 s41, s7 +; SI-NEXT: s_and_b32 s19, s7, 0xff +; SI-NEXT: v_readlane_b32 s7, v44, 13 +; SI-NEXT: s_mov_b32 s14, s7 ; SI-NEXT: s_lshl_b32 s20, s7, 8 -; SI-NEXT: v_readlane_b32 s7, v43, 12 +; SI-NEXT: v_readlane_b32 s7, v44, 12 ; SI-NEXT: s_or_b32 s29, s19, s20 -; SI-NEXT: s_mov_b32 s14, s7 +; SI-NEXT: s_mov_b32 s81, s7 ; SI-NEXT: s_and_b32 s19, s7, 0xff -; SI-NEXT: v_readlane_b32 s7, v43, 11 +; SI-NEXT: v_readlane_b32 s7, v44, 11 +; SI-NEXT: s_mov_b32 s55, s45 +; SI-NEXT: s_mov_b32 s45, s9 ; SI-NEXT: s_lshl_b32 s19, s19, 16 ; SI-NEXT: s_mov_b32 s9, s7 ; SI-NEXT: s_lshl_b32 s20, s7, 24 -; SI-NEXT: v_readlane_b32 s7, v43, 10 -; SI-NEXT: s_or_b32 s80, s20, s19 -; SI-NEXT: s_mov_b32 s56, s7 +; SI-NEXT: v_readlane_b32 s7, v44, 10 +; SI-NEXT: s_mov_b32 s38, s11 +; SI-NEXT: s_or_b32 s11, s20, s19 +; SI-NEXT: s_mov_b32 s72, s7 ; SI-NEXT: s_and_b32 s19, s7, 0xff -; SI-NEXT: v_readlane_b32 s7, v43, 9 +; SI-NEXT: v_readlane_b32 s7, v44, 9 ; SI-NEXT: s_lshl_b32 s19, s19, 16 -; SI-NEXT: s_mov_b32 s81, s7 -; SI-NEXT: s_lshl_b32 s20, s7, 24 -; SI-NEXT: v_readlane_b32 s7, v43, 8 -; SI-NEXT: s_or_b32 s11, s20, s19 ; SI-NEXT: s_mov_b32 s82, s7 +; SI-NEXT: s_lshl_b32 s20, s7, 24 +; SI-NEXT: v_readlane_b32 s7, v44, 8 +; SI-NEXT: s_or_b32 s80, s20, s19 +; SI-NEXT: s_mov_b32 s83, s7 ; SI-NEXT: s_and_b32 s19, s7, 0xff -; SI-NEXT: v_readlane_b32 s7, v43, 7 +; SI-NEXT: v_readlane_b32 s7, v44, 7 ; SI-NEXT: s_lshl_b32 s19, s19, 16 ; SI-NEXT: s_mov_b32 s96, s7 ; SI-NEXT: s_lshl_b32 s20, s7, 24 -; SI-NEXT: v_readlane_b32 s7, v43, 6 -; SI-NEXT: s_mov_b32 s36, s63 -; SI-NEXT: s_mov_b32 s63, s93 -; SI-NEXT: s_mov_b32 s93, s61 -; SI-NEXT: s_mov_b32 s61, s91 -; SI-NEXT: s_mov_b32 s91, s75 -; SI-NEXT: s_mov_b32 s75, s92 -; SI-NEXT: s_or_b32 s92, s20, s19 +; SI-NEXT: v_readlane_b32 s7, v44, 6 +; SI-NEXT: s_mov_b32 s90, s31 +; SI-NEXT: s_or_b32 s31, s20, s19 ; SI-NEXT: s_mov_b32 s98, s7 ; SI-NEXT: s_and_b32 s19, s7, 0xff -; SI-NEXT: v_readlane_b32 s7, v43, 5 +; SI-NEXT: v_readlane_b32 s7, v44, 5 ; SI-NEXT: s_mov_b32 s44, s7 ; SI-NEXT: s_lshl_b32 s20, s7, 8 -; SI-NEXT: v_readlane_b32 s7, v43, 4 -; SI-NEXT: s_mov_b32 s48, s13 -; SI-NEXT: s_mov_b32 s13, s94 -; SI-NEXT: s_mov_b32 s94, s21 +; SI-NEXT: v_readlane_b32 s7, v44, 4 +; SI-NEXT: s_mov_b32 s37, s43 +; SI-NEXT: s_mov_b32 s43, s93 +; SI-NEXT: s_mov_b32 s93, s21 ; SI-NEXT: s_or_b32 s21, s19, s20 ; SI-NEXT: s_and_b32 s19, s7, 0xff -; SI-NEXT: s_mov_b32 s95, s4 +; SI-NEXT: s_mov_b32 s34, s4 ; SI-NEXT: s_lshl_b32 s19, s19, 16 ; SI-NEXT: s_lshl_b32 s20, s22, 24 -; SI-NEXT: v_readlane_b32 s4, v42, 58 -; SI-NEXT: s_mov_b32 s46, s45 -; SI-NEXT: s_mov_b32 s34, s73 -; SI-NEXT: s_mov_b32 s73, s12 -; SI-NEXT: s_mov_b32 s37, s42 -; SI-NEXT: s_mov_b32 s38, s59 -; SI-NEXT: s_mov_b32 s59, s8 -; SI-NEXT: s_mov_b32 s30, s88 -; SI-NEXT: s_mov_b32 s88, s31 -; SI-NEXT: s_mov_b32 s78, s40 -; SI-NEXT: s_mov_b32 s31, s43 +; SI-NEXT: v_readlane_b32 s4, v43, 60 +; SI-NEXT: s_mov_b32 s54, s13 +; SI-NEXT: s_mov_b32 s13, s12 +; SI-NEXT: s_mov_b32 s50, s63 +; SI-NEXT: s_mov_b32 s63, s95 +; SI-NEXT: s_mov_b32 s49, s61 +; SI-NEXT: s_mov_b32 s61, s8 +; SI-NEXT: s_mov_b32 s60, s40 ; SI-NEXT: s_mov_b32 s12, s7 ; SI-NEXT: s_mov_b32 s7, s22 -; SI-NEXT: s_or_b32 s83, s20, s19 +; SI-NEXT: s_or_b32 s15, s20, s19 ; SI-NEXT: s_lshl_b32 s20, s4, 16 -; SI-NEXT: s_lshl_b32 s74, s5, 16 +; SI-NEXT: s_lshl_b32 s95, s5, 16 ; SI-NEXT: s_lshl_b32 s22, s6, 16 ; SI-NEXT: s_lshl_b32 s16, s16, 16 ; SI-NEXT: s_lshl_b32 s19, s17, 16 @@ -154682,16 +152021,16 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_lshl_b32 s97, s86, 16 ; SI-NEXT: s_lshl_b32 s28, s87, 16 ; SI-NEXT: s_lshl_b32 s87, s26, 16 -; SI-NEXT: v_readlane_b32 s26, v42, 56 +; SI-NEXT: v_readlane_b32 s26, v43, 58 ; SI-NEXT: s_lshl_b32 s86, s27, 16 -; SI-NEXT: v_readlane_b32 s27, v42, 57 -; SI-NEXT: v_readlane_b32 s35, v42, 61 +; SI-NEXT: v_readlane_b32 s27, v43, 59 +; SI-NEXT: v_readlane_b32 s66, v43, 63 ; SI-NEXT: s_lshl_b32 s85, s29, 16 -; SI-NEXT: v_readlane_b32 s29, v42, 60 -; SI-NEXT: v_readlane_b32 s24, v42, 59 -; SI-NEXT: v_readlane_b32 s90, v42, 62 +; SI-NEXT: v_readlane_b32 s29, v43, 62 +; SI-NEXT: v_readlane_b32 s65, v43, 61 +; SI-NEXT: v_readlane_b32 s64, v42, 0 ; SI-NEXT: s_lshl_b32 s84, s21, 16 -; SI-NEXT: s_mov_b32 s21, s47 +; SI-NEXT: v_readlane_b32 s21, v42, 1 ; SI-NEXT: s_cbranch_execnz .LBB89_3 ; SI-NEXT: .LBB89_2: ; %cmp.true ; SI-NEXT: s_add_i32 s4, s98, 3 @@ -154706,10 +152045,10 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_or_b32 s5, s5, s6 ; SI-NEXT: s_and_b32 s4, s4, 0xffff ; SI-NEXT: s_or_b32 s4, s5, s4 -; SI-NEXT: s_add_i32 s5, s56, 3 +; SI-NEXT: s_add_i32 s5, s72, 3 ; SI-NEXT: s_and_b32 s5, s5, 0xff -; SI-NEXT: s_lshl_b32 s6, s81, 8 -; SI-NEXT: s_add_i32 s16, s82, 3 +; SI-NEXT: s_lshl_b32 s6, s82, 8 +; SI-NEXT: s_add_i32 s16, s83, 3 ; SI-NEXT: s_or_b32 s5, s6, s5 ; SI-NEXT: s_and_b32 s16, s16, 0xff ; SI-NEXT: s_lshl_b32 s6, s96, 24 @@ -154718,10 +152057,10 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_or_b32 s6, s6, s16 ; SI-NEXT: s_and_b32 s5, s5, 0xffff ; SI-NEXT: s_or_b32 s5, s6, s5 -; SI-NEXT: s_add_i32 s6, s15, 3 +; SI-NEXT: s_add_i32 s6, s41, 3 ; SI-NEXT: s_and_b32 s6, s6, 0xff -; SI-NEXT: s_lshl_b32 s16, s41, 8 -; SI-NEXT: s_add_i32 s17, s14, 3 +; SI-NEXT: s_lshl_b32 s16, s14, 8 +; SI-NEXT: s_add_i32 s17, s81, 3 ; SI-NEXT: s_or_b32 s6, s16, s6 ; SI-NEXT: s_and_b32 s17, s17, 0xff ; SI-NEXT: s_lshl_b32 s16, s9, 24 @@ -154732,7 +152071,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_or_b32 s6, s16, s6 ; SI-NEXT: s_add_i32 s16, s93, 3 ; SI-NEXT: s_and_b32 s16, s16, 0xff -; SI-NEXT: s_lshl_b32 s17, s91, 8 +; SI-NEXT: s_lshl_b32 s17, s39, 8 ; SI-NEXT: s_add_i32 s18, s10, 3 ; SI-NEXT: s_or_b32 s16, s17, s16 ; SI-NEXT: s_and_b32 s18, s18, 0xff @@ -154742,150 +152081,143 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_or_b32 s17, s17, s18 ; SI-NEXT: s_and_b32 s16, s16, 0xffff ; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: s_add_i32 s17, s36, 3 +; SI-NEXT: s_add_i32 s17, s50, 3 ; SI-NEXT: s_and_b32 s17, s17, 0xff -; SI-NEXT: s_lshl_b32 s18, s30, 8 -; SI-NEXT: s_add_i32 s19, s78, 3 +; SI-NEXT: s_lshl_b32 s18, s49, 8 +; SI-NEXT: s_add_i32 s19, s60, 3 ; SI-NEXT: s_or_b32 s17, s18, s17 ; SI-NEXT: s_and_b32 s19, s19, 0xff -; SI-NEXT: s_lshl_b32 s18, s31, 24 +; SI-NEXT: s_lshl_b32 s18, s43, 24 ; SI-NEXT: s_lshl_b32 s19, s19, 16 ; SI-NEXT: s_addk_i32 s17, 0x300 ; SI-NEXT: s_or_b32 s18, s18, s19 ; SI-NEXT: s_and_b32 s17, s17, 0xffff ; SI-NEXT: s_or_b32 s17, s18, s17 -; SI-NEXT: s_add_i32 s18, s94, 3 +; SI-NEXT: s_add_i32 s18, s34, 3 ; SI-NEXT: s_and_b32 s18, s18, 0xff -; SI-NEXT: s_lshl_b32 s19, s34, 8 -; SI-NEXT: s_add_i32 s20, s37, 3 +; SI-NEXT: s_lshl_b32 s19, s37, 8 +; SI-NEXT: s_add_i32 s20, s48, 3 ; SI-NEXT: s_or_b32 s18, s19, s18 ; SI-NEXT: s_and_b32 s20, s20, 0xff -; SI-NEXT: s_lshl_b32 s19, s38, 24 +; SI-NEXT: s_lshl_b32 s19, s51, 24 ; SI-NEXT: s_lshl_b32 s20, s20, 16 ; SI-NEXT: s_addk_i32 s18, 0x300 ; SI-NEXT: s_or_b32 s19, s19, s20 ; SI-NEXT: s_and_b32 s18, s18, 0xffff ; SI-NEXT: s_or_b32 s18, s19, s18 -; SI-NEXT: s_add_i32 s19, s95, 3 +; SI-NEXT: s_add_i32 s19, s90, 3 ; SI-NEXT: s_and_b32 s19, s19, 0xff -; SI-NEXT: s_lshl_b32 s20, s46, 8 -; SI-NEXT: s_add_i32 s22, s48, 3 +; SI-NEXT: s_lshl_b32 s20, s55, 8 +; SI-NEXT: s_add_i32 s22, s54, 3 ; SI-NEXT: s_or_b32 s19, s20, s19 ; SI-NEXT: s_and_b32 s22, s22, 0xff -; SI-NEXT: s_lshl_b32 s20, s39, 24 +; SI-NEXT: s_lshl_b32 s20, s53, 24 ; SI-NEXT: s_lshl_b32 s22, s22, 16 ; SI-NEXT: s_addk_i32 s19, 0x300 ; SI-NEXT: s_or_b32 s20, s20, s22 ; SI-NEXT: s_and_b32 s19, s19, 0xffff ; SI-NEXT: s_or_b32 s19, s20, s19 -; SI-NEXT: s_add_i32 s20, s58, 3 -; SI-NEXT: v_readlane_b32 s7, v43, 18 +; SI-NEXT: s_add_i32 s20, s91, 3 ; SI-NEXT: s_and_b32 s20, s20, 0xff -; SI-NEXT: s_lshl_b32 s22, s7, 8 -; SI-NEXT: v_readlane_b32 s7, v42, 49 +; SI-NEXT: s_lshl_b32 s22, s35, 8 +; SI-NEXT: s_add_i32 s23, s38, 3 ; SI-NEXT: s_or_b32 s20, s22, s20 -; SI-NEXT: s_lshl_b32 s22, s7, 24 -; SI-NEXT: v_readlane_b32 s7, v42, 48 -; SI-NEXT: s_add_i32 s23, s7, 3 ; SI-NEXT: s_and_b32 s23, s23, 0xff +; SI-NEXT: s_lshl_b32 s22, s52, 24 ; SI-NEXT: s_lshl_b32 s23, s23, 16 ; SI-NEXT: s_addk_i32 s20, 0x300 ; SI-NEXT: s_or_b32 s22, s22, s23 ; SI-NEXT: s_and_b32 s20, s20, 0xffff -; SI-NEXT: v_readlane_b32 s7, v43, 23 ; SI-NEXT: s_or_b32 s20, s22, s20 -; SI-NEXT: s_add_i32 s22, s7, 3 -; SI-NEXT: v_readlane_b32 s7, v43, 22 +; SI-NEXT: s_add_i32 s22, s92, 3 ; SI-NEXT: s_and_b32 s22, s22, 0xff -; SI-NEXT: s_lshl_b32 s23, s7, 8 -; SI-NEXT: v_readlane_b32 s7, v43, 20 +; SI-NEXT: s_lshl_b32 s23, s36, 8 +; SI-NEXT: s_add_i32 s60, s62, 3 ; SI-NEXT: s_or_b32 s22, s23, s22 -; SI-NEXT: s_lshl_b32 s23, s7, 24 -; SI-NEXT: v_readlane_b32 s7, v43, 21 -; SI-NEXT: s_add_i32 s60, s7, 3 ; SI-NEXT: s_and_b32 s60, s60, 0xff +; SI-NEXT: s_lshl_b32 s23, s30, 24 ; SI-NEXT: s_lshl_b32 s60, s60, 16 ; SI-NEXT: s_addk_i32 s22, 0x300 ; SI-NEXT: s_or_b32 s23, s23, s60 ; SI-NEXT: s_and_b32 s22, s22, 0xffff -; SI-NEXT: v_readlane_b32 s7, v43, 27 +; SI-NEXT: v_readlane_b32 s7, v44, 28 ; SI-NEXT: s_or_b32 s22, s23, s22 ; SI-NEXT: s_add_i32 s23, s7, 3 -; SI-NEXT: v_readlane_b32 s7, v43, 26 +; SI-NEXT: v_readlane_b32 s7, v44, 27 ; SI-NEXT: s_and_b32 s23, s23, 0xff ; SI-NEXT: s_lshl_b32 s60, s7, 8 -; SI-NEXT: v_readlane_b32 s7, v43, 24 +; SI-NEXT: v_readlane_b32 s7, v44, 25 ; SI-NEXT: s_or_b32 s23, s60, s23 ; SI-NEXT: s_lshl_b32 s60, s7, 24 -; SI-NEXT: v_readlane_b32 s7, v43, 25 +; SI-NEXT: v_readlane_b32 s7, v44, 26 ; SI-NEXT: s_add_i32 s61, s7, 3 ; SI-NEXT: s_and_b32 s61, s61, 0xff ; SI-NEXT: s_lshl_b32 s61, s61, 16 ; SI-NEXT: s_addk_i32 s23, 0x300 ; SI-NEXT: s_or_b32 s60, s60, s61 ; SI-NEXT: s_and_b32 s23, s23, 0xffff -; SI-NEXT: v_readlane_b32 s7, v43, 31 +; SI-NEXT: v_readlane_b32 s7, v44, 32 ; SI-NEXT: s_or_b32 s23, s60, s23 ; SI-NEXT: s_add_i32 s60, s7, 3 -; SI-NEXT: v_readlane_b32 s7, v43, 30 +; SI-NEXT: v_readlane_b32 s7, v44, 31 ; SI-NEXT: s_and_b32 s60, s60, 0xff ; SI-NEXT: s_lshl_b32 s61, s7, 8 -; SI-NEXT: v_readlane_b32 s7, v43, 28 +; SI-NEXT: v_readlane_b32 s7, v44, 29 ; SI-NEXT: s_or_b32 s60, s61, s60 ; SI-NEXT: s_lshl_b32 s61, s7, 24 -; SI-NEXT: v_readlane_b32 s7, v43, 29 +; SI-NEXT: v_readlane_b32 s7, v44, 30 ; SI-NEXT: s_add_i32 s62, s7, 3 -; SI-NEXT: v_readlane_b32 s7, v42, 47 +; SI-NEXT: v_readlane_b32 s7, v43, 48 ; SI-NEXT: s_and_b32 s62, s62, 0xff ; SI-NEXT: s_add_i32 s59, s7, 3 -; SI-NEXT: v_readlane_b32 s7, v42, 46 +; SI-NEXT: v_readlane_b32 s7, v43, 47 ; SI-NEXT: s_lshl_b32 s62, s62, 16 ; SI-NEXT: s_addk_i32 s60, 0x300 ; SI-NEXT: s_and_b32 s59, s59, 0xff ; SI-NEXT: s_lshl_b32 s58, s7, 8 -; SI-NEXT: v_readlane_b32 s7, v43, 32 +; SI-NEXT: v_readlane_b32 s7, v44, 33 ; SI-NEXT: s_or_b32 s61, s61, s62 ; SI-NEXT: s_and_b32 s60, s60, 0xffff ; SI-NEXT: s_or_b32 s58, s58, s59 ; SI-NEXT: s_lshl_b32 s59, s7, 24 -; SI-NEXT: v_readlane_b32 s7, v43, 33 +; SI-NEXT: v_readlane_b32 s7, v44, 44 ; SI-NEXT: s_or_b32 s60, s61, s60 ; SI-NEXT: s_add_i32 s61, s7, 3 -; SI-NEXT: v_readlane_b32 s7, v42, 45 +; SI-NEXT: v_readlane_b32 s7, v43, 46 ; SI-NEXT: s_add_i32 s57, s7, 3 -; SI-NEXT: v_readlane_b32 s7, v42, 44 +; SI-NEXT: v_readlane_b32 s7, v43, 45 ; SI-NEXT: s_lshl_b32 s56, s7, 8 -; SI-NEXT: v_readlane_b32 s7, v42, 43 +; SI-NEXT: v_readlane_b32 s7, v43, 44 ; SI-NEXT: s_lshl_b32 s47, s7, 24 -; SI-NEXT: v_readlane_b32 s7, v42, 42 +; SI-NEXT: v_readlane_b32 s7, v43, 43 ; SI-NEXT: s_add_i32 s46, s7, 3 -; SI-NEXT: v_readlane_b32 s7, v42, 41 +; SI-NEXT: v_readlane_b32 s7, v43, 42 ; SI-NEXT: s_add_i32 s45, s7, 3 -; SI-NEXT: v_readlane_b32 s7, v42, 38 +; SI-NEXT: v_readlane_b32 s7, v43, 39 ; SI-NEXT: s_lshl_b32 s42, s7, 8 -; SI-NEXT: v_readlane_b32 s7, v42, 35 +; SI-NEXT: v_readlane_b32 s7, v43, 36 ; SI-NEXT: s_lshl_b32 s15, s7, 24 -; SI-NEXT: v_readlane_b32 s7, v42, 34 +; SI-NEXT: v_readlane_b32 s7, v43, 35 ; SI-NEXT: s_and_b32 s45, s45, 0xff ; SI-NEXT: s_add_i32 s14, s7, 3 ; SI-NEXT: s_or_b32 s42, s42, s45 ; SI-NEXT: s_and_b32 s14, s14, 0xff ; SI-NEXT: s_lshl_b32 s14, s14, 16 ; SI-NEXT: s_addk_i32 s42, 0x300 -; SI-NEXT: v_readlane_b32 s7, v42, 40 +; SI-NEXT: v_readlane_b32 s7, v43, 41 ; SI-NEXT: s_and_b32 s57, s57, 0xff ; SI-NEXT: s_or_b32 s14, s15, s14 ; SI-NEXT: s_and_b32 s15, s42, 0xffff ; SI-NEXT: s_add_i32 s44, s7, 3 -; SI-NEXT: v_readlane_b32 s7, v42, 39 +; SI-NEXT: v_readlane_b32 s7, v43, 40 ; SI-NEXT: s_or_b32 s56, s56, s57 ; SI-NEXT: s_or_b32 s57, s14, s15 ; SI-NEXT: s_and_b32 s14, s44, 0xff ; SI-NEXT: s_lshl_b32 s15, s7, 8 -; SI-NEXT: v_readlane_b32 s7, v42, 37 +; SI-NEXT: v_readlane_b32 s7, v43, 38 ; SI-NEXT: s_or_b32 s14, s15, s14 ; SI-NEXT: s_lshl_b32 s15, s7, 24 -; SI-NEXT: v_readlane_b32 s7, v42, 36 +; SI-NEXT: v_readlane_b32 s7, v43, 37 ; SI-NEXT: s_add_i32 s40, s7, 3 ; SI-NEXT: s_and_b32 s61, s61, 0xff ; SI-NEXT: s_and_b32 s40, s40, 0xff @@ -154900,15 +152232,15 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_or_b32 s58, s59, s58 ; SI-NEXT: s_or_b32 s59, s15, s14 ; SI-NEXT: s_add_i32 s14, s6, 0x3000000 -; SI-NEXT: v_readlane_b32 s6, v42, 31 +; SI-NEXT: v_readlane_b32 s6, v43, 32 ; SI-NEXT: s_add_i32 s11, s6, 3 -; SI-NEXT: v_readlane_b32 s7, v42, 28 +; SI-NEXT: v_readlane_b32 s7, v43, 29 ; SI-NEXT: s_and_b32 s6, s11, 0xff ; SI-NEXT: s_lshl_b32 s8, s7, 8 -; SI-NEXT: v_readlane_b32 s7, v42, 25 +; SI-NEXT: v_readlane_b32 s7, v43, 26 ; SI-NEXT: s_or_b32 s6, s8, s6 ; SI-NEXT: s_lshl_b32 s8, s7, 24 -; SI-NEXT: v_readlane_b32 s7, v42, 24 +; SI-NEXT: v_readlane_b32 s7, v43, 25 ; SI-NEXT: s_add_i32 s24, s7, 3 ; SI-NEXT: s_and_b32 s11, s24, 0xff ; SI-NEXT: s_addk_i32 s6, 0x300 @@ -154916,47 +152248,47 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_and_b32 s6, s6, 0xffff ; SI-NEXT: s_or_b32 s8, s8, s11 ; SI-NEXT: s_or_b32 s8, s8, s6 -; SI-NEXT: v_readlane_b32 s6, v42, 32 +; SI-NEXT: v_readlane_b32 s6, v43, 33 ; SI-NEXT: s_add_i32 s12, s6, 3 -; SI-NEXT: v_readlane_b32 s7, v42, 26 +; SI-NEXT: v_readlane_b32 s7, v43, 27 ; SI-NEXT: s_and_b32 s6, s12, 0xff ; SI-NEXT: s_lshl_b32 s11, s7, 8 -; SI-NEXT: v_readlane_b32 s7, v42, 16 +; SI-NEXT: v_readlane_b32 s7, v43, 17 ; SI-NEXT: s_or_b32 s6, s11, s6 ; SI-NEXT: s_lshl_b32 s11, s7, 24 -; SI-NEXT: v_readlane_b32 s7, v42, 18 +; SI-NEXT: v_readlane_b32 s7, v43, 19 ; SI-NEXT: s_add_i32 s12, s7, 3 ; SI-NEXT: s_and_b32 s12, s12, 0xff ; SI-NEXT: s_addk_i32 s6, 0x300 ; SI-NEXT: s_lshl_b32 s12, s12, 16 -; SI-NEXT: v_readlane_b32 s7, v42, 33 +; SI-NEXT: v_readlane_b32 s7, v43, 34 ; SI-NEXT: s_and_b32 s6, s6, 0xffff ; SI-NEXT: s_or_b32 s11, s11, s12 ; SI-NEXT: s_add_i32 s13, s7, 3 -; SI-NEXT: v_readlane_b32 s7, v42, 30 +; SI-NEXT: v_readlane_b32 s7, v43, 31 ; SI-NEXT: s_or_b32 s6, s11, s6 ; SI-NEXT: s_and_b32 s11, s13, 0xff ; SI-NEXT: s_lshl_b32 s10, s7, 8 -; SI-NEXT: v_readlane_b32 s7, v42, 22 +; SI-NEXT: v_readlane_b32 s7, v43, 23 ; SI-NEXT: s_or_b32 s10, s10, s11 ; SI-NEXT: s_lshl_b32 s11, s7, 24 -; SI-NEXT: v_readlane_b32 s7, v42, 23 +; SI-NEXT: v_readlane_b32 s7, v43, 24 ; SI-NEXT: s_add_i32 s25, s7, 3 ; SI-NEXT: s_and_b32 s12, s25, 0xff ; SI-NEXT: s_addk_i32 s10, 0x300 ; SI-NEXT: s_lshl_b32 s12, s12, 16 ; SI-NEXT: s_and_b32 s10, s10, 0xffff ; SI-NEXT: s_or_b32 s11, s11, s12 -; SI-NEXT: v_readlane_b32 s7, v42, 29 +; SI-NEXT: v_readlane_b32 s7, v43, 30 ; SI-NEXT: s_or_b32 s10, s11, s10 ; SI-NEXT: s_add_i32 s9, s7, 3 -; SI-NEXT: v_readlane_b32 s7, v42, 27 -; SI-NEXT: v_readlane_b32 s11, v42, 20 +; SI-NEXT: v_readlane_b32 s7, v43, 28 +; SI-NEXT: v_readlane_b32 s11, v43, 21 ; SI-NEXT: s_and_b32 s9, s9, 0xff ; SI-NEXT: s_lshl_b32 s7, s7, 8 ; SI-NEXT: s_add_i32 s11, s11, 3 ; SI-NEXT: s_or_b32 s7, s7, s9 -; SI-NEXT: v_readlane_b32 s9, v42, 21 +; SI-NEXT: v_readlane_b32 s9, v43, 22 ; SI-NEXT: s_and_b32 s11, s11, 0xff ; SI-NEXT: s_addk_i32 s7, 0x300 ; SI-NEXT: s_lshl_b32 s9, s9, 24 @@ -154964,15 +152296,15 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_and_b32 s7, s7, 0xffff ; SI-NEXT: s_or_b32 s9, s9, s11 ; SI-NEXT: s_or_b32 s7, s9, s7 -; SI-NEXT: v_readlane_b32 s9, v42, 19 +; SI-NEXT: v_readlane_b32 s9, v43, 20 ; SI-NEXT: s_add_i32 s21, s9, 3 -; SI-NEXT: v_readlane_b32 s11, v42, 17 -; SI-NEXT: v_readlane_b32 s12, v42, 14 +; SI-NEXT: v_readlane_b32 s11, v43, 18 +; SI-NEXT: v_readlane_b32 s12, v43, 15 ; SI-NEXT: s_and_b32 s9, s21, 0xff ; SI-NEXT: s_lshl_b32 s11, s11, 8 ; SI-NEXT: s_add_i32 s12, s12, 3 ; SI-NEXT: s_or_b32 s9, s11, s9 -; SI-NEXT: v_readlane_b32 s11, v42, 15 +; SI-NEXT: v_readlane_b32 s11, v43, 16 ; SI-NEXT: s_and_b32 s12, s12, 0xff ; SI-NEXT: s_addk_i32 s9, 0x300 ; SI-NEXT: s_lshl_b32 s11, s11, 24 @@ -154980,15 +152312,15 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_and_b32 s9, s9, 0xffff ; SI-NEXT: s_or_b32 s11, s11, s12 ; SI-NEXT: s_or_b32 s9, s11, s9 -; SI-NEXT: v_readlane_b32 s11, v42, 13 +; SI-NEXT: v_readlane_b32 s11, v43, 14 ; SI-NEXT: s_add_i32 s11, s11, 3 -; SI-NEXT: v_readlane_b32 s12, v42, 12 -; SI-NEXT: v_readlane_b32 s13, v42, 10 +; SI-NEXT: v_readlane_b32 s12, v43, 13 +; SI-NEXT: v_readlane_b32 s13, v43, 11 ; SI-NEXT: s_and_b32 s11, s11, 0xff ; SI-NEXT: s_lshl_b32 s12, s12, 8 ; SI-NEXT: s_add_i32 s13, s13, 3 ; SI-NEXT: s_or_b32 s11, s12, s11 -; SI-NEXT: v_readlane_b32 s12, v42, 11 +; SI-NEXT: v_readlane_b32 s12, v43, 12 ; SI-NEXT: s_and_b32 s13, s13, 0xff ; SI-NEXT: s_addk_i32 s11, 0x300 ; SI-NEXT: s_lshl_b32 s12, s12, 24 @@ -154996,16 +152328,16 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_and_b32 s11, s11, 0xffff ; SI-NEXT: s_or_b32 s12, s12, s13 ; SI-NEXT: s_or_b32 s11, s12, s11 -; SI-NEXT: v_readlane_b32 s12, v42, 9 +; SI-NEXT: v_readlane_b32 s12, v43, 10 ; SI-NEXT: s_add_i32 s15, s16, 0x3000000 ; SI-NEXT: s_add_i32 s12, s12, 3 -; SI-NEXT: v_readlane_b32 s13, v42, 8 -; SI-NEXT: v_readlane_b32 s16, v42, 6 +; SI-NEXT: v_readlane_b32 s13, v43, 9 +; SI-NEXT: v_readlane_b32 s16, v43, 7 ; SI-NEXT: s_and_b32 s12, s12, 0xff ; SI-NEXT: s_lshl_b32 s13, s13, 8 ; SI-NEXT: s_add_i32 s16, s16, 3 ; SI-NEXT: s_or_b32 s12, s13, s12 -; SI-NEXT: v_readlane_b32 s13, v42, 7 +; SI-NEXT: v_readlane_b32 s13, v43, 8 ; SI-NEXT: s_and_b32 s16, s16, 0xff ; SI-NEXT: s_addk_i32 s12, 0x300 ; SI-NEXT: s_lshl_b32 s13, s13, 24 @@ -155013,16 +152345,16 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_and_b32 s12, s12, 0xffff ; SI-NEXT: s_or_b32 s13, s13, s16 ; SI-NEXT: s_or_b32 s12, s13, s12 -; SI-NEXT: v_readlane_b32 s13, v42, 5 +; SI-NEXT: v_readlane_b32 s13, v43, 6 ; SI-NEXT: s_add_i32 s40, s17, 0x3000000 ; SI-NEXT: s_add_i32 s13, s13, 3 -; SI-NEXT: v_readlane_b32 s16, v42, 4 -; SI-NEXT: v_readlane_b32 s17, v42, 2 +; SI-NEXT: v_readlane_b32 s16, v43, 5 +; SI-NEXT: v_readlane_b32 s17, v43, 3 ; SI-NEXT: s_and_b32 s13, s13, 0xff ; SI-NEXT: s_lshl_b32 s16, s16, 8 ; SI-NEXT: s_add_i32 s17, s17, 3 ; SI-NEXT: s_or_b32 s13, s16, s13 -; SI-NEXT: v_readlane_b32 s16, v42, 3 +; SI-NEXT: v_readlane_b32 s16, v43, 4 ; SI-NEXT: s_and_b32 s17, s17, 0xff ; SI-NEXT: s_addk_i32 s13, 0x300 ; SI-NEXT: s_lshl_b32 s16, s16, 24 @@ -155030,16 +152362,16 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_and_b32 s13, s13, 0xffff ; SI-NEXT: s_or_b32 s16, s16, s17 ; SI-NEXT: s_or_b32 s13, s16, s13 -; SI-NEXT: v_readlane_b32 s16, v42, 1 +; SI-NEXT: v_readlane_b32 s16, v43, 2 ; SI-NEXT: s_add_i32 s41, s18, 0x3000000 ; SI-NEXT: s_add_i32 s16, s16, 3 -; SI-NEXT: v_readlane_b32 s17, v42, 0 -; SI-NEXT: v_readlane_b32 s18, v43, 62 +; SI-NEXT: v_readlane_b32 s17, v43, 1 +; SI-NEXT: v_readlane_b32 s18, v44, 63 ; SI-NEXT: s_and_b32 s16, s16, 0xff ; SI-NEXT: s_lshl_b32 s17, s17, 8 ; SI-NEXT: s_add_i32 s18, s18, 3 ; SI-NEXT: s_or_b32 s16, s17, s16 -; SI-NEXT: v_readlane_b32 s17, v43, 63 +; SI-NEXT: v_readlane_b32 s17, v43, 0 ; SI-NEXT: s_and_b32 s18, s18, 0xff ; SI-NEXT: s_addk_i32 s16, 0x300 ; SI-NEXT: s_lshl_b32 s17, s17, 24 @@ -155048,16 +152380,16 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_or_b32 s17, s17, s18 ; SI-NEXT: s_or_b32 s16, s17, s16 ; SI-NEXT: s_add_i32 s17, s16, 0x3000000 -; SI-NEXT: v_readlane_b32 s16, v43, 61 +; SI-NEXT: v_readlane_b32 s16, v44, 62 ; SI-NEXT: s_add_i32 s42, s19, 0x3000000 ; SI-NEXT: s_add_i32 s16, s16, 3 -; SI-NEXT: v_readlane_b32 s18, v43, 60 -; SI-NEXT: v_readlane_b32 s19, v43, 58 +; SI-NEXT: v_readlane_b32 s18, v44, 61 +; SI-NEXT: v_readlane_b32 s19, v44, 59 ; SI-NEXT: s_and_b32 s16, s16, 0xff ; SI-NEXT: s_lshl_b32 s18, s18, 8 ; SI-NEXT: s_add_i32 s19, s19, 3 ; SI-NEXT: s_or_b32 s16, s18, s16 -; SI-NEXT: v_readlane_b32 s18, v43, 59 +; SI-NEXT: v_readlane_b32 s18, v44, 60 ; SI-NEXT: s_and_b32 s19, s19, 0xff ; SI-NEXT: s_addk_i32 s16, 0x300 ; SI-NEXT: s_lshl_b32 s18, s18, 24 @@ -155065,16 +152397,16 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_and_b32 s16, s16, 0xffff ; SI-NEXT: s_or_b32 s18, s18, s19 ; SI-NEXT: s_or_b32 s16, s18, s16 -; SI-NEXT: v_readlane_b32 s18, v43, 57 +; SI-NEXT: v_readlane_b32 s18, v44, 58 ; SI-NEXT: s_add_i32 s43, s20, 0x3000000 ; SI-NEXT: s_add_i32 s18, s18, 3 -; SI-NEXT: v_readlane_b32 s19, v43, 56 -; SI-NEXT: v_readlane_b32 s20, v43, 54 +; SI-NEXT: v_readlane_b32 s19, v44, 57 +; SI-NEXT: v_readlane_b32 s20, v44, 55 ; SI-NEXT: s_and_b32 s18, s18, 0xff ; SI-NEXT: s_lshl_b32 s19, s19, 8 ; SI-NEXT: s_add_i32 s20, s20, 3 ; SI-NEXT: s_or_b32 s18, s19, s18 -; SI-NEXT: v_readlane_b32 s19, v43, 55 +; SI-NEXT: v_readlane_b32 s19, v44, 56 ; SI-NEXT: s_and_b32 s20, s20, 0xff ; SI-NEXT: s_addk_i32 s18, 0x300 ; SI-NEXT: s_lshl_b32 s19, s19, 24 @@ -155082,15 +152414,15 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_and_b32 s18, s18, 0xffff ; SI-NEXT: s_or_b32 s19, s19, s20 ; SI-NEXT: s_or_b32 s18, s19, s18 -; SI-NEXT: v_readlane_b32 s19, v43, 53 +; SI-NEXT: v_readlane_b32 s19, v44, 54 ; SI-NEXT: s_add_i32 s19, s19, 3 -; SI-NEXT: v_readlane_b32 s20, v43, 52 -; SI-NEXT: v_readlane_b32 s21, v43, 50 +; SI-NEXT: v_readlane_b32 s20, v44, 53 +; SI-NEXT: v_readlane_b32 s21, v44, 51 ; SI-NEXT: s_and_b32 s19, s19, 0xff ; SI-NEXT: s_lshl_b32 s20, s20, 8 ; SI-NEXT: s_add_i32 s21, s21, 3 ; SI-NEXT: s_or_b32 s19, s20, s19 -; SI-NEXT: v_readlane_b32 s20, v43, 51 +; SI-NEXT: v_readlane_b32 s20, v44, 52 ; SI-NEXT: s_and_b32 s21, s21, 0xff ; SI-NEXT: s_addk_i32 s19, 0x300 ; SI-NEXT: s_lshl_b32 s20, s20, 24 @@ -155098,16 +152430,16 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_and_b32 s19, s19, 0xffff ; SI-NEXT: s_or_b32 s20, s20, s21 ; SI-NEXT: s_or_b32 s19, s20, s19 -; SI-NEXT: v_readlane_b32 s20, v43, 49 +; SI-NEXT: v_readlane_b32 s20, v44, 50 ; SI-NEXT: s_add_i32 s44, s22, 0x3000000 ; SI-NEXT: s_add_i32 s20, s20, 3 -; SI-NEXT: v_readlane_b32 s21, v43, 48 -; SI-NEXT: v_readlane_b32 s22, v43, 46 +; SI-NEXT: v_readlane_b32 s21, v44, 49 +; SI-NEXT: v_readlane_b32 s22, v44, 47 ; SI-NEXT: s_and_b32 s20, s20, 0xff ; SI-NEXT: s_lshl_b32 s21, s21, 8 ; SI-NEXT: s_add_i32 s22, s22, 3 ; SI-NEXT: s_or_b32 s20, s21, s20 -; SI-NEXT: v_readlane_b32 s21, v43, 47 +; SI-NEXT: v_readlane_b32 s21, v44, 48 ; SI-NEXT: s_and_b32 s22, s22, 0xff ; SI-NEXT: s_addk_i32 s20, 0x300 ; SI-NEXT: s_lshl_b32 s21, s21, 24 @@ -155116,16 +152448,16 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_or_b32 s21, s21, s22 ; SI-NEXT: s_or_b32 s20, s21, s20 ; SI-NEXT: s_add_i32 s21, s20, 0x3000000 -; SI-NEXT: v_readlane_b32 s20, v43, 43 +; SI-NEXT: v_readlane_b32 s20, v44, 43 ; SI-NEXT: s_add_i32 s45, s23, 0x3000000 ; SI-NEXT: s_add_i32 s20, s20, 3 -; SI-NEXT: v_readlane_b32 s22, v43, 42 -; SI-NEXT: v_readlane_b32 s23, v43, 44 +; SI-NEXT: v_readlane_b32 s22, v44, 42 +; SI-NEXT: v_readlane_b32 s23, v44, 45 ; SI-NEXT: s_and_b32 s20, s20, 0xff ; SI-NEXT: s_lshl_b32 s22, s22, 8 ; SI-NEXT: s_add_i32 s23, s23, 3 ; SI-NEXT: s_or_b32 s20, s22, s20 -; SI-NEXT: v_readlane_b32 s22, v43, 45 +; SI-NEXT: v_readlane_b32 s22, v44, 46 ; SI-NEXT: s_and_b32 s23, s23, 0xff ; SI-NEXT: s_addk_i32 s20, 0x300 ; SI-NEXT: s_lshl_b32 s22, s22, 24 @@ -155134,15 +152466,15 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_or_b32 s22, s22, s23 ; SI-NEXT: s_or_b32 s20, s22, s20 ; SI-NEXT: s_add_i32 s22, s20, 0x3000000 -; SI-NEXT: v_readlane_b32 s20, v43, 41 +; SI-NEXT: v_readlane_b32 s20, v44, 41 ; SI-NEXT: s_add_i32 s20, s20, 3 -; SI-NEXT: v_readlane_b32 s23, v43, 40 -; SI-NEXT: v_readlane_b32 s24, v43, 38 +; SI-NEXT: v_readlane_b32 s23, v44, 40 +; SI-NEXT: v_readlane_b32 s24, v44, 38 ; SI-NEXT: s_and_b32 s20, s20, 0xff ; SI-NEXT: s_lshl_b32 s23, s23, 8 ; SI-NEXT: s_add_i32 s24, s24, 3 ; SI-NEXT: s_or_b32 s20, s23, s20 -; SI-NEXT: v_readlane_b32 s23, v43, 39 +; SI-NEXT: v_readlane_b32 s23, v44, 39 ; SI-NEXT: s_and_b32 s24, s24, 0xff ; SI-NEXT: s_addk_i32 s20, 0x300 ; SI-NEXT: s_lshl_b32 s23, s23, 24 @@ -155151,361 +152483,367 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: s_or_b32 s23, s23, s24 ; SI-NEXT: s_or_b32 s20, s23, s20 ; SI-NEXT: s_add_i32 s23, s20, 0x3000000 -; SI-NEXT: v_readlane_b32 s20, v43, 37 +; SI-NEXT: v_readlane_b32 s20, v44, 37 ; SI-NEXT: s_add_i32 s20, s20, 3 -; SI-NEXT: v_readlane_b32 s24, v43, 36 -; SI-NEXT: v_readlane_b32 s25, v43, 34 +; SI-NEXT: v_readlane_b32 s24, v44, 36 +; SI-NEXT: v_readlane_b32 s25, v44, 34 ; SI-NEXT: s_and_b32 s20, s20, 0xff ; SI-NEXT: s_lshl_b32 s24, s24, 8 ; SI-NEXT: s_add_i32 s25, s25, 3 ; SI-NEXT: s_or_b32 s20, s24, s20 -; SI-NEXT: v_readlane_b32 s24, v43, 35 +; SI-NEXT: v_readlane_b32 s24, v44, 35 ; SI-NEXT: s_and_b32 s25, s25, 0xff ; SI-NEXT: s_addk_i32 s20, 0x300 ; SI-NEXT: s_lshl_b32 s24, s24, 24 ; SI-NEXT: s_lshl_b32 s25, s25, 16 ; SI-NEXT: s_and_b32 s20, s20, 0xffff ; SI-NEXT: s_or_b32 s24, s24, s25 -; SI-NEXT: s_and_b32 s46, s46, 0xff ; SI-NEXT: s_or_b32 s20, s24, s20 -; SI-NEXT: v_readlane_b32 s24, v43, 3 -; SI-NEXT: s_lshl_b32 s46, s46, 16 -; SI-NEXT: s_addk_i32 s56, 0x300 +; SI-NEXT: v_readlane_b32 s24, v44, 3 ; SI-NEXT: s_add_i32 s24, s24, 3 -; SI-NEXT: v_readlane_b32 s25, v43, 2 -; SI-NEXT: v_readlane_b32 s26, v43, 1 -; SI-NEXT: s_or_b32 s46, s47, s46 -; SI-NEXT: s_and_b32 s47, s56, 0xffff -; SI-NEXT: s_add_i32 s7, s7, 0x3000000 -; SI-NEXT: s_add_i32 s9, s9, 0x3000000 +; SI-NEXT: v_readlane_b32 s25, v44, 2 +; SI-NEXT: v_readlane_b32 s26, v44, 1 ; SI-NEXT: s_and_b32 s24, s24, 0xff ; SI-NEXT: s_lshl_b32 s25, s25, 8 ; SI-NEXT: s_add_i32 s26, s26, 3 -; SI-NEXT: s_or_b32 s56, s46, s47 -; SI-NEXT: s_add_i32 s47, s58, 0x3000000 -; SI-NEXT: s_add_i32 s58, s59, 0x3000000 -; SI-NEXT: s_add_i32 s10, s10, 0x3000000 ; SI-NEXT: s_or_b32 s24, s25, s24 -; SI-NEXT: v_readlane_b32 s25, v43, 0 +; SI-NEXT: v_readlane_b32 s25, v44, 0 ; SI-NEXT: s_and_b32 s26, s26, 0xff -; SI-NEXT: s_and_b32 s73, s9, 0xffff0000 -; SI-NEXT: s_lshl_b32 s59, s9, 16 -; SI-NEXT: s_and_b32 s9, s7, 0xffff0000 -; SI-NEXT: s_add_i32 s6, s6, 0x3000000 +; SI-NEXT: s_add_i32 s13, s13, 0x3000000 ; SI-NEXT: s_addk_i32 s24, 0x300 ; SI-NEXT: s_lshl_b32 s25, s25, 24 ; SI-NEXT: s_lshl_b32 s26, s26, 16 -; SI-NEXT: s_and_b32 s63, s17, 0xffff0000 -; SI-NEXT: s_lshl_b32 s79, s17, 16 -; SI-NEXT: v_writelane_b32 v42, s9, 50 -; SI-NEXT: s_lshl_b32 s17, s7, 16 -; SI-NEXT: s_lshl_b32 s7, s10, 16 -; SI-NEXT: s_add_i32 s8, s8, 0x3000000 +; SI-NEXT: s_add_i32 s9, s9, 0x3000000 +; SI-NEXT: s_add_i32 s11, s11, 0x3000000 +; SI-NEXT: s_add_i32 s18, s18, 0x3000000 ; SI-NEXT: s_and_b32 s24, s24, 0xffff ; SI-NEXT: s_or_b32 s25, s25, s26 -; SI-NEXT: v_writelane_b32 v42, s7, 51 -; SI-NEXT: s_and_b32 s7, s6, 0xffff0000 +; SI-NEXT: s_and_b32 s89, s17, 0xffff0000 +; SI-NEXT: s_lshl_b32 s88, s17, 16 +; SI-NEXT: s_and_b32 s17, s13, 0xffff0000 +; SI-NEXT: s_add_i32 s7, s7, 0x3000000 ; SI-NEXT: s_or_b32 s24, s25, s24 -; SI-NEXT: v_writelane_b32 v42, s7, 52 +; SI-NEXT: s_and_b32 s74, s18, 0xffff0000 +; SI-NEXT: s_lshl_b32 s25, s18, 16 +; SI-NEXT: v_writelane_b32 v43, s17, 49 +; SI-NEXT: s_and_b32 s63, s11, 0xffff0000 +; SI-NEXT: s_lshl_b32 s18, s11, 16 +; SI-NEXT: s_and_b32 s11, s9, 0xffff0000 +; SI-NEXT: s_and_b32 s46, s46, 0xff +; SI-NEXT: s_add_i32 s6, s6, 0x3000000 +; SI-NEXT: v_writelane_b32 v43, s11, 50 +; SI-NEXT: s_lshl_b32 s61, s9, 16 +; SI-NEXT: s_and_b32 s9, s7, 0xffff0000 +; SI-NEXT: s_lshl_b32 s46, s46, 16 +; SI-NEXT: s_addk_i32 s56, 0x300 +; SI-NEXT: s_add_i32 s8, s8, 0x3000000 +; SI-NEXT: v_writelane_b32 v43, s9, 51 +; SI-NEXT: s_lshl_b32 s17, s7, 16 +; SI-NEXT: s_and_b32 s7, s6, 0xffff0000 +; SI-NEXT: s_or_b32 s46, s47, s46 +; SI-NEXT: s_and_b32 s47, s56, 0xffff +; SI-NEXT: v_writelane_b32 v43, s7, 52 ; SI-NEXT: s_and_b32 s7, s8, 0xffff0000 +; SI-NEXT: s_or_b32 s56, s46, s47 +; SI-NEXT: s_add_i32 s47, s58, 0x3000000 +; SI-NEXT: s_add_i32 s58, s59, 0x3000000 +; SI-NEXT: v_writelane_b32 v43, s7, 53 +; SI-NEXT: s_lshl_b32 s7, s8, 16 +; SI-NEXT: s_add_i32 s57, s57, 0x3000000 +; SI-NEXT: v_writelane_b32 v43, s7, 54 +; SI-NEXT: s_and_b32 s7, s58, 0xffff0000 ; SI-NEXT: s_add_i32 s4, s4, 0x3000000 ; SI-NEXT: s_add_i32 s5, s5, 0x3000000 ; SI-NEXT: s_add_i32 s46, s60, 0x3000000 ; SI-NEXT: s_add_i32 s56, s56, 0x3000000 -; SI-NEXT: s_add_i32 s57, s57, 0x3000000 -; SI-NEXT: s_add_i32 s11, s11, 0x3000000 +; SI-NEXT: s_add_i32 s10, s10, 0x3000000 ; SI-NEXT: s_add_i32 s12, s12, 0x3000000 -; SI-NEXT: s_add_i32 s13, s13, 0x3000000 ; SI-NEXT: s_add_i32 s16, s16, 0x3000000 -; SI-NEXT: s_add_i32 s18, s18, 0x3000000 ; SI-NEXT: s_add_i32 s19, s19, 0x3000000 ; SI-NEXT: s_add_i32 s20, s20, 0x3000000 ; SI-NEXT: s_add_i32 s24, s24, 0x3000000 -; SI-NEXT: v_writelane_b32 v42, s7, 53 -; SI-NEXT: s_lshl_b32 s7, s8, 16 +; SI-NEXT: v_writelane_b32 v43, s7, 55 +; SI-NEXT: s_and_b32 s7, s57, 0xffff0000 ; SI-NEXT: s_and_b32 s27, s24, 0xffff0000 ; SI-NEXT: s_lshl_b32 s26, s24, 16 -; SI-NEXT: s_and_b32 s24, s20, 0xffff0000 +; SI-NEXT: s_and_b32 s65, s20, 0xffff0000 ; SI-NEXT: s_lshl_b32 s20, s20, 16 -; SI-NEXT: s_and_b32 s35, s23, 0xffff0000 +; SI-NEXT: s_and_b32 s66, s23, 0xffff0000 ; SI-NEXT: s_lshl_b32 s29, s23, 16 -; SI-NEXT: s_and_b32 s90, s22, 0xffff0000 -; SI-NEXT: s_lshl_b32 s74, s22, 16 -; SI-NEXT: s_and_b32 s25, s21, 0xffff0000 +; SI-NEXT: s_and_b32 s64, s22, 0xffff0000 +; SI-NEXT: s_lshl_b32 s95, s22, 16 +; SI-NEXT: s_and_b32 s76, s21, 0xffff0000 ; SI-NEXT: s_lshl_b32 s21, s21, 16 -; SI-NEXT: s_and_b32 s75, s19, 0xffff0000 +; SI-NEXT: s_and_b32 s77, s19, 0xffff0000 ; SI-NEXT: s_lshl_b32 s22, s19, 16 -; SI-NEXT: s_and_b32 s61, s18, 0xffff0000 -; SI-NEXT: s_lshl_b32 s76, s18, 16 -; SI-NEXT: s_and_b32 s77, s16, 0xffff0000 +; SI-NEXT: s_and_b32 s78, s16, 0xffff0000 ; SI-NEXT: s_lshl_b32 s16, s16, 16 -; SI-NEXT: s_and_b32 s89, s13, 0xffff0000 ; SI-NEXT: s_lshl_b32 s19, s13, 16 -; SI-NEXT: s_and_b32 s13, s12, 0xffff0000 -; SI-NEXT: s_lshl_b32 s88, s12, 16 -; SI-NEXT: s_and_b32 s60, s11, 0xffff0000 -; SI-NEXT: s_lshl_b32 s18, s11, 16 -; SI-NEXT: s_and_b32 s23, s10, 0xffff0000 +; SI-NEXT: s_and_b32 s75, s12, 0xffff0000 +; SI-NEXT: s_lshl_b32 s79, s12, 16 +; SI-NEXT: s_and_b32 s13, s10, 0xffff0000 +; SI-NEXT: s_lshl_b32 s59, s10, 16 ; SI-NEXT: s_lshl_b32 s6, s6, 16 -; SI-NEXT: v_writelane_b32 v42, s7, 54 -; SI-NEXT: s_and_b32 s72, s58, 0xffff0000 ; SI-NEXT: s_lshl_b32 s99, s58, 16 -; SI-NEXT: s_and_b32 s7, s57, 0xffff0000 +; SI-NEXT: v_writelane_b32 v43, s7, 56 ; SI-NEXT: s_lshl_b32 s57, s57, 16 -; SI-NEXT: s_and_b32 s49, s56, 0xffff0000 +; SI-NEXT: s_and_b32 s7, s56, 0xffff0000 ; SI-NEXT: s_lshl_b32 s8, s56, 16 -; SI-NEXT: s_and_b32 s51, s47, 0xffff0000 -; SI-NEXT: s_lshl_b32 s50, s47, 16 -; SI-NEXT: s_and_b32 s52, s46, 0xffff0000 +; SI-NEXT: s_and_b32 s56, s47, 0xffff0000 +; SI-NEXT: s_lshl_b32 s23, s47, 16 +; SI-NEXT: s_and_b32 s47, s46, 0xffff0000 ; SI-NEXT: s_lshl_b32 s97, s46, 16 -; SI-NEXT: s_and_b32 s54, s45, 0xffff0000 -; SI-NEXT: s_lshl_b32 s53, s45, 16 -; SI-NEXT: s_and_b32 s55, s44, 0xffff0000 +; SI-NEXT: s_and_b32 s24, s45, 0xffff0000 +; SI-NEXT: s_lshl_b32 s45, s45, 16 +; SI-NEXT: s_and_b32 s58, s44, 0xffff0000 ; SI-NEXT: s_lshl_b32 s28, s44, 16 -; SI-NEXT: s_and_b32 s65, s43, 0xffff0000 -; SI-NEXT: s_lshl_b32 s64, s43, 16 -; SI-NEXT: s_and_b32 s66, s42, 0xffff0000 +; SI-NEXT: s_and_b32 s73, s43, 0xffff0000 +; SI-NEXT: s_lshl_b32 s46, s43, 16 +; SI-NEXT: s_and_b32 s67, s42, 0xffff0000 ; SI-NEXT: s_lshl_b32 s87, s42, 16 ; SI-NEXT: s_and_b32 s68, s41, 0xffff0000 -; SI-NEXT: s_lshl_b32 s67, s41, 16 -; SI-NEXT: s_and_b32 s69, s40, 0xffff0000 +; SI-NEXT: s_lshl_b32 s42, s41, 16 +; SI-NEXT: s_and_b32 s70, s40, 0xffff0000 ; SI-NEXT: s_lshl_b32 s86, s40, 16 -; SI-NEXT: s_and_b32 s62, s15, 0xffff0000 -; SI-NEXT: s_lshl_b32 s70, s15, 16 -; SI-NEXT: s_and_b32 s80, s14, 0xffff0000 +; SI-NEXT: s_and_b32 s94, s15, 0xffff0000 +; SI-NEXT: s_lshl_b32 s69, s15, 16 +; SI-NEXT: s_and_b32 s11, s14, 0xffff0000 ; SI-NEXT: s_lshl_b32 s85, s14, 16 -; SI-NEXT: s_and_b32 s92, s5, 0xffff0000 -; SI-NEXT: s_lshl_b32 s11, s5, 16 -; SI-NEXT: s_and_b32 s83, s4, 0xffff0000 +; SI-NEXT: s_and_b32 s31, s5, 0xffff0000 +; SI-NEXT: s_lshl_b32 s80, s5, 16 +; SI-NEXT: s_and_b32 s15, s4, 0xffff0000 ; SI-NEXT: s_lshl_b32 s84, s4, 16 -; SI-NEXT: v_writelane_b32 v42, s7, 55 +; SI-NEXT: v_writelane_b32 v43, s7, 57 ; SI-NEXT: .LBB89_3: ; %end ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s27 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s26 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s26 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_readlane_b32 s4, v43, 49 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s24 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s20 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s65 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s20 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s35 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s29 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s66 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s29 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s90 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s74 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s64 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s95 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s25 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s21 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s76 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s21 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s75 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s22 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s77 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s22 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s61 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s76 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s74 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s25 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s77 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s16 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s78 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s16 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s63 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s79 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s89 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s88 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s89 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s19 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s19 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s13 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s88 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s75 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s79 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s60 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s18 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s63 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s18 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0 +; SI-NEXT: v_readlane_b32 s4, v43, 50 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s73 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s59 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s61 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0 -; SI-NEXT: v_readlane_b32 s4, v42, 50 +; SI-NEXT: v_readlane_b32 s4, v43, 51 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s17 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s17 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s23 -; SI-NEXT: v_readlane_b32 s4, v42, 51 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s13 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s59 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0 -; SI-NEXT: v_readlane_b32 s4, v42, 52 +; SI-NEXT: v_readlane_b32 s4, v43, 52 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s6 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s6 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v0 -; SI-NEXT: v_readlane_b32 s4, v42, 53 +; SI-NEXT: v_readlane_b32 s4, v43, 53 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4 -; SI-NEXT: v_readlane_b32 s4, v42, 54 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_readlane_b32 s4, v43, 54 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 64, v0 +; SI-NEXT: v_readlane_b32 s4, v43, 55 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s72 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s99 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s99 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v0 -; SI-NEXT: v_readlane_b32 s4, v42, 55 +; SI-NEXT: v_readlane_b32 s4, v43, 56 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s57 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s57 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x48, v0 +; SI-NEXT: v_readlane_b32 s4, v43, 57 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s49 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s8 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s8 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s51 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s50 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s56 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s23 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x50, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s52 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s97 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s47 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s97 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s54 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s53 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s24 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s45 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x58, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s55 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s28 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s58 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s28 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s65 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s64 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s73 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s46 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x60, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s66 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s87 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s67 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s87 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x64, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s68 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s67 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s42 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x68, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s69 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s86 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s70 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s86 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s62 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s70 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s94 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s69 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x70, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s80 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s85 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s11 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s85 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s92 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s11 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s31 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s80 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s83 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s84 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s15 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s84 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload @@ -155549,6 +152887,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] @@ -155559,99 +152898,109 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a ; SI-NEXT: ; implicit-def: $sgpr8 ; SI-NEXT: ; implicit-def: $sgpr6 ; SI-NEXT: ; kill: killed $sgpr8 -; SI-NEXT: v_readlane_b32 s58, v43, 19 +; SI-NEXT: ; kill: killed $sgpr6 +; SI-NEXT: ; implicit-def: $sgpr6 +; SI-NEXT: ; implicit-def: $sgpr8 +; SI-NEXT: ; kill: killed $sgpr8 +; SI-NEXT: v_readlane_b32 s92, v44, 24 ; SI-NEXT: ; implicit-def: $sgpr8 -; SI-NEXT: s_mov_b32 s95, s47 -; SI-NEXT: s_mov_b32 s94, s21 -; SI-NEXT: s_mov_b32 s93, s61 -; SI-NEXT: s_mov_b32 s34, s73 -; SI-NEXT: s_mov_b32 s91, s75 -; SI-NEXT: v_readlane_b32 s56, v43, 10 -; SI-NEXT: s_mov_b32 s36, s63 -; SI-NEXT: s_mov_b32 s38, s59 -; SI-NEXT: s_mov_b32 s37, s42 -; SI-NEXT: v_readlane_b32 s30, v43, 17 -; SI-NEXT: v_readlane_b32 s98, v43, 6 -; SI-NEXT: s_mov_b32 s46, s45 -; SI-NEXT: s_mov_b32 s31, s43 -; SI-NEXT: s_mov_b32 s78, s40 -; SI-NEXT: v_readlane_b32 s15, v43, 14 -; SI-NEXT: s_mov_b32 s39, s57 -; SI-NEXT: s_mov_b32 s48, s13 -; SI-NEXT: v_readlane_b32 s41, v43, 13 -; SI-NEXT: v_readlane_b32 s44, v43, 5 -; SI-NEXT: v_readlane_b32 s9, v43, 11 -; SI-NEXT: v_readlane_b32 s14, v43, 12 -; SI-NEXT: v_readlane_b32 s81, v43, 9 -; SI-NEXT: v_readlane_b32 s10, v43, 16 -; SI-NEXT: v_readlane_b32 s12, v43, 4 -; SI-NEXT: v_readlane_b32 s96, v43, 7 -; SI-NEXT: v_readlane_b32 s82, v43, 8 -; SI-NEXT: v_readlane_b32 s71, v43, 15 +; SI-NEXT: v_readlane_b32 s91, v44, 20 +; SI-NEXT: s_mov_b32 s90, s88 +; SI-NEXT: v_readlane_b32 s36, v44, 23 +; SI-NEXT: v_readlane_b32 s35, v44, 19 +; SI-NEXT: v_readlane_b32 s62, v44, 22 +; SI-NEXT: v_readlane_b32 s38, v44, 18 +; SI-NEXT: s_mov_b32 s34, s46 +; SI-NEXT: s_mov_b32 s93, s21 +; SI-NEXT: s_mov_b32 s37, s43 +; SI-NEXT: s_mov_b32 s39, s75 +; SI-NEXT: v_readlane_b32 s72, v44, 10 +; SI-NEXT: s_mov_b32 s50, s63 +; SI-NEXT: s_mov_b32 s51, s59 +; SI-NEXT: s_mov_b32 s48, s56 +; SI-NEXT: v_readlane_b32 s30, v44, 21 +; SI-NEXT: s_mov_b32 s49, s61 +; SI-NEXT: s_mov_b32 s52, s79 +; SI-NEXT: v_readlane_b32 s98, v44, 6 +; SI-NEXT: s_mov_b32 s55, s45 +; SI-NEXT: v_readlane_b32 s43, v44, 17 +; SI-NEXT: s_mov_b32 s60, s40 +; SI-NEXT: v_readlane_b32 s41, v44, 14 +; SI-NEXT: s_mov_b32 s53, s42 +; SI-NEXT: s_mov_b32 s54, s13 +; SI-NEXT: v_readlane_b32 s14, v44, 13 +; SI-NEXT: v_readlane_b32 s44, v44, 5 +; SI-NEXT: v_readlane_b32 s9, v44, 11 +; SI-NEXT: v_readlane_b32 s81, v44, 12 +; SI-NEXT: v_readlane_b32 s82, v44, 9 +; SI-NEXT: v_readlane_b32 s10, v44, 16 +; SI-NEXT: v_readlane_b32 s12, v44, 4 +; SI-NEXT: v_readlane_b32 s96, v44, 7 +; SI-NEXT: v_readlane_b32 s83, v44, 8 +; SI-NEXT: v_readlane_b32 s71, v44, 15 ; SI-NEXT: ; kill: killed $sgpr6 ; SI-NEXT: ; implicit-def: $sgpr6 ; SI-NEXT: ; kill: killed $sgpr8 ; SI-NEXT: ; implicit-def: $sgpr8 +; SI-NEXT: ; implicit-def: $sgpr11 ; SI-NEXT: ; implicit-def: $sgpr26 ; SI-NEXT: ; implicit-def: $sgpr27 ; SI-NEXT: ; implicit-def: $sgpr20 -; SI-NEXT: ; implicit-def: $sgpr24 +; SI-NEXT: ; implicit-def: $sgpr65 ; SI-NEXT: ; implicit-def: $sgpr29 -; SI-NEXT: ; implicit-def: $sgpr35 -; SI-NEXT: ; implicit-def: $sgpr74 -; SI-NEXT: ; implicit-def: $sgpr90 +; SI-NEXT: ; implicit-def: $sgpr66 +; SI-NEXT: ; implicit-def: $sgpr95 +; SI-NEXT: ; implicit-def: $sgpr64 ; SI-NEXT: ; implicit-def: $sgpr21 -; SI-NEXT: ; implicit-def: $sgpr25 -; SI-NEXT: ; implicit-def: $sgpr22 -; SI-NEXT: ; implicit-def: $sgpr75 ; SI-NEXT: ; implicit-def: $sgpr76 -; SI-NEXT: ; implicit-def: $sgpr61 -; SI-NEXT: ; implicit-def: $sgpr16 +; SI-NEXT: ; implicit-def: $sgpr22 ; SI-NEXT: ; implicit-def: $sgpr77 -; SI-NEXT: ; implicit-def: $sgpr79 -; SI-NEXT: ; implicit-def: $sgpr63 -; SI-NEXT: ; implicit-def: $sgpr19 -; SI-NEXT: ; implicit-def: $sgpr89 +; SI-NEXT: ; implicit-def: $sgpr25 +; SI-NEXT: ; implicit-def: $sgpr74 +; SI-NEXT: ; implicit-def: $sgpr16 +; SI-NEXT: ; implicit-def: $sgpr78 ; SI-NEXT: ; implicit-def: $sgpr88 -; SI-NEXT: ; implicit-def: $sgpr13 +; SI-NEXT: ; implicit-def: $sgpr89 +; SI-NEXT: ; implicit-def: $sgpr19 +; SI-NEXT: ; implicit-def: $sgpr79 +; SI-NEXT: ; implicit-def: $sgpr75 ; SI-NEXT: ; implicit-def: $sgpr18 -; SI-NEXT: ; implicit-def: $sgpr60 -; SI-NEXT: ; implicit-def: $sgpr59 -; SI-NEXT: ; implicit-def: $sgpr73 +; SI-NEXT: ; implicit-def: $sgpr63 +; SI-NEXT: ; implicit-def: $sgpr61 ; SI-NEXT: ; implicit-def: $sgpr17 ; SI-NEXT: ; kill: killed $sgpr6 -; SI-NEXT: ; implicit-def: $sgpr23 +; SI-NEXT: ; implicit-def: $sgpr59 +; SI-NEXT: ; implicit-def: $sgpr13 ; SI-NEXT: ; implicit-def: $sgpr6 ; SI-NEXT: ; implicit-def: $sgpr99 -; SI-NEXT: ; implicit-def: $sgpr72 ; SI-NEXT: ; implicit-def: $sgpr57 ; SI-NEXT: ; kill: killed $sgpr8 ; SI-NEXT: ; implicit-def: $sgpr8 -; SI-NEXT: ; implicit-def: $sgpr49 -; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; implicit-def: $sgpr51 +; SI-NEXT: ; kill: killed $sgpr11 +; SI-NEXT: ; implicit-def: $sgpr23 +; SI-NEXT: ; implicit-def: $sgpr56 ; SI-NEXT: ; implicit-def: $sgpr97 -; SI-NEXT: ; implicit-def: $sgpr52 -; SI-NEXT: ; implicit-def: $sgpr53 -; SI-NEXT: ; implicit-def: $sgpr54 +; SI-NEXT: ; implicit-def: $sgpr47 +; SI-NEXT: ; implicit-def: $sgpr45 +; SI-NEXT: ; implicit-def: $sgpr24 ; SI-NEXT: ; implicit-def: $sgpr28 -; SI-NEXT: ; implicit-def: $sgpr55 -; SI-NEXT: ; implicit-def: $sgpr64 -; SI-NEXT: ; implicit-def: $sgpr65 +; SI-NEXT: ; implicit-def: $sgpr58 +; SI-NEXT: ; implicit-def: $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr73 ; SI-NEXT: ; implicit-def: $sgpr87 -; SI-NEXT: ; implicit-def: $sgpr66 ; SI-NEXT: ; implicit-def: $sgpr67 +; SI-NEXT: ; implicit-def: $sgpr42 ; SI-NEXT: ; implicit-def: $sgpr68 ; SI-NEXT: ; implicit-def: $sgpr86 -; SI-NEXT: ; implicit-def: $sgpr69 ; SI-NEXT: ; implicit-def: $sgpr70 -; SI-NEXT: ; implicit-def: $sgpr62 +; SI-NEXT: ; implicit-def: $sgpr69 +; SI-NEXT: ; implicit-def: $sgpr94 ; SI-NEXT: ; implicit-def: $sgpr85 -; SI-NEXT: ; implicit-def: $sgpr80 ; SI-NEXT: ; implicit-def: $sgpr11 -; SI-NEXT: ; implicit-def: $sgpr92 +; SI-NEXT: ; implicit-def: $sgpr80 +; SI-NEXT: ; implicit-def: $sgpr31 ; SI-NEXT: ; implicit-def: $sgpr84 -; SI-NEXT: ; implicit-def: $sgpr83 +; SI-NEXT: ; implicit-def: $sgpr15 ; SI-NEXT: s_branch .LBB89_2 ; ; VI-LABEL: bitcast_v128i8_to_v64bf16_scalar: @@ -164542,172 +161891,171 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: scratch_load_b32 v81, off, s32 offset:4 ; GFX11-TRUE16-NEXT: scratch_load_b32 v80, off, s32 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Spill -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:248 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:136 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:124 -; GFX11-TRUE16-NEXT: s_clause 0x1b ; 112-byte Folded Spill -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v155, s32 offset:12 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr152_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr145_lo16 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:244 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:240 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:236 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:232 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v44, s32 offset:228 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v45, s32 offset:224 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v46, s32 offset:220 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v47, s32 offset:216 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v56, s32 offset:212 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v57, s32 offset:208 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v58, s32 offset:204 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v59, s32 offset:200 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v60, s32 offset:196 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v61, s32 offset:192 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v62, s32 offset:188 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v63, s32 offset:184 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v72, s32 offset:180 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v73, s32 offset:176 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v74, s32 offset:172 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v75, s32 offset:168 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v76, s32 offset:164 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v77, s32 offset:160 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v78, s32 offset:156 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v79, s32 offset:152 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v88, s32 offset:148 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v89, s32 offset:144 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v90, s32 offset:140 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v91, s32 offset:136 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v92, s32 offset:132 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v93, s32 offset:128 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v94, s32 offset:124 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v95, s32 offset:120 +; GFX11-TRUE16-NEXT: s_clause 0x1a ; 108-byte Folded Spill +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v104, s32 offset:116 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v105, s32 offset:112 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v106, s32 offset:108 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v107, s32 offset:104 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v108, s32 offset:100 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v109, s32 offset:96 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v110, s32 offset:92 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v111, s32 offset:88 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v120, s32 offset:84 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v121, s32 offset:80 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v122, s32 offset:76 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v123, s32 offset:72 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v124, s32 offset:68 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v125, s32 offset:64 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v126, s32 offset:60 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v127, s32 offset:56 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v136, s32 offset:52 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v137, s32 offset:48 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v138, s32 offset:44 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v139, s32 offset:40 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v140, s32 offset:36 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v141, s32 offset:32 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v142, s32 offset:28 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v143, s32 offset:24 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v152, s32 offset:20 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v153, s32 offset:16 +; GFX11-TRUE16-NEXT: scratch_store_b32 off, v154, s32 offset:12 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr180_hi16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr143_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr141_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr140_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr144_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr142_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr140_lo16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr182_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr127_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr125_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr123_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr139_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr134_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr181_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr126_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr124_lo16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr40_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr121_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr111_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr109_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr122_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr133_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr183_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr110_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr108_lo16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr107_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr104_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr92_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr106_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr104_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr95_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_lo16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_hi16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr91_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr89_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr90_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr88_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr127_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_hi16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr106_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr139_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr105_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr74_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr152_hi16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr61_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr155_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr147_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr138_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr154_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr142_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr132_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr146_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr153_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr46_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr148_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr141_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr138_lo16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr137_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr126_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr136_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr125_lo16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr150_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr124_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr122_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr120_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr149_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr123_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr121_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr111_lo16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr160_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr110_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr108_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr95_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr151_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr109_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr107_lo16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr162_hi16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr94_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr161_hi16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr93_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr90_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr92_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr89_lo16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr164_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr88_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr78_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr76_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr163_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr79_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr77_lo16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr166_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr73_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr63_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr60_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr75_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr165_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr72_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr62_lo16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr176_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr58_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr56_lo16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr179_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr45_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr59_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr167_hi16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr57_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr47_lo16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr178_hi16 -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr44_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr177_hi16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42_lo16 +; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr41_lo16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_hi16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16 @@ -164726,60 +162074,60 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[99:100], 24, v[13:14] ; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[114:115], 24, v[11:12] ; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[117:118], 24, v[9:10] -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[144:145], 24, v[3:4] -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 24, v16 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 8, v16 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v15 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 24, v14 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 8, v14 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v13 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 24, v12 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v77, 8, v12 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v79, 8, v11 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v89, 24, v10 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v91, 8, v10 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v92, 8, v9 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v105, 24, v8 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v107, 8, v8 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v109, 8, v7 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v111, 24, v6 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v121, 8, v6 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v123, 8, v5 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v125, 24, v4 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v127, 8, v4 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v140, 8, v3 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v141, 24, v2 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v143, 8, v2 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v152, 8, v1 +; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[130:131], 24, v[7:8] +; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[133:134], 24, v[5:6] +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 24, v16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 8, v16 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 8, v15 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 24, v14 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 8, v14 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 8, v13 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 24, v12 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v76, 8, v12 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v78, 8, v11 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v88, 24, v10 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v90, 8, v10 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v91, 8, v9 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v104, 24, v8 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v106, 8, v8 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v108, 8, v7 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v110, 24, v6 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v120, 8, v6 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v122, 8, v5 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v124, 24, v4 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v126, 8, v4 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v139, 8, v3 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v140, 24, v2 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v142, 8, v2 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v143, 8, v1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 24, v81 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 8, v81 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 24, v81 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 8, v81 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 8, v80 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 24, v30 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 8, v30 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 8, v29 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 24, v28 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 8, v28 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v76, 8, v27 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v78, 24, v26 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v88, 8, v26 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v90, 8, v25 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v93, 24, v24 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v94, 8, v24 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v95, 8, v23 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v108, 24, v22 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v110, 8, v22 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v120, 8, v21 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v122, 24, v20 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v124, 8, v20 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v126, 8, v19 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v137, 24, v18 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v138, 8, v18 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v142, 8, v17 -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[128:129], 24, v[7:8] -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[134:135], 24, v[5:6] -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[145:146], 24, v[1:2] +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 8, v80 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 24, v30 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v30 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 8, v29 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 24, v28 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 8, v28 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 8, v27 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v77, 24, v26 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v79, 8, v26 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v89, 8, v25 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v92, 24, v24 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v93, 8, v24 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v94, 8, v23 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v107, 24, v22 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v109, 8, v22 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v111, 8, v21 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v121, 24, v20 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v123, 8, v20 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v125, 8, v19 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v136, 24, v18 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v137, 8, v18 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v141, 8, v17 +; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[134:135], 24, v[3:4] +; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[144:145], 24, v[1:2] ; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[82:83], 24, v[80:81] ; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[86:87], 24, v[29:30] ; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[100:101], 24, v[27:28] @@ -164787,70 +162135,70 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[112:113], 24, v[23:24] ; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[115:116], 24, v[21:22] ; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[118:119], 24, v[19:20] -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[132:133], 24, v[17:18] -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v181.h, v1.l +; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[131:132], 24, v[17:18] +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v180.h, v1.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.h, v1.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v180.h, v2.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v179.h, v2.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.h, v2.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v183.h, v3.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v182.h, v3.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.h, v3.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v182.h, v4.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v181.h, v4.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.h, v4.h -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v41.h, v5.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.h, v5.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.h, v5.h -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v40.h, v6.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v183.h, v6.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.h, v6.h -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v72.h, v7.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v63.h, v7.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.h, v7.h -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v46.h, v8.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v45.h, v8.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.h, v8.h -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v104.h, v9.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v95.h, v9.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.h, v9.h -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v74.h, v10.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v73.h, v10.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.h, v10.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v136.h, v11.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v127.h, v11.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.h, v11.h -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v106.h, v12.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v105.h, v12.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.h, v12.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v153.h, v13.l -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.h, v13.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v139.h, v14.l -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v131.h, v14.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v155.h, v15.l -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v147.h, v15.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v154.h, v16.l -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v148.h, v16.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v149.h, v17.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v152.h, v13.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.h, v13.h +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v138.h, v14.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.h, v14.h +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v154.h, v15.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v146.h, v15.h +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v153.h, v16.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v147.h, v16.h +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v148.h, v17.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v17.h ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.h, v18.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.h, v18.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v151.h, v19.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v150.h, v19.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.h, v19.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v150.h, v20.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v149.h, v20.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.h, v20.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v161.h, v21.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v160.h, v21.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.h, v21.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v160.h, v22.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v151.h, v22.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.h, v22.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v163.h, v23.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v162.h, v23.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v37.h, v23.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v162.h, v24.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v161.h, v24.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.h, v24.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v165.h, v25.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v164.h, v25.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.h, v25.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v164.h, v26.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v163.h, v26.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.h, v26.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v167.h, v27.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v166.h, v27.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.h, v27.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v166.h, v28.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v165.h, v28.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.h, v28.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v177.h, v29.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v176.h, v29.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.h, v29.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v176.h, v30.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v167.h, v30.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.h, v30.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v179.h, v80.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.h, v80.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.h, v80.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.h, v81.l +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v177.h, v81.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.h, v81.h ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1 ; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3 @@ -164873,151 +162221,142 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB90_4 ; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true ; GFX11-TRUE16-NEXT: v_and_b32_e32 v32, 0xffff0000, v17 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v18 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v20 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-TRUE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v32 :: v_dual_add_f32 v31, 0x40c00000, v31 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_dual_add_f32 v34, 0x40c00000, v32 :: v_dual_lshlrev_b32 v31, 16, v18 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-TRUE16-NEXT: v_bfe_u32 v38, v34, 16, 1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v31, 16, 1 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v31 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v31, 0x7fff ; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 ; GFX11-TRUE16-NEXT: v_add3_u32 v31, v38, v34, 0x7fff -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v39, v32, v37, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_lshlrev_b32 v17, 16, v17 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v18, 16, 1 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v18 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_add3_u32 v35, v35, v18, 0x7fff -; GFX11-TRUE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v33 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v34 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v35, v36, vcc_lo +; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_cndmask_b32 v32, v35, v36 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_bfe_u32 v48, v17, 16, 1 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v49, 0x400000, v17 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v39.h -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_add3_u32 v37, v48, v17, 0x7fff -; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v137, 24, v32 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v138, 8, v32 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v33, 0xffff0000, v20 +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v149, v37, v49, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v136, 24, v32 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v137, 8, v32 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v148, v37, v49, vcc_lo +; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v33 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v34 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v19 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19 ; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v20 ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v31, v33, vcc_lo ; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v20, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 -; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff +; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v20 ; GFX11-TRUE16-NEXT: v_dual_add_f32 v36, 0x40c00000, v34 :: v_dual_add_f32 v19, 0x40c00000, v19 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_add3_u32 v33, v33, v20, 0x7fff +; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff ; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v31.l, v149.h ; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v36, 16, 1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v150, v33, v35, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v31.l, v148.h +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v149, v33, v35, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v19 -; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v36, 0x7fff ; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v36 -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[132:133], 24, v[31:32] +; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v36, 0x7fff +; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v19 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v22 ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v34, v17, v34, vcc_lo ; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v19, 16, 1 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v142, 8, v31 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v34.l, v149.h +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v141, 8, v31 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v19, 0x7fff -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v151, v17, v33 :: v_dual_and_b32 v18, 0xffff0000, v22 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v150, v17, v33, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v36, v36 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_cndmask_b32 v33, v20, v35 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v21 +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v33, v20, v35 :: v_dual_and_b32 v20, 0xffff0000, v21 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22 -; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v18 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v121, 24, v34 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v123, 8, v34 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_dual_add_f32 v20, 0x40c00000, v20 :: v_dual_add_f32 v21, 0x40c00000, v21 +; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 +; GFX11-TRUE16-NEXT: v_dual_add_f32 v21, 0x40c00000, v21 :: v_dual_lshlrev_b32 v22, 16, v22 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v34.l, v150.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v33.l, v151.h ; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v22 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v122, 24, v34 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v124, 8, v34 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v24 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v126, 8, v33 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v160, v19, v35, vcc_lo +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v151, v19, v35 :: v_dual_lshlrev_b32 v22, 16, v24 +; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v20 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 +; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v20, 0x7fff +; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1 +; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v18 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 +; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff ; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v24 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v21 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v36, v17, v36, vcc_lo ; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v21, 16, 1 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v36.l, v151.h ; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v23 -; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v20 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v161, v17, v24, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v160, v17, v24 :: v_dual_lshlrev_b32 v21, 16, v23 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v20, 0x7fff +; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v23 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v36.l, v160.h +; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v18 ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v35, v19, v35, vcc_lo ; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v35.l, v161.h -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff +; GFX11-TRUE16-NEXT: v_dual_add_f32 v21, 0x40c00000, v21 :: v_dual_add_f32 v20, 0x40c00000, v20 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v26 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v120, 8, v35 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v162, v19, v23, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v107, 24, v36 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v109, 8, v36 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v161, v19, v23, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 ; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21 -; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 -; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v20, 0x7fff -; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v18 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 -; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff ; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v26 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v38, v17, v24, vcc_lo ; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v21, 16, 1 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21 +; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v20, 0x7fff ; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v20 ; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 ; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v25 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v108, 24, v36 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v110, 8, v36 +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v33.l, v150.h +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v38.l, v161.h ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v163, v17, v23, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v162, v17, v23, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 ; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22 @@ -165031,9 +162370,9 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 ; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v28 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v37.l, v163.h +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v125, 8, v33 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v164, v19, v23, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v163, v19, v23, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 ; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21 @@ -165046,9 +162385,10 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 ; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v27 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v95, 8, v37 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v165, v17, v23, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v35.l, v160.h +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v49.l, v163.h +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v164, v17, v23, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 ; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22 @@ -165061,10 +162401,10 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 ; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v30 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v38.l, v162.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v48.l, v165.h -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v166, v19, v23, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v77, 24, v49 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v79, 8, v49 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v111, 8, v35 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v165, v19, v23, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 ; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21 @@ -165077,10 +162417,10 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 ; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v29 -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[112:113], 24, v[37:38] -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v93, 24, v38 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v94, 8, v38 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v167, v17, v23, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v51.l, v165.h +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v92, 24, v38 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v93, 8, v38 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v166, v17, v23, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 ; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22 @@ -165094,9 +162434,9 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1) ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v81 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v50.l, v167.h -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v176, v19, v23, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 24, v51 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 8, v51 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v167, v19, v23, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 ; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21 @@ -165110,9 +162450,9 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v80 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v49.l, v164.h +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v53.l, v167.h ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v177, v17, v23, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v176, v17, v23, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 ; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v22 @@ -165125,10 +162465,10 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 ; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v22, 0x7fff ; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v21 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v52.l, v177.h -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v78, 24, v49 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v88, 8, v49 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v178, v19, v23, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v37.l, v162.h +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 24, v53 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v53 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v177, v19, v23, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 ; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v2 @@ -165141,9 +162481,11 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 ; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 ; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v21, 0x7fff -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v55.l, v177.h +; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[112:113], 24, v[37:38] ; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v179, v17, v22, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v94, 8, v37 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v178, v17, v22, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 ; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v1 @@ -165154,12 +162496,13 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 ; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v18, 0x7fff ; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v20, 0x40c00000, v20 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v2, 0x7fff -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v54.l, v179.h +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 24, v55 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 8, v55 ; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v20, 16, 1 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v180, v19, v21, vcc_lo +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v179, v19, v21, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v4 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 @@ -165172,10 +162515,10 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 ; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 ; GFX11-TRUE16-NEXT: v_add3_u32 v17, v17, v1, 0x7fff -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v90, 8, v48 +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v65.l, v179.h ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v18, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v181, v17, v19, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v180, v17, v19, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v3 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 @@ -165190,9 +162533,9 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v4, 0x7fff ; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v6 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v51.l, v166.h -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v64.l, v181.h -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v182, v2, v19, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v48.l, v164.h +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v140, 24, v65 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v181, v2, v19, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18 ; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v17, 16, 1 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v3 @@ -165202,13 +162545,13 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 ; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v17, 0x7fff ; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 24, v51 +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v67.l, v181.h ; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v3, 0x7fff ; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v5 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v53.l, v176.h -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 8, v51 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v183, v1, v18, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v50.l, v166.h +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v124, 24, v67 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v182, v1, v18, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17 ; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6 @@ -165219,13 +162562,13 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v4, 0x7fff ; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v66.l, v183.h +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v126, 8, v67 ; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v6, 0x7fff ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v8 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 24, v53 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 8, v53 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v76, 8, v50 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v40, v2, v17, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v142, 8, v65 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 8, v50 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v89, 8, v48 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v183, v2, v17, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v8 @@ -165239,25 +162582,26 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v3 ; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v3, 0x7fff ; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v6, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v41, v2, v8, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v69.l, v183.h +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v40, v2, v8, vcc_lo ; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v4, 16, 1 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_add3_u32 v3, v5, v6, 0x7fff ; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v110, 24, v69 ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v68, v1, v17, vcc_lo ; GFX11-TRUE16-NEXT: v_add3_u32 v1, v2, v4, 0x7fff ; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v7 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v10 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v41.h -; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v46, v3, v5, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v120, 8, v69 +; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_cndmask_b32 v45, v3, v5 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v7 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v10 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2 ; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_cndmask_b32 v71, v1, v8 ; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1 @@ -165268,8 +162612,8 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff ; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff ; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v46.h -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[86:87], 24, v[52:53] +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v45.h +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v52.l, v176.h ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v70, v1, v7, vcc_lo ; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 @@ -165277,14 +162621,15 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v6, 0x7fff ; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6 ; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v72, v4, v8, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v63, v4, v8, vcc_lo ; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v5 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v12 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v11 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v55.l, v178.h -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v74, v1, v4 :: v_dual_lshlrev_b32 v1, 16, v9 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v63.h +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v73, v1, v4, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v9 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v12 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3 @@ -165298,30 +162643,31 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v13 ; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff ; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v67.l, v182.h -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v74.h -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v72.h +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v73.h +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v54.l, v178.h +; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[130:131], 24, v[70:71] ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v84, v2, v6, vcc_lo ; GFX11-TRUE16-NEXT: v_add3_u32 v2, v7, v1, 0x7fff ; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 ; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1 -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[128:129], 24, v[70:71] ; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[82:83], 24, v[54:55] +; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[86:87], 24, v[52:53] ; GFX11-TRUE16-NEXT: v_add3_u32 v1, v6, v5, 0x7fff -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v104, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v95, v2, v3, vcc_lo ; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v5 ; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v8 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX11-TRUE16-NEXT: v_add3_u32 v3, v7, v4, 0x7fff ; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v14 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v104.h -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v106, v1, v2 :: v_dual_lshlrev_b32 v1, 16, v11 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v95.h +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v105, v1, v2, vcc_lo +; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v11 ; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v14 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v65.l, v180.h +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v64.l, v180.h ; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 ; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v6, 0x7fff ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v103, v3, v7, vcc_lo @@ -165329,7 +162675,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v13 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v106.h +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v105.h ; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[117:118], 24, v[84:85] ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v102, v2, v3, vcc_lo ; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v4 :: v_dual_add_f32 v3, 0x40c00000, v5 @@ -165340,8 +162686,8 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1 ; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1 ; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v6 -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[118:119], 24, v[33:34] -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v136, v4, v5, vcc_lo +; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[144:145], 24, v[64:65] +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v127, v4, v5, vcc_lo ; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff ; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 @@ -165349,19 +162695,19 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3 ; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1 ; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v9 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v131, v4, v5, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v129, v4, v5, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1 ; GFX11-TRUE16-NEXT: v_add3_u32 v3, v8, v1, 0x7fff ; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v16 ; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v15 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v139, v6, v7, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v138, v6, v7, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 ; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1 ; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v5 ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v15 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v131.l, v139.h -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v130, v3, v4, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.l, v138.h +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v128, v3, v4, vcc_lo ; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v16 ; GFX11-TRUE16-NEXT: v_add3_u32 v4, v6, v2, 0x7fff ; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v2 @@ -165369,11 +162715,11 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 ; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v102.l, v136.h -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v40.h +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v40.h +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v127.h ; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v5 ; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v153, v4, v6, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v152, v4, v6, vcc_lo ; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v1, 0x7fff ; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3 @@ -165382,141 +162728,135 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v8 ; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff ; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v153.h -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v154, v2, v9, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v152.h +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v153, v2, v9, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6 -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[99:100], 24, v[130:131] -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[114:115], 24, v[102:103] -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v155, v7, v11, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v66.l, v182.h +; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[99:100], 24, v[128:129] +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v154, v7, v11, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 ; GFX11-TRUE16-NEXT: v_add3_u32 v2, v10, v6, 0x7fff -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[144:145], 24, v[66:67] -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[134:135], 24, v[68:69] -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[145:146], 24, v[64:65] -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v148, v4, v8, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v148.l, v154.h +; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[114:115], 24, v[102:103] ; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[100:101], 24, v[50:51] ; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[115:116], 24, v[35:36] -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 24, v131 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v147, v2, v3, vcc_lo -; GFX11-TRUE16-NEXT: v_mov_b16_e64 v147.l, v155.h -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 24, v148 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 8, v148 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 8, v131 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v130 -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[96:97], 24, v[147:148] +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v147, v4, v8, vcc_lo +; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v147.l, v153.h +; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[133:134], 24, v[68:69] +; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[134:135], 24, v[66:67] +; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[118:119], 24, v[33:34] +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v146, v2, v3, vcc_lo +; GFX11-TRUE16-NEXT: v_mov_b16_e64 v146.l, v154.h +; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[131:132], 24, v[31:32] +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 24, v147 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 8, v147 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 24, v129 +; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[96:97], 24, v[146:147] ; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[97:98], 24, v[48:49] -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v147 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v75, 24, v103 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v77, 8, v103 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v79, 8, v102 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v89, 24, v85 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v91, 8, v85 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v92, 8, v84 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v105, 24, v71 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v107, 8, v71 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v109, 8, v70 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v111, 24, v69 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v121, 8, v69 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v123, 8, v68 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v125, 24, v67 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v127, 8, v67 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v140, 8, v66 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v141, 24, v65 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v143, 8, v65 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v152, 8, v64 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 24, v55 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 8, v55 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 8, v54 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 8, v52 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 8, v146 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 8, v129 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 8, v128 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v74, 24, v103 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v76, 8, v103 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v78, 8, v102 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v88, 24, v85 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v90, 8, v85 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v91, 8, v84 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v104, 24, v71 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v106, 8, v71 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v108, 8, v70 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v122, 8, v68 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v139, 8, v66 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v143, 8, v64 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 8, v54 +; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 8, v52 ; GFX11-TRUE16-NEXT: .LBB90_4: ; %end ; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0 -; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v181.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v152.l +; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v180.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v143.l ; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v64.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v145.l -; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v180.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v143.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v144.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v179.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v142.l ; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v65.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v141.l -; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v183.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v140.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v140.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v182.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v139.l ; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v66.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v144.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v134.l ; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.l, v1.h ; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v2.l, v2.h ; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v3.l, v3.h ; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v4.l, v4.h ; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v5.l, v5.h ; GFX11-TRUE16-NEXT: v_or_b16 v3.h, v6.l, v6.h -; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v182.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v127.l +; GFX11-TRUE16-NEXT: v_and_b16 v4.l, 0xff, v181.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.h, 8, v126.l ; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v67.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v125.l -; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v41.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v123.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v124.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v40.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v122.l ; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v68.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v134.l -; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v40.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v121.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v133.l +; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v183.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v120.l ; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v4.l, v4.h ; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v5.l, v5.h ; GFX11-TRUE16-NEXT: v_or_b16 v5.l, v6.l, v6.h ; GFX11-TRUE16-NEXT: v_or_b16 v5.h, v7.l, v7.h ; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v8.l, v8.h ; GFX11-TRUE16-NEXT: v_and_b16 v6.h, 0xff, v69.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.l, 8, v111.l -; GFX11-TRUE16-NEXT: v_and_b16 v7.h, 0xff, v72.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v109.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.l, 8, v110.l +; GFX11-TRUE16-NEXT: v_and_b16 v7.h, 0xff, v63.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v108.l ; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v70.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v128.l -; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v46.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v107.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v130.l +; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v45.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v106.l ; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v71.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v105.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v104.l ; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v6.h, v7.l ; GFX11-TRUE16-NEXT: v_or_b16 v7.l, v7.h, v8.l ; GFX11-TRUE16-NEXT: v_or_b16 v7.h, v8.h, v9.l ; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v9.h, v10.l ; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v10.h, v11.l -; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v104.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v92.l +; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v95.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v91.l ; GFX11-TRUE16-NEXT: s_clause 0x1 ; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off ; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16 ; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v85.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v89.l -; GFX11-TRUE16-NEXT: v_and_b16 v3.h, 0xff, v136.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v79.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v88.l +; GFX11-TRUE16-NEXT: v_and_b16 v3.h, 0xff, v127.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v78.l ; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v102.h ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v114.l -; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v106.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v77.l +; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v105.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v76.l ; GFX11-TRUE16-NEXT: v_and_b16 v6.h, 0xff, v103.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.l, 8, v75.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.l, 8, v74.l ; GFX11-TRUE16-NEXT: v_and_b16 v10.l, 0xff, v84.h ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.h, 8, v117.l -; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v74.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v91.l +; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v73.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v90.l ; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v9.l, v9.h ; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v2.h, v3.l ; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v3.h, v4.l ; GFX11-TRUE16-NEXT: v_or_b16 v3.h, v4.h, v5.l ; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v5.h, v6.l ; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v6.h, v7.l -; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v153.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v62.l -; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v130.h +; GFX11-TRUE16-NEXT: v_and_b16 v5.l, 0xff, v152.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.h, 8, v61.l +; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v128.h ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v99.l -; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v139.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v61.l -; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v131.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v59.l -; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v155.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v57.l +; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v138.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v60.l +; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v129.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v58.l +; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v154.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.h, 8, v56.l ; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v10.l, v10.h ; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v11.l, v11.h ; GFX11-TRUE16-NEXT: v_or_b16 v5.l, v5.l, v5.h @@ -165524,61 +162864,61 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v7.l, v7.h ; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v8.l, v8.h ; GFX11-TRUE16-NEXT: v_or_b16 v7.l, v9.l, v9.h -; GFX11-TRUE16-NEXT: v_and_b16 v7.h, 0xff, v147.h +; GFX11-TRUE16-NEXT: v_and_b16 v7.h, 0xff, v146.h ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.l, 8, v96.l -; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v154.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v47.l -; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v148.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v44.l -; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v149.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v142.l +; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v153.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v46.l +; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v147.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v43.l +; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v148.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v141.l ; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v31.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v132.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.l, 8, v131.l ; GFX11-TRUE16-NEXT: v_or_b16 v7.h, v7.h, v8.l ; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.h, v9.l ; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.h, v10.l ; GFX11-TRUE16-NEXT: v_or_b16 v9.l, v10.h, v11.l ; GFX11-TRUE16-NEXT: v_or_b16 v9.h, v11.h, v12.l ; GFX11-TRUE16-NEXT: v_and_b16 v10.l, 0xff, v39.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.h, 8, v138.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.h, 8, v137.l ; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v32.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v137.l -; GFX11-TRUE16-NEXT: v_and_b16 v12.l, 0xff, v151.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.h, 8, v126.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v136.l +; GFX11-TRUE16-NEXT: v_and_b16 v12.l, 0xff, v150.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.h, 8, v125.l ; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v33.h ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.h, 8, v118.l -; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v150.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v124.l +; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v149.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v123.l ; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.l, v10.h ; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v11.h ; GFX11-TRUE16-NEXT: v_or_b16 v11.l, v12.l, v12.h ; GFX11-TRUE16-NEXT: v_or_b16 v11.h, v13.l, v13.h ; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v14.l, v14.h ; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v34.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.l, 8, v122.l -; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v161.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.l, 8, v120.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.l, 8, v121.l +; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v160.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.l, 8, v111.l ; GFX11-TRUE16-NEXT: v_and_b16 v14.h, 0xff, v35.h ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.l, 8, v115.l -; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v160.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v110.l +; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v151.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v109.l ; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v36.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v108.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v107.l ; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v12.h, v13.l ; GFX11-TRUE16-NEXT: v_or_b16 v13.l, v13.h, v14.l ; GFX11-TRUE16-NEXT: v_or_b16 v13.h, v14.h, v15.l ; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v15.h, v16.l ; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v16.h, v17.l -; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v163.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.h, 8, v95.l +; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v162.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v15.h, 8, v94.l ; GFX11-TRUE16-NEXT: v_and_b16 v16.l, 0xff, v37.h ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.h, 8, v112.l -; GFX11-TRUE16-NEXT: v_and_b16 v17.l, 0xff, v162.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v94.l +; GFX11-TRUE16-NEXT: v_and_b16 v17.l, 0xff, v161.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v93.l ; GFX11-TRUE16-NEXT: v_and_b16 v18.l, 0xff, v38.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v93.l -; GFX11-TRUE16-NEXT: v_and_b16 v19.l, 0xff, v165.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.h, 8, v90.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v92.l +; GFX11-TRUE16-NEXT: v_and_b16 v19.l, 0xff, v164.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.h, 8, v89.l ; GFX11-TRUE16-NEXT: v_or_b16 v15.l, v15.l, v15.h ; GFX11-TRUE16-NEXT: v_or_b16 v15.h, v16.l, v16.h ; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v17.l, v17.h @@ -165586,12 +162926,12 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_or_b16 v17.l, v19.l, v19.h ; GFX11-TRUE16-NEXT: v_and_b16 v17.h, 0xff, v48.h ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v97.l -; GFX11-TRUE16-NEXT: v_and_b16 v18.h, 0xff, v164.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.l, 8, v88.l +; GFX11-TRUE16-NEXT: v_and_b16 v18.h, 0xff, v163.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.l, 8, v79.l ; GFX11-TRUE16-NEXT: v_and_b16 v19.h, 0xff, v49.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v78.l -; GFX11-TRUE16-NEXT: v_and_b16 v20.h, 0xff, v167.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v76.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v77.l +; GFX11-TRUE16-NEXT: v_and_b16 v20.h, 0xff, v166.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v75.l ; GFX11-TRUE16-NEXT: v_and_b16 v21.h, 0xff, v50.h ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v22.l, 8, v100.l ; GFX11-TRUE16-NEXT: v_or_b16 v17.h, v17.h, v18.l @@ -165599,31 +162939,31 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: v_or_b16 v18.h, v19.h, v20.l ; GFX11-TRUE16-NEXT: v_or_b16 v19.l, v20.h, v21.l ; GFX11-TRUE16-NEXT: v_or_b16 v19.h, v21.h, v22.l -; GFX11-TRUE16-NEXT: v_and_b16 v20.l, 0xff, v166.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.h, 8, v73.l +; GFX11-TRUE16-NEXT: v_and_b16 v20.l, 0xff, v165.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.h, 8, v72.l ; GFX11-TRUE16-NEXT: v_and_b16 v21.l, 0xff, v51.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.h, 8, v63.l -; GFX11-TRUE16-NEXT: v_and_b16 v22.l, 0xff, v177.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v22.h, 8, v60.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.h, 8, v62.l +; GFX11-TRUE16-NEXT: v_and_b16 v22.l, 0xff, v176.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v22.h, 8, v59.l ; GFX11-TRUE16-NEXT: v_and_b16 v23.l, 0xff, v52.h ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v23.h, 8, v86.l -; GFX11-TRUE16-NEXT: v_and_b16 v24.l, 0xff, v176.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v24.h, 8, v58.l +; GFX11-TRUE16-NEXT: v_and_b16 v24.l, 0xff, v167.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v24.h, 8, v57.l ; GFX11-TRUE16-NEXT: v_or_b16 v20.l, v20.l, v20.h ; GFX11-TRUE16-NEXT: v_or_b16 v20.h, v21.l, v21.h ; GFX11-TRUE16-NEXT: v_or_b16 v21.l, v22.l, v22.h ; GFX11-TRUE16-NEXT: v_or_b16 v21.h, v23.l, v23.h ; GFX11-TRUE16-NEXT: v_or_b16 v22.l, v24.l, v24.h ; GFX11-TRUE16-NEXT: v_and_b16 v22.h, 0xff, v53.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v23.l, 8, v56.l -; GFX11-TRUE16-NEXT: v_and_b16 v23.h, 0xff, v179.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v24.l, 8, v45.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v23.l, 8, v47.l +; GFX11-TRUE16-NEXT: v_and_b16 v23.h, 0xff, v178.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v24.l, 8, v44.l ; GFX11-TRUE16-NEXT: v_and_b16 v24.h, 0xff, v54.h ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v25.l, 8, v82.l -; GFX11-TRUE16-NEXT: v_and_b16 v25.h, 0xff, v178.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v26.l, 8, v43.l +; GFX11-TRUE16-NEXT: v_and_b16 v25.h, 0xff, v177.h +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v26.l, 8, v42.l ; GFX11-TRUE16-NEXT: v_and_b16 v26.h, 0xff, v55.h -; GFX11-TRUE16-NEXT: v_lshlrev_b16 v27.l, 8, v42.l +; GFX11-TRUE16-NEXT: v_lshlrev_b16 v27.l, 8, v41.l ; GFX11-TRUE16-NEXT: v_or_b16 v22.h, v22.h, v23.l ; GFX11-TRUE16-NEXT: v_or_b16 v23.l, v23.h, v24.l ; GFX11-TRUE16-NEXT: v_or_b16 v23.h, v24.h, v25.l @@ -165637,67 +162977,66 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) { ; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[17:20], off offset:96 ; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[21:24], off offset:112 ; GFX11-TRUE16-NEXT: s_clause 0x1f ; 128-byte Folded Reload -; GFX11-TRUE16-NEXT: scratch_load_b32 v155, off, s32 offset:12 -; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:16 -; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:20 -; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:24 -; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:28 -; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:36 -; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:40 -; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:44 -; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:48 -; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:52 -; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:56 -; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:60 -; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:64 -; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:68 -; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:72 -; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:76 -; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:80 -; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:84 -; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:88 -; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:92 -; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:96 -; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:100 -; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:104 -; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:108 -; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:112 -; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:116 -; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:120 -; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:124 -; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:128 -; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:132 -; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:136 -; GFX11-TRUE16-NEXT: s_clause 0x1b ; 112-byte Folded Reload -; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:140 -; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:144 -; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:148 -; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:152 -; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:156 -; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:160 -; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:164 -; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:168 -; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:172 -; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:176 -; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:180 -; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:184 -; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:188 -; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:192 -; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:196 -; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:200 -; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:204 -; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:208 -; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:212 -; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:216 -; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:220 -; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:224 -; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:228 -; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:232 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:236 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:240 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:244 -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:248 +; GFX11-TRUE16-NEXT: scratch_load_b32 v154, off, s32 offset:12 +; GFX11-TRUE16-NEXT: scratch_load_b32 v153, off, s32 offset:16 +; GFX11-TRUE16-NEXT: scratch_load_b32 v152, off, s32 offset:20 +; GFX11-TRUE16-NEXT: scratch_load_b32 v143, off, s32 offset:24 +; GFX11-TRUE16-NEXT: scratch_load_b32 v142, off, s32 offset:28 +; GFX11-TRUE16-NEXT: scratch_load_b32 v141, off, s32 offset:32 +; GFX11-TRUE16-NEXT: scratch_load_b32 v140, off, s32 offset:36 +; GFX11-TRUE16-NEXT: scratch_load_b32 v139, off, s32 offset:40 +; GFX11-TRUE16-NEXT: scratch_load_b32 v138, off, s32 offset:44 +; GFX11-TRUE16-NEXT: scratch_load_b32 v137, off, s32 offset:48 +; GFX11-TRUE16-NEXT: scratch_load_b32 v136, off, s32 offset:52 +; GFX11-TRUE16-NEXT: scratch_load_b32 v127, off, s32 offset:56 +; GFX11-TRUE16-NEXT: scratch_load_b32 v126, off, s32 offset:60 +; GFX11-TRUE16-NEXT: scratch_load_b32 v125, off, s32 offset:64 +; GFX11-TRUE16-NEXT: scratch_load_b32 v124, off, s32 offset:68 +; GFX11-TRUE16-NEXT: scratch_load_b32 v123, off, s32 offset:72 +; GFX11-TRUE16-NEXT: scratch_load_b32 v122, off, s32 offset:76 +; GFX11-TRUE16-NEXT: scratch_load_b32 v121, off, s32 offset:80 +; GFX11-TRUE16-NEXT: scratch_load_b32 v120, off, s32 offset:84 +; GFX11-TRUE16-NEXT: scratch_load_b32 v111, off, s32 offset:88 +; GFX11-TRUE16-NEXT: scratch_load_b32 v110, off, s32 offset:92 +; GFX11-TRUE16-NEXT: scratch_load_b32 v109, off, s32 offset:96 +; GFX11-TRUE16-NEXT: scratch_load_b32 v108, off, s32 offset:100 +; GFX11-TRUE16-NEXT: scratch_load_b32 v107, off, s32 offset:104 +; GFX11-TRUE16-NEXT: scratch_load_b32 v106, off, s32 offset:108 +; GFX11-TRUE16-NEXT: scratch_load_b32 v105, off, s32 offset:112 +; GFX11-TRUE16-NEXT: scratch_load_b32 v104, off, s32 offset:116 +; GFX11-TRUE16-NEXT: scratch_load_b32 v95, off, s32 offset:120 +; GFX11-TRUE16-NEXT: scratch_load_b32 v94, off, s32 offset:124 +; GFX11-TRUE16-NEXT: scratch_load_b32 v93, off, s32 offset:128 +; GFX11-TRUE16-NEXT: scratch_load_b32 v92, off, s32 offset:132 +; GFX11-TRUE16-NEXT: scratch_load_b32 v91, off, s32 offset:136 +; GFX11-TRUE16-NEXT: s_clause 0x1a ; 108-byte Folded Reload +; GFX11-TRUE16-NEXT: scratch_load_b32 v90, off, s32 offset:140 +; GFX11-TRUE16-NEXT: scratch_load_b32 v89, off, s32 offset:144 +; GFX11-TRUE16-NEXT: scratch_load_b32 v88, off, s32 offset:148 +; GFX11-TRUE16-NEXT: scratch_load_b32 v79, off, s32 offset:152 +; GFX11-TRUE16-NEXT: scratch_load_b32 v78, off, s32 offset:156 +; GFX11-TRUE16-NEXT: scratch_load_b32 v77, off, s32 offset:160 +; GFX11-TRUE16-NEXT: scratch_load_b32 v76, off, s32 offset:164 +; GFX11-TRUE16-NEXT: scratch_load_b32 v75, off, s32 offset:168 +; GFX11-TRUE16-NEXT: scratch_load_b32 v74, off, s32 offset:172 +; GFX11-TRUE16-NEXT: scratch_load_b32 v73, off, s32 offset:176 +; GFX11-TRUE16-NEXT: scratch_load_b32 v72, off, s32 offset:180 +; GFX11-TRUE16-NEXT: scratch_load_b32 v63, off, s32 offset:184 +; GFX11-TRUE16-NEXT: scratch_load_b32 v62, off, s32 offset:188 +; GFX11-TRUE16-NEXT: scratch_load_b32 v61, off, s32 offset:192 +; GFX11-TRUE16-NEXT: scratch_load_b32 v60, off, s32 offset:196 +; GFX11-TRUE16-NEXT: scratch_load_b32 v59, off, s32 offset:200 +; GFX11-TRUE16-NEXT: scratch_load_b32 v58, off, s32 offset:204 +; GFX11-TRUE16-NEXT: scratch_load_b32 v57, off, s32 offset:208 +; GFX11-TRUE16-NEXT: scratch_load_b32 v56, off, s32 offset:212 +; GFX11-TRUE16-NEXT: scratch_load_b32 v47, off, s32 offset:216 +; GFX11-TRUE16-NEXT: scratch_load_b32 v46, off, s32 offset:220 +; GFX11-TRUE16-NEXT: scratch_load_b32 v45, off, s32 offset:224 +; GFX11-TRUE16-NEXT: scratch_load_b32 v44, off, s32 offset:228 +; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:232 +; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:236 +; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:240 +; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:244 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] ; @@ -166896,40 +164235,43 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; SI: ; %bb.0: ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-NEXT: s_or_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill ; SI-NEXT: s_mov_b64 exec, s[4:5] -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:80 +; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80 ; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:4 ; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 -; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:12 -; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:8 -; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:20 -; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:16 -; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:28 -; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:24 -; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:36 -; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:32 -; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:44 +; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:12 +; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:8 +; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:20 +; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:16 +; SI-NEXT: s_waitcnt expcnt(3) +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:28 +; SI-NEXT: s_waitcnt expcnt(2) +; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:24 +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:36 +; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:32 +; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:44 ; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:40 ; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:52 ; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:48 -; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:60 -; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56 +; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 +; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:68 ; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:64 ; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:76 @@ -166962,1627 +164304,1841 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; SI-NEXT: v_writelane_b32 v63, s81, 25 ; SI-NEXT: v_writelane_b32 v63, s82, 26 ; SI-NEXT: v_writelane_b32 v63, s83, 27 -; SI-NEXT: s_waitcnt expcnt(5) -; SI-NEXT: v_mul_f32_e32 v56, 1.0, v2 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v10 ; SI-NEXT: v_writelane_b32 v63, s84, 28 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v9 ; SI-NEXT: v_writelane_b32 v63, s85, 29 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v14 ; SI-NEXT: v_writelane_b32 v63, s86, 30 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v15 ; SI-NEXT: v_writelane_b32 v63, s87, 31 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v18 +; SI-NEXT: v_mul_f32_e32 v39, 1.0, v10 ; SI-NEXT: v_writelane_b32 v63, s96, 32 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v26 ; SI-NEXT: v_writelane_b32 v63, s97, 33 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill ; SI-NEXT: v_writelane_b32 v63, s98, 34 -; SI-NEXT: v_mov_b32_e32 v46, v21 ; SI-NEXT: v_writelane_b32 v63, s99, 35 -; SI-NEXT: v_mul_f32_e32 v47, 1.0, v1 -; SI-NEXT: v_mul_f32_e32 v32, 1.0, v4 -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3 -; SI-NEXT: v_mul_f32_e32 v58, 1.0, v6 -; SI-NEXT: v_mul_f32_e32 v41, 1.0, v5 -; SI-NEXT: v_mul_f32_e32 v59, 1.0, v8 -; SI-NEXT: v_mul_f32_e32 v61, 1.0, v7 -; SI-NEXT: v_mul_f32_e32 v5, 1.0, v12 -; SI-NEXT: v_mul_f32_e32 v60, 1.0, v11 -; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 -; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13 -; SI-NEXT: v_mul_f32_e32 v21, 1.0, v16 -; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17 -; SI-NEXT: v_mul_f32_e32 v9, 1.0, v20 -; SI-NEXT: v_mul_f32_e32 v12, 1.0, v19 -; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22 -; SI-NEXT: v_mul_f32_e32 v20, 1.0, v46 +; SI-NEXT: v_mul_f32_e32 v35, 1.0, v2 +; SI-NEXT: v_mul_f32_e32 v51, 1.0, v1 +; SI-NEXT: v_mul_f32_e32 v47, 1.0, v4 +; SI-NEXT: v_mul_f32_e32 v46, 1.0, v3 +; SI-NEXT: v_mul_f32_e32 v6, 1.0, v6 +; SI-NEXT: v_mul_f32_e32 v3, 1.0, v5 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8 +; SI-NEXT: v_mul_f32_e32 v5, 1.0, v7 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v48 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill -; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24 -; SI-NEXT: v_mul_f32_e32 v46, 1.0, v23 +; SI-NEXT: v_mul_f32_e32 v60, 1.0, v9 +; SI-NEXT: v_mul_f32_e32 v9, 1.0, v12 +; SI-NEXT: v_mul_f32_e32 v31, 1.0, v11 +; SI-NEXT: v_mul_f32_e32 v2, 1.0, v14 +; SI-NEXT: v_mul_f32_e32 v7, 1.0, v13 +; SI-NEXT: v_mul_f32_e32 v4, 1.0, v15 +; SI-NEXT: v_mul_f32_e32 v55, 1.0, v18 +; SI-NEXT: v_mul_f32_e32 v18, 1.0, v17 +; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20 +; SI-NEXT: v_mul_f32_e32 v12, 1.0, v19 +; SI-NEXT: v_mul_f32_e32 v8, 1.0, v22 +; SI-NEXT: v_mul_f32_e32 v19, 1.0, v21 +; SI-NEXT: v_mul_f32_e32 v21, 1.0, v24 +; SI-NEXT: v_mul_f32_e32 v22, 1.0, v23 +; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v32 +; SI-NEXT: v_mul_f32_e32 v32, 1.0, v16 +; SI-NEXT: v_mul_f32_e32 v23, 1.0, v26 +; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25 +; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28 +; SI-NEXT: v_mul_f32_e32 v10, 1.0, v38 +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v52 -; SI-NEXT: v_mul_f32_e32 v26, 1.0, v25 -; SI-NEXT: v_mul_f32_e32 v57, 1.0, v28 -; SI-NEXT: v_mul_f32_e32 v16, 1.0, v27 -; SI-NEXT: v_mul_f32_e32 v28, 1.0, v30 -; SI-NEXT: v_mul_f32_e32 v30, 1.0, v29 -; SI-NEXT: v_mul_f32_e32 v31, 1.0, v33 -; SI-NEXT: v_mul_f32_e32 v27, 1.0, v34 +; SI-NEXT: v_mul_f32_e32 v10, 1.0, v48 +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27 +; SI-NEXT: v_mul_f32_e32 v26, 1.0, v30 +; SI-NEXT: v_mul_f32_e32 v24, 1.0, v29 +; SI-NEXT: v_mul_f32_e32 v29, 1.0, v33 +; SI-NEXT: v_mul_f32_e32 v17, 1.0, v34 +; SI-NEXT: s_waitcnt vmcnt(8) expcnt(0) +; SI-NEXT: v_mul_f32_e32 v10, 1.0, v54 +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill ; SI-NEXT: s_and_b64 s[4:5], vcc, exec -; SI-NEXT: v_mul_f32_e32 v29, 1.0, v35 -; SI-NEXT: v_mul_f32_e32 v36, 1.0, v36 -; SI-NEXT: v_mul_f32_e32 v35, 1.0, v37 -; SI-NEXT: v_mul_f32_e32 v34, 1.0, v38 -; SI-NEXT: v_mul_f32_e32 v37, 1.0, v39 -; SI-NEXT: v_mul_f32_e32 v48, 1.0, v49 -; SI-NEXT: v_mul_f32_e32 v39, 1.0, v50 -; SI-NEXT: v_mul_f32_e32 v33, 1.0, v51 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_mul_f32_e32 v51, 1.0, v53 -; SI-NEXT: v_mul_f32_e32 v50, 1.0, v54 -; SI-NEXT: s_waitcnt vmcnt(13) -; SI-NEXT: v_mul_f32_e32 v49, 1.0, v55 -; SI-NEXT: s_waitcnt vmcnt(12) +; SI-NEXT: s_waitcnt vmcnt(6) expcnt(0) +; SI-NEXT: v_mul_f32_e32 v10, 1.0, v42 +; SI-NEXT: v_mul_f32_e32 v33, 1.0, v36 +; SI-NEXT: v_mul_f32_e32 v37, 1.0, v37 +; SI-NEXT: v_mul_f32_e32 v57, 1.0, v57 +; SI-NEXT: v_mul_f32_e32 v36, 1.0, v58 +; SI-NEXT: v_mul_f32_e32 v58, 1.0, v59 +; SI-NEXT: v_mul_f32_e32 v59, 1.0, v49 +; SI-NEXT: v_mul_f32_e32 v50, 1.0, v50 +; SI-NEXT: v_mul_f32_e32 v49, 1.0, v52 +; SI-NEXT: v_mul_f32_e32 v53, 1.0, v53 ; SI-NEXT: v_mul_f32_e32 v38, 1.0, v40 -; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_mul_f32_e32 v55, 1.0, v42 -; SI-NEXT: s_waitcnt vmcnt(10) -; SI-NEXT: v_mul_f32_e32 v54, 1.0, v43 -; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_mul_f32_e32 v43, 1.0, v44 -; SI-NEXT: s_waitcnt vmcnt(8) -; SI-NEXT: v_mul_f32_e32 v53, 1.0, v45 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s17 -; SI-NEXT: v_mul_f32_e64 v11, 1.0, s16 -; SI-NEXT: v_mul_f32_e64 v3, 1.0, s19 -; SI-NEXT: v_mul_f32_e64 v4, 1.0, s18 -; SI-NEXT: v_mul_f32_e64 v14, 1.0, s21 -; SI-NEXT: v_mul_f32_e64 v15, 1.0, s20 -; SI-NEXT: v_mul_f32_e64 v7, 1.0, s23 -; SI-NEXT: v_mul_f32_e64 v6, 1.0, s22 -; SI-NEXT: v_mul_f32_e64 v18, 1.0, s25 -; SI-NEXT: v_mul_f32_e64 v19, 1.0, s24 -; SI-NEXT: v_mul_f32_e64 v10, 1.0, s27 -; SI-NEXT: v_mul_f32_e64 v8, 1.0, s26 -; SI-NEXT: v_mul_f32_e64 v23, 1.0, s29 -; SI-NEXT: v_mul_f32_e64 v25, 1.0, s28 +; SI-NEXT: v_mul_f32_e32 v40, 1.0, v41 +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt vmcnt(6) expcnt(0) +; SI-NEXT: v_mul_f32_e32 v10, 1.0, v43 +; SI-NEXT: s_waitcnt vmcnt(5) +; SI-NEXT: v_mul_f32_e32 v56, 1.0, v44 +; SI-NEXT: s_waitcnt vmcnt(4) +; SI-NEXT: v_mul_f32_e32 v14, 1.0, v45 +; SI-NEXT: v_mul_f32_e64 v13, 1.0, s17 +; SI-NEXT: v_mul_f32_e64 v15, 1.0, s16 +; SI-NEXT: v_mul_f32_e64 v52, 1.0, s19 +; SI-NEXT: v_mul_f32_e64 v11, 1.0, s18 +; SI-NEXT: v_mul_f32_e64 v30, 1.0, s21 +; SI-NEXT: v_mul_f32_e64 v34, 1.0, s20 +; SI-NEXT: v_mul_f32_e64 v54, 1.0, s23 +; SI-NEXT: v_mul_f32_e64 v16, 1.0, s22 +; SI-NEXT: v_mul_f32_e64 v41, 1.0, s25 +; SI-NEXT: v_mul_f32_e64 v42, 1.0, s24 +; SI-NEXT: v_mul_f32_e64 v45, 1.0, s27 +; SI-NEXT: v_mul_f32_e64 v48, 1.0, s26 +; SI-NEXT: v_mul_f32_e64 v43, 1.0, s29 +; SI-NEXT: v_mul_f32_e64 v44, 1.0, s28 ; SI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr61 : SGPR spill to VGPR lane +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB91_2 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v3 -; SI-NEXT: v_mov_b32_e32 v42, v37 -; SI-NEXT: v_alignbit_b32 v37, v2, v11, 16 -; SI-NEXT: v_alignbit_b32 v11, v44, v4, 16 -; SI-NEXT: v_readfirstlane_b32 s4, v37 -; SI-NEXT: v_readfirstlane_b32 s5, v11 -; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 24 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v14 -; SI-NEXT: v_writelane_b32 v62, s6, 0 -; SI-NEXT: v_alignbit_b32 v2, v2, v15, 16 -; SI-NEXT: v_writelane_b32 v62, s7, 1 -; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[10:11], s[4:5], 8 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s4, v2 -; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v7 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18 -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload -; SI-NEXT: v_alignbit_b32 v14, v52, v6, 16 -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload -; SI-NEXT: v_readfirstlane_b32 s5, v14 -; SI-NEXT: v_alignbit_b32 v2, v2, v19, 16 -; SI-NEXT: s_lshr_b64 s[8:9], s[4:5], 24 -; SI-NEXT: s_lshr_b64 s[12:13], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[16:17], s[4:5], 8 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s4, v2 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v10 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill -; SI-NEXT: v_alignbit_b32 v19, v2, v8, 16 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v23 -; SI-NEXT: v_readfirstlane_b32 s5, v19 -; SI-NEXT: v_alignbit_b32 v2, v2, v25, 16 -; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v56 -; SI-NEXT: s_lshr_b64 s[14:15], s[4:5], 24 -; SI-NEXT: s_lshr_b64 s[18:19], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[22:23], s[4:5], 8 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s4, v2 -; SI-NEXT: v_alignbit_b32 v47, v45, v47, 16 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v32 -; SI-NEXT: v_readfirstlane_b32 s5, v47 -; SI-NEXT: v_alignbit_b32 v2, v2, v1, 16 -; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v58 -; SI-NEXT: s_lshr_b64 s[20:21], s[4:5], 24 -; SI-NEXT: s_lshr_b64 s[24:25], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[28:29], s[4:5], 8 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s4, v2 -; SI-NEXT: v_mov_b32_e32 v4, v58 -; SI-NEXT: v_alignbit_b32 v58, v8, v41, 16 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v59 -; SI-NEXT: v_readfirstlane_b32 s5, v58 -; SI-NEXT: v_alignbit_b32 v2, v2, v61, 16 -; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 24 -; SI-NEXT: s_lshr_b64 s[40:41], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[44:45], s[4:5], 8 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s4, v2 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v5 -; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload -; SI-NEXT: v_alignbit_b32 v2, v2, v60, 16 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v23, v22 -; SI-NEXT: v_mov_b32_e32 v40, v36 -; SI-NEXT: s_mov_b64 vcc, 0 -; SI-NEXT: v_lshrrev_b32_e32 v56, 24, v56 -; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v18 -; SI-NEXT: s_waitcnt vmcnt(8) -; SI-NEXT: v_alignbit_b32 v41, v15, v6, 16 -; SI-NEXT: v_readfirstlane_b32 s5, v41 -; SI-NEXT: s_lshr_b64 s[42:43], s[4:5], 24 -; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[58:59], s[4:5], 8 -; SI-NEXT: v_readfirstlane_b32 s4, v2 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v21 -; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v32 -; SI-NEXT: v_alignbit_b32 v59, v1, v13, 16 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s5, v59 -; SI-NEXT: s_waitcnt vmcnt(3) expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v5 -; SI-NEXT: s_lshr_b64 s[56:57], s[4:5], 24 -; SI-NEXT: s_lshr_b64 s[60:61], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[72:73], s[4:5], 8 -; SI-NEXT: v_alignbit_b32 v61, v1, v17, 16 -; SI-NEXT: v_readfirstlane_b32 s5, v61 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; SI-NEXT: v_lshrrev_b32_e32 v13, 8, v58 -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_alignbit_b32 v2, v2, v21, 16 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s4, v2 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v9 -; SI-NEXT: v_alignbit_b32 v2, v2, v12, 16 -; SI-NEXT: s_lshr_b64 s[62:63], s[4:5], 24 -; SI-NEXT: s_lshr_b64 s[74:75], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[78:79], s[4:5], 8 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s4, v2 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v22 -; SI-NEXT: v_alignbit_b32 v60, v2, v20, 16 -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v24 -; SI-NEXT: v_alignbit_b32 v1, v2, v46, 16 -; SI-NEXT: v_readfirstlane_b32 s5, v60 -; SI-NEXT: s_lshr_b64 s[76:77], s[4:5], 24 -; SI-NEXT: s_lshr_b64 s[88:89], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[92:93], s[4:5], 8 +; SI-NEXT: v_readfirstlane_b32 s4, v13 +; SI-NEXT: s_lshr_b32 s5, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v15 +; SI-NEXT: s_lshr_b64 s[8:9], s[4:5], 16 +; SI-NEXT: v_readfirstlane_b32 s4, v52 +; SI-NEXT: s_lshr_b32 s7, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v30 +; SI-NEXT: s_lshr_b32 s5, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v34 +; SI-NEXT: s_lshr_b64 s[86:87], s[4:5], 16 +; SI-NEXT: v_readfirstlane_b32 s4, v54 +; SI-NEXT: s_lshr_b32 s65, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v41 +; SI-NEXT: s_lshr_b32 s5, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v42 +; SI-NEXT: s_lshr_b64 s[80:81], s[4:5], 16 +; SI-NEXT: v_readfirstlane_b32 s4, v45 +; SI-NEXT: s_lshr_b32 s69, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v43 +; SI-NEXT: s_lshr_b32 s5, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v44 +; SI-NEXT: v_mov_b32_e32 v34, v35 +; SI-NEXT: s_lshr_b64 s[66:67], s[4:5], 16 +; SI-NEXT: v_readfirstlane_b32 s4, v34 +; SI-NEXT: s_lshr_b32 s91, s4, 16 +; SI-NEXT: v_mov_b32_e32 v30, v51 +; SI-NEXT: v_readfirstlane_b32 s4, v47 +; SI-NEXT: v_mov_b32_e32 v51, v46 +; SI-NEXT: s_lshr_b32 s5, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v51 +; SI-NEXT: v_mov_b32_e32 v35, v6 +; SI-NEXT: s_lshr_b64 s[52:53], s[4:5], 16 +; SI-NEXT: v_readfirstlane_b32 s4, v35 +; SI-NEXT: s_lshr_b32 s37, s4, 16 ; SI-NEXT: v_readfirstlane_b32 s4, v1 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v1, v5 -; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v1 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v23 -; SI-NEXT: v_mov_b32_e32 v5, v28 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; SI-NEXT: v_lshrrev_b32_e32 v24, 24, v10 -; SI-NEXT: v_lshrrev_b32_e32 v9, 8, v47 -; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v41 -; SI-NEXT: v_lshrrev_b32_e32 v10, 8, v61 -; SI-NEXT: v_lshrrev_b32_e32 v23, 8, v60 -; SI-NEXT: s_waitcnt vmcnt(4) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v20 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; SI-NEXT: v_alignbit_b32 v25, v2, v26, 16 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v57 -; SI-NEXT: v_readfirstlane_b32 s5, v25 -; SI-NEXT: v_alignbit_b32 v2, v2, v16, 16 -; SI-NEXT: s_lshr_b64 s[90:91], s[4:5], 24 -; SI-NEXT: s_lshr_b64 s[94:95], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[34:35], s[4:5], 8 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s4, v2 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v28 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill -; SI-NEXT: v_alignbit_b32 v22, v2, v30, 16 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v31 -; SI-NEXT: v_readfirstlane_b32 s5, v22 -; SI-NEXT: v_alignbit_b32 v2, v2, v27, 16 -; SI-NEXT: s_lshr_b64 s[30:31], s[4:5], 24 -; SI-NEXT: s_lshr_b64 s[36:37], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[38:39], s[4:5], 8 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s4, v2 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v29 -; SI-NEXT: v_alignbit_b32 v17, v2, v36, 16 -; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v35 -; SI-NEXT: v_readfirstlane_b32 s5, v17 -; SI-NEXT: v_alignbit_b32 v2, v2, v34, 16 -; SI-NEXT: s_lshr_b64 s[48:49], s[4:5], 24 +; SI-NEXT: s_lshr_b32 s5, s4, 16 +; SI-NEXT: v_mov_b32_e32 v41, v5 +; SI-NEXT: v_readfirstlane_b32 s4, v5 +; SI-NEXT: v_mov_b32_e32 v5, v39 +; SI-NEXT: s_lshr_b64 s[30:31], s[4:5], 16 +; SI-NEXT: v_readfirstlane_b32 s4, v5 +; SI-NEXT: s_lshr_b32 s89, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v9 +; SI-NEXT: s_lshr_b32 s5, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v31 ; SI-NEXT: s_lshr_b64 s[50:51], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[52:53], s[4:5], 8 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill ; SI-NEXT: v_readfirstlane_b32 s4, v2 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v42 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v20 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v5 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v22 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v29 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v29, v37 -; SI-NEXT: v_mov_b32_e32 v37, v42 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v17 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v37 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v33 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; SI-NEXT: v_lshrrev_b32_e32 v34, 24, v4 +; SI-NEXT: s_lshr_b32 s57, s4, 16 +; SI-NEXT: v_mov_b32_e32 v42, v32 +; SI-NEXT: v_readfirstlane_b32 s4, v32 +; SI-NEXT: v_mov_b32_e32 v32, v4 +; SI-NEXT: s_lshr_b32 s5, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v32 +; SI-NEXT: v_mov_b32_e32 v6, v55 +; SI-NEXT: s_lshr_b64 s[92:93], s[4:5], 16 +; SI-NEXT: v_readfirstlane_b32 s4, v6 +; SI-NEXT: s_lshr_b32 s79, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v20 +; SI-NEXT: v_mov_b32_e32 v39, v12 +; SI-NEXT: s_lshr_b32 s5, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v39 +; SI-NEXT: v_mov_b32_e32 v9, v8 +; SI-NEXT: s_waitcnt expcnt(6) +; SI-NEXT: v_mov_b32_e32 v43, v20 +; SI-NEXT: s_lshr_b64 s[76:77], s[4:5], 16 +; SI-NEXT: v_readfirstlane_b32 s4, v9 +; SI-NEXT: v_mov_b32_e32 v20, v21 +; SI-NEXT: v_readfirstlane_b32 s78, v18 +; SI-NEXT: s_lshr_b32 s73, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v20 +; SI-NEXT: v_mov_b32_e32 v18, v22 +; SI-NEXT: s_lshr_b32 s5, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v18 +; SI-NEXT: s_lshr_b64 s[62:63], s[4:5], 16 +; SI-NEXT: v_readfirstlane_b32 s4, v23 +; SI-NEXT: s_lshr_b32 s59, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v28 +; SI-NEXT: v_mov_b32_e32 v21, v25 +; SI-NEXT: s_lshr_b32 s5, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v27 +; SI-NEXT: v_mov_b32_e32 v25, v26 +; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 16 +; SI-NEXT: v_readfirstlane_b32 s4, v25 +; SI-NEXT: v_mov_b32_e32 v12, v29 +; SI-NEXT: s_lshr_b32 s45, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v12 +; SI-NEXT: s_waitcnt expcnt(5) +; SI-NEXT: v_mov_b32_e32 v44, v1 +; SI-NEXT: s_lshr_b32 s5, s4, 16 +; SI-NEXT: v_mov_b32_e32 v1, v52 +; SI-NEXT: s_waitcnt expcnt(4) +; SI-NEXT: v_mov_b32_e32 v52, v17 +; SI-NEXT: v_readfirstlane_b32 s4, v17 +; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v29, v33 +; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v22, v24 +; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; SI-NEXT: s_lshr_b64 s[40:41], s[4:5], 16 +; SI-NEXT: v_readfirstlane_b32 s4, v29 +; SI-NEXT: s_lshr_b32 s29, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s6, v11 +; SI-NEXT: v_readfirstlane_b32 s12, v40 +; SI-NEXT: s_lshr_b64 s[96:97], s[6:7], 16 +; SI-NEXT: s_mov_b32 s9, s96 +; SI-NEXT: v_readfirstlane_b32 s88, v60 +; SI-NEXT: s_lshr_b64 s[82:83], s[88:89], 16 +; SI-NEXT: v_readfirstlane_b32 s64, v16 +; SI-NEXT: s_lshr_b64 s[84:85], s[64:65], 16 +; SI-NEXT: s_mov_b32 s87, s84 +; SI-NEXT: v_readfirstlane_b32 s68, v48 +; SI-NEXT: s_lshr_b64 s[70:71], s[68:69], 16 +; SI-NEXT: s_mov_b32 s81, s70 +; SI-NEXT: v_readfirstlane_b32 s90, v30 +; SI-NEXT: s_lshr_b64 s[38:39], s[90:91], 16 +; SI-NEXT: s_mov_b32 s67, s38 +; SI-NEXT: v_readfirstlane_b32 s36, v3 +; SI-NEXT: s_lshr_b64 s[98:99], s[36:37], 16 +; SI-NEXT: s_mov_b32 s53, s98 +; SI-NEXT: s_mov_b32 s31, s82 +; SI-NEXT: v_readfirstlane_b32 s56, v7 +; SI-NEXT: s_lshr_b64 s[94:95], s[56:57], 16 +; SI-NEXT: s_mov_b32 s51, s94 +; SI-NEXT: s_lshr_b64 s[74:75], s[78:79], 16 +; SI-NEXT: s_mov_b32 s93, s74 +; SI-NEXT: v_readfirstlane_b32 s72, v19 +; SI-NEXT: s_lshr_b64 s[60:61], s[72:73], 16 +; SI-NEXT: s_mov_b32 s77, s60 +; SI-NEXT: v_readfirstlane_b32 s58, v21 +; SI-NEXT: s_lshr_b64 s[54:55], s[58:59], 16 +; SI-NEXT: s_mov_b32 s63, s54 +; SI-NEXT: v_readfirstlane_b32 s44, v22 +; SI-NEXT: s_lshr_b64 s[42:43], s[44:45], 16 +; SI-NEXT: s_mov_b32 s47, s42 +; SI-NEXT: v_mov_b32_e32 v26, v37 +; SI-NEXT: v_readfirstlane_b32 s28, v26 +; SI-NEXT: s_lshr_b64 s[26:27], s[28:29], 16 +; SI-NEXT: s_mov_b32 s41, s26 +; SI-NEXT: v_readfirstlane_b32 s22, v36 +; SI-NEXT: v_readfirstlane_b32 s18, v49 +; SI-NEXT: v_lshrrev_b32_e32 v48, 24, v1 +; SI-NEXT: v_mov_b32_e32 v1, v56 +; SI-NEXT: v_mov_b32_e32 v3, v54 +; SI-NEXT: v_lshrrev_b32_e32 v37, 24, v6 +; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v50 +; SI-NEXT: v_lshrrev_b32_e32 v8, 24, v38 +; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v1 +; SI-NEXT: s_waitcnt expcnt(3) +; SI-NEXT: v_mov_b32_e32 v54, v59 +; SI-NEXT: s_lshr_b32 s78, s96, 8 +; SI-NEXT: s_lshr_b32 s61, s84, 8 +; SI-NEXT: s_lshr_b32 s72, s70, 8 +; SI-NEXT: s_lshr_b32 s75, s38, 8 +; SI-NEXT: s_lshr_b32 s58, s98, 8 +; SI-NEXT: s_lshr_b32 s43, s82, 8 +; SI-NEXT: s_lshr_b32 s44, s94, 8 +; SI-NEXT: s_mov_b32 s64, s74 +; SI-NEXT: s_lshr_b32 s27, s74, 8 +; SI-NEXT: s_mov_b32 s90, s60 +; SI-NEXT: s_lshr_b32 s28, s60, 8 +; SI-NEXT: s_lshr_b32 s74, s54, 8 +; SI-NEXT: s_mov_b32 s68, s42 +; SI-NEXT: s_mov_b32 s56, s26 ; SI-NEXT: v_lshrrev_b32_e32 v16, 24, v3 -; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v11 -; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v7 -; SI-NEXT: v_lshrrev_b32_e32 v7, 8, v14 -; SI-NEXT: v_lshrrev_b32_e32 v27, 8, v19 -; SI-NEXT: v_lshrrev_b32_e32 v4, 8, v59 -; SI-NEXT: v_lshrrev_b32_e32 v35, 24, v43 -; SI-NEXT: v_mov_b32_e32 v31, v20 -; SI-NEXT: v_mov_b32_e32 v20, v34 -; SI-NEXT: s_waitcnt vmcnt(10) -; SI-NEXT: v_alignbit_b32 v30, v2, v36, 16 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v48 -; SI-NEXT: v_alignbit_b32 v2, v2, v39, 16 -; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload -; SI-NEXT: v_readfirstlane_b32 s5, v30 -; SI-NEXT: s_lshr_b64 s[54:55], s[4:5], 24 -; SI-NEXT: s_lshr_b64 s[64:65], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[68:69], s[4:5], 8 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s4, v2 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v33 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v28, v36 -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_alignbit_b32 v57, v2, v39, 16 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v51 -; SI-NEXT: v_readfirstlane_b32 s5, v57 -; SI-NEXT: v_alignbit_b32 v2, v2, v50, 16 -; SI-NEXT: s_lshr_b64 s[66:67], s[4:5], 24 -; SI-NEXT: s_lshr_b64 s[70:71], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[82:83], s[4:5], 8 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s4, v2 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v49 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; SI-NEXT: v_alignbit_b32 v46, v2, v38, 16 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v55 -; SI-NEXT: v_readfirstlane_b32 s5, v46 -; SI-NEXT: v_alignbit_b32 v2, v2, v54, 16 -; SI-NEXT: s_lshr_b64 s[80:81], s[4:5], 24 -; SI-NEXT: s_lshr_b64 s[84:85], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[96:97], s[4:5], 8 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s4, v2 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v43 -; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v57 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; SI-NEXT: v_alignbit_b32 v38, v2, v53, 16 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 24, v18 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v49 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mov_b32_e32 v2, v32 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v46 -; SI-NEXT: v_readfirstlane_b32 s5, v38 -; SI-NEXT: v_lshrrev_b32_e32 v2, 24, v2 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v38 -; SI-NEXT: s_lshr_b64 s[86:87], s[4:5], 24 -; SI-NEXT: s_lshr_b64 s[98:99], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 8 -; SI-NEXT: v_mov_b32_e32 v32, v8 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; SI-NEXT: v_lshrrev_b32_e32 v18, 8, v25 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v30 -; SI-NEXT: v_mov_b32_e32 v55, v49 -; SI-NEXT: v_mov_b32_e32 v49, v15 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v8, v6 +; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v45 +; SI-NEXT: v_lshrrev_b32_e32 v13, 24, v34 +; SI-NEXT: v_lshrrev_b32_e32 v11, 24, v35 +; SI-NEXT: v_lshrrev_b32_e32 v47, 24, v5 +; SI-NEXT: v_lshrrev_b32_e32 v3, 24, v2 +; SI-NEXT: v_lshrrev_b32_e32 v55, 24, v9 +; SI-NEXT: v_lshrrev_b32_e32 v4, 24, v25 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt vmcnt(5) +; SI-NEXT: v_readfirstlane_b32 s4, v17 +; SI-NEXT: s_lshr_b32 s5, s4, 16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt vmcnt(4) +; SI-NEXT: v_readfirstlane_b32 s4, v33 +; SI-NEXT: s_lshr_b64 s[24:25], s[4:5], 16 +; SI-NEXT: v_readfirstlane_b32 s4, v57 +; SI-NEXT: s_lshr_b32 s23, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v58 +; SI-NEXT: s_lshr_b32 s5, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v59 +; SI-NEXT: s_lshr_b64 s[16:17], s[4:5], 16 +; SI-NEXT: v_readfirstlane_b32 s4, v50 +; SI-NEXT: s_lshr_b32 s19, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v53 +; SI-NEXT: s_lshr_b32 s5, s4, 16 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: v_readfirstlane_b32 s4, v24 +; SI-NEXT: s_lshr_b64 s[10:11], s[4:5], 16 +; SI-NEXT: v_readfirstlane_b32 s4, v38 +; SI-NEXT: s_lshr_b32 s13, s4, 16 +; SI-NEXT: s_mov_b32 s5, s13 +; SI-NEXT: v_writelane_b32 v61, s4, 26 +; SI-NEXT: v_writelane_b32 v61, s5, 27 +; SI-NEXT: v_readfirstlane_b32 s4, v46 +; SI-NEXT: s_lshr_b32 s5, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v10 +; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16 +; SI-NEXT: v_readfirstlane_b32 s5, v56 +; SI-NEXT: s_lshr_b64 s[20:21], s[12:13], 16 +; SI-NEXT: s_lshr_b32 s13, s5, 16 +; SI-NEXT: v_readfirstlane_b32 s12, v14 +; SI-NEXT: s_lshr_b64 vcc, s[12:13], 16 +; SI-NEXT: s_mov_b32 s5, vcc_lo +; SI-NEXT: s_mov_b32 s88, vcc_lo +; SI-NEXT: s_lshr_b32 s6, vcc_lo, 8 +; SI-NEXT: s_lshr_b64 vcc, s[8:9], 24 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 4 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 5 +; SI-NEXT: s_lshr_b64 vcc, s[8:9], 16 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 2 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 3 +; SI-NEXT: s_lshr_b64 vcc, s[8:9], 8 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 0 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 1 +; SI-NEXT: s_lshr_b64 vcc, s[86:87], 24 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 10 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 11 +; SI-NEXT: s_lshr_b64 vcc, s[86:87], 16 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 8 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 9 +; SI-NEXT: s_lshr_b64 vcc, s[86:87], 8 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 6 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 7 +; SI-NEXT: s_lshr_b64 vcc, s[80:81], 24 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 16 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 17 +; SI-NEXT: s_lshr_b64 vcc, s[80:81], 16 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 14 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 15 +; SI-NEXT: s_lshr_b64 vcc, s[80:81], 8 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 12 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 13 +; SI-NEXT: s_lshr_b64 vcc, s[66:67], 24 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 22 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 23 +; SI-NEXT: s_lshr_b64 vcc, s[66:67], 16 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 20 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 21 +; SI-NEXT: s_lshr_b64 vcc, s[66:67], 8 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 18 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 19 +; SI-NEXT: s_lshr_b64 vcc, s[52:53], 24 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 28 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 29 +; SI-NEXT: s_lshr_b64 vcc, s[52:53], 16 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 26 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 27 +; SI-NEXT: s_lshr_b64 vcc, s[52:53], 8 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 24 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 25 +; SI-NEXT: s_lshr_b64 vcc, s[30:31], 24 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 34 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 35 +; SI-NEXT: s_lshr_b64 vcc, s[30:31], 16 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 32 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 33 +; SI-NEXT: s_lshr_b64 vcc, s[30:31], 8 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 30 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 31 +; SI-NEXT: s_lshr_b64 vcc, s[50:51], 24 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 40 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 41 +; SI-NEXT: s_lshr_b64 vcc, s[50:51], 16 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 38 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 39 +; SI-NEXT: s_lshr_b64 vcc, s[50:51], 8 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 36 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 37 +; SI-NEXT: s_lshr_b64 vcc, s[92:93], 24 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 46 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 47 +; SI-NEXT: s_lshr_b64 vcc, s[92:93], 16 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 44 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 45 +; SI-NEXT: s_lshr_b64 vcc, s[92:93], 8 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 42 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 43 +; SI-NEXT: s_lshr_b64 vcc, s[76:77], 24 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 52 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 53 +; SI-NEXT: s_lshr_b64 vcc, s[76:77], 16 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 50 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 51 +; SI-NEXT: s_lshr_b64 vcc, s[76:77], 8 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 48 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 49 +; SI-NEXT: s_lshr_b64 vcc, s[62:63], 24 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 58 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 59 +; SI-NEXT: s_lshr_b64 vcc, s[62:63], 16 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 56 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 57 +; SI-NEXT: s_lshr_b64 vcc, s[62:63], 8 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 54 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 55 +; SI-NEXT: s_lshr_b64 vcc, s[46:47], 24 +; SI-NEXT: v_writelane_b32 v61, vcc_lo, 0 +; SI-NEXT: v_writelane_b32 v61, vcc_hi, 1 +; SI-NEXT: s_lshr_b64 vcc, s[46:47], 16 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 62 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 63 +; SI-NEXT: s_lshr_b64 vcc, s[46:47], 8 +; SI-NEXT: v_writelane_b32 v62, vcc_lo, 60 +; SI-NEXT: v_writelane_b32 v62, vcc_hi, 61 +; SI-NEXT: s_lshr_b64 vcc, s[40:41], 24 +; SI-NEXT: v_writelane_b32 v61, vcc_lo, 6 +; SI-NEXT: v_writelane_b32 v61, vcc_hi, 7 +; SI-NEXT: s_lshr_b64 vcc, s[40:41], 16 +; SI-NEXT: v_writelane_b32 v61, vcc_lo, 4 +; SI-NEXT: s_lshr_b64 s[34:35], s[22:23], 16 +; SI-NEXT: v_writelane_b32 v61, vcc_hi, 5 +; SI-NEXT: s_lshr_b64 vcc, s[40:41], 8 +; SI-NEXT: s_mov_b32 s25, s34 +; SI-NEXT: v_writelane_b32 v61, vcc_lo, 2 +; SI-NEXT: v_writelane_b32 v61, vcc_hi, 3 +; SI-NEXT: s_lshr_b64 vcc, s[24:25], 24 +; SI-NEXT: v_writelane_b32 v61, vcc_lo, 12 +; SI-NEXT: v_writelane_b32 v61, vcc_hi, 13 +; SI-NEXT: s_lshr_b64 vcc, s[24:25], 16 +; SI-NEXT: v_writelane_b32 v61, vcc_lo, 10 +; SI-NEXT: s_lshr_b64 s[14:15], s[18:19], 16 +; SI-NEXT: v_writelane_b32 v61, vcc_hi, 11 +; SI-NEXT: s_lshr_b64 vcc, s[24:25], 8 +; SI-NEXT: s_mov_b32 s17, s14 +; SI-NEXT: v_writelane_b32 v61, vcc_lo, 8 +; SI-NEXT: v_writelane_b32 v61, vcc_hi, 9 +; SI-NEXT: s_lshr_b64 vcc, s[16:17], 24 +; SI-NEXT: v_writelane_b32 v61, vcc_lo, 18 +; SI-NEXT: v_writelane_b32 v61, vcc_hi, 19 +; SI-NEXT: s_lshr_b64 vcc, s[16:17], 16 +; SI-NEXT: v_writelane_b32 v61, vcc_lo, 16 +; SI-NEXT: v_writelane_b32 v61, vcc_hi, 17 +; SI-NEXT: s_lshr_b64 vcc, s[16:17], 8 +; SI-NEXT: s_mov_b32 s11, s20 +; SI-NEXT: v_writelane_b32 v61, vcc_lo, 14 +; SI-NEXT: v_writelane_b32 v61, vcc_hi, 15 +; SI-NEXT: s_lshr_b64 vcc, s[10:11], 24 +; SI-NEXT: v_writelane_b32 v61, vcc_lo, 24 +; SI-NEXT: v_writelane_b32 v61, vcc_hi, 25 +; SI-NEXT: s_lshr_b64 vcc, s[10:11], 16 +; SI-NEXT: v_writelane_b32 v61, vcc_lo, 22 +; SI-NEXT: v_writelane_b32 v61, vcc_hi, 23 +; SI-NEXT: s_lshr_b64 vcc, s[10:11], 8 +; SI-NEXT: v_writelane_b32 v61, vcc_lo, 20 +; SI-NEXT: v_writelane_b32 v61, vcc_hi, 21 +; SI-NEXT: s_lshr_b64 vcc, s[4:5], 24 +; SI-NEXT: v_writelane_b32 v61, vcc_lo, 32 +; SI-NEXT: v_writelane_b32 v61, vcc_hi, 33 +; SI-NEXT: s_lshr_b64 vcc, s[4:5], 16 +; SI-NEXT: v_writelane_b32 v61, vcc_lo, 30 +; SI-NEXT: v_writelane_b32 v61, vcc_hi, 31 +; SI-NEXT: s_lshr_b64 vcc, s[4:5], 8 +; SI-NEXT: v_writelane_b32 v61, vcc_lo, 28 +; SI-NEXT: s_waitcnt expcnt(5) +; SI-NEXT: v_lshrrev_b32_e32 v10, 24, v23 +; SI-NEXT: s_lshr_b32 s22, s42, 8 +; SI-NEXT: s_lshr_b32 s21, s26, 8 +; SI-NEXT: s_lshr_b32 s18, s34, 8 +; SI-NEXT: s_mov_b32 s36, s14 +; SI-NEXT: s_lshr_b32 s15, s14, 8 +; SI-NEXT: s_mov_b32 s14, s20 +; SI-NEXT: s_lshr_b32 s12, s20, 8 +; SI-NEXT: v_writelane_b32 v61, vcc_hi, 29 +; SI-NEXT: s_mov_b64 vcc, 0 +; SI-NEXT: s_waitcnt expcnt(3) +; SI-NEXT: v_lshrrev_b32_e32 v14, 24, v29 +; SI-NEXT: v_lshrrev_b32_e32 v56, 24, v57 +; SI-NEXT: v_mov_b32_e32 v59, v30 +; SI-NEXT: v_mov_b32_e32 v31, v51 +; SI-NEXT: v_mov_b32_e32 v60, v34 +; SI-NEXT: v_mov_b32_e32 v30, v39 +; SI-NEXT: v_mov_b32_e32 v19, v5 +; SI-NEXT: v_mov_b32_e32 v39, v21 +; SI-NEXT: v_mov_b32_e32 v21, v20 +; SI-NEXT: v_mov_b32_e32 v34, v18 +; SI-NEXT: v_mov_b32_e32 v18, v37 +; SI-NEXT: s_waitcnt expcnt(2) +; SI-NEXT: v_mov_b32_e32 v7, v26 +; SI-NEXT: v_mov_b32_e32 v20, v2 +; SI-NEXT: v_mov_b32_e32 v37, v17 +; SI-NEXT: v_mov_b32_e32 v51, v33 +; SI-NEXT: v_mov_b32_e32 v17, v9 +; SI-NEXT: v_mov_b32_e32 v9, v10 +; SI-NEXT: v_mov_b32_e32 v26, v25 ; SI-NEXT: s_branch .LBB91_3 ; SI-NEXT: .LBB91_2: -; SI-NEXT: ; implicit-def: $vgpr8 -; SI-NEXT: ; kill: killed $vgpr8 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 ; SI-NEXT: ; implicit-def: $sgpr4 -; SI-NEXT: s_waitcnt expcnt(5) -; SI-NEXT: v_mov_b32_e32 v55, v49 -; SI-NEXT: ; implicit-def: $vgpr8 -; SI-NEXT: ; kill: killed $vgpr8 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 +; SI-NEXT: s_waitcnt expcnt(3) +; SI-NEXT: v_mov_b32_e32 v54, v59 ; SI-NEXT: v_writelane_b32 v62, s4, 0 -; SI-NEXT: ; implicit-def: $vgpr8 -; SI-NEXT: ; kill: killed $vgpr8 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: v_mov_b32_e32 v40, v36 -; SI-NEXT: ; implicit-def: $vgpr8 -; SI-NEXT: ; kill: killed $vgpr8 +; SI-NEXT: v_writelane_b32 v62, s5, 1 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_mov_b32_e32 v59, v51 +; SI-NEXT: v_writelane_b32 v62, s4, 2 +; SI-NEXT: v_writelane_b32 v62, s5, 3 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_mov_b32_e32 v31, v46 +; SI-NEXT: v_writelane_b32 v62, s4, 4 +; SI-NEXT: v_writelane_b32 v62, s5, 5 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_mov_b32_e32 v34, v22 +; SI-NEXT: v_writelane_b32 v62, s4, 6 +; SI-NEXT: v_writelane_b32 v62, s5, 7 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_mov_b32_e32 v22, v24 +; SI-NEXT: v_writelane_b32 v62, s4, 8 +; SI-NEXT: v_writelane_b32 v62, s5, 9 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_mov_b32_e32 v7, v37 +; SI-NEXT: v_writelane_b32 v62, s4, 10 +; SI-NEXT: v_writelane_b32 v62, s5, 11 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; SI-NEXT: v_writelane_b32 v62, s4, 12 +; SI-NEXT: v_writelane_b32 v62, s5, 13 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; SI-NEXT: v_writelane_b32 v62, s4, 14 +; SI-NEXT: v_writelane_b32 v62, s5, 15 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr21 +; SI-NEXT: ; implicit-def: $sgpr20 +; SI-NEXT: ; implicit-def: $sgpr89 +; SI-NEXT: ; implicit-def: $sgpr88 +; SI-NEXT: v_mov_b32_e32 v44, v1 +; SI-NEXT: v_writelane_b32 v62, s4, 16 +; SI-NEXT: v_writelane_b32 v62, s5, 17 +; SI-NEXT: ; implicit-def: $sgpr4 ; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 +; SI-NEXT: v_mov_b32_e32 v52, v17 +; SI-NEXT: v_writelane_b32 v62, s4, 18 +; SI-NEXT: v_writelane_b32 v62, s5, 19 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_mov_b32_e32 v43, v20 +; SI-NEXT: v_writelane_b32 v62, s4, 20 +; SI-NEXT: v_writelane_b32 v62, s5, 21 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_mov_b32_e32 v42, v32 +; SI-NEXT: v_writelane_b32 v62, s4, 22 +; SI-NEXT: v_writelane_b32 v62, s5, 23 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_mov_b32_e32 v41, v5 +; SI-NEXT: v_writelane_b32 v62, s4, 24 +; SI-NEXT: v_writelane_b32 v62, s5, 25 +; SI-NEXT: ; implicit-def: $sgpr4 ; SI-NEXT: s_mov_b64 vcc, -1 -; SI-NEXT: ; implicit-def: $vgpr8 -; SI-NEXT: ; kill: killed $vgpr8 -; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: v_writelane_b32 v62, s4, 26 +; SI-NEXT: v_writelane_b32 v62, s5, 27 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_mov_b32_e32 v60, v35 +; SI-NEXT: v_writelane_b32 v62, s4, 28 +; SI-NEXT: v_writelane_b32 v62, s5, 29 +; SI-NEXT: ; implicit-def: $sgpr4 ; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: v_writelane_b32 v62, s5, 1 -; SI-NEXT: ; implicit-def: $vgpr8 -; SI-NEXT: ; kill: killed $vgpr8 +; SI-NEXT: v_mov_b32_e32 v35, v6 +; SI-NEXT: v_writelane_b32 v62, s4, 30 +; SI-NEXT: v_writelane_b32 v62, s5, 31 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_mov_b32_e32 v32, v4 +; SI-NEXT: v_writelane_b32 v62, s4, 32 +; SI-NEXT: v_writelane_b32 v62, s5, 33 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_mov_b32_e32 v30, v12 +; SI-NEXT: v_writelane_b32 v62, s4, 34 +; SI-NEXT: v_writelane_b32 v62, s5, 35 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_mov_b32_e32 v19, v39 +; SI-NEXT: v_writelane_b32 v62, s4, 36 +; SI-NEXT: v_writelane_b32 v62, s5, 37 +; SI-NEXT: ; implicit-def: $sgpr4 ; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr29 -; SI-NEXT: ; implicit-def: $sgpr10 -; SI-NEXT: ; implicit-def: $sgpr6 +; SI-NEXT: v_mov_b32_e32 v39, v25 +; SI-NEXT: v_writelane_b32 v62, s4, 38 +; SI-NEXT: v_writelane_b32 v62, s5, 39 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_mov_b32_e32 v12, v29 +; SI-NEXT: v_writelane_b32 v62, s4, 40 +; SI-NEXT: v_writelane_b32 v62, s5, 41 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_mov_b32_e32 v20, v2 +; SI-NEXT: v_writelane_b32 v62, s4, 42 +; SI-NEXT: v_writelane_b32 v62, s5, 43 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_mov_b32_e32 v6, v55 +; SI-NEXT: v_writelane_b32 v62, s4, 44 +; SI-NEXT: v_writelane_b32 v62, s5, 45 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_mov_b32_e32 v17, v8 +; SI-NEXT: v_writelane_b32 v62, s4, 46 +; SI-NEXT: v_writelane_b32 v62, s5, 47 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_mov_b32_e32 v29, v33 +; SI-NEXT: v_writelane_b32 v62, s4, 48 +; SI-NEXT: v_writelane_b32 v62, s5, 49 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: ; implicit-def: $sgpr8 +; SI-NEXT: ; implicit-def: $sgpr96 +; SI-NEXT: ; implicit-def: $sgpr78 +; SI-NEXT: ; implicit-def: $sgpr7 +; SI-NEXT: ; implicit-def: $vgpr48 +; SI-NEXT: ; implicit-def: $sgpr86 +; SI-NEXT: ; implicit-def: $sgpr84 +; SI-NEXT: ; implicit-def: $sgpr61 +; SI-NEXT: ; implicit-def: $sgpr65 +; SI-NEXT: ; implicit-def: $vgpr16 +; SI-NEXT: ; implicit-def: $sgpr80 +; SI-NEXT: ; implicit-def: $sgpr70 +; SI-NEXT: ; implicit-def: $sgpr72 +; SI-NEXT: ; implicit-def: $sgpr69 +; SI-NEXT: ; implicit-def: $vgpr15 +; SI-NEXT: ; implicit-def: $sgpr66 +; SI-NEXT: ; implicit-def: $sgpr38 +; SI-NEXT: ; implicit-def: $sgpr75 +; SI-NEXT: ; implicit-def: $sgpr91 +; SI-NEXT: ; implicit-def: $vgpr13 +; SI-NEXT: ; implicit-def: $sgpr52 +; SI-NEXT: ; implicit-def: $sgpr98 +; SI-NEXT: ; implicit-def: $sgpr58 +; SI-NEXT: ; implicit-def: $sgpr37 ; SI-NEXT: ; implicit-def: $vgpr11 +; SI-NEXT: ; implicit-def: $sgpr30 +; SI-NEXT: ; implicit-def: $sgpr82 +; SI-NEXT: ; implicit-def: $sgpr43 +; SI-NEXT: ; implicit-def: $vgpr47 +; SI-NEXT: ; implicit-def: $sgpr44 ; SI-NEXT: ; implicit-def: $vgpr3 -; SI-NEXT: ; implicit-def: $vgpr44 -; SI-NEXT: ; implicit-def: $vgpr16 -; SI-NEXT: ; implicit-def: $sgpr16 -; SI-NEXT: ; implicit-def: $sgpr12 -; SI-NEXT: ; implicit-def: $sgpr8 -; SI-NEXT: ; implicit-def: $vgpr14 -; SI-NEXT: ; implicit-def: $vgpr7 -; SI-NEXT: ; implicit-def: $vgpr52 -; SI-NEXT: ; implicit-def: $vgpr26 -; SI-NEXT: ; implicit-def: $sgpr22 -; SI-NEXT: ; implicit-def: $sgpr18 -; SI-NEXT: ; implicit-def: $sgpr14 -; SI-NEXT: ; implicit-def: $vgpr19 -; SI-NEXT: ; implicit-def: $vgpr27 -; SI-NEXT: ; implicit-def: $vgpr24 +; SI-NEXT: ; implicit-def: $sgpr27 +; SI-NEXT: ; implicit-def: $vgpr18 ; SI-NEXT: ; implicit-def: $sgpr28 -; SI-NEXT: ; implicit-def: $sgpr24 -; SI-NEXT: ; implicit-def: $sgpr20 -; SI-NEXT: ; implicit-def: $vgpr47 +; SI-NEXT: ; implicit-def: $sgpr74 ; SI-NEXT: ; implicit-def: $vgpr9 -; SI-NEXT: ; implicit-def: $vgpr45 +; SI-NEXT: ; implicit-def: $sgpr22 +; SI-NEXT: ; implicit-def: $vgpr14 +; SI-NEXT: ; implicit-def: $sgpr18 ; SI-NEXT: ; implicit-def: $vgpr56 -; SI-NEXT: ; implicit-def: $sgpr44 -; SI-NEXT: ; implicit-def: $sgpr40 -; SI-NEXT: ; implicit-def: $sgpr26 -; SI-NEXT: ; implicit-def: $vgpr58 -; SI-NEXT: ; implicit-def: $vgpr13 -; SI-NEXT: ; implicit-def: $vgpr32 -; SI-NEXT: ; implicit-def: $vgpr20 -; SI-NEXT: ; implicit-def: $sgpr58 -; SI-NEXT: ; implicit-def: $sgpr46 -; SI-NEXT: ; implicit-def: $sgpr42 -; SI-NEXT: ; implicit-def: $vgpr41 -; SI-NEXT: ; implicit-def: $vgpr12 -; SI-NEXT: ; implicit-def: $vgpr49 -; SI-NEXT: ; implicit-def: $sgpr72 -; SI-NEXT: ; implicit-def: $sgpr60 -; SI-NEXT: ; implicit-def: $sgpr56 -; SI-NEXT: ; implicit-def: $vgpr59 -; SI-NEXT: ; implicit-def: $vgpr4 -; SI-NEXT: ; implicit-def: $sgpr78 -; SI-NEXT: ; implicit-def: $sgpr74 -; SI-NEXT: ; implicit-def: $sgpr62 -; SI-NEXT: ; implicit-def: $vgpr61 -; SI-NEXT: ; implicit-def: $vgpr10 +; SI-NEXT: ; implicit-def: $sgpr15 +; SI-NEXT: ; implicit-def: $sgpr12 +; SI-NEXT: ; implicit-def: $sgpr6 +; SI-NEXT: ; implicit-def: $sgpr50 +; SI-NEXT: ; implicit-def: $sgpr94 +; SI-NEXT: ; implicit-def: $sgpr57 ; SI-NEXT: ; implicit-def: $sgpr92 -; SI-NEXT: ; implicit-def: $sgpr88 +; SI-NEXT: ; implicit-def: $sgpr64 +; SI-NEXT: ; implicit-def: $sgpr79 ; SI-NEXT: ; implicit-def: $sgpr76 -; SI-NEXT: ; implicit-def: $vgpr60 -; SI-NEXT: ; implicit-def: $vgpr23 -; SI-NEXT: ; implicit-def: $sgpr34 -; SI-NEXT: ; implicit-def: $sgpr94 ; SI-NEXT: ; implicit-def: $sgpr90 -; SI-NEXT: ; implicit-def: $vgpr25 -; SI-NEXT: ; implicit-def: $vgpr18 -; SI-NEXT: ; implicit-def: $sgpr38 -; SI-NEXT: ; implicit-def: $sgpr36 -; SI-NEXT: ; implicit-def: $sgpr30 -; SI-NEXT: ; implicit-def: $vgpr22 -; SI-NEXT: ; implicit-def: $sgpr52 -; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $vgpr17 -; SI-NEXT: ; implicit-def: $sgpr68 -; SI-NEXT: ; implicit-def: $sgpr64 +; SI-NEXT: ; implicit-def: $sgpr73 +; SI-NEXT: ; implicit-def: $sgpr62 ; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; implicit-def: $sgpr82 -; SI-NEXT: ; implicit-def: $sgpr70 -; SI-NEXT: ; implicit-def: $sgpr66 -; SI-NEXT: ; implicit-def: $sgpr96 -; SI-NEXT: ; implicit-def: $sgpr84 -; SI-NEXT: ; implicit-def: $sgpr80 -; SI-NEXT: ; implicit-def: $sgpr4 -; SI-NEXT: ; implicit-def: $sgpr98 -; SI-NEXT: ; implicit-def: $sgpr86 -; SI-NEXT: ; implicit-def: $vgpr30 -; SI-NEXT: ; implicit-def: $vgpr57 -; SI-NEXT: ; implicit-def: $vgpr46 -; SI-NEXT: ; implicit-def: $vgpr38 -; SI-NEXT: ; implicit-def: $vgpr36 -; SI-NEXT: ; kill: killed $vgpr36 -; SI-NEXT: ; implicit-def: $vgpr35 -; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr2 +; SI-NEXT: ; implicit-def: $sgpr59 +; SI-NEXT: ; implicit-def: $sgpr46 +; SI-NEXT: ; implicit-def: $sgpr68 +; SI-NEXT: ; implicit-def: $sgpr45 +; SI-NEXT: ; implicit-def: $sgpr40 +; SI-NEXT: ; implicit-def: $sgpr56 +; SI-NEXT: ; implicit-def: $sgpr29 +; SI-NEXT: ; implicit-def: $sgpr24 +; SI-NEXT: ; implicit-def: $sgpr34 +; SI-NEXT: ; implicit-def: $sgpr23 +; SI-NEXT: ; implicit-def: $sgpr16 +; SI-NEXT: ; implicit-def: $sgpr36 +; SI-NEXT: ; implicit-def: $sgpr19 +; SI-NEXT: ; implicit-def: $sgpr10 +; SI-NEXT: ; implicit-def: $sgpr14 +; SI-NEXT: ; implicit-def: $sgpr13 +; SI-NEXT: ; implicit-def: $vgpr4 ; SI-NEXT: ; kill: killed $vgpr1 ; SI-NEXT: ; implicit-def: $vgpr1 ; SI-NEXT: ; kill: killed $vgpr1 +; SI-NEXT: ; implicit-def: $vgpr55 +; SI-NEXT: v_writelane_b32 v62, s4, 50 +; SI-NEXT: v_writelane_b32 v62, s5, 51 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v62, s4, 52 +; SI-NEXT: v_writelane_b32 v62, s5, 53 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v62, s4, 54 +; SI-NEXT: v_writelane_b32 v62, s5, 55 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v62, s4, 56 +; SI-NEXT: v_writelane_b32 v62, s5, 57 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v62, s4, 58 +; SI-NEXT: v_writelane_b32 v62, s5, 59 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v62, s4, 60 +; SI-NEXT: v_writelane_b32 v62, s5, 61 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v62, s4, 62 +; SI-NEXT: v_writelane_b32 v62, s5, 63 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s4, 0 +; SI-NEXT: v_writelane_b32 v61, s5, 1 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s4, 2 +; SI-NEXT: v_writelane_b32 v61, s5, 3 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s4, 4 +; SI-NEXT: v_writelane_b32 v61, s5, 5 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s4, 6 +; SI-NEXT: v_writelane_b32 v61, s5, 7 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s4, 8 +; SI-NEXT: v_writelane_b32 v61, s5, 9 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s4, 10 +; SI-NEXT: v_writelane_b32 v61, s5, 11 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s4, 12 +; SI-NEXT: v_writelane_b32 v61, s5, 13 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s4, 14 +; SI-NEXT: v_writelane_b32 v61, s5, 15 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s4, 16 +; SI-NEXT: v_writelane_b32 v61, s5, 17 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s4, 18 +; SI-NEXT: v_writelane_b32 v61, s5, 19 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s4, 20 +; SI-NEXT: v_writelane_b32 v61, s5, 21 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s4, 22 +; SI-NEXT: v_writelane_b32 v61, s5, 23 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s4, 24 +; SI-NEXT: v_writelane_b32 v61, s5, 25 +; SI-NEXT: ; implicit-def: $sgpr5 +; SI-NEXT: v_writelane_b32 v61, s4, 26 +; SI-NEXT: v_writelane_b32 v61, s5, 27 +; SI-NEXT: v_writelane_b32 v61, s20, 28 +; SI-NEXT: v_writelane_b32 v61, s21, 29 +; SI-NEXT: ; implicit-def: $sgpr20 +; SI-NEXT: ; implicit-def: $sgpr4 +; SI-NEXT: v_writelane_b32 v61, s20, 30 +; SI-NEXT: v_writelane_b32 v61, s21, 31 +; SI-NEXT: v_writelane_b32 v61, s88, 32 +; SI-NEXT: v_writelane_b32 v61, s89, 33 +; SI-NEXT: ; implicit-def: $sgpr88 ; SI-NEXT: .LBB91_3: ; %Flow -; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload ; SI-NEXT: s_andn2_b64 vcc, exec, vcc ; SI-NEXT: s_cbranch_vccnz .LBB91_5 ; SI-NEXT: ; %bb.4: ; %cmp.true -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v43 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v46 +; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 -; SI-NEXT: v_alignbit_b32 v7, v3, v2, 16 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload -; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s4, v7 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v1 -; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 -; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v37 -; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 -; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 -; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; SI-NEXT: v_alignbit_b32 v10, v6, v4, 16 -; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v5 -; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v33 -; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 -; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 -; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s52, v10 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v51 -; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 -; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; SI-NEXT: v_readfirstlane_b32 s4, v11 +; SI-NEXT: s_lshr_b32 s5, s4, 16 +; SI-NEXT: v_readfirstlane_b32 s4, v3 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v2 +; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; SI-NEXT: v_readfirstlane_b32 s12, v3 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v24 +; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v53 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_alignbit_b32 v9, v3, v2, 16 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload -; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s86, v9 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v50 ; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 -; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v38 +; SI-NEXT: v_readfirstlane_b32 s6, v9 +; SI-NEXT: v_readfirstlane_b32 s8, v3 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v40 +; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8 +; SI-NEXT: s_lshr_b32 s9, s6, 16 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_alignbit_b32 v12, v3, v2, 16 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload -; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s80, v12 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; SI-NEXT: v_readfirstlane_b32 s6, v8 +; SI-NEXT: s_lshr_b64 s[10:11], s[8:9], 16 +; SI-NEXT: s_lshr_b32 s9, s6, 16 +; SI-NEXT: v_readfirstlane_b32 s8, v3 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v54 +; SI-NEXT: s_mov_b32 s7, s9 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v58 +; SI-NEXT: v_writelane_b32 v61, s6, 26 +; SI-NEXT: s_lshr_b64 s[20:21], s[8:9], 16 +; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 +; SI-NEXT: v_readfirstlane_b32 s8, v3 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v49 +; SI-NEXT: v_writelane_b32 v61, s7, 27 +; SI-NEXT: v_readfirstlane_b32 s6, v5 +; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v50 +; SI-NEXT: s_lshr_b32 s9, s6, 16 ; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 -; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_alignbit_b32 v13, v3, v2, 16 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s66, v13 -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 -; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v2 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 -; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v2 -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; SI-NEXT: v_alignbit_b32 v38, v4, v3, 16 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v55 -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v15 +; SI-NEXT: v_readfirstlane_b32 s18, v3 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v37 +; SI-NEXT: s_lshr_b64 s[16:17], s[8:9], 16 +; SI-NEXT: v_readfirstlane_b32 s6, v2 +; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; SI-NEXT: s_lshr_b32 s19, s6, 16 +; SI-NEXT: v_readfirstlane_b32 s6, v3 +; SI-NEXT: s_lshr_b32 s9, s6, 16 +; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v12 +; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 +; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v21 +; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 +; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v43 +; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 +; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v44 +; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v35 ; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 +; SI-NEXT: s_lshr_b64 s[26:27], s[18:19], 16 +; SI-NEXT: s_mov_b32 s17, s26 +; SI-NEXT: s_mov_b32 s11, s20 +; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v1 +; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v51 +; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; SI-NEXT: v_readfirstlane_b32 s8, v1 +; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v36 +; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v1 +; SI-NEXT: v_readfirstlane_b32 s22, v3 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v52 +; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v57 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_alignbit_b32 v15, v7, v6, 16 -; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v4 -; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v42 -; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; SI-NEXT: v_alignbit_b32 v46, v6, v3, 16 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v48 -; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v39 -; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 -; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; SI-NEXT: s_lshr_b64 s[24:25], s[8:9], 16 +; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; SI-NEXT: v_readfirstlane_b32 s8, v3 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v7 +; SI-NEXT: v_readfirstlane_b32 s6, v1 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_alignbit_b32 v23, v7, v6, 16 -; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v5 -; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v53 -; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; SI-NEXT: v_alignbit_b32 v57, v6, v3, 16 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v54 -; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v28 -; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 -; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; SI-NEXT: s_lshr_b32 s23, s6, 16 +; SI-NEXT: v_readfirstlane_b32 s6, v5 +; SI-NEXT: v_readfirstlane_b32 s28, v3 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v27 +; SI-NEXT: s_lshr_b32 s9, s6, 16 +; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v29 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_alignbit_b32 v16, v7, v6, 16 -; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v1 -; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; SI-NEXT: v_alignbit_b32 v30, v6, v3, 16 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v21 +; SI-NEXT: s_lshr_b64 s[40:41], s[8:9], 16 +; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 +; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v28 +; SI-NEXT: v_readfirstlane_b32 s8, v3 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v22 +; SI-NEXT: v_readfirstlane_b32 s6, v5 ; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v40 -; SI-NEXT: v_alignbit_b32 v18, v9, v7, 16 -; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v34 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 -; SI-NEXT: v_alignbit_b32 v20, v10, v9, 16 -; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload -; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s38, v15 -; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s90, v16 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload -; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s30, v23 -; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s76, v18 -; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s62, v20 -; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v1 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v5 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v4 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s5, v38 -; SI-NEXT: v_readfirstlane_b32 s87, v46 -; SI-NEXT: v_readfirstlane_b32 s81, v57 -; SI-NEXT: v_readfirstlane_b32 s67, v30 -; SI-NEXT: s_lshr_b64 s[54:55], s[66:67], 24 -; SI-NEXT: s_lshr_b64 s[64:65], s[66:67], 16 -; SI-NEXT: s_lshr_b64 s[68:69], s[66:67], 8 -; SI-NEXT: s_lshr_b64 s[66:67], s[80:81], 24 -; SI-NEXT: s_lshr_b64 s[70:71], s[80:81], 16 -; SI-NEXT: s_lshr_b64 s[82:83], s[80:81], 8 -; SI-NEXT: s_lshr_b64 s[80:81], s[86:87], 24 -; SI-NEXT: s_lshr_b64 s[84:85], s[86:87], 16 -; SI-NEXT: s_lshr_b64 s[96:97], s[86:87], 8 -; SI-NEXT: s_lshr_b64 s[86:87], s[4:5], 24 -; SI-NEXT: s_lshr_b64 s[98:99], s[4:5], 16 -; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 8 -; SI-NEXT: v_lshrrev_b32_e32 v35, 24, v2 -; SI-NEXT: v_lshrrev_b32_e32 v2, 8, v30 -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 -; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6 -; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; SI-NEXT: v_alignbit_b32 v17, v7, v3, 16 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload -; SI-NEXT: v_readfirstlane_b32 s53, v17 -; SI-NEXT: s_lshr_b64 s[48:49], s[52:53], 24 -; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 -; SI-NEXT: v_alignbit_b32 v21, v12, v10, 16 -; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload -; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 -; SI-NEXT: s_waitcnt vmcnt(13) -; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 -; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; SI-NEXT: v_readfirstlane_b32 s56, v21 -; SI-NEXT: s_lshr_b64 s[50:51], s[52:53], 16 -; SI-NEXT: s_lshr_b64 s[52:53], s[52:53], 8 -; SI-NEXT: v_lshrrev_b32_e32 v6, 24, v6 -; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(8) -; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 -; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; SI-NEXT: s_waitcnt vmcnt(5) -; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; SI-NEXT: s_waitcnt vmcnt(4) -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; SI-NEXT: s_lshr_b32 s29, s6, 16 +; SI-NEXT: v_readfirstlane_b32 s6, v7 +; SI-NEXT: v_readfirstlane_b32 s44, v3 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v34 +; SI-NEXT: s_lshr_b32 s9, s6, 16 +; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v26 +; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; SI-NEXT: s_lshr_b64 s[46:47], s[8:9], 16 ; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 +; SI-NEXT: v_readfirstlane_b32 s8, v3 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v39 +; SI-NEXT: v_readfirstlane_b32 s6, v7 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v7 -; SI-NEXT: v_alignbit_b32 v22, v9, v3, 16 -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(4) -; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 -; SI-NEXT: v_alignbit_b32 v23, v13, v12, 16 -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload -; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v31 +; SI-NEXT: s_lshr_b32 s45, s6, 16 +; SI-NEXT: v_readfirstlane_b32 s6, v9 +; SI-NEXT: v_readfirstlane_b32 s58, v3 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v30 +; SI-NEXT: s_lshr_b32 s9, s6, 16 +; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; SI-NEXT: s_lshr_b64 s[62:63], s[8:9], 16 +; SI-NEXT: v_readfirstlane_b32 s8, v3 +; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v23 ; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 -; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v9 -; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s42, v23 -; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v22 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v17 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v57 -; SI-NEXT: v_readfirstlane_b32 s39, v22 +; SI-NEXT: v_readfirstlane_b32 s6, v9 +; SI-NEXT: s_lshr_b32 s59, s6, 16 +; SI-NEXT: v_readfirstlane_b32 s6, v10 +; SI-NEXT: s_lshr_b32 s9, s6, 16 +; SI-NEXT: s_lshr_b64 s[76:77], s[8:9], 16 +; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v17 +; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v11 +; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v42 +; SI-NEXT: v_readfirstlane_b32 s6, v10 +; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; SI-NEXT: s_lshr_b32 s73, s6, 16 +; SI-NEXT: v_readfirstlane_b32 s6, v11 +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v6 +; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v11 +; SI-NEXT: s_lshr_b32 s9, s6, 16 +; SI-NEXT: v_readfirstlane_b32 s6, v18 +; SI-NEXT: s_lshr_b32 s79, s6, 16 +; SI-NEXT: s_lshr_b64 s[54:55], s[58:59], 16 +; SI-NEXT: s_mov_b32 s63, s54 +; SI-NEXT: s_lshr_b64 s[60:61], s[44:45], 16 +; SI-NEXT: s_mov_b32 s47, s60 +; SI-NEXT: s_lshr_b64 s[42:43], s[28:29], 16 +; SI-NEXT: s_mov_b32 s41, s42 +; SI-NEXT: s_lshr_b64 s[34:35], s[22:23], 16 +; SI-NEXT: s_mov_b32 s25, s34 +; SI-NEXT: v_readfirstlane_b32 s5, v14 +; SI-NEXT: s_lshr_b32 s13, s5, 16 +; SI-NEXT: s_lshr_b64 vcc, s[12:13], 16 +; SI-NEXT: s_mov_b32 s5, vcc_lo +; SI-NEXT: v_lshrrev_b32_e32 v56, 24, v1 +; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v2 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v8 +; SI-NEXT: s_lshr_b32 s22, s60, 8 +; SI-NEXT: s_lshr_b32 s21, s42, 8 +; SI-NEXT: s_lshr_b32 s18, s34, 8 +; SI-NEXT: s_lshr_b32 s12, s20, 8 +; SI-NEXT: v_lshrrev_b32_e32 v18, 24, v18 +; SI-NEXT: v_lshrrev_b32_e32 v55, 24, v10 ; SI-NEXT: v_lshrrev_b32_e32 v9, 24, v9 -; SI-NEXT: v_lshrrev_b32_e32 v7, 24, v7 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v46 -; SI-NEXT: s_lshr_b64 s[36:37], s[38:39], 16 -; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v38 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(12) -; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 -; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v21 -; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 -; SI-NEXT: v_alignbit_b32 v24, v15, v13, 16 -; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload +; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v14 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(5) ; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_alignbit_b32 v25, v10, v3, 16 -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload -; SI-NEXT: v_readfirstlane_b32 s31, v25 -; SI-NEXT: v_readfirstlane_b32 s26, v24 -; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; SI-NEXT: s_lshr_b64 s[94:95], s[30:31], 16 -; SI-NEXT: s_lshr_b64 s[34:35], s[30:31], 8 -; SI-NEXT: s_waitcnt vmcnt(4) -; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 -; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v23 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 -; SI-NEXT: v_alignbit_b32 v26, v16, v15, 16 -; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; SI-NEXT: v_readfirstlane_b32 s72, v3 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v32 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_readfirstlane_b32 s20, v26 -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v21 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; SI-NEXT: v_alignbit_b32 v27, v18, v16, 16 -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 -; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v10 -; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; SI-NEXT: v_alignbit_b32 v60, v12, v3, 16 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload -; SI-NEXT: v_readfirstlane_b32 s91, v60 -; SI-NEXT: v_readfirstlane_b32 s14, v27 -; SI-NEXT: v_lshrrev_b32_e32 v10, 24, v10 -; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; SI-NEXT: s_lshr_b64 s[88:89], s[90:91], 16 -; SI-NEXT: s_lshr_b64 s[92:93], s[90:91], 8 -; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(5) -; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; SI-NEXT: v_alignbit_b32 v29, v20, v18, 16 -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload -; SI-NEXT: v_readfirstlane_b32 s8, v29 -; SI-NEXT: s_waitcnt vmcnt(5) -; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; SI-NEXT: s_waitcnt vmcnt(4) +; SI-NEXT: v_readfirstlane_b32 s8, v3 +; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; SI-NEXT: s_lshr_b64 s[92:93], s[8:9], 16 +; SI-NEXT: s_lshr_b64 s[74:75], s[72:73], 16 +; SI-NEXT: s_mov_b32 s77, s74 +; SI-NEXT: s_lshr_b32 s28, s74, 8 +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v12 -; SI-NEXT: v_alignbit_b32 v61, v11, v3, 16 -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload -; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; SI-NEXT: v_readfirstlane_b32 s77, v61 -; SI-NEXT: v_lshrrev_b32_e32 v12, 24, v12 -; SI-NEXT: s_lshr_b64 s[74:75], s[76:77], 16 -; SI-NEXT: s_lshr_b64 s[78:79], s[76:77], 8 -; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_lshrrev_b32_e32 v10, 8, v61 -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(5) -; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; SI-NEXT: s_waitcnt vmcnt(4) -; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 -; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v13 -; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v18 -; SI-NEXT: v_lshrrev_b32_e32 v13, 24, v13 -; SI-NEXT: v_lshrrev_b32_e32 v56, 24, v18 -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(4) +; SI-NEXT: v_readfirstlane_b32 s78, v3 +; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload +; SI-NEXT: s_lshr_b64 s[48:49], s[78:79], 16 +; SI-NEXT: s_mov_b32 s93, s48 +; SI-NEXT: s_lshr_b32 s27, s48, 8 +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_alignbit_b32 v59, v36, v3, 16 -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v8 -; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v3 -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload -; SI-NEXT: v_readfirstlane_b32 s63, v59 -; SI-NEXT: s_lshr_b64 s[60:61], s[62:63], 16 -; SI-NEXT: s_lshr_b64 s[72:73], s[62:63], 8 -; SI-NEXT: v_lshrrev_b32_e32 v4, 8, v59 -; SI-NEXT: v_lshrrev_b32_e32 v18, 8, v25 -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 -; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v20 -; SI-NEXT: v_lshrrev_b32_e32 v24, 24, v20 -; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_readfirstlane_b32 s8, v3 +; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; SI-NEXT: v_readfirstlane_b32 s6, v11 +; SI-NEXT: s_lshr_b32 s9, s6, 16 +; SI-NEXT: s_lshr_b64 s[50:51], s[8:9], 16 +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v3 +; SI-NEXT: v_readfirstlane_b32 s56, v11 +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v41 +; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; SI-NEXT: v_readfirstlane_b32 s8, v11 +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v20 ; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 -; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v3 -; SI-NEXT: v_alignbit_b32 v41, v49, v15, 16 -; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload -; SI-NEXT: v_readfirstlane_b32 s57, v41 +; SI-NEXT: v_readfirstlane_b32 s6, v3 +; SI-NEXT: s_lshr_b32 s57, s6, 16 +; SI-NEXT: v_readfirstlane_b32 s6, v13 +; SI-NEXT: s_lshr_b32 s9, s6, 16 +; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v19 +; SI-NEXT: s_lshr_b64 s[30:31], s[8:9], 16 +; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v13 +; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; SI-NEXT: v_readfirstlane_b32 s6, v24 +; SI-NEXT: s_lshr_b32 s89, s6, 16 +; SI-NEXT: s_lshr_b64 s[94:95], s[56:57], 16 +; SI-NEXT: s_mov_b32 s51, s94 +; SI-NEXT: s_lshr_b32 s44, s94, 8 +; SI-NEXT: s_mov_b32 s56, s42 +; SI-NEXT: v_lshrrev_b32_e32 v47, 24, v24 ; SI-NEXT: v_lshrrev_b32_e32 v3, 24, v3 -; SI-NEXT: s_lshr_b64 s[46:47], s[56:57], 16 -; SI-NEXT: s_lshr_b64 s[58:59], s[56:57], 8 -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_lshrrev_b32_e32 v12, 8, v41 ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v15 -; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; SI-NEXT: v_readfirstlane_b32 s88, v11 +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v31 +; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; SI-NEXT: v_readfirstlane_b32 s8, v11 +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; SI-NEXT: s_lshr_b64 s[82:83], s[88:89], 16 +; SI-NEXT: s_mov_b32 s31, s82 +; SI-NEXT: s_lshr_b32 s43, s82, 8 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 +; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; SI-NEXT: v_readfirstlane_b32 s6, v13 +; SI-NEXT: s_lshr_b32 s9, s6, 16 +; SI-NEXT: s_lshr_b64 s[52:53], s[8:9], 16 +; SI-NEXT: v_readfirstlane_b32 s6, v4 +; SI-NEXT: s_lshr_b32 s37, s6, 16 +; SI-NEXT: s_mov_b32 s88, vcc_lo ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 -; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 -; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v15 -; SI-NEXT: v_alignbit_b32 v58, v32, v16, 16 -; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload -; SI-NEXT: v_readfirstlane_b32 s43, v58 -; SI-NEXT: s_lshr_b64 s[40:41], s[42:43], 16 -; SI-NEXT: s_lshr_b64 s[44:45], s[42:43], 8 -; SI-NEXT: v_lshrrev_b32_e32 v20, 24, v15 -; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_lshrrev_b32_e32 v13, 8, v58 +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 +; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; SI-NEXT: v_readfirstlane_b32 s36, v11 +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v6 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; SI-NEXT: v_readfirstlane_b32 s8, v11 +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v59 +; SI-NEXT: s_lshr_b64 s[98:99], s[36:37], 16 +; SI-NEXT: s_mov_b32 s53, s98 +; SI-NEXT: s_lshr_b32 s58, s98, 8 +; SI-NEXT: s_mov_b32 s36, s26 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v6 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; SI-NEXT: v_readfirstlane_b32 s6, v13 +; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v11 +; SI-NEXT: v_readfirstlane_b32 s90, v13 +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v60 +; SI-NEXT: s_lshr_b32 s9, s6, 16 +; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; SI-NEXT: s_lshr_b64 s[66:67], s[8:9], 16 +; SI-NEXT: v_readfirstlane_b32 s6, v11 +; SI-NEXT: s_lshr_b32 s91, s6, 16 +; SI-NEXT: s_lshr_b64 s[38:39], s[90:91], 16 +; SI-NEXT: s_mov_b32 s67, s38 +; SI-NEXT: s_lshr_b32 s75, s38, 8 +; SI-NEXT: s_mov_b32 s90, s74 +; SI-NEXT: s_lshr_b32 s74, s54, 8 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v6 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; SI-NEXT: v_readfirstlane_b32 s8, v13 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; SI-NEXT: v_alignbit_b32 v47, v45, v16, 16 -; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload -; SI-NEXT: v_readfirstlane_b32 s27, v47 -; SI-NEXT: v_lshrrev_b32_e32 v9, 8, v47 -; SI-NEXT: s_lshr_b64 s[24:25], s[26:27], 16 -; SI-NEXT: s_lshr_b64 s[28:29], s[26:27], 8 +; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v6 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; SI-NEXT: v_readfirstlane_b32 s6, v15 +; SI-NEXT: s_lshr_b32 s9, s6, 16 +; SI-NEXT: s_lshr_b64 s[80:81], s[8:9], 16 ; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v6 +; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v13 +; SI-NEXT: v_readfirstlane_b32 s68, v15 +; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v45 +; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; SI-NEXT: v_readfirstlane_b32 s6, v13 +; SI-NEXT: s_lshr_b32 s69, s6, 16 +; SI-NEXT: s_lshr_b64 s[70:71], s[68:69], 16 +; SI-NEXT: s_mov_b32 s81, s70 +; SI-NEXT: s_lshr_b32 s72, s70, 8 +; SI-NEXT: s_mov_b32 s68, s60 +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; SI-NEXT: v_readfirstlane_b32 s8, v15 +; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v6 +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; SI-NEXT: v_readfirstlane_b32 s64, v15 +; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload ; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 ; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; SI-NEXT: v_alignbit_b32 v19, v11, v16, 16 -; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload -; SI-NEXT: v_readfirstlane_b32 s21, v19 -; SI-NEXT: v_lshrrev_b32_e32 v27, 8, v19 -; SI-NEXT: s_lshr_b64 s[18:19], s[20:21], 16 -; SI-NEXT: s_lshr_b64 s[22:23], s[20:21], 8 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_readfirstlane_b32 s6, v16 +; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; SI-NEXT: s_lshr_b32 s9, s6, 16 +; SI-NEXT: s_lshr_b64 s[86:87], s[8:9], 16 +; SI-NEXT: v_readfirstlane_b32 s6, v12 +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 +; SI-NEXT: s_lshr_b32 s65, s6, 16 +; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 +; SI-NEXT: s_lshr_b64 s[84:85], s[64:65], 16 +; SI-NEXT: s_mov_b32 s87, s84 +; SI-NEXT: v_lshrrev_b32_e32 v48, 24, v6 +; SI-NEXT: s_lshr_b32 s61, s84, 8 +; SI-NEXT: s_mov_b32 s64, s48 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; SI-NEXT: v_readfirstlane_b32 s8, v15 +; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 ; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; SI-NEXT: v_alignbit_b32 v14, v52, v16, 16 -; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload -; SI-NEXT: v_readfirstlane_b32 s15, v14 -; SI-NEXT: v_lshrrev_b32_e32 v7, 8, v14 -; SI-NEXT: s_lshr_b64 s[12:13], s[14:15], 16 -; SI-NEXT: s_lshr_b64 s[16:17], s[14:15], 8 +; SI-NEXT: v_readfirstlane_b32 s6, v16 +; SI-NEXT: s_lshr_b32 s9, s6, 16 +; SI-NEXT: v_readfirstlane_b32 s6, v6 +; SI-NEXT: s_lshr_b32 s7, s6, 16 +; SI-NEXT: s_lshr_b64 s[8:9], s[8:9], 16 +; SI-NEXT: v_lshrrev_b32_e32 v6, 24, v7 +; SI-NEXT: v_lshrrev_b32_e32 v16, 24, v12 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_alignbit_b32 v11, v44, v16, 16 -; SI-NEXT: v_lshrrev_b32_e32 v16, 24, v23 -; SI-NEXT: v_lshrrev_b32_e32 v23, 8, v60 -; SI-NEXT: v_readfirstlane_b32 s9, v11 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v3, 8, v11 -; SI-NEXT: s_lshr_b64 s[6:7], s[8:9], 24 -; SI-NEXT: s_lshr_b64 s[10:11], s[8:9], 8 -; SI-NEXT: v_writelane_b32 v62, s6, 0 -; SI-NEXT: v_writelane_b32 v62, s7, 1 -; SI-NEXT: s_lshr_b64 s[6:7], s[8:9], 16 -; SI-NEXT: s_lshr_b64 s[8:9], s[14:15], 24 -; SI-NEXT: s_lshr_b64 s[14:15], s[20:21], 24 -; SI-NEXT: s_lshr_b64 s[20:21], s[26:27], 24 -; SI-NEXT: s_lshr_b64 s[26:27], s[42:43], 24 -; SI-NEXT: s_lshr_b64 s[42:43], s[56:57], 24 -; SI-NEXT: s_lshr_b64 s[56:57], s[62:63], 24 -; SI-NEXT: s_lshr_b64 s[62:63], s[76:77], 24 -; SI-NEXT: s_lshr_b64 s[76:77], s[90:91], 24 -; SI-NEXT: s_lshr_b64 s[90:91], s[30:31], 24 -; SI-NEXT: s_lshr_b64 s[30:31], s[38:39], 24 -; SI-NEXT: s_lshr_b64 s[38:39], s[38:39], 8 +; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; SI-NEXT: v_readfirstlane_b32 s6, v15 +; SI-NEXT: s_lshr_b64 s[96:97], s[6:7], 16 +; SI-NEXT: s_mov_b32 s9, s96 +; SI-NEXT: s_lshr_b64 s[14:15], s[8:9], 24 +; SI-NEXT: v_writelane_b32 v62, s14, 4 +; SI-NEXT: v_writelane_b32 v62, s15, 5 +; SI-NEXT: s_lshr_b64 s[14:15], s[8:9], 16 +; SI-NEXT: v_writelane_b32 v62, s14, 2 +; SI-NEXT: v_writelane_b32 v62, s15, 3 +; SI-NEXT: s_lshr_b64 s[14:15], s[8:9], 8 +; SI-NEXT: v_writelane_b32 v62, s14, 0 +; SI-NEXT: v_writelane_b32 v62, s15, 1 +; SI-NEXT: s_lshr_b64 s[14:15], s[86:87], 24 +; SI-NEXT: v_writelane_b32 v62, s14, 10 +; SI-NEXT: v_writelane_b32 v62, s15, 11 +; SI-NEXT: s_lshr_b64 s[14:15], s[86:87], 16 +; SI-NEXT: v_writelane_b32 v62, s14, 8 +; SI-NEXT: v_writelane_b32 v62, s15, 9 +; SI-NEXT: s_lshr_b64 s[14:15], s[86:87], 8 +; SI-NEXT: v_writelane_b32 v62, s14, 6 +; SI-NEXT: v_writelane_b32 v62, s15, 7 +; SI-NEXT: s_lshr_b64 s[14:15], s[80:81], 24 +; SI-NEXT: v_writelane_b32 v62, s14, 16 +; SI-NEXT: v_writelane_b32 v62, s15, 17 +; SI-NEXT: s_lshr_b64 s[14:15], s[80:81], 16 +; SI-NEXT: v_writelane_b32 v62, s14, 14 +; SI-NEXT: v_writelane_b32 v62, s15, 15 +; SI-NEXT: s_lshr_b64 s[14:15], s[80:81], 8 +; SI-NEXT: v_writelane_b32 v62, s14, 12 +; SI-NEXT: v_writelane_b32 v62, s15, 13 +; SI-NEXT: s_lshr_b64 s[14:15], s[66:67], 24 +; SI-NEXT: v_writelane_b32 v62, s14, 22 +; SI-NEXT: v_writelane_b32 v62, s15, 23 +; SI-NEXT: s_lshr_b64 s[14:15], s[66:67], 16 +; SI-NEXT: v_writelane_b32 v62, s14, 20 +; SI-NEXT: v_writelane_b32 v62, s15, 21 +; SI-NEXT: s_lshr_b64 s[14:15], s[66:67], 8 +; SI-NEXT: v_writelane_b32 v62, s14, 18 +; SI-NEXT: v_writelane_b32 v62, s15, 19 +; SI-NEXT: s_lshr_b64 s[14:15], s[52:53], 24 +; SI-NEXT: v_writelane_b32 v62, s14, 28 +; SI-NEXT: v_writelane_b32 v62, s15, 29 +; SI-NEXT: s_lshr_b64 s[14:15], s[52:53], 16 +; SI-NEXT: v_writelane_b32 v62, s14, 26 +; SI-NEXT: v_writelane_b32 v62, s15, 27 +; SI-NEXT: s_lshr_b64 s[14:15], s[52:53], 8 +; SI-NEXT: v_writelane_b32 v62, s14, 24 +; SI-NEXT: v_writelane_b32 v62, s15, 25 +; SI-NEXT: s_lshr_b64 s[14:15], s[30:31], 24 +; SI-NEXT: v_writelane_b32 v62, s14, 34 +; SI-NEXT: v_writelane_b32 v62, s15, 35 +; SI-NEXT: s_lshr_b64 s[14:15], s[30:31], 16 +; SI-NEXT: v_writelane_b32 v62, s14, 32 +; SI-NEXT: v_writelane_b32 v62, s15, 33 +; SI-NEXT: s_lshr_b64 s[14:15], s[30:31], 8 +; SI-NEXT: v_writelane_b32 v62, s14, 30 +; SI-NEXT: v_writelane_b32 v62, s15, 31 +; SI-NEXT: s_lshr_b64 s[14:15], s[50:51], 24 +; SI-NEXT: v_writelane_b32 v62, s14, 40 +; SI-NEXT: v_writelane_b32 v62, s15, 41 +; SI-NEXT: s_lshr_b64 s[14:15], s[50:51], 16 +; SI-NEXT: v_writelane_b32 v62, s14, 38 +; SI-NEXT: v_writelane_b32 v62, s15, 39 +; SI-NEXT: s_lshr_b64 s[14:15], s[50:51], 8 +; SI-NEXT: v_writelane_b32 v62, s14, 36 +; SI-NEXT: v_writelane_b32 v62, s15, 37 +; SI-NEXT: s_lshr_b64 s[14:15], s[92:93], 24 +; SI-NEXT: v_writelane_b32 v62, s14, 46 +; SI-NEXT: v_writelane_b32 v62, s15, 47 +; SI-NEXT: s_lshr_b64 s[14:15], s[92:93], 16 +; SI-NEXT: v_writelane_b32 v62, s14, 44 +; SI-NEXT: v_writelane_b32 v62, s15, 45 +; SI-NEXT: s_lshr_b64 s[14:15], s[92:93], 8 +; SI-NEXT: v_writelane_b32 v62, s14, 42 +; SI-NEXT: v_writelane_b32 v62, s15, 43 +; SI-NEXT: s_lshr_b64 s[14:15], s[76:77], 24 +; SI-NEXT: v_writelane_b32 v62, s14, 52 +; SI-NEXT: v_writelane_b32 v62, s15, 53 +; SI-NEXT: s_lshr_b64 s[14:15], s[76:77], 16 +; SI-NEXT: v_writelane_b32 v62, s14, 50 +; SI-NEXT: v_writelane_b32 v62, s15, 51 +; SI-NEXT: s_lshr_b64 s[14:15], s[76:77], 8 +; SI-NEXT: v_writelane_b32 v62, s14, 48 +; SI-NEXT: v_writelane_b32 v62, s15, 49 +; SI-NEXT: s_lshr_b64 s[14:15], s[62:63], 24 +; SI-NEXT: v_writelane_b32 v62, s14, 58 +; SI-NEXT: v_writelane_b32 v62, s15, 59 +; SI-NEXT: s_lshr_b64 s[14:15], s[62:63], 16 +; SI-NEXT: v_writelane_b32 v62, s14, 56 +; SI-NEXT: v_writelane_b32 v62, s15, 57 +; SI-NEXT: s_lshr_b64 s[14:15], s[62:63], 8 +; SI-NEXT: v_writelane_b32 v62, s14, 54 +; SI-NEXT: v_writelane_b32 v62, s15, 55 +; SI-NEXT: s_lshr_b64 s[14:15], s[46:47], 24 +; SI-NEXT: v_writelane_b32 v61, s14, 0 +; SI-NEXT: v_writelane_b32 v61, s15, 1 +; SI-NEXT: s_lshr_b64 s[14:15], s[46:47], 16 +; SI-NEXT: v_writelane_b32 v62, s14, 62 +; SI-NEXT: v_writelane_b32 v62, s15, 63 +; SI-NEXT: s_lshr_b64 s[14:15], s[46:47], 8 +; SI-NEXT: v_writelane_b32 v62, s14, 60 +; SI-NEXT: v_writelane_b32 v62, s15, 61 +; SI-NEXT: s_lshr_b64 s[14:15], s[40:41], 24 +; SI-NEXT: v_writelane_b32 v61, s14, 6 +; SI-NEXT: v_writelane_b32 v61, s15, 7 +; SI-NEXT: s_lshr_b64 s[14:15], s[40:41], 16 +; SI-NEXT: v_writelane_b32 v61, s14, 4 +; SI-NEXT: v_writelane_b32 v61, s15, 5 +; SI-NEXT: s_lshr_b64 s[14:15], s[40:41], 8 +; SI-NEXT: v_writelane_b32 v61, s14, 2 +; SI-NEXT: v_writelane_b32 v61, s15, 3 +; SI-NEXT: s_lshr_b64 s[14:15], s[24:25], 24 +; SI-NEXT: v_writelane_b32 v61, s14, 12 +; SI-NEXT: v_writelane_b32 v61, s15, 13 +; SI-NEXT: s_lshr_b64 s[14:15], s[24:25], 16 +; SI-NEXT: v_writelane_b32 v61, s14, 10 +; SI-NEXT: v_writelane_b32 v61, s15, 11 +; SI-NEXT: s_lshr_b64 s[14:15], s[24:25], 8 +; SI-NEXT: v_writelane_b32 v61, s14, 8 +; SI-NEXT: v_writelane_b32 v61, s15, 9 +; SI-NEXT: s_lshr_b64 s[14:15], s[16:17], 24 +; SI-NEXT: v_writelane_b32 v61, s14, 18 +; SI-NEXT: v_writelane_b32 v61, s15, 19 +; SI-NEXT: s_lshr_b64 s[14:15], s[16:17], 16 +; SI-NEXT: v_writelane_b32 v61, s14, 16 +; SI-NEXT: v_writelane_b32 v61, s15, 17 +; SI-NEXT: s_lshr_b64 s[14:15], s[16:17], 8 +; SI-NEXT: v_writelane_b32 v61, s14, 14 +; SI-NEXT: v_writelane_b32 v61, s15, 15 +; SI-NEXT: s_lshr_b64 s[14:15], s[10:11], 24 +; SI-NEXT: v_writelane_b32 v61, s14, 24 +; SI-NEXT: v_writelane_b32 v61, s15, 25 +; SI-NEXT: s_lshr_b64 s[14:15], s[10:11], 16 +; SI-NEXT: v_writelane_b32 v61, s14, 22 +; SI-NEXT: v_writelane_b32 v61, s15, 23 +; SI-NEXT: s_lshr_b64 s[14:15], s[10:11], 8 +; SI-NEXT: v_writelane_b32 v61, s14, 20 +; SI-NEXT: v_writelane_b32 v61, s15, 21 +; SI-NEXT: s_lshr_b64 s[14:15], s[4:5], 24 +; SI-NEXT: v_writelane_b32 v61, s14, 32 +; SI-NEXT: v_writelane_b32 v61, s15, 33 +; SI-NEXT: s_lshr_b64 s[14:15], s[4:5], 16 +; SI-NEXT: v_writelane_b32 v61, s14, 30 +; SI-NEXT: v_writelane_b32 v61, s15, 31 +; SI-NEXT: s_lshr_b64 s[14:15], s[4:5], 8 +; SI-NEXT: v_writelane_b32 v61, s14, 28 +; SI-NEXT: v_lshrrev_b32_e32 v15, 24, v13 +; SI-NEXT: v_lshrrev_b32_e32 v13, 24, v11 +; SI-NEXT: v_lshrrev_b32_e32 v11, 24, v4 +; SI-NEXT: v_lshrrev_b32_e32 v4, 24, v5 +; SI-NEXT: v_writelane_b32 v61, s15, 29 +; SI-NEXT: s_lshr_b32 s78, s96, 8 +; SI-NEXT: s_lshr_b32 s15, s26, 8 +; SI-NEXT: s_mov_b32 s14, s20 +; SI-NEXT: s_lshr_b32 s6, vcc_lo, 8 +; SI-NEXT: v_mov_b32_e32 v14, v4 +; SI-NEXT: v_mov_b32_e32 v4, v6 ; SI-NEXT: .LBB91_5: ; %end -; SI-NEXT: s_waitcnt vmcnt(4) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v29 -; SI-NEXT: s_lshl_b32 s5, s10, 8 -; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: s_and_b32 s5, s6, 0xff -; SI-NEXT: v_readlane_b32 s6, v62, 0 -; SI-NEXT: s_lshl_b32 s5, s5, 16 -; SI-NEXT: s_lshl_b32 s6, s6, 24 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_or_b32 s5, s6, s5 -; SI-NEXT: v_or_b32_e32 v1, s5, v1 +; SI-NEXT: s_and_b32 s5, s8, 0xff +; SI-NEXT: v_readlane_b32 s8, v62, 0 +; SI-NEXT: v_readlane_b32 s9, v62, 1 +; SI-NEXT: s_lshl_b32 s8, s8, 8 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: v_readlane_b32 s8, v62, 2 +; SI-NEXT: v_readlane_b32 s9, v62, 3 +; SI-NEXT: s_and_b32 s8, s8, 0xff +; SI-NEXT: v_readlane_b32 vcc_lo, v62, 4 +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: s_lshl_b32 s9, vcc_lo, 24 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: s_or_b32 s8, s9, s8 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) +; SI-NEXT: v_mov_b32_e32 v1, s5 +; SI-NEXT: s_and_b32 s5, s96, 0xff +; SI-NEXT: s_lshl_b32 s8, s78, 8 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: s_and_b32 s8, s7, 0xff ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen +; SI-NEXT: s_lshl_b32 s8, s8, 16 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v11 -; SI-NEXT: s_waitcnt vmcnt(4) -; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v3 -; SI-NEXT: v_or_b32_e32 v1, v1, v5 -; SI-NEXT: v_and_b32_e32 v5, 0xff, v44 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v16 -; SI-NEXT: v_or_b32_e32 v5, v6, v5 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: v_or_b32_e32 v1, v1, v5 -; SI-NEXT: v_add_i32_e32 v5, vcc, 4, v0 -; SI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload -; SI-NEXT: s_lshl_b32 s5, s16, 8 -; SI-NEXT: s_lshl_b32 s6, s8, 24 -; SI-NEXT: v_add_i32_e32 v5, vcc, 8, v0 -; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v26 -; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; SI-NEXT: s_lshl_b32 s4, s4, 8 -; SI-NEXT: v_readlane_b32 s7, v62, 1 -; SI-NEXT: v_readlane_b32 s99, v63, 35 -; SI-NEXT: v_readlane_b32 s97, v63, 33 -; SI-NEXT: v_readlane_b32 s87, v63, 31 -; SI-NEXT: v_readlane_b32 s85, v63, 29 -; SI-NEXT: v_readlane_b32 s83, v63, 27 -; SI-NEXT: v_readlane_b32 s81, v63, 25 -; SI-NEXT: v_readlane_b32 s71, v63, 23 -; SI-NEXT: v_readlane_b32 s69, v63, 21 -; SI-NEXT: v_readlane_b32 s67, v63, 19 -; SI-NEXT: v_readlane_b32 s65, v63, 17 -; SI-NEXT: v_readlane_b32 s55, v63, 15 -; SI-NEXT: v_readlane_b32 s53, v63, 13 -; SI-NEXT: v_readlane_b32 s51, v63, 11 -; SI-NEXT: v_readlane_b32 s49, v63, 9 -; SI-NEXT: v_readlane_b32 s39, v63, 7 -; SI-NEXT: v_readlane_b32 s37, v63, 5 -; SI-NEXT: v_readlane_b32 s35, v63, 3 -; SI-NEXT: v_readlane_b32 s31, v63, 1 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 +; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v48 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: v_or_b32_e32 v1, s8, v1 +; SI-NEXT: v_readlane_b32 s8, v62, 6 +; SI-NEXT: v_readlane_b32 vcc_hi, v62, 5 ; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: s_and_b32 s5, s12, 0xff -; SI-NEXT: s_lshl_b32 s5, s5, 16 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_or_b32 s5, s6, s5 +; SI-NEXT: s_and_b32 s5, s86, 0xff +; SI-NEXT: v_readlane_b32 s9, v62, 7 +; SI-NEXT: s_lshl_b32 s8, s8, 8 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: v_readlane_b32 s8, v62, 8 +; SI-NEXT: v_readlane_b32 s9, v62, 9 +; SI-NEXT: s_and_b32 s8, s8, 0xff +; SI-NEXT: v_readlane_b32 vcc_lo, v62, 10 +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: s_lshl_b32 s9, vcc_lo, 24 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: s_or_b32 s8, s9, s8 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; SI-NEXT: v_readlane_b32 vcc_hi, v62, 11 +; SI-NEXT: v_mov_b32_e32 v2, s5 +; SI-NEXT: s_and_b32 s5, s84, 0xff +; SI-NEXT: s_lshl_b32 s8, s61, 8 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: s_and_b32 s8, s65, 0xff +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v16 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: v_or_b32_e32 v1, s8, v1 +; SI-NEXT: v_readlane_b32 s8, v62, 12 ; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen +; SI-NEXT: s_and_b32 s5, s80, 0xff +; SI-NEXT: v_readlane_b32 s9, v62, 13 +; SI-NEXT: s_lshl_b32 s8, s8, 8 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: v_readlane_b32 s8, v62, 14 +; SI-NEXT: v_readlane_b32 s9, v62, 15 +; SI-NEXT: s_and_b32 s8, s8, 0xff +; SI-NEXT: v_readlane_b32 s60, v62, 16 +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: s_lshl_b32 s9, s60, 24 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: s_or_b32 s8, s9, s8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v14 -; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v7 -; SI-NEXT: v_or_b32_e32 v1, v1, v5 -; SI-NEXT: v_and_b32_e32 v5, 0xff, v52 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_or_b32_e32 v5, v6, v5 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: v_or_b32_e32 v1, v1, v5 -; SI-NEXT: v_add_i32_e32 v5, vcc, 12, v0 -; SI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; SI-NEXT: v_mov_b32_e32 v2, s5 +; SI-NEXT: s_and_b32 s5, s70, 0xff +; SI-NEXT: s_lshl_b32 s8, s72, 8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload -; SI-NEXT: s_lshl_b32 s5, s22, 8 -; SI-NEXT: s_lshl_b32 s6, s14, 24 -; SI-NEXT: v_add_i32_e32 v5, vcc, 16, v0 -; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v24 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 -; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: s_and_b32 s5, s18, 0xff -; SI-NEXT: s_lshl_b32 s5, s5, 16 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_or_b32 s5, s6, s5 +; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: s_and_b32 s8, s69, 0xff +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v15 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: v_or_b32_e32 v1, s8, v1 +; SI-NEXT: v_readlane_b32 s8, v62, 18 ; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen +; SI-NEXT: s_and_b32 s5, s66, 0xff +; SI-NEXT: v_readlane_b32 s9, v62, 19 +; SI-NEXT: s_lshl_b32 s8, s8, 8 +; SI-NEXT: v_readlane_b32 s61, v62, 17 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: v_readlane_b32 s8, v62, 20 +; SI-NEXT: v_readlane_b32 s9, v62, 21 +; SI-NEXT: s_and_b32 s8, s8, 0xff +; SI-NEXT: v_readlane_b32 s60, v62, 22 +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: s_lshl_b32 s9, s60, 24 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: s_or_b32 s8, s9, s8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v19 -; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v27 -; SI-NEXT: v_or_b32_e32 v1, v1, v5 -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_lshl_b32 s5, s28, 8 -; SI-NEXT: s_lshl_b32 s6, s20, 24 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v5, 0xff, v5 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_or_b32_e32 v5, v6, v5 -; SI-NEXT: v_or_b32_e32 v1, v1, v5 -; SI-NEXT: v_add_i32_e32 v5, vcc, 20, v0 -; SI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; SI-NEXT: v_mov_b32_e32 v2, s5 +; SI-NEXT: s_and_b32 s5, s38, 0xff +; SI-NEXT: s_lshl_b32 s8, s75, 8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload -; SI-NEXT: v_add_i32_e32 v5, vcc, 24, v0 -; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v56 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 -; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: s_and_b32 s5, s24, 0xff -; SI-NEXT: s_lshl_b32 s5, s5, 16 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_or_b32 s5, s6, s5 +; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: s_and_b32 s8, s91, 0xff +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v13 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: v_or_b32_e32 v1, s8, v1 +; SI-NEXT: v_readlane_b32 s8, v62, 24 ; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen +; SI-NEXT: s_and_b32 s5, s52, 0xff +; SI-NEXT: v_readlane_b32 s9, v62, 25 +; SI-NEXT: s_lshl_b32 s8, s8, 8 +; SI-NEXT: v_readlane_b32 s61, v62, 23 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: v_readlane_b32 s8, v62, 26 +; SI-NEXT: v_readlane_b32 s9, v62, 27 +; SI-NEXT: s_and_b32 s8, s8, 0xff +; SI-NEXT: v_readlane_b32 s60, v62, 28 +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: s_lshl_b32 s9, s60, 24 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: s_or_b32 s8, s9, s8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v47 -; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v9 -; SI-NEXT: v_or_b32_e32 v1, v1, v5 -; SI-NEXT: v_and_b32_e32 v5, 0xff, v45 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_or_b32_e32 v5, v6, v5 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: v_or_b32_e32 v1, v1, v5 -; SI-NEXT: v_add_i32_e32 v5, vcc, 28, v0 -; SI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; SI-NEXT: v_mov_b32_e32 v2, s5 +; SI-NEXT: s_and_b32 s5, s98, 0xff +; SI-NEXT: s_lshl_b32 s8, s58, 8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload -; SI-NEXT: s_lshl_b32 s5, s44, 8 -; SI-NEXT: s_lshl_b32 s6, s26, 24 -; SI-NEXT: v_add_i32_e32 v5, vcc, 32, v0 -; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v20 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 -; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: s_and_b32 s5, s40, 0xff -; SI-NEXT: s_lshl_b32 s5, s5, 16 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_or_b32 s5, s6, s5 +; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: s_and_b32 s8, s37, 0xff +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v11 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: v_or_b32_e32 v1, s8, v1 +; SI-NEXT: v_readlane_b32 s8, v62, 30 ; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen +; SI-NEXT: s_and_b32 s5, s30, 0xff +; SI-NEXT: v_readlane_b32 s9, v62, 31 +; SI-NEXT: s_lshl_b32 s8, s8, 8 +; SI-NEXT: v_readlane_b32 s61, v62, 29 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: v_readlane_b32 s8, v62, 32 +; SI-NEXT: v_readlane_b32 s9, v62, 33 +; SI-NEXT: s_and_b32 s8, s8, 0xff +; SI-NEXT: v_readlane_b32 s60, v62, 34 +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: s_lshl_b32 s9, s60, 24 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: s_or_b32 s8, s9, s8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v58 -; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v13 -; SI-NEXT: v_or_b32_e32 v1, v1, v5 -; SI-NEXT: v_and_b32_e32 v5, 0xff, v32 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: v_or_b32_e32 v5, v6, v5 -; SI-NEXT: v_or_b32_e32 v1, v1, v5 -; SI-NEXT: v_add_i32_e32 v5, vcc, 36, v0 -; SI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; SI-NEXT: v_mov_b32_e32 v2, s5 +; SI-NEXT: s_and_b32 s5, s82, 0xff +; SI-NEXT: s_lshl_b32 s8, s43, 8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload -; SI-NEXT: s_lshl_b32 s5, s58, 8 -; SI-NEXT: s_lshl_b32 s6, s42, 24 -; SI-NEXT: v_add_i32_e32 v5, vcc, 40, v0 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 -; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: s_and_b32 s5, s46, 0xff -; SI-NEXT: s_lshl_b32 s5, s5, 16 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_or_b32 s5, s6, s5 +; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: s_and_b32 s8, s89, 0xff +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v47 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: v_or_b32_e32 v1, s8, v1 +; SI-NEXT: v_readlane_b32 s8, v62, 36 ; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload +; SI-NEXT: s_and_b32 s5, s50, 0xff +; SI-NEXT: v_readlane_b32 s9, v62, 37 +; SI-NEXT: s_lshl_b32 s8, s8, 8 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: v_readlane_b32 s8, v62, 38 +; SI-NEXT: v_readlane_b32 s9, v62, 39 +; SI-NEXT: s_and_b32 s8, s8, 0xff +; SI-NEXT: v_readlane_b32 s42, v62, 40 +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: s_lshl_b32 s9, s42, 24 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: s_or_b32 s8, s9, s8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v41 -; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v12 -; SI-NEXT: v_or_b32_e32 v1, v1, v5 -; SI-NEXT: v_and_b32_e32 v5, 0xff, v49 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_lshl_b32 s5, s72, 8 -; SI-NEXT: s_lshl_b32 s6, s56, 24 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3 -; SI-NEXT: v_or_b32_e32 v3, v3, v5 -; SI-NEXT: v_or_b32_e32 v1, v1, v3 -; SI-NEXT: v_add_i32_e32 v3, vcc, 44, v0 -; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; SI-NEXT: v_mov_b32_e32 v2, s5 +; SI-NEXT: s_and_b32 s5, s94, 0xff +; SI-NEXT: s_lshl_b32 s8, s44, 8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload -; SI-NEXT: v_add_i32_e32 v3, vcc, 48, v0 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 -; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: s_and_b32 s5, s60, 0xff -; SI-NEXT: s_lshl_b32 s5, s5, 16 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_or_b32 s5, s6, s5 +; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: s_and_b32 s8, s57, 0xff +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v3 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: v_or_b32_e32 v1, s8, v1 +; SI-NEXT: v_readlane_b32 s8, v62, 42 ; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v4 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload +; SI-NEXT: s_and_b32 s5, s92, 0xff +; SI-NEXT: v_readlane_b32 s9, v62, 43 +; SI-NEXT: s_lshl_b32 s8, s8, 8 +; SI-NEXT: v_readlane_b32 s43, v62, 41 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: v_readlane_b32 s8, v62, 44 +; SI-NEXT: v_readlane_b32 s9, v62, 45 +; SI-NEXT: s_and_b32 s8, s8, 0xff +; SI-NEXT: v_readlane_b32 s42, v62, 46 +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: s_lshl_b32 s9, s42, 24 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: s_or_b32 s8, s9, s8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v59 -; SI-NEXT: v_or_b32_e32 v1, v1, v3 -; SI-NEXT: v_and_b32_e32 v3, 0xff, v36 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_lshl_b32 s5, s78, 8 -; SI-NEXT: s_lshl_b32 s6, s62, 24 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4 -; SI-NEXT: v_or_b32_e32 v3, v4, v3 -; SI-NEXT: v_or_b32_e32 v1, v1, v3 -; SI-NEXT: v_add_i32_e32 v3, vcc, 52, v0 -; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; SI-NEXT: v_mov_b32_e32 v2, s5 +; SI-NEXT: s_and_b32 s5, s64, 0xff +; SI-NEXT: s_lshl_b32 s8, s27, 8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; SI-NEXT: v_add_i32_e32 v3, vcc, 56, v0 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 -; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: s_and_b32 s5, s74, 0xff -; SI-NEXT: s_lshl_b32 s5, s5, 16 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_or_b32 s5, s6, s5 +; SI-NEXT: v_add_i32_e32 v1, vcc, 56, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: s_and_b32 s8, s79, 0xff +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v18 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: v_or_b32_e32 v1, s8, v1 +; SI-NEXT: v_readlane_b32 s8, v62, 48 ; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: s_and_b32 s5, s76, 0xff +; SI-NEXT: v_readlane_b32 s9, v62, 49 +; SI-NEXT: s_lshl_b32 s8, s8, 8 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: v_readlane_b32 s8, v62, 50 +; SI-NEXT: v_readlane_b32 s9, v62, 51 +; SI-NEXT: s_and_b32 s8, s8, 0xff +; SI-NEXT: v_readlane_b32 s26, v62, 52 +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: s_lshl_b32 s9, s26, 24 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: s_or_b32 s8, s9, s8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v61 -; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v10 -; SI-NEXT: v_or_b32_e32 v1, v1, v3 -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_lshl_b32 s5, s92, 8 -; SI-NEXT: s_lshl_b32 s6, s76, 24 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v3, 0xff, v3 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4 -; SI-NEXT: v_or_b32_e32 v3, v4, v3 -; SI-NEXT: v_or_b32_e32 v1, v1, v3 -; SI-NEXT: v_add_i32_e32 v3, vcc, 60, v0 -; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; SI-NEXT: v_mov_b32_e32 v2, s5 +; SI-NEXT: s_and_b32 s5, s90, 0xff +; SI-NEXT: s_lshl_b32 s8, s28, 8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; SI-NEXT: v_add_i32_e32 v3, vcc, 64, v0 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 -; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: s_and_b32 s5, s88, 0xff -; SI-NEXT: s_lshl_b32 s5, s5, 16 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_or_b32 s5, s6, s5 +; SI-NEXT: v_add_i32_e32 v1, vcc, 64, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: s_and_b32 s8, s73, 0xff +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v55 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: v_or_b32_e32 v1, s8, v1 +; SI-NEXT: v_readlane_b32 s8, v62, 54 ; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: s_and_b32 s5, s62, 0xff +; SI-NEXT: v_readlane_b32 s9, v62, 55 +; SI-NEXT: s_lshl_b32 s8, s8, 8 +; SI-NEXT: v_readlane_b32 s27, v62, 53 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: v_readlane_b32 s8, v62, 56 +; SI-NEXT: v_readlane_b32 s9, v62, 57 +; SI-NEXT: s_and_b32 s8, s8, 0xff +; SI-NEXT: v_readlane_b32 s26, v62, 58 +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: s_lshl_b32 s9, s26, 24 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: s_or_b32 s8, s9, s8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v60 -; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v23 -; SI-NEXT: v_or_b32_e32 v1, v1, v3 -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_lshl_b32 s5, s34, 8 -; SI-NEXT: s_lshl_b32 s6, s90, 24 -; SI-NEXT: v_readlane_b32 s34, v63, 2 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v3, 0xff, v3 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4 -; SI-NEXT: v_or_b32_e32 v3, v4, v3 -; SI-NEXT: v_or_b32_e32 v1, v1, v3 -; SI-NEXT: v_add_i32_e32 v3, vcc, 0x44, v0 -; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; SI-NEXT: v_mov_b32_e32 v2, s5 +; SI-NEXT: s_and_b32 s5, s54, 0xff +; SI-NEXT: s_lshl_b32 s8, s74, 8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload -; SI-NEXT: v_add_i32_e32 v3, vcc, 0x48, v0 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 -; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: s_and_b32 s5, s94, 0xff -; SI-NEXT: s_lshl_b32 s5, s5, 16 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_or_b32 s5, s6, s5 +; SI-NEXT: v_add_i32_e32 v1, vcc, 0x48, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: s_and_b32 s8, s59, 0xff +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v9 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: v_or_b32_e32 v1, s8, v1 +; SI-NEXT: v_readlane_b32 s8, v62, 60 ; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: s_and_b32 s5, s46, 0xff +; SI-NEXT: v_readlane_b32 s9, v62, 61 +; SI-NEXT: s_lshl_b32 s8, s8, 8 +; SI-NEXT: v_readlane_b32 s27, v62, 59 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: v_readlane_b32 s8, v62, 62 +; SI-NEXT: v_readlane_b32 s9, v62, 63 +; SI-NEXT: s_and_b32 s8, s8, 0xff +; SI-NEXT: v_readlane_b32 s26, v61, 0 +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: s_lshl_b32 s9, s26, 24 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: s_or_b32 s8, s9, s8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v25 -; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v18 -; SI-NEXT: v_or_b32_e32 v1, v1, v3 -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_lshl_b32 s5, s38, 8 -; SI-NEXT: s_lshl_b32 s6, s30, 24 -; SI-NEXT: v_readlane_b32 s38, v63, 6 -; SI-NEXT: v_readlane_b32 s30, v63, 0 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v3, 0xff, v3 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4 -; SI-NEXT: v_or_b32_e32 v3, v4, v3 -; SI-NEXT: v_or_b32_e32 v1, v1, v3 -; SI-NEXT: v_add_i32_e32 v3, vcc, 0x4c, v0 -; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; SI-NEXT: v_mov_b32_e32 v2, s5 +; SI-NEXT: s_and_b32 s5, s68, 0xff +; SI-NEXT: s_lshl_b32 s8, s22, 8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload -; SI-NEXT: v_add_i32_e32 v3, vcc, 0x50, v0 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 -; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: s_and_b32 s5, s36, 0xff -; SI-NEXT: s_lshl_b32 s5, s5, 16 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_or_b32 s5, s6, s5 +; SI-NEXT: v_add_i32_e32 v1, vcc, 0x50, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: s_and_b32 s8, s45, 0xff +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v4 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: v_or_b32_e32 v1, s8, v1 +; SI-NEXT: v_readlane_b32 s8, v61, 2 ; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload +; SI-NEXT: s_and_b32 s5, s40, 0xff +; SI-NEXT: v_readlane_b32 s9, v61, 3 +; SI-NEXT: s_lshl_b32 s8, s8, 8 +; SI-NEXT: v_readlane_b32 s27, v61, 1 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: v_readlane_b32 s8, v61, 4 +; SI-NEXT: v_readlane_b32 s9, v61, 5 +; SI-NEXT: s_and_b32 s8, s8, 0xff +; SI-NEXT: v_readlane_b32 s26, v61, 6 +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: s_lshl_b32 s9, s26, 24 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: s_or_b32 s8, s9, s8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v22 -; SI-NEXT: s_lshl_b32 s5, s52, 8 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload -; SI-NEXT: s_lshl_b32 s6, s48, 24 -; SI-NEXT: v_readlane_b32 s52, v63, 12 -; SI-NEXT: v_readlane_b32 s48, v63, 8 -; SI-NEXT: v_readlane_b32 s36, v63, 4 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3 -; SI-NEXT: v_or_b32_e32 v1, v1, v3 -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v3, 0xff, v3 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_or_b32_e32 v3, v4, v3 -; SI-NEXT: v_or_b32_e32 v1, v1, v3 -; SI-NEXT: v_add_i32_e32 v3, vcc, 0x54, v0 -; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; SI-NEXT: v_mov_b32_e32 v2, s5 +; SI-NEXT: s_and_b32 s5, s56, 0xff +; SI-NEXT: s_lshl_b32 s8, s21, 8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload -; SI-NEXT: v_add_i32_e32 v3, vcc, 0x58, v0 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 -; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: s_and_b32 s5, s50, 0xff -; SI-NEXT: s_lshl_b32 s5, s5, 16 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_or_b32 s5, s6, s5 +; SI-NEXT: v_add_i32_e32 v1, vcc, 0x58, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: s_and_b32 s8, s29, 0xff +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v14 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: v_or_b32_e32 v1, s8, v1 +; SI-NEXT: v_readlane_b32 s8, v61, 8 ; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; SI-NEXT: s_and_b32 s5, s24, 0xff +; SI-NEXT: v_readlane_b32 s9, v61, 9 +; SI-NEXT: s_lshl_b32 s8, s8, 8 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: v_readlane_b32 s8, v61, 10 +; SI-NEXT: v_readlane_b32 s9, v61, 11 +; SI-NEXT: s_and_b32 s8, s8, 0xff +; SI-NEXT: v_readlane_b32 s20, v61, 12 +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: s_lshl_b32 s9, s20, 24 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: s_or_b32 s8, s9, s8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v17 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload -; SI-NEXT: s_lshl_b32 s5, s68, 8 -; SI-NEXT: s_lshl_b32 s6, s54, 24 -; SI-NEXT: v_readlane_b32 s68, v63, 20 -; SI-NEXT: v_readlane_b32 s54, v63, 14 -; SI-NEXT: v_readlane_b32 s50, v63, 10 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3 -; SI-NEXT: v_or_b32_e32 v1, v1, v3 -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v4 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v3, 0xff, v3 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_or_b32_e32 v3, v4, v3 -; SI-NEXT: v_or_b32_e32 v1, v1, v3 -; SI-NEXT: v_add_i32_e32 v3, vcc, 0x5c, v0 -; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; SI-NEXT: v_mov_b32_e32 v2, s5 +; SI-NEXT: s_and_b32 s5, s34, 0xff +; SI-NEXT: s_lshl_b32 s8, s18, 8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload -; SI-NEXT: v_add_i32_e32 v3, vcc, 0x60, v0 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 -; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: s_and_b32 s5, s64, 0xff -; SI-NEXT: s_lshl_b32 s5, s5, 16 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_or_b32 s5, s6, s5 +; SI-NEXT: v_add_i32_e32 v1, vcc, 0x60, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: s_and_b32 s8, s23, 0xff +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v56 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: v_or_b32_e32 v1, s8, v1 +; SI-NEXT: v_readlane_b32 s8, v61, 14 ; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen +; SI-NEXT: s_and_b32 s5, s16, 0xff +; SI-NEXT: v_readlane_b32 s9, v61, 15 +; SI-NEXT: s_lshl_b32 s8, s8, 8 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: v_readlane_b32 s8, v61, 16 +; SI-NEXT: v_readlane_b32 s9, v61, 17 +; SI-NEXT: s_and_b32 s8, s8, 0xff +; SI-NEXT: v_readlane_b32 s16, v61, 18 +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: s_lshl_b32 s9, s16, 24 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: s_or_b32 s8, s9, s8 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v30 -; SI-NEXT: v_or_b32_e32 v1, v1, v2 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_lshl_b32 s5, s82, 8 -; SI-NEXT: s_lshl_b32 s6, s66, 24 -; SI-NEXT: v_readlane_b32 s82, v63, 26 -; SI-NEXT: v_readlane_b32 s66, v63, 18 -; SI-NEXT: v_readlane_b32 s64, v63, 16 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v2, 0xff, v2 -; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3 -; SI-NEXT: v_or_b32_e32 v2, v3, v2 -; SI-NEXT: v_or_b32_e32 v1, v1, v2 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x64, v0 +; SI-NEXT: s_or_b32 s5, s5, s8 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload -; SI-NEXT: v_add_i32_e32 v2, vcc, 0x68, v0 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 -; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: s_and_b32 s5, s70, 0xff -; SI-NEXT: s_lshl_b32 s5, s5, 16 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_or_b32 s5, s6, s5 -; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v1, vcc, 0x68, v0 +; SI-NEXT: v_mov_b32_e32 v2, s5 +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; SI-NEXT: s_and_b32 s5, s36, 0xff +; SI-NEXT: s_lshl_b32 s8, s15, 8 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: s_and_b32 s8, s19, 0xff +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: s_and_b32 s5, s5, 0xffff ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v57 -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload -; SI-NEXT: s_lshl_b32 s5, s96, 8 -; SI-NEXT: s_lshl_b32 s6, s80, 24 +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0 +; SI-NEXT: s_and_b32 s4, s4, 0xff +; SI-NEXT: v_readlane_b32 s61, v62, 35 +; SI-NEXT: v_readlane_b32 s43, v62, 47 +; SI-NEXT: v_readlane_b32 s27, v61, 7 +; SI-NEXT: v_readlane_b32 s21, v61, 13 +; SI-NEXT: v_readlane_b32 s17, v61, 19 +; SI-NEXT: v_readlane_b32 s99, v63, 35 +; SI-NEXT: v_readlane_b32 s98, v63, 34 +; SI-NEXT: v_readlane_b32 s97, v63, 33 ; SI-NEXT: v_readlane_b32 s96, v63, 32 +; SI-NEXT: v_readlane_b32 s87, v63, 31 +; SI-NEXT: v_readlane_b32 s86, v63, 30 +; SI-NEXT: v_readlane_b32 s85, v63, 29 +; SI-NEXT: v_readlane_b32 s84, v63, 28 +; SI-NEXT: v_readlane_b32 s83, v63, 27 +; SI-NEXT: v_readlane_b32 s82, v63, 26 +; SI-NEXT: v_readlane_b32 s81, v63, 25 ; SI-NEXT: v_readlane_b32 s80, v63, 24 +; SI-NEXT: v_readlane_b32 s71, v63, 23 ; SI-NEXT: v_readlane_b32 s70, v63, 22 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; SI-NEXT: v_or_b32_e32 v1, v1, v2 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; SI-NEXT: v_readlane_b32 s69, v63, 21 +; SI-NEXT: v_readlane_b32 s68, v63, 20 +; SI-NEXT: v_readlane_b32 s67, v63, 19 +; SI-NEXT: v_readlane_b32 s66, v63, 18 +; SI-NEXT: v_readlane_b32 s65, v63, 17 +; SI-NEXT: v_readlane_b32 s64, v63, 16 +; SI-NEXT: v_readlane_b32 s55, v63, 15 +; SI-NEXT: v_readlane_b32 s54, v63, 14 +; SI-NEXT: v_readlane_b32 s53, v63, 13 +; SI-NEXT: v_readlane_b32 s52, v63, 12 +; SI-NEXT: v_readlane_b32 s51, v63, 11 +; SI-NEXT: v_readlane_b32 s50, v63, 10 +; SI-NEXT: v_readlane_b32 s49, v63, 9 +; SI-NEXT: v_readlane_b32 s48, v63, 8 +; SI-NEXT: v_readlane_b32 s39, v63, 7 +; SI-NEXT: v_readlane_b32 s38, v63, 6 +; SI-NEXT: v_readlane_b32 s37, v63, 5 +; SI-NEXT: v_readlane_b32 s36, v63, 4 +; SI-NEXT: v_readlane_b32 s35, v63, 3 +; SI-NEXT: v_readlane_b32 s34, v63, 2 +; SI-NEXT: v_readlane_b32 s31, v63, 1 +; SI-NEXT: v_readlane_b32 s30, v63, 0 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v2, 0xff, v2 -; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; SI-NEXT: v_or_b32_e32 v2, v3, v2 -; SI-NEXT: v_or_b32_e32 v1, v1, v2 -; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0 +; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1 +; SI-NEXT: v_or_b32_e32 v1, s8, v1 +; SI-NEXT: v_readlane_b32 s8, v61, 20 +; SI-NEXT: v_or_b32_e32 v1, s5, v1 +; SI-NEXT: s_and_b32 s5, s10, 0xff +; SI-NEXT: v_readlane_b32 s9, v61, 21 +; SI-NEXT: s_lshl_b32 s8, s8, 8 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: v_readlane_b32 s8, v61, 22 +; SI-NEXT: v_readlane_b32 s9, v61, 23 +; SI-NEXT: s_and_b32 s8, s8, 0xff +; SI-NEXT: v_readlane_b32 s10, v61, 24 +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: s_lshl_b32 s9, s10, 24 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: s_or_b32 s8, s9, s8 +; SI-NEXT: s_or_b32 s5, s5, s8 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload -; SI-NEXT: v_add_i32_e32 v2, vcc, 0x70, v0 +; SI-NEXT: v_add_i32_e32 v1, vcc, 0x70, v0 +; SI-NEXT: v_mov_b32_e32 v2, s5 +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; SI-NEXT: s_and_b32 s5, s14, 0xff +; SI-NEXT: s_lshl_b32 s8, s12, 8 +; SI-NEXT: s_or_b32 s5, s5, s8 +; SI-NEXT: v_readlane_b32 s8, v61, 26 +; SI-NEXT: v_readlane_b32 s9, v61, 27 +; SI-NEXT: s_and_b32 s8, s9, 0xff +; SI-NEXT: s_lshl_b32 s8, s8, 16 +; SI-NEXT: s_and_b32 s5, s5, 0xffff +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0 +; SI-NEXT: v_readlane_b32 s11, v61, 25 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 +; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1 +; SI-NEXT: v_or_b32_e32 v1, s8, v1 +; SI-NEXT: v_readlane_b32 s8, v61, 28 +; SI-NEXT: v_readlane_b32 s9, v61, 29 ; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: s_and_b32 s5, s84, 0xff +; SI-NEXT: s_lshl_b32 s5, s8, 8 +; SI-NEXT: v_readlane_b32 s8, v61, 30 +; SI-NEXT: v_readlane_b32 s9, v61, 31 +; SI-NEXT: s_or_b32 s4, s4, s5 +; SI-NEXT: s_and_b32 s5, s8, 0xff +; SI-NEXT: v_readlane_b32 s8, v61, 32 ; SI-NEXT: s_lshl_b32 s5, s5, 16 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_or_b32 s5, s6, s5 -; SI-NEXT: v_or_b32_e32 v1, s5, v1 -; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v46 -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload -; SI-NEXT: s_lshl_b32 s5, s86, 24 -; SI-NEXT: v_readlane_b32 s86, v63, 30 -; SI-NEXT: v_readlane_b32 s84, v63, 28 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; SI-NEXT: v_or_b32_e32 v1, v1, v2 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v2, 0xff, v2 -; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; SI-NEXT: v_or_b32_e32 v2, v3, v2 -; SI-NEXT: v_or_b32_e32 v1, v1, v2 -; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0 +; SI-NEXT: s_lshl_b32 s8, s8, 24 +; SI-NEXT: s_and_b32 s4, s4, 0xffff +; SI-NEXT: s_or_b32 s5, s8, s5 +; SI-NEXT: s_or_b32 s4, s4, s5 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_add_i32_e32 v1, vcc, 0x78, v0 +; SI-NEXT: v_mov_b32_e32 v2, s4 +; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload -; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0 -; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v35 +; SI-NEXT: s_and_b32 s4, s88, 0xff +; SI-NEXT: s_lshl_b32 s5, s6, 8 +; SI-NEXT: s_or_b32 s4, s4, s5 +; SI-NEXT: s_and_b32 s5, s13, 0xff +; SI-NEXT: s_lshl_b32 s5, s5, 16 +; SI-NEXT: s_and_b32 s4, s4, 0xffff ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 +; SI-NEXT: v_readlane_b32 s9, v61, 33 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v1 -; SI-NEXT: v_or_b32_e32 v1, s4, v1 -; SI-NEXT: s_and_b32 s4, s98, 0xff -; SI-NEXT: s_lshl_b32 s4, s4, 16 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_or_b32 s4, s5, s4 +; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v1 +; SI-NEXT: v_or_b32_e32 v1, s5, v1 ; SI-NEXT: v_or_b32_e32 v1, s4, v1 -; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xff, v38 -; SI-NEXT: v_readlane_b32 s98, v63, 34 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; SI-NEXT: v_or_b32_e32 v1, v1, v2 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v2, 0xff, v2 -; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; SI-NEXT: v_or_b32_e32 v2, v3, v2 -; SI-NEXT: v_or_b32_e32 v1, v1, v2 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload ; SI-NEXT: s_or_saveexec_b64 s[4:5], -1 -; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload ; SI-NEXT: s_mov_b64 exec, s[4:5] ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) ; SI-NEXT: s_setpc_b64 s[30:31] @@ -168590,1043 +166146,1753 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; VI-LABEL: bitcast_v64bf16_to_v128i8_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: s_or_saveexec_b64 s[4:5], -1 -; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill +; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 +; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v63, s30, 0 -; VI-NEXT: v_writelane_b32 v63, s31, 1 -; VI-NEXT: v_writelane_b32 v63, s34, 2 -; VI-NEXT: v_writelane_b32 v63, s35, 3 -; VI-NEXT: v_writelane_b32 v63, s36, 4 -; VI-NEXT: v_writelane_b32 v63, s37, 5 -; VI-NEXT: v_writelane_b32 v63, s38, 6 -; VI-NEXT: v_writelane_b32 v63, s39, 7 -; VI-NEXT: v_writelane_b32 v63, s48, 8 -; VI-NEXT: v_writelane_b32 v63, s49, 9 -; VI-NEXT: v_writelane_b32 v63, s50, 10 -; VI-NEXT: v_writelane_b32 v63, s51, 11 -; VI-NEXT: v_writelane_b32 v63, s52, 12 -; VI-NEXT: v_writelane_b32 v63, s53, 13 -; VI-NEXT: v_writelane_b32 v63, s54, 14 -; VI-NEXT: v_writelane_b32 v63, s55, 15 -; VI-NEXT: v_writelane_b32 v63, s64, 16 -; VI-NEXT: v_writelane_b32 v63, s65, 17 -; VI-NEXT: v_writelane_b32 v63, s66, 18 -; VI-NEXT: v_writelane_b32 v63, s67, 19 -; VI-NEXT: v_writelane_b32 v63, s68, 20 -; VI-NEXT: v_writelane_b32 v63, s69, 21 -; VI-NEXT: v_writelane_b32 v63, s70, 22 -; VI-NEXT: v_writelane_b32 v63, s71, 23 -; VI-NEXT: v_writelane_b32 v63, s80, 24 -; VI-NEXT: v_writelane_b32 v63, s81, 25 -; VI-NEXT: v_writelane_b32 v63, s82, 26 -; VI-NEXT: v_writelane_b32 v63, s83, 27 -; VI-NEXT: v_writelane_b32 v63, s84, 28 -; VI-NEXT: v_writelane_b32 v63, s85, 29 -; VI-NEXT: v_writelane_b32 v63, s86, 30 +; VI-NEXT: v_writelane_b32 v20, s30, 0 +; VI-NEXT: v_writelane_b32 v20, s31, 1 +; VI-NEXT: v_writelane_b32 v20, s34, 2 +; VI-NEXT: v_writelane_b32 v20, s35, 3 +; VI-NEXT: v_writelane_b32 v20, s36, 4 +; VI-NEXT: v_writelane_b32 v20, s37, 5 +; VI-NEXT: v_writelane_b32 v20, s38, 6 +; VI-NEXT: v_writelane_b32 v20, s39, 7 +; VI-NEXT: v_writelane_b32 v20, s48, 8 +; VI-NEXT: v_writelane_b32 v20, s49, 9 +; VI-NEXT: v_writelane_b32 v20, s50, 10 +; VI-NEXT: v_writelane_b32 v20, s51, 11 +; VI-NEXT: v_writelane_b32 v20, s52, 12 +; VI-NEXT: v_writelane_b32 v20, s53, 13 +; VI-NEXT: v_writelane_b32 v20, s54, 14 +; VI-NEXT: v_writelane_b32 v20, s55, 15 +; VI-NEXT: v_writelane_b32 v20, s64, 16 +; VI-NEXT: v_writelane_b32 v20, s65, 17 +; VI-NEXT: v_writelane_b32 v20, s66, 18 +; VI-NEXT: v_writelane_b32 v20, s67, 19 +; VI-NEXT: v_writelane_b32 v20, s68, 20 +; VI-NEXT: v_writelane_b32 v20, s69, 21 +; VI-NEXT: v_writelane_b32 v20, s70, 22 +; VI-NEXT: v_writelane_b32 v20, s71, 23 +; VI-NEXT: v_writelane_b32 v20, s80, 24 +; VI-NEXT: v_writelane_b32 v20, s81, 25 +; VI-NEXT: v_writelane_b32 v20, s82, 26 +; VI-NEXT: v_writelane_b32 v20, s83, 27 +; VI-NEXT: v_writelane_b32 v20, s84, 28 +; VI-NEXT: v_writelane_b32 v20, s85, 29 +; VI-NEXT: v_readfirstlane_b32 s40, v3 +; VI-NEXT: v_mov_b32_e32 v3, s16 +; VI-NEXT: v_readfirstlane_b32 s41, v4 +; VI-NEXT: v_mov_b32_e32 v4, s17 +; VI-NEXT: v_readfirstlane_b32 s16, v5 +; VI-NEXT: v_mov_b32_e32 v5, s18 +; VI-NEXT: v_readfirstlane_b32 s17, v6 +; VI-NEXT: v_mov_b32_e32 v6, s19 +; VI-NEXT: v_readfirstlane_b32 s14, v7 +; VI-NEXT: v_mov_b32_e32 v7, s20 +; VI-NEXT: v_readfirstlane_b32 s15, v8 +; VI-NEXT: v_mov_b32_e32 v8, s21 +; VI-NEXT: v_readfirstlane_b32 s12, v9 +; VI-NEXT: v_mov_b32_e32 v9, s22 +; VI-NEXT: v_readfirstlane_b32 s13, v10 +; VI-NEXT: v_mov_b32_e32 v10, s23 +; VI-NEXT: v_readfirstlane_b32 s10, v11 +; VI-NEXT: v_mov_b32_e32 v11, s24 +; VI-NEXT: v_readfirstlane_b32 s11, v12 +; VI-NEXT: v_mov_b32_e32 v12, s25 +; VI-NEXT: v_readfirstlane_b32 s8, v13 +; VI-NEXT: v_mov_b32_e32 v13, s26 +; VI-NEXT: v_readfirstlane_b32 s9, v14 +; VI-NEXT: v_mov_b32_e32 v14, s27 +; VI-NEXT: v_readfirstlane_b32 s6, v15 +; VI-NEXT: v_mov_b32_e32 v15, s28 +; VI-NEXT: v_readfirstlane_b32 s7, v16 +; VI-NEXT: v_mov_b32_e32 v16, s29 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; VI-NEXT: v_writelane_b32 v63, s87, 31 +; VI-NEXT: v_writelane_b32 v20, s86, 30 +; VI-NEXT: v_readfirstlane_b32 s4, v17 +; VI-NEXT: v_readfirstlane_b32 s5, v18 ; VI-NEXT: v_readfirstlane_b32 s44, v3 ; VI-NEXT: v_readfirstlane_b32 s45, v4 ; VI-NEXT: v_readfirstlane_b32 s42, v5 ; VI-NEXT: v_readfirstlane_b32 s43, v6 -; VI-NEXT: v_readfirstlane_b32 s40, v7 -; VI-NEXT: v_readfirstlane_b32 s41, v8 -; VI-NEXT: v_readfirstlane_b32 s14, v9 -; VI-NEXT: v_readfirstlane_b32 s15, v10 -; VI-NEXT: v_readfirstlane_b32 s12, v11 -; VI-NEXT: v_readfirstlane_b32 s13, v12 -; VI-NEXT: v_readfirstlane_b32 s10, v13 -; VI-NEXT: v_readfirstlane_b32 s11, v14 -; VI-NEXT: v_readfirstlane_b32 s8, v15 -; VI-NEXT: v_readfirstlane_b32 s9, v16 -; VI-NEXT: v_readfirstlane_b32 s6, v17 -; VI-NEXT: v_readfirstlane_b32 s7, v18 -; VI-NEXT: v_readfirstlane_b32 s4, v1 +; VI-NEXT: v_readfirstlane_b32 s28, v7 +; VI-NEXT: v_readfirstlane_b32 s29, v8 +; VI-NEXT: v_readfirstlane_b32 s26, v9 +; VI-NEXT: v_readfirstlane_b32 s27, v10 +; VI-NEXT: v_readfirstlane_b32 s24, v11 +; VI-NEXT: v_readfirstlane_b32 s25, v12 +; VI-NEXT: v_readfirstlane_b32 s22, v13 +; VI-NEXT: v_readfirstlane_b32 s23, v14 +; VI-NEXT: v_readfirstlane_b32 s20, v15 +; VI-NEXT: v_readfirstlane_b32 s21, v16 +; VI-NEXT: v_readfirstlane_b32 s18, v1 ; VI-NEXT: s_and_b64 s[46:47], vcc, exec -; VI-NEXT: v_readfirstlane_b32 s5, v2 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill -; VI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane -; VI-NEXT: s_cbranch_scc0 .LBB91_3 +; VI-NEXT: v_readfirstlane_b32 s19, v2 +; VI-NEXT: v_writelane_b32 v20, s87, 31 +; VI-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane +; VI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane +; VI-NEXT: s_cbranch_scc0 .LBB91_4 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_lshr_b32 s46, s5, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 57 -; VI-NEXT: s_lshr_b32 s46, s5, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 56 -; VI-NEXT: s_lshr_b32 s46, s5, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 55 -; VI-NEXT: s_lshr_b32 s46, s4, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 54 -; VI-NEXT: s_lshr_b32 s46, s4, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 53 -; VI-NEXT: s_lshr_b32 s46, s29, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 52 -; VI-NEXT: s_lshr_b32 s46, s29, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 51 -; VI-NEXT: s_lshr_b32 s46, s29, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 50 -; VI-NEXT: s_lshr_b32 s46, s28, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 49 -; VI-NEXT: s_lshr_b32 s46, s28, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 48 -; VI-NEXT: s_lshr_b32 s46, s27, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 47 -; VI-NEXT: s_lshr_b32 s46, s27, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 46 -; VI-NEXT: s_lshr_b32 s46, s27, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 45 -; VI-NEXT: s_lshr_b32 s46, s26, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 44 -; VI-NEXT: s_lshr_b32 s46, s26, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 43 -; VI-NEXT: s_lshr_b32 s46, s25, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 42 -; VI-NEXT: s_lshr_b32 s46, s25, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 41 -; VI-NEXT: s_lshr_b32 s46, s25, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 40 -; VI-NEXT: s_lshr_b32 s46, s24, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 39 -; VI-NEXT: s_lshr_b32 s46, s24, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 38 -; VI-NEXT: s_lshr_b32 s46, s23, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 37 -; VI-NEXT: s_lshr_b32 s46, s23, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 36 -; VI-NEXT: s_lshr_b32 s46, s23, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 35 -; VI-NEXT: s_lshr_b32 s46, s22, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 34 -; VI-NEXT: s_lshr_b32 s46, s22, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 33 -; VI-NEXT: s_lshr_b32 s46, s21, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 32 -; VI-NEXT: s_lshr_b32 s46, s21, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 31 -; VI-NEXT: s_lshr_b32 s46, s21, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 30 -; VI-NEXT: s_lshr_b32 s46, s20, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 29 -; VI-NEXT: s_lshr_b32 s46, s20, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 28 ; VI-NEXT: s_lshr_b32 s46, s19, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 27 +; VI-NEXT: v_writelane_b32 v22, s46, 10 ; VI-NEXT: s_lshr_b32 s46, s19, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 26 +; VI-NEXT: v_writelane_b32 v22, s46, 11 ; VI-NEXT: s_lshr_b32 s46, s19, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 25 +; VI-NEXT: v_writelane_b32 v22, s46, 12 ; VI-NEXT: s_lshr_b32 s46, s18, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 24 +; VI-NEXT: v_writelane_b32 v22, s46, 13 ; VI-NEXT: s_lshr_b32 s46, s18, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 23 -; VI-NEXT: s_lshr_b32 s46, s17, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 22 -; VI-NEXT: s_lshr_b32 s46, s17, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 21 -; VI-NEXT: s_lshr_b32 s46, s17, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 20 -; VI-NEXT: s_lshr_b32 s46, s16, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 19 -; VI-NEXT: s_lshr_b32 s46, s16, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 18 +; VI-NEXT: v_writelane_b32 v22, s46, 14 +; VI-NEXT: s_lshr_b32 s46, s21, 24 +; VI-NEXT: v_writelane_b32 v22, s46, 15 +; VI-NEXT: s_lshr_b32 s46, s21, 16 +; VI-NEXT: v_writelane_b32 v22, s46, 16 +; VI-NEXT: s_lshr_b32 s46, s21, 8 +; VI-NEXT: v_writelane_b32 v22, s46, 17 +; VI-NEXT: s_lshr_b32 s46, s20, 16 +; VI-NEXT: v_writelane_b32 v22, s46, 18 +; VI-NEXT: s_lshr_b32 s46, s20, 8 +; VI-NEXT: v_writelane_b32 v22, s46, 19 +; VI-NEXT: s_lshr_b32 s46, s23, 24 +; VI-NEXT: v_writelane_b32 v22, s46, 20 +; VI-NEXT: s_lshr_b32 s46, s23, 16 +; VI-NEXT: v_writelane_b32 v22, s46, 21 +; VI-NEXT: s_lshr_b32 s46, s23, 8 +; VI-NEXT: v_writelane_b32 v22, s46, 22 +; VI-NEXT: s_lshr_b32 s46, s22, 16 +; VI-NEXT: v_writelane_b32 v22, s46, 23 +; VI-NEXT: s_lshr_b32 s46, s22, 8 +; VI-NEXT: v_writelane_b32 v22, s46, 24 +; VI-NEXT: s_lshr_b32 s46, s25, 24 +; VI-NEXT: v_writelane_b32 v22, s46, 25 +; VI-NEXT: s_lshr_b32 s46, s25, 16 +; VI-NEXT: v_writelane_b32 v22, s46, 26 +; VI-NEXT: s_lshr_b32 s46, s25, 8 +; VI-NEXT: v_writelane_b32 v22, s46, 27 +; VI-NEXT: s_lshr_b32 s46, s24, 16 +; VI-NEXT: v_writelane_b32 v22, s46, 28 +; VI-NEXT: s_lshr_b32 s46, s24, 8 +; VI-NEXT: v_writelane_b32 v22, s46, 29 +; VI-NEXT: s_lshr_b32 s46, s27, 24 +; VI-NEXT: v_writelane_b32 v22, s46, 30 +; VI-NEXT: s_lshr_b32 s46, s27, 16 +; VI-NEXT: v_writelane_b32 v22, s46, 31 +; VI-NEXT: s_lshr_b32 s46, s27, 8 +; VI-NEXT: v_writelane_b32 v22, s46, 32 +; VI-NEXT: s_lshr_b32 s46, s26, 16 +; VI-NEXT: v_writelane_b32 v22, s46, 33 +; VI-NEXT: s_lshr_b32 s46, s26, 8 +; VI-NEXT: v_writelane_b32 v22, s46, 34 +; VI-NEXT: s_lshr_b32 s46, s29, 24 +; VI-NEXT: v_writelane_b32 v22, s46, 35 +; VI-NEXT: s_lshr_b32 s46, s29, 16 +; VI-NEXT: v_writelane_b32 v22, s46, 36 +; VI-NEXT: s_lshr_b32 s46, s29, 8 +; VI-NEXT: v_writelane_b32 v22, s46, 37 +; VI-NEXT: s_lshr_b32 s46, s28, 16 +; VI-NEXT: v_writelane_b32 v22, s46, 38 +; VI-NEXT: s_lshr_b32 s46, s28, 8 +; VI-NEXT: v_writelane_b32 v22, s46, 39 +; VI-NEXT: s_lshr_b32 s46, s5, 24 +; VI-NEXT: v_writelane_b32 v22, s46, 40 +; VI-NEXT: s_lshr_b32 s46, s5, 16 +; VI-NEXT: v_writelane_b32 v22, s46, 41 +; VI-NEXT: s_lshr_b32 s46, s5, 8 +; VI-NEXT: v_writelane_b32 v22, s46, 42 +; VI-NEXT: s_lshr_b32 s46, s4, 16 +; VI-NEXT: v_writelane_b32 v22, s46, 43 +; VI-NEXT: s_lshr_b32 s46, s4, 8 +; VI-NEXT: v_writelane_b32 v22, s46, 44 ; VI-NEXT: s_lshr_b32 s46, s7, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 17 +; VI-NEXT: v_writelane_b32 v22, s46, 45 ; VI-NEXT: s_lshr_b32 s46, s7, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 16 +; VI-NEXT: v_writelane_b32 v22, s46, 46 ; VI-NEXT: s_lshr_b32 s46, s7, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 15 +; VI-NEXT: v_writelane_b32 v22, s46, 47 ; VI-NEXT: s_lshr_b32 s46, s6, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 14 +; VI-NEXT: v_writelane_b32 v22, s46, 48 ; VI-NEXT: s_lshr_b32 s46, s6, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 13 +; VI-NEXT: v_writelane_b32 v22, s46, 49 ; VI-NEXT: s_lshr_b32 s46, s9, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 12 +; VI-NEXT: v_writelane_b32 v22, s46, 50 ; VI-NEXT: s_lshr_b32 s46, s9, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 11 +; VI-NEXT: v_writelane_b32 v22, s46, 51 ; VI-NEXT: s_lshr_b32 s46, s9, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 10 +; VI-NEXT: v_writelane_b32 v22, s46, 52 ; VI-NEXT: s_lshr_b32 s46, s8, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 9 +; VI-NEXT: v_writelane_b32 v22, s46, 53 ; VI-NEXT: s_lshr_b32 s46, s8, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 8 +; VI-NEXT: v_writelane_b32 v22, s46, 54 ; VI-NEXT: s_lshr_b32 s46, s11, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 7 +; VI-NEXT: v_writelane_b32 v22, s46, 55 ; VI-NEXT: s_lshr_b32 s46, s11, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 6 +; VI-NEXT: v_writelane_b32 v22, s46, 56 ; VI-NEXT: s_lshr_b32 s46, s11, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 5 +; VI-NEXT: v_writelane_b32 v22, s46, 57 ; VI-NEXT: s_lshr_b32 s46, s10, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 4 +; VI-NEXT: v_writelane_b32 v22, s46, 58 ; VI-NEXT: s_lshr_b32 s46, s10, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 3 +; VI-NEXT: v_writelane_b32 v22, s46, 59 ; VI-NEXT: s_lshr_b32 s46, s13, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 2 +; VI-NEXT: v_writelane_b32 v22, s46, 60 ; VI-NEXT: s_lshr_b32 s46, s13, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 1 +; VI-NEXT: v_writelane_b32 v22, s46, 61 +; VI-NEXT: s_lshr_b32 s46, s13, 8 +; VI-NEXT: v_writelane_b32 v22, s46, 62 ; VI-NEXT: s_lshr_b32 s46, s12, 16 -; VI-NEXT: s_lshr_b32 s80, s13, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 0 -; VI-NEXT: s_lshr_b32 s81, s12, 8 -; VI-NEXT: s_lshr_b32 s82, s15, 24 -; VI-NEXT: s_lshr_b32 s83, s15, 16 -; VI-NEXT: s_lshr_b32 s85, s15, 8 -; VI-NEXT: s_lshr_b32 s84, s14, 16 -; VI-NEXT: s_lshr_b32 s86, s14, 8 -; VI-NEXT: s_lshr_b32 s87, s41, 24 -; VI-NEXT: s_lshr_b32 s50, s41, 16 -; VI-NEXT: s_lshr_b32 s52, s41, 8 -; VI-NEXT: s_lshr_b32 s51, s40, 16 -; VI-NEXT: s_lshr_b32 s53, s40, 8 -; VI-NEXT: s_lshr_b32 s54, s43, 24 -; VI-NEXT: s_lshr_b32 s55, s43, 16 -; VI-NEXT: s_lshr_b32 s65, s43, 8 -; VI-NEXT: s_lshr_b32 s64, s42, 16 -; VI-NEXT: s_lshr_b32 s66, s42, 8 -; VI-NEXT: s_lshr_b32 s67, s45, 24 -; VI-NEXT: s_lshr_b32 s68, s45, 16 -; VI-NEXT: s_lshr_b32 s70, s45, 8 -; VI-NEXT: s_lshr_b32 s69, s44, 16 -; VI-NEXT: s_lshr_b32 s71, s44, 8 -; VI-NEXT: s_lshr_b64 s[46:47], s[4:5], 24 -; VI-NEXT: s_lshr_b64 s[56:57], s[28:29], 24 -; VI-NEXT: s_lshr_b64 s[58:59], s[26:27], 24 -; VI-NEXT: s_lshr_b64 s[60:61], s[24:25], 24 -; VI-NEXT: s_lshr_b64 s[62:63], s[22:23], 24 -; VI-NEXT: s_lshr_b64 s[72:73], s[20:21], 24 -; VI-NEXT: s_lshr_b64 s[74:75], s[18:19], 24 -; VI-NEXT: s_lshr_b64 s[76:77], s[16:17], 24 -; VI-NEXT: s_lshr_b64 s[78:79], s[6:7], 24 -; VI-NEXT: s_lshr_b64 s[88:89], s[8:9], 24 -; VI-NEXT: s_lshr_b64 s[90:91], s[10:11], 24 -; VI-NEXT: s_lshr_b64 s[30:31], s[12:13], 24 -; VI-NEXT: s_lshr_b64 s[34:35], s[14:15], 24 -; VI-NEXT: s_lshr_b64 s[36:37], s[40:41], 24 -; VI-NEXT: s_lshr_b64 s[38:39], s[42:43], 24 -; VI-NEXT: s_lshr_b64 s[48:49], s[44:45], 24 -; VI-NEXT: s_cbranch_execnz .LBB91_4 +; VI-NEXT: v_writelane_b32 v22, s46, 63 +; VI-NEXT: s_lshr_b32 s46, s12, 8 +; VI-NEXT: s_lshr_b64 vcc, s[4:5], 24 +; VI-NEXT: v_writelane_b32 v21, s46, 0 +; VI-NEXT: s_lshr_b32 s46, s15, 24 +; VI-NEXT: v_writelane_b32 v22, vcc_lo, 8 +; VI-NEXT: v_writelane_b32 v21, s46, 1 +; VI-NEXT: s_lshr_b32 s46, s15, 16 +; VI-NEXT: v_writelane_b32 v22, vcc_hi, 9 +; VI-NEXT: s_lshr_b64 vcc, s[6:7], 24 +; VI-NEXT: v_writelane_b32 v21, s46, 2 +; VI-NEXT: s_lshr_b32 s46, s15, 8 +; VI-NEXT: v_writelane_b32 v22, vcc_lo, 6 +; VI-NEXT: v_writelane_b32 v21, s46, 3 +; VI-NEXT: s_lshr_b32 s46, s14, 16 +; VI-NEXT: v_writelane_b32 v22, vcc_hi, 7 +; VI-NEXT: s_lshr_b64 vcc, s[8:9], 24 +; VI-NEXT: v_writelane_b32 v21, s46, 4 +; VI-NEXT: s_lshr_b32 s46, s14, 8 +; VI-NEXT: v_writelane_b32 v22, vcc_lo, 4 +; VI-NEXT: v_writelane_b32 v21, s46, 5 +; VI-NEXT: s_lshr_b32 s46, s17, 24 +; VI-NEXT: v_writelane_b32 v22, vcc_hi, 5 +; VI-NEXT: s_lshr_b64 vcc, s[10:11], 24 +; VI-NEXT: v_writelane_b32 v21, s46, 6 +; VI-NEXT: s_lshr_b32 s46, s17, 16 +; VI-NEXT: v_writelane_b32 v22, vcc_lo, 2 +; VI-NEXT: v_writelane_b32 v21, s46, 7 +; VI-NEXT: s_lshr_b32 s46, s17, 8 +; VI-NEXT: v_writelane_b32 v22, vcc_hi, 3 +; VI-NEXT: s_lshr_b64 vcc, s[12:13], 24 +; VI-NEXT: v_writelane_b32 v21, s46, 8 +; VI-NEXT: s_lshr_b32 s46, s16, 16 +; VI-NEXT: v_writelane_b32 v22, vcc_lo, 0 +; VI-NEXT: s_lshr_b32 s47, s43, 24 +; VI-NEXT: s_lshr_b32 s57, s43, 16 +; VI-NEXT: s_lshr_b32 s61, s43, 8 +; VI-NEXT: s_lshr_b32 s75, s42, 16 +; VI-NEXT: s_lshr_b32 s79, s42, 8 +; VI-NEXT: s_lshr_b32 s89, s45, 24 +; VI-NEXT: s_lshr_b32 s91, s45, 16 +; VI-NEXT: s_lshr_b32 s31, s45, 8 +; VI-NEXT: s_lshr_b32 s37, s44, 16 +; VI-NEXT: s_lshr_b32 s49, s44, 8 +; VI-NEXT: v_writelane_b32 v21, s46, 9 +; VI-NEXT: s_lshr_b32 s59, s16, 8 +; VI-NEXT: s_lshr_b32 s63, s41, 24 +; VI-NEXT: s_lshr_b32 s73, s41, 16 +; VI-NEXT: s_lshr_b32 s77, s41, 8 +; VI-NEXT: s_lshr_b32 s53, s40, 16 +; VI-NEXT: s_lshr_b32 s65, s40, 8 +; VI-NEXT: s_lshr_b64 s[80:81], s[18:19], 24 +; VI-NEXT: s_lshr_b64 s[82:83], s[20:21], 24 +; VI-NEXT: s_lshr_b64 s[86:87], s[22:23], 24 +; VI-NEXT: s_lshr_b64 s[34:35], s[24:25], 24 +; VI-NEXT: s_lshr_b64 s[38:39], s[26:27], 24 +; VI-NEXT: s_lshr_b64 s[50:51], s[28:29], 24 +; VI-NEXT: s_lshr_b64 s[54:55], s[42:43], 24 +; VI-NEXT: s_lshr_b64 s[66:67], s[44:45], 24 +; VI-NEXT: v_writelane_b32 v22, vcc_hi, 1 +; VI-NEXT: s_lshr_b64 s[68:69], s[14:15], 24 +; VI-NEXT: s_lshr_b64 s[70:71], s[16:17], 24 +; VI-NEXT: s_lshr_b64 s[84:85], s[40:41], 24 +; VI-NEXT: s_mov_b32 s78, s45 +; VI-NEXT: s_mov_b32 s88, s43 +; VI-NEXT: s_mov_b32 s90, s29 +; VI-NEXT: s_mov_b32 s30, s27 +; VI-NEXT: s_mov_b32 s36, s25 +; VI-NEXT: s_mov_b32 s48, s23 +; VI-NEXT: s_mov_b32 s52, s21 +; VI-NEXT: s_mov_b32 s64, s19 +; VI-NEXT: s_mov_b32 s46, s41 +; VI-NEXT: s_mov_b32 s56, s17 +; VI-NEXT: s_mov_b32 s58, s15 +; VI-NEXT: s_mov_b32 s60, s13 +; VI-NEXT: s_mov_b32 s62, s11 +; VI-NEXT: s_mov_b32 s72, s9 +; VI-NEXT: s_mov_b32 s74, s7 +; VI-NEXT: s_mov_b32 s76, s5 +; VI-NEXT: s_cbranch_execnz .LBB91_3 ; VI-NEXT: .LBB91_2: ; %cmp.true -; VI-NEXT: s_lshl_b32 s46, s45, 16 -; VI-NEXT: v_mov_b32_e32 v31, 0x40c00000 -; VI-NEXT: v_add_f32_e32 v1, s46, v31 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s45, s45, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s45, v31 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 -; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; VI-NEXT: s_lshl_b32 s46, s41, 16 +; VI-NEXT: v_mov_b32_e32 v1, 0x40c00000 +; VI-NEXT: v_add_f32_e32 v2, s46, v1 +; VI-NEXT: v_readfirstlane_b32 s46, v2 +; VI-NEXT: s_bfe_u32 s47, s46, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s46 +; VI-NEXT: s_add_i32 s56, s47, 0x7fff +; VI-NEXT: s_or_b32 s57, s46, 0x400000 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s45, s44, 16 -; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s45, v31 -; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 -; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v1 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s44, s44, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc -; VI-NEXT: v_add_f32_e32 v3, s44, v31 -; VI-NEXT: v_bfe_u32 v4, v3, 16, 1 -; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3 -; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4 -; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; VI-NEXT: s_lshl_b32 s44, s43, 16 -; VI-NEXT: v_alignbit_b32 v1, v3, v1, 16 -; VI-NEXT: v_add_f32_e32 v3, s44, v31 -; VI-NEXT: v_bfe_u32 v4, v3, 16, 1 -; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3 -; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4 -; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; VI-NEXT: s_and_b32 s43, s43, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; VI-NEXT: v_add_f32_e32 v4, s43, v31 -; VI-NEXT: v_bfe_u32 v5, v4, 16, 1 -; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4 -; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 -; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc -; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; VI-NEXT: s_lshl_b32 s43, s42, 16 -; VI-NEXT: v_alignbit_b32 v4, v4, v3, 16 -; VI-NEXT: v_add_f32_e32 v3, s43, v31 -; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 -; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 -; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 -; VI-NEXT: v_or_b32_e32 v6, 0x400000, v3 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; VI-NEXT: s_and_b32 s42, s42, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc -; VI-NEXT: v_add_f32_e32 v5, s42, v31 -; VI-NEXT: v_bfe_u32 v6, v5, 16, 1 -; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v5 -; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6 -; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 -; VI-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc -; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5 -; VI-NEXT: s_lshl_b32 s42, s41, 16 -; VI-NEXT: v_alignbit_b32 v3, v5, v3, 16 -; VI-NEXT: v_add_f32_e32 v5, s42, v31 -; VI-NEXT: v_bfe_u32 v6, v5, 16, 1 -; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v5 -; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6 -; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 +; VI-NEXT: s_and_b64 s[46:47], vcc, exec +; VI-NEXT: s_cselect_b32 s46, s57, s56 ; VI-NEXT: s_and_b32 s41, s41, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc -; VI-NEXT: v_add_f32_e32 v6, s41, v31 -; VI-NEXT: v_bfe_u32 v7, v6, 16, 1 -; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v6 -; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7 -; VI-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 -; VI-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc -; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6 +; VI-NEXT: v_add_f32_e32 v2, s41, v1 +; VI-NEXT: v_readfirstlane_b32 s41, v2 +; VI-NEXT: s_bfe_u32 s47, s41, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s41 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s41, 22 +; VI-NEXT: s_and_b64 s[56:57], vcc, exec +; VI-NEXT: s_cselect_b32 s41, s41, s47 +; VI-NEXT: s_lshr_b32 s47, s41, 16 ; VI-NEXT: s_lshl_b32 s41, s40, 16 -; VI-NEXT: v_alignbit_b32 v6, v6, v5, 16 -; VI-NEXT: v_add_f32_e32 v5, s41, v31 -; VI-NEXT: v_bfe_u32 v7, v5, 16, 1 -; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5 -; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7 -; VI-NEXT: v_or_b32_e32 v8, 0x400000, v5 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 +; VI-NEXT: v_add_f32_e32 v2, s41, v1 +; VI-NEXT: s_lshr_b64 s[46:47], s[46:47], 16 +; VI-NEXT: v_readfirstlane_b32 s41, v2 +; VI-NEXT: s_bfe_u32 s47, s41, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s41 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s41, 22 +; VI-NEXT: s_and_b64 s[56:57], vcc, exec +; VI-NEXT: s_cselect_b32 s56, s41, s47 ; VI-NEXT: s_and_b32 s40, s40, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc -; VI-NEXT: v_add_f32_e32 v7, s40, v31 -; VI-NEXT: v_bfe_u32 v8, v7, 16, 1 -; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v7 -; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8 -; VI-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 -; VI-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc -; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7 -; VI-NEXT: s_lshl_b32 s40, s15, 16 -; VI-NEXT: v_alignbit_b32 v5, v7, v5, 16 -; VI-NEXT: v_add_f32_e32 v7, s40, v31 -; VI-NEXT: v_bfe_u32 v8, v7, 16, 1 -; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v7 -; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8 -; VI-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 +; VI-NEXT: v_add_f32_e32 v2, s40, v1 +; VI-NEXT: v_readfirstlane_b32 s40, v2 +; VI-NEXT: s_bfe_u32 s41, s40, 0x10010 +; VI-NEXT: s_add_i32 s41, s41, s40 +; VI-NEXT: s_add_i32 s47, s41, 0x7fff +; VI-NEXT: s_or_b32 s57, s40, 0x400000 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_and_b64 s[40:41], vcc, exec +; VI-NEXT: s_cselect_b32 s40, s57, s47 +; VI-NEXT: s_lshl_b32 s47, s17, 16 +; VI-NEXT: v_add_f32_e32 v2, s47, v1 +; VI-NEXT: s_lshr_b32 s57, s40, 16 +; VI-NEXT: v_readfirstlane_b32 s47, v2 +; VI-NEXT: s_lshr_b64 s[40:41], s[56:57], 16 +; VI-NEXT: s_bfe_u32 s56, s47, 0x10010 +; VI-NEXT: s_add_i32 s56, s56, s47 +; VI-NEXT: s_add_i32 s58, s56, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s47, 22 +; VI-NEXT: s_and_b64 s[56:57], vcc, exec +; VI-NEXT: s_cselect_b32 s56, s47, s58 +; VI-NEXT: s_and_b32 s17, s17, 0xffff0000 +; VI-NEXT: v_add_f32_e32 v2, s17, v1 +; VI-NEXT: v_readfirstlane_b32 s17, v2 +; VI-NEXT: s_bfe_u32 s47, s17, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s17 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s17, 22 +; VI-NEXT: s_and_b64 s[58:59], vcc, exec +; VI-NEXT: s_cselect_b32 s17, s17, s47 +; VI-NEXT: s_lshr_b32 s57, s17, 16 +; VI-NEXT: s_lshl_b32 s17, s16, 16 +; VI-NEXT: v_add_f32_e32 v2, s17, v1 +; VI-NEXT: v_readfirstlane_b32 s17, v2 +; VI-NEXT: s_bfe_u32 s47, s17, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s17 +; VI-NEXT: s_lshr_b64 s[56:57], s[56:57], 16 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s17, 22 +; VI-NEXT: s_and_b64 s[58:59], vcc, exec +; VI-NEXT: s_cselect_b32 s58, s17, s47 +; VI-NEXT: s_and_b32 s16, s16, 0xffff0000 +; VI-NEXT: v_add_f32_e32 v2, s16, v1 +; VI-NEXT: v_readfirstlane_b32 s16, v2 +; VI-NEXT: s_bfe_u32 s17, s16, 0x10010 +; VI-NEXT: s_add_i32 s17, s17, s16 +; VI-NEXT: s_add_i32 s47, s17, 0x7fff +; VI-NEXT: s_or_b32 s57, s16, 0x400000 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_and_b64 s[16:17], vcc, exec +; VI-NEXT: s_cselect_b32 s16, s57, s47 +; VI-NEXT: s_lshl_b32 s47, s15, 16 +; VI-NEXT: v_add_f32_e32 v2, s47, v1 +; VI-NEXT: v_readfirstlane_b32 s47, v2 +; VI-NEXT: s_bfe_u32 s57, s47, 0x10010 +; VI-NEXT: s_lshr_b32 s59, s16, 16 +; VI-NEXT: s_add_i32 s57, s57, s47 +; VI-NEXT: s_lshr_b64 s[16:17], s[58:59], 16 +; VI-NEXT: s_addk_i32 s57, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s47, 22 +; VI-NEXT: s_and_b64 s[58:59], vcc, exec +; VI-NEXT: s_cselect_b32 s58, s47, s57 ; VI-NEXT: s_and_b32 s15, s15, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc -; VI-NEXT: v_add_f32_e32 v8, s15, v31 -; VI-NEXT: v_bfe_u32 v9, v8, 16, 1 -; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8 -; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9 -; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8 -; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc -; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8 +; VI-NEXT: v_add_f32_e32 v2, s15, v1 +; VI-NEXT: v_readfirstlane_b32 s15, v2 +; VI-NEXT: s_bfe_u32 s47, s15, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s15 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s15, 22 +; VI-NEXT: s_and_b64 s[60:61], vcc, exec +; VI-NEXT: s_cselect_b32 s15, s15, s47 +; VI-NEXT: s_lshr_b32 s59, s15, 16 ; VI-NEXT: s_lshl_b32 s15, s14, 16 -; VI-NEXT: v_alignbit_b32 v8, v8, v7, 16 -; VI-NEXT: v_add_f32_e32 v7, s15, v31 -; VI-NEXT: v_bfe_u32 v9, v7, 16, 1 -; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7 -; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9 -; VI-NEXT: v_or_b32_e32 v10, 0x400000, v7 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 +; VI-NEXT: v_add_f32_e32 v2, s15, v1 +; VI-NEXT: v_readfirstlane_b32 s15, v2 +; VI-NEXT: s_bfe_u32 s47, s15, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s15 +; VI-NEXT: s_lshr_b64 s[58:59], s[58:59], 16 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s15, 22 +; VI-NEXT: s_and_b64 s[60:61], vcc, exec +; VI-NEXT: s_cselect_b32 s60, s15, s47 ; VI-NEXT: s_and_b32 s14, s14, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc -; VI-NEXT: v_add_f32_e32 v9, s14, v31 -; VI-NEXT: v_bfe_u32 v10, v9, 16, 1 -; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v9 -; VI-NEXT: v_add_u32_e32 v10, vcc, 0x7fff, v10 -; VI-NEXT: v_or_b32_e32 v11, 0x400000, v9 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 -; VI-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc -; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; VI-NEXT: s_lshl_b32 s14, s13, 16 -; VI-NEXT: v_alignbit_b32 v7, v9, v7, 16 -; VI-NEXT: v_add_f32_e32 v9, s14, v31 -; VI-NEXT: v_bfe_u32 v10, v9, 16, 1 -; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v9 -; VI-NEXT: v_add_u32_e32 v10, vcc, 0x7fff, v10 -; VI-NEXT: v_or_b32_e32 v11, 0x400000, v9 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 +; VI-NEXT: v_add_f32_e32 v2, s14, v1 +; VI-NEXT: v_readfirstlane_b32 s14, v2 +; VI-NEXT: s_bfe_u32 s15, s14, 0x10010 +; VI-NEXT: s_add_i32 s15, s15, s14 +; VI-NEXT: s_add_i32 s47, s15, 0x7fff +; VI-NEXT: s_or_b32 s57, s14, 0x400000 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_and_b64 s[14:15], vcc, exec +; VI-NEXT: s_cselect_b32 s14, s57, s47 +; VI-NEXT: s_lshl_b32 s47, s13, 16 +; VI-NEXT: v_add_f32_e32 v2, s47, v1 +; VI-NEXT: v_readfirstlane_b32 s47, v2 +; VI-NEXT: s_bfe_u32 s57, s47, 0x10010 +; VI-NEXT: s_lshr_b32 s61, s14, 16 +; VI-NEXT: s_add_i32 s57, s57, s47 +; VI-NEXT: s_lshr_b64 s[14:15], s[60:61], 16 +; VI-NEXT: s_addk_i32 s57, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s47, 22 +; VI-NEXT: s_and_b64 s[60:61], vcc, exec +; VI-NEXT: s_cselect_b32 s60, s47, s57 ; VI-NEXT: s_and_b32 s13, s13, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc -; VI-NEXT: v_add_f32_e32 v10, s13, v31 -; VI-NEXT: v_bfe_u32 v11, v10, 16, 1 -; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v10 -; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 -; VI-NEXT: v_or_b32_e32 v12, 0x400000, v10 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 -; VI-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc -; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v10 +; VI-NEXT: v_add_f32_e32 v2, s13, v1 +; VI-NEXT: v_readfirstlane_b32 s13, v2 +; VI-NEXT: s_bfe_u32 s47, s13, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s13 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s13, 22 +; VI-NEXT: s_and_b64 s[62:63], vcc, exec +; VI-NEXT: s_cselect_b32 s13, s13, s47 +; VI-NEXT: s_lshr_b32 s61, s13, 16 ; VI-NEXT: s_lshl_b32 s13, s12, 16 -; VI-NEXT: v_alignbit_b32 v10, v10, v9, 16 -; VI-NEXT: v_add_f32_e32 v9, s13, v31 -; VI-NEXT: v_bfe_u32 v11, v9, 16, 1 -; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9 -; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 -; VI-NEXT: v_or_b32_e32 v12, 0x400000, v9 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 +; VI-NEXT: v_add_f32_e32 v2, s13, v1 +; VI-NEXT: v_readfirstlane_b32 s13, v2 +; VI-NEXT: s_bfe_u32 s47, s13, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s13 +; VI-NEXT: s_lshr_b64 s[60:61], s[60:61], 16 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s13, 22 +; VI-NEXT: s_and_b64 s[62:63], vcc, exec +; VI-NEXT: s_cselect_b32 s62, s13, s47 ; VI-NEXT: s_and_b32 s12, s12, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v9, v11, v12, vcc -; VI-NEXT: v_add_f32_e32 v11, s12, v31 -; VI-NEXT: v_bfe_u32 v12, v11, 16, 1 -; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v11 -; VI-NEXT: v_add_u32_e32 v12, vcc, 0x7fff, v12 -; VI-NEXT: v_or_b32_e32 v13, 0x400000, v11 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 -; VI-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc -; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; VI-NEXT: s_lshl_b32 s12, s11, 16 -; VI-NEXT: v_alignbit_b32 v9, v11, v9, 16 -; VI-NEXT: v_add_f32_e32 v11, s12, v31 -; VI-NEXT: v_bfe_u32 v12, v11, 16, 1 -; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v11 -; VI-NEXT: v_add_u32_e32 v12, vcc, 0x7fff, v12 -; VI-NEXT: v_or_b32_e32 v13, 0x400000, v11 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 +; VI-NEXT: v_add_f32_e32 v2, s12, v1 +; VI-NEXT: v_readfirstlane_b32 s12, v2 +; VI-NEXT: s_bfe_u32 s13, s12, 0x10010 +; VI-NEXT: s_add_i32 s13, s13, s12 +; VI-NEXT: s_add_i32 s47, s13, 0x7fff +; VI-NEXT: s_or_b32 s57, s12, 0x400000 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_and_b64 s[12:13], vcc, exec +; VI-NEXT: s_cselect_b32 s12, s57, s47 +; VI-NEXT: s_lshl_b32 s47, s11, 16 +; VI-NEXT: v_add_f32_e32 v2, s47, v1 +; VI-NEXT: v_readfirstlane_b32 s47, v2 +; VI-NEXT: s_bfe_u32 s57, s47, 0x10010 +; VI-NEXT: s_lshr_b32 s63, s12, 16 +; VI-NEXT: s_add_i32 s57, s57, s47 +; VI-NEXT: s_lshr_b64 s[12:13], s[62:63], 16 +; VI-NEXT: s_addk_i32 s57, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s47, 22 +; VI-NEXT: s_and_b64 s[62:63], vcc, exec +; VI-NEXT: s_cselect_b32 s62, s47, s57 ; VI-NEXT: s_and_b32 s11, s11, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc -; VI-NEXT: v_add_f32_e32 v12, s11, v31 -; VI-NEXT: v_bfe_u32 v13, v12, 16, 1 -; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v12 -; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 -; VI-NEXT: v_or_b32_e32 v14, 0x400000, v12 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 -; VI-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc -; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v12 +; VI-NEXT: v_add_f32_e32 v2, s11, v1 +; VI-NEXT: v_readfirstlane_b32 s11, v2 +; VI-NEXT: s_bfe_u32 s47, s11, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s11 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s11, 22 +; VI-NEXT: s_and_b64 s[72:73], vcc, exec +; VI-NEXT: s_cselect_b32 s11, s11, s47 +; VI-NEXT: s_lshr_b32 s63, s11, 16 ; VI-NEXT: s_lshl_b32 s11, s10, 16 -; VI-NEXT: v_alignbit_b32 v12, v12, v11, 16 -; VI-NEXT: v_add_f32_e32 v11, s11, v31 -; VI-NEXT: v_bfe_u32 v13, v11, 16, 1 -; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11 -; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 -; VI-NEXT: v_or_b32_e32 v14, 0x400000, v11 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 +; VI-NEXT: v_add_f32_e32 v2, s11, v1 +; VI-NEXT: v_readfirstlane_b32 s11, v2 +; VI-NEXT: s_bfe_u32 s47, s11, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s11 +; VI-NEXT: s_lshr_b64 s[62:63], s[62:63], 16 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s11, 22 +; VI-NEXT: s_and_b64 s[72:73], vcc, exec +; VI-NEXT: s_cselect_b32 s72, s11, s47 ; VI-NEXT: s_and_b32 s10, s10, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc -; VI-NEXT: v_add_f32_e32 v13, s10, v31 -; VI-NEXT: v_bfe_u32 v14, v13, 16, 1 -; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v13 -; VI-NEXT: v_add_u32_e32 v14, vcc, 0x7fff, v14 -; VI-NEXT: v_or_b32_e32 v15, 0x400000, v13 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 -; VI-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc -; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v13 -; VI-NEXT: s_lshl_b32 s10, s9, 16 -; VI-NEXT: v_alignbit_b32 v11, v13, v11, 16 -; VI-NEXT: v_add_f32_e32 v13, s10, v31 -; VI-NEXT: v_bfe_u32 v14, v13, 16, 1 -; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v13 -; VI-NEXT: v_add_u32_e32 v14, vcc, 0x7fff, v14 -; VI-NEXT: v_or_b32_e32 v15, 0x400000, v13 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 +; VI-NEXT: v_add_f32_e32 v2, s10, v1 +; VI-NEXT: v_readfirstlane_b32 s10, v2 +; VI-NEXT: s_bfe_u32 s11, s10, 0x10010 +; VI-NEXT: s_add_i32 s11, s11, s10 +; VI-NEXT: s_add_i32 s47, s11, 0x7fff +; VI-NEXT: s_or_b32 s57, s10, 0x400000 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_and_b64 s[10:11], vcc, exec +; VI-NEXT: s_cselect_b32 s10, s57, s47 +; VI-NEXT: s_lshl_b32 s47, s9, 16 +; VI-NEXT: v_add_f32_e32 v2, s47, v1 +; VI-NEXT: v_readfirstlane_b32 s47, v2 +; VI-NEXT: s_bfe_u32 s57, s47, 0x10010 +; VI-NEXT: s_lshr_b32 s73, s10, 16 +; VI-NEXT: s_add_i32 s57, s57, s47 +; VI-NEXT: s_lshr_b64 s[10:11], s[72:73], 16 +; VI-NEXT: s_addk_i32 s57, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s47, 22 +; VI-NEXT: s_and_b64 s[72:73], vcc, exec +; VI-NEXT: s_cselect_b32 s72, s47, s57 ; VI-NEXT: s_and_b32 s9, s9, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc -; VI-NEXT: v_add_f32_e32 v14, s9, v31 -; VI-NEXT: v_bfe_u32 v15, v14, 16, 1 -; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v14 -; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 -; VI-NEXT: v_or_b32_e32 v16, 0x400000, v14 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 -; VI-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc -; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v14 +; VI-NEXT: v_add_f32_e32 v2, s9, v1 +; VI-NEXT: v_readfirstlane_b32 s9, v2 +; VI-NEXT: s_bfe_u32 s47, s9, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s9 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s9, 22 +; VI-NEXT: s_and_b64 s[74:75], vcc, exec +; VI-NEXT: s_cselect_b32 s9, s9, s47 +; VI-NEXT: s_lshr_b32 s73, s9, 16 ; VI-NEXT: s_lshl_b32 s9, s8, 16 -; VI-NEXT: v_alignbit_b32 v14, v14, v13, 16 -; VI-NEXT: v_add_f32_e32 v13, s9, v31 -; VI-NEXT: v_bfe_u32 v15, v13, 16, 1 -; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13 -; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 -; VI-NEXT: v_or_b32_e32 v16, 0x400000, v13 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 +; VI-NEXT: v_add_f32_e32 v2, s9, v1 +; VI-NEXT: v_readfirstlane_b32 s9, v2 +; VI-NEXT: s_bfe_u32 s47, s9, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s9 +; VI-NEXT: s_lshr_b64 s[72:73], s[72:73], 16 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s9, 22 +; VI-NEXT: s_and_b64 s[74:75], vcc, exec +; VI-NEXT: s_cselect_b32 s74, s9, s47 ; VI-NEXT: s_and_b32 s8, s8, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v13, v15, v16, vcc -; VI-NEXT: v_add_f32_e32 v15, s8, v31 -; VI-NEXT: v_bfe_u32 v16, v15, 16, 1 -; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15 -; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16 -; VI-NEXT: v_or_b32_e32 v17, 0x400000, v15 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 -; VI-NEXT: v_cndmask_b32_e32 v15, v16, v17, vcc -; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15 -; VI-NEXT: s_lshl_b32 s8, s7, 16 -; VI-NEXT: v_alignbit_b32 v13, v15, v13, 16 -; VI-NEXT: v_add_f32_e32 v15, s8, v31 -; VI-NEXT: v_bfe_u32 v16, v15, 16, 1 -; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15 -; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16 -; VI-NEXT: v_or_b32_e32 v17, 0x400000, v15 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 +; VI-NEXT: v_add_f32_e32 v2, s8, v1 +; VI-NEXT: v_readfirstlane_b32 s8, v2 +; VI-NEXT: s_bfe_u32 s9, s8, 0x10010 +; VI-NEXT: s_add_i32 s9, s9, s8 +; VI-NEXT: s_add_i32 s47, s9, 0x7fff +; VI-NEXT: s_or_b32 s57, s8, 0x400000 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_and_b64 s[8:9], vcc, exec +; VI-NEXT: s_cselect_b32 s8, s57, s47 +; VI-NEXT: s_lshl_b32 s47, s7, 16 +; VI-NEXT: v_add_f32_e32 v2, s47, v1 +; VI-NEXT: v_readfirstlane_b32 s47, v2 +; VI-NEXT: s_bfe_u32 s57, s47, 0x10010 +; VI-NEXT: s_lshr_b32 s75, s8, 16 +; VI-NEXT: s_add_i32 s57, s57, s47 +; VI-NEXT: s_lshr_b64 s[8:9], s[74:75], 16 +; VI-NEXT: s_addk_i32 s57, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s47, 22 +; VI-NEXT: s_and_b64 s[74:75], vcc, exec +; VI-NEXT: s_cselect_b32 s74, s47, s57 ; VI-NEXT: s_and_b32 s7, s7, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v15, v16, v17, vcc -; VI-NEXT: v_add_f32_e32 v16, s7, v31 -; VI-NEXT: v_bfe_u32 v17, v16, 16, 1 -; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16 -; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17 -; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16 -; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc -; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; VI-NEXT: v_add_f32_e32 v2, s7, v1 +; VI-NEXT: v_readfirstlane_b32 s7, v2 +; VI-NEXT: s_bfe_u32 s47, s7, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s7 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s7, 22 +; VI-NEXT: s_and_b64 s[76:77], vcc, exec +; VI-NEXT: s_cselect_b32 s7, s7, s47 +; VI-NEXT: s_lshr_b32 s75, s7, 16 ; VI-NEXT: s_lshl_b32 s7, s6, 16 -; VI-NEXT: v_alignbit_b32 v16, v16, v15, 16 -; VI-NEXT: v_add_f32_e32 v15, s7, v31 -; VI-NEXT: v_bfe_u32 v17, v15, 16, 1 -; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v15 -; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17 -; VI-NEXT: v_or_b32_e32 v18, 0x400000, v15 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 +; VI-NEXT: v_add_f32_e32 v2, s7, v1 +; VI-NEXT: v_readfirstlane_b32 s7, v2 +; VI-NEXT: s_bfe_u32 s47, s7, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s7 +; VI-NEXT: s_lshr_b64 s[74:75], s[74:75], 16 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s7, 22 +; VI-NEXT: s_and_b64 s[76:77], vcc, exec +; VI-NEXT: s_cselect_b32 s76, s7, s47 ; VI-NEXT: s_and_b32 s6, s6, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc -; VI-NEXT: v_add_f32_e32 v17, s6, v31 -; VI-NEXT: v_bfe_u32 v18, v17, 16, 1 -; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17 -; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18 -; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 -; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc -; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; VI-NEXT: s_lshl_b32 s6, s17, 16 -; VI-NEXT: v_alignbit_b32 v15, v17, v15, 16 -; VI-NEXT: v_add_f32_e32 v17, s6, v31 -; VI-NEXT: v_bfe_u32 v18, v17, 16, 1 -; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17 -; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18 -; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 -; VI-NEXT: s_and_b32 s6, s17, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc -; VI-NEXT: v_add_f32_e32 v18, s6, v31 -; VI-NEXT: v_bfe_u32 v19, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v18 -; VI-NEXT: v_add_u32_e32 v19, vcc, 0x7fff, v19 -; VI-NEXT: v_or_b32_e32 v20, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc -; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; VI-NEXT: s_lshl_b32 s6, s16, 16 -; VI-NEXT: v_alignbit_b32 v18, v18, v17, 16 -; VI-NEXT: v_add_f32_e32 v17, s6, v31 -; VI-NEXT: v_bfe_u32 v19, v17, 16, 1 -; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v17 -; VI-NEXT: v_add_u32_e32 v19, vcc, 0x7fff, v19 -; VI-NEXT: v_or_b32_e32 v20, 0x400000, v17 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 -; VI-NEXT: s_and_b32 s6, s16, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v17, v19, v20, vcc -; VI-NEXT: v_add_f32_e32 v19, s6, v31 -; VI-NEXT: v_bfe_u32 v20, v19, 16, 1 -; VI-NEXT: v_add_u32_e32 v20, vcc, v20, v19 -; VI-NEXT: v_add_u32_e32 v20, vcc, 0x7fff, v20 -; VI-NEXT: v_or_b32_e32 v21, 0x400000, v19 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 -; VI-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc -; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; VI-NEXT: s_lshl_b32 s6, s19, 16 -; VI-NEXT: v_alignbit_b32 v17, v19, v17, 16 -; VI-NEXT: v_add_f32_e32 v19, s6, v31 -; VI-NEXT: v_bfe_u32 v20, v19, 16, 1 -; VI-NEXT: v_add_u32_e32 v20, vcc, v20, v19 -; VI-NEXT: v_add_u32_e32 v20, vcc, 0x7fff, v20 -; VI-NEXT: v_or_b32_e32 v21, 0x400000, v19 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 -; VI-NEXT: s_and_b32 s6, s19, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc -; VI-NEXT: v_add_f32_e32 v20, s6, v31 -; VI-NEXT: v_bfe_u32 v21, v20, 16, 1 -; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v20 -; VI-NEXT: v_add_u32_e32 v21, vcc, 0x7fff, v21 -; VI-NEXT: v_or_b32_e32 v22, 0x400000, v20 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 -; VI-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc -; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; VI-NEXT: s_lshl_b32 s6, s18, 16 -; VI-NEXT: v_alignbit_b32 v20, v20, v19, 16 -; VI-NEXT: v_add_f32_e32 v19, s6, v31 -; VI-NEXT: v_bfe_u32 v21, v19, 16, 1 -; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v19 -; VI-NEXT: v_add_u32_e32 v21, vcc, 0x7fff, v21 -; VI-NEXT: v_or_b32_e32 v22, 0x400000, v19 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 -; VI-NEXT: s_and_b32 s6, s18, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v19, v21, v22, vcc -; VI-NEXT: v_add_f32_e32 v21, s6, v31 -; VI-NEXT: v_bfe_u32 v22, v21, 16, 1 -; VI-NEXT: v_add_u32_e32 v22, vcc, v22, v21 -; VI-NEXT: v_add_u32_e32 v22, vcc, 0x7fff, v22 -; VI-NEXT: v_or_b32_e32 v23, 0x400000, v21 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 -; VI-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc -; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; VI-NEXT: s_lshl_b32 s6, s21, 16 -; VI-NEXT: v_alignbit_b32 v19, v21, v19, 16 -; VI-NEXT: v_add_f32_e32 v21, s6, v31 -; VI-NEXT: v_bfe_u32 v22, v21, 16, 1 -; VI-NEXT: v_add_u32_e32 v22, vcc, v22, v21 -; VI-NEXT: v_add_u32_e32 v22, vcc, 0x7fff, v22 -; VI-NEXT: v_or_b32_e32 v23, 0x400000, v21 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 -; VI-NEXT: s_and_b32 s6, s21, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc -; VI-NEXT: v_add_f32_e32 v22, s6, v31 -; VI-NEXT: v_bfe_u32 v23, v22, 16, 1 -; VI-NEXT: v_add_u32_e32 v23, vcc, v23, v22 -; VI-NEXT: v_add_u32_e32 v23, vcc, 0x7fff, v23 -; VI-NEXT: v_or_b32_e32 v24, 0x400000, v22 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 -; VI-NEXT: v_cndmask_b32_e32 v22, v23, v24, vcc -; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v22 -; VI-NEXT: s_lshl_b32 s6, s20, 16 -; VI-NEXT: v_alignbit_b32 v22, v22, v21, 16 -; VI-NEXT: v_add_f32_e32 v21, s6, v31 -; VI-NEXT: v_bfe_u32 v23, v21, 16, 1 -; VI-NEXT: v_add_u32_e32 v23, vcc, v23, v21 -; VI-NEXT: v_add_u32_e32 v23, vcc, 0x7fff, v23 -; VI-NEXT: v_or_b32_e32 v24, 0x400000, v21 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 -; VI-NEXT: s_and_b32 s6, s20, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v21, v23, v24, vcc -; VI-NEXT: v_add_f32_e32 v23, s6, v31 -; VI-NEXT: v_bfe_u32 v24, v23, 16, 1 -; VI-NEXT: v_add_u32_e32 v24, vcc, v24, v23 -; VI-NEXT: v_add_u32_e32 v24, vcc, 0x7fff, v24 -; VI-NEXT: v_or_b32_e32 v25, 0x400000, v23 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 -; VI-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc -; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v23 -; VI-NEXT: s_lshl_b32 s6, s23, 16 -; VI-NEXT: v_alignbit_b32 v21, v23, v21, 16 -; VI-NEXT: v_add_f32_e32 v23, s6, v31 -; VI-NEXT: v_bfe_u32 v24, v23, 16, 1 -; VI-NEXT: v_add_u32_e32 v24, vcc, v24, v23 -; VI-NEXT: v_add_u32_e32 v24, vcc, 0x7fff, v24 -; VI-NEXT: v_or_b32_e32 v25, 0x400000, v23 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 -; VI-NEXT: s_and_b32 s6, s23, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc -; VI-NEXT: v_add_f32_e32 v24, s6, v31 -; VI-NEXT: v_bfe_u32 v25, v24, 16, 1 -; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v24 -; VI-NEXT: v_add_u32_e32 v25, vcc, 0x7fff, v25 -; VI-NEXT: v_or_b32_e32 v26, 0x400000, v24 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; VI-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc -; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; VI-NEXT: s_lshl_b32 s6, s22, 16 -; VI-NEXT: v_alignbit_b32 v24, v24, v23, 16 -; VI-NEXT: v_add_f32_e32 v23, s6, v31 -; VI-NEXT: v_bfe_u32 v25, v23, 16, 1 -; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v23 -; VI-NEXT: v_add_u32_e32 v25, vcc, 0x7fff, v25 -; VI-NEXT: v_or_b32_e32 v26, 0x400000, v23 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 -; VI-NEXT: s_and_b32 s6, s22, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v23, v25, v26, vcc -; VI-NEXT: v_add_f32_e32 v25, s6, v31 -; VI-NEXT: v_bfe_u32 v26, v25, 16, 1 -; VI-NEXT: v_add_u32_e32 v26, vcc, v26, v25 -; VI-NEXT: v_add_u32_e32 v26, vcc, 0x7fff, v26 -; VI-NEXT: v_or_b32_e32 v27, 0x400000, v25 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 -; VI-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc -; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 -; VI-NEXT: s_lshl_b32 s6, s25, 16 -; VI-NEXT: v_alignbit_b32 v23, v25, v23, 16 -; VI-NEXT: v_add_f32_e32 v25, s6, v31 -; VI-NEXT: v_bfe_u32 v26, v25, 16, 1 -; VI-NEXT: v_add_u32_e32 v26, vcc, v26, v25 -; VI-NEXT: v_add_u32_e32 v26, vcc, 0x7fff, v26 -; VI-NEXT: v_or_b32_e32 v27, 0x400000, v25 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 -; VI-NEXT: s_and_b32 s6, s25, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc -; VI-NEXT: v_add_f32_e32 v26, s6, v31 -; VI-NEXT: v_bfe_u32 v27, v26, 16, 1 -; VI-NEXT: v_add_u32_e32 v27, vcc, v27, v26 -; VI-NEXT: v_add_u32_e32 v27, vcc, 0x7fff, v27 -; VI-NEXT: v_or_b32_e32 v28, 0x400000, v26 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 -; VI-NEXT: v_cndmask_b32_e32 v26, v27, v28, vcc -; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v26 -; VI-NEXT: s_lshl_b32 s6, s24, 16 -; VI-NEXT: v_alignbit_b32 v26, v26, v25, 16 -; VI-NEXT: v_add_f32_e32 v25, s6, v31 -; VI-NEXT: v_bfe_u32 v27, v25, 16, 1 -; VI-NEXT: v_add_u32_e32 v27, vcc, v27, v25 -; VI-NEXT: v_add_u32_e32 v27, vcc, 0x7fff, v27 -; VI-NEXT: v_or_b32_e32 v28, 0x400000, v25 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 -; VI-NEXT: s_and_b32 s6, s24, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v25, v27, v28, vcc -; VI-NEXT: v_add_f32_e32 v27, s6, v31 -; VI-NEXT: v_bfe_u32 v28, v27, 16, 1 -; VI-NEXT: v_add_u32_e32 v28, vcc, v28, v27 -; VI-NEXT: v_add_u32_e32 v28, vcc, 0x7fff, v28 -; VI-NEXT: v_or_b32_e32 v29, 0x400000, v27 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 -; VI-NEXT: v_cndmask_b32_e32 v27, v28, v29, vcc -; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; VI-NEXT: s_lshl_b32 s6, s27, 16 -; VI-NEXT: v_alignbit_b32 v25, v27, v25, 16 -; VI-NEXT: v_add_f32_e32 v27, s6, v31 -; VI-NEXT: v_bfe_u32 v28, v27, 16, 1 -; VI-NEXT: v_add_u32_e32 v28, vcc, v28, v27 -; VI-NEXT: v_add_u32_e32 v28, vcc, 0x7fff, v28 -; VI-NEXT: v_or_b32_e32 v29, 0x400000, v27 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 -; VI-NEXT: s_and_b32 s6, s27, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v27, v28, v29, vcc -; VI-NEXT: v_add_f32_e32 v28, s6, v31 -; VI-NEXT: v_bfe_u32 v29, v28, 16, 1 -; VI-NEXT: v_add_u32_e32 v29, vcc, v29, v28 -; VI-NEXT: v_add_u32_e32 v29, vcc, 0x7fff, v29 -; VI-NEXT: v_or_b32_e32 v30, 0x400000, v28 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 -; VI-NEXT: v_cndmask_b32_e32 v28, v29, v30, vcc -; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v28 -; VI-NEXT: s_lshl_b32 s6, s26, 16 -; VI-NEXT: v_alignbit_b32 v28, v28, v27, 16 -; VI-NEXT: v_add_f32_e32 v27, s6, v31 -; VI-NEXT: v_bfe_u32 v29, v27, 16, 1 -; VI-NEXT: v_add_u32_e32 v29, vcc, v29, v27 -; VI-NEXT: v_add_u32_e32 v29, vcc, 0x7fff, v29 -; VI-NEXT: v_or_b32_e32 v30, 0x400000, v27 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 -; VI-NEXT: s_and_b32 s6, s26, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v27, v29, v30, vcc -; VI-NEXT: v_add_f32_e32 v29, s6, v31 -; VI-NEXT: v_bfe_u32 v30, v29, 16, 1 -; VI-NEXT: v_add_u32_e32 v30, vcc, v30, v29 -; VI-NEXT: v_add_u32_e32 v30, vcc, 0x7fff, v30 -; VI-NEXT: v_or_b32_e32 v32, 0x400000, v29 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 -; VI-NEXT: v_cndmask_b32_e32 v29, v30, v32, vcc -; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v29 -; VI-NEXT: s_lshl_b32 s6, s29, 16 -; VI-NEXT: v_alignbit_b32 v27, v29, v27, 16 -; VI-NEXT: v_add_f32_e32 v29, s6, v31 -; VI-NEXT: v_bfe_u32 v30, v29, 16, 1 -; VI-NEXT: v_add_u32_e32 v30, vcc, v30, v29 -; VI-NEXT: v_add_u32_e32 v30, vcc, 0x7fff, v30 -; VI-NEXT: v_or_b32_e32 v32, 0x400000, v29 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 -; VI-NEXT: s_and_b32 s6, s29, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v29, v30, v32, vcc -; VI-NEXT: v_add_f32_e32 v30, s6, v31 -; VI-NEXT: v_bfe_u32 v32, v30, 16, 1 -; VI-NEXT: v_add_u32_e32 v32, vcc, v32, v30 -; VI-NEXT: v_add_u32_e32 v32, vcc, 0x7fff, v32 -; VI-NEXT: v_or_b32_e32 v33, 0x400000, v30 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 -; VI-NEXT: v_cndmask_b32_e32 v30, v32, v33, vcc -; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; VI-NEXT: s_lshl_b32 s6, s28, 16 -; VI-NEXT: v_alignbit_b32 v30, v30, v29, 16 -; VI-NEXT: v_add_f32_e32 v29, s6, v31 -; VI-NEXT: v_bfe_u32 v32, v29, 16, 1 -; VI-NEXT: v_add_u32_e32 v32, vcc, v32, v29 -; VI-NEXT: v_add_u32_e32 v32, vcc, 0x7fff, v32 -; VI-NEXT: v_or_b32_e32 v33, 0x400000, v29 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 -; VI-NEXT: s_and_b32 s6, s28, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v29, v32, v33, vcc -; VI-NEXT: v_add_f32_e32 v32, s6, v31 -; VI-NEXT: v_bfe_u32 v33, v32, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 -; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; VI-NEXT: s_lshl_b32 s6, s5, 16 -; VI-NEXT: v_alignbit_b32 v29, v32, v29, 16 -; VI-NEXT: v_add_f32_e32 v32, s6, v31 -; VI-NEXT: v_bfe_u32 v33, v32, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v32 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v32 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 +; VI-NEXT: v_add_f32_e32 v2, s6, v1 +; VI-NEXT: v_readfirstlane_b32 s6, v2 +; VI-NEXT: s_bfe_u32 s7, s6, 0x10010 +; VI-NEXT: s_add_i32 s7, s7, s6 +; VI-NEXT: s_add_i32 s47, s7, 0x7fff +; VI-NEXT: s_or_b32 s57, s6, 0x400000 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_and_b64 s[6:7], vcc, exec +; VI-NEXT: s_cselect_b32 s6, s57, s47 +; VI-NEXT: s_lshl_b32 s47, s5, 16 +; VI-NEXT: v_add_f32_e32 v2, s47, v1 +; VI-NEXT: v_readfirstlane_b32 s47, v2 +; VI-NEXT: s_bfe_u32 s57, s47, 0x10010 +; VI-NEXT: s_lshr_b32 s77, s6, 16 +; VI-NEXT: s_add_i32 s57, s57, s47 +; VI-NEXT: s_lshr_b64 s[6:7], s[76:77], 16 +; VI-NEXT: s_addk_i32 s57, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s47, 22 +; VI-NEXT: s_and_b64 s[76:77], vcc, exec +; VI-NEXT: s_cselect_b32 s76, s47, s57 ; VI-NEXT: s_and_b32 s5, s5, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v32, v33, v34, vcc -; VI-NEXT: v_add_f32_e32 v33, s5, v31 -; VI-NEXT: v_bfe_u32 v34, v33, 16, 1 -; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33 -; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34 -; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33 -; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc -; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v33 +; VI-NEXT: v_add_f32_e32 v2, s5, v1 +; VI-NEXT: v_readfirstlane_b32 s5, v2 +; VI-NEXT: s_bfe_u32 s47, s5, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s5 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s5, 22 +; VI-NEXT: s_and_b64 s[78:79], vcc, exec +; VI-NEXT: s_cselect_b32 s5, s5, s47 +; VI-NEXT: s_lshr_b32 s77, s5, 16 ; VI-NEXT: s_lshl_b32 s5, s4, 16 -; VI-NEXT: v_alignbit_b32 v32, v33, v32, 16 -; VI-NEXT: v_add_f32_e32 v33, s5, v31 -; VI-NEXT: v_bfe_u32 v34, v33, 16, 1 -; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33 -; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34 +; VI-NEXT: v_add_f32_e32 v2, s5, v1 +; VI-NEXT: v_readfirstlane_b32 s5, v2 +; VI-NEXT: s_bfe_u32 s47, s5, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s5 +; VI-NEXT: s_lshr_b64 s[76:77], s[76:77], 16 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s5, 22 +; VI-NEXT: s_and_b64 s[78:79], vcc, exec +; VI-NEXT: s_cselect_b32 s78, s5, s47 ; VI-NEXT: s_and_b32 s4, s4, 0xffff0000 -; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33 -; VI-NEXT: v_add_f32_e32 v31, s4, v31 -; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc -; VI-NEXT: v_bfe_u32 v34, v31, 16, 1 -; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v31 -; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34 -; VI-NEXT: v_or_b32_e32 v35, 0x400000, v31 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31 -; VI-NEXT: v_cndmask_b32_e32 v31, v34, v35, vcc -; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; VI-NEXT: v_alignbit_b32 v31, v31, v33, 16 -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[31:32] -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[29:30] -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[27:28] -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[25:26] -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[21:22] -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[19:20] -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[17:18] -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[15:16] -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[13:14] -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[11:12] -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[9:10] -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[7:8] -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[5:6] -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[3:4] -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[33:34], 24, v[1:2] -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v32 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v32 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v32 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v31 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v31 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v30 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v30 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v30 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v29 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v29 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v28 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v28 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v28 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v27 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v27 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v26 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v26 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v26 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v25 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v25 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v24 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v24 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v24 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v23 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v23 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v22 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v22 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v22 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v21 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v21 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v20 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v20 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v20 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v19 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v19 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v18 -; VI-NEXT: v_lshrrev_b32_e32 v34, 24, v2 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v18 -; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v16 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v2 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v18 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v51, 24, v12 -; VI-NEXT: v_lshrrev_b32_e32 v35, 24, v8 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v2 -; VI-NEXT: v_lshrrev_b64 v[41:42], 24, v[23:24] -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v17 -; VI-NEXT: v_lshrrev_b32_e32 v45, 24, v16 -; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v16 -; VI-NEXT: v_lshrrev_b32_e32 v56, 8, v13 -; VI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v51, 8, v12 -; VI-NEXT: v_lshrrev_b32_e32 v57, 16, v9 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v8 -; VI-NEXT: v_lshrrev_b32_e32 v58, 8, v7 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v1 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v17 -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v15 -; VI-NEXT: v_lshrrev_b32_e32 v50, 8, v15 -; VI-NEXT: v_lshrrev_b32_e32 v43, 24, v14 -; VI-NEXT: v_lshrrev_b32_e32 v46, 16, v14 -; VI-NEXT: v_lshrrev_b32_e32 v48, 8, v14 -; VI-NEXT: v_lshrrev_b32_e32 v47, 16, v13 -; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v56, 16, v12 -; VI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v11 -; VI-NEXT: v_lshrrev_b32_e32 v53, 8, v11 -; VI-NEXT: v_lshrrev_b32_e32 v44, 24, v10 -; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v10 -; VI-NEXT: v_lshrrev_b32_e32 v40, 8, v10 -; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v9 -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v35, 8, v8 -; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v7 -; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v59, 24, v6 -; VI-NEXT: v_lshrrev_b32_e32 v58, 16, v6 -; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v6 -; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v5 -; VI-NEXT: v_lshrrev_b32_e32 v45, 8, v5 -; VI-NEXT: v_lshrrev_b32_e32 v42, 24, v4 -; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v4 -; VI-NEXT: v_lshrrev_b32_e32 v61, 8, v4 -; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v3 -; VI-NEXT: v_lshrrev_b32_e32 v49, 8, v3 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v1 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; VI-NEXT: s_branch .LBB91_5 -; VI-NEXT: .LBB91_3: +; VI-NEXT: v_add_f32_e32 v2, s4, v1 +; VI-NEXT: v_readfirstlane_b32 s4, v2 +; VI-NEXT: s_bfe_u32 s5, s4, 0x10010 +; VI-NEXT: s_add_i32 s5, s5, s4 +; VI-NEXT: s_add_i32 s47, s5, 0x7fff +; VI-NEXT: s_or_b32 s57, s4, 0x400000 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_and_b64 s[4:5], vcc, exec +; VI-NEXT: s_cselect_b32 s4, s57, s47 +; VI-NEXT: s_lshl_b32 s47, s45, 16 +; VI-NEXT: v_add_f32_e32 v2, s47, v1 +; VI-NEXT: v_readfirstlane_b32 s47, v2 +; VI-NEXT: s_bfe_u32 s57, s47, 0x10010 +; VI-NEXT: s_lshr_b32 s79, s4, 16 +; VI-NEXT: s_add_i32 s57, s57, s47 +; VI-NEXT: s_lshr_b64 s[4:5], s[78:79], 16 +; VI-NEXT: s_addk_i32 s57, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s47, 22 +; VI-NEXT: s_and_b64 s[78:79], vcc, exec +; VI-NEXT: s_cselect_b32 s78, s47, s57 +; VI-NEXT: s_and_b32 s45, s45, 0xffff0000 +; VI-NEXT: v_add_f32_e32 v2, s45, v1 +; VI-NEXT: v_readfirstlane_b32 s45, v2 +; VI-NEXT: s_bfe_u32 s47, s45, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s45 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s45, 22 +; VI-NEXT: s_and_b64 s[88:89], vcc, exec +; VI-NEXT: s_cselect_b32 s45, s45, s47 +; VI-NEXT: s_lshr_b32 s79, s45, 16 +; VI-NEXT: s_lshl_b32 s45, s44, 16 +; VI-NEXT: v_add_f32_e32 v2, s45, v1 +; VI-NEXT: v_readfirstlane_b32 s45, v2 +; VI-NEXT: s_bfe_u32 s47, s45, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s45 +; VI-NEXT: s_lshr_b64 s[78:79], s[78:79], 16 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s45, 22 +; VI-NEXT: s_and_b64 s[88:89], vcc, exec +; VI-NEXT: s_cselect_b32 s88, s45, s47 +; VI-NEXT: s_and_b32 s44, s44, 0xffff0000 +; VI-NEXT: v_add_f32_e32 v2, s44, v1 +; VI-NEXT: v_readfirstlane_b32 s44, v2 +; VI-NEXT: s_bfe_u32 s45, s44, 0x10010 +; VI-NEXT: s_add_i32 s45, s45, s44 +; VI-NEXT: s_add_i32 s47, s45, 0x7fff +; VI-NEXT: s_or_b32 s57, s44, 0x400000 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_and_b64 s[44:45], vcc, exec +; VI-NEXT: s_cselect_b32 s44, s57, s47 +; VI-NEXT: s_lshl_b32 s47, s43, 16 +; VI-NEXT: v_add_f32_e32 v2, s47, v1 +; VI-NEXT: v_readfirstlane_b32 s47, v2 +; VI-NEXT: s_bfe_u32 s57, s47, 0x10010 +; VI-NEXT: s_lshr_b32 s89, s44, 16 +; VI-NEXT: s_add_i32 s57, s57, s47 +; VI-NEXT: s_lshr_b64 s[44:45], s[88:89], 16 +; VI-NEXT: s_addk_i32 s57, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s47, 22 +; VI-NEXT: s_and_b64 s[88:89], vcc, exec +; VI-NEXT: s_cselect_b32 s88, s47, s57 +; VI-NEXT: s_and_b32 s43, s43, 0xffff0000 +; VI-NEXT: v_add_f32_e32 v2, s43, v1 +; VI-NEXT: v_readfirstlane_b32 s43, v2 +; VI-NEXT: s_bfe_u32 s47, s43, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s43 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s43, 22 +; VI-NEXT: s_and_b64 s[90:91], vcc, exec +; VI-NEXT: s_cselect_b32 s43, s43, s47 +; VI-NEXT: s_lshr_b32 s89, s43, 16 +; VI-NEXT: s_lshl_b32 s43, s42, 16 +; VI-NEXT: v_add_f32_e32 v2, s43, v1 +; VI-NEXT: v_readfirstlane_b32 s43, v2 +; VI-NEXT: s_bfe_u32 s47, s43, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s43 +; VI-NEXT: s_lshr_b64 s[88:89], s[88:89], 16 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s43, 22 +; VI-NEXT: s_and_b64 s[90:91], vcc, exec +; VI-NEXT: s_cselect_b32 s90, s43, s47 +; VI-NEXT: s_and_b32 s42, s42, 0xffff0000 +; VI-NEXT: v_add_f32_e32 v2, s42, v1 +; VI-NEXT: v_readfirstlane_b32 s42, v2 +; VI-NEXT: s_bfe_u32 s43, s42, 0x10010 +; VI-NEXT: s_add_i32 s43, s43, s42 +; VI-NEXT: s_add_i32 s47, s43, 0x7fff +; VI-NEXT: s_or_b32 s57, s42, 0x400000 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_and_b64 s[42:43], vcc, exec +; VI-NEXT: s_cselect_b32 s42, s57, s47 +; VI-NEXT: s_lshl_b32 s47, s29, 16 +; VI-NEXT: v_add_f32_e32 v2, s47, v1 +; VI-NEXT: v_readfirstlane_b32 s47, v2 +; VI-NEXT: s_bfe_u32 s57, s47, 0x10010 +; VI-NEXT: s_lshr_b32 s91, s42, 16 +; VI-NEXT: s_add_i32 s57, s57, s47 +; VI-NEXT: s_lshr_b64 s[42:43], s[90:91], 16 +; VI-NEXT: s_addk_i32 s57, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s47, 22 +; VI-NEXT: s_and_b64 s[90:91], vcc, exec +; VI-NEXT: s_cselect_b32 s90, s47, s57 +; VI-NEXT: s_and_b32 s29, s29, 0xffff0000 +; VI-NEXT: v_add_f32_e32 v2, s29, v1 +; VI-NEXT: v_readfirstlane_b32 s29, v2 +; VI-NEXT: s_bfe_u32 s47, s29, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s29 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s29, 22 +; VI-NEXT: s_and_b64 vcc, vcc, exec +; VI-NEXT: s_cselect_b32 s29, s29, s47 +; VI-NEXT: s_lshr_b32 s91, s29, 16 +; VI-NEXT: s_lshl_b32 s29, s28, 16 +; VI-NEXT: v_add_f32_e32 v2, s29, v1 +; VI-NEXT: v_readfirstlane_b32 s29, v2 +; VI-NEXT: s_bfe_u32 s47, s29, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s29 +; VI-NEXT: s_lshr_b64 s[90:91], s[90:91], 16 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s29, 22 +; VI-NEXT: s_and_b64 vcc, vcc, exec +; VI-NEXT: s_cselect_b32 s30, s29, s47 +; VI-NEXT: s_and_b32 s28, s28, 0xffff0000 +; VI-NEXT: v_add_f32_e32 v2, s28, v1 +; VI-NEXT: v_readfirstlane_b32 s28, v2 +; VI-NEXT: s_bfe_u32 s29, s28, 0x10010 +; VI-NEXT: s_add_i32 s29, s29, s28 +; VI-NEXT: s_add_i32 s47, s29, 0x7fff +; VI-NEXT: s_or_b32 s57, s28, 0x400000 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_and_b64 s[28:29], vcc, exec +; VI-NEXT: s_cselect_b32 s28, s57, s47 +; VI-NEXT: s_lshl_b32 s47, s27, 16 +; VI-NEXT: v_add_f32_e32 v2, s47, v1 +; VI-NEXT: v_readfirstlane_b32 s47, v2 +; VI-NEXT: s_bfe_u32 s57, s47, 0x10010 +; VI-NEXT: s_lshr_b32 s31, s28, 16 +; VI-NEXT: s_add_i32 s57, s57, s47 +; VI-NEXT: s_lshr_b64 s[28:29], s[30:31], 16 +; VI-NEXT: s_addk_i32 s57, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s47, 22 +; VI-NEXT: s_and_b64 vcc, vcc, exec +; VI-NEXT: s_cselect_b32 s30, s47, s57 +; VI-NEXT: s_and_b32 s27, s27, 0xffff0000 +; VI-NEXT: v_add_f32_e32 v2, s27, v1 +; VI-NEXT: v_readfirstlane_b32 s27, v2 +; VI-NEXT: s_bfe_u32 s47, s27, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s27 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s27, 22 +; VI-NEXT: s_and_b64 vcc, vcc, exec +; VI-NEXT: s_cselect_b32 s27, s27, s47 +; VI-NEXT: s_lshr_b32 s31, s27, 16 +; VI-NEXT: s_lshl_b32 s27, s26, 16 +; VI-NEXT: v_add_f32_e32 v2, s27, v1 +; VI-NEXT: v_readfirstlane_b32 s27, v2 +; VI-NEXT: s_bfe_u32 s47, s27, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s27 +; VI-NEXT: s_lshr_b64 s[30:31], s[30:31], 16 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s27, 22 +; VI-NEXT: s_and_b64 vcc, vcc, exec +; VI-NEXT: s_cselect_b32 s34, s27, s47 +; VI-NEXT: s_and_b32 s26, s26, 0xffff0000 +; VI-NEXT: v_add_f32_e32 v2, s26, v1 +; VI-NEXT: v_readfirstlane_b32 s26, v2 +; VI-NEXT: s_bfe_u32 s27, s26, 0x10010 +; VI-NEXT: s_add_i32 s27, s27, s26 +; VI-NEXT: s_add_i32 s47, s27, 0x7fff +; VI-NEXT: s_or_b32 s57, s26, 0x400000 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_and_b64 s[26:27], vcc, exec +; VI-NEXT: s_cselect_b32 s26, s57, s47 +; VI-NEXT: s_lshl_b32 s47, s25, 16 +; VI-NEXT: v_add_f32_e32 v2, s47, v1 +; VI-NEXT: v_readfirstlane_b32 s47, v2 +; VI-NEXT: s_bfe_u32 s57, s47, 0x10010 +; VI-NEXT: s_lshr_b32 s35, s26, 16 +; VI-NEXT: s_add_i32 s57, s57, s47 +; VI-NEXT: s_lshr_b64 s[26:27], s[34:35], 16 +; VI-NEXT: s_addk_i32 s57, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s47, 22 +; VI-NEXT: s_and_b64 vcc, vcc, exec +; VI-NEXT: s_cselect_b32 s34, s47, s57 +; VI-NEXT: s_and_b32 s25, s25, 0xffff0000 +; VI-NEXT: v_add_f32_e32 v2, s25, v1 +; VI-NEXT: v_readfirstlane_b32 s25, v2 +; VI-NEXT: s_bfe_u32 s47, s25, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s25 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s25, 22 +; VI-NEXT: s_and_b64 vcc, vcc, exec +; VI-NEXT: s_cselect_b32 s25, s25, s47 +; VI-NEXT: s_lshr_b32 s35, s25, 16 +; VI-NEXT: s_lshl_b32 s25, s24, 16 +; VI-NEXT: v_add_f32_e32 v2, s25, v1 +; VI-NEXT: v_readfirstlane_b32 s25, v2 +; VI-NEXT: s_bfe_u32 s47, s25, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s25 +; VI-NEXT: s_lshr_b64 s[36:37], s[34:35], 16 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s25, 22 +; VI-NEXT: s_and_b64 vcc, vcc, exec +; VI-NEXT: s_cselect_b32 s34, s25, s47 +; VI-NEXT: s_and_b32 s24, s24, 0xffff0000 +; VI-NEXT: v_add_f32_e32 v2, s24, v1 +; VI-NEXT: v_readfirstlane_b32 s24, v2 +; VI-NEXT: s_bfe_u32 s25, s24, 0x10010 +; VI-NEXT: s_add_i32 s25, s25, s24 +; VI-NEXT: s_add_i32 s47, s25, 0x7fff +; VI-NEXT: s_or_b32 s57, s24, 0x400000 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_and_b64 s[24:25], vcc, exec +; VI-NEXT: s_cselect_b32 s24, s57, s47 +; VI-NEXT: s_lshl_b32 s47, s23, 16 +; VI-NEXT: v_add_f32_e32 v2, s47, v1 +; VI-NEXT: v_readfirstlane_b32 s47, v2 +; VI-NEXT: s_bfe_u32 s57, s47, 0x10010 +; VI-NEXT: s_lshr_b32 s35, s24, 16 +; VI-NEXT: s_add_i32 s57, s57, s47 +; VI-NEXT: s_lshr_b64 s[24:25], s[34:35], 16 +; VI-NEXT: s_addk_i32 s57, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s47, 22 +; VI-NEXT: s_and_b64 vcc, vcc, exec +; VI-NEXT: s_cselect_b32 s34, s47, s57 +; VI-NEXT: s_and_b32 s23, s23, 0xffff0000 +; VI-NEXT: v_add_f32_e32 v2, s23, v1 +; VI-NEXT: v_readfirstlane_b32 s23, v2 +; VI-NEXT: s_bfe_u32 s47, s23, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s23 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s23, 22 +; VI-NEXT: s_and_b64 vcc, vcc, exec +; VI-NEXT: s_cselect_b32 s23, s23, s47 +; VI-NEXT: s_lshr_b32 s35, s23, 16 +; VI-NEXT: s_lshl_b32 s23, s22, 16 +; VI-NEXT: v_add_f32_e32 v2, s23, v1 +; VI-NEXT: v_readfirstlane_b32 s23, v2 +; VI-NEXT: s_bfe_u32 s47, s23, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s23 +; VI-NEXT: s_lshr_b64 s[48:49], s[34:35], 16 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s23, 22 +; VI-NEXT: s_and_b64 vcc, vcc, exec +; VI-NEXT: s_cselect_b32 s34, s23, s47 +; VI-NEXT: s_and_b32 s22, s22, 0xffff0000 +; VI-NEXT: v_add_f32_e32 v2, s22, v1 +; VI-NEXT: v_readfirstlane_b32 s22, v2 +; VI-NEXT: s_bfe_u32 s23, s22, 0x10010 +; VI-NEXT: s_add_i32 s23, s23, s22 +; VI-NEXT: s_add_i32 s47, s23, 0x7fff +; VI-NEXT: s_or_b32 s57, s22, 0x400000 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_and_b64 s[22:23], vcc, exec +; VI-NEXT: s_cselect_b32 s22, s57, s47 +; VI-NEXT: s_lshl_b32 s47, s21, 16 +; VI-NEXT: v_add_f32_e32 v2, s47, v1 +; VI-NEXT: v_readfirstlane_b32 s47, v2 +; VI-NEXT: s_bfe_u32 s57, s47, 0x10010 +; VI-NEXT: s_lshr_b32 s35, s22, 16 +; VI-NEXT: s_add_i32 s57, s57, s47 +; VI-NEXT: s_lshr_b64 s[22:23], s[34:35], 16 +; VI-NEXT: s_addk_i32 s57, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s47, 22 +; VI-NEXT: s_and_b64 vcc, vcc, exec +; VI-NEXT: s_cselect_b32 s34, s47, s57 +; VI-NEXT: s_and_b32 s21, s21, 0xffff0000 +; VI-NEXT: v_add_f32_e32 v2, s21, v1 +; VI-NEXT: v_readfirstlane_b32 s21, v2 +; VI-NEXT: s_bfe_u32 s47, s21, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s21 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s21, 22 +; VI-NEXT: s_and_b64 vcc, vcc, exec +; VI-NEXT: s_cselect_b32 s21, s21, s47 +; VI-NEXT: s_lshr_b32 s35, s21, 16 +; VI-NEXT: s_lshl_b32 s21, s20, 16 +; VI-NEXT: v_add_f32_e32 v2, s21, v1 +; VI-NEXT: v_readfirstlane_b32 s21, v2 +; VI-NEXT: s_bfe_u32 s47, s21, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s21 +; VI-NEXT: s_lshr_b64 s[52:53], s[34:35], 16 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s21, 22 +; VI-NEXT: s_and_b64 vcc, vcc, exec +; VI-NEXT: s_cselect_b32 s34, s21, s47 +; VI-NEXT: s_and_b32 s20, s20, 0xffff0000 +; VI-NEXT: v_add_f32_e32 v2, s20, v1 +; VI-NEXT: v_readfirstlane_b32 s20, v2 +; VI-NEXT: s_bfe_u32 s21, s20, 0x10010 +; VI-NEXT: s_add_i32 s21, s21, s20 +; VI-NEXT: s_add_i32 s47, s21, 0x7fff +; VI-NEXT: s_or_b32 s57, s20, 0x400000 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_and_b64 s[20:21], vcc, exec +; VI-NEXT: s_cselect_b32 s20, s57, s47 +; VI-NEXT: s_lshl_b32 s47, s19, 16 +; VI-NEXT: v_add_f32_e32 v2, s47, v1 +; VI-NEXT: v_readfirstlane_b32 s47, v2 +; VI-NEXT: s_bfe_u32 s57, s47, 0x10010 +; VI-NEXT: s_lshr_b32 s35, s20, 16 +; VI-NEXT: s_add_i32 s57, s57, s47 +; VI-NEXT: s_lshr_b64 s[20:21], s[34:35], 16 +; VI-NEXT: s_addk_i32 s57, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s47, 22 +; VI-NEXT: s_and_b64 vcc, vcc, exec +; VI-NEXT: s_cselect_b32 s34, s47, s57 +; VI-NEXT: s_and_b32 s19, s19, 0xffff0000 +; VI-NEXT: v_add_f32_e32 v2, s19, v1 +; VI-NEXT: v_readfirstlane_b32 s19, v2 +; VI-NEXT: s_bfe_u32 s47, s19, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s19 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s19, 22 +; VI-NEXT: s_and_b64 vcc, vcc, exec +; VI-NEXT: s_cselect_b32 s19, s19, s47 +; VI-NEXT: s_lshr_b32 s35, s19, 16 +; VI-NEXT: s_lshl_b32 s19, s18, 16 +; VI-NEXT: v_add_f32_e32 v2, s19, v1 +; VI-NEXT: v_readfirstlane_b32 s19, v2 +; VI-NEXT: s_bfe_u32 s47, s19, 0x10010 +; VI-NEXT: s_add_i32 s47, s47, s19 +; VI-NEXT: s_lshr_b64 s[64:65], s[34:35], 16 +; VI-NEXT: s_addk_i32 s47, 0x7fff +; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; VI-NEXT: s_bitset1_b32 s19, 22 +; VI-NEXT: s_and_b64 vcc, vcc, exec +; VI-NEXT: s_cselect_b32 s34, s19, s47 +; VI-NEXT: s_and_b32 s18, s18, 0xffff0000 +; VI-NEXT: v_add_f32_e32 v1, s18, v1 +; VI-NEXT: v_readfirstlane_b32 s18, v1 +; VI-NEXT: s_bfe_u32 s19, s18, 0x10010 +; VI-NEXT: s_add_i32 s19, s19, s18 +; VI-NEXT: s_add_i32 s47, s19, 0x7fff +; VI-NEXT: s_or_b32 s57, s18, 0x400000 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: s_and_b64 s[18:19], vcc, exec +; VI-NEXT: s_cselect_b32 s18, s57, s47 +; VI-NEXT: s_lshr_b32 s47, s64, 24 +; VI-NEXT: s_lshr_b32 s35, s18, 16 +; VI-NEXT: v_writelane_b32 v22, s47, 10 +; VI-NEXT: s_lshr_b32 s47, s64, 16 +; VI-NEXT: s_lshr_b64 s[18:19], s[34:35], 16 +; VI-NEXT: v_writelane_b32 v22, s47, 11 +; VI-NEXT: s_lshr_b32 s47, s64, 8 +; VI-NEXT: v_writelane_b32 v22, s47, 12 +; VI-NEXT: s_lshr_b32 s47, s18, 16 +; VI-NEXT: v_writelane_b32 v22, s47, 13 +; VI-NEXT: s_lshr_b32 s47, s18, 8 +; VI-NEXT: v_writelane_b32 v22, s47, 14 +; VI-NEXT: s_lshr_b32 s47, s52, 24 +; VI-NEXT: v_writelane_b32 v22, s47, 15 +; VI-NEXT: s_lshr_b32 s47, s52, 16 +; VI-NEXT: v_writelane_b32 v22, s47, 16 +; VI-NEXT: s_lshr_b32 s47, s52, 8 +; VI-NEXT: v_writelane_b32 v22, s47, 17 +; VI-NEXT: s_lshr_b32 s47, s20, 16 +; VI-NEXT: v_writelane_b32 v22, s47, 18 +; VI-NEXT: s_lshr_b32 s47, s20, 8 +; VI-NEXT: v_writelane_b32 v22, s47, 19 +; VI-NEXT: s_lshr_b32 s47, s48, 24 +; VI-NEXT: v_writelane_b32 v22, s47, 20 +; VI-NEXT: s_lshr_b32 s47, s48, 16 +; VI-NEXT: v_writelane_b32 v22, s47, 21 +; VI-NEXT: s_lshr_b32 s47, s48, 8 +; VI-NEXT: v_writelane_b32 v22, s47, 22 +; VI-NEXT: s_lshr_b32 s47, s22, 16 +; VI-NEXT: v_writelane_b32 v22, s47, 23 +; VI-NEXT: s_lshr_b32 s47, s22, 8 +; VI-NEXT: v_writelane_b32 v22, s47, 24 +; VI-NEXT: s_lshr_b32 s47, s36, 24 +; VI-NEXT: v_writelane_b32 v22, s47, 25 +; VI-NEXT: s_lshr_b32 s47, s36, 16 +; VI-NEXT: v_writelane_b32 v22, s47, 26 +; VI-NEXT: s_lshr_b32 s47, s36, 8 +; VI-NEXT: v_writelane_b32 v22, s47, 27 +; VI-NEXT: s_lshr_b32 s47, s24, 16 +; VI-NEXT: v_writelane_b32 v22, s47, 28 +; VI-NEXT: s_lshr_b32 s47, s24, 8 +; VI-NEXT: v_writelane_b32 v22, s47, 29 +; VI-NEXT: s_lshr_b32 s47, s30, 24 +; VI-NEXT: v_writelane_b32 v22, s47, 30 +; VI-NEXT: s_lshr_b32 s47, s30, 16 +; VI-NEXT: v_writelane_b32 v22, s47, 31 +; VI-NEXT: s_lshr_b32 s47, s30, 8 +; VI-NEXT: v_writelane_b32 v22, s47, 32 +; VI-NEXT: s_lshr_b32 s47, s26, 16 +; VI-NEXT: v_writelane_b32 v22, s47, 33 +; VI-NEXT: s_lshr_b32 s47, s26, 8 +; VI-NEXT: v_writelane_b32 v22, s47, 34 +; VI-NEXT: s_lshr_b32 s47, s90, 24 +; VI-NEXT: v_writelane_b32 v22, s47, 35 +; VI-NEXT: s_lshr_b32 s47, s90, 16 +; VI-NEXT: v_writelane_b32 v22, s47, 36 +; VI-NEXT: s_lshr_b32 s47, s90, 8 +; VI-NEXT: v_writelane_b32 v22, s47, 37 +; VI-NEXT: s_lshr_b32 s47, s28, 16 +; VI-NEXT: v_writelane_b32 v22, s47, 38 +; VI-NEXT: s_lshr_b32 s47, s28, 8 +; VI-NEXT: v_writelane_b32 v22, s47, 39 +; VI-NEXT: s_lshr_b32 s59, s76, 24 +; VI-NEXT: v_writelane_b32 v22, s59, 40 +; VI-NEXT: s_lshr_b32 s59, s76, 16 +; VI-NEXT: v_writelane_b32 v22, s59, 41 +; VI-NEXT: s_lshr_b32 s59, s76, 8 +; VI-NEXT: v_writelane_b32 v22, s59, 42 +; VI-NEXT: s_lshr_b32 s59, s4, 16 +; VI-NEXT: v_writelane_b32 v22, s59, 43 +; VI-NEXT: s_lshr_b32 s59, s4, 8 +; VI-NEXT: v_writelane_b32 v22, s59, 44 +; VI-NEXT: s_lshr_b32 s59, s74, 24 +; VI-NEXT: v_writelane_b32 v22, s59, 45 +; VI-NEXT: s_lshr_b32 s59, s74, 16 +; VI-NEXT: v_writelane_b32 v22, s59, 46 +; VI-NEXT: s_lshr_b32 s59, s74, 8 +; VI-NEXT: v_writelane_b32 v22, s59, 47 +; VI-NEXT: s_lshr_b32 s59, s6, 16 +; VI-NEXT: v_writelane_b32 v22, s59, 48 +; VI-NEXT: s_lshr_b32 s59, s6, 8 +; VI-NEXT: v_writelane_b32 v22, s59, 49 +; VI-NEXT: s_lshr_b32 s59, s72, 24 +; VI-NEXT: v_writelane_b32 v22, s59, 50 +; VI-NEXT: s_lshr_b32 s59, s72, 16 +; VI-NEXT: v_writelane_b32 v22, s59, 51 +; VI-NEXT: s_lshr_b32 s59, s72, 8 +; VI-NEXT: v_writelane_b32 v22, s59, 52 +; VI-NEXT: s_lshr_b32 s59, s8, 16 +; VI-NEXT: v_writelane_b32 v22, s59, 53 +; VI-NEXT: s_lshr_b32 s59, s8, 8 +; VI-NEXT: v_writelane_b32 v22, s59, 54 +; VI-NEXT: s_lshr_b32 s59, s62, 24 +; VI-NEXT: v_writelane_b32 v22, s59, 55 +; VI-NEXT: s_lshr_b32 s59, s62, 16 +; VI-NEXT: v_writelane_b32 v22, s59, 56 +; VI-NEXT: s_lshr_b32 s59, s62, 8 +; VI-NEXT: v_writelane_b32 v22, s59, 57 +; VI-NEXT: s_lshr_b32 s59, s10, 16 +; VI-NEXT: v_writelane_b32 v22, s59, 58 +; VI-NEXT: s_lshr_b32 s59, s10, 8 +; VI-NEXT: v_writelane_b32 v22, s59, 59 +; VI-NEXT: s_lshr_b32 s59, s60, 24 +; VI-NEXT: v_writelane_b32 v22, s59, 60 +; VI-NEXT: s_lshr_b32 s59, s60, 16 +; VI-NEXT: v_writelane_b32 v22, s59, 61 +; VI-NEXT: s_lshr_b32 s59, s60, 8 +; VI-NEXT: v_writelane_b32 v22, s59, 62 +; VI-NEXT: s_lshr_b32 s59, s12, 16 +; VI-NEXT: s_mov_b32 s5, s76 +; VI-NEXT: v_writelane_b32 v22, s59, 63 +; VI-NEXT: s_lshr_b32 s59, s12, 8 +; VI-NEXT: v_writelane_b32 v21, s59, 0 +; VI-NEXT: s_lshr_b32 s59, s58, 24 +; VI-NEXT: s_lshr_b64 vcc, s[4:5], 24 +; VI-NEXT: s_mov_b32 s7, s74 +; VI-NEXT: v_writelane_b32 v21, s59, 1 +; VI-NEXT: s_lshr_b32 s59, s58, 16 +; VI-NEXT: v_writelane_b32 v22, vcc_lo, 8 +; VI-NEXT: v_writelane_b32 v21, s59, 2 +; VI-NEXT: s_lshr_b32 s59, s58, 8 +; VI-NEXT: v_writelane_b32 v22, vcc_hi, 9 +; VI-NEXT: s_lshr_b64 vcc, s[6:7], 24 +; VI-NEXT: s_mov_b32 s9, s72 +; VI-NEXT: v_writelane_b32 v21, s59, 3 +; VI-NEXT: s_lshr_b32 s59, s14, 16 +; VI-NEXT: v_writelane_b32 v22, vcc_lo, 6 +; VI-NEXT: v_writelane_b32 v21, s59, 4 +; VI-NEXT: s_lshr_b32 s59, s14, 8 +; VI-NEXT: v_writelane_b32 v22, vcc_hi, 7 +; VI-NEXT: s_lshr_b64 vcc, s[8:9], 24 +; VI-NEXT: s_mov_b32 s11, s62 +; VI-NEXT: v_writelane_b32 v21, s59, 5 +; VI-NEXT: s_lshr_b32 s59, s56, 24 +; VI-NEXT: v_writelane_b32 v22, vcc_lo, 4 +; VI-NEXT: v_writelane_b32 v21, s59, 6 +; VI-NEXT: s_lshr_b32 s59, s56, 16 +; VI-NEXT: v_writelane_b32 v22, vcc_hi, 5 +; VI-NEXT: s_lshr_b64 vcc, s[10:11], 24 +; VI-NEXT: s_mov_b32 s13, s60 +; VI-NEXT: v_writelane_b32 v21, s59, 7 +; VI-NEXT: s_lshr_b32 s59, s56, 8 +; VI-NEXT: v_writelane_b32 v22, vcc_lo, 2 +; VI-NEXT: s_mov_b32 s41, s46 +; VI-NEXT: s_mov_b32 s17, s56 +; VI-NEXT: s_mov_b32 s15, s58 +; VI-NEXT: s_mov_b32 s45, s78 +; VI-NEXT: s_mov_b32 s43, s88 +; VI-NEXT: s_mov_b32 s29, s90 +; VI-NEXT: s_mov_b32 s27, s30 +; VI-NEXT: s_mov_b32 s25, s36 +; VI-NEXT: s_mov_b32 s23, s48 +; VI-NEXT: s_mov_b32 s21, s52 +; VI-NEXT: s_mov_b32 s19, s64 +; VI-NEXT: v_writelane_b32 v21, s59, 8 +; VI-NEXT: s_lshr_b32 s59, s16, 16 +; VI-NEXT: v_writelane_b32 v22, vcc_hi, 3 +; VI-NEXT: s_lshr_b64 vcc, s[12:13], 24 +; VI-NEXT: s_lshr_b32 s47, s88, 24 +; VI-NEXT: s_lshr_b32 s57, s88, 16 +; VI-NEXT: s_lshr_b32 s61, s88, 8 +; VI-NEXT: s_lshr_b32 s75, s42, 16 +; VI-NEXT: s_lshr_b32 s79, s42, 8 +; VI-NEXT: s_lshr_b32 s89, s78, 24 +; VI-NEXT: s_lshr_b32 s91, s78, 16 +; VI-NEXT: s_lshr_b32 s31, s78, 8 +; VI-NEXT: s_lshr_b32 s37, s44, 16 +; VI-NEXT: s_lshr_b32 s49, s44, 8 +; VI-NEXT: v_writelane_b32 v21, s59, 9 +; VI-NEXT: s_lshr_b32 s59, s16, 8 +; VI-NEXT: s_lshr_b32 s63, s46, 24 +; VI-NEXT: s_lshr_b32 s73, s46, 16 +; VI-NEXT: s_lshr_b32 s77, s46, 8 +; VI-NEXT: s_lshr_b32 s53, s40, 16 +; VI-NEXT: s_lshr_b32 s65, s40, 8 +; VI-NEXT: s_lshr_b64 s[80:81], s[18:19], 24 +; VI-NEXT: s_lshr_b64 s[82:83], s[20:21], 24 +; VI-NEXT: s_lshr_b64 s[86:87], s[22:23], 24 +; VI-NEXT: s_lshr_b64 s[34:35], s[24:25], 24 +; VI-NEXT: s_lshr_b64 s[38:39], s[26:27], 24 +; VI-NEXT: s_lshr_b64 s[50:51], s[28:29], 24 +; VI-NEXT: s_lshr_b64 s[54:55], s[42:43], 24 +; VI-NEXT: s_lshr_b64 s[66:67], s[44:45], 24 +; VI-NEXT: v_writelane_b32 v22, vcc_lo, 0 +; VI-NEXT: s_lshr_b64 s[68:69], s[14:15], 24 +; VI-NEXT: s_lshr_b64 s[70:71], s[16:17], 24 +; VI-NEXT: s_lshr_b64 s[84:85], s[40:41], 24 +; VI-NEXT: v_writelane_b32 v22, vcc_hi, 1 +; VI-NEXT: .LBB91_3: ; %end +; VI-NEXT: s_and_b32 s5, s44, 0xff +; VI-NEXT: s_lshl_b32 s7, s49, 8 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: s_lshl_b32 s7, s66, 8 +; VI-NEXT: s_and_b32 s9, s37, 0xff +; VI-NEXT: s_or_b32 s7, s9, s7 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_mov_b32_e32 v1, s5 +; VI-NEXT: s_and_b32 s5, s78, 0xff +; VI-NEXT: s_lshl_b32 s7, s31, 8 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: s_and_b32 s7, s91, 0xff +; VI-NEXT: s_lshl_b32 s9, s89, 8 +; VI-NEXT: s_or_b32 s7, s7, s9 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_mov_b32_e32 v2, s5 +; VI-NEXT: s_and_b32 s5, s42, 0xff +; VI-NEXT: s_lshl_b32 s7, s79, 8 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: s_lshl_b32 s7, s54, 8 +; VI-NEXT: s_and_b32 s9, s75, 0xff +; VI-NEXT: s_or_b32 s7, s9, s7 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_mov_b32_e32 v3, s5 +; VI-NEXT: s_and_b32 s5, s88, 0xff +; VI-NEXT: s_lshl_b32 s7, s61, 8 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: s_and_b32 s7, s57, 0xff +; VI-NEXT: s_lshl_b32 s9, s47, 8 +; VI-NEXT: s_or_b32 s7, s7, s9 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 39 +; VI-NEXT: v_mov_b32_e32 v4, s5 +; VI-NEXT: s_and_b32 s5, s28, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: v_readlane_b32 s9, v22, 38 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: s_lshl_b32 s7, s50, 8 +; VI-NEXT: s_and_b32 s9, s9, 0xff +; VI-NEXT: s_or_b32 s7, s9, s7 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 37 +; VI-NEXT: v_mov_b32_e32 v5, s5 +; VI-NEXT: s_and_b32 s5, s90, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 36 +; VI-NEXT: v_readlane_b32 s9, v22, 35 +; VI-NEXT: s_and_b32 s7, s7, 0xff +; VI-NEXT: s_lshl_b32 s9, s9, 8 +; VI-NEXT: s_or_b32 s7, s7, s9 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 34 +; VI-NEXT: v_mov_b32_e32 v6, s5 +; VI-NEXT: s_and_b32 s5, s26, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: v_readlane_b32 s9, v22, 33 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: s_lshl_b32 s7, s38, 8 +; VI-NEXT: s_and_b32 s9, s9, 0xff +; VI-NEXT: s_or_b32 s7, s9, s7 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 32 +; VI-NEXT: v_mov_b32_e32 v7, s5 +; VI-NEXT: s_and_b32 s5, s30, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 31 +; VI-NEXT: v_readlane_b32 s9, v22, 30 +; VI-NEXT: s_and_b32 s7, s7, 0xff +; VI-NEXT: s_lshl_b32 s9, s9, 8 +; VI-NEXT: s_or_b32 s7, s7, s9 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 29 +; VI-NEXT: v_mov_b32_e32 v8, s5 +; VI-NEXT: s_and_b32 s5, s24, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: v_readlane_b32 s9, v22, 28 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: s_lshl_b32 s7, s34, 8 +; VI-NEXT: s_and_b32 s9, s9, 0xff +; VI-NEXT: s_or_b32 s7, s9, s7 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 27 +; VI-NEXT: v_mov_b32_e32 v9, s5 +; VI-NEXT: s_and_b32 s5, s36, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 26 +; VI-NEXT: v_readlane_b32 s9, v22, 25 +; VI-NEXT: s_and_b32 s7, s7, 0xff +; VI-NEXT: s_lshl_b32 s9, s9, 8 +; VI-NEXT: s_or_b32 s7, s7, s9 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 24 +; VI-NEXT: v_mov_b32_e32 v10, s5 +; VI-NEXT: s_and_b32 s5, s22, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: v_readlane_b32 s9, v22, 23 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: s_lshl_b32 s7, s86, 8 +; VI-NEXT: s_and_b32 s9, s9, 0xff +; VI-NEXT: s_or_b32 s7, s9, s7 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 22 +; VI-NEXT: v_mov_b32_e32 v11, s5 +; VI-NEXT: s_and_b32 s5, s48, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 21 +; VI-NEXT: v_readlane_b32 s9, v22, 20 +; VI-NEXT: s_and_b32 s7, s7, 0xff +; VI-NEXT: s_lshl_b32 s9, s9, 8 +; VI-NEXT: s_or_b32 s7, s7, s9 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 19 +; VI-NEXT: v_mov_b32_e32 v12, s5 +; VI-NEXT: s_and_b32 s5, s20, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: v_readlane_b32 s9, v22, 18 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: s_lshl_b32 s7, s82, 8 +; VI-NEXT: s_and_b32 s9, s9, 0xff +; VI-NEXT: s_or_b32 s7, s9, s7 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 17 +; VI-NEXT: v_mov_b32_e32 v13, s5 +; VI-NEXT: s_and_b32 s5, s52, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 16 +; VI-NEXT: v_readlane_b32 s9, v22, 15 +; VI-NEXT: s_and_b32 s7, s7, 0xff +; VI-NEXT: s_lshl_b32 s9, s9, 8 +; VI-NEXT: s_or_b32 s7, s7, s9 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 14 +; VI-NEXT: v_mov_b32_e32 v14, s5 +; VI-NEXT: s_and_b32 s5, s18, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: v_readlane_b32 s9, v22, 13 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: s_lshl_b32 s7, s80, 8 +; VI-NEXT: s_and_b32 s9, s9, 0xff +; VI-NEXT: s_or_b32 s7, s9, s7 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 12 +; VI-NEXT: v_mov_b32_e32 v15, s5 +; VI-NEXT: s_and_b32 s5, s64, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 11 +; VI-NEXT: v_readlane_b32 s9, v22, 10 +; VI-NEXT: s_and_b32 s7, s7, 0xff +; VI-NEXT: s_lshl_b32 s9, s9, 8 +; VI-NEXT: s_or_b32 s7, s7, s9 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_mov_b32_e32 v16, s5 +; VI-NEXT: s_and_b32 s5, s40, 0xff +; VI-NEXT: s_lshl_b32 s7, s65, 8 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: s_lshl_b32 s7, s84, 8 +; VI-NEXT: s_and_b32 s9, s53, 0xff +; VI-NEXT: s_or_b32 s7, s9, s7 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v1, vcc, 4, v0 +; VI-NEXT: v_mov_b32_e32 v17, s5 +; VI-NEXT: s_and_b32 s5, s46, 0xff +; VI-NEXT: s_lshl_b32 s7, s77, 8 +; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v1, vcc, 8, v0 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: s_and_b32 s7, s73, 0xff +; VI-NEXT: s_lshl_b32 s9, s63, 8 +; VI-NEXT: buffer_store_dword v3, v1, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v1, vcc, 12, v0 +; VI-NEXT: s_or_b32 s7, s7, s9 +; VI-NEXT: buffer_store_dword v4, v1, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v1, vcc, 16, v0 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: buffer_store_dword v5, v1, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v1, vcc, 20, v0 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: buffer_store_dword v6, v1, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v1, vcc, 24, v0 +; VI-NEXT: v_mov_b32_e32 v18, s5 +; VI-NEXT: s_and_b32 s5, s16, 0xff +; VI-NEXT: s_lshl_b32 s7, s59, 8 +; VI-NEXT: buffer_store_dword v7, v1, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v1, vcc, 28, v0 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: buffer_store_dword v8, v1, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v1, vcc, 32, v0 +; VI-NEXT: v_readlane_b32 s7, v21, 9 +; VI-NEXT: buffer_store_dword v9, v1, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v1, vcc, 36, v0 +; VI-NEXT: s_and_b32 s7, s7, 0xff +; VI-NEXT: s_lshl_b32 s9, s70, 8 +; VI-NEXT: buffer_store_dword v10, v1, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v1, vcc, 40, v0 +; VI-NEXT: s_or_b32 s7, s7, s9 +; VI-NEXT: buffer_store_dword v11, v1, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v1, vcc, 44, v0 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: buffer_store_dword v12, v1, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v1, vcc, 48, v0 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v21, 8 +; VI-NEXT: buffer_store_dword v13, v1, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v1, vcc, 52, v0 +; VI-NEXT: v_mov_b32_e32 v2, s5 +; VI-NEXT: s_and_b32 s5, s56, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: buffer_store_dword v14, v1, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v1, vcc, 56, v0 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v21, 7 +; VI-NEXT: v_readlane_b32 s9, v21, 6 +; VI-NEXT: buffer_store_dword v15, v1, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v1, vcc, 60, v0 +; VI-NEXT: s_and_b32 s7, s7, 0xff +; VI-NEXT: s_lshl_b32 s9, s9, 8 +; VI-NEXT: buffer_store_dword v16, v1, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v1, vcc, 64, v0 +; VI-NEXT: s_or_b32 s7, s7, s9 +; VI-NEXT: buffer_store_dword v17, v1, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x44, v0 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: buffer_store_dword v18, v1, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x48, v0 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v21, 5 +; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; VI-NEXT: v_mov_b32_e32 v2, s5 +; VI-NEXT: s_and_b32 s5, s14, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v21, 4 +; VI-NEXT: s_and_b32 s7, s7, 0xff +; VI-NEXT: s_lshl_b32 s9, s68, 8 +; VI-NEXT: s_or_b32 s7, s7, s9 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x4c, v0 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v21, 3 +; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; VI-NEXT: v_mov_b32_e32 v2, s5 +; VI-NEXT: s_and_b32 s5, s58, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v21, 2 +; VI-NEXT: v_readlane_b32 s9, v21, 1 +; VI-NEXT: s_and_b32 s7, s7, 0xff +; VI-NEXT: s_lshl_b32 s9, s9, 8 +; VI-NEXT: s_or_b32 s7, s7, s9 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x50, v0 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v21, 0 +; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; VI-NEXT: v_mov_b32_e32 v2, s5 +; VI-NEXT: s_and_b32 s5, s12, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 63 +; VI-NEXT: v_readlane_b32 s12, v22, 0 +; VI-NEXT: s_and_b32 s7, s7, 0xff +; VI-NEXT: s_lshl_b32 s9, s12, 8 +; VI-NEXT: s_or_b32 s7, s7, s9 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x54, v0 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 62 +; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; VI-NEXT: v_mov_b32_e32 v2, s5 +; VI-NEXT: s_and_b32 s5, s60, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 61 +; VI-NEXT: v_readlane_b32 s9, v22, 60 +; VI-NEXT: s_and_b32 s7, s7, 0xff +; VI-NEXT: s_lshl_b32 s9, s9, 8 +; VI-NEXT: s_or_b32 s7, s7, s9 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x58, v0 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 59 +; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; VI-NEXT: v_mov_b32_e32 v2, s5 +; VI-NEXT: s_and_b32 s5, s10, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 58 +; VI-NEXT: v_readlane_b32 s10, v22, 2 +; VI-NEXT: s_and_b32 s7, s7, 0xff +; VI-NEXT: s_lshl_b32 s9, s10, 8 +; VI-NEXT: s_or_b32 s7, s7, s9 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x5c, v0 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 57 +; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; VI-NEXT: v_mov_b32_e32 v2, s5 +; VI-NEXT: s_and_b32 s5, s62, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 56 +; VI-NEXT: v_readlane_b32 s9, v22, 55 +; VI-NEXT: s_and_b32 s7, s7, 0xff +; VI-NEXT: s_lshl_b32 s9, s9, 8 +; VI-NEXT: s_or_b32 s7, s7, s9 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x60, v0 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 54 +; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; VI-NEXT: v_mov_b32_e32 v2, s5 +; VI-NEXT: s_and_b32 s5, s8, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 53 +; VI-NEXT: v_readlane_b32 s8, v22, 4 +; VI-NEXT: s_and_b32 s7, s7, 0xff +; VI-NEXT: s_lshl_b32 s8, s8, 8 +; VI-NEXT: s_or_b32 s7, s7, s8 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x64, v0 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 52 +; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; VI-NEXT: v_mov_b32_e32 v2, s5 +; VI-NEXT: s_and_b32 s5, s72, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: v_readlane_b32 s7, v22, 51 +; VI-NEXT: v_readlane_b32 s8, v22, 50 +; VI-NEXT: s_and_b32 s7, s7, 0xff +; VI-NEXT: s_lshl_b32 s8, s8, 8 +; VI-NEXT: s_or_b32 s7, s7, s8 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s7, s7, 16 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x68, v0 +; VI-NEXT: s_or_b32 s5, s5, s7 +; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; VI-NEXT: v_mov_b32_e32 v2, s5 +; VI-NEXT: s_and_b32 s5, s6, 0xff +; VI-NEXT: v_readlane_b32 s6, v22, 49 +; VI-NEXT: v_readlane_b32 s9, v22, 5 +; VI-NEXT: s_lshl_b32 s6, s6, 8 +; VI-NEXT: s_or_b32 s5, s5, s6 +; VI-NEXT: v_readlane_b32 s6, v22, 48 +; VI-NEXT: v_readlane_b32 s8, v22, 6 +; VI-NEXT: s_and_b32 s6, s6, 0xff +; VI-NEXT: s_lshl_b32 s7, s8, 8 +; VI-NEXT: s_or_b32 s6, s6, s7 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s6, s6, 16 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x6c, v0 +; VI-NEXT: s_or_b32 s5, s5, s6 +; VI-NEXT: v_readlane_b32 s6, v22, 47 +; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; VI-NEXT: v_mov_b32_e32 v2, s5 +; VI-NEXT: s_and_b32 s5, s74, 0xff +; VI-NEXT: s_lshl_b32 s6, s6, 8 +; VI-NEXT: s_or_b32 s5, s5, s6 +; VI-NEXT: v_readlane_b32 s6, v22, 46 +; VI-NEXT: v_readlane_b32 s7, v22, 45 +; VI-NEXT: s_and_b32 s6, s6, 0xff +; VI-NEXT: s_lshl_b32 s7, s7, 8 +; VI-NEXT: s_or_b32 s6, s6, s7 +; VI-NEXT: s_and_b32 s5, s5, 0xffff +; VI-NEXT: s_lshl_b32 s6, s6, 16 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x70, v0 +; VI-NEXT: s_or_b32 s5, s5, s6 +; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; VI-NEXT: v_mov_b32_e32 v2, s5 +; VI-NEXT: v_readlane_b32 s5, v22, 44 +; VI-NEXT: s_and_b32 s4, s4, 0xff +; VI-NEXT: s_lshl_b32 s5, s5, 8 +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: v_readlane_b32 s5, v22, 43 +; VI-NEXT: v_readlane_b32 s6, v22, 8 +; VI-NEXT: s_and_b32 s5, s5, 0xff +; VI-NEXT: s_lshl_b32 s6, s6, 8 +; VI-NEXT: s_or_b32 s5, s5, s6 +; VI-NEXT: s_and_b32 s4, s4, 0xffff +; VI-NEXT: s_lshl_b32 s5, s5, 16 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x74, v0 +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: v_readlane_b32 s5, v22, 42 +; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; VI-NEXT: v_mov_b32_e32 v2, s4 +; VI-NEXT: s_and_b32 s4, s76, 0xff +; VI-NEXT: s_lshl_b32 s5, s5, 8 +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: v_readlane_b32 s5, v22, 41 +; VI-NEXT: v_readlane_b32 s6, v22, 40 +; VI-NEXT: s_and_b32 s5, s5, 0xff +; VI-NEXT: s_lshl_b32 s6, s6, 8 +; VI-NEXT: s_or_b32 s5, s5, s6 +; VI-NEXT: s_and_b32 s4, s4, 0xffff +; VI-NEXT: s_lshl_b32 s5, s5, 16 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x78, v0 +; VI-NEXT: s_or_b32 s4, s4, s5 +; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen +; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0 +; VI-NEXT: v_mov_b32_e32 v1, s4 +; VI-NEXT: v_readlane_b32 s13, v22, 1 +; VI-NEXT: v_readlane_b32 s11, v22, 3 +; VI-NEXT: v_readlane_b32 s9, v22, 7 +; VI-NEXT: v_readlane_b32 s7, v22, 9 +; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen +; VI-NEXT: v_readlane_b32 s87, v20, 31 +; VI-NEXT: v_readlane_b32 s86, v20, 30 +; VI-NEXT: v_readlane_b32 s85, v20, 29 +; VI-NEXT: v_readlane_b32 s84, v20, 28 +; VI-NEXT: v_readlane_b32 s83, v20, 27 +; VI-NEXT: v_readlane_b32 s82, v20, 26 +; VI-NEXT: v_readlane_b32 s81, v20, 25 +; VI-NEXT: v_readlane_b32 s80, v20, 24 +; VI-NEXT: v_readlane_b32 s71, v20, 23 +; VI-NEXT: v_readlane_b32 s70, v20, 22 +; VI-NEXT: v_readlane_b32 s69, v20, 21 +; VI-NEXT: v_readlane_b32 s68, v20, 20 +; VI-NEXT: v_readlane_b32 s67, v20, 19 +; VI-NEXT: v_readlane_b32 s66, v20, 18 +; VI-NEXT: v_readlane_b32 s65, v20, 17 +; VI-NEXT: v_readlane_b32 s64, v20, 16 +; VI-NEXT: v_readlane_b32 s55, v20, 15 +; VI-NEXT: v_readlane_b32 s54, v20, 14 +; VI-NEXT: v_readlane_b32 s53, v20, 13 +; VI-NEXT: v_readlane_b32 s52, v20, 12 +; VI-NEXT: v_readlane_b32 s51, v20, 11 +; VI-NEXT: v_readlane_b32 s50, v20, 10 +; VI-NEXT: v_readlane_b32 s49, v20, 9 +; VI-NEXT: v_readlane_b32 s48, v20, 8 +; VI-NEXT: v_readlane_b32 s39, v20, 7 +; VI-NEXT: v_readlane_b32 s38, v20, 6 +; VI-NEXT: v_readlane_b32 s37, v20, 5 +; VI-NEXT: v_readlane_b32 s36, v20, 4 +; VI-NEXT: v_readlane_b32 s35, v20, 3 +; VI-NEXT: v_readlane_b32 s34, v20, 2 +; VI-NEXT: v_readlane_b32 s31, v20, 1 +; VI-NEXT: v_readlane_b32 s30, v20, 0 +; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1 +; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; VI-NEXT: s_mov_b64 exec, s[4:5] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_setpc_b64 s[30:31] +; VI-NEXT: .LBB91_4: ; VI-NEXT: ; implicit-def: $sgpr46 ; VI-NEXT: ; kill: killed $sgpr46 +; VI-NEXT: ; implicit-def: $sgpr61 +; VI-NEXT: ; implicit-def: $sgpr60 +; VI-NEXT: ; implicit-def: $sgpr63 +; VI-NEXT: ; implicit-def: $sgpr62 +; VI-NEXT: ; implicit-def: $sgpr73 +; VI-NEXT: ; implicit-def: $sgpr72 +; VI-NEXT: ; implicit-def: $sgpr75 +; VI-NEXT: ; implicit-def: $sgpr74 +; VI-NEXT: ; implicit-def: $sgpr77 +; VI-NEXT: ; implicit-def: $sgpr76 ; VI-NEXT: ; implicit-def: $sgpr46 ; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr71 -; VI-NEXT: ; implicit-def: $sgpr69 -; VI-NEXT: ; implicit-def: $sgpr70 -; VI-NEXT: ; implicit-def: $sgpr68 -; VI-NEXT: ; implicit-def: $sgpr67 -; VI-NEXT: ; implicit-def: $sgpr66 -; VI-NEXT: ; implicit-def: $sgpr64 +; VI-NEXT: v_writelane_b32 v22, s60, 0 +; VI-NEXT: ; implicit-def: $sgpr46 +; VI-NEXT: ; kill: killed $sgpr46 +; VI-NEXT: v_writelane_b32 v22, s61, 1 +; VI-NEXT: ; implicit-def: $sgpr46 +; VI-NEXT: ; kill: killed $sgpr46 +; VI-NEXT: v_writelane_b32 v22, s62, 2 +; VI-NEXT: ; implicit-def: $sgpr46 +; VI-NEXT: ; kill: killed $sgpr46 +; VI-NEXT: v_writelane_b32 v22, s63, 3 +; VI-NEXT: ; implicit-def: $sgpr46 +; VI-NEXT: ; kill: killed $sgpr46 +; VI-NEXT: v_writelane_b32 v22, s72, 4 +; VI-NEXT: ; implicit-def: $sgpr46 +; VI-NEXT: ; kill: killed $sgpr46 +; VI-NEXT: v_writelane_b32 v22, s73, 5 +; VI-NEXT: ; implicit-def: $sgpr46 +; VI-NEXT: ; kill: killed $sgpr46 +; VI-NEXT: v_writelane_b32 v22, s74, 6 +; VI-NEXT: ; implicit-def: $sgpr46 +; VI-NEXT: ; kill: killed $sgpr46 +; VI-NEXT: v_writelane_b32 v22, s75, 7 +; VI-NEXT: ; implicit-def: $sgpr46 +; VI-NEXT: ; kill: killed $sgpr46 +; VI-NEXT: v_writelane_b32 v22, s76, 8 +; VI-NEXT: ; implicit-def: $sgpr46 +; VI-NEXT: ; kill: killed $sgpr46 +; VI-NEXT: ; implicit-def: $sgpr49 +; VI-NEXT: ; implicit-def: $sgpr37 +; VI-NEXT: ; implicit-def: $sgpr31 +; VI-NEXT: ; implicit-def: $sgpr91 +; VI-NEXT: ; implicit-def: $sgpr89 +; VI-NEXT: ; implicit-def: $sgpr79 +; VI-NEXT: ; implicit-def: $sgpr57 +; VI-NEXT: ; implicit-def: $sgpr47 ; VI-NEXT: ; implicit-def: $sgpr65 -; VI-NEXT: ; implicit-def: $sgpr55 -; VI-NEXT: ; implicit-def: $sgpr54 ; VI-NEXT: ; implicit-def: $sgpr53 -; VI-NEXT: ; implicit-def: $sgpr51 -; VI-NEXT: ; implicit-def: $sgpr52 +; VI-NEXT: ; implicit-def: $sgpr59 +; VI-NEXT: ; implicit-def: $sgpr66 +; VI-NEXT: ; implicit-def: $sgpr78 +; VI-NEXT: ; implicit-def: $sgpr54 +; VI-NEXT: ; implicit-def: $sgpr88 ; VI-NEXT: ; implicit-def: $sgpr50 -; VI-NEXT: ; implicit-def: $sgpr87 +; VI-NEXT: ; implicit-def: $sgpr90 +; VI-NEXT: ; implicit-def: $sgpr38 +; VI-NEXT: ; implicit-def: $sgpr30 +; VI-NEXT: ; implicit-def: $sgpr34 +; VI-NEXT: ; implicit-def: $sgpr36 ; VI-NEXT: ; implicit-def: $sgpr86 -; VI-NEXT: ; implicit-def: $sgpr84 -; VI-NEXT: ; implicit-def: $sgpr85 -; VI-NEXT: ; implicit-def: $sgpr83 +; VI-NEXT: ; implicit-def: $sgpr48 ; VI-NEXT: ; implicit-def: $sgpr82 -; VI-NEXT: ; implicit-def: $sgpr81 +; VI-NEXT: ; implicit-def: $sgpr52 ; VI-NEXT: ; implicit-def: $sgpr80 -; VI-NEXT: ; implicit-def: $sgpr76 -; VI-NEXT: ; implicit-def: $sgpr74 -; VI-NEXT: ; implicit-def: $sgpr72 -; VI-NEXT: ; implicit-def: $sgpr62 -; VI-NEXT: ; implicit-def: $sgpr60 -; VI-NEXT: ; implicit-def: $sgpr58 +; VI-NEXT: ; implicit-def: $sgpr64 +; VI-NEXT: ; implicit-def: $sgpr84 +; VI-NEXT: ; implicit-def: $sgpr70 ; VI-NEXT: ; implicit-def: $sgpr56 -; VI-NEXT: ; implicit-def: $sgpr48 -; VI-NEXT: ; implicit-def: $sgpr38 -; VI-NEXT: ; implicit-def: $sgpr36 -; VI-NEXT: ; implicit-def: $sgpr34 -; VI-NEXT: ; implicit-def: $sgpr30 -; VI-NEXT: ; implicit-def: $sgpr90 -; VI-NEXT: ; implicit-def: $sgpr88 -; VI-NEXT: ; implicit-def: $sgpr78 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 +; VI-NEXT: ; implicit-def: $sgpr68 +; VI-NEXT: ; implicit-def: $sgpr58 +; VI-NEXT: ; implicit-def: $sgpr60 +; VI-NEXT: ; implicit-def: $sgpr62 +; VI-NEXT: ; implicit-def: $sgpr72 +; VI-NEXT: ; implicit-def: $sgpr74 +; VI-NEXT: v_writelane_b32 v22, s77, 9 ; VI-NEXT: ; implicit-def: $sgpr46 ; VI-NEXT: ; kill: killed $sgpr46 +; VI-NEXT: ; implicit-def: $sgpr76 ; VI-NEXT: ; implicit-def: $sgpr46 ; VI-NEXT: ; kill: killed $sgpr46 ; VI-NEXT: ; implicit-def: $sgpr46 @@ -169733,5453 +167999,3350 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a ; VI-NEXT: ; kill: killed $sgpr46 ; VI-NEXT: ; implicit-def: $sgpr46 ; VI-NEXT: s_branch .LBB91_2 -; VI-NEXT: .LBB91_4: -; VI-NEXT: v_mov_b32_e32 v33, s71 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s69 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s70 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s68 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s67 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s86 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s83 -; VI-NEXT: v_mov_b32_e32 v31, s4 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s82 -; VI-NEXT: v_readlane_b32 s4, v62, 0 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 1 -; VI-NEXT: v_mov_b32_e32 v40, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 2 -; VI-NEXT: v_mov_b32_e32 v44, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 3 -; VI-NEXT: v_mov_b32_e32 v54, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 4 -; VI-NEXT: v_mov_b32_e32 v53, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 5 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 6 -; VI-NEXT: v_mov_b32_e32 v51, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 7 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 8 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 9 -; VI-NEXT: v_mov_b32_e32 v56, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 10 -; VI-NEXT: v_mov_b32_e32 v47, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 11 -; VI-NEXT: v_mov_b32_e32 v48, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 12 -; VI-NEXT: v_mov_b32_e32 v43, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 13 -; VI-NEXT: v_mov_b32_e32 v46, s4 -; VI-NEXT: v_mov_b32_e32 v45, s72 -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v45, s74 -; VI-NEXT: v_mov_b32_e32 v42, s54 -; VI-NEXT: v_mov_b32_e32 v41, s46 -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v41, s56 -; VI-NEXT: v_readlane_b32 s4, v62, 14 -; VI-NEXT: v_mov_b32_e32 v50, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 15 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 16 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 17 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 18 -; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v33, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 19 -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 20 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 21 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 22 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v45, s76 -; VI-NEXT: v_readlane_b32 s4, v62, 23 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 24 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 25 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 26 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 27 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 28 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 29 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 30 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 31 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 32 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 33 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 34 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 35 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 36 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 37 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill -; VI-NEXT: v_readlane_b32 s4, v62, 38 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 39 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 40 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 41 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 42 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 43 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 44 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 45 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 46 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 47 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 48 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 49 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 50 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 51 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 52 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 53 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 54 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 55 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 56 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 57 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v55, s4 -; VI-NEXT: v_mov_b32_e32 v36, s66 -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v45, s78 -; VI-NEXT: v_mov_b32_e32 v55, s88 -; VI-NEXT: v_mov_b32_e32 v35, s30 -; VI-NEXT: v_mov_b32_e32 v41, s58 -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v35, s85 -; VI-NEXT: v_mov_b32_e32 v34, s38 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v52, s64 -; VI-NEXT: v_mov_b32_e32 v59, s87 -; VI-NEXT: v_mov_b32_e32 v41, s60 -; VI-NEXT: v_mov_b32_e32 v55, v50 -; VI-NEXT: v_mov_b32_e32 v58, s34 -; VI-NEXT: v_mov_b32_e32 v45, s36 -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v50, v46 -; VI-NEXT: v_mov_b32_e32 v46, v48 -; VI-NEXT: v_mov_b32_e32 v48, v47 -; VI-NEXT: v_mov_b32_e32 v47, v56 -; VI-NEXT: v_mov_b32_e32 v56, v51 -; VI-NEXT: v_mov_b32_e32 v51, s90 -; VI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v34, s48 -; VI-NEXT: v_mov_b32_e32 v1, s44 -; VI-NEXT: v_mov_b32_e32 v2, s45 -; VI-NEXT: v_mov_b32_e32 v3, s42 -; VI-NEXT: v_mov_b32_e32 v4, s43 -; VI-NEXT: v_mov_b32_e32 v5, s40 -; VI-NEXT: v_mov_b32_e32 v6, s41 -; VI-NEXT: v_mov_b32_e32 v7, s14 -; VI-NEXT: v_mov_b32_e32 v8, s15 -; VI-NEXT: v_mov_b32_e32 v9, s12 -; VI-NEXT: v_mov_b32_e32 v10, s13 -; VI-NEXT: v_mov_b32_e32 v11, s10 -; VI-NEXT: v_mov_b32_e32 v12, s11 -; VI-NEXT: v_mov_b32_e32 v13, s8 -; VI-NEXT: v_mov_b32_e32 v14, s9 -; VI-NEXT: v_mov_b32_e32 v15, s6 -; VI-NEXT: v_mov_b32_e32 v16, s7 -; VI-NEXT: v_mov_b32_e32 v17, s16 -; VI-NEXT: v_mov_b32_e32 v18, s17 -; VI-NEXT: v_mov_b32_e32 v19, s18 -; VI-NEXT: v_mov_b32_e32 v20, s19 -; VI-NEXT: v_mov_b32_e32 v21, s20 -; VI-NEXT: v_mov_b32_e32 v22, s21 -; VI-NEXT: v_mov_b32_e32 v23, s22 -; VI-NEXT: v_mov_b32_e32 v24, s23 -; VI-NEXT: v_mov_b32_e32 v25, s24 -; VI-NEXT: v_mov_b32_e32 v26, s25 -; VI-NEXT: v_mov_b32_e32 v27, s26 -; VI-NEXT: v_mov_b32_e32 v28, s27 -; VI-NEXT: v_mov_b32_e32 v29, s28 -; VI-NEXT: v_mov_b32_e32 v30, s29 -; VI-NEXT: v_mov_b32_e32 v32, s5 -; VI-NEXT: v_mov_b32_e32 v41, s62 -; VI-NEXT: v_mov_b32_e32 v51, v53 -; VI-NEXT: v_mov_b32_e32 v53, v54 -; VI-NEXT: v_mov_b32_e32 v54, v40 -; VI-NEXT: v_mov_b32_e32 v40, s80 -; VI-NEXT: v_mov_b32_e32 v57, s81 -; VI-NEXT: v_mov_b32_e32 v37, s84 -; VI-NEXT: v_mov_b32_e32 v58, s50 -; VI-NEXT: v_mov_b32_e32 v60, s52 -; VI-NEXT: v_mov_b32_e32 v38, s51 -; VI-NEXT: v_mov_b32_e32 v61, s65 -; VI-NEXT: v_mov_b32_e32 v49, s66 -; VI-NEXT: v_mov_b32_e32 v45, s53 -; VI-NEXT: v_mov_b32_e32 v39, s55 -; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; VI-NEXT: .LBB91_5: ; %end -; VI-NEXT: v_lshlrev_b32_e32 v36, 8, v33 -; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload -; VI-NEXT: v_or_b32_sdwa v17, v17, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_readlane_b32 s87, v63, 31 -; VI-NEXT: v_readlane_b32 s86, v63, 30 -; VI-NEXT: v_readlane_b32 s85, v63, 29 -; VI-NEXT: v_readlane_b32 s84, v63, 28 -; VI-NEXT: v_readlane_b32 s83, v63, 27 -; VI-NEXT: v_readlane_b32 s82, v63, 26 -; VI-NEXT: v_readlane_b32 s81, v63, 25 -; VI-NEXT: v_readlane_b32 s80, v63, 24 -; VI-NEXT: v_readlane_b32 s71, v63, 23 -; VI-NEXT: v_readlane_b32 s70, v63, 22 -; VI-NEXT: v_readlane_b32 s69, v63, 21 -; VI-NEXT: v_readlane_b32 s68, v63, 20 -; VI-NEXT: v_readlane_b32 s67, v63, 19 -; VI-NEXT: v_readlane_b32 s66, v63, 18 -; VI-NEXT: v_readlane_b32 s65, v63, 17 -; VI-NEXT: v_readlane_b32 s64, v63, 16 -; VI-NEXT: v_readlane_b32 s55, v63, 15 -; VI-NEXT: v_readlane_b32 s54, v63, 14 -; VI-NEXT: v_readlane_b32 s53, v63, 13 -; VI-NEXT: v_readlane_b32 s52, v63, 12 -; VI-NEXT: v_readlane_b32 s51, v63, 11 -; VI-NEXT: v_readlane_b32 s50, v63, 10 -; VI-NEXT: v_readlane_b32 s49, v63, 9 -; VI-NEXT: v_readlane_b32 s48, v63, 8 -; VI-NEXT: v_readlane_b32 s39, v63, 7 -; VI-NEXT: v_readlane_b32 s38, v63, 6 -; VI-NEXT: v_readlane_b32 s37, v63, 5 -; VI-NEXT: v_readlane_b32 s36, v63, 4 -; VI-NEXT: v_readlane_b32 s35, v63, 3 -; VI-NEXT: v_readlane_b32 s34, v63, 2 -; VI-NEXT: v_readlane_b32 s31, v63, 1 -; VI-NEXT: v_readlane_b32 s30, v63, 0 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v36, 8, v33 -; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload -; VI-NEXT: v_or_b32_sdwa v18, v18, v36 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v36, 8, v33 -; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v34, v33, v36 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v17, v17, v34 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v17, v33, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v18, vcc, 4, v0 -; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18 -; VI-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v18, vcc, 8, v0 -; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18 -; VI-NEXT: v_or_b32_sdwa v17, v20, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v17, v17, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v18, vcc, 12, v0 -; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18 -; VI-NEXT: v_or_b32_sdwa v18, v21, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v18, vcc, 16, v0 -; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18 -; VI-NEXT: v_or_b32_sdwa v17, v22, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v17, v17, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v18, vcc, 20, v0 -; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v41 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18 -; VI-NEXT: v_or_b32_sdwa v18, v23, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v18, vcc, 24, v0 -; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18 -; VI-NEXT: v_or_b32_sdwa v17, v24, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v17, v17, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v18, vcc, 28, v0 -; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18 -; VI-NEXT: v_or_b32_sdwa v18, v25, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v18, vcc, 32, v0 -; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18 -; VI-NEXT: v_or_b32_sdwa v17, v26, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v17, v17, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v18, vcc, 36, v0 -; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18 -; VI-NEXT: v_or_b32_sdwa v18, v27, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v18, vcc, 40, v0 -; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18 -; VI-NEXT: v_or_b32_sdwa v17, v28, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v17, v17, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v18, vcc, 44, v0 -; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18 -; VI-NEXT: v_or_b32_sdwa v18, v29, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v18, vcc, 48, v0 -; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18 -; VI-NEXT: v_or_b32_sdwa v17, v30, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v17, v17, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v18, vcc, 52, v0 -; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18 -; VI-NEXT: v_or_b32_sdwa v18, v31, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v18, vcc, 56, v0 -; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18 -; VI-NEXT: v_or_b32_sdwa v17, v32, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v17, v17, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v18, vcc, 60, v0 -; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18 -; VI-NEXT: v_or_b32_sdwa v1, v1, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v17, vcc, 64, v0 -; VI-NEXT: buffer_store_dword v1, v17, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; VI-NEXT: v_or_b32_sdwa v2, v17, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v49 -; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; VI-NEXT: v_or_b32_sdwa v1, v52, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v61 -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v42 -; VI-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v2, v39, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v45 -; VI-NEXT: v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; VI-NEXT: v_or_b32_sdwa v2, v38, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v60 -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v59 -; VI-NEXT: v_or_b32_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v2, v58, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; VI-NEXT: v_or_b32_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v2, v37, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v35 -; VI-NEXT: v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v57 -; VI-NEXT: v_or_b32_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v40 -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v44 -; VI-NEXT: v_or_b32_sdwa v1, v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v2, v54, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v53 -; VI-NEXT: v_or_b32_sdwa v1, v11, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; VI-NEXT: v_or_b32_sdwa v2, v51, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; VI-NEXT: v_or_b32_sdwa v1, v12, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v2, v56, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; VI-NEXT: v_or_b32_sdwa v1, v13, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v2, v47, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v48 -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v43 -; VI-NEXT: v_or_b32_sdwa v1, v14, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v2, v46, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v50 -; VI-NEXT: v_or_b32_sdwa v1, v15, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; VI-NEXT: v_or_b32_sdwa v2, v55, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0 -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; VI-NEXT: v_or_b32_sdwa v1, v16, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload -; VI-NEXT: s_or_saveexec_b64 s[4:5], -1 -; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload -; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: bitcast_v64bf16_to_v128i8_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 -; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 +; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v63, s30, 0 -; GFX9-NEXT: v_writelane_b32 v63, s31, 1 -; GFX9-NEXT: v_writelane_b32 v63, s34, 2 -; GFX9-NEXT: v_writelane_b32 v63, s35, 3 -; GFX9-NEXT: v_writelane_b32 v63, s36, 4 -; GFX9-NEXT: v_writelane_b32 v63, s37, 5 -; GFX9-NEXT: v_writelane_b32 v63, s38, 6 -; GFX9-NEXT: v_writelane_b32 v63, s39, 7 -; GFX9-NEXT: v_writelane_b32 v63, s48, 8 -; GFX9-NEXT: v_writelane_b32 v63, s49, 9 -; GFX9-NEXT: v_writelane_b32 v63, s50, 10 -; GFX9-NEXT: v_writelane_b32 v63, s51, 11 -; GFX9-NEXT: v_writelane_b32 v63, s52, 12 -; GFX9-NEXT: v_writelane_b32 v63, s53, 13 -; GFX9-NEXT: v_writelane_b32 v63, s54, 14 -; GFX9-NEXT: v_writelane_b32 v63, s55, 15 -; GFX9-NEXT: v_writelane_b32 v63, s64, 16 -; GFX9-NEXT: v_writelane_b32 v63, s65, 17 -; GFX9-NEXT: v_writelane_b32 v63, s66, 18 -; GFX9-NEXT: v_writelane_b32 v63, s67, 19 -; GFX9-NEXT: v_writelane_b32 v63, s68, 20 -; GFX9-NEXT: v_writelane_b32 v63, s69, 21 -; GFX9-NEXT: v_writelane_b32 v63, s70, 22 -; GFX9-NEXT: v_writelane_b32 v63, s71, 23 -; GFX9-NEXT: v_writelane_b32 v63, s80, 24 -; GFX9-NEXT: v_writelane_b32 v63, s81, 25 -; GFX9-NEXT: v_writelane_b32 v63, s82, 26 -; GFX9-NEXT: v_writelane_b32 v63, s83, 27 -; GFX9-NEXT: v_writelane_b32 v63, s84, 28 -; GFX9-NEXT: v_writelane_b32 v63, s85, 29 -; GFX9-NEXT: v_writelane_b32 v63, s86, 30 -; GFX9-NEXT: v_writelane_b32 v63, s87, 31 -; GFX9-NEXT: v_writelane_b32 v63, s96, 32 -; GFX9-NEXT: v_writelane_b32 v63, s97, 33 -; GFX9-NEXT: v_writelane_b32 v63, s98, 34 +; GFX9-NEXT: v_writelane_b32 v20, s30, 0 +; GFX9-NEXT: v_writelane_b32 v20, s31, 1 +; GFX9-NEXT: v_writelane_b32 v20, s34, 2 +; GFX9-NEXT: v_writelane_b32 v20, s35, 3 +; GFX9-NEXT: v_writelane_b32 v20, s36, 4 +; GFX9-NEXT: v_writelane_b32 v20, s37, 5 +; GFX9-NEXT: v_writelane_b32 v20, s38, 6 +; GFX9-NEXT: v_writelane_b32 v20, s39, 7 +; GFX9-NEXT: v_writelane_b32 v20, s48, 8 +; GFX9-NEXT: v_writelane_b32 v20, s49, 9 +; GFX9-NEXT: v_writelane_b32 v20, s50, 10 +; GFX9-NEXT: v_writelane_b32 v20, s51, 11 +; GFX9-NEXT: v_writelane_b32 v20, s52, 12 +; GFX9-NEXT: v_writelane_b32 v20, s53, 13 +; GFX9-NEXT: v_writelane_b32 v20, s54, 14 +; GFX9-NEXT: v_writelane_b32 v20, s55, 15 +; GFX9-NEXT: v_writelane_b32 v20, s64, 16 +; GFX9-NEXT: v_writelane_b32 v20, s65, 17 +; GFX9-NEXT: v_writelane_b32 v20, s66, 18 +; GFX9-NEXT: v_writelane_b32 v20, s67, 19 +; GFX9-NEXT: v_writelane_b32 v20, s68, 20 +; GFX9-NEXT: v_writelane_b32 v20, s69, 21 +; GFX9-NEXT: v_writelane_b32 v20, s70, 22 +; GFX9-NEXT: v_writelane_b32 v20, s71, 23 +; GFX9-NEXT: v_writelane_b32 v20, s80, 24 +; GFX9-NEXT: v_writelane_b32 v20, s81, 25 +; GFX9-NEXT: v_writelane_b32 v20, s82, 26 +; GFX9-NEXT: v_writelane_b32 v20, s83, 27 +; GFX9-NEXT: v_writelane_b32 v20, s84, 28 +; GFX9-NEXT: v_writelane_b32 v20, s85, 29 +; GFX9-NEXT: v_writelane_b32 v20, s86, 30 +; GFX9-NEXT: v_writelane_b32 v20, s87, 31 +; GFX9-NEXT: v_writelane_b32 v20, s96, 32 +; GFX9-NEXT: v_writelane_b32 v20, s97, 33 +; GFX9-NEXT: v_readfirstlane_b32 s40, v3 +; GFX9-NEXT: v_mov_b32_e32 v3, s16 +; GFX9-NEXT: v_readfirstlane_b32 s41, v4 +; GFX9-NEXT: v_mov_b32_e32 v4, s17 +; GFX9-NEXT: v_readfirstlane_b32 s16, v5 +; GFX9-NEXT: v_mov_b32_e32 v5, s18 +; GFX9-NEXT: v_readfirstlane_b32 s17, v6 +; GFX9-NEXT: v_mov_b32_e32 v6, s19 +; GFX9-NEXT: v_readfirstlane_b32 s14, v7 +; GFX9-NEXT: v_mov_b32_e32 v7, s20 +; GFX9-NEXT: v_readfirstlane_b32 s15, v8 +; GFX9-NEXT: v_mov_b32_e32 v8, s21 +; GFX9-NEXT: v_readfirstlane_b32 s12, v9 +; GFX9-NEXT: v_mov_b32_e32 v9, s22 +; GFX9-NEXT: v_readfirstlane_b32 s13, v10 +; GFX9-NEXT: v_mov_b32_e32 v10, s23 +; GFX9-NEXT: v_readfirstlane_b32 s10, v11 +; GFX9-NEXT: v_mov_b32_e32 v11, s24 +; GFX9-NEXT: v_readfirstlane_b32 s11, v12 +; GFX9-NEXT: v_mov_b32_e32 v12, s25 +; GFX9-NEXT: v_readfirstlane_b32 s8, v13 +; GFX9-NEXT: v_mov_b32_e32 v13, s26 +; GFX9-NEXT: v_readfirstlane_b32 s9, v14 +; GFX9-NEXT: v_mov_b32_e32 v14, s27 +; GFX9-NEXT: v_readfirstlane_b32 s6, v15 +; GFX9-NEXT: v_mov_b32_e32 v15, s28 +; GFX9-NEXT: v_readfirstlane_b32 s7, v16 +; GFX9-NEXT: v_mov_b32_e32 v16, s29 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; GFX9-NEXT: v_writelane_b32 v63, s99, 35 -; GFX9-NEXT: v_readfirstlane_b32 s76, v3 -; GFX9-NEXT: v_readfirstlane_b32 s77, v4 -; GFX9-NEXT: v_readfirstlane_b32 s74, v5 -; GFX9-NEXT: v_readfirstlane_b32 s75, v6 -; GFX9-NEXT: v_readfirstlane_b32 s72, v7 -; GFX9-NEXT: v_readfirstlane_b32 s73, v8 -; GFX9-NEXT: v_readfirstlane_b32 s62, v9 -; GFX9-NEXT: v_readfirstlane_b32 s63, v10 -; GFX9-NEXT: v_readfirstlane_b32 s60, v11 -; GFX9-NEXT: v_readfirstlane_b32 s61, v12 -; GFX9-NEXT: v_readfirstlane_b32 s58, v13 -; GFX9-NEXT: v_readfirstlane_b32 s59, v14 -; GFX9-NEXT: v_readfirstlane_b32 s56, v15 -; GFX9-NEXT: v_readfirstlane_b32 s57, v16 -; GFX9-NEXT: v_readfirstlane_b32 s46, v17 -; GFX9-NEXT: v_readfirstlane_b32 s47, v18 -; GFX9-NEXT: v_readfirstlane_b32 s4, v1 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: v_readfirstlane_b32 s5, v2 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 ; 4-byte Folded Spill -; GFX9-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane -; GFX9-NEXT: s_cbranch_scc0 .LBB91_3 +; GFX9-NEXT: v_writelane_b32 v20, s98, 34 +; GFX9-NEXT: v_readfirstlane_b32 s4, v17 +; GFX9-NEXT: v_readfirstlane_b32 s5, v18 +; GFX9-NEXT: v_readfirstlane_b32 s44, v3 +; GFX9-NEXT: v_readfirstlane_b32 s45, v4 +; GFX9-NEXT: v_readfirstlane_b32 s42, v5 +; GFX9-NEXT: v_readfirstlane_b32 s43, v6 +; GFX9-NEXT: v_readfirstlane_b32 s28, v7 +; GFX9-NEXT: v_readfirstlane_b32 s29, v8 +; GFX9-NEXT: v_readfirstlane_b32 s26, v9 +; GFX9-NEXT: v_readfirstlane_b32 s27, v10 +; GFX9-NEXT: v_readfirstlane_b32 s24, v11 +; GFX9-NEXT: v_readfirstlane_b32 s25, v12 +; GFX9-NEXT: v_readfirstlane_b32 s22, v13 +; GFX9-NEXT: v_readfirstlane_b32 s23, v14 +; GFX9-NEXT: v_readfirstlane_b32 s20, v15 +; GFX9-NEXT: v_readfirstlane_b32 s21, v16 +; GFX9-NEXT: v_readfirstlane_b32 s18, v1 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: v_readfirstlane_b32 s19, v2 +; GFX9-NEXT: v_writelane_b32 v20, s99, 35 +; GFX9-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane +; GFX9-NEXT: s_cbranch_scc0 .LBB91_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false -; GFX9-NEXT: s_lshr_b32 s6, s5, 24 -; GFX9-NEXT: v_writelane_b32 v62, s6, 18 -; GFX9-NEXT: s_lshr_b32 s6, s5, 16 -; GFX9-NEXT: v_writelane_b32 v62, s6, 17 -; GFX9-NEXT: s_lshr_b32 s6, s5, 8 -; GFX9-NEXT: v_writelane_b32 v62, s6, 19 -; GFX9-NEXT: s_lshr_b32 s6, s4, 16 -; GFX9-NEXT: v_writelane_b32 v62, s6, 20 -; GFX9-NEXT: s_lshr_b32 s6, s4, 8 -; GFX9-NEXT: v_writelane_b32 v62, s6, 21 -; GFX9-NEXT: s_lshr_b32 s6, s29, 24 -; GFX9-NEXT: v_writelane_b32 v62, s6, 22 -; GFX9-NEXT: s_lshr_b32 s6, s29, 16 -; GFX9-NEXT: v_writelane_b32 v62, s6, 16 -; GFX9-NEXT: s_lshr_b32 s6, s29, 8 -; GFX9-NEXT: v_writelane_b32 v62, s6, 23 -; GFX9-NEXT: s_lshr_b32 s6, s28, 16 -; GFX9-NEXT: v_writelane_b32 v62, s6, 24 -; GFX9-NEXT: s_lshr_b32 s6, s28, 8 -; GFX9-NEXT: v_writelane_b32 v62, s6, 25 -; GFX9-NEXT: s_lshr_b32 s6, s27, 24 -; GFX9-NEXT: v_writelane_b32 v62, s6, 26 -; GFX9-NEXT: s_lshr_b32 s6, s27, 16 -; GFX9-NEXT: v_writelane_b32 v62, s6, 15 -; GFX9-NEXT: s_lshr_b32 s6, s27, 8 -; GFX9-NEXT: v_writelane_b32 v62, s6, 27 -; GFX9-NEXT: s_lshr_b32 s6, s26, 16 -; GFX9-NEXT: v_writelane_b32 v62, s6, 28 -; GFX9-NEXT: s_lshr_b32 s6, s26, 8 -; GFX9-NEXT: v_writelane_b32 v62, s6, 29 -; GFX9-NEXT: s_lshr_b32 s6, s25, 24 -; GFX9-NEXT: v_writelane_b32 v62, s6, 30 -; GFX9-NEXT: s_lshr_b32 s6, s25, 16 -; GFX9-NEXT: v_writelane_b32 v62, s6, 14 -; GFX9-NEXT: s_lshr_b32 s6, s25, 8 -; GFX9-NEXT: v_writelane_b32 v62, s6, 31 -; GFX9-NEXT: s_lshr_b32 s6, s24, 16 -; GFX9-NEXT: v_writelane_b32 v62, s6, 32 -; GFX9-NEXT: s_lshr_b32 s6, s24, 8 -; GFX9-NEXT: v_writelane_b32 v62, s6, 33 -; GFX9-NEXT: s_lshr_b32 s6, s23, 24 -; GFX9-NEXT: v_writelane_b32 v62, s6, 34 -; GFX9-NEXT: s_lshr_b32 s6, s23, 16 -; GFX9-NEXT: v_writelane_b32 v62, s6, 13 -; GFX9-NEXT: s_lshr_b32 s6, s23, 8 -; GFX9-NEXT: v_writelane_b32 v62, s6, 35 -; GFX9-NEXT: s_lshr_b32 s6, s22, 16 -; GFX9-NEXT: v_writelane_b32 v62, s6, 36 -; GFX9-NEXT: s_lshr_b32 s6, s22, 8 -; GFX9-NEXT: v_writelane_b32 v62, s6, 37 -; GFX9-NEXT: s_lshr_b32 s6, s21, 24 -; GFX9-NEXT: v_writelane_b32 v62, s6, 38 -; GFX9-NEXT: s_lshr_b32 s6, s21, 16 -; GFX9-NEXT: v_writelane_b32 v62, s6, 12 -; GFX9-NEXT: s_lshr_b32 s6, s21, 8 -; GFX9-NEXT: v_writelane_b32 v62, s6, 39 -; GFX9-NEXT: s_lshr_b32 s6, s20, 16 -; GFX9-NEXT: v_writelane_b32 v62, s6, 40 -; GFX9-NEXT: s_lshr_b32 s6, s20, 8 -; GFX9-NEXT: v_writelane_b32 v62, s6, 41 -; GFX9-NEXT: s_lshr_b32 s6, s19, 24 -; GFX9-NEXT: v_writelane_b32 v62, s6, 42 -; GFX9-NEXT: s_lshr_b32 s6, s19, 16 -; GFX9-NEXT: v_writelane_b32 v62, s6, 11 -; GFX9-NEXT: s_lshr_b32 s6, s19, 8 -; GFX9-NEXT: v_writelane_b32 v62, s6, 43 -; GFX9-NEXT: s_lshr_b32 s6, s18, 16 -; GFX9-NEXT: v_writelane_b32 v62, s6, 44 -; GFX9-NEXT: s_lshr_b32 s6, s18, 8 -; GFX9-NEXT: v_writelane_b32 v62, s6, 45 -; GFX9-NEXT: s_lshr_b32 s6, s17, 24 -; GFX9-NEXT: v_writelane_b32 v62, s6, 46 -; GFX9-NEXT: s_lshr_b32 s6, s17, 16 -; GFX9-NEXT: v_writelane_b32 v62, s6, 10 -; GFX9-NEXT: s_lshr_b32 s6, s17, 8 -; GFX9-NEXT: v_writelane_b32 v62, s6, 47 -; GFX9-NEXT: s_lshr_b32 s6, s16, 16 -; GFX9-NEXT: v_writelane_b32 v62, s6, 48 -; GFX9-NEXT: s_lshr_b32 s6, s16, 8 -; GFX9-NEXT: v_writelane_b32 v62, s6, 49 -; GFX9-NEXT: s_lshr_b64 s[40:41], s[4:5], 24 -; GFX9-NEXT: v_writelane_b32 v62, s40, 8 -; GFX9-NEXT: v_writelane_b32 v62, s41, 9 -; GFX9-NEXT: s_lshr_b64 s[40:41], s[28:29], 24 -; GFX9-NEXT: v_writelane_b32 v62, s40, 6 -; GFX9-NEXT: v_writelane_b32 v62, s41, 7 -; GFX9-NEXT: s_lshr_b64 s[40:41], s[26:27], 24 -; GFX9-NEXT: v_writelane_b32 v62, s40, 4 -; GFX9-NEXT: v_writelane_b32 v62, s41, 5 -; GFX9-NEXT: s_lshr_b64 s[40:41], s[24:25], 24 -; GFX9-NEXT: v_writelane_b32 v62, s40, 2 -; GFX9-NEXT: v_writelane_b32 v62, s41, 3 -; GFX9-NEXT: s_lshr_b64 s[40:41], s[22:23], 24 -; GFX9-NEXT: v_writelane_b32 v62, s40, 0 -; GFX9-NEXT: s_lshr_b32 s70, s47, 24 -; GFX9-NEXT: s_lshr_b32 s15, s47, 16 -; GFX9-NEXT: s_lshr_b32 s7, s47, 8 -; GFX9-NEXT: s_lshr_b32 s53, s46, 16 -; GFX9-NEXT: s_lshr_b32 s52, s46, 8 -; GFX9-NEXT: s_lshr_b32 s67, s57, 24 -; GFX9-NEXT: s_lshr_b32 s14, s57, 16 -; GFX9-NEXT: s_lshr_b32 s69, s57, 8 -; GFX9-NEXT: s_lshr_b32 s6, s56, 16 -; GFX9-NEXT: s_lshr_b32 s71, s56, 8 -; GFX9-NEXT: s_lshr_b32 s64, s59, 24 -; GFX9-NEXT: s_lshr_b32 s13, s59, 16 -; GFX9-NEXT: s_lshr_b32 s66, s59, 8 -; GFX9-NEXT: s_lshr_b32 s51, s58, 16 -; GFX9-NEXT: s_lshr_b32 s68, s58, 8 -; GFX9-NEXT: s_lshr_b32 s99, s61, 24 -; GFX9-NEXT: s_lshr_b32 s12, s61, 16 -; GFX9-NEXT: s_lshr_b32 s55, s61, 8 -; GFX9-NEXT: s_lshr_b32 s50, s60, 16 -; GFX9-NEXT: s_lshr_b32 s65, s60, 8 -; GFX9-NEXT: s_lshr_b32 s96, s63, 24 -; GFX9-NEXT: s_lshr_b32 s11, s63, 16 -; GFX9-NEXT: s_lshr_b32 s98, s63, 8 -; GFX9-NEXT: s_lshr_b32 s49, s62, 16 -; GFX9-NEXT: s_lshr_b32 s54, s62, 8 -; GFX9-NEXT: s_lshr_b32 s85, s73, 24 -; GFX9-NEXT: s_lshr_b32 s10, s73, 16 -; GFX9-NEXT: s_lshr_b32 s87, s73, 8 -; GFX9-NEXT: s_lshr_b32 s48, s72, 16 -; GFX9-NEXT: s_lshr_b32 s97, s72, 8 -; GFX9-NEXT: s_lshr_b32 s82, s75, 24 -; GFX9-NEXT: s_lshr_b32 s9, s75, 16 -; GFX9-NEXT: s_lshr_b32 s84, s75, 8 -; GFX9-NEXT: s_lshr_b32 s39, s74, 16 -; GFX9-NEXT: s_lshr_b32 s86, s74, 8 -; GFX9-NEXT: s_lshr_b32 s80, s77, 24 -; GFX9-NEXT: s_lshr_b32 s8, s77, 16 -; GFX9-NEXT: s_lshr_b32 s81, s77, 8 -; GFX9-NEXT: s_lshr_b32 s38, s76, 16 -; GFX9-NEXT: s_lshr_b32 s83, s76, 8 -; GFX9-NEXT: v_writelane_b32 v62, s41, 1 -; GFX9-NEXT: s_lshr_b64 s[40:41], s[20:21], 24 -; GFX9-NEXT: s_lshr_b64 s[42:43], s[18:19], 24 -; GFX9-NEXT: s_lshr_b64 s[44:45], s[16:17], 24 -; GFX9-NEXT: s_lshr_b64 s[78:79], s[46:47], 24 -; GFX9-NEXT: s_lshr_b64 s[88:89], s[56:57], 24 -; GFX9-NEXT: s_lshr_b64 s[90:91], s[58:59], 24 -; GFX9-NEXT: s_lshr_b64 s[92:93], s[60:61], 24 -; GFX9-NEXT: s_lshr_b64 s[94:95], s[62:63], 24 -; GFX9-NEXT: s_lshr_b64 s[30:31], s[72:73], 24 -; GFX9-NEXT: s_lshr_b64 s[34:35], s[74:75], 24 -; GFX9-NEXT: s_lshr_b64 s[36:37], s[76:77], 24 -; GFX9-NEXT: s_cbranch_execnz .LBB91_4 +; GFX9-NEXT: s_lshr_b32 s46, s19, 24 +; GFX9-NEXT: v_writelane_b32 v21, s46, 14 +; GFX9-NEXT: s_lshr_b32 s46, s19, 8 +; GFX9-NEXT: v_writelane_b32 v21, s46, 15 +; GFX9-NEXT: s_lshr_b32 s46, s18, 16 +; GFX9-NEXT: v_writelane_b32 v21, s46, 16 +; GFX9-NEXT: s_lshr_b32 s46, s18, 8 +; GFX9-NEXT: v_writelane_b32 v21, s46, 17 +; GFX9-NEXT: s_lshr_b32 s46, s21, 24 +; GFX9-NEXT: v_writelane_b32 v21, s46, 18 +; GFX9-NEXT: s_lshr_b32 s46, s21, 8 +; GFX9-NEXT: v_writelane_b32 v21, s46, 19 +; GFX9-NEXT: s_lshr_b32 s46, s20, 16 +; GFX9-NEXT: v_writelane_b32 v21, s46, 20 +; GFX9-NEXT: s_lshr_b32 s46, s20, 8 +; GFX9-NEXT: v_writelane_b32 v21, s46, 21 +; GFX9-NEXT: s_lshr_b32 s46, s23, 24 +; GFX9-NEXT: v_writelane_b32 v21, s46, 22 +; GFX9-NEXT: s_lshr_b32 s46, s23, 16 +; GFX9-NEXT: v_writelane_b32 v21, s46, 13 +; GFX9-NEXT: s_lshr_b32 s46, s23, 8 +; GFX9-NEXT: v_writelane_b32 v21, s46, 23 +; GFX9-NEXT: s_lshr_b32 s46, s22, 16 +; GFX9-NEXT: v_writelane_b32 v21, s46, 24 +; GFX9-NEXT: s_lshr_b32 s46, s22, 8 +; GFX9-NEXT: v_writelane_b32 v21, s46, 25 +; GFX9-NEXT: s_lshr_b32 s46, s25, 24 +; GFX9-NEXT: v_writelane_b32 v21, s46, 26 +; GFX9-NEXT: s_lshr_b32 s46, s25, 16 +; GFX9-NEXT: v_writelane_b32 v21, s46, 12 +; GFX9-NEXT: s_lshr_b32 s46, s25, 8 +; GFX9-NEXT: v_writelane_b32 v21, s46, 27 +; GFX9-NEXT: s_lshr_b32 s46, s24, 16 +; GFX9-NEXT: v_writelane_b32 v21, s46, 28 +; GFX9-NEXT: s_lshr_b32 s46, s24, 8 +; GFX9-NEXT: v_writelane_b32 v21, s46, 29 +; GFX9-NEXT: s_lshr_b32 s46, s27, 24 +; GFX9-NEXT: v_writelane_b32 v21, s46, 30 +; GFX9-NEXT: s_lshr_b32 s46, s27, 16 +; GFX9-NEXT: v_writelane_b32 v21, s46, 11 +; GFX9-NEXT: s_lshr_b32 s46, s27, 8 +; GFX9-NEXT: v_writelane_b32 v21, s46, 31 +; GFX9-NEXT: s_lshr_b32 s46, s29, 16 +; GFX9-NEXT: v_writelane_b32 v21, s46, 10 +; GFX9-NEXT: s_lshr_b32 s46, s43, 16 +; GFX9-NEXT: v_writelane_b32 v21, s46, 9 +; GFX9-NEXT: s_lshr_b32 s46, s45, 16 +; GFX9-NEXT: v_writelane_b32 v21, s46, 8 +; GFX9-NEXT: s_lshr_b32 s46, s5, 16 +; GFX9-NEXT: v_writelane_b32 v21, s46, 7 +; GFX9-NEXT: s_lshr_b32 s46, s7, 16 +; GFX9-NEXT: v_writelane_b32 v21, s46, 6 +; GFX9-NEXT: s_lshr_b32 s46, s9, 24 +; GFX9-NEXT: v_writelane_b32 v21, s46, 32 +; GFX9-NEXT: s_lshr_b32 s46, s9, 16 +; GFX9-NEXT: v_writelane_b32 v21, s46, 5 +; GFX9-NEXT: s_lshr_b32 s46, s9, 8 +; GFX9-NEXT: v_writelane_b32 v21, s46, 33 +; GFX9-NEXT: s_lshr_b32 s46, s8, 16 +; GFX9-NEXT: v_writelane_b32 v21, s46, 34 +; GFX9-NEXT: s_lshr_b32 s46, s8, 8 +; GFX9-NEXT: v_writelane_b32 v21, s46, 35 +; GFX9-NEXT: s_lshr_b32 s46, s11, 16 +; GFX9-NEXT: v_writelane_b32 v21, s46, 4 +; GFX9-NEXT: s_lshr_b32 s46, s11, 8 +; GFX9-NEXT: v_writelane_b32 v21, s46, 36 +; GFX9-NEXT: s_lshr_b32 s46, s10, 16 +; GFX9-NEXT: v_writelane_b32 v21, s46, 37 +; GFX9-NEXT: s_lshr_b32 s46, s10, 8 +; GFX9-NEXT: v_writelane_b32 v21, s46, 38 +; GFX9-NEXT: s_lshr_b32 s46, s13, 16 +; GFX9-NEXT: v_writelane_b32 v21, s46, 3 +; GFX9-NEXT: s_lshr_b32 s46, s13, 8 +; GFX9-NEXT: v_writelane_b32 v21, s46, 39 +; GFX9-NEXT: s_lshr_b32 s46, s15, 16 +; GFX9-NEXT: s_lshr_b32 s60, s4, 8 +; GFX9-NEXT: s_lshr_b32 s61, s7, 24 +; GFX9-NEXT: s_lshr_b32 s62, s7, 8 +; GFX9-NEXT: s_lshr_b32 s63, s6, 16 +; GFX9-NEXT: v_writelane_b32 v21, s46, 2 +; GFX9-NEXT: s_lshr_b32 s46, s17, 16 +; GFX9-NEXT: s_lshr_b64 s[90:91], s[24:25], 24 +; GFX9-NEXT: s_lshr_b64 s[94:95], s[26:27], 24 +; GFX9-NEXT: s_lshr_b64 s[30:31], s[28:29], 24 +; GFX9-NEXT: s_lshr_b64 s[34:35], s[42:43], 24 +; GFX9-NEXT: s_lshr_b32 s47, s5, 24 +; GFX9-NEXT: s_lshr_b32 s56, s5, 8 +; GFX9-NEXT: s_lshr_b32 s57, s4, 16 +; GFX9-NEXT: s_lshr_b32 s74, s6, 8 +; GFX9-NEXT: s_lshr_b32 s75, s11, 24 +; GFX9-NEXT: s_lshr_b32 s78, s13, 24 +; GFX9-NEXT: v_writelane_b32 v21, s46, 1 +; GFX9-NEXT: s_lshr_b32 s46, s41, 16 +; GFX9-NEXT: s_lshr_b64 s[58:59], s[18:19], 24 +; GFX9-NEXT: s_lshr_b64 s[72:73], s[20:21], 24 +; GFX9-NEXT: s_lshr_b64 s[76:77], s[22:23], 24 +; GFX9-NEXT: s_mov_b32 s91, s60 +; GFX9-NEXT: s_mov_b32 s95, s61 +; GFX9-NEXT: s_mov_b32 s31, s62 +; GFX9-NEXT: s_mov_b32 s35, s63 +; GFX9-NEXT: s_lshr_b64 s[36:37], s[44:45], 24 +; GFX9-NEXT: s_lshr_b64 s[60:61], s[8:9], 24 +; GFX9-NEXT: s_lshr_b64 s[62:63], s[10:11], 24 +; GFX9-NEXT: s_lshr_b32 s69, s19, 16 +; GFX9-NEXT: s_lshr_b32 s68, s21, 16 +; GFX9-NEXT: s_lshr_b32 s38, s26, 16 +; GFX9-NEXT: s_lshr_b32 s48, s26, 8 +; GFX9-NEXT: s_lshr_b32 s50, s29, 24 +; GFX9-NEXT: s_lshr_b32 s51, s29, 8 +; GFX9-NEXT: s_lshr_b32 s53, s28, 16 +; GFX9-NEXT: s_lshr_b32 s71, s28, 8 +; GFX9-NEXT: s_lshr_b32 s80, s43, 24 +; GFX9-NEXT: s_lshr_b32 s82, s43, 8 +; GFX9-NEXT: s_lshr_b32 s65, s42, 16 +; GFX9-NEXT: s_lshr_b32 s85, s42, 8 +; GFX9-NEXT: s_lshr_b32 s66, s45, 24 +; GFX9-NEXT: s_lshr_b32 s97, s45, 8 +; GFX9-NEXT: s_lshr_b32 s99, s44, 16 +; GFX9-NEXT: s_lshr_b32 s67, s44, 8 +; GFX9-NEXT: s_lshr_b32 s54, s12, 16 +; GFX9-NEXT: s_lshr_b32 s39, s12, 8 +; GFX9-NEXT: s_lshr_b32 s49, s15, 24 +; GFX9-NEXT: s_lshr_b32 s55, s15, 8 +; GFX9-NEXT: s_lshr_b32 s52, s14, 16 +; GFX9-NEXT: s_lshr_b32 s70, s14, 8 +; GFX9-NEXT: s_lshr_b32 s64, s17, 24 +; GFX9-NEXT: s_lshr_b32 s81, s17, 8 +; GFX9-NEXT: s_lshr_b32 s83, s16, 16 +; GFX9-NEXT: s_lshr_b32 s84, s16, 8 +; GFX9-NEXT: s_lshr_b32 s86, s41, 24 +; GFX9-NEXT: v_writelane_b32 v21, s46, 0 +; GFX9-NEXT: s_lshr_b32 s87, s41, 8 +; GFX9-NEXT: s_lshr_b32 s96, s40, 16 +; GFX9-NEXT: s_lshr_b32 s98, s40, 8 +; GFX9-NEXT: s_mov_b32 s59, s47 +; GFX9-NEXT: s_mov_b32 s73, s56 +; GFX9-NEXT: s_mov_b32 s77, s57 +; GFX9-NEXT: s_mov_b32 s37, s74 +; GFX9-NEXT: s_lshr_b64 s[46:47], s[4:5], 24 +; GFX9-NEXT: s_lshr_b64 s[56:57], s[6:7], 24 +; GFX9-NEXT: s_mov_b32 s61, s75 +; GFX9-NEXT: s_mov_b32 s63, s78 +; GFX9-NEXT: s_lshr_b64 s[74:75], s[12:13], 24 +; GFX9-NEXT: s_lshr_b64 s[78:79], s[14:15], 24 +; GFX9-NEXT: s_lshr_b64 s[92:93], s[16:17], 24 +; GFX9-NEXT: s_lshr_b64 s[88:89], s[40:41], 24 +; GFX9-NEXT: s_cbranch_execnz .LBB91_3 ; GFX9-NEXT: .LBB91_2: ; %cmp.true -; GFX9-NEXT: s_and_b32 s6, s77, 0xffff0000 +; GFX9-NEXT: s_and_b32 s46, s41, 0xffff0000 ; GFX9-NEXT: v_mov_b32_e32 v1, 0x40c00000 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: v_add_f32_e32 v2, s46, v1 +; GFX9-NEXT: v_readfirstlane_b32 s46, v2 +; GFX9-NEXT: s_bfe_u32 s47, s46, 0x10010 +; GFX9-NEXT: s_add_i32 s47, s47, s46 +; GFX9-NEXT: s_add_i32 s56, s47, 0x7fff +; GFX9-NEXT: s_or_b32 s57, s46, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: s_lshl_b32 s6, s77, 16 -; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s46, s57, s56 +; GFX9-NEXT: s_lshl_b32 s41, s41, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s41, v1 +; GFX9-NEXT: v_readfirstlane_b32 s41, v2 +; GFX9-NEXT: s_lshr_b32 s57, s46, 16 +; GFX9-NEXT: s_bfe_u32 s46, s41, 0x10010 +; GFX9-NEXT: s_add_i32 s46, s46, s41 +; GFX9-NEXT: s_add_i32 s56, s46, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX9-NEXT: s_and_b32 s6, s76, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v8, v5, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_bitset1_b32 s41, 22 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s41, s41, s56 +; GFX9-NEXT: s_and_b32 s46, s40, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s46, v1 +; GFX9-NEXT: v_readfirstlane_b32 s46, v2 +; GFX9-NEXT: s_bfe_u32 s47, s46, 0x10010 +; GFX9-NEXT: s_lshr_b32 s41, s41, 16 +; GFX9-NEXT: s_add_i32 s47, s47, s46 +; GFX9-NEXT: v_writelane_b32 v21, s57, 0 +; GFX9-NEXT: s_pack_ll_b32_b16 s89, s41, s57 +; GFX9-NEXT: s_add_i32 s56, s47, 0x7fff +; GFX9-NEXT: s_or_b32 s57, s46, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_lshl_b32 s6, s76, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_add_f32_e32 v3, s6, v1 -; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v4, v4, v3 -; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; GFX9-NEXT: v_add_u32_e32 v4, 0x7fff, v4 -; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill -; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX9-NEXT: s_and_b32 s6, s75, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v7, v2, 16, v3 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s46, s57, s56 +; GFX9-NEXT: s_lshl_b32 s40, s40, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s40, v1 +; GFX9-NEXT: v_readfirstlane_b32 s40, v2 +; GFX9-NEXT: s_lshr_b32 s56, s46, 16 +; GFX9-NEXT: s_bfe_u32 s46, s40, 0x10010 +; GFX9-NEXT: s_add_i32 s46, s46, s40 +; GFX9-NEXT: s_add_i32 s57, s46, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: s_lshl_b32 s6, s75, 16 -; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_bitset1_b32 s40, 22 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s40, s40, s57 +; GFX9-NEXT: s_and_b32 s46, s17, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s46, v1 +; GFX9-NEXT: v_readfirstlane_b32 s46, v2 +; GFX9-NEXT: s_bfe_u32 s47, s46, 0x10010 +; GFX9-NEXT: s_lshr_b32 s40, s40, 16 +; GFX9-NEXT: s_add_i32 s47, s47, s46 +; GFX9-NEXT: s_pack_ll_b32_b16 s88, s40, s56 +; GFX9-NEXT: s_add_i32 s56, s47, 0x7fff +; GFX9-NEXT: s_or_b32 s57, s46, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v2 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v31 -; GFX9-NEXT: s_and_b32 s6, s74, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v14, v5, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s46, s57, s56 +; GFX9-NEXT: s_lshl_b32 s17, s17, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s17, v1 +; GFX9-NEXT: v_readfirstlane_b32 s17, v2 +; GFX9-NEXT: s_lshr_b32 s57, s46, 16 +; GFX9-NEXT: s_bfe_u32 s46, s17, 0x10010 +; GFX9-NEXT: s_add_i32 s46, s46, s17 +; GFX9-NEXT: s_add_i32 s56, s46, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_lshl_b32 s6, s74, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_add_f32_e32 v3, s6, v1 -; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v4, v4, v3 -; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; GFX9-NEXT: v_add_u32_e32 v4, 0x7fff, v4 -; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v3 -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v33 -; GFX9-NEXT: s_and_b32 s6, s73, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v13, v2, 16, v3 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_bitset1_b32 s17, 22 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s17, s17, s56 +; GFX9-NEXT: s_and_b32 s46, s16, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s46, v1 +; GFX9-NEXT: v_readfirstlane_b32 s46, v2 +; GFX9-NEXT: s_bfe_u32 s47, s46, 0x10010 +; GFX9-NEXT: s_lshr_b32 s17, s17, 16 +; GFX9-NEXT: s_add_i32 s47, s47, s46 +; GFX9-NEXT: v_writelane_b32 v21, s57, 1 +; GFX9-NEXT: s_pack_ll_b32_b16 s93, s17, s57 +; GFX9-NEXT: s_add_i32 s56, s47, 0x7fff +; GFX9-NEXT: s_or_b32 s57, s46, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: s_lshl_b32 s6, s73, 16 -; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s46, s57, s56 +; GFX9-NEXT: s_lshl_b32 s16, s16, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s16, v1 +; GFX9-NEXT: v_readfirstlane_b32 s16, v2 +; GFX9-NEXT: s_lshr_b32 s56, s46, 16 +; GFX9-NEXT: s_bfe_u32 s46, s16, 0x10010 +; GFX9-NEXT: s_add_i32 s46, s46, s16 +; GFX9-NEXT: s_add_i32 s57, s46, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v2 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v34 -; GFX9-NEXT: s_and_b32 s6, s72, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v16, v32, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_bitset1_b32 s16, 22 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s16, s16, s57 +; GFX9-NEXT: s_and_b32 s46, s15, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s46, v1 +; GFX9-NEXT: v_readfirstlane_b32 s46, v2 +; GFX9-NEXT: s_bfe_u32 s47, s46, 0x10010 +; GFX9-NEXT: s_lshr_b32 s16, s16, 16 +; GFX9-NEXT: s_add_i32 s47, s47, s46 +; GFX9-NEXT: s_pack_ll_b32_b16 s92, s16, s56 +; GFX9-NEXT: s_add_i32 s56, s47, 0x7fff +; GFX9-NEXT: s_or_b32 s57, s46, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_lshl_b32 s6, s72, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_add_f32_e32 v3, s6, v1 -; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v4, v4, v3 -; GFX9-NEXT: v_add_u32_e32 v4, 0x7fff, v4 -; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v3 -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v36 -; GFX9-NEXT: s_and_b32 s6, s63, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v15, v2, 16, v3 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s46, s57, s56 +; GFX9-NEXT: s_lshl_b32 s15, s15, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s15, v1 +; GFX9-NEXT: v_readfirstlane_b32 s15, v2 +; GFX9-NEXT: s_lshr_b32 s57, s46, 16 +; GFX9-NEXT: s_bfe_u32 s46, s15, 0x10010 +; GFX9-NEXT: s_add_i32 s46, s46, s15 +; GFX9-NEXT: s_add_i32 s56, s46, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: s_lshl_b32 s6, s63, 16 -; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_bitset1_b32 s15, 22 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s15, s15, s56 +; GFX9-NEXT: s_and_b32 s46, s14, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s46, v1 +; GFX9-NEXT: v_readfirstlane_b32 s46, v2 +; GFX9-NEXT: s_bfe_u32 s47, s46, 0x10010 +; GFX9-NEXT: s_lshr_b32 s15, s15, 16 +; GFX9-NEXT: s_add_i32 s47, s47, s46 +; GFX9-NEXT: v_writelane_b32 v21, s57, 2 +; GFX9-NEXT: s_pack_ll_b32_b16 s79, s15, s57 +; GFX9-NEXT: s_add_i32 s56, s47, 0x7fff +; GFX9-NEXT: s_or_b32 s57, s46, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v2 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v37 -; GFX9-NEXT: s_and_b32 s6, s62, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v18, v35, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s46, s57, s56 +; GFX9-NEXT: s_lshl_b32 s14, s14, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s14, v1 +; GFX9-NEXT: v_readfirstlane_b32 s14, v2 +; GFX9-NEXT: s_lshr_b32 s56, s46, 16 +; GFX9-NEXT: s_bfe_u32 s46, s14, 0x10010 +; GFX9-NEXT: s_add_i32 s46, s46, s14 +; GFX9-NEXT: s_add_i32 s57, s46, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_lshl_b32 s6, s62, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_add_f32_e32 v3, s6, v1 -; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v4, v4, v3 -; GFX9-NEXT: v_add_u32_e32 v4, 0x7fff, v4 -; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v3 -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v39 -; GFX9-NEXT: s_and_b32 s6, s61, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v17, v2, 16, v3 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_bitset1_b32 s14, 22 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s14, s14, s57 +; GFX9-NEXT: s_and_b32 s46, s13, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s46, v1 +; GFX9-NEXT: v_readfirstlane_b32 s46, v2 +; GFX9-NEXT: s_bfe_u32 s47, s46, 0x10010 +; GFX9-NEXT: s_lshr_b32 s14, s14, 16 +; GFX9-NEXT: s_add_i32 s47, s47, s46 +; GFX9-NEXT: s_pack_ll_b32_b16 s78, s14, s56 +; GFX9-NEXT: s_add_i32 s56, s47, 0x7fff +; GFX9-NEXT: s_or_b32 s57, s46, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: s_lshl_b32 s6, s61, 16 -; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s46, s57, s56 +; GFX9-NEXT: s_lshl_b32 s13, s13, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s13, v1 +; GFX9-NEXT: v_readfirstlane_b32 s13, v2 +; GFX9-NEXT: s_lshr_b32 s57, s46, 16 +; GFX9-NEXT: s_bfe_u32 s46, s13, 0x10010 +; GFX9-NEXT: s_add_i32 s46, s46, s13 +; GFX9-NEXT: s_add_i32 s56, s46, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v2 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v48 -; GFX9-NEXT: s_and_b32 s6, s60, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v20, v38, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_bitset1_b32 s13, 22 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s13, s13, s56 +; GFX9-NEXT: s_and_b32 s46, s12, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s46, v1 +; GFX9-NEXT: v_readfirstlane_b32 s46, v2 +; GFX9-NEXT: s_bfe_u32 s47, s46, 0x10010 +; GFX9-NEXT: s_lshr_b32 s13, s13, 16 +; GFX9-NEXT: s_add_i32 s47, s47, s46 +; GFX9-NEXT: v_writelane_b32 v21, s57, 3 +; GFX9-NEXT: s_pack_ll_b32_b16 s75, s13, s57 +; GFX9-NEXT: s_add_i32 s56, s47, 0x7fff +; GFX9-NEXT: s_or_b32 s57, s46, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_lshl_b32 s6, s60, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_add_f32_e32 v3, s6, v1 -; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v4, v4, v3 -; GFX9-NEXT: v_add_u32_e32 v4, 0x7fff, v4 -; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v3 -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v50 -; GFX9-NEXT: s_and_b32 s6, s59, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v19, v2, 16, v3 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s46, s57, s56 +; GFX9-NEXT: s_lshl_b32 s12, s12, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s12, v1 +; GFX9-NEXT: v_readfirstlane_b32 s12, v2 +; GFX9-NEXT: s_lshr_b32 s56, s46, 16 +; GFX9-NEXT: s_bfe_u32 s46, s12, 0x10010 +; GFX9-NEXT: s_add_i32 s46, s46, s12 +; GFX9-NEXT: s_add_i32 s57, s46, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: s_lshl_b32 s6, s59, 16 -; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_bitset1_b32 s12, 22 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s12, s12, s57 +; GFX9-NEXT: s_and_b32 s46, s11, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s46, v1 +; GFX9-NEXT: v_readfirstlane_b32 s46, v2 +; GFX9-NEXT: s_bfe_u32 s47, s46, 0x10010 +; GFX9-NEXT: s_lshr_b32 s12, s12, 16 +; GFX9-NEXT: s_add_i32 s47, s47, s46 +; GFX9-NEXT: s_pack_ll_b32_b16 s74, s12, s56 +; GFX9-NEXT: s_add_i32 s56, s47, 0x7fff +; GFX9-NEXT: s_or_b32 s57, s46, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v2 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v51 -; GFX9-NEXT: s_and_b32 s6, s58, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v22, v49, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s46, s57, s56 +; GFX9-NEXT: s_lshl_b32 s11, s11, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s11, v1 +; GFX9-NEXT: v_readfirstlane_b32 s11, v2 +; GFX9-NEXT: s_lshr_b32 s57, s46, 16 +; GFX9-NEXT: s_bfe_u32 s46, s11, 0x10010 +; GFX9-NEXT: s_add_i32 s46, s46, s11 +; GFX9-NEXT: s_add_i32 s56, s46, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_lshl_b32 s6, s58, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_add_f32_e32 v3, s6, v1 -; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v4, v4, v3 -; GFX9-NEXT: v_add_u32_e32 v4, 0x7fff, v4 -; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v3 -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v53 -; GFX9-NEXT: s_and_b32 s6, s57, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v21, v2, 16, v3 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_bitset1_b32 s11, 22 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s11, s11, s56 +; GFX9-NEXT: s_and_b32 s46, s10, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s46, v1 +; GFX9-NEXT: v_readfirstlane_b32 s46, v2 +; GFX9-NEXT: s_bfe_u32 s47, s46, 0x10010 +; GFX9-NEXT: s_lshr_b32 s11, s11, 16 +; GFX9-NEXT: s_add_i32 s47, s47, s46 +; GFX9-NEXT: v_writelane_b32 v21, s57, 4 +; GFX9-NEXT: s_pack_ll_b32_b16 s63, s11, s57 +; GFX9-NEXT: s_add_i32 s56, s47, 0x7fff +; GFX9-NEXT: s_or_b32 s57, s46, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: s_lshl_b32 s6, s57, 16 -; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s46, s57, s56 +; GFX9-NEXT: s_lshl_b32 s10, s10, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s10, v1 +; GFX9-NEXT: v_readfirstlane_b32 s10, v2 +; GFX9-NEXT: s_lshr_b32 s56, s46, 16 +; GFX9-NEXT: s_bfe_u32 s46, s10, 0x10010 +; GFX9-NEXT: s_add_i32 s46, s46, s10 +; GFX9-NEXT: s_add_i32 s57, s46, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v2 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v54 -; GFX9-NEXT: s_and_b32 s6, s56, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v24, v52, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_bitset1_b32 s10, 22 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s10, s10, s57 +; GFX9-NEXT: s_and_b32 s46, s9, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s46, v1 +; GFX9-NEXT: v_readfirstlane_b32 s46, v2 +; GFX9-NEXT: s_bfe_u32 s47, s46, 0x10010 +; GFX9-NEXT: s_lshr_b32 s10, s10, 16 +; GFX9-NEXT: s_add_i32 s47, s47, s46 +; GFX9-NEXT: s_pack_ll_b32_b16 s62, s10, s56 +; GFX9-NEXT: s_add_i32 s56, s47, 0x7fff +; GFX9-NEXT: s_or_b32 s57, s46, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_lshl_b32 s6, s56, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_add_f32_e32 v3, s6, v1 -; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v4, v4, v3 -; GFX9-NEXT: v_add_u32_e32 v4, 0x7fff, v4 -; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v3 -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v40 -; GFX9-NEXT: s_and_b32 s6, s47, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v23, v2, 16, v3 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s46, s57, s56 +; GFX9-NEXT: s_lshl_b32 s9, s9, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s9, v1 +; GFX9-NEXT: v_readfirstlane_b32 s9, v2 +; GFX9-NEXT: s_lshr_b32 s57, s46, 16 +; GFX9-NEXT: s_bfe_u32 s46, s9, 0x10010 +; GFX9-NEXT: s_add_i32 s46, s46, s9 +; GFX9-NEXT: s_add_i32 s56, s46, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: s_lshl_b32 s6, s47, 16 -; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_bitset1_b32 s9, 22 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s9, s9, s56 +; GFX9-NEXT: s_and_b32 s46, s8, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s46, v1 +; GFX9-NEXT: v_readfirstlane_b32 s46, v2 +; GFX9-NEXT: s_bfe_u32 s47, s46, 0x10010 +; GFX9-NEXT: s_lshr_b32 s9, s9, 16 +; GFX9-NEXT: s_add_i32 s47, s47, s46 +; GFX9-NEXT: v_writelane_b32 v21, s57, 5 +; GFX9-NEXT: s_pack_ll_b32_b16 s61, s9, s57 +; GFX9-NEXT: s_add_i32 s56, s47, 0x7fff +; GFX9-NEXT: s_or_b32 s57, s46, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v2 -; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v41 -; GFX9-NEXT: s_and_b32 s6, s46, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v26, v55, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s46, s57, s56 +; GFX9-NEXT: s_lshl_b32 s8, s8, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s8, v1 +; GFX9-NEXT: v_readfirstlane_b32 s8, v2 +; GFX9-NEXT: s_lshr_b32 s56, s46, 16 +; GFX9-NEXT: s_bfe_u32 s46, s8, 0x10010 +; GFX9-NEXT: s_add_i32 s46, s46, s8 +; GFX9-NEXT: s_add_i32 s57, s46, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_lshl_b32 s6, s46, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_add_f32_e32 v3, s6, v1 -; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v4, v4, v3 -; GFX9-NEXT: v_add_u32_e32 v4, 0x7fff, v4 -; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v3 -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v42 -; GFX9-NEXT: s_and_b32 s6, s17, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v25, v2, 16, v3 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_bitset1_b32 s8, 22 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s8, s8, s57 +; GFX9-NEXT: s_and_b32 s46, s7, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s46, v1 +; GFX9-NEXT: v_readfirstlane_b32 s46, v2 +; GFX9-NEXT: s_bfe_u32 s47, s46, 0x10010 +; GFX9-NEXT: s_lshr_b32 s8, s8, 16 +; GFX9-NEXT: s_add_i32 s47, s47, s46 +; GFX9-NEXT: s_pack_ll_b32_b16 s60, s8, s56 +; GFX9-NEXT: s_add_i32 s56, s47, 0x7fff +; GFX9-NEXT: s_or_b32 s57, s46, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s11, s6, 16 -; GFX9-NEXT: s_lshl_b32 s6, s17, 16 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s46, s57, s56 +; GFX9-NEXT: s_lshl_b32 s7, s7, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s7, v1 +; GFX9-NEXT: v_readfirstlane_b32 s7, v2 +; GFX9-NEXT: s_lshr_b32 s57, s46, 16 +; GFX9-NEXT: s_bfe_u32 s46, s7, 0x10010 +; GFX9-NEXT: s_add_i32 s46, s46, s7 +; GFX9-NEXT: s_add_i32 s56, s46, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s17, s6, 16 -; GFX9-NEXT: s_and_b32 s6, s16, 0xffff0000 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_bitset1_b32 s7, 22 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s7, s7, s56 +; GFX9-NEXT: s_and_b32 s46, s6, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s46, v1 +; GFX9-NEXT: v_readfirstlane_b32 s46, v2 +; GFX9-NEXT: s_bfe_u32 s47, s46, 0x10010 +; GFX9-NEXT: s_add_i32 s47, s47, s46 +; GFX9-NEXT: s_lshr_b32 s7, s7, 16 +; GFX9-NEXT: s_add_i32 s56, s47, 0x7fff +; GFX9-NEXT: s_or_b32 s58, s46, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s8, s6, 16 -; GFX9-NEXT: s_lshl_b32 s6, s16, 16 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s46, s58, s56 +; GFX9-NEXT: s_lshl_b32 s6, s6, 16 ; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 ; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s9, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s10, s6, 0x400000 +; GFX9-NEXT: s_lshr_b32 s56, s46, 16 +; GFX9-NEXT: s_bfe_u32 s46, s6, 0x10010 +; GFX9-NEXT: s_add_i32 s46, s46, s6 +; GFX9-NEXT: s_add_i32 s58, s46, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s10, s9 -; GFX9-NEXT: s_lshr_b32 s16, s6, 16 -; GFX9-NEXT: s_and_b32 s6, s19, 0xffff0000 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s46, s16, s8 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_bitset1_b32 s6, 22 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s6, s6, s58 +; GFX9-NEXT: s_and_b32 s46, s5, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s46, v1 +; GFX9-NEXT: v_readfirstlane_b32 s46, v2 +; GFX9-NEXT: s_bfe_u32 s47, s46, 0x10010 +; GFX9-NEXT: s_add_i32 s47, s47, s46 +; GFX9-NEXT: s_lshr_b32 s6, s6, 16 +; GFX9-NEXT: s_add_i32 s58, s47, 0x7fff +; GFX9-NEXT: s_or_b32 s59, s46, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s12, s6, 16 -; GFX9-NEXT: s_lshl_b32 s6, s19, 16 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s46, s59, s58 +; GFX9-NEXT: s_lshl_b32 s5, s5, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s5, v1 +; GFX9-NEXT: v_readfirstlane_b32 s5, v2 +; GFX9-NEXT: s_lshr_b32 s59, s46, 16 +; GFX9-NEXT: s_bfe_u32 s46, s5, 0x10010 +; GFX9-NEXT: s_add_i32 s46, s46, s5 +; GFX9-NEXT: s_add_i32 s58, s46, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s19, s6, 16 -; GFX9-NEXT: s_and_b32 s6, s18, 0xffff0000 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_bitset1_b32 s5, 22 +; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_cselect_b32 s5, s5, s58 +; GFX9-NEXT: s_and_b32 s46, s4, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s46, v1 +; GFX9-NEXT: v_readfirstlane_b32 s46, v2 +; GFX9-NEXT: s_bfe_u32 s58, s46, 0x10010 +; GFX9-NEXT: s_add_i32 s58, s58, s46 +; GFX9-NEXT: v_writelane_b32 v21, s57, 6 +; GFX9-NEXT: s_lshr_b32 s5, s5, 16 +; GFX9-NEXT: s_add_i32 s72, s58, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s8, s6, 16 -; GFX9-NEXT: s_lshl_b32 s6, s18, 16 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s9, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s10, s6, 0x400000 +; GFX9-NEXT: v_writelane_b32 v21, s59, 7 +; GFX9-NEXT: s_pack_ll_b32_b16 s47, s5, s59 +; GFX9-NEXT: s_bitset1_b32 s46, 22 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s46, s46, s72 +; GFX9-NEXT: s_lshl_b32 s4, s4, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s4, v1 +; GFX9-NEXT: v_readfirstlane_b32 s4, v2 +; GFX9-NEXT: s_bfe_u32 s58, s4, 0x10010 +; GFX9-NEXT: s_add_i32 s58, s58, s4 +; GFX9-NEXT: s_lshr_b32 s46, s46, 16 +; GFX9-NEXT: s_add_i32 s72, s58, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s10, s9 -; GFX9-NEXT: s_lshr_b32 s18, s6, 16 -; GFX9-NEXT: s_and_b32 s6, s21, 0xffff0000 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s56, s18, s8 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_bitset1_b32 s4, 22 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s4, s4, s72 +; GFX9-NEXT: s_and_b32 s58, s45, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s58, v1 +; GFX9-NEXT: v_readfirstlane_b32 s58, v2 +; GFX9-NEXT: s_bfe_u32 s59, s58, 0x10010 +; GFX9-NEXT: s_add_i32 s59, s59, s58 +; GFX9-NEXT: s_lshr_b32 s4, s4, 16 +; GFX9-NEXT: s_add_i32 s72, s59, 0x7fff +; GFX9-NEXT: s_or_b32 s73, s58, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s13, s6, 16 -; GFX9-NEXT: s_lshl_b32 s6, s21, 16 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s58, s73, s72 +; GFX9-NEXT: s_lshl_b32 s45, s45, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s45, v1 +; GFX9-NEXT: v_readfirstlane_b32 s45, v2 +; GFX9-NEXT: s_lshr_b32 s73, s58, 16 +; GFX9-NEXT: s_bfe_u32 s58, s45, 0x10010 +; GFX9-NEXT: s_add_i32 s58, s58, s45 +; GFX9-NEXT: s_add_i32 s72, s58, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s21, s6, 16 -; GFX9-NEXT: s_and_b32 s6, s20, 0xffff0000 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_bitset1_b32 s45, 22 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s45, s45, s72 +; GFX9-NEXT: s_and_b32 s58, s44, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s58, v1 +; GFX9-NEXT: v_readfirstlane_b32 s58, v2 +; GFX9-NEXT: s_bfe_u32 s59, s58, 0x10010 +; GFX9-NEXT: s_lshr_b32 s45, s45, 16 +; GFX9-NEXT: s_add_i32 s59, s59, s58 +; GFX9-NEXT: v_writelane_b32 v21, s73, 8 +; GFX9-NEXT: s_pack_ll_b32_b16 s37, s45, s73 +; GFX9-NEXT: s_add_i32 s72, s59, 0x7fff +; GFX9-NEXT: s_or_b32 s73, s58, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s8, s6, 16 -; GFX9-NEXT: s_lshl_b32 s6, s20, 16 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s9, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s10, s6, 0x400000 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s58, s73, s72 +; GFX9-NEXT: s_lshl_b32 s44, s44, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s44, v1 +; GFX9-NEXT: v_readfirstlane_b32 s44, v2 +; GFX9-NEXT: s_lshr_b32 s72, s58, 16 +; GFX9-NEXT: s_bfe_u32 s58, s44, 0x10010 +; GFX9-NEXT: s_add_i32 s58, s58, s44 +; GFX9-NEXT: s_add_i32 s73, s58, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s10, s9 -; GFX9-NEXT: s_lshr_b32 s20, s6, 16 -; GFX9-NEXT: s_and_b32 s6, s23, 0xffff0000 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s58, s20, s8 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_bitset1_b32 s44, 22 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s44, s44, s73 +; GFX9-NEXT: s_and_b32 s58, s43, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s58, v1 +; GFX9-NEXT: v_readfirstlane_b32 s58, v2 +; GFX9-NEXT: s_bfe_u32 s59, s58, 0x10010 +; GFX9-NEXT: s_lshr_b32 s44, s44, 16 +; GFX9-NEXT: s_add_i32 s59, s59, s58 +; GFX9-NEXT: s_pack_ll_b32_b16 s36, s44, s72 +; GFX9-NEXT: s_add_i32 s72, s59, 0x7fff +; GFX9-NEXT: s_or_b32 s73, s58, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s14, s6, 16 -; GFX9-NEXT: s_lshl_b32 s6, s23, 16 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s58, s73, s72 +; GFX9-NEXT: s_lshl_b32 s43, s43, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s43, v1 +; GFX9-NEXT: v_readfirstlane_b32 s43, v2 +; GFX9-NEXT: s_lshr_b32 s73, s58, 16 +; GFX9-NEXT: s_bfe_u32 s58, s43, 0x10010 +; GFX9-NEXT: s_add_i32 s58, s58, s43 +; GFX9-NEXT: s_add_i32 s72, s58, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s23, s6, 16 -; GFX9-NEXT: s_and_b32 s6, s22, 0xffff0000 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_bitset1_b32 s43, 22 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s43, s43, s72 +; GFX9-NEXT: s_and_b32 s58, s42, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s58, v1 +; GFX9-NEXT: v_readfirstlane_b32 s58, v2 +; GFX9-NEXT: s_bfe_u32 s59, s58, 0x10010 +; GFX9-NEXT: s_lshr_b32 s43, s43, 16 +; GFX9-NEXT: s_add_i32 s59, s59, s58 +; GFX9-NEXT: v_writelane_b32 v21, s73, 9 +; GFX9-NEXT: s_pack_ll_b32_b16 s35, s43, s73 +; GFX9-NEXT: s_add_i32 s72, s59, 0x7fff +; GFX9-NEXT: s_or_b32 s73, s58, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s8, s6, 16 -; GFX9-NEXT: s_lshl_b32 s6, s22, 16 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s9, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s10, s6, 0x400000 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s58, s73, s72 +; GFX9-NEXT: s_lshl_b32 s42, s42, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s42, v1 +; GFX9-NEXT: v_readfirstlane_b32 s42, v2 +; GFX9-NEXT: s_lshr_b32 s72, s58, 16 +; GFX9-NEXT: s_bfe_u32 s58, s42, 0x10010 +; GFX9-NEXT: s_add_i32 s58, s58, s42 +; GFX9-NEXT: s_add_i32 s73, s58, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s10, s9 -; GFX9-NEXT: s_lshr_b32 s22, s6, 16 -; GFX9-NEXT: s_and_b32 s6, s25, 0xffff0000 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s60, s22, s8 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_bitset1_b32 s42, 22 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s42, s42, s73 +; GFX9-NEXT: s_and_b32 s58, s29, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s58, v1 +; GFX9-NEXT: v_readfirstlane_b32 s58, v2 +; GFX9-NEXT: s_bfe_u32 s59, s58, 0x10010 +; GFX9-NEXT: s_lshr_b32 s42, s42, 16 +; GFX9-NEXT: s_add_i32 s59, s59, s58 +; GFX9-NEXT: s_pack_ll_b32_b16 s34, s42, s72 +; GFX9-NEXT: s_add_i32 s72, s59, 0x7fff +; GFX9-NEXT: s_or_b32 s73, s58, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s15, s6, 16 -; GFX9-NEXT: s_lshl_b32 s6, s25, 16 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s58, s73, s72 +; GFX9-NEXT: s_lshl_b32 s29, s29, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s29, v1 +; GFX9-NEXT: v_readfirstlane_b32 s29, v2 +; GFX9-NEXT: s_lshr_b32 s73, s58, 16 +; GFX9-NEXT: s_bfe_u32 s58, s29, 0x10010 +; GFX9-NEXT: s_add_i32 s58, s58, s29 +; GFX9-NEXT: s_add_i32 s72, s58, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s25, s6, 16 -; GFX9-NEXT: s_and_b32 s6, s24, 0xffff0000 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_bitset1_b32 s29, 22 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s29, s29, s72 +; GFX9-NEXT: s_and_b32 s58, s28, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s58, v1 +; GFX9-NEXT: v_readfirstlane_b32 s58, v2 +; GFX9-NEXT: s_bfe_u32 s59, s58, 0x10010 +; GFX9-NEXT: s_lshr_b32 s29, s29, 16 +; GFX9-NEXT: s_add_i32 s59, s59, s58 +; GFX9-NEXT: v_writelane_b32 v21, s73, 10 +; GFX9-NEXT: s_pack_ll_b32_b16 s31, s29, s73 +; GFX9-NEXT: s_add_i32 s72, s59, 0x7fff +; GFX9-NEXT: s_or_b32 s73, s58, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s8, s6, 16 -; GFX9-NEXT: s_lshl_b32 s6, s24, 16 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s9, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s10, s6, 0x400000 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s58, s73, s72 +; GFX9-NEXT: s_lshl_b32 s28, s28, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s28, v1 +; GFX9-NEXT: v_readfirstlane_b32 s28, v2 +; GFX9-NEXT: s_lshr_b32 s72, s58, 16 +; GFX9-NEXT: s_bfe_u32 s58, s28, 0x10010 +; GFX9-NEXT: s_add_i32 s58, s58, s28 +; GFX9-NEXT: s_add_i32 s73, s58, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s10, s9 -; GFX9-NEXT: s_lshr_b32 s24, s6, 16 -; GFX9-NEXT: s_and_b32 s6, s27, 0xffff0000 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s62, s24, s8 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_bitset1_b32 s28, 22 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s28, s28, s73 +; GFX9-NEXT: s_and_b32 s58, s27, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s58, v1 +; GFX9-NEXT: v_readfirstlane_b32 s58, v2 +; GFX9-NEXT: s_bfe_u32 s59, s58, 0x10010 +; GFX9-NEXT: s_lshr_b32 s28, s28, 16 +; GFX9-NEXT: s_add_i32 s59, s59, s58 +; GFX9-NEXT: s_pack_ll_b32_b16 s30, s28, s72 +; GFX9-NEXT: s_add_i32 s72, s59, 0x7fff +; GFX9-NEXT: s_or_b32 s73, s58, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s76, s6, 16 -; GFX9-NEXT: s_lshl_b32 s6, s27, 16 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s58, s73, s72 +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s27, v1 +; GFX9-NEXT: v_readfirstlane_b32 s27, v2 +; GFX9-NEXT: s_lshr_b32 s73, s58, 16 +; GFX9-NEXT: s_bfe_u32 s58, s27, 0x10010 +; GFX9-NEXT: s_add_i32 s58, s58, s27 +; GFX9-NEXT: s_add_i32 s72, s58, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s27, s6, 16 -; GFX9-NEXT: s_and_b32 s6, s26, 0xffff0000 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_bitset1_b32 s27, 22 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s27, s27, s72 +; GFX9-NEXT: s_and_b32 s58, s26, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s58, v1 +; GFX9-NEXT: v_readfirstlane_b32 s58, v2 +; GFX9-NEXT: s_bfe_u32 s59, s58, 0x10010 +; GFX9-NEXT: s_lshr_b32 s27, s27, 16 +; GFX9-NEXT: s_add_i32 s59, s59, s58 +; GFX9-NEXT: v_writelane_b32 v21, s73, 11 +; GFX9-NEXT: s_pack_ll_b32_b16 s95, s27, s73 +; GFX9-NEXT: s_add_i32 s72, s59, 0x7fff +; GFX9-NEXT: s_or_b32 s73, s58, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s8, s6, 16 -; GFX9-NEXT: s_lshl_b32 s6, s26, 16 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s9, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s10, s6, 0x400000 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s58, s73, s72 +; GFX9-NEXT: s_lshl_b32 s26, s26, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s26, v1 +; GFX9-NEXT: v_readfirstlane_b32 s26, v2 +; GFX9-NEXT: s_lshr_b32 s72, s58, 16 +; GFX9-NEXT: s_bfe_u32 s58, s26, 0x10010 +; GFX9-NEXT: s_add_i32 s58, s58, s26 +; GFX9-NEXT: s_add_i32 s73, s58, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s10, s9 -; GFX9-NEXT: s_lshr_b32 s26, s6, 16 -; GFX9-NEXT: s_and_b32 s6, s29, 0xffff0000 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s72, s26, s8 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_bitset1_b32 s26, 22 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s26, s26, s73 +; GFX9-NEXT: s_and_b32 s58, s25, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s58, v1 +; GFX9-NEXT: v_readfirstlane_b32 s58, v2 +; GFX9-NEXT: s_bfe_u32 s59, s58, 0x10010 +; GFX9-NEXT: s_lshr_b32 s26, s26, 16 +; GFX9-NEXT: s_add_i32 s59, s59, s58 +; GFX9-NEXT: s_pack_ll_b32_b16 s94, s26, s72 +; GFX9-NEXT: s_add_i32 s72, s59, 0x7fff +; GFX9-NEXT: s_or_b32 s73, s58, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s77, s6, 16 -; GFX9-NEXT: s_lshl_b32 s6, s29, 16 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s58, s73, s72 +; GFX9-NEXT: s_lshl_b32 s25, s25, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s25, v1 +; GFX9-NEXT: v_readfirstlane_b32 s25, v2 +; GFX9-NEXT: s_lshr_b32 s73, s58, 16 +; GFX9-NEXT: s_bfe_u32 s58, s25, 0x10010 +; GFX9-NEXT: s_add_i32 s58, s58, s25 +; GFX9-NEXT: s_add_i32 s72, s58, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s29, s6, 16 -; GFX9-NEXT: s_and_b32 s6, s28, 0xffff0000 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_bitset1_b32 s25, 22 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s25, s25, s72 +; GFX9-NEXT: s_and_b32 s58, s24, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s58, v1 +; GFX9-NEXT: v_readfirstlane_b32 s58, v2 +; GFX9-NEXT: s_bfe_u32 s59, s58, 0x10010 +; GFX9-NEXT: s_lshr_b32 s25, s25, 16 +; GFX9-NEXT: s_add_i32 s59, s59, s58 +; GFX9-NEXT: v_writelane_b32 v21, s73, 12 +; GFX9-NEXT: s_pack_ll_b32_b16 s91, s25, s73 +; GFX9-NEXT: s_add_i32 s72, s59, 0x7fff +; GFX9-NEXT: s_or_b32 s73, s58, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshr_b32 s8, s6, 16 -; GFX9-NEXT: s_lshl_b32 s6, s28, 16 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_add_i32 s9, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s10, s6, 0x400000 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s58, s73, s72 +; GFX9-NEXT: s_lshl_b32 s24, s24, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s24, v1 +; GFX9-NEXT: v_readfirstlane_b32 s24, v2 +; GFX9-NEXT: s_lshr_b32 s72, s58, 16 +; GFX9-NEXT: s_bfe_u32 s58, s24, 0x10010 +; GFX9-NEXT: s_add_i32 s58, s58, s24 +; GFX9-NEXT: s_add_i32 s73, s58, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s10, s9 -; GFX9-NEXT: s_lshr_b32 s28, s6, 16 -; GFX9-NEXT: s_and_b32 s6, s5, 0xffff0000 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s7, s7, s6 -; GFX9-NEXT: s_pack_ll_b32_b16 s74, s28, s8 -; GFX9-NEXT: s_add_i32 s8, s7, 0x7fff -; GFX9-NEXT: s_or_b32 s9, s6, 0x400000 +; GFX9-NEXT: s_bitset1_b32 s24, 22 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s24, s24, s73 +; GFX9-NEXT: s_and_b32 s58, s23, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s58, v1 +; GFX9-NEXT: v_readfirstlane_b32 s58, v2 +; GFX9-NEXT: s_bfe_u32 s59, s58, 0x10010 +; GFX9-NEXT: s_lshr_b32 s24, s24, 16 +; GFX9-NEXT: s_add_i32 s59, s59, s58 +; GFX9-NEXT: s_pack_ll_b32_b16 s90, s24, s72 +; GFX9-NEXT: s_add_i32 s72, s59, 0x7fff +; GFX9-NEXT: s_or_b32 s73, s58, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s9, s8 -; GFX9-NEXT: s_lshl_b32 s5, s5, 16 -; GFX9-NEXT: v_add_f32_e32 v2, s5, v1 -; GFX9-NEXT: v_readfirstlane_b32 s5, v2 -; GFX9-NEXT: s_lshr_b32 s78, s6, 16 -; GFX9-NEXT: s_bfe_u32 s6, s5, 0x10010 -; GFX9-NEXT: s_add_i32 s6, s6, s5 -; GFX9-NEXT: s_add_i32 s8, s6, 0x7fff -; GFX9-NEXT: s_bitset1_b32 s5, 22 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s58, s73, s72 +; GFX9-NEXT: s_lshl_b32 s23, s23, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s23, v1 +; GFX9-NEXT: v_readfirstlane_b32 s23, v2 +; GFX9-NEXT: s_lshr_b32 s73, s58, 16 +; GFX9-NEXT: s_bfe_u32 s58, s23, 0x10010 +; GFX9-NEXT: s_add_i32 s58, s58, s23 +; GFX9-NEXT: s_add_i32 s72, s58, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec -; GFX9-NEXT: s_cselect_b32 s5, s5, s8 -; GFX9-NEXT: s_and_b32 s6, s4, 0xffff0000 -; GFX9-NEXT: v_add_f32_e32 v2, s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s6, v2 -; GFX9-NEXT: s_bfe_u32 s8, s6, 0x10010 -; GFX9-NEXT: s_add_i32 s8, s8, s6 -; GFX9-NEXT: s_lshr_b32 s5, s5, 16 -; GFX9-NEXT: s_add_i32 s10, s8, 0x7fff -; GFX9-NEXT: s_bitset1_b32 s6, 22 +; GFX9-NEXT: s_bitset1_b32 s23, 22 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s23, s23, s72 +; GFX9-NEXT: s_and_b32 s58, s22, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s58, v1 +; GFX9-NEXT: v_readfirstlane_b32 s58, v2 +; GFX9-NEXT: s_bfe_u32 s59, s58, 0x10010 +; GFX9-NEXT: s_lshr_b32 s23, s23, 16 +; GFX9-NEXT: s_add_i32 s59, s59, s58 +; GFX9-NEXT: v_writelane_b32 v21, s73, 13 +; GFX9-NEXT: s_pack_ll_b32_b16 s77, s23, s73 +; GFX9-NEXT: s_add_i32 s72, s59, 0x7fff +; GFX9-NEXT: s_or_b32 s73, s58, 0x400000 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b64 s[8:9], vcc, exec -; GFX9-NEXT: s_cselect_b32 s6, s6, s10 -; GFX9-NEXT: s_lshl_b32 s4, s4, 16 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v1 -; GFX9-NEXT: v_readfirstlane_b32 s4, v1 -; GFX9-NEXT: s_bfe_u32 s8, s4, 0x10010 -; GFX9-NEXT: s_add_i32 s8, s8, s4 -; GFX9-NEXT: s_lshr_b32 s6, s6, 16 -; GFX9-NEXT: s_add_i32 s10, s8, 0x7fff -; GFX9-NEXT: s_bitset1_b32 s4, 22 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s58, s73, s72 +; GFX9-NEXT: s_lshl_b32 s22, s22, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s22, v1 +; GFX9-NEXT: v_readfirstlane_b32 s22, v2 +; GFX9-NEXT: s_lshr_b32 s72, s58, 16 +; GFX9-NEXT: s_bfe_u32 s58, s22, 0x10010 +; GFX9-NEXT: s_add_i32 s58, s58, s22 +; GFX9-NEXT: s_add_i32 s73, s58, 0x7fff +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; GFX9-NEXT: s_bitset1_b32 s22, 22 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s22, s22, s73 +; GFX9-NEXT: s_and_b32 s58, s21, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s58, v1 +; GFX9-NEXT: v_readfirstlane_b32 s58, v2 +; GFX9-NEXT: s_bfe_u32 s59, s58, 0x10010 +; GFX9-NEXT: s_lshr_b32 s22, s22, 16 +; GFX9-NEXT: s_add_i32 s59, s59, s58 +; GFX9-NEXT: s_pack_ll_b32_b16 s76, s22, s72 +; GFX9-NEXT: s_add_i32 s72, s59, 0x7fff +; GFX9-NEXT: s_or_b32 s73, s58, 0x400000 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s58, s73, s72 +; GFX9-NEXT: s_lshl_b32 s21, s21, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s21, v1 +; GFX9-NEXT: v_readfirstlane_b32 s21, v2 +; GFX9-NEXT: s_lshr_b32 s68, s58, 16 +; GFX9-NEXT: s_bfe_u32 s58, s21, 0x10010 +; GFX9-NEXT: s_add_i32 s58, s58, s21 +; GFX9-NEXT: s_add_i32 s72, s58, 0x7fff +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; GFX9-NEXT: s_bitset1_b32 s21, 22 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s21, s21, s72 +; GFX9-NEXT: s_and_b32 s58, s20, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s58, v1 +; GFX9-NEXT: v_readfirstlane_b32 s58, v2 +; GFX9-NEXT: s_bfe_u32 s59, s58, 0x10010 +; GFX9-NEXT: s_add_i32 s59, s59, s58 +; GFX9-NEXT: s_lshr_b32 s21, s21, 16 +; GFX9-NEXT: s_add_i32 s72, s59, 0x7fff +; GFX9-NEXT: s_or_b32 s38, s58, 0x400000 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s58, s38, s72 +; GFX9-NEXT: s_lshl_b32 s20, s20, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s20, v1 +; GFX9-NEXT: v_readfirstlane_b32 s20, v2 +; GFX9-NEXT: s_lshr_b32 s72, s58, 16 +; GFX9-NEXT: s_bfe_u32 s58, s20, 0x10010 +; GFX9-NEXT: s_add_i32 s58, s58, s20 +; GFX9-NEXT: s_add_i32 s38, s58, 0x7fff +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; GFX9-NEXT: s_bitset1_b32 s20, 22 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s20, s20, s38 +; GFX9-NEXT: s_and_b32 s58, s19, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s58, v1 +; GFX9-NEXT: v_readfirstlane_b32 s58, v2 +; GFX9-NEXT: s_bfe_u32 s59, s58, 0x10010 +; GFX9-NEXT: s_add_i32 s59, s59, s58 +; GFX9-NEXT: s_lshr_b32 s20, s20, 16 +; GFX9-NEXT: s_add_i32 s38, s59, 0x7fff +; GFX9-NEXT: s_or_b32 s39, s58, 0x400000 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s58, s39, s38 +; GFX9-NEXT: s_lshl_b32 s19, s19, 16 +; GFX9-NEXT: v_add_f32_e32 v2, s19, v1 +; GFX9-NEXT: v_readfirstlane_b32 s19, v2 +; GFX9-NEXT: s_lshr_b32 s69, s58, 16 +; GFX9-NEXT: s_bfe_u32 s58, s19, 0x10010 +; GFX9-NEXT: s_add_i32 s58, s58, s19 +; GFX9-NEXT: s_add_i32 s38, s58, 0x7fff +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; GFX9-NEXT: s_bitset1_b32 s19, 22 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s19, s19, s38 +; GFX9-NEXT: s_and_b32 s58, s18, 0xffff0000 +; GFX9-NEXT: v_add_f32_e32 v2, s58, v1 +; GFX9-NEXT: v_readfirstlane_b32 s58, v2 +; GFX9-NEXT: s_bfe_u32 s59, s58, 0x10010 +; GFX9-NEXT: s_add_i32 s59, s59, s58 +; GFX9-NEXT: s_lshr_b32 s19, s19, 16 +; GFX9-NEXT: s_add_i32 s38, s59, 0x7fff +; GFX9-NEXT: s_or_b32 s39, s58, 0x400000 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_cselect_b32 s58, s39, s38 +; GFX9-NEXT: s_lshl_b32 s18, s18, 16 +; GFX9-NEXT: v_add_f32_e32 v1, s18, v1 +; GFX9-NEXT: v_readfirstlane_b32 s18, v1 +; GFX9-NEXT: s_lshr_b32 s38, s58, 16 +; GFX9-NEXT: s_bfe_u32 s58, s18, 0x10010 +; GFX9-NEXT: s_add_i32 s58, s58, s18 +; GFX9-NEXT: s_add_i32 s39, s58, 0x7fff ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: v_lshrrev_b64 v[1:2], 24, v[25:26] -; GFX9-NEXT: s_and_b64 s[8:9], vcc, exec -; GFX9-NEXT: v_lshrrev_b64 v[2:3], 24, v[23:24] -; GFX9-NEXT: s_cselect_b32 s4, s4, s10 -; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[21:22] -; GFX9-NEXT: v_lshrrev_b64 v[9:10], 24, v[15:16] -; GFX9-NEXT: s_pack_ll_b32_b16 s47, s17, s11 -; GFX9-NEXT: s_pack_ll_b32_b16 s57, s19, s12 -; GFX9-NEXT: s_pack_ll_b32_b16 s59, s21, s13 -; GFX9-NEXT: s_lshr_b32 s4, s4, 16 -; GFX9-NEXT: v_lshrrev_b64 v[4:5], 24, v[19:20] -; GFX9-NEXT: v_lshrrev_b64 v[10:11], 24, v[13:14] -; GFX9-NEXT: s_pack_ll_b32_b16 s61, s23, s14 -; GFX9-NEXT: s_pack_ll_b32_b16 s63, s25, s15 -; GFX9-NEXT: s_pack_ll_b32_b16 s73, s27, s76 -; GFX9-NEXT: s_pack_ll_b32_b16 s75, s29, s77 -; GFX9-NEXT: s_pack_ll_b32_b16 s7, s5, s78 -; GFX9-NEXT: s_pack_ll_b32_b16 s6, s4, s6 -; GFX9-NEXT: s_lshr_b64 s[40:41], s[58:59], 24 -; GFX9-NEXT: s_lshr_b64 s[42:43], s[56:57], 24 -; GFX9-NEXT: s_lshr_b64 s[44:45], s[46:47], 24 -; GFX9-NEXT: v_lshrrev_b64 v[5:6], 24, v[17:18] -; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[7:8] -; GFX9-NEXT: s_lshr_b64 s[34:35], s[6:7], 24 -; GFX9-NEXT: s_lshr_b64 s[36:37], s[74:75], 24 -; GFX9-NEXT: s_lshr_b64 s[38:39], s[72:73], 24 -; GFX9-NEXT: s_lshr_b64 s[48:49], s[62:63], 24 -; GFX9-NEXT: s_lshr_b64 s[50:51], s[60:61], 24 -; GFX9-NEXT: s_lshr_b32 s9, s7, 24 -; GFX9-NEXT: s_lshr_b32 s10, s7, 8 -; GFX9-NEXT: s_lshr_b32 s41, s6, 16 -; GFX9-NEXT: s_lshr_b32 s43, s6, 8 -; GFX9-NEXT: s_lshr_b32 s45, s75, 24 -; GFX9-NEXT: s_lshr_b32 s75, s75, 8 -; GFX9-NEXT: s_lshr_b32 s79, s74, 16 -; GFX9-NEXT: s_lshr_b32 s74, s74, 8 -; GFX9-NEXT: s_lshr_b32 s88, s73, 24 -; GFX9-NEXT: s_lshr_b32 s73, s73, 8 -; GFX9-NEXT: s_lshr_b32 s89, s72, 16 -; GFX9-NEXT: s_lshr_b32 s72, s72, 8 -; GFX9-NEXT: s_lshr_b32 s90, s63, 24 -; GFX9-NEXT: s_lshr_b32 s63, s63, 8 -; GFX9-NEXT: s_lshr_b32 s91, s62, 16 -; GFX9-NEXT: s_lshr_b32 s62, s62, 8 -; GFX9-NEXT: s_lshr_b32 s92, s61, 24 -; GFX9-NEXT: s_lshr_b32 s61, s61, 8 -; GFX9-NEXT: s_lshr_b32 s93, s60, 16 -; GFX9-NEXT: s_lshr_b32 s60, s60, 8 -; GFX9-NEXT: s_lshr_b32 s94, s59, 24 -; GFX9-NEXT: s_lshr_b32 s59, s59, 8 -; GFX9-NEXT: s_lshr_b32 s95, s58, 16 -; GFX9-NEXT: s_lshr_b32 s58, s58, 8 -; GFX9-NEXT: s_lshr_b32 vcc_lo, s57, 24 -; GFX9-NEXT: s_lshr_b32 s57, s57, 8 -; GFX9-NEXT: s_lshr_b32 vcc_hi, s56, 16 -; GFX9-NEXT: s_lshr_b32 s56, s56, 8 -; GFX9-NEXT: s_lshr_b32 s30, s47, 24 -; GFX9-NEXT: s_lshr_b32 s47, s47, 8 -; GFX9-NEXT: s_lshr_b32 s8, s46, 16 -; GFX9-NEXT: s_lshr_b32 s7, s46, 8 -; GFX9-NEXT: v_lshrrev_b32_e32 v6, 24, v26 -; GFX9-NEXT: v_lshrrev_b32_e32 v12, 8, v26 -; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v25 -; GFX9-NEXT: v_lshrrev_b32_e32 v25, 8, v25 -; GFX9-NEXT: v_lshrrev_b32_e32 v43, 24, v24 -; GFX9-NEXT: v_lshrrev_b32_e32 v24, 8, v24 -; GFX9-NEXT: v_lshrrev_b32_e32 v44, 16, v23 -; GFX9-NEXT: v_lshrrev_b32_e32 v23, 8, v23 -; GFX9-NEXT: v_lshrrev_b32_e32 v45, 24, v22 -; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v22 -; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v21 -; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v21 -; GFX9-NEXT: v_lshrrev_b32_e32 v47, 24, v20 -; GFX9-NEXT: v_lshrrev_b32_e32 v20, 8, v20 -; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v19 -; GFX9-NEXT: v_lshrrev_b32_e32 v19, 8, v19 -; GFX9-NEXT: v_lshrrev_b32_e32 v57, 24, v18 -; GFX9-NEXT: v_lshrrev_b32_e32 v18, 8, v18 -; GFX9-NEXT: v_lshrrev_b32_e32 v58, 16, v17 -; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v17 -; GFX9-NEXT: v_lshrrev_b32_e32 v59, 24, v16 -; GFX9-NEXT: v_lshrrev_b32_e32 v16, 8, v16 -; GFX9-NEXT: v_lshrrev_b32_e32 v60, 16, v15 -; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v15 -; GFX9-NEXT: v_lshrrev_b32_e32 v61, 24, v14 -; GFX9-NEXT: v_lshrrev_b32_e32 v14, 8, v14 -; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v13 -; GFX9-NEXT: v_lshrrev_b32_e32 v13, 8, v13 -; GFX9-NEXT: v_lshrrev_b32_e32 v28, 24, v8 -; GFX9-NEXT: v_lshrrev_b32_e32 v8, 8, v8 -; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v7 -; GFX9-NEXT: v_lshrrev_b32_e32 v7, 8, v7 -; GFX9-NEXT: s_branch .LBB91_5 -; GFX9-NEXT: .LBB91_3: -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr78 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: v_writelane_b32 v62, s78, 0 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: v_writelane_b32 v62, s79, 1 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr78 -; GFX9-NEXT: ; implicit-def: $sgpr83 -; GFX9-NEXT: ; implicit-def: $sgpr38 -; GFX9-NEXT: ; implicit-def: $sgpr81 -; GFX9-NEXT: ; implicit-def: $sgpr8 -; GFX9-NEXT: ; implicit-def: $sgpr80 -; GFX9-NEXT: ; implicit-def: $sgpr86 -; GFX9-NEXT: ; implicit-def: $sgpr39 -; GFX9-NEXT: ; implicit-def: $sgpr84 -; GFX9-NEXT: ; implicit-def: $sgpr9 -; GFX9-NEXT: ; implicit-def: $sgpr82 -; GFX9-NEXT: ; implicit-def: $sgpr97 -; GFX9-NEXT: ; implicit-def: $sgpr48 -; GFX9-NEXT: ; implicit-def: $sgpr87 -; GFX9-NEXT: ; implicit-def: $sgpr10 -; GFX9-NEXT: ; implicit-def: $sgpr85 -; GFX9-NEXT: ; implicit-def: $sgpr54 -; GFX9-NEXT: ; implicit-def: $sgpr49 -; GFX9-NEXT: ; implicit-def: $sgpr98 -; GFX9-NEXT: ; implicit-def: $sgpr11 -; GFX9-NEXT: ; implicit-def: $sgpr96 -; GFX9-NEXT: ; implicit-def: $sgpr65 -; GFX9-NEXT: ; implicit-def: $sgpr50 -; GFX9-NEXT: ; implicit-def: $sgpr55 -; GFX9-NEXT: ; implicit-def: $sgpr12 -; GFX9-NEXT: ; implicit-def: $sgpr99 -; GFX9-NEXT: ; implicit-def: $sgpr68 -; GFX9-NEXT: ; implicit-def: $sgpr51 -; GFX9-NEXT: ; implicit-def: $sgpr66 -; GFX9-NEXT: ; implicit-def: $sgpr13 -; GFX9-NEXT: ; implicit-def: $sgpr64 -; GFX9-NEXT: ; implicit-def: $sgpr71 -; GFX9-NEXT: ; implicit-def: $sgpr69 -; GFX9-NEXT: ; implicit-def: $sgpr14 -; GFX9-NEXT: ; implicit-def: $sgpr67 -; GFX9-NEXT: ; implicit-def: $sgpr52 -; GFX9-NEXT: ; implicit-def: $sgpr53 -; GFX9-NEXT: ; implicit-def: $sgpr7 -; GFX9-NEXT: ; implicit-def: $sgpr15 -; GFX9-NEXT: ; implicit-def: $sgpr70 -; GFX9-NEXT: ; implicit-def: $sgpr44 -; GFX9-NEXT: ; implicit-def: $sgpr42 -; GFX9-NEXT: ; implicit-def: $sgpr40 -; GFX9-NEXT: ; implicit-def: $sgpr36 -; GFX9-NEXT: ; implicit-def: $sgpr34 -; GFX9-NEXT: ; implicit-def: $sgpr30 -; GFX9-NEXT: ; implicit-def: $sgpr94 -; GFX9-NEXT: ; implicit-def: $sgpr92 -; GFX9-NEXT: ; implicit-def: $sgpr90 -; GFX9-NEXT: ; implicit-def: $sgpr88 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: v_writelane_b32 v62, s78, 2 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: v_writelane_b32 v62, s79, 3 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr78 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: v_writelane_b32 v62, s78, 4 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: v_writelane_b32 v62, s79, 5 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr78 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: v_writelane_b32 v62, s78, 6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: v_writelane_b32 v62, s79, 7 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr78 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: v_writelane_b32 v62, s78, 8 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: v_writelane_b32 v62, s79, 9 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr78 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: ; kill: killed $sgpr6 -; GFX9-NEXT: ; implicit-def: $sgpr6 -; GFX9-NEXT: s_branch .LBB91_2 -; GFX9-NEXT: .LBB91_4: -; GFX9-NEXT: v_mov_b32_e32 v1, s9 -; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v1, s76 -; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v1, s77 -; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: s_bitset1_b32 s18, 22 +; GFX9-NEXT: s_and_b64 s[58:59], vcc, exec +; GFX9-NEXT: s_pack_ll_b32_b16 s59, s19, s69 +; GFX9-NEXT: s_cselect_b32 s18, s18, s39 +; GFX9-NEXT: s_lshr_b32 s18, s18, 16 +; GFX9-NEXT: s_lshr_b32 vcc_lo, s59, 24 +; GFX9-NEXT: s_pack_ll_b32_b16 s58, s18, s38 +; GFX9-NEXT: v_writelane_b32 v21, vcc_lo, 14 +; GFX9-NEXT: s_lshr_b32 vcc_lo, s59, 8 +; GFX9-NEXT: v_writelane_b32 v21, vcc_lo, 15 +; GFX9-NEXT: s_lshr_b32 vcc_lo, s58, 16 +; GFX9-NEXT: s_pack_ll_b32_b16 s73, s21, s68 +; GFX9-NEXT: v_writelane_b32 v21, vcc_lo, 16 +; GFX9-NEXT: s_lshr_b32 vcc_lo, s58, 8 +; GFX9-NEXT: s_lshr_b64 s[58:59], s[58:59], 24 +; GFX9-NEXT: v_writelane_b32 v21, vcc_lo, 17 +; GFX9-NEXT: s_lshr_b32 s59, s73, 24 +; GFX9-NEXT: s_pack_ll_b32_b16 s72, s20, s72 +; GFX9-NEXT: v_writelane_b32 v21, s59, 18 +; GFX9-NEXT: s_lshr_b32 s59, s73, 8 +; GFX9-NEXT: v_writelane_b32 v21, s59, 19 +; GFX9-NEXT: s_lshr_b32 s59, s72, 16 +; GFX9-NEXT: v_writelane_b32 v21, s59, 20 +; GFX9-NEXT: s_lshr_b32 s59, s72, 8 +; GFX9-NEXT: v_writelane_b32 v21, s59, 21 +; GFX9-NEXT: s_lshr_b32 s59, s77, 24 +; GFX9-NEXT: v_writelane_b32 v21, s59, 22 +; GFX9-NEXT: s_lshr_b32 s59, s77, 8 +; GFX9-NEXT: v_writelane_b32 v21, s59, 23 +; GFX9-NEXT: s_lshr_b32 s59, s76, 16 +; GFX9-NEXT: v_writelane_b32 v21, s59, 24 +; GFX9-NEXT: s_lshr_b32 s59, s76, 8 +; GFX9-NEXT: v_writelane_b32 v21, s59, 25 +; GFX9-NEXT: s_lshr_b32 s59, s91, 24 +; GFX9-NEXT: v_writelane_b32 v21, s59, 26 +; GFX9-NEXT: s_lshr_b32 s59, s91, 8 +; GFX9-NEXT: v_writelane_b32 v21, s59, 27 +; GFX9-NEXT: s_lshr_b32 s59, s90, 16 +; GFX9-NEXT: v_writelane_b32 v21, s59, 28 +; GFX9-NEXT: s_lshr_b32 s59, s90, 8 +; GFX9-NEXT: v_writelane_b32 v21, s59, 29 +; GFX9-NEXT: s_lshr_b32 s59, s95, 24 +; GFX9-NEXT: s_pack_ll_b32_b16 s46, s4, s46 +; GFX9-NEXT: s_lshr_b64 s[72:73], s[72:73], 24 +; GFX9-NEXT: s_lshr_b64 s[76:77], s[76:77], 24 +; GFX9-NEXT: s_lshr_b64 s[90:91], s[90:91], 24 +; GFX9-NEXT: v_writelane_b32 v21, s59, 30 +; GFX9-NEXT: s_lshr_b32 s59, s95, 8 +; GFX9-NEXT: v_writelane_b32 v21, s59, 31 +; GFX9-NEXT: s_lshr_b32 s59, s47, 24 +; GFX9-NEXT: s_lshr_b32 s73, s47, 8 +; GFX9-NEXT: s_lshr_b32 s77, s46, 16 +; GFX9-NEXT: s_lshr_b32 s91, s46, 8 +; GFX9-NEXT: s_lshr_b64 s[46:47], s[46:47], 24 +; GFX9-NEXT: s_lshr_b32 s47, s61, 24 +; GFX9-NEXT: v_writelane_b32 v21, s47, 32 +; GFX9-NEXT: s_lshr_b32 s47, s61, 8 +; GFX9-NEXT: v_writelane_b32 v21, s47, 33 +; GFX9-NEXT: s_lshr_b32 s47, s60, 16 +; GFX9-NEXT: v_writelane_b32 v21, s47, 34 +; GFX9-NEXT: s_lshr_b32 s47, s60, 8 +; GFX9-NEXT: v_writelane_b32 v21, s47, 35 +; GFX9-NEXT: s_lshr_b32 s47, s63, 8 +; GFX9-NEXT: s_lshr_b64 s[60:61], s[60:61], 24 +; GFX9-NEXT: v_writelane_b32 v21, s47, 36 +; GFX9-NEXT: s_lshr_b32 s47, s62, 16 +; GFX9-NEXT: s_pack_ll_b32_b16 s57, s7, s57 +; GFX9-NEXT: s_pack_ll_b32_b16 s56, s6, s56 +; GFX9-NEXT: s_lshr_b32 s38, s94, 16 +; GFX9-NEXT: s_lshr_b32 s48, s94, 8 +; GFX9-NEXT: s_lshr_b64 s[94:95], s[94:95], 24 +; GFX9-NEXT: s_lshr_b32 s50, s31, 24 +; GFX9-NEXT: s_lshr_b32 s51, s31, 8 +; GFX9-NEXT: s_lshr_b32 s53, s30, 16 +; GFX9-NEXT: s_lshr_b32 s71, s30, 8 +; GFX9-NEXT: s_lshr_b64 s[30:31], s[30:31], 24 +; GFX9-NEXT: s_lshr_b32 s80, s35, 24 +; GFX9-NEXT: s_lshr_b32 s82, s35, 8 +; GFX9-NEXT: s_lshr_b32 s65, s34, 16 +; GFX9-NEXT: s_lshr_b32 s85, s34, 8 +; GFX9-NEXT: s_lshr_b64 s[34:35], s[34:35], 24 +; GFX9-NEXT: s_lshr_b32 s66, s37, 24 +; GFX9-NEXT: s_lshr_b32 s97, s37, 8 +; GFX9-NEXT: s_lshr_b32 s99, s36, 16 +; GFX9-NEXT: s_lshr_b32 s67, s36, 8 +; GFX9-NEXT: s_lshr_b64 s[36:37], s[36:37], 24 +; GFX9-NEXT: s_lshr_b32 s61, s63, 24 +; GFX9-NEXT: v_writelane_b32 v21, s47, 37 +; GFX9-NEXT: s_lshr_b32 s47, s62, 8 +; GFX9-NEXT: s_lshr_b64 s[62:63], s[62:63], 24 +; GFX9-NEXT: s_lshr_b32 s95, s57, 24 +; GFX9-NEXT: s_lshr_b32 s31, s57, 8 +; GFX9-NEXT: s_lshr_b32 s35, s56, 16 +; GFX9-NEXT: s_lshr_b32 s37, s56, 8 +; GFX9-NEXT: s_lshr_b64 s[56:57], s[56:57], 24 +; GFX9-NEXT: v_writelane_b32 v21, s47, 38 +; GFX9-NEXT: s_lshr_b32 s63, s75, 24 +; GFX9-NEXT: s_lshr_b32 s47, s75, 8 +; GFX9-NEXT: s_lshr_b32 s54, s74, 16 +; GFX9-NEXT: s_lshr_b32 s39, s74, 8 +; GFX9-NEXT: s_lshr_b64 s[74:75], s[74:75], 24 +; GFX9-NEXT: s_lshr_b32 s49, s79, 24 +; GFX9-NEXT: s_lshr_b32 s55, s79, 8 +; GFX9-NEXT: s_lshr_b32 s52, s78, 16 +; GFX9-NEXT: s_lshr_b32 s70, s78, 8 +; GFX9-NEXT: s_lshr_b64 s[78:79], s[78:79], 24 +; GFX9-NEXT: s_lshr_b32 s64, s93, 24 +; GFX9-NEXT: s_lshr_b32 s81, s93, 8 +; GFX9-NEXT: s_lshr_b32 s83, s92, 16 +; GFX9-NEXT: s_lshr_b32 s84, s92, 8 +; GFX9-NEXT: s_lshr_b64 s[92:93], s[92:93], 24 +; GFX9-NEXT: s_lshr_b32 s86, s89, 24 +; GFX9-NEXT: s_lshr_b32 s87, s89, 8 +; GFX9-NEXT: s_lshr_b32 s96, s88, 16 +; GFX9-NEXT: s_lshr_b32 s98, s88, 8 +; GFX9-NEXT: s_lshr_b64 s[88:89], s[88:89], 24 +; GFX9-NEXT: v_writelane_b32 v21, s47, 39 +; GFX9-NEXT: .LBB91_3: ; %end +; GFX9-NEXT: s_lshl_b32 s47, s67, 8 +; GFX9-NEXT: s_and_b32 s44, s44, 0xff +; GFX9-NEXT: s_or_b32 s44, s44, s47 +; GFX9-NEXT: s_lshl_b32 s47, s36, 8 +; GFX9-NEXT: s_and_b32 s57, s99, 0xff +; GFX9-NEXT: s_or_b32 s47, s57, s47 +; GFX9-NEXT: s_and_b32 s44, s44, 0xffff +; GFX9-NEXT: s_lshl_b32 s47, s47, 16 +; GFX9-NEXT: s_or_b32 s44, s44, s47 +; GFX9-NEXT: v_mov_b32_e32 v1, s44 +; GFX9-NEXT: s_and_b32 s44, s45, 0xff +; GFX9-NEXT: s_lshl_b32 s45, s97, 8 +; GFX9-NEXT: s_or_b32 s44, s44, s45 +; GFX9-NEXT: v_readlane_b32 s45, v21, 8 +; GFX9-NEXT: s_and_b32 s45, s45, 0xff +; GFX9-NEXT: s_lshl_b32 s47, s66, 8 +; GFX9-NEXT: s_or_b32 s45, s45, s47 +; GFX9-NEXT: s_and_b32 s44, s44, 0xffff +; GFX9-NEXT: s_lshl_b32 s45, s45, 16 +; GFX9-NEXT: s_or_b32 s44, s44, s45 +; GFX9-NEXT: v_mov_b32_e32 v2, s44 +; GFX9-NEXT: s_lshl_b32 s44, s85, 8 +; GFX9-NEXT: s_and_b32 s42, s42, 0xff +; GFX9-NEXT: s_or_b32 s42, s42, s44 +; GFX9-NEXT: s_lshl_b32 s44, s34, 8 +; GFX9-NEXT: s_and_b32 s45, s65, 0xff +; GFX9-NEXT: s_or_b32 s44, s45, s44 +; GFX9-NEXT: s_and_b32 s42, s42, 0xffff +; GFX9-NEXT: s_lshl_b32 s44, s44, 16 +; GFX9-NEXT: s_or_b32 s42, s42, s44 +; GFX9-NEXT: v_mov_b32_e32 v3, s42 +; GFX9-NEXT: s_and_b32 s42, s43, 0xff +; GFX9-NEXT: s_lshl_b32 s43, s82, 8 +; GFX9-NEXT: s_or_b32 s42, s42, s43 +; GFX9-NEXT: v_readlane_b32 s43, v21, 9 +; GFX9-NEXT: s_and_b32 s43, s43, 0xff +; GFX9-NEXT: s_lshl_b32 s44, s80, 8 +; GFX9-NEXT: s_or_b32 s43, s43, s44 +; GFX9-NEXT: s_and_b32 s42, s42, 0xffff +; GFX9-NEXT: s_lshl_b32 s43, s43, 16 +; GFX9-NEXT: s_or_b32 s42, s42, s43 +; GFX9-NEXT: v_mov_b32_e32 v4, s42 +; GFX9-NEXT: s_lshl_b32 s42, s71, 8 +; GFX9-NEXT: s_and_b32 s28, s28, 0xff +; GFX9-NEXT: s_or_b32 s28, s28, s42 +; GFX9-NEXT: s_lshl_b32 s42, s30, 8 +; GFX9-NEXT: s_and_b32 s43, s53, 0xff +; GFX9-NEXT: s_or_b32 s42, s43, s42 +; GFX9-NEXT: s_and_b32 s28, s28, 0xffff +; GFX9-NEXT: s_lshl_b32 s42, s42, 16 +; GFX9-NEXT: s_or_b32 s28, s28, s42 +; GFX9-NEXT: v_mov_b32_e32 v5, s28 +; GFX9-NEXT: s_and_b32 s28, s29, 0xff +; GFX9-NEXT: s_lshl_b32 s29, s51, 8 +; GFX9-NEXT: s_or_b32 s28, s28, s29 +; GFX9-NEXT: v_readlane_b32 s29, v21, 10 +; GFX9-NEXT: s_and_b32 s29, s29, 0xff +; GFX9-NEXT: s_lshl_b32 s42, s50, 8 +; GFX9-NEXT: s_or_b32 s29, s29, s42 +; GFX9-NEXT: s_and_b32 s28, s28, 0xffff +; GFX9-NEXT: s_lshl_b32 s29, s29, 16 +; GFX9-NEXT: s_or_b32 s28, s28, s29 +; GFX9-NEXT: v_mov_b32_e32 v6, s28 +; GFX9-NEXT: s_lshl_b32 s28, s48, 8 +; GFX9-NEXT: s_and_b32 s26, s26, 0xff +; GFX9-NEXT: s_or_b32 s26, s26, s28 +; GFX9-NEXT: s_lshl_b32 s28, s94, 8 +; GFX9-NEXT: s_and_b32 s29, s38, 0xff +; GFX9-NEXT: s_or_b32 s28, s29, s28 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s28, s28, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s28 +; GFX9-NEXT: v_mov_b32_e32 v7, s26 +; GFX9-NEXT: s_and_b32 s26, s27, 0xff +; GFX9-NEXT: v_readlane_b32 s27, v21, 31 +; GFX9-NEXT: s_lshl_b32 s27, s27, 8 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_readlane_b32 s27, v21, 11 +; GFX9-NEXT: v_readlane_b32 s28, v21, 30 +; GFX9-NEXT: s_and_b32 s27, s27, 0xff +; GFX9-NEXT: s_lshl_b32 s28, s28, 8 +; GFX9-NEXT: s_or_b32 s27, s27, s28 +; GFX9-NEXT: s_and_b32 s26, s26, 0xffff +; GFX9-NEXT: s_lshl_b32 s27, s27, 16 +; GFX9-NEXT: s_or_b32 s26, s26, s27 +; GFX9-NEXT: v_mov_b32_e32 v8, s26 +; GFX9-NEXT: v_readlane_b32 s26, v21, 29 +; GFX9-NEXT: s_lshl_b32 s26, s26, 8 +; GFX9-NEXT: s_and_b32 s24, s24, 0xff +; GFX9-NEXT: v_readlane_b32 s27, v21, 28 +; GFX9-NEXT: s_or_b32 s24, s24, s26 +; GFX9-NEXT: s_lshl_b32 s26, s90, 8 +; GFX9-NEXT: s_and_b32 s27, s27, 0xff +; GFX9-NEXT: s_or_b32 s26, s27, s26 +; GFX9-NEXT: s_and_b32 s24, s24, 0xffff +; GFX9-NEXT: s_lshl_b32 s26, s26, 16 +; GFX9-NEXT: s_or_b32 s24, s24, s26 +; GFX9-NEXT: v_mov_b32_e32 v9, s24 +; GFX9-NEXT: s_and_b32 s24, s25, 0xff +; GFX9-NEXT: v_readlane_b32 s25, v21, 27 +; GFX9-NEXT: s_lshl_b32 s25, s25, 8 +; GFX9-NEXT: s_or_b32 s24, s24, s25 +; GFX9-NEXT: v_readlane_b32 s25, v21, 12 +; GFX9-NEXT: v_readlane_b32 s26, v21, 26 +; GFX9-NEXT: s_and_b32 s25, s25, 0xff +; GFX9-NEXT: s_lshl_b32 s26, s26, 8 +; GFX9-NEXT: s_or_b32 s25, s25, s26 +; GFX9-NEXT: s_and_b32 s24, s24, 0xffff +; GFX9-NEXT: s_lshl_b32 s25, s25, 16 +; GFX9-NEXT: s_or_b32 s24, s24, s25 +; GFX9-NEXT: v_mov_b32_e32 v10, s24 +; GFX9-NEXT: v_readlane_b32 s24, v21, 25 +; GFX9-NEXT: s_lshl_b32 s24, s24, 8 +; GFX9-NEXT: s_and_b32 s22, s22, 0xff +; GFX9-NEXT: v_readlane_b32 s25, v21, 24 +; GFX9-NEXT: s_or_b32 s22, s22, s24 +; GFX9-NEXT: s_lshl_b32 s24, s76, 8 +; GFX9-NEXT: s_and_b32 s25, s25, 0xff +; GFX9-NEXT: s_or_b32 s24, s25, s24 +; GFX9-NEXT: s_and_b32 s22, s22, 0xffff +; GFX9-NEXT: s_lshl_b32 s24, s24, 16 +; GFX9-NEXT: s_or_b32 s22, s22, s24 +; GFX9-NEXT: v_mov_b32_e32 v11, s22 +; GFX9-NEXT: s_and_b32 s22, s23, 0xff +; GFX9-NEXT: v_readlane_b32 s23, v21, 23 +; GFX9-NEXT: s_lshl_b32 s23, s23, 8 +; GFX9-NEXT: s_or_b32 s22, s22, s23 +; GFX9-NEXT: v_readlane_b32 s23, v21, 13 +; GFX9-NEXT: v_readlane_b32 s24, v21, 22 +; GFX9-NEXT: s_and_b32 s23, s23, 0xff +; GFX9-NEXT: s_lshl_b32 s24, s24, 8 +; GFX9-NEXT: s_or_b32 s23, s23, s24 +; GFX9-NEXT: s_and_b32 s22, s22, 0xffff +; GFX9-NEXT: s_lshl_b32 s23, s23, 16 +; GFX9-NEXT: s_or_b32 s22, s22, s23 +; GFX9-NEXT: v_mov_b32_e32 v12, s22 +; GFX9-NEXT: v_readlane_b32 s22, v21, 21 +; GFX9-NEXT: s_lshl_b32 s22, s22, 8 +; GFX9-NEXT: s_and_b32 s20, s20, 0xff +; GFX9-NEXT: v_readlane_b32 s23, v21, 20 +; GFX9-NEXT: s_or_b32 s20, s20, s22 +; GFX9-NEXT: s_lshl_b32 s22, s72, 8 +; GFX9-NEXT: s_and_b32 s23, s23, 0xff +; GFX9-NEXT: s_or_b32 s22, s23, s22 +; GFX9-NEXT: s_and_b32 s20, s20, 0xffff +; GFX9-NEXT: s_lshl_b32 s22, s22, 16 +; GFX9-NEXT: s_or_b32 s20, s20, s22 +; GFX9-NEXT: v_mov_b32_e32 v13, s20 +; GFX9-NEXT: s_and_b32 s20, s21, 0xff +; GFX9-NEXT: v_readlane_b32 s21, v21, 19 +; GFX9-NEXT: s_lshl_b32 s21, s21, 8 +; GFX9-NEXT: v_readlane_b32 s22, v21, 18 +; GFX9-NEXT: s_or_b32 s20, s20, s21 +; GFX9-NEXT: s_and_b32 s21, s68, 0xff +; GFX9-NEXT: s_lshl_b32 s22, s22, 8 +; GFX9-NEXT: s_or_b32 s21, s21, s22 +; GFX9-NEXT: s_and_b32 s20, s20, 0xffff +; GFX9-NEXT: s_lshl_b32 s21, s21, 16 +; GFX9-NEXT: s_or_b32 s20, s20, s21 +; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen +; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:4 +; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:8 +; GFX9-NEXT: buffer_store_dword v4, v0, s[0:3], 0 offen offset:12 +; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:16 +; GFX9-NEXT: buffer_store_dword v6, v0, s[0:3], 0 offen offset:20 +; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:24 +; GFX9-NEXT: buffer_store_dword v8, v0, s[0:3], 0 offen offset:28 +; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:32 +; GFX9-NEXT: buffer_store_dword v10, v0, s[0:3], 0 offen offset:36 +; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:40 +; GFX9-NEXT: buffer_store_dword v12, v0, s[0:3], 0 offen offset:44 +; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:48 +; GFX9-NEXT: v_mov_b32_e32 v1, s20 +; GFX9-NEXT: v_readlane_b32 s20, v21, 17 +; GFX9-NEXT: s_and_b32 s18, s18, 0xff +; GFX9-NEXT: s_lshl_b32 s20, s20, 8 +; GFX9-NEXT: s_or_b32 s18, s18, s20 +; GFX9-NEXT: v_readlane_b32 s20, v21, 16 +; GFX9-NEXT: s_and_b32 s20, s20, 0xff +; GFX9-NEXT: s_lshl_b32 s21, s58, 8 +; GFX9-NEXT: s_or_b32 s20, s20, s21 +; GFX9-NEXT: s_and_b32 s18, s18, 0xffff +; GFX9-NEXT: s_lshl_b32 s20, s20, 16 +; GFX9-NEXT: s_or_b32 s18, s18, s20 +; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52 +; GFX9-NEXT: v_mov_b32_e32 v1, s18 +; GFX9-NEXT: s_and_b32 s18, s19, 0xff +; GFX9-NEXT: v_readlane_b32 s19, v21, 15 +; GFX9-NEXT: s_lshl_b32 s19, s19, 8 +; GFX9-NEXT: v_readlane_b32 s20, v21, 14 +; GFX9-NEXT: s_or_b32 s18, s18, s19 +; GFX9-NEXT: s_and_b32 s19, s69, 0xff +; GFX9-NEXT: s_lshl_b32 s20, s20, 8 +; GFX9-NEXT: s_or_b32 s19, s19, s20 +; GFX9-NEXT: s_and_b32 s18, s18, 0xffff +; GFX9-NEXT: s_lshl_b32 s19, s19, 16 +; GFX9-NEXT: s_or_b32 s18, s18, s19 +; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56 +; GFX9-NEXT: v_mov_b32_e32 v1, s18 +; GFX9-NEXT: s_and_b32 s18, s40, 0xff +; GFX9-NEXT: s_lshl_b32 s19, s98, 8 +; GFX9-NEXT: s_or_b32 s18, s18, s19 +; GFX9-NEXT: s_and_b32 s19, s96, 0xff +; GFX9-NEXT: s_lshl_b32 s20, s88, 8 +; GFX9-NEXT: s_or_b32 s19, s19, s20 +; GFX9-NEXT: s_and_b32 s18, s18, 0xffff +; GFX9-NEXT: s_lshl_b32 s19, s19, 16 +; GFX9-NEXT: s_or_b32 s18, s18, s19 +; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60 +; GFX9-NEXT: v_mov_b32_e32 v1, s18 +; GFX9-NEXT: s_and_b32 s18, s41, 0xff +; GFX9-NEXT: s_lshl_b32 s19, s87, 8 +; GFX9-NEXT: s_or_b32 s18, s18, s19 +; GFX9-NEXT: v_readlane_b32 s19, v21, 0 +; GFX9-NEXT: s_and_b32 s19, s19, 0xff +; GFX9-NEXT: s_lshl_b32 s20, s86, 8 +; GFX9-NEXT: s_or_b32 s19, s19, s20 +; GFX9-NEXT: s_and_b32 s18, s18, 0xffff +; GFX9-NEXT: s_lshl_b32 s19, s19, 16 +; GFX9-NEXT: s_or_b32 s18, s18, s19 +; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:64 +; GFX9-NEXT: v_mov_b32_e32 v1, s18 +; GFX9-NEXT: s_and_b32 s16, s16, 0xff +; GFX9-NEXT: s_lshl_b32 s18, s84, 8 +; GFX9-NEXT: s_or_b32 s16, s16, s18 +; GFX9-NEXT: s_and_b32 s18, s83, 0xff +; GFX9-NEXT: s_lshl_b32 s19, s92, 8 +; GFX9-NEXT: s_or_b32 s18, s18, s19 +; GFX9-NEXT: s_and_b32 s16, s16, 0xffff +; GFX9-NEXT: s_lshl_b32 s18, s18, 16 +; GFX9-NEXT: s_or_b32 s16, s16, s18 +; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:68 +; GFX9-NEXT: v_mov_b32_e32 v1, s16 +; GFX9-NEXT: s_and_b32 s16, s17, 0xff +; GFX9-NEXT: s_lshl_b32 s17, s81, 8 +; GFX9-NEXT: s_or_b32 s16, s16, s17 +; GFX9-NEXT: v_readlane_b32 s17, v21, 1 +; GFX9-NEXT: s_and_b32 s17, s17, 0xff +; GFX9-NEXT: s_lshl_b32 s18, s64, 8 +; GFX9-NEXT: s_or_b32 s17, s17, s18 +; GFX9-NEXT: s_and_b32 s16, s16, 0xffff +; GFX9-NEXT: s_lshl_b32 s17, s17, 16 +; GFX9-NEXT: s_or_b32 s16, s16, s17 +; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:72 +; GFX9-NEXT: v_mov_b32_e32 v1, s16 +; GFX9-NEXT: s_and_b32 s14, s14, 0xff +; GFX9-NEXT: s_lshl_b32 s16, s70, 8 +; GFX9-NEXT: s_or_b32 s14, s14, s16 +; GFX9-NEXT: s_and_b32 s16, s52, 0xff +; GFX9-NEXT: s_lshl_b32 s17, s78, 8 +; GFX9-NEXT: s_or_b32 s16, s16, s17 +; GFX9-NEXT: s_and_b32 s14, s14, 0xffff +; GFX9-NEXT: s_lshl_b32 s16, s16, 16 +; GFX9-NEXT: s_or_b32 s14, s14, s16 +; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:76 +; GFX9-NEXT: v_mov_b32_e32 v1, s14 +; GFX9-NEXT: s_and_b32 s14, s15, 0xff +; GFX9-NEXT: s_lshl_b32 s15, s55, 8 +; GFX9-NEXT: s_or_b32 s14, s14, s15 +; GFX9-NEXT: v_readlane_b32 s15, v21, 2 +; GFX9-NEXT: s_and_b32 s15, s15, 0xff +; GFX9-NEXT: s_lshl_b32 s16, s49, 8 +; GFX9-NEXT: s_or_b32 s15, s15, s16 +; GFX9-NEXT: s_and_b32 s14, s14, 0xffff +; GFX9-NEXT: s_lshl_b32 s15, s15, 16 +; GFX9-NEXT: s_or_b32 s14, s14, s15 +; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:80 +; GFX9-NEXT: v_mov_b32_e32 v1, s14 +; GFX9-NEXT: s_and_b32 s12, s12, 0xff +; GFX9-NEXT: s_lshl_b32 s14, s39, 8 +; GFX9-NEXT: s_or_b32 s12, s12, s14 +; GFX9-NEXT: s_and_b32 s14, s54, 0xff +; GFX9-NEXT: s_lshl_b32 s15, s74, 8 +; GFX9-NEXT: s_or_b32 s14, s14, s15 +; GFX9-NEXT: s_and_b32 s12, s12, 0xffff +; GFX9-NEXT: s_lshl_b32 s14, s14, 16 +; GFX9-NEXT: s_or_b32 s12, s12, s14 +; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:84 +; GFX9-NEXT: v_mov_b32_e32 v1, s12 +; GFX9-NEXT: s_and_b32 s12, s13, 0xff +; GFX9-NEXT: v_readlane_b32 s13, v21, 39 +; GFX9-NEXT: s_lshl_b32 s13, s13, 8 +; GFX9-NEXT: s_or_b32 s12, s12, s13 +; GFX9-NEXT: v_readlane_b32 s13, v21, 3 +; GFX9-NEXT: s_and_b32 s13, s13, 0xff +; GFX9-NEXT: s_lshl_b32 s14, s63, 8 +; GFX9-NEXT: s_or_b32 s13, s13, s14 +; GFX9-NEXT: s_and_b32 s12, s12, 0xffff +; GFX9-NEXT: s_lshl_b32 s13, s13, 16 +; GFX9-NEXT: s_or_b32 s12, s12, s13 +; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:88 +; GFX9-NEXT: v_mov_b32_e32 v1, s12 +; GFX9-NEXT: v_readlane_b32 s12, v21, 38 +; GFX9-NEXT: s_and_b32 s10, s10, 0xff +; GFX9-NEXT: s_lshl_b32 s12, s12, 8 +; GFX9-NEXT: s_or_b32 s10, s10, s12 +; GFX9-NEXT: v_readlane_b32 s12, v21, 37 +; GFX9-NEXT: s_and_b32 s12, s12, 0xff +; GFX9-NEXT: s_lshl_b32 s13, s62, 8 +; GFX9-NEXT: s_or_b32 s12, s12, s13 +; GFX9-NEXT: s_and_b32 s10, s10, 0xffff +; GFX9-NEXT: s_lshl_b32 s12, s12, 16 +; GFX9-NEXT: s_or_b32 s10, s10, s12 +; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:92 +; GFX9-NEXT: v_mov_b32_e32 v1, s10 +; GFX9-NEXT: s_and_b32 s10, s11, 0xff +; GFX9-NEXT: v_readlane_b32 s11, v21, 36 +; GFX9-NEXT: s_lshl_b32 s11, s11, 8 +; GFX9-NEXT: s_or_b32 s10, s10, s11 +; GFX9-NEXT: v_readlane_b32 s11, v21, 4 +; GFX9-NEXT: s_and_b32 s11, s11, 0xff +; GFX9-NEXT: s_lshl_b32 s12, s61, 8 +; GFX9-NEXT: s_or_b32 s11, s11, s12 +; GFX9-NEXT: s_and_b32 s10, s10, 0xffff +; GFX9-NEXT: s_lshl_b32 s11, s11, 16 +; GFX9-NEXT: s_or_b32 s10, s10, s11 +; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:96 +; GFX9-NEXT: v_mov_b32_e32 v1, s10 +; GFX9-NEXT: v_readlane_b32 s10, v21, 35 +; GFX9-NEXT: s_and_b32 s8, s8, 0xff +; GFX9-NEXT: s_lshl_b32 s10, s10, 8 +; GFX9-NEXT: s_or_b32 s8, s8, s10 +; GFX9-NEXT: v_readlane_b32 s10, v21, 34 +; GFX9-NEXT: s_and_b32 s10, s10, 0xff +; GFX9-NEXT: s_lshl_b32 s11, s60, 8 +; GFX9-NEXT: s_or_b32 s10, s10, s11 +; GFX9-NEXT: s_and_b32 s8, s8, 0xffff +; GFX9-NEXT: s_lshl_b32 s10, s10, 16 +; GFX9-NEXT: s_or_b32 s8, s8, s10 +; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:100 ; GFX9-NEXT: v_mov_b32_e32 v1, s8 -; GFX9-NEXT: v_mov_b32_e32 v46, s51 -; GFX9-NEXT: v_mov_b32_e32 v56, s50 -; GFX9-NEXT: v_mov_b32_e32 v58, s49 -; GFX9-NEXT: v_mov_b32_e32 v60, s48 -; GFX9-NEXT: v_mov_b32_e32 v27, s39 -; GFX9-NEXT: v_mov_b32_e32 v29, s38 -; GFX9-NEXT: v_mov_b32_e32 v10, s34 -; GFX9-NEXT: v_mov_b32_e32 v11, s36 -; GFX9-NEXT: v_readlane_b32 s34, v62, 8 -; GFX9-NEXT: v_readlane_b32 s36, v62, 6 -; GFX9-NEXT: v_readlane_b32 s38, v62, 4 -; GFX9-NEXT: v_readlane_b32 s48, v62, 2 -; GFX9-NEXT: v_readlane_b32 s50, v62, 0 -; GFX9-NEXT: v_mov_b32_e32 v42, s46 -; GFX9-NEXT: v_mov_b32_e32 v41, s47 -; GFX9-NEXT: v_mov_b32_e32 v55, s15 -; GFX9-NEXT: v_mov_b32_e32 v40, s56 -; GFX9-NEXT: v_mov_b32_e32 v54, s57 -; GFX9-NEXT: v_mov_b32_e32 v52, s14 -; GFX9-NEXT: v_mov_b32_e32 v53, s58 -; GFX9-NEXT: v_mov_b32_e32 v51, s59 -; GFX9-NEXT: v_mov_b32_e32 v49, s13 -; GFX9-NEXT: v_mov_b32_e32 v50, s60 -; GFX9-NEXT: v_mov_b32_e32 v48, s61 -; GFX9-NEXT: v_mov_b32_e32 v38, s12 -; GFX9-NEXT: v_mov_b32_e32 v39, s62 -; GFX9-NEXT: v_mov_b32_e32 v37, s63 -; GFX9-NEXT: v_mov_b32_e32 v35, s11 -; GFX9-NEXT: v_mov_b32_e32 v36, s72 -; GFX9-NEXT: v_mov_b32_e32 v34, s73 -; GFX9-NEXT: v_mov_b32_e32 v32, s10 -; GFX9-NEXT: v_mov_b32_e32 v33, s74 -; GFX9-NEXT: v_mov_b32_e32 v31, s75 -; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v26, s53 -; GFX9-NEXT: v_mov_b32_e32 v25, s52 -; GFX9-NEXT: v_mov_b32_e32 v6, s70 -; GFX9-NEXT: v_mov_b32_e32 v12, s7 -; GFX9-NEXT: v_mov_b32_e32 v44, s6 -; GFX9-NEXT: v_mov_b32_e32 v23, s71 -; GFX9-NEXT: v_mov_b32_e32 v43, s67 -; GFX9-NEXT: v_mov_b32_e32 v24, s69 -; GFX9-NEXT: v_mov_b32_e32 v21, s68 -; GFX9-NEXT: v_mov_b32_e32 v45, s64 -; GFX9-NEXT: v_mov_b32_e32 v22, s66 -; GFX9-NEXT: v_mov_b32_e32 v19, s65 -; GFX9-NEXT: v_mov_b32_e32 v47, s99 -; GFX9-NEXT: v_mov_b32_e32 v20, s55 -; GFX9-NEXT: v_mov_b32_e32 v17, s54 -; GFX9-NEXT: v_mov_b32_e32 v57, s96 -; GFX9-NEXT: v_mov_b32_e32 v18, s98 -; GFX9-NEXT: v_mov_b32_e32 v15, s97 -; GFX9-NEXT: v_mov_b32_e32 v59, s85 -; GFX9-NEXT: v_mov_b32_e32 v16, s87 -; GFX9-NEXT: v_mov_b32_e32 v13, s86 -; GFX9-NEXT: v_mov_b32_e32 v61, s82 -; GFX9-NEXT: v_mov_b32_e32 v14, s84 -; GFX9-NEXT: v_mov_b32_e32 v7, s83 -; GFX9-NEXT: v_mov_b32_e32 v28, s80 -; GFX9-NEXT: v_mov_b32_e32 v8, s81 -; GFX9-NEXT: v_mov_b32_e32 v1, s78 -; GFX9-NEXT: v_mov_b32_e32 v2, s88 -; GFX9-NEXT: v_mov_b32_e32 v3, s90 -; GFX9-NEXT: v_mov_b32_e32 v4, s92 -; GFX9-NEXT: v_mov_b32_e32 v5, s94 -; GFX9-NEXT: v_mov_b32_e32 v9, s30 -; GFX9-NEXT: v_readlane_b32 s11, v62, 10 -; GFX9-NEXT: v_readlane_b32 s12, v62, 11 -; GFX9-NEXT: v_readlane_b32 s13, v62, 12 -; GFX9-NEXT: v_readlane_b32 s14, v62, 13 -; GFX9-NEXT: v_readlane_b32 s15, v62, 14 -; GFX9-NEXT: v_readlane_b32 s76, v62, 15 -; GFX9-NEXT: v_readlane_b32 s77, v62, 16 -; GFX9-NEXT: v_readlane_b32 s78, v62, 17 -; GFX9-NEXT: v_readlane_b32 s9, v62, 18 -; GFX9-NEXT: v_readlane_b32 s10, v62, 19 -; GFX9-NEXT: v_readlane_b32 s41, v62, 20 -; GFX9-NEXT: v_readlane_b32 s43, v62, 21 -; GFX9-NEXT: v_readlane_b32 s45, v62, 22 -; GFX9-NEXT: v_readlane_b32 s75, v62, 23 -; GFX9-NEXT: v_readlane_b32 s79, v62, 24 -; GFX9-NEXT: v_readlane_b32 s74, v62, 25 -; GFX9-NEXT: v_readlane_b32 s88, v62, 26 -; GFX9-NEXT: v_readlane_b32 s73, v62, 27 -; GFX9-NEXT: v_readlane_b32 s89, v62, 28 -; GFX9-NEXT: v_readlane_b32 s72, v62, 29 -; GFX9-NEXT: v_readlane_b32 s90, v62, 30 -; GFX9-NEXT: v_readlane_b32 s63, v62, 31 -; GFX9-NEXT: v_readlane_b32 s91, v62, 32 -; GFX9-NEXT: v_readlane_b32 s62, v62, 33 -; GFX9-NEXT: v_readlane_b32 s92, v62, 34 -; GFX9-NEXT: v_readlane_b32 s61, v62, 35 -; GFX9-NEXT: v_readlane_b32 s93, v62, 36 -; GFX9-NEXT: v_readlane_b32 s60, v62, 37 -; GFX9-NEXT: v_readlane_b32 s94, v62, 38 -; GFX9-NEXT: v_readlane_b32 s59, v62, 39 -; GFX9-NEXT: v_readlane_b32 s95, v62, 40 -; GFX9-NEXT: v_readlane_b32 s58, v62, 41 -; GFX9-NEXT: v_readlane_b32 vcc_lo, v62, 42 -; GFX9-NEXT: v_readlane_b32 s57, v62, 43 -; GFX9-NEXT: v_readlane_b32 vcc_hi, v62, 44 -; GFX9-NEXT: v_readlane_b32 s56, v62, 45 -; GFX9-NEXT: v_readlane_b32 s30, v62, 46 -; GFX9-NEXT: v_readlane_b32 s47, v62, 47 -; GFX9-NEXT: v_readlane_b32 s8, v62, 48 -; GFX9-NEXT: v_readlane_b32 s7, v62, 49 -; GFX9-NEXT: v_readlane_b32 s35, v62, 9 -; GFX9-NEXT: v_readlane_b32 s37, v62, 7 -; GFX9-NEXT: v_readlane_b32 s39, v62, 5 -; GFX9-NEXT: v_readlane_b32 s49, v62, 3 -; GFX9-NEXT: v_readlane_b32 s51, v62, 1 -; GFX9-NEXT: .LBB91_5: ; %end -; GFX9-NEXT: s_and_b32 s6, s16, 0xff -; GFX9-NEXT: s_lshl_b32 s7, s7, 8 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: s_and_b32 s7, s8, 0xff -; GFX9-NEXT: s_lshl_b32 s8, s44, 8 -; GFX9-NEXT: s_or_b32 s7, s7, s8 -; GFX9-NEXT: s_and_b32 s6, s6, 0xffff -; GFX9-NEXT: s_lshl_b32 s7, s7, 16 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: v_mov_b32_e32 v30, s6 -; GFX9-NEXT: s_and_b32 s6, s17, 0xff -; GFX9-NEXT: s_lshl_b32 s7, s47, 8 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: s_and_b32 s7, s11, 0xff -; GFX9-NEXT: s_lshl_b32 s8, s30, 8 -; GFX9-NEXT: s_or_b32 s7, s7, s8 -; GFX9-NEXT: s_and_b32 s6, s6, 0xffff -; GFX9-NEXT: s_lshl_b32 s7, s7, 16 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: buffer_store_dword v30, v0, s[0:3], 0 offen -; GFX9-NEXT: v_mov_b32_e32 v30, s6 -; GFX9-NEXT: s_and_b32 s6, s18, 0xff -; GFX9-NEXT: s_lshl_b32 s7, s56, 8 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: s_and_b32 s7, vcc_hi, 0xff -; GFX9-NEXT: s_lshl_b32 s8, s42, 8 -; GFX9-NEXT: s_or_b32 s7, s7, s8 -; GFX9-NEXT: s_and_b32 s6, s6, 0xffff -; GFX9-NEXT: s_lshl_b32 s7, s7, 16 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: buffer_store_dword v30, v0, s[0:3], 0 offen offset:4 -; GFX9-NEXT: v_mov_b32_e32 v30, s6 -; GFX9-NEXT: s_and_b32 s6, s19, 0xff -; GFX9-NEXT: s_lshl_b32 s7, s57, 8 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: s_and_b32 s7, s12, 0xff -; GFX9-NEXT: s_lshl_b32 s8, vcc_lo, 8 -; GFX9-NEXT: s_or_b32 s7, s7, s8 -; GFX9-NEXT: s_and_b32 s6, s6, 0xffff -; GFX9-NEXT: s_lshl_b32 s7, s7, 16 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: buffer_store_dword v30, v0, s[0:3], 0 offen offset:8 -; GFX9-NEXT: v_mov_b32_e32 v30, s6 -; GFX9-NEXT: s_and_b32 s6, s20, 0xff -; GFX9-NEXT: s_lshl_b32 s7, s58, 8 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: s_and_b32 s7, s95, 0xff -; GFX9-NEXT: s_lshl_b32 s8, s40, 8 -; GFX9-NEXT: s_or_b32 s7, s7, s8 -; GFX9-NEXT: s_and_b32 s6, s6, 0xffff -; GFX9-NEXT: s_lshl_b32 s7, s7, 16 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: buffer_store_dword v30, v0, s[0:3], 0 offen offset:12 -; GFX9-NEXT: v_mov_b32_e32 v30, s6 -; GFX9-NEXT: s_and_b32 s6, s21, 0xff -; GFX9-NEXT: s_lshl_b32 s7, s59, 8 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: s_and_b32 s7, s13, 0xff -; GFX9-NEXT: s_lshl_b32 s8, s94, 8 -; GFX9-NEXT: s_or_b32 s7, s7, s8 -; GFX9-NEXT: s_and_b32 s6, s6, 0xffff -; GFX9-NEXT: s_lshl_b32 s7, s7, 16 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: buffer_store_dword v30, v0, s[0:3], 0 offen offset:16 -; GFX9-NEXT: v_mov_b32_e32 v30, s6 -; GFX9-NEXT: s_and_b32 s6, s22, 0xff -; GFX9-NEXT: s_lshl_b32 s7, s60, 8 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: s_and_b32 s7, s93, 0xff -; GFX9-NEXT: s_lshl_b32 s8, s50, 8 -; GFX9-NEXT: s_or_b32 s7, s7, s8 -; GFX9-NEXT: s_and_b32 s6, s6, 0xffff -; GFX9-NEXT: s_lshl_b32 s7, s7, 16 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: buffer_store_dword v30, v0, s[0:3], 0 offen offset:20 -; GFX9-NEXT: v_mov_b32_e32 v30, s6 -; GFX9-NEXT: s_and_b32 s6, s23, 0xff -; GFX9-NEXT: s_lshl_b32 s7, s61, 8 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: s_and_b32 s7, s14, 0xff -; GFX9-NEXT: s_lshl_b32 s8, s92, 8 -; GFX9-NEXT: s_or_b32 s7, s7, s8 -; GFX9-NEXT: s_and_b32 s6, s6, 0xffff -; GFX9-NEXT: s_lshl_b32 s7, s7, 16 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: buffer_store_dword v30, v0, s[0:3], 0 offen offset:24 -; GFX9-NEXT: v_mov_b32_e32 v30, s6 -; GFX9-NEXT: s_and_b32 s6, s24, 0xff -; GFX9-NEXT: s_lshl_b32 s7, s62, 8 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: s_and_b32 s7, s91, 0xff -; GFX9-NEXT: s_lshl_b32 s8, s48, 8 -; GFX9-NEXT: s_or_b32 s7, s7, s8 -; GFX9-NEXT: s_and_b32 s6, s6, 0xffff -; GFX9-NEXT: s_lshl_b32 s7, s7, 16 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: buffer_store_dword v30, v0, s[0:3], 0 offen offset:28 -; GFX9-NEXT: v_mov_b32_e32 v30, s6 -; GFX9-NEXT: s_and_b32 s6, s25, 0xff -; GFX9-NEXT: s_lshl_b32 s7, s63, 8 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: s_and_b32 s7, s15, 0xff -; GFX9-NEXT: s_lshl_b32 s8, s90, 8 -; GFX9-NEXT: s_or_b32 s7, s7, s8 -; GFX9-NEXT: s_and_b32 s6, s6, 0xffff -; GFX9-NEXT: s_lshl_b32 s7, s7, 16 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: buffer_store_dword v30, v0, s[0:3], 0 offen offset:32 -; GFX9-NEXT: v_mov_b32_e32 v30, s6 -; GFX9-NEXT: s_and_b32 s6, s26, 0xff -; GFX9-NEXT: s_lshl_b32 s7, s72, 8 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: s_and_b32 s7, s89, 0xff -; GFX9-NEXT: s_lshl_b32 s8, s38, 8 -; GFX9-NEXT: s_or_b32 s7, s7, s8 -; GFX9-NEXT: s_and_b32 s6, s6, 0xffff -; GFX9-NEXT: s_lshl_b32 s7, s7, 16 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: buffer_store_dword v30, v0, s[0:3], 0 offen offset:36 -; GFX9-NEXT: v_mov_b32_e32 v30, s6 -; GFX9-NEXT: s_and_b32 s6, s27, 0xff -; GFX9-NEXT: s_lshl_b32 s7, s73, 8 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: s_and_b32 s7, s76, 0xff -; GFX9-NEXT: s_lshl_b32 s8, s88, 8 -; GFX9-NEXT: s_or_b32 s7, s7, s8 -; GFX9-NEXT: s_and_b32 s6, s6, 0xffff -; GFX9-NEXT: s_lshl_b32 s7, s7, 16 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: buffer_store_dword v30, v0, s[0:3], 0 offen offset:40 -; GFX9-NEXT: v_mov_b32_e32 v30, s6 -; GFX9-NEXT: s_and_b32 s6, s28, 0xff -; GFX9-NEXT: s_lshl_b32 s7, s74, 8 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: s_and_b32 s7, s79, 0xff -; GFX9-NEXT: s_lshl_b32 s8, s36, 8 -; GFX9-NEXT: s_or_b32 s7, s7, s8 +; GFX9-NEXT: s_and_b32 s8, s9, 0xff +; GFX9-NEXT: v_readlane_b32 s9, v21, 33 +; GFX9-NEXT: s_lshl_b32 s9, s9, 8 +; GFX9-NEXT: s_or_b32 s8, s8, s9 +; GFX9-NEXT: v_readlane_b32 s9, v21, 5 +; GFX9-NEXT: v_readlane_b32 s10, v21, 32 +; GFX9-NEXT: s_and_b32 s9, s9, 0xff +; GFX9-NEXT: s_lshl_b32 s10, s10, 8 +; GFX9-NEXT: s_or_b32 s9, s9, s10 +; GFX9-NEXT: s_and_b32 s8, s8, 0xffff +; GFX9-NEXT: s_lshl_b32 s9, s9, 16 +; GFX9-NEXT: s_or_b32 s8, s8, s9 +; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:104 +; GFX9-NEXT: v_mov_b32_e32 v1, s8 +; GFX9-NEXT: s_and_b32 s6, s6, 0xff +; GFX9-NEXT: s_lshl_b32 s8, s37, 8 +; GFX9-NEXT: s_or_b32 s6, s6, s8 +; GFX9-NEXT: s_and_b32 s8, s35, 0xff +; GFX9-NEXT: s_lshl_b32 s9, s56, 8 +; GFX9-NEXT: s_or_b32 s8, s8, s9 ; GFX9-NEXT: s_and_b32 s6, s6, 0xffff -; GFX9-NEXT: s_lshl_b32 s7, s7, 16 -; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: buffer_store_dword v30, v0, s[0:3], 0 offen offset:44 -; GFX9-NEXT: v_mov_b32_e32 v30, s6 -; GFX9-NEXT: s_and_b32 s6, s29, 0xff -; GFX9-NEXT: s_lshl_b32 s7, s75, 8 +; GFX9-NEXT: s_lshl_b32 s8, s8, 16 +; GFX9-NEXT: s_or_b32 s6, s6, s8 +; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:108 +; GFX9-NEXT: v_mov_b32_e32 v1, s6 +; GFX9-NEXT: s_and_b32 s6, s7, 0xff +; GFX9-NEXT: s_lshl_b32 s7, s31, 8 ; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: s_and_b32 s7, s77, 0xff -; GFX9-NEXT: s_lshl_b32 s8, s45, 8 +; GFX9-NEXT: v_readlane_b32 s7, v21, 6 +; GFX9-NEXT: s_and_b32 s7, s7, 0xff +; GFX9-NEXT: s_lshl_b32 s8, s95, 8 ; GFX9-NEXT: s_or_b32 s7, s7, s8 ; GFX9-NEXT: s_and_b32 s6, s6, 0xffff ; GFX9-NEXT: s_lshl_b32 s7, s7, 16 ; GFX9-NEXT: s_or_b32 s6, s6, s7 -; GFX9-NEXT: buffer_store_dword v30, v0, s[0:3], 0 offen offset:48 -; GFX9-NEXT: v_mov_b32_e32 v30, s6 +; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:112 +; GFX9-NEXT: v_mov_b32_e32 v1, s6 ; GFX9-NEXT: s_and_b32 s4, s4, 0xff -; GFX9-NEXT: s_lshl_b32 s6, s43, 8 +; GFX9-NEXT: s_lshl_b32 s6, s91, 8 ; GFX9-NEXT: s_or_b32 s4, s4, s6 -; GFX9-NEXT: s_and_b32 s6, s41, 0xff -; GFX9-NEXT: s_lshl_b32 s7, s34, 8 +; GFX9-NEXT: s_and_b32 s6, s77, 0xff +; GFX9-NEXT: s_lshl_b32 s7, s46, 8 ; GFX9-NEXT: s_or_b32 s6, s6, s7 ; GFX9-NEXT: s_and_b32 s4, s4, 0xffff ; GFX9-NEXT: s_lshl_b32 s6, s6, 16 ; GFX9-NEXT: s_or_b32 s4, s4, s6 -; GFX9-NEXT: buffer_store_dword v30, v0, s[0:3], 0 offen offset:52 -; GFX9-NEXT: v_mov_b32_e32 v30, s4 +; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:116 +; GFX9-NEXT: v_mov_b32_e32 v1, s4 ; GFX9-NEXT: s_and_b32 s4, s5, 0xff -; GFX9-NEXT: s_lshl_b32 s5, s10, 8 +; GFX9-NEXT: s_lshl_b32 s5, s73, 8 ; GFX9-NEXT: s_or_b32 s4, s4, s5 -; GFX9-NEXT: s_and_b32 s5, s78, 0xff -; GFX9-NEXT: s_lshl_b32 s6, s9, 8 +; GFX9-NEXT: v_readlane_b32 s5, v21, 7 +; GFX9-NEXT: s_and_b32 s5, s5, 0xff +; GFX9-NEXT: s_lshl_b32 s6, s59, 8 ; GFX9-NEXT: s_or_b32 s5, s5, s6 ; GFX9-NEXT: s_and_b32 s4, s4, 0xffff ; GFX9-NEXT: s_lshl_b32 s5, s5, 16 ; GFX9-NEXT: s_or_b32 s4, s4, s5 -; GFX9-NEXT: buffer_store_dword v30, v0, s[0:3], 0 offen offset:56 -; GFX9-NEXT: v_mov_b32_e32 v30, s4 -; GFX9-NEXT: buffer_store_dword v30, v0, s[0:3], 0 offen offset:60 -; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; GFX9-NEXT: v_lshlrev_b32_e32 v7, 8, v7 -; GFX9-NEXT: v_lshlrev_b32_e32 v11, 8, v11 -; GFX9-NEXT: v_or_b32_sdwa v11, v29, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5 -; GFX9-NEXT: v_or_b32_sdwa v5, v58, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b32_e32 v4, 8, v4 -; GFX9-NEXT: v_or_b32_sdwa v4, v56, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3 -; GFX9-NEXT: v_or_b32_sdwa v3, v46, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; GFX9-NEXT: v_or_b32_sdwa v2, v44, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; GFX9-NEXT: v_or_b32_sdwa v1, v26, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_readlane_b32 s99, v63, 35 -; GFX9-NEXT: v_readlane_b32 s98, v63, 34 -; GFX9-NEXT: v_readlane_b32 s97, v63, 33 -; GFX9-NEXT: v_readlane_b32 s96, v63, 32 -; GFX9-NEXT: v_readlane_b32 s87, v63, 31 -; GFX9-NEXT: v_readlane_b32 s86, v63, 30 -; GFX9-NEXT: v_readlane_b32 s85, v63, 29 -; GFX9-NEXT: v_readlane_b32 s84, v63, 28 -; GFX9-NEXT: v_readlane_b32 s83, v63, 27 -; GFX9-NEXT: v_readlane_b32 s82, v63, 26 -; GFX9-NEXT: v_readlane_b32 s81, v63, 25 -; GFX9-NEXT: v_readlane_b32 s80, v63, 24 -; GFX9-NEXT: v_readlane_b32 s71, v63, 23 -; GFX9-NEXT: v_readlane_b32 s70, v63, 22 -; GFX9-NEXT: v_readlane_b32 s69, v63, 21 -; GFX9-NEXT: v_readlane_b32 s68, v63, 20 -; GFX9-NEXT: v_readlane_b32 s67, v63, 19 -; GFX9-NEXT: v_readlane_b32 s66, v63, 18 -; GFX9-NEXT: v_readlane_b32 s65, v63, 17 -; GFX9-NEXT: v_readlane_b32 s64, v63, 16 -; GFX9-NEXT: v_readlane_b32 s55, v63, 15 -; GFX9-NEXT: v_readlane_b32 s54, v63, 14 -; GFX9-NEXT: v_readlane_b32 s53, v63, 13 -; GFX9-NEXT: v_readlane_b32 s52, v63, 12 -; GFX9-NEXT: v_readlane_b32 s51, v63, 11 -; GFX9-NEXT: v_readlane_b32 s50, v63, 10 -; GFX9-NEXT: v_readlane_b32 s49, v63, 9 -; GFX9-NEXT: v_readlane_b32 s48, v63, 8 -; GFX9-NEXT: v_readlane_b32 s39, v63, 7 -; GFX9-NEXT: v_readlane_b32 s38, v63, 6 -; GFX9-NEXT: v_readlane_b32 s37, v63, 5 -; GFX9-NEXT: v_readlane_b32 s36, v63, 4 -; GFX9-NEXT: v_readlane_b32 s35, v63, 3 -; GFX9-NEXT: v_readlane_b32 s34, v63, 2 -; GFX9-NEXT: v_readlane_b32 s31, v63, 1 -; GFX9-NEXT: v_readlane_b32 s30, v63, 0 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v7, v30, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v7, v7, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:64 -; GFX9-NEXT: v_lshlrev_b32_e32 v7, 8, v8 -; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload -; GFX9-NEXT: s_waitcnt vmcnt(1) -; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_lshlrev_b32_e32 v8, 8, v28 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v8, v11, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:68 -; GFX9-NEXT: v_lshlrev_b32_e32 v7, 8, v13 -; GFX9-NEXT: v_lshlrev_b32_e32 v8, 8, v10 -; GFX9-NEXT: v_or_b32_sdwa v7, v33, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v8, v27, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:72 -; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; GFX9-NEXT: v_lshlrev_b32_e32 v7, 8, v14 -; GFX9-NEXT: v_lshlrev_b32_e32 v8, 8, v61 -; GFX9-NEXT: v_or_b32_sdwa v7, v31, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_or_b32_sdwa v8, v10, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:76 -; GFX9-NEXT: v_lshlrev_b32_e32 v7, 8, v15 -; GFX9-NEXT: v_lshlrev_b32_e32 v8, 8, v9 -; GFX9-NEXT: v_or_b32_sdwa v7, v36, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v8, v60, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:80 -; GFX9-NEXT: v_lshlrev_b32_e32 v7, 8, v16 -; GFX9-NEXT: v_lshlrev_b32_e32 v8, 8, v59 -; GFX9-NEXT: v_or_b32_sdwa v7, v34, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v8, v32, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:84 -; GFX9-NEXT: v_lshlrev_b32_e32 v7, 8, v17 -; GFX9-NEXT: v_or_b32_sdwa v7, v39, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v5, v7, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:88 -; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v18 -; GFX9-NEXT: v_lshlrev_b32_e32 v7, 8, v57 -; GFX9-NEXT: v_or_b32_sdwa v5, v37, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v7, v35, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v5, v5, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:92 -; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v19 -; GFX9-NEXT: v_or_b32_sdwa v5, v50, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v4, v0, s[0:3], 0 offen offset:96 -; GFX9-NEXT: v_lshlrev_b32_e32 v4, 8, v20 -; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v47 -; GFX9-NEXT: v_or_b32_sdwa v4, v48, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v5, v38, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v4, v0, s[0:3], 0 offen offset:100 -; GFX9-NEXT: v_lshlrev_b32_e32 v4, 8, v21 -; GFX9-NEXT: v_or_b32_sdwa v4, v53, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:104 -; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v22 -; GFX9-NEXT: v_lshlrev_b32_e32 v4, 8, v45 -; GFX9-NEXT: v_or_b32_sdwa v3, v51, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v4, v49, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:108 -; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v23 -; GFX9-NEXT: v_or_b32_sdwa v3, v40, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:112 -; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v24 -; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v43 -; GFX9-NEXT: v_or_b32_sdwa v2, v54, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v3, v52, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:116 -; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v25 -; GFX9-NEXT: v_or_b32_sdwa v2, v42, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120 -; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v12 -; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v6 -; GFX9-NEXT: v_or_b32_sdwa v1, v41, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v2, v55, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: v_mov_b32_e32 v1, s4 ; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124 -; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload -; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 -; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; GFX9-NEXT: v_readlane_b32 s99, v20, 35 +; GFX9-NEXT: v_readlane_b32 s98, v20, 34 +; GFX9-NEXT: v_readlane_b32 s97, v20, 33 +; GFX9-NEXT: v_readlane_b32 s96, v20, 32 +; GFX9-NEXT: v_readlane_b32 s87, v20, 31 +; GFX9-NEXT: v_readlane_b32 s86, v20, 30 +; GFX9-NEXT: v_readlane_b32 s85, v20, 29 +; GFX9-NEXT: v_readlane_b32 s84, v20, 28 +; GFX9-NEXT: v_readlane_b32 s83, v20, 27 +; GFX9-NEXT: v_readlane_b32 s82, v20, 26 +; GFX9-NEXT: v_readlane_b32 s81, v20, 25 +; GFX9-NEXT: v_readlane_b32 s80, v20, 24 +; GFX9-NEXT: v_readlane_b32 s71, v20, 23 +; GFX9-NEXT: v_readlane_b32 s70, v20, 22 +; GFX9-NEXT: v_readlane_b32 s69, v20, 21 +; GFX9-NEXT: v_readlane_b32 s68, v20, 20 +; GFX9-NEXT: v_readlane_b32 s67, v20, 19 +; GFX9-NEXT: v_readlane_b32 s66, v20, 18 +; GFX9-NEXT: v_readlane_b32 s65, v20, 17 +; GFX9-NEXT: v_readlane_b32 s64, v20, 16 +; GFX9-NEXT: v_readlane_b32 s55, v20, 15 +; GFX9-NEXT: v_readlane_b32 s54, v20, 14 +; GFX9-NEXT: v_readlane_b32 s53, v20, 13 +; GFX9-NEXT: v_readlane_b32 s52, v20, 12 +; GFX9-NEXT: v_readlane_b32 s51, v20, 11 +; GFX9-NEXT: v_readlane_b32 s50, v20, 10 +; GFX9-NEXT: v_readlane_b32 s49, v20, 9 +; GFX9-NEXT: v_readlane_b32 s48, v20, 8 +; GFX9-NEXT: v_readlane_b32 s39, v20, 7 +; GFX9-NEXT: v_readlane_b32 s38, v20, 6 +; GFX9-NEXT: v_readlane_b32 s37, v20, 5 +; GFX9-NEXT: v_readlane_b32 s36, v20, 4 +; GFX9-NEXT: v_readlane_b32 s35, v20, 3 +; GFX9-NEXT: v_readlane_b32 s34, v20, 2 +; GFX9-NEXT: v_readlane_b32 s31, v20, 1 +; GFX9-NEXT: v_readlane_b32 s30, v20, 0 +; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1 +; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX9-NEXT: .LBB91_4: +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr67 +; GFX9-NEXT: ; implicit-def: $sgpr99 +; GFX9-NEXT: ; implicit-def: $sgpr97 +; GFX9-NEXT: ; implicit-def: $sgpr66 +; GFX9-NEXT: ; implicit-def: $sgpr85 +; GFX9-NEXT: ; implicit-def: $sgpr65 +; GFX9-NEXT: ; implicit-def: $sgpr82 +; GFX9-NEXT: ; implicit-def: $sgpr80 +; GFX9-NEXT: ; implicit-def: $sgpr71 +; GFX9-NEXT: ; implicit-def: $sgpr53 +; GFX9-NEXT: ; implicit-def: $sgpr51 +; GFX9-NEXT: ; implicit-def: $sgpr50 +; GFX9-NEXT: ; implicit-def: $sgpr48 +; GFX9-NEXT: ; implicit-def: $sgpr38 +; GFX9-NEXT: ; implicit-def: $sgpr68 +; GFX9-NEXT: ; implicit-def: $sgpr69 +; GFX9-NEXT: ; implicit-def: $sgpr98 +; GFX9-NEXT: ; implicit-def: $sgpr96 +; GFX9-NEXT: ; implicit-def: $sgpr87 +; GFX9-NEXT: ; implicit-def: $sgpr86 +; GFX9-NEXT: ; implicit-def: $sgpr84 +; GFX9-NEXT: ; implicit-def: $sgpr83 +; GFX9-NEXT: ; implicit-def: $sgpr81 +; GFX9-NEXT: ; implicit-def: $sgpr64 +; GFX9-NEXT: ; implicit-def: $sgpr70 +; GFX9-NEXT: ; implicit-def: $sgpr52 +; GFX9-NEXT: ; implicit-def: $sgpr55 +; GFX9-NEXT: ; implicit-def: $sgpr49 +; GFX9-NEXT: ; implicit-def: $sgpr39 +; GFX9-NEXT: ; implicit-def: $sgpr54 +; GFX9-NEXT: ; implicit-def: $sgpr63 +; GFX9-NEXT: ; implicit-def: $sgpr61 +; GFX9-NEXT: ; implicit-def: $sgpr37 +; GFX9-NEXT: ; implicit-def: $sgpr35 +; GFX9-NEXT: ; implicit-def: $sgpr31 +; GFX9-NEXT: ; implicit-def: $sgpr95 +; GFX9-NEXT: ; implicit-def: $sgpr91 +; GFX9-NEXT: ; implicit-def: $sgpr77 +; GFX9-NEXT: ; implicit-def: $sgpr73 +; GFX9-NEXT: ; implicit-def: $sgpr59 +; GFX9-NEXT: ; implicit-def: $sgpr36 +; GFX9-NEXT: ; implicit-def: $sgpr34 +; GFX9-NEXT: ; implicit-def: $sgpr30 +; GFX9-NEXT: ; implicit-def: $sgpr94 +; GFX9-NEXT: ; implicit-def: $sgpr90 +; GFX9-NEXT: ; implicit-def: $sgpr76 +; GFX9-NEXT: ; implicit-def: $sgpr72 +; GFX9-NEXT: ; implicit-def: $sgpr58 +; GFX9-NEXT: ; implicit-def: $sgpr88 +; GFX9-NEXT: ; implicit-def: $sgpr92 +; GFX9-NEXT: ; implicit-def: $sgpr78 +; GFX9-NEXT: ; implicit-def: $sgpr74 +; GFX9-NEXT: ; implicit-def: $sgpr62 +; GFX9-NEXT: ; implicit-def: $sgpr60 +; GFX9-NEXT: ; implicit-def: $sgpr56 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: s_branch .LBB91_2 ; -; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v128i8_scalar: -; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s4, -1 -; GFX11-TRUE16-NEXT: s_clause 0x3 ; 16-byte Folded Spill -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_store_b32 off, v43, s32 offset:12 -; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s4 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s96, 0 -; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v1 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v2 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 1 -; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s97, 1 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v3 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v4 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v5 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s34, 2 -; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s98, 2 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v6 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v7 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v8 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s35, 3 -; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s99, 3 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v9 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v10 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v11 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s36, 4 -; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s100, 4 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v12 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v13 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v14 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s37, 5 -; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s101, 5 -; GFX11-TRUE16-NEXT: s_mov_b32 vcc_hi, 0 -; GFX11-TRUE16-NEXT: s_and_b32 s4, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane -; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s38, 6 -; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s102, 6 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s39, 7 -; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s103, 7 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s48, 8 -; GFX11-TRUE16-NEXT: v_writelane_b32 v41, s104, 8 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s49, 9 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s50, 10 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s51, 11 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s52, 12 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s53, 13 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s54, 14 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s55, 15 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s64, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s65, 17 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s66, 18 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s67, 19 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s68, 20 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s69, 21 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s70, 22 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s71, 23 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s80, 24 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s81, 25 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s82, 26 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s83, 27 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s84, 28 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s85, 29 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s86, 30 -; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s87, 31 -; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB91_3 -; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s27, 24 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[12:13], s[26:27], 24 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 15 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s27, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s99, s2, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s100, s2, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s101, s1, 24 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 14 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s27, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s1, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s102, s1, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s103, s0, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s26, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s104, s0, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s85, s43, 24 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s43, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 17 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s26, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s43, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s87, s42, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s86, s42, 8 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 18 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s25, 24 -; GFX11-TRUE16-NEXT: s_lshr_b32 s81, s45, 24 -; GFX11-TRUE16-NEXT: s_lshr_b32 s98, s45, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s84, s45, 8 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 19 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s25, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s48, s44, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s70, s47, 24 -; GFX11-TRUE16-NEXT: s_lshr_b32 s97, s47, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 13 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s25, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s80, s47, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s83, s46, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s82, s46, 8 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 20 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s24, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s66, s59, 24 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s59, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s69, s59, 8 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 21 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s24, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s71, s58, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s39, s58, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s55, s61, 24 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 22 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s23, 24 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s61, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s65, s61, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s68, s60, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 23 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s23, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s67, s60, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s51, s63, 24 -; GFX11-TRUE16-NEXT: s_lshr_b32 s96, s63, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 12 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s23, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s54, s63, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s38, s62, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s64, s62, 8 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 24 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s22, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s36, s73, 24 -; GFX11-TRUE16-NEXT: s_lshr_b32 s7, s73, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s50, s73, 8 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 25 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s22, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s53, s72, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s52, s72, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s34, s29, 24 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 26 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s21, 24 -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s29, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s35, s29, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s37, s28, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 27 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s21, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s49, s28, 8 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[14:15], s[16:17], 24 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[40:41], s[2:3], 24 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 11 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s21, 8 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[56:57], s[0:1], 24 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[74:75], s[42:43], 24 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[76:77], s[44:45], 24 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 28 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s20, 16 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[78:79], s[46:47], 24 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[88:89], s[58:59], 24 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[90:91], s[60:61], 24 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 29 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s20, 8 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[92:93], s[62:63], 24 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[94:95], s[72:73], 24 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[30:31], s[28:29], 24 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 30 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s19, 24 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 31 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s19, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 10 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s19, 8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s4, 0 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s4, 1 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s18, 8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s4, 2 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s17, 24 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s4, 3 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s17, 16 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 9 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s17, 8 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s4, 4 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 16 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s4, 5 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s16, 8 -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s4, 6 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s3, 24 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s4, 7 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s3, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s3, 8 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1) -; GFX11-TRUE16-NEXT: v_writelane_b32 v42, s4, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s44, 16 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s12, 6 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s13, 7 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[12:13], s[24:25], 24 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s12, 4 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s13, 5 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[12:13], s[22:23], 24 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s12, 2 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s13, 3 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[12:13], s[20:21], 24 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s12, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s13, 1 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[12:13], s[18:19], 24 -; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, vcc_hi -; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB91_4 -; GFX11-TRUE16-NEXT: .LBB91_2: ; %cmp.true -; GFX11-TRUE16-NEXT: s_and_b32 s5, s29, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s29, 16 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s5 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: s_and_b32 s4, s28, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s28, 16 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v2, 16, 1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v2 -; GFX11-TRUE16-NEXT: s_and_b32 s4, s1, 0xffff0000 -; GFX11-TRUE16-NEXT: s_and_b32 s15, s45, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s28, s45, 16 -; GFX11-TRUE16-NEXT: s_and_b32 s8, s43, 0xffff0000 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1 -; GFX11-TRUE16-NEXT: s_lshl_b32 s7, s43, 16 -; GFX11-TRUE16-NEXT: s_and_b32 s6, s73, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s73, 16 -; GFX11-TRUE16-NEXT: s_and_b32 s76, s72, 0xffff0000 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3 -; GFX11-TRUE16-NEXT: s_lshl_b32 s75, s72, 16 -; GFX11-TRUE16-NEXT: s_and_b32 s11, s63, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s74, s63, 16 -; GFX11-TRUE16-NEXT: s_and_b32 s73, s62, 0xffff0000 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: s_lshl_b32 s72, s62, 16 -; GFX11-TRUE16-NEXT: s_and_b32 s62, s61, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s63, s61, 16 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v1 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc_lo -; GFX11-TRUE16-NEXT: s_and_b32 s61, s60, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s57, s60, 16 -; GFX11-TRUE16-NEXT: s_and_b32 s40, s59, 0xffff0000 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_lshl_b32 s56, s59, 16 -; GFX11-TRUE16-NEXT: s_and_b32 s29, s58, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s14, s58, 16 -; GFX11-TRUE16-NEXT: s_bfe_u32 s4, s45, 0x10010 -; GFX11-TRUE16-NEXT: s_and_b32 s12, s47, 0xffff0000 -; GFX11-TRUE16-NEXT: s_add_i32 s43, s4, s45 -; GFX11-TRUE16-NEXT: s_lshl_b32 s13, s47, 16 -; GFX11-TRUE16-NEXT: s_and_b32 s47, s46, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s41, s46, 16 -; GFX11-TRUE16-NEXT: s_and_b32 s10, s44, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s9, s44, 16 -; GFX11-TRUE16-NEXT: s_and_b32 s5, s42, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s42, 16 -; GFX11-TRUE16-NEXT: s_addk_i32 s43, 0x7fff -; GFX11-TRUE16-NEXT: s_bitset1_b32 s45, 22 -; GFX11-TRUE16-NEXT: s_and_b32 s42, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s42, s45, s43 -; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s1 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s78 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v2 -; GFX11-TRUE16-NEXT: s_lshr_b32 s58, s42, 16 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v3, v6 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s1, v4 -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1 -; GFX11-TRUE16-NEXT: s_bfe_u32 s43, s1, 0x10010 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v24.l -; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, s1 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s1, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s43, 0x7fff -; GFX11-TRUE16-NEXT: s_and_b32 s42, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1 -; GFX11-TRUE16-NEXT: s_cselect_b32 s1, s1, s43 -; GFX11-TRUE16-NEXT: s_and_b32 s42, s0, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 16 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s42 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s77 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v25.l -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v4 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v6, 16, 1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 24, v5 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s6 -; GFX11-TRUE16-NEXT: s_bfe_u32 s6, s42, 0x10010 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, s42 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s42, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s6, 0x7fff -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v1 -; GFX11-TRUE16-NEXT: s_and_b32 s43, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s6, s42, s6 -; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v6 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v2.l -; GFX11-TRUE16-NEXT: s_lshr_b32 s6, s6, 16 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v8, v3 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v6 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v2 -; GFX11-TRUE16-NEXT: s_bfe_u32 s42, s0, 0x10010 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3 -; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, s0 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s0, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s42, 0x7fff -; GFX11-TRUE16-NEXT: s_and_b32 s43, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s0, s0, s42 -; GFX11-TRUE16-NEXT: s_and_b32 s42, s3, 0xffff0000 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s42 -; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 16 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v27.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc_lo -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v2 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s76 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v4 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v6 -; GFX11-TRUE16-NEXT: s_bfe_u32 s43, s42, 0x10010 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, s42 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s42, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s43, 0x7fff -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v7, 16, 1 -; GFX11-TRUE16-NEXT: s_and_b32 s44, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s42, s42, s43 -; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s75 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s3 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v7 -; GFX11-TRUE16-NEXT: s_lshr_b32 s59, s42, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v7 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2 -; GFX11-TRUE16-NEXT: s_bfe_u32 s43, s3, 0x10010 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2 -; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, s3 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s3, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s43, 0x7fff -; GFX11-TRUE16-NEXT: s_and_b32 s42, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s3, s3, s43 -; GFX11-TRUE16-NEXT: s_and_b32 s42, s2, 0xffff0000 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s42 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3 -; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s3, 16 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s74 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v26.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v7, 16, 1 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v28.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v9, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s11 -; GFX11-TRUE16-NEXT: s_bfe_u32 s11, s42, 0x10010 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: s_add_i32 s11, s11, s42 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s42, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s11, 0x7fff -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v2 -; GFX11-TRUE16-NEXT: s_and_b32 s43, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s11, s42, s11 -; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s2 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v7 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s11, 16 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v1.l -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v6, v3 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v2 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v8 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v7 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_bfe_u32 s42, s2, 0x10010 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3 -; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, s2 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s2, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s42, 0x7fff -; GFX11-TRUE16-NEXT: s_and_b32 s43, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s2, s2, s42 -; GFX11-TRUE16-NEXT: s_and_b32 s42, s17, 0xffff0000 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s42 -; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, 16 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s73 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v30.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v2 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v7, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v7 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v6 -; GFX11-TRUE16-NEXT: s_bfe_u32 s43, s42, 0x10010 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, s42 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s42, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s43, 0x7fff -; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s72 -; GFX11-TRUE16-NEXT: s_and_b32 s44, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s42, s42, s43 -; GFX11-TRUE16-NEXT: s_lshl_b32 s17, s17, 16 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v1 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s17 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v7 -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX11-TRUE16-NEXT: s_lshr_b32 s60, s42, 16 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s17, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v29.l -; GFX11-TRUE16-NEXT: s_bfe_u32 s43, s17, 0x10010 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v31.l -; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, s17 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s17, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s43, 0x7fff -; GFX11-TRUE16-NEXT: s_and_b32 s42, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s17, s17, s43 -; GFX11-TRUE16-NEXT: s_and_b32 s42, s16, 0xffff0000 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s42 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s63 -; GFX11-TRUE16-NEXT: s_lshr_b32 s17, s17, 16 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v7, 16, 1 -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[13:14], 24, v[11:12] -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[4:5] -; GFX11-TRUE16-NEXT: s_bfe_u32 s43, s42, 0x10010 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v9, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, s42 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s42, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s43, 0x7fff -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v2 -; GFX11-TRUE16-NEXT: s_and_b32 s44, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s42, s42, s43 -; GFX11-TRUE16-NEXT: s_lshl_b32 s16, s16, 16 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s62 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s16 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v7 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s42, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s16, v2 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v1.l -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v6, v3 -; GFX11-TRUE16-NEXT: s_bfe_u32 s43, s16, 0x10010 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v8 -; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, s16 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s16, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s43, 0x7fff -; GFX11-TRUE16-NEXT: s_and_b32 s42, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s16, s16, s43 -; GFX11-TRUE16-NEXT: s_and_b32 s42, s19, 0xffff0000 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v7 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s42 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: s_lshr_b32 s16, s16, 16 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s61 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v33.l -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v7, 16, 1 -; GFX11-TRUE16-NEXT: s_bfe_u32 s43, s42, 0x10010 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, s42 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s42, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s43, 0x7fff -; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s57 -; GFX11-TRUE16-NEXT: s_and_b32 s45, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s42, s42, s43 -; GFX11-TRUE16-NEXT: s_lshl_b32 s19, s19, 16 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v1 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s19 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v7 -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX11-TRUE16-NEXT: s_lshr_b32 s61, s42, 16 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v7 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s19, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2 -; GFX11-TRUE16-NEXT: s_bfe_u32 s43, s19, 0x10010 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v32.l -; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, s19 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s19, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s43, 0x7fff -; GFX11-TRUE16-NEXT: s_and_b32 s42, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s19, s19, s43 -; GFX11-TRUE16-NEXT: s_and_b32 s42, s18, 0xffff0000 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s42 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s56 -; GFX11-TRUE16-NEXT: s_lshr_b32 s19, s19, 16 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v7, 16, 1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v34.l -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s45, s17, s60 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s44, s16, s44 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v9, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s40 -; GFX11-TRUE16-NEXT: s_bfe_u32 s40, s42, 0x10010 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, s42 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s42, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s40, 0x7fff -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v2 -; GFX11-TRUE16-NEXT: s_and_b32 s43, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s40, s42, s40 -; GFX11-TRUE16-NEXT: s_lshl_b32 s18, s18, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s18 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v7 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX11-TRUE16-NEXT: s_lshr_b32 s40, s40, 16 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s18, v2 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v1.l -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v6, v3 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v8 -; GFX11-TRUE16-NEXT: s_bfe_u32 s42, s18, 0x10010 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v7 -; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, s18 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s18, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s42, 0x7fff -; GFX11-TRUE16-NEXT: s_and_b32 s43, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s18, s18, s42 -; GFX11-TRUE16-NEXT: s_and_b32 s42, s21, 0xffff0000 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s42 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s29 -; GFX11-TRUE16-NEXT: s_lshr_b32 s18, s18, 16 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s29, v2 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v7, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v7 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v6 -; GFX11-TRUE16-NEXT: s_bfe_u32 s42, s29, 0x10010 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, s29 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s29, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s42, 0x7fff -; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s14 -; GFX11-TRUE16-NEXT: s_and_b32 s43, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s29, s29, s42 -; GFX11-TRUE16-NEXT: s_lshl_b32 s21, s21, 16 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v1 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s21 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v7 -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX11-TRUE16-NEXT: s_lshr_b32 s62, s29, 16 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s42, s2, s11 -; GFX11-TRUE16-NEXT: s_bfe_u32 s21, s14, 0x10010 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v35.l -; GFX11-TRUE16-NEXT: s_add_i32 s21, s21, s14 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s14, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s21, 0x7fff -; GFX11-TRUE16-NEXT: s_and_b32 s29, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s14, s14, s21 -; GFX11-TRUE16-NEXT: s_and_b32 s21, s20, 0xffff0000 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s21 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s13 -; GFX11-TRUE16-NEXT: s_lshr_b32 s21, s14, 16 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v7, 16, 1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v37.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v36.l -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s43, s3, s59 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v9, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s12 -; GFX11-TRUE16-NEXT: s_bfe_u32 s12, s13, 0x10010 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, s13 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s13, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s12, 0x7fff -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v2 -; GFX11-TRUE16-NEXT: s_and_b32 s14, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s12, s13, s12 -; GFX11-TRUE16-NEXT: s_lshl_b32 s13, s20, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v3, 16, 1 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s13 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v7 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX11-TRUE16-NEXT: s_lshr_b32 s12, s12, 16 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v2 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v1.l -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v6, v3 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v8 -; GFX11-TRUE16-NEXT: s_bfe_u32 s14, s13, 0x10010 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v7 -; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, s13 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s13, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s14, 0x7fff -; GFX11-TRUE16-NEXT: s_and_b32 s20, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s13, s13, s14 -; GFX11-TRUE16-NEXT: s_and_b32 s14, s23, 0xffff0000 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s14 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s47 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v39.l -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v2 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v7, 16, 1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v7 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v6 -; GFX11-TRUE16-NEXT: s_bfe_u32 s20, s14, 0x10010 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: s_add_i32 s29, s20, s14 -; GFX11-TRUE16-NEXT: s_lshr_b32 s20, s13, 16 -; GFX11-TRUE16-NEXT: s_addk_i32 s29, 0x7fff -; GFX11-TRUE16-NEXT: s_bitset1_b32 s14, 22 -; GFX11-TRUE16-NEXT: s_and_b32 s13, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s13, s14, s29 -; GFX11-TRUE16-NEXT: s_lshl_b32 s14, s23, 16 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s41 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s14 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v7 -; GFX11-TRUE16-NEXT: s_lshr_b32 s63, s13, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s28 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2 -; GFX11-TRUE16-NEXT: s_bfe_u32 s23, s14, 0x10010 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s28, s0, s6 -; GFX11-TRUE16-NEXT: s_add_i32 s23, s23, s14 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s14, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s23, 0x7fff -; GFX11-TRUE16-NEXT: s_and_b32 s13, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s13, s14, s23 -; GFX11-TRUE16-NEXT: s_and_b32 s14, s22, 0xffff0000 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s14 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2 -; GFX11-TRUE16-NEXT: s_lshr_b32 s23, s13, 16 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v6 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s15 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v38.l -; GFX11-TRUE16-NEXT: s_bfe_u32 s15, s14, 0x10010 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, s14 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s14, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s15, 0x7fff -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v2 -; GFX11-TRUE16-NEXT: s_and_b32 s13, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s13, s14, s15 -; GFX11-TRUE16-NEXT: s_lshl_b32 s14, s22, 16 -; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v8, 16, 1 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s14 -; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v9, 16, 1 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s13, 16 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v48.l -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v8 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v2 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v7, v9 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v8 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3 -; GFX11-TRUE16-NEXT: s_bfe_u32 s15, s14, 0x10010 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, s14 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s14, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s15, 0x7fff -; GFX11-TRUE16-NEXT: s_and_b32 s22, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-TRUE16-NEXT: s_cselect_b32 s14, s14, s15 -; GFX11-TRUE16-NEXT: s_and_b32 s15, s25, 0xffff0000 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6 -; GFX11-TRUE16-NEXT: s_lshr_b32 s22, s14, 16 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v7, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s15 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s10 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s8 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v2 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v3 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo -; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s9 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v1.l -; GFX11-TRUE16-NEXT: s_bfe_u32 s9, s10, 0x10010 -; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v7, 16, 1 -; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, s10 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s10, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s9, 0x7fff -; GFX11-TRUE16-NEXT: s_and_b32 s14, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s9, s10, s9 -; GFX11-TRUE16-NEXT: s_lshl_b32 s10, s25, 16 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v6 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s10 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v7 -; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1 -; GFX11-TRUE16-NEXT: s_lshr_b32 s72, s9, 16 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v7 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v3 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v2 -; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1 -; GFX11-TRUE16-NEXT: s_bfe_u32 s10, s8, 0x10010 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v51.l -; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, s8 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s8, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s10, 0x7fff -; GFX11-TRUE16-NEXT: s_and_b32 s9, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s8, s8, s10 -; GFX11-TRUE16-NEXT: s_and_b32 s9, s24, 0xffff0000 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s9 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2 -; GFX11-TRUE16-NEXT: s_lshr_b32 s25, s8, 16 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v10, v8 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v3 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v50.l -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.h, v49.l -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s29, s1, s58 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v7, vcc_lo -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v9 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s7 -; GFX11-TRUE16-NEXT: s_bfe_u32 s7, s9, 0x10010 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-TRUE16-NEXT: s_add_i32 s7, s7, s9 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s9, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s7, 0x7fff -; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v8 -; GFX11-TRUE16-NEXT: s_and_b32 s8, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s7, s9, s7 -; GFX11-TRUE16-NEXT: s_lshl_b32 s8, s24, 16 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v2 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s8 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s7, 16 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.h, v1.l -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v53.l -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s5 -; GFX11-TRUE16-NEXT: s_bfe_u32 s5, s8, 0x10010 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v6, v9 -; GFX11-TRUE16-NEXT: s_add_i32 s5, s5, s8 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s8, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s5, 0x7fff -; GFX11-TRUE16-NEXT: s_and_b32 s7, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s5, s8, s5 -; GFX11-TRUE16-NEXT: s_and_b32 s7, s27, 0xffff0000 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s7 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1 -; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v2, 16, 1 -; GFX11-TRUE16-NEXT: s_lshr_b32 s24, s5, 16 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v6 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v8, v3 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v10, v2 -; GFX11-TRUE16-NEXT: s_bfe_u32 s7, s4, 0x10010 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v1 -; GFX11-TRUE16-NEXT: s_add_i32 s7, s7, s4 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s4, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s7, 0x7fff -; GFX11-TRUE16-NEXT: s_and_b32 s5, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s4, s4, s7 -; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s27, 16 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v7 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s5 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v1 -; GFX11-TRUE16-NEXT: s_lshr_b32 s73, s4, 16 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v54.l -; GFX11-TRUE16-NEXT: s_bfe_u32 s7, s5, 0x10010 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.h, v52.l -; GFX11-TRUE16-NEXT: s_add_i32 s7, s7, s5 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v8, v9, vcc_lo -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: s_addk_i32 s7, 0x7fff -; GFX11-TRUE16-NEXT: s_bitset1_b32 s5, 22 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s8, s22, s13 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v2 -; GFX11-TRUE16-NEXT: s_and_b32 s4, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s4, s5, s7 -; GFX11-TRUE16-NEXT: s_and_b32 s5, s26, 0xffff0000 -; GFX11-TRUE16-NEXT: s_lshr_b32 s27, s4, 16 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s5 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v55.l -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[6:7], 24, v[22:23] -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[7:8], 24, v[20:21] -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.h, v2.l -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[18:19] -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[9:10], 24, v[16:17] -; GFX11-TRUE16-NEXT: s_bfe_u32 s6, s5, 0x10010 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s9, s23, s63 -; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, s5 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s5, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s6, 0x7fff -; GFX11-TRUE16-NEXT: s_and_b32 s4, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s14, s5, s6 -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s26, 16 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s6, s20, s12 -; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s14, 16 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s5, s19, s61 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s4, s18, s40 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 8, v65 -; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v1 -; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[1:2], 24, v[64:65] -; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[2:3], 24, v[68:69] -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v65 -; GFX11-TRUE16-NEXT: s_bfe_u32 s12, s11, 0x10010 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v64 -; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, s11 -; GFX11-TRUE16-NEXT: s_bitset1_b32 s11, 22 -; GFX11-TRUE16-NEXT: s_addk_i32 s12, 0x7fff -; GFX11-TRUE16-NEXT: s_and_b32 s14, vcc_lo, exec_lo -; GFX11-TRUE16-NEXT: s_cselect_b32 s12, s11, s12 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v64 -; GFX11-TRUE16-NEXT: s_lshr_b32 s26, s12, 16 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 24, v69 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 8, v69 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v68 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 8, v68 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 24, v23 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 8, v23 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v22 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 8, v22 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 24, v21 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 8, v21 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v20 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 8, v20 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 24, v19 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v19 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v18 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 8, v18 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 24, v17 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 8, v17 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v16 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 8, v16 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v12 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 8, v12 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v11 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 8, v11 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5 -; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 8, v4 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s7, s21, s62 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s11, s25, s72 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s47, s27, s73 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s46, s26, s13 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s10, s24, s10 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[94:95], s[8:9], 24 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[12:13], s[4:5], 24 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[14:15], s[44:45], 24 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[40:41], s[42:43], 24 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[56:57], s[28:29], 24 -; GFX11-TRUE16-NEXT: s_lshr_b64 vcc, s[46:47], 24 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[34:35], s[10:11], 24 -; GFX11-TRUE16-NEXT: s_lshr_b64 s[30:31], s[6:7], 24 -; GFX11-TRUE16-NEXT: s_lshr_b32 s13, s47, 24 -; GFX11-TRUE16-NEXT: s_lshr_b32 s15, s47, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s41, s46, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s46, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s47, s11, 24 -; GFX11-TRUE16-NEXT: s_lshr_b32 s11, s11, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s57, s10, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s10, s10, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s74, s9, 24 -; GFX11-TRUE16-NEXT: s_lshr_b32 s9, s9, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s75, s8, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s8, s8, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s76, s7, 24 -; GFX11-TRUE16-NEXT: s_lshr_b32 s77, s7, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s78, s6, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s79, s6, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s88, s5, 24 -; GFX11-TRUE16-NEXT: s_lshr_b32 s89, s5, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s90, s4, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s91, s4, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s92, s45, 24 -; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s45, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s93, s44, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s44, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s95, s43, 24 -; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s43, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s99, s42, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s100, s42, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s101, s29, 24 -; GFX11-TRUE16-NEXT: s_lshr_b32 s102, s29, 8 -; GFX11-TRUE16-NEXT: s_lshr_b32 s103, s28, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s104, s28, 8 -; GFX11-TRUE16-NEXT: s_branch .LBB91_5 -; GFX11-TRUE16-NEXT: .LBB91_3: -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr74 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr104 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr103 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr56 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr102 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr11 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr101 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr100 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr99 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr40 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr14 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr12 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr49 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr37 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr35 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr6 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr34 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr52 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr53 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr50 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr7 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr36 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr64 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr38 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr54 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr96 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr51 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr67 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr68 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr65 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr8 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr55 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr39 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr71 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr69 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr9 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr66 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr82 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr83 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr80 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr97 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr70 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr48 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr84 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr98 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr81 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr86 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr87 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr10 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr85 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr30 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr94 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr92 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr90 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr88 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr78 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr76 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 0 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s5, 1 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s4, 2 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s5, 3 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s74, 4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s75, 5 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr74 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; kill: killed $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr5 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s74, 6 -; GFX11-TRUE16-NEXT: v_writelane_b32 v43, s75, 7 -; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr74 -; GFX11-TRUE16-NEXT: s_branch .LBB91_2 -; GFX11-TRUE16-NEXT: .LBB91_4: -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v13, s94 :: v_dual_mov_b32 v14, s30 -; GFX11-TRUE16-NEXT: v_readlane_b32 s94, v43, 2 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v96, s37 :: v_dual_mov_b32 v87, s34 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s49 :: v_dual_mov_b32 v5, s35 -; GFX11-TRUE16-NEXT: v_readlane_b32 s95, v43, 3 -; GFX11-TRUE16-NEXT: v_readlane_b32 vcc_lo, v43, 6 -; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v43, 0 -; GFX11-TRUE16-NEXT: v_readlane_b32 s34, v43, 4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v55, s42 :: v_dual_mov_b32 v54, s43 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v52, s10 :: v_dual_mov_b32 v53, s44 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v50, s45 :: v_dual_mov_b32 v49, s98 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v51, s46 :: v_dual_mov_b32 v38, s47 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v48, s97 :: v_dual_mov_b32 v39, s58 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v35, s59 :: v_dual_mov_b32 v36, s60 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v37, s9 :: v_dual_mov_b32 v32, s61 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v34, s8 :: v_dual_mov_b32 v33, s62 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, s63 :: v_dual_mov_b32 v30, s72 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, s96 :: v_dual_mov_b32 v26, s73 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, s7 :: v_dual_mov_b32 v27, s28 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v24, s29 :: v_dual_mov_b32 v25, s6 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, s87 :: v_dual_mov_b32 v64, s86 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, s85 :: v_dual_mov_b32 v10, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v67, s4 :: v_dual_mov_b32 v68, s48 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v65, s81 :: v_dual_mov_b32 v66, s84 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v70, s83 :: v_dual_mov_b32 v69, s70 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, s82 :: v_dual_mov_b32 v23, s80 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v80, s71 :: v_dual_mov_b32 v71, s66 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s39 :: v_dual_mov_b32 v21, s69 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v82, s68 :: v_dual_mov_b32 v81, s55 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, s67 :: v_dual_mov_b32 v19, s65 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v84, s38 :: v_dual_mov_b32 v83, s51 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s64 :: v_dual_mov_b32 v17, s54 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v86, s53 :: v_dual_mov_b32 v11, s52 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v85, s36 :: v_dual_mov_b32 v12, s50 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, s74 :: v_dual_mov_b32 v2, s76 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s78 :: v_dual_mov_b32 v7, s88 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s90 :: v_dual_mov_b32 v9, s92 -; GFX11-TRUE16-NEXT: s_mov_b32 s58, s11 -; GFX11-TRUE16-NEXT: v_readlane_b32 s59, v43, 8 -; GFX11-TRUE16-NEXT: v_readlane_b32 s60, v43, 9 -; GFX11-TRUE16-NEXT: v_readlane_b32 s61, v43, 10 -; GFX11-TRUE16-NEXT: v_readlane_b32 s62, v43, 11 -; GFX11-TRUE16-NEXT: v_readlane_b32 s63, v43, 12 -; GFX11-TRUE16-NEXT: v_readlane_b32 s72, v43, 13 -; GFX11-TRUE16-NEXT: v_readlane_b32 s73, v43, 14 -; GFX11-TRUE16-NEXT: v_readlane_b32 s13, v43, 15 -; GFX11-TRUE16-NEXT: v_readlane_b32 s15, v43, 16 -; GFX11-TRUE16-NEXT: v_readlane_b32 s41, v43, 17 -; GFX11-TRUE16-NEXT: v_readlane_b32 s46, v43, 18 -; GFX11-TRUE16-NEXT: v_readlane_b32 s47, v43, 19 -; GFX11-TRUE16-NEXT: v_readlane_b32 s11, v43, 20 -; GFX11-TRUE16-NEXT: v_readlane_b32 s57, v43, 21 -; GFX11-TRUE16-NEXT: v_readlane_b32 s10, v43, 22 -; GFX11-TRUE16-NEXT: v_readlane_b32 s74, v43, 23 -; GFX11-TRUE16-NEXT: v_readlane_b32 s9, v43, 24 -; GFX11-TRUE16-NEXT: v_readlane_b32 s75, v43, 25 -; GFX11-TRUE16-NEXT: v_readlane_b32 s8, v43, 26 -; GFX11-TRUE16-NEXT: v_readlane_b32 s76, v43, 27 -; GFX11-TRUE16-NEXT: v_readlane_b32 s77, v43, 28 -; GFX11-TRUE16-NEXT: v_readlane_b32 s78, v43, 29 -; GFX11-TRUE16-NEXT: v_readlane_b32 s79, v43, 30 -; GFX11-TRUE16-NEXT: v_readlane_b32 s88, v43, 31 -; GFX11-TRUE16-NEXT: v_readlane_b32 s89, v42, 0 -; GFX11-TRUE16-NEXT: v_readlane_b32 s90, v42, 1 -; GFX11-TRUE16-NEXT: v_readlane_b32 s91, v42, 2 -; GFX11-TRUE16-NEXT: v_readlane_b32 s92, v42, 3 -; GFX11-TRUE16-NEXT: v_readlane_b32 s45, v42, 4 -; GFX11-TRUE16-NEXT: v_readlane_b32 s93, v42, 5 -; GFX11-TRUE16-NEXT: v_readlane_b32 vcc_hi, v43, 7 -; GFX11-TRUE16-NEXT: v_readlane_b32 s44, v42, 6 -; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v43, 1 -; GFX11-TRUE16-NEXT: v_readlane_b32 s95, v42, 7 -; GFX11-TRUE16-NEXT: v_readlane_b32 s43, v42, 8 -; GFX11-TRUE16-NEXT: v_readlane_b32 s35, v43, 5 -; GFX11-TRUE16-NEXT: .LBB91_5: ; %end -; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s104, 8 -; GFX11-TRUE16-NEXT: s_and_b32 s5, s103, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s6, s56, 8 -; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s4 -; GFX11-TRUE16-NEXT: s_or_b32 s4, s5, s6 -; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s102, 8 -; GFX11-TRUE16-NEXT: s_and_b32 s6, s58, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s7, s101, 8 -; GFX11-TRUE16-NEXT: s_or_b32 s1, s1, s5 -; GFX11-TRUE16-NEXT: s_or_b32 s5, s6, s7 -; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s4, 16 -; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 0xffff -; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s5, 16 -; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s4 -; GFX11-TRUE16-NEXT: s_or_b32 s1, s1, s5 -; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s100, 8 -; GFX11-TRUE16-NEXT: s_and_b32 s5, s99, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s6, s40, 8 -; GFX11-TRUE16-NEXT: s_or_b32 s2, s2, s4 -; GFX11-TRUE16-NEXT: s_or_b32 s4, s5, s6 -; GFX11-TRUE16-NEXT: s_and_b32 s3, s3, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s43, 8 -; GFX11-TRUE16-NEXT: s_and_b32 s6, s59, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s7, s95, 8 -; GFX11-TRUE16-NEXT: s_or_b32 s3, s3, s5 -; GFX11-TRUE16-NEXT: s_or_b32 s5, s6, s7 -; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s4, 16 -; GFX11-TRUE16-NEXT: s_and_b32 s3, s3, 0xffff -; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s5, 16 -; GFX11-TRUE16-NEXT: s_or_b32 s2, s2, s4 -; GFX11-TRUE16-NEXT: s_or_b32 s3, s3, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v97, s0 :: v_dual_mov_b32 v98, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v99, s2 :: v_dual_mov_b32 v100, s3 -; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s44, 8 -; GFX11-TRUE16-NEXT: s_and_b32 s2, s93, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s14, 8 -; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s1 -; GFX11-TRUE16-NEXT: s_or_b32 s1, s2, s3 -; GFX11-TRUE16-NEXT: s_and_b32 s2, s17, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s45, 8 -; GFX11-TRUE16-NEXT: s_and_b32 s4, s60, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s92, 8 -; GFX11-TRUE16-NEXT: s_or_b32 s2, s2, s3 -; GFX11-TRUE16-NEXT: s_or_b32 s3, s4, s5 -; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s1 -; GFX11-TRUE16-NEXT: s_or_b32 s1, s2, s3 -; GFX11-TRUE16-NEXT: s_and_b32 s2, s18, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s91, 8 -; GFX11-TRUE16-NEXT: s_and_b32 s4, s90, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s12, 8 -; GFX11-TRUE16-NEXT: s_or_b32 s2, s2, s3 -; GFX11-TRUE16-NEXT: s_or_b32 s3, s4, s5 -; GFX11-TRUE16-NEXT: s_and_b32 s4, s19, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s89, 8 -; GFX11-TRUE16-NEXT: s_and_b32 s6, s61, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s7, s88, 8 -; GFX11-TRUE16-NEXT: s_or_b32 s4, s4, s5 -; GFX11-TRUE16-NEXT: s_or_b32 s5, s6, s7 -; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-TRUE16-NEXT: s_and_b32 s4, s4, 0xffff -; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s5, 16 -; GFX11-TRUE16-NEXT: s_or_b32 s2, s2, s3 -; GFX11-TRUE16-NEXT: s_or_b32 s3, s4, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v112, s0 :: v_dual_mov_b32 v113, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v114, s2 :: v_dual_mov_b32 v115, s3 -; GFX11-TRUE16-NEXT: s_and_b32 s0, s20, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s79, 8 -; GFX11-TRUE16-NEXT: s_and_b32 s2, s78, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s30, 8 -; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s1 -; GFX11-TRUE16-NEXT: s_or_b32 s1, s2, s3 -; GFX11-TRUE16-NEXT: s_and_b32 s2, s21, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s77, 8 -; GFX11-TRUE16-NEXT: s_and_b32 s4, s62, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s76, 8 -; GFX11-TRUE16-NEXT: s_or_b32 s2, s2, s3 -; GFX11-TRUE16-NEXT: s_or_b32 s3, s4, s5 -; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s1 -; GFX11-TRUE16-NEXT: s_or_b32 s1, s2, s3 -; GFX11-TRUE16-NEXT: s_and_b32 s2, s22, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s8, 8 -; GFX11-TRUE16-NEXT: s_and_b32 s4, s75, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s94, 8 -; GFX11-TRUE16-NEXT: s_or_b32 s2, s2, s3 -; GFX11-TRUE16-NEXT: s_or_b32 s3, s4, s5 -; GFX11-TRUE16-NEXT: s_and_b32 s4, s23, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s9, 8 -; GFX11-TRUE16-NEXT: s_and_b32 s6, s63, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s7, s74, 8 -; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-TRUE16-NEXT: s_or_b32 s4, s4, s5 -; GFX11-TRUE16-NEXT: s_or_b32 s5, s6, s7 -; GFX11-TRUE16-NEXT: s_and_b32 s4, s4, 0xffff -; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s5, 16 -; GFX11-TRUE16-NEXT: s_or_b32 s2, s2, s3 -; GFX11-TRUE16-NEXT: s_clause 0x1 -; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[97:100], off -; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[112:115], off offset:16 -; GFX11-TRUE16-NEXT: s_or_b32 s3, s4, s5 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v97, s0 :: v_dual_mov_b32 v98, s1 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v99, s2 :: v_dual_mov_b32 v100, s3 -; GFX11-TRUE16-NEXT: s_and_b32 s0, s24, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s10, 8 -; GFX11-TRUE16-NEXT: s_and_b32 s2, s57, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s34, 8 -; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s1 -; GFX11-TRUE16-NEXT: s_or_b32 s1, s2, s4 -; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s11, 8 -; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s1 -; GFX11-TRUE16-NEXT: s_and_b32 s1, s25, 0xff -; GFX11-TRUE16-NEXT: s_and_b32 s3, s72, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s47, 8 -; GFX11-TRUE16-NEXT: s_or_b32 s1, s1, s2 -; GFX11-TRUE16-NEXT: s_or_b32 s2, s3, s4 -; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 0xffff -; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 16 -; GFX11-TRUE16-NEXT: s_and_b32 s3, s26, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s46, 8 -; GFX11-TRUE16-NEXT: s_or_b32 s1, s1, s2 -; GFX11-TRUE16-NEXT: s_or_b32 s2, s3, s4 -; GFX11-TRUE16-NEXT: s_and_b32 s3, s41, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s4, vcc_lo, 8 -; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s15, 8 -; GFX11-TRUE16-NEXT: s_or_b32 s3, s3, s4 -; GFX11-TRUE16-NEXT: s_and_b32 s4, s27, 0xff -; GFX11-TRUE16-NEXT: s_lshl_b32 s6, s13, 8 -; GFX11-TRUE16-NEXT: s_or_b32 s4, s4, s5 -; GFX11-TRUE16-NEXT: s_and_b32 s5, s73, 0xff -; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-TRUE16-NEXT: s_or_b32 s5, s5, s6 -; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-TRUE16-NEXT: s_and_b32 s4, s4, 0xffff -; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s5, 16 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v112, s0 :: v_dual_and_b32 v27, 0xff, v27 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v113, s1 :: v_dual_lshlrev_b32 v4, 8, v4 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 8, v14 -; GFX11-TRUE16-NEXT: s_or_b32 s2, s2, s3 -; GFX11-TRUE16-NEXT: s_or_b32 s3, s4, s5 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v115, s3 :: v_dual_and_b32 v96, 0xff, v96 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v27, v4 -; GFX11-TRUE16-NEXT: v_dual_mov_b32 v114, s2 :: v_dual_lshlrev_b32 v5, 8, v5 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v96, v14 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 8, v11 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v13 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v26 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v12 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v16 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 8, v9 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v17 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, v4, v14 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xff, v24 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v25 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v87 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xff, v30 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v86 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v5 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v26, v12 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v14, v24 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v25, v11 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v30, v13 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v28 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v85 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xff, v33 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v84 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v29 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v31 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 8, v83 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v14, v24 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v25, v16 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v26, v9 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, v28, v17 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v29, v30 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff, v12 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff, v16 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff, v17 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v4, v5 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, v11, v13 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v12, v14 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v16, v9 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v17, v24 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xff, v36 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 8, v18 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xff, v82 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 8, v8 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xff, v32 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 8, v19 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v34 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v81 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xff, v39 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 8, v20 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v9, v11 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v8 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v16, v17 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v18, v19 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v80 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 8, v7 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v35 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v21 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xff, v37 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 8, v71 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xff, v51 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 8, v22 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xff, v70 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 8, v6 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v14, v7 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v16, v17 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v18, v19 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, v20, v21 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v22, v6 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff, v9 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v7 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff, v14 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff, v17 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v6 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v9, v8 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v11, v12 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v18 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v14, v16 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v17, v19 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v38 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 8, v23 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v48 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v69 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xff, v53 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 8, v68 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xff, v67 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xff, v50 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 8, v66 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v8, v9 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v16 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v17, v18 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v19, v2 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v20, v21 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 8, v65 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xff, v55 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff, v14 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v49 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 8, v64 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v15 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xff, v54 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v10 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xff, v52 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v14, v18 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v19, v20 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v15, v1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v21, v10 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v22, v3 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff, v16 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v14 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff, v18 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff, v10 -; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v8, v9 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v17, v2 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v16, v19 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, v18, v1 -; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v10, v3 -; GFX11-TRUE16-NEXT: s_clause 0x5 -; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[97:100], off offset:32 -; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[112:115], off offset:48 -; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[27:30], off offset:64 -; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[4:7], off offset:80 -; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[11:14], off offset:96 -; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[15:18], off offset:112 -; GFX11-TRUE16-NEXT: v_readlane_b32 s104, v41, 8 -; GFX11-TRUE16-NEXT: v_readlane_b32 s103, v41, 7 -; GFX11-TRUE16-NEXT: v_readlane_b32 s102, v41, 6 -; GFX11-TRUE16-NEXT: v_readlane_b32 s101, v41, 5 -; GFX11-TRUE16-NEXT: v_readlane_b32 s100, v41, 4 -; GFX11-TRUE16-NEXT: v_readlane_b32 s99, v41, 3 -; GFX11-TRUE16-NEXT: v_readlane_b32 s98, v41, 2 -; GFX11-TRUE16-NEXT: v_readlane_b32 s97, v41, 1 -; GFX11-TRUE16-NEXT: v_readlane_b32 s96, v41, 0 -; GFX11-TRUE16-NEXT: v_readlane_b32 s87, v40, 31 -; GFX11-TRUE16-NEXT: v_readlane_b32 s86, v40, 30 -; GFX11-TRUE16-NEXT: v_readlane_b32 s85, v40, 29 -; GFX11-TRUE16-NEXT: v_readlane_b32 s84, v40, 28 -; GFX11-TRUE16-NEXT: v_readlane_b32 s83, v40, 27 -; GFX11-TRUE16-NEXT: v_readlane_b32 s82, v40, 26 -; GFX11-TRUE16-NEXT: v_readlane_b32 s81, v40, 25 -; GFX11-TRUE16-NEXT: v_readlane_b32 s80, v40, 24 -; GFX11-TRUE16-NEXT: v_readlane_b32 s71, v40, 23 -; GFX11-TRUE16-NEXT: v_readlane_b32 s70, v40, 22 -; GFX11-TRUE16-NEXT: v_readlane_b32 s69, v40, 21 -; GFX11-TRUE16-NEXT: v_readlane_b32 s68, v40, 20 -; GFX11-TRUE16-NEXT: v_readlane_b32 s67, v40, 19 -; GFX11-TRUE16-NEXT: v_readlane_b32 s66, v40, 18 -; GFX11-TRUE16-NEXT: v_readlane_b32 s65, v40, 17 -; GFX11-TRUE16-NEXT: v_readlane_b32 s64, v40, 16 -; GFX11-TRUE16-NEXT: v_readlane_b32 s55, v40, 15 -; GFX11-TRUE16-NEXT: v_readlane_b32 s54, v40, 14 -; GFX11-TRUE16-NEXT: v_readlane_b32 s53, v40, 13 -; GFX11-TRUE16-NEXT: v_readlane_b32 s52, v40, 12 -; GFX11-TRUE16-NEXT: v_readlane_b32 s51, v40, 11 -; GFX11-TRUE16-NEXT: v_readlane_b32 s50, v40, 10 -; GFX11-TRUE16-NEXT: v_readlane_b32 s49, v40, 9 -; GFX11-TRUE16-NEXT: v_readlane_b32 s48, v40, 8 -; GFX11-TRUE16-NEXT: v_readlane_b32 s39, v40, 7 -; GFX11-TRUE16-NEXT: v_readlane_b32 s38, v40, 6 -; GFX11-TRUE16-NEXT: v_readlane_b32 s37, v40, 5 -; GFX11-TRUE16-NEXT: v_readlane_b32 s36, v40, 4 -; GFX11-TRUE16-NEXT: v_readlane_b32 s35, v40, 3 -; GFX11-TRUE16-NEXT: v_readlane_b32 s34, v40, 2 -; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 1 -; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 0 -; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s0, -1 -; GFX11-TRUE16-NEXT: s_clause 0x3 ; 16-byte Folded Reload -; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 -; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:4 -; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:8 -; GFX11-TRUE16-NEXT: scratch_load_b32 v43, off, s32 offset:12 -; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s0 -; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-FAKE16-LABEL: bitcast_v64bf16_to_v128i8_scalar: -; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s4, -1 -; GFX11-FAKE16-NEXT: s_clause 0x3 ; 16-byte Folded Spill -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:4 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v42, s32 offset:8 -; GFX11-FAKE16-NEXT: scratch_store_b32 off, v43, s32 offset:12 -; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s4 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s96, 0 -; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s72, v1 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v2 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 1 -; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s97, 1 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s62, v3 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s63, v4 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s60, v5 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s34, 2 -; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s98, 2 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s61, v6 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s58, v7 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s59, v8 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s35, 3 -; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s99, 3 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s56, v9 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s57, v10 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s46, v11 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s36, 4 -; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s100, 4 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s47, v12 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v13 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s45, v14 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s37, 5 -; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s101, 5 -; GFX11-FAKE16-NEXT: s_mov_b32 vcc_hi, 0 -; GFX11-FAKE16-NEXT: s_and_b32 s4, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr43 : SGPR spill to VGPR lane -; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr42 : SGPR spill to VGPR lane -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s38, 6 -; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s102, 6 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s39, 7 -; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s103, 7 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s48, 8 -; GFX11-FAKE16-NEXT: v_writelane_b32 v41, s104, 8 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s49, 9 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s50, 10 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s51, 11 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s52, 12 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s53, 13 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s54, 14 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s55, 15 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s64, 16 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s65, 17 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s66, 18 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s67, 19 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s68, 20 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s69, 21 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s70, 22 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s71, 23 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s80, 24 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s81, 25 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s82, 26 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s83, 27 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s84, 28 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s85, 29 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s86, 30 -; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s87, 31 -; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB91_3 -; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s27, 24 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[12:13], s[26:27], 24 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 15 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s27, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s99, s2, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s100, s2, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s101, s1, 24 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 14 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s27, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s11, s1, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s102, s1, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s103, s0, 16 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s26, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s104, s0, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s85, s45, 24 -; GFX11-FAKE16-NEXT: s_lshr_b32 s10, s45, 16 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 17 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s26, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s5, s45, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s87, s44, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s86, s44, 8 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 18 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s25, 24 -; GFX11-FAKE16-NEXT: s_lshr_b32 s81, s47, 24 -; GFX11-FAKE16-NEXT: s_lshr_b32 s98, s47, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s84, s47, 8 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 19 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s25, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s48, s46, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s70, s57, 24 -; GFX11-FAKE16-NEXT: s_lshr_b32 s97, s57, 16 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 13 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s25, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s80, s57, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s83, s56, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s82, s56, 8 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 20 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s24, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s66, s59, 24 -; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s59, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s69, s59, 8 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 21 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s24, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s71, s58, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s39, s58, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s55, s61, 24 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 22 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s23, 24 -; GFX11-FAKE16-NEXT: s_lshr_b32 s8, s61, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s65, s61, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s68, s60, 16 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 23 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s23, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s67, s60, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s51, s63, 24 -; GFX11-FAKE16-NEXT: s_lshr_b32 s96, s63, 16 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 12 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s23, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s54, s63, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s38, s62, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s64, s62, 8 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 24 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s22, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s36, s73, 24 -; GFX11-FAKE16-NEXT: s_lshr_b32 s7, s73, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s50, s73, 8 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 25 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s22, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s53, s72, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s52, s72, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s34, s29, 24 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 26 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s21, 24 -; GFX11-FAKE16-NEXT: s_lshr_b32 s6, s29, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s35, s29, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s37, s28, 16 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 27 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s21, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s49, s28, 8 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[14:15], s[16:17], 24 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[40:41], s[2:3], 24 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 11 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s21, 8 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[42:43], s[0:1], 24 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[74:75], s[44:45], 24 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[76:77], s[46:47], 24 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 28 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s20, 16 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[78:79], s[56:57], 24 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[88:89], s[58:59], 24 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[90:91], s[60:61], 24 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 29 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s20, 8 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[92:93], s[62:63], 24 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[94:95], s[72:73], 24 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[30:31], s[28:29], 24 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 30 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s19, 24 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 31 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s19, 16 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 10 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s19, 8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s4, 0 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s18, 16 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s4, 1 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s18, 8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s4, 2 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s17, 24 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s4, 3 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s17, 16 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 9 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s17, 8 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s4, 4 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s16, 16 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s4, 5 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s16, 8 -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s4, 6 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s3, 24 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s4, 7 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s3, 16 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s3, 8 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1) -; GFX11-FAKE16-NEXT: v_writelane_b32 v42, s4, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s46, 16 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s12, 6 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s13, 7 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[12:13], s[24:25], 24 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s12, 4 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s13, 5 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[12:13], s[22:23], 24 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s12, 2 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s13, 3 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[12:13], s[20:21], 24 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s12, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s13, 1 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[12:13], s[18:19], 24 -; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, vcc_hi -; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB91_4 -; GFX11-FAKE16-NEXT: .LBB91_2: ; %cmp.true -; GFX11-FAKE16-NEXT: s_and_b32 s4, s29, 0xffff0000 -; GFX11-FAKE16-NEXT: s_and_b32 s14, s47, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_and_b32 s4, s1, 0xffff0000 -; GFX11-FAKE16-NEXT: s_lshl_b32 s15, s47, 16 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s29, 16 -; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v1, 16, 1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s6 -; GFX11-FAKE16-NEXT: s_and_b32 s8, s45, 0xffff0000 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s47, v6 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v1 -; GFX11-FAKE16-NEXT: s_lshl_b32 s7, s45, 16 -; GFX11-FAKE16-NEXT: s_and_b32 s78, s28, 0xffff0000 -; GFX11-FAKE16-NEXT: s_bfe_u32 s6, s47, 0x10010 -; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s28, 16 -; GFX11-FAKE16-NEXT: s_add_i32 s45, s6, s47 -; GFX11-FAKE16-NEXT: s_and_b32 s5, s73, 0xffff0000 -; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s73, 16 -; GFX11-FAKE16-NEXT: s_and_b32 s75, s72, 0xffff0000 -; GFX11-FAKE16-NEXT: s_lshl_b32 s76, s72, 16 -; GFX11-FAKE16-NEXT: s_and_b32 s11, s63, 0xffff0000 -; GFX11-FAKE16-NEXT: s_lshl_b32 s74, s63, 16 -; GFX11-FAKE16-NEXT: s_and_b32 s72, s62, 0xffff0000 -; GFX11-FAKE16-NEXT: s_lshl_b32 s73, s62, 16 -; GFX11-FAKE16-NEXT: s_and_b32 s63, s61, 0xffff0000 -; GFX11-FAKE16-NEXT: s_lshl_b32 s62, s61, 16 -; GFX11-FAKE16-NEXT: s_and_b32 s61, s60, 0xffff0000 -; GFX11-FAKE16-NEXT: s_lshl_b32 s60, s60, 16 -; GFX11-FAKE16-NEXT: s_and_b32 s41, s59, 0xffff0000 -; GFX11-FAKE16-NEXT: s_lshl_b32 s40, s59, 16 -; GFX11-FAKE16-NEXT: s_and_b32 s28, s58, 0xffff0000 -; GFX11-FAKE16-NEXT: s_lshl_b32 s29, s58, 16 -; GFX11-FAKE16-NEXT: s_and_b32 s13, s57, 0xffff0000 -; GFX11-FAKE16-NEXT: s_lshl_b32 s10, s57, 16 -; GFX11-FAKE16-NEXT: s_and_b32 s42, s56, 0xffff0000 -; GFX11-FAKE16-NEXT: s_lshl_b32 s43, s56, 16 -; GFX11-FAKE16-NEXT: s_and_b32 s12, s46, 0xffff0000 -; GFX11-FAKE16-NEXT: s_lshl_b32 s9, s46, 16 -; GFX11-FAKE16-NEXT: s_and_b32 s4, s44, 0xffff0000 -; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s44, 16 -; GFX11-FAKE16-NEXT: s_addk_i32 s45, 0x7fff -; GFX11-FAKE16-NEXT: s_bitset1_b32 s47, 22 -; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v2, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3 -; GFX11-FAKE16-NEXT: s_and_b32 s44, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-FAKE16-NEXT: s_cselect_b32 s44, s47, s45 -; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v2 -; GFX11-FAKE16-NEXT: s_lshr_b32 s58, s44, 16 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v2 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s78 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s1, v3 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s79 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-FAKE16-NEXT: s_bfe_u32 s45, s1, 0x10010 -; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1 -; GFX11-FAKE16-NEXT: s_add_i32 s45, s45, s1 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s1, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s45, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s44, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s1, s1, s45 -; GFX11-FAKE16-NEXT: s_and_b32 s44, s0, 0xffff0000 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v2 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s44 -; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v7, 16, 1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v4, v6 -; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s1, 16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v7 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v2 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3 -; GFX11-FAKE16-NEXT: s_bfe_u32 s45, s44, 0x10010 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-FAKE16-NEXT: s_add_i32 s45, s45, s44 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s44, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s45, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s46, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v5, v7 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v6 -; GFX11-FAKE16-NEXT: s_cselect_b32 s44, s44, s45 -; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, 16 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v21 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s5 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v3 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s77 -; GFX11-FAKE16-NEXT: s_bfe_u32 s5, s0, 0x10010 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v22, 16, v4 -; GFX11-FAKE16-NEXT: s_add_i32 s45, s5, s0 -; GFX11-FAKE16-NEXT: s_lshr_b32 s5, s44, 16 -; GFX11-FAKE16-NEXT: s_addk_i32 s45, 0x7fff -; GFX11-FAKE16-NEXT: s_bitset1_b32 s0, 22 -; GFX11-FAKE16-NEXT: s_and_b32 s44, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s0, s0, s45 -; GFX11-FAKE16-NEXT: s_and_b32 s44, s3, 0xffff0000 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s44 -; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v8, 16, 1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v1, v5, 16, 1 -; GFX11-FAKE16-NEXT: s_lshr_b32 s0, s0, 16 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v23 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v9 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v6, v8 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v1, v5 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v2, 16, v3 -; GFX11-FAKE16-NEXT: s_bfe_u32 s45, s44, 0x10010 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v5 -; GFX11-FAKE16-NEXT: s_add_i32 s45, s45, s44 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s44, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s45, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s46, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v4 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8 -; GFX11-FAKE16-NEXT: s_cselect_b32 s44, s44, s45 -; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s3 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s76 -; GFX11-FAKE16-NEXT: s_lshr_b32 s59, s44, 16 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s75 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s3, v10 -; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v9, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 24, v7 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v6 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v4, 16, 1 -; GFX11-FAKE16-NEXT: s_bfe_u32 s45, s3, 0x10010 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: s_add_i32 s45, s45, s3 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s3, 22 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v4 -; GFX11-FAKE16-NEXT: s_addk_i32 s45, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s44, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s3, s3, s45 -; GFX11-FAKE16-NEXT: s_and_b32 s44, s2, 0xffff0000 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s44 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v3 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v8, v9 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v9 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s3, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v4 -; GFX11-FAKE16-NEXT: s_bfe_u32 s45, s44, 0x10010 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v24 -; GFX11-FAKE16-NEXT: s_add_i32 s45, s45, s44 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-FAKE16-NEXT: s_addk_i32 s45, 0x7fff -; GFX11-FAKE16-NEXT: s_bitset1_b32 s44, 22 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s74 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v25, 16, v5 -; GFX11-FAKE16-NEXT: s_and_b32 s46, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s44, s44, s45 -; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s2 -; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 24, v14 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s2, v8 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v3 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s11 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: s_bfe_u32 s11, s2, 0x10010 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX11-FAKE16-NEXT: s_add_i32 s45, s11, s2 -; GFX11-FAKE16-NEXT: s_lshr_b32 s11, s44, 16 -; GFX11-FAKE16-NEXT: s_addk_i32 s45, 0x7fff -; GFX11-FAKE16-NEXT: s_bitset1_b32 s2, 22 -; GFX11-FAKE16-NEXT: s_and_b32 s44, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s2, s2, s45 -; GFX11-FAKE16-NEXT: s_and_b32 s44, s17, 0xffff0000 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v26 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s44 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v3, 16, 1 -; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s2, 16 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v2, 16, v9 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v1 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v5 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v3 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v13 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo -; GFX11-FAKE16-NEXT: s_bfe_u32 s45, s44, 0x10010 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: s_add_i32 s45, s45, s44 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s44, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s45, 0x7fff -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8 -; GFX11-FAKE16-NEXT: s_and_b32 s46, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s44, s44, s45 -; GFX11-FAKE16-NEXT: s_lshl_b32 s17, s17, 16 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s73 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s17 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s72 -; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v2, 16, 1 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s17, v4 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v8, v9, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-FAKE16-NEXT: s_lshr_b32 s72, s44, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v2 -; GFX11-FAKE16-NEXT: s_bfe_u32 s45, s17, 0x10010 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v3 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v27 -; GFX11-FAKE16-NEXT: s_add_i32 s45, s45, s17 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s17, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s45, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s44, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v28, 16, v3 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v2 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v1, 16, 1 -; GFX11-FAKE16-NEXT: s_cselect_b32 s17, s17, s45 -; GFX11-FAKE16-NEXT: s_and_b32 s44, s16, 0xffff0000 -; GFX11-FAKE16-NEXT: s_lshr_b32 s17, s17, 16 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s63 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 24, v16 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v2 -; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v3, 16, 1 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v5, v3 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v29 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v8, v1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s44 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v8 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: s_bfe_u32 s45, s44, 0x10010 -; GFX11-FAKE16-NEXT: s_add_i32 s45, s45, s44 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s44, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s45, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s46, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s44, s44, s45 -; GFX11-FAKE16-NEXT: s_lshl_b32 s16, s16, 16 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s46, s44, 16 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v9, vcc_lo -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s16, v8 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v3 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s62 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX11-FAKE16-NEXT: s_bfe_u32 s45, s16, 0x10010 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-FAKE16-NEXT: s_add_i32 s45, s45, s16 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s16, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s45, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s44, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s16, s16, s45 -; GFX11-FAKE16-NEXT: s_and_b32 s44, s19, 0xffff0000 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s44 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v1, 16, v5 -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v4, 16, 1 -; GFX11-FAKE16-NEXT: s_lshr_b32 s16, s16, 16 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v10 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v9, v4 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s60 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v4 -; GFX11-FAKE16-NEXT: s_bfe_u32 s45, s44, 0x10010 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s61 -; GFX11-FAKE16-NEXT: s_add_i32 s45, s45, s44 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s44, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s45, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s47, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s44, s44, s45 -; GFX11-FAKE16-NEXT: s_lshl_b32 s19, s19, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v9 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s19 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v8, 16, 1 -; GFX11-FAKE16-NEXT: s_lshr_b32 s60, s44, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v1 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s19, v10 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v5, 16, 1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v9, v8 -; GFX11-FAKE16-NEXT: s_bfe_u32 s45, s19, 0x10010 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v2 -; GFX11-FAKE16-NEXT: s_add_i32 s45, s45, s19 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s19, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s45, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s44, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s19, s19, s45 -; GFX11-FAKE16-NEXT: s_and_b32 s44, s18, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v3, v5 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v8 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s44 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX11-FAKE16-NEXT: s_lshr_b32 s19, s19, 16 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s29 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s41 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s41, v4 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s47, s17, s72 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v2 -; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v3, 16, 1 -; GFX11-FAKE16-NEXT: s_bfe_u32 s44, s41, 0x10010 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, s41 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s41, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s44, 0x7fff -; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s40 -; GFX11-FAKE16-NEXT: s_and_b32 s45, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s41, s41, s44 -; GFX11-FAKE16-NEXT: s_lshl_b32 s18, s18, 16 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v31 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s18 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v32 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v3 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v30, 16, v4 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s18, v5 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v1, 16, v8 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v2 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v3 -; GFX11-FAKE16-NEXT: s_bfe_u32 s40, s18, 0x10010 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s28 -; GFX11-FAKE16-NEXT: s_add_i32 s44, s40, s18 -; GFX11-FAKE16-NEXT: s_lshr_b32 s40, s41, 16 -; GFX11-FAKE16-NEXT: s_addk_i32 s44, 0x7fff -; GFX11-FAKE16-NEXT: s_bitset1_b32 s18, 22 -; GFX11-FAKE16-NEXT: s_and_b32 s41, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s18, s18, s44 -; GFX11-FAKE16-NEXT: s_and_b32 s41, s21, 0xffff0000 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s41 -; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v9, 16, 1 -; GFX11-FAKE16-NEXT: s_lshr_b32 s18, s18, 16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s28, v5 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v9 -; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v8, 16, 1 -; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v10, 16, 1 -; GFX11-FAKE16-NEXT: s_bfe_u32 s29, s28, 0x10010 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v1 -; GFX11-FAKE16-NEXT: s_add_i32 s29, s29, s28 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s28, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s29, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s41, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s28, s28, s29 -; GFX11-FAKE16-NEXT: s_lshl_b32 s21, s21, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s21 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: s_lshr_b32 s61, s28, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v5, v10 -; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s44, s2, s11 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s21, v11 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v4, v8 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-FAKE16-NEXT: s_bfe_u32 s29, s21, 0x10010 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v2 -; GFX11-FAKE16-NEXT: s_add_i32 s29, s29, s21 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s21, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s29, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s28, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s21, s21, s29 -; GFX11-FAKE16-NEXT: s_and_b32 s28, s20, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v3 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v8 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s28 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v10 -; GFX11-FAKE16-NEXT: s_lshr_b32 s21, s21, 16 -; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s45, s3, s59 -; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s46, s16, s46 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s13 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v5 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 24, v18 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: s_bfe_u32 s28, s13, 0x10010 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v34 -; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, s13 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s13, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s28, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s29, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s13, s13, s28 -; GFX11-FAKE16-NEXT: s_lshl_b32 s20, s20, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s20 -; GFX11-FAKE16-NEXT: v_bfe_u32 v1, v3, 16, 1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s10 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v33, 16, v4 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v35 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s20, v8 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v1, v3 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v2, 16, v9 -; GFX11-FAKE16-NEXT: s_bfe_u32 s10, s20, 0x10010 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-FAKE16-NEXT: s_add_i32 s28, s10, s20 -; GFX11-FAKE16-NEXT: s_lshr_b32 s10, s13, 16 -; GFX11-FAKE16-NEXT: s_addk_i32 s28, 0x7fff -; GFX11-FAKE16-NEXT: s_bitset1_b32 s20, 22 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v3 -; GFX11-FAKE16-NEXT: s_and_b32 s13, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-FAKE16-NEXT: s_cselect_b32 s13, s20, s28 -; GFX11-FAKE16-NEXT: s_and_b32 s20, s23, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s42 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s20 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v4 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v5 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s43 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s28, v2 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v19 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-FAKE16-NEXT: s_bfe_u32 s20, s28, 0x10010 -; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v8, 16, 1 -; GFX11-FAKE16-NEXT: s_add_i32 s29, s20, s28 -; GFX11-FAKE16-NEXT: s_lshr_b32 s20, s13, 16 -; GFX11-FAKE16-NEXT: s_addk_i32 s29, 0x7fff -; GFX11-FAKE16-NEXT: s_bitset1_b32 s28, 22 -; GFX11-FAKE16-NEXT: s_and_b32 s13, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s13, s28, s29 -; GFX11-FAKE16-NEXT: s_lshl_b32 s23, s23, 16 -; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v9, 16, 1 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s23 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v3 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v4, v8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s62, s13, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v5, v9 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s23, v2 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v8 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-FAKE16-NEXT: s_bfe_u32 s28, s23, 0x10010 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v9 -; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, s23 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s23, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s28, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s13, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: s_cselect_b32 s13, s23, s28 -; GFX11-FAKE16-NEXT: s_and_b32 s23, s22, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s15 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v36 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s23 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s14 -; GFX11-FAKE16-NEXT: s_lshr_b32 s23, s13, 16 -; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v8, 16, 1 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s14, v3 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v71, v37, 16, v4 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s12 -; GFX11-FAKE16-NEXT: s_bfe_u32 s15, s14, 0x10010 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v1 -; GFX11-FAKE16-NEXT: s_add_i32 s15, s15, s14 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s14, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s15, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s13, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s13, s14, s15 -; GFX11-FAKE16-NEXT: s_lshl_b32 s14, s22, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s14 -; GFX11-FAKE16-NEXT: v_bfe_u32 v1, v5, 16, 1 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v38 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v9, v8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s13, s13, 16 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s14, v10 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v1, v5 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v70, v2, 16, v3 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v9 -; GFX11-FAKE16-NEXT: s_bfe_u32 s12, s14, 0x10010 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v8 -; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, s14 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s14, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s12, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s15, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s12, s14, s12 -; GFX11-FAKE16-NEXT: s_and_b32 s14, s25, 0xffff0000 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s14 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v10 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 -; GFX11-FAKE16-NEXT: s_lshr_b32 s22, s12, 16 -; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v4, 16, 1 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v2 -; GFX11-FAKE16-NEXT: s_bfe_u32 s14, s9, 0x10010 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: s_add_i32 s14, s14, s9 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s9, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s14, 0x7fff -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v1 -; GFX11-FAKE16-NEXT: s_and_b32 s12, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s9, s9, s14 -; GFX11-FAKE16-NEXT: s_lshl_b32 s12, s25, 16 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s8 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s12 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v3, v4 -; GFX11-FAKE16-NEXT: s_lshr_b32 s63, s9, 16 -; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v8, 16, 1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v4 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v8 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8 -; GFX11-FAKE16-NEXT: s_bfe_u32 s12, s8, 0x10010 -; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v9, 16, 1 -; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, s8 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s8, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s12, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s9, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4 -; GFX11-FAKE16-NEXT: s_cselect_b32 s8, s8, s12 -; GFX11-FAKE16-NEXT: s_and_b32 s9, s24, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3 -; GFX11-FAKE16-NEXT: s_lshr_b32 s25, s8, 16 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v2, v10, vcc_lo -; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s9 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s7 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v12, v9 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s6 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v2 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v9 -; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s28, s0, s5 -; GFX11-FAKE16-NEXT: s_bfe_u32 s9, s7, 0x10010 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v3 -; GFX11-FAKE16-NEXT: s_add_i32 s9, s9, s7 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s7, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s9, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s8, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s7, s7, s9 -; GFX11-FAKE16-NEXT: s_lshl_b32 s8, s24, 16 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v4 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s8 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v8, 16, 1 -; GFX11-FAKE16-NEXT: s_lshr_b32 s12, s7, 16 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v10 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v8 -; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v12, 16, 1 -; GFX11-FAKE16-NEXT: s_bfe_u32 s4, s8, 0x10010 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v2 -; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, s8 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s8, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s4, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s6, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s4, s8, s4 -; GFX11-FAKE16-NEXT: s_and_b32 s6, s27, 0xffff0000 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v4 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v52, 0x40c00000, s6 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v12 -; GFX11-FAKE16-NEXT: s_lshr_b32 s24, s4, 16 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v52 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v9 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52 -; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v9, 16, 1 -; GFX11-FAKE16-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX11-FAKE16-NEXT: s_add_i32 s7, s7, s6 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s6, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s7, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s4, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s4, s6, s7 -; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s27, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v3 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v4, v9 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v8 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v12 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s6 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12 -; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2 -; GFX11-FAKE16-NEXT: s_lshr_b32 s73, s4, 16 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v49 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v8 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v51 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v66, v1, 16, v11 -; GFX11-FAKE16-NEXT: s_bfe_u32 s7, s6, 0x10010 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8 -; GFX11-FAKE16-NEXT: s_add_i32 s7, s7, s6 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s6, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s7, 0x7fff -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX11-FAKE16-NEXT: s_and_b32 s4, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s4, s6, s7 -; GFX11-FAKE16-NEXT: s_and_b32 s6, s26, 0xffff0000 -; GFX11-FAKE16-NEXT: s_lshr_b32 s27, s4, 16 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s6 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v52 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v39 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v55, v50, 16, v4 -; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s8, s22, s13 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v3 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v54, v2, 16, v8 -; GFX11-FAKE16-NEXT: v_lshl_or_b32 v67, v48, 16, v5 -; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[17:18] -; GFX11-FAKE16-NEXT: s_bfe_u32 s5, s6, 0x10010 -; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[9:10], 24, v[15:16] -; GFX11-FAKE16-NEXT: s_add_i32 s5, s5, s6 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s6, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s5, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s4, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s14, s6, s5 -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s26, 16 -; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s6, s20, s10 -; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 -; GFX11-FAKE16-NEXT: s_lshr_b32 s13, s14, 16 -; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[10:11], 24, v[13:14] -; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[11:12], 24, v[6:7] -; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s29, s1, s58 -; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v1 -; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 -; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[1:2], 24, v[54:55] -; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[2:3], 24, v[66:67] -; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[70:71] -; GFX11-FAKE16-NEXT: s_bfe_u32 s10, s11, 0x10010 -; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[4:5], 24, v[19:20] -; GFX11-FAKE16-NEXT: s_add_i32 s10, s10, s11 -; GFX11-FAKE16-NEXT: s_bitset1_b32 s11, 22 -; GFX11-FAKE16-NEXT: s_addk_i32 s10, 0x7fff -; GFX11-FAKE16-NEXT: s_and_b32 s14, vcc_lo, exec_lo -; GFX11-FAKE16-NEXT: s_cselect_b32 s10, s11, s10 -; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s5, s19, s60 -; GFX11-FAKE16-NEXT: s_lshr_b32 s26, s10, 16 -; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s4, s18, s40 -; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s9, s23, s62 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 24, v55 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 8, v55 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v54 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 8, v54 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 24, v67 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 8, v67 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v66 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 8, v66 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 24, v71 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 8, v71 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 16, v70 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 8, v70 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 24, v20 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 8, v20 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 8, v19 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 8, v18 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v17 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 8, v17 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 8, v16 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v15 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 8, v15 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 8, v14 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 8, v13 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 8, v7 -; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 8, v6 -; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s7, s21, s61 -; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s11, s25, s63 -; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s57, s27, s73 -; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s56, s26, s13 -; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s10, s24, s12 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[94:95], s[8:9], 24 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[12:13], s[4:5], 24 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[14:15], s[46:47], 24 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[40:41], s[44:45], 24 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[42:43], s[28:29], 24 -; GFX11-FAKE16-NEXT: s_lshr_b64 vcc, s[56:57], 24 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[34:35], s[10:11], 24 -; GFX11-FAKE16-NEXT: s_lshr_b64 s[30:31], s[6:7], 24 -; GFX11-FAKE16-NEXT: s_lshr_b32 s13, s57, 24 -; GFX11-FAKE16-NEXT: s_lshr_b32 s15, s57, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s41, s56, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s43, s56, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s56, s11, 24 -; GFX11-FAKE16-NEXT: s_lshr_b32 s11, s11, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s57, s10, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s10, s10, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s74, s9, 24 -; GFX11-FAKE16-NEXT: s_lshr_b32 s9, s9, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s75, s8, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s8, s8, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s76, s7, 24 -; GFX11-FAKE16-NEXT: s_lshr_b32 s77, s7, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s78, s6, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s79, s6, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s88, s5, 24 -; GFX11-FAKE16-NEXT: s_lshr_b32 s89, s5, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s90, s4, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s91, s4, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s92, s47, 24 -; GFX11-FAKE16-NEXT: s_lshr_b32 s47, s47, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s93, s46, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s46, s46, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s95, s45, 24 -; GFX11-FAKE16-NEXT: s_lshr_b32 s45, s45, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s99, s44, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s100, s44, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s101, s29, 24 -; GFX11-FAKE16-NEXT: s_lshr_b32 s102, s29, 8 -; GFX11-FAKE16-NEXT: s_lshr_b32 s103, s28, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s104, s28, 8 -; GFX11-FAKE16-NEXT: s_branch .LBB91_5 -; GFX11-FAKE16-NEXT: .LBB91_3: -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr74 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr104 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr103 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr42 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr102 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr11 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr101 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr100 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr99 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr40 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr14 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr12 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr49 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr37 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr35 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr6 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr34 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr52 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr53 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr50 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr7 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr36 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr64 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr38 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr54 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr96 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr51 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr67 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr68 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr65 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr8 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr55 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr39 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr71 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr69 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr9 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr66 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr82 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr83 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr80 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr97 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr70 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr48 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr84 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr98 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr81 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr86 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr87 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr10 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr85 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr30 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr94 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr92 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr90 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr88 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr78 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr76 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 0 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s5, 1 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s4, 2 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s5, 3 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s74, 4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s75, 5 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr74 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; kill: killed $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr5 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s74, 6 -; GFX11-FAKE16-NEXT: v_writelane_b32 v43, s75, 7 -; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr74 -; GFX11-FAKE16-NEXT: s_branch .LBB91_2 -; GFX11-FAKE16-NEXT: .LBB91_4: -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s94 :: v_dual_mov_b32 v11, s30 -; GFX11-FAKE16-NEXT: v_readlane_b32 s94, v43, 2 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v96, s37 :: v_dual_mov_b32 v87, s34 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s49 :: v_dual_mov_b32 v7, s35 -; GFX11-FAKE16-NEXT: v_readlane_b32 s95, v43, 3 -; GFX11-FAKE16-NEXT: v_readlane_b32 vcc_lo, v43, 6 -; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v43, 0 -; GFX11-FAKE16-NEXT: v_readlane_b32 s34, v43, 4 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, s44 :: v_dual_mov_b32 v51, s45 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, s10 :: v_dual_mov_b32 v49, s46 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, s47 :: v_dual_mov_b32 v48, s98 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, s56 :: v_dual_mov_b32 v37, s97 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, s57 :: v_dual_mov_b32 v35, s58 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, s59 :: v_dual_mov_b32 v33, s9 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, s60 :: v_dual_mov_b32 v31, s61 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v30, s8 :: v_dual_mov_b32 v29, s62 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v27, s63 :: v_dual_mov_b32 v28, s96 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v26, s72 :: v_dual_mov_b32 v25, s7 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v24, s73 :: v_dual_mov_b32 v23, s28 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v21, s29 :: v_dual_mov_b32 v22, s6 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, s87 :: v_dual_mov_b32 v54, s86 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v5, s85 :: v_dual_mov_b32 v12, s5 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v65, s4 :: v_dual_mov_b32 v66, s48 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v55, s81 :: v_dual_mov_b32 v64, s84 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v69, s83 :: v_dual_mov_b32 v70, s82 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v67, s70 :: v_dual_mov_b32 v68, s80 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, s71 :: v_dual_mov_b32 v19, s39 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v71, s66 :: v_dual_mov_b32 v20, s69 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, s68 :: v_dual_mov_b32 v17, s67 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v81, s55 :: v_dual_mov_b32 v18, s65 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v84, s38 :: v_dual_mov_b32 v15, s64 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v83, s51 :: v_dual_mov_b32 v16, s54 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v86, s53 :: v_dual_mov_b32 v13, s52 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v85, s36 :: v_dual_mov_b32 v14, s50 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, s74 :: v_dual_mov_b32 v2, s76 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, s78 :: v_dual_mov_b32 v4, s88 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, s90 :: v_dual_mov_b32 v9, s92 -; GFX11-FAKE16-NEXT: s_mov_b32 s58, s11 -; GFX11-FAKE16-NEXT: v_readlane_b32 s59, v43, 8 -; GFX11-FAKE16-NEXT: v_readlane_b32 s72, v43, 9 -; GFX11-FAKE16-NEXT: v_readlane_b32 s60, v43, 10 -; GFX11-FAKE16-NEXT: v_readlane_b32 s61, v43, 11 -; GFX11-FAKE16-NEXT: v_readlane_b32 s62, v43, 12 -; GFX11-FAKE16-NEXT: v_readlane_b32 s63, v43, 13 -; GFX11-FAKE16-NEXT: v_readlane_b32 s73, v43, 14 -; GFX11-FAKE16-NEXT: v_readlane_b32 s13, v43, 15 -; GFX11-FAKE16-NEXT: v_readlane_b32 s15, v43, 16 -; GFX11-FAKE16-NEXT: v_readlane_b32 s41, v43, 17 -; GFX11-FAKE16-NEXT: v_readlane_b32 s43, v43, 18 -; GFX11-FAKE16-NEXT: v_readlane_b32 s56, v43, 19 -; GFX11-FAKE16-NEXT: v_readlane_b32 s11, v43, 20 -; GFX11-FAKE16-NEXT: v_readlane_b32 s57, v43, 21 -; GFX11-FAKE16-NEXT: v_readlane_b32 s10, v43, 22 -; GFX11-FAKE16-NEXT: v_readlane_b32 s74, v43, 23 -; GFX11-FAKE16-NEXT: v_readlane_b32 s9, v43, 24 -; GFX11-FAKE16-NEXT: v_readlane_b32 s75, v43, 25 -; GFX11-FAKE16-NEXT: v_readlane_b32 s8, v43, 26 -; GFX11-FAKE16-NEXT: v_readlane_b32 s76, v43, 27 -; GFX11-FAKE16-NEXT: v_readlane_b32 s77, v43, 28 -; GFX11-FAKE16-NEXT: v_readlane_b32 s78, v43, 29 -; GFX11-FAKE16-NEXT: v_readlane_b32 s79, v43, 30 -; GFX11-FAKE16-NEXT: v_readlane_b32 s88, v43, 31 -; GFX11-FAKE16-NEXT: v_readlane_b32 s89, v42, 0 -; GFX11-FAKE16-NEXT: v_readlane_b32 s90, v42, 1 -; GFX11-FAKE16-NEXT: v_readlane_b32 s91, v42, 2 -; GFX11-FAKE16-NEXT: v_readlane_b32 s92, v42, 3 -; GFX11-FAKE16-NEXT: v_readlane_b32 s47, v42, 4 -; GFX11-FAKE16-NEXT: v_readlane_b32 s93, v42, 5 -; GFX11-FAKE16-NEXT: v_readlane_b32 vcc_hi, v43, 7 -; GFX11-FAKE16-NEXT: v_readlane_b32 s46, v42, 6 -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v43, 1 -; GFX11-FAKE16-NEXT: v_readlane_b32 s95, v42, 7 -; GFX11-FAKE16-NEXT: v_readlane_b32 s45, v42, 8 -; GFX11-FAKE16-NEXT: v_readlane_b32 s35, v43, 5 -; GFX11-FAKE16-NEXT: .LBB91_5: ; %end -; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s104, 8 -; GFX11-FAKE16-NEXT: s_and_b32 s5, s103, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s42, 8 -; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s4 -; GFX11-FAKE16-NEXT: s_or_b32 s4, s5, s6 -; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s102, 8 -; GFX11-FAKE16-NEXT: s_and_b32 s6, s58, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s7, s101, 8 -; GFX11-FAKE16-NEXT: s_or_b32 s1, s1, s5 -; GFX11-FAKE16-NEXT: s_or_b32 s5, s6, s7 -; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s4, 16 -; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, 0xffff -; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s5, 16 -; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s4 -; GFX11-FAKE16-NEXT: s_or_b32 s1, s1, s5 -; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s100, 8 -; GFX11-FAKE16-NEXT: s_and_b32 s5, s99, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s40, 8 -; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s4 -; GFX11-FAKE16-NEXT: s_or_b32 s4, s5, s6 -; GFX11-FAKE16-NEXT: s_and_b32 s3, s3, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s45, 8 -; GFX11-FAKE16-NEXT: s_and_b32 s6, s59, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s7, s95, 8 -; GFX11-FAKE16-NEXT: s_or_b32 s3, s3, s5 -; GFX11-FAKE16-NEXT: s_or_b32 s5, s6, s7 -; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s4, 16 -; GFX11-FAKE16-NEXT: s_and_b32 s3, s3, 0xffff -; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s5, 16 -; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s4 -; GFX11-FAKE16-NEXT: s_or_b32 s3, s3, s5 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v97, s0 :: v_dual_mov_b32 v98, s1 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v99, s2 :: v_dual_mov_b32 v100, s3 -; GFX11-FAKE16-NEXT: s_and_b32 s0, s16, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s46, 8 -; GFX11-FAKE16-NEXT: s_and_b32 s2, s93, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s14, 8 -; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s1 -; GFX11-FAKE16-NEXT: s_or_b32 s1, s2, s3 -; GFX11-FAKE16-NEXT: s_and_b32 s2, s17, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s47, 8 -; GFX11-FAKE16-NEXT: s_and_b32 s4, s72, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s92, 8 -; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s3 -; GFX11-FAKE16-NEXT: s_or_b32 s3, s4, s5 -; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s1 -; GFX11-FAKE16-NEXT: s_or_b32 s1, s2, s3 -; GFX11-FAKE16-NEXT: s_and_b32 s2, s18, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s91, 8 -; GFX11-FAKE16-NEXT: s_and_b32 s4, s90, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s12, 8 -; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s3 -; GFX11-FAKE16-NEXT: s_or_b32 s3, s4, s5 -; GFX11-FAKE16-NEXT: s_and_b32 s4, s19, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s89, 8 -; GFX11-FAKE16-NEXT: s_and_b32 s6, s60, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s7, s88, 8 -; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s5 -; GFX11-FAKE16-NEXT: s_or_b32 s5, s6, s7 -; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-FAKE16-NEXT: s_and_b32 s4, s4, 0xffff -; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s5, 16 -; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s3 -; GFX11-FAKE16-NEXT: s_or_b32 s3, s4, s5 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v112, s0 :: v_dual_mov_b32 v113, s1 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v114, s2 :: v_dual_mov_b32 v115, s3 -; GFX11-FAKE16-NEXT: s_and_b32 s0, s20, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s79, 8 -; GFX11-FAKE16-NEXT: s_and_b32 s2, s78, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s30, 8 -; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s1 -; GFX11-FAKE16-NEXT: s_or_b32 s1, s2, s3 -; GFX11-FAKE16-NEXT: s_and_b32 s2, s21, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s77, 8 -; GFX11-FAKE16-NEXT: s_and_b32 s4, s61, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s76, 8 -; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s3 -; GFX11-FAKE16-NEXT: s_or_b32 s3, s4, s5 -; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s1 -; GFX11-FAKE16-NEXT: s_or_b32 s1, s2, s3 -; GFX11-FAKE16-NEXT: s_and_b32 s2, s22, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s8, 8 -; GFX11-FAKE16-NEXT: s_and_b32 s4, s75, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s94, 8 -; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s3 -; GFX11-FAKE16-NEXT: s_or_b32 s3, s4, s5 -; GFX11-FAKE16-NEXT: s_and_b32 s4, s23, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s9, 8 -; GFX11-FAKE16-NEXT: s_and_b32 s6, s62, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s7, s74, 8 -; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s5 -; GFX11-FAKE16-NEXT: s_or_b32 s5, s6, s7 -; GFX11-FAKE16-NEXT: s_and_b32 s4, s4, 0xffff -; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s5, 16 -; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s3 -; GFX11-FAKE16-NEXT: s_clause 0x1 -; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[97:100], off -; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[112:115], off offset:16 -; GFX11-FAKE16-NEXT: s_or_b32 s3, s4, s5 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v97, s0 :: v_dual_mov_b32 v98, s1 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v99, s2 :: v_dual_mov_b32 v100, s3 -; GFX11-FAKE16-NEXT: s_and_b32 s0, s24, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s10, 8 -; GFX11-FAKE16-NEXT: s_and_b32 s2, s57, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s34, 8 -; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s1 -; GFX11-FAKE16-NEXT: s_or_b32 s1, s2, s4 -; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16 -; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s11, 8 -; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s1 -; GFX11-FAKE16-NEXT: s_and_b32 s1, s25, 0xff -; GFX11-FAKE16-NEXT: s_and_b32 s3, s63, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s56, 8 -; GFX11-FAKE16-NEXT: s_or_b32 s1, s1, s2 -; GFX11-FAKE16-NEXT: s_or_b32 s2, s3, s4 -; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, 0xffff -; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16 -; GFX11-FAKE16-NEXT: s_and_b32 s3, s26, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s43, 8 -; GFX11-FAKE16-NEXT: s_or_b32 s1, s1, s2 -; GFX11-FAKE16-NEXT: s_or_b32 s2, s3, s4 -; GFX11-FAKE16-NEXT: s_and_b32 s3, s41, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s4, vcc_lo, 8 -; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s15, 8 -; GFX11-FAKE16-NEXT: s_or_b32 s3, s3, s4 -; GFX11-FAKE16-NEXT: s_and_b32 s4, s27, 0xff -; GFX11-FAKE16-NEXT: s_lshl_b32 s6, s13, 8 -; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s5 -; GFX11-FAKE16-NEXT: s_and_b32 s5, s73, 0xff -; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff -; GFX11-FAKE16-NEXT: s_or_b32 s5, s5, s6 -; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-FAKE16-NEXT: s_and_b32 s4, s4, 0xffff -; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s5, 16 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v112, s0 :: v_dual_and_b32 v23, 0xff, v23 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v113, s1 :: v_dual_lshlrev_b32 v6, 8, v6 -; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v114, s2 :: v_dual_lshlrev_b32 v11, 8, v11 -; GFX11-FAKE16-NEXT: s_or_b32 s3, s4, s5 -; GFX11-FAKE16-NEXT: v_dual_mov_b32 v115, s3 :: v_dual_and_b32 v96, 0xff, v96 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v23, v6 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 8, v7 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 8, v13 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v96, v11 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v10 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v14 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 8, v15 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 8, v9 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v16 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 8, v8 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v6, v11 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v21 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v22 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 8, v87 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v26 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v86 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v7 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 8, v4 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v21 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v22, v13 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v26, v10 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v24, v14 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v25 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 8, v85 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v29 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v84 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v27 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v28 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 8, v83 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v14, v21 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v22, v15 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v24, v9 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v25, v16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v26, v27 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v6, v7 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v11, v10 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v13, v14 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v15, v9 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v16, v21 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v32 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v17 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v82 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v31 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v18 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v30 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v81 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v35 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 8, v19 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v10 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v11, v8 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v13, v14 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v18 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v80 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v34 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v20 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v33 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 8, v71 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v38 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 8, v70 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v69 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v14, v4 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v18 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v19, v20 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v21, v3 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v11 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v4 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v14, v15 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v16, v3 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v36 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 8, v68 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v37 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v67 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v49 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 8, v66 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v65 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v39 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 8, v64 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v3, v4 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v10, v11 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v16, v17 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v18, v2 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v19, v20 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v48 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 8, v55 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v52 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 8, v54 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v53 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v51 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v12 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v50 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 8, v5 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v16, v17 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v18, v19 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v20, v1 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v21, v12 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v22, v5 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v16 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v1 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12 -; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v3, v4 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v10, v2 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v11, v18 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v17, v19 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v12, v5 -; GFX11-FAKE16-NEXT: s_clause 0x5 -; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[97:100], off offset:32 -; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[112:115], off offset:48 -; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[23:26], off offset:64 -; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[6:9], off offset:80 -; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:96 -; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[1:4], off offset:112 -; GFX11-FAKE16-NEXT: v_readlane_b32 s104, v41, 8 -; GFX11-FAKE16-NEXT: v_readlane_b32 s103, v41, 7 -; GFX11-FAKE16-NEXT: v_readlane_b32 s102, v41, 6 -; GFX11-FAKE16-NEXT: v_readlane_b32 s101, v41, 5 -; GFX11-FAKE16-NEXT: v_readlane_b32 s100, v41, 4 -; GFX11-FAKE16-NEXT: v_readlane_b32 s99, v41, 3 -; GFX11-FAKE16-NEXT: v_readlane_b32 s98, v41, 2 -; GFX11-FAKE16-NEXT: v_readlane_b32 s97, v41, 1 -; GFX11-FAKE16-NEXT: v_readlane_b32 s96, v41, 0 -; GFX11-FAKE16-NEXT: v_readlane_b32 s87, v40, 31 -; GFX11-FAKE16-NEXT: v_readlane_b32 s86, v40, 30 -; GFX11-FAKE16-NEXT: v_readlane_b32 s85, v40, 29 -; GFX11-FAKE16-NEXT: v_readlane_b32 s84, v40, 28 -; GFX11-FAKE16-NEXT: v_readlane_b32 s83, v40, 27 -; GFX11-FAKE16-NEXT: v_readlane_b32 s82, v40, 26 -; GFX11-FAKE16-NEXT: v_readlane_b32 s81, v40, 25 -; GFX11-FAKE16-NEXT: v_readlane_b32 s80, v40, 24 -; GFX11-FAKE16-NEXT: v_readlane_b32 s71, v40, 23 -; GFX11-FAKE16-NEXT: v_readlane_b32 s70, v40, 22 -; GFX11-FAKE16-NEXT: v_readlane_b32 s69, v40, 21 -; GFX11-FAKE16-NEXT: v_readlane_b32 s68, v40, 20 -; GFX11-FAKE16-NEXT: v_readlane_b32 s67, v40, 19 -; GFX11-FAKE16-NEXT: v_readlane_b32 s66, v40, 18 -; GFX11-FAKE16-NEXT: v_readlane_b32 s65, v40, 17 -; GFX11-FAKE16-NEXT: v_readlane_b32 s64, v40, 16 -; GFX11-FAKE16-NEXT: v_readlane_b32 s55, v40, 15 -; GFX11-FAKE16-NEXT: v_readlane_b32 s54, v40, 14 -; GFX11-FAKE16-NEXT: v_readlane_b32 s53, v40, 13 -; GFX11-FAKE16-NEXT: v_readlane_b32 s52, v40, 12 -; GFX11-FAKE16-NEXT: v_readlane_b32 s51, v40, 11 -; GFX11-FAKE16-NEXT: v_readlane_b32 s50, v40, 10 -; GFX11-FAKE16-NEXT: v_readlane_b32 s49, v40, 9 -; GFX11-FAKE16-NEXT: v_readlane_b32 s48, v40, 8 -; GFX11-FAKE16-NEXT: v_readlane_b32 s39, v40, 7 -; GFX11-FAKE16-NEXT: v_readlane_b32 s38, v40, 6 -; GFX11-FAKE16-NEXT: v_readlane_b32 s37, v40, 5 -; GFX11-FAKE16-NEXT: v_readlane_b32 s36, v40, 4 -; GFX11-FAKE16-NEXT: v_readlane_b32 s35, v40, 3 -; GFX11-FAKE16-NEXT: v_readlane_b32 s34, v40, 2 -; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 1 -; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 0 -; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s0, -1 -; GFX11-FAKE16-NEXT: s_clause 0x3 ; 16-byte Folded Reload -; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 -; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s32 offset:4 -; GFX11-FAKE16-NEXT: scratch_load_b32 v42, off, s32 offset:8 -; GFX11-FAKE16-NEXT: scratch_load_b32 v43, off, s32 offset:12 -; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s0 -; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +; GFX11-LABEL: bitcast_v64bf16_to_v128i8_scalar: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_xor_saveexec_b32 s4, -1 +; GFX11-NEXT: s_clause 0x2 ; 12-byte Folded Spill +; GFX11-NEXT: scratch_store_b32 off, v18, s32 +; GFX11-NEXT: scratch_store_b32 off, v19, s32 offset:4 +; GFX11-NEXT: scratch_store_b32 off, v20, s32 offset:8 +; GFX11-NEXT: s_mov_b32 exec_lo, s4 +; GFX11-NEXT: v_writelane_b32 v18, s30, 0 +; GFX11-NEXT: v_writelane_b32 v19, s96, 0 +; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 +; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 +; GFX11-NEXT: v_writelane_b32 v18, s31, 1 +; GFX11-NEXT: v_writelane_b32 v19, s97, 1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-NEXT: v_readfirstlane_b32 s40, v16 +; GFX11-NEXT: v_readfirstlane_b32 s41, v17 +; GFX11-NEXT: v_readfirstlane_b32 s28, v1 +; GFX11-NEXT: v_writelane_b32 v18, s34, 2 +; GFX11-NEXT: v_writelane_b32 v19, s98, 2 +; GFX11-NEXT: v_readfirstlane_b32 s29, v2 +; GFX11-NEXT: v_readfirstlane_b32 s14, v3 +; GFX11-NEXT: v_readfirstlane_b32 s15, v4 +; GFX11-NEXT: v_writelane_b32 v18, s35, 3 +; GFX11-NEXT: v_writelane_b32 v19, s99, 3 +; GFX11-NEXT: v_readfirstlane_b32 s12, v5 +; GFX11-NEXT: v_readfirstlane_b32 s13, v6 +; GFX11-NEXT: v_readfirstlane_b32 s10, v7 +; GFX11-NEXT: v_writelane_b32 v18, s36, 4 +; GFX11-NEXT: v_writelane_b32 v19, s100, 4 +; GFX11-NEXT: v_readfirstlane_b32 s11, v8 +; GFX11-NEXT: v_readfirstlane_b32 s8, v9 +; GFX11-NEXT: v_readfirstlane_b32 s9, v10 +; GFX11-NEXT: v_writelane_b32 v18, s37, 5 +; GFX11-NEXT: v_writelane_b32 v19, s101, 5 +; GFX11-NEXT: v_readfirstlane_b32 s6, v11 +; GFX11-NEXT: v_readfirstlane_b32 s7, v12 +; GFX11-NEXT: v_readfirstlane_b32 s4, v13 +; GFX11-NEXT: v_writelane_b32 v18, s38, 6 +; GFX11-NEXT: v_writelane_b32 v19, s102, 6 +; GFX11-NEXT: v_readfirstlane_b32 s5, v14 +; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo +; GFX11-NEXT: ; implicit-def: $vgpr20 : SGPR spill to VGPR lane +; GFX11-NEXT: v_writelane_b32 v18, s39, 7 +; GFX11-NEXT: v_writelane_b32 v19, s103, 7 +; GFX11-NEXT: v_writelane_b32 v18, s48, 8 +; GFX11-NEXT: v_writelane_b32 v19, s104, 8 +; GFX11-NEXT: s_mov_b32 s104, 0 +; GFX11-NEXT: v_writelane_b32 v18, s49, 9 +; GFX11-NEXT: v_writelane_b32 v18, s50, 10 +; GFX11-NEXT: v_writelane_b32 v18, s51, 11 +; GFX11-NEXT: v_writelane_b32 v18, s52, 12 +; GFX11-NEXT: v_writelane_b32 v18, s53, 13 +; GFX11-NEXT: v_writelane_b32 v18, s54, 14 +; GFX11-NEXT: v_writelane_b32 v18, s55, 15 +; GFX11-NEXT: v_writelane_b32 v18, s64, 16 +; GFX11-NEXT: v_writelane_b32 v18, s65, 17 +; GFX11-NEXT: v_writelane_b32 v18, s66, 18 +; GFX11-NEXT: v_writelane_b32 v18, s67, 19 +; GFX11-NEXT: v_writelane_b32 v18, s68, 20 +; GFX11-NEXT: v_writelane_b32 v18, s69, 21 +; GFX11-NEXT: v_writelane_b32 v18, s70, 22 +; GFX11-NEXT: v_writelane_b32 v18, s71, 23 +; GFX11-NEXT: v_writelane_b32 v18, s80, 24 +; GFX11-NEXT: v_writelane_b32 v18, s81, 25 +; GFX11-NEXT: v_writelane_b32 v18, s82, 26 +; GFX11-NEXT: v_writelane_b32 v18, s83, 27 +; GFX11-NEXT: v_writelane_b32 v18, s84, 28 +; GFX11-NEXT: v_writelane_b32 v18, s85, 29 +; GFX11-NEXT: v_writelane_b32 v18, s86, 30 +; GFX11-NEXT: v_writelane_b32 v18, s87, 31 +; GFX11-NEXT: s_cbranch_scc0 .LBB91_2 +; GFX11-NEXT: ; %bb.1: ; %cmp.false +; GFX11-NEXT: s_lshr_b32 s42, s25, 16 +; GFX11-NEXT: s_lshr_b32 s44, s28, 16 +; GFX11-NEXT: v_writelane_b32 v20, s42, 20 +; GFX11-NEXT: s_lshr_b32 s42, s23, 16 +; GFX11-NEXT: s_lshr_b32 s46, s41, 24 +; GFX11-NEXT: s_lshr_b64 s[90:91], s[26:27], 24 +; GFX11-NEXT: s_mov_b32 s91, s46 +; GFX11-NEXT: v_writelane_b32 v20, s42, 19 +; GFX11-NEXT: s_lshr_b32 s42, s21, 16 +; GFX11-NEXT: s_lshr_b64 s[46:47], s[24:25], 24 +; GFX11-NEXT: s_lshr_b32 s72, s7, 24 +; GFX11-NEXT: s_lshr_b32 s73, s7, 8 +; GFX11-NEXT: v_writelane_b32 v20, s42, 18 +; GFX11-NEXT: s_lshr_b32 s42, s19, 16 +; GFX11-NEXT: s_lshr_b32 s77, s27, 24 +; GFX11-NEXT: s_lshr_b32 s76, s6, 16 +; GFX11-NEXT: s_lshr_b64 s[78:79], s[16:17], 24 +; GFX11-NEXT: v_writelane_b32 v20, s42, 17 +; GFX11-NEXT: s_lshr_b32 s42, s17, 16 +; GFX11-NEXT: s_lshr_b64 s[92:93], s[2:3], 24 +; GFX11-NEXT: s_lshr_b32 s88, s27, 8 +; GFX11-NEXT: s_mov_b32 s79, s72 +; GFX11-NEXT: v_writelane_b32 v20, s42, 16 +; GFX11-NEXT: s_lshr_b32 s42, s3, 24 +; GFX11-NEXT: s_mov_b32 s93, s73 +; GFX11-NEXT: s_lshr_b64 s[94:95], s[0:1], 24 +; GFX11-NEXT: s_lshr_b64 s[72:73], s[12:13], 24 +; GFX11-NEXT: v_writelane_b32 v20, s42, 21 +; GFX11-NEXT: s_lshr_b32 s42, s3, 16 +; GFX11-NEXT: s_lshr_b32 vcc_lo, s26, 16 +; GFX11-NEXT: s_lshr_b32 s56, s4, 16 +; GFX11-NEXT: s_lshr_b32 s57, s4, 8 +; GFX11-NEXT: v_writelane_b32 v20, s42, 15 +; GFX11-NEXT: s_lshr_b32 s42, s3, 8 +; GFX11-NEXT: s_mov_b32 s95, s76 +; GFX11-NEXT: s_mov_b32 s73, s77 +; GFX11-NEXT: s_lshr_b64 s[76:77], s[14:15], 24 +; GFX11-NEXT: v_writelane_b32 v20, s42, 22 +; GFX11-NEXT: s_lshr_b32 s42, s2, 16 +; GFX11-NEXT: s_lshr_b64 s[62:63], s[20:21], 24 +; GFX11-NEXT: s_lshr_b64 s[74:75], s[18:19], 24 +; GFX11-NEXT: s_mov_b32 s77, s88 +; GFX11-NEXT: v_writelane_b32 v20, s42, 23 +; GFX11-NEXT: s_lshr_b32 s42, s2, 8 +; GFX11-NEXT: s_lshr_b64 s[88:89], s[28:29], 24 +; GFX11-NEXT: s_lshr_b32 s71, s27, 16 +; GFX11-NEXT: s_lshr_b32 s83, s26, 8 +; GFX11-NEXT: v_writelane_b32 v20, s42, 24 +; GFX11-NEXT: s_lshr_b32 s42, s1, 24 +; GFX11-NEXT: s_lshr_b32 s66, s25, 24 +; GFX11-NEXT: s_lshr_b32 s67, s25, 8 +; GFX11-NEXT: s_lshr_b32 s68, s24, 16 +; GFX11-NEXT: v_writelane_b32 v20, s42, 25 +; GFX11-NEXT: s_lshr_b32 s42, s1, 16 +; GFX11-NEXT: s_lshr_b32 s49, s24, 8 +; GFX11-NEXT: s_lshr_b32 s69, s23, 24 +; GFX11-NEXT: s_lshr_b32 s70, s23, 8 +; GFX11-NEXT: v_writelane_b32 v20, s42, 14 +; GFX11-NEXT: s_lshr_b32 s42, s1, 8 +; GFX11-NEXT: s_lshr_b32 s64, s22, 16 +; GFX11-NEXT: s_lshr_b32 s80, s22, 8 +; GFX11-NEXT: s_lshr_b32 s58, s21, 24 +; GFX11-NEXT: v_writelane_b32 v20, s42, 26 +; GFX11-NEXT: s_lshr_b32 s42, s5, 24 +; GFX11-NEXT: s_lshr_b32 s59, s21, 8 +; GFX11-NEXT: s_lshr_b32 s50, s20, 16 +; GFX11-NEXT: s_lshr_b32 s81, s20, 8 +; GFX11-NEXT: v_writelane_b32 v20, s42, 27 +; GFX11-NEXT: s_lshr_b32 s42, s5, 16 +; GFX11-NEXT: s_lshr_b32 s85, s19, 24 +; GFX11-NEXT: s_lshr_b32 s60, s19, 8 +; GFX11-NEXT: s_lshr_b32 s61, s18, 16 +; GFX11-NEXT: v_writelane_b32 v20, s42, 13 +; GFX11-NEXT: s_lshr_b32 s42, s5, 8 +; GFX11-NEXT: s_lshr_b32 s96, s18, 8 +; GFX11-NEXT: s_lshr_b32 s98, s17, 24 +; GFX11-NEXT: s_lshr_b32 s99, s17, 8 +; GFX11-NEXT: v_writelane_b32 v20, s42, 28 +; GFX11-NEXT: s_lshr_b32 s42, s7, 16 +; GFX11-NEXT: s_lshr_b32 s53, s16, 16 +; GFX11-NEXT: s_lshr_b32 s43, s16, 8 +; GFX11-NEXT: s_lshr_b32 s102, s0, 16 +; GFX11-NEXT: v_writelane_b32 v20, s42, 12 +; GFX11-NEXT: s_lshr_b32 s42, s9, 16 +; GFX11-NEXT: s_lshr_b32 s103, s0, 8 +; GFX11-NEXT: s_lshr_b32 s34, s6, 8 +; GFX11-NEXT: s_lshr_b32 s65, s9, 24 +; GFX11-NEXT: v_writelane_b32 v20, s42, 11 +; GFX11-NEXT: s_lshr_b32 s42, s11, 16 +; GFX11-NEXT: s_lshr_b32 s55, s9, 8 +; GFX11-NEXT: s_lshr_b32 s35, s8, 16 +; GFX11-NEXT: s_lshr_b32 s36, s8, 8 +; GFX11-NEXT: v_writelane_b32 v20, s42, 10 +; GFX11-NEXT: s_lshr_b32 s42, s13, 16 +; GFX11-NEXT: s_lshr_b32 s37, s11, 24 +; GFX11-NEXT: s_lshr_b32 s38, s11, 8 +; GFX11-NEXT: s_lshr_b32 s39, s10, 16 +; GFX11-NEXT: v_writelane_b32 v20, s42, 9 +; GFX11-NEXT: s_lshr_b32 s42, s15, 16 +; GFX11-NEXT: s_lshr_b32 s48, s10, 8 +; GFX11-NEXT: s_lshr_b32 s84, s13, 24 +; GFX11-NEXT: s_lshr_b32 s82, s13, 8 +; GFX11-NEXT: v_writelane_b32 v20, s42, 8 +; GFX11-NEXT: s_lshr_b32 s86, s12, 16 +; GFX11-NEXT: s_lshr_b32 s51, s12, 8 +; GFX11-NEXT: s_lshr_b32 s97, s15, 24 +; GFX11-NEXT: s_lshr_b32 s87, s15, 8 +; GFX11-NEXT: v_writelane_b32 v20, s44, 29 +; GFX11-NEXT: s_lshr_b32 s44, s28, 8 +; GFX11-NEXT: s_lshr_b32 s52, s14, 16 +; GFX11-NEXT: s_lshr_b32 s100, s14, 8 +; GFX11-NEXT: s_lshr_b32 s42, s29, 24 +; GFX11-NEXT: v_writelane_b32 v20, s44, 30 +; GFX11-NEXT: s_lshr_b32 s44, s41, 8 +; GFX11-NEXT: s_lshr_b32 vcc_hi, s29, 16 +; GFX11-NEXT: s_lshr_b32 s101, s29, 8 +; GFX11-NEXT: s_lshr_b32 s54, s41, 16 +; GFX11-NEXT: v_writelane_b32 v20, s44, 31 +; GFX11-NEXT: s_lshr_b32 s44, s40, 16 +; GFX11-NEXT: s_lshr_b32 s45, s40, 8 +; GFX11-NEXT: s_mov_b32 s63, s56 +; GFX11-NEXT: s_mov_b32 s75, s57 +; GFX11-NEXT: v_writelane_b32 v20, s46, 2 +; GFX11-NEXT: s_lshr_b64 s[56:57], s[10:11], 24 +; GFX11-NEXT: s_mov_b32 s89, vcc_lo +; GFX11-NEXT: s_lshr_b64 s[30:31], s[40:41], 24 +; GFX11-NEXT: v_writelane_b32 v20, s47, 3 +; GFX11-NEXT: s_lshr_b64 s[46:47], s[22:23], 24 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_writelane_b32 v20, s46, 0 +; GFX11-NEXT: v_writelane_b32 v20, s47, 1 +; GFX11-NEXT: s_lshr_b64 s[46:47], s[4:5], 24 +; GFX11-NEXT: v_writelane_b32 v20, s46, 6 +; GFX11-NEXT: v_writelane_b32 v20, s47, 7 +; GFX11-NEXT: s_lshr_b64 s[46:47], s[6:7], 24 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_writelane_b32 v20, s46, 4 +; GFX11-NEXT: v_writelane_b32 v20, s47, 5 +; GFX11-NEXT: s_lshr_b64 s[46:47], s[8:9], 24 +; GFX11-NEXT: s_branch .LBB91_3 +; GFX11-NEXT: .LBB91_2: +; GFX11-NEXT: ; implicit-def: $sgpr42 +; GFX11-NEXT: ; kill: killed $sgpr42 +; GFX11-NEXT: ; implicit-def: $sgpr43 +; GFX11-NEXT: ; implicit-def: $sgpr46 +; GFX11-NEXT: ; kill: killed $sgpr46 +; GFX11-NEXT: ; implicit-def: $vcc_hi +; GFX11-NEXT: ; implicit-def: $vcc_lo +; GFX11-NEXT: s_mov_b32 s104, -1 +; GFX11-NEXT: ; implicit-def: $sgpr42 +; GFX11-NEXT: ; kill: killed $sgpr42 +; GFX11-NEXT: ; implicit-def: $sgpr46 +; GFX11-NEXT: ; kill: killed $sgpr46 +; GFX11-NEXT: ; implicit-def: $sgpr103 +; GFX11-NEXT: ; implicit-def: $sgpr102 +; GFX11-NEXT: ; implicit-def: $sgpr94 +; GFX11-NEXT: ; implicit-def: $sgpr92 +; GFX11-NEXT: ; implicit-def: $sgpr53 +; GFX11-NEXT: ; implicit-def: $sgpr78 +; GFX11-NEXT: ; implicit-def: $sgpr99 +; GFX11-NEXT: ; implicit-def: $sgpr98 +; GFX11-NEXT: ; implicit-def: $sgpr96 +; GFX11-NEXT: ; implicit-def: $sgpr61 +; GFX11-NEXT: ; implicit-def: $sgpr74 +; GFX11-NEXT: ; implicit-def: $sgpr60 +; GFX11-NEXT: ; implicit-def: $sgpr85 +; GFX11-NEXT: ; implicit-def: $sgpr81 +; GFX11-NEXT: ; implicit-def: $sgpr50 +; GFX11-NEXT: ; implicit-def: $sgpr62 +; GFX11-NEXT: ; implicit-def: $sgpr59 +; GFX11-NEXT: ; implicit-def: $sgpr58 +; GFX11-NEXT: ; implicit-def: $sgpr80 +; GFX11-NEXT: ; implicit-def: $sgpr64 +; GFX11-NEXT: ; implicit-def: $sgpr70 +; GFX11-NEXT: ; implicit-def: $sgpr69 +; GFX11-NEXT: ; implicit-def: $sgpr49 +; GFX11-NEXT: ; implicit-def: $sgpr68 +; GFX11-NEXT: ; implicit-def: $sgpr67 +; GFX11-NEXT: ; implicit-def: $sgpr66 +; GFX11-NEXT: ; implicit-def: $sgpr83 +; GFX11-NEXT: ; implicit-def: $sgpr89 +; GFX11-NEXT: ; implicit-def: $sgpr77 +; GFX11-NEXT: ; implicit-def: $sgpr71 +; GFX11-NEXT: ; implicit-def: $sgpr73 +; GFX11-NEXT: ; implicit-def: $sgpr45 +; GFX11-NEXT: ; implicit-def: $sgpr44 +; GFX11-NEXT: ; implicit-def: $sgpr54 +; GFX11-NEXT: ; implicit-def: $sgpr91 +; GFX11-NEXT: ; implicit-def: $sgpr101 +; GFX11-NEXT: ; implicit-def: $sgpr100 +; GFX11-NEXT: ; implicit-def: $sgpr52 +; GFX11-NEXT: ; implicit-def: $sgpr87 +; GFX11-NEXT: ; implicit-def: $sgpr97 +; GFX11-NEXT: ; implicit-def: $sgpr51 +; GFX11-NEXT: ; implicit-def: $sgpr86 +; GFX11-NEXT: ; implicit-def: $sgpr82 +; GFX11-NEXT: ; implicit-def: $sgpr84 +; GFX11-NEXT: ; implicit-def: $sgpr48 +; GFX11-NEXT: ; implicit-def: $sgpr39 +; GFX11-NEXT: ; implicit-def: $sgpr38 +; GFX11-NEXT: ; implicit-def: $sgpr37 +; GFX11-NEXT: ; implicit-def: $sgpr36 +; GFX11-NEXT: ; implicit-def: $sgpr35 +; GFX11-NEXT: ; implicit-def: $sgpr55 +; GFX11-NEXT: ; implicit-def: $sgpr65 +; GFX11-NEXT: ; implicit-def: $sgpr34 +; GFX11-NEXT: ; implicit-def: $sgpr95 +; GFX11-NEXT: ; implicit-def: $sgpr93 +; GFX11-NEXT: ; implicit-def: $sgpr79 +; GFX11-NEXT: ; implicit-def: $sgpr75 +; GFX11-NEXT: ; implicit-def: $sgpr63 +; GFX11-NEXT: ; implicit-def: $sgpr90 +; GFX11-NEXT: ; implicit-def: $sgpr30 +; GFX11-NEXT: ; implicit-def: $sgpr88 +; GFX11-NEXT: ; implicit-def: $sgpr76 +; GFX11-NEXT: ; implicit-def: $sgpr72 +; GFX11-NEXT: ; implicit-def: $sgpr56 +; GFX11-NEXT: ; implicit-def: $sgpr42 +; GFX11-NEXT: ; kill: killed $sgpr42 +; GFX11-NEXT: ; implicit-def: $sgpr46 +; GFX11-NEXT: ; kill: killed $sgpr46 +; GFX11-NEXT: ; implicit-def: $sgpr42 +; GFX11-NEXT: ; kill: killed $sgpr42 +; GFX11-NEXT: ; implicit-def: $sgpr46 +; GFX11-NEXT: ; kill: killed $sgpr46 +; GFX11-NEXT: ; implicit-def: $sgpr42 +; GFX11-NEXT: ; kill: killed $sgpr42 +; GFX11-NEXT: ; implicit-def: $sgpr46 +; GFX11-NEXT: ; kill: killed $sgpr46 +; GFX11-NEXT: ; implicit-def: $sgpr42 +; GFX11-NEXT: ; kill: killed $sgpr42 +; GFX11-NEXT: ; implicit-def: $sgpr46 +; GFX11-NEXT: ; kill: killed $sgpr46 +; GFX11-NEXT: ; implicit-def: $sgpr42 +; GFX11-NEXT: ; kill: killed $sgpr42 +; GFX11-NEXT: ; implicit-def: $sgpr46 +; GFX11-NEXT: ; kill: killed $sgpr46 +; GFX11-NEXT: ; implicit-def: $sgpr42 +; GFX11-NEXT: ; kill: killed $sgpr42 +; GFX11-NEXT: ; implicit-def: $sgpr46 +; GFX11-NEXT: ; kill: killed $sgpr46 +; GFX11-NEXT: ; implicit-def: $sgpr42 +; GFX11-NEXT: ; kill: killed $sgpr42 +; GFX11-NEXT: ; implicit-def: $sgpr46 +; GFX11-NEXT: ; implicit-def: $sgpr42 +; GFX11-NEXT: ; kill: killed $sgpr42 +; GFX11-NEXT: ; implicit-def: $sgpr42 +; GFX11-NEXT: ; kill: killed $sgpr42 +; GFX11-NEXT: ; implicit-def: $sgpr42 +; GFX11-NEXT: v_writelane_b32 v20, s42, 0 +; GFX11-NEXT: v_writelane_b32 v20, s43, 1 +; GFX11-NEXT: ; implicit-def: $sgpr42 +; GFX11-NEXT: ; kill: killed $sgpr42 +; GFX11-NEXT: ; implicit-def: $sgpr42 +; GFX11-NEXT: ; kill: killed $sgpr42 +; GFX11-NEXT: ; implicit-def: $sgpr42 +; GFX11-NEXT: ; kill: killed $sgpr42 +; GFX11-NEXT: ; implicit-def: $sgpr42 +; GFX11-NEXT: ; kill: killed $sgpr42 +; GFX11-NEXT: ; implicit-def: $sgpr42 +; GFX11-NEXT: v_writelane_b32 v20, s46, 2 +; GFX11-NEXT: ; kill: killed $sgpr42 +; GFX11-NEXT: ; implicit-def: $sgpr42 +; GFX11-NEXT: v_writelane_b32 v20, s47, 3 +; GFX11-NEXT: ; implicit-def: $sgpr46 +; GFX11-NEXT: v_writelane_b32 v20, vcc_lo, 4 +; GFX11-NEXT: v_writelane_b32 v20, vcc_hi, 5 +; GFX11-NEXT: ; implicit-def: $vcc_lo +; GFX11-NEXT: v_writelane_b32 v20, vcc_lo, 6 +; GFX11-NEXT: v_writelane_b32 v20, vcc_hi, 7 +; GFX11-NEXT: .LBB91_3: ; %Flow +; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s104 +; GFX11-NEXT: s_mov_b32 s104, s54 +; GFX11-NEXT: s_mov_b32 s54, vcc_hi +; GFX11-NEXT: s_mov_b32 vcc_hi, s34 +; GFX11-NEXT: s_mov_b32 s34, s65 +; GFX11-NEXT: s_mov_b32 s65, s84 +; GFX11-NEXT: s_mov_b32 s84, s86 +; GFX11-NEXT: s_mov_b32 s86, s97 +; GFX11-NEXT: s_mov_b32 s97, s43 +; GFX11-NEXT: s_cbranch_vccnz .LBB91_5 +; GFX11-NEXT: ; %bb.4: ; %cmp.true +; GFX11-NEXT: s_and_b32 s42, s41, 0xffff0000 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s42 +; GFX11-NEXT: v_readfirstlane_b32 s42, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s43, s42, 0x10010 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_add_i32 s43, s43, s42 +; GFX11-NEXT: s_bitset1_b32 s42, 22 +; GFX11-NEXT: s_addk_i32 s43, 0x7fff +; GFX11-NEXT: s_and_b32 s44, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s42, s42, s43 +; GFX11-NEXT: s_lshl_b32 s41, s41, 16 +; GFX11-NEXT: s_lshr_b32 s104, s42, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s41 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s41, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s43, s41, 0x10010 +; GFX11-NEXT: s_add_i32 s42, s43, s41 +; GFX11-NEXT: s_bitset1_b32 s41, 22 +; GFX11-NEXT: s_addk_i32 s42, 0x7fff +; GFX11-NEXT: s_and_b32 s43, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s41, s41, s42 +; GFX11-NEXT: s_and_b32 s42, s40, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s41, s41, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s42 +; GFX11-NEXT: s_pack_ll_b32_b16 s31, s41, s104 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s42, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s43, s42, 0x10010 +; GFX11-NEXT: s_add_i32 s43, s43, s42 +; GFX11-NEXT: s_bitset1_b32 s42, 22 +; GFX11-NEXT: s_addk_i32 s43, 0x7fff +; GFX11-NEXT: s_and_b32 s44, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s42, s42, s43 +; GFX11-NEXT: s_lshl_b32 s40, s40, 16 +; GFX11-NEXT: s_lshr_b32 s42, s42, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s40 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s40, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s43, s40, 0x10010 +; GFX11-NEXT: s_add_i32 s43, s43, s40 +; GFX11-NEXT: s_bitset1_b32 s40, 22 +; GFX11-NEXT: s_addk_i32 s43, 0x7fff +; GFX11-NEXT: s_and_b32 s44, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s40, s40, s43 +; GFX11-NEXT: s_and_b32 s43, s29, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s40, s40, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s43 +; GFX11-NEXT: s_pack_ll_b32_b16 s30, s40, s42 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s43, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s44, s43, 0x10010 +; GFX11-NEXT: s_add_i32 s44, s44, s43 +; GFX11-NEXT: s_bitset1_b32 s43, 22 +; GFX11-NEXT: s_addk_i32 s44, 0x7fff +; GFX11-NEXT: s_and_b32 s45, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s43, s43, s44 +; GFX11-NEXT: s_lshl_b32 s29, s29, 16 +; GFX11-NEXT: s_lshr_b32 s54, s43, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s29 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s29, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s44, s29, 0x10010 +; GFX11-NEXT: s_add_i32 s43, s44, s29 +; GFX11-NEXT: s_bitset1_b32 s29, 22 +; GFX11-NEXT: s_addk_i32 s43, 0x7fff +; GFX11-NEXT: s_and_b32 s44, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s29, s29, s43 +; GFX11-NEXT: s_and_b32 s43, s28, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s29, s29, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s43 +; GFX11-NEXT: s_pack_ll_b32_b16 s89, s29, s54 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s43, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s44, s43, 0x10010 +; GFX11-NEXT: s_add_i32 s44, s44, s43 +; GFX11-NEXT: s_bitset1_b32 s43, 22 +; GFX11-NEXT: s_addk_i32 s44, 0x7fff +; GFX11-NEXT: s_and_b32 s45, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s43, s43, s44 +; GFX11-NEXT: s_lshl_b32 s28, s28, 16 +; GFX11-NEXT: s_lshr_b32 s43, s43, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s28 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s28, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s44, s28, 0x10010 +; GFX11-NEXT: s_add_i32 s44, s44, s28 +; GFX11-NEXT: s_bitset1_b32 s28, 22 +; GFX11-NEXT: s_addk_i32 s44, 0x7fff +; GFX11-NEXT: s_and_b32 s45, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s28, s28, s44 +; GFX11-NEXT: s_and_b32 s44, s15, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s28, s28, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s44 +; GFX11-NEXT: s_pack_ll_b32_b16 s88, s28, s43 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s44, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s45, s44, 0x10010 +; GFX11-NEXT: s_add_i32 s45, s45, s44 +; GFX11-NEXT: s_bitset1_b32 s44, 22 +; GFX11-NEXT: s_addk_i32 s45, 0x7fff +; GFX11-NEXT: s_and_b32 s46, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s44, s44, s45 +; GFX11-NEXT: s_lshl_b32 s15, s15, 16 +; GFX11-NEXT: s_lshr_b32 s72, s44, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s15 +; GFX11-NEXT: v_writelane_b32 v20, s72, 8 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s15, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s45, s15, 0x10010 +; GFX11-NEXT: s_add_i32 s44, s45, s15 +; GFX11-NEXT: s_bitset1_b32 s15, 22 +; GFX11-NEXT: s_addk_i32 s44, 0x7fff +; GFX11-NEXT: s_and_b32 s45, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s15, s15, s44 +; GFX11-NEXT: s_and_b32 s44, s14, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s15, s15, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s44 +; GFX11-NEXT: s_pack_ll_b32_b16 s77, s15, s72 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s44, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s45, s44, 0x10010 +; GFX11-NEXT: s_add_i32 s45, s45, s44 +; GFX11-NEXT: s_bitset1_b32 s44, 22 +; GFX11-NEXT: s_addk_i32 s45, 0x7fff +; GFX11-NEXT: s_and_b32 s46, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s44, s44, s45 +; GFX11-NEXT: s_lshl_b32 s14, s14, 16 +; GFX11-NEXT: s_lshr_b32 s44, s44, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s14 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s14, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s45, s14, 0x10010 +; GFX11-NEXT: s_add_i32 s45, s45, s14 +; GFX11-NEXT: s_bitset1_b32 s14, 22 +; GFX11-NEXT: s_addk_i32 s45, 0x7fff +; GFX11-NEXT: s_and_b32 s46, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s14, s14, s45 +; GFX11-NEXT: s_and_b32 s45, s13, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s14, s14, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s45 +; GFX11-NEXT: s_pack_ll_b32_b16 s76, s14, s44 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s45, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s46, s45, 0x10010 +; GFX11-NEXT: s_add_i32 s46, s46, s45 +; GFX11-NEXT: s_bitset1_b32 s45, 22 +; GFX11-NEXT: s_addk_i32 s46, 0x7fff +; GFX11-NEXT: s_and_b32 s47, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s45, s45, s46 +; GFX11-NEXT: s_lshl_b32 s13, s13, 16 +; GFX11-NEXT: s_lshr_b32 s73, s45, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s13 +; GFX11-NEXT: v_writelane_b32 v20, s73, 9 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s13, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s46, s13, 0x10010 +; GFX11-NEXT: s_add_i32 s45, s46, s13 +; GFX11-NEXT: s_bitset1_b32 s13, 22 +; GFX11-NEXT: s_addk_i32 s45, 0x7fff +; GFX11-NEXT: s_and_b32 s46, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s13, s13, s45 +; GFX11-NEXT: s_and_b32 s45, s12, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s13, s13, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s45 +; GFX11-NEXT: s_pack_ll_b32_b16 s73, s13, s73 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s45, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s46, s45, 0x10010 +; GFX11-NEXT: s_add_i32 s46, s46, s45 +; GFX11-NEXT: s_bitset1_b32 s45, 22 +; GFX11-NEXT: s_addk_i32 s46, 0x7fff +; GFX11-NEXT: s_and_b32 s47, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s45, s45, s46 +; GFX11-NEXT: s_lshl_b32 s12, s12, 16 +; GFX11-NEXT: s_lshr_b32 s45, s45, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s12 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s12, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s46, s12, 0x10010 +; GFX11-NEXT: s_add_i32 s46, s46, s12 +; GFX11-NEXT: s_bitset1_b32 s12, 22 +; GFX11-NEXT: s_addk_i32 s46, 0x7fff +; GFX11-NEXT: s_and_b32 s47, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s12, s12, s46 +; GFX11-NEXT: s_and_b32 s46, s11, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s12, s12, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s46 +; GFX11-NEXT: s_pack_ll_b32_b16 s72, s12, s45 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s46, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s47, s46, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s47, s46 +; GFX11-NEXT: s_bitset1_b32 s46, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s46, s46, s47 +; GFX11-NEXT: s_lshl_b32 s11, s11, 16 +; GFX11-NEXT: s_lshr_b32 s75, s46, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s11 +; GFX11-NEXT: v_writelane_b32 v20, s75, 10 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s11, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s47, s11, 0x10010 +; GFX11-NEXT: s_add_i32 s46, s47, s11 +; GFX11-NEXT: s_bitset1_b32 s11, 22 +; GFX11-NEXT: s_addk_i32 s46, 0x7fff +; GFX11-NEXT: s_and_b32 s47, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s11, s11, s46 +; GFX11-NEXT: s_and_b32 s46, s10, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s11, s11, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s46 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s46, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s47, s46, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s47, s46 +; GFX11-NEXT: s_bitset1_b32 s46, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s46, s46, s47 +; GFX11-NEXT: s_lshl_b32 s10, s10, 16 +; GFX11-NEXT: s_lshr_b32 s46, s46, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s10 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s10, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s47, s10, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s47, s10 +; GFX11-NEXT: s_bitset1_b32 s10, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s10, s10, s47 +; GFX11-NEXT: s_and_b32 s47, s9, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s10, s10, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s47, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s47, 0x10010 +; GFX11-NEXT: s_add_i32 s56, s56, s47 +; GFX11-NEXT: s_bitset1_b32 s47, 22 +; GFX11-NEXT: s_addk_i32 s56, 0x7fff +; GFX11-NEXT: s_and_b32 s57, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s47, s47, s56 +; GFX11-NEXT: s_lshl_b32 s9, s9, 16 +; GFX11-NEXT: s_lshr_b32 s78, s47, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s9 +; GFX11-NEXT: v_writelane_b32 v20, s78, 11 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s9, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s9, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s56, s9 +; GFX11-NEXT: s_bitset1_b32 s9, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s9, s9, s47 +; GFX11-NEXT: s_and_b32 s47, s8, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s9, s9, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s47, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s47, 0x10010 +; GFX11-NEXT: s_add_i32 s56, s56, s47 +; GFX11-NEXT: s_bitset1_b32 s47, 22 +; GFX11-NEXT: s_addk_i32 s56, 0x7fff +; GFX11-NEXT: s_and_b32 s57, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s47, s47, s56 +; GFX11-NEXT: s_lshl_b32 s8, s8, 16 +; GFX11-NEXT: s_lshr_b32 s58, s47, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s8 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s8, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s8, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s56, s8 +; GFX11-NEXT: s_bitset1_b32 s8, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s8, s8, s47 +; GFX11-NEXT: s_and_b32 s47, s7, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s8, s8, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s47, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s47, 0x10010 +; GFX11-NEXT: s_add_i32 s56, s56, s47 +; GFX11-NEXT: s_bitset1_b32 s47, 22 +; GFX11-NEXT: s_addk_i32 s56, 0x7fff +; GFX11-NEXT: s_and_b32 s57, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s47, s47, s56 +; GFX11-NEXT: s_lshl_b32 s7, s7, 16 +; GFX11-NEXT: s_lshr_b32 s79, s47, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s7 +; GFX11-NEXT: v_writelane_b32 v20, s79, 12 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s7, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s7, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s56, s7 +; GFX11-NEXT: s_bitset1_b32 s7, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s7, s7, s47 +; GFX11-NEXT: s_and_b32 s47, s6, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s7, s7, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_pack_ll_b32_b16 s45, s7, s79 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s47, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s47, 0x10010 +; GFX11-NEXT: s_add_i32 s56, s56, s47 +; GFX11-NEXT: s_bitset1_b32 s47, 22 +; GFX11-NEXT: s_addk_i32 s56, 0x7fff +; GFX11-NEXT: s_and_b32 s57, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s47, s47, s56 +; GFX11-NEXT: s_lshl_b32 s6, s6, 16 +; GFX11-NEXT: s_lshr_b32 s59, s47, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s6 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s6, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s6, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s56, s6 +; GFX11-NEXT: s_bitset1_b32 s6, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s6, s6, s47 +; GFX11-NEXT: s_and_b32 s47, s5, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s6, s6, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s47, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s47, 0x10010 +; GFX11-NEXT: s_add_i32 s56, s56, s47 +; GFX11-NEXT: s_bitset1_b32 s47, 22 +; GFX11-NEXT: s_addk_i32 s56, 0x7fff +; GFX11-NEXT: s_and_b32 s57, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s47, s47, s56 +; GFX11-NEXT: s_lshl_b32 s5, s5, 16 +; GFX11-NEXT: s_lshr_b32 s92, s47, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s5 +; GFX11-NEXT: v_writelane_b32 v20, s92, 13 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s5, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s5, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s56, s5 +; GFX11-NEXT: s_bitset1_b32 s5, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s5, s5, s47 +; GFX11-NEXT: s_and_b32 s47, s4, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s5, s5, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s47, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s47, 0x10010 +; GFX11-NEXT: s_add_i32 s56, s56, s47 +; GFX11-NEXT: s_bitset1_b32 s47, 22 +; GFX11-NEXT: s_addk_i32 s56, 0x7fff +; GFX11-NEXT: s_and_b32 s57, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s47, s47, s56 +; GFX11-NEXT: s_lshl_b32 s4, s4, 16 +; GFX11-NEXT: s_lshr_b32 s60, s47, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s4 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s4, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s4, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s56, s4 +; GFX11-NEXT: s_bitset1_b32 s4, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s4, s4, s47 +; GFX11-NEXT: s_and_b32 s47, s1, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s4, s4, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s47, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s47, 0x10010 +; GFX11-NEXT: s_add_i32 s56, s56, s47 +; GFX11-NEXT: s_bitset1_b32 s47, 22 +; GFX11-NEXT: s_addk_i32 s56, 0x7fff +; GFX11-NEXT: s_and_b32 s57, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s47, s47, s56 +; GFX11-NEXT: s_lshl_b32 s1, s1, 16 +; GFX11-NEXT: s_lshr_b32 s93, s47, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s1 +; GFX11-NEXT: v_writelane_b32 v20, s93, 14 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s1, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s1, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s56, s1 +; GFX11-NEXT: s_bitset1_b32 s1, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s1, s1, s47 +; GFX11-NEXT: s_and_b32 s47, s0, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s1, s1, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_pack_ll_b32_b16 s95, s1, s93 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s47, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s47, 0x10010 +; GFX11-NEXT: s_add_i32 s56, s56, s47 +; GFX11-NEXT: s_bitset1_b32 s47, 22 +; GFX11-NEXT: s_addk_i32 s56, 0x7fff +; GFX11-NEXT: s_and_b32 s57, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s47, s47, s56 +; GFX11-NEXT: s_lshl_b32 s0, s0, 16 +; GFX11-NEXT: s_lshr_b32 s61, s47, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s0, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s0, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s56, s0 +; GFX11-NEXT: s_bitset1_b32 s0, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s0, s0, s47 +; GFX11-NEXT: s_and_b32 s47, s3, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s0, s0, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_pack_ll_b32_b16 s94, s0, s61 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s47, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s47, 0x10010 +; GFX11-NEXT: s_add_i32 s56, s56, s47 +; GFX11-NEXT: s_bitset1_b32 s47, 22 +; GFX11-NEXT: s_addk_i32 s56, 0x7fff +; GFX11-NEXT: s_and_b32 s57, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s47, s47, s56 +; GFX11-NEXT: s_lshl_b32 s3, s3, 16 +; GFX11-NEXT: s_lshr_b32 s34, s47, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s3 +; GFX11-NEXT: v_writelane_b32 v20, s34, 15 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s3, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s3, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s56, s3 +; GFX11-NEXT: s_bitset1_b32 s3, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s3, s3, s47 +; GFX11-NEXT: s_and_b32 s47, s2, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s3, s3, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_pack_ll_b32_b16 s93, s3, s34 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s47, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s47, 0x10010 +; GFX11-NEXT: s_add_i32 s56, s56, s47 +; GFX11-NEXT: s_bitset1_b32 s47, 22 +; GFX11-NEXT: s_addk_i32 s56, 0x7fff +; GFX11-NEXT: s_and_b32 s57, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s47, s47, s56 +; GFX11-NEXT: s_lshl_b32 s2, s2, 16 +; GFX11-NEXT: s_lshr_b32 s62, s47, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s2, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s2, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s56, s2 +; GFX11-NEXT: s_bitset1_b32 s2, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s2, s2, s47 +; GFX11-NEXT: s_and_b32 s47, s17, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s2, s2, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s47, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s47, 0x10010 +; GFX11-NEXT: s_add_i32 s56, s56, s47 +; GFX11-NEXT: s_bitset1_b32 s47, 22 +; GFX11-NEXT: s_addk_i32 s56, 0x7fff +; GFX11-NEXT: s_and_b32 s57, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s47, s47, s56 +; GFX11-NEXT: s_lshl_b32 s17, s17, 16 +; GFX11-NEXT: s_lshr_b32 s35, s47, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s17 +; GFX11-NEXT: v_writelane_b32 v20, s35, 16 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s17, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s17, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s56, s17 +; GFX11-NEXT: s_bitset1_b32 s17, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s17, s17, s47 +; GFX11-NEXT: s_and_b32 s47, s16, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s17, s17, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_pack_ll_b32_b16 s79, s17, s35 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s47, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s47, 0x10010 +; GFX11-NEXT: s_add_i32 s56, s56, s47 +; GFX11-NEXT: s_bitset1_b32 s47, 22 +; GFX11-NEXT: s_addk_i32 s56, 0x7fff +; GFX11-NEXT: s_and_b32 s57, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s47, s47, s56 +; GFX11-NEXT: s_lshl_b32 s16, s16, 16 +; GFX11-NEXT: s_lshr_b32 s63, s47, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s16 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s16, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s16, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s56, s16 +; GFX11-NEXT: s_bitset1_b32 s16, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s16, s16, s47 +; GFX11-NEXT: s_and_b32 s47, s19, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s16, s16, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s47, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s47, 0x10010 +; GFX11-NEXT: s_add_i32 s56, s56, s47 +; GFX11-NEXT: s_bitset1_b32 s47, 22 +; GFX11-NEXT: s_addk_i32 s56, 0x7fff +; GFX11-NEXT: s_and_b32 s57, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s47, s47, s56 +; GFX11-NEXT: s_lshl_b32 s19, s19, 16 +; GFX11-NEXT: s_lshr_b32 s36, s47, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s19 +; GFX11-NEXT: v_writelane_b32 v20, s36, 17 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s19, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s19, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s56, s19 +; GFX11-NEXT: s_bitset1_b32 s19, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s19, s19, s47 +; GFX11-NEXT: s_and_b32 s47, s18, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s19, s19, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s47, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s47, 0x10010 +; GFX11-NEXT: s_add_i32 s56, s56, s47 +; GFX11-NEXT: s_bitset1_b32 s47, 22 +; GFX11-NEXT: s_addk_i32 s56, 0x7fff +; GFX11-NEXT: s_and_b32 s57, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s47, s47, s56 +; GFX11-NEXT: s_lshl_b32 s18, s18, 16 +; GFX11-NEXT: s_lshr_b32 s74, s47, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s18 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s18, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s18, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s56, s18 +; GFX11-NEXT: s_bitset1_b32 s18, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s18, s18, s47 +; GFX11-NEXT: s_and_b32 s47, s21, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s18, s18, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_pack_ll_b32_b16 s74, s18, s74 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s47, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s47, 0x10010 +; GFX11-NEXT: s_add_i32 s56, s56, s47 +; GFX11-NEXT: s_bitset1_b32 s47, 22 +; GFX11-NEXT: s_addk_i32 s56, 0x7fff +; GFX11-NEXT: s_and_b32 s57, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s47, s47, s56 +; GFX11-NEXT: s_lshl_b32 s21, s21, 16 +; GFX11-NEXT: s_lshr_b32 s37, s47, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s21 +; GFX11-NEXT: v_writelane_b32 v20, s37, 18 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s21, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s21, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s56, s21 +; GFX11-NEXT: s_bitset1_b32 s21, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s21, s21, s47 +; GFX11-NEXT: s_and_b32 s47, s20, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s21, s21, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s47, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s47, 0x10010 +; GFX11-NEXT: s_add_i32 s56, s56, s47 +; GFX11-NEXT: s_bitset1_b32 s47, 22 +; GFX11-NEXT: s_addk_i32 s56, 0x7fff +; GFX11-NEXT: s_and_b32 s57, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s47, s47, s56 +; GFX11-NEXT: s_lshl_b32 s20, s20, 16 +; GFX11-NEXT: s_lshr_b32 s90, s47, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s20 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s20, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s20, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s56, s20 +; GFX11-NEXT: s_bitset1_b32 s20, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s20, s20, s47 +; GFX11-NEXT: s_and_b32 s47, s23, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s20, s20, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s47, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s47, 0x10010 +; GFX11-NEXT: s_add_i32 s56, s56, s47 +; GFX11-NEXT: s_bitset1_b32 s47, 22 +; GFX11-NEXT: s_addk_i32 s56, 0x7fff +; GFX11-NEXT: s_and_b32 s57, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s47, s47, s56 +; GFX11-NEXT: s_lshl_b32 s23, s23, 16 +; GFX11-NEXT: s_lshr_b32 s38, s47, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s23 +; GFX11-NEXT: v_writelane_b32 v20, s38, 19 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s23, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s23, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s56, s23 +; GFX11-NEXT: s_bitset1_b32 s23, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s23, s23, s47 +; GFX11-NEXT: s_and_b32 s47, s22, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s23, s23, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_pack_ll_b32_b16 s35, s23, s38 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s47, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s47, 0x10010 +; GFX11-NEXT: s_add_i32 s56, s56, s47 +; GFX11-NEXT: s_bitset1_b32 s47, 22 +; GFX11-NEXT: s_addk_i32 s56, 0x7fff +; GFX11-NEXT: s_and_b32 s57, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s47, s47, s56 +; GFX11-NEXT: s_lshl_b32 s22, s22, 16 +; GFX11-NEXT: s_lshr_b32 s91, s47, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s22 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s22, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s22, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s56, s22 +; GFX11-NEXT: s_bitset1_b32 s22, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s22, s22, s47 +; GFX11-NEXT: s_and_b32 s47, s25, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s22, s22, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_pack_ll_b32_b16 s34, s22, s91 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s47, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s47, 0x10010 +; GFX11-NEXT: s_add_i32 s56, s56, s47 +; GFX11-NEXT: s_bitset1_b32 s47, 22 +; GFX11-NEXT: s_addk_i32 s56, 0x7fff +; GFX11-NEXT: s_and_b32 s57, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s47, s47, s56 +; GFX11-NEXT: s_lshl_b32 s25, s25, 16 +; GFX11-NEXT: s_lshr_b32 s39, s47, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s25 +; GFX11-NEXT: v_writelane_b32 v20, s39, 20 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s25, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s25, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s56, s25 +; GFX11-NEXT: s_bitset1_b32 s25, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s25, s25, s47 +; GFX11-NEXT: s_and_b32 s47, s24, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s25, s25, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s47, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s47, 0x10010 +; GFX11-NEXT: s_add_i32 s56, s56, s47 +; GFX11-NEXT: s_bitset1_b32 s47, 22 +; GFX11-NEXT: s_addk_i32 s56, 0x7fff +; GFX11-NEXT: s_and_b32 s57, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s47, s47, s56 +; GFX11-NEXT: s_lshl_b32 s24, s24, 16 +; GFX11-NEXT: s_lshr_b32 vcc_hi, s47, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s24 +; GFX11-NEXT: s_pack_ll_b32_b16 s57, s11, s75 +; GFX11-NEXT: s_pack_ll_b32_b16 s75, s19, s36 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s24, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s56, s24, 0x10010 +; GFX11-NEXT: s_add_i32 s47, s56, s24 +; GFX11-NEXT: s_bitset1_b32 s24, 22 +; GFX11-NEXT: s_addk_i32 s47, 0x7fff +; GFX11-NEXT: s_and_b32 s56, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s24, s24, s47 +; GFX11-NEXT: s_and_b32 s47, s27, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s24, s24, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s47 +; GFX11-NEXT: s_pack_ll_b32_b16 s56, s10, s46 +; GFX11-NEXT: s_pack_ll_b32_b16 s46, s8, s58 +; GFX11-NEXT: s_pack_ll_b32_b16 s47, s9, s78 +; GFX11-NEXT: s_pack_ll_b32_b16 s78, s16, s63 +; GFX11-NEXT: v_readfirstlane_b32 s42, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_pack_ll_b32_b16 s63, s21, s37 +; GFX11-NEXT: s_pack_ll_b32_b16 s37, s25, s39 +; GFX11-NEXT: s_pack_ll_b32_b16 s36, s24, vcc_hi +; GFX11-NEXT: s_bfe_u32 s43, s42, 0x10010 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_add_i32 s43, s43, s42 +; GFX11-NEXT: s_bitset1_b32 s42, 22 +; GFX11-NEXT: s_addk_i32 s43, 0x7fff +; GFX11-NEXT: s_and_b32 s44, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s42, s42, s43 +; GFX11-NEXT: s_lshl_b32 s27, s27, 16 +; GFX11-NEXT: s_lshr_b32 s71, s42, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s27 +; GFX11-NEXT: s_pack_ll_b32_b16 s44, s6, s59 +; GFX11-NEXT: s_pack_ll_b32_b16 s43, s5, s92 +; GFX11-NEXT: s_pack_ll_b32_b16 s92, s2, s62 +; GFX11-NEXT: s_pack_ll_b32_b16 s62, s20, s90 +; GFX11-NEXT: v_readfirstlane_b32 s27, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s58, s27, 0x10010 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_add_i32 s42, s58, s27 +; GFX11-NEXT: s_bitset1_b32 s27, 22 +; GFX11-NEXT: s_addk_i32 s42, 0x7fff +; GFX11-NEXT: s_and_b32 s58, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s27, s27, s42 +; GFX11-NEXT: s_and_b32 s58, s26, 0xffff0000 +; GFX11-NEXT: s_lshr_b32 s27, s27, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s58 +; GFX11-NEXT: s_pack_ll_b32_b16 s42, s4, s60 +; GFX11-NEXT: s_pack_ll_b32_b16 s91, s27, s71 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s58, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s59, s58, 0x10010 +; GFX11-NEXT: s_add_i32 s59, s59, s58 +; GFX11-NEXT: s_bitset1_b32 s58, 22 +; GFX11-NEXT: s_addk_i32 s59, 0x7fff +; GFX11-NEXT: s_and_b32 s60, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s58, s58, s59 +; GFX11-NEXT: s_lshl_b32 s26, s26, 16 +; GFX11-NEXT: s_lshr_b32 s90, s58, 16 +; GFX11-NEXT: v_add_f32_e64 v1, 0x40c00000, s26 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: v_readfirstlane_b32 s26, v1 +; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1 +; GFX11-NEXT: s_bfe_u32 s59, s26, 0x10010 +; GFX11-NEXT: s_add_i32 s58, s59, s26 +; GFX11-NEXT: s_bitset1_b32 s26, 22 +; GFX11-NEXT: s_addk_i32 s58, 0x7fff +; GFX11-NEXT: s_and_b32 s59, vcc_lo, exec_lo +; GFX11-NEXT: s_cselect_b32 s26, s26, s58 +; GFX11-NEXT: s_lshr_b64 s[58:59], s[36:37], 24 +; GFX11-NEXT: s_lshr_b32 s50, s62, 16 +; GFX11-NEXT: v_writelane_b32 v20, s58, 2 +; GFX11-NEXT: s_lshr_b32 s81, s62, 8 +; GFX11-NEXT: s_lshr_b32 s85, s75, 24 +; GFX11-NEXT: s_lshr_b32 s60, s75, 8 +; GFX11-NEXT: s_lshr_b32 s61, s74, 16 +; GFX11-NEXT: v_writelane_b32 v20, s59, 3 +; GFX11-NEXT: s_lshr_b64 s[58:59], s[34:35], 24 +; GFX11-NEXT: s_lshr_b32 s96, s74, 8 +; GFX11-NEXT: s_lshr_b64 s[74:75], s[74:75], 24 +; GFX11-NEXT: s_lshr_b32 s75, s42, 8 +; GFX11-NEXT: v_writelane_b32 v20, s58, 0 +; GFX11-NEXT: s_lshr_b32 s26, s26, 16 +; GFX11-NEXT: s_lshr_b32 s65, s73, 24 +; GFX11-NEXT: s_pack_ll_b32_b16 s90, s26, s90 +; GFX11-NEXT: s_lshr_b32 s82, s73, 8 +; GFX11-NEXT: v_writelane_b32 v20, s59, 1 +; GFX11-NEXT: s_lshr_b32 s58, s63, 24 +; GFX11-NEXT: s_lshr_b32 s59, s63, 8 +; GFX11-NEXT: s_lshr_b64 s[62:63], s[62:63], 24 +; GFX11-NEXT: s_lshr_b32 s63, s93, 24 +; GFX11-NEXT: s_lshr_b32 s84, s72, 16 +; GFX11-NEXT: v_writelane_b32 v20, s63, 21 +; GFX11-NEXT: s_lshr_b32 s63, s93, 8 +; GFX11-NEXT: s_lshr_b32 s51, s72, 8 +; GFX11-NEXT: s_lshr_b64 s[72:73], s[72:73], 24 +; GFX11-NEXT: s_lshr_b32 s86, s77, 24 +; GFX11-NEXT: v_writelane_b32 v20, s63, 22 +; GFX11-NEXT: s_lshr_b32 s63, s92, 16 +; GFX11-NEXT: s_lshr_b32 s87, s77, 8 +; GFX11-NEXT: s_lshr_b32 s52, s76, 16 +; GFX11-NEXT: s_lshr_b32 s100, s76, 8 +; GFX11-NEXT: v_writelane_b32 v20, s63, 23 +; GFX11-NEXT: s_lshr_b32 s63, s92, 8 +; GFX11-NEXT: s_lshr_b64 s[76:77], s[76:77], 24 +; GFX11-NEXT: s_lshr_b32 s101, s89, 8 +; GFX11-NEXT: s_lshr_b32 s98, s79, 24 +; GFX11-NEXT: v_writelane_b32 v20, s63, 24 +; GFX11-NEXT: s_lshr_b32 s63, s95, 24 +; GFX11-NEXT: s_lshr_b32 s99, s79, 8 +; GFX11-NEXT: s_lshr_b32 s53, s78, 16 +; GFX11-NEXT: s_lshr_b32 s97, s78, 8 +; GFX11-NEXT: v_writelane_b32 v20, s63, 25 +; GFX11-NEXT: s_lshr_b32 s63, s95, 8 +; GFX11-NEXT: s_lshr_b64 s[78:79], s[78:79], 24 +; GFX11-NEXT: s_lshr_b64 s[92:93], s[92:93], 24 +; GFX11-NEXT: s_lshr_b32 s102, s94, 16 +; GFX11-NEXT: v_writelane_b32 v20, s63, 26 +; GFX11-NEXT: s_lshr_b32 s63, s43, 24 +; GFX11-NEXT: s_lshr_b32 s103, s94, 8 +; GFX11-NEXT: s_lshr_b64 s[94:95], s[94:95], 24 +; GFX11-NEXT: s_lshr_b32 s73, s91, 24 +; GFX11-NEXT: v_writelane_b32 v20, s63, 27 +; GFX11-NEXT: s_lshr_b32 s63, s43, 8 +; GFX11-NEXT: s_lshr_b32 s77, s91, 8 +; GFX11-NEXT: s_lshr_b32 s83, s90, 8 +; GFX11-NEXT: s_lshr_b32 s66, s37, 24 +; GFX11-NEXT: v_writelane_b32 v20, s63, 28 +; GFX11-NEXT: s_lshr_b32 s63, s42, 16 +; GFX11-NEXT: s_lshr_b64 s[42:43], s[42:43], 24 +; GFX11-NEXT: s_lshr_b32 s67, s37, 8 +; GFX11-NEXT: s_lshr_b32 s68, s36, 16 +; GFX11-NEXT: v_writelane_b32 v20, s42, 6 +; GFX11-NEXT: s_lshr_b32 s49, s36, 8 +; GFX11-NEXT: s_lshr_b32 s69, s35, 24 +; GFX11-NEXT: s_lshr_b32 s70, s35, 8 +; GFX11-NEXT: s_lshr_b32 s64, s34, 16 +; GFX11-NEXT: v_writelane_b32 v20, s43, 7 +; GFX11-NEXT: s_lshr_b64 s[42:43], s[44:45], 24 +; GFX11-NEXT: s_lshr_b32 s80, s34, 8 +; GFX11-NEXT: s_lshr_b32 s79, s45, 24 +; GFX11-NEXT: s_lshr_b32 s93, s45, 8 +; GFX11-NEXT: v_writelane_b32 v20, s42, 4 +; GFX11-NEXT: s_lshr_b32 s95, s44, 16 +; GFX11-NEXT: s_lshr_b32 vcc_hi, s44, 8 +; GFX11-NEXT: s_lshr_b32 s34, s47, 24 +; GFX11-NEXT: s_lshr_b32 s55, s47, 8 +; GFX11-NEXT: v_writelane_b32 v20, s43, 5 +; GFX11-NEXT: s_lshr_b32 s43, s88, 16 +; GFX11-NEXT: s_lshr_b32 s42, s89, 24 +; GFX11-NEXT: s_lshr_b32 s35, s46, 16 +; GFX11-NEXT: s_lshr_b32 s36, s46, 8 +; GFX11-NEXT: v_writelane_b32 v20, s43, 29 +; GFX11-NEXT: s_lshr_b32 s43, s88, 8 +; GFX11-NEXT: s_lshr_b64 s[88:89], s[88:89], 24 +; GFX11-NEXT: s_lshr_b32 s89, s90, 16 +; GFX11-NEXT: s_lshr_b64 s[90:91], s[90:91], 24 +; GFX11-NEXT: v_writelane_b32 v20, s43, 30 +; GFX11-NEXT: s_lshr_b64 s[46:47], s[46:47], 24 +; GFX11-NEXT: s_lshr_b32 s37, s57, 24 +; GFX11-NEXT: s_lshr_b32 s38, s57, 8 +; GFX11-NEXT: s_lshr_b32 s39, s56, 16 +; GFX11-NEXT: s_lshr_b32 s48, s56, 8 +; GFX11-NEXT: s_lshr_b64 s[56:57], s[56:57], 24 +; GFX11-NEXT: s_lshr_b32 s91, s31, 24 +; GFX11-NEXT: s_lshr_b32 s43, s31, 8 +; GFX11-NEXT: s_lshr_b32 s44, s30, 16 +; GFX11-NEXT: s_lshr_b32 s45, s30, 8 +; GFX11-NEXT: s_lshr_b64 s[30:31], s[30:31], 24 +; GFX11-NEXT: v_writelane_b32 v20, s43, 31 +; GFX11-NEXT: .LBB91_5: ; %end +; GFX11-NEXT: s_lshl_b32 s47, s103, 8 +; GFX11-NEXT: s_and_b32 s0, s0, 0xff +; GFX11-NEXT: s_and_b32 s57, s102, 0xff +; GFX11-NEXT: s_or_b32 s0, s0, s47 +; GFX11-NEXT: s_lshl_b32 s47, s94, 8 +; GFX11-NEXT: v_readlane_b32 s43, v20, 26 +; GFX11-NEXT: s_or_b32 s47, s57, s47 +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_lshl_b32 s47, s47, 16 +; GFX11-NEXT: s_and_b32 s1, s1, 0xff +; GFX11-NEXT: s_or_b32 s0, s0, s47 +; GFX11-NEXT: s_lshl_b32 s47, s43, 8 +; GFX11-NEXT: v_readlane_b32 s43, v20, 25 +; GFX11-NEXT: s_or_b32 s1, s1, s47 +; GFX11-NEXT: v_readlane_b32 s47, v20, 14 +; GFX11-NEXT: s_and_b32 s1, s1, 0xffff +; GFX11-NEXT: s_and_b32 s2, s2, 0xff +; GFX11-NEXT: s_lshl_b32 s57, s43, 8 +; GFX11-NEXT: v_readlane_b32 s43, v20, 24 +; GFX11-NEXT: s_and_b32 s47, s47, 0xff +; GFX11-NEXT: s_and_b32 s3, s3, 0xff +; GFX11-NEXT: s_or_b32 s47, s47, s57 +; GFX11-NEXT: v_readlane_b32 s103, v19, 7 +; GFX11-NEXT: s_lshl_b32 s47, s47, 16 +; GFX11-NEXT: v_readlane_b32 s102, v19, 6 +; GFX11-NEXT: s_or_b32 s1, s1, s47 +; GFX11-NEXT: s_lshl_b32 s47, s43, 8 +; GFX11-NEXT: v_readlane_b32 s43, v20, 23 +; GFX11-NEXT: s_or_b32 s2, s2, s47 +; GFX11-NEXT: s_lshl_b32 s47, s92, 8 +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1 +; GFX11-NEXT: s_and_b32 s57, s43, 0xff +; GFX11-NEXT: v_readlane_b32 s43, v20, 22 +; GFX11-NEXT: s_or_b32 s47, s57, s47 +; GFX11-NEXT: s_lshl_b32 s0, s97, 8 +; GFX11-NEXT: s_lshl_b32 s47, s47, 16 +; GFX11-NEXT: s_and_b32 s1, s16, 0xff +; GFX11-NEXT: s_or_b32 s2, s2, s47 +; GFX11-NEXT: s_lshl_b32 s47, s43, 8 +; GFX11-NEXT: v_readlane_b32 s43, v20, 21 +; GFX11-NEXT: s_or_b32 s3, s3, s47 +; GFX11-NEXT: v_readlane_b32 s47, v20, 15 +; GFX11-NEXT: s_and_b32 s3, s3, 0xffff +; GFX11-NEXT: s_or_b32 s0, s1, s0 +; GFX11-NEXT: s_lshl_b32 s57, s43, 8 +; GFX11-NEXT: s_lshl_b32 s1, s78, 8 +; GFX11-NEXT: s_and_b32 s47, s47, 0xff +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_or_b32 s47, s47, s57 +; GFX11-NEXT: s_and_b32 s16, s61, 0xff +; GFX11-NEXT: s_lshl_b32 s47, s47, 16 +; GFX11-NEXT: v_readlane_b32 s97, v19, 1 +; GFX11-NEXT: s_or_b32 s3, s3, s47 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3 +; GFX11-NEXT: s_and_b32 s2, s53, 0xff +; GFX11-NEXT: s_lshl_b32 s3, s98, 8 +; GFX11-NEXT: s_or_b32 s1, s2, s1 +; GFX11-NEXT: s_lshl_b32 s2, s99, 8 +; GFX11-NEXT: s_lshl_b32 s1, s1, 16 +; GFX11-NEXT: v_readlane_b32 s99, v19, 3 +; GFX11-NEXT: s_or_b32 s0, s0, s1 +; GFX11-NEXT: s_and_b32 s1, s17, 0xff +; GFX11-NEXT: s_lshl_b32 s17, s85, 8 +; GFX11-NEXT: s_or_b32 s1, s1, s2 +; GFX11-NEXT: v_readlane_b32 s2, v20, 16 +; GFX11-NEXT: s_and_b32 s1, s1, 0xffff +; GFX11-NEXT: v_readlane_b32 s98, v19, 2 +; GFX11-NEXT: v_readlane_b32 s85, v18, 29 +; GFX11-NEXT: v_readlane_b32 s53, v18, 13 +; GFX11-NEXT: s_and_b32 s2, s2, 0xff +; GFX11-NEXT: v_readlane_b32 s31, v18, 1 +; GFX11-NEXT: s_or_b32 s2, s2, s3 +; GFX11-NEXT: s_and_b32 s3, s18, 0xff +; GFX11-NEXT: s_lshl_b32 s2, s2, 16 +; GFX11-NEXT: s_lshl_b32 s18, s69, 8 +; GFX11-NEXT: s_or_b32 s1, s1, s2 +; GFX11-NEXT: s_lshl_b32 s2, s96, 8 +; GFX11-NEXT: v_dual_mov_b32 v5, s0 :: v_dual_mov_b32 v6, s1 +; GFX11-NEXT: s_or_b32 s2, s3, s2 +; GFX11-NEXT: s_lshl_b32 s3, s74, 8 +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_or_b32 s3, s16, s3 +; GFX11-NEXT: s_lshl_b32 s16, s60, 8 +; GFX11-NEXT: s_lshl_b32 s3, s3, 16 +; GFX11-NEXT: s_lshl_b32 s0, s81, 8 +; GFX11-NEXT: s_or_b32 s2, s2, s3 +; GFX11-NEXT: s_and_b32 s3, s19, 0xff +; GFX11-NEXT: s_and_b32 s1, s20, 0xff +; GFX11-NEXT: s_or_b32 s3, s3, s16 +; GFX11-NEXT: v_readlane_b32 s16, v20, 17 +; GFX11-NEXT: s_and_b32 s3, s3, 0xffff +; GFX11-NEXT: s_or_b32 s0, s1, s0 +; GFX11-NEXT: s_lshl_b32 s1, s62, 8 +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_and_b32 s16, s16, 0xff +; GFX11-NEXT: s_lshl_b32 s19, s73, 8 +; GFX11-NEXT: s_or_b32 s16, s16, s17 +; GFX11-NEXT: v_readlane_b32 s96, v19, 0 +; GFX11-NEXT: s_lshl_b32 s16, s16, 16 +; GFX11-NEXT: v_readlane_b32 s81, v18, 25 +; GFX11-NEXT: s_or_b32 s3, s3, s16 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v8, s3 +; GFX11-NEXT: s_and_b32 s2, s50, 0xff +; GFX11-NEXT: s_lshl_b32 s3, s58, 8 +; GFX11-NEXT: s_or_b32 s1, s2, s1 +; GFX11-NEXT: s_lshl_b32 s2, s59, 8 +; GFX11-NEXT: s_lshl_b32 s1, s1, 16 +; GFX11-NEXT: v_readlane_b32 s16, v20, 0 +; GFX11-NEXT: s_or_b32 s0, s0, s1 +; GFX11-NEXT: s_and_b32 s1, s21, 0xff +; GFX11-NEXT: v_readlane_b32 s17, v20, 1 +; GFX11-NEXT: s_or_b32 s1, s1, s2 +; GFX11-NEXT: v_readlane_b32 s2, v20, 18 +; GFX11-NEXT: s_and_b32 s1, s1, 0xffff +; GFX11-NEXT: s_lshl_b32 s17, s70, 8 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off +; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:16 +; GFX11-NEXT: v_readlane_b32 s70, v18, 22 +; GFX11-NEXT: s_and_b32 s2, s2, 0xff +; GFX11-NEXT: v_readlane_b32 s69, v18, 21 +; GFX11-NEXT: s_or_b32 s2, s2, s3 +; GFX11-NEXT: s_and_b32 s3, s22, 0xff +; GFX11-NEXT: s_lshl_b32 s2, s2, 16 +; GFX11-NEXT: v_readlane_b32 s50, v18, 10 +; GFX11-NEXT: s_or_b32 s1, s1, s2 +; GFX11-NEXT: s_lshl_b32 s2, s80, 8 +; GFX11-NEXT: v_dual_mov_b32 v9, s0 :: v_dual_mov_b32 v10, s1 +; GFX11-NEXT: s_or_b32 s2, s3, s2 +; GFX11-NEXT: s_lshl_b32 s3, s16, 8 +; GFX11-NEXT: s_and_b32 s16, s64, 0xff +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_or_b32 s3, s16, s3 +; GFX11-NEXT: s_and_b32 s16, s23, 0xff +; GFX11-NEXT: s_lshl_b32 s3, s3, 16 +; GFX11-NEXT: s_or_b32 s16, s16, s17 +; GFX11-NEXT: v_readlane_b32 s17, v20, 19 +; GFX11-NEXT: s_or_b32 s2, s2, s3 +; GFX11-NEXT: s_and_b32 s3, s16, 0xffff +; GFX11-NEXT: s_and_b32 s0, s24, 0xff +; GFX11-NEXT: s_lshl_b32 s1, s49, 8 +; GFX11-NEXT: s_and_b32 s17, s17, 0xff +; GFX11-NEXT: s_or_b32 s0, s0, s1 +; GFX11-NEXT: s_or_b32 s17, s17, s18 +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_lshl_b32 s16, s17, 16 +; GFX11-NEXT: s_and_b32 s18, s71, 0xff +; GFX11-NEXT: s_or_b32 s3, s3, s16 +; GFX11-NEXT: v_readlane_b32 s16, v20, 2 +; GFX11-NEXT: v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v12, s3 +; GFX11-NEXT: s_and_b32 s2, s68, 0xff +; GFX11-NEXT: v_readlane_b32 s17, v20, 3 +; GFX11-NEXT: s_lshl_b32 s3, s16, 8 +; GFX11-NEXT: v_readlane_b32 s16, v20, 20 +; GFX11-NEXT: s_or_b32 s1, s2, s3 +; GFX11-NEXT: s_and_b32 s2, s25, 0xff +; GFX11-NEXT: s_lshl_b32 s3, s67, 8 +; GFX11-NEXT: s_lshl_b32 s17, s66, 8 +; GFX11-NEXT: s_and_b32 s16, s16, 0xff +; GFX11-NEXT: s_or_b32 s2, s2, s3 +; GFX11-NEXT: s_or_b32 s3, s16, s17 +; GFX11-NEXT: s_lshl_b32 s1, s1, 16 +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_lshl_b32 s3, s3, 16 +; GFX11-NEXT: s_or_b32 s0, s0, s1 +; GFX11-NEXT: s_or_b32 s1, s2, s3 +; GFX11-NEXT: s_and_b32 s2, s26, 0xff +; GFX11-NEXT: s_lshl_b32 s3, s83, 8 +; GFX11-NEXT: s_and_b32 s16, s89, 0xff +; GFX11-NEXT: s_lshl_b32 s17, s90, 8 +; GFX11-NEXT: s_or_b32 s2, s2, s3 +; GFX11-NEXT: s_or_b32 s3, s16, s17 +; GFX11-NEXT: s_and_b32 s16, s27, 0xff +; GFX11-NEXT: s_lshl_b32 s17, s77, 8 +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_or_b32 s16, s16, s17 +; GFX11-NEXT: s_or_b32 s17, s18, s19 +; GFX11-NEXT: s_lshl_b32 s3, s3, 16 +; GFX11-NEXT: s_and_b32 s16, s16, 0xffff +; GFX11-NEXT: s_lshl_b32 s17, s17, 16 +; GFX11-NEXT: s_or_b32 s2, s2, s3 +; GFX11-NEXT: s_or_b32 s3, s16, s17 +; GFX11-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1 +; GFX11-NEXT: v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3 +; GFX11-NEXT: s_and_b32 s0, s40, 0xff +; GFX11-NEXT: s_lshl_b32 s1, s45, 8 +; GFX11-NEXT: s_and_b32 s2, s44, 0xff +; GFX11-NEXT: s_lshl_b32 s3, s30, 8 +; GFX11-NEXT: s_or_b32 s0, s0, s1 +; GFX11-NEXT: s_or_b32 s1, s2, s3 +; GFX11-NEXT: v_readlane_b32 s3, v20, 31 +; GFX11-NEXT: s_and_b32 s2, s41, 0xff +; GFX11-NEXT: s_and_b32 s16, s104, 0xff +; GFX11-NEXT: s_lshl_b32 s17, s91, 8 +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_lshl_b32 s3, s3, 8 +; GFX11-NEXT: s_lshl_b32 s1, s1, 16 +; GFX11-NEXT: s_or_b32 s2, s2, s3 +; GFX11-NEXT: s_or_b32 s3, s16, s17 +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_lshl_b32 s3, s3, 16 +; GFX11-NEXT: s_or_b32 s0, s0, s1 +; GFX11-NEXT: s_or_b32 s1, s2, s3 +; GFX11-NEXT: v_readlane_b32 s3, v20, 30 +; GFX11-NEXT: v_readlane_b32 s16, v20, 29 +; GFX11-NEXT: s_and_b32 s2, s28, 0xff +; GFX11-NEXT: s_lshl_b32 s17, s88, 8 +; GFX11-NEXT: s_and_b32 s18, s54, 0xff +; GFX11-NEXT: s_lshl_b32 s3, s3, 8 +; GFX11-NEXT: s_and_b32 s16, s16, 0xff +; GFX11-NEXT: s_or_b32 s2, s2, s3 +; GFX11-NEXT: s_or_b32 s3, s16, s17 +; GFX11-NEXT: s_and_b32 s16, s29, 0xff +; GFX11-NEXT: s_lshl_b32 s17, s101, 8 +; GFX11-NEXT: s_lshl_b32 s19, s42, 8 +; GFX11-NEXT: s_or_b32 s16, s16, s17 +; GFX11-NEXT: s_or_b32 s17, s18, s19 +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_lshl_b32 s3, s3, 16 +; GFX11-NEXT: s_and_b32 s16, s16, 0xffff +; GFX11-NEXT: s_lshl_b32 s17, s17, 16 +; GFX11-NEXT: v_dual_mov_b32 v5, s0 :: v_dual_mov_b32 v6, s1 +; GFX11-NEXT: s_and_b32 s0, s14, 0xff +; GFX11-NEXT: v_readlane_b32 s14, v20, 8 +; GFX11-NEXT: s_or_b32 s2, s2, s3 +; GFX11-NEXT: s_or_b32 s3, s16, s17 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v8, s3 +; GFX11-NEXT: s_lshl_b32 s1, s100, 8 +; GFX11-NEXT: s_and_b32 s2, s52, 0xff +; GFX11-NEXT: s_lshl_b32 s3, s76, 8 +; GFX11-NEXT: s_or_b32 s0, s0, s1 +; GFX11-NEXT: s_or_b32 s1, s2, s3 +; GFX11-NEXT: s_and_b32 s2, s15, 0xff +; GFX11-NEXT: s_lshl_b32 s3, s87, 8 +; GFX11-NEXT: s_and_b32 s14, s14, 0xff +; GFX11-NEXT: s_lshl_b32 s15, s86, 8 +; GFX11-NEXT: s_or_b32 s2, s2, s3 +; GFX11-NEXT: s_or_b32 s3, s14, s15 +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_lshl_b32 s1, s1, 16 +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_lshl_b32 s3, s3, 16 +; GFX11-NEXT: s_or_b32 s0, s0, s1 +; GFX11-NEXT: s_or_b32 s1, s2, s3 +; GFX11-NEXT: s_and_b32 s2, s12, 0xff +; GFX11-NEXT: s_lshl_b32 s3, s51, 8 +; GFX11-NEXT: s_and_b32 s12, s84, 0xff +; GFX11-NEXT: s_lshl_b32 s14, s72, 8 +; GFX11-NEXT: s_or_b32 s2, s2, s3 +; GFX11-NEXT: s_or_b32 s3, s12, s14 +; GFX11-NEXT: v_readlane_b32 s14, v20, 9 +; GFX11-NEXT: s_and_b32 s12, s13, 0xff +; GFX11-NEXT: s_lshl_b32 s13, s82, 8 +; GFX11-NEXT: s_lshl_b32 s15, s65, 8 +; GFX11-NEXT: s_or_b32 s12, s12, s13 +; GFX11-NEXT: s_and_b32 s14, s14, 0xff +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_or_b32 s13, s14, s15 +; GFX11-NEXT: s_lshl_b32 s3, s3, 16 +; GFX11-NEXT: s_and_b32 s12, s12, 0xffff +; GFX11-NEXT: s_lshl_b32 s13, s13, 16 +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: scratch_store_b128 v0, v[9:12], off offset:32 +; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:48 +; GFX11-NEXT: v_dual_mov_b32 v9, s0 :: v_dual_mov_b32 v10, s1 +; GFX11-NEXT: s_and_b32 s0, s10, 0xff +; GFX11-NEXT: v_readlane_b32 s10, v20, 10 +; GFX11-NEXT: s_or_b32 s2, s2, s3 +; GFX11-NEXT: s_or_b32 s3, s12, s13 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_dual_mov_b32 v11, s2 :: v_dual_mov_b32 v12, s3 +; GFX11-NEXT: s_lshl_b32 s1, s48, 8 +; GFX11-NEXT: s_and_b32 s2, s39, 0xff +; GFX11-NEXT: s_lshl_b32 s3, s56, 8 +; GFX11-NEXT: s_or_b32 s0, s0, s1 +; GFX11-NEXT: s_or_b32 s1, s2, s3 +; GFX11-NEXT: s_and_b32 s2, s11, 0xff +; GFX11-NEXT: s_lshl_b32 s3, s38, 8 +; GFX11-NEXT: s_and_b32 s10, s10, 0xff +; GFX11-NEXT: s_lshl_b32 s11, s37, 8 +; GFX11-NEXT: s_or_b32 s2, s2, s3 +; GFX11-NEXT: s_or_b32 s3, s10, s11 +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_lshl_b32 s1, s1, 16 +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_lshl_b32 s3, s3, 16 +; GFX11-NEXT: s_or_b32 s0, s0, s1 +; GFX11-NEXT: s_or_b32 s1, s2, s3 +; GFX11-NEXT: s_and_b32 s2, s8, 0xff +; GFX11-NEXT: s_lshl_b32 s3, s36, 8 +; GFX11-NEXT: s_and_b32 s8, s35, 0xff +; GFX11-NEXT: s_lshl_b32 s10, s46, 8 +; GFX11-NEXT: s_or_b32 s2, s2, s3 +; GFX11-NEXT: s_or_b32 s3, s8, s10 +; GFX11-NEXT: v_readlane_b32 s10, v20, 11 +; GFX11-NEXT: s_and_b32 s8, s9, 0xff +; GFX11-NEXT: s_lshl_b32 s9, s55, 8 +; GFX11-NEXT: s_lshl_b32 s11, s34, 8 +; GFX11-NEXT: s_or_b32 s8, s8, s9 +; GFX11-NEXT: s_and_b32 s10, s10, 0xff +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_or_b32 s9, s10, s11 +; GFX11-NEXT: s_lshl_b32 s3, s3, 16 +; GFX11-NEXT: s_and_b32 s8, s8, 0xffff +; GFX11-NEXT: s_lshl_b32 s9, s9, 16 +; GFX11-NEXT: s_or_b32 s2, s2, s3 +; GFX11-NEXT: s_or_b32 s3, s8, s9 +; GFX11-NEXT: v_readlane_b32 s8, v20, 4 +; GFX11-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1 +; GFX11-NEXT: s_and_b32 s0, s6, 0xff +; GFX11-NEXT: v_readlane_b32 s6, v20, 12 +; GFX11-NEXT: v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3 +; GFX11-NEXT: s_lshl_b32 s1, vcc_hi, 8 +; GFX11-NEXT: s_and_b32 s2, s95, 0xff +; GFX11-NEXT: s_lshl_b32 s3, s8, 8 +; GFX11-NEXT: s_or_b32 s0, s0, s1 +; GFX11-NEXT: s_or_b32 s1, s2, s3 +; GFX11-NEXT: s_and_b32 s2, s7, 0xff +; GFX11-NEXT: s_lshl_b32 s3, s93, 8 +; GFX11-NEXT: s_and_b32 s6, s6, 0xff +; GFX11-NEXT: s_lshl_b32 s7, s79, 8 +; GFX11-NEXT: s_or_b32 s2, s2, s3 +; GFX11-NEXT: s_or_b32 s3, s6, s7 +; GFX11-NEXT: v_readlane_b32 s6, v20, 6 +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_lshl_b32 s1, s1, 16 +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_lshl_b32 s3, s3, 16 +; GFX11-NEXT: s_or_b32 s0, s0, s1 +; GFX11-NEXT: s_or_b32 s1, s2, s3 +; GFX11-NEXT: s_and_b32 s2, s4, 0xff +; GFX11-NEXT: s_lshl_b32 s3, s75, 8 +; GFX11-NEXT: s_and_b32 s4, s63, 0xff +; GFX11-NEXT: s_lshl_b32 s6, s6, 8 +; GFX11-NEXT: v_readlane_b32 s7, v20, 7 +; GFX11-NEXT: s_or_b32 s2, s2, s3 +; GFX11-NEXT: s_or_b32 s3, s4, s6 +; GFX11-NEXT: s_and_b32 s4, s5, 0xff +; GFX11-NEXT: v_readlane_b32 s5, v20, 28 +; GFX11-NEXT: v_readlane_b32 s6, v20, 13 +; GFX11-NEXT: v_readlane_b32 s7, v20, 27 +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-NEXT: s_lshl_b32 s3, s3, 16 +; GFX11-NEXT: s_lshl_b32 s5, s5, 8 +; GFX11-NEXT: s_and_b32 s6, s6, 0xff +; GFX11-NEXT: s_lshl_b32 s7, s7, 8 +; GFX11-NEXT: s_or_b32 s4, s4, s5 +; GFX11-NEXT: s_or_b32 s5, s6, s7 +; GFX11-NEXT: s_and_b32 s4, s4, 0xffff +; GFX11-NEXT: s_lshl_b32 s5, s5, 16 +; GFX11-NEXT: s_or_b32 s2, s2, s3 +; GFX11-NEXT: s_or_b32 s3, s4, s5 +; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:64 +; GFX11-NEXT: v_dual_mov_b32 v5, s0 :: v_dual_mov_b32 v6, s1 +; GFX11-NEXT: v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v8, s3 +; GFX11-NEXT: v_readlane_b32 s9, v20, 5 +; GFX11-NEXT: s_clause 0x2 +; GFX11-NEXT: scratch_store_b128 v0, v[9:12], off offset:80 +; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:96 +; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:112 +; GFX11-NEXT: v_readlane_b32 s104, v19, 8 +; GFX11-NEXT: v_readlane_b32 s101, v19, 5 +; GFX11-NEXT: v_readlane_b32 s100, v19, 4 +; GFX11-NEXT: v_readlane_b32 s87, v18, 31 +; GFX11-NEXT: v_readlane_b32 s86, v18, 30 +; GFX11-NEXT: v_readlane_b32 s84, v18, 28 +; GFX11-NEXT: v_readlane_b32 s83, v18, 27 +; GFX11-NEXT: v_readlane_b32 s82, v18, 26 +; GFX11-NEXT: v_readlane_b32 s80, v18, 24 +; GFX11-NEXT: v_readlane_b32 s71, v18, 23 +; GFX11-NEXT: v_readlane_b32 s68, v18, 20 +; GFX11-NEXT: v_readlane_b32 s67, v18, 19 +; GFX11-NEXT: v_readlane_b32 s66, v18, 18 +; GFX11-NEXT: v_readlane_b32 s65, v18, 17 +; GFX11-NEXT: v_readlane_b32 s64, v18, 16 +; GFX11-NEXT: v_readlane_b32 s55, v18, 15 +; GFX11-NEXT: v_readlane_b32 s54, v18, 14 +; GFX11-NEXT: v_readlane_b32 s52, v18, 12 +; GFX11-NEXT: v_readlane_b32 s51, v18, 11 +; GFX11-NEXT: v_readlane_b32 s49, v18, 9 +; GFX11-NEXT: v_readlane_b32 s48, v18, 8 +; GFX11-NEXT: v_readlane_b32 s39, v18, 7 +; GFX11-NEXT: v_readlane_b32 s38, v18, 6 +; GFX11-NEXT: v_readlane_b32 s37, v18, 5 +; GFX11-NEXT: v_readlane_b32 s36, v18, 4 +; GFX11-NEXT: v_readlane_b32 s35, v18, 3 +; GFX11-NEXT: v_readlane_b32 s34, v18, 2 +; GFX11-NEXT: v_readlane_b32 s30, v18, 0 +; GFX11-NEXT: s_xor_saveexec_b32 s0, -1 +; GFX11-NEXT: s_clause 0x2 ; 12-byte Folded Reload +; GFX11-NEXT: scratch_load_b32 v18, off, s32 +; GFX11-NEXT: scratch_load_b32 v19, off, s32 offset:4 +; GFX11-NEXT: scratch_load_b32 v20, off, s32 offset:8 +; GFX11-NEXT: s_mov_b32 exec_lo, s0 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: s_setpc_b64 s[30:31] %cmp = icmp eq i32 %b, 0 br i1 %cmp, label %cmp.true, label %cmp.false @@ -193844,8 +190007,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VI-NEXT: s_or_saveexec_b64 s[4:5], -1 -; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill ; VI-NEXT: s_mov_b64 exec, s[4:5] ; VI-NEXT: v_writelane_b32 v63, s30, 0 ; VI-NEXT: v_writelane_b32 v63, s31, 1 @@ -193878,26 +190041,55 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; VI-NEXT: v_writelane_b32 v63, s84, 28 ; VI-NEXT: v_writelane_b32 v63, s85, 29 ; VI-NEXT: v_writelane_b32 v63, s86, 30 +; VI-NEXT: v_readfirstlane_b32 s56, v3 +; VI-NEXT: v_mov_b32_e32 v3, s16 +; VI-NEXT: v_readfirstlane_b32 s57, v4 +; VI-NEXT: v_mov_b32_e32 v4, s17 +; VI-NEXT: v_readfirstlane_b32 s46, v5 +; VI-NEXT: v_mov_b32_e32 v5, s18 +; VI-NEXT: v_readfirstlane_b32 s47, v6 +; VI-NEXT: v_mov_b32_e32 v6, s19 +; VI-NEXT: v_readfirstlane_b32 s44, v7 +; VI-NEXT: v_mov_b32_e32 v7, s20 +; VI-NEXT: v_readfirstlane_b32 s45, v8 +; VI-NEXT: v_mov_b32_e32 v8, s21 +; VI-NEXT: v_readfirstlane_b32 s42, v9 +; VI-NEXT: v_mov_b32_e32 v9, s22 +; VI-NEXT: v_readfirstlane_b32 s43, v10 +; VI-NEXT: v_mov_b32_e32 v10, s23 +; VI-NEXT: v_readfirstlane_b32 s40, v11 +; VI-NEXT: v_mov_b32_e32 v11, s24 +; VI-NEXT: v_readfirstlane_b32 s41, v12 +; VI-NEXT: v_mov_b32_e32 v12, s25 +; VI-NEXT: v_readfirstlane_b32 s24, v13 +; VI-NEXT: v_mov_b32_e32 v13, s26 +; VI-NEXT: v_readfirstlane_b32 s25, v14 +; VI-NEXT: v_mov_b32_e32 v14, s27 +; VI-NEXT: v_readfirstlane_b32 s22, v15 +; VI-NEXT: v_mov_b32_e32 v15, s28 +; VI-NEXT: v_readfirstlane_b32 s23, v16 +; VI-NEXT: v_mov_b32_e32 v16, s29 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; VI-NEXT: v_writelane_b32 v63, s87, 31 -; VI-NEXT: v_readfirstlane_b32 s44, v3 -; VI-NEXT: v_readfirstlane_b32 s45, v4 -; VI-NEXT: v_readfirstlane_b32 s42, v5 -; VI-NEXT: v_readfirstlane_b32 s43, v6 -; VI-NEXT: v_readfirstlane_b32 s40, v7 -; VI-NEXT: v_readfirstlane_b32 s41, v8 -; VI-NEXT: v_readfirstlane_b32 s14, v9 -; VI-NEXT: v_readfirstlane_b32 s15, v10 -; VI-NEXT: v_readfirstlane_b32 s12, v11 -; VI-NEXT: v_readfirstlane_b32 s13, v12 -; VI-NEXT: v_readfirstlane_b32 s10, v13 -; VI-NEXT: v_readfirstlane_b32 s11, v14 -; VI-NEXT: v_readfirstlane_b32 s8, v15 -; VI-NEXT: v_readfirstlane_b32 s9, v16 -; VI-NEXT: v_readfirstlane_b32 s6, v17 -; VI-NEXT: v_readfirstlane_b32 s7, v18 +; VI-NEXT: v_mov_b32_e32 v39, v0 +; VI-NEXT: v_readfirstlane_b32 s20, v17 +; VI-NEXT: v_readfirstlane_b32 s21, v18 +; VI-NEXT: v_readfirstlane_b32 s18, v3 +; VI-NEXT: v_readfirstlane_b32 s19, v4 +; VI-NEXT: v_readfirstlane_b32 s16, v5 +; VI-NEXT: v_readfirstlane_b32 s17, v6 +; VI-NEXT: v_readfirstlane_b32 s14, v7 +; VI-NEXT: v_readfirstlane_b32 s15, v8 +; VI-NEXT: v_readfirstlane_b32 s12, v9 +; VI-NEXT: v_readfirstlane_b32 s13, v10 +; VI-NEXT: v_readfirstlane_b32 s10, v11 +; VI-NEXT: v_readfirstlane_b32 s11, v12 +; VI-NEXT: v_readfirstlane_b32 s8, v13 +; VI-NEXT: v_readfirstlane_b32 s9, v14 +; VI-NEXT: v_readfirstlane_b32 s6, v15 +; VI-NEXT: v_readfirstlane_b32 s7, v16 ; VI-NEXT: v_readfirstlane_b32 s4, v1 -; VI-NEXT: s_and_b64 s[46:47], vcc, exec +; VI-NEXT: s_and_b64 s[26:27], vcc, exec ; VI-NEXT: v_readfirstlane_b32 s5, v2 ; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill @@ -193916,471 +190108,497 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; VI-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; VI-NEXT: s_cbranch_scc0 .LBB95_3 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_lshr_b32 s46, s5, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 23 -; VI-NEXT: s_lshr_b32 s46, s5, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 15 -; VI-NEXT: s_lshr_b32 s46, s5, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 33 -; VI-NEXT: s_lshr_b32 s46, s4, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 14 -; VI-NEXT: s_lshr_b32 s46, s4, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 34 -; VI-NEXT: s_lshr_b32 s46, s29, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 22 -; VI-NEXT: s_lshr_b32 s46, s29, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 13 -; VI-NEXT: s_lshr_b32 s46, s29, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 32 -; VI-NEXT: s_lshr_b32 s46, s28, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 12 -; VI-NEXT: s_lshr_b32 s46, s28, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 35 -; VI-NEXT: s_lshr_b32 s46, s27, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 21 -; VI-NEXT: s_lshr_b32 s46, s27, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 11 -; VI-NEXT: s_lshr_b32 s46, s27, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 31 -; VI-NEXT: s_lshr_b32 s46, s26, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 10 -; VI-NEXT: s_lshr_b32 s46, s26, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 36 -; VI-NEXT: s_lshr_b32 s46, s25, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 20 -; VI-NEXT: s_lshr_b32 s46, s25, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 9 -; VI-NEXT: s_lshr_b32 s46, s25, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 30 -; VI-NEXT: s_lshr_b32 s46, s24, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 8 -; VI-NEXT: s_lshr_b32 s46, s24, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 37 -; VI-NEXT: s_lshr_b32 s46, s23, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 19 -; VI-NEXT: s_lshr_b32 s46, s23, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 7 -; VI-NEXT: s_lshr_b32 s46, s23, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 29 -; VI-NEXT: s_lshr_b32 s46, s22, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 6 -; VI-NEXT: s_lshr_b32 s46, s22, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 38 -; VI-NEXT: s_lshr_b32 s46, s21, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 18 -; VI-NEXT: s_lshr_b32 s46, s21, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 5 -; VI-NEXT: s_lshr_b32 s46, s21, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 28 -; VI-NEXT: s_lshr_b32 s46, s20, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 4 -; VI-NEXT: s_lshr_b32 s46, s20, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 39 -; VI-NEXT: s_lshr_b32 s46, s19, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 17 -; VI-NEXT: s_lshr_b32 s46, s19, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 3 -; VI-NEXT: s_lshr_b32 s46, s19, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 27 -; VI-NEXT: s_lshr_b32 s46, s18, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 2 -; VI-NEXT: s_lshr_b32 s46, s18, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 40 -; VI-NEXT: s_lshr_b32 s46, s17, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 16 -; VI-NEXT: s_lshr_b32 s46, s17, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 1 -; VI-NEXT: s_lshr_b32 s46, s17, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 26 -; VI-NEXT: s_lshr_b32 s46, s16, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 0 -; VI-NEXT: s_lshr_b32 s46, s16, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 41 -; VI-NEXT: s_lshr_b32 s46, s7, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 24 -; VI-NEXT: s_lshr_b32 s46, s7, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 43 -; VI-NEXT: s_lshr_b32 s46, s6, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 42 -; VI-NEXT: s_lshr_b32 s46, s9, 24 -; VI-NEXT: v_writelane_b32 v62, s46, 25 -; VI-NEXT: s_lshr_b32 s46, s9, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 45 -; VI-NEXT: s_lshr_b32 s46, s8, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 44 -; VI-NEXT: s_lshr_b32 s46, s11, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 47 -; VI-NEXT: s_lshr_b32 s46, s10, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 46 -; VI-NEXT: s_lshr_b32 s46, s13, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 49 -; VI-NEXT: s_lshr_b32 s46, s12, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 48 -; VI-NEXT: s_lshr_b32 s46, s15, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 51 -; VI-NEXT: s_lshr_b32 s46, s14, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 50 -; VI-NEXT: s_lshr_b32 s46, s41, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 53 -; VI-NEXT: s_lshr_b32 s46, s40, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 52 -; VI-NEXT: s_lshr_b32 s46, s43, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 55 -; VI-NEXT: s_lshr_b32 s46, s42, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 54 -; VI-NEXT: s_lshr_b32 s46, s45, 8 -; VI-NEXT: v_writelane_b32 v62, s46, 57 -; VI-NEXT: s_lshr_b32 s46, s44, 8 -; VI-NEXT: s_lshr_b32 s52, s7, 16 -; VI-NEXT: s_lshr_b32 s53, s6, 16 -; VI-NEXT: s_lshr_b32 s84, s9, 16 -; VI-NEXT: s_lshr_b32 s85, s8, 16 -; VI-NEXT: s_lshr_b32 s80, s11, 24 -; VI-NEXT: s_lshr_b32 s86, s11, 16 -; VI-NEXT: s_lshr_b32 s87, s10, 16 -; VI-NEXT: s_lshr_b32 s81, s13, 24 -; VI-NEXT: s_lshr_b32 s54, s13, 16 -; VI-NEXT: s_lshr_b32 s55, s12, 16 -; VI-NEXT: s_lshr_b32 s82, s15, 24 -; VI-NEXT: s_lshr_b32 s64, s15, 16 -; VI-NEXT: s_lshr_b32 s65, s14, 16 -; VI-NEXT: s_lshr_b32 s83, s41, 24 -; VI-NEXT: s_lshr_b32 s66, s41, 16 -; VI-NEXT: s_lshr_b32 s67, s40, 16 -; VI-NEXT: s_lshr_b32 s50, s43, 24 -; VI-NEXT: s_lshr_b32 s68, s43, 16 -; VI-NEXT: s_lshr_b32 s69, s42, 16 -; VI-NEXT: s_lshr_b32 s51, s45, 24 -; VI-NEXT: s_lshr_b32 s70, s45, 16 -; VI-NEXT: s_lshr_b32 s71, s44, 16 -; VI-NEXT: v_writelane_b32 v62, s46, 56 -; VI-NEXT: s_lshr_b64 s[46:47], s[4:5], 24 -; VI-NEXT: s_lshr_b64 s[56:57], s[28:29], 24 -; VI-NEXT: s_lshr_b64 s[58:59], s[26:27], 24 -; VI-NEXT: s_lshr_b64 s[60:61], s[24:25], 24 -; VI-NEXT: s_lshr_b64 s[62:63], s[22:23], 24 -; VI-NEXT: s_lshr_b64 s[72:73], s[20:21], 24 -; VI-NEXT: s_lshr_b64 s[74:75], s[18:19], 24 -; VI-NEXT: s_lshr_b64 s[76:77], s[16:17], 24 -; VI-NEXT: s_lshr_b64 s[78:79], s[6:7], 24 -; VI-NEXT: s_lshr_b64 s[88:89], s[8:9], 24 -; VI-NEXT: s_lshr_b64 s[90:91], s[10:11], 24 -; VI-NEXT: s_lshr_b64 s[30:31], s[12:13], 24 -; VI-NEXT: s_lshr_b64 s[34:35], s[14:15], 24 -; VI-NEXT: s_lshr_b64 s[36:37], s[40:41], 24 -; VI-NEXT: s_lshr_b64 s[38:39], s[42:43], 24 -; VI-NEXT: s_lshr_b64 s[48:49], s[44:45], 24 +; VI-NEXT: s_lshr_b32 s26, s5, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 26 +; VI-NEXT: s_lshr_b32 s26, s5, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 15 +; VI-NEXT: s_lshr_b32 s26, s5, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 57 +; VI-NEXT: s_lshr_b32 s26, s4, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 14 +; VI-NEXT: s_lshr_b32 s26, s4, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 56 +; VI-NEXT: s_lshr_b32 s26, s7, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 25 +; VI-NEXT: s_lshr_b32 s26, s7, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 13 +; VI-NEXT: s_lshr_b32 s26, s7, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 55 +; VI-NEXT: s_lshr_b32 s26, s6, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 12 +; VI-NEXT: s_lshr_b32 s26, s6, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 54 +; VI-NEXT: s_lshr_b32 s26, s9, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 24 +; VI-NEXT: s_lshr_b32 s26, s9, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 11 +; VI-NEXT: s_lshr_b32 s26, s9, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 53 +; VI-NEXT: s_lshr_b32 s26, s8, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 10 +; VI-NEXT: s_lshr_b32 s26, s8, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 52 +; VI-NEXT: s_lshr_b32 s26, s11, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 23 +; VI-NEXT: s_lshr_b32 s26, s11, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 9 +; VI-NEXT: s_lshr_b32 s26, s11, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 51 +; VI-NEXT: s_lshr_b32 s26, s10, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 8 +; VI-NEXT: s_lshr_b32 s26, s10, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 50 +; VI-NEXT: s_lshr_b32 s26, s13, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 22 +; VI-NEXT: s_lshr_b32 s26, s13, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 7 +; VI-NEXT: s_lshr_b32 s26, s13, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 49 +; VI-NEXT: s_lshr_b32 s26, s12, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 6 +; VI-NEXT: s_lshr_b32 s26, s12, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 48 +; VI-NEXT: s_lshr_b32 s26, s15, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 21 +; VI-NEXT: s_lshr_b32 s26, s15, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 5 +; VI-NEXT: s_lshr_b32 s26, s15, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 47 +; VI-NEXT: s_lshr_b32 s26, s14, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 4 +; VI-NEXT: s_lshr_b32 s26, s14, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 46 +; VI-NEXT: s_lshr_b32 s26, s17, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 20 +; VI-NEXT: s_lshr_b32 s26, s17, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 3 +; VI-NEXT: s_lshr_b32 s26, s17, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 45 +; VI-NEXT: s_lshr_b32 s26, s16, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 2 +; VI-NEXT: s_lshr_b32 s26, s16, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 44 +; VI-NEXT: s_lshr_b32 s26, s19, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 19 +; VI-NEXT: s_lshr_b32 s26, s19, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 1 +; VI-NEXT: s_lshr_b32 s26, s19, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 43 +; VI-NEXT: s_lshr_b32 s26, s18, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 0 +; VI-NEXT: s_lshr_b32 s26, s18, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 42 +; VI-NEXT: s_lshr_b32 s26, s21, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 18 +; VI-NEXT: s_lshr_b32 s26, s21, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 41 +; VI-NEXT: s_lshr_b32 s26, s20, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 40 +; VI-NEXT: s_lshr_b32 s26, s23, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 17 +; VI-NEXT: s_lshr_b32 s26, s23, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 39 +; VI-NEXT: s_lshr_b32 s26, s22, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 38 +; VI-NEXT: s_lshr_b32 s26, s25, 24 +; VI-NEXT: v_writelane_b32 v62, s26, 16 +; VI-NEXT: s_lshr_b32 s26, s25, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 37 +; VI-NEXT: s_lshr_b32 s26, s24, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 36 +; VI-NEXT: s_lshr_b32 s26, s41, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 35 +; VI-NEXT: s_lshr_b32 s26, s40, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 34 +; VI-NEXT: s_lshr_b32 s26, s43, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 33 +; VI-NEXT: s_lshr_b32 s26, s42, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 32 +; VI-NEXT: s_lshr_b32 s26, s45, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 31 +; VI-NEXT: s_lshr_b32 s26, s44, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 30 +; VI-NEXT: s_lshr_b32 s26, s47, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 29 +; VI-NEXT: s_lshr_b32 s26, s46, 8 +; VI-NEXT: v_writelane_b32 v62, s26, 28 +; VI-NEXT: s_lshr_b32 s26, s57, 8 +; VI-NEXT: s_lshr_b32 s86, s21, 16 +; VI-NEXT: s_lshr_b32 s87, s20, 16 +; VI-NEXT: s_lshr_b32 s50, s23, 16 +; VI-NEXT: s_lshr_b32 s51, s22, 16 +; VI-NEXT: s_lshr_b32 s52, s25, 16 +; VI-NEXT: s_lshr_b32 s53, s24, 16 +; VI-NEXT: s_lshr_b32 s81, s41, 24 +; VI-NEXT: s_lshr_b32 s54, s41, 16 +; VI-NEXT: s_lshr_b32 s55, s40, 16 +; VI-NEXT: s_lshr_b32 s82, s43, 24 +; VI-NEXT: s_lshr_b32 s64, s43, 16 +; VI-NEXT: s_lshr_b32 s65, s42, 16 +; VI-NEXT: s_lshr_b32 s83, s45, 24 +; VI-NEXT: s_lshr_b32 s66, s45, 16 +; VI-NEXT: s_lshr_b32 s67, s44, 16 +; VI-NEXT: s_lshr_b32 s84, s47, 24 +; VI-NEXT: s_lshr_b32 s68, s47, 16 +; VI-NEXT: s_lshr_b32 s69, s46, 16 +; VI-NEXT: s_lshr_b32 s85, s57, 24 +; VI-NEXT: s_lshr_b32 s70, s57, 16 +; VI-NEXT: v_writelane_b32 v62, s26, 27 +; VI-NEXT: s_lshr_b32 s71, s56, 16 +; VI-NEXT: s_lshr_b32 s80, s56, 8 +; VI-NEXT: s_lshr_b64 s[26:27], s[4:5], 24 +; VI-NEXT: s_lshr_b64 s[28:29], s[6:7], 24 +; VI-NEXT: s_lshr_b64 s[58:59], s[8:9], 24 +; VI-NEXT: s_lshr_b64 s[60:61], s[10:11], 24 +; VI-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 +; VI-NEXT: s_lshr_b64 s[72:73], s[14:15], 24 +; VI-NEXT: s_lshr_b64 s[74:75], s[16:17], 24 +; VI-NEXT: s_lshr_b64 s[76:77], s[18:19], 24 +; VI-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 +; VI-NEXT: s_lshr_b64 s[88:89], s[22:23], 24 +; VI-NEXT: s_lshr_b64 s[90:91], s[24:25], 24 +; VI-NEXT: s_lshr_b64 s[30:31], s[40:41], 24 +; VI-NEXT: s_lshr_b64 s[34:35], s[42:43], 24 +; VI-NEXT: s_lshr_b64 s[36:37], s[44:45], 24 +; VI-NEXT: s_lshr_b64 s[38:39], s[46:47], 24 +; VI-NEXT: s_lshr_b64 s[48:49], s[56:57], 24 ; VI-NEXT: s_cbranch_execnz .LBB95_4 ; VI-NEXT: .LBB95_2: ; %cmp.true -; VI-NEXT: s_lshr_b32 s46, s45, 16 -; VI-NEXT: v_mov_b32_e32 v7, 0x200 -; VI-NEXT: v_add_f16_e32 v11, s46, v7 -; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v11 -; VI-NEXT: v_add_f16_e32 v2, s45, v7 -; VI-NEXT: s_lshr_b32 s45, s44, 16 +; VI-NEXT: s_lshr_b32 s26, s57, 16 +; VI-NEXT: v_mov_b32_e32 v9, 0x200 +; VI-NEXT: v_add_f16_e32 v0, s26, v9 +; VI-NEXT: s_lshr_b32 s26, s56, 16 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0 +; VI-NEXT: v_add_f16_e32 v2, s57, v9 +; VI-NEXT: v_add_f16_e32 v0, s26, v9 +; VI-NEXT: s_lshr_b32 s26, s47, 16 ; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v23, v2, v1 -; VI-NEXT: v_add_f16_e32 v40, s45, v7 -; VI-NEXT: v_add_f16_e32 v2, s44, v7 -; VI-NEXT: s_lshr_b32 s44, s43, 16 -; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v40 -; VI-NEXT: v_add_f16_e32 v43, s44, v7 +; VI-NEXT: v_or_b32_e32 v35, v2, v1 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0 +; VI-NEXT: v_add_f16_e32 v2, s56, v9 +; VI-NEXT: v_add_f16_e32 v0, s26, v9 +; VI-NEXT: s_lshr_b32 s26, s46, 16 ; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v22, v2, v1 -; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v43 -; VI-NEXT: v_add_f16_e32 v2, s43, v7 -; VI-NEXT: s_lshr_b32 s43, s42, 16 +; VI-NEXT: v_or_b32_e32 v34, v2, v1 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0 +; VI-NEXT: v_add_f16_e32 v2, s47, v9 +; VI-NEXT: v_add_f16_e32 v0, s26, v9 +; VI-NEXT: s_lshr_b32 s26, s45, 16 ; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v25, v2, v1 -; VI-NEXT: v_add_f16_e32 v54, s43, v7 -; VI-NEXT: v_add_f16_e32 v2, s42, v7 -; VI-NEXT: s_lshr_b32 s42, s41, 16 -; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v54 -; VI-NEXT: v_add_f16_e32 v37, s42, v7 +; VI-NEXT: v_or_b32_e32 v23, v2, v1 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0 +; VI-NEXT: v_add_f16_e32 v2, s46, v9 +; VI-NEXT: v_add_f16_e32 v0, s26, v9 +; VI-NEXT: s_lshr_b32 s26, s44, 16 ; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v24, v2, v1 -; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v37 -; VI-NEXT: v_add_f16_e32 v2, s41, v7 -; VI-NEXT: s_lshr_b32 s41, s40, 16 +; VI-NEXT: v_or_b32_e32 v22, v2, v1 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0 +; VI-NEXT: v_add_f16_e32 v2, s45, v9 +; VI-NEXT: v_add_f16_e32 v0, s26, v9 +; VI-NEXT: s_lshr_b32 s26, s43, 16 ; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v27, v2, v1 -; VI-NEXT: v_add_f16_e32 v49, s41, v7 -; VI-NEXT: v_add_f16_e32 v2, s40, v7 -; VI-NEXT: s_lshr_b32 s40, s15, 16 -; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v49 -; VI-NEXT: v_add_f16_e32 v52, s40, v7 +; VI-NEXT: v_or_b32_e32 v21, v2, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0 +; VI-NEXT: v_add_f16_e32 v2, s44, v9 +; VI-NEXT: v_add_f16_e32 v58, s26, v9 ; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v26, v2, v1 -; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v52 -; VI-NEXT: v_add_f16_e32 v2, s15, v7 -; VI-NEXT: s_lshr_b32 s15, s14, 16 +; VI-NEXT: v_or_b32_e32 v20, v2, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v58 +; VI-NEXT: v_add_f16_e32 v2, s43, v9 +; VI-NEXT: s_lshr_b32 s26, s42, 16 +; VI-NEXT: v_or_b32_e32 v25, v2, v1 +; VI-NEXT: v_add_f16_e32 v1, s26, v9 +; VI-NEXT: s_lshr_b32 s26, s41, 16 ; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v29, v2, v1 -; VI-NEXT: v_add_f16_e32 v55, s15, v7 -; VI-NEXT: v_add_f16_e32 v2, s14, v7 -; VI-NEXT: s_lshr_b32 s14, s13, 16 -; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v55 -; VI-NEXT: v_add_f16_e32 v53, s14, v7 +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; VI-NEXT: v_add_f16_e32 v2, s42, v9 +; VI-NEXT: v_add_f16_e32 v46, s26, v9 ; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v28, v2, v1 -; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v53 -; VI-NEXT: v_add_f16_e32 v2, s13, v7 -; VI-NEXT: s_lshr_b32 s13, s12, 16 +; VI-NEXT: v_or_b32_e32 v24, v2, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v46 +; VI-NEXT: v_add_f16_e32 v2, s41, v9 +; VI-NEXT: s_lshr_b32 s26, s40, 16 +; VI-NEXT: v_or_b32_e32 v7, v2, v1 +; VI-NEXT: v_add_f16_e32 v1, s26, v9 +; VI-NEXT: s_lshr_b32 s26, s25, 16 ; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v6, v2, v1 -; VI-NEXT: v_add_f16_e32 v1, s13, v7 -; VI-NEXT: v_add_f16_e32 v2, s12, v7 -; VI-NEXT: s_lshr_b32 s12, s11, 16 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; VI-NEXT: v_add_f16_e32 v39, s12, v7 +; VI-NEXT: v_add_f16_e32 v2, s40, v9 +; VI-NEXT: v_add_f16_e32 v47, s26, v9 ; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v5, v2, v1 -; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v39 -; VI-NEXT: v_add_f16_e32 v2, s11, v7 -; VI-NEXT: s_lshr_b32 s11, s10, 16 +; VI-NEXT: v_or_b32_e32 v6, v2, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v47 +; VI-NEXT: v_add_f16_e32 v2, s25, v9 +; VI-NEXT: s_lshr_b32 s25, s24, 16 ; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v31, v2, v1 -; VI-NEXT: v_add_f16_e32 v60, s11, v7 -; VI-NEXT: v_add_f16_e32 v2, s10, v7 -; VI-NEXT: s_lshr_b32 s10, s9, 16 -; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v60 -; VI-NEXT: v_add_f16_e32 v48, s10, v7 +; VI-NEXT: v_or_b32_e32 v27, v2, v1 +; VI-NEXT: v_add_f16_e32 v1, s25, v9 +; VI-NEXT: v_add_f16_e32 v2, s24, v9 +; VI-NEXT: s_lshr_b32 s24, s23, 16 +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; VI-NEXT: v_add_f16_e32 v44, s24, v9 ; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v30, v2, v1 -; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v48 -; VI-NEXT: v_add_f16_e32 v2, s9, v7 -; VI-NEXT: s_lshr_b32 s9, s8, 16 +; VI-NEXT: v_or_b32_e32 v26, v2, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v44 +; VI-NEXT: v_add_f16_e32 v2, s23, v9 +; VI-NEXT: s_lshr_b32 s23, s22, 16 ; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill ; VI-NEXT: v_or_b32_e32 v4, v2, v1 -; VI-NEXT: v_add_f16_e32 v1, s9, v7 -; VI-NEXT: v_add_f16_e32 v2, s8, v7 -; VI-NEXT: s_lshr_b32 s8, s7, 16 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; VI-NEXT: v_add_f16_e32 v1, s23, v9 +; VI-NEXT: v_add_f16_e32 v2, s22, v9 +; VI-NEXT: s_lshr_b32 s22, s21, 16 +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; VI-NEXT: v_add_f16_e32 v50, s8, v7 +; VI-NEXT: v_add_f16_e32 v60, s22, v9 ; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill ; VI-NEXT: v_or_b32_e32 v3, v2, v1 -; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v50 -; VI-NEXT: v_add_f16_e32 v2, s7, v7 -; VI-NEXT: s_lshr_b32 s7, s6, 16 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v60 +; VI-NEXT: v_add_f16_e32 v2, s21, v9 +; VI-NEXT: s_lshr_b32 s21, s20, 16 ; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill ; VI-NEXT: v_or_b32_e32 v2, v2, v1 -; VI-NEXT: v_add_f16_e32 v1, s7, v7 -; VI-NEXT: v_add_f16_e32 v8, s6, v7 -; VI-NEXT: s_lshr_b32 s6, s17, 16 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; VI-NEXT: v_add_f16_e32 v1, s21, v9 +; VI-NEXT: v_add_f16_e32 v10, s20, v9 +; VI-NEXT: s_lshr_b32 s20, s19, 16 +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill ; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; VI-NEXT: v_add_f16_e32 v36, s6, v7 -; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v1, v8, v1 -; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v36 -; VI-NEXT: v_add_f16_e32 v9, s17, v7 -; VI-NEXT: s_lshr_b32 s6, s16, 16 -; VI-NEXT: v_or_b32_e32 v33, v9, v8 -; VI-NEXT: v_add_f16_e32 v8, s6, v7 -; VI-NEXT: s_lshr_b32 s6, s19, 16 -; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; VI-NEXT: v_add_f16_e32 v9, s16, v7 -; VI-NEXT: v_add_f16_e32 v38, s6, v7 -; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v32, v9, v8 -; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v38 -; VI-NEXT: v_add_f16_e32 v9, s19, v7 -; VI-NEXT: s_lshr_b32 s6, s18, 16 -; VI-NEXT: v_or_b32_e32 v21, v9, v8 -; VI-NEXT: v_add_f16_e32 v8, s6, v7 -; VI-NEXT: s_lshr_b32 s6, s21, 16 -; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill -; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; VI-NEXT: v_add_f16_e32 v9, s18, v7 -; VI-NEXT: v_add_f16_e32 v61, s6, v7 -; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v20, v9, v8 -; VI-NEXT: s_lshr_b32 s7, s20, 16 -; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v61 -; VI-NEXT: v_add_f16_e32 v9, s21, v7 -; VI-NEXT: v_or_b32_e32 v35, v9, v8 -; VI-NEXT: v_add_f16_e32 v8, s7, v7 -; VI-NEXT: s_lshr_b32 s6, s23, 16 -; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; VI-NEXT: v_add_f16_e32 v9, s20, v7 -; VI-NEXT: v_add_f16_e32 v45, s6, v7 -; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v34, v9, v8 -; VI-NEXT: s_lshr_b32 s7, s22, 16 -; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v45 -; VI-NEXT: v_add_f16_e32 v9, s23, v7 -; VI-NEXT: v_or_b32_e32 v19, v9, v8 -; VI-NEXT: v_add_f16_e32 v8, s7, v7 -; VI-NEXT: s_lshr_b32 s6, s25, 16 -; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; VI-NEXT: v_add_f16_e32 v9, s22, v7 -; VI-NEXT: v_add_f16_e32 v47, s6, v7 -; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v18, v9, v8 -; VI-NEXT: s_lshr_b32 s7, s24, 16 -; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v47 -; VI-NEXT: v_add_f16_e32 v9, s25, v7 -; VI-NEXT: v_or_b32_e32 v16, v9, v8 -; VI-NEXT: v_add_f16_e32 v8, s7, v7 -; VI-NEXT: s_lshr_b32 s6, s27, 16 -; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; VI-NEXT: v_add_f16_e32 v9, s24, v7 -; VI-NEXT: v_add_f16_e32 v57, s6, v7 -; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v15, v9, v8 -; VI-NEXT: s_lshr_b32 s7, s26, 16 -; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v57 -; VI-NEXT: v_add_f16_e32 v9, s27, v7 -; VI-NEXT: v_or_b32_e32 v13, v9, v8 -; VI-NEXT: v_add_f16_e32 v8, s7, v7 -; VI-NEXT: s_lshr_b32 s6, s29, 16 -; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; VI-NEXT: v_add_f16_e32 v9, s26, v7 -; VI-NEXT: v_add_f16_e32 v59, s6, v7 -; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v12, v9, v8 -; VI-NEXT: s_lshr_b32 s7, s28, 16 -; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v59 -; VI-NEXT: v_add_f16_e32 v9, s29, v7 -; VI-NEXT: v_or_b32_e32 v10, v9, v8 -; VI-NEXT: v_add_f16_e32 v8, s7, v7 +; VI-NEXT: v_add_f16_e32 v43, s20, v9 +; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; VI-NEXT: v_or_b32_e32 v1, v10, v1 +; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v43 +; VI-NEXT: v_add_f16_e32 v51, s19, v9 +; VI-NEXT: s_lshr_b32 s19, s18, 16 +; VI-NEXT: v_or_b32_e32 v29, v51, v10 +; VI-NEXT: v_add_f16_e32 v10, s19, v9 +; VI-NEXT: v_add_f16_e32 v54, s18, v9 +; VI-NEXT: s_lshr_b32 s18, s17, 16 +; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; VI-NEXT: v_add_f16_e32 v45, s18, v9 +; VI-NEXT: v_add_f16_e32 v11, s17, v9 +; VI-NEXT: s_lshr_b32 s17, s16, 16 +; VI-NEXT: v_or_b32_e32 v28, v54, v10 +; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v45 +; VI-NEXT: v_add_f16_e32 v36, s17, v9 +; VI-NEXT: v_add_f16_e32 v55, s16, v9 +; VI-NEXT: s_lshr_b32 s16, s15, 16 +; VI-NEXT: v_or_b32_e32 v19, v11, v10 +; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v36 +; VI-NEXT: v_add_f16_e32 v52, s16, v9 +; VI-NEXT: v_or_b32_e32 v18, v55, v10 +; VI-NEXT: s_lshr_b32 s17, s14, 16 +; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v52 +; VI-NEXT: v_add_f16_e32 v13, s15, v9 +; VI-NEXT: v_or_b32_e32 v31, v13, v10 +; VI-NEXT: v_add_f16_e32 v10, s17, v9 +; VI-NEXT: v_add_f16_e32 v59, s14, v9 +; VI-NEXT: s_lshr_b32 s14, s13, 16 +; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; VI-NEXT: s_lshr_b32 s15, s12, 16 +; VI-NEXT: v_add_f16_e32 v50, s14, v9 +; VI-NEXT: v_or_b32_e32 v30, v59, v10 +; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v50 +; VI-NEXT: v_add_f16_e32 v53, s13, v9 +; VI-NEXT: v_add_f16_e32 v8, s15, v9 +; VI-NEXT: v_add_f16_e32 v41, s12, v9 +; VI-NEXT: s_lshr_b32 s12, s11, 16 +; VI-NEXT: v_or_b32_e32 v17, v53, v10 +; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v8 +; VI-NEXT: s_lshr_b32 s13, s10, 16 +; VI-NEXT: v_add_f16_e32 v5, s12, v9 +; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; VI-NEXT: v_or_b32_e32 v16, v41, v10 +; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v5 +; VI-NEXT: v_add_f16_e32 v57, s11, v9 +; VI-NEXT: v_add_f16_e32 v38, s13, v9 +; VI-NEXT: v_add_f16_e32 v11, s10, v9 +; VI-NEXT: s_lshr_b32 s10, s9, 16 +; VI-NEXT: v_or_b32_e32 v33, v57, v10 +; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v38 +; VI-NEXT: s_lshr_b32 s11, s8, 16 +; VI-NEXT: v_add_f16_e32 v37, s10, v9 +; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; VI-NEXT: v_or_b32_e32 v32, v11, v10 +; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v37 +; VI-NEXT: v_add_f16_e32 v61, s9, v9 +; VI-NEXT: v_add_f16_e32 v48, s11, v9 +; VI-NEXT: v_add_f16_e32 v11, s8, v9 +; VI-NEXT: s_lshr_b32 s8, s7, 16 +; VI-NEXT: v_or_b32_e32 v15, v61, v10 +; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v48 +; VI-NEXT: v_add_f16_e32 v49, s8, v9 +; VI-NEXT: v_or_b32_e32 v14, v11, v10 +; VI-NEXT: s_lshr_b32 s9, s6, 16 +; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v49 +; VI-NEXT: v_add_f16_e32 v56, s7, v9 +; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; VI-NEXT: v_or_b32_e32 v12, v56, v10 +; VI-NEXT: v_add_f16_e32 v10, s9, v9 +; VI-NEXT: v_add_f16_e32 v11, s6, v9 ; VI-NEXT: s_lshr_b32 s6, s5, 16 -; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8 -; VI-NEXT: v_add_f16_e32 v9, s28, v7 +; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10 ; VI-NEXT: s_lshr_b32 s7, s4, 16 -; VI-NEXT: v_add_f16_e32 v51, s6, v7 -; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v9, v9, v8 -; VI-NEXT: v_add_f16_e32 v8, s5, v7 -; VI-NEXT: v_add_f16_e32 v14, s7, v7 -; VI-NEXT: v_add_f16_e32 v17, s4, v7 -; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v51 -; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v8, v8, v7 -; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v14 -; VI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; VI-NEXT: v_or_b32_e32 v7, v17, v7 -; VI-NEXT: v_lshrrev_b32_e32 v14, 8, v8 -; VI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v14, 8, v7 -; VI-NEXT: v_lshrrev_b64 v[7:8], 24, v[7:8] -; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v10 -; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v9 -; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v13 -; VI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v12 -; VI-NEXT: v_lshrrev_b64 v[13:14], 24, v[12:13] -; VI-NEXT: v_lshrrev_b32_e32 v12, 8, v2 -; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v12, 8, v1 -; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[1:2] -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v4 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v3 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[3:4] -; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[9:10], 24, v[9:10] -; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v16 -; VI-NEXT: v_lshrrev_b64 v[16:17], 24, v[15:16] +; VI-NEXT: v_add_f16_e32 v40, s6, v9 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; VI-NEXT: v_or_b32_e32 v11, v11, v10 +; VI-NEXT: v_add_f16_e32 v10, s5, v9 +; VI-NEXT: v_add_f16_e32 v0, s7, v9 +; VI-NEXT: v_add_f16_e32 v42, s4, v9 +; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v40 +; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; VI-NEXT: v_or_b32_e32 v10, v10, v9 +; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v0 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; VI-NEXT: v_or_b32_e32 v9, v42, v9 +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v10 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v9 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v12 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v11 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v15 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v14 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v33 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v32 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v17 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v2 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v1 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b64 v[0:1], 24, v[1:2] +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v4 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v3 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b64 v[0:1], 24, v[3:4] +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v27 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v26 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b64 v[0:1], 24, v[26:27] +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill ; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v8, 8, v19 -; VI-NEXT: v_lshrrev_b32_e32 v10, 8, v18 +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v7 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v6 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v25 +; VI-NEXT: v_lshrrev_b64 v[9:10], 24, v[9:10] +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v24 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b64 v[0:1], 24, v[24:25] +; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b64 v[9:10], 24, v[11:12] +; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[14:15] +; VI-NEXT: v_lshrrev_b64 v[14:15], 24, v[32:33] +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v12, 8, v16 +; VI-NEXT: v_lshrrev_b64 v[15:16], 24, v[16:17] +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v21 +; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b64 v[16:17], 24, v[30:31] +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v20 +; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v18 ; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[18:19] -; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v31 -; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v15 -; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v8, 8, v35 -; VI-NEXT: v_lshrrev_b64 v[18:19], 24, v[34:35] -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v30 -; VI-NEXT: v_lshrrev_b32_e32 v35, 8, v23 -; VI-NEXT: v_lshrrev_b64 v[14:15], 24, v[22:23] -; VI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill -; VI-NEXT: v_bfe_u32 v23, v50, 8, 8 -; VI-NEXT: v_mov_b32_e32 v50, v11 -; VI-NEXT: v_bfe_u32 v11, v48, 8, 8 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[30:31] -; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v6 -; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; VI-NEXT: v_bfe_u32 v11, v39, 8, 8 -; VI-NEXT: v_lshrrev_b32_e32 v56, 8, v20 -; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[20:21] -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v5 -; VI-NEXT: v_lshrrev_b64 v[4:5], 24, v[5:6] -; VI-NEXT: v_lshrrev_b64 v[30:31], 24, v[26:27] -; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; VI-NEXT: v_bfe_u32 v11, v53, 8, 8 -; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v34 -; VI-NEXT: v_lshrrev_b32_e32 v41, 8, v21 -; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[32:33] -; VI-NEXT: v_lshrrev_b64 v[5:6], 24, v[28:29] -; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v25 -; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v24 -; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[24:25] -; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; VI-NEXT: v_bfe_u32 v11, v52, 8, 8 -; VI-NEXT: v_lshrrev_b32_e32 v46, 8, v33 -; VI-NEXT: v_lshrrev_b32_e32 v58, 8, v32 -; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill -; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v29 -; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v28 -; VI-NEXT: v_lshrrev_b32_e32 v28, 8, v27 -; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v26 -; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v22 -; VI-NEXT: v_bfe_u32 v25, v51, 8, 8 -; VI-NEXT: v_bfe_u32 v27, v59, 8, 8 -; VI-NEXT: v_bfe_u32 v6, v57, 8, 8 -; VI-NEXT: v_bfe_u32 v12, v47, 8, 8 -; VI-NEXT: v_bfe_u32 v15, v45, 8, 8 -; VI-NEXT: v_bfe_u32 v1, v61, 8, 8 -; VI-NEXT: v_bfe_u32 v22, v38, 8, 8 -; VI-NEXT: v_bfe_u32 v2, v36, 8, 8 -; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; VI-NEXT: v_bfe_u32 v44, v37, 8, 8 -; VI-NEXT: v_bfe_u32 v11, v43, 8, 8 -; VI-NEXT: v_bfe_u32 v26, v50, 8, 8 -; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v23 +; VI-NEXT: v_lshrrev_b32_e32 v33, 8, v30 +; VI-NEXT: v_lshrrev_b32_e32 v30, 8, v19 +; VI-NEXT: v_lshrrev_b64 v[18:19], 24, v[28:29] +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v22 +; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[6:7] +; VI-NEXT: v_lshrrev_b64 v[6:7], 24, v[20:21] +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[22:23] +; VI-NEXT: v_bfe_u32 v0, v60, 8, 8 +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; VI-NEXT: v_bfe_u32 v20, v40, 8, 8 +; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v42, v40 +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload +; VI-NEXT: v_lshrrev_b32_e32 v22, 8, v35 +; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[34:35] +; VI-NEXT: v_mov_b32_e32 v4, v5 +; VI-NEXT: v_bfe_u32 v27, v5, 8, 8 +; VI-NEXT: v_mov_b32_e32 v5, v50 +; VI-NEXT: v_bfe_u32 v1, v50, 8, 8 +; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload +; VI-NEXT: v_mov_b32_e32 v25, v52 +; VI-NEXT: v_bfe_u32 v23, v52, 8, 8 +; VI-NEXT: v_mov_b32_e32 v52, v36 +; VI-NEXT: v_mov_b32_e32 v36, v44 +; VI-NEXT: v_lshrrev_b32_e32 v26, 8, v34 +; VI-NEXT: v_bfe_u32 v34, v36, 8, 8 +; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; VI-NEXT: v_bfe_u32 v34, v47, 8, 8 +; VI-NEXT: v_mov_b32_e32 v44, v58 +; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; VI-NEXT: v_bfe_u32 v34, v46, 8, 8 +; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; VI-NEXT: v_bfe_u32 v34, v44, 8, 8 +; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v31 +; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v29 +; VI-NEXT: v_lshrrev_b32_e32 v10, 8, v28 +; VI-NEXT: v_mov_b32_e32 v2, v54 +; VI-NEXT: v_bfe_u32 v21, v49, 8, 8 +; VI-NEXT: v_bfe_u32 v54, v37, 8, 8 +; VI-NEXT: v_bfe_u32 v28, v45, 8, 8 +; VI-NEXT: v_bfe_u32 v29, v43, 8, 8 +; VI-NEXT: s_waitcnt vmcnt(10) +; VI-NEXT: v_bfe_u32 v34, v0, 8, 8 +; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; VI-NEXT: s_waitcnt vmcnt(10) +; VI-NEXT: v_bfe_u32 v34, v40, 8, 8 +; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; VI-NEXT: s_waitcnt vmcnt(9) +; VI-NEXT: v_bfe_u32 v34, v60, 8, 8 ; VI-NEXT: s_branch .LBB95_5 ; VI-NEXT: .LBB95_3: -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr80 ; VI-NEXT: ; implicit-def: $sgpr71 ; VI-NEXT: ; implicit-def: $sgpr70 -; VI-NEXT: ; implicit-def: $sgpr51 +; VI-NEXT: ; implicit-def: $sgpr85 ; VI-NEXT: ; implicit-def: $sgpr69 ; VI-NEXT: ; implicit-def: $sgpr68 -; VI-NEXT: ; implicit-def: $sgpr50 +; VI-NEXT: ; implicit-def: $sgpr84 ; VI-NEXT: ; implicit-def: $sgpr67 ; VI-NEXT: ; implicit-def: $sgpr66 ; VI-NEXT: ; implicit-def: $sgpr83 @@ -194390,20 +190608,19 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; VI-NEXT: ; implicit-def: $sgpr55 ; VI-NEXT: ; implicit-def: $sgpr54 ; VI-NEXT: ; implicit-def: $sgpr81 -; VI-NEXT: ; implicit-def: $sgpr87 -; VI-NEXT: ; implicit-def: $sgpr86 -; VI-NEXT: ; implicit-def: $sgpr80 -; VI-NEXT: ; implicit-def: $sgpr85 -; VI-NEXT: ; implicit-def: $sgpr84 ; VI-NEXT: ; implicit-def: $sgpr53 ; VI-NEXT: ; implicit-def: $sgpr52 +; VI-NEXT: ; implicit-def: $sgpr51 +; VI-NEXT: ; implicit-def: $sgpr50 +; VI-NEXT: ; implicit-def: $sgpr87 +; VI-NEXT: ; implicit-def: $sgpr86 ; VI-NEXT: ; implicit-def: $sgpr76 ; VI-NEXT: ; implicit-def: $sgpr74 ; VI-NEXT: ; implicit-def: $sgpr72 ; VI-NEXT: ; implicit-def: $sgpr62 ; VI-NEXT: ; implicit-def: $sgpr60 ; VI-NEXT: ; implicit-def: $sgpr58 -; VI-NEXT: ; implicit-def: $sgpr56 +; VI-NEXT: ; implicit-def: $sgpr28 ; VI-NEXT: ; implicit-def: $sgpr48 ; VI-NEXT: ; implicit-def: $sgpr38 ; VI-NEXT: ; implicit-def: $sgpr36 @@ -194412,388 +190629,399 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; VI-NEXT: ; implicit-def: $sgpr90 ; VI-NEXT: ; implicit-def: $sgpr88 ; VI-NEXT: ; implicit-def: $sgpr78 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 -; VI-NEXT: ; kill: killed $sgpr46 -; VI-NEXT: ; implicit-def: $sgpr46 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 +; VI-NEXT: ; kill: killed $sgpr26 +; VI-NEXT: ; implicit-def: $sgpr26 ; VI-NEXT: s_branch .LBB95_2 ; VI-NEXT: .LBB95_4: -; VI-NEXT: v_mov_b32_e32 v1, s44 +; VI-NEXT: v_mov_b32_e32 v1, s56 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s45 +; VI-NEXT: v_mov_b32_e32 v1, s57 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s42 +; VI-NEXT: v_mov_b32_e32 v1, s46 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s43 +; VI-NEXT: v_mov_b32_e32 v1, s47 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s40 +; VI-NEXT: v_mov_b32_e32 v1, s44 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s41 +; VI-NEXT: v_mov_b32_e32 v1, s45 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s14 +; VI-NEXT: v_mov_b32_e32 v1, s42 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s15 +; VI-NEXT: v_mov_b32_e32 v1, s43 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s12 +; VI-NEXT: v_mov_b32_e32 v1, s40 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s13 +; VI-NEXT: v_mov_b32_e32 v1, s41 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s10 +; VI-NEXT: v_mov_b32_e32 v1, s24 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s11 +; VI-NEXT: v_mov_b32_e32 v1, s25 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s8 +; VI-NEXT: v_mov_b32_e32 v1, s22 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s9 +; VI-NEXT: v_mov_b32_e32 v1, s23 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s6 +; VI-NEXT: v_mov_b32_e32 v1, s20 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s7 +; VI-NEXT: v_mov_b32_e32 v1, s21 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s16 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v1, s17 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s18 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s19 +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v1, s10 +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v1, s8 +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v1, s6 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s20 +; VI-NEXT: v_mov_b32_e32 v1, s65 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s21 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s22 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s23 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s24 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s25 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s26 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s27 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s28 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s29 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v1, s55 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s85 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v1, s53 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s52 +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v1, s51 +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v1, s87 +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v1, s86 ; VI-NEXT: v_readlane_b32 s6, v62, 0 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v1, s6 ; VI-NEXT: v_readlane_b32 s6, v62, 1 -; VI-NEXT: v_mov_b32_e32 v36, s6 +; VI-NEXT: v_mov_b32_e32 v43, s6 ; VI-NEXT: v_readlane_b32 s6, v62, 2 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s6 +; VI-NEXT: v_mov_b32_e32 v52, s6 ; VI-NEXT: v_readlane_b32 s6, v62, 3 -; VI-NEXT: v_mov_b32_e32 v38, s6 +; VI-NEXT: v_mov_b32_e32 v45, s6 ; VI-NEXT: v_readlane_b32 s6, v62, 4 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v1, s6 ; VI-NEXT: v_readlane_b32 s6, v62, 5 -; VI-NEXT: v_mov_b32_e32 v61, s6 +; VI-NEXT: v_mov_b32_e32 v25, s6 ; VI-NEXT: v_readlane_b32 s6, v62, 6 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s6 +; VI-NEXT: v_mov_b32_e32 v8, s6 ; VI-NEXT: v_readlane_b32 s6, v62, 7 -; VI-NEXT: v_mov_b32_e32 v45, s6 +; VI-NEXT: v_mov_b32_e32 v5, s6 ; VI-NEXT: v_readlane_b32 s6, v62, 8 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s6 +; VI-NEXT: v_mov_b32_e32 v38, s6 ; VI-NEXT: v_readlane_b32 s6, v62, 9 -; VI-NEXT: v_mov_b32_e32 v47, s6 +; VI-NEXT: v_mov_b32_e32 v4, s6 ; VI-NEXT: v_readlane_b32 s6, v62, 10 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s6 +; VI-NEXT: v_mov_b32_e32 v48, s6 ; VI-NEXT: v_readlane_b32 s6, v62, 11 -; VI-NEXT: v_mov_b32_e32 v57, s6 +; VI-NEXT: v_mov_b32_e32 v37, s6 ; VI-NEXT: v_readlane_b32 s6, v62, 12 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v1, s6 ; VI-NEXT: v_readlane_b32 s6, v62, 13 -; VI-NEXT: v_mov_b32_e32 v59, s6 +; VI-NEXT: v_mov_b32_e32 v49, s6 ; VI-NEXT: v_readlane_b32 s6, v62, 14 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v1, s6 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v1, s4 +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v1, s5 +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v1, s84 +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v1, s83 +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v1, s82 +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v1, s81 ; VI-NEXT: v_readlane_b32 s4, v62, 16 -; VI-NEXT: v_mov_b32_e32 v2, s4 +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v1, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 17 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v1, s5 -; VI-NEXT: v_mov_b32_e32 v22, s4 +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v1, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 18 -; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v1, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 19 -; VI-NEXT: v_mov_b32_e32 v15, s4 +; VI-NEXT: v_mov_b32_e32 v29, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 20 -; VI-NEXT: v_mov_b32_e32 v12, s4 +; VI-NEXT: v_mov_b32_e32 v28, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 21 -; VI-NEXT: v_mov_b32_e32 v6, s4 +; VI-NEXT: v_mov_b32_e32 v23, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 22 -; VI-NEXT: v_mov_b32_e32 v27, s4 +; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v1, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 23 -; VI-NEXT: v_mov_b32_e32 v25, s4 +; VI-NEXT: v_mov_b32_e32 v27, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 24 -; VI-NEXT: v_mov_b32_e32 v3, s4 +; VI-NEXT: v_mov_b32_e32 v54, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 25 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v3, s4 +; VI-NEXT: v_mov_b32_e32 v21, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 26 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v3, s80 -; VI-NEXT: v_mov_b32_e32 v46, s4 +; VI-NEXT: v_mov_b32_e32 v20, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 27 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v3, s81 -; VI-NEXT: v_mov_b32_e32 v41, s4 +; VI-NEXT: v_mov_b32_e32 v22, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 28 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v3, s82 -; VI-NEXT: v_mov_b32_e32 v8, s4 +; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 29 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 30 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 31 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 32 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 33 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 34 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 35 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 36 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 37 -; VI-NEXT: v_mov_b32_e32 v7, s4 +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 38 -; VI-NEXT: v_mov_b32_e32 v10, s4 +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 39 -; VI-NEXT: v_mov_b32_e32 v42, s4 +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 40 -; VI-NEXT: v_mov_b32_e32 v56, s4 +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 41 -; VI-NEXT: v_mov_b32_e32 v58, s4 -; VI-NEXT: v_readlane_b32 s4, v62, 42 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v3, s4 +; VI-NEXT: v_readlane_b32 s4, v62, 42 +; VI-NEXT: v_mov_b32_e32 v10, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 43 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v3, s4 +; VI-NEXT: v_mov_b32_e32 v31, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 44 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v3, s4 +; VI-NEXT: v_mov_b32_e32 v9, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 45 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v3, s4 +; VI-NEXT: v_mov_b32_e32 v30, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 46 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v3, s4 +; VI-NEXT: v_mov_b32_e32 v33, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 47 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v3, s4 +; VI-NEXT: v_mov_b32_e32 v32, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 48 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v3, s4 +; VI-NEXT: v_mov_b32_e32 v12, s4 +; VI-NEXT: v_mov_b32_e32 v11, s90 +; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v11, s88 +; VI-NEXT: v_mov_b32_e32 v59, s14 +; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v58, s28 +; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill ; VI-NEXT: v_readlane_b32 s4, v62, 49 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v3, s4 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v3, s46 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v3, s78 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill ; VI-NEXT: v_readlane_b32 s4, v62, 50 -; VI-NEXT: v_mov_b32_e32 v33, s4 +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 51 -; VI-NEXT: v_mov_b32_e32 v32, s4 +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 52 -; VI-NEXT: v_mov_b32_e32 v29, s4 +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 53 -; VI-NEXT: v_mov_b32_e32 v28, s4 +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 54 -; VI-NEXT: v_mov_b32_e32 v34, s4 +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 55 -; VI-NEXT: v_mov_b32_e32 v31, s4 +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 56 -; VI-NEXT: v_mov_b32_e32 v3, s88 -; VI-NEXT: v_readlane_b32 s6, v62, 15 -; VI-NEXT: v_mov_b32_e32 v21, s4 +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v3, s4 ; VI-NEXT: v_readlane_b32 s4, v62, 57 -; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; VI-NEXT: v_mov_b32_e32 v40, s71 -; VI-NEXT: v_mov_b32_e32 v50, s70 -; VI-NEXT: v_mov_b32_e32 v54, s69 -; VI-NEXT: v_mov_b32_e32 v43, s68 -; VI-NEXT: v_mov_b32_e32 v49, s67 -; VI-NEXT: v_mov_b32_e32 v37, s66 -; VI-NEXT: v_mov_b32_e32 v55, s65 -; VI-NEXT: v_mov_b32_e32 v52, s64 -; VI-NEXT: v_mov_b32_e32 v53, s54 -; VI-NEXT: v_mov_b32_e32 v60, s87 -; VI-NEXT: v_mov_b32_e32 v39, s86 -; VI-NEXT: v_mov_b32_e32 v48, s84 -; VI-NEXT: v_mov_b32_e32 v51, s6 -; VI-NEXT: v_mov_b32_e32 v44, s83 -; VI-NEXT: v_mov_b32_e32 v11, s50 -; VI-NEXT: v_mov_b32_e32 v26, s51 -; VI-NEXT: v_mov_b32_e32 v35, s4 -; VI-NEXT: v_mov_b32_e32 v20, s76 -; VI-NEXT: v_mov_b32_e32 v19, s74 -; VI-NEXT: v_mov_b32_e32 v18, s72 -; VI-NEXT: v_mov_b32_e32 v17, s62 -; VI-NEXT: v_mov_b32_e32 v16, s60 -; VI-NEXT: v_mov_b32_e32 v13, s58 -; VI-NEXT: v_mov_b32_e32 v9, s56 -; VI-NEXT: v_mov_b32_e32 v3, s90 -; VI-NEXT: v_mov_b32_e32 v4, s30 -; VI-NEXT: v_mov_b32_e32 v5, s34 -; VI-NEXT: v_mov_b32_e32 v30, s36 -; VI-NEXT: v_mov_b32_e32 v24, s38 -; VI-NEXT: v_mov_b32_e32 v14, s48 +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v3, s4 +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v3, s34 +; VI-NEXT: v_mov_b32_e32 v11, s78 +; VI-NEXT: v_readlane_b32 s6, v62, 15 +; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; VI-NEXT: v_mov_b32_e32 v58, s26 +; VI-NEXT: v_mov_b32_e32 v2, s18 +; VI-NEXT: v_mov_b32_e32 v51, s19 +; VI-NEXT: v_mov_b32_e32 v55, s16 +; VI-NEXT: v_mov_b32_e32 v13, s15 +; VI-NEXT: v_mov_b32_e32 v41, s12 +; VI-NEXT: v_mov_b32_e32 v53, s13 +; VI-NEXT: v_mov_b32_e32 v57, s11 +; VI-NEXT: v_mov_b32_e32 v61, s9 +; VI-NEXT: v_mov_b32_e32 v56, s7 +; VI-NEXT: v_mov_b32_e32 v7, s71 +; VI-NEXT: v_mov_b32_e32 v60, s70 +; VI-NEXT: v_mov_b32_e32 v50, s69 +; VI-NEXT: v_mov_b32_e32 v40, s68 +; VI-NEXT: v_mov_b32_e32 v35, s67 +; VI-NEXT: v_mov_b32_e32 v0, s66 +; VI-NEXT: v_mov_b32_e32 v44, s64 +; VI-NEXT: v_mov_b32_e32 v46, s54 +; VI-NEXT: v_mov_b32_e32 v47, s52 +; VI-NEXT: v_mov_b32_e32 v36, s50 +; VI-NEXT: v_mov_b32_e32 v42, s6 +; VI-NEXT: v_mov_b32_e32 v34, s85 +; VI-NEXT: v_mov_b32_e32 v26, s80 +; VI-NEXT: v_mov_b32_e32 v24, s48 +; VI-NEXT: v_mov_b32_e32 v19, s38 +; VI-NEXT: v_mov_b32_e32 v6, s36 +; VI-NEXT: v_mov_b32_e32 v3, s30 +; VI-NEXT: v_mov_b32_e32 v18, s76 +; VI-NEXT: v_mov_b32_e32 v17, s74 +; VI-NEXT: v_mov_b32_e32 v16, s72 +; VI-NEXT: v_mov_b32_e32 v15, s62 +; VI-NEXT: v_mov_b32_e32 v14, s60 +; VI-NEXT: v_mov_b32_e32 v11, s58 +; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill ; VI-NEXT: .LBB95_5: ; %end -; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v58, 8, v58 -; VI-NEXT: v_lshlrev_b32_e32 v20, 8, v20 -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; VI-NEXT: v_or_b32_sdwa v2, v36, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v19, 8, v19 +; VI-NEXT: v_lshlrev_b32_e32 v58, 8, v10 +; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload ; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v18 +; VI-NEXT: v_or_b32_sdwa v58, v2, v58 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v29, 8, v29 +; VI-NEXT: v_or_b32_sdwa v29, v43, v29 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v17 +; VI-NEXT: v_or_b32_sdwa v17, v52, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v16, 8, v16 +; VI-NEXT: v_lshlrev_b32_e32 v15, 8, v15 +; VI-NEXT: v_or_b32_sdwa v15, v8, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; VI-NEXT: v_or_b32_sdwa v1, v61, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v1, v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v14, 8, v14 +; VI-NEXT: v_or_b32_sdwa v14, v38, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v8, 8, v34 +; VI-NEXT: v_or_b32_sdwa v8, v60, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_readlane_b32 s87, v63, 31 ; VI-NEXT: v_readlane_b32 s86, v63, 30 ; VI-NEXT: v_readlane_b32 s85, v63, 29 @@ -194827,356 +191055,350 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; VI-NEXT: v_readlane_b32 s31, v63, 1 ; VI-NEXT: v_readlane_b32 s30, v63, 0 ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v58, v23, v58 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v20, v23, v20 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v20, v58, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: buffer_store_dword v20, v0, s[0:3], 0 offen -; VI-NEXT: v_lshlrev_b32_e32 v20, 8, v46 -; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v20, v46, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v2, v20, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v20, vcc, 4, v0 -; VI-NEXT: buffer_store_dword v2, v20, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v56 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v2, v20, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v19, v20, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v2, v2, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v19, vcc, 8, v0 -; VI-NEXT: buffer_store_dword v2, v19, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v41 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v2, v19, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v19, 8, v22 -; VI-NEXT: v_or_b32_sdwa v19, v38, v19 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v2, v2, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v19, vcc, 12, v0 -; VI-NEXT: buffer_store_dword v2, v19, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v42 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v2, v19, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v18, v19, v18 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v2, v2, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v18, vcc, 16, v0 -; VI-NEXT: buffer_store_dword v2, v18, s[0:3], 0 offen -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v8 -; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v2, v8, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v10 -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v17 +; VI-NEXT: v_or_b32_sdwa v18, v10, v18 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v18, v58, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: buffer_store_dword v18, v39, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v31 +; VI-NEXT: v_or_b32_sdwa v18, v51, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v18, v18, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v29, vcc, 4, v39 +; VI-NEXT: buffer_store_dword v18, v29, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v9 +; VI-NEXT: v_or_b32_sdwa v18, v55, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v18, vcc, 8, v39 +; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen +; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload +; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v30 +; VI-NEXT: v_lshlrev_b32_e32 v18, 8, v28 +; VI-NEXT: v_or_b32_sdwa v18, v45, v18 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v2, v8, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; VI-NEXT: v_or_b32_sdwa v17, v2, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v17, v17, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v18, vcc, 12, v39 +; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen +; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v33 +; VI-NEXT: v_or_b32_sdwa v17, v59, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_or_b32_sdwa v16, v2, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v17, vcc, 16, v39 +; VI-NEXT: buffer_store_dword v16, v17, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v16, 8, v32 +; VI-NEXT: v_lshlrev_b32_e32 v17, 8, v23 +; VI-NEXT: v_or_b32_sdwa v16, v13, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v17, v25, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v16, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v17, vcc, 20, v39 +; VI-NEXT: buffer_store_dword v16, v17, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v16, 8, v12 +; VI-NEXT: v_or_b32_sdwa v16, v41, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v16, vcc, 24, v39 +; VI-NEXT: buffer_store_dword v15, v16, s[0:3], 0 offen +; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload +; VI-NEXT: v_lshlrev_b32_e32 v13, 8, v11 +; VI-NEXT: v_or_b32_sdwa v13, v48, v13 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v11, 8, v54 +; VI-NEXT: v_or_b32_sdwa v11, v37, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b32_e32 v15, 8, v2 +; VI-NEXT: v_or_b32_sdwa v15, v53, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v1, v15, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v15, vcc, 28, v39 +; VI-NEXT: buffer_store_dword v1, v15, s[0:3], 0 offen +; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload ; VI-NEXT: s_waitcnt vmcnt(1) ; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v15 -; VI-NEXT: v_or_b32_sdwa v2, v45, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v7 -; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v16 +; VI-NEXT: v_or_b32_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v1, v1, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v14, vcc, 32, v39 +; VI-NEXT: buffer_store_dword v1, v14, s[0:3], 0 offen +; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; VI-NEXT: v_lshlrev_b32_e32 v14, 8, v27 +; VI-NEXT: v_or_b32_sdwa v14, v4, v14 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v2, v7, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 +; VI-NEXT: v_or_b32_sdwa v1, v57, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v1, v1, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v14, vcc, 36, v39 +; VI-NEXT: buffer_store_dword v1, v14, s[0:3], 0 offen +; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload ; VI-NEXT: s_waitcnt vmcnt(1) ; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v12 -; VI-NEXT: v_or_b32_sdwa v2, v47, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; VI-NEXT: v_or_b32_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v1, v1, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v13, vcc, 40, v39 +; VI-NEXT: buffer_store_dword v1, v13, s[0:3], 0 offen ; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v13 ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v2, v7, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(1) ; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v6 -; VI-NEXT: v_or_b32_sdwa v2, v57, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; VI-NEXT: v_or_b32_sdwa v1, v61, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v1, v1, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v11, vcc, 44, v39 +; VI-NEXT: buffer_store_dword v1, v11, s[0:3], 0 offen ; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(4) ; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 +; VI-NEXT: s_waitcnt vmcnt(3) +; VI-NEXT: v_or_b32_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v9 -; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v2, v6, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v11, 8, v4 +; VI-NEXT: v_or_b32_sdwa v11, v2, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v1, v1, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v11, vcc, 48, v39 +; VI-NEXT: buffer_store_dword v1, v11, s[0:3], 0 offen ; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 +; VI-NEXT: v_lshlrev_b32_e32 v11, 8, v21 +; VI-NEXT: v_or_b32_sdwa v11, v49, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v27 -; VI-NEXT: v_or_b32_sdwa v2, v59, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 +; VI-NEXT: v_or_b32_sdwa v1, v56, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v1, v1, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v11, vcc, 52, v39 +; VI-NEXT: buffer_store_dword v1, v11, s[0:3], 0 offen ; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload ; VI-NEXT: s_waitcnt vmcnt(3) ; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; VI-NEXT: s_waitcnt vmcnt(2) ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v6 -; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b32_e32 v9, 8, v4 ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v2, v6, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; VI-NEXT: v_or_b32_sdwa v9, v2, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v1, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v9, vcc, 56, v39 +; VI-NEXT: buffer_store_dword v1, v9, s[0:3], 0 offen +; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; VI-NEXT: v_lshlrev_b32_e32 v9, 8, v20 +; VI-NEXT: v_or_b32_sdwa v9, v42, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: s_waitcnt vmcnt(1) ; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v25 -; VI-NEXT: v_or_b32_sdwa v2, v51, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 60, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v21 +; VI-NEXT: v_or_b32_sdwa v1, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v9, vcc, 60, v39 +; VI-NEXT: buffer_store_dword v1, v9, s[0:3], 0 offen +; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v26 ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v14 -; VI-NEXT: v_or_b32_sdwa v2, v40, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 64, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v35 +; VI-NEXT: v_or_b32_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v9, 8, v24 +; VI-NEXT: v_or_b32_sdwa v9, v7, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v1, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v9, vcc, 64, v39 +; VI-NEXT: buffer_store_dword v1, v9, s[0:3], 0 offen +; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v22 +; VI-NEXT: v_lshlrev_b32_e32 v7, 8, v19 +; VI-NEXT: v_or_b32_sdwa v7, v50, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v26 -; VI-NEXT: v_or_b32_sdwa v2, v50, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v34 +; VI-NEXT: v_or_b32_sdwa v1, v9, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v1, v1, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v8, vcc, 0x44, v39 +; VI-NEXT: buffer_store_dword v1, v8, s[0:3], 0 offen +; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v24 -; VI-NEXT: v_or_b32_sdwa v2, v54, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v31 +; VI-NEXT: v_or_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v1, v1, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x48, v39 +; VI-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen +; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_or_b32_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v11 -; VI-NEXT: v_or_b32_sdwa v2, v43, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0 -; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; VI-NEXT: v_lshlrev_b32_e32 v7, 8, v2 +; VI-NEXT: v_or_b32_sdwa v7, v40, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v1, v1, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x4c, v39 +; VI-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen +; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v29 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v30 -; VI-NEXT: v_or_b32_sdwa v2, v49, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v6 +; VI-NEXT: v_or_b32_sdwa v2, v35, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0 +; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v39 ; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v28 +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v44 -; VI-NEXT: v_or_b32_sdwa v2, v37, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 +; VI-NEXT: v_or_b32_sdwa v2, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0 +; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v39 ; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v33 -; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(3) +; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v0 +; VI-NEXT: s_waitcnt vmcnt(2) ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v5 -; VI-NEXT: v_or_b32_sdwa v2, v55, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v4 +; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0 +; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v39 ; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v32 -; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v0 +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(1) ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; VI-NEXT: v_or_b32_sdwa v2, v52, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v0 +; VI-NEXT: v_or_b32_sdwa v2, v44, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0 +; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v39 ; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload ; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v0 ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v4 -; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload +; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v3 +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0 +; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v39 ; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload ; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v0 +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(1) ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; VI-NEXT: v_or_b32_sdwa v2, v53, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v0 +; VI-NEXT: v_or_b32_sdwa v2, v46, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0 +; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v39 ; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload ; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v0 ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v3 -; VI-NEXT: v_or_b32_sdwa v2, v60, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) +; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0 +; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v39 ; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload ; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v0 +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(1) ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; VI-NEXT: v_or_b32_sdwa v2, v39, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v0 +; VI-NEXT: v_or_b32_sdwa v2, v47, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0 +; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v39 ; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v0 ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload ; VI-NEXT: s_waitcnt vmcnt(2) ; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0 +; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v39 ; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v0 +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(1) ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 -; VI-NEXT: v_or_b32_sdwa v2, v48, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v0 +; VI-NEXT: v_or_b32_sdwa v2, v36, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0 +; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v39 ; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload ; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v0 ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload ; VI-NEXT: s_waitcnt vmcnt(2) ; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0 +; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v39 ; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload -; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0 ; VI-NEXT: s_waitcnt vmcnt(2) -; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 -; VI-NEXT: s_waitcnt vmcnt(1) +; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v0 +; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(2) ; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD -; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2 +; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v0 ; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v39 ; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload @@ -195193,8 +191415,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload ; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload ; VI-NEXT: s_or_saveexec_b64 s[4:5], -1 -; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload ; VI-NEXT: s_mov_b64 exec, s[4:5] ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_setpc_b64 s[30:31] @@ -195241,26 +191463,54 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; GFX9-NEXT: v_writelane_b32 v63, s96, 32 ; GFX9-NEXT: v_writelane_b32 v63, s97, 33 ; GFX9-NEXT: v_writelane_b32 v63, s98, 34 +; GFX9-NEXT: v_readfirstlane_b32 s56, v3 +; GFX9-NEXT: v_mov_b32_e32 v3, s16 +; GFX9-NEXT: v_readfirstlane_b32 s57, v4 +; GFX9-NEXT: v_mov_b32_e32 v4, s17 +; GFX9-NEXT: v_readfirstlane_b32 s46, v5 +; GFX9-NEXT: v_mov_b32_e32 v5, s18 +; GFX9-NEXT: v_readfirstlane_b32 s47, v6 +; GFX9-NEXT: v_mov_b32_e32 v6, s19 +; GFX9-NEXT: v_readfirstlane_b32 s44, v7 +; GFX9-NEXT: v_mov_b32_e32 v7, s20 +; GFX9-NEXT: v_readfirstlane_b32 s45, v8 +; GFX9-NEXT: v_mov_b32_e32 v8, s21 +; GFX9-NEXT: v_readfirstlane_b32 s42, v9 +; GFX9-NEXT: v_mov_b32_e32 v9, s22 +; GFX9-NEXT: v_readfirstlane_b32 s43, v10 +; GFX9-NEXT: v_mov_b32_e32 v10, s23 +; GFX9-NEXT: v_readfirstlane_b32 s40, v11 +; GFX9-NEXT: v_mov_b32_e32 v11, s24 +; GFX9-NEXT: v_readfirstlane_b32 s41, v12 +; GFX9-NEXT: v_mov_b32_e32 v12, s25 +; GFX9-NEXT: v_readfirstlane_b32 s24, v13 +; GFX9-NEXT: v_mov_b32_e32 v13, s26 +; GFX9-NEXT: v_readfirstlane_b32 s25, v14 +; GFX9-NEXT: v_mov_b32_e32 v14, s27 +; GFX9-NEXT: v_readfirstlane_b32 s22, v15 +; GFX9-NEXT: v_mov_b32_e32 v15, s28 +; GFX9-NEXT: v_readfirstlane_b32 s23, v16 +; GFX9-NEXT: v_mov_b32_e32 v16, s29 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; GFX9-NEXT: v_writelane_b32 v63, s99, 35 -; GFX9-NEXT: v_readfirstlane_b32 s44, v3 -; GFX9-NEXT: v_readfirstlane_b32 s45, v4 -; GFX9-NEXT: v_readfirstlane_b32 s42, v5 -; GFX9-NEXT: v_readfirstlane_b32 s43, v6 -; GFX9-NEXT: v_readfirstlane_b32 s40, v7 -; GFX9-NEXT: v_readfirstlane_b32 s41, v8 -; GFX9-NEXT: v_readfirstlane_b32 s14, v9 -; GFX9-NEXT: v_readfirstlane_b32 s15, v10 -; GFX9-NEXT: v_readfirstlane_b32 s12, v11 -; GFX9-NEXT: v_readfirstlane_b32 s13, v12 -; GFX9-NEXT: v_readfirstlane_b32 s10, v13 -; GFX9-NEXT: v_readfirstlane_b32 s11, v14 -; GFX9-NEXT: v_readfirstlane_b32 s8, v15 -; GFX9-NEXT: v_readfirstlane_b32 s9, v16 -; GFX9-NEXT: v_readfirstlane_b32 s6, v17 -; GFX9-NEXT: v_readfirstlane_b32 s7, v18 +; GFX9-NEXT: v_readfirstlane_b32 s20, v17 +; GFX9-NEXT: v_readfirstlane_b32 s21, v18 +; GFX9-NEXT: v_readfirstlane_b32 s18, v3 +; GFX9-NEXT: v_readfirstlane_b32 s19, v4 +; GFX9-NEXT: v_readfirstlane_b32 s16, v5 +; GFX9-NEXT: v_readfirstlane_b32 s17, v6 +; GFX9-NEXT: v_readfirstlane_b32 s14, v7 +; GFX9-NEXT: v_readfirstlane_b32 s15, v8 +; GFX9-NEXT: v_readfirstlane_b32 s12, v9 +; GFX9-NEXT: v_readfirstlane_b32 s13, v10 +; GFX9-NEXT: v_readfirstlane_b32 s10, v11 +; GFX9-NEXT: v_readfirstlane_b32 s11, v12 +; GFX9-NEXT: v_readfirstlane_b32 s8, v13 +; GFX9-NEXT: v_readfirstlane_b32 s9, v14 +; GFX9-NEXT: v_readfirstlane_b32 s6, v15 +; GFX9-NEXT: v_readfirstlane_b32 s7, v16 ; GFX9-NEXT: v_readfirstlane_b32 s4, v1 -; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_and_b64 s[26:27], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s5, v2 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill @@ -195279,187 +191529,187 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; GFX9-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; GFX9-NEXT: s_cbranch_scc0 .LBB95_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false -; GFX9-NEXT: s_lshr_b32 s46, s5, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 49 -; GFX9-NEXT: s_lshr_b32 s46, s5, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 48 -; GFX9-NEXT: s_lshr_b32 s46, s5, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 47 -; GFX9-NEXT: s_lshr_b32 s46, s4, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 46 -; GFX9-NEXT: s_lshr_b32 s46, s4, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 45 -; GFX9-NEXT: s_lshr_b32 s46, s29, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 44 -; GFX9-NEXT: s_lshr_b32 s46, s29, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 43 -; GFX9-NEXT: s_lshr_b32 s46, s29, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 42 -; GFX9-NEXT: s_lshr_b32 s46, s28, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 41 -; GFX9-NEXT: s_lshr_b32 s46, s28, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 40 -; GFX9-NEXT: s_lshr_b32 s46, s27, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 39 -; GFX9-NEXT: s_lshr_b32 s46, s27, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 38 -; GFX9-NEXT: s_lshr_b32 s46, s27, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 37 -; GFX9-NEXT: s_lshr_b32 s46, s26, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 36 -; GFX9-NEXT: s_lshr_b32 s46, s26, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 35 -; GFX9-NEXT: s_lshr_b32 s46, s25, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 34 -; GFX9-NEXT: s_lshr_b32 s46, s25, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 33 -; GFX9-NEXT: s_lshr_b32 s46, s25, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 32 -; GFX9-NEXT: s_lshr_b32 s46, s24, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 31 -; GFX9-NEXT: s_lshr_b32 s46, s24, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 30 -; GFX9-NEXT: s_lshr_b32 s46, s23, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 29 -; GFX9-NEXT: s_lshr_b32 s46, s23, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 28 -; GFX9-NEXT: s_lshr_b32 s46, s23, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 27 -; GFX9-NEXT: s_lshr_b32 s46, s22, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 26 -; GFX9-NEXT: s_lshr_b32 s46, s22, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 25 -; GFX9-NEXT: s_lshr_b32 s46, s21, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 24 -; GFX9-NEXT: s_lshr_b32 s46, s21, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 23 -; GFX9-NEXT: s_lshr_b32 s46, s21, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 22 -; GFX9-NEXT: s_lshr_b32 s46, s20, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 21 -; GFX9-NEXT: s_lshr_b32 s46, s20, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 20 -; GFX9-NEXT: s_lshr_b32 s46, s19, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 19 -; GFX9-NEXT: s_lshr_b32 s46, s19, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 18 -; GFX9-NEXT: s_lshr_b32 s46, s19, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 17 -; GFX9-NEXT: s_lshr_b32 s46, s18, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 16 -; GFX9-NEXT: s_lshr_b32 s46, s18, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 15 -; GFX9-NEXT: s_lshr_b32 s46, s17, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 14 -; GFX9-NEXT: s_lshr_b32 s46, s17, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 13 -; GFX9-NEXT: s_lshr_b32 s46, s17, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 12 -; GFX9-NEXT: s_lshr_b32 s46, s16, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 11 -; GFX9-NEXT: s_lshr_b32 s46, s16, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 10 -; GFX9-NEXT: s_lshr_b32 s46, s7, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 9 -; GFX9-NEXT: s_lshr_b32 s46, s7, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 8 -; GFX9-NEXT: s_lshr_b32 s46, s7, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 7 -; GFX9-NEXT: s_lshr_b32 s46, s6, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 6 -; GFX9-NEXT: s_lshr_b32 s46, s6, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 5 -; GFX9-NEXT: s_lshr_b32 s46, s9, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 4 -; GFX9-NEXT: s_lshr_b32 s46, s9, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 3 -; GFX9-NEXT: s_lshr_b32 s46, s9, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 2 -; GFX9-NEXT: s_lshr_b32 s46, s8, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 1 -; GFX9-NEXT: s_lshr_b32 s46, s8, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 0 -; GFX9-NEXT: s_lshr_b32 s82, s11, 24 -; GFX9-NEXT: s_lshr_b32 s83, s11, 16 -; GFX9-NEXT: s_lshr_b32 s85, s11, 8 -; GFX9-NEXT: s_lshr_b32 s84, s10, 16 -; GFX9-NEXT: s_lshr_b32 s86, s10, 8 -; GFX9-NEXT: s_lshr_b32 s87, s13, 24 -; GFX9-NEXT: s_lshr_b32 s96, s13, 16 -; GFX9-NEXT: s_lshr_b32 s98, s13, 8 -; GFX9-NEXT: s_lshr_b32 s97, s12, 16 -; GFX9-NEXT: s_lshr_b32 s99, s12, 8 -; GFX9-NEXT: s_lshr_b32 s38, s15, 24 -; GFX9-NEXT: s_lshr_b32 s39, s15, 16 -; GFX9-NEXT: s_lshr_b32 s49, s15, 8 -; GFX9-NEXT: s_lshr_b32 s48, s14, 16 -; GFX9-NEXT: s_lshr_b32 s50, s14, 8 -; GFX9-NEXT: s_lshr_b32 s51, s41, 24 -; GFX9-NEXT: s_lshr_b32 s52, s41, 16 -; GFX9-NEXT: s_lshr_b32 s54, s41, 8 -; GFX9-NEXT: s_lshr_b32 s53, s40, 16 -; GFX9-NEXT: s_lshr_b32 s55, s40, 8 -; GFX9-NEXT: s_lshr_b32 s64, s43, 24 -; GFX9-NEXT: s_lshr_b32 s65, s43, 16 -; GFX9-NEXT: s_lshr_b32 s67, s43, 8 -; GFX9-NEXT: s_lshr_b32 s66, s42, 16 -; GFX9-NEXT: s_lshr_b32 s68, s42, 8 -; GFX9-NEXT: s_lshr_b32 s69, s45, 24 -; GFX9-NEXT: s_lshr_b32 s70, s45, 16 -; GFX9-NEXT: s_lshr_b32 s80, s45, 8 -; GFX9-NEXT: s_lshr_b32 s71, s44, 16 -; GFX9-NEXT: s_lshr_b32 s81, s44, 8 -; GFX9-NEXT: s_lshr_b64 s[46:47], s[4:5], 24 -; GFX9-NEXT: s_lshr_b64 s[56:57], s[28:29], 24 -; GFX9-NEXT: s_lshr_b64 s[58:59], s[26:27], 24 -; GFX9-NEXT: s_lshr_b64 s[60:61], s[24:25], 24 -; GFX9-NEXT: s_lshr_b64 s[62:63], s[22:23], 24 -; GFX9-NEXT: s_lshr_b64 s[72:73], s[20:21], 24 -; GFX9-NEXT: s_lshr_b64 s[74:75], s[18:19], 24 -; GFX9-NEXT: s_lshr_b64 s[76:77], s[16:17], 24 -; GFX9-NEXT: s_lshr_b64 s[78:79], s[6:7], 24 -; GFX9-NEXT: s_lshr_b64 s[88:89], s[8:9], 24 -; GFX9-NEXT: s_lshr_b64 s[90:91], s[10:11], 24 -; GFX9-NEXT: s_lshr_b64 s[92:93], s[12:13], 24 -; GFX9-NEXT: s_lshr_b64 s[94:95], s[14:15], 24 -; GFX9-NEXT: s_lshr_b64 s[30:31], s[40:41], 24 -; GFX9-NEXT: s_lshr_b64 s[34:35], s[42:43], 24 -; GFX9-NEXT: s_lshr_b64 s[36:37], s[44:45], 24 +; GFX9-NEXT: s_lshr_b32 s26, s5, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 49 +; GFX9-NEXT: s_lshr_b32 s26, s5, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 48 +; GFX9-NEXT: s_lshr_b32 s26, s5, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 47 +; GFX9-NEXT: s_lshr_b32 s26, s4, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 46 +; GFX9-NEXT: s_lshr_b32 s26, s4, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 45 +; GFX9-NEXT: s_lshr_b32 s26, s7, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 44 +; GFX9-NEXT: s_lshr_b32 s26, s7, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 43 +; GFX9-NEXT: s_lshr_b32 s26, s7, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 42 +; GFX9-NEXT: s_lshr_b32 s26, s6, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 41 +; GFX9-NEXT: s_lshr_b32 s26, s6, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 40 +; GFX9-NEXT: s_lshr_b32 s26, s9, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 39 +; GFX9-NEXT: s_lshr_b32 s26, s9, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 38 +; GFX9-NEXT: s_lshr_b32 s26, s9, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 37 +; GFX9-NEXT: s_lshr_b32 s26, s8, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 36 +; GFX9-NEXT: s_lshr_b32 s26, s8, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 35 +; GFX9-NEXT: s_lshr_b32 s26, s11, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 34 +; GFX9-NEXT: s_lshr_b32 s26, s11, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 33 +; GFX9-NEXT: s_lshr_b32 s26, s11, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 32 +; GFX9-NEXT: s_lshr_b32 s26, s10, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 31 +; GFX9-NEXT: s_lshr_b32 s26, s10, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 30 +; GFX9-NEXT: s_lshr_b32 s26, s13, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 29 +; GFX9-NEXT: s_lshr_b32 s26, s13, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 28 +; GFX9-NEXT: s_lshr_b32 s26, s13, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 27 +; GFX9-NEXT: s_lshr_b32 s26, s12, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 26 +; GFX9-NEXT: s_lshr_b32 s26, s12, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 25 +; GFX9-NEXT: s_lshr_b32 s26, s15, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 24 +; GFX9-NEXT: s_lshr_b32 s26, s15, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 23 +; GFX9-NEXT: s_lshr_b32 s26, s15, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 22 +; GFX9-NEXT: s_lshr_b32 s26, s14, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 21 +; GFX9-NEXT: s_lshr_b32 s26, s14, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 20 +; GFX9-NEXT: s_lshr_b32 s26, s17, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 19 +; GFX9-NEXT: s_lshr_b32 s26, s17, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 18 +; GFX9-NEXT: s_lshr_b32 s26, s17, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 17 +; GFX9-NEXT: s_lshr_b32 s26, s16, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 16 +; GFX9-NEXT: s_lshr_b32 s26, s16, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 15 +; GFX9-NEXT: s_lshr_b32 s26, s19, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 14 +; GFX9-NEXT: s_lshr_b32 s26, s19, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 13 +; GFX9-NEXT: s_lshr_b32 s26, s19, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 12 +; GFX9-NEXT: s_lshr_b32 s26, s18, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 11 +; GFX9-NEXT: s_lshr_b32 s26, s18, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 10 +; GFX9-NEXT: s_lshr_b32 s26, s21, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 9 +; GFX9-NEXT: s_lshr_b32 s26, s21, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 8 +; GFX9-NEXT: s_lshr_b32 s26, s21, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 7 +; GFX9-NEXT: s_lshr_b32 s26, s20, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 6 +; GFX9-NEXT: s_lshr_b32 s26, s20, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 5 +; GFX9-NEXT: s_lshr_b32 s26, s23, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 4 +; GFX9-NEXT: s_lshr_b32 s26, s23, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 3 +; GFX9-NEXT: s_lshr_b32 s26, s23, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 2 +; GFX9-NEXT: s_lshr_b32 s26, s22, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 1 +; GFX9-NEXT: s_lshr_b32 s26, s22, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 0 +; GFX9-NEXT: s_lshr_b32 s82, s25, 24 +; GFX9-NEXT: s_lshr_b32 s83, s25, 16 +; GFX9-NEXT: s_lshr_b32 s85, s25, 8 +; GFX9-NEXT: s_lshr_b32 s84, s24, 16 +; GFX9-NEXT: s_lshr_b32 s86, s24, 8 +; GFX9-NEXT: s_lshr_b32 s87, s41, 24 +; GFX9-NEXT: s_lshr_b32 s96, s41, 16 +; GFX9-NEXT: s_lshr_b32 s98, s41, 8 +; GFX9-NEXT: s_lshr_b32 s97, s40, 16 +; GFX9-NEXT: s_lshr_b32 s99, s40, 8 +; GFX9-NEXT: s_lshr_b32 s38, s43, 24 +; GFX9-NEXT: s_lshr_b32 s39, s43, 16 +; GFX9-NEXT: s_lshr_b32 s49, s43, 8 +; GFX9-NEXT: s_lshr_b32 s48, s42, 16 +; GFX9-NEXT: s_lshr_b32 s50, s42, 8 +; GFX9-NEXT: s_lshr_b32 s51, s45, 24 +; GFX9-NEXT: s_lshr_b32 s52, s45, 16 +; GFX9-NEXT: s_lshr_b32 s54, s45, 8 +; GFX9-NEXT: s_lshr_b32 s53, s44, 16 +; GFX9-NEXT: s_lshr_b32 s55, s44, 8 +; GFX9-NEXT: s_lshr_b32 s64, s47, 24 +; GFX9-NEXT: s_lshr_b32 s65, s47, 16 +; GFX9-NEXT: s_lshr_b32 s67, s47, 8 +; GFX9-NEXT: s_lshr_b32 s66, s46, 16 +; GFX9-NEXT: s_lshr_b32 s68, s46, 8 +; GFX9-NEXT: s_lshr_b32 s69, s57, 24 +; GFX9-NEXT: s_lshr_b32 s70, s57, 16 +; GFX9-NEXT: s_lshr_b32 s80, s57, 8 +; GFX9-NEXT: s_lshr_b32 s71, s56, 16 +; GFX9-NEXT: s_lshr_b32 s81, s56, 8 +; GFX9-NEXT: s_lshr_b64 s[26:27], s[4:5], 24 +; GFX9-NEXT: s_lshr_b64 s[28:29], s[6:7], 24 +; GFX9-NEXT: s_lshr_b64 s[58:59], s[8:9], 24 +; GFX9-NEXT: s_lshr_b64 s[60:61], s[10:11], 24 +; GFX9-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 +; GFX9-NEXT: s_lshr_b64 s[72:73], s[14:15], 24 +; GFX9-NEXT: s_lshr_b64 s[74:75], s[16:17], 24 +; GFX9-NEXT: s_lshr_b64 s[76:77], s[18:19], 24 +; GFX9-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 +; GFX9-NEXT: s_lshr_b64 s[88:89], s[22:23], 24 +; GFX9-NEXT: s_lshr_b64 s[90:91], s[24:25], 24 +; GFX9-NEXT: s_lshr_b64 s[92:93], s[40:41], 24 +; GFX9-NEXT: s_lshr_b64 s[94:95], s[42:43], 24 +; GFX9-NEXT: s_lshr_b64 s[30:31], s[44:45], 24 +; GFX9-NEXT: s_lshr_b64 s[34:35], s[46:47], 24 +; GFX9-NEXT: s_lshr_b64 s[36:37], s[56:57], 24 ; GFX9-NEXT: s_cbranch_execnz .LBB95_4 ; GFX9-NEXT: .LBB95_2: ; %cmp.true ; GFX9-NEXT: v_mov_b32_e32 v15, 0x200 ; GFX9-NEXT: v_pk_add_f16 v26, s5, v15 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_f16 v25, s4, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v22, s45, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v21, s44, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v14, s43, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v13, s42, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v12, s41, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v11, s40, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v10, s15, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v9, s14, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v8, s13, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v7, s12, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v6, s11, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v5, s10, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v4, s9, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v3, s8, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v2, s7, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v1, s6, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v49, s17, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v48, s16, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v38, s19, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v37, s18, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v36, s21, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v35, s20, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v34, s23, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v33, s22, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v32, s25, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v31, s24, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v30, s27, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v29, s26, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v28, s29, v15 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_f16 v27, s28, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v22, s57, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v21, s56, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v14, s47, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v13, s46, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v12, s45, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v11, s44, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v10, s43, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v9, s42, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v8, s41, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v7, s40, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v6, s25, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v5, s24, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v4, s23, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v3, s22, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v2, s21, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v1, s20, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v49, s19, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v48, s18, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v38, s17, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v37, s16, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v36, s15, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v35, s14, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v34, s13, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v33, s12, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v32, s11, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v31, s10, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v30, s9, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v29, s8, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v28, s7, v15 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_f16 v27, s6, v15 op_sel_hi:[1,0] ; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[25:26] ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 @@ -195658,10 +191908,10 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; GFX9-NEXT: v_lshrrev_b32_e32 v19, 8, v21 ; GFX9-NEXT: s_branch .LBB95_5 ; GFX9-NEXT: .LBB95_3: -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 ; GFX9-NEXT: ; implicit-def: $sgpr81 ; GFX9-NEXT: ; implicit-def: $sgpr71 ; GFX9-NEXT: ; implicit-def: $sgpr80 @@ -195698,7 +191948,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; GFX9-NEXT: ; implicit-def: $sgpr62 ; GFX9-NEXT: ; implicit-def: $sgpr60 ; GFX9-NEXT: ; implicit-def: $sgpr58 -; GFX9-NEXT: ; implicit-def: $sgpr56 +; GFX9-NEXT: ; implicit-def: $sgpr28 ; GFX9-NEXT: ; implicit-def: $sgpr36 ; GFX9-NEXT: ; implicit-def: $sgpr34 ; GFX9-NEXT: ; implicit-def: $sgpr30 @@ -195707,103 +191957,103 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; GFX9-NEXT: ; implicit-def: $sgpr90 ; GFX9-NEXT: ; implicit-def: $sgpr88 ; GFX9-NEXT: ; implicit-def: $sgpr78 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 ; GFX9-NEXT: s_branch .LBB95_2 ; GFX9-NEXT: .LBB95_4: ; GFX9-NEXT: v_mov_b32_e32 v15, s71 @@ -195988,11 +192238,11 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v41, s4 ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v41, s46 +; GFX9-NEXT: v_mov_b32_e32 v41, s26 ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v41, s56 +; GFX9-NEXT: v_mov_b32_e32 v41, s28 ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill @@ -196052,36 +192302,36 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v21, s44 -; GFX9-NEXT: v_mov_b32_e32 v22, s45 -; GFX9-NEXT: v_mov_b32_e32 v13, s42 -; GFX9-NEXT: v_mov_b32_e32 v14, s43 -; GFX9-NEXT: v_mov_b32_e32 v11, s40 -; GFX9-NEXT: v_mov_b32_e32 v12, s41 -; GFX9-NEXT: v_mov_b32_e32 v9, s14 -; GFX9-NEXT: v_mov_b32_e32 v10, s15 -; GFX9-NEXT: v_mov_b32_e32 v7, s12 -; GFX9-NEXT: v_mov_b32_e32 v8, s13 -; GFX9-NEXT: v_mov_b32_e32 v5, s10 -; GFX9-NEXT: v_mov_b32_e32 v6, s11 -; GFX9-NEXT: v_mov_b32_e32 v3, s8 -; GFX9-NEXT: v_mov_b32_e32 v4, s9 -; GFX9-NEXT: v_mov_b32_e32 v1, s6 -; GFX9-NEXT: v_mov_b32_e32 v2, s7 -; GFX9-NEXT: v_mov_b32_e32 v48, s16 -; GFX9-NEXT: v_mov_b32_e32 v49, s17 -; GFX9-NEXT: v_mov_b32_e32 v37, s18 -; GFX9-NEXT: v_mov_b32_e32 v38, s19 -; GFX9-NEXT: v_mov_b32_e32 v35, s20 -; GFX9-NEXT: v_mov_b32_e32 v36, s21 -; GFX9-NEXT: v_mov_b32_e32 v33, s22 -; GFX9-NEXT: v_mov_b32_e32 v34, s23 -; GFX9-NEXT: v_mov_b32_e32 v31, s24 -; GFX9-NEXT: v_mov_b32_e32 v32, s25 -; GFX9-NEXT: v_mov_b32_e32 v29, s26 -; GFX9-NEXT: v_mov_b32_e32 v30, s27 -; GFX9-NEXT: v_mov_b32_e32 v27, s28 -; GFX9-NEXT: v_mov_b32_e32 v28, s29 +; GFX9-NEXT: v_mov_b32_e32 v21, s56 +; GFX9-NEXT: v_mov_b32_e32 v22, s57 +; GFX9-NEXT: v_mov_b32_e32 v13, s46 +; GFX9-NEXT: v_mov_b32_e32 v14, s47 +; GFX9-NEXT: v_mov_b32_e32 v11, s44 +; GFX9-NEXT: v_mov_b32_e32 v12, s45 +; GFX9-NEXT: v_mov_b32_e32 v9, s42 +; GFX9-NEXT: v_mov_b32_e32 v10, s43 +; GFX9-NEXT: v_mov_b32_e32 v7, s40 +; GFX9-NEXT: v_mov_b32_e32 v8, s41 +; GFX9-NEXT: v_mov_b32_e32 v5, s24 +; GFX9-NEXT: v_mov_b32_e32 v6, s25 +; GFX9-NEXT: v_mov_b32_e32 v3, s22 +; GFX9-NEXT: v_mov_b32_e32 v4, s23 +; GFX9-NEXT: v_mov_b32_e32 v1, s20 +; GFX9-NEXT: v_mov_b32_e32 v2, s21 +; GFX9-NEXT: v_mov_b32_e32 v48, s18 +; GFX9-NEXT: v_mov_b32_e32 v49, s19 +; GFX9-NEXT: v_mov_b32_e32 v37, s16 +; GFX9-NEXT: v_mov_b32_e32 v38, s17 +; GFX9-NEXT: v_mov_b32_e32 v35, s14 +; GFX9-NEXT: v_mov_b32_e32 v36, s15 +; GFX9-NEXT: v_mov_b32_e32 v33, s12 +; GFX9-NEXT: v_mov_b32_e32 v34, s13 +; GFX9-NEXT: v_mov_b32_e32 v31, s10 +; GFX9-NEXT: v_mov_b32_e32 v32, s11 +; GFX9-NEXT: v_mov_b32_e32 v29, s8 +; GFX9-NEXT: v_mov_b32_e32 v30, s9 +; GFX9-NEXT: v_mov_b32_e32 v27, s6 +; GFX9-NEXT: v_mov_b32_e32 v28, s7 ; GFX9-NEXT: v_mov_b32_e32 v26, s5 ; GFX9-NEXT: v_mov_b32_e32 v41, v50 ; GFX9-NEXT: v_mov_b32_e32 v50, v51 @@ -196519,33 +192769,41 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; GFX11-NEXT: s_mov_b32 exec_lo, s4 ; GFX11-NEXT: v_writelane_b32 v75, s30, 0 ; GFX11-NEXT: v_writelane_b32 v76, s96, 0 +; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 -; GFX11-NEXT: v_readfirstlane_b32 s40, v1 -; GFX11-NEXT: v_readfirstlane_b32 s41, v2 ; GFX11-NEXT: v_writelane_b32 v75, s31, 1 ; GFX11-NEXT: v_writelane_b32 v76, s97, 1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-NEXT: v_readfirstlane_b32 s40, v16 +; GFX11-NEXT: v_readfirstlane_b32 s41, v17 +; GFX11-NEXT: v_readfirstlane_b32 s28, v1 +; GFX11-NEXT: v_writelane_b32 v75, s34, 2 +; GFX11-NEXT: v_writelane_b32 v76, s98, 2 +; GFX11-NEXT: v_readfirstlane_b32 s29, v2 ; GFX11-NEXT: v_readfirstlane_b32 s14, v3 ; GFX11-NEXT: v_readfirstlane_b32 s15, v4 +; GFX11-NEXT: v_writelane_b32 v75, s35, 3 +; GFX11-NEXT: v_writelane_b32 v76, s99, 3 ; GFX11-NEXT: v_readfirstlane_b32 s12, v5 -; GFX11-NEXT: v_writelane_b32 v75, s34, 2 -; GFX11-NEXT: v_writelane_b32 v76, s98, 2 ; GFX11-NEXT: v_readfirstlane_b32 s13, v6 ; GFX11-NEXT: v_readfirstlane_b32 s10, v7 +; GFX11-NEXT: v_writelane_b32 v75, s36, 4 +; GFX11-NEXT: v_writelane_b32 v76, s100, 4 ; GFX11-NEXT: v_readfirstlane_b32 s11, v8 -; GFX11-NEXT: v_writelane_b32 v75, s35, 3 -; GFX11-NEXT: v_writelane_b32 v76, s99, 3 ; GFX11-NEXT: v_readfirstlane_b32 s8, v9 ; GFX11-NEXT: v_readfirstlane_b32 s9, v10 +; GFX11-NEXT: v_writelane_b32 v75, s37, 5 +; GFX11-NEXT: v_writelane_b32 v76, s101, 5 ; GFX11-NEXT: v_readfirstlane_b32 s6, v11 -; GFX11-NEXT: v_writelane_b32 v75, s36, 4 -; GFX11-NEXT: v_writelane_b32 v76, s100, 4 ; GFX11-NEXT: v_readfirstlane_b32 s7, v12 ; GFX11-NEXT: v_readfirstlane_b32 s4, v13 +; GFX11-NEXT: v_writelane_b32 v75, s38, 6 +; GFX11-NEXT: v_writelane_b32 v76, s102, 6 ; GFX11-NEXT: v_readfirstlane_b32 s5, v14 -; GFX11-NEXT: v_writelane_b32 v75, s37, 5 -; GFX11-NEXT: v_writelane_b32 v76, s101, 5 ; GFX11-NEXT: s_mov_b32 s99, 0 ; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo +; GFX11-NEXT: v_writelane_b32 v75, s39, 7 +; GFX11-NEXT: v_writelane_b32 v76, s103, 7 ; GFX11-NEXT: s_clause 0x12 ; 76-byte Folded Spill ; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:72 ; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:68 @@ -196566,12 +192824,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:8 ; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:4 ; GFX11-NEXT: scratch_store_b32 off, v74, s32 -; GFX11-NEXT: v_writelane_b32 v75, s38, 6 -; GFX11-NEXT: v_writelane_b32 v76, s102, 6 ; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane ; GFX11-NEXT: ; implicit-def: $vgpr77 : SGPR spill to VGPR lane -; GFX11-NEXT: v_writelane_b32 v75, s39, 7 -; GFX11-NEXT: v_writelane_b32 v76, s103, 7 ; GFX11-NEXT: v_writelane_b32 v75, s48, 8 ; GFX11-NEXT: v_writelane_b32 v76, s104, 8 ; GFX11-NEXT: v_writelane_b32 v75, s49, 9 @@ -196656,19 +192910,19 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; GFX11-NEXT: s_lshr_b32 s87, s14, 8 ; GFX11-NEXT: v_writelane_b32 v78, s42, 29 ; GFX11-NEXT: s_lshr_b32 s42, s22, 16 -; GFX11-NEXT: s_lshr_b32 s96, s41, 24 -; GFX11-NEXT: s_lshr_b32 s97, s41, 16 -; GFX11-NEXT: s_lshr_b32 s100, s41, 8 +; GFX11-NEXT: s_lshr_b32 s96, s29, 24 +; GFX11-NEXT: s_lshr_b32 s97, s29, 16 +; GFX11-NEXT: s_lshr_b32 s100, s29, 8 ; GFX11-NEXT: v_writelane_b32 v78, s42, 28 ; GFX11-NEXT: s_lshr_b32 s42, s22, 8 -; GFX11-NEXT: s_lshr_b32 s98, s40, 16 -; GFX11-NEXT: s_lshr_b32 s101, s40, 8 -; GFX11-NEXT: s_lshr_b32 s102, s29, 24 +; GFX11-NEXT: s_lshr_b32 s98, s28, 16 +; GFX11-NEXT: s_lshr_b32 s101, s28, 8 +; GFX11-NEXT: s_lshr_b32 s102, s41, 24 ; GFX11-NEXT: v_writelane_b32 v78, s42, 27 ; GFX11-NEXT: s_lshr_b32 s42, s21, 24 -; GFX11-NEXT: s_lshr_b32 s103, s29, 16 -; GFX11-NEXT: s_lshr_b32 vcc_hi, s29, 8 -; GFX11-NEXT: s_lshr_b32 s104, s28, 16 +; GFX11-NEXT: s_lshr_b32 s103, s41, 16 +; GFX11-NEXT: s_lshr_b32 vcc_hi, s41, 8 +; GFX11-NEXT: s_lshr_b32 s104, s40, 16 ; GFX11-NEXT: v_writelane_b32 v78, s42, 26 ; GFX11-NEXT: s_lshr_b32 s42, s21, 16 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[26:27], 24 @@ -196691,8 +192945,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; GFX11-NEXT: s_lshr_b64 s[92:93], s[14:15], 24 ; GFX11-NEXT: v_writelane_b32 v78, s42, 22 ; GFX11-NEXT: s_lshr_b32 s42, s19, 24 -; GFX11-NEXT: s_lshr_b64 s[94:95], s[40:41], 24 -; GFX11-NEXT: s_lshr_b64 s[30:31], s[28:29], 24 +; GFX11-NEXT: s_lshr_b64 s[94:95], s[28:29], 24 +; GFX11-NEXT: s_lshr_b64 s[30:31], s[40:41], 24 ; GFX11-NEXT: v_writelane_b32 v78, s42, 21 ; GFX11-NEXT: s_lshr_b32 s42, s19, 16 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) @@ -196742,7 +192996,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; GFX11-NEXT: s_lshr_b32 s42, s0, 8 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: v_writelane_b32 v78, s42, 2 -; GFX11-NEXT: s_lshr_b32 s42, s28, 8 +; GFX11-NEXT: s_lshr_b32 s42, s40, 8 ; GFX11-NEXT: v_writelane_b32 v78, s74, 0 ; GFX11-NEXT: v_writelane_b32 v78, s75, 1 ; GFX11-NEXT: s_lshr_b64 s[74:75], s[4:5], 24 @@ -196759,10 +193013,10 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; GFX11-NEXT: v_pk_add_f16 v29, 0x200, s23 op_sel_hi:[0,1] ; GFX11-NEXT: v_pk_add_f16 v28, 0x200, s22 op_sel_hi:[0,1] ; GFX11-NEXT: v_pk_add_f16 v32, 0x200, s20 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v16, 0x200, s29 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s28 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v14, 0x200, s41 op_sel_hi:[0,1] -; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s40 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v16, 0x200, s41 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s40 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v14, 0x200, s29 op_sel_hi:[0,1] +; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s28 op_sel_hi:[0,1] ; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s15 op_sel_hi:[0,1] ; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s14 op_sel_hi:[0,1] ; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s13 op_sel_hi:[0,1] @@ -197022,8 +193276,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i ; GFX11-NEXT: v_dual_mov_b32 v52, s0 :: v_dual_mov_b32 v53, s1 ; GFX11-NEXT: v_readlane_b32 s0, v78, 2 ; GFX11-NEXT: v_mov_b32_e32 v71, s50 -; GFX11-NEXT: v_dual_mov_b32 v15, s28 :: v_dual_mov_b32 v16, s29 -; GFX11-NEXT: v_dual_mov_b32 v13, s40 :: v_dual_mov_b32 v14, s41 +; GFX11-NEXT: v_dual_mov_b32 v15, s40 :: v_dual_mov_b32 v16, s41 +; GFX11-NEXT: v_dual_mov_b32 v13, s28 :: v_dual_mov_b32 v14, s29 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_mov_b32_e32 v74, s0 ; GFX11-NEXT: v_readlane_b32 s0, v78, 3 @@ -216364,60 +212618,88 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; VI-NEXT: v_writelane_b32 v20, s83, 27 ; VI-NEXT: v_writelane_b32 v20, s84, 28 ; VI-NEXT: v_writelane_b32 v20, s85, 29 -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 -; VI-NEXT: v_writelane_b32 v20, s86, 30 -; VI-NEXT: v_readfirstlane_b32 s42, v3 -; VI-NEXT: v_readfirstlane_b32 s43, v4 -; VI-NEXT: v_readfirstlane_b32 s40, v5 -; VI-NEXT: v_readfirstlane_b32 s41, v6 +; VI-NEXT: v_readfirstlane_b32 s40, v3 +; VI-NEXT: v_mov_b32_e32 v3, s16 +; VI-NEXT: v_readfirstlane_b32 s41, v4 +; VI-NEXT: v_mov_b32_e32 v4, s17 +; VI-NEXT: v_readfirstlane_b32 s16, v5 +; VI-NEXT: v_mov_b32_e32 v5, s18 +; VI-NEXT: v_readfirstlane_b32 s17, v6 +; VI-NEXT: v_mov_b32_e32 v6, s19 ; VI-NEXT: v_readfirstlane_b32 s14, v7 +; VI-NEXT: v_mov_b32_e32 v7, s20 ; VI-NEXT: v_readfirstlane_b32 s15, v8 +; VI-NEXT: v_mov_b32_e32 v8, s21 ; VI-NEXT: v_readfirstlane_b32 s12, v9 +; VI-NEXT: v_mov_b32_e32 v9, s22 ; VI-NEXT: v_readfirstlane_b32 s13, v10 +; VI-NEXT: v_mov_b32_e32 v10, s23 ; VI-NEXT: v_readfirstlane_b32 s10, v11 +; VI-NEXT: v_mov_b32_e32 v11, s24 ; VI-NEXT: v_readfirstlane_b32 s11, v12 +; VI-NEXT: v_mov_b32_e32 v12, s25 ; VI-NEXT: v_readfirstlane_b32 s8, v13 +; VI-NEXT: v_mov_b32_e32 v13, s26 ; VI-NEXT: v_readfirstlane_b32 s9, v14 +; VI-NEXT: v_mov_b32_e32 v14, s27 ; VI-NEXT: v_readfirstlane_b32 s6, v15 +; VI-NEXT: v_mov_b32_e32 v15, s28 ; VI-NEXT: v_readfirstlane_b32 s7, v16 +; VI-NEXT: v_mov_b32_e32 v16, s29 +; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 +; VI-NEXT: v_writelane_b32 v20, s86, 30 ; VI-NEXT: v_readfirstlane_b32 s4, v17 ; VI-NEXT: v_readfirstlane_b32 s5, v18 -; VI-NEXT: v_readfirstlane_b32 s44, v1 +; VI-NEXT: v_readfirstlane_b32 s44, v3 +; VI-NEXT: v_readfirstlane_b32 s45, v4 +; VI-NEXT: v_readfirstlane_b32 s42, v5 +; VI-NEXT: v_readfirstlane_b32 s43, v6 +; VI-NEXT: v_readfirstlane_b32 s28, v7 +; VI-NEXT: v_readfirstlane_b32 s29, v8 +; VI-NEXT: v_readfirstlane_b32 s26, v9 +; VI-NEXT: v_readfirstlane_b32 s27, v10 +; VI-NEXT: v_readfirstlane_b32 s24, v11 +; VI-NEXT: v_readfirstlane_b32 s25, v12 +; VI-NEXT: v_readfirstlane_b32 s22, v13 +; VI-NEXT: v_readfirstlane_b32 s23, v14 +; VI-NEXT: v_readfirstlane_b32 s20, v15 +; VI-NEXT: v_readfirstlane_b32 s21, v16 +; VI-NEXT: v_readfirstlane_b32 s18, v1 ; VI-NEXT: s_and_b64 s[46:47], vcc, exec -; VI-NEXT: v_readfirstlane_b32 s45, v2 +; VI-NEXT: v_readfirstlane_b32 s19, v2 ; VI-NEXT: v_writelane_b32 v20, s87, 31 ; VI-NEXT: ; implicit-def: $vgpr21 : SGPR spill to VGPR lane ; VI-NEXT: s_cbranch_scc0 .LBB99_4 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_lshr_b32 s46, s45, 24 +; VI-NEXT: s_lshr_b32 s46, s19, 24 ; VI-NEXT: v_writelane_b32 v21, s46, 0 -; VI-NEXT: s_lshr_b32 s46, s45, 16 +; VI-NEXT: s_lshr_b32 s46, s19, 16 ; VI-NEXT: v_writelane_b32 v21, s46, 1 -; VI-NEXT: s_lshr_b32 s46, s45, 8 +; VI-NEXT: s_lshr_b32 s46, s19, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 2 -; VI-NEXT: s_lshr_b32 s46, s44, 16 +; VI-NEXT: s_lshr_b32 s46, s18, 16 ; VI-NEXT: v_writelane_b32 v21, s46, 3 -; VI-NEXT: s_lshr_b32 s46, s44, 8 +; VI-NEXT: s_lshr_b32 s46, s18, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 4 -; VI-NEXT: s_lshr_b32 s46, s29, 24 +; VI-NEXT: s_lshr_b32 s46, s21, 24 ; VI-NEXT: v_writelane_b32 v21, s46, 5 -; VI-NEXT: s_lshr_b32 s46, s29, 16 +; VI-NEXT: s_lshr_b32 s46, s21, 16 ; VI-NEXT: v_writelane_b32 v21, s46, 6 -; VI-NEXT: s_lshr_b32 s46, s29, 8 +; VI-NEXT: s_lshr_b32 s46, s21, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 7 -; VI-NEXT: s_lshr_b32 s46, s28, 16 +; VI-NEXT: s_lshr_b32 s46, s20, 16 ; VI-NEXT: v_writelane_b32 v21, s46, 8 -; VI-NEXT: s_lshr_b32 s46, s28, 8 +; VI-NEXT: s_lshr_b32 s46, s20, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 9 -; VI-NEXT: s_lshr_b32 s46, s27, 24 +; VI-NEXT: s_lshr_b32 s46, s23, 24 ; VI-NEXT: v_writelane_b32 v21, s46, 10 -; VI-NEXT: s_lshr_b32 s46, s27, 16 +; VI-NEXT: s_lshr_b32 s46, s23, 16 ; VI-NEXT: v_writelane_b32 v21, s46, 11 -; VI-NEXT: s_lshr_b32 s46, s27, 8 +; VI-NEXT: s_lshr_b32 s46, s23, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 12 -; VI-NEXT: s_lshr_b32 s46, s26, 16 +; VI-NEXT: s_lshr_b32 s46, s22, 16 ; VI-NEXT: v_writelane_b32 v21, s46, 13 -; VI-NEXT: s_lshr_b32 s46, s26, 8 +; VI-NEXT: s_lshr_b32 s46, s22, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 14 ; VI-NEXT: s_lshr_b32 s46, s25, 24 ; VI-NEXT: v_writelane_b32 v21, s46, 15 @@ -216429,17 +212711,17 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; VI-NEXT: v_writelane_b32 v21, s46, 18 ; VI-NEXT: s_lshr_b32 s46, s24, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 19 -; VI-NEXT: s_lshr_b32 s46, s23, 24 +; VI-NEXT: s_lshr_b32 s46, s27, 24 ; VI-NEXT: v_writelane_b32 v21, s46, 20 -; VI-NEXT: s_lshr_b32 s46, s23, 16 +; VI-NEXT: s_lshr_b32 s46, s27, 16 ; VI-NEXT: v_writelane_b32 v21, s46, 21 -; VI-NEXT: s_lshr_b32 s46, s23, 8 +; VI-NEXT: s_lshr_b32 s46, s27, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 22 -; VI-NEXT: s_lshr_b32 s46, s22, 16 +; VI-NEXT: s_lshr_b32 s46, s26, 16 ; VI-NEXT: v_writelane_b32 v21, s46, 23 -; VI-NEXT: s_lshr_b32 s46, s22, 8 +; VI-NEXT: s_lshr_b32 s46, s26, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 24 -; VI-NEXT: s_lshr_b32 s46, s21, 24 +; VI-NEXT: s_lshr_b32 s46, s29, 24 ; VI-NEXT: v_writelane_b32 v21, s46, 25 ; VI-NEXT: s_lshr_b32 s46, s5, 24 ; VI-NEXT: v_writelane_b32 v21, s46, 26 @@ -216501,58 +212783,50 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; VI-NEXT: v_writelane_b32 v21, s46, 54 ; VI-NEXT: s_lshr_b32 s46, s14, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 55 -; VI-NEXT: s_lshr_b32 s46, s41, 24 +; VI-NEXT: s_lshr_b32 s46, s17, 24 ; VI-NEXT: v_writelane_b32 v21, s46, 56 -; VI-NEXT: s_lshr_b32 s46, s41, 16 -; VI-NEXT: s_lshr_b32 s80, s21, 16 -; VI-NEXT: s_lshr_b32 s82, s21, 8 -; VI-NEXT: s_lshr_b32 s84, s20, 16 -; VI-NEXT: s_lshr_b32 s86, s20, 8 -; VI-NEXT: s_lshr_b32 s51, s19, 24 -; VI-NEXT: s_lshr_b32 s53, s19, 16 -; VI-NEXT: s_lshr_b32 s54, s19, 8 -; VI-NEXT: s_lshr_b32 s65, s18, 16 -; VI-NEXT: s_lshr_b32 s66, s18, 8 -; VI-NEXT: s_lshr_b32 s67, s17, 24 -; VI-NEXT: s_lshr_b32 s68, s17, 16 -; VI-NEXT: s_lshr_b32 s69, s17, 8 -; VI-NEXT: s_lshr_b32 s70, s16, 16 -; VI-NEXT: s_lshr_b32 s71, s16, 8 +; VI-NEXT: s_lshr_b32 s46, s17, 16 +; VI-NEXT: s_lshr_b32 s80, s29, 16 +; VI-NEXT: s_lshr_b32 s82, s29, 8 +; VI-NEXT: s_lshr_b32 s84, s28, 16 +; VI-NEXT: s_lshr_b32 s86, s28, 8 +; VI-NEXT: s_lshr_b32 s51, s43, 24 +; VI-NEXT: s_lshr_b32 s53, s43, 16 +; VI-NEXT: s_lshr_b32 s54, s43, 8 +; VI-NEXT: s_lshr_b32 s65, s42, 16 +; VI-NEXT: s_lshr_b32 s66, s42, 8 +; VI-NEXT: s_lshr_b32 s67, s45, 24 +; VI-NEXT: s_lshr_b32 s68, s45, 16 +; VI-NEXT: s_lshr_b32 s69, s45, 8 +; VI-NEXT: s_lshr_b32 s70, s44, 16 +; VI-NEXT: s_lshr_b32 s71, s44, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 57 -; VI-NEXT: s_lshr_b32 s81, s41, 8 -; VI-NEXT: s_lshr_b32 s83, s40, 16 -; VI-NEXT: s_lshr_b32 s85, s40, 8 -; VI-NEXT: s_lshr_b32 s87, s43, 24 -; VI-NEXT: s_lshr_b32 s50, s43, 16 -; VI-NEXT: s_lshr_b32 s52, s43, 8 -; VI-NEXT: s_lshr_b32 s55, s42, 16 -; VI-NEXT: s_lshr_b32 s64, s42, 8 -; VI-NEXT: s_lshr_b64 s[76:77], s[44:45], 24 -; VI-NEXT: s_lshr_b64 s[88:89], s[28:29], 24 -; VI-NEXT: s_lshr_b64 s[90:91], s[26:27], 24 +; VI-NEXT: s_lshr_b32 s81, s17, 8 +; VI-NEXT: s_lshr_b32 s83, s16, 16 +; VI-NEXT: s_lshr_b32 s85, s16, 8 +; VI-NEXT: s_lshr_b32 s87, s41, 24 +; VI-NEXT: s_lshr_b32 s50, s41, 16 +; VI-NEXT: s_lshr_b32 s52, s41, 8 +; VI-NEXT: s_lshr_b32 s55, s40, 16 +; VI-NEXT: s_lshr_b32 s64, s40, 8 +; VI-NEXT: s_lshr_b64 s[76:77], s[18:19], 24 +; VI-NEXT: s_lshr_b64 s[88:89], s[20:21], 24 +; VI-NEXT: s_lshr_b64 s[90:91], s[22:23], 24 ; VI-NEXT: s_lshr_b64 s[30:31], s[24:25], 24 -; VI-NEXT: s_lshr_b64 s[34:35], s[22:23], 24 -; VI-NEXT: s_lshr_b64 s[36:37], s[20:21], 24 -; VI-NEXT: s_lshr_b64 s[38:39], s[18:19], 24 -; VI-NEXT: s_lshr_b64 s[48:49], s[16:17], 24 +; VI-NEXT: s_lshr_b64 s[34:35], s[26:27], 24 +; VI-NEXT: s_lshr_b64 s[36:37], s[28:29], 24 +; VI-NEXT: s_lshr_b64 s[38:39], s[42:43], 24 +; VI-NEXT: s_lshr_b64 s[48:49], s[44:45], 24 ; VI-NEXT: s_lshr_b64 s[46:47], s[4:5], 24 ; VI-NEXT: s_lshr_b64 s[56:57], s[6:7], 24 ; VI-NEXT: s_lshr_b64 s[58:59], s[8:9], 24 ; VI-NEXT: s_lshr_b64 s[60:61], s[10:11], 24 ; VI-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 ; VI-NEXT: s_lshr_b64 s[72:73], s[14:15], 24 -; VI-NEXT: s_lshr_b64 s[74:75], s[40:41], 24 -; VI-NEXT: s_lshr_b64 s[78:79], s[42:43], 24 +; VI-NEXT: s_lshr_b64 s[74:75], s[16:17], 24 +; VI-NEXT: s_lshr_b64 s[78:79], s[40:41], 24 ; VI-NEXT: s_cbranch_execnz .LBB99_3 ; VI-NEXT: .LBB99_2: ; %cmp.true -; VI-NEXT: s_and_b32 s46, s43, 0xffff0000 -; VI-NEXT: s_add_i32 s43, s43, 3 -; VI-NEXT: s_and_b32 s43, s43, 0xffff -; VI-NEXT: s_or_b32 s43, s46, s43 -; VI-NEXT: s_and_b32 s46, s42, 0xffff0000 -; VI-NEXT: s_add_i32 s42, s42, 3 -; VI-NEXT: s_and_b32 s42, s42, 0xffff -; VI-NEXT: s_or_b32 s42, s46, s42 ; VI-NEXT: s_and_b32 s46, s41, 0xffff0000 ; VI-NEXT: s_add_i32 s41, s41, 3 ; VI-NEXT: s_and_b32 s41, s41, 0xffff @@ -216561,6 +212835,14 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; VI-NEXT: s_add_i32 s40, s40, 3 ; VI-NEXT: s_and_b32 s40, s40, 0xffff ; VI-NEXT: s_or_b32 s40, s46, s40 +; VI-NEXT: s_and_b32 s46, s17, 0xffff0000 +; VI-NEXT: s_add_i32 s17, s17, 3 +; VI-NEXT: s_and_b32 s17, s17, 0xffff +; VI-NEXT: s_or_b32 s17, s46, s17 +; VI-NEXT: s_and_b32 s46, s16, 0xffff0000 +; VI-NEXT: s_add_i32 s16, s16, 3 +; VI-NEXT: s_and_b32 s16, s16, 0xffff +; VI-NEXT: s_or_b32 s16, s46, s16 ; VI-NEXT: s_and_b32 s46, s15, 0xffff0000 ; VI-NEXT: s_add_i32 s15, s15, 3 ; VI-NEXT: s_and_b32 s15, s15, 0xffff @@ -216609,106 +212891,106 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; VI-NEXT: s_add_i32 s4, s4, 3 ; VI-NEXT: s_and_b32 s4, s4, 0xffff ; VI-NEXT: s_or_b32 s4, s46, s4 -; VI-NEXT: s_and_b32 s46, s17, 0xffff0000 -; VI-NEXT: s_add_i32 s17, s17, 3 -; VI-NEXT: s_and_b32 s17, s17, 0xffff -; VI-NEXT: s_or_b32 s17, s46, s17 -; VI-NEXT: s_and_b32 s46, s16, 0xffff0000 -; VI-NEXT: s_add_i32 s16, s16, 3 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_or_b32 s16, s46, s16 -; VI-NEXT: s_and_b32 s46, s19, 0xffff0000 -; VI-NEXT: s_add_i32 s19, s19, 3 -; VI-NEXT: s_and_b32 s19, s19, 0xffff -; VI-NEXT: s_or_b32 s19, s46, s19 -; VI-NEXT: s_and_b32 s46, s18, 0xffff0000 -; VI-NEXT: s_add_i32 s18, s18, 3 -; VI-NEXT: s_and_b32 s18, s18, 0xffff -; VI-NEXT: s_or_b32 s18, s46, s18 -; VI-NEXT: s_and_b32 s46, s21, 0xffff0000 -; VI-NEXT: s_add_i32 s21, s21, 3 -; VI-NEXT: s_and_b32 s21, s21, 0xffff -; VI-NEXT: s_or_b32 s21, s46, s21 -; VI-NEXT: s_and_b32 s46, s20, 0xffff0000 -; VI-NEXT: s_add_i32 s20, s20, 3 -; VI-NEXT: s_and_b32 s20, s20, 0xffff -; VI-NEXT: s_or_b32 s20, s46, s20 -; VI-NEXT: s_and_b32 s46, s23, 0xffff0000 -; VI-NEXT: s_add_i32 s23, s23, 3 -; VI-NEXT: s_and_b32 s23, s23, 0xffff -; VI-NEXT: s_or_b32 s23, s46, s23 -; VI-NEXT: s_and_b32 s46, s22, 0xffff0000 -; VI-NEXT: s_add_i32 s22, s22, 3 -; VI-NEXT: s_and_b32 s22, s22, 0xffff -; VI-NEXT: s_or_b32 s22, s46, s22 -; VI-NEXT: s_and_b32 s46, s25, 0xffff0000 -; VI-NEXT: s_add_i32 s25, s25, 3 -; VI-NEXT: s_and_b32 s25, s25, 0xffff -; VI-NEXT: s_or_b32 s25, s46, s25 -; VI-NEXT: s_and_b32 s46, s24, 0xffff0000 -; VI-NEXT: s_add_i32 s24, s24, 3 -; VI-NEXT: s_and_b32 s24, s24, 0xffff -; VI-NEXT: s_or_b32 s24, s46, s24 -; VI-NEXT: s_and_b32 s46, s27, 0xffff0000 -; VI-NEXT: s_add_i32 s27, s27, 3 -; VI-NEXT: s_and_b32 s27, s27, 0xffff -; VI-NEXT: s_or_b32 s27, s46, s27 -; VI-NEXT: s_and_b32 s46, s26, 0xffff0000 -; VI-NEXT: s_add_i32 s26, s26, 3 -; VI-NEXT: s_and_b32 s26, s26, 0xffff -; VI-NEXT: s_or_b32 s26, s46, s26 -; VI-NEXT: s_and_b32 s46, s29, 0xffff0000 -; VI-NEXT: s_add_i32 s29, s29, 3 -; VI-NEXT: s_and_b32 s29, s29, 0xffff -; VI-NEXT: s_or_b32 s29, s46, s29 -; VI-NEXT: s_and_b32 s46, s28, 0xffff0000 -; VI-NEXT: s_add_i32 s28, s28, 3 -; VI-NEXT: s_and_b32 s28, s28, 0xffff -; VI-NEXT: s_or_b32 s28, s46, s28 ; VI-NEXT: s_and_b32 s46, s45, 0xffff0000 ; VI-NEXT: s_add_i32 s45, s45, 3 ; VI-NEXT: s_and_b32 s45, s45, 0xffff ; VI-NEXT: s_or_b32 s45, s46, s45 ; VI-NEXT: s_and_b32 s46, s44, 0xffff0000 ; VI-NEXT: s_add_i32 s44, s44, 3 -; VI-NEXT: s_add_i32 s45, s45, 0x30000 ; VI-NEXT: s_and_b32 s44, s44, 0xffff ; VI-NEXT: s_or_b32 s44, s46, s44 -; VI-NEXT: s_lshr_b32 s46, s45, 24 +; VI-NEXT: s_and_b32 s46, s43, 0xffff0000 +; VI-NEXT: s_add_i32 s43, s43, 3 +; VI-NEXT: s_and_b32 s43, s43, 0xffff +; VI-NEXT: s_or_b32 s43, s46, s43 +; VI-NEXT: s_and_b32 s46, s42, 0xffff0000 +; VI-NEXT: s_add_i32 s42, s42, 3 +; VI-NEXT: s_and_b32 s42, s42, 0xffff +; VI-NEXT: s_or_b32 s42, s46, s42 +; VI-NEXT: s_and_b32 s46, s29, 0xffff0000 +; VI-NEXT: s_add_i32 s29, s29, 3 +; VI-NEXT: s_and_b32 s29, s29, 0xffff +; VI-NEXT: s_or_b32 s29, s46, s29 +; VI-NEXT: s_and_b32 s46, s28, 0xffff0000 +; VI-NEXT: s_add_i32 s28, s28, 3 +; VI-NEXT: s_and_b32 s28, s28, 0xffff +; VI-NEXT: s_or_b32 s28, s46, s28 +; VI-NEXT: s_and_b32 s46, s27, 0xffff0000 +; VI-NEXT: s_add_i32 s27, s27, 3 +; VI-NEXT: s_and_b32 s27, s27, 0xffff +; VI-NEXT: s_or_b32 s27, s46, s27 +; VI-NEXT: s_and_b32 s46, s26, 0xffff0000 +; VI-NEXT: s_add_i32 s26, s26, 3 +; VI-NEXT: s_and_b32 s26, s26, 0xffff +; VI-NEXT: s_or_b32 s26, s46, s26 +; VI-NEXT: s_and_b32 s46, s25, 0xffff0000 +; VI-NEXT: s_add_i32 s25, s25, 3 +; VI-NEXT: s_and_b32 s25, s25, 0xffff +; VI-NEXT: s_or_b32 s25, s46, s25 +; VI-NEXT: s_and_b32 s46, s24, 0xffff0000 +; VI-NEXT: s_add_i32 s24, s24, 3 +; VI-NEXT: s_and_b32 s24, s24, 0xffff +; VI-NEXT: s_or_b32 s24, s46, s24 +; VI-NEXT: s_and_b32 s46, s23, 0xffff0000 +; VI-NEXT: s_add_i32 s23, s23, 3 +; VI-NEXT: s_and_b32 s23, s23, 0xffff +; VI-NEXT: s_or_b32 s23, s46, s23 +; VI-NEXT: s_and_b32 s46, s22, 0xffff0000 +; VI-NEXT: s_add_i32 s22, s22, 3 +; VI-NEXT: s_and_b32 s22, s22, 0xffff +; VI-NEXT: s_or_b32 s22, s46, s22 +; VI-NEXT: s_and_b32 s46, s21, 0xffff0000 +; VI-NEXT: s_add_i32 s21, s21, 3 +; VI-NEXT: s_and_b32 s21, s21, 0xffff +; VI-NEXT: s_or_b32 s21, s46, s21 +; VI-NEXT: s_and_b32 s46, s20, 0xffff0000 +; VI-NEXT: s_add_i32 s20, s20, 3 +; VI-NEXT: s_and_b32 s20, s20, 0xffff +; VI-NEXT: s_or_b32 s20, s46, s20 +; VI-NEXT: s_and_b32 s46, s19, 0xffff0000 +; VI-NEXT: s_add_i32 s19, s19, 3 +; VI-NEXT: s_and_b32 s19, s19, 0xffff +; VI-NEXT: s_or_b32 s19, s46, s19 +; VI-NEXT: s_and_b32 s46, s18, 0xffff0000 +; VI-NEXT: s_add_i32 s18, s18, 3 +; VI-NEXT: s_add_i32 s19, s19, 0x30000 +; VI-NEXT: s_and_b32 s18, s18, 0xffff +; VI-NEXT: s_or_b32 s18, s46, s18 +; VI-NEXT: s_lshr_b32 s46, s19, 24 ; VI-NEXT: v_writelane_b32 v21, s46, 0 -; VI-NEXT: s_lshr_b32 s46, s45, 16 -; VI-NEXT: s_add_i32 s44, s44, 0x30000 +; VI-NEXT: s_lshr_b32 s46, s19, 16 +; VI-NEXT: s_add_i32 s18, s18, 0x30000 ; VI-NEXT: v_writelane_b32 v21, s46, 1 -; VI-NEXT: s_lshr_b32 s46, s45, 8 +; VI-NEXT: s_lshr_b32 s46, s19, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 2 -; VI-NEXT: s_lshr_b32 s46, s44, 16 -; VI-NEXT: s_add_i32 s29, s29, 0x30000 +; VI-NEXT: s_lshr_b32 s46, s18, 16 +; VI-NEXT: s_add_i32 s21, s21, 0x30000 ; VI-NEXT: v_writelane_b32 v21, s46, 3 -; VI-NEXT: s_lshr_b32 s46, s44, 8 +; VI-NEXT: s_lshr_b32 s46, s18, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 4 -; VI-NEXT: s_lshr_b32 s46, s29, 24 +; VI-NEXT: s_lshr_b32 s46, s21, 24 ; VI-NEXT: v_writelane_b32 v21, s46, 5 -; VI-NEXT: s_lshr_b32 s46, s29, 16 -; VI-NEXT: s_add_i32 s28, s28, 0x30000 +; VI-NEXT: s_lshr_b32 s46, s21, 16 +; VI-NEXT: s_add_i32 s20, s20, 0x30000 ; VI-NEXT: v_writelane_b32 v21, s46, 6 -; VI-NEXT: s_lshr_b32 s46, s29, 8 +; VI-NEXT: s_lshr_b32 s46, s21, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 7 -; VI-NEXT: s_lshr_b32 s46, s28, 16 -; VI-NEXT: s_add_i32 s27, s27, 0x30000 +; VI-NEXT: s_lshr_b32 s46, s20, 16 +; VI-NEXT: s_add_i32 s23, s23, 0x30000 ; VI-NEXT: v_writelane_b32 v21, s46, 8 -; VI-NEXT: s_lshr_b32 s46, s28, 8 +; VI-NEXT: s_lshr_b32 s46, s20, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 9 -; VI-NEXT: s_lshr_b32 s46, s27, 24 +; VI-NEXT: s_lshr_b32 s46, s23, 24 ; VI-NEXT: v_writelane_b32 v21, s46, 10 -; VI-NEXT: s_lshr_b32 s46, s27, 16 -; VI-NEXT: s_add_i32 s26, s26, 0x30000 +; VI-NEXT: s_lshr_b32 s46, s23, 16 +; VI-NEXT: s_add_i32 s22, s22, 0x30000 ; VI-NEXT: v_writelane_b32 v21, s46, 11 -; VI-NEXT: s_lshr_b32 s46, s27, 8 +; VI-NEXT: s_lshr_b32 s46, s23, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 12 -; VI-NEXT: s_lshr_b32 s46, s26, 16 +; VI-NEXT: s_lshr_b32 s46, s22, 16 ; VI-NEXT: s_add_i32 s25, s25, 0x30000 ; VI-NEXT: v_writelane_b32 v21, s46, 13 -; VI-NEXT: s_lshr_b32 s46, s26, 8 +; VI-NEXT: s_lshr_b32 s46, s22, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 14 ; VI-NEXT: s_lshr_b32 s46, s25, 24 ; VI-NEXT: v_writelane_b32 v21, s46, 15 @@ -216718,24 +213000,24 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; VI-NEXT: s_lshr_b32 s46, s25, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 17 ; VI-NEXT: s_lshr_b32 s46, s24, 16 -; VI-NEXT: s_add_i32 s23, s23, 0x30000 +; VI-NEXT: s_add_i32 s27, s27, 0x30000 ; VI-NEXT: v_writelane_b32 v21, s46, 18 ; VI-NEXT: s_lshr_b32 s46, s24, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 19 -; VI-NEXT: s_lshr_b32 s46, s23, 24 +; VI-NEXT: s_lshr_b32 s46, s27, 24 ; VI-NEXT: v_writelane_b32 v21, s46, 20 -; VI-NEXT: s_lshr_b32 s46, s23, 16 -; VI-NEXT: s_add_i32 s22, s22, 0x30000 +; VI-NEXT: s_lshr_b32 s46, s27, 16 +; VI-NEXT: s_add_i32 s26, s26, 0x30000 ; VI-NEXT: v_writelane_b32 v21, s46, 21 -; VI-NEXT: s_lshr_b32 s46, s23, 8 +; VI-NEXT: s_lshr_b32 s46, s27, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 22 -; VI-NEXT: s_lshr_b32 s46, s22, 16 -; VI-NEXT: s_add_i32 s21, s21, 0x30000 +; VI-NEXT: s_lshr_b32 s46, s26, 16 +; VI-NEXT: s_add_i32 s29, s29, 0x30000 ; VI-NEXT: v_writelane_b32 v21, s46, 23 -; VI-NEXT: s_lshr_b32 s46, s22, 8 +; VI-NEXT: s_lshr_b32 s46, s26, 8 ; VI-NEXT: s_add_i32 s5, s5, 0x30000 ; VI-NEXT: v_writelane_b32 v21, s46, 24 -; VI-NEXT: s_lshr_b32 s46, s21, 24 +; VI-NEXT: s_lshr_b32 s46, s29, 24 ; VI-NEXT: v_writelane_b32 v21, s46, 25 ; VI-NEXT: s_lshr_b32 s46, s5, 24 ; VI-NEXT: v_writelane_b32 v21, s46, 26 @@ -216805,313 +213087,313 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; VI-NEXT: s_lshr_b32 s46, s15, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 53 ; VI-NEXT: s_lshr_b32 s46, s14, 16 -; VI-NEXT: s_add_i32 s41, s41, 0x30000 +; VI-NEXT: s_add_i32 s17, s17, 0x30000 ; VI-NEXT: v_writelane_b32 v21, s46, 54 ; VI-NEXT: s_lshr_b32 s46, s14, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 55 -; VI-NEXT: s_lshr_b32 s46, s41, 24 -; VI-NEXT: s_add_i32 s43, s43, 0x30000 -; VI-NEXT: s_add_i32 s42, s42, 0x30000 +; VI-NEXT: s_lshr_b32 s46, s17, 24 +; VI-NEXT: s_add_i32 s41, s41, 0x30000 ; VI-NEXT: s_add_i32 s40, s40, 0x30000 -; VI-NEXT: s_add_i32 s17, s17, 0x30000 ; VI-NEXT: s_add_i32 s16, s16, 0x30000 -; VI-NEXT: s_add_i32 s19, s19, 0x30000 -; VI-NEXT: s_add_i32 s18, s18, 0x30000 -; VI-NEXT: s_add_i32 s20, s20, 0x30000 +; VI-NEXT: s_add_i32 s45, s45, 0x30000 +; VI-NEXT: s_add_i32 s44, s44, 0x30000 +; VI-NEXT: s_add_i32 s43, s43, 0x30000 +; VI-NEXT: s_add_i32 s42, s42, 0x30000 +; VI-NEXT: s_add_i32 s28, s28, 0x30000 ; VI-NEXT: v_writelane_b32 v21, s46, 56 -; VI-NEXT: s_lshr_b32 s46, s41, 16 -; VI-NEXT: s_lshr_b32 s80, s21, 16 -; VI-NEXT: s_lshr_b32 s82, s21, 8 -; VI-NEXT: s_lshr_b32 s84, s20, 16 -; VI-NEXT: s_lshr_b32 s86, s20, 8 -; VI-NEXT: s_lshr_b32 s51, s19, 24 -; VI-NEXT: s_lshr_b32 s53, s19, 16 -; VI-NEXT: s_lshr_b32 s54, s19, 8 -; VI-NEXT: s_lshr_b32 s65, s18, 16 -; VI-NEXT: s_lshr_b32 s66, s18, 8 -; VI-NEXT: s_lshr_b32 s67, s17, 24 -; VI-NEXT: s_lshr_b32 s68, s17, 16 -; VI-NEXT: s_lshr_b32 s69, s17, 8 -; VI-NEXT: s_lshr_b32 s70, s16, 16 -; VI-NEXT: s_lshr_b32 s71, s16, 8 +; VI-NEXT: s_lshr_b32 s46, s17, 16 +; VI-NEXT: s_lshr_b32 s80, s29, 16 +; VI-NEXT: s_lshr_b32 s82, s29, 8 +; VI-NEXT: s_lshr_b32 s84, s28, 16 +; VI-NEXT: s_lshr_b32 s86, s28, 8 +; VI-NEXT: s_lshr_b32 s51, s43, 24 +; VI-NEXT: s_lshr_b32 s53, s43, 16 +; VI-NEXT: s_lshr_b32 s54, s43, 8 +; VI-NEXT: s_lshr_b32 s65, s42, 16 +; VI-NEXT: s_lshr_b32 s66, s42, 8 +; VI-NEXT: s_lshr_b32 s67, s45, 24 +; VI-NEXT: s_lshr_b32 s68, s45, 16 +; VI-NEXT: s_lshr_b32 s69, s45, 8 +; VI-NEXT: s_lshr_b32 s70, s44, 16 +; VI-NEXT: s_lshr_b32 s71, s44, 8 ; VI-NEXT: v_writelane_b32 v21, s46, 57 -; VI-NEXT: s_lshr_b32 s81, s41, 8 -; VI-NEXT: s_lshr_b32 s83, s40, 16 -; VI-NEXT: s_lshr_b32 s85, s40, 8 -; VI-NEXT: s_lshr_b32 s87, s43, 24 -; VI-NEXT: s_lshr_b32 s50, s43, 16 -; VI-NEXT: s_lshr_b32 s52, s43, 8 -; VI-NEXT: s_lshr_b32 s55, s42, 16 -; VI-NEXT: s_lshr_b32 s64, s42, 8 -; VI-NEXT: s_lshr_b64 s[76:77], s[44:45], 24 -; VI-NEXT: s_lshr_b64 s[88:89], s[28:29], 24 -; VI-NEXT: s_lshr_b64 s[90:91], s[26:27], 24 +; VI-NEXT: s_lshr_b32 s81, s17, 8 +; VI-NEXT: s_lshr_b32 s83, s16, 16 +; VI-NEXT: s_lshr_b32 s85, s16, 8 +; VI-NEXT: s_lshr_b32 s87, s41, 24 +; VI-NEXT: s_lshr_b32 s50, s41, 16 +; VI-NEXT: s_lshr_b32 s52, s41, 8 +; VI-NEXT: s_lshr_b32 s55, s40, 16 +; VI-NEXT: s_lshr_b32 s64, s40, 8 +; VI-NEXT: s_lshr_b64 s[76:77], s[18:19], 24 +; VI-NEXT: s_lshr_b64 s[88:89], s[20:21], 24 +; VI-NEXT: s_lshr_b64 s[90:91], s[22:23], 24 ; VI-NEXT: s_lshr_b64 s[30:31], s[24:25], 24 -; VI-NEXT: s_lshr_b64 s[34:35], s[22:23], 24 -; VI-NEXT: s_lshr_b64 s[36:37], s[20:21], 24 -; VI-NEXT: s_lshr_b64 s[38:39], s[18:19], 24 -; VI-NEXT: s_lshr_b64 s[48:49], s[16:17], 24 +; VI-NEXT: s_lshr_b64 s[34:35], s[26:27], 24 +; VI-NEXT: s_lshr_b64 s[36:37], s[28:29], 24 +; VI-NEXT: s_lshr_b64 s[38:39], s[42:43], 24 +; VI-NEXT: s_lshr_b64 s[48:49], s[44:45], 24 ; VI-NEXT: s_lshr_b64 s[46:47], s[4:5], 24 ; VI-NEXT: s_lshr_b64 s[56:57], s[6:7], 24 ; VI-NEXT: s_lshr_b64 s[58:59], s[8:9], 24 ; VI-NEXT: s_lshr_b64 s[60:61], s[10:11], 24 ; VI-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 ; VI-NEXT: s_lshr_b64 s[72:73], s[14:15], 24 -; VI-NEXT: s_lshr_b64 s[74:75], s[40:41], 24 -; VI-NEXT: s_lshr_b64 s[78:79], s[42:43], 24 +; VI-NEXT: s_lshr_b64 s[74:75], s[16:17], 24 +; VI-NEXT: s_lshr_b64 s[78:79], s[40:41], 24 ; VI-NEXT: .LBB99_3: ; %end ; VI-NEXT: s_lshl_b32 s47, s71, 8 -; VI-NEXT: s_and_b32 s16, s16, 0xff -; VI-NEXT: s_or_b32 s16, s16, s47 +; VI-NEXT: s_and_b32 s44, s44, 0xff +; VI-NEXT: s_or_b32 s44, s44, s47 ; VI-NEXT: s_lshl_b32 s47, s48, 8 ; VI-NEXT: s_and_b32 s57, s70, 0xff ; VI-NEXT: s_or_b32 s47, s57, s47 -; VI-NEXT: s_and_b32 s16, s16, 0xffff +; VI-NEXT: s_and_b32 s44, s44, 0xffff ; VI-NEXT: s_lshl_b32 s47, s47, 16 -; VI-NEXT: s_or_b32 s16, s16, s47 -; VI-NEXT: v_mov_b32_e32 v1, s16 -; VI-NEXT: s_and_b32 s16, s17, 0xff -; VI-NEXT: s_lshl_b32 s17, s69, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, s68, 0xff +; VI-NEXT: s_or_b32 s44, s44, s47 +; VI-NEXT: v_mov_b32_e32 v1, s44 +; VI-NEXT: s_and_b32 s44, s45, 0xff +; VI-NEXT: s_lshl_b32 s45, s69, 8 +; VI-NEXT: s_or_b32 s44, s44, s45 +; VI-NEXT: s_and_b32 s45, s68, 0xff ; VI-NEXT: s_lshl_b32 s47, s67, 8 -; VI-NEXT: s_or_b32 s17, s17, s47 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: s_lshl_b32 s16, s66, 8 -; VI-NEXT: s_and_b32 s17, s18, 0xff -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s38, 8 -; VI-NEXT: s_and_b32 s18, s65, 0xff -; VI-NEXT: s_or_b32 s17, s18, s17 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v3, s16 -; VI-NEXT: s_and_b32 s16, s19, 0xff -; VI-NEXT: s_lshl_b32 s17, s54, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, s53, 0xff -; VI-NEXT: s_lshl_b32 s18, s51, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v4, s16 -; VI-NEXT: s_lshl_b32 s16, s86, 8 -; VI-NEXT: s_and_b32 s17, s20, 0xff -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s36, 8 -; VI-NEXT: s_and_b32 s18, s84, 0xff -; VI-NEXT: s_or_b32 s17, s18, s17 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v5, s16 -; VI-NEXT: s_and_b32 s16, s21, 0xff -; VI-NEXT: s_lshl_b32 s17, s82, 8 -; VI-NEXT: v_readlane_b32 s18, v21, 25 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, s80, 0xff -; VI-NEXT: s_lshl_b32 s18, s18, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v6, s16 -; VI-NEXT: v_readlane_b32 s16, v21, 24 -; VI-NEXT: s_lshl_b32 s16, s16, 8 -; VI-NEXT: s_and_b32 s17, s22, 0xff -; VI-NEXT: v_readlane_b32 s18, v21, 23 -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s34, 8 -; VI-NEXT: s_and_b32 s18, s18, 0xff -; VI-NEXT: s_or_b32 s17, s18, s17 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 22 -; VI-NEXT: v_mov_b32_e32 v7, s16 -; VI-NEXT: s_and_b32 s16, s23, 0xff -; VI-NEXT: s_lshl_b32 s17, s17, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 21 -; VI-NEXT: v_readlane_b32 s18, v21, 20 -; VI-NEXT: s_and_b32 s17, s17, 0xff -; VI-NEXT: s_lshl_b32 s18, s18, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v8, s16 -; VI-NEXT: v_readlane_b32 s16, v21, 19 -; VI-NEXT: s_lshl_b32 s16, s16, 8 -; VI-NEXT: s_and_b32 s17, s24, 0xff -; VI-NEXT: v_readlane_b32 s18, v21, 18 -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s30, 8 -; VI-NEXT: s_and_b32 s18, s18, 0xff -; VI-NEXT: s_or_b32 s17, s18, s17 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 17 -; VI-NEXT: v_mov_b32_e32 v9, s16 -; VI-NEXT: s_and_b32 s16, s25, 0xff -; VI-NEXT: s_lshl_b32 s17, s17, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 16 -; VI-NEXT: v_readlane_b32 s18, v21, 15 -; VI-NEXT: s_and_b32 s17, s17, 0xff -; VI-NEXT: s_lshl_b32 s18, s18, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v10, s16 -; VI-NEXT: v_readlane_b32 s16, v21, 14 -; VI-NEXT: s_lshl_b32 s16, s16, 8 -; VI-NEXT: s_and_b32 s17, s26, 0xff -; VI-NEXT: v_readlane_b32 s18, v21, 13 -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s90, 8 -; VI-NEXT: s_and_b32 s18, s18, 0xff -; VI-NEXT: s_or_b32 s17, s18, s17 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 12 -; VI-NEXT: v_mov_b32_e32 v11, s16 -; VI-NEXT: s_and_b32 s16, s27, 0xff -; VI-NEXT: s_lshl_b32 s17, s17, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 11 -; VI-NEXT: v_readlane_b32 s18, v21, 10 -; VI-NEXT: s_and_b32 s17, s17, 0xff -; VI-NEXT: s_lshl_b32 s18, s18, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v12, s16 -; VI-NEXT: v_readlane_b32 s16, v21, 9 -; VI-NEXT: s_lshl_b32 s16, s16, 8 -; VI-NEXT: s_and_b32 s17, s28, 0xff -; VI-NEXT: v_readlane_b32 s18, v21, 8 -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s88, 8 -; VI-NEXT: s_and_b32 s18, s18, 0xff -; VI-NEXT: s_or_b32 s17, s18, s17 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 7 -; VI-NEXT: v_mov_b32_e32 v13, s16 -; VI-NEXT: s_and_b32 s16, s29, 0xff -; VI-NEXT: s_lshl_b32 s17, s17, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 6 -; VI-NEXT: v_readlane_b32 s18, v21, 5 -; VI-NEXT: s_and_b32 s17, s17, 0xff -; VI-NEXT: s_lshl_b32 s18, s18, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_mov_b32_e32 v14, s16 -; VI-NEXT: v_readlane_b32 s16, v21, 4 -; VI-NEXT: s_lshl_b32 s16, s16, 8 -; VI-NEXT: s_and_b32 s17, s44, 0xff -; VI-NEXT: v_readlane_b32 s18, v21, 3 -; VI-NEXT: s_or_b32 s16, s17, s16 -; VI-NEXT: s_lshl_b32 s17, s76, 8 +; VI-NEXT: s_or_b32 s45, s45, s47 +; VI-NEXT: s_and_b32 s44, s44, 0xffff +; VI-NEXT: s_lshl_b32 s45, s45, 16 +; VI-NEXT: s_or_b32 s44, s44, s45 +; VI-NEXT: v_mov_b32_e32 v2, s44 +; VI-NEXT: s_lshl_b32 s44, s66, 8 +; VI-NEXT: s_and_b32 s42, s42, 0xff +; VI-NEXT: s_or_b32 s42, s42, s44 +; VI-NEXT: s_lshl_b32 s44, s38, 8 +; VI-NEXT: s_and_b32 s45, s65, 0xff +; VI-NEXT: s_or_b32 s44, s45, s44 +; VI-NEXT: s_and_b32 s42, s42, 0xffff +; VI-NEXT: s_lshl_b32 s44, s44, 16 +; VI-NEXT: s_or_b32 s42, s42, s44 +; VI-NEXT: v_mov_b32_e32 v3, s42 +; VI-NEXT: s_and_b32 s42, s43, 0xff +; VI-NEXT: s_lshl_b32 s43, s54, 8 +; VI-NEXT: s_or_b32 s42, s42, s43 +; VI-NEXT: s_and_b32 s43, s53, 0xff +; VI-NEXT: s_lshl_b32 s44, s51, 8 +; VI-NEXT: s_or_b32 s43, s43, s44 +; VI-NEXT: s_and_b32 s42, s42, 0xffff +; VI-NEXT: s_lshl_b32 s43, s43, 16 +; VI-NEXT: s_or_b32 s42, s42, s43 +; VI-NEXT: v_mov_b32_e32 v4, s42 +; VI-NEXT: s_lshl_b32 s42, s86, 8 +; VI-NEXT: s_and_b32 s28, s28, 0xff +; VI-NEXT: s_or_b32 s28, s28, s42 +; VI-NEXT: s_lshl_b32 s42, s36, 8 +; VI-NEXT: s_and_b32 s43, s84, 0xff +; VI-NEXT: s_or_b32 s42, s43, s42 +; VI-NEXT: s_and_b32 s28, s28, 0xffff +; VI-NEXT: s_lshl_b32 s42, s42, 16 +; VI-NEXT: s_or_b32 s28, s28, s42 +; VI-NEXT: v_mov_b32_e32 v5, s28 +; VI-NEXT: s_and_b32 s28, s29, 0xff +; VI-NEXT: s_lshl_b32 s29, s82, 8 +; VI-NEXT: v_readlane_b32 s42, v21, 25 +; VI-NEXT: s_or_b32 s28, s28, s29 +; VI-NEXT: s_and_b32 s29, s80, 0xff +; VI-NEXT: s_lshl_b32 s42, s42, 8 +; VI-NEXT: s_or_b32 s29, s29, s42 +; VI-NEXT: s_and_b32 s28, s28, 0xffff +; VI-NEXT: s_lshl_b32 s29, s29, 16 +; VI-NEXT: s_or_b32 s28, s28, s29 +; VI-NEXT: v_mov_b32_e32 v6, s28 +; VI-NEXT: v_readlane_b32 s28, v21, 24 +; VI-NEXT: s_lshl_b32 s28, s28, 8 +; VI-NEXT: s_and_b32 s26, s26, 0xff +; VI-NEXT: v_readlane_b32 s29, v21, 23 +; VI-NEXT: s_or_b32 s26, s26, s28 +; VI-NEXT: s_lshl_b32 s28, s34, 8 +; VI-NEXT: s_and_b32 s29, s29, 0xff +; VI-NEXT: s_or_b32 s28, s29, s28 +; VI-NEXT: s_and_b32 s26, s26, 0xffff +; VI-NEXT: s_lshl_b32 s28, s28, 16 +; VI-NEXT: s_or_b32 s26, s26, s28 +; VI-NEXT: v_mov_b32_e32 v7, s26 +; VI-NEXT: s_and_b32 s26, s27, 0xff +; VI-NEXT: v_readlane_b32 s27, v21, 22 +; VI-NEXT: s_lshl_b32 s27, s27, 8 +; VI-NEXT: s_or_b32 s26, s26, s27 +; VI-NEXT: v_readlane_b32 s27, v21, 21 +; VI-NEXT: v_readlane_b32 s28, v21, 20 +; VI-NEXT: s_and_b32 s27, s27, 0xff +; VI-NEXT: s_lshl_b32 s28, s28, 8 +; VI-NEXT: s_or_b32 s27, s27, s28 +; VI-NEXT: s_and_b32 s26, s26, 0xffff +; VI-NEXT: s_lshl_b32 s27, s27, 16 +; VI-NEXT: s_or_b32 s26, s26, s27 +; VI-NEXT: v_mov_b32_e32 v8, s26 +; VI-NEXT: v_readlane_b32 s26, v21, 19 +; VI-NEXT: s_lshl_b32 s26, s26, 8 +; VI-NEXT: s_and_b32 s24, s24, 0xff +; VI-NEXT: v_readlane_b32 s27, v21, 18 +; VI-NEXT: s_or_b32 s24, s24, s26 +; VI-NEXT: s_lshl_b32 s26, s30, 8 +; VI-NEXT: s_and_b32 s27, s27, 0xff +; VI-NEXT: s_or_b32 s26, s27, s26 +; VI-NEXT: s_and_b32 s24, s24, 0xffff +; VI-NEXT: s_lshl_b32 s26, s26, 16 +; VI-NEXT: s_or_b32 s24, s24, s26 +; VI-NEXT: v_mov_b32_e32 v9, s24 +; VI-NEXT: s_and_b32 s24, s25, 0xff +; VI-NEXT: v_readlane_b32 s25, v21, 17 +; VI-NEXT: s_lshl_b32 s25, s25, 8 +; VI-NEXT: s_or_b32 s24, s24, s25 +; VI-NEXT: v_readlane_b32 s25, v21, 16 +; VI-NEXT: v_readlane_b32 s26, v21, 15 +; VI-NEXT: s_and_b32 s25, s25, 0xff +; VI-NEXT: s_lshl_b32 s26, s26, 8 +; VI-NEXT: s_or_b32 s25, s25, s26 +; VI-NEXT: s_and_b32 s24, s24, 0xffff +; VI-NEXT: s_lshl_b32 s25, s25, 16 +; VI-NEXT: s_or_b32 s24, s24, s25 +; VI-NEXT: v_mov_b32_e32 v10, s24 +; VI-NEXT: v_readlane_b32 s24, v21, 14 +; VI-NEXT: s_lshl_b32 s24, s24, 8 +; VI-NEXT: s_and_b32 s22, s22, 0xff +; VI-NEXT: v_readlane_b32 s25, v21, 13 +; VI-NEXT: s_or_b32 s22, s22, s24 +; VI-NEXT: s_lshl_b32 s24, s90, 8 +; VI-NEXT: s_and_b32 s25, s25, 0xff +; VI-NEXT: s_or_b32 s24, s25, s24 +; VI-NEXT: s_and_b32 s22, s22, 0xffff +; VI-NEXT: s_lshl_b32 s24, s24, 16 +; VI-NEXT: s_or_b32 s22, s22, s24 +; VI-NEXT: v_mov_b32_e32 v11, s22 +; VI-NEXT: s_and_b32 s22, s23, 0xff +; VI-NEXT: v_readlane_b32 s23, v21, 12 +; VI-NEXT: s_lshl_b32 s23, s23, 8 +; VI-NEXT: s_or_b32 s22, s22, s23 +; VI-NEXT: v_readlane_b32 s23, v21, 11 +; VI-NEXT: v_readlane_b32 s24, v21, 10 +; VI-NEXT: s_and_b32 s23, s23, 0xff +; VI-NEXT: s_lshl_b32 s24, s24, 8 +; VI-NEXT: s_or_b32 s23, s23, s24 +; VI-NEXT: s_and_b32 s22, s22, 0xffff +; VI-NEXT: s_lshl_b32 s23, s23, 16 +; VI-NEXT: s_or_b32 s22, s22, s23 +; VI-NEXT: v_mov_b32_e32 v12, s22 +; VI-NEXT: v_readlane_b32 s22, v21, 9 +; VI-NEXT: s_lshl_b32 s22, s22, 8 +; VI-NEXT: s_and_b32 s20, s20, 0xff +; VI-NEXT: v_readlane_b32 s23, v21, 8 +; VI-NEXT: s_or_b32 s20, s20, s22 +; VI-NEXT: s_lshl_b32 s22, s88, 8 +; VI-NEXT: s_and_b32 s23, s23, 0xff +; VI-NEXT: s_or_b32 s22, s23, s22 +; VI-NEXT: s_and_b32 s20, s20, 0xffff +; VI-NEXT: s_lshl_b32 s22, s22, 16 +; VI-NEXT: s_or_b32 s20, s20, s22 +; VI-NEXT: v_mov_b32_e32 v13, s20 +; VI-NEXT: s_and_b32 s20, s21, 0xff +; VI-NEXT: v_readlane_b32 s21, v21, 7 +; VI-NEXT: s_lshl_b32 s21, s21, 8 +; VI-NEXT: s_or_b32 s20, s20, s21 +; VI-NEXT: v_readlane_b32 s21, v21, 6 +; VI-NEXT: v_readlane_b32 s22, v21, 5 +; VI-NEXT: s_and_b32 s21, s21, 0xff +; VI-NEXT: s_lshl_b32 s22, s22, 8 +; VI-NEXT: s_or_b32 s21, s21, s22 +; VI-NEXT: s_and_b32 s20, s20, 0xffff +; VI-NEXT: s_lshl_b32 s21, s21, 16 +; VI-NEXT: s_or_b32 s20, s20, s21 +; VI-NEXT: v_mov_b32_e32 v14, s20 +; VI-NEXT: v_readlane_b32 s20, v21, 4 +; VI-NEXT: s_lshl_b32 s20, s20, 8 ; VI-NEXT: s_and_b32 s18, s18, 0xff +; VI-NEXT: v_readlane_b32 s21, v21, 3 +; VI-NEXT: s_or_b32 s18, s18, s20 +; VI-NEXT: s_lshl_b32 s20, s76, 8 +; VI-NEXT: s_and_b32 s21, s21, 0xff +; VI-NEXT: s_or_b32 s20, s21, s20 ; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 4, v0 -; VI-NEXT: s_or_b32 s17, s18, s17 +; VI-NEXT: s_and_b32 s18, s18, 0xffff +; VI-NEXT: s_lshl_b32 s20, s20, 16 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 8, v0 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 +; VI-NEXT: s_or_b32 s18, s18, s20 ; VI-NEXT: buffer_store_dword v3, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 12, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: v_readlane_b32 s17, v21, 2 +; VI-NEXT: v_mov_b32_e32 v15, s18 +; VI-NEXT: s_and_b32 s18, s19, 0xff +; VI-NEXT: v_readlane_b32 s19, v21, 2 ; VI-NEXT: buffer_store_dword v4, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 16, v0 -; VI-NEXT: v_mov_b32_e32 v15, s16 -; VI-NEXT: s_and_b32 s16, s45, 0xff -; VI-NEXT: s_lshl_b32 s17, s17, 8 +; VI-NEXT: s_lshl_b32 s19, s19, 8 ; VI-NEXT: buffer_store_dword v5, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 20, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 +; VI-NEXT: s_or_b32 s18, s18, s19 ; VI-NEXT: buffer_store_dword v6, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 24, v0 -; VI-NEXT: v_readlane_b32 s17, v21, 1 -; VI-NEXT: v_readlane_b32 s18, v21, 0 +; VI-NEXT: v_readlane_b32 s19, v21, 1 +; VI-NEXT: v_readlane_b32 s20, v21, 0 ; VI-NEXT: buffer_store_dword v7, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 28, v0 -; VI-NEXT: s_and_b32 s17, s17, 0xff -; VI-NEXT: s_lshl_b32 s18, s18, 8 +; VI-NEXT: s_and_b32 s19, s19, 0xff +; VI-NEXT: s_lshl_b32 s20, s20, 8 ; VI-NEXT: buffer_store_dword v8, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 32, v0 -; VI-NEXT: s_or_b32 s17, s17, s18 +; VI-NEXT: s_or_b32 s19, s19, s20 ; VI-NEXT: buffer_store_dword v9, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 36, v0 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 +; VI-NEXT: s_and_b32 s18, s18, 0xffff +; VI-NEXT: s_lshl_b32 s19, s19, 16 ; VI-NEXT: buffer_store_dword v10, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 40, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 +; VI-NEXT: s_or_b32 s18, s18, s19 ; VI-NEXT: buffer_store_dword v11, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 44, v0 -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: s_and_b32 s16, s42, 0xff -; VI-NEXT: s_lshl_b32 s17, s64, 8 +; VI-NEXT: v_mov_b32_e32 v2, s18 +; VI-NEXT: s_and_b32 s18, s40, 0xff +; VI-NEXT: s_lshl_b32 s19, s64, 8 ; VI-NEXT: buffer_store_dword v12, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 48, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, s55, 0xff -; VI-NEXT: s_lshl_b32 s18, s78, 8 +; VI-NEXT: s_or_b32 s18, s18, s19 +; VI-NEXT: s_and_b32 s19, s55, 0xff +; VI-NEXT: s_lshl_b32 s20, s78, 8 ; VI-NEXT: buffer_store_dword v13, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 52, v0 -; VI-NEXT: s_or_b32 s17, s17, s18 +; VI-NEXT: s_or_b32 s19, s19, s20 ; VI-NEXT: buffer_store_dword v14, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 56, v0 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 +; VI-NEXT: s_and_b32 s18, s18, 0xffff +; VI-NEXT: s_lshl_b32 s19, s19, 16 ; VI-NEXT: buffer_store_dword v15, v1, s[0:3], 0 offen ; VI-NEXT: v_add_u32_e32 v1, vcc, 60, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 +; VI-NEXT: s_or_b32 s18, s18, s19 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: s_and_b32 s16, s43, 0xff -; VI-NEXT: s_lshl_b32 s17, s52, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, s50, 0xff -; VI-NEXT: s_lshl_b32 s18, s87, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 -; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 +; VI-NEXT: v_mov_b32_e32 v2, s18 +; VI-NEXT: s_and_b32 s18, s41, 0xff +; VI-NEXT: s_lshl_b32 s19, s52, 8 +; VI-NEXT: s_or_b32 s18, s18, s19 +; VI-NEXT: s_and_b32 s19, s50, 0xff +; VI-NEXT: s_lshl_b32 s20, s87, 8 +; VI-NEXT: s_or_b32 s19, s19, s20 +; VI-NEXT: s_and_b32 s18, s18, 0xffff +; VI-NEXT: s_lshl_b32 s19, s19, 16 ; VI-NEXT: v_add_u32_e32 v1, vcc, 64, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 +; VI-NEXT: s_or_b32 s18, s18, s19 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen -; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: s_and_b32 s16, s40, 0xff -; VI-NEXT: s_lshl_b32 s17, s85, 8 -; VI-NEXT: s_or_b32 s16, s16, s17 -; VI-NEXT: s_and_b32 s17, s83, 0xff -; VI-NEXT: s_lshl_b32 s18, s74, 8 -; VI-NEXT: s_or_b32 s17, s17, s18 +; VI-NEXT: v_mov_b32_e32 v2, s18 +; VI-NEXT: s_and_b32 s16, s16, 0xff +; VI-NEXT: s_lshl_b32 s18, s85, 8 +; VI-NEXT: s_or_b32 s16, s16, s18 +; VI-NEXT: s_and_b32 s18, s83, 0xff +; VI-NEXT: s_lshl_b32 s19, s74, 8 +; VI-NEXT: s_or_b32 s18, s18, s19 ; VI-NEXT: s_and_b32 s16, s16, 0xffff -; VI-NEXT: s_lshl_b32 s17, s17, 16 +; VI-NEXT: s_lshl_b32 s18, s18, 16 ; VI-NEXT: v_add_u32_e32 v1, vcc, 0x44, v0 -; VI-NEXT: s_or_b32 s16, s16, s17 +; VI-NEXT: s_or_b32 s16, s16, s18 ; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; VI-NEXT: v_mov_b32_e32 v2, s16 -; VI-NEXT: s_and_b32 s16, s41, 0xff +; VI-NEXT: s_and_b32 s16, s17, 0xff ; VI-NEXT: s_lshl_b32 s17, s81, 8 ; VI-NEXT: s_or_b32 s16, s16, s17 ; VI-NEXT: v_readlane_b32 s17, v21, 57 @@ -217538,26 +213820,54 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX9-NEXT: v_writelane_b32 v63, s96, 32 ; GFX9-NEXT: v_writelane_b32 v63, s97, 33 ; GFX9-NEXT: v_writelane_b32 v63, s98, 34 +; GFX9-NEXT: v_readfirstlane_b32 s56, v3 +; GFX9-NEXT: v_mov_b32_e32 v3, s16 +; GFX9-NEXT: v_readfirstlane_b32 s57, v4 +; GFX9-NEXT: v_mov_b32_e32 v4, s17 +; GFX9-NEXT: v_readfirstlane_b32 s46, v5 +; GFX9-NEXT: v_mov_b32_e32 v5, s18 +; GFX9-NEXT: v_readfirstlane_b32 s47, v6 +; GFX9-NEXT: v_mov_b32_e32 v6, s19 +; GFX9-NEXT: v_readfirstlane_b32 s44, v7 +; GFX9-NEXT: v_mov_b32_e32 v7, s20 +; GFX9-NEXT: v_readfirstlane_b32 s45, v8 +; GFX9-NEXT: v_mov_b32_e32 v8, s21 +; GFX9-NEXT: v_readfirstlane_b32 s42, v9 +; GFX9-NEXT: v_mov_b32_e32 v9, s22 +; GFX9-NEXT: v_readfirstlane_b32 s43, v10 +; GFX9-NEXT: v_mov_b32_e32 v10, s23 +; GFX9-NEXT: v_readfirstlane_b32 s40, v11 +; GFX9-NEXT: v_mov_b32_e32 v11, s24 +; GFX9-NEXT: v_readfirstlane_b32 s41, v12 +; GFX9-NEXT: v_mov_b32_e32 v12, s25 +; GFX9-NEXT: v_readfirstlane_b32 s24, v13 +; GFX9-NEXT: v_mov_b32_e32 v13, s26 +; GFX9-NEXT: v_readfirstlane_b32 s25, v14 +; GFX9-NEXT: v_mov_b32_e32 v14, s27 +; GFX9-NEXT: v_readfirstlane_b32 s22, v15 +; GFX9-NEXT: v_mov_b32_e32 v15, s28 +; GFX9-NEXT: v_readfirstlane_b32 s23, v16 +; GFX9-NEXT: v_mov_b32_e32 v16, s29 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v19 ; GFX9-NEXT: v_writelane_b32 v63, s99, 35 -; GFX9-NEXT: v_readfirstlane_b32 s44, v3 -; GFX9-NEXT: v_readfirstlane_b32 s45, v4 -; GFX9-NEXT: v_readfirstlane_b32 s42, v5 -; GFX9-NEXT: v_readfirstlane_b32 s43, v6 -; GFX9-NEXT: v_readfirstlane_b32 s40, v7 -; GFX9-NEXT: v_readfirstlane_b32 s41, v8 -; GFX9-NEXT: v_readfirstlane_b32 s14, v9 -; GFX9-NEXT: v_readfirstlane_b32 s15, v10 -; GFX9-NEXT: v_readfirstlane_b32 s12, v11 -; GFX9-NEXT: v_readfirstlane_b32 s13, v12 -; GFX9-NEXT: v_readfirstlane_b32 s10, v13 -; GFX9-NEXT: v_readfirstlane_b32 s11, v14 -; GFX9-NEXT: v_readfirstlane_b32 s8, v15 -; GFX9-NEXT: v_readfirstlane_b32 s9, v16 -; GFX9-NEXT: v_readfirstlane_b32 s6, v17 -; GFX9-NEXT: v_readfirstlane_b32 s7, v18 +; GFX9-NEXT: v_readfirstlane_b32 s20, v17 +; GFX9-NEXT: v_readfirstlane_b32 s21, v18 +; GFX9-NEXT: v_readfirstlane_b32 s18, v3 +; GFX9-NEXT: v_readfirstlane_b32 s19, v4 +; GFX9-NEXT: v_readfirstlane_b32 s16, v5 +; GFX9-NEXT: v_readfirstlane_b32 s17, v6 +; GFX9-NEXT: v_readfirstlane_b32 s14, v7 +; GFX9-NEXT: v_readfirstlane_b32 s15, v8 +; GFX9-NEXT: v_readfirstlane_b32 s12, v9 +; GFX9-NEXT: v_readfirstlane_b32 s13, v10 +; GFX9-NEXT: v_readfirstlane_b32 s10, v11 +; GFX9-NEXT: v_readfirstlane_b32 s11, v12 +; GFX9-NEXT: v_readfirstlane_b32 s8, v13 +; GFX9-NEXT: v_readfirstlane_b32 s9, v14 +; GFX9-NEXT: v_readfirstlane_b32 s6, v15 +; GFX9-NEXT: v_readfirstlane_b32 s7, v16 ; GFX9-NEXT: v_readfirstlane_b32 s4, v1 -; GFX9-NEXT: s_and_b64 s[46:47], vcc, exec +; GFX9-NEXT: s_and_b64 s[26:27], vcc, exec ; GFX9-NEXT: v_readfirstlane_b32 s5, v2 ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill @@ -217576,225 +213886,225 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX9-NEXT: ; implicit-def: $vgpr62 : SGPR spill to VGPR lane ; GFX9-NEXT: s_cbranch_scc0 .LBB99_3 ; GFX9-NEXT: ; %bb.1: ; %cmp.false -; GFX9-NEXT: s_lshr_b32 s46, s5, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 49 -; GFX9-NEXT: s_lshr_b32 s46, s5, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 48 -; GFX9-NEXT: s_lshr_b32 s46, s5, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 47 -; GFX9-NEXT: s_lshr_b32 s46, s4, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 46 -; GFX9-NEXT: s_lshr_b32 s46, s4, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 45 -; GFX9-NEXT: s_lshr_b32 s46, s29, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 44 -; GFX9-NEXT: s_lshr_b32 s46, s29, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 43 -; GFX9-NEXT: s_lshr_b32 s46, s29, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 42 -; GFX9-NEXT: s_lshr_b32 s46, s28, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 41 -; GFX9-NEXT: s_lshr_b32 s46, s28, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 40 -; GFX9-NEXT: s_lshr_b32 s46, s27, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 39 -; GFX9-NEXT: s_lshr_b32 s46, s27, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 38 -; GFX9-NEXT: s_lshr_b32 s46, s27, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 37 -; GFX9-NEXT: s_lshr_b32 s46, s26, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 36 -; GFX9-NEXT: s_lshr_b32 s46, s26, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 35 -; GFX9-NEXT: s_lshr_b32 s46, s25, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 34 -; GFX9-NEXT: s_lshr_b32 s46, s25, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 33 -; GFX9-NEXT: s_lshr_b32 s46, s25, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 32 -; GFX9-NEXT: s_lshr_b32 s46, s24, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 31 -; GFX9-NEXT: s_lshr_b32 s46, s24, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 30 -; GFX9-NEXT: s_lshr_b32 s46, s23, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 29 -; GFX9-NEXT: s_lshr_b32 s46, s23, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 28 -; GFX9-NEXT: s_lshr_b32 s46, s23, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 27 -; GFX9-NEXT: s_lshr_b32 s46, s22, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 26 -; GFX9-NEXT: s_lshr_b32 s46, s22, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 25 -; GFX9-NEXT: s_lshr_b32 s46, s21, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 24 -; GFX9-NEXT: s_lshr_b32 s46, s21, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 23 -; GFX9-NEXT: s_lshr_b32 s46, s21, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 22 -; GFX9-NEXT: s_lshr_b32 s46, s20, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 21 -; GFX9-NEXT: s_lshr_b32 s46, s20, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 20 -; GFX9-NEXT: s_lshr_b32 s46, s19, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 19 -; GFX9-NEXT: s_lshr_b32 s46, s19, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 18 -; GFX9-NEXT: s_lshr_b32 s46, s19, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 17 -; GFX9-NEXT: s_lshr_b32 s46, s18, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 16 -; GFX9-NEXT: s_lshr_b32 s46, s18, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 15 -; GFX9-NEXT: s_lshr_b32 s46, s17, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 14 -; GFX9-NEXT: s_lshr_b32 s46, s17, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 13 -; GFX9-NEXT: s_lshr_b32 s46, s17, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 12 -; GFX9-NEXT: s_lshr_b32 s46, s16, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 11 -; GFX9-NEXT: s_lshr_b32 s46, s16, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 10 -; GFX9-NEXT: s_lshr_b32 s46, s7, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 9 -; GFX9-NEXT: s_lshr_b32 s46, s7, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 8 -; GFX9-NEXT: s_lshr_b32 s46, s7, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 7 -; GFX9-NEXT: s_lshr_b32 s46, s6, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 6 -; GFX9-NEXT: s_lshr_b32 s46, s6, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 5 -; GFX9-NEXT: s_lshr_b32 s46, s9, 24 -; GFX9-NEXT: v_writelane_b32 v62, s46, 4 -; GFX9-NEXT: s_lshr_b32 s46, s9, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 3 -; GFX9-NEXT: s_lshr_b32 s46, s9, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 2 -; GFX9-NEXT: s_lshr_b32 s46, s8, 16 -; GFX9-NEXT: v_writelane_b32 v62, s46, 1 -; GFX9-NEXT: s_lshr_b32 s46, s8, 8 -; GFX9-NEXT: v_writelane_b32 v62, s46, 0 -; GFX9-NEXT: s_lshr_b32 s82, s11, 24 -; GFX9-NEXT: s_lshr_b32 s83, s11, 16 -; GFX9-NEXT: s_lshr_b32 s85, s11, 8 -; GFX9-NEXT: s_lshr_b32 s84, s10, 16 -; GFX9-NEXT: s_lshr_b32 s86, s10, 8 -; GFX9-NEXT: s_lshr_b32 s87, s13, 24 -; GFX9-NEXT: s_lshr_b32 s96, s13, 16 -; GFX9-NEXT: s_lshr_b32 s98, s13, 8 -; GFX9-NEXT: s_lshr_b32 s97, s12, 16 -; GFX9-NEXT: s_lshr_b32 s99, s12, 8 -; GFX9-NEXT: s_lshr_b32 s38, s15, 24 -; GFX9-NEXT: s_lshr_b32 s39, s15, 16 -; GFX9-NEXT: s_lshr_b32 s49, s15, 8 -; GFX9-NEXT: s_lshr_b32 s48, s14, 16 -; GFX9-NEXT: s_lshr_b32 s50, s14, 8 -; GFX9-NEXT: s_lshr_b32 s51, s41, 24 -; GFX9-NEXT: s_lshr_b32 s52, s41, 16 -; GFX9-NEXT: s_lshr_b32 s54, s41, 8 -; GFX9-NEXT: s_lshr_b32 s53, s40, 16 -; GFX9-NEXT: s_lshr_b32 s55, s40, 8 -; GFX9-NEXT: s_lshr_b32 s64, s43, 24 -; GFX9-NEXT: s_lshr_b32 s65, s43, 16 -; GFX9-NEXT: s_lshr_b32 s67, s43, 8 -; GFX9-NEXT: s_lshr_b32 s66, s42, 16 -; GFX9-NEXT: s_lshr_b32 s68, s42, 8 -; GFX9-NEXT: s_lshr_b32 s69, s45, 24 -; GFX9-NEXT: s_lshr_b32 s70, s45, 16 -; GFX9-NEXT: s_lshr_b32 s80, s45, 8 -; GFX9-NEXT: s_lshr_b32 s71, s44, 16 -; GFX9-NEXT: s_lshr_b32 s81, s44, 8 -; GFX9-NEXT: s_lshr_b64 s[46:47], s[4:5], 24 -; GFX9-NEXT: s_lshr_b64 s[56:57], s[28:29], 24 -; GFX9-NEXT: s_lshr_b64 s[58:59], s[26:27], 24 -; GFX9-NEXT: s_lshr_b64 s[60:61], s[24:25], 24 -; GFX9-NEXT: s_lshr_b64 s[62:63], s[22:23], 24 -; GFX9-NEXT: s_lshr_b64 s[72:73], s[20:21], 24 -; GFX9-NEXT: s_lshr_b64 s[74:75], s[18:19], 24 -; GFX9-NEXT: s_lshr_b64 s[76:77], s[16:17], 24 -; GFX9-NEXT: s_lshr_b64 s[78:79], s[6:7], 24 -; GFX9-NEXT: s_lshr_b64 s[88:89], s[8:9], 24 -; GFX9-NEXT: s_lshr_b64 s[90:91], s[10:11], 24 -; GFX9-NEXT: s_lshr_b64 s[92:93], s[12:13], 24 -; GFX9-NEXT: s_lshr_b64 s[94:95], s[14:15], 24 -; GFX9-NEXT: s_lshr_b64 s[30:31], s[40:41], 24 -; GFX9-NEXT: s_lshr_b64 s[34:35], s[42:43], 24 -; GFX9-NEXT: s_lshr_b64 s[36:37], s[44:45], 24 +; GFX9-NEXT: s_lshr_b32 s26, s5, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 49 +; GFX9-NEXT: s_lshr_b32 s26, s5, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 48 +; GFX9-NEXT: s_lshr_b32 s26, s5, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 47 +; GFX9-NEXT: s_lshr_b32 s26, s4, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 46 +; GFX9-NEXT: s_lshr_b32 s26, s4, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 45 +; GFX9-NEXT: s_lshr_b32 s26, s7, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 44 +; GFX9-NEXT: s_lshr_b32 s26, s7, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 43 +; GFX9-NEXT: s_lshr_b32 s26, s7, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 42 +; GFX9-NEXT: s_lshr_b32 s26, s6, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 41 +; GFX9-NEXT: s_lshr_b32 s26, s6, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 40 +; GFX9-NEXT: s_lshr_b32 s26, s9, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 39 +; GFX9-NEXT: s_lshr_b32 s26, s9, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 38 +; GFX9-NEXT: s_lshr_b32 s26, s9, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 37 +; GFX9-NEXT: s_lshr_b32 s26, s8, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 36 +; GFX9-NEXT: s_lshr_b32 s26, s8, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 35 +; GFX9-NEXT: s_lshr_b32 s26, s11, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 34 +; GFX9-NEXT: s_lshr_b32 s26, s11, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 33 +; GFX9-NEXT: s_lshr_b32 s26, s11, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 32 +; GFX9-NEXT: s_lshr_b32 s26, s10, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 31 +; GFX9-NEXT: s_lshr_b32 s26, s10, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 30 +; GFX9-NEXT: s_lshr_b32 s26, s13, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 29 +; GFX9-NEXT: s_lshr_b32 s26, s13, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 28 +; GFX9-NEXT: s_lshr_b32 s26, s13, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 27 +; GFX9-NEXT: s_lshr_b32 s26, s12, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 26 +; GFX9-NEXT: s_lshr_b32 s26, s12, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 25 +; GFX9-NEXT: s_lshr_b32 s26, s15, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 24 +; GFX9-NEXT: s_lshr_b32 s26, s15, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 23 +; GFX9-NEXT: s_lshr_b32 s26, s15, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 22 +; GFX9-NEXT: s_lshr_b32 s26, s14, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 21 +; GFX9-NEXT: s_lshr_b32 s26, s14, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 20 +; GFX9-NEXT: s_lshr_b32 s26, s17, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 19 +; GFX9-NEXT: s_lshr_b32 s26, s17, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 18 +; GFX9-NEXT: s_lshr_b32 s26, s17, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 17 +; GFX9-NEXT: s_lshr_b32 s26, s16, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 16 +; GFX9-NEXT: s_lshr_b32 s26, s16, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 15 +; GFX9-NEXT: s_lshr_b32 s26, s19, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 14 +; GFX9-NEXT: s_lshr_b32 s26, s19, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 13 +; GFX9-NEXT: s_lshr_b32 s26, s19, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 12 +; GFX9-NEXT: s_lshr_b32 s26, s18, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 11 +; GFX9-NEXT: s_lshr_b32 s26, s18, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 10 +; GFX9-NEXT: s_lshr_b32 s26, s21, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 9 +; GFX9-NEXT: s_lshr_b32 s26, s21, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 8 +; GFX9-NEXT: s_lshr_b32 s26, s21, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 7 +; GFX9-NEXT: s_lshr_b32 s26, s20, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 6 +; GFX9-NEXT: s_lshr_b32 s26, s20, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 5 +; GFX9-NEXT: s_lshr_b32 s26, s23, 24 +; GFX9-NEXT: v_writelane_b32 v62, s26, 4 +; GFX9-NEXT: s_lshr_b32 s26, s23, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 3 +; GFX9-NEXT: s_lshr_b32 s26, s23, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 2 +; GFX9-NEXT: s_lshr_b32 s26, s22, 16 +; GFX9-NEXT: v_writelane_b32 v62, s26, 1 +; GFX9-NEXT: s_lshr_b32 s26, s22, 8 +; GFX9-NEXT: v_writelane_b32 v62, s26, 0 +; GFX9-NEXT: s_lshr_b32 s82, s25, 24 +; GFX9-NEXT: s_lshr_b32 s83, s25, 16 +; GFX9-NEXT: s_lshr_b32 s85, s25, 8 +; GFX9-NEXT: s_lshr_b32 s84, s24, 16 +; GFX9-NEXT: s_lshr_b32 s86, s24, 8 +; GFX9-NEXT: s_lshr_b32 s87, s41, 24 +; GFX9-NEXT: s_lshr_b32 s96, s41, 16 +; GFX9-NEXT: s_lshr_b32 s98, s41, 8 +; GFX9-NEXT: s_lshr_b32 s97, s40, 16 +; GFX9-NEXT: s_lshr_b32 s99, s40, 8 +; GFX9-NEXT: s_lshr_b32 s38, s43, 24 +; GFX9-NEXT: s_lshr_b32 s39, s43, 16 +; GFX9-NEXT: s_lshr_b32 s49, s43, 8 +; GFX9-NEXT: s_lshr_b32 s48, s42, 16 +; GFX9-NEXT: s_lshr_b32 s50, s42, 8 +; GFX9-NEXT: s_lshr_b32 s51, s45, 24 +; GFX9-NEXT: s_lshr_b32 s52, s45, 16 +; GFX9-NEXT: s_lshr_b32 s54, s45, 8 +; GFX9-NEXT: s_lshr_b32 s53, s44, 16 +; GFX9-NEXT: s_lshr_b32 s55, s44, 8 +; GFX9-NEXT: s_lshr_b32 s64, s47, 24 +; GFX9-NEXT: s_lshr_b32 s65, s47, 16 +; GFX9-NEXT: s_lshr_b32 s67, s47, 8 +; GFX9-NEXT: s_lshr_b32 s66, s46, 16 +; GFX9-NEXT: s_lshr_b32 s68, s46, 8 +; GFX9-NEXT: s_lshr_b32 s69, s57, 24 +; GFX9-NEXT: s_lshr_b32 s70, s57, 16 +; GFX9-NEXT: s_lshr_b32 s80, s57, 8 +; GFX9-NEXT: s_lshr_b32 s71, s56, 16 +; GFX9-NEXT: s_lshr_b32 s81, s56, 8 +; GFX9-NEXT: s_lshr_b64 s[26:27], s[4:5], 24 +; GFX9-NEXT: s_lshr_b64 s[28:29], s[6:7], 24 +; GFX9-NEXT: s_lshr_b64 s[58:59], s[8:9], 24 +; GFX9-NEXT: s_lshr_b64 s[60:61], s[10:11], 24 +; GFX9-NEXT: s_lshr_b64 s[62:63], s[12:13], 24 +; GFX9-NEXT: s_lshr_b64 s[72:73], s[14:15], 24 +; GFX9-NEXT: s_lshr_b64 s[74:75], s[16:17], 24 +; GFX9-NEXT: s_lshr_b64 s[76:77], s[18:19], 24 +; GFX9-NEXT: s_lshr_b64 s[78:79], s[20:21], 24 +; GFX9-NEXT: s_lshr_b64 s[88:89], s[22:23], 24 +; GFX9-NEXT: s_lshr_b64 s[90:91], s[24:25], 24 +; GFX9-NEXT: s_lshr_b64 s[92:93], s[40:41], 24 +; GFX9-NEXT: s_lshr_b64 s[94:95], s[42:43], 24 +; GFX9-NEXT: s_lshr_b64 s[30:31], s[44:45], 24 +; GFX9-NEXT: s_lshr_b64 s[34:35], s[46:47], 24 +; GFX9-NEXT: s_lshr_b64 s[36:37], s[56:57], 24 ; GFX9-NEXT: s_cbranch_execnz .LBB99_4 ; GFX9-NEXT: .LBB99_2: ; %cmp.true ; GFX9-NEXT: v_pk_add_u16 v26, s5, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_add_u16 v25, s4, 3 op_sel_hi:[1,0] ; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[25:26] -; GFX9-NEXT: v_pk_add_u16 v28, s29, 3 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_u16 v27, s28, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v28, s7, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v27, s6, 3 op_sel_hi:[1,0] ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[27:28] -; GFX9-NEXT: v_pk_add_u16 v30, s27, 3 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_u16 v29, s26, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v30, s9, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v29, s8, 3 op_sel_hi:[1,0] ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[29:30] -; GFX9-NEXT: v_pk_add_u16 v32, s25, 3 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_u16 v31, s24, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v32, s11, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v31, s10, 3 op_sel_hi:[1,0] ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[31:32] -; GFX9-NEXT: v_pk_add_u16 v34, s23, 3 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_u16 v33, s22, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v34, s13, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v33, s12, 3 op_sel_hi:[1,0] ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[33:34] -; GFX9-NEXT: v_pk_add_u16 v36, s21, 3 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_u16 v35, s20, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v36, s15, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v35, s14, 3 op_sel_hi:[1,0] ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[35:36] -; GFX9-NEXT: v_pk_add_u16 v38, s19, 3 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_u16 v37, s18, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v38, s17, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v37, s16, 3 op_sel_hi:[1,0] ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[37:38] -; GFX9-NEXT: v_pk_add_u16 v49, s17, 3 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_u16 v48, s16, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v49, s19, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v48, s18, 3 op_sel_hi:[1,0] ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[48:49] -; GFX9-NEXT: v_pk_add_u16 v2, s7, 3 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_u16 v1, s6, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v2, s21, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v1, s20, 3 op_sel_hi:[1,0] ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2] -; GFX9-NEXT: v_pk_add_u16 v4, s9, 3 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_u16 v3, s8, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v4, s23, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v3, s22, 3 op_sel_hi:[1,0] ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[3:4] -; GFX9-NEXT: v_pk_add_u16 v6, s11, 3 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_u16 v5, s10, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v6, s25, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v5, s24, 3 op_sel_hi:[1,0] ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[5:6] -; GFX9-NEXT: v_pk_add_u16 v8, s13, 3 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_u16 v7, s12, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v8, s41, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v7, s40, 3 op_sel_hi:[1,0] ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[7:8] -; GFX9-NEXT: v_pk_add_u16 v10, s15, 3 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_u16 v9, s14, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v10, s43, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v9, s42, 3 op_sel_hi:[1,0] ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill @@ -217802,8 +214112,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX9-NEXT: v_lshrrev_b32_e32 v19, 24, v4 ; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v3 -; GFX9-NEXT: v_pk_add_u16 v12, s41, 3 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_u16 v11, s40, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v12, s45, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v11, s44, 3 op_sel_hi:[1,0] ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill @@ -217814,8 +214124,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX9-NEXT: v_lshrrev_b32_e32 v19, 24, v6 ; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v6 -; GFX9-NEXT: v_pk_add_u16 v14, s43, 3 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_u16 v13, s42, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v14, s47, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v13, s46, 3 op_sel_hi:[1,0] ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill @@ -217826,8 +214136,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v5 ; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill ; GFX9-NEXT: v_lshrrev_b32_e32 v19, 8, v5 -; GFX9-NEXT: v_pk_add_u16 v22, s45, 3 op_sel_hi:[1,0] -; GFX9-NEXT: v_pk_add_u16 v21, s44, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v22, s57, 3 op_sel_hi:[1,0] +; GFX9-NEXT: v_pk_add_u16 v21, s56, 3 op_sel_hi:[1,0] ; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill @@ -217954,10 +214264,10 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX9-NEXT: v_lshrrev_b32_e32 v19, 8, v21 ; GFX9-NEXT: s_branch .LBB99_5 ; GFX9-NEXT: .LBB99_3: -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 ; GFX9-NEXT: ; implicit-def: $sgpr81 ; GFX9-NEXT: ; implicit-def: $sgpr71 ; GFX9-NEXT: ; implicit-def: $sgpr80 @@ -217994,7 +214304,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX9-NEXT: ; implicit-def: $sgpr62 ; GFX9-NEXT: ; implicit-def: $sgpr60 ; GFX9-NEXT: ; implicit-def: $sgpr58 -; GFX9-NEXT: ; implicit-def: $sgpr56 +; GFX9-NEXT: ; implicit-def: $sgpr28 ; GFX9-NEXT: ; implicit-def: $sgpr36 ; GFX9-NEXT: ; implicit-def: $sgpr34 ; GFX9-NEXT: ; implicit-def: $sgpr30 @@ -218003,103 +214313,103 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX9-NEXT: ; implicit-def: $sgpr90 ; GFX9-NEXT: ; implicit-def: $sgpr88 ; GFX9-NEXT: ; implicit-def: $sgpr78 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 -; GFX9-NEXT: ; kill: killed $sgpr46 -; GFX9-NEXT: ; implicit-def: $sgpr46 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 +; GFX9-NEXT: ; kill: killed $sgpr26 +; GFX9-NEXT: ; implicit-def: $sgpr26 ; GFX9-NEXT: s_branch .LBB99_2 ; GFX9-NEXT: .LBB99_4: ; GFX9-NEXT: v_mov_b32_e32 v15, s71 @@ -218284,11 +214594,11 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v41, s4 ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v41, s46 +; GFX9-NEXT: v_mov_b32_e32 v41, s26 ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v41, s56 +; GFX9-NEXT: v_mov_b32_e32 v41, s28 ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill @@ -218348,36 +214658,36 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill ; GFX9-NEXT: s_nop 0 ; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill -; GFX9-NEXT: v_mov_b32_e32 v21, s44 -; GFX9-NEXT: v_mov_b32_e32 v22, s45 -; GFX9-NEXT: v_mov_b32_e32 v13, s42 -; GFX9-NEXT: v_mov_b32_e32 v14, s43 -; GFX9-NEXT: v_mov_b32_e32 v11, s40 -; GFX9-NEXT: v_mov_b32_e32 v12, s41 -; GFX9-NEXT: v_mov_b32_e32 v9, s14 -; GFX9-NEXT: v_mov_b32_e32 v10, s15 -; GFX9-NEXT: v_mov_b32_e32 v7, s12 -; GFX9-NEXT: v_mov_b32_e32 v8, s13 -; GFX9-NEXT: v_mov_b32_e32 v5, s10 -; GFX9-NEXT: v_mov_b32_e32 v6, s11 -; GFX9-NEXT: v_mov_b32_e32 v3, s8 -; GFX9-NEXT: v_mov_b32_e32 v4, s9 -; GFX9-NEXT: v_mov_b32_e32 v1, s6 -; GFX9-NEXT: v_mov_b32_e32 v2, s7 -; GFX9-NEXT: v_mov_b32_e32 v48, s16 -; GFX9-NEXT: v_mov_b32_e32 v49, s17 -; GFX9-NEXT: v_mov_b32_e32 v37, s18 -; GFX9-NEXT: v_mov_b32_e32 v38, s19 -; GFX9-NEXT: v_mov_b32_e32 v35, s20 -; GFX9-NEXT: v_mov_b32_e32 v36, s21 -; GFX9-NEXT: v_mov_b32_e32 v33, s22 -; GFX9-NEXT: v_mov_b32_e32 v34, s23 -; GFX9-NEXT: v_mov_b32_e32 v31, s24 -; GFX9-NEXT: v_mov_b32_e32 v32, s25 -; GFX9-NEXT: v_mov_b32_e32 v29, s26 -; GFX9-NEXT: v_mov_b32_e32 v30, s27 -; GFX9-NEXT: v_mov_b32_e32 v27, s28 -; GFX9-NEXT: v_mov_b32_e32 v28, s29 +; GFX9-NEXT: v_mov_b32_e32 v21, s56 +; GFX9-NEXT: v_mov_b32_e32 v22, s57 +; GFX9-NEXT: v_mov_b32_e32 v13, s46 +; GFX9-NEXT: v_mov_b32_e32 v14, s47 +; GFX9-NEXT: v_mov_b32_e32 v11, s44 +; GFX9-NEXT: v_mov_b32_e32 v12, s45 +; GFX9-NEXT: v_mov_b32_e32 v9, s42 +; GFX9-NEXT: v_mov_b32_e32 v10, s43 +; GFX9-NEXT: v_mov_b32_e32 v7, s40 +; GFX9-NEXT: v_mov_b32_e32 v8, s41 +; GFX9-NEXT: v_mov_b32_e32 v5, s24 +; GFX9-NEXT: v_mov_b32_e32 v6, s25 +; GFX9-NEXT: v_mov_b32_e32 v3, s22 +; GFX9-NEXT: v_mov_b32_e32 v4, s23 +; GFX9-NEXT: v_mov_b32_e32 v1, s20 +; GFX9-NEXT: v_mov_b32_e32 v2, s21 +; GFX9-NEXT: v_mov_b32_e32 v48, s18 +; GFX9-NEXT: v_mov_b32_e32 v49, s19 +; GFX9-NEXT: v_mov_b32_e32 v37, s16 +; GFX9-NEXT: v_mov_b32_e32 v38, s17 +; GFX9-NEXT: v_mov_b32_e32 v35, s14 +; GFX9-NEXT: v_mov_b32_e32 v36, s15 +; GFX9-NEXT: v_mov_b32_e32 v33, s12 +; GFX9-NEXT: v_mov_b32_e32 v34, s13 +; GFX9-NEXT: v_mov_b32_e32 v31, s10 +; GFX9-NEXT: v_mov_b32_e32 v32, s11 +; GFX9-NEXT: v_mov_b32_e32 v29, s8 +; GFX9-NEXT: v_mov_b32_e32 v30, s9 +; GFX9-NEXT: v_mov_b32_e32 v27, s6 +; GFX9-NEXT: v_mov_b32_e32 v28, s7 ; GFX9-NEXT: v_mov_b32_e32 v26, s5 ; GFX9-NEXT: v_mov_b32_e32 v41, v50 ; GFX9-NEXT: v_mov_b32_e32 v50, v51 @@ -218815,33 +215125,41 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX11-NEXT: s_mov_b32 exec_lo, s4 ; GFX11-NEXT: v_writelane_b32 v75, s30, 0 ; GFX11-NEXT: v_writelane_b32 v76, s96, 0 +; GFX11-NEXT: v_dual_mov_b32 v16, s28 :: v_dual_mov_b32 v17, s29 ; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15 -; GFX11-NEXT: v_readfirstlane_b32 s40, v1 -; GFX11-NEXT: v_readfirstlane_b32 s41, v2 ; GFX11-NEXT: v_writelane_b32 v75, s31, 1 ; GFX11-NEXT: v_writelane_b32 v76, s97, 1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX11-NEXT: v_readfirstlane_b32 s40, v16 +; GFX11-NEXT: v_readfirstlane_b32 s41, v17 +; GFX11-NEXT: v_readfirstlane_b32 s28, v1 +; GFX11-NEXT: v_writelane_b32 v75, s34, 2 +; GFX11-NEXT: v_writelane_b32 v76, s98, 2 +; GFX11-NEXT: v_readfirstlane_b32 s29, v2 ; GFX11-NEXT: v_readfirstlane_b32 s14, v3 ; GFX11-NEXT: v_readfirstlane_b32 s15, v4 +; GFX11-NEXT: v_writelane_b32 v75, s35, 3 +; GFX11-NEXT: v_writelane_b32 v76, s99, 3 ; GFX11-NEXT: v_readfirstlane_b32 s12, v5 -; GFX11-NEXT: v_writelane_b32 v75, s34, 2 -; GFX11-NEXT: v_writelane_b32 v76, s98, 2 ; GFX11-NEXT: v_readfirstlane_b32 s13, v6 ; GFX11-NEXT: v_readfirstlane_b32 s10, v7 +; GFX11-NEXT: v_writelane_b32 v75, s36, 4 +; GFX11-NEXT: v_writelane_b32 v76, s100, 4 ; GFX11-NEXT: v_readfirstlane_b32 s11, v8 -; GFX11-NEXT: v_writelane_b32 v75, s35, 3 -; GFX11-NEXT: v_writelane_b32 v76, s99, 3 ; GFX11-NEXT: v_readfirstlane_b32 s8, v9 ; GFX11-NEXT: v_readfirstlane_b32 s9, v10 +; GFX11-NEXT: v_writelane_b32 v75, s37, 5 +; GFX11-NEXT: v_writelane_b32 v76, s101, 5 ; GFX11-NEXT: v_readfirstlane_b32 s6, v11 -; GFX11-NEXT: v_writelane_b32 v75, s36, 4 -; GFX11-NEXT: v_writelane_b32 v76, s100, 4 ; GFX11-NEXT: v_readfirstlane_b32 s7, v12 ; GFX11-NEXT: v_readfirstlane_b32 s4, v13 +; GFX11-NEXT: v_writelane_b32 v75, s38, 6 +; GFX11-NEXT: v_writelane_b32 v76, s102, 6 ; GFX11-NEXT: v_readfirstlane_b32 s5, v14 -; GFX11-NEXT: v_writelane_b32 v75, s37, 5 -; GFX11-NEXT: v_writelane_b32 v76, s101, 5 ; GFX11-NEXT: s_mov_b32 s99, 0 ; GFX11-NEXT: s_and_b32 s42, vcc_lo, exec_lo +; GFX11-NEXT: v_writelane_b32 v75, s39, 7 +; GFX11-NEXT: v_writelane_b32 v76, s103, 7 ; GFX11-NEXT: s_clause 0x12 ; 76-byte Folded Spill ; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:72 ; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:68 @@ -218862,12 +215180,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:8 ; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:4 ; GFX11-NEXT: scratch_store_b32 off, v74, s32 -; GFX11-NEXT: v_writelane_b32 v75, s38, 6 -; GFX11-NEXT: v_writelane_b32 v76, s102, 6 ; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane ; GFX11-NEXT: ; implicit-def: $vgpr77 : SGPR spill to VGPR lane -; GFX11-NEXT: v_writelane_b32 v75, s39, 7 -; GFX11-NEXT: v_writelane_b32 v76, s103, 7 ; GFX11-NEXT: v_writelane_b32 v75, s48, 8 ; GFX11-NEXT: v_writelane_b32 v76, s104, 8 ; GFX11-NEXT: v_writelane_b32 v75, s49, 9 @@ -218952,19 +215266,19 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX11-NEXT: s_lshr_b32 s87, s14, 8 ; GFX11-NEXT: v_writelane_b32 v78, s42, 29 ; GFX11-NEXT: s_lshr_b32 s42, s22, 16 -; GFX11-NEXT: s_lshr_b32 s96, s41, 24 -; GFX11-NEXT: s_lshr_b32 s97, s41, 16 -; GFX11-NEXT: s_lshr_b32 s100, s41, 8 +; GFX11-NEXT: s_lshr_b32 s96, s29, 24 +; GFX11-NEXT: s_lshr_b32 s97, s29, 16 +; GFX11-NEXT: s_lshr_b32 s100, s29, 8 ; GFX11-NEXT: v_writelane_b32 v78, s42, 28 ; GFX11-NEXT: s_lshr_b32 s42, s22, 8 -; GFX11-NEXT: s_lshr_b32 s98, s40, 16 -; GFX11-NEXT: s_lshr_b32 s101, s40, 8 -; GFX11-NEXT: s_lshr_b32 s102, s29, 24 +; GFX11-NEXT: s_lshr_b32 s98, s28, 16 +; GFX11-NEXT: s_lshr_b32 s101, s28, 8 +; GFX11-NEXT: s_lshr_b32 s102, s41, 24 ; GFX11-NEXT: v_writelane_b32 v78, s42, 27 ; GFX11-NEXT: s_lshr_b32 s42, s21, 24 -; GFX11-NEXT: s_lshr_b32 s103, s29, 16 -; GFX11-NEXT: s_lshr_b32 vcc_hi, s29, 8 -; GFX11-NEXT: s_lshr_b32 s104, s28, 16 +; GFX11-NEXT: s_lshr_b32 s103, s41, 16 +; GFX11-NEXT: s_lshr_b32 vcc_hi, s41, 8 +; GFX11-NEXT: s_lshr_b32 s104, s40, 16 ; GFX11-NEXT: v_writelane_b32 v78, s42, 26 ; GFX11-NEXT: s_lshr_b32 s42, s21, 16 ; GFX11-NEXT: s_lshr_b64 s[62:63], s[26:27], 24 @@ -218987,8 +215301,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX11-NEXT: s_lshr_b64 s[92:93], s[14:15], 24 ; GFX11-NEXT: v_writelane_b32 v78, s42, 22 ; GFX11-NEXT: s_lshr_b32 s42, s19, 24 -; GFX11-NEXT: s_lshr_b64 s[94:95], s[40:41], 24 -; GFX11-NEXT: s_lshr_b64 s[30:31], s[28:29], 24 +; GFX11-NEXT: s_lshr_b64 s[94:95], s[28:29], 24 +; GFX11-NEXT: s_lshr_b64 s[30:31], s[40:41], 24 ; GFX11-NEXT: v_writelane_b32 v78, s42, 21 ; GFX11-NEXT: s_lshr_b32 s42, s19, 16 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) @@ -219038,7 +215352,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX11-NEXT: s_lshr_b32 s42, s0, 8 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: v_writelane_b32 v78, s42, 2 -; GFX11-NEXT: s_lshr_b32 s42, s28, 8 +; GFX11-NEXT: s_lshr_b32 s42, s40, 8 ; GFX11-NEXT: v_writelane_b32 v78, s74, 0 ; GFX11-NEXT: v_writelane_b32 v78, s75, 1 ; GFX11-NEXT: s_lshr_b64 s[74:75], s[4:5], 24 @@ -219055,10 +215369,10 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX11-NEXT: v_pk_add_u16 v29, s23, 3 op_sel_hi:[1,0] ; GFX11-NEXT: v_pk_add_u16 v28, s22, 3 op_sel_hi:[1,0] ; GFX11-NEXT: v_pk_add_u16 v32, s20, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v16, s29, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v15, s28, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v14, s41, 3 op_sel_hi:[1,0] -; GFX11-NEXT: v_pk_add_u16 v13, s40, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v16, s41, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v15, s40, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v14, s29, 3 op_sel_hi:[1,0] +; GFX11-NEXT: v_pk_add_u16 v13, s28, 3 op_sel_hi:[1,0] ; GFX11-NEXT: v_pk_add_u16 v12, s15, 3 op_sel_hi:[1,0] ; GFX11-NEXT: v_pk_add_u16 v11, s14, 3 op_sel_hi:[1,0] ; GFX11-NEXT: v_pk_add_u16 v10, s13, 3 op_sel_hi:[1,0] @@ -219318,8 +215632,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3 ; GFX11-NEXT: v_dual_mov_b32 v52, s0 :: v_dual_mov_b32 v53, s1 ; GFX11-NEXT: v_readlane_b32 s0, v78, 2 ; GFX11-NEXT: v_mov_b32_e32 v71, s50 -; GFX11-NEXT: v_dual_mov_b32 v15, s28 :: v_dual_mov_b32 v16, s29 -; GFX11-NEXT: v_dual_mov_b32 v13, s40 :: v_dual_mov_b32 v14, s41 +; GFX11-NEXT: v_dual_mov_b32 v15, s40 :: v_dual_mov_b32 v16, s41 +; GFX11-NEXT: v_dual_mov_b32 v13, s28 :: v_dual_mov_b32 v14, s29 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_mov_b32_e32 v74, s0 ; GFX11-NEXT: v_readlane_b32 s0, v78, 3 @@ -224727,655 +221041,724 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg % ; VI-LABEL: bitcast_v64bf16_to_v64f16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: s_or_saveexec_b64 s[4:5], -1 -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v42, s30, 0 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 -; VI-NEXT: v_writelane_b32 v42, s31, 1 +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v31, v17 ; VI-NEXT: v_mov_b32_e32 v30, v16 -; VI-NEXT: v_mov_b32_e32 v29, v15 +; VI-NEXT: v_mov_b32_e32 v48, v15 +; VI-NEXT: v_mov_b32_e32 v49, v13 +; VI-NEXT: v_mov_b32_e32 v50, v11 +; VI-NEXT: v_mov_b32_e32 v51, v9 +; VI-NEXT: v_mov_b32_e32 v52, v7 +; VI-NEXT: v_mov_b32_e32 v53, v5 +; VI-NEXT: v_mov_b32_e32 v54, v3 +; VI-NEXT: v_mov_b32_e32 v55, v1 ; VI-NEXT: v_mov_b32_e32 v28, v14 -; VI-NEXT: v_mov_b32_e32 v27, v13 ; VI-NEXT: v_mov_b32_e32 v26, v12 -; VI-NEXT: v_mov_b32_e32 v25, v11 ; VI-NEXT: v_mov_b32_e32 v24, v10 -; VI-NEXT: v_mov_b32_e32 v23, v9 ; VI-NEXT: v_mov_b32_e32 v22, v8 -; VI-NEXT: v_mov_b32_e32 v21, v7 ; VI-NEXT: v_mov_b32_e32 v20, v6 -; VI-NEXT: v_mov_b32_e32 v19, v5 -; VI-NEXT: v_mov_b32_e32 v32, v4 -; VI-NEXT: v_mov_b32_e32 v17, v3 +; VI-NEXT: v_mov_b32_e32 v40, v4 ; VI-NEXT: v_mov_b32_e32 v16, v2 -; VI-NEXT: v_readfirstlane_b32 s30, v0 +; VI-NEXT: v_mov_b32_e32 v14, v0 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec -; VI-NEXT: v_readfirstlane_b32 s31, v1 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill -; VI-NEXT: s_cbranch_scc0 .LBB101_3 +; VI-NEXT: v_mov_b32_e32 v39, s17 +; VI-NEXT: v_mov_b32_e32 v38, s19 +; VI-NEXT: v_mov_b32_e32 v37, s21 +; VI-NEXT: v_mov_b32_e32 v36, s23 +; VI-NEXT: v_mov_b32_e32 v35, s25 +; VI-NEXT: v_mov_b32_e32 v34, s27 +; VI-NEXT: v_mov_b32_e32 v18, s29 +; VI-NEXT: v_mov_b32_e32 v0, s16 +; VI-NEXT: v_mov_b32_e32 v2, s18 +; VI-NEXT: v_mov_b32_e32 v4, s20 +; VI-NEXT: v_mov_b32_e32 v6, s22 +; VI-NEXT: v_mov_b32_e32 v8, s24 +; VI-NEXT: v_mov_b32_e32 v10, s26 +; VI-NEXT: v_mov_b32_e32 v12, s28 +; VI-NEXT: s_cbranch_scc0 .LBB101_4 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_cbranch_execnz .LBB101_4 +; VI-NEXT: s_cbranch_execnz .LBB101_3 ; VI-NEXT: .LBB101_2: ; %cmp.true -; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000 -; VI-NEXT: s_lshl_b32 s4, s30, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v16 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v16 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s30, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v54 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v3 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v15, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: s_lshl_b32 s4, s31, 16 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_add_f32_e32 v3, s4, v0 -; VI-NEXT: v_bfe_u32 v4, v3, 16, 1 -; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3 -; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4 -; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v54 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; VI-NEXT: s_and_b32 s4, s31, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; VI-NEXT: v_add_f32_e32 v4, s4, v0 -; VI-NEXT: v_bfe_u32 v5, v4, 16, 1 -; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4 -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s29, 16 +; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v40 +; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_cndmask_b32_e32 v15, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v40 ; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 -; VI-NEXT: v_alignbit_b32 v14, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_alignbit_b32 v15, v4, v3, 16 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s29, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v53 +; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v3 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v15, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s28, 16 -; VI-NEXT: v_alignbit_b32 v13, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s28, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 -; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s27, 16 -; VI-NEXT: v_alignbit_b32 v12, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v53 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v20 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_cndmask_b32_e32 v40, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v20 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s27, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v52 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v3 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v20, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s26, 16 -; VI-NEXT: v_alignbit_b32 v11, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s26, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v52 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v22 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_cndmask_b32_e32 v52, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v22 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v51 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v3 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v22, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s25, 16 -; VI-NEXT: v_alignbit_b32 v10, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s25, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v51 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v24 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_cndmask_b32_e32 v42, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v24 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v50 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v3 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v24, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s24, 16 -; VI-NEXT: v_alignbit_b32 v9, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s24, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v50 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v26 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_cndmask_b32_e32 v50, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v26 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v49 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v3 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v26, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s23, 16 -; VI-NEXT: v_alignbit_b32 v8, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s23, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v49 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v28 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_cndmask_b32_e32 v44, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_lshrrev_b32_e32 v45, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v28 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v48 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v3 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v28, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s22, 16 -; VI-NEXT: v_alignbit_b32 v7, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s22, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v48 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v30 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_cndmask_b32_e32 v48, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v30 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v31 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v47, 16, v3 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v46, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s21, 16 -; VI-NEXT: v_alignbit_b32 v6, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s21, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v31 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0 +; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_bfe_u32 v3, v0, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v30, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0 ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s20, 16 -; VI-NEXT: v_alignbit_b32 v5, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v0 +; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v39 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s20, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_bfe_u32 v1, v0, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v16, v3, v5, vcc +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1 +; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v39 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s19, 16 -; VI-NEXT: v_alignbit_b32 v4, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v57, 16, v0 +; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v2 ; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v56, v3, v5, vcc ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 ; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 ; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s19, 0xffff0000 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 ; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 -; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v18, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v18, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s18, 16 -; VI-NEXT: v_alignbit_b32 v3, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 +; VI-NEXT: v_bfe_u32 v2, v0, 16, 1 +; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0 ; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v18, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v38 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; VI-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc +; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1 +; VI-NEXT: v_bfe_u32 v1, v0, 16, 1 +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_cndmask_b32_e32 v0, v1, v5, vcc +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v38 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v5, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s18, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v18, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v18, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v2 -; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18 -; VI-NEXT: v_or_b32_e32 v33, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v18, v33, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s17, 16 -; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v18, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v1 -; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18 -; VI-NEXT: v_or_b32_e32 v33, 0x400000, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v59, 16, v0 +; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v4 +; VI-NEXT: v_bfe_u32 v4, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v58, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v1 +; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s17, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v18, v33, vcc -; VI-NEXT: v_add_f32_e32 v18, s4, v0 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; VI-NEXT: s_lshl_b32 s4, s16, 16 -; VI-NEXT: v_alignbit_b32 v1, v18, v1, 16 -; VI-NEXT: v_add_f32_e32 v18, s4, v0 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: s_and_b32 s4, s16, 0xffff0000 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v0, s4, v0 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v0, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v0 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v0 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; VI-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc +; VI-NEXT: v_bfe_u32 v4, v0, 16, 1 +; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v0 +; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v0 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; VI-NEXT: v_cndmask_b32_e32 v0, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; VI-NEXT: v_alignbit_b32 v0, v0, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v16 +; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v37 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; VI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v1 +; VI-NEXT: v_bfe_u32 v1, v0, 16, 1 +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_cndmask_b32_e32 v0, v1, v7, vcc +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v37 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v7, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v1 +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7 +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v6 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v61, 16, v0 +; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v6 +; VI-NEXT: v_bfe_u32 v6, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v60, v7, v9, vcc +; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v1 +; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; VI-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc +; VI-NEXT: v_bfe_u32 v6, v0, 16, 1 +; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v0 +; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v36 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; VI-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc +; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v1 +; VI-NEXT: v_bfe_u32 v1, v0, 16, 1 +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1 +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_cndmask_b32_e32 v0, v1, v9, vcc +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v36 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v9, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v1 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9 +; VI-NEXT: v_or_b32_e32 v11, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v8 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v63, 16, v0 +; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v8 +; VI-NEXT: v_bfe_u32 v8, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v62, v9, v11, vcc +; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v1 +; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8 +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; VI-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc +; VI-NEXT: v_bfe_u32 v8, v0, 16, 1 +; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v0 +; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8 +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v35 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; VI-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc +; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v1 +; VI-NEXT: v_bfe_u32 v1, v0, 16, 1 +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1 +; VI-NEXT: v_or_b32_e32 v11, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v35 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; VI-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc +; VI-NEXT: v_bfe_u32 v11, v0, 16, 1 +; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v0 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 +; VI-NEXT: v_or_b32_e32 v13, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_cndmask_b32_e32 v0, v11, v13, vcc +; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 +; VI-NEXT: v_bfe_u32 v13, v10, 16, 1 +; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v10 +; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 +; VI-NEXT: v_or_b32_e32 v15, 0x400000, v10 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 +; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v11 +; VI-NEXT: v_bfe_u32 v11, v10, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc +; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v10 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 +; VI-NEXT: v_or_b32_e32 v15, 0x400000, v10 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 +; VI-NEXT: v_cndmask_b32_e32 v10, v11, v15, vcc +; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v13 +; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v34 +; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; VI-NEXT: v_bfe_u32 v15, v13, 16, 1 +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 +; VI-NEXT: v_or_b32_e32 v19, 0x400000, v13 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 +; VI-NEXT: v_cndmask_b32_e32 v13, v15, v19, vcc +; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v34 +; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; VI-NEXT: v_bfe_u32 v19, v15, 16, 1 +; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v15 +; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v13 +; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v12 +; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; VI-NEXT: v_add_u32_e32 v19, vcc, 0x7fff, v19 +; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 +; VI-NEXT: v_or_b32_e32 v32, 0x400000, v15 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 +; VI-NEXT: v_bfe_u32 v15, v12, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v32, v19, v32, vcc +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v12 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 +; VI-NEXT: v_or_b32_e32 v19, 0x400000, v12 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 +; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v13 +; VI-NEXT: v_bfe_u32 v13, v12, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v15, v15, v19, vcc +; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v12 +; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 +; VI-NEXT: v_or_b32_e32 v19, 0x400000, v12 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 +; VI-NEXT: v_cndmask_b32_e32 v12, v13, v19, vcc +; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v15 +; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v18 +; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; VI-NEXT: v_bfe_u32 v19, v15, 16, 1 +; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v15 +; VI-NEXT: v_add_u32_e32 v19, vcc, 0x7fff, v19 +; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; VI-NEXT: v_or_b32_e32 v34, 0x400000, v15 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 ; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; VI-NEXT: v_cndmask_b32_e32 v15, v19, v34, vcc +; VI-NEXT: v_bfe_u32 v19, v18, 16, 1 +; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v18 +; VI-NEXT: v_add_u32_e32 v19, vcc, 0x7fff, v19 ; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v16, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v16 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v16 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16 -; VI-NEXT: v_cndmask_b32_e32 v16, v33, v34, vcc -; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v17 -; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33 -; VI-NEXT: v_bfe_u32 v34, v33, 16, 1 -; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33 -; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34 -; VI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33 -; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 -; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc -; VI-NEXT: v_bfe_u32 v34, v17, 16, 1 -; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v17 +; VI-NEXT: v_cndmask_b32_e32 v18, v19, v34, vcc +; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v15 +; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v14 +; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 +; VI-NEXT: v_bfe_u32 v34, v14, 16, 1 +; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v14 ; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34 -; VI-NEXT: v_or_b32_e32 v35, 0x400000, v17 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 -; VI-NEXT: v_cndmask_b32_e32 v17, v34, v35, vcc -; VI-NEXT: v_lshlrev_b32_e32 v34, 16, v32 +; VI-NEXT: v_or_b32_e32 v35, 0x400000, v14 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 +; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v15 +; VI-NEXT: v_bfe_u32 v15, v14, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v34, v34, v35, vcc +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v14 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 +; VI-NEXT: v_or_b32_e32 v35, 0x400000, v14 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 +; VI-NEXT: v_cndmask_b32_e32 v14, v15, v35, vcc +; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v34 +; VI-NEXT: v_and_b32_e32 v34, 0xffff0000, v55 ; VI-NEXT: v_add_f32_e32 v34, 0x40c00000, v34 ; VI-NEXT: v_bfe_u32 v35, v34, 16, 1 ; VI-NEXT: v_add_u32_e32 v35, vcc, v35, v34 ; VI-NEXT: v_add_u32_e32 v35, vcc, 0x7fff, v35 -; VI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32 ; VI-NEXT: v_or_b32_e32 v36, 0x400000, v34 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v34, v34 -; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32 ; VI-NEXT: v_cndmask_b32_e32 v34, v35, v36, vcc -; VI-NEXT: v_bfe_u32 v35, v32, 16, 1 -; VI-NEXT: v_add_u32_e32 v35, vcc, v35, v32 -; VI-NEXT: v_add_u32_e32 v35, vcc, 0x7fff, v35 -; VI-NEXT: v_or_b32_e32 v36, 0x400000, v32 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 -; VI-NEXT: v_cndmask_b32_e32 v32, v35, v36, vcc -; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v19 +; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v55 ; VI-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 ; VI-NEXT: v_bfe_u32 v36, v35, 16, 1 ; VI-NEXT: v_add_u32_e32 v36, vcc, v36, v35 ; VI-NEXT: v_add_u32_e32 v36, vcc, 0x7fff, v36 -; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 ; VI-NEXT: v_or_b32_e32 v37, 0x400000, v35 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v35, v35 -; VI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 -; VI-NEXT: v_cndmask_b32_e32 v35, v36, v37, vcc -; VI-NEXT: v_bfe_u32 v36, v19, 16, 1 -; VI-NEXT: v_add_u32_e32 v36, vcc, v36, v19 -; VI-NEXT: v_add_u32_e32 v36, vcc, 0x7fff, v36 -; VI-NEXT: v_or_b32_e32 v37, 0x400000, v19 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 -; VI-NEXT: v_cndmask_b32_e32 v19, v36, v37, vcc -; VI-NEXT: v_lshlrev_b32_e32 v36, 16, v20 -; VI-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 -; VI-NEXT: v_bfe_u32 v37, v36, 16, 1 -; VI-NEXT: v_add_u32_e32 v37, vcc, v37, v36 -; VI-NEXT: v_add_u32_e32 v37, vcc, 0x7fff, v37 -; VI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; VI-NEXT: v_or_b32_e32 v38, 0x400000, v36 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v36, v36 -; VI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 -; VI-NEXT: v_cndmask_b32_e32 v36, v37, v38, vcc -; VI-NEXT: v_bfe_u32 v37, v20, 16, 1 -; VI-NEXT: v_add_u32_e32 v37, vcc, v37, v20 -; VI-NEXT: v_add_u32_e32 v37, vcc, 0x7fff, v37 -; VI-NEXT: v_or_b32_e32 v38, 0x400000, v20 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 -; VI-NEXT: v_cndmask_b32_e32 v20, v37, v38, vcc -; VI-NEXT: v_lshlrev_b32_e32 v37, 16, v21 -; VI-NEXT: v_add_f32_e32 v37, 0x40c00000, v37 -; VI-NEXT: v_bfe_u32 v38, v37, 16, 1 -; VI-NEXT: v_add_u32_e32 v38, vcc, v38, v37 -; VI-NEXT: v_add_u32_e32 v38, vcc, 0x7fff, v38 -; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; VI-NEXT: v_or_b32_e32 v39, 0x400000, v37 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 -; VI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 -; VI-NEXT: v_cndmask_b32_e32 v37, v38, v39, vcc -; VI-NEXT: v_bfe_u32 v38, v21, 16, 1 -; VI-NEXT: v_add_u32_e32 v38, vcc, v38, v21 -; VI-NEXT: v_add_u32_e32 v38, vcc, 0x7fff, v38 -; VI-NEXT: v_or_b32_e32 v39, 0x400000, v21 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 -; VI-NEXT: v_cndmask_b32_e32 v21, v38, v39, vcc -; VI-NEXT: v_lshlrev_b32_e32 v38, 16, v22 -; VI-NEXT: v_add_f32_e32 v38, 0x40c00000, v38 -; VI-NEXT: v_bfe_u32 v39, v38, 16, 1 -; VI-NEXT: v_add_u32_e32 v39, vcc, v39, v38 -; VI-NEXT: v_add_u32_e32 v39, vcc, 0x7fff, v39 -; VI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; VI-NEXT: v_or_b32_e32 v48, 0x400000, v38 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v38, v38 -; VI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 -; VI-NEXT: v_cndmask_b32_e32 v38, v39, v48, vcc -; VI-NEXT: v_bfe_u32 v39, v22, 16, 1 -; VI-NEXT: v_add_u32_e32 v39, vcc, v39, v22 -; VI-NEXT: v_add_u32_e32 v39, vcc, 0x7fff, v39 -; VI-NEXT: v_or_b32_e32 v48, 0x400000, v22 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 -; VI-NEXT: v_cndmask_b32_e32 v22, v39, v48, vcc -; VI-NEXT: v_lshlrev_b32_e32 v39, 16, v23 -; VI-NEXT: v_add_f32_e32 v39, 0x40c00000, v39 -; VI-NEXT: v_bfe_u32 v48, v39, 16, 1 -; VI-NEXT: v_add_u32_e32 v48, vcc, v48, v39 -; VI-NEXT: v_add_u32_e32 v48, vcc, 0x7fff, v48 -; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; VI-NEXT: v_or_b32_e32 v49, 0x400000, v39 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v39, v39 -; VI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 -; VI-NEXT: v_cndmask_b32_e32 v39, v48, v49, vcc -; VI-NEXT: v_bfe_u32 v48, v23, 16, 1 -; VI-NEXT: v_add_u32_e32 v48, vcc, v48, v23 -; VI-NEXT: v_add_u32_e32 v48, vcc, 0x7fff, v48 -; VI-NEXT: v_or_b32_e32 v49, 0x400000, v23 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 -; VI-NEXT: v_cndmask_b32_e32 v23, v48, v49, vcc -; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v24 -; VI-NEXT: v_add_f32_e32 v48, 0x40c00000, v48 -; VI-NEXT: v_bfe_u32 v49, v48, 16, 1 -; VI-NEXT: v_add_u32_e32 v49, vcc, v49, v48 -; VI-NEXT: v_add_u32_e32 v49, vcc, 0x7fff, v49 -; VI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; VI-NEXT: v_or_b32_e32 v50, 0x400000, v48 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v48, v48 -; VI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 -; VI-NEXT: v_cndmask_b32_e32 v48, v49, v50, vcc -; VI-NEXT: v_bfe_u32 v49, v24, 16, 1 -; VI-NEXT: v_add_u32_e32 v49, vcc, v49, v24 -; VI-NEXT: v_add_u32_e32 v49, vcc, 0x7fff, v49 -; VI-NEXT: v_or_b32_e32 v50, 0x400000, v24 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; VI-NEXT: v_cndmask_b32_e32 v24, v49, v50, vcc -; VI-NEXT: v_lshlrev_b32_e32 v49, 16, v25 -; VI-NEXT: v_add_f32_e32 v49, 0x40c00000, v49 -; VI-NEXT: v_bfe_u32 v50, v49, 16, 1 -; VI-NEXT: v_add_u32_e32 v50, vcc, v50, v49 -; VI-NEXT: v_add_u32_e32 v50, vcc, 0x7fff, v50 -; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; VI-NEXT: v_or_b32_e32 v51, 0x400000, v49 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v49, v49 -; VI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 -; VI-NEXT: v_cndmask_b32_e32 v49, v50, v51, vcc -; VI-NEXT: v_bfe_u32 v50, v25, 16, 1 -; VI-NEXT: v_add_u32_e32 v50, vcc, v50, v25 -; VI-NEXT: v_add_u32_e32 v50, vcc, 0x7fff, v50 -; VI-NEXT: v_or_b32_e32 v51, 0x400000, v25 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 -; VI-NEXT: v_cndmask_b32_e32 v25, v50, v51, vcc -; VI-NEXT: v_lshlrev_b32_e32 v50, 16, v26 -; VI-NEXT: v_add_f32_e32 v50, 0x40c00000, v50 -; VI-NEXT: v_bfe_u32 v51, v50, 16, 1 -; VI-NEXT: v_add_u32_e32 v51, vcc, v51, v50 -; VI-NEXT: v_add_u32_e32 v51, vcc, 0x7fff, v51 -; VI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; VI-NEXT: v_or_b32_e32 v52, 0x400000, v50 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 -; VI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 -; VI-NEXT: v_cndmask_b32_e32 v50, v51, v52, vcc -; VI-NEXT: v_bfe_u32 v51, v26, 16, 1 -; VI-NEXT: v_add_u32_e32 v51, vcc, v51, v26 -; VI-NEXT: v_add_u32_e32 v51, vcc, 0x7fff, v51 -; VI-NEXT: v_or_b32_e32 v52, 0x400000, v26 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 -; VI-NEXT: v_cndmask_b32_e32 v26, v51, v52, vcc -; VI-NEXT: v_lshlrev_b32_e32 v51, 16, v27 -; VI-NEXT: v_add_f32_e32 v51, 0x40c00000, v51 -; VI-NEXT: v_bfe_u32 v52, v51, 16, 1 -; VI-NEXT: v_add_u32_e32 v52, vcc, v52, v51 -; VI-NEXT: v_add_u32_e32 v52, vcc, 0x7fff, v52 -; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; VI-NEXT: v_or_b32_e32 v53, 0x400000, v51 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 -; VI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 -; VI-NEXT: v_cndmask_b32_e32 v51, v52, v53, vcc -; VI-NEXT: v_bfe_u32 v52, v27, 16, 1 -; VI-NEXT: v_add_u32_e32 v52, vcc, v52, v27 -; VI-NEXT: v_add_u32_e32 v52, vcc, 0x7fff, v52 -; VI-NEXT: v_or_b32_e32 v53, 0x400000, v27 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 -; VI-NEXT: v_cndmask_b32_e32 v27, v52, v53, vcc -; VI-NEXT: v_lshlrev_b32_e32 v52, 16, v28 -; VI-NEXT: v_add_f32_e32 v52, 0x40c00000, v52 -; VI-NEXT: v_bfe_u32 v53, v52, 16, 1 -; VI-NEXT: v_add_u32_e32 v53, vcc, v53, v52 -; VI-NEXT: v_add_u32_e32 v53, vcc, 0x7fff, v53 -; VI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; VI-NEXT: v_or_b32_e32 v54, 0x400000, v52 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v52, v52 -; VI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 -; VI-NEXT: v_cndmask_b32_e32 v52, v53, v54, vcc -; VI-NEXT: v_bfe_u32 v53, v28, 16, 1 -; VI-NEXT: v_add_u32_e32 v53, vcc, v53, v28 -; VI-NEXT: v_add_u32_e32 v53, vcc, 0x7fff, v53 -; VI-NEXT: v_or_b32_e32 v54, 0x400000, v28 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 -; VI-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc -; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v29 -; VI-NEXT: v_add_f32_e32 v53, 0x40c00000, v53 -; VI-NEXT: v_bfe_u32 v54, v53, 16, 1 -; VI-NEXT: v_add_u32_e32 v54, vcc, v54, v53 -; VI-NEXT: v_add_u32_e32 v54, vcc, 0x7fff, v54 -; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; VI-NEXT: v_or_b32_e32 v55, 0x400000, v53 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v53, v53 -; VI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 -; VI-NEXT: v_cndmask_b32_e32 v53, v54, v55, vcc -; VI-NEXT: v_bfe_u32 v54, v29, 16, 1 -; VI-NEXT: v_add_u32_e32 v54, vcc, v54, v29 -; VI-NEXT: v_add_u32_e32 v54, vcc, 0x7fff, v54 -; VI-NEXT: v_or_b32_e32 v55, 0x400000, v29 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 -; VI-NEXT: v_cndmask_b32_e32 v29, v54, v55, vcc -; VI-NEXT: v_lshlrev_b32_e32 v54, 16, v30 -; VI-NEXT: v_add_f32_e32 v54, 0x40c00000, v54 -; VI-NEXT: v_bfe_u32 v55, v54, 16, 1 -; VI-NEXT: v_add_u32_e32 v55, vcc, v55, v54 -; VI-NEXT: v_add_u32_e32 v55, vcc, 0x7fff, v55 -; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; VI-NEXT: v_or_b32_e32 v40, 0x400000, v54 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v54, v54 -; VI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 -; VI-NEXT: v_cndmask_b32_e32 v54, v55, v40, vcc -; VI-NEXT: v_bfe_u32 v55, v30, 16, 1 -; VI-NEXT: v_add_u32_e32 v55, vcc, v55, v30 -; VI-NEXT: v_add_u32_e32 v55, vcc, 0x7fff, v55 -; VI-NEXT: v_or_b32_e32 v40, 0x400000, v30 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 -; VI-NEXT: v_cndmask_b32_e32 v30, v55, v40, vcc -; VI-NEXT: v_lshlrev_b32_e32 v55, 16, v31 -; VI-NEXT: v_add_f32_e32 v55, 0x40c00000, v55 -; VI-NEXT: v_bfe_u32 v40, v55, 16, 1 -; VI-NEXT: v_add_u32_e32 v40, vcc, v40, v55 -; VI-NEXT: v_add_u32_e32 v40, vcc, 0x7fff, v40 -; VI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 -; VI-NEXT: v_or_b32_e32 v41, 0x400000, v55 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v55, v55 -; VI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 -; VI-NEXT: v_cndmask_b32_e32 v55, v40, v41, vcc -; VI-NEXT: v_bfe_u32 v40, v31, 16, 1 -; VI-NEXT: v_add_u32_e32 v40, vcc, v40, v31 -; VI-NEXT: v_add_u32_e32 v40, vcc, 0x7fff, v40 -; VI-NEXT: v_or_b32_e32 v41, 0x400000, v31 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31 -; VI-NEXT: v_cndmask_b32_e32 v31, v40, v41, vcc -; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v29 -; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v28 -; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v26 -; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 -; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v23 -; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v22 -; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; VI-NEXT: v_alignbit_b32 v31, v31, v55, 16 -; VI-NEXT: v_alignbit_b32 v30, v30, v54, 16 -; VI-NEXT: v_alignbit_b32 v29, v29, v53, 16 -; VI-NEXT: v_alignbit_b32 v28, v28, v52, 16 -; VI-NEXT: v_alignbit_b32 v27, v27, v51, 16 -; VI-NEXT: v_alignbit_b32 v26, v26, v50, 16 -; VI-NEXT: v_alignbit_b32 v25, v25, v49, 16 -; VI-NEXT: v_alignbit_b32 v24, v24, v48, 16 -; VI-NEXT: v_alignbit_b32 v23, v23, v39, 16 -; VI-NEXT: v_alignbit_b32 v22, v22, v38, 16 -; VI-NEXT: v_alignbit_b32 v21, v21, v37, 16 -; VI-NEXT: v_alignbit_b32 v20, v20, v36, 16 -; VI-NEXT: v_alignbit_b32 v19, v19, v35, 16 -; VI-NEXT: v_alignbit_b32 v32, v32, v34, 16 -; VI-NEXT: v_alignbit_b32 v17, v17, v33, 16 -; VI-NEXT: v_alignbit_b32 v16, v16, v18, 16 -; VI-NEXT: s_branch .LBB101_5 -; VI-NEXT: .LBB101_3: -; VI-NEXT: s_branch .LBB101_2 -; VI-NEXT: .LBB101_4: -; VI-NEXT: v_mov_b32_e32 v0, s16 -; VI-NEXT: v_mov_b32_e32 v1, s17 -; VI-NEXT: v_mov_b32_e32 v2, s18 -; VI-NEXT: v_mov_b32_e32 v3, s19 -; VI-NEXT: v_mov_b32_e32 v4, s20 -; VI-NEXT: v_mov_b32_e32 v5, s21 -; VI-NEXT: v_mov_b32_e32 v6, s22 -; VI-NEXT: v_mov_b32_e32 v7, s23 -; VI-NEXT: v_mov_b32_e32 v8, s24 -; VI-NEXT: v_mov_b32_e32 v9, s25 -; VI-NEXT: v_mov_b32_e32 v10, s26 -; VI-NEXT: v_mov_b32_e32 v11, s27 -; VI-NEXT: v_mov_b32_e32 v12, s28 -; VI-NEXT: v_mov_b32_e32 v13, s29 -; VI-NEXT: v_mov_b32_e32 v14, s30 -; VI-NEXT: v_mov_b32_e32 v15, s31 -; VI-NEXT: .LBB101_5: ; %end -; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload -; VI-NEXT: v_mov_b32_e32 v18, v32 -; VI-NEXT: v_readlane_b32 s31, v42, 1 -; VI-NEXT: v_readlane_b32 s30, v42, 0 -; VI-NEXT: s_or_saveexec_b64 s[4:5], -1 -; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload -; VI-NEXT: s_mov_b64 exec, s[4:5] +; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v34 +; VI-NEXT: v_lshrrev_b64 v[34:35], 16, v[56:57] +; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; VI-NEXT: v_mov_b32_e32 v39, v34 +; VI-NEXT: v_lshrrev_b64 v[34:35], 16, v[58:59] +; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1] +; VI-NEXT: v_mov_b32_e32 v38, v34 +; VI-NEXT: v_lshrrev_b64 v[34:35], 16, v[60:61] +; VI-NEXT: v_cndmask_b32_e32 v54, v36, v37, vcc +; VI-NEXT: v_mov_b32_e32 v37, v34 +; VI-NEXT: v_lshrrev_b64 v[34:35], 16, v[62:63] +; VI-NEXT: v_mov_b32_e32 v35, v0 +; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[32:33] +; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; VI-NEXT: v_mov_b32_e32 v36, v34 +; VI-NEXT: v_mov_b32_e32 v34, v0 +; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[54:55] +; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[14:15] +; VI-NEXT: v_mov_b32_e32 v55, v0 +; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[40:41] +; VI-NEXT: v_lshrrev_b64 v[18:19], 16, v[18:19] +; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[12:13] +; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[10:11] +; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[8:9] +; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[6:7] +; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[4:5] +; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[2:3] +; VI-NEXT: v_lshrrev_b64 v[28:29], 16, v[28:29] +; VI-NEXT: v_lshrrev_b64 v[26:27], 16, v[26:27] +; VI-NEXT: v_lshrrev_b64 v[24:25], 16, v[24:25] +; VI-NEXT: v_lshrrev_b64 v[22:23], 16, v[22:23] +; VI-NEXT: v_lshrrev_b64 v[20:21], 16, v[20:21] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshrrev_b64 v[32:33], 16, v[32:33] +; VI-NEXT: v_mov_b32_e32 v54, v32 +; VI-NEXT: v_lshrrev_b64 v[32:33], 16, v[52:53] +; VI-NEXT: v_mov_b32_e32 v53, v0 +; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[42:43] +; VI-NEXT: v_mov_b32_e32 v52, v32 +; VI-NEXT: v_lshrrev_b64 v[32:33], 16, v[50:51] +; VI-NEXT: v_mov_b32_e32 v51, v0 +; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[44:45] +; VI-NEXT: v_mov_b32_e32 v50, v32 +; VI-NEXT: v_lshrrev_b64 v[32:33], 16, v[48:49] +; VI-NEXT: v_mov_b32_e32 v49, v0 +; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[16:17] +; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; VI-NEXT: v_mov_b32_e32 v48, v32 +; VI-NEXT: v_lshrrev_b64 v[32:33], 16, v[30:31] +; VI-NEXT: v_lshrrev_b64 v[30:31], 16, v[46:47] +; VI-NEXT: v_mov_b32_e32 v31, v32 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshrrev_b64 v[40:41], 16, v[15:16] +; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[15:16] +; VI-NEXT: .LBB101_3: ; %end +; VI-NEXT: v_mov_b32_e32 v13, v18 +; VI-NEXT: v_mov_b32_e32 v18, v40 +; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; VI-NEXT: v_mov_b32_e32 v1, v39 +; VI-NEXT: v_mov_b32_e32 v3, v38 +; VI-NEXT: v_mov_b32_e32 v5, v37 +; VI-NEXT: v_mov_b32_e32 v7, v36 +; VI-NEXT: v_mov_b32_e32 v9, v35 +; VI-NEXT: v_mov_b32_e32 v11, v34 +; VI-NEXT: v_mov_b32_e32 v15, v55 +; VI-NEXT: v_mov_b32_e32 v17, v54 +; VI-NEXT: v_mov_b32_e32 v19, v53 +; VI-NEXT: v_mov_b32_e32 v21, v52 +; VI-NEXT: v_mov_b32_e32 v23, v51 +; VI-NEXT: v_mov_b32_e32 v25, v50 +; VI-NEXT: v_mov_b32_e32 v27, v49 +; VI-NEXT: v_mov_b32_e32 v29, v48 ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_setpc_b64 s[30:31] +; VI-NEXT: .LBB101_4: +; VI-NEXT: s_branch .LBB101_2 ; ; GFX9-LABEL: bitcast_v64bf16_to_v64f16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v43, s30, 0 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 -; GFX9-NEXT: v_writelane_b32 v43, s31, 1 +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v31, v17 ; GFX9-NEXT: v_mov_b32_e32 v30, v16 ; GFX9-NEXT: v_mov_b32_e32 v29, v15 @@ -225392,658 +221775,669 @@ define inreg <64 x half> @bitcast_v64bf16_to_v64f16_scalar(<64 x bfloat> inreg % ; GFX9-NEXT: v_mov_b32_e32 v32, v4 ; GFX9-NEXT: v_mov_b32_e32 v17, v3 ; GFX9-NEXT: v_mov_b32_e32 v16, v2 -; GFX9-NEXT: v_readfirstlane_b32 s30, v0 +; GFX9-NEXT: v_mov_b32_e32 v63, v1 +; GFX9-NEXT: v_mov_b32_e32 v14, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s16 +; GFX9-NEXT: v_mov_b32_e32 v1, s17 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec -; GFX9-NEXT: v_readfirstlane_b32 s31, v1 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill -; GFX9-NEXT: s_cbranch_scc0 .LBB101_3 +; GFX9-NEXT: v_mov_b32_e32 v2, s18 +; GFX9-NEXT: v_mov_b32_e32 v3, s19 +; GFX9-NEXT: v_mov_b32_e32 v4, s20 +; GFX9-NEXT: v_mov_b32_e32 v5, s21 +; GFX9-NEXT: v_mov_b32_e32 v6, s22 +; GFX9-NEXT: v_mov_b32_e32 v7, s23 +; GFX9-NEXT: v_mov_b32_e32 v8, s24 +; GFX9-NEXT: v_mov_b32_e32 v9, s25 +; GFX9-NEXT: v_mov_b32_e32 v10, s26 +; GFX9-NEXT: v_mov_b32_e32 v11, s27 +; GFX9-NEXT: v_mov_b32_e32 v12, s28 +; GFX9-NEXT: v_mov_b32_e32 v13, s29 +; GFX9-NEXT: s_cbranch_scc0 .LBB101_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false -; GFX9-NEXT: s_cbranch_execnz .LBB101_4 +; GFX9-NEXT: s_cbranch_execnz .LBB101_3 ; GFX9-NEXT: .LBB101_2: ; %cmp.true -; GFX9-NEXT: v_mov_b32_e32 v0, 0x40c00000 -; GFX9-NEXT: s_and_b32 s4, s30, 0xffff0000 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s30, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b32 s4, s31, 0xffff0000 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_add_f32_e32 v3, s4, v0 -; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v4, v4, v3 -; GFX9-NEXT: v_add_u32_e32 v4, 0x7fff, v4 -; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX9-NEXT: s_lshl_b32 s4, s31, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX9-NEXT: v_add_f32_e32 v4, s4, v0 -; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1 -; GFX9-NEXT: v_mov_b32_e32 v18, 0xffff -; GFX9-NEXT: v_add_u32_e32 v5, v5, v4 -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_and_b32_sdwa v2, v18, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: s_and_b32 s4, s29, 0xffff0000 -; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5 -; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; GFX9-NEXT: v_lshl_or_b32 v14, v1, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3 -; GFX9-NEXT: v_and_b32_sdwa v4, v18, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_lshl_or_b32 v15, v3, 16, v4 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s29, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_and_b32_sdwa v2, v18, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: s_and_b32 s4, s28, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v13, v1, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s28, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_and_b32_sdwa v2, v18, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: s_and_b32 s4, s27, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v12, v1, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s27, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_and_b32_sdwa v2, v18, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: s_and_b32 s4, s26, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v11, v1, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s26, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_and_b32_sdwa v2, v18, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: s_and_b32 s4, s25, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v10, v1, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s25, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_and_b32_sdwa v2, v18, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: s_and_b32 s4, s24, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v9, v1, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s24, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_and_b32_sdwa v2, v18, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: s_and_b32 s4, s23, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v8, v1, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s23, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_and_b32_sdwa v2, v18, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: s_and_b32 s4, s22, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v7, v1, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s22, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_and_b32_sdwa v2, v18, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: s_and_b32 s4, s21, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v6, v1, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s21, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_and_b32_sdwa v2, v18, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: s_and_b32 s4, s20, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v5, v1, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s20, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_and_b32_sdwa v2, v18, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: s_and_b32 s4, s19, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v4, v1, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s19, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v33, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v33, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_and_b32_sdwa v2, v18, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: s_and_b32 s4, s18, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v3, v1, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v33, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s18, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v33, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v33, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v33, v33, v2 +; GFX9-NEXT: v_and_b32_e32 v18, 0xffff0000, v16 +; GFX9-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 +; GFX9-NEXT: v_bfe_u32 v33, v18, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v33, v33, v18 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16 ; GFX9-NEXT: v_add_u32_e32 v33, 0x7fff, v33 -; GFX9-NEXT: v_or_b32_e32 v34, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v33, v34, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_and_b32_sdwa v2, v18, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: s_and_b32 s4, s17, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v2, v1, 16, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v33, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v33, v33, v1 +; GFX9-NEXT: v_or_b32_e32 v34, 0x400000, v18 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 +; GFX9-NEXT: v_cndmask_b32_e32 v15, v33, v34, vcc +; GFX9-NEXT: v_bfe_u32 v33, v16, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v33, v33, v16 ; GFX9-NEXT: v_add_u32_e32 v33, 0x7fff, v33 -; GFX9-NEXT: v_or_b32_e32 v34, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s17, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc -; GFX9-NEXT: v_add_f32_e32 v33, s4, v0 -; GFX9-NEXT: v_bfe_u32 v34, v33, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v34, v34, v33 -; GFX9-NEXT: v_add_u32_e32 v34, 0x7fff, v34 -; GFX9-NEXT: v_or_b32_e32 v35, 0x400000, v33 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v33, v33 -; GFX9-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; GFX9-NEXT: v_and_b32_sdwa v33, v18, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: s_and_b32 s4, s16, 0xffff0000 -; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v33 -; GFX9-NEXT: v_add_f32_e32 v33, s4, v0 -; GFX9-NEXT: v_bfe_u32 v34, v33, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v34, v34, v33 -; GFX9-NEXT: s_lshl_b32 s4, s16, 16 -; GFX9-NEXT: v_add_u32_e32 v34, 0x7fff, v34 -; GFX9-NEXT: v_or_b32_e32 v35, 0x400000, v33 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v33, v33 -; GFX9-NEXT: v_add_f32_e32 v0, s4, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc -; GFX9-NEXT: v_bfe_u32 v34, v0, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v34, v34, v0 -; GFX9-NEXT: v_add_u32_e32 v34, 0x7fff, v34 -; GFX9-NEXT: v_or_b32_e32 v35, 0x400000, v0 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v34, v35, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v33 -; GFX9-NEXT: v_and_b32_sdwa v0, v18, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: v_lshl_or_b32 v0, v33, 16, v0 -; GFX9-NEXT: v_and_b32_e32 v33, 0xffff0000, v16 +; GFX9-NEXT: v_or_b32_e32 v34, 0x400000, v16 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16 +; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-NEXT: v_cndmask_b32_e32 v15, v33, v34, vcc +; GFX9-NEXT: v_and_b32_e32 v33, 0xffff0000, v17 ; GFX9-NEXT: v_add_f32_e32 v33, 0x40c00000, v33 ; GFX9-NEXT: v_bfe_u32 v34, v33, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v34, v34, v33 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17 ; GFX9-NEXT: v_add_u32_e32 v34, 0x7fff, v34 ; GFX9-NEXT: v_or_b32_e32 v35, 0x400000, v33 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v33, v33 -; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; GFX9-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc -; GFX9-NEXT: v_bfe_u32 v34, v16, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v34, v34, v16 +; GFX9-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 +; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-NEXT: v_cndmask_b32_e32 v15, v34, v35, vcc +; GFX9-NEXT: v_bfe_u32 v34, v17, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v34, v34, v17 ; GFX9-NEXT: v_add_u32_e32 v34, 0x7fff, v34 -; GFX9-NEXT: v_or_b32_e32 v35, 0x400000, v16 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16 -; GFX9-NEXT: v_cndmask_b32_e32 v16, v34, v35, vcc -; GFX9-NEXT: v_and_b32_e32 v34, 0xffff0000, v17 +; GFX9-NEXT: v_or_b32_e32 v35, 0x400000, v17 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 +; GFX9-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc +; GFX9-NEXT: v_and_b32_e32 v34, 0xffff0000, v32 ; GFX9-NEXT: v_add_f32_e32 v34, 0x40c00000, v34 ; GFX9-NEXT: v_bfe_u32 v35, v34, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v35, v35, v34 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v32 ; GFX9-NEXT: v_add_u32_e32 v35, 0x7fff, v35 ; GFX9-NEXT: v_or_b32_e32 v36, 0x400000, v34 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v34, v34 -; GFX9-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 +; GFX9-NEXT: v_add_f32_e32 v32, 0x40c00000, v32 ; GFX9-NEXT: v_cndmask_b32_e32 v34, v35, v36, vcc -; GFX9-NEXT: v_bfe_u32 v35, v17, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v35, v35, v17 +; GFX9-NEXT: v_bfe_u32 v35, v32, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v35, v35, v32 ; GFX9-NEXT: v_add_u32_e32 v35, 0x7fff, v35 -; GFX9-NEXT: v_or_b32_e32 v36, 0x400000, v17 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 -; GFX9-NEXT: v_cndmask_b32_e32 v17, v35, v36, vcc -; GFX9-NEXT: v_and_b32_e32 v35, 0xffff0000, v32 +; GFX9-NEXT: v_or_b32_e32 v36, 0x400000, v32 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 +; GFX9-NEXT: v_cndmask_b32_e32 v32, v35, v36, vcc +; GFX9-NEXT: v_and_b32_e32 v35, 0xffff0000, v19 ; GFX9-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 ; GFX9-NEXT: v_bfe_u32 v36, v35, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v36, v36, v35 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v32 +; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v19 ; GFX9-NEXT: v_add_u32_e32 v36, 0x7fff, v36 ; GFX9-NEXT: v_or_b32_e32 v37, 0x400000, v35 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v35, v35 -; GFX9-NEXT: v_add_f32_e32 v32, 0x40c00000, v32 +; GFX9-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 ; GFX9-NEXT: v_cndmask_b32_e32 v35, v36, v37, vcc -; GFX9-NEXT: v_bfe_u32 v36, v32, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v36, v36, v32 +; GFX9-NEXT: v_bfe_u32 v36, v19, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v36, v36, v19 ; GFX9-NEXT: v_add_u32_e32 v36, 0x7fff, v36 -; GFX9-NEXT: v_or_b32_e32 v37, 0x400000, v32 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 -; GFX9-NEXT: v_cndmask_b32_e32 v32, v36, v37, vcc -; GFX9-NEXT: v_and_b32_e32 v36, 0xffff0000, v19 +; GFX9-NEXT: v_or_b32_e32 v37, 0x400000, v19 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 +; GFX9-NEXT: v_cndmask_b32_e32 v19, v36, v37, vcc +; GFX9-NEXT: v_and_b32_e32 v36, 0xffff0000, v20 ; GFX9-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 ; GFX9-NEXT: v_bfe_u32 v37, v36, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v37, v37, v36 -; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v20 ; GFX9-NEXT: v_add_u32_e32 v37, 0x7fff, v37 ; GFX9-NEXT: v_or_b32_e32 v38, 0x400000, v36 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v36, v36 -; GFX9-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 +; GFX9-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 ; GFX9-NEXT: v_cndmask_b32_e32 v36, v37, v38, vcc -; GFX9-NEXT: v_bfe_u32 v37, v19, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v37, v37, v19 +; GFX9-NEXT: v_bfe_u32 v37, v20, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v37, v37, v20 ; GFX9-NEXT: v_add_u32_e32 v37, 0x7fff, v37 -; GFX9-NEXT: v_or_b32_e32 v38, 0x400000, v19 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v37, v38, vcc -; GFX9-NEXT: v_and_b32_e32 v37, 0xffff0000, v20 +; GFX9-NEXT: v_or_b32_e32 v38, 0x400000, v20 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 +; GFX9-NEXT: v_cndmask_b32_e32 v20, v37, v38, vcc +; GFX9-NEXT: v_and_b32_e32 v37, 0xffff0000, v21 ; GFX9-NEXT: v_add_f32_e32 v37, 0x40c00000, v37 ; GFX9-NEXT: v_bfe_u32 v38, v37, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v38, v38, v37 -; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v20 +; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v21 ; GFX9-NEXT: v_add_u32_e32 v38, 0x7fff, v38 ; GFX9-NEXT: v_or_b32_e32 v39, 0x400000, v37 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 -; GFX9-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 +; GFX9-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 ; GFX9-NEXT: v_cndmask_b32_e32 v37, v38, v39, vcc -; GFX9-NEXT: v_bfe_u32 v38, v20, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v38, v38, v20 +; GFX9-NEXT: v_bfe_u32 v38, v21, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v38, v38, v21 ; GFX9-NEXT: v_add_u32_e32 v38, 0x7fff, v38 -; GFX9-NEXT: v_or_b32_e32 v39, 0x400000, v20 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 -; GFX9-NEXT: v_cndmask_b32_e32 v20, v38, v39, vcc -; GFX9-NEXT: v_and_b32_e32 v38, 0xffff0000, v21 +; GFX9-NEXT: v_or_b32_e32 v39, 0x400000, v21 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 +; GFX9-NEXT: v_cndmask_b32_e32 v21, v38, v39, vcc +; GFX9-NEXT: v_and_b32_e32 v38, 0xffff0000, v22 ; GFX9-NEXT: v_add_f32_e32 v38, 0x40c00000, v38 ; GFX9-NEXT: v_bfe_u32 v39, v38, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v39, v39, v38 -; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v22 ; GFX9-NEXT: v_add_u32_e32 v39, 0x7fff, v39 ; GFX9-NEXT: v_or_b32_e32 v48, 0x400000, v38 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v38, v38 -; GFX9-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 +; GFX9-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 ; GFX9-NEXT: v_cndmask_b32_e32 v38, v39, v48, vcc -; GFX9-NEXT: v_bfe_u32 v39, v21, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v39, v39, v21 +; GFX9-NEXT: v_bfe_u32 v39, v22, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v39, v39, v22 ; GFX9-NEXT: v_add_u32_e32 v39, 0x7fff, v39 -; GFX9-NEXT: v_or_b32_e32 v48, 0x400000, v21 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 -; GFX9-NEXT: v_cndmask_b32_e32 v21, v39, v48, vcc -; GFX9-NEXT: v_and_b32_e32 v39, 0xffff0000, v22 +; GFX9-NEXT: v_or_b32_e32 v48, 0x400000, v22 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 +; GFX9-NEXT: v_cndmask_b32_e32 v22, v39, v48, vcc +; GFX9-NEXT: v_and_b32_e32 v39, 0xffff0000, v23 ; GFX9-NEXT: v_add_f32_e32 v39, 0x40c00000, v39 ; GFX9-NEXT: v_bfe_u32 v48, v39, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v48, v48, v39 -; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v22 +; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v23 ; GFX9-NEXT: v_add_u32_e32 v48, 0x7fff, v48 ; GFX9-NEXT: v_or_b32_e32 v49, 0x400000, v39 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v39, v39 -; GFX9-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 +; GFX9-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 ; GFX9-NEXT: v_cndmask_b32_e32 v39, v48, v49, vcc -; GFX9-NEXT: v_bfe_u32 v48, v22, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v48, v48, v22 +; GFX9-NEXT: v_bfe_u32 v48, v23, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v48, v48, v23 ; GFX9-NEXT: v_add_u32_e32 v48, 0x7fff, v48 -; GFX9-NEXT: v_or_b32_e32 v49, 0x400000, v22 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 -; GFX9-NEXT: v_cndmask_b32_e32 v22, v48, v49, vcc -; GFX9-NEXT: v_and_b32_e32 v48, 0xffff0000, v23 +; GFX9-NEXT: v_or_b32_e32 v49, 0x400000, v23 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 +; GFX9-NEXT: v_cndmask_b32_e32 v23, v48, v49, vcc +; GFX9-NEXT: v_and_b32_e32 v48, 0xffff0000, v24 ; GFX9-NEXT: v_add_f32_e32 v48, 0x40c00000, v48 ; GFX9-NEXT: v_bfe_u32 v49, v48, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v49, v49, v48 -; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24 ; GFX9-NEXT: v_add_u32_e32 v49, 0x7fff, v49 ; GFX9-NEXT: v_or_b32_e32 v50, 0x400000, v48 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v48, v48 -; GFX9-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 +; GFX9-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 ; GFX9-NEXT: v_cndmask_b32_e32 v48, v49, v50, vcc -; GFX9-NEXT: v_bfe_u32 v49, v23, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v49, v49, v23 +; GFX9-NEXT: v_bfe_u32 v49, v24, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v49, v49, v24 ; GFX9-NEXT: v_add_u32_e32 v49, 0x7fff, v49 -; GFX9-NEXT: v_or_b32_e32 v50, 0x400000, v23 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 -; GFX9-NEXT: v_cndmask_b32_e32 v23, v49, v50, vcc -; GFX9-NEXT: v_and_b32_e32 v49, 0xffff0000, v24 +; GFX9-NEXT: v_or_b32_e32 v50, 0x400000, v24 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 +; GFX9-NEXT: v_cndmask_b32_e32 v24, v49, v50, vcc +; GFX9-NEXT: v_and_b32_e32 v49, 0xffff0000, v25 ; GFX9-NEXT: v_add_f32_e32 v49, 0x40c00000, v49 ; GFX9-NEXT: v_bfe_u32 v50, v49, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v50, v50, v49 -; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25 ; GFX9-NEXT: v_add_u32_e32 v50, 0x7fff, v50 ; GFX9-NEXT: v_or_b32_e32 v51, 0x400000, v49 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v49, v49 -; GFX9-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 +; GFX9-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 ; GFX9-NEXT: v_cndmask_b32_e32 v49, v50, v51, vcc -; GFX9-NEXT: v_bfe_u32 v50, v24, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v50, v50, v24 +; GFX9-NEXT: v_bfe_u32 v50, v25, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v50, v50, v25 ; GFX9-NEXT: v_add_u32_e32 v50, 0x7fff, v50 -; GFX9-NEXT: v_or_b32_e32 v51, 0x400000, v24 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; GFX9-NEXT: v_cndmask_b32_e32 v24, v50, v51, vcc -; GFX9-NEXT: v_and_b32_e32 v50, 0xffff0000, v25 +; GFX9-NEXT: v_or_b32_e32 v51, 0x400000, v25 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 +; GFX9-NEXT: v_cndmask_b32_e32 v25, v50, v51, vcc +; GFX9-NEXT: v_and_b32_e32 v50, 0xffff0000, v26 ; GFX9-NEXT: v_add_f32_e32 v50, 0x40c00000, v50 ; GFX9-NEXT: v_bfe_u32 v51, v50, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v51, v51, v50 -; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26 ; GFX9-NEXT: v_add_u32_e32 v51, 0x7fff, v51 ; GFX9-NEXT: v_or_b32_e32 v52, 0x400000, v50 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 -; GFX9-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 +; GFX9-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 ; GFX9-NEXT: v_cndmask_b32_e32 v50, v51, v52, vcc -; GFX9-NEXT: v_bfe_u32 v51, v25, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v51, v51, v25 +; GFX9-NEXT: v_bfe_u32 v51, v26, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v51, v51, v26 ; GFX9-NEXT: v_add_u32_e32 v51, 0x7fff, v51 -; GFX9-NEXT: v_or_b32_e32 v52, 0x400000, v25 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 -; GFX9-NEXT: v_cndmask_b32_e32 v25, v51, v52, vcc -; GFX9-NEXT: v_and_b32_e32 v51, 0xffff0000, v26 +; GFX9-NEXT: v_or_b32_e32 v52, 0x400000, v26 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 +; GFX9-NEXT: v_cndmask_b32_e32 v26, v51, v52, vcc +; GFX9-NEXT: v_and_b32_e32 v51, 0xffff0000, v27 ; GFX9-NEXT: v_add_f32_e32 v51, 0x40c00000, v51 ; GFX9-NEXT: v_bfe_u32 v52, v51, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v52, v52, v51 -; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26 +; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27 ; GFX9-NEXT: v_add_u32_e32 v52, 0x7fff, v52 ; GFX9-NEXT: v_or_b32_e32 v53, 0x400000, v51 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 -; GFX9-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 +; GFX9-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 ; GFX9-NEXT: v_cndmask_b32_e32 v51, v52, v53, vcc -; GFX9-NEXT: v_bfe_u32 v52, v26, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v52, v52, v26 +; GFX9-NEXT: v_bfe_u32 v52, v27, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v52, v52, v27 ; GFX9-NEXT: v_add_u32_e32 v52, 0x7fff, v52 -; GFX9-NEXT: v_or_b32_e32 v53, 0x400000, v26 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 -; GFX9-NEXT: v_cndmask_b32_e32 v26, v52, v53, vcc -; GFX9-NEXT: v_and_b32_e32 v52, 0xffff0000, v27 +; GFX9-NEXT: v_or_b32_e32 v53, 0x400000, v27 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 +; GFX9-NEXT: v_cndmask_b32_e32 v27, v52, v53, vcc +; GFX9-NEXT: v_and_b32_e32 v52, 0xffff0000, v28 ; GFX9-NEXT: v_add_f32_e32 v52, 0x40c00000, v52 ; GFX9-NEXT: v_bfe_u32 v53, v52, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v53, v53, v52 -; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27 +; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v28 ; GFX9-NEXT: v_add_u32_e32 v53, 0x7fff, v53 ; GFX9-NEXT: v_or_b32_e32 v54, 0x400000, v52 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v52, v52 -; GFX9-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 +; GFX9-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 ; GFX9-NEXT: v_cndmask_b32_e32 v52, v53, v54, vcc -; GFX9-NEXT: v_bfe_u32 v53, v27, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v53, v53, v27 +; GFX9-NEXT: v_bfe_u32 v53, v28, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v53, v53, v28 ; GFX9-NEXT: v_add_u32_e32 v53, 0x7fff, v53 -; GFX9-NEXT: v_or_b32_e32 v54, 0x400000, v27 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 -; GFX9-NEXT: v_cndmask_b32_e32 v27, v53, v54, vcc -; GFX9-NEXT: v_and_b32_e32 v53, 0xffff0000, v28 +; GFX9-NEXT: v_or_b32_e32 v54, 0x400000, v28 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 +; GFX9-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc +; GFX9-NEXT: v_and_b32_e32 v53, 0xffff0000, v29 ; GFX9-NEXT: v_add_f32_e32 v53, 0x40c00000, v53 ; GFX9-NEXT: v_bfe_u32 v54, v53, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v54, v54, v53 -; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v28 +; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29 ; GFX9-NEXT: v_add_u32_e32 v54, 0x7fff, v54 ; GFX9-NEXT: v_or_b32_e32 v55, 0x400000, v53 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v53, v53 -; GFX9-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 +; GFX9-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 ; GFX9-NEXT: v_cndmask_b32_e32 v53, v54, v55, vcc -; GFX9-NEXT: v_bfe_u32 v54, v28, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v54, v54, v28 +; GFX9-NEXT: v_bfe_u32 v54, v29, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v54, v54, v29 ; GFX9-NEXT: v_add_u32_e32 v54, 0x7fff, v54 -; GFX9-NEXT: v_or_b32_e32 v55, 0x400000, v28 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 -; GFX9-NEXT: v_cndmask_b32_e32 v28, v54, v55, vcc -; GFX9-NEXT: v_and_b32_e32 v54, 0xffff0000, v29 +; GFX9-NEXT: v_or_b32_e32 v55, 0x400000, v29 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 +; GFX9-NEXT: v_cndmask_b32_e32 v29, v54, v55, vcc +; GFX9-NEXT: v_and_b32_e32 v54, 0xffff0000, v30 ; GFX9-NEXT: v_add_f32_e32 v54, 0x40c00000, v54 ; GFX9-NEXT: v_bfe_u32 v55, v54, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v55, v55, v54 -; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29 +; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v30 ; GFX9-NEXT: v_add_u32_e32 v55, 0x7fff, v55 ; GFX9-NEXT: v_or_b32_e32 v40, 0x400000, v54 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v54, v54 -; GFX9-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 +; GFX9-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 ; GFX9-NEXT: v_cndmask_b32_e32 v54, v55, v40, vcc -; GFX9-NEXT: v_bfe_u32 v55, v29, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v55, v55, v29 +; GFX9-NEXT: v_bfe_u32 v55, v30, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v55, v55, v30 ; GFX9-NEXT: v_add_u32_e32 v55, 0x7fff, v55 -; GFX9-NEXT: v_or_b32_e32 v40, 0x400000, v29 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 -; GFX9-NEXT: v_cndmask_b32_e32 v29, v55, v40, vcc -; GFX9-NEXT: v_and_b32_e32 v55, 0xffff0000, v30 +; GFX9-NEXT: v_or_b32_e32 v40, 0x400000, v30 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 +; GFX9-NEXT: v_cndmask_b32_e32 v30, v55, v40, vcc +; GFX9-NEXT: v_and_b32_e32 v55, 0xffff0000, v31 ; GFX9-NEXT: v_add_f32_e32 v55, 0x40c00000, v55 ; GFX9-NEXT: v_bfe_u32 v40, v55, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v40, v40, v55 -; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v30 +; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31 ; GFX9-NEXT: v_add_u32_e32 v40, 0x7fff, v40 ; GFX9-NEXT: v_or_b32_e32 v41, 0x400000, v55 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v55, v55 -; GFX9-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 +; GFX9-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 ; GFX9-NEXT: v_cndmask_b32_e32 v55, v40, v41, vcc -; GFX9-NEXT: v_bfe_u32 v40, v30, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v40, v40, v30 +; GFX9-NEXT: v_bfe_u32 v40, v31, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v40, v40, v31 ; GFX9-NEXT: v_add_u32_e32 v40, 0x7fff, v40 -; GFX9-NEXT: v_or_b32_e32 v41, 0x400000, v30 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 -; GFX9-NEXT: v_cndmask_b32_e32 v30, v40, v41, vcc -; GFX9-NEXT: v_and_b32_e32 v40, 0xffff0000, v31 +; GFX9-NEXT: v_or_b32_e32 v41, 0x400000, v31 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v31, v31 +; GFX9-NEXT: v_cndmask_b32_e32 v31, v40, v41, vcc +; GFX9-NEXT: v_and_b32_e32 v40, 0xffff0000, v0 ; GFX9-NEXT: v_add_f32_e32 v40, 0x40c00000, v40 ; GFX9-NEXT: v_bfe_u32 v41, v40, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v41, v41, v40 -; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX9-NEXT: v_add_u32_e32 v41, 0x7fff, v41 ; GFX9-NEXT: v_or_b32_e32 v42, 0x400000, v40 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 -; GFX9-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 +; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 ; GFX9-NEXT: v_cndmask_b32_e32 v40, v41, v42, vcc -; GFX9-NEXT: v_bfe_u32 v41, v31, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v41, v41, v31 +; GFX9-NEXT: v_bfe_u32 v41, v0, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v41, v41, v0 ; GFX9-NEXT: v_add_u32_e32 v41, 0x7fff, v41 -; GFX9-NEXT: v_or_b32_e32 v42, 0x400000, v31 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v31, v31 -; GFX9-NEXT: v_cndmask_b32_e32 v31, v41, v42, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v40 -; GFX9-NEXT: v_and_b32_sdwa v31, v18, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v55 -; GFX9-NEXT: v_and_b32_sdwa v30, v18, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v54 -; GFX9-NEXT: v_and_b32_sdwa v29, v18, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v53 -; GFX9-NEXT: v_and_b32_sdwa v28, v18, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v52 -; GFX9-NEXT: v_and_b32_sdwa v27, v18, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v51 -; GFX9-NEXT: v_and_b32_sdwa v26, v18, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v50 -; GFX9-NEXT: v_and_b32_sdwa v25, v18, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v49 -; GFX9-NEXT: v_and_b32_sdwa v24, v18, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v48 -; GFX9-NEXT: v_and_b32_sdwa v23, v18, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v39 -; GFX9-NEXT: v_and_b32_sdwa v22, v18, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v38 -; GFX9-NEXT: v_and_b32_sdwa v21, v18, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v37 -; GFX9-NEXT: v_and_b32_sdwa v20, v18, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v36 -; GFX9-NEXT: v_and_b32_sdwa v19, v18, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v35 -; GFX9-NEXT: v_and_b32_sdwa v32, v18, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v34 -; GFX9-NEXT: v_and_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: v_and_b32_sdwa v16, v18, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v33 -; GFX9-NEXT: v_lshl_or_b32 v31, v40, 16, v31 -; GFX9-NEXT: v_lshl_or_b32 v30, v55, 16, v30 -; GFX9-NEXT: v_lshl_or_b32 v29, v54, 16, v29 -; GFX9-NEXT: v_lshl_or_b32 v28, v53, 16, v28 -; GFX9-NEXT: v_lshl_or_b32 v27, v52, 16, v27 -; GFX9-NEXT: v_lshl_or_b32 v26, v51, 16, v26 -; GFX9-NEXT: v_lshl_or_b32 v25, v50, 16, v25 -; GFX9-NEXT: v_lshl_or_b32 v24, v49, 16, v24 -; GFX9-NEXT: v_lshl_or_b32 v23, v48, 16, v23 -; GFX9-NEXT: v_lshl_or_b32 v22, v39, 16, v22 -; GFX9-NEXT: v_lshl_or_b32 v21, v38, 16, v21 -; GFX9-NEXT: v_lshl_or_b32 v20, v37, 16, v20 -; GFX9-NEXT: v_lshl_or_b32 v19, v36, 16, v19 -; GFX9-NEXT: v_lshl_or_b32 v32, v35, 16, v32 -; GFX9-NEXT: v_lshl_or_b32 v17, v34, 16, v17 -; GFX9-NEXT: v_lshl_or_b32 v16, v18, 16, v16 -; GFX9-NEXT: s_branch .LBB101_5 -; GFX9-NEXT: .LBB101_3: -; GFX9-NEXT: s_branch .LBB101_2 -; GFX9-NEXT: .LBB101_4: -; GFX9-NEXT: v_mov_b32_e32 v0, s16 -; GFX9-NEXT: v_mov_b32_e32 v1, s17 -; GFX9-NEXT: v_mov_b32_e32 v2, s18 -; GFX9-NEXT: v_mov_b32_e32 v3, s19 -; GFX9-NEXT: v_mov_b32_e32 v4, s20 -; GFX9-NEXT: v_mov_b32_e32 v5, s21 -; GFX9-NEXT: v_mov_b32_e32 v6, s22 -; GFX9-NEXT: v_mov_b32_e32 v7, s23 -; GFX9-NEXT: v_mov_b32_e32 v8, s24 -; GFX9-NEXT: v_mov_b32_e32 v9, s25 -; GFX9-NEXT: v_mov_b32_e32 v10, s26 -; GFX9-NEXT: v_mov_b32_e32 v11, s27 -; GFX9-NEXT: v_mov_b32_e32 v12, s28 -; GFX9-NEXT: v_mov_b32_e32 v13, s29 -; GFX9-NEXT: v_mov_b32_e32 v14, s30 -; GFX9-NEXT: v_mov_b32_e32 v15, s31 -; GFX9-NEXT: .LBB101_5: ; %end -; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; GFX9-NEXT: v_or_b32_e32 v42, 0x400000, v0 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; GFX9-NEXT: v_cndmask_b32_e32 v18, v41, v42, vcc +; GFX9-NEXT: v_and_b32_e32 v41, 0xffff0000, v1 +; GFX9-NEXT: v_add_f32_e32 v41, 0x40c00000, v41 +; GFX9-NEXT: v_bfe_u32 v42, v41, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v42, v42, v41 +; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX9-NEXT: v_add_u32_e32 v42, 0x7fff, v42 +; GFX9-NEXT: v_or_b32_e32 v43, 0x400000, v41 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v41, v41 +; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v41, v42, v43, vcc +; GFX9-NEXT: v_bfe_u32 v42, v1, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v42, v42, v1 +; GFX9-NEXT: v_add_u32_e32 v42, 0x7fff, v42 +; GFX9-NEXT: v_or_b32_e32 v43, 0x400000, v1 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v17, v42, v43, vcc +; GFX9-NEXT: v_and_b32_e32 v42, 0xffff0000, v2 +; GFX9-NEXT: v_add_f32_e32 v42, 0x40c00000, v42 +; GFX9-NEXT: v_bfe_u32 v43, v42, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v43, v43, v42 +; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX9-NEXT: v_add_u32_e32 v43, 0x7fff, v43 +; GFX9-NEXT: v_or_b32_e32 v44, 0x400000, v42 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v42, v42 +; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v42, v43, v44, vcc +; GFX9-NEXT: v_bfe_u32 v43, v2, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v43, v43, v2 +; GFX9-NEXT: v_add_u32_e32 v43, 0x7fff, v43 +; GFX9-NEXT: v_or_b32_e32 v44, 0x400000, v2 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v16, v43, v44, vcc +; GFX9-NEXT: v_and_b32_e32 v43, 0xffff0000, v3 +; GFX9-NEXT: v_add_f32_e32 v43, 0x40c00000, v43 +; GFX9-NEXT: v_bfe_u32 v44, v43, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v44, v44, v43 +; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GFX9-NEXT: v_add_u32_e32 v44, 0x7fff, v44 +; GFX9-NEXT: v_or_b32_e32 v45, 0x400000, v43 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v43, v43 +; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v43, v44, v45, vcc +; GFX9-NEXT: v_bfe_u32 v44, v3, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v44, v44, v3 +; GFX9-NEXT: v_add_u32_e32 v44, 0x7fff, v44 +; GFX9-NEXT: v_or_b32_e32 v45, 0x400000, v3 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v3, v44, v45, vcc +; GFX9-NEXT: v_and_b32_e32 v44, 0xffff0000, v4 +; GFX9-NEXT: v_add_f32_e32 v44, 0x40c00000, v44 +; GFX9-NEXT: v_bfe_u32 v45, v44, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v45, v45, v44 +; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX9-NEXT: v_add_u32_e32 v45, 0x7fff, v45 +; GFX9-NEXT: v_or_b32_e32 v46, 0x400000, v44 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v44, v44 +; GFX9-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 +; GFX9-NEXT: v_cndmask_b32_e32 v44, v45, v46, vcc +; GFX9-NEXT: v_bfe_u32 v45, v4, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v45, v45, v4 +; GFX9-NEXT: v_add_u32_e32 v45, 0x7fff, v45 +; GFX9-NEXT: v_or_b32_e32 v46, 0x400000, v4 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 +; GFX9-NEXT: v_cndmask_b32_e32 v4, v45, v46, vcc +; GFX9-NEXT: v_and_b32_e32 v45, 0xffff0000, v5 +; GFX9-NEXT: v_add_f32_e32 v45, 0x40c00000, v45 +; GFX9-NEXT: v_bfe_u32 v46, v45, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v46, v46, v45 +; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5 +; GFX9-NEXT: v_add_u32_e32 v46, 0x7fff, v46 +; GFX9-NEXT: v_or_b32_e32 v47, 0x400000, v45 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v45, v45 +; GFX9-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 +; GFX9-NEXT: v_cndmask_b32_e32 v45, v46, v47, vcc +; GFX9-NEXT: v_bfe_u32 v46, v5, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v46, v46, v5 +; GFX9-NEXT: v_add_u32_e32 v46, 0x7fff, v46 +; GFX9-NEXT: v_or_b32_e32 v47, 0x400000, v5 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 +; GFX9-NEXT: v_cndmask_b32_e32 v5, v46, v47, vcc +; GFX9-NEXT: v_and_b32_e32 v46, 0xffff0000, v6 +; GFX9-NEXT: v_add_f32_e32 v46, 0x40c00000, v46 +; GFX9-NEXT: v_bfe_u32 v47, v46, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v47, v47, v46 +; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GFX9-NEXT: v_add_u32_e32 v47, 0x7fff, v47 +; GFX9-NEXT: v_or_b32_e32 v56, 0x400000, v46 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v46, v46 +; GFX9-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 +; GFX9-NEXT: v_cndmask_b32_e32 v46, v47, v56, vcc +; GFX9-NEXT: v_bfe_u32 v47, v6, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v47, v47, v6 +; GFX9-NEXT: v_add_u32_e32 v47, 0x7fff, v47 +; GFX9-NEXT: v_or_b32_e32 v56, 0x400000, v6 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 +; GFX9-NEXT: v_cndmask_b32_e32 v6, v47, v56, vcc +; GFX9-NEXT: v_and_b32_e32 v47, 0xffff0000, v7 +; GFX9-NEXT: v_add_f32_e32 v47, 0x40c00000, v47 +; GFX9-NEXT: v_bfe_u32 v56, v47, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v56, v56, v47 +; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GFX9-NEXT: v_add_u32_e32 v56, 0x7fff, v56 +; GFX9-NEXT: v_or_b32_e32 v57, 0x400000, v47 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v47, v47 +; GFX9-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 +; GFX9-NEXT: v_cndmask_b32_e32 v47, v56, v57, vcc +; GFX9-NEXT: v_bfe_u32 v56, v7, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v56, v56, v7 +; GFX9-NEXT: v_add_u32_e32 v56, 0x7fff, v56 +; GFX9-NEXT: v_or_b32_e32 v57, 0x400000, v7 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 +; GFX9-NEXT: v_cndmask_b32_e32 v7, v56, v57, vcc +; GFX9-NEXT: v_and_b32_e32 v56, 0xffff0000, v8 +; GFX9-NEXT: v_add_f32_e32 v56, 0x40c00000, v56 +; GFX9-NEXT: v_bfe_u32 v57, v56, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v57, v57, v56 +; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GFX9-NEXT: v_add_u32_e32 v57, 0x7fff, v57 +; GFX9-NEXT: v_or_b32_e32 v58, 0x400000, v56 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v56, v56 +; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8 +; GFX9-NEXT: v_cndmask_b32_e32 v56, v57, v58, vcc +; GFX9-NEXT: v_bfe_u32 v57, v8, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v57, v57, v8 +; GFX9-NEXT: v_add_u32_e32 v57, 0x7fff, v57 +; GFX9-NEXT: v_or_b32_e32 v58, 0x400000, v8 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8 +; GFX9-NEXT: v_cndmask_b32_e32 v8, v57, v58, vcc +; GFX9-NEXT: v_and_b32_e32 v57, 0xffff0000, v9 +; GFX9-NEXT: v_add_f32_e32 v57, 0x40c00000, v57 +; GFX9-NEXT: v_bfe_u32 v58, v57, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v58, v58, v57 +; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX9-NEXT: v_add_u32_e32 v58, 0x7fff, v58 +; GFX9-NEXT: v_or_b32_e32 v59, 0x400000, v57 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v57, v57 +; GFX9-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 +; GFX9-NEXT: v_cndmask_b32_e32 v57, v58, v59, vcc +; GFX9-NEXT: v_bfe_u32 v58, v9, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v58, v58, v9 +; GFX9-NEXT: v_add_u32_e32 v58, 0x7fff, v58 +; GFX9-NEXT: v_or_b32_e32 v59, 0x400000, v9 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 +; GFX9-NEXT: v_cndmask_b32_e32 v9, v58, v59, vcc +; GFX9-NEXT: v_and_b32_e32 v58, 0xffff0000, v10 +; GFX9-NEXT: v_add_f32_e32 v58, 0x40c00000, v58 +; GFX9-NEXT: v_bfe_u32 v59, v58, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v59, v59, v58 +; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX9-NEXT: v_add_u32_e32 v59, 0x7fff, v59 +; GFX9-NEXT: v_or_b32_e32 v60, 0x400000, v58 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v58, v58 +; GFX9-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 +; GFX9-NEXT: v_cndmask_b32_e32 v58, v59, v60, vcc +; GFX9-NEXT: v_bfe_u32 v59, v10, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v59, v59, v10 +; GFX9-NEXT: v_add_u32_e32 v59, 0x7fff, v59 +; GFX9-NEXT: v_or_b32_e32 v60, 0x400000, v10 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 +; GFX9-NEXT: v_cndmask_b32_e32 v10, v59, v60, vcc +; GFX9-NEXT: v_and_b32_e32 v59, 0xffff0000, v11 +; GFX9-NEXT: v_add_f32_e32 v59, 0x40c00000, v59 +; GFX9-NEXT: v_bfe_u32 v60, v59, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v60, v60, v59 +; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX9-NEXT: v_add_u32_e32 v60, 0x7fff, v60 +; GFX9-NEXT: v_or_b32_e32 v61, 0x400000, v59 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v59, v59 +; GFX9-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; GFX9-NEXT: v_cndmask_b32_e32 v59, v60, v61, vcc +; GFX9-NEXT: v_bfe_u32 v60, v11, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v60, v60, v11 +; GFX9-NEXT: v_add_u32_e32 v60, 0x7fff, v60 +; GFX9-NEXT: v_or_b32_e32 v61, 0x400000, v11 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 +; GFX9-NEXT: v_cndmask_b32_e32 v11, v60, v61, vcc +; GFX9-NEXT: v_and_b32_e32 v60, 0xffff0000, v12 +; GFX9-NEXT: v_add_f32_e32 v60, 0x40c00000, v60 +; GFX9-NEXT: v_bfe_u32 v61, v60, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v61, v61, v60 +; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX9-NEXT: v_add_u32_e32 v61, 0x7fff, v61 +; GFX9-NEXT: v_or_b32_e32 v62, 0x400000, v60 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v60, v60 +; GFX9-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 +; GFX9-NEXT: v_cndmask_b32_e32 v60, v61, v62, vcc +; GFX9-NEXT: v_bfe_u32 v61, v12, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v61, v61, v12 +; GFX9-NEXT: v_add_u32_e32 v61, 0x7fff, v61 +; GFX9-NEXT: v_or_b32_e32 v62, 0x400000, v12 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 +; GFX9-NEXT: v_cndmask_b32_e32 v12, v61, v62, vcc +; GFX9-NEXT: v_and_b32_e32 v61, 0xffff0000, v13 +; GFX9-NEXT: v_add_f32_e32 v61, 0x40c00000, v61 +; GFX9-NEXT: v_bfe_u32 v62, v61, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v62, v62, v61 +; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13 +; GFX9-NEXT: v_add_u32_e32 v62, 0x7fff, v62 +; GFX9-NEXT: v_mov_b32_e32 v1, v63 +; GFX9-NEXT: v_or_b32_e32 v63, 0x400000, v61 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v61, v61 +; GFX9-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; GFX9-NEXT: v_cndmask_b32_e32 v61, v62, v63, vcc +; GFX9-NEXT: v_bfe_u32 v62, v13, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v62, v62, v13 +; GFX9-NEXT: v_add_u32_e32 v62, 0x7fff, v62 +; GFX9-NEXT: v_or_b32_e32 v63, 0x400000, v13 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 +; GFX9-NEXT: v_cndmask_b32_e32 v13, v62, v63, vcc +; GFX9-NEXT: v_and_b32_e32 v62, 0xffff0000, v14 +; GFX9-NEXT: v_add_f32_e32 v62, 0x40c00000, v62 +; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14 +; GFX9-NEXT: v_bfe_u32 v63, v62, 16, 1 +; GFX9-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 +; GFX9-NEXT: v_add_u32_e32 v63, v63, v62 +; GFX9-NEXT: v_or_b32_e32 v0, 0x400000, v62 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v62, v62 +; GFX9-NEXT: v_bfe_u32 v62, v14, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v63, 0x7fff, v63 +; GFX9-NEXT: v_add_u32_e32 v62, v62, v14 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v63, v0, vcc +; GFX9-NEXT: v_add_u32_e32 v62, 0x7fff, v62 +; GFX9-NEXT: v_or_b32_e32 v63, 0x400000, v14 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 +; GFX9-NEXT: v_cndmask_b32_e32 v14, v62, v63, vcc +; GFX9-NEXT: v_and_b32_e32 v62, 0xffff0000, v1 +; GFX9-NEXT: v_add_f32_e32 v62, 0x40c00000, v62 +; GFX9-NEXT: v_bfe_u32 v63, v62, 16, 1 +; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-NEXT: v_add_u32_e32 v63, v63, v62 +; GFX9-NEXT: v_or_b32_e32 v15, 0x400000, v62 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v62, v62 +; GFX9-NEXT: v_lshlrev_b32_e32 v62, 16, v1 +; GFX9-NEXT: v_add_u32_e32 v63, 0x7fff, v63 +; GFX9-NEXT: v_add_f32_e32 v62, 0x40c00000, v62 +; GFX9-NEXT: v_cndmask_b32_e32 v15, v63, v15, vcc +; GFX9-NEXT: v_bfe_u32 v63, v62, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v63, v63, v62 +; GFX9-NEXT: v_add_u32_e32 v63, 0x7fff, v63 +; GFX9-NEXT: v_or_b32_e32 v0, 0x400000, v62 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v62, v62 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v63, v0, vcc +; GFX9-NEXT: v_mov_b32_e32 v62, 0xffff +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GFX9-NEXT: v_and_b32_sdwa v0, v62, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v63, v15, 16, v0 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v2 +; GFX9-NEXT: v_and_b32_sdwa v1, v62, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v14, v0, 16, v1 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v61 +; GFX9-NEXT: v_and_b32_sdwa v1, v62, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v13, v0, 16, v1 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v60 +; GFX9-NEXT: v_and_b32_sdwa v1, v62, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v12, v0, 16, v1 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v59 +; GFX9-NEXT: v_and_b32_sdwa v1, v62, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v11, v0, 16, v1 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v58 +; GFX9-NEXT: v_and_b32_sdwa v1, v62, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v10, v0, 16, v1 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v57 +; GFX9-NEXT: v_and_b32_sdwa v1, v62, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v9, v0, 16, v1 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v56 +; GFX9-NEXT: v_and_b32_sdwa v1, v62, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v8, v0, 16, v1 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v47 +; GFX9-NEXT: v_and_b32_sdwa v1, v62, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v7, v0, 16, v1 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v46 +; GFX9-NEXT: v_and_b32_sdwa v1, v62, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v6, v0, 16, v1 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v45 +; GFX9-NEXT: v_and_b32_sdwa v1, v62, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v5, v0, 16, v1 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v44 +; GFX9-NEXT: v_and_b32_sdwa v1, v62, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v4, v0, 16, v1 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v43 +; GFX9-NEXT: v_and_b32_sdwa v1, v62, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v3, v0, 16, v1 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v42 +; GFX9-NEXT: v_and_b32_sdwa v1, v62, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v2, v0, 16, v1 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v41 +; GFX9-NEXT: v_and_b32_sdwa v1, v62, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v1, v0, 16, v1 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v40 +; GFX9-NEXT: v_and_b32_sdwa v15, v62, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v15 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v55 +; GFX9-NEXT: v_and_b32_sdwa v16, v62, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v31, v15, 16, v16 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v54 +; GFX9-NEXT: v_and_b32_sdwa v16, v62, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v30, v15, 16, v16 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v53 +; GFX9-NEXT: v_and_b32_sdwa v16, v62, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v29, v15, 16, v16 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v52 +; GFX9-NEXT: v_and_b32_sdwa v16, v62, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v28, v15, 16, v16 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v51 +; GFX9-NEXT: v_and_b32_sdwa v16, v62, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v27, v15, 16, v16 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v50 +; GFX9-NEXT: v_and_b32_sdwa v16, v62, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v26, v15, 16, v16 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v49 +; GFX9-NEXT: v_and_b32_sdwa v16, v62, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v25, v15, 16, v16 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v48 +; GFX9-NEXT: v_and_b32_sdwa v16, v62, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v24, v15, 16, v16 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v39 +; GFX9-NEXT: v_and_b32_sdwa v16, v62, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v23, v15, 16, v16 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v38 +; GFX9-NEXT: v_and_b32_sdwa v16, v62, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v22, v15, 16, v16 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v37 +; GFX9-NEXT: v_and_b32_sdwa v16, v62, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v21, v15, 16, v16 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v36 +; GFX9-NEXT: v_and_b32_sdwa v16, v62, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v20, v15, 16, v16 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v35 +; GFX9-NEXT: v_and_b32_sdwa v16, v62, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v19, v15, 16, v16 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v34 +; GFX9-NEXT: v_and_b32_sdwa v16, v62, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_lshl_or_b32 v32, v15, 16, v16 +; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-NEXT: v_and_b32_sdwa v16, v62, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GFX9-NEXT: v_lshl_or_b32 v17, v15, 16, v16 +; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_and_b32_sdwa v15, v62, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v16 +; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v15 +; GFX9-NEXT: .LBB101_3: ; %end +; GFX9-NEXT: v_mov_b32_e32 v15, v63 +; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload ; GFX9-NEXT: v_mov_b32_e32 v18, v32 -; GFX9-NEXT: v_readlane_b32 s31, v43, 1 -; GFX9-NEXT: v_readlane_b32 s30, v43, 0 -; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 -; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload -; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX9-NEXT: .LBB101_4: +; GFX9-NEXT: s_branch .LBB101_2 ; ; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v64f16_scalar: ; GFX11-TRUE16: ; %bb.0: @@ -228975,1105 +225369,1194 @@ define inreg <64 x bfloat> @bitcast_v64f16_to_v64bf16_scalar(<64 x half> inreg % ; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v37, v0 -; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:80 -; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 -; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:4 -; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:8 -; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:12 -; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:16 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:20 -; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:24 -; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:28 -; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:32 -; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:36 -; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:40 -; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:44 -; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:48 -; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:52 -; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 -; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:60 +; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80 +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 +; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:4 +; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:8 +; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:12 +; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:16 +; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:20 +; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:24 +; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:28 +; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:32 +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:36 +; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:40 +; SI-NEXT: s_waitcnt expcnt(6) +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:44 +; SI-NEXT: s_waitcnt expcnt(5) +; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:48 +; SI-NEXT: s_waitcnt expcnt(4) +; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:52 +; SI-NEXT: s_waitcnt expcnt(3) +; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:56 +; SI-NEXT: s_waitcnt expcnt(2) +; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:60 ; SI-NEXT: s_waitcnt expcnt(1) ; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:64 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:68 -; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:72 -; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:76 -; SI-NEXT: v_cvt_f16_f32_e32 v40, v1 -; SI-NEXT: v_cvt_f16_f32_e32 v1, v9 -; SI-NEXT: v_mov_b32_e32 v46, v28 -; SI-NEXT: v_cvt_f16_f32_e32 v43, v2 +; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:72 +; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:76 +; SI-NEXT: v_cvt_f16_f32_e32 v34, v1 +; SI-NEXT: v_mov_b32_e32 v37, v20 +; SI-NEXT: v_cvt_f16_f32_e32 v35, v2 ; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 ; SI-NEXT: v_cvt_f16_f32_e32 v4, v4 ; SI-NEXT: v_cvt_f16_f32_e32 v5, v5 ; SI-NEXT: v_cvt_f16_f32_e32 v6, v6 -; SI-NEXT: v_cvt_f16_f32_e32 v7, v7 +; SI-NEXT: v_cvt_f16_f32_e32 v36, v7 ; SI-NEXT: v_cvt_f16_f32_e32 v8, v8 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f16_f32_e32 v9, v9 ; SI-NEXT: v_cvt_f16_f32_e32 v10, v10 ; SI-NEXT: v_cvt_f16_f32_e32 v11, v11 ; SI-NEXT: v_cvt_f16_f32_e32 v12, v12 ; SI-NEXT: v_cvt_f16_f32_e32 v13, v13 ; SI-NEXT: v_cvt_f16_f32_e32 v14, v14 -; SI-NEXT: v_cvt_f16_f32_e32 v16, v16 -; SI-NEXT: v_cvt_f16_f32_e32 v18, v18 -; SI-NEXT: v_cvt_f16_f32_e32 v44, v24 -; SI-NEXT: v_cvt_f16_f32_e32 v45, v25 -; SI-NEXT: v_cvt_f16_f32_e32 v26, v26 -; SI-NEXT: v_cvt_f16_f32_e32 v28, v27 -; SI-NEXT: v_cvt_f16_f32_e32 v27, v46 -; SI-NEXT: v_cvt_f16_f32_e32 v46, v29 -; SI-NEXT: v_cvt_f16_f32_e32 v47, v30 -; SI-NEXT: v_cvt_f16_f32_e32 v24, s18 -; SI-NEXT: v_cvt_f16_f32_e32 v25, s19 -; SI-NEXT: v_cvt_f16_f32_e32 v29, s20 -; SI-NEXT: v_cvt_f16_f32_e32 v30, s21 +; SI-NEXT: v_cvt_f16_f32_e32 v20, v16 +; SI-NEXT: v_cvt_f16_f32_e32 v16, v17 +; SI-NEXT: v_cvt_f16_f32_e32 v17, v18 +; SI-NEXT: v_cvt_f16_f32_e32 v19, v19 +; SI-NEXT: v_cvt_f16_f32_e32 v21, v21 +; SI-NEXT: v_cvt_f16_f32_e32 v22, v22 +; SI-NEXT: v_cvt_f16_f32_e32 v23, v23 +; SI-NEXT: v_cvt_f16_f32_e32 v24, v24 +; SI-NEXT: v_cvt_f16_f32_e32 v54, v25 +; SI-NEXT: v_cvt_f16_f32_e32 v48, v26 +; SI-NEXT: v_cvt_f16_f32_e32 v50, v27 +; SI-NEXT: v_cvt_f16_f32_e32 v51, v28 +; SI-NEXT: v_cvt_f16_f32_e32 v55, v29 +; SI-NEXT: v_cvt_f16_f32_e32 v40, v30 +; SI-NEXT: v_cvt_f16_f32_e32 v7, s16 +; SI-NEXT: v_cvt_f16_f32_e32 v18, s17 +; SI-NEXT: v_cvt_f16_f32_e32 v27, s20 +; SI-NEXT: v_cvt_f16_f32_e32 v26, s21 +; SI-NEXT: v_cvt_f16_f32_e32 v25, s22 +; SI-NEXT: v_cvt_f16_f32_e32 v28, s23 +; SI-NEXT: v_cvt_f16_f32_e32 v38, s24 +; SI-NEXT: v_cvt_f16_f32_e32 v30, s27 ; SI-NEXT: s_waitcnt vmcnt(14) -; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 -; SI-NEXT: v_cvt_f16_f32_e32 v31, v15 -; SI-NEXT: v_cvt_f16_f32_e32 v15, v17 -; SI-NEXT: v_cvt_f16_f32_e32 v17, v19 -; SI-NEXT: v_cvt_f16_f32_e32 v19, v20 -; SI-NEXT: v_cvt_f16_f32_e32 v20, v21 -; SI-NEXT: v_cvt_f16_f32_e32 v21, v22 -; SI-NEXT: v_cvt_f16_f32_e32 v22, v23 -; SI-NEXT: v_cvt_f16_f32_e32 v32, v32 -; SI-NEXT: v_cvt_f16_f32_e32 v56, v33 -; SI-NEXT: v_cvt_f16_f32_e32 v34, v34 -; SI-NEXT: v_cvt_f16_f32_e32 v35, v35 -; SI-NEXT: v_cvt_f16_f32_e32 v57, v36 -; SI-NEXT: v_cvt_f16_f32_e32 v58, v0 -; SI-NEXT: v_cvt_f16_f32_e32 v38, v38 +; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v32 +; SI-NEXT: v_cvt_f16_f32_e32 v32, v15 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v49 +; SI-NEXT: v_cvt_f16_f32_e32 v15, v37 +; SI-NEXT: v_cvt_f16_f32_e32 v41, v39 +; SI-NEXT: v_cvt_f16_f32_e32 v2, v52 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f16_f32_e32 v29, v53 +; SI-NEXT: v_cvt_f16_f32_e32 v42, v42 +; SI-NEXT: v_cvt_f16_f32_e32 v43, v43 +; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: v_cvt_f16_f32_e32 v44, v44 ; SI-NEXT: s_waitcnt vmcnt(13) -; SI-NEXT: v_cvt_f16_f32_e32 v59, v39 +; SI-NEXT: v_cvt_f16_f32_e32 v45, v45 ; SI-NEXT: s_waitcnt vmcnt(12) -; SI-NEXT: v_cvt_f16_f32_e32 v60, v48 +; SI-NEXT: v_cvt_f16_f32_e32 v46, v46 ; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_cvt_f16_f32_e32 v61, v49 -; SI-NEXT: s_waitcnt vmcnt(10) expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v1, v52 +; SI-NEXT: v_cvt_f16_f32_e32 v47, v47 +; SI-NEXT: s_waitcnt vmcnt(10) +; SI-NEXT: v_cvt_f16_f32_e32 v56, v56 ; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_cvt_f16_f32_e32 v53, v53 +; SI-NEXT: v_cvt_f16_f32_e32 v57, v57 ; SI-NEXT: s_waitcnt vmcnt(8) -; SI-NEXT: v_cvt_f16_f32_e32 v2, v54 +; SI-NEXT: v_cvt_f16_f32_e32 v58, v58 ; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_cvt_f16_f32_e32 v54, v55 +; SI-NEXT: v_cvt_f16_f32_e32 v59, v59 ; SI-NEXT: s_waitcnt vmcnt(6) -; SI-NEXT: v_cvt_f16_f32_e32 v41, v41 +; SI-NEXT: v_cvt_f16_f32_e32 v60, v60 ; SI-NEXT: s_waitcnt vmcnt(5) -; SI-NEXT: v_cvt_f16_f32_e32 v42, v42 +; SI-NEXT: v_cvt_f16_f32_e32 v61, v61 ; SI-NEXT: s_waitcnt vmcnt(4) ; SI-NEXT: v_cvt_f16_f32_e32 v62, v62 ; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_cvt_f16_f32_e32 v63, v63 ; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_cvt_f16_f32_e32 v55, v50 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_cvt_f16_f32_e32 v9, v51 -; SI-NEXT: v_cvt_f16_f32_e32 v0, s16 -; SI-NEXT: v_cvt_f16_f32_e32 v23, s17 -; SI-NEXT: v_cvt_f16_f32_e32 v36, s22 -; SI-NEXT: v_cvt_f16_f32_e32 v39, s23 -; SI-NEXT: v_cvt_f16_f32_e32 v48, s24 -; SI-NEXT: v_cvt_f16_f32_e32 v49, s25 -; SI-NEXT: v_cvt_f16_f32_e32 v33, s26 -; SI-NEXT: v_cvt_f16_f32_e32 v50, s27 -; SI-NEXT: v_cvt_f16_f32_e32 v51, s28 -; SI-NEXT: v_cvt_f16_f32_e32 v52, s29 +; SI-NEXT: v_cvt_f16_f32_e32 v37, v31 +; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v1, v33 +; SI-NEXT: v_cvt_f16_f32_e32 v31, s18 +; SI-NEXT: v_cvt_f16_f32_e32 v33, s19 +; SI-NEXT: v_cvt_f16_f32_e32 v39, s25 +; SI-NEXT: v_cvt_f16_f32_e32 v49, s26 +; SI-NEXT: v_cvt_f16_f32_e32 v52, s28 +; SI-NEXT: v_cvt_f16_f32_e32 v53, s29 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec -; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB103_2 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v23 -; SI-NEXT: v_mov_b32_e32 v23, v6 -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v24 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v6 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v36 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v25 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v8 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v29 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v10 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v30 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v11 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v36 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v12 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v39 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v14 +; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v48 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v32 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v49 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v18 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v18, v20 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v33 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v20 +; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v50 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v16 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v51 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v17 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v52 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v19 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v40 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v15 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v43 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v22 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v4 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v23 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v23 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v24 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v54 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v31 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v48 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v33 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v50 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v27 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v51 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v26 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v55 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v25 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v40 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v8 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v5 ; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v28 -; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v46 -; SI-NEXT: s_mov_b64 s[4:5], 0 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17 -; SI-NEXT: v_mov_b32_e32 v51, v21 -; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21 -; SI-NEXT: v_mov_b32_e32 v36, v22 -; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v44 -; SI-NEXT: v_mov_b32_e32 v50, v26 -; SI-NEXT: v_mov_b32_e32 v33, v28 -; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v38 -; SI-NEXT: v_mov_b32_e32 v38, v7 -; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v59 -; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v60 -; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v61 -; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v1 -; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v53 -; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v2 -; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v54 -; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v41 -; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v42 -; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v62 -; SI-NEXT: s_waitcnt vmcnt(14) expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v6 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v10 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v41 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v11 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v38 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v12 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v2 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v13 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v39 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v14 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v29 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v31 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v49 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v16 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v42 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v18 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v30 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v19 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v44 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v20 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v52 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v26 -; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v27 -; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v47 -; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v15 -; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v22 -; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v45 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v32 -; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v56 -; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v34 -; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v35 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v45 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v57 -; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v58 -; SI-NEXT: v_mov_b32_e32 v58, v5 -; SI-NEXT: v_mov_b32_e32 v59, v11 -; SI-NEXT: v_mov_b32_e32 v60, v12 -; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v63 -; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v55 -; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v9 -; SI-NEXT: v_mov_b32_e32 v5, v23 -; SI-NEXT: v_mov_b32_e32 v7, v6 +; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v53 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v46 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v34 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v56 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v35 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v58 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v60 +; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v37 +; SI-NEXT: s_mov_b64 s[4:5], 0 +; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v5 +; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v9 +; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v13 +; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v21 +; SI-NEXT: v_mov_b32_e32 v38, v54 +; SI-NEXT: v_mov_b32_e32 v52, v51 +; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v20 +; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v43 +; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v47 +; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v57 +; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v59 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v61 +; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v62 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v63 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v1 +; SI-NEXT: v_mov_b32_e32 v11, v32 +; SI-NEXT: v_mov_b32_e32 v27, v26 +; SI-NEXT: v_mov_b32_e32 v25, v28 +; SI-NEXT: v_mov_b32_e32 v30, v48 +; SI-NEXT: v_mov_b32_e32 v32, v50 +; SI-NEXT: v_mov_b32_e32 v39, v49 +; SI-NEXT: v_mov_b32_e32 v48, v55 +; SI-NEXT: v_mov_b32_e32 v49, v40 +; SI-NEXT: v_mov_b32_e32 v50, v20 ; SI-NEXT: s_branch .LBB103_3 ; SI-NEXT: .LBB103_2: -; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: v_mov_b32_e32 v33, v28 -; SI-NEXT: v_mov_b32_e32 v50, v26 -; SI-NEXT: v_mov_b32_e32 v36, v22 -; SI-NEXT: v_mov_b32_e32 v51, v21 +; SI-NEXT: v_mov_b32_e32 v11, v32 +; SI-NEXT: v_mov_b32_e32 v32, v50 +; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: s_waitcnt expcnt(3) +; SI-NEXT: v_mov_b32_e32 v52, v51 +; SI-NEXT: v_mov_b32_e32 v38, v54 +; SI-NEXT: v_mov_b32_e32 v18, v20 ; SI-NEXT: s_mov_b64 s[4:5], -1 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: v_mov_b32_e32 v5, v6 +; SI-NEXT: ; kill: killed $vgpr3 ; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr7 +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_mov_b32_e32 v27, v26 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mov_b32_e32 v25, v28 +; SI-NEXT: v_mov_b32_e32 v30, v48 +; SI-NEXT: v_mov_b32_e32 v39, v49 +; SI-NEXT: v_mov_b32_e32 v48, v55 +; SI-NEXT: v_mov_b32_e32 v49, v40 ; SI-NEXT: ; implicit-def: $vgpr4 -; SI-NEXT: ; implicit-def: $vgpr16 -; SI-NEXT: ; implicit-def: $vgpr17 -; SI-NEXT: ; implicit-def: $vgpr21 -; SI-NEXT: ; implicit-def: $vgpr13 -; SI-NEXT: ; implicit-def: $vgpr40 -; SI-NEXT: ; implicit-def: $vgpr22 -; SI-NEXT: ; kill: killed $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr38 -; SI-NEXT: ; implicit-def: $vgpr59 -; SI-NEXT: ; implicit-def: $vgpr58 -; SI-NEXT: ; implicit-def: $vgpr60 +; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: ; implicit-def: $vgpr36 +; SI-NEXT: ; implicit-def: $vgpr8 +; SI-NEXT: ; implicit-def: $vgpr5 +; SI-NEXT: ; implicit-def: $vgpr9 ; SI-NEXT: ; implicit-def: $vgpr10 -; SI-NEXT: ; implicit-def: $vgpr18 -; SI-NEXT: ; implicit-def: $vgpr15 ; SI-NEXT: ; implicit-def: $vgpr31 -; SI-NEXT: ; implicit-def: $vgpr0 -; SI-NEXT: ; implicit-def: $vgpr14 -; SI-NEXT: ; implicit-def: $vgpr8 -; SI-NEXT: ; implicit-def: $vgpr24 -; SI-NEXT: ; implicit-def: $vgpr39 -; SI-NEXT: ; implicit-def: $vgpr48 -; SI-NEXT: ; implicit-def: $vgpr25 -; SI-NEXT: ; implicit-def: $vgpr49 -; SI-NEXT: ; implicit-def: $vgpr29 -; SI-NEXT: ; implicit-def: $vgpr52 -; SI-NEXT: ; implicit-def: $vgpr30 -; SI-NEXT: ; implicit-def: $vgpr28 -; SI-NEXT: ; implicit-def: $vgpr43 -; SI-NEXT: ; implicit-def: $vgpr12 -; SI-NEXT: ; implicit-def: $vgpr26 -; SI-NEXT: ; implicit-def: $vgpr11 +; SI-NEXT: ; implicit-def: $vgpr34 +; SI-NEXT: ; kill: killed $vgpr3 +; SI-NEXT: ; implicit-def: $vgpr6 +; SI-NEXT: ; implicit-def: $vgpr33 +; SI-NEXT: ; implicit-def: $vgpr3 +; SI-NEXT: ; kill: killed $vgpr7 +; SI-NEXT: ; implicit-def: $vgpr7 ; SI-NEXT: .LBB103_3: ; %Flow -; SI-NEXT: v_mov_b32_e32 v19, v20 -; SI-NEXT: v_mov_b32_e32 v6, v27 -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_mov_b32_e32 v61, v2 +; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v51, v2 ; SI-NEXT: s_andn2_b64 vcc, exec, s[4:5] ; SI-NEXT: s_cbranch_vccnz .LBB103_5 ; SI-NEXT: ; %bb.4: ; %cmp.true -; SI-NEXT: v_cvt_f32_f16_e32 v2, v9 -; SI-NEXT: v_cvt_f32_f16_e32 v8, v55 -; SI-NEXT: v_cvt_f32_f16_e32 v10, v63 -; SI-NEXT: v_cvt_f32_f16_e32 v14, v62 -; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v2 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v8 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f32_f16_e32 v31, v58 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v46 +; SI-NEXT: v_mov_b32_e32 v28, v38 +; SI-NEXT: v_cvt_f32_f16_e32 v36, v24 +; SI-NEXT: v_add_f32_e32 v58, 0x38000000, v31 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v47 +; SI-NEXT: v_add_f32_e32 v47, 0x38000000, v33 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v43 +; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v46, 0x38000000, v31 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v44 +; SI-NEXT: v_cvt_f32_f16_e32 v44, v42 +; SI-NEXT: v_add_f32_e32 v43, 0x38000000, v33 +; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: v_cvt_f32_f16_e32 v33, v50 +; SI-NEXT: v_add_f32_e32 v42, 0x38000000, v31 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v51 +; SI-NEXT: v_cvt_f32_f16_e32 v51, v32 +; SI-NEXT: v_cvt_f32_f16_e32 v50, v52 +; SI-NEXT: v_add_f32_e32 v55, 0x38000000, v33 +; SI-NEXT: v_add_f32_e32 v54, 0x38000000, v31 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v49 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v48 +; SI-NEXT: v_cvt_f32_f16_e32 v4, v15 +; SI-NEXT: v_cvt_f32_f16_e32 v3, v13 +; SI-NEXT: v_add_f32_e32 v38, 0x38000000, v31 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v30 +; SI-NEXT: v_add_f32_e32 v48, 0x38000000, v33 +; SI-NEXT: v_cvt_f32_f16_e32 v33, v28 +; SI-NEXT: v_cvt_f32_f16_e32 v5, v37 +; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v31 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v21 +; SI-NEXT: v_add_f32_e32 v35, 0x38000000, v33 +; SI-NEXT: v_add_f32_e32 v33, 0x38000000, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v4, v17 +; SI-NEXT: v_add_f32_e32 v32, 0x38000000, v31 +; SI-NEXT: v_cvt_f32_f16_e32 v31, v11 +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload +; SI-NEXT: v_cvt_f32_f16_e32 v37, v23 +; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v4 +; SI-NEXT: v_cvt_f32_f16_e32 v4, v14 +; SI-NEXT: v_cvt_f32_f16_e32 v14, v12 +; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v3 +; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload +; SI-NEXT: v_cvt_f32_f16_e32 v40, v41 +; SI-NEXT: v_cvt_f32_f16_e32 v2, v1 +; SI-NEXT: v_cvt_f32_f16_e32 v6, v63 +; SI-NEXT: v_cvt_f32_f16_e32 v7, v62 +; SI-NEXT: v_cvt_f32_f16_e32 v9, v60 +; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v2 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v10 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill +; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v5, v61 +; SI-NEXT: v_add_f32_e32 v62, 0x38000000, v6 +; SI-NEXT: v_cvt_f32_f16_e32 v10, v59 +; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v9 +; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v5, v57 +; SI-NEXT: v_cvt_f32_f16_e32 v9, v56 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v55, 0x38000000, v14 -; SI-NEXT: v_cvt_f32_f16_e32 v15, v61 -; SI-NEXT: v_cvt_f32_f16_e32 v8, v42 -; SI-NEXT: v_cvt_f32_f16_e32 v10, v41 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v34 -; SI-NEXT: v_add_f32_e32 v29, 0x38000000, v15 -; SI-NEXT: v_add_f32_e32 v54, 0x38000000, v8 -; SI-NEXT: v_cvt_f32_f16_e32 v8, v53 -; SI-NEXT: v_add_f32_e32 v30, 0x38000000, v10 -; SI-NEXT: v_cvt_f32_f16_e32 v10, v1 -; SI-NEXT: v_cvt_f32_f16_e32 v9, v51 -; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v8 -; SI-NEXT: v_cvt_f32_f16_e32 v4, v35 -; SI-NEXT: v_add_f32_e32 v39, 0x38000000, v10 -; SI-NEXT: s_waitcnt vmcnt(4) -; SI-NEXT: v_cvt_f32_f16_e32 v10, v27 -; SI-NEXT: v_cvt_f32_f16_e32 v11, v19 -; SI-NEXT: v_cvt_f32_f16_e32 v42, v7 -; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9 -; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v10 -; SI-NEXT: v_cvt_f32_f16_e32 v10, v32 -; SI-NEXT: v_add_f32_e32 v42, 0x38000000, v42 -; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11 -; SI-NEXT: v_cvt_f16_f32_e32 v9, v9 -; SI-NEXT: v_add_f32_e32 v27, 0x38000000, v10 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v14, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v52, 0x38000000, v14 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v14, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v48, 0x38000000, v14 -; SI-NEXT: v_cvt_f32_f16_e32 v14, v20 -; SI-NEXT: v_cvt_f32_f16_e32 v20, v33 -; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v14 -; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v4 -; SI-NEXT: v_cvt_f32_f16_e32 v4, v46 -; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20 -; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v4 -; SI-NEXT: v_cvt_f32_f16_e32 v4, v45 -; SI-NEXT: v_cvt_f32_f16_e32 v45, v5 -; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4 -; SI-NEXT: v_add_f32_e32 v45, 0x38000000, v45 -; SI-NEXT: v_cvt_f16_f32_e32 v4, v4 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v15, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v49, 0x38000000, v15 -; SI-NEXT: v_cvt_f32_f16_e32 v15, v57 -; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v15 -; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v47 -; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v3 -; SI-NEXT: v_cvt_f32_f16_e32 v3, v50 -; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v8, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v8 -; SI-NEXT: v_cvt_f32_f16_e32 v8, v56 -; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v8 -; SI-NEXT: v_cvt_f32_f16_e32 v8, v6 -; SI-NEXT: v_cvt_f32_f16_e32 v6, v44 -; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v8 -; SI-NEXT: v_cvt_f32_f16_e32 v8, v36 -; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6 -; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v21, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v28, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v28, 0x38000000, v28 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v31, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v31, 0x38000000, v31 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v32, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v32, 0x38000000, v32 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v33, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v33, 0x38000000, v33 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v34, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v10 +; SI-NEXT: v_add_f32_e32 v56, 0x38000000, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v5, v45 +; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v9 +; SI-NEXT: v_cvt_f32_f16_e32 v34, v19 +; SI-NEXT: v_cvt_f32_f16_e32 v17, v16 +; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v5, v29 +; SI-NEXT: s_waitcnt vmcnt(6) +; SI-NEXT: v_cvt_f32_f16_e32 v29, v26 +; SI-NEXT: v_cvt_f32_f16_e32 v26, v20 +; SI-NEXT: v_cvt_f32_f16_e32 v18, v18 +; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v17 +; SI-NEXT: v_cvt_f32_f16_e32 v27, v27 +; SI-NEXT: v_cvt_f32_f16_e32 v25, v25 +; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v18 +; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v31 +; SI-NEXT: v_add_f32_e32 v26, 0x38000000, v26 +; SI-NEXT: v_add_f32_e32 v27, 0x38000000, v27 +; SI-NEXT: v_add_f32_e32 v29, 0x38000000, v29 +; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25 +; SI-NEXT: v_cvt_f32_f16_e32 v39, v39 +; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14 +; SI-NEXT: v_cvt_f32_f16_e32 v22, v22 ; SI-NEXT: v_add_f32_e32 v34, 0x38000000, v34 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v36, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v39, 0x38000000, v39 +; SI-NEXT: v_add_f32_e32 v37, 0x38000000, v37 +; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22 ; SI-NEXT: v_add_f32_e32 v36, 0x38000000, v36 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v50, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v50, 0x38000000, v50 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v51, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload ; SI-NEXT: v_add_f32_e32 v51, 0x38000000, v51 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v40, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v50, 0x38000000, v50 ; SI-NEXT: v_add_f32_e32 v40, 0x38000000, v40 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v41, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v41, 0x38000000, v41 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v43, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v43, 0x38000000, v43 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v44, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5 ; SI-NEXT: v_add_f32_e32 v44, 0x38000000, v44 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v46, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v46, 0x38000000, v46 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v47, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v47, 0x38000000, v47 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v56, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v56, 0x38000000, v56 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v57, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v57, 0x38000000, v57 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v58, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v58, 0x38000000, v58 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v26, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v26, 0x38000000, v26 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v22, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v19, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7 +; SI-NEXT: v_cvt_f16_f32_e32 v6, v6 +; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload +; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; SI-NEXT: s_waitcnt vmcnt(5) +; SI-NEXT: v_cvt_f32_f16_e32 v53, v11 +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v53, 0x38000000, v53 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f32_f16_e32 v61, v19 +; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v61, 0x38000000, v61 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f32_f16_e32 v52, v11 +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v52, 0x38000000, v52 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f32_f16_e32 v63, v19 +; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v63, 0x38000000, v63 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f32_f16_e32 v49, v11 +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v49, 0x38000000, v49 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f32_f16_e32 v19, v19 ; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19 +; SI-NEXT: v_cvt_f16_f32_e32 v19, v19 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v35, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v35, 0x38000000, v35 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v13, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v12, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12 +; SI-NEXT: v_cvt_f32_f16_e32 v30, v11 +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v30, 0x38000000, v30 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v7, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7 -; SI-NEXT: v_cvt_f16_f32_e32 v7, v7 +; SI-NEXT: v_cvt_f32_f16_e32 v28, v11 +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v28, 0x38000000, v28 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v5, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v5 +; SI-NEXT: v_cvt_f32_f16_e32 v23, v11 +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23 +; SI-NEXT: v_cvt_f16_f32_e32 v23, v23 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v59, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload +; SI-NEXT: v_cvt_f32_f16_e32 v21, v11 +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload +; SI-NEXT: v_cvt_f32_f16_e32 v41, v13 +; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21 +; SI-NEXT: v_cvt_f16_f32_e32 v21, v21 +; SI-NEXT: v_add_f32_e32 v41, 0x38000000, v41 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f32_f16_e32 v20, v11 +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f32_f16_e32 v45, v13 +; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload +; SI-NEXT: v_cvt_f32_f16_e32 v31, v8 +; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v4 +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20 +; SI-NEXT: v_cvt_f16_f32_e32 v20, v20 +; SI-NEXT: v_add_f32_e32 v45, 0x38000000, v45 +; SI-NEXT: v_add_f32_e32 v31, 0x38000000, v31 +; SI-NEXT: v_cvt_f16_f32_e32 v8, v8 +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_cvt_f32_f16_e32 v11, v11 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_cvt_f32_f16_e32 v57, v13 +; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11 +; SI-NEXT: v_cvt_f16_f32_e32 v11, v11 +; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 +; SI-NEXT: v_add_f32_e32 v57, 0x38000000, v57 +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v20 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v21 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v23 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v11, v26 +; SI-NEXT: v_cvt_f16_f32_e32 v20, v27 +; SI-NEXT: v_cvt_f16_f32_e32 v21, v29 +; SI-NEXT: v_cvt_f16_f32_e32 v23, v25 +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v20 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v21 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v23 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v11, v28 +; SI-NEXT: v_cvt_f16_f32_e32 v20, v30 +; SI-NEXT: v_cvt_f16_f32_e32 v21, v39 +; SI-NEXT: v_cvt_f16_f32_e32 v23, v49 +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v20 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v21 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v23 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v11, v52 +; SI-NEXT: v_cvt_f16_f32_e32 v20, v53 +; SI-NEXT: v_cvt_f16_f32_e32 v21, v63 +; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3 +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v20 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f16_f32_e32 v3, v3 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v19 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v21 +; SI-NEXT: v_cvt_f16_f32_e32 v21, v57 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v3, v31 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_cvt_f16_f32_e32 v11, v61 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt vmcnt(14) +; SI-NEXT: v_cvt_f32_f16_e32 v59, v13 +; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload +; SI-NEXT: v_cvt_f32_f16_e32 v4, v4 ; SI-NEXT: v_add_f32_e32 v59, 0x38000000, v59 -; SI-NEXT: v_cvt_f16_f32_e32 v59, v59 +; SI-NEXT: v_cvt_f16_f32_e32 v20, v59 +; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4 +; SI-NEXT: v_cvt_f16_f32_e32 v4, v4 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v60, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload +; SI-NEXT: v_cvt_f32_f16_e32 v60, v13 +; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v20 ; SI-NEXT: v_add_f32_e32 v60, 0x38000000, v60 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v61, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v61, 0x38000000, v61 -; SI-NEXT: v_cvt_f16_f32_e32 v61, v61 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v62, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v62, 0x38000000, v62 -; SI-NEXT: v_cvt_f16_f32_e32 v62, v62 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v63, v0 -; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload -; SI-NEXT: v_add_f32_e32 v63, 0x38000000, v63 -; SI-NEXT: v_cvt_f16_f32_e32 v63, v63 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f32_f16_e32 v0, v0 -; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0 -; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f16_f32_e32 v19, v60 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v63 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v19 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v62 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v21 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v61 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f16_f32_e32 v11, v45 +; SI-NEXT: v_cvt_f16_f32_e32 v19, v41 +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v0, v60 -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v19 +; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v4 +; SI-NEXT: v_cvt_f16_f32_e32 v4, v14 +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v59 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f16_f32_e32 v11, v12 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v8 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f16_f32_e32 v3, v18 +; SI-NEXT: v_cvt_f16_f32_e32 v4, v17 +; SI-NEXT: v_cvt_f16_f32_e32 v8, v16 +; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v11 +; SI-NEXT: v_cvt_f16_f32_e32 v11, v15 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v0, v12 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v13 -; SI-NEXT: v_cvt_f16_f32_e32 v7, v35 -; SI-NEXT: v_cvt_f16_f32_e32 v12, v19 -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v8 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v11 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v12 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f16_f32_e32 v3, v34 +; SI-NEXT: v_cvt_f16_f32_e32 v4, v33 +; SI-NEXT: v_cvt_f16_f32_e32 v11, v22 +; SI-NEXT: v_cvt_f16_f32_e32 v8, v32 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v0, v22 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v26 -; SI-NEXT: v_cvt_f16_f32_e32 v7, v58 -; SI-NEXT: v_cvt_f16_f32_e32 v12, v57 -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v11 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f16_f32_e32 v3, v37 +; SI-NEXT: v_cvt_f16_f32_e32 v4, v36 +; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v8 +; SI-NEXT: v_cvt_f16_f32_e32 v8, v35 +; SI-NEXT: v_cvt_f16_f32_e32 v11, v24 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v12 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v0, v56 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v47 -; SI-NEXT: v_cvt_f16_f32_e32 v12, v45 -; SI-NEXT: v_cvt_f16_f32_e32 v7, v46 -; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v0 -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v8 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v12 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v11 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v0, v44 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v43 -; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v7 -; SI-NEXT: v_cvt_f16_f32_e32 v7, v42 -; SI-NEXT: v_cvt_f16_f32_e32 v12, v41 -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f16_f32_e32 v3, v51 +; SI-NEXT: v_cvt_f16_f32_e32 v4, v50 +; SI-NEXT: v_cvt_f16_f32_e32 v8, v48 +; SI-NEXT: v_cvt_f16_f32_e32 v11, v38 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v8 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v12 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v11 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v0, v40 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v51 -; SI-NEXT: v_cvt_f16_f32_e32 v7, v50 -; SI-NEXT: v_cvt_f16_f32_e32 v12, v36 -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f16_f32_e32 v3, v40 +; SI-NEXT: v_cvt_f16_f32_e32 v8, v54 +; SI-NEXT: v_cvt_f16_f32_e32 v11, v5 +; SI-NEXT: v_cvt_f16_f32_e32 v4, v55 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v8 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v11 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v12 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f16_f32_e32 v3, v44 +; SI-NEXT: v_cvt_f16_f32_e32 v8, v42 +; SI-NEXT: v_cvt_f16_f32_e32 v11, v9 +; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v4 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v0, v34 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v33 -; SI-NEXT: v_cvt_f16_f32_e32 v12, v31 -; SI-NEXT: v_cvt_f16_f32_e32 v7, v32 -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v8 +; SI-NEXT: v_cvt_f16_f32_e32 v4, v43 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v11 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v12 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f16_f32_e32 v3, v47 +; SI-NEXT: v_cvt_f16_f32_e32 v8, v10 +; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v4 +; SI-NEXT: v_cvt_f16_f32_e32 v4, v46 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v0, v28 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v21 -; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v7 -; SI-NEXT: v_cvt_f16_f32_e32 v7, v11 -; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v0 -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v5 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v8 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v7 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; SI-NEXT: v_cvt_f16_f32_e32 v3, v58 +; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v4 +; SI-NEXT: v_cvt_f16_f32_e32 v4, v1 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v2 +; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v4 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v0, v8 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v6 -; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v4, v16 -; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v0 -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v3 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_cvt_f16_f32_e32 v11, v56 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v0, v20 -; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v5 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v10 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v17 -; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v0 -; SI-NEXT: v_cvt_f16_f32_e32 v0, v27 -; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v4 -; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v3 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v18 -; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v0 -; SI-NEXT: v_cvt_f16_f32_e32 v0, v1 -; SI-NEXT: v_cvt_f16_f32_e32 v1, v2 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload -; SI-NEXT: v_cvt_f16_f32_e32 v4, v15 -; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v3 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v24 -; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v5 -; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v4, v23 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v14 -; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v3 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v48 -; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v4, v39 -; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v5 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v25 -; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v3 -; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v4 -; SI-NEXT: v_cvt_f16_f32_e32 v3, v52 -; SI-NEXT: v_cvt_f16_f32_e32 v4, v30 -; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v1 -; SI-NEXT: v_cvt_f16_f32_e32 v1, v49 -; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v3 -; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v4 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v1 -; SI-NEXT: v_cvt_f16_f32_e32 v1, v29 -; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v5 -; SI-NEXT: v_cvt_f16_f32_e32 v5, v54 -; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v9 -; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v1 -; SI-NEXT: v_cvt_f16_f32_e32 v1, v55 -; SI-NEXT: v_mov_b32_e32 v17, v11 -; SI-NEXT: v_mov_b32_e32 v16, v26 -; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v5 -; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v1 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_cvt_f16_f32_e32 v3, v2 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload -; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v3 -; SI-NEXT: v_mov_b32_e32 v3, v19 +; SI-NEXT: v_cvt_f16_f32_e32 v1, v7 +; SI-NEXT: v_cvt_f16_f32_e32 v3, v62 +; SI-NEXT: v_mov_b32_e32 v36, v12 +; SI-NEXT: v_mov_b32_e32 v35, v19 +; SI-NEXT: v_mov_b32_e32 v8, v14 +; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v11 +; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v1 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: s_waitcnt vmcnt(2) +; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_cvt_f16_f32_e32 v4, v4 -; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v4 -; SI-NEXT: v_mov_b32_e32 v4, v22 -; SI-NEXT: v_mov_b32_e32 v22, v6 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v2 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2 +; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v4 +; SI-NEXT: v_mov_b32_e32 v4, v13 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill ; SI-NEXT: .LBB103_5: ; %end -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0 -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: buffer_store_dword v1, v37, s[0:3], 0 offen +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v37 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v37 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v37 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v37 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v37 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v37 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v37 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v3 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v37 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v4 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v37 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v4 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v37 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v37 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v35 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v37 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v37 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v36 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v37 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v16 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v37 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v17 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 64, v37 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 64, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v21 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v37 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v40 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v13 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 0x48, v37 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x48, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v22 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v37 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v59 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v38 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 0x50, v37 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x50, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v60 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v58 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v37 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v18 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v10 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 0x58, v37 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x58, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v31 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e32 v2, 1.0, v15 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 -; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v37 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v14 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16 -; SI-NEXT: v_add_i32_e32 v1, vcc, 0x60, v37 -; SI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v9 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x60, v0 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v24 -; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8 -; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16 -; SI-NEXT: v_add_i32_e32 v1, vcc, 0x64, v37 -; SI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x64, v0 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v48 -; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v39 -; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16 -; SI-NEXT: v_add_i32_e32 v1, vcc, 0x68, v37 -; SI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v10 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x68, v0 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v49 -; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v25 -; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16 -; SI-NEXT: v_add_i32_e32 v1, vcc, 0x6c, v37 -; SI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v31 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v52 -; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v29 -; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16 -; SI-NEXT: v_add_i32_e32 v1, vcc, 0x70, v37 -; SI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v34 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x70, v0 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v28 -; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v30 -; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16 -; SI-NEXT: v_add_i32_e32 v1, vcc, 0x74, v37 -; SI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v6 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v12 -; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v43 -; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16 -; SI-NEXT: v_add_i32_e32 v1, vcc, 0x78, v37 -; SI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v33 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0 +; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v0, 1.0, v11 -; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v26 -; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16 -; SI-NEXT: v_add_i32_e32 v1, vcc, 0x7c, v37 -; SI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v7 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload +; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload ; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload @@ -233838,1081 +230321,1237 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a ; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:12 ; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:16 ; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:20 -; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:24 -; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:28 +; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:24 +; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:28 ; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:32 ; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:36 -; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:40 -; SI-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:44 -; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:48 -; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:52 -; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 -; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:60 -; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:64 -; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:68 +; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:40 +; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:44 +; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:48 +; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:52 +; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:56 +; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:60 +; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:64 ; SI-NEXT: s_waitcnt expcnt(6) -; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:72 -; SI-NEXT: s_waitcnt expcnt(5) -; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:76 -; SI-NEXT: v_mul_f32_e32 v38, 1.0, v1 -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v4 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:68 +; SI-NEXT: s_waitcnt expcnt(4) +; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:72 +; SI-NEXT: s_waitcnt expcnt(3) +; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:76 +; SI-NEXT: v_mul_f32_e32 v52, 1.0, v2 +; SI-NEXT: v_mul_f32_e32 v2, 1.0, v13 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v5 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v2, 1.0, v17 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v8 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v2, 1.0, v21 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v12 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v2, 1.0, v25 +; SI-NEXT: v_mov_b32_e32 v50, v27 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v16 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v2, 1.0, v29 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v20 -; SI-NEXT: v_mul_f32_e32 v59, 1.0, v2 -; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3 -; SI-NEXT: v_mul_f32_e32 v4, 1.0, v6 -; SI-NEXT: v_mul_f32_e32 v50, 1.0, v7 -; SI-NEXT: v_mul_f32_e32 v8, 1.0, v9 -; SI-NEXT: v_mul_f32_e32 v6, 1.0, v10 -; SI-NEXT: v_mul_f32_e32 v45, 1.0, v11 -; SI-NEXT: v_mul_f32_e32 v12, 1.0, v13 -; SI-NEXT: v_mul_f32_e32 v10, 1.0, v14 -; SI-NEXT: v_mul_f32_e32 v15, 1.0, v15 -; SI-NEXT: v_mul_f32_e32 v14, 1.0, v18 +; SI-NEXT: v_mul_f32_e32 v1, 1.0, v3 +; SI-NEXT: v_mul_f32_e32 v54, 1.0, v4 +; SI-NEXT: v_mul_f32_e32 v58, 1.0, v5 +; SI-NEXT: v_mul_f32_e32 v3, 1.0, v6 +; SI-NEXT: v_mul_f32_e32 v48, 1.0, v7 +; SI-NEXT: v_mul_f32_e32 v40, 1.0, v8 +; SI-NEXT: v_mul_f32_e32 v61, 1.0, v9 +; SI-NEXT: v_mul_f32_e32 v9, 1.0, v10 +; SI-NEXT: v_mul_f32_e32 v5, 1.0, v11 +; SI-NEXT: v_mul_f32_e32 v42, 1.0, v12 +; SI-NEXT: v_mul_f32_e32 v46, 1.0, v14 +; SI-NEXT: v_mul_f32_e32 v27, 1.0, v15 +; SI-NEXT: v_mul_f32_e32 v11, 1.0, v16 +; SI-NEXT: v_mul_f32_e32 v63, 1.0, v18 ; SI-NEXT: v_mul_f32_e32 v13, 1.0, v19 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill -; SI-NEXT: v_mul_f32_e32 v18, 1.0, v21 -; SI-NEXT: v_mul_f32_e32 v16, 1.0, v22 -; SI-NEXT: v_mul_f32_e32 v19, 1.0, v23 -; SI-NEXT: v_mul_f32_e32 v23, 1.0, v25 -; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27 -; SI-NEXT: v_mul_f32_e32 v63, 1.0, v28 -; SI-NEXT: v_mul_f32_e32 v7, 1.0, v29 -; SI-NEXT: v_mul_f32_e32 v11, 1.0, v30 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s16 -; SI-NEXT: v_mul_f32_e64 v30, 1.0, s17 -; SI-NEXT: v_mul_f32_e64 v22, 1.0, s18 -; SI-NEXT: v_mul_f32_e64 v20, 1.0, s19 -; SI-NEXT: v_mul_f32_e64 v29, 1.0, s21 -; SI-NEXT: v_mul_f32_e64 v28, 1.0, s22 -; SI-NEXT: v_mul_f32_e64 v9, 1.0, s27 -; SI-NEXT: v_mul_f32_e64 v21, 1.0, s28 +; SI-NEXT: v_mul_f32_e32 v19, 1.0, v20 +; SI-NEXT: v_mul_f32_e32 v56, 1.0, v22 +; SI-NEXT: v_mul_f32_e32 v21, 1.0, v23 +; SI-NEXT: v_mul_f32_e32 v17, 1.0, v24 +; SI-NEXT: v_mul_f32_e32 v23, 1.0, v26 +; SI-NEXT: v_mul_f32_e32 v22, 1.0, v50 +; SI-NEXT: v_mul_f32_e32 v24, 1.0, v28 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v29, 1.0, v30 +; SI-NEXT: v_mul_f32_e64 v28, 1.0, s24 +; SI-NEXT: v_mul_f32_e64 v30, 1.0, s25 +; SI-NEXT: v_mul_f32_e64 v50, 1.0, s27 +; SI-NEXT: v_mul_f32_e64 v7, 1.0, s28 +; SI-NEXT: v_mul_f32_e64 v26, 1.0, s29 ; SI-NEXT: s_waitcnt vmcnt(14) ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31 -; SI-NEXT: v_mul_f32_e32 v31, 1.0, v17 -; SI-NEXT: v_mul_f32_e32 v17, 1.0, v24 -; SI-NEXT: v_mul_f32_e32 v24, 1.0, v26 -; SI-NEXT: v_mul_f32_e32 v62, 1.0, v32 -; SI-NEXT: v_mul_f32_e32 v61, 1.0, v33 +; SI-NEXT: v_mul_f32_e32 v18, 1.0, v32 +; SI-NEXT: v_mul_f32_e32 v20, 1.0, v33 ; SI-NEXT: s_and_b64 s[4:5], vcc, exec -; SI-NEXT: v_mul_f32_e32 v53, 1.0, v34 -; SI-NEXT: v_mul_f32_e32 v35, 1.0, v35 -; SI-NEXT: v_mul_f32_e32 v25, 1.0, v36 -; SI-NEXT: v_mul_f32_e32 v60, 1.0, v37 -; SI-NEXT: v_mul_f32_e32 v37, 1.0, v39 -; SI-NEXT: v_mul_f32_e32 v36, 1.0, v48 -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e32 v1, 1.0, v49 -; SI-NEXT: v_mul_f32_e32 v56, 1.0, v51 -; SI-NEXT: v_mul_f32_e32 v5, 1.0, v52 -; SI-NEXT: v_mul_f32_e32 v39, 1.0, v54 -; SI-NEXT: s_waitcnt vmcnt(13) +; SI-NEXT: v_mul_f32_e32 v32, 1.0, v34 +; SI-NEXT: v_mul_f32_e32 v25, 1.0, v35 +; SI-NEXT: v_mul_f32_e32 v14, 1.0, v36 +; SI-NEXT: v_mul_f32_e32 v16, 1.0, v37 +; SI-NEXT: v_mul_f32_e32 v37, 1.0, v38 +; SI-NEXT: v_mul_f32_e32 v39, 1.0, v39 +; SI-NEXT: v_mul_f32_e32 v10, 1.0, v49 +; SI-NEXT: v_mul_f32_e32 v12, 1.0, v51 +; SI-NEXT: v_mul_f32_e32 v15, 1.0, v53 ; SI-NEXT: v_mul_f32_e32 v51, 1.0, v55 +; SI-NEXT: s_waitcnt vmcnt(13) +; SI-NEXT: v_mul_f32_e32 v6, 1.0, v41 ; SI-NEXT: s_waitcnt vmcnt(12) -; SI-NEXT: v_mul_f32_e32 v55, 1.0, v40 +; SI-NEXT: v_mul_f32_e32 v8, 1.0, v43 ; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_mul_f32_e32 v42, 1.0, v41 +; SI-NEXT: v_mul_f32_e32 v55, 1.0, v44 ; SI-NEXT: s_waitcnt vmcnt(10) -; SI-NEXT: v_mul_f32_e32 v48, 1.0, v43 -; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_mul_f32_e32 v49, 1.0, v44 +; SI-NEXT: v_mul_f32_e32 v44, 1.0, v45 +; SI-NEXT: s_waitcnt vmcnt(9) expcnt(0) +; SI-NEXT: v_mul_f32_e32 v2, 1.0, v47 ; SI-NEXT: s_waitcnt vmcnt(8) -; SI-NEXT: v_mul_f32_e32 v47, 1.0, v46 +; SI-NEXT: v_mul_f32_e32 v4, 1.0, v57 ; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_mul_f32_e32 v43, 1.0, v57 +; SI-NEXT: v_mul_f32_e32 v45, 1.0, v59 ; SI-NEXT: s_waitcnt vmcnt(6) -; SI-NEXT: v_mul_f32_e32 v58, 1.0, v58 -; SI-NEXT: v_mul_f32_e64 v54, 1.0, s20 -; SI-NEXT: v_mul_f32_e64 v26, 1.0, s23 -; SI-NEXT: v_mul_f32_e64 v52, 1.0, s24 -; SI-NEXT: v_mul_f32_e64 v34, 1.0, s25 -; SI-NEXT: v_mul_f32_e64 v33, 1.0, s26 -; SI-NEXT: v_mul_f32_e64 v32, 1.0, s29 -; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill +; SI-NEXT: v_mul_f32_e32 v59, 1.0, v60 +; SI-NEXT: v_mul_f32_e64 v34, 1.0, s16 +; SI-NEXT: v_mul_f32_e64 v36, 1.0, s17 +; SI-NEXT: v_mul_f32_e64 v53, 1.0, s18 +; SI-NEXT: v_mul_f32_e64 v38, 1.0, s19 +; SI-NEXT: v_mul_f32_e64 v31, 1.0, s20 +; SI-NEXT: v_mul_f32_e64 v33, 1.0, s21 +; SI-NEXT: v_mul_f32_e64 v60, 1.0, s22 +; SI-NEXT: v_mul_f32_e64 v49, 1.0, s23 +; SI-NEXT: v_mul_f32_e64 v35, 1.0, s26 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill ; SI-NEXT: s_cbranch_scc0 .LBB105_2 ; SI-NEXT: ; %bb.1: ; %cmp.false -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v20 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v54 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v26 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v52 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v21 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v3 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v50 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v45 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v15 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v14 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v13 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v16 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v19 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v24 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v27 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v11 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v62 +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v54 +; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28 +; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v34 +; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v38 +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31 +; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7 +; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(4) +; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v30 +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v26 +; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v60 +; SI-NEXT: v_mov_b32_e32 v28, v3 +; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v3 +; SI-NEXT: v_mov_b32_e32 v3, v9 +; SI-NEXT: s_mov_b64 s[4:5], 0 +; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v36 +; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v50 +; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v52 +; SI-NEXT: v_mov_b32_e32 v50, v48 +; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v3 +; SI-NEXT: v_mov_b32_e32 v38, v13 +; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v23 +; SI-NEXT: v_mov_b32_e32 v41, v44 +; SI-NEXT: v_mov_b32_e32 v52, v63 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v48 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v33 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v49 +; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(3) +; SI-NEXT: v_mov_b32_e32 v7, v40 +; SI-NEXT: v_mov_b32_e32 v48, v27 +; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v12 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v35 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v25 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v36 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v53 +; SI-NEXT: v_mov_b32_e32 v53, v58 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v39 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v51 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v48 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v49 -; SI-NEXT: v_mov_b32_e32 v25, v1 +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v40 +; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v46 +; SI-NEXT: v_mov_b32_e32 v46, v9 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v5 +; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v51 +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v35 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v58 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v30 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v57, v13 -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v34 -; SI-NEXT: v_mov_b32_e32 v40, v3 -; SI-NEXT: v_mov_b32_e32 v54, v50 -; SI-NEXT: v_mov_b32_e32 v46, v19 -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload -; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v9 -; SI-NEXT: v_mov_b32_e32 v44, v15 -; SI-NEXT: v_mov_b32_e32 v9, v11 -; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload -; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v6 -; SI-NEXT: s_mov_b64 s[4:5], 0 -; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v59 -; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v10 -; SI-NEXT: v_mov_b32_e32 v41, v27 -; SI-NEXT: v_mov_b32_e32 v52, v62 -; SI-NEXT: v_mov_b32_e32 v21, v58 -; SI-NEXT: v_mov_b32_e32 v58, v20 -; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v22 -; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v29 -; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v28 -; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v33 -; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v32 -; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v38 -; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v8 -; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v12 -; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v31 -; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v23 -; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v7 -; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v53 -; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v60 +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v42 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v27 +; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v8 ; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v37 -; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v56 -; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v5 -; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v55 -; SI-NEXT: v_mov_b32_e32 v55, v4 -; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v42 -; SI-NEXT: v_mov_b32_e32 v56, v47 -; SI-NEXT: v_mov_b32_e32 v53, v5 -; SI-NEXT: v_mov_b32_e32 v42, v43 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(7) expcnt(1) +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v11 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v63 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v13 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(6) expcnt(1) +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) ; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v19 -; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v3 -; SI-NEXT: s_waitcnt vmcnt(5) -; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v11 -; SI-NEXT: s_waitcnt vmcnt(4) -; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v15 -; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v50 -; SI-NEXT: v_mov_b32_e32 v5, v19 -; SI-NEXT: v_mov_b32_e32 v7, v15 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v56 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v21 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) ; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v17 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v63 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v22 +; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v61 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v61 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v24 +; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v58 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v47 -; SI-NEXT: v_mov_b32_e32 v47, v3 -; SI-NEXT: v_mov_b32_e32 v3, v17 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v29 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v43 -; SI-NEXT: v_mov_b32_e32 v1, v13 +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v18 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v20 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v25 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v14 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v39 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v10 +; SI-NEXT: v_mov_b32_e32 v39, v35 +; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v32 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v6 +; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v44 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v4 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v15 +; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v55 +; SI-NEXT: v_mov_b32_e32 v5, v23 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v59 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v45 +; SI-NEXT: s_waitcnt vmcnt(9) +; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v35 +; SI-NEXT: s_waitcnt vmcnt(8) +; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v42 +; SI-NEXT: s_waitcnt vmcnt(7) +; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v60 +; SI-NEXT: s_waitcnt vmcnt(6) +; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v21 +; SI-NEXT: s_waitcnt vmcnt(5) +; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v11 +; SI-NEXT: v_mov_b32_e32 v9, v11 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v1 ; SI-NEXT: s_branch .LBB105_3 ; SI-NEXT: .LBB105_2: -; SI-NEXT: s_waitcnt expcnt(5) -; SI-NEXT: v_mov_b32_e32 v25, v1 -; SI-NEXT: ; implicit-def: $vgpr2 ; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: s_waitcnt expcnt(3) -; SI-NEXT: v_mov_b32_e32 v21, v58 -; SI-NEXT: s_waitcnt expcnt(2) -; SI-NEXT: v_mov_b32_e32 v52, v62 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; SI-NEXT: ; implicit-def: $vgpr39 +; SI-NEXT: v_mov_b32_e32 v41, v44 +; SI-NEXT: v_mov_b32_e32 v7, v40 +; SI-NEXT: s_waitcnt expcnt(6) +; SI-NEXT: v_mov_b32_e32 v50, v48 +; SI-NEXT: v_mov_b32_e32 v48, v27 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr43 ; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr62 -; SI-NEXT: ; implicit-def: $vgpr35 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill ; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr31 ; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; SI-NEXT: ; implicit-def: $vgpr28 -; SI-NEXT: ; implicit-def: $vgpr58 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr51 -; SI-NEXT: ; implicit-def: $vgpr26 -; SI-NEXT: ; implicit-def: $vgpr59 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill ; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; SI-NEXT: ; implicit-def: $vgpr24 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr34 +; SI-NEXT: ; implicit-def: $vgpr62 ; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill ; SI-NEXT: ; implicit-def: $vgpr36 -; SI-NEXT: ; implicit-def: $vgpr20 -; SI-NEXT: ; implicit-def: $vgpr55 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr33 -; SI-NEXT: ; implicit-def: $vgpr16 -; SI-NEXT: ; implicit-def: $vgpr45 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 ; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill ; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: ; kill: killed $vgpr1 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr2 -; SI-NEXT: ; kill: killed $vgpr2 -; SI-NEXT: ; implicit-def: $vgpr48 -; SI-NEXT: ; implicit-def: $vgpr22 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr47 ; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; SI-NEXT: ; implicit-def: $vgpr18 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill ; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr57 +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr40 +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr54 +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr49 +; SI-NEXT: ; implicit-def: $vgpr2 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill -; SI-NEXT: ; implicit-def: $vgpr14 ; SI-NEXT: ; implicit-def: $vgpr1 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr27 +; SI-NEXT: ; implicit-def: $vgpr2 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill ; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill -; SI-NEXT: ; implicit-def: $vgpr12 ; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; SI-NEXT: ; implicit-def: $vgpr44 +; SI-NEXT: ; implicit-def: $vgpr2 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v39, v35 +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v46, v9 +; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v53, v58 +; SI-NEXT: v_mov_b32_e32 v28, v3 +; SI-NEXT: v_mov_b32_e32 v38, v13 +; SI-NEXT: s_mov_b64 s[4:5], -1 +; SI-NEXT: v_mov_b32_e32 v52, v63 +; SI-NEXT: v_mov_b32_e32 v5, v23 +; SI-NEXT: ; implicit-def: $vgpr33 +; SI-NEXT: ; implicit-def: $vgpr30 +; SI-NEXT: ; implicit-def: $vgpr51 +; SI-NEXT: ; implicit-def: $vgpr26 +; SI-NEXT: ; implicit-def: $vgpr24 +; SI-NEXT: ; implicit-def: $vgpr22 +; SI-NEXT: ; implicit-def: $vgpr20 +; SI-NEXT: ; implicit-def: $vgpr18 +; SI-NEXT: ; implicit-def: $vgpr16 +; SI-NEXT: ; implicit-def: $vgpr14 +; SI-NEXT: ; implicit-def: $vgpr12 ; SI-NEXT: ; implicit-def: $vgpr10 -; SI-NEXT: ; implicit-def: $vgpr49 ; SI-NEXT: ; implicit-def: $vgpr8 -; SI-NEXT: ; implicit-def: $vgpr37 ; SI-NEXT: ; implicit-def: $vgpr6 -; SI-NEXT: ; implicit-def: $vgpr31 ; SI-NEXT: ; implicit-def: $vgpr4 -; SI-NEXT: ; implicit-def: $vgpr1 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; SI-NEXT: v_mov_b32_e32 v54, v50 -; SI-NEXT: v_mov_b32_e32 v9, v11 -; SI-NEXT: v_mov_b32_e32 v53, v5 -; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(1) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload -; SI-NEXT: v_mov_b32_e32 v56, v47 -; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload -; SI-NEXT: v_mov_b32_e32 v40, v3 -; SI-NEXT: v_mov_b32_e32 v44, v15 -; SI-NEXT: v_mov_b32_e32 v57, v13 -; SI-NEXT: v_mov_b32_e32 v46, v19 -; SI-NEXT: v_mov_b32_e32 v41, v27 -; SI-NEXT: s_mov_b64 s[4:5], -1 -; SI-NEXT: v_mov_b32_e32 v42, v43 -; SI-NEXT: v_mov_b32_e32 v3, v17 ; SI-NEXT: ; implicit-def: $vgpr2 ; SI-NEXT: .LBB105_3: ; %Flow -; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload +; SI-NEXT: v_mov_b32_e32 v13, v37 ; SI-NEXT: s_andn2_b64 vcc, exec, s[4:5] +; SI-NEXT: v_mov_b32_e32 v19, v48 +; SI-NEXT: v_mov_b32_e32 v63, v7 +; SI-NEXT: v_mov_b32_e32 v58, v53 +; SI-NEXT: v_mov_b32_e32 v37, v27 +; SI-NEXT: v_mov_b32_e32 v48, v49 ; SI-NEXT: s_cbranch_vccnz .LBB105_5 ; SI-NEXT: ; %bb.4: ; %cmp.true +; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v59 +; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 +; SI-NEXT: v_mov_b32_e32 v7, v28 +; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v4 +; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v41 +; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 +; SI-NEXT: v_mov_b32_e32 v17, v38 +; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v4 +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v30 -; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v4 -; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v31 -; SI-NEXT: v_mov_b32_e32 v38, v9 -; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v38 -; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 -; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14 -; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; SI-NEXT: v_and_b32_e32 v38, 0xffff0000, v31 -; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v45 +; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v2 +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v55 +; SI-NEXT: v_add_f32_e32 v37, 0x40c00000, v2 +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v15 +; SI-NEXT: v_add_f32_e32 v48, 0x40c00000, v2 +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v13 +; SI-NEXT: v_mov_b32_e32 v11, v50 +; SI-NEXT: v_add_f32_e32 v50, 0x40c00000, v2 +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v32 ; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 -; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 +; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v4 +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 +; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 +; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v4 +; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v25 +; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 +; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v4 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill ; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v29 -; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v4 -; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v30 -; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6 -; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 -; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6 -; SI-NEXT: s_waitcnt vmcnt(8) -; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8 -; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8 -; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 -; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10 -; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 -; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12 -; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 -; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(9) -; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 -; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v28 -; SI-NEXT: s_waitcnt vmcnt(6) -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v9 +; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 ; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 -; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v34 -; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v4 -; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v29 -; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v30 -; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload +; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v4 +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v5 +; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v21 +; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v3 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v56 +; SI-NEXT: v_add_f32_e32 v53, 0x40c00000, v2 +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v60 +; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v2 +; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v3 +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v42 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v52 +; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; SI-NEXT: v_add_f32_e32 v40, 0x40c00000, v2 +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v35 +; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v3 +; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v59, 0x40c00000, v2 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 +; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; SI-NEXT: v_add_f32_e32 v56, 0x40c00000, v2 +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v58 +; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v3 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v46 +; SI-NEXT: v_add_f32_e32 v46, 0x40c00000, v2 +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v1 +; SI-NEXT: v_add_f32_e32 v35, 0x40c00000, v2 +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v39 +; SI-NEXT: v_add_f32_e32 v61, 0x40c00000, v2 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v3 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v7 +; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v3 ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 ; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 -; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v32 -; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v4 -; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v27 -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 +; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v2 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 ; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 -; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16 -; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v1 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v40 -; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v4 -; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 -; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v26 -; SI-NEXT: v_alignbit_b32 v2, v4, v2, 16 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v11 -; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v54 -; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v2 -; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v19 -; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v7 -; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v2 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v15 -; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 -; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15 +; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v2 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload +; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v3 +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; SI-NEXT: v_add_f32_e32 v34, 0x40c00000, v2 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v34 +; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v3 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; SI-NEXT: v_add_f32_e32 v43, 0x40c00000, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v1 +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 ; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16 -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v50 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v44 -; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v2 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; SI-NEXT: v_add_f32_e32 v31, 0x40c00000, v2 ; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v16 -; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16 -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v5 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v31 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v57 -; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v2 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; SI-NEXT: v_add_f32_e32 v52, 0x40c00000, v2 ; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v17 -; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16 -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v3 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v52 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v46 -; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v2 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v2 ; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v13 -; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16 -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v63 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v26 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v41 -; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v2 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v2 ; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v11 -; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16 -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v61 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v24 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v52 -; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v2 +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v63 +; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v11 +; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v2 ; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v9 -; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v22 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v60 -; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v2 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v7 -; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13 -; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11 -; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9 -; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v2 ; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v20 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v25 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v19 ; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 -; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(3) +; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v2 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v5 -; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v2 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v17 +; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v2 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v16 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 -; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v2 +; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v2 ; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v3 -; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v14 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v56 -; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v2 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4 -; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3 -; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v2 ; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16 -; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v21 -; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v12 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v42 -; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v2 ; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 -; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v10 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_alignbit_b32 v2, v2, v1, 16 -; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4 -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4 -; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 -; SI-NEXT: v_alignbit_b32 v4, v6, v4, 16 -; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v53 -; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 -; SI-NEXT: v_alignbit_b32 v6, v8, v6, 16 -; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 -; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; SI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8 -; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8 -; SI-NEXT: v_alignbit_b32 v8, v10, v8, 16 -; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 -; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 -; SI-NEXT: v_alignbit_b32 v10, v12, v10, 16 -; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 -; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 -; SI-NEXT: v_alignbit_b32 v12, v14, v12, 16 -; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v23 -; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 -; SI-NEXT: v_alignbit_b32 v14, v18, v14, 16 -; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18 -; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; SI-NEXT: v_alignbit_b32 v18, v20, v18, 16 -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 -; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v23 -; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v47 -; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 -; SI-NEXT: v_alignbit_b32 v24, v24, v23, 16 -; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v26 -; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload -; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 -; SI-NEXT: v_alignbit_b32 v22, v21, v20, 16 -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v2 +; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v8 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v16 -; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload -; SI-NEXT: v_lshr_b64 v[48:49], v[21:22], 16 -; SI-NEXT: v_lshr_b64 v[49:50], v[7:8], 16 -; SI-NEXT: s_waitcnt vmcnt(2) -; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 -; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v26 -; SI-NEXT: v_alignbit_b32 v26, v59, v25, 16 -; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v27 -; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload -; SI-NEXT: v_lshr_b64 v[51:52], v[25:26], 16 -; SI-NEXT: v_lshr_b64 v[52:53], v[1:2], 16 -; SI-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt vmcnt(4) -; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 -; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v20 -; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(4) -; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 -; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; SI-NEXT: v_alignbit_b32 v16, v45, v16, 16 -; SI-NEXT: s_waitcnt vmcnt(3) -; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; SI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 -; SI-NEXT: v_alignbit_b32 v28, v58, v27, 16 -; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v29 -; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 -; SI-NEXT: v_alignbit_b32 v20, v55, v20, 16 -; SI-NEXT: v_lshr_b64 v[36:37], v[19:20], 16 +; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v29 -; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v2 +; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v6 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 -; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v29 -; SI-NEXT: v_alignbit_b32 v35, v43, v32, 16 -; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v30 -; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload -; SI-NEXT: v_lshr_b64 v[62:63], v[34:35], 16 -; SI-NEXT: v_lshr_b64 v[33:34], v[15:16], 16 +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v2 +; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 -; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v30 -; SI-NEXT: v_alignbit_b32 v39, v29, v32, 16 -; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill -; SI-NEXT: v_lshr_b64 v[31:32], v[38:39], 16 -; SI-NEXT: v_lshr_b64 v[37:38], v[5:6], 16 -; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[31:32], v[27:28], 16 -; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[31:32], v[23:24], 16 -; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[31:32], v[17:18], 16 -; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[31:32], v[13:14], 16 -; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2 +; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v2 +; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v3 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v3 ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[31:32], v[11:12], 16 -; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: v_mov_b32_e32 v2, v28 +; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[31:32], v[9:10], 16 -; SI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill -; SI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; SI-NEXT: v_lshr_b64 v[2:3], v[27:28], 16 +; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v4 +; SI-NEXT: v_mov_b32_e32 v4, v38 +; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[4:5], v[37:38], 16 +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v6 +; SI-NEXT: v_mov_b32_e32 v6, v49 +; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[6:7], v[48:49], 16 +; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v8 +; SI-NEXT: v_mov_b32_e32 v8, v51 +; SI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshr_b64 v[31:32], v[3:4], 16 +; SI-NEXT: v_lshr_b64 v[8:9], v[50:51], 16 +; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v10 +; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v52 +; SI-NEXT: v_lshr_b64 v[51:52], v[61:62], 16 +; SI-NEXT: s_waitcnt vmcnt(6) +; SI-NEXT: v_lshr_b64 v[10:11], v[27:28], 16 +; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v12 +; SI-NEXT: s_waitcnt vmcnt(4) +; SI-NEXT: v_lshr_b64 v[12:13], v[37:38], 16 +; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v14 +; SI-NEXT: v_lshr_b64 v[14:15], v[53:54], 16 +; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v16 +; SI-NEXT: v_mov_b32_e32 v16, v33 +; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[16:17], v[32:33], 16 +; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v18 +; SI-NEXT: v_mov_b32_e32 v18, v41 +; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[18:19], v[40:41], 16 +; SI-NEXT: v_mov_b32_e32 v39, v59 +; SI-NEXT: v_mov_b32_e32 v40, v60 +; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v20 +; SI-NEXT: v_lshr_b64 v[20:21], v[39:40], 16 +; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v22 +; SI-NEXT: v_lshr_b64 v[22:23], v[56:57], 16 +; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v24 +; SI-NEXT: v_lshr_b64 v[24:25], v[46:47], 16 +; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v26 +; SI-NEXT: v_lshr_b64 v[26:27], v[35:36], 16 +; SI-NEXT: v_mov_b32_e32 v27, v30 +; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v34 +; SI-NEXT: v_lshr_b64 v[33:34], v[29:30], 16 +; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v31 +; SI-NEXT: v_mov_b32_e32 v30, v44 +; SI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[30:31], v[43:44], 16 +; SI-NEXT: v_lshr_b64 v[43:44], v[32:33], 16 +; SI-NEXT: v_lshr_b64 v[34:35], v[50:51], 16 +; SI-NEXT: v_lshr_b64 v[48:49], v[5:6], 16 +; SI-NEXT: v_lshr_b64 v[37:38], v[3:4], 16 +; SI-NEXT: v_lshr_b64 v[44:45], v[1:2], 16 +; SI-NEXT: v_lshr_b64 v[27:28], v[25:26], 16 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[27:28], v[23:24], 16 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[27:28], v[21:22], 16 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[27:28], v[19:20], 16 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[27:28], v[17:18], 16 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[27:28], v[15:16], 16 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[27:28], v[13:14], 16 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[27:28], v[11:12], 16 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[27:28], v[9:10], 16 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill +; SI-NEXT: v_lshr_b64 v[31:32], v[29:30], 16 +; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_lshr_b64 v[27:28], v[7:8], 16 +; SI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill ; SI-NEXT: .LBB105_5: ; %end -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(5) +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v33 +; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload +; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v43 ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v52 -; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 -; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v39 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: v_and_b32_e32 v3, 0xffff, v32 +; SI-NEXT: v_or_b32_e32 v3, v3, v5 +; SI-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen +; SI-NEXT: s_waitcnt expcnt(2) +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt expcnt(1) +; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v28 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 4, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v62 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 +; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v31 +; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v32 +; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 8, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v35 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v43 +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v30 +; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(0) +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v30 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 12, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v34 ; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v29 -; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v27 +; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 16, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v28 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v58 +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v51 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v62 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 20, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v51 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v27 +; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v27 +; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 24, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_and_b32_e32 v1, 0xffff, v26 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v59 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v36 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 28, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v25 -; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v25 +; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v25 +; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 32, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_and_b32_e32 v1, 0xffff, v24 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v47 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 36, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v36 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 +; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v23 +; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v23 +; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 40, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v20 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v55 +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v22 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v57 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 44, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v33 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; SI-NEXT: v_or_b32_e32 v1, v3, v1 +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v21 +; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v21 +; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 48, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v16 -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v45 +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v20 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v40 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 52, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v48 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v19 +; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v19 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 56, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v22 +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v18 +; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v18 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 60, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v17 +; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v15 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v17 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 64, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v18 +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v16 +; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v16 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x44, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15 +; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v15 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x48, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_and_b32_e32 v1, 0xffff, v14 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v54 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x4c, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13 +; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v13 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x50, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_and_b32_e32 v1, 0xffff, v12 +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v12 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x54, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11 +; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v11 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x58, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_and_b32_e32 v1, 0xffff, v10 +; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v10 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x5c, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v49 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9 +; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v9 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x60, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_and_b32_e32 v1, 0xffff, v8 +; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v8 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x64, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v37 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v48 +; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x68, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_and_b32_e32 v1, 0xffff, v6 +; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v6 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x6c, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v31 -; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v37 +; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x70, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_and_b32_e32 v1, 0xffff, v4 +; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x74, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen -; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload -; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload -; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload +; SI-NEXT: s_waitcnt vmcnt(1) expcnt(0) +; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3 +; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v44 ; SI-NEXT: v_or_b32_e32 v1, v1, v3 ; SI-NEXT: v_add_i32_e32 v3, vcc, 0x78, v0 ; SI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_and_b32_e32 v1, 0xffff, v2 -; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3 ; SI-NEXT: v_or_b32_e32 v1, v1, v2 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload @@ -234937,655 +231576,724 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a ; VI-LABEL: bitcast_v64bf16_to_v64i16_scalar: ; VI: ; %bb.0: ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; VI-NEXT: s_or_saveexec_b64 s[4:5], -1 -; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; VI-NEXT: s_mov_b64 exec, s[4:5] -; VI-NEXT: v_writelane_b32 v42, s30, 0 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 -; VI-NEXT: v_writelane_b32 v42, s31, 1 +; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; VI-NEXT: v_mov_b32_e32 v31, v17 ; VI-NEXT: v_mov_b32_e32 v30, v16 -; VI-NEXT: v_mov_b32_e32 v29, v15 +; VI-NEXT: v_mov_b32_e32 v48, v15 +; VI-NEXT: v_mov_b32_e32 v49, v13 +; VI-NEXT: v_mov_b32_e32 v50, v11 +; VI-NEXT: v_mov_b32_e32 v51, v9 +; VI-NEXT: v_mov_b32_e32 v52, v7 +; VI-NEXT: v_mov_b32_e32 v53, v5 +; VI-NEXT: v_mov_b32_e32 v54, v3 +; VI-NEXT: v_mov_b32_e32 v55, v1 ; VI-NEXT: v_mov_b32_e32 v28, v14 -; VI-NEXT: v_mov_b32_e32 v27, v13 ; VI-NEXT: v_mov_b32_e32 v26, v12 -; VI-NEXT: v_mov_b32_e32 v25, v11 ; VI-NEXT: v_mov_b32_e32 v24, v10 -; VI-NEXT: v_mov_b32_e32 v23, v9 ; VI-NEXT: v_mov_b32_e32 v22, v8 -; VI-NEXT: v_mov_b32_e32 v21, v7 ; VI-NEXT: v_mov_b32_e32 v20, v6 -; VI-NEXT: v_mov_b32_e32 v19, v5 -; VI-NEXT: v_mov_b32_e32 v32, v4 -; VI-NEXT: v_mov_b32_e32 v17, v3 +; VI-NEXT: v_mov_b32_e32 v40, v4 ; VI-NEXT: v_mov_b32_e32 v16, v2 -; VI-NEXT: v_readfirstlane_b32 s30, v0 +; VI-NEXT: v_mov_b32_e32 v14, v0 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec -; VI-NEXT: v_readfirstlane_b32 s31, v1 -; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 ; 4-byte Folded Spill -; VI-NEXT: s_cbranch_scc0 .LBB105_3 +; VI-NEXT: v_mov_b32_e32 v39, s17 +; VI-NEXT: v_mov_b32_e32 v38, s19 +; VI-NEXT: v_mov_b32_e32 v37, s21 +; VI-NEXT: v_mov_b32_e32 v36, s23 +; VI-NEXT: v_mov_b32_e32 v35, s25 +; VI-NEXT: v_mov_b32_e32 v34, s27 +; VI-NEXT: v_mov_b32_e32 v18, s29 +; VI-NEXT: v_mov_b32_e32 v0, s16 +; VI-NEXT: v_mov_b32_e32 v2, s18 +; VI-NEXT: v_mov_b32_e32 v4, s20 +; VI-NEXT: v_mov_b32_e32 v6, s22 +; VI-NEXT: v_mov_b32_e32 v8, s24 +; VI-NEXT: v_mov_b32_e32 v10, s26 +; VI-NEXT: v_mov_b32_e32 v12, s28 +; VI-NEXT: s_cbranch_scc0 .LBB105_4 ; VI-NEXT: ; %bb.1: ; %cmp.false -; VI-NEXT: s_cbranch_execnz .LBB105_4 +; VI-NEXT: s_cbranch_execnz .LBB105_3 ; VI-NEXT: .LBB105_2: ; %cmp.true -; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000 -; VI-NEXT: s_lshl_b32 s4, s30, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v16 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v16 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s30, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v54 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v3 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v15, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: s_lshl_b32 s4, s31, 16 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_add_f32_e32 v3, s4, v0 -; VI-NEXT: v_bfe_u32 v4, v3, 16, 1 -; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3 -; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4 -; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v54 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; VI-NEXT: s_and_b32 s4, s31, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; VI-NEXT: v_add_f32_e32 v4, s4, v0 -; VI-NEXT: v_bfe_u32 v5, v4, 16, 1 -; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4 -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s29, 16 +; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v40 +; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_cndmask_b32_e32 v15, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v40 ; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 -; VI-NEXT: v_alignbit_b32 v14, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_alignbit_b32 v15, v4, v3, 16 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s29, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v53 +; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v3 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v15, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s28, 16 -; VI-NEXT: v_alignbit_b32 v13, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s28, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 -; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s27, 16 -; VI-NEXT: v_alignbit_b32 v12, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v53 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v20 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_cndmask_b32_e32 v40, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v20 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s27, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v52 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v3 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v20, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s26, 16 -; VI-NEXT: v_alignbit_b32 v11, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s26, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v52 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v22 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_cndmask_b32_e32 v52, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v22 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v51 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v3 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v22, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s25, 16 -; VI-NEXT: v_alignbit_b32 v10, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s25, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v51 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v24 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_cndmask_b32_e32 v42, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v24 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v50 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v3 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v24, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s24, 16 -; VI-NEXT: v_alignbit_b32 v9, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s24, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v50 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v26 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_cndmask_b32_e32 v50, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v26 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v49 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v3 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v26, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s23, 16 -; VI-NEXT: v_alignbit_b32 v8, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s23, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v49 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v28 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_cndmask_b32_e32 v44, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_lshrrev_b32_e32 v45, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v28 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v48 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v3 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v28, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s22, 16 -; VI-NEXT: v_alignbit_b32 v7, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s22, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v48 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v30 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_cndmask_b32_e32 v48, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v30 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v7, vcc +; VI-NEXT: v_bfe_u32 v5, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v31 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v47, 16, v3 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v46, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s21, 16 -; VI-NEXT: v_alignbit_b32 v6, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s21, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc +; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v31 +; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; VI-NEXT: v_bfe_u32 v5, v3, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0 +; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; VI-NEXT: v_bfe_u32 v3, v0, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v30, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v0 ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s20, 16 -; VI-NEXT: v_alignbit_b32 v5, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 -; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v0 +; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v39 +; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s20, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 +; VI-NEXT: v_bfe_u32 v1, v0, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v16, v3, v5, vcc +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1 +; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v39 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v3, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v1 ; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s19, 16 -; VI-NEXT: v_alignbit_b32 v4, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v2 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v57, 16, v0 +; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v2 ; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v56, v3, v5, vcc ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 ; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 ; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s19, 0xffff0000 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 ; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v3, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2 -; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3 -; VI-NEXT: v_or_b32_e32 v18, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v3, v18, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s18, 16 -; VI-NEXT: v_alignbit_b32 v3, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v2, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1 +; VI-NEXT: v_bfe_u32 v2, v0, 16, 1 +; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0 ; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2 -; VI-NEXT: v_or_b32_e32 v18, 0x400000, v1 +; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v38 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; VI-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc +; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1 +; VI-NEXT: v_bfe_u32 v1, v0, 16, 1 +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_cndmask_b32_e32 v0, v1, v5, vcc +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v38 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v5, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v1 +; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s18, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v2, v18, vcc -; VI-NEXT: v_add_f32_e32 v2, s4, v0 -; VI-NEXT: v_bfe_u32 v18, v2, 16, 1 -; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v2 -; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18 -; VI-NEXT: v_or_b32_e32 v33, 0x400000, v2 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; VI-NEXT: v_cndmask_b32_e32 v2, v18, v33, vcc -; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; VI-NEXT: s_lshl_b32 s4, s17, 16 -; VI-NEXT: v_alignbit_b32 v2, v2, v1, 16 -; VI-NEXT: v_add_f32_e32 v1, s4, v0 -; VI-NEXT: v_bfe_u32 v18, v1, 16, 1 -; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v1 -; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18 -; VI-NEXT: v_or_b32_e32 v33, 0x400000, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v4 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v59, 16, v0 +; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v4 +; VI-NEXT: v_bfe_u32 v4, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v58, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v1 +; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v1 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; VI-NEXT: s_and_b32 s4, s17, 0xffff0000 -; VI-NEXT: v_cndmask_b32_e32 v1, v18, v33, vcc -; VI-NEXT: v_add_f32_e32 v18, s4, v0 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v18 -; VI-NEXT: s_lshl_b32 s4, s16, 16 -; VI-NEXT: v_alignbit_b32 v1, v18, v1, 16 -; VI-NEXT: v_add_f32_e32 v18, s4, v0 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: s_and_b32 s4, s16, 0xffff0000 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v0, s4, v0 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v0, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v0 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v0 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; VI-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc +; VI-NEXT: v_bfe_u32 v4, v0, 16, 1 +; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v0 +; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4 +; VI-NEXT: v_or_b32_e32 v5, 0x400000, v0 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; VI-NEXT: v_cndmask_b32_e32 v0, v33, v34, vcc -; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; VI-NEXT: v_alignbit_b32 v0, v0, v18, 16 -; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v16 +; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v37 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; VI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc +; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v1 +; VI-NEXT: v_bfe_u32 v1, v0, 16, 1 +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_cndmask_b32_e32 v0, v1, v7, vcc +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v37 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v7, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v1 +; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7 +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v6 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v61, 16, v0 +; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v6 +; VI-NEXT: v_bfe_u32 v6, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v60, v7, v9, vcc +; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v1 +; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; VI-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc +; VI-NEXT: v_bfe_u32 v6, v0, 16, 1 +; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v0 +; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6 +; VI-NEXT: v_or_b32_e32 v7, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v36 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; VI-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc +; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v1 +; VI-NEXT: v_bfe_u32 v1, v0, 16, 1 +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1 +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_cndmask_b32_e32 v0, v1, v9, vcc +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v36 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_bfe_u32 v9, v1, 16, 1 +; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v1 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9 +; VI-NEXT: v_or_b32_e32 v11, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v8 +; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; VI-NEXT: v_lshrrev_b32_e32 v63, 16, v0 +; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v8 +; VI-NEXT: v_bfe_u32 v8, v1, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v62, v9, v11, vcc +; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v1 +; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8 +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v1 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; VI-NEXT: v_cndmask_b32_e32 v1, v8, v9, vcc +; VI-NEXT: v_bfe_u32 v8, v0, 16, 1 +; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v0 +; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8 +; VI-NEXT: v_or_b32_e32 v9, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v35 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; VI-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc +; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v1 +; VI-NEXT: v_bfe_u32 v1, v0, 16, 1 +; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0 +; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1 +; VI-NEXT: v_or_b32_e32 v11, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v35 +; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 +; VI-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc +; VI-NEXT: v_bfe_u32 v11, v0, 16, 1 +; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v0 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 +; VI-NEXT: v_or_b32_e32 v13, 0x400000, v0 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; VI-NEXT: v_cndmask_b32_e32 v0, v11, v13, vcc +; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v10 +; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10 +; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 +; VI-NEXT: v_bfe_u32 v13, v10, 16, 1 +; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v10 +; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 +; VI-NEXT: v_or_b32_e32 v15, 0x400000, v10 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 +; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v11 +; VI-NEXT: v_bfe_u32 v11, v10, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc +; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v10 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11 +; VI-NEXT: v_or_b32_e32 v15, 0x400000, v10 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 +; VI-NEXT: v_cndmask_b32_e32 v10, v11, v15, vcc +; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v13 +; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v34 +; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; VI-NEXT: v_bfe_u32 v15, v13, 16, 1 +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 +; VI-NEXT: v_or_b32_e32 v19, 0x400000, v13 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 +; VI-NEXT: v_cndmask_b32_e32 v13, v15, v19, vcc +; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v34 +; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; VI-NEXT: v_bfe_u32 v19, v15, 16, 1 +; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v15 +; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v13 +; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v12 +; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12 +; VI-NEXT: v_add_u32_e32 v19, vcc, 0x7fff, v19 +; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 +; VI-NEXT: v_or_b32_e32 v32, 0x400000, v15 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 +; VI-NEXT: v_bfe_u32 v15, v12, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v32, v19, v32, vcc +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v12 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 +; VI-NEXT: v_or_b32_e32 v19, 0x400000, v12 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 +; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v13 +; VI-NEXT: v_bfe_u32 v13, v12, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v15, v15, v19, vcc +; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v12 +; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13 +; VI-NEXT: v_or_b32_e32 v19, 0x400000, v12 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 +; VI-NEXT: v_cndmask_b32_e32 v12, v13, v19, vcc +; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v15 +; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v18 +; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15 +; VI-NEXT: v_bfe_u32 v19, v15, 16, 1 +; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v15 +; VI-NEXT: v_add_u32_e32 v19, vcc, 0x7fff, v19 +; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18 +; VI-NEXT: v_or_b32_e32 v34, 0x400000, v15 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 ; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 -; VI-NEXT: v_bfe_u32 v33, v18, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v18 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16 +; VI-NEXT: v_cndmask_b32_e32 v15, v19, v34, vcc +; VI-NEXT: v_bfe_u32 v19, v18, 16, 1 +; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v18 +; VI-NEXT: v_add_u32_e32 v19, vcc, 0x7fff, v19 ; VI-NEXT: v_or_b32_e32 v34, 0x400000, v18 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 -; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; VI-NEXT: v_cndmask_b32_e32 v18, v33, v34, vcc -; VI-NEXT: v_bfe_u32 v33, v16, 16, 1 -; VI-NEXT: v_add_u32_e32 v33, vcc, v33, v16 -; VI-NEXT: v_add_u32_e32 v33, vcc, 0x7fff, v33 -; VI-NEXT: v_or_b32_e32 v34, 0x400000, v16 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16 -; VI-NEXT: v_cndmask_b32_e32 v16, v33, v34, vcc -; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v17 -; VI-NEXT: v_add_f32_e32 v33, 0x40c00000, v33 -; VI-NEXT: v_bfe_u32 v34, v33, 16, 1 -; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v33 -; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34 -; VI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17 -; VI-NEXT: v_or_b32_e32 v35, 0x400000, v33 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v33, v33 -; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 -; VI-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc -; VI-NEXT: v_bfe_u32 v34, v17, 16, 1 -; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v17 +; VI-NEXT: v_cndmask_b32_e32 v18, v19, v34, vcc +; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v15 +; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v14 +; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14 +; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 +; VI-NEXT: v_bfe_u32 v34, v14, 16, 1 +; VI-NEXT: v_add_u32_e32 v34, vcc, v34, v14 ; VI-NEXT: v_add_u32_e32 v34, vcc, 0x7fff, v34 -; VI-NEXT: v_or_b32_e32 v35, 0x400000, v17 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 -; VI-NEXT: v_cndmask_b32_e32 v17, v34, v35, vcc -; VI-NEXT: v_lshlrev_b32_e32 v34, 16, v32 +; VI-NEXT: v_or_b32_e32 v35, 0x400000, v14 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 +; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v15 +; VI-NEXT: v_bfe_u32 v15, v14, 16, 1 +; VI-NEXT: v_cndmask_b32_e32 v34, v34, v35, vcc +; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v14 +; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15 +; VI-NEXT: v_or_b32_e32 v35, 0x400000, v14 +; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 +; VI-NEXT: v_cndmask_b32_e32 v14, v15, v35, vcc +; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v34 +; VI-NEXT: v_and_b32_e32 v34, 0xffff0000, v55 ; VI-NEXT: v_add_f32_e32 v34, 0x40c00000, v34 ; VI-NEXT: v_bfe_u32 v35, v34, 16, 1 ; VI-NEXT: v_add_u32_e32 v35, vcc, v35, v34 ; VI-NEXT: v_add_u32_e32 v35, vcc, 0x7fff, v35 -; VI-NEXT: v_and_b32_e32 v32, 0xffff0000, v32 ; VI-NEXT: v_or_b32_e32 v36, 0x400000, v34 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v34, v34 -; VI-NEXT: v_add_f32_e32 v32, 0x40c00000, v32 ; VI-NEXT: v_cndmask_b32_e32 v34, v35, v36, vcc -; VI-NEXT: v_bfe_u32 v35, v32, 16, 1 -; VI-NEXT: v_add_u32_e32 v35, vcc, v35, v32 -; VI-NEXT: v_add_u32_e32 v35, vcc, 0x7fff, v35 -; VI-NEXT: v_or_b32_e32 v36, 0x400000, v32 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 -; VI-NEXT: v_cndmask_b32_e32 v32, v35, v36, vcc -; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v19 +; VI-NEXT: v_lshlrev_b32_e32 v35, 16, v55 ; VI-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 ; VI-NEXT: v_bfe_u32 v36, v35, 16, 1 ; VI-NEXT: v_add_u32_e32 v36, vcc, v36, v35 ; VI-NEXT: v_add_u32_e32 v36, vcc, 0x7fff, v36 -; VI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19 ; VI-NEXT: v_or_b32_e32 v37, 0x400000, v35 ; VI-NEXT: v_cmp_u_f32_e32 vcc, v35, v35 -; VI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 -; VI-NEXT: v_cndmask_b32_e32 v35, v36, v37, vcc -; VI-NEXT: v_bfe_u32 v36, v19, 16, 1 -; VI-NEXT: v_add_u32_e32 v36, vcc, v36, v19 -; VI-NEXT: v_add_u32_e32 v36, vcc, 0x7fff, v36 -; VI-NEXT: v_or_b32_e32 v37, 0x400000, v19 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 -; VI-NEXT: v_cndmask_b32_e32 v19, v36, v37, vcc -; VI-NEXT: v_lshlrev_b32_e32 v36, 16, v20 -; VI-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 -; VI-NEXT: v_bfe_u32 v37, v36, 16, 1 -; VI-NEXT: v_add_u32_e32 v37, vcc, v37, v36 -; VI-NEXT: v_add_u32_e32 v37, vcc, 0x7fff, v37 -; VI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20 -; VI-NEXT: v_or_b32_e32 v38, 0x400000, v36 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v36, v36 -; VI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 -; VI-NEXT: v_cndmask_b32_e32 v36, v37, v38, vcc -; VI-NEXT: v_bfe_u32 v37, v20, 16, 1 -; VI-NEXT: v_add_u32_e32 v37, vcc, v37, v20 -; VI-NEXT: v_add_u32_e32 v37, vcc, 0x7fff, v37 -; VI-NEXT: v_or_b32_e32 v38, 0x400000, v20 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 -; VI-NEXT: v_cndmask_b32_e32 v20, v37, v38, vcc -; VI-NEXT: v_lshlrev_b32_e32 v37, 16, v21 -; VI-NEXT: v_add_f32_e32 v37, 0x40c00000, v37 -; VI-NEXT: v_bfe_u32 v38, v37, 16, 1 -; VI-NEXT: v_add_u32_e32 v38, vcc, v38, v37 -; VI-NEXT: v_add_u32_e32 v38, vcc, 0x7fff, v38 -; VI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21 -; VI-NEXT: v_or_b32_e32 v39, 0x400000, v37 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 -; VI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 -; VI-NEXT: v_cndmask_b32_e32 v37, v38, v39, vcc -; VI-NEXT: v_bfe_u32 v38, v21, 16, 1 -; VI-NEXT: v_add_u32_e32 v38, vcc, v38, v21 -; VI-NEXT: v_add_u32_e32 v38, vcc, 0x7fff, v38 -; VI-NEXT: v_or_b32_e32 v39, 0x400000, v21 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 -; VI-NEXT: v_cndmask_b32_e32 v21, v38, v39, vcc -; VI-NEXT: v_lshlrev_b32_e32 v38, 16, v22 -; VI-NEXT: v_add_f32_e32 v38, 0x40c00000, v38 -; VI-NEXT: v_bfe_u32 v39, v38, 16, 1 -; VI-NEXT: v_add_u32_e32 v39, vcc, v39, v38 -; VI-NEXT: v_add_u32_e32 v39, vcc, 0x7fff, v39 -; VI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22 -; VI-NEXT: v_or_b32_e32 v48, 0x400000, v38 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v38, v38 -; VI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 -; VI-NEXT: v_cndmask_b32_e32 v38, v39, v48, vcc -; VI-NEXT: v_bfe_u32 v39, v22, 16, 1 -; VI-NEXT: v_add_u32_e32 v39, vcc, v39, v22 -; VI-NEXT: v_add_u32_e32 v39, vcc, 0x7fff, v39 -; VI-NEXT: v_or_b32_e32 v48, 0x400000, v22 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 -; VI-NEXT: v_cndmask_b32_e32 v22, v39, v48, vcc -; VI-NEXT: v_lshlrev_b32_e32 v39, 16, v23 -; VI-NEXT: v_add_f32_e32 v39, 0x40c00000, v39 -; VI-NEXT: v_bfe_u32 v48, v39, 16, 1 -; VI-NEXT: v_add_u32_e32 v48, vcc, v48, v39 -; VI-NEXT: v_add_u32_e32 v48, vcc, 0x7fff, v48 -; VI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23 -; VI-NEXT: v_or_b32_e32 v49, 0x400000, v39 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v39, v39 -; VI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 -; VI-NEXT: v_cndmask_b32_e32 v39, v48, v49, vcc -; VI-NEXT: v_bfe_u32 v48, v23, 16, 1 -; VI-NEXT: v_add_u32_e32 v48, vcc, v48, v23 -; VI-NEXT: v_add_u32_e32 v48, vcc, 0x7fff, v48 -; VI-NEXT: v_or_b32_e32 v49, 0x400000, v23 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 -; VI-NEXT: v_cndmask_b32_e32 v23, v48, v49, vcc -; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v24 -; VI-NEXT: v_add_f32_e32 v48, 0x40c00000, v48 -; VI-NEXT: v_bfe_u32 v49, v48, 16, 1 -; VI-NEXT: v_add_u32_e32 v49, vcc, v49, v48 -; VI-NEXT: v_add_u32_e32 v49, vcc, 0x7fff, v49 -; VI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24 -; VI-NEXT: v_or_b32_e32 v50, 0x400000, v48 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v48, v48 -; VI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 -; VI-NEXT: v_cndmask_b32_e32 v48, v49, v50, vcc -; VI-NEXT: v_bfe_u32 v49, v24, 16, 1 -; VI-NEXT: v_add_u32_e32 v49, vcc, v49, v24 -; VI-NEXT: v_add_u32_e32 v49, vcc, 0x7fff, v49 -; VI-NEXT: v_or_b32_e32 v50, 0x400000, v24 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; VI-NEXT: v_cndmask_b32_e32 v24, v49, v50, vcc -; VI-NEXT: v_lshlrev_b32_e32 v49, 16, v25 -; VI-NEXT: v_add_f32_e32 v49, 0x40c00000, v49 -; VI-NEXT: v_bfe_u32 v50, v49, 16, 1 -; VI-NEXT: v_add_u32_e32 v50, vcc, v50, v49 -; VI-NEXT: v_add_u32_e32 v50, vcc, 0x7fff, v50 -; VI-NEXT: v_and_b32_e32 v25, 0xffff0000, v25 -; VI-NEXT: v_or_b32_e32 v51, 0x400000, v49 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v49, v49 -; VI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 -; VI-NEXT: v_cndmask_b32_e32 v49, v50, v51, vcc -; VI-NEXT: v_bfe_u32 v50, v25, 16, 1 -; VI-NEXT: v_add_u32_e32 v50, vcc, v50, v25 -; VI-NEXT: v_add_u32_e32 v50, vcc, 0x7fff, v50 -; VI-NEXT: v_or_b32_e32 v51, 0x400000, v25 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 -; VI-NEXT: v_cndmask_b32_e32 v25, v50, v51, vcc -; VI-NEXT: v_lshlrev_b32_e32 v50, 16, v26 -; VI-NEXT: v_add_f32_e32 v50, 0x40c00000, v50 -; VI-NEXT: v_bfe_u32 v51, v50, 16, 1 -; VI-NEXT: v_add_u32_e32 v51, vcc, v51, v50 -; VI-NEXT: v_add_u32_e32 v51, vcc, 0x7fff, v51 -; VI-NEXT: v_and_b32_e32 v26, 0xffff0000, v26 -; VI-NEXT: v_or_b32_e32 v52, 0x400000, v50 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 -; VI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 -; VI-NEXT: v_cndmask_b32_e32 v50, v51, v52, vcc -; VI-NEXT: v_bfe_u32 v51, v26, 16, 1 -; VI-NEXT: v_add_u32_e32 v51, vcc, v51, v26 -; VI-NEXT: v_add_u32_e32 v51, vcc, 0x7fff, v51 -; VI-NEXT: v_or_b32_e32 v52, 0x400000, v26 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 -; VI-NEXT: v_cndmask_b32_e32 v26, v51, v52, vcc -; VI-NEXT: v_lshlrev_b32_e32 v51, 16, v27 -; VI-NEXT: v_add_f32_e32 v51, 0x40c00000, v51 -; VI-NEXT: v_bfe_u32 v52, v51, 16, 1 -; VI-NEXT: v_add_u32_e32 v52, vcc, v52, v51 -; VI-NEXT: v_add_u32_e32 v52, vcc, 0x7fff, v52 -; VI-NEXT: v_and_b32_e32 v27, 0xffff0000, v27 -; VI-NEXT: v_or_b32_e32 v53, 0x400000, v51 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 -; VI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 -; VI-NEXT: v_cndmask_b32_e32 v51, v52, v53, vcc -; VI-NEXT: v_bfe_u32 v52, v27, 16, 1 -; VI-NEXT: v_add_u32_e32 v52, vcc, v52, v27 -; VI-NEXT: v_add_u32_e32 v52, vcc, 0x7fff, v52 -; VI-NEXT: v_or_b32_e32 v53, 0x400000, v27 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 -; VI-NEXT: v_cndmask_b32_e32 v27, v52, v53, vcc -; VI-NEXT: v_lshlrev_b32_e32 v52, 16, v28 -; VI-NEXT: v_add_f32_e32 v52, 0x40c00000, v52 -; VI-NEXT: v_bfe_u32 v53, v52, 16, 1 -; VI-NEXT: v_add_u32_e32 v53, vcc, v53, v52 -; VI-NEXT: v_add_u32_e32 v53, vcc, 0x7fff, v53 -; VI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28 -; VI-NEXT: v_or_b32_e32 v54, 0x400000, v52 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v52, v52 -; VI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 -; VI-NEXT: v_cndmask_b32_e32 v52, v53, v54, vcc -; VI-NEXT: v_bfe_u32 v53, v28, 16, 1 -; VI-NEXT: v_add_u32_e32 v53, vcc, v53, v28 -; VI-NEXT: v_add_u32_e32 v53, vcc, 0x7fff, v53 -; VI-NEXT: v_or_b32_e32 v54, 0x400000, v28 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 -; VI-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc -; VI-NEXT: v_lshlrev_b32_e32 v53, 16, v29 -; VI-NEXT: v_add_f32_e32 v53, 0x40c00000, v53 -; VI-NEXT: v_bfe_u32 v54, v53, 16, 1 -; VI-NEXT: v_add_u32_e32 v54, vcc, v54, v53 -; VI-NEXT: v_add_u32_e32 v54, vcc, 0x7fff, v54 -; VI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29 -; VI-NEXT: v_or_b32_e32 v55, 0x400000, v53 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v53, v53 -; VI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 -; VI-NEXT: v_cndmask_b32_e32 v53, v54, v55, vcc -; VI-NEXT: v_bfe_u32 v54, v29, 16, 1 -; VI-NEXT: v_add_u32_e32 v54, vcc, v54, v29 -; VI-NEXT: v_add_u32_e32 v54, vcc, 0x7fff, v54 -; VI-NEXT: v_or_b32_e32 v55, 0x400000, v29 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 -; VI-NEXT: v_cndmask_b32_e32 v29, v54, v55, vcc -; VI-NEXT: v_lshlrev_b32_e32 v54, 16, v30 -; VI-NEXT: v_add_f32_e32 v54, 0x40c00000, v54 -; VI-NEXT: v_bfe_u32 v55, v54, 16, 1 -; VI-NEXT: v_add_u32_e32 v55, vcc, v55, v54 -; VI-NEXT: v_add_u32_e32 v55, vcc, 0x7fff, v55 -; VI-NEXT: v_and_b32_e32 v30, 0xffff0000, v30 -; VI-NEXT: v_or_b32_e32 v40, 0x400000, v54 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v54, v54 -; VI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 -; VI-NEXT: v_cndmask_b32_e32 v54, v55, v40, vcc -; VI-NEXT: v_bfe_u32 v55, v30, 16, 1 -; VI-NEXT: v_add_u32_e32 v55, vcc, v55, v30 -; VI-NEXT: v_add_u32_e32 v55, vcc, 0x7fff, v55 -; VI-NEXT: v_or_b32_e32 v40, 0x400000, v30 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 -; VI-NEXT: v_cndmask_b32_e32 v30, v55, v40, vcc -; VI-NEXT: v_lshlrev_b32_e32 v55, 16, v31 -; VI-NEXT: v_add_f32_e32 v55, 0x40c00000, v55 -; VI-NEXT: v_bfe_u32 v40, v55, 16, 1 -; VI-NEXT: v_add_u32_e32 v40, vcc, v40, v55 -; VI-NEXT: v_add_u32_e32 v40, vcc, 0x7fff, v40 -; VI-NEXT: v_and_b32_e32 v31, 0xffff0000, v31 -; VI-NEXT: v_or_b32_e32 v41, 0x400000, v55 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v55, v55 -; VI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 -; VI-NEXT: v_cndmask_b32_e32 v55, v40, v41, vcc -; VI-NEXT: v_bfe_u32 v40, v31, 16, 1 -; VI-NEXT: v_add_u32_e32 v40, vcc, v40, v31 -; VI-NEXT: v_add_u32_e32 v40, vcc, 0x7fff, v40 -; VI-NEXT: v_or_b32_e32 v41, 0x400000, v31 -; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31 -; VI-NEXT: v_cndmask_b32_e32 v31, v40, v41, vcc -; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v29 -; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v28 -; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v26 -; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v25 -; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v23 -; VI-NEXT: v_lshrrev_b32_e32 v22, 16, v22 -; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; VI-NEXT: v_alignbit_b32 v31, v31, v55, 16 -; VI-NEXT: v_alignbit_b32 v30, v30, v54, 16 -; VI-NEXT: v_alignbit_b32 v29, v29, v53, 16 -; VI-NEXT: v_alignbit_b32 v28, v28, v52, 16 -; VI-NEXT: v_alignbit_b32 v27, v27, v51, 16 -; VI-NEXT: v_alignbit_b32 v26, v26, v50, 16 -; VI-NEXT: v_alignbit_b32 v25, v25, v49, 16 -; VI-NEXT: v_alignbit_b32 v24, v24, v48, 16 -; VI-NEXT: v_alignbit_b32 v23, v23, v39, 16 -; VI-NEXT: v_alignbit_b32 v22, v22, v38, 16 -; VI-NEXT: v_alignbit_b32 v21, v21, v37, 16 -; VI-NEXT: v_alignbit_b32 v20, v20, v36, 16 -; VI-NEXT: v_alignbit_b32 v19, v19, v35, 16 -; VI-NEXT: v_alignbit_b32 v32, v32, v34, 16 -; VI-NEXT: v_alignbit_b32 v17, v17, v33, 16 -; VI-NEXT: v_alignbit_b32 v16, v16, v18, 16 -; VI-NEXT: s_branch .LBB105_5 -; VI-NEXT: .LBB105_3: -; VI-NEXT: s_branch .LBB105_2 -; VI-NEXT: .LBB105_4: -; VI-NEXT: v_mov_b32_e32 v0, s16 -; VI-NEXT: v_mov_b32_e32 v1, s17 -; VI-NEXT: v_mov_b32_e32 v2, s18 -; VI-NEXT: v_mov_b32_e32 v3, s19 -; VI-NEXT: v_mov_b32_e32 v4, s20 -; VI-NEXT: v_mov_b32_e32 v5, s21 -; VI-NEXT: v_mov_b32_e32 v6, s22 -; VI-NEXT: v_mov_b32_e32 v7, s23 -; VI-NEXT: v_mov_b32_e32 v8, s24 -; VI-NEXT: v_mov_b32_e32 v9, s25 -; VI-NEXT: v_mov_b32_e32 v10, s26 -; VI-NEXT: v_mov_b32_e32 v11, s27 -; VI-NEXT: v_mov_b32_e32 v12, s28 -; VI-NEXT: v_mov_b32_e32 v13, s29 -; VI-NEXT: v_mov_b32_e32 v14, s30 -; VI-NEXT: v_mov_b32_e32 v15, s31 -; VI-NEXT: .LBB105_5: ; %end -; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 ; 4-byte Folded Reload -; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload -; VI-NEXT: v_mov_b32_e32 v18, v32 -; VI-NEXT: v_readlane_b32 s31, v42, 1 -; VI-NEXT: v_readlane_b32 s30, v42, 0 -; VI-NEXT: s_or_saveexec_b64 s[4:5], -1 -; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload -; VI-NEXT: s_mov_b64 exec, s[4:5] +; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v34 +; VI-NEXT: v_lshrrev_b64 v[34:35], 16, v[56:57] +; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 +; VI-NEXT: v_mov_b32_e32 v39, v34 +; VI-NEXT: v_lshrrev_b64 v[34:35], 16, v[58:59] +; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1] +; VI-NEXT: v_mov_b32_e32 v38, v34 +; VI-NEXT: v_lshrrev_b64 v[34:35], 16, v[60:61] +; VI-NEXT: v_cndmask_b32_e32 v54, v36, v37, vcc +; VI-NEXT: v_mov_b32_e32 v37, v34 +; VI-NEXT: v_lshrrev_b64 v[34:35], 16, v[62:63] +; VI-NEXT: v_mov_b32_e32 v35, v0 +; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[32:33] +; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; VI-NEXT: v_mov_b32_e32 v36, v34 +; VI-NEXT: v_mov_b32_e32 v34, v0 +; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[54:55] +; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[14:15] +; VI-NEXT: v_mov_b32_e32 v55, v0 +; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[40:41] +; VI-NEXT: v_lshrrev_b64 v[18:19], 16, v[18:19] +; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[12:13] +; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[10:11] +; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[8:9] +; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[6:7] +; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[4:5] +; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[2:3] +; VI-NEXT: v_lshrrev_b64 v[28:29], 16, v[28:29] +; VI-NEXT: v_lshrrev_b64 v[26:27], 16, v[26:27] +; VI-NEXT: v_lshrrev_b64 v[24:25], 16, v[24:25] +; VI-NEXT: v_lshrrev_b64 v[22:23], 16, v[22:23] +; VI-NEXT: v_lshrrev_b64 v[20:21], 16, v[20:21] +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshrrev_b64 v[32:33], 16, v[32:33] +; VI-NEXT: v_mov_b32_e32 v54, v32 +; VI-NEXT: v_lshrrev_b64 v[32:33], 16, v[52:53] +; VI-NEXT: v_mov_b32_e32 v53, v0 +; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[42:43] +; VI-NEXT: v_mov_b32_e32 v52, v32 +; VI-NEXT: v_lshrrev_b64 v[32:33], 16, v[50:51] +; VI-NEXT: v_mov_b32_e32 v51, v0 +; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[44:45] +; VI-NEXT: v_mov_b32_e32 v50, v32 +; VI-NEXT: v_lshrrev_b64 v[32:33], 16, v[48:49] +; VI-NEXT: v_mov_b32_e32 v49, v0 +; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[16:17] +; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; VI-NEXT: v_mov_b32_e32 v48, v32 +; VI-NEXT: v_lshrrev_b64 v[32:33], 16, v[30:31] +; VI-NEXT: v_lshrrev_b64 v[30:31], 16, v[46:47] +; VI-NEXT: v_mov_b32_e32 v31, v32 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshrrev_b64 v[40:41], 16, v[15:16] +; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[15:16] +; VI-NEXT: .LBB105_3: ; %end +; VI-NEXT: v_mov_b32_e32 v13, v18 +; VI-NEXT: v_mov_b32_e32 v18, v40 +; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; VI-NEXT: v_mov_b32_e32 v1, v39 +; VI-NEXT: v_mov_b32_e32 v3, v38 +; VI-NEXT: v_mov_b32_e32 v5, v37 +; VI-NEXT: v_mov_b32_e32 v7, v36 +; VI-NEXT: v_mov_b32_e32 v9, v35 +; VI-NEXT: v_mov_b32_e32 v11, v34 +; VI-NEXT: v_mov_b32_e32 v15, v55 +; VI-NEXT: v_mov_b32_e32 v17, v54 +; VI-NEXT: v_mov_b32_e32 v19, v53 +; VI-NEXT: v_mov_b32_e32 v21, v52 +; VI-NEXT: v_mov_b32_e32 v23, v51 +; VI-NEXT: v_mov_b32_e32 v25, v50 +; VI-NEXT: v_mov_b32_e32 v27, v49 +; VI-NEXT: v_mov_b32_e32 v29, v48 ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_setpc_b64 s[30:31] +; VI-NEXT: .LBB105_4: +; VI-NEXT: s_branch .LBB105_2 ; ; GFX9-LABEL: bitcast_v64bf16_to_v64i16_scalar: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 -; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill -; GFX9-NEXT: s_mov_b64 exec, s[4:5] -; GFX9-NEXT: v_writelane_b32 v43, s30, 0 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 -; GFX9-NEXT: v_writelane_b32 v43, s31, 1 +; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill +; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: v_mov_b32_e32 v31, v17 ; GFX9-NEXT: v_mov_b32_e32 v30, v16 ; GFX9-NEXT: v_mov_b32_e32 v29, v15 @@ -235602,626 +232310,637 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a ; GFX9-NEXT: v_mov_b32_e32 v32, v4 ; GFX9-NEXT: v_mov_b32_e32 v17, v3 ; GFX9-NEXT: v_mov_b32_e32 v16, v2 -; GFX9-NEXT: v_readfirstlane_b32 s30, v0 +; GFX9-NEXT: v_mov_b32_e32 v63, v1 +; GFX9-NEXT: v_mov_b32_e32 v14, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s16 +; GFX9-NEXT: v_mov_b32_e32 v1, s17 ; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec -; GFX9-NEXT: v_readfirstlane_b32 s31, v1 -; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill -; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 ; 4-byte Folded Spill -; GFX9-NEXT: s_cbranch_scc0 .LBB105_3 +; GFX9-NEXT: v_mov_b32_e32 v2, s18 +; GFX9-NEXT: v_mov_b32_e32 v3, s19 +; GFX9-NEXT: v_mov_b32_e32 v4, s20 +; GFX9-NEXT: v_mov_b32_e32 v5, s21 +; GFX9-NEXT: v_mov_b32_e32 v6, s22 +; GFX9-NEXT: v_mov_b32_e32 v7, s23 +; GFX9-NEXT: v_mov_b32_e32 v8, s24 +; GFX9-NEXT: v_mov_b32_e32 v9, s25 +; GFX9-NEXT: v_mov_b32_e32 v10, s26 +; GFX9-NEXT: v_mov_b32_e32 v11, s27 +; GFX9-NEXT: v_mov_b32_e32 v12, s28 +; GFX9-NEXT: v_mov_b32_e32 v13, s29 +; GFX9-NEXT: s_cbranch_scc0 .LBB105_4 ; GFX9-NEXT: ; %bb.1: ; %cmp.false -; GFX9-NEXT: s_cbranch_execnz .LBB105_4 +; GFX9-NEXT: s_cbranch_execnz .LBB105_3 ; GFX9-NEXT: .LBB105_2: ; %cmp.true -; GFX9-NEXT: v_mov_b32_e32 v0, 0x40c00000 -; GFX9-NEXT: s_and_b32 s4, s30, 0xffff0000 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s30, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: s_and_b32 s4, s31, 0xffff0000 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_add_f32_e32 v3, s4, v0 -; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v4, v4, v3 -; GFX9-NEXT: v_add_u32_e32 v4, 0x7fff, v4 -; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 -; GFX9-NEXT: s_lshl_b32 s4, s31, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc -; GFX9-NEXT: v_add_f32_e32 v4, s4, v0 -; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v5, v5, v4 -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: v_mov_b32_e32 v18, 0xffff0000 -; GFX9-NEXT: s_and_b32 s4, s29, 0xffff0000 -; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5 -; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 -; GFX9-NEXT: v_and_or_b32 v14, v1, v18, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_and_or_b32 v15, v3, v18, v4 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s29, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: s_and_b32 s4, s28, 0xffff0000 -; GFX9-NEXT: v_and_or_b32 v13, v1, v18, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s28, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: s_and_b32 s4, s27, 0xffff0000 -; GFX9-NEXT: v_and_or_b32 v12, v1, v18, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s27, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: s_and_b32 s4, s26, 0xffff0000 -; GFX9-NEXT: v_and_or_b32 v11, v1, v18, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s26, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: s_and_b32 s4, s25, 0xffff0000 -; GFX9-NEXT: v_and_or_b32 v10, v1, v18, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s25, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: s_and_b32 s4, s24, 0xffff0000 -; GFX9-NEXT: v_and_or_b32 v9, v1, v18, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s24, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: s_and_b32 s4, s23, 0xffff0000 -; GFX9-NEXT: v_and_or_b32 v8, v1, v18, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s23, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: s_and_b32 s4, s22, 0xffff0000 -; GFX9-NEXT: v_and_or_b32 v7, v1, v18, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s22, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: s_and_b32 s4, s21, 0xffff0000 -; GFX9-NEXT: v_and_or_b32 v6, v1, v18, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s21, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: s_and_b32 s4, s20, 0xffff0000 -; GFX9-NEXT: v_and_or_b32 v5, v1, v18, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s20, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: s_and_b32 s4, s19, 0xffff0000 -; GFX9-NEXT: v_and_or_b32 v4, v1, v18, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s19, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3 -; GFX9-NEXT: v_or_b32_e32 v33, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v33, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: s_and_b32 s4, s18, 0xffff0000 -; GFX9-NEXT: v_and_or_b32 v3, v1, v18, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v1 -; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2 -; GFX9-NEXT: v_or_b32_e32 v33, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s18, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v33, vcc -; GFX9-NEXT: v_add_f32_e32 v2, s4, v0 -; GFX9-NEXT: v_bfe_u32 v33, v2, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v33, v33, v2 +; GFX9-NEXT: v_and_b32_e32 v18, 0xffff0000, v16 +; GFX9-NEXT: v_add_f32_e32 v18, 0x40c00000, v18 +; GFX9-NEXT: v_bfe_u32 v33, v18, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v33, v33, v18 +; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16 ; GFX9-NEXT: v_add_u32_e32 v33, 0x7fff, v33 -; GFX9-NEXT: v_or_b32_e32 v34, 0x400000, v2 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v33, v34, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 -; GFX9-NEXT: s_and_b32 s4, s17, 0xffff0000 -; GFX9-NEXT: v_and_or_b32 v2, v1, v18, v2 -; GFX9-NEXT: v_add_f32_e32 v1, s4, v0 -; GFX9-NEXT: v_bfe_u32 v33, v1, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v33, v33, v1 +; GFX9-NEXT: v_or_b32_e32 v34, 0x400000, v18 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 +; GFX9-NEXT: v_cndmask_b32_e32 v15, v33, v34, vcc +; GFX9-NEXT: v_bfe_u32 v33, v16, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v33, v33, v16 ; GFX9-NEXT: v_add_u32_e32 v33, 0x7fff, v33 -; GFX9-NEXT: v_or_b32_e32 v34, 0x400000, v1 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 -; GFX9-NEXT: s_lshl_b32 s4, s17, 16 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v33, v34, vcc -; GFX9-NEXT: v_add_f32_e32 v33, s4, v0 -; GFX9-NEXT: v_bfe_u32 v34, v33, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v34, v34, v33 -; GFX9-NEXT: v_add_u32_e32 v34, 0x7fff, v34 -; GFX9-NEXT: v_or_b32_e32 v35, 0x400000, v33 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v33, v33 -; GFX9-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v33 -; GFX9-NEXT: s_and_b32 s4, s16, 0xffff0000 -; GFX9-NEXT: v_and_or_b32 v1, v1, v18, v33 -; GFX9-NEXT: v_add_f32_e32 v33, s4, v0 -; GFX9-NEXT: v_bfe_u32 v34, v33, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v34, v34, v33 -; GFX9-NEXT: s_lshl_b32 s4, s16, 16 -; GFX9-NEXT: v_add_u32_e32 v34, 0x7fff, v34 -; GFX9-NEXT: v_or_b32_e32 v35, 0x400000, v33 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v33, v33 -; GFX9-NEXT: v_add_f32_e32 v0, s4, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc -; GFX9-NEXT: v_bfe_u32 v34, v0, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v34, v34, v0 -; GFX9-NEXT: v_add_u32_e32 v34, 0x7fff, v34 -; GFX9-NEXT: v_or_b32_e32 v35, 0x400000, v0 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v34, v35, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 -; GFX9-NEXT: v_and_or_b32 v0, v33, v18, v0 -; GFX9-NEXT: v_and_b32_e32 v33, 0xffff0000, v16 +; GFX9-NEXT: v_or_b32_e32 v34, 0x400000, v16 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16 +; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-NEXT: v_cndmask_b32_e32 v15, v33, v34, vcc +; GFX9-NEXT: v_and_b32_e32 v33, 0xffff0000, v17 ; GFX9-NEXT: v_add_f32_e32 v33, 0x40c00000, v33 ; GFX9-NEXT: v_bfe_u32 v34, v33, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v34, v34, v33 -; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16 +; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17 ; GFX9-NEXT: v_add_u32_e32 v34, 0x7fff, v34 ; GFX9-NEXT: v_or_b32_e32 v35, 0x400000, v33 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v33, v33 -; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16 -; GFX9-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc -; GFX9-NEXT: v_bfe_u32 v34, v16, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v34, v34, v16 +; GFX9-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 +; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-NEXT: v_cndmask_b32_e32 v15, v34, v35, vcc +; GFX9-NEXT: v_bfe_u32 v34, v17, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v34, v34, v17 ; GFX9-NEXT: v_add_u32_e32 v34, 0x7fff, v34 -; GFX9-NEXT: v_or_b32_e32 v35, 0x400000, v16 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16 -; GFX9-NEXT: v_cndmask_b32_e32 v16, v34, v35, vcc -; GFX9-NEXT: v_and_b32_e32 v34, 0xffff0000, v17 +; GFX9-NEXT: v_or_b32_e32 v35, 0x400000, v17 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 +; GFX9-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc +; GFX9-NEXT: v_and_b32_e32 v34, 0xffff0000, v32 ; GFX9-NEXT: v_add_f32_e32 v34, 0x40c00000, v34 ; GFX9-NEXT: v_bfe_u32 v35, v34, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v35, v35, v34 -; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17 +; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v32 ; GFX9-NEXT: v_add_u32_e32 v35, 0x7fff, v35 ; GFX9-NEXT: v_or_b32_e32 v36, 0x400000, v34 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v34, v34 -; GFX9-NEXT: v_add_f32_e32 v17, 0x40c00000, v17 +; GFX9-NEXT: v_add_f32_e32 v32, 0x40c00000, v32 ; GFX9-NEXT: v_cndmask_b32_e32 v34, v35, v36, vcc -; GFX9-NEXT: v_bfe_u32 v35, v17, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v35, v35, v17 +; GFX9-NEXT: v_bfe_u32 v35, v32, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v35, v35, v32 ; GFX9-NEXT: v_add_u32_e32 v35, 0x7fff, v35 -; GFX9-NEXT: v_or_b32_e32 v36, 0x400000, v17 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 -; GFX9-NEXT: v_cndmask_b32_e32 v17, v35, v36, vcc -; GFX9-NEXT: v_and_b32_e32 v35, 0xffff0000, v32 +; GFX9-NEXT: v_or_b32_e32 v36, 0x400000, v32 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 +; GFX9-NEXT: v_cndmask_b32_e32 v32, v35, v36, vcc +; GFX9-NEXT: v_and_b32_e32 v35, 0xffff0000, v19 ; GFX9-NEXT: v_add_f32_e32 v35, 0x40c00000, v35 ; GFX9-NEXT: v_bfe_u32 v36, v35, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v36, v36, v35 -; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v32 +; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v19 ; GFX9-NEXT: v_add_u32_e32 v36, 0x7fff, v36 ; GFX9-NEXT: v_or_b32_e32 v37, 0x400000, v35 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v35, v35 -; GFX9-NEXT: v_add_f32_e32 v32, 0x40c00000, v32 +; GFX9-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 ; GFX9-NEXT: v_cndmask_b32_e32 v35, v36, v37, vcc -; GFX9-NEXT: v_bfe_u32 v36, v32, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v36, v36, v32 +; GFX9-NEXT: v_bfe_u32 v36, v19, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v36, v36, v19 ; GFX9-NEXT: v_add_u32_e32 v36, 0x7fff, v36 -; GFX9-NEXT: v_or_b32_e32 v37, 0x400000, v32 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v32, v32 -; GFX9-NEXT: v_cndmask_b32_e32 v32, v36, v37, vcc -; GFX9-NEXT: v_and_b32_e32 v36, 0xffff0000, v19 +; GFX9-NEXT: v_or_b32_e32 v37, 0x400000, v19 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 +; GFX9-NEXT: v_cndmask_b32_e32 v19, v36, v37, vcc +; GFX9-NEXT: v_and_b32_e32 v36, 0xffff0000, v20 ; GFX9-NEXT: v_add_f32_e32 v36, 0x40c00000, v36 ; GFX9-NEXT: v_bfe_u32 v37, v36, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v37, v37, v36 -; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v19 +; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v20 ; GFX9-NEXT: v_add_u32_e32 v37, 0x7fff, v37 ; GFX9-NEXT: v_or_b32_e32 v38, 0x400000, v36 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v36, v36 -; GFX9-NEXT: v_add_f32_e32 v19, 0x40c00000, v19 +; GFX9-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 ; GFX9-NEXT: v_cndmask_b32_e32 v36, v37, v38, vcc -; GFX9-NEXT: v_bfe_u32 v37, v19, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v37, v37, v19 +; GFX9-NEXT: v_bfe_u32 v37, v20, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v37, v37, v20 ; GFX9-NEXT: v_add_u32_e32 v37, 0x7fff, v37 -; GFX9-NEXT: v_or_b32_e32 v38, 0x400000, v19 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 -; GFX9-NEXT: v_cndmask_b32_e32 v19, v37, v38, vcc -; GFX9-NEXT: v_and_b32_e32 v37, 0xffff0000, v20 +; GFX9-NEXT: v_or_b32_e32 v38, 0x400000, v20 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 +; GFX9-NEXT: v_cndmask_b32_e32 v20, v37, v38, vcc +; GFX9-NEXT: v_and_b32_e32 v37, 0xffff0000, v21 ; GFX9-NEXT: v_add_f32_e32 v37, 0x40c00000, v37 ; GFX9-NEXT: v_bfe_u32 v38, v37, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v38, v38, v37 -; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v20 +; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v21 ; GFX9-NEXT: v_add_u32_e32 v38, 0x7fff, v38 ; GFX9-NEXT: v_or_b32_e32 v39, 0x400000, v37 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v37, v37 -; GFX9-NEXT: v_add_f32_e32 v20, 0x40c00000, v20 +; GFX9-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 ; GFX9-NEXT: v_cndmask_b32_e32 v37, v38, v39, vcc -; GFX9-NEXT: v_bfe_u32 v38, v20, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v38, v38, v20 +; GFX9-NEXT: v_bfe_u32 v38, v21, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v38, v38, v21 ; GFX9-NEXT: v_add_u32_e32 v38, 0x7fff, v38 -; GFX9-NEXT: v_or_b32_e32 v39, 0x400000, v20 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 -; GFX9-NEXT: v_cndmask_b32_e32 v20, v38, v39, vcc -; GFX9-NEXT: v_and_b32_e32 v38, 0xffff0000, v21 +; GFX9-NEXT: v_or_b32_e32 v39, 0x400000, v21 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 +; GFX9-NEXT: v_cndmask_b32_e32 v21, v38, v39, vcc +; GFX9-NEXT: v_and_b32_e32 v38, 0xffff0000, v22 ; GFX9-NEXT: v_add_f32_e32 v38, 0x40c00000, v38 ; GFX9-NEXT: v_bfe_u32 v39, v38, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v39, v39, v38 -; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v21 +; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v22 ; GFX9-NEXT: v_add_u32_e32 v39, 0x7fff, v39 ; GFX9-NEXT: v_or_b32_e32 v48, 0x400000, v38 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v38, v38 -; GFX9-NEXT: v_add_f32_e32 v21, 0x40c00000, v21 +; GFX9-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 ; GFX9-NEXT: v_cndmask_b32_e32 v38, v39, v48, vcc -; GFX9-NEXT: v_bfe_u32 v39, v21, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v39, v39, v21 +; GFX9-NEXT: v_bfe_u32 v39, v22, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v39, v39, v22 ; GFX9-NEXT: v_add_u32_e32 v39, 0x7fff, v39 -; GFX9-NEXT: v_or_b32_e32 v48, 0x400000, v21 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 -; GFX9-NEXT: v_cndmask_b32_e32 v21, v39, v48, vcc -; GFX9-NEXT: v_and_b32_e32 v39, 0xffff0000, v22 +; GFX9-NEXT: v_or_b32_e32 v48, 0x400000, v22 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 +; GFX9-NEXT: v_cndmask_b32_e32 v22, v39, v48, vcc +; GFX9-NEXT: v_and_b32_e32 v39, 0xffff0000, v23 ; GFX9-NEXT: v_add_f32_e32 v39, 0x40c00000, v39 ; GFX9-NEXT: v_bfe_u32 v48, v39, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v48, v48, v39 -; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v22 +; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v23 ; GFX9-NEXT: v_add_u32_e32 v48, 0x7fff, v48 ; GFX9-NEXT: v_or_b32_e32 v49, 0x400000, v39 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v39, v39 -; GFX9-NEXT: v_add_f32_e32 v22, 0x40c00000, v22 +; GFX9-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 ; GFX9-NEXT: v_cndmask_b32_e32 v39, v48, v49, vcc -; GFX9-NEXT: v_bfe_u32 v48, v22, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v48, v48, v22 +; GFX9-NEXT: v_bfe_u32 v48, v23, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v48, v48, v23 ; GFX9-NEXT: v_add_u32_e32 v48, 0x7fff, v48 -; GFX9-NEXT: v_or_b32_e32 v49, 0x400000, v22 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 -; GFX9-NEXT: v_cndmask_b32_e32 v22, v48, v49, vcc -; GFX9-NEXT: v_and_b32_e32 v48, 0xffff0000, v23 +; GFX9-NEXT: v_or_b32_e32 v49, 0x400000, v23 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 +; GFX9-NEXT: v_cndmask_b32_e32 v23, v48, v49, vcc +; GFX9-NEXT: v_and_b32_e32 v48, 0xffff0000, v24 ; GFX9-NEXT: v_add_f32_e32 v48, 0x40c00000, v48 ; GFX9-NEXT: v_bfe_u32 v49, v48, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v49, v49, v48 -; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v23 +; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24 ; GFX9-NEXT: v_add_u32_e32 v49, 0x7fff, v49 ; GFX9-NEXT: v_or_b32_e32 v50, 0x400000, v48 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v48, v48 -; GFX9-NEXT: v_add_f32_e32 v23, 0x40c00000, v23 +; GFX9-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 ; GFX9-NEXT: v_cndmask_b32_e32 v48, v49, v50, vcc -; GFX9-NEXT: v_bfe_u32 v49, v23, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v49, v49, v23 +; GFX9-NEXT: v_bfe_u32 v49, v24, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v49, v49, v24 ; GFX9-NEXT: v_add_u32_e32 v49, 0x7fff, v49 -; GFX9-NEXT: v_or_b32_e32 v50, 0x400000, v23 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 -; GFX9-NEXT: v_cndmask_b32_e32 v23, v49, v50, vcc -; GFX9-NEXT: v_and_b32_e32 v49, 0xffff0000, v24 +; GFX9-NEXT: v_or_b32_e32 v50, 0x400000, v24 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 +; GFX9-NEXT: v_cndmask_b32_e32 v24, v49, v50, vcc +; GFX9-NEXT: v_and_b32_e32 v49, 0xffff0000, v25 ; GFX9-NEXT: v_add_f32_e32 v49, 0x40c00000, v49 ; GFX9-NEXT: v_bfe_u32 v50, v49, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v50, v50, v49 -; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24 +; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25 ; GFX9-NEXT: v_add_u32_e32 v50, 0x7fff, v50 ; GFX9-NEXT: v_or_b32_e32 v51, 0x400000, v49 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v49, v49 -; GFX9-NEXT: v_add_f32_e32 v24, 0x40c00000, v24 +; GFX9-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 ; GFX9-NEXT: v_cndmask_b32_e32 v49, v50, v51, vcc -; GFX9-NEXT: v_bfe_u32 v50, v24, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v50, v50, v24 +; GFX9-NEXT: v_bfe_u32 v50, v25, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v50, v50, v25 ; GFX9-NEXT: v_add_u32_e32 v50, 0x7fff, v50 -; GFX9-NEXT: v_or_b32_e32 v51, 0x400000, v24 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 -; GFX9-NEXT: v_cndmask_b32_e32 v24, v50, v51, vcc -; GFX9-NEXT: v_and_b32_e32 v50, 0xffff0000, v25 +; GFX9-NEXT: v_or_b32_e32 v51, 0x400000, v25 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 +; GFX9-NEXT: v_cndmask_b32_e32 v25, v50, v51, vcc +; GFX9-NEXT: v_and_b32_e32 v50, 0xffff0000, v26 ; GFX9-NEXT: v_add_f32_e32 v50, 0x40c00000, v50 ; GFX9-NEXT: v_bfe_u32 v51, v50, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v51, v51, v50 -; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25 +; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26 ; GFX9-NEXT: v_add_u32_e32 v51, 0x7fff, v51 ; GFX9-NEXT: v_or_b32_e32 v52, 0x400000, v50 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v50, v50 -; GFX9-NEXT: v_add_f32_e32 v25, 0x40c00000, v25 +; GFX9-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 ; GFX9-NEXT: v_cndmask_b32_e32 v50, v51, v52, vcc -; GFX9-NEXT: v_bfe_u32 v51, v25, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v51, v51, v25 +; GFX9-NEXT: v_bfe_u32 v51, v26, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v51, v51, v26 ; GFX9-NEXT: v_add_u32_e32 v51, 0x7fff, v51 -; GFX9-NEXT: v_or_b32_e32 v52, 0x400000, v25 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 -; GFX9-NEXT: v_cndmask_b32_e32 v25, v51, v52, vcc -; GFX9-NEXT: v_and_b32_e32 v51, 0xffff0000, v26 +; GFX9-NEXT: v_or_b32_e32 v52, 0x400000, v26 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 +; GFX9-NEXT: v_cndmask_b32_e32 v26, v51, v52, vcc +; GFX9-NEXT: v_and_b32_e32 v51, 0xffff0000, v27 ; GFX9-NEXT: v_add_f32_e32 v51, 0x40c00000, v51 ; GFX9-NEXT: v_bfe_u32 v52, v51, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v52, v52, v51 -; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26 +; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27 ; GFX9-NEXT: v_add_u32_e32 v52, 0x7fff, v52 ; GFX9-NEXT: v_or_b32_e32 v53, 0x400000, v51 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v51, v51 -; GFX9-NEXT: v_add_f32_e32 v26, 0x40c00000, v26 +; GFX9-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 ; GFX9-NEXT: v_cndmask_b32_e32 v51, v52, v53, vcc -; GFX9-NEXT: v_bfe_u32 v52, v26, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v52, v52, v26 +; GFX9-NEXT: v_bfe_u32 v52, v27, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v52, v52, v27 ; GFX9-NEXT: v_add_u32_e32 v52, 0x7fff, v52 -; GFX9-NEXT: v_or_b32_e32 v53, 0x400000, v26 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 -; GFX9-NEXT: v_cndmask_b32_e32 v26, v52, v53, vcc -; GFX9-NEXT: v_and_b32_e32 v52, 0xffff0000, v27 +; GFX9-NEXT: v_or_b32_e32 v53, 0x400000, v27 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 +; GFX9-NEXT: v_cndmask_b32_e32 v27, v52, v53, vcc +; GFX9-NEXT: v_and_b32_e32 v52, 0xffff0000, v28 ; GFX9-NEXT: v_add_f32_e32 v52, 0x40c00000, v52 ; GFX9-NEXT: v_bfe_u32 v53, v52, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v53, v53, v52 -; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27 +; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v28 ; GFX9-NEXT: v_add_u32_e32 v53, 0x7fff, v53 ; GFX9-NEXT: v_or_b32_e32 v54, 0x400000, v52 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v52, v52 -; GFX9-NEXT: v_add_f32_e32 v27, 0x40c00000, v27 +; GFX9-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 ; GFX9-NEXT: v_cndmask_b32_e32 v52, v53, v54, vcc -; GFX9-NEXT: v_bfe_u32 v53, v27, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v53, v53, v27 +; GFX9-NEXT: v_bfe_u32 v53, v28, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v53, v53, v28 ; GFX9-NEXT: v_add_u32_e32 v53, 0x7fff, v53 -; GFX9-NEXT: v_or_b32_e32 v54, 0x400000, v27 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 -; GFX9-NEXT: v_cndmask_b32_e32 v27, v53, v54, vcc -; GFX9-NEXT: v_and_b32_e32 v53, 0xffff0000, v28 +; GFX9-NEXT: v_or_b32_e32 v54, 0x400000, v28 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 +; GFX9-NEXT: v_cndmask_b32_e32 v28, v53, v54, vcc +; GFX9-NEXT: v_and_b32_e32 v53, 0xffff0000, v29 ; GFX9-NEXT: v_add_f32_e32 v53, 0x40c00000, v53 ; GFX9-NEXT: v_bfe_u32 v54, v53, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v54, v54, v53 -; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v28 +; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29 ; GFX9-NEXT: v_add_u32_e32 v54, 0x7fff, v54 ; GFX9-NEXT: v_or_b32_e32 v55, 0x400000, v53 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v53, v53 -; GFX9-NEXT: v_add_f32_e32 v28, 0x40c00000, v28 +; GFX9-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 ; GFX9-NEXT: v_cndmask_b32_e32 v53, v54, v55, vcc -; GFX9-NEXT: v_bfe_u32 v54, v28, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v54, v54, v28 +; GFX9-NEXT: v_bfe_u32 v54, v29, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v54, v54, v29 ; GFX9-NEXT: v_add_u32_e32 v54, 0x7fff, v54 -; GFX9-NEXT: v_or_b32_e32 v55, 0x400000, v28 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 -; GFX9-NEXT: v_cndmask_b32_e32 v28, v54, v55, vcc -; GFX9-NEXT: v_and_b32_e32 v54, 0xffff0000, v29 +; GFX9-NEXT: v_or_b32_e32 v55, 0x400000, v29 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 +; GFX9-NEXT: v_cndmask_b32_e32 v29, v54, v55, vcc +; GFX9-NEXT: v_and_b32_e32 v54, 0xffff0000, v30 ; GFX9-NEXT: v_add_f32_e32 v54, 0x40c00000, v54 ; GFX9-NEXT: v_bfe_u32 v55, v54, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v55, v55, v54 -; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29 +; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v30 ; GFX9-NEXT: v_add_u32_e32 v55, 0x7fff, v55 ; GFX9-NEXT: v_or_b32_e32 v40, 0x400000, v54 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v54, v54 -; GFX9-NEXT: v_add_f32_e32 v29, 0x40c00000, v29 +; GFX9-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 ; GFX9-NEXT: v_cndmask_b32_e32 v54, v55, v40, vcc -; GFX9-NEXT: v_bfe_u32 v55, v29, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v55, v55, v29 +; GFX9-NEXT: v_bfe_u32 v55, v30, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v55, v55, v30 ; GFX9-NEXT: v_add_u32_e32 v55, 0x7fff, v55 -; GFX9-NEXT: v_or_b32_e32 v40, 0x400000, v29 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 -; GFX9-NEXT: v_cndmask_b32_e32 v29, v55, v40, vcc -; GFX9-NEXT: v_and_b32_e32 v55, 0xffff0000, v30 +; GFX9-NEXT: v_or_b32_e32 v40, 0x400000, v30 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 +; GFX9-NEXT: v_cndmask_b32_e32 v30, v55, v40, vcc +; GFX9-NEXT: v_and_b32_e32 v55, 0xffff0000, v31 ; GFX9-NEXT: v_add_f32_e32 v55, 0x40c00000, v55 ; GFX9-NEXT: v_bfe_u32 v40, v55, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v40, v40, v55 -; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v30 +; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31 ; GFX9-NEXT: v_add_u32_e32 v40, 0x7fff, v40 ; GFX9-NEXT: v_or_b32_e32 v41, 0x400000, v55 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v55, v55 -; GFX9-NEXT: v_add_f32_e32 v30, 0x40c00000, v30 +; GFX9-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 ; GFX9-NEXT: v_cndmask_b32_e32 v55, v40, v41, vcc -; GFX9-NEXT: v_bfe_u32 v40, v30, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v40, v40, v30 +; GFX9-NEXT: v_bfe_u32 v40, v31, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v40, v40, v31 ; GFX9-NEXT: v_add_u32_e32 v40, 0x7fff, v40 -; GFX9-NEXT: v_or_b32_e32 v41, 0x400000, v30 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 -; GFX9-NEXT: v_cndmask_b32_e32 v30, v40, v41, vcc -; GFX9-NEXT: v_and_b32_e32 v40, 0xffff0000, v31 +; GFX9-NEXT: v_or_b32_e32 v41, 0x400000, v31 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v31, v31 +; GFX9-NEXT: v_cndmask_b32_e32 v31, v40, v41, vcc +; GFX9-NEXT: v_and_b32_e32 v40, 0xffff0000, v0 ; GFX9-NEXT: v_add_f32_e32 v40, 0x40c00000, v40 ; GFX9-NEXT: v_bfe_u32 v41, v40, 16, 1 ; GFX9-NEXT: v_add_u32_e32 v41, v41, v40 -; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31 +; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX9-NEXT: v_add_u32_e32 v41, 0x7fff, v41 ; GFX9-NEXT: v_or_b32_e32 v42, 0x400000, v40 ; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v40, v40 -; GFX9-NEXT: v_add_f32_e32 v31, 0x40c00000, v31 +; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0 ; GFX9-NEXT: v_cndmask_b32_e32 v40, v41, v42, vcc -; GFX9-NEXT: v_bfe_u32 v41, v31, 16, 1 -; GFX9-NEXT: v_add_u32_e32 v41, v41, v31 +; GFX9-NEXT: v_bfe_u32 v41, v0, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v41, v41, v0 ; GFX9-NEXT: v_add_u32_e32 v41, 0x7fff, v41 -; GFX9-NEXT: v_or_b32_e32 v42, 0x400000, v31 -; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v31, v31 -; GFX9-NEXT: v_cndmask_b32_e32 v31, v41, v42, vcc -; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v31 -; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v30 -; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v29 -; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v28 -; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v27 -; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v26 -; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v25 -; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v24 -; GFX9-NEXT: v_lshrrev_b32_e32 v23, 16, v23 -; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v22 -; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v21 -; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v20 -; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v19 -; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v32 -; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v17 -; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v16 -; GFX9-NEXT: v_and_or_b32 v31, v40, v18, v31 -; GFX9-NEXT: v_and_or_b32 v30, v55, v18, v30 -; GFX9-NEXT: v_and_or_b32 v29, v54, v18, v29 -; GFX9-NEXT: v_and_or_b32 v28, v53, v18, v28 -; GFX9-NEXT: v_and_or_b32 v27, v52, v18, v27 -; GFX9-NEXT: v_and_or_b32 v26, v51, v18, v26 -; GFX9-NEXT: v_and_or_b32 v25, v50, v18, v25 -; GFX9-NEXT: v_and_or_b32 v24, v49, v18, v24 -; GFX9-NEXT: v_and_or_b32 v23, v48, v18, v23 -; GFX9-NEXT: v_and_or_b32 v22, v39, v18, v22 -; GFX9-NEXT: v_and_or_b32 v21, v38, v18, v21 -; GFX9-NEXT: v_and_or_b32 v20, v37, v18, v20 -; GFX9-NEXT: v_and_or_b32 v19, v36, v18, v19 -; GFX9-NEXT: v_and_or_b32 v32, v35, v18, v32 -; GFX9-NEXT: v_and_or_b32 v17, v34, v18, v17 -; GFX9-NEXT: v_and_or_b32 v16, v33, v18, v16 -; GFX9-NEXT: s_branch .LBB105_5 -; GFX9-NEXT: .LBB105_3: -; GFX9-NEXT: s_branch .LBB105_2 -; GFX9-NEXT: .LBB105_4: -; GFX9-NEXT: v_mov_b32_e32 v0, s16 -; GFX9-NEXT: v_mov_b32_e32 v1, s17 -; GFX9-NEXT: v_mov_b32_e32 v2, s18 -; GFX9-NEXT: v_mov_b32_e32 v3, s19 -; GFX9-NEXT: v_mov_b32_e32 v4, s20 -; GFX9-NEXT: v_mov_b32_e32 v5, s21 -; GFX9-NEXT: v_mov_b32_e32 v6, s22 -; GFX9-NEXT: v_mov_b32_e32 v7, s23 -; GFX9-NEXT: v_mov_b32_e32 v8, s24 -; GFX9-NEXT: v_mov_b32_e32 v9, s25 -; GFX9-NEXT: v_mov_b32_e32 v10, s26 -; GFX9-NEXT: v_mov_b32_e32 v11, s27 -; GFX9-NEXT: v_mov_b32_e32 v12, s28 -; GFX9-NEXT: v_mov_b32_e32 v13, s29 -; GFX9-NEXT: v_mov_b32_e32 v14, s30 -; GFX9-NEXT: v_mov_b32_e32 v15, s31 -; GFX9-NEXT: .LBB105_5: ; %end -; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload -; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; GFX9-NEXT: v_or_b32_e32 v42, 0x400000, v0 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; GFX9-NEXT: v_cndmask_b32_e32 v18, v41, v42, vcc +; GFX9-NEXT: v_and_b32_e32 v41, 0xffff0000, v1 +; GFX9-NEXT: v_add_f32_e32 v41, 0x40c00000, v41 +; GFX9-NEXT: v_bfe_u32 v42, v41, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v42, v42, v41 +; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX9-NEXT: v_add_u32_e32 v42, 0x7fff, v42 +; GFX9-NEXT: v_or_b32_e32 v43, 0x400000, v41 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v41, v41 +; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v41, v42, v43, vcc +; GFX9-NEXT: v_bfe_u32 v42, v1, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v42, v42, v1 +; GFX9-NEXT: v_add_u32_e32 v42, 0x7fff, v42 +; GFX9-NEXT: v_or_b32_e32 v43, 0x400000, v1 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v17, v42, v43, vcc +; GFX9-NEXT: v_and_b32_e32 v42, 0xffff0000, v2 +; GFX9-NEXT: v_add_f32_e32 v42, 0x40c00000, v42 +; GFX9-NEXT: v_bfe_u32 v43, v42, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v43, v43, v42 +; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX9-NEXT: v_add_u32_e32 v43, 0x7fff, v43 +; GFX9-NEXT: v_or_b32_e32 v44, 0x400000, v42 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v42, v42 +; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v42, v43, v44, vcc +; GFX9-NEXT: v_bfe_u32 v43, v2, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v43, v43, v2 +; GFX9-NEXT: v_add_u32_e32 v43, 0x7fff, v43 +; GFX9-NEXT: v_or_b32_e32 v44, 0x400000, v2 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v16, v43, v44, vcc +; GFX9-NEXT: v_and_b32_e32 v43, 0xffff0000, v3 +; GFX9-NEXT: v_add_f32_e32 v43, 0x40c00000, v43 +; GFX9-NEXT: v_bfe_u32 v44, v43, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v44, v44, v43 +; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GFX9-NEXT: v_add_u32_e32 v44, 0x7fff, v44 +; GFX9-NEXT: v_or_b32_e32 v45, 0x400000, v43 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v43, v43 +; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v43, v44, v45, vcc +; GFX9-NEXT: v_bfe_u32 v44, v3, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v44, v44, v3 +; GFX9-NEXT: v_add_u32_e32 v44, 0x7fff, v44 +; GFX9-NEXT: v_or_b32_e32 v45, 0x400000, v3 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v3, v44, v45, vcc +; GFX9-NEXT: v_and_b32_e32 v44, 0xffff0000, v4 +; GFX9-NEXT: v_add_f32_e32 v44, 0x40c00000, v44 +; GFX9-NEXT: v_bfe_u32 v45, v44, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v45, v45, v44 +; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX9-NEXT: v_add_u32_e32 v45, 0x7fff, v45 +; GFX9-NEXT: v_or_b32_e32 v46, 0x400000, v44 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v44, v44 +; GFX9-NEXT: v_add_f32_e32 v4, 0x40c00000, v4 +; GFX9-NEXT: v_cndmask_b32_e32 v44, v45, v46, vcc +; GFX9-NEXT: v_bfe_u32 v45, v4, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v45, v45, v4 +; GFX9-NEXT: v_add_u32_e32 v45, 0x7fff, v45 +; GFX9-NEXT: v_or_b32_e32 v46, 0x400000, v4 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 +; GFX9-NEXT: v_cndmask_b32_e32 v4, v45, v46, vcc +; GFX9-NEXT: v_and_b32_e32 v45, 0xffff0000, v5 +; GFX9-NEXT: v_add_f32_e32 v45, 0x40c00000, v45 +; GFX9-NEXT: v_bfe_u32 v46, v45, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v46, v46, v45 +; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5 +; GFX9-NEXT: v_add_u32_e32 v46, 0x7fff, v46 +; GFX9-NEXT: v_or_b32_e32 v47, 0x400000, v45 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v45, v45 +; GFX9-NEXT: v_add_f32_e32 v5, 0x40c00000, v5 +; GFX9-NEXT: v_cndmask_b32_e32 v45, v46, v47, vcc +; GFX9-NEXT: v_bfe_u32 v46, v5, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v46, v46, v5 +; GFX9-NEXT: v_add_u32_e32 v46, 0x7fff, v46 +; GFX9-NEXT: v_or_b32_e32 v47, 0x400000, v5 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 +; GFX9-NEXT: v_cndmask_b32_e32 v5, v46, v47, vcc +; GFX9-NEXT: v_and_b32_e32 v46, 0xffff0000, v6 +; GFX9-NEXT: v_add_f32_e32 v46, 0x40c00000, v46 +; GFX9-NEXT: v_bfe_u32 v47, v46, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v47, v47, v46 +; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6 +; GFX9-NEXT: v_add_u32_e32 v47, 0x7fff, v47 +; GFX9-NEXT: v_or_b32_e32 v56, 0x400000, v46 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v46, v46 +; GFX9-NEXT: v_add_f32_e32 v6, 0x40c00000, v6 +; GFX9-NEXT: v_cndmask_b32_e32 v46, v47, v56, vcc +; GFX9-NEXT: v_bfe_u32 v47, v6, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v47, v47, v6 +; GFX9-NEXT: v_add_u32_e32 v47, 0x7fff, v47 +; GFX9-NEXT: v_or_b32_e32 v56, 0x400000, v6 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 +; GFX9-NEXT: v_cndmask_b32_e32 v6, v47, v56, vcc +; GFX9-NEXT: v_and_b32_e32 v47, 0xffff0000, v7 +; GFX9-NEXT: v_add_f32_e32 v47, 0x40c00000, v47 +; GFX9-NEXT: v_bfe_u32 v56, v47, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v56, v56, v47 +; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GFX9-NEXT: v_add_u32_e32 v56, 0x7fff, v56 +; GFX9-NEXT: v_or_b32_e32 v57, 0x400000, v47 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v47, v47 +; GFX9-NEXT: v_add_f32_e32 v7, 0x40c00000, v7 +; GFX9-NEXT: v_cndmask_b32_e32 v47, v56, v57, vcc +; GFX9-NEXT: v_bfe_u32 v56, v7, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v56, v56, v7 +; GFX9-NEXT: v_add_u32_e32 v56, 0x7fff, v56 +; GFX9-NEXT: v_or_b32_e32 v57, 0x400000, v7 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 +; GFX9-NEXT: v_cndmask_b32_e32 v7, v56, v57, vcc +; GFX9-NEXT: v_and_b32_e32 v56, 0xffff0000, v8 +; GFX9-NEXT: v_add_f32_e32 v56, 0x40c00000, v56 +; GFX9-NEXT: v_bfe_u32 v57, v56, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v57, v57, v56 +; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8 +; GFX9-NEXT: v_add_u32_e32 v57, 0x7fff, v57 +; GFX9-NEXT: v_or_b32_e32 v58, 0x400000, v56 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v56, v56 +; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8 +; GFX9-NEXT: v_cndmask_b32_e32 v56, v57, v58, vcc +; GFX9-NEXT: v_bfe_u32 v57, v8, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v57, v57, v8 +; GFX9-NEXT: v_add_u32_e32 v57, 0x7fff, v57 +; GFX9-NEXT: v_or_b32_e32 v58, 0x400000, v8 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8 +; GFX9-NEXT: v_cndmask_b32_e32 v8, v57, v58, vcc +; GFX9-NEXT: v_and_b32_e32 v57, 0xffff0000, v9 +; GFX9-NEXT: v_add_f32_e32 v57, 0x40c00000, v57 +; GFX9-NEXT: v_bfe_u32 v58, v57, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v58, v58, v57 +; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9 +; GFX9-NEXT: v_add_u32_e32 v58, 0x7fff, v58 +; GFX9-NEXT: v_or_b32_e32 v59, 0x400000, v57 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v57, v57 +; GFX9-NEXT: v_add_f32_e32 v9, 0x40c00000, v9 +; GFX9-NEXT: v_cndmask_b32_e32 v57, v58, v59, vcc +; GFX9-NEXT: v_bfe_u32 v58, v9, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v58, v58, v9 +; GFX9-NEXT: v_add_u32_e32 v58, 0x7fff, v58 +; GFX9-NEXT: v_or_b32_e32 v59, 0x400000, v9 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 +; GFX9-NEXT: v_cndmask_b32_e32 v9, v58, v59, vcc +; GFX9-NEXT: v_and_b32_e32 v58, 0xffff0000, v10 +; GFX9-NEXT: v_add_f32_e32 v58, 0x40c00000, v58 +; GFX9-NEXT: v_bfe_u32 v59, v58, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v59, v59, v58 +; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10 +; GFX9-NEXT: v_add_u32_e32 v59, 0x7fff, v59 +; GFX9-NEXT: v_or_b32_e32 v60, 0x400000, v58 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v58, v58 +; GFX9-NEXT: v_add_f32_e32 v10, 0x40c00000, v10 +; GFX9-NEXT: v_cndmask_b32_e32 v58, v59, v60, vcc +; GFX9-NEXT: v_bfe_u32 v59, v10, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v59, v59, v10 +; GFX9-NEXT: v_add_u32_e32 v59, 0x7fff, v59 +; GFX9-NEXT: v_or_b32_e32 v60, 0x400000, v10 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 +; GFX9-NEXT: v_cndmask_b32_e32 v10, v59, v60, vcc +; GFX9-NEXT: v_and_b32_e32 v59, 0xffff0000, v11 +; GFX9-NEXT: v_add_f32_e32 v59, 0x40c00000, v59 +; GFX9-NEXT: v_bfe_u32 v60, v59, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v60, v60, v59 +; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11 +; GFX9-NEXT: v_add_u32_e32 v60, 0x7fff, v60 +; GFX9-NEXT: v_or_b32_e32 v61, 0x400000, v59 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v59, v59 +; GFX9-NEXT: v_add_f32_e32 v11, 0x40c00000, v11 +; GFX9-NEXT: v_cndmask_b32_e32 v59, v60, v61, vcc +; GFX9-NEXT: v_bfe_u32 v60, v11, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v60, v60, v11 +; GFX9-NEXT: v_add_u32_e32 v60, 0x7fff, v60 +; GFX9-NEXT: v_or_b32_e32 v61, 0x400000, v11 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 +; GFX9-NEXT: v_cndmask_b32_e32 v11, v60, v61, vcc +; GFX9-NEXT: v_and_b32_e32 v60, 0xffff0000, v12 +; GFX9-NEXT: v_add_f32_e32 v60, 0x40c00000, v60 +; GFX9-NEXT: v_bfe_u32 v61, v60, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v61, v61, v60 +; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12 +; GFX9-NEXT: v_add_u32_e32 v61, 0x7fff, v61 +; GFX9-NEXT: v_or_b32_e32 v62, 0x400000, v60 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v60, v60 +; GFX9-NEXT: v_add_f32_e32 v12, 0x40c00000, v12 +; GFX9-NEXT: v_cndmask_b32_e32 v60, v61, v62, vcc +; GFX9-NEXT: v_bfe_u32 v61, v12, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v61, v61, v12 +; GFX9-NEXT: v_add_u32_e32 v61, 0x7fff, v61 +; GFX9-NEXT: v_or_b32_e32 v62, 0x400000, v12 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 +; GFX9-NEXT: v_cndmask_b32_e32 v12, v61, v62, vcc +; GFX9-NEXT: v_and_b32_e32 v61, 0xffff0000, v13 +; GFX9-NEXT: v_add_f32_e32 v61, 0x40c00000, v61 +; GFX9-NEXT: v_bfe_u32 v62, v61, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v62, v62, v61 +; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13 +; GFX9-NEXT: v_add_u32_e32 v62, 0x7fff, v62 +; GFX9-NEXT: v_mov_b32_e32 v1, v63 +; GFX9-NEXT: v_or_b32_e32 v63, 0x400000, v61 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v61, v61 +; GFX9-NEXT: v_add_f32_e32 v13, 0x40c00000, v13 +; GFX9-NEXT: v_cndmask_b32_e32 v61, v62, v63, vcc +; GFX9-NEXT: v_bfe_u32 v62, v13, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v62, v62, v13 +; GFX9-NEXT: v_add_u32_e32 v62, 0x7fff, v62 +; GFX9-NEXT: v_or_b32_e32 v63, 0x400000, v13 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 +; GFX9-NEXT: v_cndmask_b32_e32 v13, v62, v63, vcc +; GFX9-NEXT: v_and_b32_e32 v62, 0xffff0000, v14 +; GFX9-NEXT: v_add_f32_e32 v62, 0x40c00000, v62 +; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14 +; GFX9-NEXT: v_bfe_u32 v63, v62, 16, 1 +; GFX9-NEXT: v_add_f32_e32 v14, 0x40c00000, v14 +; GFX9-NEXT: v_add_u32_e32 v63, v63, v62 +; GFX9-NEXT: v_or_b32_e32 v0, 0x400000, v62 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v62, v62 +; GFX9-NEXT: v_bfe_u32 v62, v14, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v63, 0x7fff, v63 +; GFX9-NEXT: v_add_u32_e32 v62, v62, v14 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v63, v0, vcc +; GFX9-NEXT: v_add_u32_e32 v62, 0x7fff, v62 +; GFX9-NEXT: v_or_b32_e32 v63, 0x400000, v14 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 +; GFX9-NEXT: v_cndmask_b32_e32 v14, v62, v63, vcc +; GFX9-NEXT: v_and_b32_e32 v62, 0xffff0000, v1 +; GFX9-NEXT: v_add_f32_e32 v62, 0x40c00000, v62 +; GFX9-NEXT: v_bfe_u32 v63, v62, 16, 1 +; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-NEXT: v_add_u32_e32 v63, v63, v62 +; GFX9-NEXT: v_or_b32_e32 v15, 0x400000, v62 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v62, v62 +; GFX9-NEXT: v_lshlrev_b32_e32 v62, 16, v1 +; GFX9-NEXT: v_add_u32_e32 v63, 0x7fff, v63 +; GFX9-NEXT: v_add_f32_e32 v62, 0x40c00000, v62 +; GFX9-NEXT: v_cndmask_b32_e32 v15, v63, v15, vcc +; GFX9-NEXT: v_bfe_u32 v63, v62, 16, 1 +; GFX9-NEXT: v_add_u32_e32 v63, v63, v62 +; GFX9-NEXT: v_add_u32_e32 v63, 0x7fff, v63 +; GFX9-NEXT: v_or_b32_e32 v0, 0x400000, v62 +; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v62, v62 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v63, v0, vcc +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0 +; GFX9-NEXT: v_mov_b32_e32 v62, 0xffff0000 +; GFX9-NEXT: v_and_or_b32 v63, v15, v62, v0 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v14 +; GFX9-NEXT: v_and_or_b32 v14, v2, v62, v0 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v13 +; GFX9-NEXT: v_and_or_b32 v13, v61, v62, v0 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v12 +; GFX9-NEXT: v_and_or_b32 v12, v60, v62, v0 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v11 +; GFX9-NEXT: v_and_or_b32 v11, v59, v62, v0 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v10 +; GFX9-NEXT: v_and_or_b32 v10, v58, v62, v0 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v9 +; GFX9-NEXT: v_and_or_b32 v9, v57, v62, v0 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v8 +; GFX9-NEXT: v_and_or_b32 v8, v56, v62, v0 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v7 +; GFX9-NEXT: v_and_or_b32 v7, v47, v62, v0 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v6 +; GFX9-NEXT: v_and_or_b32 v6, v46, v62, v0 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v5 +; GFX9-NEXT: v_and_or_b32 v5, v45, v62, v0 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v4 +; GFX9-NEXT: v_and_or_b32 v4, v44, v62, v0 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v3 +; GFX9-NEXT: v_and_or_b32 v3, v43, v62, v0 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v16 +; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v31 +; GFX9-NEXT: v_and_or_b32 v31, v55, v62, v15 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v30 +; GFX9-NEXT: v_and_or_b32 v30, v54, v62, v15 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v29 +; GFX9-NEXT: v_and_or_b32 v29, v53, v62, v15 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v28 +; GFX9-NEXT: v_and_or_b32 v28, v52, v62, v15 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v27 +; GFX9-NEXT: v_and_or_b32 v27, v51, v62, v15 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v26 +; GFX9-NEXT: v_and_or_b32 v26, v50, v62, v15 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v25 +; GFX9-NEXT: v_and_or_b32 v25, v49, v62, v15 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v24 +; GFX9-NEXT: v_and_or_b32 v24, v48, v62, v15 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v23 +; GFX9-NEXT: v_and_or_b32 v23, v39, v62, v15 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v22 +; GFX9-NEXT: v_and_or_b32 v22, v38, v62, v15 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v21 +; GFX9-NEXT: v_and_or_b32 v21, v37, v62, v15 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v20 +; GFX9-NEXT: v_and_or_b32 v20, v36, v62, v15 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v19 +; GFX9-NEXT: v_and_or_b32 v19, v35, v62, v15 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v32 +; GFX9-NEXT: v_and_or_b32 v32, v34, v62, v15 +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v33 +; GFX9-NEXT: v_and_or_b32 v2, v42, v62, v0 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v17 +; GFX9-NEXT: v_and_or_b32 v1, v41, v62, v0 +; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v18 +; GFX9-NEXT: v_and_or_b32 v0, v40, v62, v0 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_and_or_b32 v17, v16, v62, v15 +; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v15 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_and_or_b32 v16, v16, v62, v15 +; GFX9-NEXT: .LBB105_3: ; %end +; GFX9-NEXT: v_mov_b32_e32 v15, v63 +; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload ; GFX9-NEXT: v_mov_b32_e32 v18, v32 -; GFX9-NEXT: v_readlane_b32 s31, v43, 1 -; GFX9-NEXT: v_readlane_b32 s30, v43, 0 -; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 -; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload -; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] +; GFX9-NEXT: .LBB105_4: +; GFX9-NEXT: s_branch .LBB105_2 ; ; GFX11-TRUE16-LABEL: bitcast_v64bf16_to_v64i16_scalar: ; GFX11-TRUE16: ; %bb.0: @@ -236541,11 +233260,11 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a ; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v2 -; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v54, v0, v4 :: v_dual_add_nc_u32 v1, v1, v2 +; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v1, v2 +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v55, v0, v4, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0 ; GFX11-TRUE16-NEXT: s_and_b32 s0, s13, 0xffff0000 -; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v1 ; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v8, 16, 1 ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v6, v7, vcc_lo @@ -236573,7 +233292,7 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a ; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0 ; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v7 ; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s14, 16 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v55, v1, v6, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v1, v6, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v7 ; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0 @@ -236609,7 +233328,7 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6 ; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v11, 16, 1 ; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v10 -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v54.h +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v55.h ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v66.h ; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v4, v9 :: v_dual_add_nc_u32 v4, 0x7fff, v7 ; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0 @@ -236807,7 +233526,7 @@ define inreg <64 x i16> @bitcast_v64bf16_to_v64i16_scalar(<64 x bfloat> inreg %a ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v81, v100, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v99, v99 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v83.h -; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v55.h +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v54.h ; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v96, v101, vcc_lo ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v97.h ; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31] @@ -238611,54 +235330,54 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a ; SI-NEXT: v_writelane_b32 v40, s85, 29 ; SI-NEXT: v_writelane_b32 v40, s86, 30 ; SI-NEXT: v_writelane_b32 v40, s87, 31 +; SI-NEXT: s_mov_b32 s74, s23 +; SI-NEXT: s_mov_b32 s72, s21 +; SI-NEXT: s_mov_b32 s61, s18 ; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane ; SI-NEXT: s_mov_b32 s60, s16 ; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: v_writelane_b32 v41, s17, 0 -; SI-NEXT: s_mov_b32 s61, s19 ; SI-NEXT: v_writelane_b32 v41, s60, 1 -; SI-NEXT: s_mov_b32 s63, s18 -; SI-NEXT: v_writelane_b32 v41, s61, 2 -; SI-NEXT: s_mov_b32 s72, s21 -; SI-NEXT: v_writelane_b32 v41, s63, 3 +; SI-NEXT: v_writelane_b32 v41, s19, 2 +; SI-NEXT: v_writelane_b32 v41, s61, 3 ; SI-NEXT: v_writelane_b32 v41, s72, 4 -; SI-NEXT: s_mov_b32 s74, s23 ; SI-NEXT: v_writelane_b32 v41, s20, 5 ; SI-NEXT: v_writelane_b32 v41, s74, 6 -; SI-NEXT: s_mov_b32 s75, s25 +; SI-NEXT: s_mov_b32 s76, s25 ; SI-NEXT: v_writelane_b32 v41, s22, 7 -; SI-NEXT: v_writelane_b32 v41, s75, 8 -; SI-NEXT: s_mov_b32 s76, s27 +; SI-NEXT: v_writelane_b32 v41, s76, 8 +; SI-NEXT: s_mov_b32 s78, s27 ; SI-NEXT: v_writelane_b32 v41, s24, 9 -; SI-NEXT: v_writelane_b32 v41, s76, 10 -; SI-NEXT: s_mov_b32 s93, s29 +; SI-NEXT: v_writelane_b32 v41, s78, 10 +; SI-NEXT: s_mov_b32 s88, s29 ; SI-NEXT: v_writelane_b32 v41, s26, 11 -; SI-NEXT: v_writelane_b32 v41, s93, 12 -; SI-NEXT: v_readfirstlane_b32 s16, v2 +; SI-NEXT: v_writelane_b32 v41, s88, 12 +; SI-NEXT: v_readfirstlane_b32 s77, v2 ; SI-NEXT: v_writelane_b32 v41, s28, 13 -; SI-NEXT: v_readfirstlane_b32 s73, v4 -; SI-NEXT: v_writelane_b32 v41, s16, 14 -; SI-NEXT: v_readfirstlane_b32 s89, v3 -; SI-NEXT: v_writelane_b32 v41, s73, 15 -; SI-NEXT: v_readfirstlane_b32 s90, v6 -; SI-NEXT: v_writelane_b32 v41, s89, 16 -; SI-NEXT: v_readfirstlane_b32 s91, v5 -; SI-NEXT: v_writelane_b32 v41, s90, 17 -; SI-NEXT: v_readfirstlane_b32 s34, v8 -; SI-NEXT: v_writelane_b32 v41, s91, 18 -; SI-NEXT: v_readfirstlane_b32 s35, v7 -; SI-NEXT: v_writelane_b32 v41, s34, 19 -; SI-NEXT: v_readfirstlane_b32 s36, v10 -; SI-NEXT: v_writelane_b32 v41, s35, 20 -; SI-NEXT: v_writelane_b32 v40, s96, 32 -; SI-NEXT: v_readfirstlane_b32 s37, v9 -; SI-NEXT: v_writelane_b32 v41, s36, 21 +; SI-NEXT: v_readfirstlane_b32 s79, v4 +; SI-NEXT: v_writelane_b32 v41, s77, 14 +; SI-NEXT: v_readfirstlane_b32 s90, v3 +; SI-NEXT: v_writelane_b32 v41, s79, 15 +; SI-NEXT: v_readfirstlane_b32 s91, v6 +; SI-NEXT: v_writelane_b32 v41, s90, 16 +; SI-NEXT: v_readfirstlane_b32 s92, v5 +; SI-NEXT: v_writelane_b32 v41, s91, 17 +; SI-NEXT: v_readfirstlane_b32 s93, v8 +; SI-NEXT: v_writelane_b32 v41, s92, 18 +; SI-NEXT: v_readfirstlane_b32 s94, v7 +; SI-NEXT: v_writelane_b32 v41, s93, 19 +; SI-NEXT: v_readfirstlane_b32 s95, v10 +; SI-NEXT: v_writelane_b32 v41, s94, 20 +; SI-NEXT: v_readfirstlane_b32 s30, v9 +; SI-NEXT: v_writelane_b32 v41, s95, 21 +; SI-NEXT: v_readfirstlane_b32 s31, v12 +; SI-NEXT: v_writelane_b32 v41, s30, 22 ; SI-NEXT: s_waitcnt vmcnt(7) -; SI-NEXT: v_readfirstlane_b32 s62, v31 +; SI-NEXT: v_readfirstlane_b32 s21, v31 ; SI-NEXT: s_waitcnt vmcnt(6) ; SI-NEXT: v_readfirstlane_b32 s80, v32 ; SI-NEXT: s_waitcnt vmcnt(5) -; SI-NEXT: v_readfirstlane_b32 s69, v33 +; SI-NEXT: v_readfirstlane_b32 s75, v33 ; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:44 ; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:40 ; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:36 @@ -238670,20 +235389,25 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a ; SI-NEXT: s_waitcnt vmcnt(12) ; SI-NEXT: v_readfirstlane_b32 s84, v34 ; SI-NEXT: s_waitcnt vmcnt(11) -; SI-NEXT: v_readfirstlane_b32 s68, v35 +; SI-NEXT: v_readfirstlane_b32 s23, v35 ; SI-NEXT: s_waitcnt vmcnt(10) ; SI-NEXT: v_readfirstlane_b32 s83, v36 ; SI-NEXT: s_waitcnt vmcnt(8) ; SI-NEXT: v_readfirstlane_b32 s87, v38 ; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:80 -; SI-NEXT: v_readfirstlane_b32 s6, v37 +; SI-NEXT: v_readfirstlane_b32 s18, v37 ; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:12 ; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:8 ; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:4 ; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 +; SI-NEXT: v_writelane_b32 v41, s31, 23 +; SI-NEXT: v_readfirstlane_b32 s34, v11 +; SI-NEXT: v_readfirstlane_b32 s35, v14 +; SI-NEXT: v_readfirstlane_b32 s36, v13 +; SI-NEXT: v_writelane_b32 v40, s96, 32 +; SI-NEXT: v_readfirstlane_b32 s37, v16 ; SI-NEXT: v_writelane_b32 v40, s97, 33 -; SI-NEXT: v_readfirstlane_b32 s38, v12 -; SI-NEXT: v_writelane_b32 v41, s37, 22 +; SI-NEXT: v_readfirstlane_b32 s38, v15 ; SI-NEXT: v_writelane_b32 v40, s98, 34 ; SI-NEXT: v_readfirstlane_b32 s14, v30 ; SI-NEXT: v_readfirstlane_b32 s15, v29 @@ -238693,21 +235417,13 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a ; SI-NEXT: v_readfirstlane_b32 s11, v25 ; SI-NEXT: v_readfirstlane_b32 s8, v24 ; SI-NEXT: v_readfirstlane_b32 s9, v23 -; SI-NEXT: v_readfirstlane_b32 s88, v22 -; SI-NEXT: v_readfirstlane_b32 s29, v21 -; SI-NEXT: v_readfirstlane_b32 s79, v20 -; SI-NEXT: v_readfirstlane_b32 s27, v19 -; SI-NEXT: v_readfirstlane_b32 s78, v18 -; SI-NEXT: v_readfirstlane_b32 s25, v17 -; SI-NEXT: v_readfirstlane_b32 s77, v16 -; SI-NEXT: v_readfirstlane_b32 s23, v15 -; SI-NEXT: v_readfirstlane_b32 s39, v14 -; SI-NEXT: v_readfirstlane_b32 s21, v13 -; SI-NEXT: v_readfirstlane_b32 s19, v11 -; SI-NEXT: v_readfirstlane_b32 s18, v1 -; SI-NEXT: v_writelane_b32 v41, s38, 23 +; SI-NEXT: v_readfirstlane_b32 s89, v22 +; SI-NEXT: v_readfirstlane_b32 s7, v21 +; SI-NEXT: v_readfirstlane_b32 s25, v20 +; SI-NEXT: v_readfirstlane_b32 s29, v19 +; SI-NEXT: v_readfirstlane_b32 s39, v18 +; SI-NEXT: v_readfirstlane_b32 s27, v17 ; SI-NEXT: v_writelane_b32 v40, s99, 35 -; SI-NEXT: v_writelane_b32 v41, s39, 24 ; SI-NEXT: s_waitcnt vmcnt(12) ; SI-NEXT: v_readfirstlane_b32 s58, v31 ; SI-NEXT: s_waitcnt vmcnt(11) @@ -238727,261 +235443,289 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a ; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_readfirstlane_b32 s42, v34 ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v38 +; SI-NEXT: s_and_b64 s[4:5], vcc, exec +; SI-NEXT: v_readfirstlane_b32 s5, v1 +; SI-NEXT: v_writelane_b32 v41, s5, 24 +; SI-NEXT: v_writelane_b32 v41, s34, 25 +; SI-NEXT: v_writelane_b32 v41, s35, 26 +; SI-NEXT: v_writelane_b32 v41, s36, 27 +; SI-NEXT: v_writelane_b32 v41, s37, 28 ; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_readfirstlane_b32 s43, v35 ; SI-NEXT: s_waitcnt vmcnt(1) ; SI-NEXT: v_readfirstlane_b32 s40, v36 ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: v_readfirstlane_b32 s41, v37 -; SI-NEXT: s_and_b64 s[4:5], vcc, exec +; SI-NEXT: v_writelane_b32 v41, s38, 29 +; SI-NEXT: v_writelane_b32 v41, s39, 30 ; SI-NEXT: s_cbranch_scc0 .LBB107_2 ; SI-NEXT: ; %bb.1: ; %cmp.false ; SI-NEXT: s_lshl_b32 s4, s60, 16 -; SI-NEXT: v_writelane_b32 v41, s4, 25 -; SI-NEXT: s_lshl_b32 s4, s63, 16 -; SI-NEXT: v_writelane_b32 v41, s4, 26 -; SI-NEXT: s_lshl_b32 s4, s20, 16 -; SI-NEXT: v_writelane_b32 v41, s4, 27 -; SI-NEXT: s_lshl_b32 s4, s22, 16 -; SI-NEXT: v_writelane_b32 v41, s4, 28 -; SI-NEXT: s_lshl_b32 s4, s24, 16 -; SI-NEXT: v_writelane_b32 v41, s4, 29 -; SI-NEXT: s_lshl_b32 s4, s26, 16 -; SI-NEXT: v_writelane_b32 v41, s4, 30 -; SI-NEXT: s_lshl_b32 s4, s28, 16 -; SI-NEXT: v_writelane_b32 v41, s4, 31 -; SI-NEXT: s_lshl_b32 s4, s18, 16 ; SI-NEXT: v_writelane_b32 v41, s4, 32 -; SI-NEXT: s_lshl_b32 s4, s89, 16 -; SI-NEXT: v_writelane_b32 v41, s4, 33 -; SI-NEXT: s_lshl_b32 s4, s91, 16 +; SI-NEXT: s_lshl_b32 s4, s17, 16 +; SI-NEXT: v_writelane_b32 v41, s4, 31 +; SI-NEXT: s_lshl_b32 s4, s61, 16 ; SI-NEXT: v_writelane_b32 v41, s4, 34 -; SI-NEXT: s_lshl_b32 s4, s35, 16 -; SI-NEXT: v_writelane_b32 v41, s4, 35 -; SI-NEXT: s_lshl_b32 s4, s37, 16 -; SI-NEXT: s_lshl_b32 s7, s17, 16 -; SI-NEXT: s_lshl_b32 s96, s61, 16 -; SI-NEXT: s_lshl_b32 s99, s72, 16 -; SI-NEXT: s_lshl_b32 s97, s74, 16 -; SI-NEXT: s_lshl_b32 s92, s75, 16 -; SI-NEXT: s_lshl_b32 s94, s76, 16 -; SI-NEXT: s_lshl_b32 s95, s93, 16 -; SI-NEXT: s_lshl_b32 s93, s16, 16 -; SI-NEXT: s_lshl_b32 s30, s73, 16 -; SI-NEXT: s_lshl_b32 s31, s90, 16 -; SI-NEXT: s_lshl_b32 s34, s34, 16 +; SI-NEXT: s_lshl_b32 s4, s19, 16 +; SI-NEXT: v_writelane_b32 v41, s4, 33 +; SI-NEXT: s_lshl_b32 s4, s20, 16 ; SI-NEXT: v_writelane_b32 v41, s4, 36 -; SI-NEXT: s_lshl_b32 s35, s36, 16 -; SI-NEXT: s_lshl_b32 s86, s19, 16 -; SI-NEXT: s_lshl_b32 s36, s38, 16 -; SI-NEXT: s_lshl_b32 s22, s21, 16 -; SI-NEXT: s_lshl_b32 s37, s39, 16 -; SI-NEXT: s_lshl_b32 s24, s23, 16 -; SI-NEXT: s_lshl_b32 s38, s77, 16 -; SI-NEXT: s_lshl_b32 s28, s25, 16 -; SI-NEXT: s_lshl_b32 s39, s78, 16 -; SI-NEXT: s_lshl_b32 s61, s27, 16 -; SI-NEXT: s_lshl_b32 s48, s79, 16 -; SI-NEXT: s_lshl_b32 s89, s29, 16 -; SI-NEXT: s_lshl_b32 s49, s88, 16 -; SI-NEXT: s_lshl_b32 s60, s9, 16 -; SI-NEXT: s_lshl_b32 s50, s8, 16 -; SI-NEXT: s_lshl_b32 s90, s11, 16 -; SI-NEXT: s_lshl_b32 s91, s10, 16 -; SI-NEXT: s_lshl_b32 s70, s13, 16 -; SI-NEXT: s_lshl_b32 s51, s12, 16 -; SI-NEXT: s_lshl_b32 s71, s15, 16 -; SI-NEXT: s_lshl_b32 s52, s14, 16 -; SI-NEXT: s_lshl_b32 s20, s41, 16 -; SI-NEXT: s_lshl_b32 s53, s40, 16 -; SI-NEXT: s_lshl_b32 s81, s43, 16 -; SI-NEXT: s_lshl_b32 s54, s42, 16 -; SI-NEXT: s_lshl_b32 s63, s45, 16 -; SI-NEXT: s_lshl_b32 s55, s44, 16 -; SI-NEXT: s_lshl_b32 s72, s47, 16 -; SI-NEXT: s_lshl_b32 s64, s46, 16 -; SI-NEXT: s_lshl_b32 s82, s57, 16 -; SI-NEXT: s_lshl_b32 s65, s56, 16 -; SI-NEXT: s_lshl_b32 s74, s59, 16 -; SI-NEXT: s_lshl_b32 s66, s58, 16 -; SI-NEXT: s_lshl_b32 s75, s87, 16 -; SI-NEXT: s_mov_b32 s73, s6 -; SI-NEXT: s_lshl_b32 s67, s6, 16 -; SI-NEXT: s_lshl_b32 s76, s83, 16 -; SI-NEXT: s_mov_b32 s16, s68 -; SI-NEXT: s_lshl_b32 s68, s68, 16 -; SI-NEXT: s_lshl_b32 s85, s84, 16 -; SI-NEXT: s_mov_b32 s98, s69 -; SI-NEXT: s_lshl_b32 s69, s69, 16 -; SI-NEXT: s_lshl_b32 s17, s80, 16 -; SI-NEXT: s_mov_b32 s6, s62 -; SI-NEXT: s_lshl_b32 s26, s62, 16 +; SI-NEXT: s_lshl_b32 s4, s72, 16 +; SI-NEXT: v_writelane_b32 v41, s4, 35 +; SI-NEXT: s_lshl_b32 s4, s74, 16 +; SI-NEXT: s_lshl_b32 s16, s22, 16 +; SI-NEXT: v_writelane_b32 v41, s4, 37 +; SI-NEXT: s_lshl_b32 s6, s24, 16 +; SI-NEXT: s_lshl_b32 s73, s76, 16 +; SI-NEXT: s_lshl_b32 s98, s26, 16 +; SI-NEXT: s_lshl_b32 s63, s78, 16 +; SI-NEXT: s_lshl_b32 s96, s28, 16 +; SI-NEXT: s_lshl_b32 s62, s88, 16 +; SI-NEXT: s_lshl_b32 s97, s5, 16 +; SI-NEXT: s_lshl_b32 s99, s77, 16 +; SI-NEXT: s_lshl_b32 s85, s90, 16 +; SI-NEXT: s_lshl_b32 s86, s79, 16 +; SI-NEXT: s_lshl_b32 s81, s92, 16 +; SI-NEXT: s_lshl_b32 s82, s91, 16 +; SI-NEXT: s_lshl_b32 s70, s94, 16 +; SI-NEXT: s_lshl_b32 s71, s93, 16 +; SI-NEXT: s_lshl_b32 s68, s30, 16 +; SI-NEXT: s_lshl_b32 s69, s95, 16 +; SI-NEXT: s_lshl_b32 s66, s34, 16 +; SI-NEXT: s_lshl_b32 s67, s31, 16 +; SI-NEXT: s_lshl_b32 s64, s36, 16 +; SI-NEXT: s_lshl_b32 s65, s35, 16 +; SI-NEXT: s_lshl_b32 s54, s38, 16 +; SI-NEXT: s_lshl_b32 s55, s37, 16 +; SI-NEXT: s_lshl_b32 s52, s27, 16 +; SI-NEXT: s_lshl_b32 s53, s39, 16 +; SI-NEXT: s_lshl_b32 s50, s29, 16 +; SI-NEXT: s_lshl_b32 s51, s25, 16 +; SI-NEXT: s_lshl_b32 s48, s7, 16 +; SI-NEXT: s_lshl_b32 s49, s89, 16 +; SI-NEXT: s_lshl_b32 s38, s9, 16 +; SI-NEXT: s_lshl_b32 s39, s8, 16 +; SI-NEXT: s_lshl_b32 s37, s11, 16 +; SI-NEXT: s_lshl_b32 s35, s10, 16 +; SI-NEXT: s_lshl_b32 s31, s13, 16 +; SI-NEXT: s_lshl_b32 s36, s12, 16 +; SI-NEXT: s_lshl_b32 s95, s15, 16 +; SI-NEXT: s_lshl_b32 s34, s14, 16 +; SI-NEXT: s_lshl_b32 s93, s41, 16 +; SI-NEXT: s_lshl_b32 s30, s40, 16 +; SI-NEXT: s_lshl_b32 s91, s43, 16 +; SI-NEXT: s_lshl_b32 s94, s42, 16 +; SI-NEXT: s_lshl_b32 s92, s45, 16 +; SI-NEXT: s_lshl_b32 s90, s44, 16 +; SI-NEXT: s_lshl_b32 s88, s47, 16 +; SI-NEXT: s_lshl_b32 s28, s46, 16 +; SI-NEXT: s_lshl_b32 s78, s57, 16 +; SI-NEXT: s_lshl_b32 s26, s56, 16 +; SI-NEXT: s_lshl_b32 s76, s59, 16 +; SI-NEXT: s_lshl_b32 s24, s58, 16 +; SI-NEXT: s_lshl_b32 s74, s87, 16 +; SI-NEXT: s_mov_b32 s77, s18 +; SI-NEXT: s_lshl_b32 s22, s18, 16 +; SI-NEXT: s_lshl_b32 s72, s83, 16 +; SI-NEXT: s_mov_b32 s79, s23 +; SI-NEXT: s_lshl_b32 s20, s23, 16 +; SI-NEXT: s_lshl_b32 s61, s84, 16 +; SI-NEXT: s_mov_b32 s18, s75 +; SI-NEXT: s_lshl_b32 s19, s75, 16 +; SI-NEXT: s_lshl_b32 s60, s80, 16 +; SI-NEXT: s_lshl_b32 s17, s21, 16 ; SI-NEXT: s_mov_b64 s[4:5], 0 ; SI-NEXT: s_branch .LBB107_3 ; SI-NEXT: .LBB107_2: -; SI-NEXT: ; implicit-def: $sgpr17 -; SI-NEXT: ; kill: killed $sgpr17 -; SI-NEXT: s_mov_b32 s16, s68 -; SI-NEXT: ; implicit-def: $sgpr17 -; SI-NEXT: ; kill: killed $sgpr17 -; SI-NEXT: s_mov_b32 s73, s6 -; SI-NEXT: ; implicit-def: $sgpr17 -; SI-NEXT: ; kill: killed $sgpr17 -; SI-NEXT: s_mov_b32 s6, s62 -; SI-NEXT: ; implicit-def: $sgpr17 -; SI-NEXT: ; kill: killed $sgpr17 -; SI-NEXT: s_mov_b32 s98, s69 -; SI-NEXT: ; implicit-def: $sgpr17 -; SI-NEXT: ; kill: killed $sgpr17 +; SI-NEXT: ; implicit-def: $sgpr6 +; SI-NEXT: ; kill: killed $sgpr6 +; SI-NEXT: s_mov_b32 s79, s23 +; SI-NEXT: ; implicit-def: $sgpr6 +; SI-NEXT: ; kill: killed $sgpr6 +; SI-NEXT: s_mov_b32 s77, s18 +; SI-NEXT: ; implicit-def: $sgpr6 +; SI-NEXT: ; kill: killed $sgpr6 +; SI-NEXT: s_mov_b32 s18, s75 +; SI-NEXT: ; implicit-def: $sgpr6 +; SI-NEXT: ; kill: killed $sgpr6 ; SI-NEXT: s_mov_b64 s[4:5], -1 -; SI-NEXT: ; implicit-def: $sgpr17 -; SI-NEXT: ; kill: killed $sgpr17 -; SI-NEXT: ; implicit-def: $sgpr7 +; SI-NEXT: ; implicit-def: $sgpr6 +; SI-NEXT: ; kill: killed $sgpr6 +; SI-NEXT: ; implicit-def: $sgpr16 +; SI-NEXT: ; implicit-def: $sgpr73 +; SI-NEXT: ; implicit-def: $sgpr98 +; SI-NEXT: ; implicit-def: $sgpr63 ; SI-NEXT: ; implicit-def: $sgpr96 -; SI-NEXT: ; implicit-def: $sgpr99 +; SI-NEXT: ; implicit-def: $sgpr62 ; SI-NEXT: ; implicit-def: $sgpr97 -; SI-NEXT: ; implicit-def: $sgpr92 -; SI-NEXT: ; implicit-def: $sgpr94 -; SI-NEXT: ; implicit-def: $sgpr95 -; SI-NEXT: ; implicit-def: $sgpr93 -; SI-NEXT: ; implicit-def: $sgpr30 -; SI-NEXT: ; implicit-def: $sgpr31 -; SI-NEXT: ; implicit-def: $sgpr34 -; SI-NEXT: ; implicit-def: $sgpr35 +; SI-NEXT: ; implicit-def: $sgpr99 +; SI-NEXT: ; implicit-def: $sgpr85 ; SI-NEXT: ; implicit-def: $sgpr86 -; SI-NEXT: ; implicit-def: $sgpr36 -; SI-NEXT: ; implicit-def: $sgpr22 -; SI-NEXT: ; implicit-def: $sgpr37 -; SI-NEXT: ; implicit-def: $sgpr24 -; SI-NEXT: ; implicit-def: $sgpr38 -; SI-NEXT: ; implicit-def: $sgpr28 -; SI-NEXT: ; implicit-def: $sgpr39 -; SI-NEXT: ; implicit-def: $sgpr61 -; SI-NEXT: ; implicit-def: $sgpr48 -; SI-NEXT: ; implicit-def: $sgpr89 -; SI-NEXT: ; implicit-def: $sgpr49 -; SI-NEXT: ; implicit-def: $sgpr60 -; SI-NEXT: ; implicit-def: $sgpr50 -; SI-NEXT: ; implicit-def: $sgpr90 -; SI-NEXT: ; implicit-def: $sgpr91 -; SI-NEXT: ; implicit-def: $sgpr70 -; SI-NEXT: ; implicit-def: $sgpr51 -; SI-NEXT: ; implicit-def: $sgpr71 -; SI-NEXT: ; implicit-def: $sgpr52 -; SI-NEXT: ; implicit-def: $sgpr20 -; SI-NEXT: ; implicit-def: $sgpr53 ; SI-NEXT: ; implicit-def: $sgpr81 -; SI-NEXT: ; implicit-def: $sgpr54 -; SI-NEXT: ; implicit-def: $sgpr63 -; SI-NEXT: ; implicit-def: $sgpr55 -; SI-NEXT: ; implicit-def: $sgpr72 -; SI-NEXT: ; implicit-def: $sgpr64 ; SI-NEXT: ; implicit-def: $sgpr82 -; SI-NEXT: ; implicit-def: $sgpr65 -; SI-NEXT: ; implicit-def: $sgpr74 -; SI-NEXT: ; implicit-def: $sgpr66 -; SI-NEXT: ; implicit-def: $sgpr75 -; SI-NEXT: ; implicit-def: $sgpr67 -; SI-NEXT: ; implicit-def: $sgpr76 +; SI-NEXT: ; implicit-def: $sgpr70 +; SI-NEXT: ; implicit-def: $sgpr71 ; SI-NEXT: ; implicit-def: $sgpr68 -; SI-NEXT: ; implicit-def: $sgpr85 ; SI-NEXT: ; implicit-def: $sgpr69 +; SI-NEXT: ; implicit-def: $sgpr66 +; SI-NEXT: ; implicit-def: $sgpr67 +; SI-NEXT: ; implicit-def: $sgpr64 +; SI-NEXT: ; implicit-def: $sgpr65 +; SI-NEXT: ; implicit-def: $sgpr54 +; SI-NEXT: ; implicit-def: $sgpr55 +; SI-NEXT: ; implicit-def: $sgpr52 +; SI-NEXT: ; implicit-def: $sgpr53 +; SI-NEXT: ; implicit-def: $sgpr50 +; SI-NEXT: ; implicit-def: $sgpr51 +; SI-NEXT: ; implicit-def: $sgpr48 +; SI-NEXT: ; implicit-def: $sgpr49 +; SI-NEXT: ; implicit-def: $sgpr38 +; SI-NEXT: ; implicit-def: $sgpr39 +; SI-NEXT: ; implicit-def: $sgpr37 +; SI-NEXT: ; implicit-def: $sgpr35 +; SI-NEXT: ; implicit-def: $sgpr31 +; SI-NEXT: ; implicit-def: $sgpr36 +; SI-NEXT: ; implicit-def: $sgpr95 +; SI-NEXT: ; implicit-def: $sgpr34 +; SI-NEXT: ; implicit-def: $sgpr93 +; SI-NEXT: ; implicit-def: $sgpr30 +; SI-NEXT: ; implicit-def: $sgpr91 +; SI-NEXT: ; implicit-def: $sgpr94 +; SI-NEXT: ; implicit-def: $sgpr92 +; SI-NEXT: ; implicit-def: $sgpr90 +; SI-NEXT: ; implicit-def: $sgpr88 +; SI-NEXT: ; implicit-def: $sgpr28 +; SI-NEXT: ; implicit-def: $sgpr78 ; SI-NEXT: ; implicit-def: $sgpr26 +; SI-NEXT: ; implicit-def: $sgpr76 +; SI-NEXT: ; implicit-def: $sgpr24 +; SI-NEXT: ; implicit-def: $sgpr74 +; SI-NEXT: ; implicit-def: $sgpr22 +; SI-NEXT: ; implicit-def: $sgpr72 +; SI-NEXT: ; implicit-def: $sgpr20 +; SI-NEXT: ; implicit-def: $sgpr61 +; SI-NEXT: ; implicit-def: $sgpr19 +; SI-NEXT: ; implicit-def: $sgpr60 ; SI-NEXT: ; implicit-def: $sgpr17 -; SI-NEXT: ; kill: killed $sgpr17 -; SI-NEXT: ; implicit-def: $sgpr17 -; SI-NEXT: ; kill: killed $sgpr17 -; SI-NEXT: ; implicit-def: $sgpr17 -; SI-NEXT: ; kill: killed $sgpr17 -; SI-NEXT: ; implicit-def: $sgpr17 -; SI-NEXT: ; kill: killed $sgpr17 -; SI-NEXT: ; implicit-def: $sgpr17 -; SI-NEXT: ; kill: killed $sgpr17 -; SI-NEXT: ; implicit-def: $sgpr17 -; SI-NEXT: ; kill: killed $sgpr17 -; SI-NEXT: ; implicit-def: $sgpr17 +; SI-NEXT: ; implicit-def: $sgpr6 +; SI-NEXT: ; kill: killed $sgpr6 +; SI-NEXT: ; implicit-def: $sgpr6 +; SI-NEXT: ; kill: killed $sgpr6 +; SI-NEXT: ; implicit-def: $sgpr6 ; SI-NEXT: .LBB107_3: ; %Flow ; SI-NEXT: s_andn2_b64 vcc, exec, s[4:5] +; SI-NEXT: s_mov_b32 s4, s60 ; SI-NEXT: s_mov_b32 s5, s17 -; SI-NEXT: s_mov_b32 s17, s86 -; SI-NEXT: s_mov_b32 s86, s7 +; SI-NEXT: s_mov_b32 s17, s61 +; SI-NEXT: s_mov_b32 s60, s72 +; SI-NEXT: s_mov_b32 s61, s74 +; SI-NEXT: s_mov_b32 s72, s76 +; SI-NEXT: s_mov_b32 s74, s78 +; SI-NEXT: s_mov_b32 s76, s88 +; SI-NEXT: s_mov_b32 s78, s92 +; SI-NEXT: s_mov_b32 s88, s91 +; SI-NEXT: s_mov_b32 s91, s93 +; SI-NEXT: s_mov_b32 s92, s94 +; SI-NEXT: s_mov_b32 s93, s95 +; SI-NEXT: s_mov_b32 s94, s30 +; SI-NEXT: s_mov_b32 s95, s31 +; SI-NEXT: s_mov_b32 s30, s34 +; SI-NEXT: s_mov_b32 s31, s37 +; SI-NEXT: s_mov_b32 s34, s36 +; SI-NEXT: s_mov_b32 s36, s38 +; SI-NEXT: s_mov_b32 s37, s39 +; SI-NEXT: s_mov_b32 s38, s48 +; SI-NEXT: s_mov_b32 s39, s49 +; SI-NEXT: s_mov_b32 s48, s50 +; SI-NEXT: s_mov_b32 s49, s51 +; SI-NEXT: s_mov_b32 s50, s52 +; SI-NEXT: s_mov_b32 s51, s53 +; SI-NEXT: s_mov_b32 s52, s54 +; SI-NEXT: s_mov_b32 s53, s55 +; SI-NEXT: s_mov_b32 s54, s6 +; SI-NEXT: s_mov_b32 s55, s16 ; SI-NEXT: s_cbranch_vccnz .LBB107_5 ; SI-NEXT: ; %bb.4: ; %cmp.true -; SI-NEXT: s_lshl_b32 s5, s6, 16 -; SI-NEXT: v_readlane_b32 s6, v41, 24 -; SI-NEXT: s_lshl_b32 s20, s6, 16 -; SI-NEXT: v_readlane_b32 s6, v41, 23 -; SI-NEXT: s_lshl_b32 s17, s6, 16 -; SI-NEXT: v_readlane_b32 s6, v41, 22 -; SI-NEXT: s_lshl_b32 s61, s16, 16 -; SI-NEXT: s_add_i32 s16, s6, 3 -; SI-NEXT: v_readlane_b32 s6, v41, 21 -; SI-NEXT: s_and_b32 s16, s16, 0xffff -; SI-NEXT: s_lshl_b32 s7, s6, 16 -; SI-NEXT: v_readlane_b32 s6, v41, 20 -; SI-NEXT: s_or_b32 s7, s7, s16 -; SI-NEXT: s_add_i32 s6, s6, 3 -; SI-NEXT: v_readlane_b32 s16, v41, 19 -; SI-NEXT: s_add_i32 s19, s19, 3 -; SI-NEXT: s_and_b32 s6, s6, 0xffff -; SI-NEXT: s_lshl_b32 s16, s16, 16 -; SI-NEXT: s_and_b32 s19, s19, 0xffff -; SI-NEXT: s_or_b32 s6, s16, s6 -; SI-NEXT: v_readlane_b32 s16, v41, 18 -; SI-NEXT: s_lshl_b32 s60, s98, 16 -; SI-NEXT: s_or_b32 s17, s17, s19 -; SI-NEXT: s_add_i32 s98, s16, 3 -; SI-NEXT: v_readlane_b32 s19, v41, 17 -; SI-NEXT: s_add_i32 s21, s21, 3 -; SI-NEXT: s_and_b32 s16, s98, 0xffff -; SI-NEXT: s_lshl_b32 s19, s19, 16 -; SI-NEXT: s_add_i32 s11, s11, 3 -; SI-NEXT: s_add_i32 s9, s9, 3 -; SI-NEXT: s_and_b32 s21, s21, 0xffff -; SI-NEXT: s_or_b32 s16, s19, s16 -; SI-NEXT: v_readlane_b32 s19, v41, 16 ; SI-NEXT: s_add_i32 s13, s13, 3 +; SI-NEXT: s_and_b32 s13, s13, 0xffff +; SI-NEXT: s_lshl_b32 s12, s12, 16 +; SI-NEXT: s_add_i32 s11, s11, 3 +; SI-NEXT: v_readlane_b32 s6, v41, 30 +; SI-NEXT: s_add_i32 s15, s15, 3 +; SI-NEXT: s_or_b32 s12, s12, s13 ; SI-NEXT: s_and_b32 s11, s11, 0xffff ; SI-NEXT: s_lshl_b32 s10, s10, 16 +; SI-NEXT: s_lshl_b32 s13, s6, 16 +; SI-NEXT: v_readlane_b32 s6, v41, 29 +; SI-NEXT: s_and_b32 s15, s15, 0xffff +; SI-NEXT: s_lshl_b32 s14, s14, 16 +; SI-NEXT: s_or_b32 s10, s10, s11 +; SI-NEXT: s_lshl_b32 s11, s25, 16 +; SI-NEXT: s_add_i32 s25, s6, 3 +; SI-NEXT: v_readlane_b32 s6, v41, 28 +; SI-NEXT: s_or_b32 s14, s14, s15 +; SI-NEXT: s_lshl_b32 s15, s6, 16 +; SI-NEXT: v_readlane_b32 s6, v41, 27 +; SI-NEXT: s_add_i32 s23, s6, 3 +; SI-NEXT: v_readlane_b32 s6, v41, 26 +; SI-NEXT: s_add_i32 s9, s9, 3 +; SI-NEXT: s_lshl_b32 s20, s6, 16 +; SI-NEXT: v_readlane_b32 s6, v41, 25 +; SI-NEXT: s_lshl_b32 s5, s21, 16 ; SI-NEXT: s_and_b32 s9, s9, 0xffff ; SI-NEXT: s_lshl_b32 s8, s8, 16 -; SI-NEXT: s_add_i32 s29, s29, 3 -; SI-NEXT: s_or_b32 s20, s20, s21 -; SI-NEXT: s_add_i32 s96, s19, 3 -; SI-NEXT: v_readlane_b32 s21, v41, 15 -; SI-NEXT: s_add_i32 s15, s15, 3 -; SI-NEXT: s_and_b32 s13, s13, 0xffff -; SI-NEXT: s_lshl_b32 s12, s12, 16 -; SI-NEXT: s_or_b32 s10, s10, s11 +; SI-NEXT: s_add_i32 s7, s7, 3 +; SI-NEXT: s_add_i32 s21, s6, 3 +; SI-NEXT: v_readlane_b32 s6, v41, 23 ; SI-NEXT: s_or_b32 s8, s8, s9 +; SI-NEXT: s_and_b32 s7, s7, 0xffff +; SI-NEXT: s_lshl_b32 s9, s89, 16 +; SI-NEXT: s_add_i32 s29, s29, 3 +; SI-NEXT: s_lshl_b32 s19, s6, 16 +; SI-NEXT: v_readlane_b32 s6, v41, 22 +; SI-NEXT: s_or_b32 s7, s9, s7 ; SI-NEXT: s_and_b32 s9, s29, 0xffff -; SI-NEXT: s_lshl_b32 s11, s88, 16 ; SI-NEXT: s_add_i32 s27, s27, 3 -; SI-NEXT: s_and_b32 s19, s96, 0xffff -; SI-NEXT: s_lshl_b32 s21, s21, 16 -; SI-NEXT: s_and_b32 s15, s15, 0xffff -; SI-NEXT: s_lshl_b32 s14, s14, 16 -; SI-NEXT: s_or_b32 s12, s12, s13 +; SI-NEXT: s_add_i32 s16, s6, 3 +; SI-NEXT: v_readlane_b32 s6, v41, 21 ; SI-NEXT: s_or_b32 s9, s11, s9 ; SI-NEXT: s_and_b32 s11, s27, 0xffff -; SI-NEXT: s_lshl_b32 s13, s79, 16 -; SI-NEXT: s_add_i32 s25, s25, 3 -; SI-NEXT: s_or_b32 s19, s21, s19 -; SI-NEXT: s_add_i32 s18, s18, 3 -; SI-NEXT: v_readlane_b32 s21, v41, 14 -; SI-NEXT: s_or_b32 s14, s14, s15 +; SI-NEXT: s_and_b32 s16, s16, 0xffff +; SI-NEXT: s_lshl_b32 s17, s6, 16 +; SI-NEXT: v_readlane_b32 s6, v41, 20 ; SI-NEXT: s_or_b32 s11, s13, s11 ; SI-NEXT: s_and_b32 s13, s25, 0xffff -; SI-NEXT: s_lshl_b32 s15, s78, 16 -; SI-NEXT: s_add_i32 s23, s23, 3 -; SI-NEXT: s_and_b32 s18, s18, 0xffff -; SI-NEXT: s_lshl_b32 s21, s21, 16 +; SI-NEXT: s_or_b32 s16, s17, s16 +; SI-NEXT: s_add_i32 s6, s6, 3 +; SI-NEXT: v_readlane_b32 s17, v41, 19 ; SI-NEXT: s_or_b32 s13, s15, s13 ; SI-NEXT: s_and_b32 s15, s23, 0xffff -; SI-NEXT: s_lshl_b32 s22, s77, 16 +; SI-NEXT: s_and_b32 s6, s6, 0xffff +; SI-NEXT: s_lshl_b32 s17, s17, 16 +; SI-NEXT: s_lshl_b32 s60, s18, 16 +; SI-NEXT: s_or_b32 s15, s20, s15 +; SI-NEXT: s_and_b32 s20, s21, 0xffff +; SI-NEXT: s_or_b32 s6, s17, s6 +; SI-NEXT: v_readlane_b32 s17, v41, 18 +; SI-NEXT: v_readlane_b32 s18, v41, 17 +; SI-NEXT: s_or_b32 s19, s19, s20 +; SI-NEXT: s_add_i32 s98, s17, 3 +; SI-NEXT: s_lshl_b32 s20, s18, 16 +; SI-NEXT: v_readlane_b32 s18, v41, 16 +; SI-NEXT: s_and_b32 s17, s98, 0xffff +; SI-NEXT: s_add_i32 s96, s18, 3 +; SI-NEXT: v_readlane_b32 s18, v41, 15 +; SI-NEXT: s_or_b32 s17, s20, s17 +; SI-NEXT: s_and_b32 s20, s96, 0xffff +; SI-NEXT: s_lshl_b32 s21, s18, 16 +; SI-NEXT: v_readlane_b32 s18, v41, 24 +; SI-NEXT: s_or_b32 s20, s21, s20 +; SI-NEXT: s_add_i32 s18, s18, 3 +; SI-NEXT: v_readlane_b32 s21, v41, 14 +; SI-NEXT: s_and_b32 s18, s18, 0xffff +; SI-NEXT: s_lshl_b32 s21, s21, 16 ; SI-NEXT: s_or_b32 s18, s21, s18 ; SI-NEXT: v_readlane_b32 s21, v41, 13 -; SI-NEXT: s_or_b32 s15, s22, s15 ; SI-NEXT: s_add_i32 s21, s21, 3 ; SI-NEXT: v_readlane_b32 s22, v41, 12 ; SI-NEXT: s_and_b32 s21, s21, 0xffff @@ -239023,42 +235767,20 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a ; SI-NEXT: s_and_b32 s27, s27, 0xffff ; SI-NEXT: s_lshl_b32 s28, s28, 16 ; SI-NEXT: s_or_b32 s27, s28, s27 -; SI-NEXT: s_add_i32 s27, s27, 0x30000 -; SI-NEXT: s_add_i32 s26, s26, 0x30000 -; SI-NEXT: s_and_b32 s86, s27, 0xffff0000 -; SI-NEXT: s_lshl_b32 s27, s27, 16 -; SI-NEXT: s_add_i32 s25, s25, 0x30000 -; SI-NEXT: v_writelane_b32 v41, s27, 25 -; SI-NEXT: s_and_b32 s96, s26, 0xffff0000 -; SI-NEXT: s_lshl_b32 s26, s26, 16 -; SI-NEXT: s_add_i32 s24, s24, 0x30000 -; SI-NEXT: v_writelane_b32 v41, s26, 26 -; SI-NEXT: s_and_b32 s99, s25, 0xffff0000 -; SI-NEXT: s_lshl_b32 s25, s25, 16 -; SI-NEXT: s_add_i32 s23, s23, 0x30000 -; SI-NEXT: v_writelane_b32 v41, s25, 27 -; SI-NEXT: s_and_b32 s97, s24, 0xffff0000 -; SI-NEXT: s_lshl_b32 s24, s24, 16 ; SI-NEXT: s_add_i32 s80, s80, 3 -; SI-NEXT: s_add_i32 s22, s22, 0x30000 -; SI-NEXT: v_writelane_b32 v41, s24, 28 -; SI-NEXT: s_and_b32 s92, s23, 0xffff0000 -; SI-NEXT: s_lshl_b32 s23, s23, 16 +; SI-NEXT: s_add_i32 s27, s27, 0x30000 ; SI-NEXT: s_and_b32 s4, s80, 0xffff ; SI-NEXT: s_add_i32 s84, s84, 3 -; SI-NEXT: s_add_i32 s21, s21, 0x30000 -; SI-NEXT: v_writelane_b32 v41, s23, 29 -; SI-NEXT: s_and_b32 s94, s22, 0xffff0000 -; SI-NEXT: s_lshl_b32 s22, s22, 16 +; SI-NEXT: s_and_b32 s28, s27, 0xffff0000 ; SI-NEXT: s_or_b32 s4, s5, s4 ; SI-NEXT: s_and_b32 s5, s84, 0xffff ; SI-NEXT: s_add_i32 s83, s83, 3 -; SI-NEXT: s_add_i32 s18, s18, 0x30000 -; SI-NEXT: v_writelane_b32 v41, s22, 30 -; SI-NEXT: s_and_b32 s95, s21, 0xffff0000 -; SI-NEXT: s_lshl_b32 s21, s21, 16 +; SI-NEXT: s_add_i32 s26, s26, 0x30000 +; SI-NEXT: v_writelane_b32 v41, s28, 31 +; SI-NEXT: s_lshl_b32 s27, s27, 16 ; SI-NEXT: s_or_b32 s5, s60, s5 ; SI-NEXT: s_and_b32 s60, s83, 0xffff +; SI-NEXT: s_lshl_b32 s61, s79, 16 ; SI-NEXT: s_add_i32 s87, s87, 3 ; SI-NEXT: s_add_i32 s59, s59, 3 ; SI-NEXT: s_add_i32 s57, s57, 3 @@ -239066,13 +235788,11 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a ; SI-NEXT: s_add_i32 s45, s45, 3 ; SI-NEXT: s_add_i32 s43, s43, 3 ; SI-NEXT: s_add_i32 s41, s41, 3 -; SI-NEXT: s_add_i32 s19, s19, 0x30000 -; SI-NEXT: v_writelane_b32 v41, s21, 31 -; SI-NEXT: s_and_b32 s93, s18, 0xffff0000 -; SI-NEXT: s_lshl_b32 s18, s18, 16 -; SI-NEXT: s_or_b32 s76, s61, s60 +; SI-NEXT: v_writelane_b32 v41, s27, 32 +; SI-NEXT: s_and_b32 s27, s26, 0xffff0000 +; SI-NEXT: s_or_b32 vcc_lo, s61, s60 ; SI-NEXT: s_and_b32 s60, s87, 0xffff -; SI-NEXT: s_lshl_b32 s61, s73, 16 +; SI-NEXT: s_lshl_b32 s61, s77, 16 ; SI-NEXT: s_and_b32 s59, s59, 0xffff ; SI-NEXT: s_lshl_b32 s58, s58, 16 ; SI-NEXT: s_and_b32 s57, s57, 0xffff @@ -239085,24 +235805,22 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a ; SI-NEXT: s_lshl_b32 s42, s42, 16 ; SI-NEXT: s_and_b32 s41, s41, 0xffff ; SI-NEXT: s_lshl_b32 s40, s40, 16 -; SI-NEXT: s_add_i32 s16, s16, 0x30000 -; SI-NEXT: v_writelane_b32 v41, s18, 32 -; SI-NEXT: s_lshl_b32 s18, s19, 16 -; SI-NEXT: s_or_b32 s75, s61, s60 +; SI-NEXT: s_add_i32 s25, s25, 0x30000 +; SI-NEXT: v_writelane_b32 v41, s27, 33 +; SI-NEXT: s_lshl_b32 s26, s26, 16 +; SI-NEXT: s_or_b32 vcc_hi, s61, s60 ; SI-NEXT: s_or_b32 s58, s58, s59 ; SI-NEXT: s_or_b32 s56, s56, s57 ; SI-NEXT: s_or_b32 s46, s46, s47 ; SI-NEXT: s_or_b32 s44, s44, s45 ; SI-NEXT: s_or_b32 s42, s42, s43 ; SI-NEXT: s_or_b32 s40, s40, s41 -; SI-NEXT: s_add_i32 s6, s6, 0x30000 -; SI-NEXT: v_writelane_b32 v41, s18, 33 -; SI-NEXT: s_and_b32 s31, s16, 0xffff0000 -; SI-NEXT: s_lshl_b32 s16, s16, 16 +; SI-NEXT: v_writelane_b32 v41, s26, 34 +; SI-NEXT: s_and_b32 s26, s25, 0xffff0000 ; SI-NEXT: s_add_i32 s4, s4, 0x30000 ; SI-NEXT: s_add_i32 s5, s5, 0x30000 -; SI-NEXT: s_add_i32 s76, s76, 0x30000 -; SI-NEXT: s_add_i32 s75, s75, 0x30000 +; SI-NEXT: s_add_i32 vcc_lo, vcc_lo, 0x30000 +; SI-NEXT: s_add_i32 vcc_hi, vcc_hi, 0x30000 ; SI-NEXT: s_add_i32 s58, s58, 0x30000 ; SI-NEXT: s_add_i32 s56, s56, 0x30000 ; SI-NEXT: s_add_i32 s46, s46, 0x30000 @@ -239113,294 +235831,311 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a ; SI-NEXT: s_add_i32 s12, s12, 0x30000 ; SI-NEXT: s_add_i32 s10, s10, 0x30000 ; SI-NEXT: s_add_i32 s8, s8, 0x30000 +; SI-NEXT: s_add_i32 s7, s7, 0x30000 ; SI-NEXT: s_add_i32 s9, s9, 0x30000 ; SI-NEXT: s_add_i32 s11, s11, 0x30000 ; SI-NEXT: s_add_i32 s13, s13, 0x30000 ; SI-NEXT: s_add_i32 s15, s15, 0x30000 -; SI-NEXT: s_add_i32 s20, s20, 0x30000 +; SI-NEXT: s_add_i32 s19, s19, 0x30000 +; SI-NEXT: s_add_i32 s16, s16, 0x30000 +; SI-NEXT: s_add_i32 s6, s6, 0x30000 ; SI-NEXT: s_add_i32 s17, s17, 0x30000 -; SI-NEXT: s_add_i32 s7, s7, 0x30000 -; SI-NEXT: v_writelane_b32 v41, s16, 34 -; SI-NEXT: s_and_b32 s34, s6, 0xffff0000 -; SI-NEXT: s_lshl_b32 s6, s6, 16 -; SI-NEXT: s_and_b32 s30, s19, 0xffff0000 -; SI-NEXT: v_writelane_b32 v41, s6, 35 -; SI-NEXT: s_and_b32 s35, s7, 0xffff0000 -; SI-NEXT: s_lshl_b32 s6, s7, 16 -; SI-NEXT: s_and_b32 s36, s17, 0xffff0000 -; SI-NEXT: s_lshl_b32 s17, s17, 16 -; SI-NEXT: s_and_b32 s37, s20, 0xffff0000 -; SI-NEXT: s_lshl_b32 s22, s20, 16 -; SI-NEXT: s_and_b32 s38, s15, 0xffff0000 -; SI-NEXT: s_lshl_b32 s24, s15, 16 -; SI-NEXT: s_and_b32 s39, s13, 0xffff0000 -; SI-NEXT: s_lshl_b32 s28, s13, 16 -; SI-NEXT: s_and_b32 s48, s11, 0xffff0000 -; SI-NEXT: s_lshl_b32 s61, s11, 16 +; SI-NEXT: s_add_i32 s20, s20, 0x30000 +; SI-NEXT: s_add_i32 s18, s18, 0x30000 +; SI-NEXT: s_add_i32 s21, s21, 0x30000 +; SI-NEXT: s_add_i32 s22, s22, 0x30000 +; SI-NEXT: s_add_i32 s23, s23, 0x30000 +; SI-NEXT: s_add_i32 s24, s24, 0x30000 +; SI-NEXT: v_writelane_b32 v41, s26, 35 +; SI-NEXT: s_lshl_b32 s25, s25, 16 +; SI-NEXT: v_writelane_b32 v41, s25, 36 +; SI-NEXT: s_and_b32 s25, s24, 0xffff0000 +; SI-NEXT: s_lshl_b32 s55, s24, 16 +; SI-NEXT: s_and_b32 s73, s23, 0xffff0000 +; SI-NEXT: s_lshl_b32 s54, s23, 16 +; SI-NEXT: s_and_b32 s63, s22, 0xffff0000 +; SI-NEXT: s_lshl_b32 s98, s22, 16 +; SI-NEXT: s_and_b32 s62, s21, 0xffff0000 +; SI-NEXT: s_lshl_b32 s96, s21, 16 +; SI-NEXT: s_and_b32 s99, s18, 0xffff0000 +; SI-NEXT: s_lshl_b32 s97, s18, 16 +; SI-NEXT: s_and_b32 s86, s20, 0xffff0000 +; SI-NEXT: s_lshl_b32 s85, s20, 16 +; SI-NEXT: s_and_b32 s82, s17, 0xffff0000 +; SI-NEXT: s_lshl_b32 s81, s17, 16 +; SI-NEXT: s_and_b32 s71, s6, 0xffff0000 +; SI-NEXT: s_lshl_b32 s70, s6, 16 +; SI-NEXT: s_and_b32 s69, s16, 0xffff0000 +; SI-NEXT: s_lshl_b32 s68, s16, 16 +; SI-NEXT: s_and_b32 s67, s19, 0xffff0000 +; SI-NEXT: s_lshl_b32 s66, s19, 16 +; SI-NEXT: s_and_b32 s65, s15, 0xffff0000 +; SI-NEXT: s_lshl_b32 s64, s15, 16 +; SI-NEXT: s_and_b32 s53, s13, 0xffff0000 +; SI-NEXT: s_lshl_b32 s52, s13, 16 +; SI-NEXT: s_and_b32 s51, s11, 0xffff0000 +; SI-NEXT: s_lshl_b32 s50, s11, 16 ; SI-NEXT: s_and_b32 s49, s9, 0xffff0000 -; SI-NEXT: s_lshl_b32 s89, s9, 16 -; SI-NEXT: s_and_b32 s50, s8, 0xffff0000 -; SI-NEXT: s_lshl_b32 s60, s8, 16 -; SI-NEXT: s_and_b32 s91, s10, 0xffff0000 -; SI-NEXT: s_lshl_b32 s90, s10, 16 -; SI-NEXT: s_and_b32 s51, s12, 0xffff0000 -; SI-NEXT: s_lshl_b32 s70, s12, 16 -; SI-NEXT: s_and_b32 s52, s14, 0xffff0000 -; SI-NEXT: s_lshl_b32 s71, s14, 16 -; SI-NEXT: s_and_b32 s53, s40, 0xffff0000 -; SI-NEXT: s_lshl_b32 s20, s40, 16 -; SI-NEXT: s_and_b32 s54, s42, 0xffff0000 -; SI-NEXT: s_lshl_b32 s81, s42, 16 -; SI-NEXT: s_and_b32 s55, s44, 0xffff0000 -; SI-NEXT: s_lshl_b32 s63, s44, 16 -; SI-NEXT: s_and_b32 s64, s46, 0xffff0000 -; SI-NEXT: s_lshl_b32 s72, s46, 16 -; SI-NEXT: s_and_b32 s65, s56, 0xffff0000 -; SI-NEXT: s_lshl_b32 s82, s56, 16 -; SI-NEXT: s_and_b32 s66, s58, 0xffff0000 -; SI-NEXT: s_lshl_b32 s74, s58, 16 -; SI-NEXT: s_and_b32 s67, s75, 0xffff0000 -; SI-NEXT: s_lshl_b32 s75, s75, 16 -; SI-NEXT: s_and_b32 s68, s76, 0xffff0000 -; SI-NEXT: s_lshl_b32 s76, s76, 16 -; SI-NEXT: s_and_b32 s69, s5, 0xffff0000 -; SI-NEXT: s_lshl_b32 s85, s5, 16 -; SI-NEXT: s_and_b32 s26, s4, 0xffff0000 -; SI-NEXT: s_lshl_b32 s5, s4, 16 -; SI-NEXT: v_writelane_b32 v41, s6, 36 +; SI-NEXT: s_lshl_b32 s48, s9, 16 +; SI-NEXT: s_and_b32 s39, s7, 0xffff0000 +; SI-NEXT: s_lshl_b32 s38, s7, 16 +; SI-NEXT: s_and_b32 s37, s8, 0xffff0000 +; SI-NEXT: s_lshl_b32 s36, s8, 16 +; SI-NEXT: s_and_b32 s35, s10, 0xffff0000 +; SI-NEXT: s_lshl_b32 s31, s10, 16 +; SI-NEXT: s_and_b32 s34, s12, 0xffff0000 +; SI-NEXT: s_lshl_b32 s95, s12, 16 +; SI-NEXT: s_and_b32 s30, s14, 0xffff0000 +; SI-NEXT: s_lshl_b32 s93, s14, 16 +; SI-NEXT: s_and_b32 s94, s40, 0xffff0000 +; SI-NEXT: s_lshl_b32 s91, s40, 16 +; SI-NEXT: s_and_b32 s92, s42, 0xffff0000 +; SI-NEXT: s_lshl_b32 s88, s42, 16 +; SI-NEXT: s_and_b32 s90, s44, 0xffff0000 +; SI-NEXT: s_lshl_b32 s78, s44, 16 +; SI-NEXT: s_and_b32 s28, s46, 0xffff0000 +; SI-NEXT: s_lshl_b32 s76, s46, 16 +; SI-NEXT: s_and_b32 s26, s56, 0xffff0000 +; SI-NEXT: s_lshl_b32 s74, s56, 16 +; SI-NEXT: s_and_b32 s24, s58, 0xffff0000 +; SI-NEXT: s_lshl_b32 s72, s58, 16 +; SI-NEXT: s_and_b32 s22, vcc_hi, 0xffff0000 +; SI-NEXT: s_lshl_b32 s61, vcc_hi, 16 +; SI-NEXT: s_and_b32 s20, vcc_lo, 0xffff0000 +; SI-NEXT: s_lshl_b32 s60, vcc_lo, 16 +; SI-NEXT: s_and_b32 s19, s5, 0xffff0000 +; SI-NEXT: s_lshl_b32 s17, s5, 16 +; SI-NEXT: s_and_b32 s5, s4, 0xffff0000 +; SI-NEXT: s_lshl_b32 s4, s4, 16 +; SI-NEXT: v_writelane_b32 v41, s25, 37 ; SI-NEXT: .LBB107_5: ; %end -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s86 -; SI-NEXT: v_readlane_b32 s4, v41, 25 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_readlane_b32 s6, v41, 31 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s6 +; SI-NEXT: v_readlane_b32 s6, v41, 32 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s6 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 +; SI-NEXT: v_readlane_b32 s6, v41, 33 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s96 -; SI-NEXT: v_readlane_b32 s4, v41, 26 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s6 +; SI-NEXT: v_readlane_b32 s6, v41, 34 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s6 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0 +; SI-NEXT: v_readlane_b32 s6, v41, 35 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s99 -; SI-NEXT: v_readlane_b32 s4, v41, 27 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s6 +; SI-NEXT: v_readlane_b32 s6, v41, 36 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s6 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0 +; SI-NEXT: v_readlane_b32 s6, v41, 37 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s97 -; SI-NEXT: v_readlane_b32 s4, v41, 28 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s6 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s55 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s92 -; SI-NEXT: v_readlane_b32 s4, v41, 29 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s73 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s54 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s94 -; SI-NEXT: v_readlane_b32 s4, v41, 30 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s63 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s98 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s95 -; SI-NEXT: v_readlane_b32 s4, v41, 31 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s62 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s96 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s93 -; SI-NEXT: v_readlane_b32 s4, v41, 32 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s99 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s97 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s30 -; SI-NEXT: v_readlane_b32 s4, v41, 33 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s86 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s85 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s31 -; SI-NEXT: v_readlane_b32 s4, v41, 34 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s82 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s81 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s34 -; SI-NEXT: v_readlane_b32 s4, v41, 35 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s71 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s70 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s35 -; SI-NEXT: v_readlane_b32 s4, v41, 36 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s4 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s69 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s68 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s36 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s17 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s67 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s66 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s37 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s22 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s65 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s64 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s38 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s24 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s53 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s52 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s39 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s28 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s51 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s50 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 60, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s49 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 ; SI-NEXT: v_mul_f32_e64 v1, 1.0, s48 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s61 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 64, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s49 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s89 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s39 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s38 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x44, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s50 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s60 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s37 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s36 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x48, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s91 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s90 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s35 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s31 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x4c, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s51 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s70 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s34 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s95 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x50, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s52 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s71 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s30 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s93 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x54, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s53 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s20 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s94 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s91 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x58, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s54 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s81 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s92 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s88 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x5c, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s55 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s63 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s90 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s78 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x60, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s64 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s72 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s28 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s76 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x64, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s65 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s82 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s26 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s74 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x68, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s66 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s74 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s24 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s72 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x6c, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s67 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s75 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s22 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s61 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x70, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s68 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s76 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s20 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s60 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x74, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s69 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s85 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s19 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s17 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v2, vcc, 0x78, v0 ; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; SI-NEXT: s_waitcnt expcnt(0) -; SI-NEXT: v_mul_f32_e64 v1, 1.0, s26 -; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 -; SI-NEXT: v_mul_f32_e64 v2, 1.0, s5 -; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s5 +; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; SI-NEXT: v_mul_f32_e64 v1, 1.0, s4 +; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16 ; SI-NEXT: v_add_i32_e32 v0, vcc, 0x7c, v0 ; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; SI-NEXT: v_readlane_b32 s99, v40, 35 @@ -239458,120 +236193,146 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a ; VI-NEXT: v_writelane_b32 v32, s35, 3 ; VI-NEXT: v_writelane_b32 v32, s36, 4 ; VI-NEXT: v_writelane_b32 v32, s37, 5 +; VI-NEXT: v_mov_b32_e32 v19, s16 +; VI-NEXT: v_readfirstlane_b32 s57, v2 +; VI-NEXT: v_mov_b32_e32 v2, s17 +; VI-NEXT: v_readfirstlane_b32 s56, v3 +; VI-NEXT: v_mov_b32_e32 v3, s18 +; VI-NEXT: v_readfirstlane_b32 s47, v4 +; VI-NEXT: v_mov_b32_e32 v4, s19 +; VI-NEXT: v_readfirstlane_b32 s46, v5 +; VI-NEXT: v_mov_b32_e32 v5, s20 +; VI-NEXT: v_readfirstlane_b32 s45, v6 +; VI-NEXT: v_mov_b32_e32 v6, s21 +; VI-NEXT: v_readfirstlane_b32 s44, v7 +; VI-NEXT: v_mov_b32_e32 v7, s22 +; VI-NEXT: v_readfirstlane_b32 s43, v8 +; VI-NEXT: v_mov_b32_e32 v8, s23 +; VI-NEXT: v_readfirstlane_b32 s42, v9 +; VI-NEXT: v_mov_b32_e32 v9, s24 +; VI-NEXT: v_readfirstlane_b32 s41, v10 +; VI-NEXT: v_mov_b32_e32 v10, s25 +; VI-NEXT: v_readfirstlane_b32 s40, v11 +; VI-NEXT: v_mov_b32_e32 v11, s26 +; VI-NEXT: v_readfirstlane_b32 s26, v12 +; VI-NEXT: v_mov_b32_e32 v12, s27 +; VI-NEXT: v_readfirstlane_b32 s24, v13 +; VI-NEXT: v_mov_b32_e32 v13, s28 +; VI-NEXT: v_readfirstlane_b32 s22, v14 +; VI-NEXT: v_mov_b32_e32 v14, s29 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 ; VI-NEXT: v_writelane_b32 v32, s38, 6 -; VI-NEXT: v_readfirstlane_b32 s47, v2 -; VI-NEXT: v_readfirstlane_b32 s46, v3 -; VI-NEXT: v_readfirstlane_b32 s45, v4 -; VI-NEXT: v_readfirstlane_b32 s44, v5 -; VI-NEXT: v_readfirstlane_b32 s43, v6 -; VI-NEXT: v_readfirstlane_b32 s42, v7 -; VI-NEXT: v_readfirstlane_b32 s41, v8 -; VI-NEXT: v_readfirstlane_b32 s40, v9 -; VI-NEXT: v_readfirstlane_b32 s15, v10 -; VI-NEXT: v_readfirstlane_b32 s14, v11 -; VI-NEXT: v_readfirstlane_b32 s13, v12 -; VI-NEXT: v_readfirstlane_b32 s12, v13 -; VI-NEXT: v_readfirstlane_b32 s11, v14 -; VI-NEXT: v_readfirstlane_b32 s10, v15 -; VI-NEXT: v_readfirstlane_b32 s9, v16 -; VI-NEXT: v_readfirstlane_b32 s8, v17 +; VI-NEXT: v_readfirstlane_b32 s20, v15 +; VI-NEXT: v_readfirstlane_b32 s18, v16 +; VI-NEXT: v_readfirstlane_b32 s16, v17 +; VI-NEXT: v_readfirstlane_b32 s27, v19 +; VI-NEXT: v_readfirstlane_b32 s25, v2 +; VI-NEXT: v_readfirstlane_b32 s23, v3 +; VI-NEXT: v_readfirstlane_b32 s21, v4 +; VI-NEXT: v_readfirstlane_b32 s19, v5 +; VI-NEXT: v_readfirstlane_b32 s17, v6 +; VI-NEXT: v_readfirstlane_b32 s15, v7 +; VI-NEXT: v_readfirstlane_b32 s14, v8 +; VI-NEXT: v_readfirstlane_b32 s13, v9 +; VI-NEXT: v_readfirstlane_b32 s12, v10 +; VI-NEXT: v_readfirstlane_b32 s11, v11 +; VI-NEXT: v_readfirstlane_b32 s10, v12 +; VI-NEXT: v_readfirstlane_b32 s8, v13 +; VI-NEXT: v_readfirstlane_b32 s7, v14 ; VI-NEXT: v_readfirstlane_b32 s6, v0 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec -; VI-NEXT: v_readfirstlane_b32 s7, v1 +; VI-NEXT: v_readfirstlane_b32 s9, v1 ; VI-NEXT: v_writelane_b32 v32, s39, 7 ; VI-NEXT: s_cbranch_scc0 .LBB107_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_cbranch_execnz .LBB107_3 ; VI-NEXT: .LBB107_2: ; %cmp.true -; VI-NEXT: s_and_b32 s4, s47, 0xffff0000 -; VI-NEXT: s_add_i32 s5, s47, 3 -; VI-NEXT: s_and_b32 s47, s46, 0xffff0000 +; VI-NEXT: s_and_b32 s4, s57, 0xffff0000 +; VI-NEXT: s_add_i32 s5, s57, 3 +; VI-NEXT: s_and_b32 s28, s56, 0xffff0000 +; VI-NEXT: s_add_i32 s29, s56, 3 +; VI-NEXT: s_and_b32 s56, s47, 0xffff0000 +; VI-NEXT: s_add_i32 s47, s47, 3 +; VI-NEXT: s_and_b32 s57, s46, 0xffff0000 ; VI-NEXT: s_add_i32 s46, s46, 3 -; VI-NEXT: s_and_b32 s56, s45, 0xffff0000 +; VI-NEXT: s_and_b32 s58, s45, 0xffff0000 ; VI-NEXT: s_add_i32 s45, s45, 3 -; VI-NEXT: s_and_b32 s57, s44, 0xffff0000 +; VI-NEXT: s_and_b32 s59, s44, 0xffff0000 ; VI-NEXT: s_add_i32 s44, s44, 3 -; VI-NEXT: s_and_b32 s58, s43, 0xffff0000 +; VI-NEXT: s_and_b32 s60, s43, 0xffff0000 ; VI-NEXT: s_add_i32 s43, s43, 3 -; VI-NEXT: s_and_b32 s59, s42, 0xffff0000 +; VI-NEXT: s_and_b32 s61, s42, 0xffff0000 ; VI-NEXT: s_add_i32 s42, s42, 3 -; VI-NEXT: s_and_b32 s60, s41, 0xffff0000 +; VI-NEXT: s_and_b32 s62, s41, 0xffff0000 ; VI-NEXT: s_add_i32 s41, s41, 3 -; VI-NEXT: s_and_b32 s61, s40, 0xffff0000 +; VI-NEXT: s_and_b32 s63, s40, 0xffff0000 ; VI-NEXT: s_add_i32 s40, s40, 3 -; VI-NEXT: s_and_b32 s62, s15, 0xffff0000 +; VI-NEXT: s_and_b32 s72, s26, 0xffff0000 +; VI-NEXT: s_add_i32 s26, s26, 3 +; VI-NEXT: s_and_b32 s73, s24, 0xffff0000 +; VI-NEXT: s_add_i32 s24, s24, 3 +; VI-NEXT: s_and_b32 s74, s22, 0xffff0000 +; VI-NEXT: s_add_i32 s22, s22, 3 +; VI-NEXT: s_and_b32 s75, s20, 0xffff0000 +; VI-NEXT: s_add_i32 s20, s20, 3 +; VI-NEXT: s_and_b32 s76, s18, 0xffff0000 +; VI-NEXT: s_add_i32 s18, s18, 3 +; VI-NEXT: s_and_b32 s77, s16, 0xffff0000 +; VI-NEXT: s_add_i32 s16, s16, 3 +; VI-NEXT: s_and_b32 s78, s27, 0xffff0000 +; VI-NEXT: s_add_i32 s27, s27, 3 +; VI-NEXT: s_and_b32 s79, s25, 0xffff0000 +; VI-NEXT: s_add_i32 s25, s25, 3 +; VI-NEXT: s_and_b32 s88, s23, 0xffff0000 +; VI-NEXT: s_add_i32 s23, s23, 3 +; VI-NEXT: s_and_b32 s89, s21, 0xffff0000 +; VI-NEXT: s_add_i32 s21, s21, 3 +; VI-NEXT: s_and_b32 s90, s19, 0xffff0000 +; VI-NEXT: s_add_i32 s19, s19, 3 +; VI-NEXT: s_and_b32 s91, s17, 0xffff0000 +; VI-NEXT: s_add_i32 s17, s17, 3 +; VI-NEXT: s_and_b32 vcc_lo, s15, 0xffff0000 ; VI-NEXT: s_add_i32 s15, s15, 3 -; VI-NEXT: s_and_b32 s63, s14, 0xffff0000 +; VI-NEXT: s_and_b32 vcc_hi, s14, 0xffff0000 ; VI-NEXT: s_add_i32 s14, s14, 3 -; VI-NEXT: s_and_b32 s72, s13, 0xffff0000 +; VI-NEXT: s_and_b32 s30, s13, 0xffff0000 ; VI-NEXT: s_add_i32 s13, s13, 3 -; VI-NEXT: s_and_b32 s73, s12, 0xffff0000 +; VI-NEXT: s_and_b32 s31, s12, 0xffff0000 ; VI-NEXT: s_add_i32 s12, s12, 3 -; VI-NEXT: s_and_b32 s74, s11, 0xffff0000 +; VI-NEXT: s_and_b32 s34, s11, 0xffff0000 ; VI-NEXT: s_add_i32 s11, s11, 3 -; VI-NEXT: s_and_b32 s75, s10, 0xffff0000 +; VI-NEXT: s_and_b32 s35, s10, 0xffff0000 ; VI-NEXT: s_add_i32 s10, s10, 3 -; VI-NEXT: s_and_b32 s76, s9, 0xffff0000 -; VI-NEXT: s_add_i32 s9, s9, 3 -; VI-NEXT: s_and_b32 s77, s8, 0xffff0000 +; VI-NEXT: s_and_b32 s36, s8, 0xffff0000 ; VI-NEXT: s_add_i32 s8, s8, 3 -; VI-NEXT: s_and_b32 s78, s16, 0xffff0000 -; VI-NEXT: s_add_i32 s16, s16, 3 -; VI-NEXT: s_and_b32 s79, s17, 0xffff0000 -; VI-NEXT: s_add_i32 s17, s17, 3 -; VI-NEXT: s_and_b32 s88, s18, 0xffff0000 -; VI-NEXT: s_add_i32 s18, s18, 3 -; VI-NEXT: s_and_b32 s89, s19, 0xffff0000 -; VI-NEXT: s_add_i32 s19, s19, 3 -; VI-NEXT: s_and_b32 s90, s20, 0xffff0000 -; VI-NEXT: s_add_i32 s20, s20, 3 -; VI-NEXT: s_and_b32 s91, s21, 0xffff0000 -; VI-NEXT: s_add_i32 s21, s21, 3 -; VI-NEXT: s_and_b32 vcc_lo, s22, 0xffff0000 -; VI-NEXT: s_add_i32 s22, s22, 3 -; VI-NEXT: s_and_b32 vcc_hi, s23, 0xffff0000 -; VI-NEXT: s_add_i32 s23, s23, 3 -; VI-NEXT: s_and_b32 s30, s24, 0xffff0000 -; VI-NEXT: s_add_i32 s24, s24, 3 -; VI-NEXT: s_and_b32 s31, s25, 0xffff0000 -; VI-NEXT: s_add_i32 s25, s25, 3 -; VI-NEXT: s_and_b32 s34, s26, 0xffff0000 -; VI-NEXT: s_add_i32 s26, s26, 3 -; VI-NEXT: s_and_b32 s35, s27, 0xffff0000 -; VI-NEXT: s_add_i32 s27, s27, 3 -; VI-NEXT: s_and_b32 s36, s28, 0xffff0000 -; VI-NEXT: s_add_i32 s28, s28, 3 -; VI-NEXT: s_and_b32 s37, s29, 0xffff0000 -; VI-NEXT: s_add_i32 s29, s29, 3 +; VI-NEXT: s_and_b32 s37, s7, 0xffff0000 +; VI-NEXT: s_add_i32 s7, s7, 3 ; VI-NEXT: s_and_b32 s38, s6, 0xffff0000 ; VI-NEXT: s_add_i32 s6, s6, 3 -; VI-NEXT: s_and_b32 s39, s7, 0xffff0000 -; VI-NEXT: s_add_i32 s7, s7, 3 -; VI-NEXT: s_and_b32 s7, s7, 0xffff +; VI-NEXT: s_and_b32 s39, s9, 0xffff0000 +; VI-NEXT: s_add_i32 s9, s9, 3 +; VI-NEXT: s_and_b32 s9, s9, 0xffff ; VI-NEXT: s_and_b32 s6, s6, 0xffff -; VI-NEXT: s_and_b32 s29, s29, 0xffff -; VI-NEXT: s_and_b32 s28, s28, 0xffff -; VI-NEXT: s_and_b32 s27, s27, 0xffff -; VI-NEXT: s_and_b32 s26, s26, 0xffff -; VI-NEXT: s_and_b32 s25, s25, 0xffff -; VI-NEXT: s_and_b32 s24, s24, 0xffff -; VI-NEXT: s_and_b32 s23, s23, 0xffff -; VI-NEXT: s_and_b32 s22, s22, 0xffff -; VI-NEXT: s_and_b32 s21, s21, 0xffff -; VI-NEXT: s_and_b32 s20, s20, 0xffff -; VI-NEXT: s_and_b32 s19, s19, 0xffff -; VI-NEXT: s_and_b32 s18, s18, 0xffff -; VI-NEXT: s_and_b32 s17, s17, 0xffff -; VI-NEXT: s_and_b32 s16, s16, 0xffff +; VI-NEXT: s_and_b32 s7, s7, 0xffff ; VI-NEXT: s_and_b32 s8, s8, 0xffff -; VI-NEXT: s_and_b32 s9, s9, 0xffff ; VI-NEXT: s_and_b32 s10, s10, 0xffff ; VI-NEXT: s_and_b32 s11, s11, 0xffff ; VI-NEXT: s_and_b32 s12, s12, 0xffff ; VI-NEXT: s_and_b32 s13, s13, 0xffff ; VI-NEXT: s_and_b32 s14, s14, 0xffff ; VI-NEXT: s_and_b32 s15, s15, 0xffff +; VI-NEXT: s_and_b32 s17, s17, 0xffff +; VI-NEXT: s_and_b32 s19, s19, 0xffff +; VI-NEXT: s_and_b32 s21, s21, 0xffff +; VI-NEXT: s_and_b32 s23, s23, 0xffff +; VI-NEXT: s_and_b32 s25, s25, 0xffff +; VI-NEXT: s_and_b32 s27, s27, 0xffff +; VI-NEXT: s_and_b32 s16, s16, 0xffff +; VI-NEXT: s_and_b32 s18, s18, 0xffff +; VI-NEXT: s_and_b32 s20, s20, 0xffff +; VI-NEXT: s_and_b32 s22, s22, 0xffff +; VI-NEXT: s_and_b32 s24, s24, 0xffff +; VI-NEXT: s_and_b32 s26, s26, 0xffff ; VI-NEXT: s_and_b32 s40, s40, 0xffff ; VI-NEXT: s_and_b32 s41, s41, 0xffff ; VI-NEXT: s_and_b32 s42, s42, 0xffff @@ -239579,63 +236340,63 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a ; VI-NEXT: s_and_b32 s44, s44, 0xffff ; VI-NEXT: s_and_b32 s45, s45, 0xffff ; VI-NEXT: s_and_b32 s46, s46, 0xffff +; VI-NEXT: s_and_b32 s47, s47, 0xffff +; VI-NEXT: s_and_b32 s29, s29, 0xffff ; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s7, s39, s7 +; VI-NEXT: s_or_b32 s9, s39, s9 ; VI-NEXT: s_or_b32 s6, s38, s6 -; VI-NEXT: s_or_b32 s29, s37, s29 -; VI-NEXT: s_or_b32 s28, s36, s28 -; VI-NEXT: s_or_b32 s27, s35, s27 -; VI-NEXT: s_or_b32 s26, s34, s26 -; VI-NEXT: s_or_b32 s25, s31, s25 -; VI-NEXT: s_or_b32 s24, s30, s24 -; VI-NEXT: s_or_b32 s23, vcc_hi, s23 -; VI-NEXT: s_or_b32 s22, vcc_lo, s22 -; VI-NEXT: s_or_b32 s21, s91, s21 -; VI-NEXT: s_or_b32 s20, s90, s20 -; VI-NEXT: s_or_b32 s19, s89, s19 -; VI-NEXT: s_or_b32 s18, s88, s18 -; VI-NEXT: s_or_b32 s17, s79, s17 -; VI-NEXT: s_or_b32 s16, s78, s16 -; VI-NEXT: s_or_b32 s8, s77, s8 -; VI-NEXT: s_or_b32 s9, s76, s9 -; VI-NEXT: s_or_b32 s10, s75, s10 -; VI-NEXT: s_or_b32 s11, s74, s11 -; VI-NEXT: s_or_b32 s12, s73, s12 -; VI-NEXT: s_or_b32 s13, s72, s13 -; VI-NEXT: s_or_b32 s14, s63, s14 -; VI-NEXT: s_or_b32 s15, s62, s15 -; VI-NEXT: s_or_b32 s40, s61, s40 -; VI-NEXT: s_or_b32 s41, s60, s41 -; VI-NEXT: s_or_b32 s42, s59, s42 -; VI-NEXT: s_or_b32 s43, s58, s43 -; VI-NEXT: s_or_b32 s44, s57, s44 -; VI-NEXT: s_or_b32 s45, s56, s45 -; VI-NEXT: s_or_b32 s46, s47, s46 +; VI-NEXT: s_or_b32 s7, s37, s7 +; VI-NEXT: s_or_b32 s8, s36, s8 +; VI-NEXT: s_or_b32 s10, s35, s10 +; VI-NEXT: s_or_b32 s11, s34, s11 +; VI-NEXT: s_or_b32 s12, s31, s12 +; VI-NEXT: s_or_b32 s13, s30, s13 +; VI-NEXT: s_or_b32 s14, vcc_hi, s14 +; VI-NEXT: s_or_b32 s15, vcc_lo, s15 +; VI-NEXT: s_or_b32 s17, s91, s17 +; VI-NEXT: s_or_b32 s19, s90, s19 +; VI-NEXT: s_or_b32 s21, s89, s21 +; VI-NEXT: s_or_b32 s23, s88, s23 +; VI-NEXT: s_or_b32 s25, s79, s25 +; VI-NEXT: s_or_b32 s27, s78, s27 +; VI-NEXT: s_or_b32 s16, s77, s16 +; VI-NEXT: s_or_b32 s18, s76, s18 +; VI-NEXT: s_or_b32 s20, s75, s20 +; VI-NEXT: s_or_b32 s22, s74, s22 +; VI-NEXT: s_or_b32 s24, s73, s24 +; VI-NEXT: s_or_b32 s26, s72, s26 +; VI-NEXT: s_or_b32 s40, s63, s40 +; VI-NEXT: s_or_b32 s41, s62, s41 +; VI-NEXT: s_or_b32 s42, s61, s42 +; VI-NEXT: s_or_b32 s43, s60, s43 +; VI-NEXT: s_or_b32 s44, s59, s44 +; VI-NEXT: s_or_b32 s45, s58, s45 +; VI-NEXT: s_or_b32 s46, s57, s46 +; VI-NEXT: s_or_b32 s47, s56, s47 +; VI-NEXT: s_or_b32 s28, s28, s29 ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s7, s7, 0x30000 +; VI-NEXT: s_add_i32 s9, s9, 0x30000 ; VI-NEXT: s_add_i32 s6, s6, 0x30000 -; VI-NEXT: s_add_i32 s29, s29, 0x30000 -; VI-NEXT: s_add_i32 s28, s28, 0x30000 -; VI-NEXT: s_add_i32 s27, s27, 0x30000 -; VI-NEXT: s_add_i32 s26, s26, 0x30000 -; VI-NEXT: s_add_i32 s25, s25, 0x30000 -; VI-NEXT: s_add_i32 s24, s24, 0x30000 -; VI-NEXT: s_add_i32 s23, s23, 0x30000 -; VI-NEXT: s_add_i32 s22, s22, 0x30000 -; VI-NEXT: s_add_i32 s21, s21, 0x30000 -; VI-NEXT: s_add_i32 s20, s20, 0x30000 -; VI-NEXT: s_add_i32 s19, s19, 0x30000 -; VI-NEXT: s_add_i32 s18, s18, 0x30000 -; VI-NEXT: s_add_i32 s17, s17, 0x30000 -; VI-NEXT: s_add_i32 s16, s16, 0x30000 +; VI-NEXT: s_add_i32 s7, s7, 0x30000 ; VI-NEXT: s_add_i32 s8, s8, 0x30000 -; VI-NEXT: s_add_i32 s9, s9, 0x30000 ; VI-NEXT: s_add_i32 s10, s10, 0x30000 ; VI-NEXT: s_add_i32 s11, s11, 0x30000 ; VI-NEXT: s_add_i32 s12, s12, 0x30000 ; VI-NEXT: s_add_i32 s13, s13, 0x30000 ; VI-NEXT: s_add_i32 s14, s14, 0x30000 ; VI-NEXT: s_add_i32 s15, s15, 0x30000 +; VI-NEXT: s_add_i32 s17, s17, 0x30000 +; VI-NEXT: s_add_i32 s19, s19, 0x30000 +; VI-NEXT: s_add_i32 s21, s21, 0x30000 +; VI-NEXT: s_add_i32 s23, s23, 0x30000 +; VI-NEXT: s_add_i32 s25, s25, 0x30000 +; VI-NEXT: s_add_i32 s27, s27, 0x30000 +; VI-NEXT: s_add_i32 s16, s16, 0x30000 +; VI-NEXT: s_add_i32 s18, s18, 0x30000 +; VI-NEXT: s_add_i32 s20, s20, 0x30000 +; VI-NEXT: s_add_i32 s22, s22, 0x30000 +; VI-NEXT: s_add_i32 s24, s24, 0x30000 +; VI-NEXT: s_add_i32 s26, s26, 0x30000 ; VI-NEXT: s_add_i32 s40, s40, 0x30000 ; VI-NEXT: s_add_i32 s41, s41, 0x30000 ; VI-NEXT: s_add_i32 s42, s42, 0x30000 @@ -239643,40 +236404,42 @@ define inreg <64 x bfloat> @bitcast_v64i16_to_v64bf16_scalar(<64 x i16> inreg %a ; VI-NEXT: s_add_i32 s44, s44, 0x30000 ; VI-NEXT: s_add_i32 s45, s45, 0x30000 ; VI-NEXT: s_add_i32 s46, s46, 0x30000 -; VI-NEXT: s_add_i32 s47, s4, 0x30000 +; VI-NEXT: s_add_i32 s47, s47, 0x30000 +; VI-NEXT: s_add_i32 s56, s28, 0x30000 +; VI-NEXT: s_add_i32 s57, s4, 0x30000 ; VI-NEXT: .LBB107_3: ; %end -; VI-NEXT: v_mov_b32_e32 v0, s16 -; VI-NEXT: v_mov_b32_e32 v1, s17 -; VI-NEXT: v_mov_b32_e32 v2, s18 -; VI-NEXT: v_mov_b32_e32 v3, s19 -; VI-NEXT: v_mov_b32_e32 v4, s20 -; VI-NEXT: v_mov_b32_e32 v5, s21 -; VI-NEXT: v_mov_b32_e32 v6, s22 -; VI-NEXT: v_mov_b32_e32 v7, s23 -; VI-NEXT: v_mov_b32_e32 v8, s24 -; VI-NEXT: v_mov_b32_e32 v9, s25 -; VI-NEXT: v_mov_b32_e32 v10, s26 -; VI-NEXT: v_mov_b32_e32 v11, s27 -; VI-NEXT: v_mov_b32_e32 v12, s28 -; VI-NEXT: v_mov_b32_e32 v13, s29 +; VI-NEXT: v_mov_b32_e32 v0, s27 +; VI-NEXT: v_mov_b32_e32 v1, s25 +; VI-NEXT: v_mov_b32_e32 v2, s23 +; VI-NEXT: v_mov_b32_e32 v3, s21 +; VI-NEXT: v_mov_b32_e32 v4, s19 +; VI-NEXT: v_mov_b32_e32 v5, s17 +; VI-NEXT: v_mov_b32_e32 v6, s15 +; VI-NEXT: v_mov_b32_e32 v7, s14 +; VI-NEXT: v_mov_b32_e32 v8, s13 +; VI-NEXT: v_mov_b32_e32 v9, s12 +; VI-NEXT: v_mov_b32_e32 v10, s11 +; VI-NEXT: v_mov_b32_e32 v11, s10 +; VI-NEXT: v_mov_b32_e32 v12, s8 +; VI-NEXT: v_mov_b32_e32 v13, s7 ; VI-NEXT: v_mov_b32_e32 v14, s6 -; VI-NEXT: v_mov_b32_e32 v15, s7 -; VI-NEXT: v_mov_b32_e32 v16, s47 -; VI-NEXT: v_mov_b32_e32 v17, s46 -; VI-NEXT: v_mov_b32_e32 v18, s45 -; VI-NEXT: v_mov_b32_e32 v19, s44 -; VI-NEXT: v_mov_b32_e32 v20, s43 -; VI-NEXT: v_mov_b32_e32 v21, s42 -; VI-NEXT: v_mov_b32_e32 v22, s41 -; VI-NEXT: v_mov_b32_e32 v23, s40 -; VI-NEXT: v_mov_b32_e32 v24, s15 -; VI-NEXT: v_mov_b32_e32 v25, s14 -; VI-NEXT: v_mov_b32_e32 v26, s13 -; VI-NEXT: v_mov_b32_e32 v27, s12 -; VI-NEXT: v_mov_b32_e32 v28, s11 -; VI-NEXT: v_mov_b32_e32 v29, s10 -; VI-NEXT: v_mov_b32_e32 v30, s9 -; VI-NEXT: v_mov_b32_e32 v31, s8 +; VI-NEXT: v_mov_b32_e32 v15, s9 +; VI-NEXT: v_mov_b32_e32 v16, s57 +; VI-NEXT: v_mov_b32_e32 v17, s56 +; VI-NEXT: v_mov_b32_e32 v18, s47 +; VI-NEXT: v_mov_b32_e32 v19, s46 +; VI-NEXT: v_mov_b32_e32 v20, s45 +; VI-NEXT: v_mov_b32_e32 v21, s44 +; VI-NEXT: v_mov_b32_e32 v22, s43 +; VI-NEXT: v_mov_b32_e32 v23, s42 +; VI-NEXT: v_mov_b32_e32 v24, s41 +; VI-NEXT: v_mov_b32_e32 v25, s40 +; VI-NEXT: v_mov_b32_e32 v26, s26 +; VI-NEXT: v_mov_b32_e32 v27, s24 +; VI-NEXT: v_mov_b32_e32 v28, s22 +; VI-NEXT: v_mov_b32_e32 v29, s20 +; VI-NEXT: v_mov_b32_e32 v30, s18 +; VI-NEXT: v_mov_b32_e32 v31, s16 ; VI-NEXT: v_readlane_b32 s39, v32, 7 ; VI-NEXT: v_readlane_b32 s38, v32, 6 ; VI-NEXT: v_readlane_b32 s37, v32, 5 @@ -244093,120 +240856,146 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i ; VI-NEXT: v_writelane_b32 v32, s35, 3 ; VI-NEXT: v_writelane_b32 v32, s36, 4 ; VI-NEXT: v_writelane_b32 v32, s37, 5 +; VI-NEXT: v_mov_b32_e32 v19, s16 +; VI-NEXT: v_readfirstlane_b32 s57, v2 +; VI-NEXT: v_mov_b32_e32 v2, s17 +; VI-NEXT: v_readfirstlane_b32 s56, v3 +; VI-NEXT: v_mov_b32_e32 v3, s18 +; VI-NEXT: v_readfirstlane_b32 s47, v4 +; VI-NEXT: v_mov_b32_e32 v4, s19 +; VI-NEXT: v_readfirstlane_b32 s46, v5 +; VI-NEXT: v_mov_b32_e32 v5, s20 +; VI-NEXT: v_readfirstlane_b32 s45, v6 +; VI-NEXT: v_mov_b32_e32 v6, s21 +; VI-NEXT: v_readfirstlane_b32 s44, v7 +; VI-NEXT: v_mov_b32_e32 v7, s22 +; VI-NEXT: v_readfirstlane_b32 s43, v8 +; VI-NEXT: v_mov_b32_e32 v8, s23 +; VI-NEXT: v_readfirstlane_b32 s42, v9 +; VI-NEXT: v_mov_b32_e32 v9, s24 +; VI-NEXT: v_readfirstlane_b32 s41, v10 +; VI-NEXT: v_mov_b32_e32 v10, s25 +; VI-NEXT: v_readfirstlane_b32 s40, v11 +; VI-NEXT: v_mov_b32_e32 v11, s26 +; VI-NEXT: v_readfirstlane_b32 s26, v12 +; VI-NEXT: v_mov_b32_e32 v12, s27 +; VI-NEXT: v_readfirstlane_b32 s24, v13 +; VI-NEXT: v_mov_b32_e32 v13, s28 +; VI-NEXT: v_readfirstlane_b32 s22, v14 +; VI-NEXT: v_mov_b32_e32 v14, s29 ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18 ; VI-NEXT: v_writelane_b32 v32, s38, 6 -; VI-NEXT: v_readfirstlane_b32 s47, v2 -; VI-NEXT: v_readfirstlane_b32 s46, v3 -; VI-NEXT: v_readfirstlane_b32 s45, v4 -; VI-NEXT: v_readfirstlane_b32 s44, v5 -; VI-NEXT: v_readfirstlane_b32 s43, v6 -; VI-NEXT: v_readfirstlane_b32 s42, v7 -; VI-NEXT: v_readfirstlane_b32 s41, v8 -; VI-NEXT: v_readfirstlane_b32 s40, v9 -; VI-NEXT: v_readfirstlane_b32 s15, v10 -; VI-NEXT: v_readfirstlane_b32 s14, v11 -; VI-NEXT: v_readfirstlane_b32 s13, v12 -; VI-NEXT: v_readfirstlane_b32 s12, v13 -; VI-NEXT: v_readfirstlane_b32 s11, v14 -; VI-NEXT: v_readfirstlane_b32 s10, v15 -; VI-NEXT: v_readfirstlane_b32 s9, v16 -; VI-NEXT: v_readfirstlane_b32 s8, v17 +; VI-NEXT: v_readfirstlane_b32 s20, v15 +; VI-NEXT: v_readfirstlane_b32 s18, v16 +; VI-NEXT: v_readfirstlane_b32 s16, v17 +; VI-NEXT: v_readfirstlane_b32 s27, v19 +; VI-NEXT: v_readfirstlane_b32 s25, v2 +; VI-NEXT: v_readfirstlane_b32 s23, v3 +; VI-NEXT: v_readfirstlane_b32 s21, v4 +; VI-NEXT: v_readfirstlane_b32 s19, v5 +; VI-NEXT: v_readfirstlane_b32 s17, v6 +; VI-NEXT: v_readfirstlane_b32 s15, v7 +; VI-NEXT: v_readfirstlane_b32 s14, v8 +; VI-NEXT: v_readfirstlane_b32 s13, v9 +; VI-NEXT: v_readfirstlane_b32 s12, v10 +; VI-NEXT: v_readfirstlane_b32 s11, v11 +; VI-NEXT: v_readfirstlane_b32 s10, v12 +; VI-NEXT: v_readfirstlane_b32 s8, v13 +; VI-NEXT: v_readfirstlane_b32 s7, v14 ; VI-NEXT: v_readfirstlane_b32 s6, v0 ; VI-NEXT: s_and_b64 s[4:5], vcc, exec -; VI-NEXT: v_readfirstlane_b32 s7, v1 +; VI-NEXT: v_readfirstlane_b32 s9, v1 ; VI-NEXT: v_writelane_b32 v32, s39, 7 ; VI-NEXT: s_cbranch_scc0 .LBB111_4 ; VI-NEXT: ; %bb.1: ; %cmp.false ; VI-NEXT: s_cbranch_execnz .LBB111_3 ; VI-NEXT: .LBB111_2: ; %cmp.true -; VI-NEXT: s_and_b32 s4, s47, 0xffff0000 -; VI-NEXT: s_add_i32 s5, s47, 3 -; VI-NEXT: s_and_b32 s47, s46, 0xffff0000 +; VI-NEXT: s_and_b32 s4, s57, 0xffff0000 +; VI-NEXT: s_add_i32 s5, s57, 3 +; VI-NEXT: s_and_b32 s28, s56, 0xffff0000 +; VI-NEXT: s_add_i32 s29, s56, 3 +; VI-NEXT: s_and_b32 s56, s47, 0xffff0000 +; VI-NEXT: s_add_i32 s47, s47, 3 +; VI-NEXT: s_and_b32 s57, s46, 0xffff0000 ; VI-NEXT: s_add_i32 s46, s46, 3 -; VI-NEXT: s_and_b32 s56, s45, 0xffff0000 +; VI-NEXT: s_and_b32 s58, s45, 0xffff0000 ; VI-NEXT: s_add_i32 s45, s45, 3 -; VI-NEXT: s_and_b32 s57, s44, 0xffff0000 +; VI-NEXT: s_and_b32 s59, s44, 0xffff0000 ; VI-NEXT: s_add_i32 s44, s44, 3 -; VI-NEXT: s_and_b32 s58, s43, 0xffff0000 +; VI-NEXT: s_and_b32 s60, s43, 0xffff0000 ; VI-NEXT: s_add_i32 s43, s43, 3 -; VI-NEXT: s_and_b32 s59, s42, 0xffff0000 +; VI-NEXT: s_and_b32 s61, s42, 0xffff0000 ; VI-NEXT: s_add_i32 s42, s42, 3 -; VI-NEXT: s_and_b32 s60, s41, 0xffff0000 +; VI-NEXT: s_and_b32 s62, s41, 0xffff0000 ; VI-NEXT: s_add_i32 s41, s41, 3 -; VI-NEXT: s_and_b32 s61, s40, 0xffff0000 +; VI-NEXT: s_and_b32 s63, s40, 0xffff0000 ; VI-NEXT: s_add_i32 s40, s40, 3 -; VI-NEXT: s_and_b32 s62, s15, 0xffff0000 +; VI-NEXT: s_and_b32 s72, s26, 0xffff0000 +; VI-NEXT: s_add_i32 s26, s26, 3 +; VI-NEXT: s_and_b32 s73, s24, 0xffff0000 +; VI-NEXT: s_add_i32 s24, s24, 3 +; VI-NEXT: s_and_b32 s74, s22, 0xffff0000 +; VI-NEXT: s_add_i32 s22, s22, 3 +; VI-NEXT: s_and_b32 s75, s20, 0xffff0000 +; VI-NEXT: s_add_i32 s20, s20, 3 +; VI-NEXT: s_and_b32 s76, s18, 0xffff0000 +; VI-NEXT: s_add_i32 s18, s18, 3 +; VI-NEXT: s_and_b32 s77, s16, 0xffff0000 +; VI-NEXT: s_add_i32 s16, s16, 3 +; VI-NEXT: s_and_b32 s78, s27, 0xffff0000 +; VI-NEXT: s_add_i32 s27, s27, 3 +; VI-NEXT: s_and_b32 s79, s25, 0xffff0000 +; VI-NEXT: s_add_i32 s25, s25, 3 +; VI-NEXT: s_and_b32 s88, s23, 0xffff0000 +; VI-NEXT: s_add_i32 s23, s23, 3 +; VI-NEXT: s_and_b32 s89, s21, 0xffff0000 +; VI-NEXT: s_add_i32 s21, s21, 3 +; VI-NEXT: s_and_b32 s90, s19, 0xffff0000 +; VI-NEXT: s_add_i32 s19, s19, 3 +; VI-NEXT: s_and_b32 s91, s17, 0xffff0000 +; VI-NEXT: s_add_i32 s17, s17, 3 +; VI-NEXT: s_and_b32 vcc_lo, s15, 0xffff0000 ; VI-NEXT: s_add_i32 s15, s15, 3 -; VI-NEXT: s_and_b32 s63, s14, 0xffff0000 +; VI-NEXT: s_and_b32 vcc_hi, s14, 0xffff0000 ; VI-NEXT: s_add_i32 s14, s14, 3 -; VI-NEXT: s_and_b32 s72, s13, 0xffff0000 +; VI-NEXT: s_and_b32 s30, s13, 0xffff0000 ; VI-NEXT: s_add_i32 s13, s13, 3 -; VI-NEXT: s_and_b32 s73, s12, 0xffff0000 +; VI-NEXT: s_and_b32 s31, s12, 0xffff0000 ; VI-NEXT: s_add_i32 s12, s12, 3 -; VI-NEXT: s_and_b32 s74, s11, 0xffff0000 +; VI-NEXT: s_and_b32 s34, s11, 0xffff0000 ; VI-NEXT: s_add_i32 s11, s11, 3 -; VI-NEXT: s_and_b32 s75, s10, 0xffff0000 +; VI-NEXT: s_and_b32 s35, s10, 0xffff0000 ; VI-NEXT: s_add_i32 s10, s10, 3 -; VI-NEXT: s_and_b32 s76, s9, 0xffff0000 -; VI-NEXT: s_add_i32 s9, s9, 3 -; VI-NEXT: s_and_b32 s77, s8, 0xffff0000 +; VI-NEXT: s_and_b32 s36, s8, 0xffff0000 ; VI-NEXT: s_add_i32 s8, s8, 3 -; VI-NEXT: s_and_b32 s78, s16, 0xffff0000 -; VI-NEXT: s_add_i32 s16, s16, 3 -; VI-NEXT: s_and_b32 s79, s17, 0xffff0000 -; VI-NEXT: s_add_i32 s17, s17, 3 -; VI-NEXT: s_and_b32 s88, s18, 0xffff0000 -; VI-NEXT: s_add_i32 s18, s18, 3 -; VI-NEXT: s_and_b32 s89, s19, 0xffff0000 -; VI-NEXT: s_add_i32 s19, s19, 3 -; VI-NEXT: s_and_b32 s90, s20, 0xffff0000 -; VI-NEXT: s_add_i32 s20, s20, 3 -; VI-NEXT: s_and_b32 s91, s21, 0xffff0000 -; VI-NEXT: s_add_i32 s21, s21, 3 -; VI-NEXT: s_and_b32 vcc_lo, s22, 0xffff0000 -; VI-NEXT: s_add_i32 s22, s22, 3 -; VI-NEXT: s_and_b32 vcc_hi, s23, 0xffff0000 -; VI-NEXT: s_add_i32 s23, s23, 3 -; VI-NEXT: s_and_b32 s30, s24, 0xffff0000 -; VI-NEXT: s_add_i32 s24, s24, 3 -; VI-NEXT: s_and_b32 s31, s25, 0xffff0000 -; VI-NEXT: s_add_i32 s25, s25, 3 -; VI-NEXT: s_and_b32 s34, s26, 0xffff0000 -; VI-NEXT: s_add_i32 s26, s26, 3 -; VI-NEXT: s_and_b32 s35, s27, 0xffff0000 -; VI-NEXT: s_add_i32 s27, s27, 3 -; VI-NEXT: s_and_b32 s36, s28, 0xffff0000 -; VI-NEXT: s_add_i32 s28, s28, 3 -; VI-NEXT: s_and_b32 s37, s29, 0xffff0000 -; VI-NEXT: s_add_i32 s29, s29, 3 +; VI-NEXT: s_and_b32 s37, s7, 0xffff0000 +; VI-NEXT: s_add_i32 s7, s7, 3 ; VI-NEXT: s_and_b32 s38, s6, 0xffff0000 ; VI-NEXT: s_add_i32 s6, s6, 3 -; VI-NEXT: s_and_b32 s39, s7, 0xffff0000 -; VI-NEXT: s_add_i32 s7, s7, 3 -; VI-NEXT: s_and_b32 s7, s7, 0xffff +; VI-NEXT: s_and_b32 s39, s9, 0xffff0000 +; VI-NEXT: s_add_i32 s9, s9, 3 +; VI-NEXT: s_and_b32 s9, s9, 0xffff ; VI-NEXT: s_and_b32 s6, s6, 0xffff -; VI-NEXT: s_and_b32 s29, s29, 0xffff -; VI-NEXT: s_and_b32 s28, s28, 0xffff -; VI-NEXT: s_and_b32 s27, s27, 0xffff -; VI-NEXT: s_and_b32 s26, s26, 0xffff -; VI-NEXT: s_and_b32 s25, s25, 0xffff -; VI-NEXT: s_and_b32 s24, s24, 0xffff -; VI-NEXT: s_and_b32 s23, s23, 0xffff -; VI-NEXT: s_and_b32 s22, s22, 0xffff -; VI-NEXT: s_and_b32 s21, s21, 0xffff -; VI-NEXT: s_and_b32 s20, s20, 0xffff -; VI-NEXT: s_and_b32 s19, s19, 0xffff -; VI-NEXT: s_and_b32 s18, s18, 0xffff -; VI-NEXT: s_and_b32 s17, s17, 0xffff -; VI-NEXT: s_and_b32 s16, s16, 0xffff +; VI-NEXT: s_and_b32 s7, s7, 0xffff ; VI-NEXT: s_and_b32 s8, s8, 0xffff -; VI-NEXT: s_and_b32 s9, s9, 0xffff ; VI-NEXT: s_and_b32 s10, s10, 0xffff ; VI-NEXT: s_and_b32 s11, s11, 0xffff ; VI-NEXT: s_and_b32 s12, s12, 0xffff ; VI-NEXT: s_and_b32 s13, s13, 0xffff ; VI-NEXT: s_and_b32 s14, s14, 0xffff ; VI-NEXT: s_and_b32 s15, s15, 0xffff +; VI-NEXT: s_and_b32 s17, s17, 0xffff +; VI-NEXT: s_and_b32 s19, s19, 0xffff +; VI-NEXT: s_and_b32 s21, s21, 0xffff +; VI-NEXT: s_and_b32 s23, s23, 0xffff +; VI-NEXT: s_and_b32 s25, s25, 0xffff +; VI-NEXT: s_and_b32 s27, s27, 0xffff +; VI-NEXT: s_and_b32 s16, s16, 0xffff +; VI-NEXT: s_and_b32 s18, s18, 0xffff +; VI-NEXT: s_and_b32 s20, s20, 0xffff +; VI-NEXT: s_and_b32 s22, s22, 0xffff +; VI-NEXT: s_and_b32 s24, s24, 0xffff +; VI-NEXT: s_and_b32 s26, s26, 0xffff ; VI-NEXT: s_and_b32 s40, s40, 0xffff ; VI-NEXT: s_and_b32 s41, s41, 0xffff ; VI-NEXT: s_and_b32 s42, s42, 0xffff @@ -244214,63 +241003,63 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i ; VI-NEXT: s_and_b32 s44, s44, 0xffff ; VI-NEXT: s_and_b32 s45, s45, 0xffff ; VI-NEXT: s_and_b32 s46, s46, 0xffff +; VI-NEXT: s_and_b32 s47, s47, 0xffff +; VI-NEXT: s_and_b32 s29, s29, 0xffff ; VI-NEXT: s_and_b32 s5, s5, 0xffff -; VI-NEXT: s_or_b32 s7, s39, s7 +; VI-NEXT: s_or_b32 s9, s39, s9 ; VI-NEXT: s_or_b32 s6, s38, s6 -; VI-NEXT: s_or_b32 s29, s37, s29 -; VI-NEXT: s_or_b32 s28, s36, s28 -; VI-NEXT: s_or_b32 s27, s35, s27 -; VI-NEXT: s_or_b32 s26, s34, s26 -; VI-NEXT: s_or_b32 s25, s31, s25 -; VI-NEXT: s_or_b32 s24, s30, s24 -; VI-NEXT: s_or_b32 s23, vcc_hi, s23 -; VI-NEXT: s_or_b32 s22, vcc_lo, s22 -; VI-NEXT: s_or_b32 s21, s91, s21 -; VI-NEXT: s_or_b32 s20, s90, s20 -; VI-NEXT: s_or_b32 s19, s89, s19 -; VI-NEXT: s_or_b32 s18, s88, s18 -; VI-NEXT: s_or_b32 s17, s79, s17 -; VI-NEXT: s_or_b32 s16, s78, s16 -; VI-NEXT: s_or_b32 s8, s77, s8 -; VI-NEXT: s_or_b32 s9, s76, s9 -; VI-NEXT: s_or_b32 s10, s75, s10 -; VI-NEXT: s_or_b32 s11, s74, s11 -; VI-NEXT: s_or_b32 s12, s73, s12 -; VI-NEXT: s_or_b32 s13, s72, s13 -; VI-NEXT: s_or_b32 s14, s63, s14 -; VI-NEXT: s_or_b32 s15, s62, s15 -; VI-NEXT: s_or_b32 s40, s61, s40 -; VI-NEXT: s_or_b32 s41, s60, s41 -; VI-NEXT: s_or_b32 s42, s59, s42 -; VI-NEXT: s_or_b32 s43, s58, s43 -; VI-NEXT: s_or_b32 s44, s57, s44 -; VI-NEXT: s_or_b32 s45, s56, s45 -; VI-NEXT: s_or_b32 s46, s47, s46 +; VI-NEXT: s_or_b32 s7, s37, s7 +; VI-NEXT: s_or_b32 s8, s36, s8 +; VI-NEXT: s_or_b32 s10, s35, s10 +; VI-NEXT: s_or_b32 s11, s34, s11 +; VI-NEXT: s_or_b32 s12, s31, s12 +; VI-NEXT: s_or_b32 s13, s30, s13 +; VI-NEXT: s_or_b32 s14, vcc_hi, s14 +; VI-NEXT: s_or_b32 s15, vcc_lo, s15 +; VI-NEXT: s_or_b32 s17, s91, s17 +; VI-NEXT: s_or_b32 s19, s90, s19 +; VI-NEXT: s_or_b32 s21, s89, s21 +; VI-NEXT: s_or_b32 s23, s88, s23 +; VI-NEXT: s_or_b32 s25, s79, s25 +; VI-NEXT: s_or_b32 s27, s78, s27 +; VI-NEXT: s_or_b32 s16, s77, s16 +; VI-NEXT: s_or_b32 s18, s76, s18 +; VI-NEXT: s_or_b32 s20, s75, s20 +; VI-NEXT: s_or_b32 s22, s74, s22 +; VI-NEXT: s_or_b32 s24, s73, s24 +; VI-NEXT: s_or_b32 s26, s72, s26 +; VI-NEXT: s_or_b32 s40, s63, s40 +; VI-NEXT: s_or_b32 s41, s62, s41 +; VI-NEXT: s_or_b32 s42, s61, s42 +; VI-NEXT: s_or_b32 s43, s60, s43 +; VI-NEXT: s_or_b32 s44, s59, s44 +; VI-NEXT: s_or_b32 s45, s58, s45 +; VI-NEXT: s_or_b32 s46, s57, s46 +; VI-NEXT: s_or_b32 s47, s56, s47 +; VI-NEXT: s_or_b32 s28, s28, s29 ; VI-NEXT: s_or_b32 s4, s4, s5 -; VI-NEXT: s_add_i32 s7, s7, 0x30000 +; VI-NEXT: s_add_i32 s9, s9, 0x30000 ; VI-NEXT: s_add_i32 s6, s6, 0x30000 -; VI-NEXT: s_add_i32 s29, s29, 0x30000 -; VI-NEXT: s_add_i32 s28, s28, 0x30000 -; VI-NEXT: s_add_i32 s27, s27, 0x30000 -; VI-NEXT: s_add_i32 s26, s26, 0x30000 -; VI-NEXT: s_add_i32 s25, s25, 0x30000 -; VI-NEXT: s_add_i32 s24, s24, 0x30000 -; VI-NEXT: s_add_i32 s23, s23, 0x30000 -; VI-NEXT: s_add_i32 s22, s22, 0x30000 -; VI-NEXT: s_add_i32 s21, s21, 0x30000 -; VI-NEXT: s_add_i32 s20, s20, 0x30000 -; VI-NEXT: s_add_i32 s19, s19, 0x30000 -; VI-NEXT: s_add_i32 s18, s18, 0x30000 -; VI-NEXT: s_add_i32 s17, s17, 0x30000 -; VI-NEXT: s_add_i32 s16, s16, 0x30000 +; VI-NEXT: s_add_i32 s7, s7, 0x30000 ; VI-NEXT: s_add_i32 s8, s8, 0x30000 -; VI-NEXT: s_add_i32 s9, s9, 0x30000 ; VI-NEXT: s_add_i32 s10, s10, 0x30000 ; VI-NEXT: s_add_i32 s11, s11, 0x30000 ; VI-NEXT: s_add_i32 s12, s12, 0x30000 ; VI-NEXT: s_add_i32 s13, s13, 0x30000 ; VI-NEXT: s_add_i32 s14, s14, 0x30000 ; VI-NEXT: s_add_i32 s15, s15, 0x30000 +; VI-NEXT: s_add_i32 s17, s17, 0x30000 +; VI-NEXT: s_add_i32 s19, s19, 0x30000 +; VI-NEXT: s_add_i32 s21, s21, 0x30000 +; VI-NEXT: s_add_i32 s23, s23, 0x30000 +; VI-NEXT: s_add_i32 s25, s25, 0x30000 +; VI-NEXT: s_add_i32 s27, s27, 0x30000 +; VI-NEXT: s_add_i32 s16, s16, 0x30000 +; VI-NEXT: s_add_i32 s18, s18, 0x30000 +; VI-NEXT: s_add_i32 s20, s20, 0x30000 +; VI-NEXT: s_add_i32 s22, s22, 0x30000 +; VI-NEXT: s_add_i32 s24, s24, 0x30000 +; VI-NEXT: s_add_i32 s26, s26, 0x30000 ; VI-NEXT: s_add_i32 s40, s40, 0x30000 ; VI-NEXT: s_add_i32 s41, s41, 0x30000 ; VI-NEXT: s_add_i32 s42, s42, 0x30000 @@ -244278,40 +241067,42 @@ define inreg <64 x half> @bitcast_v64i16_to_v64f16_scalar(<64 x i16> inreg %a, i ; VI-NEXT: s_add_i32 s44, s44, 0x30000 ; VI-NEXT: s_add_i32 s45, s45, 0x30000 ; VI-NEXT: s_add_i32 s46, s46, 0x30000 -; VI-NEXT: s_add_i32 s47, s4, 0x30000 +; VI-NEXT: s_add_i32 s47, s47, 0x30000 +; VI-NEXT: s_add_i32 s56, s28, 0x30000 +; VI-NEXT: s_add_i32 s57, s4, 0x30000 ; VI-NEXT: .LBB111_3: ; %end -; VI-NEXT: v_mov_b32_e32 v0, s16 -; VI-NEXT: v_mov_b32_e32 v1, s17 -; VI-NEXT: v_mov_b32_e32 v2, s18 -; VI-NEXT: v_mov_b32_e32 v3, s19 -; VI-NEXT: v_mov_b32_e32 v4, s20 -; VI-NEXT: v_mov_b32_e32 v5, s21 -; VI-NEXT: v_mov_b32_e32 v6, s22 -; VI-NEXT: v_mov_b32_e32 v7, s23 -; VI-NEXT: v_mov_b32_e32 v8, s24 -; VI-NEXT: v_mov_b32_e32 v9, s25 -; VI-NEXT: v_mov_b32_e32 v10, s26 -; VI-NEXT: v_mov_b32_e32 v11, s27 -; VI-NEXT: v_mov_b32_e32 v12, s28 -; VI-NEXT: v_mov_b32_e32 v13, s29 +; VI-NEXT: v_mov_b32_e32 v0, s27 +; VI-NEXT: v_mov_b32_e32 v1, s25 +; VI-NEXT: v_mov_b32_e32 v2, s23 +; VI-NEXT: v_mov_b32_e32 v3, s21 +; VI-NEXT: v_mov_b32_e32 v4, s19 +; VI-NEXT: v_mov_b32_e32 v5, s17 +; VI-NEXT: v_mov_b32_e32 v6, s15 +; VI-NEXT: v_mov_b32_e32 v7, s14 +; VI-NEXT: v_mov_b32_e32 v8, s13 +; VI-NEXT: v_mov_b32_e32 v9, s12 +; VI-NEXT: v_mov_b32_e32 v10, s11 +; VI-NEXT: v_mov_b32_e32 v11, s10 +; VI-NEXT: v_mov_b32_e32 v12, s8 +; VI-NEXT: v_mov_b32_e32 v13, s7 ; VI-NEXT: v_mov_b32_e32 v14, s6 -; VI-NEXT: v_mov_b32_e32 v15, s7 -; VI-NEXT: v_mov_b32_e32 v16, s47 -; VI-NEXT: v_mov_b32_e32 v17, s46 -; VI-NEXT: v_mov_b32_e32 v18, s45 -; VI-NEXT: v_mov_b32_e32 v19, s44 -; VI-NEXT: v_mov_b32_e32 v20, s43 -; VI-NEXT: v_mov_b32_e32 v21, s42 -; VI-NEXT: v_mov_b32_e32 v22, s41 -; VI-NEXT: v_mov_b32_e32 v23, s40 -; VI-NEXT: v_mov_b32_e32 v24, s15 -; VI-NEXT: v_mov_b32_e32 v25, s14 -; VI-NEXT: v_mov_b32_e32 v26, s13 -; VI-NEXT: v_mov_b32_e32 v27, s12 -; VI-NEXT: v_mov_b32_e32 v28, s11 -; VI-NEXT: v_mov_b32_e32 v29, s10 -; VI-NEXT: v_mov_b32_e32 v30, s9 -; VI-NEXT: v_mov_b32_e32 v31, s8 +; VI-NEXT: v_mov_b32_e32 v15, s9 +; VI-NEXT: v_mov_b32_e32 v16, s57 +; VI-NEXT: v_mov_b32_e32 v17, s56 +; VI-NEXT: v_mov_b32_e32 v18, s47 +; VI-NEXT: v_mov_b32_e32 v19, s46 +; VI-NEXT: v_mov_b32_e32 v20, s45 +; VI-NEXT: v_mov_b32_e32 v21, s44 +; VI-NEXT: v_mov_b32_e32 v22, s43 +; VI-NEXT: v_mov_b32_e32 v23, s42 +; VI-NEXT: v_mov_b32_e32 v24, s41 +; VI-NEXT: v_mov_b32_e32 v25, s40 +; VI-NEXT: v_mov_b32_e32 v26, s26 +; VI-NEXT: v_mov_b32_e32 v27, s24 +; VI-NEXT: v_mov_b32_e32 v28, s22 +; VI-NEXT: v_mov_b32_e32 v29, s20 +; VI-NEXT: v_mov_b32_e32 v30, s18 +; VI-NEXT: v_mov_b32_e32 v31, s16 ; VI-NEXT: v_readlane_b32 s39, v32, 7 ; VI-NEXT: v_readlane_b32 s38, v32, 6 ; VI-NEXT: v_readlane_b32 s37, v32, 5 |