1 files changed, 30 insertions, 12 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-srl-and.ll b/llvm/test/CodeGen/AArch64/arm64-srl-and.ll
index b58f6ba..330f27b 100644
--- a/llvm/test/CodeGen/AArch64/arm64-srl-and.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-srl-and.ll
@@ -1,22 +1,38 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -O3 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -O3 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64-linux-gnu -O3 -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
 ; This used to miscompile:
 ; The 16-bit -1 should not become 32-bit -1 (sub w8, w8, #1).
 
 @g = global i16 0, align 4
 define i32 @srl_and()  {
-; CHECK-LABEL: srl_and:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    adrp x8, :got:g
-; CHECK-NEXT:    mov w9, #50
-; CHECK-NEXT:    ldr x8, [x8, :got_lo12:g]
-; CHECK-NEXT:    ldrh w8, [x8]
-; CHECK-NEXT:    eor w8, w8, w9
-; CHECK-NEXT:    mov w9, #65535
-; CHECK-NEXT:    add w8, w8, w9
-; CHECK-NEXT:    and w0, w8, w8, lsr #16
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: srl_and:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    adrp x8, :got:g
+; CHECK-SD-NEXT:    mov w9, #50 // =0x32
+; CHECK-SD-NEXT:    ldr x8, [x8, :got_lo12:g]
+; CHECK-SD-NEXT:    ldrh w8, [x8]
+; CHECK-SD-NEXT:    eor w8, w8, w9
+; CHECK-SD-NEXT:    mov w9, #65535 // =0xffff
+; CHECK-SD-NEXT:    add w8, w8, w9
+; CHECK-SD-NEXT:    and w0, w8, w8, lsr #16
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: srl_and:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    adrp x8, :got:g
+; CHECK-GI-NEXT:    mov w9, #50 // =0x32
+; CHECK-GI-NEXT:    ldr x8, [x8, :got_lo12:g]
+; CHECK-GI-NEXT:    ldrh w8, [x8]
+; CHECK-GI-NEXT:    eor w8, w8, w9
+; CHECK-GI-NEXT:    mov w9, #65535 // =0xffff
+; CHECK-GI-NEXT:    add w8, w9, w8, uxth
+; CHECK-GI-NEXT:    and w9, w8, #0xffff
+; CHECK-GI-NEXT:    cmp w8, w9
+; CHECK-GI-NEXT:    cset w8, ne
+; CHECK-GI-NEXT:    and w0, w9, w8
+; CHECK-GI-NEXT:    ret
 entry:
   %0 = load i16, ptr @g, align 4
   %1 = xor i16 %0, 50
@@ -29,3 +45,5 @@ entry:
 
   ret i32 %and
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}