diff options
Diffstat (limited to 'llvm/lib/TargetParser')
| -rw-r--r-- | llvm/lib/TargetParser/AArch64TargetParser.cpp | 31 | ||||
| -rw-r--r-- | llvm/lib/TargetParser/Host.cpp | 94 | ||||
| -rw-r--r-- | llvm/lib/TargetParser/PPCTargetParser.cpp | 15 | ||||
| -rw-r--r-- | llvm/lib/TargetParser/RISCVISAInfo.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/TargetParser/TargetDataLayout.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/TargetParser/TargetParser.cpp | 56 | ||||
| -rw-r--r-- | llvm/lib/TargetParser/X86TargetParser.cpp | 36 | ||||
| -rw-r--r-- | llvm/lib/TargetParser/XtensaTargetParser.cpp | 1 |
8 files changed, 177 insertions, 58 deletions
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp index 7e35832..2c0211b 100644 --- a/llvm/lib/TargetParser/AArch64TargetParser.cpp +++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp @@ -55,21 +55,30 @@ std::optional<AArch64::FMVInfo> lookupFMVByID(AArch64::ArchExtKind ExtID) { return {}; } +std::optional<AArch64::FMVInfo> getFMVInfoFrom(StringRef Feature) { + std::optional<AArch64::FMVInfo> FMV = AArch64::parseFMVExtension(Feature); + if (!FMV && Feature.starts_with('+')) + if (std::optional<AArch64::ExtensionInfo> Ext = + AArch64::targetFeatureToExtension(Feature)) + FMV = lookupFMVByID(Ext->ID); + return FMV; +} + APInt AArch64::getFMVPriority(ArrayRef<StringRef> Features) { // Transitively enable the Arch Extensions which correspond to each feature. ExtensionSet FeatureBits; + APInt PriorityMask = APInt::getZero(128); for (const StringRef Feature : Features) { - std::optional<FMVInfo> FMV = parseFMVExtension(Feature); - if (!FMV && Feature.starts_with('+')) { - if (std::optional<ExtensionInfo> Info = targetFeatureToExtension(Feature)) - FMV = lookupFMVByID(Info->ID); + if (std::optional<FMVInfo> FMV = getFMVInfoFrom(Feature)) { + // FMV feature without a corresponding Arch Extension may affect priority + if (FMV->ID) + FeatureBits.enable(*FMV->ID); + else + PriorityMask.setBit(FMV->PriorityBit); } - if (FMV && FMV->ID) - FeatureBits.enable(*FMV->ID); } // Construct a bitmask for all the transitively enabled Arch Extensions. - APInt PriorityMask = APInt::getZero(128); for (const FMVInfo &Info : getFMVInfo()) if (Info.ID && FeatureBits.Enabled.test(*Info.ID)) PriorityMask.setBit(Info.PriorityBit); @@ -81,15 +90,15 @@ APInt AArch64::getCpuSupportsMask(ArrayRef<StringRef> Features) { // Transitively enable the Arch Extensions which correspond to each feature. ExtensionSet FeatureBits; for (const StringRef Feature : Features) - if (std::optional<FMVInfo> Info = parseFMVExtension(Feature)) - if (Info->ID) - FeatureBits.enable(*Info->ID); + if (std::optional<FMVInfo> FMV = getFMVInfoFrom(Feature)) + if (FMV->ID) + FeatureBits.enable(*FMV->ID); // Construct a bitmask for all the transitively enabled Arch Extensions. APInt FeaturesMask = APInt::getZero(128); for (const FMVInfo &Info : getFMVInfo()) if (Info.ID && FeatureBits.Enabled.test(*Info.ID)) - FeaturesMask.setBit(Info.FeatureBit); + FeaturesMask.setBit(*Info.FeatureBit); return FeaturesMask; } diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp index 0849fc7..cb793d6 100644 --- a/llvm/lib/TargetParser/Host.cpp +++ b/llvm/lib/TargetParser/Host.cpp @@ -512,11 +512,11 @@ StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { // Look for the CPU features. SmallVector<StringRef, 32> CPUFeatures; - for (unsigned I = 0, E = Lines.size(); I != E; ++I) - if (Lines[I].starts_with("features")) { - size_t Pos = Lines[I].find(':'); + for (StringRef Line : Lines) + if (Line.starts_with("features")) { + size_t Pos = Line.find(':'); if (Pos != StringRef::npos) { - Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); + Line.drop_front(Pos + 1).split(CPUFeatures, ' '); break; } } @@ -524,20 +524,16 @@ StringRef sys::detail::getHostCPUNameForS390x(StringRef ProcCpuinfoContent) { // We need to check for the presence of vector support independently of // the machine type, since we may only use the vector register set when // supported by the kernel (and hypervisor). - bool HaveVectorSupport = false; - for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { - if (CPUFeatures[I] == "vx") - HaveVectorSupport = true; - } + bool HaveVectorSupport = llvm::is_contained(CPUFeatures, "vx"); // Now check the processor machine type. - for (unsigned I = 0, E = Lines.size(); I != E; ++I) { - if (Lines[I].starts_with("processor ")) { - size_t Pos = Lines[I].find("machine = "); + for (StringRef Line : Lines) { + if (Line.starts_with("processor ")) { + size_t Pos = Line.find("machine = "); if (Pos != StringRef::npos) { Pos += sizeof("machine = ") - 1; unsigned int Id; - if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) + if (!Line.drop_front(Pos).getAsInteger(10, Id)) return getCPUNameFromS390Model(Id, HaveVectorSupport); } break; @@ -554,9 +550,9 @@ StringRef sys::detail::getHostCPUNameForRISCV(StringRef ProcCpuinfoContent) { // Look for uarch line to determine cpu name StringRef UArch; - for (unsigned I = 0, E = Lines.size(); I != E; ++I) { - if (Lines[I].starts_with("uarch")) { - UArch = Lines[I].substr(5).ltrim("\t :"); + for (StringRef Line : Lines) { + if (Line.starts_with("uarch")) { + UArch = Line.substr(5).ltrim("\t :"); break; } } @@ -2192,7 +2188,6 @@ StringMap<bool> sys::getHostCPUFeatures() { bool HasLeaf1E = MaxLevel >= 0x1e && !getX86CpuIDAndInfoEx(0x1e, 0x1, &EAX, &EBX, &ECX, &EDX); Features["amx-fp8"] = HasLeaf1E && ((EAX >> 4) & 1) && HasAMXSave; - Features["amx-transpose"] = HasLeaf1E && ((EAX >> 5) & 1) && HasAMXSave; Features["amx-tf32"] = HasLeaf1E && ((EAX >> 6) & 1) && HasAMXSave; Features["amx-avx512"] = HasLeaf1E && ((EAX >> 7) & 1) && HasAMXSave; Features["amx-movrs"] = HasLeaf1E && ((EAX >> 8) & 1) && HasAMXSave; @@ -2282,20 +2277,81 @@ StringMap<bool> sys::getHostCPUFeatures() { uint32_t Sha2 = CAP_SHA1 | CAP_SHA2; Features["aes"] = (crypto & Aes) == Aes; Features["sha2"] = (crypto & Sha2) == Sha2; + + // Even if an underlying core supports SVE, it might not be available if + // it's disabled by the OS, or some other layer. Disable SVE if we don't + // detect support at runtime. + if (!Features.contains("sve")) + Features["sve"] = false; #endif return Features; } #elif defined(_WIN32) && (defined(__aarch64__) || defined(_M_ARM64) || \ defined(__arm64ec__) || defined(_M_ARM64EC)) +#ifndef PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE +#define PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE 43 +#endif +#ifndef PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE +#define PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE 44 +#endif +#ifndef PF_ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE +#define PF_ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE 45 +#endif +#ifndef PF_ARM_SVE_INSTRUCTIONS_AVAILABLE +#define PF_ARM_SVE_INSTRUCTIONS_AVAILABLE 46 +#endif +#ifndef PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE +#define PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE 47 +#endif +#ifndef PF_ARM_SVE_PMULL128_INSTRUCTIONS_AVAILABLE +#define PF_ARM_SVE_PMULL128_INSTRUCTIONS_AVAILABLE 50 +#endif +#ifndef PF_ARM_SVE_SHA3_INSTRUCTIONS_AVAILABLE +#define PF_ARM_SVE_SHA3_INSTRUCTIONS_AVAILABLE 55 +#endif +#ifndef PF_ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE +#define PF_ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE 56 +#endif +#ifndef PF_ARM_SVE_I8MM_INSTRUCTIONS_AVAILABLE +#define PF_ARM_SVE_I8MM_INSTRUCTIONS_AVAILABLE 57 +#endif +#ifndef PF_ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE +#define PF_ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE 58 +#endif +#ifndef PF_ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE +#define PF_ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE 59 +#endif StringMap<bool> sys::getHostCPUFeatures() { StringMap<bool> Features; // If we're asking the OS at runtime, believe what the OS says - Features["neon"] = - IsProcessorFeaturePresent(PF_ARM_NEON_INSTRUCTIONS_AVAILABLE); Features["crc"] = IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE); + Features["lse"] = + IsProcessorFeaturePresent(PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE); + Features["dotprod"] = + IsProcessorFeaturePresent(PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE); + Features["jsconv"] = + IsProcessorFeaturePresent(PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE); + Features["rcpc"] = + IsProcessorFeaturePresent(PF_ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE); + Features["sve"] = + IsProcessorFeaturePresent(PF_ARM_SVE_INSTRUCTIONS_AVAILABLE); + Features["sve2"] = + IsProcessorFeaturePresent(PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE); + Features["sve-aes"] = + IsProcessorFeaturePresent(PF_ARM_SVE_PMULL128_INSTRUCTIONS_AVAILABLE); + Features["sve-sha3"] = + IsProcessorFeaturePresent(PF_ARM_SVE_SHA3_INSTRUCTIONS_AVAILABLE); + Features["sve-sm4"] = + IsProcessorFeaturePresent(PF_ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE); + Features["f32mm"] = + IsProcessorFeaturePresent(PF_ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE); + Features["f64mm"] = + IsProcessorFeaturePresent(PF_ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE); + Features["i8mm"] = + IsProcessorFeaturePresent(PF_ARM_SVE_I8MM_INSTRUCTIONS_AVAILABLE); // Avoid inferring "crypto" means more than the traditional AES + SHA2 bool TradCrypto = diff --git a/llvm/lib/TargetParser/PPCTargetParser.cpp b/llvm/lib/TargetParser/PPCTargetParser.cpp index d510445..106d071 100644 --- a/llvm/lib/TargetParser/PPCTargetParser.cpp +++ b/llvm/lib/TargetParser/PPCTargetParser.cpp @@ -48,9 +48,9 @@ StringRef normalizeCPUName(StringRef CPUName) { // accepting it. Clang has always ignored it and passed the // generic CPU ID to the back end. return StringSwitch<StringRef>(CPUName) - .Cases("common", "405", "generic") - .Cases("ppc440", "440fp", "440") - .Cases("630", "power3", "pwr3") + .Cases({"common", "405"}, "generic") + .Cases({"ppc440", "440fp"}, "440") + .Cases({"630", "power3"}, "pwr3") .Case("G3", "g3") .Case("G4", "g4") .Case("G4+", "g4+") @@ -69,7 +69,7 @@ StringRef normalizeCPUName(StringRef CPUName) { .Case("power9", "pwr9") .Case("power10", "pwr10") .Case("power11", "pwr11") - .Cases("powerpc", "powerpc32", "ppc") + .Cases({"powerpc", "powerpc32"}, "ppc") .Case("powerpc64", "ppc64") .Case("powerpc64le", "ppc64le") .Default(CPUName); @@ -138,8 +138,11 @@ std::optional<StringMap<bool>> getPPCDefaultTargetFeatures(const Triple &T, // The target feature `quadword-atomics` is only supported for 64-bit // POWER8 and above. - if (Features.find("quadword-atomics") != Features.end() && !T.isArch64Bit()) - Features["quadword-atomics"] = false; + if (!T.isArch64Bit()) { + auto It = Features.find("quadword-atomics"); + if (It != Features.end()) + It->second = false; + } return Features; } } // namespace PPC diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp index f08a0c0..94ae64c 100644 --- a/llvm/lib/TargetParser/RISCVISAInfo.cpp +++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp @@ -14,7 +14,6 @@ #include "llvm/Support/Error.h" #include "llvm/Support/raw_ostream.h" -#include <array> #include <atomic> #include <optional> #include <string> diff --git a/llvm/lib/TargetParser/TargetDataLayout.cpp b/llvm/lib/TargetParser/TargetDataLayout.cpp index d735923..cbcbb5e 100644 --- a/llvm/lib/TargetParser/TargetDataLayout.cpp +++ b/llvm/lib/TargetParser/TargetDataLayout.cpp @@ -595,6 +595,7 @@ std::string Triple::computeDataLayout(StringRef ABIName) const { case Triple::x86_64: return computeX86DataLayout(*this); case Triple::xcore: + return "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32"; case Triple::xtensa: return "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32"; case Triple::nvptx: diff --git a/llvm/lib/TargetParser/TargetParser.cpp b/llvm/lib/TargetParser/TargetParser.cpp index 975a271..28f3649 100644 --- a/llvm/lib/TargetParser/TargetParser.cpp +++ b/llvm/lib/TargetParser/TargetParser.cpp @@ -174,8 +174,8 @@ constexpr GPUInfo AMDGCNGPUs[] = { {{"gfx1153"}, {"gfx1153"}, GK_GFX1153, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP}, {{"gfx1200"}, {"gfx1200"}, GK_GFX1200, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP}, {{"gfx1201"}, {"gfx1201"}, GK_GFX1201, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP}, - {{"gfx1250"}, {"gfx1250"}, GK_GFX1250, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32}, - {{"gfx1251"}, {"gfx1251"}, GK_GFX1251, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32}, + {{"gfx1250"}, {"gfx1250"}, GK_GFX1250, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK_ALWAYS}, + {{"gfx1251"}, {"gfx1251"}, GK_GFX1251, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK_ALWAYS}, {{"gfx9-generic"}, {"gfx9-generic"}, GK_GFX9_GENERIC, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK}, {{"gfx10-1-generic"}, {"gfx10-1-generic"}, GK_GFX10_1_GENERIC, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_WGP}, @@ -447,6 +447,11 @@ static void fillAMDGCNFeatureMap(StringRef GPU, const Triple &T, Features["atomic-fmin-fmax-global-f64"] = true; Features["wavefrontsize32"] = true; Features["clusters"] = true; + Features["cube-insts"] = true; + Features["lerp-inst"] = true; + Features["sad-insts"] = true; + Features["qsad-insts"] = true; + Features["cvt-pknorm-vop2-insts"] = true; break; case GK_GFX1201: case GK_GFX1200: @@ -474,6 +479,11 @@ static void fillAMDGCNFeatureMap(StringRef GPU, const Triple &T, Features["gfx12-insts"] = true; Features["atomic-fadd-rtn-insts"] = true; Features["image-insts"] = true; + Features["cube-insts"] = true; + Features["lerp-inst"] = true; + Features["sad-insts"] = true; + Features["qsad-insts"] = true; + Features["cvt-pknorm-vop2-insts"] = true; Features["fp8-conversion-insts"] = true; Features["atomic-fmin-fmax-global-f32"] = true; break; @@ -503,6 +513,11 @@ static void fillAMDGCNFeatureMap(StringRef GPU, const Triple &T, Features["gfx11-insts"] = true; Features["atomic-fadd-rtn-insts"] = true; Features["image-insts"] = true; + Features["cube-insts"] = true; + Features["lerp-inst"] = true; + Features["sad-insts"] = true; + Features["qsad-insts"] = true; + Features["cvt-pknorm-vop2-insts"] = true; Features["gws"] = true; Features["atomic-fmin-fmax-global-f32"] = true; break; @@ -535,6 +550,11 @@ static void fillAMDGCNFeatureMap(StringRef GPU, const Triple &T, Features["vmem-to-lds-load-insts"] = true; Features["atomic-fmin-fmax-global-f32"] = true; Features["atomic-fmin-fmax-global-f64"] = true; + Features["cube-insts"] = true; + Features["lerp-inst"] = true; + Features["sad-insts"] = true; + Features["qsad-insts"] = true; + Features["cvt-pknorm-vop2-insts"] = true; break; case GK_GFX1012: case GK_GFX1011: @@ -562,6 +582,11 @@ static void fillAMDGCNFeatureMap(StringRef GPU, const Triple &T, Features["vmem-to-lds-load-insts"] = true; Features["atomic-fmin-fmax-global-f32"] = true; Features["atomic-fmin-fmax-global-f64"] = true; + Features["cube-insts"] = true; + Features["lerp-inst"] = true; + Features["sad-insts"] = true; + Features["qsad-insts"] = true; + Features["cvt-pknorm-vop2-insts"] = true; break; case GK_GFX950: Features["bitop3-insts"] = true; @@ -615,6 +640,11 @@ static void fillAMDGCNFeatureMap(StringRef GPU, const Triple &T, Features["vmem-to-lds-load-insts"] = true; Features["atomic-fmin-fmax-global-f64"] = true; Features["wavefrontsize64"] = true; + Features["cube-insts"] = true; + Features["lerp-inst"] = true; + Features["sad-insts"] = true; + Features["qsad-insts"] = true; + Features["cvt-pknorm-vop2-insts"] = true; break; case GK_GFX90A: Features["gfx90a-insts"] = true; @@ -659,6 +689,11 @@ static void fillAMDGCNFeatureMap(StringRef GPU, const Triple &T, Features["s-memtime-inst"] = true; Features["gws"] = true; Features["wavefrontsize64"] = true; + Features["cube-insts"] = true; + Features["lerp-inst"] = true; + Features["sad-insts"] = true; + Features["qsad-insts"] = true; + Features["cvt-pknorm-vop2-insts"] = true; break; case GK_GFX705: case GK_GFX704: @@ -667,7 +702,18 @@ static void fillAMDGCNFeatureMap(StringRef GPU, const Triple &T, case GK_GFX701: case GK_GFX700: Features["ci-insts"] = true; - [[fallthrough]]; + Features["cube-insts"] = true; + Features["lerp-inst"] = true; + Features["sad-insts"] = true; + Features["qsad-insts"] = true; + Features["cvt-pknorm-vop2-insts"] = true; + Features["image-insts"] = true; + Features["s-memtime-inst"] = true; + Features["gws"] = true; + Features["atomic-fmin-fmax-global-f32"] = true; + Features["atomic-fmin-fmax-global-f64"] = true; + Features["wavefrontsize64"] = true; + break; case GK_GFX602: case GK_GFX601: case GK_GFX600: @@ -677,6 +723,10 @@ static void fillAMDGCNFeatureMap(StringRef GPU, const Triple &T, Features["atomic-fmin-fmax-global-f32"] = true; Features["atomic-fmin-fmax-global-f64"] = true; Features["wavefrontsize64"] = true; + Features["cube-insts"] = true; + Features["lerp-inst"] = true; + Features["sad-insts"] = true; + Features["cvt-pknorm-vop2-insts"] = true; break; case GK_NONE: break; diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp index b13c795..2810849 100644 --- a/llvm/lib/TargetParser/X86TargetParser.cpp +++ b/llvm/lib/TargetParser/X86TargetParser.cpp @@ -143,7 +143,7 @@ constexpr FeatureBitset FeaturesDiamondRapids = FeatureAVXVNNIINT8 | FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 | FeatureSM4 | FeatureEGPR | FeatureZU | FeatureCCMP | FeaturePush2Pop2 | FeaturePPX | FeatureNDD | FeatureNF | FeatureMOVRS | FeatureAMX_MOVRS | - FeatureAMX_AVX512 | FeatureAMX_FP8 | FeatureAMX_TF32 | FeatureAMX_TRANSPOSE; + FeatureAMX_AVX512 | FeatureAMX_FP8 | FeatureAMX_TF32; // Intel Atom processors. // Bonnell has feature parity with Core2 and adds MOVBE. @@ -176,7 +176,9 @@ constexpr FeatureBitset FeaturesArrowlakeS = constexpr FeatureBitset FeaturesPantherlake = (FeaturesArrowlakeS ^ FeatureWIDEKL); constexpr FeatureBitset FeaturesNovalake = - FeaturesPantherlake | FeaturePREFETCHI; + FeaturesPantherlake | FeaturePREFETCHI | FeatureAVX10_2 | FeatureMOVRS | + FeatureEGPR | FeatureZU | FeatureCCMP | FeaturePush2Pop2 | FeaturePPX | + FeatureNDD | FeatureNF; constexpr FeatureBitset FeaturesClearwaterforest = (FeaturesSierraforest ^ FeatureWIDEKL) | FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 | FeatureSM4 | FeaturePREFETCHI | FeatureUSERMSR; @@ -542,8 +544,6 @@ constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {}; constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {}; constexpr FeatureBitset ImpliedFeaturesX87 = {}; constexpr FeatureBitset ImpliedFeaturesXSAVE = {}; -constexpr FeatureBitset ImpliedFeaturesDUMMYFEATURE1 = {}; -constexpr FeatureBitset ImpliedFeaturesDUMMYFEATURE2 = {}; // Not really CPU features, but need to be in the table because clang uses // target features to communicate them to the backend. @@ -615,7 +615,6 @@ constexpr FeatureBitset ImpliedFeaturesAMX_FP16 = FeatureAMX_TILE; constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE; constexpr FeatureBitset ImpliedFeaturesAMX_COMPLEX = FeatureAMX_TILE; constexpr FeatureBitset ImpliedFeaturesAMX_FP8 = FeatureAMX_TILE; -constexpr FeatureBitset ImpliedFeaturesAMX_TRANSPOSE = FeatureAMX_TILE; constexpr FeatureBitset ImpliedFeaturesAMX_MOVRS = FeatureAMX_TILE; constexpr FeatureBitset ImpliedFeaturesAMX_AVX512 = FeatureAMX_TILE | FeatureAVX10_2; @@ -645,8 +644,6 @@ constexpr FeatureBitset ImpliedFeaturesAVX10_1 = FeatureAVX512VBMI2 | FeatureAVX512BITALG | FeatureAVX512FP16 | FeatureAVX512DQ | FeatureAVX512VL; constexpr FeatureBitset ImpliedFeaturesAVX10_2 = FeatureAVX10_1; -constexpr FeatureBitset ImpliedFeaturesAVX10_1_512 = FeatureAVX10_1; -constexpr FeatureBitset ImpliedFeaturesAVX10_2_512 = FeatureAVX10_2; // APX Features constexpr FeatureBitset ImpliedFeaturesEGPR = {}; @@ -658,9 +655,14 @@ constexpr FeatureBitset ImpliedFeaturesNF = {}; constexpr FeatureBitset ImpliedFeaturesCF = {}; constexpr FeatureBitset ImpliedFeaturesZU = {}; +constexpr FeatureBitset ImpliedFeaturesAPXF = + ImpliedFeaturesEGPR | ImpliedFeaturesPush2Pop2 | ImpliedFeaturesPPX | + ImpliedFeaturesNDD | ImpliedFeaturesCCMP | ImpliedFeaturesNF | + ImpliedFeaturesCF | ImpliedFeaturesZU; + constexpr FeatureBitset ImpliedFeaturesMOVRS = {}; -constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = { +constexpr FeatureInfo FeatureInfos[] = { #define X86_FEATURE(ENUM, STR) {{"+" STR}, ImpliedFeatures##ENUM}, #include "llvm/TargetParser/X86TargetParser.def" }; @@ -760,10 +762,9 @@ llvm::X86::getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs) { std::array<uint32_t, 4> FeatureMask{}; for (StringRef FeatureStr : FeatureStrs) { unsigned Feature = StringSwitch<unsigned>(FeatureStr) -#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ - .Case(STR, llvm::X86::FEATURE_##ENUM) -#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY) \ - .Case(STR, llvm::X86::FEATURE_##ENUM) +#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) .Case(STR, ABI_VALUE) +#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY, ABI_VALUE) \ + .Case(STR, ABI_VALUE) #include "llvm/TargetParser/X86TargetParser.def" ; assert(Feature / 32 < FeatureMask.size()); @@ -776,15 +777,14 @@ unsigned llvm::X86::getFeaturePriority(ProcessorFeatures Feat) { #ifndef NDEBUG // Check that priorities are set properly in the .def file. We expect that // "compat" features are assigned non-duplicate consecutive priorities - // starting from one (1, ..., 37) and multiple zeros. -#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) PRIORITY, + // starting from one (1, ..., MAX_PRIORITY) and multiple zeros. +#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) PRIORITY, unsigned Priorities[] = { #include "llvm/TargetParser/X86TargetParser.def" }; std::array<unsigned, std::size(Priorities)> HelperList; - const size_t MaxPriority = 37; - std::iota(HelperList.begin(), HelperList.begin() + MaxPriority + 1, 0); - for (size_t i = MaxPriority + 1; i != std::size(Priorities); ++i) + std::iota(HelperList.begin(), HelperList.begin() + MAX_PRIORITY + 1, 0); + for (size_t i = MAX_PRIORITY + 1; i != std::size(Priorities); ++i) HelperList[i] = 0; assert(std::is_permutation(HelperList.begin(), HelperList.end(), std::begin(Priorities), std::end(Priorities)) && @@ -792,7 +792,7 @@ unsigned llvm::X86::getFeaturePriority(ProcessorFeatures Feat) { #endif switch (Feat) { -#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ +#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY, ABI_VALUE) \ case X86::FEATURE_##ENUM: \ return PRIORITY; #include "llvm/TargetParser/X86TargetParser.def" diff --git a/llvm/lib/TargetParser/XtensaTargetParser.cpp b/llvm/lib/TargetParser/XtensaTargetParser.cpp index 25725f2..208722a 100644 --- a/llvm/lib/TargetParser/XtensaTargetParser.cpp +++ b/llvm/lib/TargetParser/XtensaTargetParser.cpp @@ -13,6 +13,7 @@ #include "llvm/TargetParser/XtensaTargetParser.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringSwitch.h" +#include <vector> namespace llvm { |