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-rw-r--r--llvm/lib/Target/Xtensa/CMakeLists.txt2
-rw-r--r--llvm/lib/Target/Xtensa/Xtensa.td2
-rw-r--r--llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp2
-rw-r--r--llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp1
-rw-r--r--llvm/lib/Target/Xtensa/XtensaISelLowering.cpp55
-rw-r--r--llvm/lib/Target/Xtensa/XtensaISelLowering.h63
-rw-r--r--llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp18
-rw-r--r--llvm/lib/Target/Xtensa/XtensaInstrInfo.h5
-rw-r--r--llvm/lib/Target/Xtensa/XtensaSelectionDAGInfo.cpp19
-rw-r--r--llvm/lib/Target/Xtensa/XtensaSelectionDAGInfo.h28
-rw-r--r--llvm/lib/Target/Xtensa/XtensaSubtarget.cpp11
-rw-r--r--llvm/lib/Target/Xtensa/XtensaSubtarget.h10
12 files changed, 82 insertions, 134 deletions
diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt
index c698b42..9d3a893 100644
--- a/llvm/lib/Target/Xtensa/CMakeLists.txt
+++ b/llvm/lib/Target/Xtensa/CMakeLists.txt
@@ -10,6 +10,7 @@ tablegen(LLVM XtensaGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM XtensaGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM XtensaGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM XtensaGenRegisterInfo.inc -gen-register-info)
+tablegen(LLVM XtensaGenSDNodeInfo.inc -gen-sd-node-info)
tablegen(LLVM XtensaGenSubtargetInfo.inc -gen-subtarget)
add_public_tablegen_target(XtensaCommonTableGen)
@@ -22,6 +23,7 @@ add_llvm_target(XtensaCodeGen
XtensaISelDAGToDAG.cpp
XtensaISelLowering.cpp
XtensaRegisterInfo.cpp
+ XtensaSelectionDAGInfo.cpp
XtensaSubtarget.cpp
XtensaTargetMachine.cpp
diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td
index 4ef885e1..eecf42f 100644
--- a/llvm/lib/Target/Xtensa/Xtensa.td
+++ b/llvm/lib/Target/Xtensa/Xtensa.td
@@ -44,6 +44,8 @@ include "XtensaCallingConv.td"
include "XtensaInstrInfo.td"
+defm : RemapAllTargetPseudoPointerOperands<AR>;
+
def XtensaInstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
index cf9a2a0..1c0dc66 100644
--- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
@@ -314,7 +314,7 @@ bool XtensaFrameLowering::spillCalleeSavedRegisters(
bool IsKill = !IsA0AndRetAddrIsTaken;
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
TII.storeRegToStackSlot(EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(),
- RC, TRI, Register());
+ RC, Register());
}
return true;
diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
index 959553d..655b40f 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
@@ -12,6 +12,7 @@
#include "MCTargetDesc/XtensaMCTargetDesc.h"
#include "Xtensa.h"
+#include "XtensaSelectionDAGInfo.h"
#include "XtensaTargetMachine.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index c211777..a9cf671 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -15,6 +15,7 @@
#include "XtensaConstantPoolValue.h"
#include "XtensaInstrInfo.h"
#include "XtensaMachineFunctionInfo.h"
+#include "XtensaSelectionDAGInfo.h"
#include "XtensaSubtarget.h"
#include "XtensaTargetMachine.h"
#include "llvm/CodeGen/CallingConvLower.h"
@@ -53,7 +54,7 @@ static unsigned toCallerWindow(unsigned Reg) {
XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM,
const XtensaSubtarget &STI)
- : TargetLowering(TM), Subtarget(STI) {
+ : TargetLowering(TM, STI), Subtarget(STI) {
MVT PtrVT = MVT::i32;
// Set up the register classes.
addRegisterClass(MVT::i32, &Xtensa::ARRegClass);
@@ -1510,58 +1511,6 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op,
}
}
-const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const {
- switch (Opcode) {
- case XtensaISD::BR_JT:
- return "XtensaISD::BR_JT";
- case XtensaISD::CALL:
- return "XtensaISD::CALL";
- case XtensaISD::CALLW8:
- return "XtensaISD::CALLW8";
- case XtensaISD::EXTUI:
- return "XtensaISD::EXTUI";
- case XtensaISD::MOVSP:
- return "XtensaISD::MOVSP";
- case XtensaISD::PCREL_WRAPPER:
- return "XtensaISD::PCREL_WRAPPER";
- case XtensaISD::RET:
- return "XtensaISD::RET";
- case XtensaISD::RETW:
- return "XtensaISD::RETW";
- case XtensaISD::RUR:
- return "XtensaISD::RUR";
- case XtensaISD::SELECT_CC:
- return "XtensaISD::SELECT_CC";
- case XtensaISD::SELECT_CC_FP:
- return "XtensaISD::SELECT_CC_FP";
- case XtensaISD::SRCL:
- return "XtensaISD::SRCL";
- case XtensaISD::SRCR:
- return "XtensaISD::SRCR";
- case XtensaISD::CMPUO:
- return "XtensaISD::CMPUO";
- case XtensaISD::CMPUEQ:
- return "XtensaISD::CMPUEQ";
- case XtensaISD::CMPULE:
- return "XtensaISD::CMPULE";
- case XtensaISD::CMPULT:
- return "XtensaISD::CMPULT";
- case XtensaISD::CMPOEQ:
- return "XtensaISD::CMPOEQ";
- case XtensaISD::CMPOLE:
- return "XtensaISD::CMPOLE";
- case XtensaISD::CMPOLT:
- return "XtensaISD::CMPOLT";
- case XtensaISD::MADD:
- return "XtensaISD::MADD";
- case XtensaISD::MSUB:
- return "XtensaISD::MSUB";
- case XtensaISD::MOVS:
- return "XtensaISD::MOVS";
- }
- return nullptr;
-}
-
TargetLowering::AtomicExpansionKind
XtensaTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
return AtomicExpansionKind::CmpXChg;
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
index d84cbdb..829de0f 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
@@ -20,67 +20,6 @@
namespace llvm {
-namespace XtensaISD {
-enum {
- FIRST_NUMBER = ISD::BUILTIN_OP_END,
- BR_JT,
-
- // Calls a function. Operand 0 is the chain operand and operand 1
- // is the target address. The arguments start at operand 2.
- // There is an optional glue operand at the end.
- CALL,
- // Call with rotation window by 8 registers
- CALLW8,
-
- // Extract unsigned immediate. Operand 0 is value, operand 1
- // is bit position of the field [0..31], operand 2 is bit size
- // of the field [1..16]
- EXTUI,
-
- MOVSP,
-
- // Wraps a TargetGlobalAddress that should be loaded using PC-relative
- // accesses. Operand 0 is the address.
- PCREL_WRAPPER,
- RET,
- RETW,
-
- RUR,
-
- // Select with condition operator - This selects between a true value and
- // a false value (ops #2 and #3) based on the boolean result of comparing
- // the lhs and rhs (ops #0 and #1) of a conditional expression with the
- // condition code in op #4
- SELECT_CC,
- // Select with condition operator - This selects between a true value and
- // a false value (ops #2 and #3) based on the boolean result of comparing
- // f32 operands lhs and rhs (ops #0 and #1) of a conditional expression
- // with the condition code in op #4 and boolean branch kind in op #5
- SELECT_CC_FP,
-
- // SRCL(R) performs shift left(right) of the concatenation of 2 registers
- // and returns high(low) 32-bit part of 64-bit result
- SRCL,
- // Shift Right Combined
- SRCR,
-
- // Floating point unordered compare conditions
- CMPUEQ,
- CMPULE,
- CMPULT,
- CMPUO,
- // Floating point compare conditions
- CMPOEQ,
- CMPOLE,
- CMPOLT,
- // FP multipy-add/sub
- MADD,
- MSUB,
- // FP move
- MOVS,
-};
-}
-
class XtensaSubtarget;
class XtensaTargetLowering : public TargetLowering {
@@ -104,8 +43,6 @@ public:
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
- const char *getTargetNodeName(unsigned Opcode) const override;
-
bool isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize) const override;
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
index 6bbebde..d7b05ac 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
@@ -145,8 +145,8 @@ void XtensaInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
void XtensaInstrInfo::storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
bool isKill, int FrameIdx, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI, Register VReg,
- MachineInstr::MIFlag Flags) const {
+
+ Register VReg, MachineInstr::MIFlag Flags) const {
DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
unsigned LoadOpcode, StoreOpcode;
getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode, FrameIdx);
@@ -155,10 +155,12 @@ void XtensaInstrInfo::storeRegToStackSlot(
addFrameReference(MIB, FrameIdx);
}
-void XtensaInstrInfo::loadRegFromStackSlot(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg,
- int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
- Register VReg, MachineInstr::MIFlag Flags) const {
+void XtensaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ Register DestReg, int FrameIdx,
+ const TargetRegisterClass *RC,
+ Register VReg,
+ MachineInstr::MIFlag Flags) const {
DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
unsigned LoadOpcode, StoreOpcode;
getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode, FrameIdx);
@@ -544,12 +546,12 @@ void XtensaInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
"function code size is significantly larger than estimated");
storeRegToStackSlot(MBB, L32R, ScavRegister, /*IsKill=*/true, FrameIndex,
- &Xtensa::ARRegClass, &RI, Register());
+ &Xtensa::ARRegClass, Register());
RI.eliminateFrameIndex(std::prev(L32R.getIterator()),
/*SpAdj=*/0, /*FIOperandNum=*/1);
loadRegFromStackSlot(RestoreBB, RestoreBB.end(), ScavRegister, FrameIndex,
- &Xtensa::ARRegClass, &RI, Register());
+ &Xtensa::ARRegClass, Register());
RI.eliminateFrameIndex(RestoreBB.back(),
/*SpAdj=*/0, /*FIOperandNum=*/1);
JumpToMBB = &RestoreBB;
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h
index 1808cb3..0b46d6c 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h
@@ -56,14 +56,13 @@ public:
void storeRegToStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
- bool isKill, int FrameIndex, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI, Register VReg,
+ bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg,
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
void loadRegFromStackSlot(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
Register DestReg, int FrameIdx, const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI, Register VReg,
+ Register VReg,
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
// Get the load and store opcodes for a given register class and offset.
diff --git a/llvm/lib/Target/Xtensa/XtensaSelectionDAGInfo.cpp b/llvm/lib/Target/Xtensa/XtensaSelectionDAGInfo.cpp
new file mode 100644
index 0000000..79fa81d
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaSelectionDAGInfo.cpp
@@ -0,0 +1,19 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "XtensaSelectionDAGInfo.h"
+
+#define GET_SDNODE_DESC
+#include "XtensaGenSDNodeInfo.inc"
+
+using namespace llvm;
+
+XtensaSelectionDAGInfo::XtensaSelectionDAGInfo()
+ : SelectionDAGGenTargetInfo(XtensaGenSDNodeInfo) {}
+
+XtensaSelectionDAGInfo::~XtensaSelectionDAGInfo() = default;
diff --git a/llvm/lib/Target/Xtensa/XtensaSelectionDAGInfo.h b/llvm/lib/Target/Xtensa/XtensaSelectionDAGInfo.h
new file mode 100644
index 0000000..6fb2281
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaSelectionDAGInfo.h
@@ -0,0 +1,28 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSASELECTIONDAGINFO_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSASELECTIONDAGINFO_H
+
+#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+
+#define GET_SDNODE_ENUM
+#include "XtensaGenSDNodeInfo.inc"
+
+namespace llvm {
+
+class XtensaSelectionDAGInfo : public SelectionDAGGenTargetInfo {
+public:
+ XtensaSelectionDAGInfo();
+
+ ~XtensaSelectionDAGInfo() override;
+};
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_XTENSA_XTENSASELECTIONDAGINFO_H
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
index 6b1d325..c1a1efc 100644
--- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
@@ -11,6 +11,7 @@
//===----------------------------------------------------------------------===//
#include "XtensaSubtarget.h"
+#include "XtensaSelectionDAGInfo.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/Support/Debug.h"
@@ -39,4 +40,12 @@ XtensaSubtarget::XtensaSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
const TargetMachine &TM)
: XtensaGenSubtargetInfo(TT, CPU, /*TuneCPU=*/CPU, FS), TargetTriple(TT),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
- TSInfo(), FrameLowering(*this) {}
+ FrameLowering(*this) {
+ TSInfo = std::make_unique<SelectionDAGTargetInfo>();
+}
+
+XtensaSubtarget::~XtensaSubtarget() = default;
+
+const SelectionDAGTargetInfo *XtensaSubtarget::getSelectionDAGInfo() const {
+ return TSInfo.get();
+}
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
index b406534..6a5201b 100644
--- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
@@ -17,7 +17,6 @@
#include "XtensaISelLowering.h"
#include "XtensaInstrInfo.h"
#include "XtensaRegisterInfo.h"
-#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
@@ -38,7 +37,7 @@ private:
const Triple &TargetTriple;
XtensaInstrInfo InstrInfo;
XtensaTargetLowering TLInfo;
- SelectionDAGTargetInfo TSInfo;
+ std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
XtensaFrameLowering FrameLowering;
XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
@@ -47,6 +46,8 @@ public:
XtensaSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
const TargetMachine &TM);
+ ~XtensaSubtarget() override;
+
const Triple &getTargetTriple() const { return TargetTriple; }
const TargetFrameLowering *getFrameLowering() const override {
@@ -60,9 +61,8 @@ public:
const XtensaTargetLowering *getTargetLowering() const override {
return &TLInfo;
}
- const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
- return &TSInfo;
- }
+
+ const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
bool hasDensity() const { return HasDensity; }
bool hasMAC16() const { return HasMAC16; }
generated by cgit v1.1 at 2026-01-05 11:45:16 +0000