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-rw-r--r--llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp10
1 files changed, 9 insertions, 1 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
index 6f93248..bac635d 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
@@ -166,7 +166,15 @@ void WebAssemblyPassConfig::addPreRegAlloc() {}
void WebAssemblyPassConfig::addRegAllocPasses(bool Optimized) {}
-void WebAssemblyPassConfig::addPostRegAlloc() {}
+void WebAssemblyPassConfig::addPostRegAlloc() {
+ // FIXME: the following passes dislike virtual registers. Disable them for now
+ // so that basic tests can pass. Future patches will remedy this.
+ //
+ // Fails with: Regalloc must assign all vregs.
+ disablePass(&PrologEpilogCodeInserterID);
+ // Fails with: should be run after register allocation.
+ disablePass(&MachineCopyPropagationID);
+}
void WebAssemblyPassConfig::addPreSched2() {}