diff options
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVInstrInfoP.td')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 245 |
1 files changed, 205 insertions, 40 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td index cc085bb..bba9f96 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td @@ -18,15 +18,22 @@ // Operand and SDNode transformation definitions. //===----------------------------------------------------------------------===// -def simm10 : RISCVSImmOp<10>; +def simm10 : RISCVSImmOp<10>, ImmLeaf<XLenVT, "return isInt<10>(Imm);">; def SImm8UnsignedAsmOperand : SImmAsmOperand<8, "Unsigned"> { let RenderMethod = "addSImm8UnsignedOperands"; } +// (<2 x i16>, <2 x i16>) PPACK_DH (<4 x i8>, <4 x i8>, <4 x i8>, <4 x i8>) +def SDT_RISCVPPackDH + : SDTypeProfile<2, 4, [SDTCisVT<0, v2i16>, SDTCisSameAs<0, 1>, + SDTCisVT<2, v4i8>, SDTCisSameAs<0, 3>, + SDTCisSameAs<0, 4>, SDTCisSameAs<0, 5>]>; +def riscv_ppack_dh : RVSDNode<"PPACK_DH", SDT_RISCVPPackDH>; + // A 8-bit signed immediate allowing range [-128, 255] // but represented as [-128, 127]. -def simm8_unsigned : RISCVOp { +def simm8_unsigned : RISCVOp, ImmLeaf<XLenVT, "return isInt<8>(Imm);"> { let ParserMatchClass = SImm8UnsignedAsmOperand; let EncoderMethod = "getImmOpValue"; let DecoderMethod = "decodeSImmOperand<8>"; @@ -625,8 +632,8 @@ let Predicates = [HasStdExtP] in { def PSUB_H : RVPBinary_rr<0b1000, 0b00, 0b000, "psub.h">; def PSUB_B : RVPBinary_rr<0b1000, 0b10, 0b000, "psub.b">; - def PDIF_H : RVPBinary_rr<0b1001, 0b00, 0b000, "pdif.h">; - def PDIF_B : RVPBinary_rr<0b1001, 0b10, 0b000, "pdif.b">; + def PABD_H : RVPBinary_rr<0b1001, 0b00, 0b000, "pabd.h">; + def PABD_B : RVPBinary_rr<0b1001, 0b10, 0b000, "pabd.b">; def PSSUB_H : RVPBinary_rr<0b1010, 0b00, 0b000, "pssub.h">; def PSSUB_B : RVPBinary_rr<0b1010, 0b10, 0b000, "pssub.b">; @@ -634,8 +641,8 @@ let Predicates = [HasStdExtP] in { def PASUB_H : RVPBinary_rr<0b1011, 0b00, 0b000, "pasub.h">; def PASUB_B : RVPBinary_rr<0b1011, 0b10, 0b000, "pasub.b">; - def PDIFU_H : RVPBinary_rr<0b1101, 0b00, 0b000, "pdifu.h">; - def PDIFU_B : RVPBinary_rr<0b1101, 0b10, 0b000, "pdifu.b">; + def PABDU_H : RVPBinary_rr<0b1101, 0b00, 0b000, "pabdu.h">; + def PABDU_B : RVPBinary_rr<0b1101, 0b10, 0b000, "pabdu.b">; def PSSUBU_H : RVPBinary_rr<0b1110, 0b00, 0b000, "pssubu.h">; def PSSUBU_B : RVPBinary_rr<0b1110, 0b10, 0b000, "pssubu.b">; @@ -693,9 +700,9 @@ let Predicates = [HasStdExtP] in { def SRX : RVPTernary_rrr<0b0101, 0b11, 0b001, "srx">; def PMULU_H_B01 : RVPBinary_rr<0b0110, 0b00, 0b001, "pmulu.h.b01">; - def PDIFSUMU_B : RVPBinary_rr<0b0110, 0b10, 0b001, "pdifsumu.b">; + def PABDSUMU_B : RVPBinary_rr<0b0110, 0b10, 0b001, "pabdsumu.b">; - def PDIFSUMAU_B : RVPTernary_rrr<0b0111, 0b10, 0b001, "pdifsumau.b">; + def PABDSUMAU_B : RVPTernary_rrr<0b0111, 0b10, 0b001, "pabdsumau.b">; } // Predicates = [HasStdExtP] let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in { def MUL_H01 : RVPBinary_rr<0b0010, 0b01, 0b001, "mul.h01">; @@ -825,32 +832,25 @@ let Predicates = [HasStdExtP, IsRV64] in { // Note the spec has a 3-bit f field in bits 30:28 with 0 in bit 27. // Here we include the 0 in the f field to reduce number of tablegen classes. let Predicates = [HasStdExtP] in { - def PPACK_H : RVPBinary_rr<0b0000, 0b00, 0b100, "ppack.h">; + def PPAIRE_B : RVPBinary_rr<0b0000, 0b00, 0b100, "ppaire.b">; - def PPACKBT_H : RVPBinary_rr<0b0010, 0b00, 0b100, "ppackbt.h">; + def PPAIREO_B : RVPBinary_rr<0b0010, 0b00, 0b100, "ppaireo.b">; + def PPAIREO_H : RVPBinary_rr<0b0010, 0b01, 0b100, "ppaireo.h">; - def PPACKTB_H : RVPBinary_rr<0b0100, 0b00, 0b100, "ppacktb.h">; + def PPAIROE_B : RVPBinary_rr<0b0100, 0b00, 0b100, "ppairoe.b">; + def PPAIROE_H : RVPBinary_rr<0b0100, 0b01, 0b100, "ppairoe.h">; - def PPACKT_H : RVPBinary_rr<0b0110, 0b00, 0b100, "ppackt.h">; + def PPAIRO_B : RVPBinary_rr<0b0110, 0b00, 0b100, "ppairo.b">; + def PPAIRO_H : RVPBinary_rr<0b0110, 0b01, 0b100, "ppairo.h">; } // Predicates = [HasStdExtP] -let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in { - def PACKBT_RV32 : RVPBinary_rr<0b0010, 0b01, 0b100, "packbt">; - - def PACKTB_RV32 : RVPBinary_rr<0b0100, 0b01, 0b100, "packtb">; - - def PACKT_RV32 : RVPBinary_rr<0b0110, 0b01, 0b100, "packt">; -} // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" let Predicates = [HasStdExtP, IsRV64] in { - def PPACK_W : RVPBinary_rr<0b0000, 0b01, 0b100, "ppack.w">; + def PPAIRE_H : RVPBinary_rr<0b0000, 0b01, 0b100, "ppaire.h">; - def PPACKBT_W : RVPBinary_rr<0b0010, 0b01, 0b100, "ppackbt.w">; - def PACKBT_RV64 : RVPBinary_rr<0b0010, 0b11, 0b100, "packbt">; + def PPAIREO_W : RVPBinary_rr<0b0010, 0b11, 0b100, "ppaireo.w">; - def PPACKTB_W : RVPBinary_rr<0b0100, 0b01, 0b100, "ppacktb.w">; - def PACKTB_RV64 : RVPBinary_rr<0b0100, 0b11, 0b100, "packtb">; + def PPAIROE_W : RVPBinary_rr<0b0100, 0b11, 0b100, "ppairoe.w">; - def PPACKT_W : RVPBinary_rr<0b0110, 0b01, 0b100, "ppackt.w">; - def PACKT_RV64 : RVPBinary_rr<0b0110, 0b11, 0b100, "packt">; + def PPAIRO_W : RVPBinary_rr<0b0110, 0b11, 0b100, "ppairo.w">; } // Predicates = [HasStdExtP, IsRV64] let Predicates = [HasStdExtP] in { @@ -1378,8 +1378,8 @@ let Predicates = [HasStdExtP, IsRV32] in { def PSUB_DB : RVPPairBinary_rr<0b1000, 0b10, "psub.db">; def SUBD : RVPPairBinary_rr<0b1000, 0b11, "subd">; - def PDIF_DH : RVPPairBinary_rr<0b1001, 0b00, "pdif.dh">; - def PDIF_DB : RVPPairBinary_rr<0b1001, 0b10, "pdif.db">; + def PABD_DH : RVPPairBinary_rr<0b1001, 0b00, "pabd.dh">; + def PABD_DB : RVPPairBinary_rr<0b1001, 0b10, "pabd.db">; def PSSUB_DH : RVPPairBinary_rr<0b1010, 0b00, "pssub.dh">; def PSSUB_DW : RVPPairBinary_rr<0b1010, 0b01, "pssub.dw">; @@ -1389,8 +1389,8 @@ let Predicates = [HasStdExtP, IsRV32] in { def PASUB_DW : RVPPairBinary_rr<0b1011, 0b01, "pasub.dw">; def PASUB_DB : RVPPairBinary_rr<0b1011, 0b10, "pasub.db">; - def PDIFU_DH : RVPPairBinary_rr<0b1101, 0b00, "pdifu.dh">; - def PDIFU_DB : RVPPairBinary_rr<0b1101, 0b10, "pdifu.db">; + def PABDU_DH : RVPPairBinary_rr<0b1101, 0b00, "pabdu.dh">; + def PABDU_DB : RVPPairBinary_rr<0b1101, 0b10, "pabdu.db">; def PSSUBU_DH : RVPPairBinary_rr<0b1110, 0b00, "pssubu.dh">; def PSSUBU_DW : RVPPairBinary_rr<0b1110, 0b01, "pssubu.dw">; @@ -1406,17 +1406,17 @@ let Predicates = [HasStdExtP, IsRV32] in { def PSSH1SADD_DH : RVPPairBinaryShift_rr<0b011, 0b00, "pssh1sadd.dh">; def PSSH1SADD_DW : RVPPairBinaryShift_rr<0b011, 0b01, "pssh1sadd.dw">; - def PPACK_DH : RVPPairBinaryPack_rr<0b000, 0b00, "ppack.dh">; - def PPACK_DW : RVPPairBinaryPack_rr<0b000, 0b01, "ppack.dw">; + def PPAIRE_DB : RVPPairBinaryPack_rr<0b000, 0b00, "ppaire.db">; + def PPAIRE_DH : RVPPairBinaryPack_rr<0b000, 0b01, "ppaire.dh">; - def PPACKBT_DH : RVPPairBinaryPack_rr<0b001, 0b00, "ppackbt.dh">; - def PPACKBT_DW : RVPPairBinaryPack_rr<0b001, 0b01, "ppackbt.dw">; + def PPAIREO_DB : RVPPairBinaryPack_rr<0b001, 0b00, "ppaireo.db">; + def PPAIREO_DH : RVPPairBinaryPack_rr<0b001, 0b01, "ppaireo.dh">; - def PPACKTB_DH : RVPPairBinaryPack_rr<0b010, 0b00, "ppacktb.dh">; - def PPACKTB_DW : RVPPairBinaryPack_rr<0b010, 0b01, "ppacktb.dw">; + def PPAIROE_DB : RVPPairBinaryPack_rr<0b010, 0b00, "ppairoe.db">; + def PPAIROE_DH : RVPPairBinaryPack_rr<0b010, 0b01, "ppairoe.dh">; - def PPACKT_DH : RVPPairBinaryPack_rr<0b011, 0b00, "ppackt.dh">; - def PPACKT_DW : RVPPairBinaryPack_rr<0b011, 0b01, "ppackt.dw">; + def PPAIRO_DB : RVPPairBinaryPack_rr<0b011, 0b00, "ppairo.db">; + def PPAIRO_DH : RVPPairBinaryPack_rr<0b011, 0b01, "ppairo.dh">; def PAS_DHX : RVPPairBinaryExchanged_rr<0b0000, 0b00, "pas.dhx">; def PSA_DHX : RVPPairBinaryExchanged_rr<0b0000, 0b10, "psa.dhx">; @@ -1461,5 +1461,170 @@ let Predicates = [HasStdExtP, IsRV32] in { // Codegen patterns //===----------------------------------------------------------------------===// -let Predicates = [HasStdExtP] in -def : PatGpr<abs, ABS>; +def riscv_absw : RVSDNode<"ABSW", SDT_RISCVIntUnaryOpW>; + +def SDT_RISCVPASUB : SDTypeProfile<1, 2, [SDTCisVec<0>, + SDTCisInt<0>, + SDTCisSameAs<0, 1>, + SDTCisSameAs<0, 2>]>; +def riscv_pasub : RVSDNode<"PASUB", SDT_RISCVPASUB>; +def riscv_pasubu : RVSDNode<"PASUBU", SDT_RISCVPASUB>; + +let Predicates = [HasStdExtP] in { + def : PatGpr<abs, ABS>; + + // Basic 8-bit arithmetic patterns + def: Pat<(XLenVecI8VT (add GPR:$rs1, GPR:$rs2)), (PADD_B GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI8VT (sub GPR:$rs1, GPR:$rs2)), (PSUB_B GPR:$rs1, GPR:$rs2)>; + + // Basic 16-bit arithmetic patterns + def: Pat<(XLenVecI16VT (add GPR:$rs1, GPR:$rs2)), (PADD_H GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI16VT (sub GPR:$rs1, GPR:$rs2)), (PSUB_H GPR:$rs1, GPR:$rs2)>; + + // 8-bit saturating add/sub patterns + def: Pat<(XLenVecI8VT (saddsat GPR:$rs1, GPR:$rs2)), (PSADD_B GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI8VT (uaddsat GPR:$rs1, GPR:$rs2)), (PSADDU_B GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI8VT (ssubsat GPR:$rs1, GPR:$rs2)), (PSSUB_B GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI8VT (usubsat GPR:$rs1, GPR:$rs2)), (PSSUBU_B GPR:$rs1, GPR:$rs2)>; + + // 16-bit saturating add/sub patterns + def: Pat<(XLenVecI16VT (saddsat GPR:$rs1, GPR:$rs2)), (PSADD_H GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI16VT (uaddsat GPR:$rs1, GPR:$rs2)), (PSADDU_H GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI16VT (ssubsat GPR:$rs1, GPR:$rs2)), (PSSUB_H GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI16VT (usubsat GPR:$rs1, GPR:$rs2)), (PSSUBU_H GPR:$rs1, GPR:$rs2)>; + + // 8-bit averaging patterns + def: Pat<(XLenVecI8VT (avgfloors GPR:$rs1, GPR:$rs2)), (PAADD_B GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI8VT (avgflooru GPR:$rs1, GPR:$rs2)), (PAADDU_B GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI8VT (riscv_pasub GPR:$rs1, GPR:$rs2)), (PASUB_B GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI8VT (riscv_pasubu GPR:$rs1, GPR:$rs2)), (PASUBU_B GPR:$rs1, GPR:$rs2)>; + + // 16-bit averaging patterns + def: Pat<(XLenVecI16VT (avgfloors GPR:$rs1, GPR:$rs2)), (PAADD_H GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI16VT (avgflooru GPR:$rs1, GPR:$rs2)), (PAADDU_H GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI16VT (riscv_pasub GPR:$rs1, GPR:$rs2)), (PASUB_H GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI16VT (riscv_pasubu GPR:$rs1, GPR:$rs2)), (PASUBU_H GPR:$rs1, GPR:$rs2)>; + + // 8-bit absolute difference patterns + def: Pat<(XLenVecI8VT (abds GPR:$rs1, GPR:$rs2)), (PABD_B GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI8VT (abdu GPR:$rs1, GPR:$rs2)), (PABDU_B GPR:$rs1, GPR:$rs2)>; + + // 16-bit absolute difference patterns + def: Pat<(XLenVecI16VT (abds GPR:$rs1, GPR:$rs2)), (PABD_H GPR:$rs1, GPR:$rs2)>; + def: Pat<(XLenVecI16VT (abdu GPR:$rs1, GPR:$rs2)), (PABDU_H GPR:$rs1, GPR:$rs2)>; + + // 8-bit logical shift left patterns + def: Pat<(XLenVecI8VT (shl GPR:$rs1, (XLenVecI8VT (splat_vector uimm3:$shamt)))), + (PSLLI_B GPR:$rs1, uimm3:$shamt)>; + + // 16-bit logical shift left patterns + def: Pat<(XLenVecI16VT (shl GPR:$rs1, (XLenVecI16VT (splat_vector uimm4:$shamt)))), + (PSLLI_H GPR:$rs1, uimm4:$shamt)>; + + // 16-bit signed saturation shift left patterns + def: Pat<(XLenVecI16VT (sshlsat GPR:$rs1, (XLenVecI16VT (splat_vector uimm4:$shamt)))), + (PSSLAI_H GPR:$rs1, uimm4:$shamt)>; + + // 8-bit logical shift left + def: Pat<(XLenVecI8VT (shl GPR:$rs1, + (XLenVecI8VT (splat_vector (XLenVT GPR:$rs2))))), + (PSLL_BS GPR:$rs1, GPR:$rs2)>; + // 16-bit logical shift left + def: Pat<(XLenVecI16VT (shl GPR:$rs1, + (XLenVecI16VT (splat_vector (XLenVT GPR:$rs2))))), + (PSLL_HS GPR:$rs1, GPR:$rs2)>; + + // 8-bit PLI SD node pattern + def: Pat<(XLenVecI8VT (splat_vector simm8_unsigned:$imm8)), (PLI_B simm8_unsigned:$imm8)>; + // 16-bit PLI SD node pattern + def: Pat<(XLenVecI16VT (splat_vector simm10:$imm10)), (PLI_H simm10:$imm10)>; + + // // splat pattern + def: Pat<(XLenVecI8VT (splat_vector (XLenVT GPR:$rs2))), (PADD_BS (XLenVT X0), GPR:$rs2)>; + def: Pat<(XLenVecI16VT (splat_vector (XLenVT GPR:$rs2))), (PADD_HS (XLenVT X0), GPR:$rs2)>; +} // Predicates = [HasStdExtP] + +let Predicates = [HasStdExtP, IsRV32] in { + // Load/Store patterns + def : StPat<store, SW, GPR, v4i8>; + def : StPat<store, SW, GPR, v2i16>; + def : LdPat<load, LW, v4i8>; + def : LdPat<load, LW, v2i16>; + + // Build vector patterns + def : Pat<(v2i16 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b))), + (PACK GPR:$a, GPR:$b)>; +} // Predicates = [HasStdExtP, IsRV32] + +let Predicates = [HasStdExtP, IsRV64] in { + def : PatGpr<riscv_absw, ABSW>; + + // 32-bit PLI SD node pattern + def: Pat<(v2i32 (splat_vector simm10:$imm10)), (PLI_W simm10:$imm10)>; + + // Basic 32-bit arithmetic patterns + def: Pat<(v2i32 (add GPR:$rs1, GPR:$rs2)), (PADD_W GPR:$rs1, GPR:$rs2)>; + def: Pat<(v2i32 (sub GPR:$rs1, GPR:$rs2)), (PSUB_W GPR:$rs1, GPR:$rs2)>; + + // 32-bit saturating add/sub patterns + def: Pat<(v2i32 (saddsat GPR:$rs1, GPR:$rs2)), (PSADD_W GPR:$rs1, GPR:$rs2)>; + def: Pat<(v2i32 (uaddsat GPR:$rs1, GPR:$rs2)), (PSADDU_W GPR:$rs1, GPR:$rs2)>; + def: Pat<(v2i32 (ssubsat GPR:$rs1, GPR:$rs2)), (PSSUB_W GPR:$rs1, GPR:$rs2)>; + def: Pat<(v2i32 (usubsat GPR:$rs1, GPR:$rs2)), (PSSUBU_W GPR:$rs1, GPR:$rs2)>; + + // 32-bit averaging patterns + def: Pat<(v2i32 (avgfloors GPR:$rs1, GPR:$rs2)), (PAADD_W GPR:$rs1, GPR:$rs2)>; + def: Pat<(v2i32 (avgflooru GPR:$rs1, GPR:$rs2)), (PAADDU_W GPR:$rs1, GPR:$rs2)>; + + // 32-bit averaging-sub patterns + def: Pat<(v2i32 (riscv_pasub GPR:$rs1, GPR:$rs2)), (PASUB_W GPR:$rs1, GPR:$rs2)>; + def: Pat<(v2i32 (riscv_pasubu GPR:$rs1, GPR:$rs2)), (PASUBU_W GPR:$rs1, GPR:$rs2)>; + + // 32-bit logical shift left + def: Pat<(v2i32 (shl GPR:$rs1, (v2i32 (splat_vector (XLenVT GPR:$rs2))))), + (PSLL_WS GPR:$rs1, GPR:$rs2)>; + + // splat pattern + def: Pat<(v2i32 (splat_vector (XLenVT GPR:$rs2))), (PADD_WS (XLenVT X0), GPR:$rs2)>; + + // 32-bit logical shift left patterns + def: Pat<(v2i32 (shl GPR:$rs1, (v2i32 (splat_vector uimm5:$shamt)))), + (PSLLI_W GPR:$rs1, uimm5:$shamt)>; + + // 32-bit signed saturation shift left patterns + def: Pat<(v2i32 (sshlsat GPR:$rs1, (v2i32 (splat_vector uimm5:$shamt)))), + (PSSLAI_W GPR:$rs1, uimm5:$shamt)>; + + // Load/Store patterns + def : StPat<store, SD, GPR, v8i8>; + def : StPat<store, SD, GPR, v4i16>; + def : StPat<store, SD, GPR, v2i32>; + def : LdPat<load, LD, v8i8>; + def : LdPat<load, LD, v4i16>; + def : LdPat<load, LD, v2i32>; + + // Build vector patterns + def : Pat<(v8i8 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b), + (XLenVT GPR:$c), (XLenVT GPR:$d), + (XLenVT undef), (XLenVT undef), + (XLenVT undef), (XLenVT undef))), + (PPAIRE_H (PPAIRE_B GPR:$a, GPR:$b), (PPAIRE_B GPR:$c, GPR:$d))>; + + def : Pat<(v8i8 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b), + (XLenVT GPR:$c), (XLenVT GPR:$d), + (XLenVT GPR:$e), (XLenVT GPR:$f), + (XLenVT GPR:$g), (XLenVT GPR:$h))), + (PACK (PPAIRE_H (PPAIRE_B GPR:$a, GPR:$b), (PPAIRE_B GPR:$c, GPR:$d)), + (PPAIRE_H (PPAIRE_B GPR:$e, GPR:$f), (PPAIRE_B GPR:$g, GPR:$h)))>; + + def : Pat<(v4i16 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b), + (XLenVT undef), (XLenVT undef))), + (PPAIRE_H GPR:$a, GPR:$b)>; + + def : Pat<(v4i16 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b), + (XLenVT GPR:$c), (XLenVT GPR:$d))), + (PACK (PPAIRE_H GPR:$a, GPR:$b), (PPAIRE_H GPR:$c, GPR:$d))>; + + def : Pat<(v2i32 (build_vector (XLenVT GPR:$a), (XLenVT GPR:$b))), + (PACK GPR:$a, GPR:$b)>; +} // Predicates = [HasStdExtP, IsRV64] |