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path: root/llvm/lib/Target/RISCV/RISCVInstrInfo.h
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-rw-r--r--llvm/lib/Target/RISCV/RISCVInstrInfo.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index c5eddb9..800af26 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -79,10 +79,13 @@ enum RISCVMachineCombinerPattern : unsigned {
};
class RISCVInstrInfo : public RISCVGenInstrInfo {
+ const RISCVRegisterInfo RegInfo;
public:
explicit RISCVInstrInfo(const RISCVSubtarget &STI);
+ const RISCVRegisterInfo &getRegisterInfo() const { return RegInfo; }
+
MCInst getNop() const override;
Register isLoadFromStackSlot(const MachineInstr &MI,