diff options
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVFeatures.td')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVFeatures.td | 156 |
1 files changed, 101 insertions, 55 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 2754d78..1a5bb83 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -194,6 +194,10 @@ def HasStdExtZilsd : Predicate<"Subtarget->hasStdExtZilsd()">, AssemblerPredicate<(all_of FeatureStdExtZilsd), "'Zilsd' (Load/Store pair instructions)">; +def FeatureZilsd4ByteAlign + : SubtargetFeature<"zilsd-4byte-align", "AllowZilsd4ByteAlign", "true", + "Allow 4-byte alignment for Zilsd LD/SD instructions">; + // Multiply Extensions def FeatureStdExtZmmul @@ -956,6 +960,9 @@ def FeatureStdExtSsdbltrp def FeatureStdExtSmepmp : RISCVExtension<1, 0, "Enhanced Physical Memory Protection">; +def FeatureStdExtSmpmpmt + : RISCVExperimentalExtension<0, 6, "PMP-based Memory Types Extension">; + def FeatureStdExtSmrnmi : RISCVExtension<1, 0, "Resumable Non-Maskable Interrupts">; def HasStdExtSmrnmi : Predicate<"Subtarget->hasStdExtSmrnmi()">, @@ -1099,38 +1106,18 @@ def HasStdExtSmctrOrSsctr : Predicate<"Subtarget->hasStdExtSmctrOrSsctr()">, // Packed SIMD Extensions def FeatureStdExtP - : RISCVExperimentalExtension<0, 15, + : RISCVExperimentalExtension<0, 18, "'Base P' (Packed SIMD)">; def HasStdExtP : Predicate<"Subtarget->hasStdExtP()">, AssemblerPredicate<(all_of FeatureStdExtP), "'Base P' (Packed SIMD)">; -def HasStdExtZbaOrP - : Predicate<"Subtarget->hasStdExtZba() || Subtarget->hasStdExtP()">, - AssemblerPredicate<(any_of FeatureStdExtZba, FeatureStdExtP), - "'Zba' (Address Generation Instructions) or " - "'Base P' (Packed-SIMD)">; - -def HasStdExtZbbOrP - : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtP()">, - AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtP), - "'Zbb' (Basic Bit-Manipulation) or " - "'Base P' (Packed-SIMD)">; - def HasStdExtZbkbOrP : Predicate<"Subtarget->hasStdExtZbkb() || Subtarget->hasStdExtP()">, AssemblerPredicate<(any_of FeatureStdExtZbkb, FeatureStdExtP), "'Zbkb' (Bitmanip instructions for Cryptography) or " "'Base P' (Packed-SIMD)">; -def HasStdExtZbbOrZbkbOrP - : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb() || " - "Subtarget->hasStdExtP()">, - AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb, FeatureStdExtP), - "'Zbb' (Basic Bit-Manipulation) or " - "'Zbkb' (Bitmanip instructions for Cryptography) or " - "'Base P' (Packed-SIMD)">; - //===----------------------------------------------------------------------===// // Vendor extensions //===----------------------------------------------------------------------===// @@ -1784,6 +1771,45 @@ def FeatureUnalignedVectorMem "true", "Has reasonably performant unaligned vector " "loads and stores">; +// Assume that lock-free native-width atomics are available, even if the target +// and operating system combination would not usually provide them. The user +// is responsible for providing any necessary __sync implementations. Code +// built with this feature is not ABI-compatible with code built without this +// feature, if atomic variables are exposed across the ABI boundary. +def FeatureForcedAtomics : SubtargetFeature< + "forced-atomics", "HasForcedAtomics", "true", + "Assume that lock-free native-width atomics are available">; +def HasAtomicLdSt + : Predicate<"Subtarget->hasStdExtZalrsc() || Subtarget->hasForcedAtomics()">; + +// The RISC-V Unprivileged Architecture - ISA Volume 1 (Version: 20250508) +// [https://docs.riscv.org/reference/isa/_attachments/riscv-unprivileged.pdf] +// in section 13.3. Eventual Success of Store-Conditional Instructions, defines +// _constrained_ LR/SC loops: +// The dynamic code executed between the LR and SC instructions can only +// contain instructions from the base ''I'' instruction set, excluding loads, +// stores, backward jumps, taken backward branches, JALR, FENCE, and SYSTEM +// instructions. Compressed forms of the aforementioned ''I'' instructions in +// the Zca and Zcb extensions are also permitted. +// LR/SC loops that do not adhere to the above are _unconstrained_ LR/SC loops, +// and success is implementation specific. For implementations which know that +// non-base instructions (such as the ''B'' extension) will not violate any +// forward progress guarantees, using these instructions to reduce the LR/SC +// sequence length is desirable. +def FeaturePermissiveZalrsc + : SubtargetFeature< + "permissive-zalrsc", "HasPermissiveZalrsc", "true", + "Implementation permits non-base instructions between LR/SC pairs">; + +def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", + "AllowTaggedGlobals", + "true", "Use an instruction sequence for taking the address of a global " + "that allows a memory tag in the upper address bits">; + +//===----------------------------------------------------------------------===// +// Tuning features +//===----------------------------------------------------------------------===// + def TuneNLogNVRGather : SubtargetFeature<"log-vrgather", "RISCVVRGatherCostModel", "NLog2N", "Has vrgather.vv with LMUL*log2(LMUL) latency">; @@ -1843,13 +1869,44 @@ def TuneNoDefaultUnroll : SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false", "Disable default unroll preference.">; -// SiFive 7 is able to fuse integer ALU operations with a preceding branch -// instruction. -def TuneShortForwardBranchOpt - : SubtargetFeature<"short-forward-branch-opt", "HasShortForwardBranchOpt", - "true", "Enable short forward branch optimization">; -def HasShortForwardBranchOpt : Predicate<"Subtarget->hasShortForwardBranchOpt()">; -def NoShortForwardBranchOpt : Predicate<"!Subtarget->hasShortForwardBranchOpt()">; +// Many Microarchitectures are able to fuse a branch over a single instruction +// with the branched-over instruction. We call this fusion "short forward +// branches". +// +// We can do this for a variety of instruction groups, depending on the +// microarch. We broadly group these by their scheduler class: +// - IALU: RVI Integer instructions, plus ANDN/ORN/XNOR (Zbb/Zbkb) +// - IMinMax: Zbb MIN(U)/MAX(U) +// - IMul: MUL +// +// We make the simplifying assumption that any microarches that implement +// any "short forward branches" can do the IALU fusions, and can opt into +// the other fusions they implement. +// +// The important Pseudo used by all these instructions requires the IALU +// short forward branches. +// +// Vendor-specific short-forward-branch opts may be added under IALU, as +// the vendor-specific instructions should only be enabled for vendor +// cores. +def TuneShortForwardBranchIALU + : SubtargetFeature<"short-forward-branch-ialu", "HasShortForwardBranchIALU", + "true", "Enable short forward branch optimization for RVI base instructions">; +def HasShortForwardBranchIALU : Predicate<"Subtarget->hasShortForwardBranchIALU()">; +def NoShortForwardBranch : Predicate<"!Subtarget->hasShortForwardBranchIALU()">; + +def TuneShortForwardBranchIMinMax + : SubtargetFeature<"short-forward-branch-iminmax", "HasShortForwardBranchIMinMax", + "true", "Enable short forward branch optimization for MIN,MAX instructions in Zbb", + [TuneShortForwardBranchIALU]>; +def HasShortForwardBranchIMinMax : Predicate<"Subtarget->hasShortForwardBranchIMinMax()">; + +def TuneShortForwardBranchIMul + : SubtargetFeature<"short-forward-branch-imul", "HasShortForwardBranchIMul", + "true", "Enable short forward branch optimization for MUL instruction", + [TuneShortForwardBranchIALU]>; +def HasShortForwardBranchIMul : Predicate<"Subtarget->hasShortForwardBranchIMul()">; + // Some subtargets require a S2V transfer buffer to move scalars into vectors. // FIXME: Forming .vx/.vf/.wx/.wf can reduce register pressure. @@ -1873,19 +1930,6 @@ def TuneHasSingleElementVecFP64 "Certain vector FP64 operations produce a single result " "element per cycle">; -def TuneMIPSP8700 - : SubtargetFeature<"mips-p8700", "RISCVProcFamily", "MIPSP8700", - "MIPS p8700 processor">; - -def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7", - "SiFive 7-Series processors">; - -def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron", - "Ventana Veyron-Series processors">; - -def TuneAndes45 : SubtargetFeature<"andes45", "RISCVProcFamily", "Andes45", - "Andes 45-Series processors">; - def TuneVXRMPipelineFlush : SubtargetFeature<"vxrm-pipeline-flush", "HasVXRMPipelineFlush", "true", "VXRM writes causes pipeline flush">; @@ -1895,18 +1939,20 @@ def TunePreferVsetvliOverReadVLENB "true", "Prefer vsetvli over read vlenb CSR to calculate VLEN">; -// Assume that lock-free native-width atomics are available, even if the target -// and operating system combination would not usually provide them. The user -// is responsible for providing any necessary __sync implementations. Code -// built with this feature is not ABI-compatible with code built without this -// feature, if atomic variables are exposed across the ABI boundary. -def FeatureForcedAtomics : SubtargetFeature< - "forced-atomics", "HasForcedAtomics", "true", - "Assume that lock-free native-width atomics are available">; -def HasAtomicLdSt - : Predicate<"Subtarget->hasStdExtZalrsc() || Subtarget->hasForcedAtomics()">; +//===----------------------------------------------------------------------===// +// CPU Families (alphabetized by vendor). +//===----------------------------------------------------------------------===// + +def TuneAndes45 : SubtargetFeature<"andes45", "RISCVProcFamily", "Andes45", + "Andes 45-Series processors">; + +def TuneMIPSP8700 + : SubtargetFeature<"mips-p8700", "RISCVProcFamily", "MIPSP8700", + "MIPS p8700 processor">; + +def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7", + "SiFive 7-Series processors">; + +def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron", + "Ventana Veyron-Series processors">; -def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", - "AllowTaggedGlobals", - "true", "Use an instruction sequence for taking the address of a global " - "that allows a memory tag in the upper address bits">; |