diff options
Diffstat (limited to 'llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h')
| -rw-r--r-- | llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h index e75dfe3..dbf5cfe 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -393,7 +393,6 @@ enum OperandType : unsigned { OPERAND_UIMM14_LSB00, OPERAND_UIMM16, OPERAND_UIMM16_NONZERO, - OPERAND_UIMM20, OPERAND_UIMMLOG2XLEN, OPERAND_UIMMLOG2XLEN_NONZERO, OPERAND_UIMM32, @@ -407,19 +406,16 @@ enum OperandType : unsigned { OPERAND_SIMM5_PLUS1, OPERAND_SIMM6, OPERAND_SIMM6_NONZERO, - OPERAND_SIMM8, OPERAND_SIMM8_UNSIGNED, OPERAND_SIMM10, OPERAND_SIMM10_LSB0000_NONZERO, OPERAND_SIMM10_UNSIGNED, OPERAND_SIMM11, - OPERAND_SIMM12, OPERAND_SIMM12_LSB00000, OPERAND_SIMM16, OPERAND_SIMM16_NONZERO, OPERAND_SIMM20_LI, OPERAND_SIMM26, - OPERAND_BARE_SIMM32, OPERAND_CLUI_IMM, OPERAND_VTYPEI10, OPERAND_VTYPEI11, @@ -448,6 +444,15 @@ enum OperandType : unsigned { // Vtype operand for XSfmm extension. OPERAND_XSFMM_VTYPE, OPERAND_LAST_RISCV_IMM = OPERAND_XSFMM_VTYPE, + + OPERAND_UIMM20_LUI, + OPERAND_UIMM20_AUIPC, + + // Simm12 or constant pool, global, basicblock, etc. + OPERAND_SIMM12_LO, + + OPERAND_BARE_SIMM32, + // Operand is either a register or uimm5, this is used by V extension pseudo // instructions to represent a value that be passed as AVL to either vsetvli // or vsetivli. @@ -701,7 +706,7 @@ enum RLISTENCODE { inline unsigned encodeRegList(MCRegister EndReg, bool IsRVE = false) { assert((!IsRVE || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E"); - switch (EndReg) { + switch (EndReg.id()) { case RISCV::X1: return RLISTENCODE::RA; case RISCV::X8: |