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-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrFuture.td20
1 files changed, 20 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index b0bed71c..da3efdc 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -194,6 +194,22 @@ class XX3Form_XTAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
let Inst{31} = XT{5};
}
+class XForm_RBS5<bits<6> opCode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<opCode, OOL, IOL, asmstr, itin> {
+
+ bits<5> RB;
+ bits<5> RS;
+
+ let Pattern = pattern;
+
+ let Inst{6...10} = RS;
+ let Inst{11...15} = 0;
+ let Inst{16...20} = RB;
+ let Inst{21...30} = xo;
+ let Inst{31} = 0;
+}
+
class XX3Form_XTAB6_S<bits<5> xo, dag OOL, dag IOL, string asmstr,
list<dag> pattern>
: I<59, OOL, IOL, asmstr, NoItinerary> {
@@ -317,12 +333,16 @@ let Predicates = [IsISAFuture] in {
def TLBIEIO
: XForm_RSB5_UIMM2<31, 18, (outs), (ins g8rc:$RB, g8rc:$RS, u2imm:$RIC),
"tlbieio $RB, $RS, $RIC", []>;
+ def MTLPL : XForm_RBS5<31, 275, (outs), (ins gprc:$RB, gprc:$RS),
+ "mtlpl $RB, $RS", IIC_SprMTSPR, []>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
def TLBIEP8
: XForm_RSB5_UIMM2_2UIMM1<31, 50, (outs),
(ins g8rc:$RB, g8rc:$RS, u2imm:$RIC,
u1imm:$PRS, u1imm:$R),
"tlbiep $RB, $RS, $RIC, $PRS, $R", []>;
+ def MTLPL8 : XForm_RBS5<31, 275, (outs), (ins g8rc:$RB, g8rc:$RS),
+ "mtlpl $RB, $RS", IIC_SprMTSPR, []>, isPPC64;
}
}