diff options
Diffstat (limited to 'llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp | 41 |
1 files changed, 40 insertions, 1 deletions
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp index 729c077..5d5553c 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp @@ -318,7 +318,7 @@ static Instruction *convertNvvmIntrinsicToLlvm(InstCombiner &IC, // answer. These include: // // - nvvm_cos_approx_{f,ftz_f} - // - nvvm_ex2_approx_{d,f,ftz_f} + // - nvvm_ex2_approx(_ftz) // - nvvm_lg2_approx_{d,f,ftz_f} // - nvvm_sin_approx_{f,ftz_f} // - nvvm_sqrt_approx_{f,ftz_f} @@ -592,6 +592,45 @@ Value *NVPTXTTIImpl::rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, return nullptr; } +bool NVPTXTTIImpl::isLegalMaskedStore(Type *DataTy, Align Alignment, + unsigned AddrSpace, + TTI::MaskKind MaskKind) const { + if (MaskKind != TTI::MaskKind::ConstantMask) + return false; + + // We currently only support this feature for 256-bit vectors, so the + // alignment must be at least 32 + if (Alignment < 32) + return false; + + if (!ST->has256BitVectorLoadStore(AddrSpace)) + return false; + + auto *VTy = dyn_cast<FixedVectorType>(DataTy); + if (!VTy) + return false; + + auto *ElemTy = VTy->getScalarType(); + return (ElemTy->getScalarSizeInBits() == 32 && VTy->getNumElements() == 8) || + (ElemTy->getScalarSizeInBits() == 64 && VTy->getNumElements() == 4); +} + +bool NVPTXTTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment, + unsigned /*AddrSpace*/, + TTI::MaskKind MaskKind) const { + if (MaskKind != TTI::MaskKind::ConstantMask) + return false; + + if (Alignment < DL.getTypeStoreSize(DataTy)) + return false; + + // We do not support sub-byte element type masked loads. + auto *VTy = dyn_cast<FixedVectorType>(DataTy); + if (!VTy) + return false; + return VTy->getElementType()->getScalarSizeInBits() >= 8; +} + unsigned NVPTXTTIImpl::getLoadStoreVecRegBitWidth(unsigned AddrSpace) const { // 256 bit loads/stores are currently only supported for global address space if (ST->has256BitVectorLoadStore(AddrSpace)) |
