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Diffstat (limited to 'llvm/lib/Target/ARM/ARMSubtarget.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMSubtarget.cpp9
1 files changed, 4 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 5d052c08..a26fba1 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -310,15 +310,14 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
(hasV7Ops() && (isTargetLinux() || isTargetNaCl() ||
isTargetNetBSD())) ||
(hasV6Ops() && (isTargetMachO() || isTargetNetBSD()));
- // The one exception is cortex-m0, which despite being v6, does not
- // support unaligned accesses. Rather than make the above boolean
- // expression even more obtuse, just override the value here.
- if (isThumb1Only() && isMClass())
- AllowsUnalignedMem = false;
} else {
AllowsUnalignedMem = !(Align == StrictAlign);
}
+ // No v6M core supports unaligned memory access (v6M ARM ARM A3.2)
+ if (isV6M())
+ AllowsUnalignedMem = false;
+
switch (IT) {
case DefaultIT:
RestrictIT = hasV8Ops() ? true : false;