diff options
Diffstat (limited to 'llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 4693407..4a5b672 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -495,7 +495,7 @@ void ARMLoadStoreOpt::UpdateBaseRegUses(MachineBasicBlock &MBB, bool InsertSub = false; unsigned Opc = MBBI->getOpcode(); - if (MBBI->readsRegister(Base)) { + if (MBBI->readsRegister(Base, /*TRI=*/nullptr)) { int Offset; bool IsLoad = Opc == ARM::tLDRi || Opc == ARM::tLDRHi || Opc == ARM::tLDRBi; @@ -560,7 +560,8 @@ void ARMLoadStoreOpt::UpdateBaseRegUses(MachineBasicBlock &MBB, return; } - if (MBBI->killsRegister(Base) || MBBI->definesRegister(Base)) + if (MBBI->killsRegister(Base, /*TRI=*/nullptr) || + MBBI->definesRegister(Base, /*TRI=*/nullptr)) // Register got killed. Stop updating. return; } @@ -888,7 +889,7 @@ MachineInstr *ARMLoadStoreOpt::MergeOpsUpdate(const MergeCandidate &Cand) { if (is_contained(ImpDefs, DefReg)) continue; // We can ignore cases where the super-reg is read and written. - if (MI->readsRegister(DefReg)) + if (MI->readsRegister(DefReg, /*TRI=*/nullptr)) continue; ImpDefs.push_back(DefReg); } @@ -903,7 +904,7 @@ MachineInstr *ARMLoadStoreOpt::MergeOpsUpdate(const MergeCandidate &Cand) { MachineBasicBlock &MBB = *LatestMI->getParent(); unsigned Offset = getMemoryOpOffset(*First); Register Base = getLoadStoreBaseOp(*First).getReg(); - bool BaseKill = LatestMI->killsRegister(Base); + bool BaseKill = LatestMI->killsRegister(Base, /*TRI=*/nullptr); Register PredReg; ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg); DebugLoc DL = First->getDebugLoc(); @@ -2076,7 +2077,8 @@ bool ARMLoadStoreOpt::CombineMovBx(MachineBasicBlock &MBB) { MachineBasicBlock::iterator Prev = MBBI; --Prev; - if (Prev->getOpcode() != ARM::tMOVr || !Prev->definesRegister(ARM::LR)) + if (Prev->getOpcode() != ARM::tMOVr || + !Prev->definesRegister(ARM::LR, /*TRI=*/nullptr)) return false; for (auto Use : Prev->uses()) @@ -3176,7 +3178,7 @@ bool ARMPreAllocLoadStoreOpt::DistributeIncrements(Register Base) { if (PrePostInc || BaseAccess->getParent() != Increment->getParent()) return false; Register PredReg; - if (Increment->definesRegister(ARM::CPSR) || + if (Increment->definesRegister(ARM::CPSR, /*TRI=*/nullptr) || getInstrPredicate(*Increment, PredReg) != ARMCC::AL) return false; |