diff options
Diffstat (limited to 'llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 28fe01c..fd06bfd 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -2726,9 +2726,18 @@ static bool isLegalOrConvertableAddressImm(unsigned Opcode, int Imm, // by -Offset. This can either happen in-place or be a replacement as MI is // converted to another instruction type. static void AdjustBaseAndOffset(MachineInstr *MI, Register NewBaseReg, - int Offset, const TargetInstrInfo *TII) { + int Offset, const TargetInstrInfo *TII, + const TargetRegisterInfo *TRI) { + // Set the Base reg unsigned BaseOp = getBaseOperandIndex(*MI); MI->getOperand(BaseOp).setReg(NewBaseReg); + // and constrain the reg class to that required by the instruction. + MachineFunction *MF = MI->getMF(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + const MCInstrDesc &MCID = TII->get(MI->getOpcode()); + const TargetRegisterClass *TRC = TII->getRegClass(MCID, BaseOp, TRI, *MF); + MRI.constrainRegClass(NewBaseReg, TRC); + int OldOffset = MI->getOperand(BaseOp + 1).getImm(); if (isLegalAddressImm(MI->getOpcode(), OldOffset - Offset, TII)) MI->getOperand(BaseOp + 1).setImm(OldOffset - Offset); @@ -2971,7 +2980,7 @@ bool ARMPreAllocLoadStoreOpt::DistributeIncrements(Register Base) { for (auto *Use : SuccessorAccesses) { LLVM_DEBUG(dbgs() << "Changing: "; Use->dump()); - AdjustBaseAndOffset(Use, NewBaseReg, IncrementOffset, TII); + AdjustBaseAndOffset(Use, NewBaseReg, IncrementOffset, TII, TRI); LLVM_DEBUG(dbgs() << " To : "; Use->dump()); } |