diff options
Diffstat (limited to 'llvm/lib/Target/ARM/ARMFrameLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMFrameLowering.cpp | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp index 5fa7068..ae5a45f 100644 --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -357,6 +357,34 @@ static MachineBasicBlock::iterator insertSEH(MachineBasicBlock::iterator MBBI, .setMIFlags(Flags); break; + case ARM::t2STR_PRE: + if (MBBI->getOperand(0).getReg() == ARM::SP && + MBBI->getOperand(2).getReg() == ARM::SP && + MBBI->getOperand(3).getImm() == -4) { + unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); + MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs)) + .addImm(1 << Reg) + .addImm(/*Wide=*/1) + .setMIFlags(Flags); + } else { + report_fatal_error("No matching SEH Opcode for t2STR_PRE"); + } + break; + + case ARM::t2LDR_POST: + if (MBBI->getOperand(1).getReg() == ARM::SP && + MBBI->getOperand(2).getReg() == ARM::SP && + MBBI->getOperand(3).getImm() == 4) { + unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); + MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs)) + .addImm(1 << Reg) + .addImm(/*Wide=*/1) + .setMIFlags(Flags); + } else { + report_fatal_error("No matching SEH Opcode for t2LDR_POST"); + } + break; + case ARM::t2LDMIA_RET: case ARM::t2LDMIA_UPD: case ARM::t2STMDB_UPD: { |