diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp index 774920a..c47eea2 100644 --- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp @@ -2055,10 +2055,16 @@ bool SILoadStoreOptimizer::promoteConstantOffsetToImm( if (!(MI.mayLoad() ^ MI.mayStore())) return false; - // TODO: Support flat and scratch. - if (AMDGPU::getGlobalSaddrOp(MI.getOpcode()) < 0) + if (!STM->hasFlatInstOffsets() || !SIInstrInfo::isFLAT(MI)) return false; + // TODO: Support FLAT_SCRATCH. Currently code expects 64-bit pointers. + if (SIInstrInfo::isFLATScratch(MI)) + return false; + + unsigned AS = SIInstrInfo::isFLATGlobal(MI) ? AMDGPUAS::GLOBAL_ADDRESS + : AMDGPUAS::FLAT_ADDRESS; + if (MI.mayLoad() && TII->getNamedOperand(MI, AMDGPU::OpName::vdata) != nullptr) return false; @@ -2157,7 +2163,7 @@ bool SILoadStoreOptimizer::promoteConstantOffsetToImm( TargetLoweringBase::AddrMode AM; AM.HasBaseReg = true; AM.BaseOffs = Dist; - if (TLI->isLegalGlobalAddressingMode(AM) && + if (TLI->isLegalFlatAddressingMode(AM, AS) && (uint32_t)std::abs(Dist) > MaxDist) { MaxDist = std::abs(Dist); @@ -2183,7 +2189,7 @@ bool SILoadStoreOptimizer::promoteConstantOffsetToImm( AM.HasBaseReg = true; AM.BaseOffs = OtherOffset - AnchorAddr.Offset; - if (TLI->isLegalGlobalAddressingMode(AM)) { + if (TLI->isLegalFlatAddressingMode(AM, AS)) { LLVM_DEBUG(dbgs() << " Promote Offset(" << OtherOffset; dbgs() << ")"; OtherMI->dump()); updateBaseAndOffset(*OtherMI, Base, OtherOffset - AnchorAddr.Offset); |