aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64InstrInfo.cpp')
-rw-r--r--llvm/lib/Target/AArch64/AArch64InstrInfo.cpp362
1 files changed, 300 insertions, 62 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 66e4949..f82180f 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -241,6 +241,17 @@ static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
Cond.push_back(LastInst->getOperand(1));
Cond.push_back(LastInst->getOperand(2));
break;
+ case AArch64::CBBAssertExt:
+ case AArch64::CBHAssertExt:
+ Target = LastInst->getOperand(3).getMBB();
+ Cond.push_back(MachineOperand::CreateImm(-1)); // -1
+ Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); // Opc
+ Cond.push_back(LastInst->getOperand(0)); // Cond
+ Cond.push_back(LastInst->getOperand(1)); // Op0
+ Cond.push_back(LastInst->getOperand(2)); // Op1
+ Cond.push_back(LastInst->getOperand(4)); // Ext0
+ Cond.push_back(LastInst->getOperand(5)); // Ext1
+ break;
}
}
@@ -264,6 +275,8 @@ static unsigned getBranchDisplacementBits(unsigned Opc) {
return BCCDisplacementBits;
case AArch64::CBWPri:
case AArch64::CBXPri:
+ case AArch64::CBBAssertExt:
+ case AArch64::CBHAssertExt:
case AArch64::CBWPrr:
case AArch64::CBXPrr:
return CBDisplacementBits;
@@ -298,6 +311,8 @@ AArch64InstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
return MI.getOperand(1).getMBB();
case AArch64::CBWPri:
case AArch64::CBXPri:
+ case AArch64::CBBAssertExt:
+ case AArch64::CBHAssertExt:
case AArch64::CBWPrr:
case AArch64::CBXPrr:
return MI.getOperand(3).getMBB();
@@ -580,9 +595,11 @@ bool AArch64InstrInfo::reverseBranchCondition(
Cond[1].setImm(AArch64::TBZX);
break;
- // Cond is { -1, Opcode, CC, Op0, Op1 }
+ // Cond is { -1, Opcode, CC, Op0, Op1, ... }
case AArch64::CBWPri:
case AArch64::CBXPri:
+ case AArch64::CBBAssertExt:
+ case AArch64::CBHAssertExt:
case AArch64::CBWPrr:
case AArch64::CBXPrr: {
// Pseudos using standard 4bit Arm condition codes
@@ -654,6 +671,12 @@ void AArch64InstrInfo::instantiateCondBranch(
MIB.add(Cond[4]);
MIB.addMBB(TBB);
+
+ // cb[b,h]
+ if (Cond.size() > 5) {
+ MIB.addImm(Cond[5].getImm());
+ MIB.addImm(Cond[6].getImm());
+ }
}
}
@@ -685,6 +708,53 @@ unsigned AArch64InstrInfo::insertBranch(
return 2;
}
+bool llvm::optimizeTerminators(MachineBasicBlock *MBB,
+ const TargetInstrInfo &TII) {
+ for (MachineInstr &MI : MBB->terminators()) {
+ unsigned Opc = MI.getOpcode();
+ switch (Opc) {
+ case AArch64::CBZW:
+ case AArch64::CBZX:
+ case AArch64::TBZW:
+ case AArch64::TBZX:
+ // CBZ/TBZ with WZR/XZR -> unconditional B
+ if (MI.getOperand(0).getReg() == AArch64::WZR ||
+ MI.getOperand(0).getReg() == AArch64::XZR) {
+ DEBUG_WITH_TYPE("optimizeTerminators",
+ dbgs() << "Removing always taken branch: " << MI);
+ MachineBasicBlock *Target = TII.getBranchDestBlock(MI);
+ SmallVector<MachineBasicBlock *> Succs(MBB->successors());
+ for (auto *S : Succs)
+ if (S != Target)
+ MBB->removeSuccessor(S);
+ DebugLoc DL = MI.getDebugLoc();
+ while (MBB->rbegin() != &MI)
+ MBB->rbegin()->eraseFromParent();
+ MI.eraseFromParent();
+ BuildMI(MBB, DL, TII.get(AArch64::B)).addMBB(Target);
+ return true;
+ }
+ break;
+ case AArch64::CBNZW:
+ case AArch64::CBNZX:
+ case AArch64::TBNZW:
+ case AArch64::TBNZX:
+ // CBNZ/TBNZ with WZR/XZR -> never taken, remove branch and successor
+ if (MI.getOperand(0).getReg() == AArch64::WZR ||
+ MI.getOperand(0).getReg() == AArch64::XZR) {
+ DEBUG_WITH_TYPE("optimizeTerminators",
+ dbgs() << "Removing never taken branch: " << MI);
+ MachineBasicBlock *Target = TII.getBranchDestBlock(MI);
+ MI.getParent()->removeSuccessor(Target);
+ MI.eraseFromParent();
+ return true;
+ }
+ break;
+ }
+ }
+ return false;
+}
+
// Find the original register that VReg is copied from.
static unsigned removeCopies(const MachineRegisterInfo &MRI, unsigned VReg) {
while (Register::isVirtualRegister(VReg)) {
@@ -931,44 +1001,122 @@ void AArch64InstrInfo::insertSelect(MachineBasicBlock &MBB,
// We must insert a cmp, that is a subs
// 0 1 2 3 4
// Cond is { -1, Opcode, CC, Op0, Op1 }
- unsigned SUBSOpC, SUBSDestReg;
+
+ unsigned SubsOpc, SubsDestReg;
bool IsImm = false;
CC = static_cast<AArch64CC::CondCode>(Cond[2].getImm());
switch (Cond[1].getImm()) {
default:
llvm_unreachable("Unknown branch opcode in Cond");
case AArch64::CBWPri:
- SUBSOpC = AArch64::SUBSWri;
- SUBSDestReg = AArch64::WZR;
+ SubsOpc = AArch64::SUBSWri;
+ SubsDestReg = AArch64::WZR;
IsImm = true;
break;
case AArch64::CBXPri:
- SUBSOpC = AArch64::SUBSXri;
- SUBSDestReg = AArch64::XZR;
+ SubsOpc = AArch64::SUBSXri;
+ SubsDestReg = AArch64::XZR;
IsImm = true;
break;
case AArch64::CBWPrr:
- SUBSOpC = AArch64::SUBSWrr;
- SUBSDestReg = AArch64::WZR;
+ SubsOpc = AArch64::SUBSWrr;
+ SubsDestReg = AArch64::WZR;
IsImm = false;
break;
case AArch64::CBXPrr:
- SUBSOpC = AArch64::SUBSXrr;
- SUBSDestReg = AArch64::XZR;
+ SubsOpc = AArch64::SUBSXrr;
+ SubsDestReg = AArch64::XZR;
IsImm = false;
break;
}
if (IsImm)
- BuildMI(MBB, I, DL, get(SUBSOpC), SUBSDestReg)
+ BuildMI(MBB, I, DL, get(SubsOpc), SubsDestReg)
.addReg(Cond[3].getReg())
.addImm(Cond[4].getImm())
.addImm(0);
else
- BuildMI(MBB, I, DL, get(SUBSOpC), SUBSDestReg)
+ BuildMI(MBB, I, DL, get(SubsOpc), SubsDestReg)
.addReg(Cond[3].getReg())
.addReg(Cond[4].getReg());
- }
+ } break;
+ case 7: { // cb[b,h]
+ // We must insert a cmp, that is a subs, but also zero- or sign-extensions
+ // that have been folded. For the first operand we codegen an explicit
+ // extension, for the second operand we fold the extension into cmp.
+ // 0 1 2 3 4 5 6
+ // Cond is { -1, Opcode, CC, Op0, Op1, Ext0, Ext1 }
+
+ // We need a new register for the now explicitly extended register
+ Register Reg = Cond[4].getReg();
+ if (Cond[5].getImm() != AArch64_AM::InvalidShiftExtend) {
+ unsigned ExtOpc;
+ unsigned ExtBits;
+ AArch64_AM::ShiftExtendType ExtendType =
+ AArch64_AM::getExtendType(Cond[5].getImm());
+ switch (ExtendType) {
+ default:
+ llvm_unreachable("Unknown shift-extend for CB instruction");
+ case AArch64_AM::SXTB:
+ assert(
+ Cond[1].getImm() == AArch64::CBBAssertExt &&
+ "Unexpected compare-and-branch instruction for SXTB shift-extend");
+ ExtOpc = AArch64::SBFMWri;
+ ExtBits = AArch64_AM::encodeLogicalImmediate(0xff, 32);
+ break;
+ case AArch64_AM::SXTH:
+ assert(
+ Cond[1].getImm() == AArch64::CBHAssertExt &&
+ "Unexpected compare-and-branch instruction for SXTH shift-extend");
+ ExtOpc = AArch64::SBFMWri;
+ ExtBits = AArch64_AM::encodeLogicalImmediate(0xffff, 32);
+ break;
+ case AArch64_AM::UXTB:
+ assert(
+ Cond[1].getImm() == AArch64::CBBAssertExt &&
+ "Unexpected compare-and-branch instruction for UXTB shift-extend");
+ ExtOpc = AArch64::ANDWri;
+ ExtBits = AArch64_AM::encodeLogicalImmediate(0xff, 32);
+ break;
+ case AArch64_AM::UXTH:
+ assert(
+ Cond[1].getImm() == AArch64::CBHAssertExt &&
+ "Unexpected compare-and-branch instruction for UXTH shift-extend");
+ ExtOpc = AArch64::ANDWri;
+ ExtBits = AArch64_AM::encodeLogicalImmediate(0xffff, 32);
+ break;
+ }
+
+ // Build the explicit extension of the first operand
+ Reg = MRI.createVirtualRegister(&AArch64::GPR32spRegClass);
+ MachineInstrBuilder MBBI =
+ BuildMI(MBB, I, DL, get(ExtOpc), Reg).addReg(Cond[4].getReg());
+ if (ExtOpc != AArch64::ANDWri)
+ MBBI.addImm(0);
+ MBBI.addImm(ExtBits);
+ }
+
+ // Now, subs with an extended second operand
+ if (Cond[6].getImm() != AArch64_AM::InvalidShiftExtend) {
+ AArch64_AM::ShiftExtendType ExtendType =
+ AArch64_AM::getExtendType(Cond[6].getImm());
+ MRI.constrainRegClass(Reg, MRI.getRegClass(Cond[3].getReg()));
+ MRI.constrainRegClass(Cond[3].getReg(), &AArch64::GPR32spRegClass);
+ BuildMI(MBB, I, DL, get(AArch64::SUBSWrx), AArch64::WZR)
+ .addReg(Cond[3].getReg())
+ .addReg(Reg)
+ .addImm(AArch64_AM::getArithExtendImm(ExtendType, 0));
+ } // If no extension is needed, just a regular subs
+ else {
+ MRI.constrainRegClass(Reg, MRI.getRegClass(Cond[3].getReg()));
+ MRI.constrainRegClass(Cond[3].getReg(), &AArch64::GPR32spRegClass);
+ BuildMI(MBB, I, DL, get(AArch64::SUBSWrr), AArch64::WZR)
+ .addReg(Cond[3].getReg())
+ .addReg(Reg);
+ }
+
+ CC = static_cast<AArch64CC::CondCode>(Cond[2].getImm());
+ } break;
}
unsigned Opc = 0;
@@ -1043,6 +1191,28 @@ static bool isCheapImmediate(const MachineInstr &MI, unsigned BitSize) {
return Is.size() <= 2;
}
+// Check if a COPY instruction is cheap.
+static bool isCheapCopy(const MachineInstr &MI, const AArch64RegisterInfo &RI) {
+ assert(MI.isCopy() && "Expected COPY instruction");
+ const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
+
+ // Cross-bank copies (e.g., between GPR and FPR) are expensive on AArch64,
+ // typically requiring an FMOV instruction with a 2-6 cycle latency.
+ auto GetRegClass = [&](Register Reg) -> const TargetRegisterClass * {
+ if (Reg.isVirtual())
+ return MRI.getRegClass(Reg);
+ if (Reg.isPhysical())
+ return RI.getMinimalPhysRegClass(Reg);
+ return nullptr;
+ };
+ const TargetRegisterClass *DstRC = GetRegClass(MI.getOperand(0).getReg());
+ const TargetRegisterClass *SrcRC = GetRegClass(MI.getOperand(1).getReg());
+ if (DstRC && SrcRC && !RI.getCommonSubClass(DstRC, SrcRC))
+ return false;
+
+ return MI.isAsCheapAsAMove();
+}
+
// FIXME: this implementation should be micro-architecture dependent, so a
// micro-architecture target hook should be introduced here in future.
bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
@@ -1056,6 +1226,9 @@ bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
default:
return MI.isAsCheapAsAMove();
+ case TargetOpcode::COPY:
+ return isCheapCopy(MI, RI);
+
case AArch64::ADDWrs:
case AArch64::ADDXrs:
case AArch64::SUBWrs:
@@ -1776,10 +1949,14 @@ static unsigned sForm(MachineInstr &Instr) {
case AArch64::ADDSWri:
case AArch64::ADDSXrr:
case AArch64::ADDSXri:
+ case AArch64::ADDSWrx:
+ case AArch64::ADDSXrx:
case AArch64::SUBSWrr:
case AArch64::SUBSWri:
+ case AArch64::SUBSWrx:
case AArch64::SUBSXrr:
case AArch64::SUBSXri:
+ case AArch64::SUBSXrx:
case AArch64::ANDSWri:
case AArch64::ANDSWrr:
case AArch64::ANDSWrs:
@@ -1800,6 +1977,10 @@ static unsigned sForm(MachineInstr &Instr) {
return AArch64::ADDSXrr;
case AArch64::ADDXri:
return AArch64::ADDSXri;
+ case AArch64::ADDWrx:
+ return AArch64::ADDSWrx;
+ case AArch64::ADDXrx:
+ return AArch64::ADDSXrx;
case AArch64::ADCWr:
return AArch64::ADCSWr;
case AArch64::ADCXr:
@@ -1812,6 +1993,10 @@ static unsigned sForm(MachineInstr &Instr) {
return AArch64::SUBSXrr;
case AArch64::SUBXri:
return AArch64::SUBSXri;
+ case AArch64::SUBWrx:
+ return AArch64::SUBSWrx;
+ case AArch64::SUBXrx:
+ return AArch64::SUBSXrx;
case AArch64::SBCWr:
return AArch64::SBCSWr;
case AArch64::SBCXr:
@@ -2440,11 +2625,10 @@ bool AArch64InstrInfo::isFPRCopy(const MachineInstr &MI) {
return false;
}
-Register AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
- int &FrameIndex) const {
- switch (MI.getOpcode()) {
+static bool isFrameLoadOpcode(int Opcode) {
+ switch (Opcode) {
default:
- break;
+ return false;
case AArch64::LDRWui:
case AArch64::LDRXui:
case AArch64::LDRBui:
@@ -2453,22 +2637,27 @@ Register AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
case AArch64::LDRDui:
case AArch64::LDRQui:
case AArch64::LDR_PXI:
- if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
- MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
- FrameIndex = MI.getOperand(1).getIndex();
- return MI.getOperand(0).getReg();
- }
- break;
+ return true;
}
+}
+
+Register AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (!isFrameLoadOpcode(MI.getOpcode()))
+ return Register();
- return 0;
+ if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
+ MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
+ FrameIndex = MI.getOperand(1).getIndex();
+ return MI.getOperand(0).getReg();
+ }
+ return Register();
}
-Register AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
- int &FrameIndex) const {
- switch (MI.getOpcode()) {
+static bool isFrameStoreOpcode(int Opcode) {
+ switch (Opcode) {
default:
- break;
+ return false;
case AArch64::STRWui:
case AArch64::STRXui:
case AArch64::STRBui:
@@ -2477,14 +2666,63 @@ Register AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
case AArch64::STRDui:
case AArch64::STRQui:
case AArch64::STR_PXI:
- if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
- MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
- FrameIndex = MI.getOperand(1).getIndex();
- return MI.getOperand(0).getReg();
- }
- break;
+ return true;
+ }
+}
+
+Register AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (!isFrameStoreOpcode(MI.getOpcode()))
+ return Register();
+
+ if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
+ MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
+ FrameIndex = MI.getOperand(1).getIndex();
+ return MI.getOperand(0).getReg();
}
- return 0;
+ return Register();
+}
+
+Register AArch64InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (!isFrameStoreOpcode(MI.getOpcode()))
+ return Register();
+
+ if (Register Reg = isStoreToStackSlot(MI, FrameIndex))
+ return Reg;
+
+ SmallVector<const MachineMemOperand *, 1> Accesses;
+ if (hasStoreToStackSlot(MI, Accesses)) {
+ if (Accesses.size() > 1)
+ return Register();
+
+ FrameIndex =
+ cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
+ ->getFrameIndex();
+ return MI.getOperand(0).getReg();
+ }
+ return Register();
+}
+
+Register AArch64InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
+ int &FrameIndex) const {
+ if (!isFrameLoadOpcode(MI.getOpcode()))
+ return Register();
+
+ if (Register Reg = isLoadFromStackSlot(MI, FrameIndex))
+ return Reg;
+
+ SmallVector<const MachineMemOperand *, 1> Accesses;
+ if (hasLoadFromStackSlot(MI, Accesses)) {
+ if (Accesses.size() > 1)
+ return Register();
+
+ FrameIndex =
+ cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
+ ->getFrameIndex();
+ return MI.getOperand(0).getReg();
+ }
+ return Register();
}
/// Check all MachineMemOperands for a hint to suppress pairing.
@@ -5664,7 +5902,6 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
Register SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC,
- const TargetRegisterInfo *TRI,
Register VReg,
MachineInstr::MIFlag Flags) const {
MachineFunction &MF = *MBB.getParent();
@@ -5678,7 +5915,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
bool Offset = true;
MCRegister PNRReg = MCRegister::NoRegister;
unsigned StackID = TargetStackID::Default;
- switch (TRI->getSpillSize(*RC)) {
+ switch (RI.getSpillSize(*RC)) {
case 1:
if (AArch64::FPR8RegClass.hasSubClassEq(RC))
Opc = AArch64::STRBui;
@@ -5841,10 +6078,12 @@ static void loadRegPairFromStackSlot(const TargetRegisterInfo &TRI,
.addMemOperand(MMO);
}
-void AArch64InstrInfo::loadRegFromStackSlot(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg,
- int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
- Register VReg, MachineInstr::MIFlag Flags) const {
+void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI,
+ Register DestReg, int FI,
+ const TargetRegisterClass *RC,
+ Register VReg,
+ MachineInstr::MIFlag Flags) const {
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);
@@ -5856,7 +6095,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
bool Offset = true;
unsigned StackID = TargetStackID::Default;
Register PNRReg = MCRegister::NoRegister;
- switch (TRI->getSpillSize(*RC)) {
+ switch (TRI.getSpillSize(*RC)) {
case 1:
if (AArch64::FPR8RegClass.hasSubClassEq(RC))
Opc = AArch64::LDRBui;
@@ -6492,10 +6731,10 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
"Mismatched register size in non subreg COPY");
if (IsSpill)
storeRegToStackSlot(MBB, InsertPt, SrcReg, SrcMO.isKill(), FrameIndex,
- getRegClass(SrcReg), &TRI, Register());
+ getRegClass(SrcReg), Register());
else
loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex,
- getRegClass(DstReg), &TRI, Register());
+ getRegClass(DstReg), Register());
return &*--InsertPt;
}
@@ -6513,8 +6752,7 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
assert(SrcMO.getSubReg() == 0 &&
"Unexpected subreg on physical register");
storeRegToStackSlot(MBB, InsertPt, AArch64::XZR, SrcMO.isKill(),
- FrameIndex, &AArch64::GPR64RegClass, &TRI,
- Register());
+ FrameIndex, &AArch64::GPR64RegClass, Register());
return &*--InsertPt;
}
@@ -6548,7 +6786,7 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
assert(TRI.getRegSizeInBits(*getRegClass(SrcReg)) ==
TRI.getRegSizeInBits(*FillRC) &&
"Mismatched regclass size on folded subreg COPY");
- loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex, FillRC, &TRI,
+ loadRegFromStackSlot(MBB, InsertPt, DstReg, FrameIndex, FillRC,
Register());
MachineInstr &LoadMI = *--InsertPt;
MachineOperand &LoadDst = LoadMI.getOperand(0);
@@ -6710,12 +6948,10 @@ bool llvm::rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
void AArch64InstrInfo::insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
DebugLoc DL;
- BuildMI(MBB, MI, DL, get(AArch64::HINT)).addImm(0);
+ BuildMI(MBB, MI, DL, get(AArch64::NOP));
}
-MCInst AArch64InstrInfo::getNop() const {
- return MCInstBuilder(AArch64::HINT).addImm(0);
-}
+MCInst AArch64InstrInfo::getNop() const { return MCInstBuilder(AArch64::NOP); }
// AArch64 supports MachineCombiner.
bool AArch64InstrInfo::useMachineCombiner() const { return true; }
@@ -9307,6 +9543,8 @@ bool AArch64InstrInfo::optimizeCondBranch(MachineInstr &MI) const {
case AArch64::Bcc:
case AArch64::CBWPri:
case AArch64::CBXPri:
+ case AArch64::CBBAssertExt:
+ case AArch64::CBHAssertExt:
case AArch64::CBWPrr:
case AArch64::CBXPrr:
return false;
@@ -9603,8 +9841,8 @@ outliningCandidatesSigningScopeConsensus(const outliner::Candidate &a,
const auto &MFIa = a.getMF()->getInfo<AArch64FunctionInfo>();
const auto &MFIb = b.getMF()->getInfo<AArch64FunctionInfo>();
- return MFIa->shouldSignReturnAddress(false) == MFIb->shouldSignReturnAddress(false) &&
- MFIa->shouldSignReturnAddress(true) == MFIb->shouldSignReturnAddress(true);
+ return MFIa->getSignReturnAddressCondition() ==
+ MFIb->getSignReturnAddressCondition();
}
static bool
@@ -9695,10 +9933,11 @@ AArch64InstrInfo::getOutliningCandidateInfo(
// Performing a tail call may require extra checks when PAuth is enabled.
// If PAuth is disabled, set it to zero for uniformity.
unsigned NumBytesToCheckLRInTCEpilogue = 0;
- if (RepeatedSequenceLocs[0]
- .getMF()
- ->getInfo<AArch64FunctionInfo>()
- ->shouldSignReturnAddress(true)) {
+ const auto RASignCondition = RepeatedSequenceLocs[0]
+ .getMF()
+ ->getInfo<AArch64FunctionInfo>()
+ ->getSignReturnAddressCondition();
+ if (RASignCondition != SignReturnAddress::None) {
// One PAC and one AUT instructions
NumBytesToCreateFrame += 8;
@@ -10502,7 +10741,9 @@ void AArch64InstrInfo::buildOutlinedFrame(
Et = MBB.insert(Et, LDRXpost);
}
- bool ShouldSignReturnAddr = FI->shouldSignReturnAddress(!IsLeafFunction);
+ auto RASignCondition = FI->getSignReturnAddressCondition();
+ bool ShouldSignReturnAddr = AArch64FunctionInfo::shouldSignReturnAddress(
+ RASignCondition, !IsLeafFunction);
// If this is a tail call outlined function, then there's already a return.
if (OF.FrameConstructionID == MachineOutlinerTailCall ||
@@ -11063,8 +11304,6 @@ static Register cloneInstr(const MachineInstr *MI, unsigned ReplaceOprNum,
MachineBasicBlock::iterator InsertTo) {
MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
const TargetInstrInfo *TII = MBB.getParent()->getSubtarget().getInstrInfo();
- const TargetRegisterInfo *TRI =
- MBB.getParent()->getSubtarget().getRegisterInfo();
MachineInstr *NewMI = MBB.getParent()->CloneMachineInstr(MI);
Register Result = 0;
for (unsigned I = 0; I < NewMI->getNumOperands(); ++I) {
@@ -11073,8 +11312,7 @@ static Register cloneInstr(const MachineInstr *MI, unsigned ReplaceOprNum,
MRI.getRegClass(NewMI->getOperand(0).getReg()));
NewMI->getOperand(I).setReg(Result);
} else if (I == ReplaceOprNum) {
- MRI.constrainRegClass(ReplaceReg,
- TII->getRegClass(NewMI->getDesc(), I, TRI));
+ MRI.constrainRegClass(ReplaceReg, TII->getRegClass(NewMI->getDesc(), I));
NewMI->getOperand(I).setReg(ReplaceReg);
}
}
generated by cgit v1.1 at 2026-01-04 22:45:59 +0000