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-rw-r--r--llvm/lib/IR/RuntimeLibcalls.cpp123
1 files changed, 123 insertions, 0 deletions
diff --git a/llvm/lib/IR/RuntimeLibcalls.cpp b/llvm/lib/IR/RuntimeLibcalls.cpp
index f4c5c6f..e66b9ad 100644
--- a/llvm/lib/IR/RuntimeLibcalls.cpp
+++ b/llvm/lib/IR/RuntimeLibcalls.cpp
@@ -10,6 +10,7 @@
#include "llvm/ADT/FloatingPointMode.h"
#include "llvm/ADT/StringTable.h"
#include "llvm/IR/Module.h"
+#include "llvm/IR/SystemLibraries.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/xxhash.h"
#include "llvm/TargetParser/ARMTargetParser.h"
@@ -25,6 +26,49 @@ using namespace RTLIB;
#define DEFINE_GET_LOOKUP_LIBCALL_IMPL_NAME
#include "llvm/IR/RuntimeLibcalls.inc"
+RuntimeLibcallsInfo::RuntimeLibcallsInfo(const Triple &TT,
+ ExceptionHandling ExceptionModel,
+ FloatABI::ABIType FloatABI,
+ EABI EABIVersion, StringRef ABIName) {
+ // FIXME: The ExceptionModel parameter is to handle the field in
+ // TargetOptions. This interface fails to distinguish the forced disable
+ // case for targets which support exceptions by default. This should
+ // probably be a module flag and removed from TargetOptions.
+ if (ExceptionModel == ExceptionHandling::None)
+ ExceptionModel = TT.getDefaultExceptionHandling();
+
+ initLibcalls(TT, ExceptionModel, FloatABI, EABIVersion, ABIName);
+
+ // TODO: Tablegen should generate these sets
+ switch (ClVectorLibrary) {
+ case VectorLibrary::SLEEFGNUABI:
+ for (RTLIB::LibcallImpl Impl :
+ {RTLIB::impl__ZGVnN2vl8l8_sincos, RTLIB::impl__ZGVnN4vl4l4_sincosf,
+ RTLIB::impl__ZGVsNxvl8l8_sincos, RTLIB::impl__ZGVsNxvl4l4_sincosf,
+ RTLIB::impl__ZGVnN4vl4l4_sincospif, RTLIB::impl__ZGVnN2vl8l8_sincospi,
+ RTLIB::impl__ZGVsNxvl4l4_sincospif,
+ RTLIB::impl__ZGVsNxvl8l8_sincospi})
+ setAvailable(Impl);
+ break;
+ case VectorLibrary::ArmPL:
+ for (RTLIB::LibcallImpl Impl :
+ {RTLIB::impl_armpl_vsincosq_f64, RTLIB::impl_armpl_vsincosq_f32,
+ RTLIB::impl_armpl_svsincos_f64_x, RTLIB::impl_armpl_svsincos_f32_x,
+ RTLIB::impl_armpl_vsincospiq_f32, RTLIB::impl_armpl_vsincospiq_f64,
+ RTLIB::impl_armpl_svsincospi_f32_x,
+ RTLIB::impl_armpl_svsincospi_f64_x})
+ setAvailable(Impl);
+
+ for (RTLIB::LibcallImpl Impl :
+ {RTLIB::impl_armpl_vsincosq_f64, RTLIB::impl_armpl_vsincosq_f32})
+ setLibcallImplCallingConv(Impl, CallingConv::AArch64_VectorCall);
+
+ break;
+ default:
+ break;
+ }
+}
+
RuntimeLibcallsInfo::RuntimeLibcallsInfo(const Module &M)
: RuntimeLibcallsInfo(M.getTargetTriple()) {
// TODO: Consider module flags
@@ -88,6 +132,8 @@ RuntimeLibcallsInfo::getFunctionTy(LLVMContext &Ctx, const Triple &TT,
static constexpr Attribute::AttrKind CommonFnAttrs[] = {
Attribute::NoCallback, Attribute::NoFree, Attribute::NoSync,
Attribute::NoUnwind, Attribute::WillReturn};
+ static constexpr Attribute::AttrKind CommonPtrArgAttrs[] = {
+ Attribute::NoAlias, Attribute::WriteOnly, Attribute::NonNull};
switch (LibcallImpl) {
case RTLIB::impl___sincos_stret:
@@ -151,9 +197,86 @@ RuntimeLibcallsInfo::getFunctionTy(LLVMContext &Ctx, const Triple &TT,
fcNegNormal));
return {FuncTy, Attrs};
}
+ case RTLIB::impl__ZGVnN2vl8l8_sincos:
+ case RTLIB::impl__ZGVnN4vl4l4_sincosf:
+ case RTLIB::impl__ZGVsNxvl8l8_sincos:
+ case RTLIB::impl__ZGVsNxvl4l4_sincosf:
+ case RTLIB::impl_armpl_vsincosq_f64:
+ case RTLIB::impl_armpl_vsincosq_f32:
+ case RTLIB::impl_armpl_svsincos_f64_x:
+ case RTLIB::impl_armpl_svsincos_f32_x:
+ case RTLIB::impl__ZGVnN4vl4l4_sincospif:
+ case RTLIB::impl__ZGVnN2vl8l8_sincospi:
+ case RTLIB::impl__ZGVsNxvl4l4_sincospif:
+ case RTLIB::impl__ZGVsNxvl8l8_sincospi:
+ case RTLIB::impl_armpl_vsincospiq_f32:
+ case RTLIB::impl_armpl_vsincospiq_f64:
+ case RTLIB::impl_armpl_svsincospi_f32_x:
+ case RTLIB::impl_armpl_svsincospi_f64_x: {
+ AttrBuilder FuncAttrBuilder(Ctx);
+
+ bool IsF32 = LibcallImpl == RTLIB::impl__ZGVnN4vl4l4_sincospif ||
+ LibcallImpl == RTLIB::impl__ZGVsNxvl4l4_sincospif ||
+ LibcallImpl == RTLIB::impl_armpl_vsincospiq_f32 ||
+ LibcallImpl == RTLIB::impl_armpl_svsincospi_f32_x ||
+ LibcallImpl == RTLIB::impl__ZGVnN4vl4l4_sincosf ||
+ LibcallImpl == RTLIB::impl__ZGVsNxvl4l4_sincosf ||
+ LibcallImpl == RTLIB::impl_armpl_vsincosq_f32 ||
+ LibcallImpl == RTLIB::impl_armpl_svsincos_f32_x;
+
+ Type *ScalarTy = IsF32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx);
+ unsigned EC = IsF32 ? 4 : 2;
+
+ bool IsScalable = LibcallImpl == RTLIB::impl__ZGVsNxvl8l8_sincos ||
+ LibcallImpl == RTLIB::impl__ZGVsNxvl4l4_sincosf ||
+ LibcallImpl == RTLIB::impl_armpl_svsincos_f32_x ||
+ LibcallImpl == RTLIB::impl_armpl_svsincos_f64_x ||
+ LibcallImpl == RTLIB::impl__ZGVsNxvl4l4_sincospif ||
+ LibcallImpl == RTLIB::impl__ZGVsNxvl8l8_sincospi ||
+ LibcallImpl == RTLIB::impl_armpl_svsincospi_f32_x ||
+ LibcallImpl == RTLIB::impl_armpl_svsincospi_f64_x;
+ VectorType *VecTy = VectorType::get(ScalarTy, EC, IsScalable);
+
+ for (Attribute::AttrKind Attr : CommonFnAttrs)
+ FuncAttrBuilder.addAttribute(Attr);
+ FuncAttrBuilder.addMemoryAttr(MemoryEffects::argMemOnly(ModRefInfo::Mod));
+
+ AttributeList Attrs;
+ Attrs = Attrs.addFnAttributes(Ctx, FuncAttrBuilder);
+
+ {
+ AttrBuilder ArgAttrBuilder(Ctx);
+ for (Attribute::AttrKind AK : CommonPtrArgAttrs)
+ ArgAttrBuilder.addAttribute(AK);
+ ArgAttrBuilder.addAlignmentAttr(DL.getABITypeAlign(VecTy));
+ Attrs = Attrs.addParamAttributes(Ctx, 1, ArgAttrBuilder);
+ Attrs = Attrs.addParamAttributes(Ctx, 2, ArgAttrBuilder);
+ }
+
+ PointerType *PtrTy = PointerType::get(Ctx, 0);
+ SmallVector<Type *, 4> ArgTys = {VecTy, PtrTy, PtrTy};
+ if (hasVectorMaskArgument(LibcallImpl))
+ ArgTys.push_back(VectorType::get(Type::getInt1Ty(Ctx), EC, IsScalable));
+
+ return {FunctionType::get(Type::getVoidTy(Ctx), ArgTys, false), Attrs};
+ }
default:
return {};
}
return {};
}
+
+bool RuntimeLibcallsInfo::hasVectorMaskArgument(RTLIB::LibcallImpl Impl) {
+ /// FIXME: This should be generated by tablegen and support the argument at an
+ /// arbitrary position
+ switch (Impl) {
+ case RTLIB::impl_armpl_svsincos_f32_x:
+ case RTLIB::impl_armpl_svsincos_f64_x:
+ case RTLIB::impl_armpl_svsincospi_f32_x:
+ case RTLIB::impl_armpl_svsincospi_f64_x:
+ return true;
+ default:
+ return false;
+ }
+}
generated by cgit v1.1 at 2025-11-11 06:23:29 +0000