diff options
Diffstat (limited to 'llvm/lib/CodeGen/TargetLoweringBase.cpp')
-rw-r--r-- | llvm/lib/CodeGen/TargetLoweringBase.cpp | 36 |
1 files changed, 34 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index acc2dce..6ec6498 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -955,6 +955,12 @@ static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned NumVectorRegs = 1; + // Scalable vectors cannot be scalarized, so splitting or widening is + // required. + if (VT.isScalableVector() && !isPowerOf2_32(EC.Min)) + llvm_unreachable( + "Splitting or widening of non-power-of-2 MVTs is not implemented."); + // FIXME: We don't support non-power-of-2-sized vectors for now. // Ideally we could break down into LHS/RHS like LegalizeDAG does. if (!isPowerOf2_32(EC.Min)) { @@ -1418,8 +1424,34 @@ unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT unsigned NumVectorRegs = 1; - // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we - // could break down into LHS/RHS like LegalizeDAG does. + // Scalable vectors cannot be scalarized, so handle the legalisation of the + // types like done elsewhere in SelectionDAG. + if (VT.isScalableVector() && !isPowerOf2_32(EltCnt.Min)) { + LegalizeKind LK; + EVT PartVT = VT; + do { + // Iterate until we've found a legal (part) type to hold VT. + LK = getTypeConversion(Context, PartVT); + PartVT = LK.second; + } while (LK.first != TypeLegal); + + NumIntermediates = + VT.getVectorElementCount().Min / PartVT.getVectorElementCount().Min; + + // FIXME: This code needs to be extended to handle more complex vector + // breakdowns, like nxv7i64 -> nxv8i64 -> 4 x nxv2i64. Currently the only + // supported cases are vectors that are broken down into equal parts + // such as nxv6i64 -> 3 x nxv2i64. + assert(NumIntermediates * PartVT.getVectorElementCount().Min == + VT.getVectorElementCount().Min && + "Expected an integer multiple of PartVT"); + IntermediateVT = PartVT; + RegisterVT = getRegisterType(Context, IntermediateVT); + return NumIntermediates; + } + + // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally + // we could break down into LHS/RHS like LegalizeDAG does. if (!isPowerOf2_32(EltCnt.Min)) { NumVectorRegs = EltCnt.Min; EltCnt.Min = 1; |