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path: root/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp

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M (0,0,1,1,1,1,1,1,1,0,0,0); break; case '%': mask = M (1,1,1,1,1,1,1,1,1,0,0,0); break; case ';': mask = M (1,0,1,1,1,1,1,1,1,1,1,1); break; case '@': mask = M (1,0,1,1,1,1,1,1,1,1,1,0); break; case '!': mask = M (0,0,1,0,0,1,1,1,1,1,1,0); break; case '&': mask = M (0,0,1,0,0,1,1,1,1,0,0,0); break; case '$': mask = M (1,0,1,1,1,1,1,1,1,0,0,0); break; case '?': mask = M (1,0,1,0,0,1,1,1,1,0,0,0); break; case '/': mask = M (1,0,1,0,0,1,1,1,1,1,1,0); break; case '|': mask = M (0,0,1,0,0,1,1,1,1,1,1,0); break; case '>': mask = M (0,0,1,0,1,1,1,1,1,0,0,0); break; case '<': mask = M (0,0,1,1,0,1,1,1,1,1,1,0); break; case 'm': mask = M (1,1,1,1,1,0,0,0,0,0,0,0); break; case 'n': mask = M (0,0,0,0,0,1,0,0,0,1,0,0); break; case 'o': mask = M (0,0,0,0,0,0,1,1,1,0,1,1); break; case 'p': mask = M (1,1,1,1,1,1,0,0,0,0,0,0); break; case 'q': mask = M (1,0,1,1,1,1,0,0,0,0,0,0); break; case 'v': mask = M (1,0,1,1,1,1,0,1,1,0,0,0); break; case 'b': mask = M (1,0,1,1,1,1,0,0,0,1,0,0); break; case 'w': mask = M (0,0,1,1,1,1,0,0,0,1,0,0); break; case 'y': mask = M (0,0,1,0,0,1,0,0,0,0,0,0); break; case 'z': mask = M (0,0,1,0,0,1,0,0,0,1,0,0); break; case '4': mask = M (0,0,1,1,1,1,0,0,0,0,0,0); break; default: abort (); } #undef M mode = (val >> 3) & 7; if (mode == 7) mode += val & 7; return (mask & (1 << mode)) != 0; } /* Print a base register REGNO and displacement DISP, on INFO->STREAM. REGNO = -1 for pc, -2 for none (suppressed). */ static void print_base (int regno, bfd_vma disp, disassemble_info *info) { if (regno == -1) { (*info->fprintf_func) (info->stream, "%%pc@("); (*info->print_address_func) (disp, info); } else { char buf[50]; if (regno == -2) (*info->fprintf_func) (info->stream, "@("); else if (regno == -3) (*info->fprintf_func) (info->stream, "%%zpc@("); else (*info->fprintf_func) (info->stream, "%s@(", reg_names[regno]); sprintf_vma (buf, disp); (*info->fprintf_func) (info->stream, "%s", buf); } } /* Print an indexed argument. The base register is BASEREG (-1 for pc). P points to extension word, in buffer. ADDR is the nominal core address of that extension word. */ static unsigned char * print_indexed (int basereg, unsigned char *p, bfd_vma addr, disassemble_info *info) { int word; static const char *const scales[] = { "", ":2", ":4", ":8" }; bfd_vma base_disp; bfd_vma outer_disp; char buf[40]; char vmabuf[50]; word = NEXTWORD (p); /* Generate the text for the index register. Where this will be output is not yet determined. */ sprintf (buf, "%s:%c%s", reg_names[(word >> 12) & 0xf], (word & 0x800) ? 'l' : 'w', scales[(word >> 9) & 3]); /* Handle the 68000 style of indexing. */ if ((word & 0x100) == 0) { base_disp = word & 0xff; if ((base_disp & 0x80) != 0) base_disp -= 0x100; if (basereg == -1) base_disp += addr; print_base (basereg, base_disp, info); (*info->fprintf_func) (info->stream, ",%s)", buf); return p; } /* Handle the generalized kind. */ /* First, compute the displacement to add to the base register. */ if (word & 0200) { if (basereg == -1) basereg = -3; else basereg = -2; } if (word & 0100) buf[0] = '\0'; base_disp = 0; switch ((word >> 4) & 3) { case 2: base_disp = NEXTWORD (p); break; case 3: base_disp = NEXTLONG (p); } if (basereg == -1) base_disp += addr; /* Handle single-level case (not indirect). */ if ((word & 7) == 0) { print_base (basereg, base_disp, info); if (buf[0] != '\0') (*info->fprintf_func) (info->stream, ",%s", buf); (*info->fprintf_func) (info->stream, ")"); return p; } /* Two level. Compute displacement to add after indirection. */ outer_disp = 0; switch (word & 3) { case 2: outer_disp = NEXTWORD (p); break; case 3: outer_disp = NEXTLONG (p); } print_base (basereg, base_disp, info); if ((word & 4) == 0 && buf[0] != '\0') { (*info->fprintf_func) (info->stream, ",%s", buf); buf[0] = '\0'; } sprintf_vma (vmabuf, outer_disp); (*info->fprintf_func) (info->stream, ")@(%s", vmabuf); if (buf[0] != '\0') (*info->fprintf_func) (info->stream, ",%s", buf); (*info->fprintf_func) (info->stream, ")"); return p; } /* Returns number of bytes "eaten" by the operand, or return -1 if an invalid operand was found, or -2 if an opcode tabe error was found. ADDR is the pc for this arg to be relative to. */ static int print_insn_arg (const char *d, unsigned char *buffer, unsigned char *p0, bfd_vma addr, disassemble_info *info) { int val = 0; int place = d[1]; unsigned char *p = p0; int regno; const char *regname; unsigned char *p1; double flval; int flt_p; bfd_signed_vma disp; unsigned int uval; switch (*d) { case 'c': /* Cache identifier. */ { static const char *const cacheFieldName[] = { "nc", "dc", "ic", "bc" }; val = fetch_arg (buffer, place, 2, info); (*info->fprintf_func) (info->stream, "%s", cacheFieldName[val]); break; } case 'a': /* Address register indirect only. Cf. case '+'. */ { (*info->fprintf_func) (info->stream, "%s@", reg_names[fetch_arg (buffer, place, 3, info) + 8]); break; } case '_': /* 32-bit absolute address for move16. */ { uval = NEXTULONG (p); (*info->print_address_func) (uval, info); break; } case 'C': (*info->fprintf_func) (info->stream, "%%ccr"); break; case 'S': (*info->fprintf_func) (info->stream, "%%sr"); break; case 'U': (*info->fprintf_func) (info->stream, "%%usp"); break; case 'E': (*info->fprintf_func) (info->stream, "%%acc"); break; case 'G': (*info->fprintf_func) (info->stream, "%%macsr"); break; case 'H': (*info->fprintf_func) (info->stream, "%%mask"); break; case 'J': { /* FIXME: There's a problem here, different m68k processors call the same address different names. This table can't get it right because it doesn't know which processor it's disassembling for. */ static const struct { const char *name; int value; } names[] = {{"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002}, {"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005}, {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008}, {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802}, {"%msp", 0x803}, {"%isp", 0x804}, {"%flashbar", 0xc04}, {"%rambar", 0xc05}, /* mcf528x added these. */ /* Should we be calling this psr like we do in case 'Y'? */ {"%mmusr",0x805}, {"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808}}; val = fetch_arg (buffer, place, 12, info); for (regno = sizeof names / sizeof names[0] - 1; regno >= 0; regno--) if (names[regno].value == val) { (*info->fprintf_func) (info->stream, "%s", names[regno].name); break; } if (regno < 0) (*info->fprintf_func) (info->stream, "%d", val); } break; case 'Q': val = fetch_arg (buffer, place, 3, info); /* 0 means 8, except for the bkpt instruction... */ if (val == 0 && d[1] != 's') val = 8; (*info->fprintf_func) (info->stream, "#%d", val); break; case 'x': val = fetch_arg (buffer, place, 3, info); /* 0 means -1. */ if (val == 0) val = -1; (*info->fprintf_func) (info->stream, "#%d", val); break; case 'M': if (place == 'h') { static const char *const scalefactor_name[] = { "<<", ">>" }; val = fetch_arg (buffer, place, 1, info); (*info->fprintf_func) (info->stream, "%s", scalefactor_name[val]); } else { val = fetch_arg (buffer, place, 8, info); if (val & 0x80) val = val - 0x100; (*info->fprintf_func) (info->stream, "#%d", val); } break; case 'T': val = fetch_arg (buffer, place, 4, info); (*info->fprintf_func) (info->stream, "#%d", val); break; case 'D': (*info->fprintf_func) (info->stream, "%s", reg_names[fetch_arg (buffer, place, 3, info)]); break; case 'A': (*info->fprintf_func) (info->stream, "%s", reg_names[fetch_arg (buffer, place, 3, info) + 010]); break; case 'R': (*info->fprintf_func) (info->stream, "%s", reg_names[fetch_arg (buffer, place, 4, info)]); break; case 'r': regno = fetch_arg (buffer, place, 4, info); if (regno > 7) (*info->fprintf_func) (info->stream, "%s@", reg_names[regno]); else (*info->fprintf_func) (info->stream, "@(%s)", reg_names[regno]); break; case 'F': (*info->fprintf_func) (info->stream, "%%fp%d", fetch_arg (buffer, place, 3, info)); break; case 'O': val = fetch_arg (buffer, place, 6, info); if (val & 0x20) (*info->fprintf_func) (info->stream, "%s", reg_names[val & 7]); else (*info->fprintf_func) (info->stream, "%d", val); break; case '+': (*info->fprintf_func) (info->stream, "%s@+", reg_names[fetch_arg (buffer, place, 3, info) + 8]); break; case '-': (*info->fprintf_func) (info->stream, "%s@-", reg_names[fetch_arg (buffer, place, 3, info) + 8]); break; case 'k': if (place == 'k') (*info->fprintf_func) (info->stream, "{%s}", reg_names[fetch_arg (buffer, place, 3, info)]); else if (place == 'C') { val = fetch_arg (buffer, place, 7, info); if (val > 63) /* This is a signed constant. */ val -= 128; (*info->fprintf_func) (info->stream, "{#%d}", val); } else return -2; break; case '#': case '^': p1 = buffer + (*d == '#' ? 2 : 4); if (place == 's') val = fetch_arg (buffer, place, 4, info); else if (place == 'C') val = fetch_arg (buffer, place, 7, info); else if (place == '8') val = fetch_arg (buffer, place, 3, info); else if (place == '3') val = fetch_arg (buffer, place, 8, info); else if (place == 'b') val = NEXTBYTE (p1); else if (place == 'w' || place == 'W') val = NEXTWORD (p1); else if (place == 'l') val = NEXTLONG (p1); else return -2; (*info->fprintf_func) (info->stream, "#%d", val); break; case 'B': if (place == 'b') disp = NEXTBYTE (p); else if (place == 'B') disp = COERCE_SIGNED_CHAR (buffer[1]); else if (place == 'w' || place == 'W') disp = NEXTWORD (p); else if (place == 'l' || place == 'L' || place == 'C') disp = NEXTLONG (p); else if (place == 'g') { disp = NEXTBYTE (buffer); if (disp == 0) disp = NEXTWORD (p); else if (disp == -1) disp = NEXTLONG (p); } else if (place == 'c') { if (buffer[1] & 0x40) /* If bit six is one, long offset. */ disp = NEXTLONG (p); else disp = NEXTWORD (p); } else return -2; (*info->print_address_func) (addr + disp, info); break; case 'd': val = NEXTWORD (p); (*info->fprintf_func) (info->stream, "%s@(%d)", reg_names[fetch_arg (buffer, place, 3, info) + 8], val); break; case 's': (*info->fprintf_func) (info->stream, "%s", fpcr_names[fetch_arg (buffer, place, 3, info)]); break; case 'e': val = fetch_arg(buffer, place, 2, info); (*info->fprintf_func) (info->stream, "%%acc%d", val); break; case 'g': val = fetch_arg(buffer, place, 1, info); (*info->fprintf_func) (info->stream, "%%accext%s", val==0 ? "01" : "23"); break; case 'i': val = fetch_arg(buffer, place, 2, info); if (val == 1) (*info->fprintf_func) (info->stream, "<<"); else if (val == 3) (*info->fprintf_func) (info->stream, ">>"); else return -1; break; case 'I': /* Get coprocessor ID... */ val = fetch_arg (buffer, 'd', 3, info); if (val != 1) /* Unusual coprocessor ID? */ (*info->fprintf_func) (info->stream, "(cpid=%d) ", val); break; case '4': case '*': case '~': case '%': case ';': case '@': case '!': case '$': case '?': case '/': case '&': case '|': case '<': case '>': case 'm': case 'n': case 'o': case 'p': case 'q': case 'v': case 'b': case 'w': case 'y': case 'z': if (place == 'd') { val = fetch_arg (buffer, 'x', 6, info); val = ((val & 7) << 3) + ((val >> 3) & 7); } else val = fetch_arg (buffer, 's', 6, info); /* If the <ea> is invalid for *d, then reject this match. */ if (!m68k_valid_ea (*d, val)) return -1; /* Get register number assuming address register. */ regno = (val & 7) + 8; regname = reg_names[regno]; switch (val >> 3) { case 0: (*info->fprintf_func) (info->stream, "%s", reg_names[val]); break; case 1: (*info->fprintf_func) (info->stream, "%s", regname); break; case 2: (*info->fprintf_func) (info->stream, "%s@", regname); break; case 3: (*info->fprintf_func) (info->stream, "%s@+", regname); break; case 4: (*info->fprintf_func) (info->stream, "%s@-", regname); break; case 5: val = NEXTWORD (p); (*info->fprintf_func) (info->stream, "%s@(%d)", regname, val); break; case 6: p = print_indexed (regno, p, addr, info); break; case 7: switch (val & 7) { case 0: val = NEXTWORD (p); (*info->print_address_func) (val, info); break; case 1: uval = NEXTULONG (p); (*info->print_address_func) (uval, info); break; case 2: val = NEXTWORD (p); (*info->fprintf_func) (info->stream, "%%pc@("); (*info->print_address_func) (addr + val, info); (*info->fprintf_func) (info->stream, ")"); break; case 3: p = print_indexed (-1, p, addr, info); break; case 4: flt_p = 1; /* Assume it's a float... */ switch (place) { case 'b': val = NEXTBYTE (p); flt_p = 0; break; case 'w': val = NEXTWORD (p); flt_p = 0; break; case 'l': val = NEXTLONG (p); flt_p = 0; break; case 'f': NEXTSINGLE (flval, p); break; case 'F': NEXTDOUBLE (flval, p); break; case 'x': NEXTEXTEND (flval, p); break; case 'p': flval = NEXTPACKED (p); break; default: return -1; } if (flt_p) /* Print a float? */ (*info->fprintf_func) (info->stream, "#%g", flval); else (*info->fprintf_func) (info->stream, "#%d", val); break; default: return -1; } } /* If place is '/', then this is the case of the mask bit for mac/emac loads. Now that the arg has been printed, grab the mask bit and if set, add a '&' to the arg. */ if (place == '/') { val = fetch_arg (buffer, place, 1, info); if (val) info->fprintf_func (info->stream, "&"); } break; case 'L': case 'l': if (place == 'w') { char doneany; p1 = buffer + 2; val = NEXTWORD (p1); /* Move the pointer ahead if this point is farther ahead than the last. */ p = p1 > p ? p1 : p; if (val == 0) { (*info->fprintf_func) (info->stream, "#0"); break; } if (*d == 'l') { int newval = 0; for (regno = 0; regno < 16; ++regno) if (val & (0x8000 >> regno)) newval |= 1 << regno; val = newval; } val &= 0xffff; doneany = 0; for (regno = 0; regno < 16; ++regno) if (val & (1 << regno)) { int first_regno; if (doneany) (*info->fprintf_func) (info->stream, "/"); doneany = 1; (*info->fprintf_func) (info->stream, "%s", reg_names[regno]); first_regno = regno; while (val & (1 << (regno + 1))) ++regno; if (regno > first_regno) (*info->fprintf_func) (info->stream, "-%s", reg_names[regno]); } } else if (place == '3') { /* `fmovem' insn. */ char doneany; val = fetch_arg (buffer, place, 8, info); if (val == 0) { (*info->fprintf_func) (info->stream, "#0"); break; } if (*d == 'l') { int newval = 0; for (regno = 0; regno < 8; ++regno) if (val & (0x80 >> regno)) newval |= 1 << regno; val = newval; } val &= 0xff; doneany = 0; for (regno = 0; regno < 8; ++regno) if (val & (1 << regno)) { int first_regno; if (doneany) (*info->fprintf_func) (info->stream, "/"); doneany = 1; (*info->fprintf_func) (info->stream, "%%fp%d", regno); first_regno = regno; while (val & (1 << (regno + 1))) ++regno; if (regno > first_regno) (*info->fprintf_func) (info->stream, "-%%fp%d", regno); } } else if (place == '8') { /* fmoveml for FP status registers. */ (*info->fprintf_func) (info->stream, "%s", fpcr_names[fetch_arg (buffer, place, 3, info)]); } else return -2; break; case 'X': place = '8'; case 'Y': case 'Z': case 'W': case '0': case '1': case '2': case '3': { int val = fetch_arg (buffer, place, 5, info); const char *name = 0; switch (val) { case 2: name = "%tt0"; break; case 3: name = "%tt1"; break; case 0x10: name = "%tc"; break; case 0x11: name = "%drp"; break; case 0x12: name = "%srp"; break; case 0x13: name = "%crp"; break; case 0x14: name = "%cal"; break; case 0x15: name = "%val"; break; case 0x16: name = "%scc"; break; case 0x17: name = "%ac"; break; case 0x18: name = "%psr"; break; case 0x19: name = "%pcsr"; break; case 0x1c: case 0x1d: { int break_reg = ((buffer[3] >> 2) & 7); (*info->fprintf_func) (info->stream, val == 0x1c ? "%%bad%d" : "%%bac%d", break_reg); } break; default: (*info->fprintf_func) (info->stream, "<mmu register %d>", val); } if (name) (*info->fprintf_func) (info->stream, "%s", name); } break; case 'f': { int fc = fetch_arg (buffer, place, 5, info); if (fc == 1) (*info->fprintf_func) (info->stream, "%%dfc"); else if (fc == 0) (*info->fprintf_func) (info->stream, "%%sfc"); else /* xgettext:c-format */ (*info->fprintf_func) (info->stream, _("<function code %d>"), fc); } break; case 'V': (*info->fprintf_func) (info->stream, "%%val"); break; case 't': { int level = fetch_arg (buffer, place, 3, info); (*info->fprintf_func) (info->stream, "%d", level); } break; case 'u': { short is_upper = 0; int reg = fetch_arg (buffer, place, 5, info); if (reg & 0x10) { is_upper = 1; reg &= 0xf; } (*info->fprintf_func) (info->stream, "%s%s", reg_half_names[reg], is_upper ? "u" : "l"); } break; default: return -2; } return p - p0; } /* Try to match the current instruction to best and if so, return the number of bytes consumed from the instruction stream, else zero. */ static int match_insn_m68k (bfd_vma memaddr, disassemble_info * info, const struct m68k_opcode * best, struct private * priv) { unsigned char *save_p; unsigned char *p; const char *d; bfd_byte *buffer = priv->the_buffer; fprintf_function save_printer = info->fprintf_func; void (* save_print_address) (bfd_vma, struct disassemble_info *) = info->print_address_func; /* Point at first word of argument data, and at descriptor for first argument. */ p = buffer + 2; /* Figure out how long the fixed-size portion of the instruction is. The only place this is stored in the opcode table is in the arguments--look for arguments which specify fields in the 2nd or 3rd words of the instruction. */ for (d = best->args; *d; d += 2) { /* I don't think it is necessary to be checking d[0] here; I suspect all this could be moved to the case statement below. */ if (d[0] == '#') { if (d[1] == 'l' && p - buffer < 6) p = buffer + 6; else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8') p = buffer + 4; } if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4) p = buffer + 4; switch (d[1]) { case '1': case '2': case '3': case '7': case '8': case '9': case 'i': if (p - buffer < 4) p = buffer + 4; break; case '4': case '5': case '6': if (p - buffer < 6) p = buffer + 6; break; default: break; } } /* pflusha is an exceptions. It takes no arguments but is two words long. Recognize it by looking at the lower 16 bits of the mask. */ if (p - buffer < 4 && (best->match & 0xFFFF) != 0) p = buffer + 4; /* lpstop is another exception. It takes a one word argument but is three words long. */ if (p - buffer < 6 && (best->match & 0xffff) == 0xffff && best->args[0] == '#' && best->args[1] == 'w') { /* Copy the one word argument into the usual location for a one word argument, to simplify printing it. We can get away with this because we know exactly what the second word is, and we aren't going to print anything based on it. */ p = buffer + 6; fetch_data(info, p); buffer[2] = buffer[4]; buffer[3] = buffer[5]; } fetch_data(info, p); d = best->args; save_p = p; info->print_address_func = dummy_print_address; info->fprintf_func = dummy_printer; /* We scan the operands twice. The first time we don't print anything, but look for errors. */ for (; *d; d += 2) { int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info); if (eaten >= 0) p += eaten; else if (eaten == -1) { info->fprintf_func = save_printer; info->print_address_func = save_print_address; return 0; } else { info->fprintf_func (info->stream, /* xgettext:c-format */ _("<internal error in opcode table: %s %s>\n"), best->name, best->args); info->fprintf_func = save_printer; info->print_address_func = save_print_address; return 2; } } p = save_p; info->fprintf_func = save_printer; info->print_address_func = save_print_address; d = best->args; info->fprintf_func (info->stream, "%s", best->name); if (*d) info->fprintf_func (info->stream, " "); while (*d) { p += print_insn_arg (d, buffer, p, memaddr + (p - buffer), info); d += 2; if (*d && *(d - 2) != 'I' && *d != 'k') info->fprintf_func (info->stream, ","); } return p - buffer; } /* Print the m68k instruction at address MEMADDR in debugged memory, on INFO->STREAM. Returns length of the instruction, in bytes. */ int print_insn_m68k (bfd_vma memaddr, disassemble_info *info) { int i; const char *d; unsigned int arch_mask; struct private priv; bfd_byte *buffer = priv.the_buffer; int major_opcode; static int numopcodes[16]; static const struct m68k_opcode **opcodes[16]; int val; if (!opcodes[0]) { /* Speed up the matching by sorting the opcode table on the upper four bits of the opcode. */ const struct m68k_opcode **opc_pointer[16]; /* First count how many opcodes are in each of the sixteen buckets. */ for (i = 0; i < m68k_numopcodes; i++) numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++; /* Then create a sorted table of pointers that point into the unsorted table. */ opc_pointer[0] = malloc (sizeof (struct m68k_opcode *) * m68k_numopcodes); opcodes[0] = opc_pointer[0]; for (i = 1; i < 16; i++) { opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1]; opcodes[i] = opc_pointer[i]; } for (i = 0; i < m68k_numopcodes; i++) *opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i]; } info->private_data = (PTR) &priv; /* Tell objdump to use two bytes per chunk and six bytes per line for displaying raw data. */ info->bytes_per_chunk = 2; info->bytes_per_line = 6; info->display_endian = BFD_ENDIAN_BIG; priv.max_fetched = priv.the_buffer; priv.insn_start = memaddr; if (setjmp (priv.bailout) != 0) /* Error return. */ return -1; switch (info->mach) { default: case 0: arch_mask = (unsigned int) -1; break; case bfd_mach_m68000: arch_mask = m68000|m68881|m68851; break; case bfd_mach_m68008: arch_mask = m68008|m68881|m68851; break; case bfd_mach_m68010: arch_mask = m68010|m68881|m68851; break; case bfd_mach_m68020: arch_mask = m68020|m68881|m68851; break; case bfd_mach_m68030: arch_mask = m68030|m68881|m68851; break; case bfd_mach_m68040: arch_mask = m68040|m68881|m68851; break; case bfd_mach_m68060: arch_mask = m68060|m68881|m68851; break; case bfd_mach_mcf5200: arch_mask = mcfisa_a; break; case bfd_mach_mcf521x: case bfd_mach_mcf528x: arch_mask = mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp|mcfemac; break; case bfd_mach_mcf5206e: arch_mask = mcfisa_a|mcfhwdiv|mcfmac; break; case bfd_mach_mcf5249: arch_mask = mcfisa_a|mcfhwdiv|mcfemac; break; case bfd_mach_mcf5307: arch_mask = mcfisa_a|mcfhwdiv|mcfmac; break; case bfd_mach_mcf5407: arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac; break; case bfd_mach_mcf547x: case bfd_mach_mcf548x: case bfd_mach_mcfv4e: arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp|cfloat|mcfemac; break; } fetch_data(info, buffer + 2); major_opcode = (buffer[0] >> 4) & 15; for (i = 0; i < numopcodes[major_opcode]; i++) { const struct m68k_opcode *opc = opcodes[major_opcode][i]; unsigned long opcode = opc->opcode; unsigned long match = opc->match; if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24))) && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16))) /* Only fetch the next two bytes if we need to. */ && (((0xffff & match) == 0) || (fetch_data(info, buffer + 4) && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8))) && ((0xff & buffer[3] & match) == (0xff & opcode))) ) && (opc->arch & arch_mask) != 0) { /* Don't use for printout the variants of divul and divsl that have the same register number in two places. The more general variants will match instead. */ for (d = opc->args; *d; d += 2) if (d[1] == 'D') break; /* Don't use for printout the variants of most floating point coprocessor instructions which use the same register number in two places, as above. */ if (*d == '\0') for (d = opc->args; *d; d += 2) if (d[1] == 't') break; /* Don't match fmovel with more than one register; wait for fmoveml. */ if (*d == '\0') { for (d = opc->args; *d; d += 2) { if (d[0] == 's' && d[1] == '8') { val = fetch_arg (buffer, d[1], 3, info); if ((val & (val - 1)) != 0) break; } } } if (*d == '\0') if ((val = match_insn_m68k (memaddr, info, opc, & priv))) return val; } } /* Handle undefined instructions. */ info->fprintf_func (info->stream, "0%o", (buffer[0] << 8) + buffer[1]); return 2; } /* **** End of m68k-dis.c */ /* **** m68k-opc.h from sourceware.org CVS 2005-08-14. */ /* Opcode table for m680[012346]0/m6888[12]/m68851/mcf5200. Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005 Free Software Foundation, Inc. This file is part of GDB, GAS, and the GNU binutils. GDB, GAS, and the GNU binutils are free software; you can redistribute them and/or modify them under the terms of the GNU General Public License as published by the Free Software Foundation; either version 1, or (at your option) any later version. GDB, GAS, and the GNU binutils are distributed in the hope that they will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this file; see the file COPYING. If not, see <http://www.gnu.org/licenses/>. */ #define one(x) ((unsigned int) (x) << 16) #define two(x, y) (((unsigned int) (x) << 16) + (y)) /* The assembler requires that all instances of the same mnemonic must be consecutive. If they aren't, the assembler will bomb at runtime. */ const struct m68k_opcode m68k_opcodes[] = { {"abcd", 2, one(0140400), one(0170770), "DsDd", m68000up }, {"abcd", 2, one(0140410), one(0170770), "-s-d", m68000up }, {"addaw", 2, one(0150300), one(0170700), "*wAd", m68000up }, {"addal", 2, one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a }, {"addib", 4, one(0003000), one(0177700), "#b$s", m68000up }, {"addiw", 4, one(0003100), one(0177700), "#w$s", m68000up }, {"addil", 6, one(0003200), one(0177700), "#l$s", m68000up }, {"addil", 6, one(0003200), one(0177700), "#lDs", mcfisa_a }, {"addqb", 2, one(0050000), one(0170700), "Qd$b", m68000up }, {"addqw", 2, one(0050100), one(0170700), "Qd%w", m68000up }, {"addql", 2, one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a }, /* The add opcode can generate the adda, addi, and addq instructions. */ {"addb", 2, one(0050000), one(0170700), "Qd$b", m68000up }, {"addb", 4, one(0003000), one(0177700), "#b$s", m68000up }, {"addb", 2, one(0150000), one(0170700), ";bDd", m68000up }, {"addb", 2, one(0150400), one(0170700), "Dd~b", m68000up }, {"addw", 2, one(0050100), one(0170700), "Qd%w", m68000up }, {"addw", 2, one(0150300), one(0170700), "*wAd", m68000up }, {"addw", 4, one(0003100), one(0177700), "#w$s", m68000up }, {"addw", 2, one(0150100), one(0170700), "*wDd", m68000up }, {"addw", 2, one(0150500), one(0170700), "Dd~w", m68000up }, {"addl", 2, one(0050200), one(0170700), "Qd%l", m68000up | mcfisa_a }, {"addl", 6, one(0003200), one(0177700), "#l$s", m68000up }, {"addl", 6, one(0003200), one(0177700), "#lDs", mcfisa_a }, {"addl", 2, one(0150700), one(0170700), "*lAd", m68000up | mcfisa_a }, {"addl", 2, one(0150200), one(0170700), "*lDd", m68000up | mcfisa_a }, {"addl", 2, one(0150600), one(0170700), "Dd~l", m68000up | mcfisa_a }, {"addxb", 2, one(0150400), one(0170770), "DsDd", m68000up }, {"addxb", 2, one(0150410), one(0170770), "-s-d", m68000up }, {"addxw", 2, one(0150500), one(0170770), "DsDd", m68000up }, {"addxw", 2, one(0150510), one(0170770), "-s-d", m68000up }, {"addxl", 2, one(0150600), one(0170770), "DsDd", m68000up | mcfisa_a }, {"addxl", 2, one(0150610), one(0170770), "-s-d", m68000up }, {"andib", 4, one(0001000), one(0177700), "#b$s", m68000up }, {"andib", 4, one(0001074), one(0177777), "#bCs", m68000up }, {"andiw", 4, one(0001100), one(0177700), "#w$s", m68000up }, {"andiw", 4, one(0001174), one(0177777), "#wSs", m68000up }, {"andil", 6, one(0001200), one(0177700), "#l$s", m68000up }, {"andil", 6, one(0001200), one(0177700), "#lDs", mcfisa_a }, {"andi", 4, one(0001100), one(0177700), "#w$s", m68000up }, {"andi", 4, one(0001074), one(0177777), "#bCs", m68000up }, {"andi", 4, one(0001174), one(0177777), "#wSs", m68000up }, /* The and opcode can generate the andi instruction. */ {"andb", 4, one(0001000), one(0177700), "#b$s", m68000up }, {"andb", 4, one(0001074), one(0177777), "#bCs", m68000up }, {"andb", 2, one(0140000), one(0170700), ";bDd", m68000up }, {"andb", 2, one(0140400), one(0170700), "Dd~b", m68000up }, {"andw", 4, one(0001100), one(0177700), "#w$s", m68000up }, {"andw", 4, one(0001174), one(0177777), "#wSs", m68000up }, {"andw", 2, one(0140100), one(0170700), ";wDd", m68000up }, {"andw", 2, one(0140500), one(0170700), "Dd~w", m68000up }, {"andl", 6, one(0001200), one(0177700), "#l$s", m68000up }, {"andl", 6, one(0001200), one(0177700), "#lDs", mcfisa_a }, {"andl", 2, one(0140200), one(0170700), ";lDd", m68000up | mcfisa_a }, {"andl", 2, one(0140600), one(0170700), "Dd~l", m68000up | mcfisa_a }, {"and", 4, one(0001100), one(0177700), "#w$w", m68000up }, {"and", 4, one(0001074), one(0177777), "#bCs", m68000up }, {"and", 4, one(0001174), one(0177777), "#wSs", m68000up }, {"and", 2, one(0140100), one(0170700), ";wDd", m68000up }, {"and", 2, one(0140500), one(0170700), "Dd~w", m68000up }, {"aslb", 2, one(0160400), one(0170770), "QdDs", m68000up }, {"aslb", 2, one(0160440), one(0170770), "DdDs", m68000up }, {"aslw", 2, one(0160500), one(0170770), "QdDs", m68000up }, {"aslw", 2, one(0160540), one(0170770), "DdDs", m68000up }, {"aslw", 2, one(0160700), one(0177700), "~s", m68000up }, {"asll", 2, one(0160600), one(0170770), "QdDs", m68000up | mcfisa_a }, {"asll", 2, one(0160640), one(0170770), "DdDs", m68000up | mcfisa_a }, {"asrb", 2, one(0160000), one(0170770), "QdDs", m68000up }, {"asrb", 2, one(0160040), one(0170770), "DdDs", m68000up }, {"asrw", 2, one(0160100), one(0170770), "QdDs", m68000up }, {"asrw", 2, one(0160140), one(0170770), "DdDs", m68000up }, {"asrw", 2, one(0160300), one(0177700), "~s", m68000up }, {"asrl", 2, one(0160200), one(0170770), "QdDs", m68000up | mcfisa_a }, {"asrl", 2, one(0160240), one(0170770), "DdDs", m68000up | mcfisa_a }, {"bhiw", 2, one(0061000), one(0177777), "BW", m68000up | mcfisa_a }, {"blsw", 2, one(0061400), one(0177777), "BW", m68000up | mcfisa_a }, {"bccw", 2, one(0062000), one(0177777), "BW", m68000up | mcfisa_a }, {"bcsw", 2, one(0062400), one(0177777), "BW", m68000up | mcfisa_a }, {"bnew", 2, one(0063000), one(0177777), "BW", m68000up | mcfisa_a }, {"beqw", 2, one(0063400), one(0177777), "BW", m68000up | mcfisa_a }, {"bvcw", 2, one(0064000), one(0177777), "BW", m68000up | mcfisa_a }, {"bvsw", 2, one(0064400), one(0177777), "BW", m68000up | mcfisa_a }, {"bplw", 2, one(0065000), one(0177777), "BW", m68000up | mcfisa_a }, {"bmiw", 2, one(0065400), one(0177777), "BW", m68000up | mcfisa_a }, {"bgew", 2, one(0066000), one(0177777), "BW", m68000up | mcfisa_a }, {"bltw", 2, one(0066400), one(0177777), "BW", m68000up | mcfisa_a }, {"bgtw", 2, one(0067000), one(0177777), "BW", m68000up | mcfisa_a }, {"blew", 2, one(0067400), one(0177777), "BW", m68000up | mcfisa_a }, {"bhil", 2, one(0061377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, {"blsl", 2, one(0061777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, {"bccl", 2, one(0062377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, {"bcsl", 2, one(0062777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, {"bnel", 2, one(0063377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, {"beql", 2, one(0063777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, {"bvcl", 2, one(0064377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, {"bvsl", 2, one(0064777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, {"bpll", 2, one(0065377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, {"bmil", 2, one(0065777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, {"bgel", 2, one(0066377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, {"bltl", 2, one(0066777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, {"bgtl", 2, one(0067377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, {"blel", 2, one(0067777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, {"bhis", 2, one(0061000), one(0177400), "BB", m68000up | mcfisa_a }, {"blss", 2, one(0061400), one(0177400), "BB", m68000up | mcfisa_a }, {"bccs", 2, one(0062000), one(0177400), "BB", m68000up | mcfisa_a }, {"bcss", 2, one(0062400), one(0177400), "BB", m68000up | mcfisa_a }, {"bnes", 2, one(0063000), one(0177400), "BB", m68000up | mcfisa_a }, {"beqs", 2, one(0063400), one(0177400), "BB", m68000up | mcfisa_a }, {"bvcs", 2, one(0064000), one(0177400), "BB", m68000up | mcfisa_a }, {"bvss", 2, one(0064400), one(0177400), "BB", m68000up | mcfisa_a }, {"bpls", 2, one(0065000), one(0177400), "BB", m68000up | mcfisa_a }, {"bmis", 2, one(0065400), one(0177400), "BB", m68000up | mcfisa_a }, {"bges", 2, one(0066000), one(0177400), "BB", m68000up | mcfisa_a }, {"blts", 2, one(0066400), one(0177400), "BB", m68000up | mcfisa_a }, {"bgts", 2, one(0067000), one(0177400), "BB", m68000up | mcfisa_a }, {"bles", 2, one(0067400), one(0177400), "BB", m68000up | mcfisa_a }, {"jhi", 2, one(0061000), one(0177400), "Bg", m68000up | mcfisa_a }, {"jls", 2, one(0061400), one(0177400), "Bg", m68000up | mcfisa_a }, {"jcc", 2, one(0062000), one(0177400), "Bg", m68000up | mcfisa_a }, {"jcs", 2, one(0062400), one(0177400), "Bg", m68000up | mcfisa_a }, {"jne", 2, one(0063000), one(0177400), "Bg", m68000up | mcfisa_a }, {"jeq", 2, one(0063400), one(0177400), "Bg", m68000up | mcfisa_a }, {"jvc", 2, one(0064000), one(0177400), "Bg", m68000up | mcfisa_a }, {"jvs", 2, one(0064400), one(0177400), "Bg", m68000up | mcfisa_a }, {"jpl", 2, one(0065000), one(0177400), "Bg", m68000up | mcfisa_a }, {"jmi", 2, one(0065400), one(0177400), "Bg", m68000up | mcfisa_a }, {"jge", 2, one(0066000), one(0177400), "Bg", m68000up | mcfisa_a }, {"jlt", 2, one(0066400), one(0177400), "Bg", m68000up | mcfisa_a }, {"jgt", 2, one(0067000), one(0177400), "Bg", m68000up | mcfisa_a }, {"jle", 2, one(0067400), one(0177400), "Bg", m68000up | mcfisa_a }, {"bchg", 2, one(0000500), one(0170700), "Dd$s", m68000up | mcfisa_a }, {"bchg", 4, one(0004100), one(0177700), "#b$s", m68000up }, {"bchg", 4, one(0004100), one(0177700), "#bqs", mcfisa_a }, {"bclr", 2, one(0000600), one(0170700), "Dd$s", m68000up | mcfisa_a }, {"bclr", 4, one(0004200), one(0177700), "#b$s", m68000up }, {"bclr", 4, one(0004200), one(0177700), "#bqs", mcfisa_a }, {"bfchg", 4, two(0165300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, {"bfclr", 4, two(0166300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, {"bfexts", 4, two(0165700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, {"bfextu", 4, two(0164700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, {"bfffo", 4, two(0166700, 0), two(0177700, 0100000), "/sO2O3D1", m68020up }, {"bfins", 4, two(0167700, 0), two(0177700, 0100000), "D1?sO2O3", m68020up }, {"bfset", 4, two(0167300, 0), two(0177700, 0170000), "?sO2O3", m68020up }, {"bftst", 4, two(0164300, 0), two(0177700, 0170000), "/sO2O3", m68020up }, {"bgnd", 2, one(0045372), one(0177777), "", cpu32 }, {"bitrev", 2, one(0000300), one(0177770), "Ds", mcfisa_aa}, {"bkpt", 2, one(0044110), one(0177770), "ts", m68010up }, {"braw", 2, one(0060000), one(0177777), "BW", m68000up | mcfisa_a }, {"bral", 2, one(0060377), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, {"bras", 2, one(0060000), one(0177400), "BB", m68000up | mcfisa_a }, {"bset", 2, one(0000700), one(0170700), "Dd$s", m68000up | mcfisa_a }, {"bset", 2, one(0000700), one(0170700), "Ddvs", mcfisa_a }, {"bset", 4, one(0004300), one(0177700), "#b$s", m68000up }, {"bset", 4, one(0004300), one(0177700), "#bqs", mcfisa_a }, {"bsrw", 2, one(0060400), one(0177777), "BW", m68000up | mcfisa_a }, {"bsrl", 2, one(0060777), one(0177777), "BL", m68020up | cpu32 | mcfisa_b}, {"bsrs", 2, one(0060400), one(0177400), "BB", m68000up | mcfisa_a }, {"btst", 2, one(0000400), one(0170700), "Dd;b", m68000up | mcfisa_a }, {"btst", 4, one(0004000), one(0177700), "#b@s", m68000up }, {"btst", 4, one(0004000), one(0177700), "#bqs", mcfisa_a }, {"byterev", 2, one(0001300), one(0177770), "Ds", mcfisa_aa}, {"callm", 4, one(0003300), one(0177700), "#b!s", m68020 }, {"cas2w", 6, two(0006374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up }, {"cas2w", 6, two(0006374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up }, {"cas2l", 6, two(0007374,0), two(0177777,0007070), "D3D6D2D5r1r4", m68020up }, {"cas2l", 6, two(0007374,0), two(0177777,0007070), "D3D6D2D5R1R4", m68020up }, {"casb", 4, two(0005300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, {"casw", 4, two(0006300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, {"casl", 4, two(0007300, 0), two(0177700, 0177070), "D3D2~s", m68020up }, {"chk2b", 4, two(0000300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 }, {"chk2w", 4, two(0001300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 }, {"chk2l", 4, two(0002300,0004000), two(0177700,07777), "!sR1", m68020up | cpu32 }, {"chkl", 2, one(0040400), one(0170700), ";lDd", m68000up }, {"chkw", 2, one(0040600), one(0170700), ";wDd", m68000up }, #define SCOPE_LINE (0x1 << 3) #define SCOPE_PAGE (0x2 << 3) #define SCOPE_ALL (0x3 << 3) {"cinva", 2, one(0xf400|SCOPE_ALL), one(0xff38), "ce", m68040up }, {"cinvl", 2, one(0xf400|SCOPE_LINE), one(0xff38), "ceas", m68040up }, {"cinvp", 2, one(0xf400|SCOPE_PAGE), one(0xff38), "ceas", m68040up }, {"cpusha", 2, one(0xf420|SCOPE_ALL), one(0xff38), "ce", m68040up }, {"cpushl", 2, one(0xf420|SCOPE_LINE), one(0xff38), "ceas", m68040up | mcfisa_a }, {"cpushp", 2, one(0xf420|SCOPE_PAGE), one(0xff38), "ceas", m68040up }, #undef SCOPE_LINE #undef SCOPE_PAGE #undef SCOPE_ALL {"clrb", 2, one(0041000), one(0177700), "$s", m68000up | mcfisa_a }, {"clrw", 2, one(0041100), one(0177700), "$s", m68000up | mcfisa_a }, {"clrl", 2, one(0041200), one(0177700), "$s", m68000up | mcfisa_a }, {"cmp2b", 4, two(0000300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, {"cmp2w", 4, two(0001300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, {"cmp2l", 4, two(0002300,0), two(0177700,07777), "!sR1", m68020up | cpu32 }, {"cmpaw", 2, one(0130300), one(0170700), "*wAd", m68000up }, {"cmpal", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a }, {"cmpib", 4, one(0006000), one(0177700), "#b@s", m68000up }, {"cmpib", 4, one(0006000), one(0177700), "#bDs", mcfisa_b }, {"cmpiw", 4, one(0006100), one(0177700), "#w@s", m68000up }, {"cmpiw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b }, {"cmpil", 6, one(0006200), one(0177700), "#l@s", m68000up }, {"cmpil", 6, one(0006200), one(0177700), "#lDs", mcfisa_a }, {"cmpmb", 2, one(0130410), one(0170770), "+s+d", m68000up }, {"cmpmw", 2, one(0130510), one(0170770), "+s+d", m68000up }, {"cmpml", 2, one(0130610), one(0170770), "+s+d", m68000up }, /* The cmp opcode can generate the cmpa, cmpm, and cmpi instructions. */ {"cmpb", 4, one(0006000), one(0177700), "#b@s", m68000up }, {"cmpb", 4, one(0006000), one(0177700), "#bDs", mcfisa_b }, {"cmpb", 2, one(0130410), one(0170770), "+s+d", m68000up }, {"cmpb", 2, one(0130000), one(0170700), ";bDd", m68000up }, {"cmpb", 2, one(0130000), one(0170700), "*bDd", mcfisa_b }, {"cmpw", 2, one(0130300), one(0170700), "*wAd", m68000up }, {"cmpw", 4, one(0006100), one(0177700), "#w@s", m68000up }, {"cmpw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b }, {"cmpw", 2, one(0130510), one(0170770), "+s+d", m68000up }, {"cmpw", 2, one(0130100), one(0170700), "*wDd", m68000up | mcfisa_b }, {"cmpl", 2, one(0130700), one(0170700), "*lAd", m68000up | mcfisa_a }, {"cmpl", 6, one(0006200), one(0177700), "#l@s", m68000up }, {"cmpl", 6, one(0006200), one(0177700), "#lDs", mcfisa_a }, {"cmpl", 2, one(0130610), one(0170770), "+s+d", m68000up }, {"cmpl", 2, one(0130200), one(0170700), "*lDd", m68000up | mcfisa_a }, {"dbcc", 2, one(0052310), one(0177770), "DsBw", m68000up }, {"dbcs", 2, one(0052710), one(0177770), "DsBw", m68000up }, {"dbeq", 2, one(0053710), one(0177770), "DsBw", m68000up }, {"dbf", 2, one(0050710), one(0177770), "DsBw", m68000up }, {"dbge", 2, one(0056310), one(0177770), "DsBw", m68000up }, {"dbgt", 2, one(0057310), one(0177770), "DsBw", m68000up }, {"dbhi", 2, one(0051310), one(0177770), "DsBw", m68000up }, {"dble", 2, one(0057710), one(0177770), "DsBw", m68000up }, {"dbls", 2, one(0051710), one(0177770), "DsBw", m68000up }, {"dblt", 2, one(0056710), one(0177770), "DsBw", m68000up }, {"dbmi", 2, one(0055710), one(0177770), "DsBw", m68000up }, {"dbne", 2, one(0053310), one(0177770), "DsBw", m68000up }, {"dbpl", 2, one(0055310), one(0177770), "DsBw", m68000up }, {"dbt", 2, one(0050310), one(0177770), "DsBw", m68000up }, {"dbvc", 2, one(0054310), one(0177770), "DsBw", m68000up }, {"dbvs", 2, one(0054710), one(0177770), "DsBw", m68000up }, {"divsw", 2, one(0100700), one(0170700), ";wDd", m68000up | mcfhwdiv }, {"divsl", 4, two(0046100,0006000),two(0177700,0107770),";lD3D1", m68020up|cpu32 }, {"divsl", 4, two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 }, {"divsl", 4, two(0046100,0004000),two(0177700,0107770),"qsDD", mcfhwdiv }, {"divsll", 4, two(0046100,0004000),two(0177700,0107770),";lD3D1",m68020up|cpu32 }, {"divsll", 4, two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 }, {"divuw", 2, one(0100300), one(0170700), ";wDd", m68000up | mcfhwdiv }, {"divul", 4, two(0046100,0002000),two(0177700,0107770),";lD3D1", m68020up|cpu32 }, {"divul", 4, two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 }, {"divul", 4, two(0046100,0000000),two(0177700,0107770),"qsDD", mcfhwdiv }, {"divull", 4, two(0046100,0000000),two(0177700,0107770),";lD3D1",m68020up|cpu32 }, {"divull", 4, two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 }, {"eorib", 4, one(0005000), one(0177700), "#b$s", m68000up }, {"eorib", 4, one(0005074), one(0177777), "#bCs", m68000up }, {"eoriw", 4, one(0005100), one(0177700), "#w$s", m68000up }, {"eoriw", 4, one(0005174), one(0177777), "#wSs", m68000up }, {"eoril", 6, one(0005200), one(0177700), "#l$s", m68000up }, {"eoril", 6, one(0005200), one(0177700), "#lDs", mcfisa_a }, {"eori", 4, one(0005074), one(0177777), "#bCs", m68000up }, {"eori", 4, one(0005174), one(0177777), "#wSs", m68000up }, {"eori", 4, one(0005100), one(0177700), "#w$s", m68000up }, /* The eor opcode can generate the eori instruction. */ {"eorb", 4, one(0005000), one(0177700), "#b$s", m68000up }, {"eorb", 4, one(0005074), one(0177777), "#bCs", m68000up }, {"eorb", 2, one(0130400), one(0170700), "Dd$s", m68000up }, {"eorw", 4, one(0005100), one(0177700), "#w$s", m68000up }, {"eorw", 4, one(0005174), one(0177777), "#wSs", m68000up }, {"eorw", 2, one(0130500), one(0170700), "Dd$s", m68000up }, {"eorl", 6, one(0005200), one(0177700), "#l$s", m68000up }, {"eorl", 6, one(0005200), one(0177700), "#lDs", mcfisa_a }, {"eorl", 2, one(0130600), one(0170700), "Dd$s", m68000up | mcfisa_a }, {"eor", 4, one(0005074), one(0177777), "#bCs", m68000up }, {"eor", 4, one(0005174), one(0177777), "#wSs", m68000up }, {"eor", 4, one(0005100), one(0177700), "#w$s", m68000up }, {"eor", 2, one(0130500), one(0170700), "Dd$s", m68000up }, {"exg", 2, one(0140500), one(0170770), "DdDs", m68000up }, {"exg", 2, one(0140510), one(0170770), "AdAs", m68000up }, {"exg", 2, one(0140610), one(0170770), "DdAs", m68000up }, {"exg", 2, one(0140610), one(0170770), "AsDd", m68000up }, {"extw", 2, one(0044200), one(0177770), "Ds", m68000up|mcfisa_a }, {"extl", 2, one(0044300), one(0177770), "Ds", m68000up|mcfisa_a }, {"extbl", 2, one(0044700), one(0177770), "Ds", m68020up|cpu32|mcfisa_a }, {"ff1", 2, one(0002300), one(0177770), "Ds", mcfisa_aa}, /* float stuff starts here */ {"fabsb", 4, two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"fabsb", 4, two(0xF000, 0x5818), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fabsd", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, {"fabsd", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", cfloat }, {"fabsd", 4, two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"fabsd", 4, two(0xF000, 0x5418), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, {"fabsl", 4, two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"fabsl", 4, two(0xF000, 0x4018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fabsp", 4, two(0xF000, 0x4C18), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"fabss", 4, two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", cfloat }, {"fabss", 4, two(0xF000, 0x4418), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"fabsw", 4, two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"fabsw", 4, two(0xF000, 0x5018), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fabsx", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"fabsx", 4, two(0xF000, 0x4818), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"fabsx", 4, two(0xF000, 0x0018), two(0xF1C0, 0xE07F), "IiFt", mfloat }, {"fsabsb", 4, two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, {"fsabsb", 4, two(0xF000, 0x5858), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fsabsd", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, {"fsabsd", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", cfloat }, {"fsabsd", 4, two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, {"fsabsd", 4, two(0xF000, 0x5458), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, {"fsabsl", 4, two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, {"fsabsl", 4, two(0xF000, 0x4058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fsabsp", 4, two(0xF000, 0x4C58), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, {"fsabss", 4, two(0xF000, 0x4258), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fsabss", 4, two(0xF000, 0x4458), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, {"fsabsw", 4, two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, {"fsabsw", 4, two(0xF000, 0x5058), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fsabsx", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, {"fsabsx", 4, two(0xF000, 0x4858), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, {"fsabsx", 4, two(0xF000, 0x0058), two(0xF1C0, 0xE07F), "IiFt", m68040up }, {"fdabsb", 4, two(0xF000, 0x585C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fdabsb", 4, two(0xF000, 0x585c), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up}, {"fdabsd", 4, two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, {"fdabsd", 4, two(0xF000, 0x005C), two(0xF1C0, 0xE07F), "IiFt", cfloat }, {"fdabsd", 4, two(0xF000, 0x545C), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, {"fdabsd", 4, two(0xF000, 0x545c), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up}, {"fdabsl", 4, two(0xF000, 0x405C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fdabsl", 4, two(0xF000, 0x405c), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up}, {"fdabsp", 4, two(0xF000, 0x4C5c), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up}, {"fdabss", 4, two(0xF000, 0x425C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fdabss", 4, two(0xF000, 0x445c), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up}, {"fdabsw", 4, two(0xF000, 0x505C), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fdabsw", 4, two(0xF000, 0x505c), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up}, {"fdabsx", 4, two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiF8F7", m68040up}, {"fdabsx", 4, two(0xF000, 0x485c), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up}, {"fdabsx", 4, two(0xF000, 0x005c), two(0xF1C0, 0xE07F), "IiFt", m68040up}, {"facosb", 4, two(0xF000, 0x581C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"facosd", 4, two(0xF000, 0x541C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"facosl", 4, two(0xF000, 0x401C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"facosp", 4, two(0xF000, 0x4C1C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"facoss", 4, two(0xF000, 0x441C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"facosw", 4, two(0xF000, 0x501C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"facosx", 4, two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"facosx", 4, two(0xF000, 0x481C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"facosx", 4, two(0xF000, 0x001C), two(0xF1C0, 0xE07F), "IiFt", mfloat }, {"faddb", 4, two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"faddb", 4, two(0xF000, 0x5822), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"faddd", 4, two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"faddd", 4, two(0xF000, 0x5422), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, {"faddl", 4, two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"faddl", 4, two(0xF000, 0x4022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"faddp", 4, two(0xF000, 0x4C22), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"fadds", 4, two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"fadds", 4, two(0xF000, 0x4422), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"faddw", 4, two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"faddw", 4, two(0xF000, 0x5022), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"faddx", 4, two(0xF000, 0x0022), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"faddx", 4, two(0xF000, 0x4822), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"fsaddb", 4, two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, {"fsaddb", 4, two(0xF000, 0x5862), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fsaddd", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, {"fsaddd", 4, two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, {"fsaddd", 4, two(0xF000, 0x5462), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, {"fsaddl", 4, two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, {"fsaddl", 4, two(0xF000, 0x4062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fsaddp", 4, two(0xF000, 0x4C62), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, {"fsadds", 4, two(0xF000, 0x4462), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, {"fsadds", 4, two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fsaddw", 4, two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, {"fsaddw", 4, two(0xF000, 0x5062), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fsaddx", 4, two(0xF000, 0x0062), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, {"fsaddx", 4, two(0xF000, 0x4862), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, {"fdaddb", 4, two(0xF000, 0x5826), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fdaddb", 4, two(0xF000, 0x5866), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, {"fdaddd", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, {"fdaddd", 4, two(0xF000, 0x5426), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fdaddd", 4, two(0xF000, 0x5466), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, {"fdaddl", 4, two(0xF000, 0x4026), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, {"fdaddl", 4, two(0xF000, 0x4066), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, {"fdaddp", 4, two(0xF000, 0x4C66), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, {"fdadds", 4, two(0xF000, 0x4466), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, {"fdadds", 4, two(0xF000, 0x4826), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fdaddw", 4, two(0xF000, 0x5026), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fdaddw", 4, two(0xF000, 0x5066), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, {"fdaddx", 4, two(0xF000, 0x0066), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, {"fdaddx", 4, two(0xF000, 0x4866), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, {"fasinb", 4, two(0xF000, 0x580C), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"fasind", 4, two(0xF000, 0x540C), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"fasinl", 4, two(0xF000, 0x400C), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"fasinp", 4, two(0xF000, 0x4C0C), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"fasins", 4, two(0xF000, 0x440C), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"fasinw", 4, two(0xF000, 0x500C), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"fasinx", 4, two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"fasinx", 4, two(0xF000, 0x480C), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"fasinx", 4, two(0xF000, 0x000C), two(0xF1C0, 0xE07F), "IiFt", mfloat }, {"fatanb", 4, two(0xF000, 0x580A), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"fatand", 4, two(0xF000, 0x540A), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"fatanl", 4, two(0xF000, 0x400A), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"fatanp", 4, two(0xF000, 0x4C0A), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"fatans", 4, two(0xF000, 0x440A), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"fatanw", 4, two(0xF000, 0x500A), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"fatanx", 4, two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"fatanx", 4, two(0xF000, 0x480A), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"fatanx", 4, two(0xF000, 0x000A), two(0xF1C0, 0xE07F), "IiFt", mfloat }, {"fatanhb", 4, two(0xF000, 0x580D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"fatanhd", 4, two(0xF000, 0x540D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"fatanhl", 4, two(0xF000, 0x400D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"fatanhp", 4, two(0xF000, 0x4C0D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"fatanhs", 4, two(0xF000, 0x440D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"fatanhw", 4, two(0xF000, 0x500D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"fatanhx", 4, two(0xF000, 0x480D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"fatanhx", 4, two(0xF000, 0x000D), two(0xF1C0, 0xE07F), "IiFt", mfloat }, {"fbeq", 2, one(0xF081), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbf", 2, one(0xF080), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbge", 2, one(0xF093), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbgl", 2, one(0xF096), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbgle", 2, one(0xF097), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbgt", 2, one(0xF092), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fble", 2, one(0xF095), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fblt", 2, one(0xF094), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbne", 2, one(0xF08E), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbnge", 2, one(0xF09C), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbngl", 2, one(0xF099), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbngle", 2, one(0xF098), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbngt", 2, one(0xF09D), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbnle", 2, one(0xF09A), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbnlt", 2, one(0xF09B), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fboge", 2, one(0xF083), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbogl", 2, one(0xF086), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbogt", 2, one(0xF082), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbole", 2, one(0xF085), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbolt", 2, one(0xF084), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbor", 2, one(0xF087), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbseq", 2, one(0xF091), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbsf", 2, one(0xF090), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbsne", 2, one(0xF09E), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbst", 2, one(0xF09F), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbt", 2, one(0xF08F), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbueq", 2, one(0xF089), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbuge", 2, one(0xF08B), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbugt", 2, one(0xF08A), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbule", 2, one(0xF08D), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbult", 2, one(0xF08C), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbun", 2, one(0xF088), one(0xF1FF), "IdBW", mfloat | cfloat }, {"fbeql", 2, one(0xF0C1), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbfl", 2, one(0xF0C0), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbgel", 2, one(0xF0D3), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbgll", 2, one(0xF0D6), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbglel", 2, one(0xF0D7), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbgtl", 2, one(0xF0D2), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fblel", 2, one(0xF0D5), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbltl", 2, one(0xF0D4), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbnel", 2, one(0xF0CE), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbngel", 2, one(0xF0DC), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbngll", 2, one(0xF0D9), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbnglel", 2, one(0xF0D8), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbngtl", 2, one(0xF0DD), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbnlel", 2, one(0xF0DA), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbnltl", 2, one(0xF0DB), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbogel", 2, one(0xF0C3), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbogll", 2, one(0xF0C6), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbogtl", 2, one(0xF0C2), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbolel", 2, one(0xF0C5), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fboltl", 2, one(0xF0C4), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fborl", 2, one(0xF0C7), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbseql", 2, one(0xF0D1), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbsfl", 2, one(0xF0D0), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbsnel", 2, one(0xF0DE), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbstl", 2, one(0xF0DF), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbtl", 2, one(0xF0CF), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbueql", 2, one(0xF0C9), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbugel", 2, one(0xF0CB), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbugtl", 2, one(0xF0CA), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbulel", 2, one(0xF0CD), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbultl", 2, one(0xF0CC), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fbunl", 2, one(0xF0C8), one(0xF1FF), "IdBC", mfloat | cfloat }, {"fjeq", 2, one(0xF081), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjf", 2, one(0xF080), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjge", 2, one(0xF093), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjgl", 2, one(0xF096), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjgle", 2, one(0xF097), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjgt", 2, one(0xF092), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjle", 2, one(0xF095), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjlt", 2, one(0xF094), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjne", 2, one(0xF08E), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjnge", 2, one(0xF09C), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjngl", 2, one(0xF099), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjngle", 2, one(0xF098), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjngt", 2, one(0xF09D), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjnle", 2, one(0xF09A), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjnlt", 2, one(0xF09B), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjoge", 2, one(0xF083), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjogl", 2, one(0xF086), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjogt", 2, one(0xF082), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjole", 2, one(0xF085), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjolt", 2, one(0xF084), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjor", 2, one(0xF087), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjseq", 2, one(0xF091), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjsf", 2, one(0xF090), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjsne", 2, one(0xF09E), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjst", 2, one(0xF09F), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjt", 2, one(0xF08F), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjueq", 2, one(0xF089), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjuge", 2, one(0xF08B), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjugt", 2, one(0xF08A), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjule", 2, one(0xF08D), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjult", 2, one(0xF08C), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fjun", 2, one(0xF088), one(0xF1BF), "IdBc", mfloat | cfloat }, {"fcmpb", 4, two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fcmpb", 4, two(0xF000, 0x5838), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"fcmpd", 4, two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"fcmpd", 4, two(0xF000, 0x5438), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, {"fcmpd", 4, two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, {"fcmpl", 4, two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"fcmpl", 4, two(0xF000, 0x4038), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fcmpp", 4, two(0xF000, 0x4C38), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"fcmps", 4, two(0xF000, 0x4438), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"fcmps", 4, two(0xF000, 0x4438), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fcmpw", 4, two(0xF000, 0x5038), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"fcmpw", 4, two(0xF000, 0x5038), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fcmpx", 4, two(0xF000, 0x0038), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"fcmpx", 4, two(0xF000, 0x4838), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"fcosb", 4, two(0xF000, 0x581D), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"fcosd", 4, two(0xF000, 0x541D), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"fcosl", 4, two(0xF000, 0x401D), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"fcosp", 4, two(0xF000, 0x4C1D), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"fcoss", 4, two(0xF000, 0x441D), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"fcosw", 4, two(0xF000, 0x501D), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"fcosx", 4, two(0xF000, 0x001D), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"fcosx", 4, two(0xF000, 0x481D), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"fcosx", 4, two(0xF000, 0x001D), two(0xF1C0, 0xE07F), "IiFt", mfloat }, {"fcoshb", 4, two(0xF000, 0x5819), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"fcoshd", 4, two(0xF000, 0x5419), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"fcoshl", 4, two(0xF000, 0x4019), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"fcoshp", 4, two(0xF000, 0x4C19), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"fcoshs", 4, two(0xF000, 0x4419), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"fcoshw", 4, two(0xF000, 0x5019), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"fcoshx", 4, two(0xF000, 0x0019), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"fcoshx", 4, two(0xF000, 0x4819), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"fcoshx", 4, two(0xF000, 0x0019), two(0xF1C0, 0xE07F), "IiFt", mfloat }, {"fdbeq", 4, two(0xF048, 0x0001), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbf", 4, two(0xF048, 0x0000), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbge", 4, two(0xF048, 0x0013), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbgl", 4, two(0xF048, 0x0016), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbgle", 4, two(0xF048, 0x0017), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbgt", 4, two(0xF048, 0x0012), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdble", 4, two(0xF048, 0x0015), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdblt", 4, two(0xF048, 0x0014), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbne", 4, two(0xF048, 0x000E), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbnge", 4, two(0xF048, 0x001C), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbngl", 4, two(0xF048, 0x0019), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbngle", 4, two(0xF048, 0x0018), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbngt", 4, two(0xF048, 0x001D), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbnle", 4, two(0xF048, 0x001A), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbnlt", 4, two(0xF048, 0x001B), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdboge", 4, two(0xF048, 0x0003), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbogl", 4, two(0xF048, 0x0006), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbogt", 4, two(0xF048, 0x0002), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbole", 4, two(0xF048, 0x0005), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbolt", 4, two(0xF048, 0x0004), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbor", 4, two(0xF048, 0x0007), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbseq", 4, two(0xF048, 0x0011), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbsf", 4, two(0xF048, 0x0010), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbsne", 4, two(0xF048, 0x001E), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbst", 4, two(0xF048, 0x001F), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbt", 4, two(0xF048, 0x000F), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbueq", 4, two(0xF048, 0x0009), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbuge", 4, two(0xF048, 0x000B), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbugt", 4, two(0xF048, 0x000A), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbule", 4, two(0xF048, 0x000D), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbult", 4, two(0xF048, 0x000C), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdbun", 4, two(0xF048, 0x0008), two(0xF1F8, 0xFFFF), "IiDsBw", mfloat }, {"fdivb", 4, two(0xF000, 0x5820), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"fdivb", 4, two(0xF000, 0x5820), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fdivd", 4, two(0xF000, 0x0020), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, {"fdivd", 4, two(0xF000, 0x5420), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"fdivd", 4, two(0xF000, 0x5420), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, {"fdivl", 4, two(0xF000, 0x4020), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"fdivl", 4, two(0xF000, 0x4020), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fdivp", 4, two(0xF000, 0x4C20), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"fdivs", 4, two(0xF000, 0x4420), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"fdivs", 4, two(0xF000, 0x4420), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fdivw", 4, two(0xF000, 0x5020), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"fdivw", 4, two(0xF000, 0x5020), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fdivx", 4, two(0xF000, 0x0020), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"fdivx", 4, two(0xF000, 0x4820), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"fsdivb", 4, two(0xF000, 0x5860), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, {"fsdivb", 4, two(0xF000, 0x5860), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fsdivd", 4, two(0xF000, 0x0060), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, {"fsdivd", 4, two(0xF000, 0x5460), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, {"fsdivd", 4, two(0xF000, 0x5460), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, {"fsdivl", 4, two(0xF000, 0x4060), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, {"fsdivl", 4, two(0xF000, 0x4060), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fsdivp", 4, two(0xF000, 0x4C60), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, {"fsdivs", 4, two(0xF000, 0x4460), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, {"fsdivs", 4, two(0xF000, 0x4460), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fsdivw", 4, two(0xF000, 0x5060), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, {"fsdivw", 4, two(0xF000, 0x5060), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fsdivx", 4, two(0xF000, 0x0060), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, {"fsdivx", 4, two(0xF000, 0x4860), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, {"fddivb", 4, two(0xF000, 0x5864), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, {"fddivb", 4, two(0xF000, 0x5864), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fddivd", 4, two(0xF000, 0x0064), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, {"fddivd", 4, two(0xF000, 0x5464), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, {"fddivd", 4, two(0xF000, 0x5464), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, {"fddivl", 4, two(0xF000, 0x4064), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, {"fddivl", 4, two(0xF000, 0x4064), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fddivp", 4, two(0xF000, 0x4C64), two(0xF1C0, 0xFC7F), "Ii;pF7", m68040up }, {"fddivs", 4, two(0xF000, 0x4464), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, {"fddivs", 4, two(0xF000, 0x4464), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fddivw", 4, two(0xF000, 0x5064), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, {"fddivw", 4, two(0xF000, 0x5064), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fddivx", 4, two(0xF000, 0x0064), two(0xF1C0, 0xE07F), "IiF8F7", m68040up }, {"fddivx", 4, two(0xF000, 0x4864), two(0xF1C0, 0xFC7F), "Ii;xF7", m68040up }, {"fetoxb", 4, two(0xF000, 0x5810), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"fetoxd", 4, two(0xF000, 0x5410), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"fetoxl", 4, two(0xF000, 0x4010), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"fetoxp", 4, two(0xF000, 0x4C10), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"fetoxs", 4, two(0xF000, 0x4410), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"fetoxw", 4, two(0xF000, 0x5010), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"fetoxx", 4, two(0xF000, 0x0010), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"fetoxx", 4, two(0xF000, 0x4810), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"fetoxx", 4, two(0xF000, 0x0010), two(0xF1C0, 0xE07F), "IiFt", mfloat }, {"fetoxm1b", 4, two(0xF000, 0x5808), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"fetoxm1d", 4, two(0xF000, 0x5408), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"fetoxm1l", 4, two(0xF000, 0x4008), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"fetoxm1p", 4, two(0xF000, 0x4C08), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"fetoxm1s", 4, two(0xF000, 0x4408), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"fetoxm1w", 4, two(0xF000, 0x5008), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"fetoxm1x", 4, two(0xF000, 0x0008), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"fetoxm1x", 4, two(0xF000, 0x4808), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"fetoxm1x", 4, two(0xF000, 0x0008), two(0xF1C0, 0xE07F), "IiFt", mfloat }, {"fgetexpb", 4, two(0xF000, 0x581E), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"fgetexpd", 4, two(0xF000, 0x541E), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"fgetexpl", 4, two(0xF000, 0x401E), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"fgetexpp", 4, two(0xF000, 0x4C1E), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"fgetexps", 4, two(0xF000, 0x441E), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"fgetexpw", 4, two(0xF000, 0x501E), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"fgetexpx", 4, two(0xF000, 0x001E), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"fgetexpx", 4, two(0xF000, 0x481E), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"fgetexpx", 4, two(0xF000, 0x001E), two(0xF1C0, 0xE07F), "IiFt", mfloat }, {"fgetmanb", 4, two(0xF000, 0x581F), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"fgetmand", 4, two(0xF000, 0x541F), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"fgetmanl", 4, two(0xF000, 0x401F), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"fgetmanp", 4, two(0xF000, 0x4C1F), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"fgetmans", 4, two(0xF000, 0x441F), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"fgetmanw", 4, two(0xF000, 0x501F), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"fgetmanx", 4, two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"fgetmanx", 4, two(0xF000, 0x481F), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"fgetmanx", 4, two(0xF000, 0x001F), two(0xF1C0, 0xE07F), "IiFt", mfloat }, {"fintb", 4, two(0xF000, 0x5801), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"fintb", 4, two(0xF000, 0x5801), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fintd", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, {"fintd", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiFt", cfloat }, {"fintd", 4, two(0xF000, 0x5401), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"fintd", 4, two(0xF000, 0x5401), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, {"fintl", 4, two(0xF000, 0x4001), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"fintl", 4, two(0xF000, 0x4001), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fintp", 4, two(0xF000, 0x4C01), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"fints", 4, two(0xF000, 0x4401), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"fints", 4, two(0xF000, 0x4401), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fintw", 4, two(0xF000, 0x5001), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"fintw", 4, two(0xF000, 0x5001), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fintx", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"fintx", 4, two(0xF000, 0x4801), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"fintx", 4, two(0xF000, 0x0001), two(0xF1C0, 0xE07F), "IiFt", mfloat }, {"fintrzb", 4, two(0xF000, 0x5803), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"fintrzb", 4, two(0xF000, 0x5803), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fintrzd", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, {"fintrzd", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiFt", cfloat }, {"fintrzd", 4, two(0xF000, 0x5403), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"fintrzd", 4, two(0xF000, 0x5403), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, {"fintrzl", 4, two(0xF000, 0x4003), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"fintrzl", 4, two(0xF000, 0x4003), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fintrzp", 4, two(0xF000, 0x4C03), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"fintrzs", 4, two(0xF000, 0x4403), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"fintrzs", 4, two(0xF000, 0x4403), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fintrzw", 4, two(0xF000, 0x5003), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"fintrzw", 4, two(0xF000, 0x5003), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fintrzx", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"fintrzx", 4, two(0xF000, 0x4803), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"fintrzx", 4, two(0xF000, 0x0003), two(0xF1C0, 0xE07F), "IiFt", mfloat }, {"flog10b", 4, two(0xF000, 0x5815), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"flog10d", 4, two(0xF000, 0x5415), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"flog10l", 4, two(0xF000, 0x4015), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"flog10p", 4, two(0xF000, 0x4C15), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"flog10s", 4, two(0xF000, 0x4415), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"flog10w", 4, two(0xF000, 0x5015), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"flog10x", 4, two(0xF000, 0x0015), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"flog10x", 4, two(0xF000, 0x4815), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"flog10x", 4, two(0xF000, 0x0015), two(0xF1C0, 0xE07F), "IiFt", mfloat }, {"flog2b", 4, two(0xF000, 0x5816), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"flog2d", 4, two(0xF000, 0x5416), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"flog2l", 4, two(0xF000, 0x4016), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"flog2p", 4, two(0xF000, 0x4C16), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"flog2s", 4, two(0xF000, 0x4416), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"flog2w", 4, two(0xF000, 0x5016), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"flog2x", 4, two(0xF000, 0x0016), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"flog2x", 4, two(0xF000, 0x4816), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"flog2x", 4, two(0xF000, 0x0016), two(0xF1C0, 0xE07F), "IiFt", mfloat }, {"flognb", 4, two(0xF000, 0x5814), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"flognd", 4, two(0xF000, 0x5414), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"flognl", 4, two(0xF000, 0x4014), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"flognp", 4, two(0xF000, 0x4C14), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"flogns", 4, two(0xF000, 0x4414), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"flognw", 4, two(0xF000, 0x5014), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"flognx", 4, two(0xF000, 0x0014), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"flognx", 4, two(0xF000, 0x4814), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"flognx", 4, two(0xF000, 0x0014), two(0xF1C0, 0xE07F), "IiFt", mfloat }, {"flognp1b", 4, two(0xF000, 0x5806), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"flognp1d", 4, two(0xF000, 0x5406), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"flognp1l", 4, two(0xF000, 0x4006), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"flognp1p", 4, two(0xF000, 0x4C06), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"flognp1s", 4, two(0xF000, 0x4406), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"flognp1w", 4, two(0xF000, 0x5006), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"flognp1x", 4, two(0xF000, 0x0006), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"flognp1x", 4, two(0xF000, 0x4806), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"flognp1x", 4, two(0xF000, 0x0006), two(0xF1C0, 0xE07F), "IiFt", mfloat }, {"fmodb", 4, two(0xF000, 0x5821), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"fmodd", 4, two(0xF000, 0x5421), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"fmodl", 4, two(0xF000, 0x4021), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"fmodp", 4, two(0xF000, 0x4C21), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"fmods", 4, two(0xF000, 0x4421), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"fmodw", 4, two(0xF000, 0x5021), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"fmodx", 4, two(0xF000, 0x0021), two(0xF1C0, 0xE07F), "IiF8F7", mfloat }, {"fmodx", 4, two(0xF000, 0x4821), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"fmoveb", 4, two(0xF000, 0x5800), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fmoveb", 4, two(0xF000, 0x7800), two(0xF1C0, 0xFC7F), "IiF7bs", cfloat }, {"fmoveb", 4, two(0xF000, 0x5800), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat }, {"fmoveb", 4, two(0xF000, 0x7800), two(0xF1C0, 0xFC7F), "IiF7$b", mfloat }, {"fmoved", 4, two(0xF000, 0x5400), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat }, {"fmoved", 4, two(0xF000, 0x7400), two(0xF1C0, 0xFC7F), "IiF7~F", mfloat }, {"fmoved", 4, two(0xF000, 0x0000), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, {"fmoved", 4, two(0xF000, 0x5400), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, {"fmoved", 4, two(0xF000, 0x7400), two(0xF1C0, 0xFC7F), "IiF7ws", cfloat }, {"fmovel", 4, two(0xF000, 0x4000), two(0xF1C0, 0xFC7F), "Ii;lF7", mfloat }, {"fmovel", 4, two(0xF000, 0x6000), two(0xF1C0, 0xFC7F), "IiF7$l", mfloat }, /* FIXME: the next two variants should not permit moving an address register to anything but the floating point instruction register. */ {"fmovel", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8%s", mfloat }, {"fmovel", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Ii*ls8", mfloat }, {"fmovel", 4, two(0xF000, 0x4000), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fmovel", 4, two(0xF000, 0x6000), two(0xF1C0, 0xFC7F), "IiF7bs", cfloat }, /* Move the FP control registers. */ {"fmovel", 4, two(0xF000, 0xA000), two(0xF1C0, 0xE3FF), "Iis8ps", cfloat }, {"fmovel", 4, two(0xF000, 0x8000), two(0xF1C0, 0xE3FF), "Iibss8", cfloat }, {"fmovep", 4, two(0xF000, 0x4C00), two(0xF1C0, 0xFC7F), "Ii;pF7", mfloat }, {"fmovep", 4, two(0xF000, 0x6C00), two(0xF1C0, 0xFC00), "IiF7~pkC", mfloat }, {"fmovep", 4, two(0xF000, 0x7C00), two(0xF1C0, 0xFC0F), "IiF7~pDk", mfloat }, {"fmoves", 4, two(0xF000, 0x4400), two(0xF1C0, 0xFC7F), "Ii;fF7", mfloat }, {"fmoves", 4, two(0xF000, 0x6400), two(0xF1C0, 0xFC7F), "IiF7$f", mfloat }, {"fmoves", 4, two(0xF000, 0x4400), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fmoves", 4, two(0xF000, 0x6400), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, {"fmovew", 4, two(0xF000, 0x5000), two(0xF1C0, 0xFC7F), "Ii;wF7", mfloat }, {"fmovew", 4, two(0xF000, 0x7000), two(0xF1C0, 0xFC7F), "IiF7$w", mfloat }, {"fmovew", 4, two(0xF000, 0x5000), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fmovew", 4, two(0xF000, 0x7000), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, {"fmovex", 4, two(0xF000, 0x0000), two(0xF1FF, 0xE07F), "IiF8F7", mfloat }, {"fmovex", 4, two(0xF000, 0x4800), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat }, {"fmovex", 4, two(0xF000, 0x6800), two(0xF1C0, 0xFC7F), "IiF7~x", mfloat }, {"fsmoveb", 4, two(0xF000, 0x5840), two(0xF1C0, 0xFC7F), "Ii;bF7", m68040up }, {"fsmoveb", 4, two(0xF000, 0x5840), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fsmoveb", 4, two(0xF000, 0x7840), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, {"fsmoved", 4, two(0xF000, 0x0040), two(0xF1C0, 0xE07F), "IiF8F7", cfloat }, {"fsmoved", 4, two(0xF000, 0x5440), two(0xF1C0, 0xFC7F), "Ii;FF7", m68040up }, {"fsmoved", 4, two(0xF000, 0x5440), two(0xF1C0, 0xFC7F), "IiwsF7", cfloat }, {"fsmoved", 4, two(0xF000, 0x7440), two(0xF1C0, 0xFC7F), "IiF7ws", cfloat }, {"fsmovel", 4, two(0xF000, 0x4040), two(0xF1C0, 0xFC7F), "Ii;lF7", m68040up }, {"fsmovel", 4, two(0xF000, 0x4040), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fsmovel", 4, two(0xF000, 0x6040), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, {"fsmoves", 4, two(0xF000, 0x4440), two(0xF1C0, 0xFC7F), "Ii;fF7", m68040up }, {"fsmoves", 4, two(0xF000, 0x4440), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fsmoves", 4, two(0xF000, 0x6440), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, {"fsmovew", 4, two(0xF000, 0x5040), two(0xF1C0, 0xFC7F), "Ii;wF7", m68040up }, {"fsmovew", 4, two(0xF000, 0x5040), two(0xF1C0, 0xFC7F), "IibsF7", cfloat }, {"fsmovew", 4, two(0xF000, 0x7040), two(0xF1C0, 0xFC7F), "IiF7qs", cfloat }, {"fsmovex", 4, two(0xF000, 0x0040), two(0xF1C0, 0xE07F), "IiF8F7", m68040up },


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