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-rw-r--r--clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c8
-rw-r--r--clang/test/CodeGen/SystemZ/builtins-systemz-zvector5.c2
-rw-r--r--clang/test/CodeGen/builtins-nvptx-native-half-type-native.c2
-rw-r--r--clang/test/CodeGen/builtins-nvptx-native-half-type.c2
4 files changed, 7 insertions, 7 deletions
diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
index d5d15b4d..35fde87 100644
--- a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
+++ b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
@@ -3584,13 +3584,13 @@ void test_integer(void) {
// CHECK-ASM: vsrlb
vsc = vec_abs(vsc);
- // CHECK-ASM: vlcb
+ // CHECK-ASM: vlpb
vss = vec_abs(vss);
- // CHECK-ASM: vlch
+ // CHECK-ASM: vlph
vsi = vec_abs(vsi);
- // CHECK-ASM: vlcf
+ // CHECK-ASM: vlpf
vsl = vec_abs(vsl);
- // CHECK-ASM: vlcg
+ // CHECK-ASM: vlpg
vsc = vec_max(vsc, vsc);
// CHECK-ASM: vmxb
diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector5.c b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector5.c
index 6ee9e1e..cd0fafd 100644
--- a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector5.c
+++ b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector5.c
@@ -246,7 +246,7 @@ void test_integer(void) {
// CHECK-ASM: vctzq
vslll = vec_abs(vslll);
- // CHECK-ASM: vlcq
+ // CHECK-ASM: vlpq
vslll = vec_avg(vslll, vslll);
// CHECK: call i128 @llvm.s390.vavgq(i128 %{{.*}}, i128 %{{.*}})
diff --git a/clang/test/CodeGen/builtins-nvptx-native-half-type-native.c b/clang/test/CodeGen/builtins-nvptx-native-half-type-native.c
index 035c4c6..60a35f4 100644
--- a/clang/test/CodeGen/builtins-nvptx-native-half-type-native.c
+++ b/clang/test/CodeGen/builtins-nvptx-native-half-type-native.c
@@ -8,7 +8,7 @@
typedef __fp16 __fp16v2 __attribute__((ext_vector_type(2)));
// CHECK: call half @llvm.nvvm.ex2.approx.f16(half {{.*}})
-// CHECK: call <2 x half> @llvm.nvvm.ex2.approx.f16x2(<2 x half> {{.*}})
+// CHECK: call <2 x half> @llvm.nvvm.ex2.approx.v2f16(<2 x half> {{.*}})
// CHECK: call half @llvm.nvvm.fma.rn.relu.f16(half {{.*}}, half {{.*}}, half {{.*}})
// CHECK: call half @llvm.nvvm.fma.rn.ftz.relu.f16(half {{.*}}, half {{.*}}, half {{.*}})
// CHECK: call <2 x half> @llvm.nvvm.fma.rn.relu.f16x2(<2 x half> {{.*}}, <2 x half> {{.*}}, <2 x half> {{.*}})
diff --git a/clang/test/CodeGen/builtins-nvptx-native-half-type.c b/clang/test/CodeGen/builtins-nvptx-native-half-type.c
index 01a004e..1f16c7e 100644
--- a/clang/test/CodeGen/builtins-nvptx-native-half-type.c
+++ b/clang/test/CodeGen/builtins-nvptx-native-half-type.c
@@ -41,7 +41,7 @@ __device__ void nvvm_ex2_sm75() {
#if __CUDA_ARCH__ >= 750
// CHECK_PTX70_SM75: call half @llvm.nvvm.ex2.approx.f16
__nvvm_ex2_approx_f16(0.1f16);
- // CHECK_PTX70_SM75: call <2 x half> @llvm.nvvm.ex2.approx.f16x2
+ // CHECK_PTX70_SM75: call <2 x half> @llvm.nvvm.ex2.approx.v2f16
__nvvm_ex2_approx_f16x2({0.1f16, 0.7f16});
#endif
// CHECK: ret void