diff options
Diffstat (limited to 'clang/test/CodeGen/scoped-fence-ops.c')
| -rw-r--r-- | clang/test/CodeGen/scoped-fence-ops.c | 41 |
1 files changed, 28 insertions, 13 deletions
diff --git a/clang/test/CodeGen/scoped-fence-ops.c b/clang/test/CodeGen/scoped-fence-ops.c index d83ae05..259e8d33 100644 --- a/clang/test/CodeGen/scoped-fence-ops.c +++ b/clang/test/CodeGen/scoped-fence-ops.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 // RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa -ffreestanding \ -// RUN: -fvisibility=hidden | FileCheck --check-prefix=AMDGCN %s +// RUN: -fvisibility=hidden | FileCheck --check-prefixes=AMDGCN,AMDGCN_CL_DEF %s // RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa -ffreestanding \ -// RUN: -cl-std=CL2.0 -fvisibility=hidden | FileCheck --check-prefix=AMDGCN %s +// RUN: -cl-std=CL2.0 -fvisibility=hidden | FileCheck --check-prefixes=AMDGCN,AMDGCN_CL_20 %s // RUN: %clang_cc1 %s -emit-llvm -o - -triple=spirv64-unknown-unknown -ffreestanding \ // RUN: -fvisibility=hidden | FileCheck --check-prefix=SPIRV %s // RUN: %clang_cc1 %s -emit-llvm -o - -triple=x86_64-unknown-linux-gnu -ffreestanding \ @@ -127,23 +127,27 @@ void fe1b(int ord) { // AMDGCN-NEXT: store i32 [[SCOPE]], ptr [[SCOPE_ADDR_ASCAST]], align 4 // AMDGCN-NEXT: [[TMP0:%.*]] = load i32, ptr [[SCOPE_ADDR_ASCAST]], align 4 // AMDGCN-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [ -// AMDGCN-NEXT: i32 1, label %[[DEVICE_SCOPE:.*]] // AMDGCN-NEXT: i32 0, label %[[SYSTEM_SCOPE:.*]] +// AMDGCN-NEXT: i32 1, label %[[DEVICE_SCOPE:.*]] // AMDGCN-NEXT: i32 2, label %[[WORKGROUP_SCOPE:.*]] +// AMDGCN-NEXT: i32 5, label %[[CLUSTER_SCOPE:.*]] // AMDGCN-NEXT: i32 3, label %[[WAVEFRONT_SCOPE:.*]] // AMDGCN-NEXT: i32 4, label %[[SINGLE_SCOPE:.*]] // AMDGCN-NEXT: ] // AMDGCN: [[ATOMIC_SCOPE_CONTINUE]]: // AMDGCN-NEXT: ret void -// AMDGCN: [[DEVICE_SCOPE]]: -// AMDGCN-NEXT: fence syncscope("agent") release -// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]] // AMDGCN: [[SYSTEM_SCOPE]]: // AMDGCN-NEXT: fence release // AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]] +// AMDGCN: [[DEVICE_SCOPE]]: +// AMDGCN-NEXT: fence syncscope("agent") release +// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]] // AMDGCN: [[WORKGROUP_SCOPE]]: // AMDGCN-NEXT: fence syncscope("workgroup") release // AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]] +// AMDGCN: [[CLUSTER_SCOPE]]: +// AMDGCN-NEXT: fence syncscope("cluster") release +// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]] // AMDGCN: [[WAVEFRONT_SCOPE]]: // AMDGCN-NEXT: fence syncscope("wavefront") release // AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]] @@ -158,23 +162,27 @@ void fe1b(int ord) { // SPIRV-NEXT: store i32 [[SCOPE]], ptr [[SCOPE_ADDR]], align 4 // SPIRV-NEXT: [[TMP0:%.*]] = load i32, ptr [[SCOPE_ADDR]], align 4 // SPIRV-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [ -// SPIRV-NEXT: i32 1, label %[[DEVICE_SCOPE:.*]] // SPIRV-NEXT: i32 0, label %[[SYSTEM_SCOPE:.*]] +// SPIRV-NEXT: i32 1, label %[[DEVICE_SCOPE:.*]] // SPIRV-NEXT: i32 2, label %[[WORKGROUP_SCOPE:.*]] +// SPIRV-NEXT: i32 5, label %[[CLUSTER_SCOPE:.*]] // SPIRV-NEXT: i32 3, label %[[WAVEFRONT_SCOPE:.*]] // SPIRV-NEXT: i32 4, label %[[SINGLE_SCOPE:.*]] // SPIRV-NEXT: ] // SPIRV: [[ATOMIC_SCOPE_CONTINUE]]: // SPIRV-NEXT: ret void -// SPIRV: [[DEVICE_SCOPE]]: -// SPIRV-NEXT: fence syncscope("device") release -// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]] // SPIRV: [[SYSTEM_SCOPE]]: // SPIRV-NEXT: fence release // SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]] +// SPIRV: [[DEVICE_SCOPE]]: +// SPIRV-NEXT: fence syncscope("device") release +// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]] // SPIRV: [[WORKGROUP_SCOPE]]: // SPIRV-NEXT: fence syncscope("workgroup") release // SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]] +// SPIRV: [[CLUSTER_SCOPE]]: +// SPIRV-NEXT: fence syncscope("workgroup") release +// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]] // SPIRV: [[WAVEFRONT_SCOPE]]: // SPIRV-NEXT: fence syncscope("subgroup") release // SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]] @@ -189,23 +197,27 @@ void fe1b(int ord) { // X86_64-NEXT: store i32 [[SCOPE]], ptr [[SCOPE_ADDR]], align 4 // X86_64-NEXT: [[TMP0:%.*]] = load i32, ptr [[SCOPE_ADDR]], align 4 // X86_64-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [ -// X86_64-NEXT: i32 1, label %[[DEVICE_SCOPE:.*]] // X86_64-NEXT: i32 0, label %[[SYSTEM_SCOPE:.*]] +// X86_64-NEXT: i32 1, label %[[DEVICE_SCOPE:.*]] // X86_64-NEXT: i32 2, label %[[WORKGROUP_SCOPE:.*]] +// X86_64-NEXT: i32 5, label %[[CLUSTER_SCOPE:.*]] // X86_64-NEXT: i32 3, label %[[WAVEFRONT_SCOPE:.*]] // X86_64-NEXT: i32 4, label %[[SINGLE_SCOPE:.*]] // X86_64-NEXT: ] // X86_64: [[ATOMIC_SCOPE_CONTINUE]]: // X86_64-NEXT: ret void -// X86_64: [[DEVICE_SCOPE]]: +// X86_64: [[SYSTEM_SCOPE]]: // X86_64-NEXT: fence release // X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]] -// X86_64: [[SYSTEM_SCOPE]]: +// X86_64: [[DEVICE_SCOPE]]: // X86_64-NEXT: fence release // X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]] // X86_64: [[WORKGROUP_SCOPE]]: // X86_64-NEXT: fence release // X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]] +// X86_64: [[CLUSTER_SCOPE]]: +// X86_64-NEXT: fence release +// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]] // X86_64: [[WAVEFRONT_SCOPE]]: // X86_64-NEXT: fence release // X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]] @@ -257,3 +269,6 @@ void fe2a() { void fe2b() { __scoped_atomic_thread_fence(__ATOMIC_RELEASE, 999); } +//// NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +// AMDGCN_CL_20: {{.*}} +// AMDGCN_CL_DEF: {{.*}} |