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-rw-r--r--clang/lib/AST/CommentSema.cpp2
-rw-r--r--clang/lib/Basic/Targets/AVR.cpp34
-rw-r--r--clang/lib/Basic/Targets/NVPTX.cpp2
-rw-r--r--clang/lib/Basic/Targets/PPC.h7
-rw-r--r--clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp2
-rw-r--r--clang/lib/CodeGen/BackendUtil.cpp2
-rw-r--r--clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp57
-rw-r--r--clang/lib/Driver/Driver.cpp12
-rw-r--r--clang/lib/Driver/ToolChains/Arch/M68k.cpp12
-rw-r--r--clang/lib/Driver/ToolChains/Arch/Mips.cpp4
-rw-r--r--clang/lib/Driver/ToolChains/Darwin.cpp12
-rw-r--r--clang/lib/Driver/ToolChains/Solaris.cpp2
-rw-r--r--clang/lib/Format/FormatTokenLexer.cpp13
-rw-r--r--clang/lib/Format/TokenAnnotator.cpp23
-rw-r--r--clang/lib/Frontend/CompilerInvocation.cpp24
-rw-r--r--clang/lib/Headers/hlsl/hlsl_compat_overloads.h2
-rw-r--r--clang/lib/Headers/hvx_hexagon_protos.h393
-rw-r--r--clang/lib/Tooling/DependencyScanning/DependencyScannerImpl.cpp2
18 files changed, 520 insertions, 85 deletions
diff --git a/clang/lib/AST/CommentSema.cpp b/clang/lib/AST/CommentSema.cpp
index 27ff5ab..d5ba240 100644
--- a/clang/lib/AST/CommentSema.cpp
+++ b/clang/lib/AST/CommentSema.cpp
@@ -225,7 +225,7 @@ static ParamCommandPassDirection getParamPassDirection(StringRef Arg) {
return llvm::StringSwitch<ParamCommandPassDirection>(Arg)
.Case("[in]", ParamCommandPassDirection::In)
.Case("[out]", ParamCommandPassDirection::Out)
- .Cases("[in,out]", "[out,in]", ParamCommandPassDirection::InOut)
+ .Cases({"[in,out]", "[out,in]"}, ParamCommandPassDirection::InOut)
.Default(static_cast<ParamCommandPassDirection>(-1));
}
diff --git a/clang/lib/Basic/Targets/AVR.cpp b/clang/lib/Basic/Targets/AVR.cpp
index 2673669..90b4ac1 100644
--- a/clang/lib/Basic/Targets/AVR.cpp
+++ b/clang/lib/Basic/Targets/AVR.cpp
@@ -30,13 +30,13 @@ struct LLVM_LIBRARY_VISIBILITY MCUInfo {
// NOTE: This list has been synchronized with gcc-avr 5.4.0 and avr-libc 2.0.0.
static MCUInfo AVRMcus[] = {
- {"avr1", NULL, "1", 0},
+ {"avr1", nullptr, "1", 0},
{"at90s1200", "__AVR_AT90S1200__", "1", 0},
{"attiny11", "__AVR_ATtiny11__", "1", 0},
{"attiny12", "__AVR_ATtiny12__", "1", 0},
{"attiny15", "__AVR_ATtiny15__", "1", 0},
{"attiny28", "__AVR_ATtiny28__", "1", 0},
- {"avr2", NULL, "2", 1},
+ {"avr2", nullptr, "2", 1},
{"at90s2313", "__AVR_AT90S2313__", "2", 1},
{"at90s2323", "__AVR_AT90S2323__", "2", 1},
{"at90s2333", "__AVR_AT90S2333__", "2", 1},
@@ -50,7 +50,7 @@ static MCUInfo AVRMcus[] = {
{"at90s8515", "__AVR_AT90S8515__", "2", 1},
{"at90c8534", "__AVR_AT90c8534__", "2", 1},
{"at90s8535", "__AVR_AT90S8535__", "2", 1},
- {"avr25", NULL, "25", 1},
+ {"avr25", nullptr, "25", 1},
{"ata5272", "__AVR_ATA5272__", "25", 1},
{"ata6616c", "__AVR_ATA6616c__", "25", 1},
{"attiny13", "__AVR_ATtiny13__", "25", 1},
@@ -80,13 +80,13 @@ static MCUInfo AVRMcus[] = {
{"attiny48", "__AVR_ATtiny48__", "25", 1},
{"attiny88", "__AVR_ATtiny88__", "25", 1},
{"attiny828", "__AVR_ATtiny828__", "25", 1},
- {"avr3", NULL, "3", 1},
+ {"avr3", nullptr, "3", 1},
{"at43usb355", "__AVR_AT43USB355__", "3", 1},
{"at76c711", "__AVR_AT76C711__", "3", 1},
- {"avr31", NULL, "31", 1},
+ {"avr31", nullptr, "31", 1},
{"atmega103", "__AVR_ATmega103__", "31", 1},
{"at43usb320", "__AVR_AT43USB320__", "31", 1},
- {"avr35", NULL, "35", 1},
+ {"avr35", nullptr, "35", 1},
{"attiny167", "__AVR_ATtiny167__", "35", 1},
{"at90usb82", "__AVR_AT90USB82__", "35", 1},
{"at90usb162", "__AVR_AT90USB162__", "35", 1},
@@ -97,7 +97,7 @@ static MCUInfo AVRMcus[] = {
{"atmega16u2", "__AVR_ATmega16U2__", "35", 1},
{"atmega32u2", "__AVR_ATmega32U2__", "35", 1},
{"attiny1634", "__AVR_ATtiny1634__", "35", 1},
- {"avr4", NULL, "4", 1},
+ {"avr4", nullptr, "4", 1},
{"atmega8", "__AVR_ATmega8__", "4", 1},
{"ata6289", "__AVR_ATA6289__", "4", 1},
{"atmega8a", "__AVR_ATmega8A__", "4", 1},
@@ -123,7 +123,7 @@ static MCUInfo AVRMcus[] = {
{"at90pwm3", "__AVR_AT90PWM3__", "4", 1},
{"at90pwm3b", "__AVR_AT90PWM3B__", "4", 1},
{"at90pwm81", "__AVR_AT90PWM81__", "4", 1},
- {"avr5", NULL, "5", 1},
+ {"avr5", nullptr, "5", 1},
{"ata5702m322", "__AVR_ATA5702M322__", "5", 1},
{"ata5782", "__AVR_ATA5782__", "5", 1},
{"ata5790", "__AVR_ATA5790__", "5", 1},
@@ -230,7 +230,7 @@ static MCUInfo AVRMcus[] = {
{"at90scr100", "__AVR_AT90SCR100__", "5", 1},
{"at94k", "__AVR_AT94K__", "5", 1},
{"m3000", "__AVR_AT000__", "5", 1},
- {"avr51", NULL, "51", 2},
+ {"avr51", nullptr, "51", 2},
{"atmega128", "__AVR_ATmega128__", "51", 2},
{"atmega128a", "__AVR_ATmega128A__", "51", 2},
{"atmega1280", "__AVR_ATmega1280__", "51", 2},
@@ -243,12 +243,12 @@ static MCUInfo AVRMcus[] = {
{"at90can128", "__AVR_AT90CAN128__", "51", 2},
{"at90usb1286", "__AVR_AT90USB1286__", "51", 2},
{"at90usb1287", "__AVR_AT90USB1287__", "51", 2},
- {"avr6", NULL, "6", 4},
+ {"avr6", nullptr, "6", 4},
{"atmega2560", "__AVR_ATmega2560__", "6", 4},
{"atmega2561", "__AVR_ATmega2561__", "6", 4},
{"atmega256rfr2", "__AVR_ATmega256RFR2__", "6", 4},
{"atmega2564rfr2", "__AVR_ATmega2564RFR2__", "6", 4},
- {"avrxmega2", NULL, "102", 1},
+ {"avrxmega2", nullptr, "102", 1},
{"atxmega16a4", "__AVR_ATxmega16A4__", "102", 1},
{"atxmega16a4u", "__AVR_ATxmega16A4U__", "102", 1},
{"atxmega16c4", "__AVR_ATxmega16C4__", "102", 1},
@@ -262,7 +262,7 @@ static MCUInfo AVRMcus[] = {
{"atxmega32e5", "__AVR_ATxmega32E5__", "102", 1},
{"atxmega16e5", "__AVR_ATxmega16E5__", "102", 1},
{"atxmega8e5", "__AVR_ATxmega8E5__", "102", 1},
- {"avrxmega4", NULL, "104", 1},
+ {"avrxmega4", nullptr, "104", 1},
{"atxmega64a3", "__AVR_ATxmega64A3__", "104", 1},
{"atxmega64a3u", "__AVR_ATxmega64A3U__", "104", 1},
{"atxmega64a4u", "__AVR_ATxmega64A4U__", "104", 1},
@@ -271,10 +271,10 @@ static MCUInfo AVRMcus[] = {
{"atxmega64c3", "__AVR_ATxmega64C3__", "104", 1},
{"atxmega64d3", "__AVR_ATxmega64D3__", "104", 1},
{"atxmega64d4", "__AVR_ATxmega64D4__", "104", 1},
- {"avrxmega5", NULL, "105", 1},
+ {"avrxmega5", nullptr, "105", 1},
{"atxmega64a1", "__AVR_ATxmega64A1__", "105", 1},
{"atxmega64a1u", "__AVR_ATxmega64A1U__", "105", 1},
- {"avrxmega6", NULL, "106", 6},
+ {"avrxmega6", nullptr, "106", 6},
{"atxmega128a3", "__AVR_ATxmega128A3__", "106", 2},
{"atxmega128a3u", "__AVR_ATxmega128A3U__", "106", 2},
{"atxmega128b1", "__AVR_ATxmega128B1__", "106", 2},
@@ -294,11 +294,11 @@ static MCUInfo AVRMcus[] = {
{"atxmega256d3", "__AVR_ATxmega256D3__", "106", 4},
{"atxmega384c3", "__AVR_ATxmega384C3__", "106", 6},
{"atxmega384d3", "__AVR_ATxmega384D3__", "106", 6},
- {"avrxmega7", NULL, "107", 2},
+ {"avrxmega7", nullptr, "107", 2},
{"atxmega128a1", "__AVR_ATxmega128A1__", "107", 2},
{"atxmega128a1u", "__AVR_ATxmega128A1U__", "107", 2},
{"atxmega128a4u", "__AVR_ATxmega128A4U__", "107", 2},
- {"avrtiny", NULL, "100", 0},
+ {"avrtiny", nullptr, "100", 0},
{"attiny4", "__AVR_ATtiny4__", "100", 0},
{"attiny5", "__AVR_ATtiny5__", "100", 0},
{"attiny9", "__AVR_ATtiny9__", "100", 0},
@@ -307,7 +307,7 @@ static MCUInfo AVRMcus[] = {
{"attiny40", "__AVR_ATtiny40__", "100", 0},
{"attiny102", "__AVR_ATtiny102__", "100", 0},
{"attiny104", "__AVR_ATtiny104__", "100", 0},
- {"avrxmega3", NULL, "103", 1},
+ {"avrxmega3", nullptr, "103", 1},
{"attiny202", "__AVR_ATtiny202__", "103", 1},
{"attiny402", "__AVR_ATtiny402__", "103", 1},
{"attiny204", "__AVR_ATtiny204__", "103", 1},
diff --git a/clang/lib/Basic/Targets/NVPTX.cpp b/clang/lib/Basic/Targets/NVPTX.cpp
index 9651c38..ec4e40b 100644
--- a/clang/lib/Basic/Targets/NVPTX.cpp
+++ b/clang/lib/Basic/Targets/NVPTX.cpp
@@ -171,7 +171,7 @@ ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
bool NVPTXTargetInfo::hasFeature(StringRef Feature) const {
return llvm::StringSwitch<bool>(Feature)
- .Cases("ptx", "nvptx", true)
+ .Cases({"ptx", "nvptx"}, true)
.Default(false);
}
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index d2eb9c5..d4ada2a 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -125,9 +125,8 @@ public:
.Cases({"power3", "pwr3"}, ArchDefinePpcgr)
.Cases({"power4", "pwr4"},
ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
- .Cases("power5", "pwr5",
- ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
- ArchDefinePpcsq)
+ .Cases({"power5", "pwr5"}, ArchDefinePwr5 | ArchDefinePwr4 |
+ ArchDefinePpcgr | ArchDefinePpcsq)
.Cases({"power5x", "pwr5x"},
ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
ArchDefinePpcgr | ArchDefinePpcsq)
@@ -166,7 +165,7 @@ public:
ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
- .Cases("8548", "e500", ArchDefineE500)
+ .Cases({"8548", "e500"}, ArchDefineE500)
.Default(ArchDefineNone);
}
return CPUKnown;
diff --git a/clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp b/clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
index 5010137..527dfd2 100644
--- a/clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenOpenACCClause.cpp
@@ -126,7 +126,7 @@ class OpenACCClauseCIREmitter final
.CaseLower("default", mlir::acc::DeviceType::Default)
.CaseLower("host", mlir::acc::DeviceType::Host)
.CaseLower("multicore", mlir::acc::DeviceType::Multicore)
- .CasesLower("nvidia", "acc_device_nvidia",
+ .CasesLower({"nvidia", "acc_device_nvidia"},
mlir::acc::DeviceType::Nvidia)
.CaseLower("radeon", mlir::acc::DeviceType::Radeon);
}
diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp
index 3c31314..b967a26 100644
--- a/clang/lib/CodeGen/BackendUtil.cpp
+++ b/clang/lib/CodeGen/BackendUtil.cpp
@@ -313,7 +313,7 @@ getCodeModel(const CodeGenOptions &CodeGenOpts) {
.Case("kernel", llvm::CodeModel::Kernel)
.Case("medium", llvm::CodeModel::Medium)
.Case("large", llvm::CodeModel::Large)
- .Cases("default", "", ~1u)
+ .Cases({"default", ""}, ~1u)
.Default(~0u);
assert(CodeModel != ~0u && "invalid code model!");
if (CodeModel == ~1u)
diff --git a/clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp b/clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
index 6da65b6..8a1cab3 100644
--- a/clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/NVPTX.cpp
@@ -375,28 +375,28 @@ static Value *MakeCpAsync(unsigned IntrinsicID, unsigned IntrinsicIDS,
CGF.EmitScalarExpr(E->getArg(1))});
}
-static Value *MakeHalfType(unsigned IntrinsicID, unsigned BuiltinID,
- const CallExpr *E, CodeGenFunction &CGF) {
+static bool EnsureNativeHalfSupport(unsigned BuiltinID, const CallExpr *E,
+ CodeGenFunction &CGF) {
auto &C = CGF.CGM.getContext();
- if (!(C.getLangOpts().NativeHalfType ||
- !C.getTargetInfo().useFP16ConversionIntrinsics())) {
+ if (!C.getLangOpts().NativeHalfType &&
+ C.getTargetInfo().useFP16ConversionIntrinsics()) {
CGF.CGM.Error(E->getExprLoc(), C.BuiltinInfo.getQuotedName(BuiltinID) +
" requires native half type support.");
- return nullptr;
+ return false;
}
+ return true;
+}
- if (BuiltinID == NVPTX::BI__nvvm_ldg_h || BuiltinID == NVPTX::BI__nvvm_ldg_h2)
- return MakeLdg(CGF, E);
-
- if (IntrinsicID == Intrinsic::nvvm_ldu_global_f)
- return MakeLdu(IntrinsicID, CGF, E);
+static Value *MakeHalfType(Function *Intrinsic, unsigned BuiltinID,
+ const CallExpr *E, CodeGenFunction &CGF) {
+ if (!EnsureNativeHalfSupport(BuiltinID, E, CGF))
+ return nullptr;
SmallVector<Value *, 16> Args;
- auto *F = CGF.CGM.getIntrinsic(IntrinsicID);
- auto *FTy = F->getFunctionType();
+ auto *FTy = Intrinsic->getFunctionType();
unsigned ICEArguments = 0;
ASTContext::GetBuiltinTypeError Error;
- C.GetBuiltinType(BuiltinID, Error, &ICEArguments);
+ CGF.CGM.getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments);
assert(Error == ASTContext::GE_None && "Should not codegen an error");
for (unsigned i = 0, e = E->getNumArgs(); i != e; ++i) {
assert((ICEArguments & (1 << i)) == 0);
@@ -407,8 +407,14 @@ static Value *MakeHalfType(unsigned IntrinsicID, unsigned BuiltinID,
Args.push_back(ArgValue);
}
- return CGF.Builder.CreateCall(F, Args);
+ return CGF.Builder.CreateCall(Intrinsic, Args);
}
+
+static Value *MakeHalfType(unsigned IntrinsicID, unsigned BuiltinID,
+ const CallExpr *E, CodeGenFunction &CGF) {
+ return MakeHalfType(CGF.CGM.getIntrinsic(IntrinsicID), BuiltinID, E, CGF);
+}
+
} // namespace
Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID,
@@ -913,9 +919,14 @@ Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID,
}
// The following builtins require half type support
case NVPTX::BI__nvvm_ex2_approx_f16:
- return MakeHalfType(Intrinsic::nvvm_ex2_approx_f16, BuiltinID, E, *this);
+ return MakeHalfType(
+ CGM.getIntrinsic(Intrinsic::nvvm_ex2_approx, Builder.getHalfTy()),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_ex2_approx_f16x2:
- return MakeHalfType(Intrinsic::nvvm_ex2_approx_f16x2, BuiltinID, E, *this);
+ return MakeHalfType(
+ CGM.getIntrinsic(Intrinsic::nvvm_ex2_approx,
+ FixedVectorType::get(Builder.getHalfTy(), 2)),
+ BuiltinID, E, *this);
case NVPTX::BI__nvvm_ff2f16x2_rn:
return MakeHalfType(Intrinsic::nvvm_ff2f16x2_rn, BuiltinID, E, *this);
case NVPTX::BI__nvvm_ff2f16x2_rn_relu:
@@ -1049,12 +1060,22 @@ Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID,
case NVPTX::BI__nvvm_fabs_d:
return Builder.CreateUnaryIntrinsic(Intrinsic::fabs,
EmitScalarExpr(E->getArg(0)));
+ case NVPTX::BI__nvvm_ex2_approx_d:
+ case NVPTX::BI__nvvm_ex2_approx_f:
+ return Builder.CreateUnaryIntrinsic(Intrinsic::nvvm_ex2_approx,
+ EmitScalarExpr(E->getArg(0)));
+ case NVPTX::BI__nvvm_ex2_approx_ftz_f:
+ return Builder.CreateUnaryIntrinsic(Intrinsic::nvvm_ex2_approx_ftz,
+ EmitScalarExpr(E->getArg(0)));
case NVPTX::BI__nvvm_ldg_h:
case NVPTX::BI__nvvm_ldg_h2:
- return MakeHalfType(Intrinsic::not_intrinsic, BuiltinID, E, *this);
+ return EnsureNativeHalfSupport(BuiltinID, E, *this) ? MakeLdg(*this, E)
+ : nullptr;
case NVPTX::BI__nvvm_ldu_h:
case NVPTX::BI__nvvm_ldu_h2:
- return MakeHalfType(Intrinsic::nvvm_ldu_global_f, BuiltinID, E, *this);
+ return EnsureNativeHalfSupport(BuiltinID, E, *this)
+ ? MakeLdu(Intrinsic::nvvm_ldu_global_f, *this, E)
+ : nullptr;
case NVPTX::BI__nvvm_cp_async_ca_shared_global_4:
return MakeCpAsync(Intrinsic::nvvm_cp_async_ca_shared_global_4,
Intrinsic::nvvm_cp_async_ca_shared_global_4_s, *this, E,
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 71c5280..51618d1 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -2540,10 +2540,14 @@ bool Driver::HandleImmediateArgs(Compilation &C) {
}
if (C.getArgs().hasArg(options::OPT_print_runtime_dir)) {
- if (std::optional<std::string> RuntimePath = TC.getRuntimePath())
- llvm::outs() << *RuntimePath << '\n';
- else
- llvm::outs() << TC.getCompilerRTPath() << '\n';
+ for (auto RuntimePath :
+ {TC.getRuntimePath(), std::make_optional(TC.getCompilerRTPath())}) {
+ if (RuntimePath && getVFS().exists(*RuntimePath)) {
+ llvm::outs() << *RuntimePath << '\n';
+ return false;
+ }
+ }
+ llvm::outs() << "(runtime dir is not present)" << '\n';
return false;
}
diff --git a/clang/lib/Driver/ToolChains/Arch/M68k.cpp b/clang/lib/Driver/ToolChains/Arch/M68k.cpp
index 1037c0e..708ec84 100644
--- a/clang/lib/Driver/ToolChains/Arch/M68k.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/M68k.cpp
@@ -36,12 +36,12 @@ std::string m68k::getM68kTargetCPU(const ArgList &Args) {
return "generic";
return llvm::StringSwitch<std::string>(CPUName)
- .Cases("m68000", "68000", "M68000")
- .Cases("m68010", "68010", "M68010")
- .Cases("m68020", "68020", "M68020")
- .Cases("m68030", "68030", "M68030")
- .Cases("m68040", "68040", "M68040")
- .Cases("m68060", "68060", "M68060")
+ .Cases({"m68000", "68000"}, "M68000")
+ .Cases({"m68010", "68010"}, "M68010")
+ .Cases({"m68020", "68020"}, "M68020")
+ .Cases({"m68030", "68030"}, "M68030")
+ .Cases({"m68040", "68040"}, "M68040")
+ .Cases({"m68060", "68060"}, "M68060")
.Default(CPUName.str());
}
// FIXME: Throw error when multiple sub-architecture flag exist
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index 6a6a4ee..8d7b85d 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -117,7 +117,7 @@ void mips::getMipsCPUAndABI(const ArgList &Args, const llvm::Triple &Triple,
// Deduce CPU name from ABI name.
CPUName = llvm::StringSwitch<const char *>(ABIName)
.Case("o32", DefMips32CPU)
- .Cases("n32", "n64", DefMips64CPU)
+ .Cases({"n32", "n64"}, DefMips64CPU)
.Default("");
}
@@ -467,7 +467,7 @@ bool mips::isNaN2008(const Driver &D, const ArgList &Args,
// NaN2008 is the default for MIPS32r6/MIPS64r6.
return llvm::StringSwitch<bool>(getCPUName(D, Args, Triple))
- .Cases("mips32r6", "mips64r6", true)
+ .Cases({"mips32r6", "mips64r6"}, true)
.Default(false);
}
diff --git a/clang/lib/Driver/ToolChains/Darwin.cpp b/clang/lib/Driver/ToolChains/Darwin.cpp
index cc5bcd1..2fb7652 100644
--- a/clang/lib/Driver/ToolChains/Darwin.cpp
+++ b/clang/lib/Driver/ToolChains/Darwin.cpp
@@ -1035,12 +1035,12 @@ static const char *ArmMachOArchName(StringRef Arch) {
.Case("xscale", "xscale")
.Case("armv4t", "armv4t")
.Case("armv7", "armv7")
- .Cases("armv7a", "armv7-a", "armv7")
- .Cases("armv7r", "armv7-r", "armv7")
- .Cases("armv7em", "armv7e-m", "armv7em")
- .Cases("armv7k", "armv7-k", "armv7k")
- .Cases("armv7m", "armv7-m", "armv7m")
- .Cases("armv7s", "armv7-s", "armv7s")
+ .Cases({"armv7a", "armv7-a"}, "armv7")
+ .Cases({"armv7r", "armv7-r"}, "armv7")
+ .Cases({"armv7em", "armv7e-m"}, "armv7em")
+ .Cases({"armv7k", "armv7-k"}, "armv7k")
+ .Cases({"armv7m", "armv7-m"}, "armv7m")
+ .Cases({"armv7s", "armv7-s"}, "armv7s")
.Default(nullptr);
}
diff --git a/clang/lib/Driver/ToolChains/Solaris.cpp b/clang/lib/Driver/ToolChains/Solaris.cpp
index 02aa598..64c7d1c 100644
--- a/clang/lib/Driver/ToolChains/Solaris.cpp
+++ b/clang/lib/Driver/ToolChains/Solaris.cpp
@@ -346,7 +346,7 @@ SanitizerMask Solaris::getSupportedSanitizers() const {
const char *Solaris::getDefaultLinker() const {
// FIXME: Only handle Solaris ld and GNU ld here.
return llvm::StringSwitch<const char *>(getDriver().getPreferredLinker())
- .Cases("bfd", "gld", "/usr/gnu/bin/ld")
+ .Cases({"bfd", "gld"}, "/usr/gnu/bin/ld")
.Default("/usr/bin/ld");
}
diff --git a/clang/lib/Format/FormatTokenLexer.cpp b/clang/lib/Format/FormatTokenLexer.cpp
index ab32938..a9ea5ec 100644
--- a/clang/lib/Format/FormatTokenLexer.cpp
+++ b/clang/lib/Format/FormatTokenLexer.cpp
@@ -318,14 +318,21 @@ void FormatTokenLexer::tryMergePreviousTokens() {
{tok::equal, tok::greater},
{tok::star, tok::greater},
{tok::pipeequal, tok::greater},
- {tok::pipe, tok::arrow},
- {tok::hash, tok::minus, tok::hash},
- {tok::hash, tok::equal, tok::hash}},
+ {tok::pipe, tok::arrow}},
TT_BinaryOperator) ||
Tokens.back()->is(tok::arrow)) {
Tokens.back()->ForcedPrecedence = prec::Comma;
return;
}
+ if (Tokens.size() >= 3 &&
+ Tokens[Tokens.size() - 3]->is(Keywords.kw_verilogHash) &&
+ Tokens[Tokens.size() - 2]->isOneOf(tok::minus, tok::equal) &&
+ Tokens[Tokens.size() - 1]->is(Keywords.kw_verilogHash) &&
+ tryMergeTokens(3, TT_BinaryOperator)) {
+ Tokens.back()->setFinalizedType(TT_BinaryOperator);
+ Tokens.back()->ForcedPrecedence = prec::Comma;
+ return;
+ }
} else if (Style.isTableGen()) {
// TableGen's Multi line string starts with [{
if (tryMergeTokens({tok::l_square, tok::l_brace},
diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp
index 8e227da..cb41756c 100644
--- a/clang/lib/Format/TokenAnnotator.cpp
+++ b/clang/lib/Format/TokenAnnotator.cpp
@@ -358,11 +358,11 @@ private:
Contexts.back().IsExpression = false;
} else if (OpeningParen.Previous &&
(OpeningParen.Previous->isOneOf(
- tok::kw_static_assert, tok::kw_noexcept, tok::kw_explicit,
- tok::kw_while, tok::l_paren, tok::comma, TT_CastRParen,
+ tok::kw_noexcept, tok::kw_explicit, tok::kw_while,
+ tok::l_paren, tok::comma, TT_CastRParen,
TT_BinaryOperator) ||
OpeningParen.Previous->isIf())) {
- // static_assert, if and while usually contain expressions.
+ // if and while usually contain expressions.
Contexts.back().IsExpression = true;
} else if (Style.isJavaScript() && OpeningParen.Previous &&
(OpeningParen.Previous->is(Keywords.kw_function) ||
@@ -454,6 +454,11 @@ private:
if (StartsObjCSelector)
OpeningParen.setType(TT_ObjCSelector);
+ const bool IsStaticAssert =
+ PrevNonComment && PrevNonComment->is(tok::kw_static_assert);
+ if (IsStaticAssert)
+ Contexts.back().InStaticAssertFirstArgument = true;
+
// MightBeFunctionType and ProbablyFunctionType are used for
// function pointer and reference types as well as Objective-C
// block types:
@@ -583,8 +588,12 @@ private:
}
// When we discover a 'new', we set CanBeExpression to 'false' in order to
// parse the type correctly. Reset that after a comma.
- if (CurrentToken->is(tok::comma))
- Contexts.back().CanBeExpression = true;
+ if (CurrentToken->is(tok::comma)) {
+ if (IsStaticAssert)
+ Contexts.back().InStaticAssertFirstArgument = false;
+ else
+ Contexts.back().CanBeExpression = true;
+ }
if (Style.isTableGen()) {
if (CurrentToken->is(tok::comma)) {
@@ -2144,6 +2153,7 @@ private:
bool CaretFound = false;
bool InCpp11AttributeSpecifier = false;
bool InCSharpAttributeSpecifier = false;
+ bool InStaticAssertFirstArgument = false;
bool VerilogAssignmentFound = false;
// Whether the braces may mean concatenation instead of structure or array
// literal.
@@ -2440,7 +2450,8 @@ private:
} else if (Current.isPointerOrReference()) {
Current.setType(determineStarAmpUsage(
Current,
- Contexts.back().CanBeExpression && Contexts.back().IsExpression,
+ (Contexts.back().CanBeExpression && Contexts.back().IsExpression) ||
+ Contexts.back().InStaticAssertFirstArgument,
Contexts.back().ContextType == Context::TemplateArgument));
} else if (Current.isOneOf(tok::minus, tok::plus, tok::caret) ||
(Style.isVerilog() && Current.is(tok::pipe))) {
diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp
index 1951e7f..be7c1d3 100644
--- a/clang/lib/Frontend/CompilerInvocation.cpp
+++ b/clang/lib/Frontend/CompilerInvocation.cpp
@@ -4049,18 +4049,18 @@ bool CompilerInvocation::ParseLangArgs(LangOptions &Opts, ArgList &Args,
// -cl-std only applies for OpenCL language standards.
// Override the -std option in this case.
if (const Arg *A = Args.getLastArg(OPT_cl_std_EQ)) {
- LangStandard::Kind OpenCLLangStd
- = llvm::StringSwitch<LangStandard::Kind>(A->getValue())
- .Cases("cl", "CL", LangStandard::lang_opencl10)
- .Cases("cl1.0", "CL1.0", LangStandard::lang_opencl10)
- .Cases("cl1.1", "CL1.1", LangStandard::lang_opencl11)
- .Cases("cl1.2", "CL1.2", LangStandard::lang_opencl12)
- .Cases("cl2.0", "CL2.0", LangStandard::lang_opencl20)
- .Cases("cl3.0", "CL3.0", LangStandard::lang_opencl30)
- .Cases("clc++", "CLC++", LangStandard::lang_openclcpp10)
- .Cases("clc++1.0", "CLC++1.0", LangStandard::lang_openclcpp10)
- .Cases("clc++2021", "CLC++2021", LangStandard::lang_openclcpp2021)
- .Default(LangStandard::lang_unspecified);
+ LangStandard::Kind OpenCLLangStd =
+ llvm::StringSwitch<LangStandard::Kind>(A->getValue())
+ .Cases({"cl", "CL"}, LangStandard::lang_opencl10)
+ .Cases({"cl1.0", "CL1.0"}, LangStandard::lang_opencl10)
+ .Cases({"cl1.1", "CL1.1"}, LangStandard::lang_opencl11)
+ .Cases({"cl1.2", "CL1.2"}, LangStandard::lang_opencl12)
+ .Cases({"cl2.0", "CL2.0"}, LangStandard::lang_opencl20)
+ .Cases({"cl3.0", "CL3.0"}, LangStandard::lang_opencl30)
+ .Cases({"clc++", "CLC++"}, LangStandard::lang_openclcpp10)
+ .Cases({"clc++1.0", "CLC++1.0"}, LangStandard::lang_openclcpp10)
+ .Cases({"clc++2021", "CLC++2021"}, LangStandard::lang_openclcpp2021)
+ .Default(LangStandard::lang_unspecified);
if (OpenCLLangStd == LangStandard::lang_unspecified) {
Diags.Report(diag::err_drv_invalid_value)
diff --git a/clang/lib/Headers/hlsl/hlsl_compat_overloads.h b/clang/lib/Headers/hlsl/hlsl_compat_overloads.h
index fe4277e..ee243ab 100644
--- a/clang/lib/Headers/hlsl/hlsl_compat_overloads.h
+++ b/clang/lib/Headers/hlsl/hlsl_compat_overloads.h
@@ -7,7 +7,7 @@
//===----------------------------------------------------------------------===//
#ifndef _HLSL_COMPAT_OVERLOADS_H_
-#define _HLSl_COMPAT_OVERLOADS_H_
+#define _HLSL_COMPAT_OVERLOADS_H_
namespace hlsl {
diff --git a/clang/lib/Headers/hvx_hexagon_protos.h b/clang/lib/Headers/hvx_hexagon_protos.h
index fd120a5..19309a4 100644
--- a/clang/lib/Headers/hvx_hexagon_protos.h
+++ b/clang/lib/Headers/hvx_hexagon_protos.h
@@ -5605,6 +5605,399 @@
__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_f8)(Vu, Vv)
#endif /* __HEXAGON_ARCH___ >= 79 */
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.qf16=vabs(Vu32.hf)
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vabs_Vhf(HVX_Vector Vu)
+ Instruction Type: CVI_VS
+ Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Vqf16_vabs_Vhf(Vu) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_hf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.qf16=vabs(Vu32.qf16)
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vabs_Vqf16(HVX_Vector Vu)
+ Instruction Type: CVI_VS
+ Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Vqf16_vabs_Vqf16(Vu) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf16_qf16)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.qf32=vabs(Vu32.qf32)
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vabs_Vqf32(HVX_Vector Vu)
+ Instruction Type: CVI_VS
+ Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Vqf32_vabs_Vqf32(Vu) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_qf32)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.qf32=vabs(Vu32.sf)
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vabs_Vsf(HVX_Vector Vu)
+ Instruction Type: CVI_VS
+ Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Vqf32_vabs_Vsf(Vu) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_qf32_sf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32=valign4(Vu32,Vv32,Rt8)
+ C Intrinsic Prototype: HVX_Vector Q6_V_valign4_VVR(HVX_Vector Vu, HVX_Vector
+ Vv, Word32 Rt) Instruction Type: CVI_VA Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_V_valign4_VVR(Vu, Vv, Rt) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valign4)(Vu, Vv, Rt)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.bf=Vuu32.qf32
+ C Intrinsic Prototype: HVX_Vector Q6_Vbf_equals_Wqf32(HVX_VectorPair Vuu)
+ Instruction Type: CVI_VS
+ Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Vbf_equals_Wqf32(Vuu) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_bf_qf32)(Vuu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.f8=Vu32.qf16
+ C Intrinsic Prototype: HVX_Vector Q6_V_equals_Vqf16(HVX_Vector Vu)
+ Instruction Type: CVI_VS
+ Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_V_equals_Vqf16(Vu) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_f8_qf16)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.h=Vu32.hf:rnd
+ C Intrinsic Prototype: HVX_Vector Q6_Vh_equals_Vhf_rnd(HVX_Vector Vu)
+ Instruction Type: CVI_VS
+ Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Vh_equals_Vhf_rnd(Vu) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_h_hf_rnd)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vdd32.qf16=Vu32.f8
+ C Intrinsic Prototype: HVX_VectorPair Q6_Wqf16_equals_V(HVX_Vector Vu)
+ Instruction Type: CVI_VP_VS
+ Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Wqf16_equals_V(Vu) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_f8)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.qf16=Vu32.hf
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf16_equals_Vhf(HVX_Vector Vu)
+ Instruction Type: CVI_VS
+ Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Vqf16_equals_Vhf(Vu) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_hf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.qf16=Vu32.qf16
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf16_equals_Vqf16(HVX_Vector Vu)
+ Instruction Type: CVI_VS
+ Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Vqf16_equals_Vqf16(Vu) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf16_qf16)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.qf32=Vu32.qf32
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf32_equals_Vqf32(HVX_Vector Vu)
+ Instruction Type: CVI_VS
+ Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Vqf32_equals_Vqf32(Vu) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_qf32)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.qf32=Vu32.sf
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf32_equals_Vsf(HVX_Vector Vu)
+ Instruction Type: CVI_VS
+ Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Vqf32_equals_Vsf(Vu) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_qf32_sf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Qd4=vcmp.eq(Vu32.hf,Vv32.hf)
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhfVhf(HVX_Vector Vu,
+ HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Q_vcmp_eq_VhfVhf(Vu, Vv) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \
+ (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf)(Vu, Vv)), -1)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Qx4&=vcmp.eq(Vu32.hf,Vv32.hf)
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhfVhf(HVX_VectorPred
+ Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
+ Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Q_vcmp_eqand_QVhfVhf(Qx, Vu, Vv) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \
+ (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_and)( \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \
+ Vv)), \
+ -1)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Qx4|=vcmp.eq(Vu32.hf,Vv32.hf)
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhfVhf(HVX_VectorPred
+ Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
+ Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Q_vcmp_eqor_QVhfVhf(Qx, Vu, Vv) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \
+ (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_or)( \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \
+ Vv)), \
+ -1)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Qx4^=vcmp.eq(Vu32.hf,Vv32.hf)
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhfVhf(HVX_VectorPred
+ Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
+ Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Q_vcmp_eqxacc_QVhfVhf(Qx, Vu, Vv) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \
+ (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqhf_xor)( \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \
+ Vv)), \
+ -1)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Qd4=vcmp.eq(Vu32.sf,Vv32.sf)
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VsfVsf(HVX_Vector Vu,
+ HVX_Vector Vv) Instruction Type: CVI_VA Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Q_vcmp_eq_VsfVsf(Vu, Vv) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \
+ (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf)(Vu, Vv)), -1)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Qx4&=vcmp.eq(Vu32.sf,Vv32.sf)
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVsfVsf(HVX_VectorPred
+ Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
+ Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Q_vcmp_eqand_QVsfVsf(Qx, Vu, Vv) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \
+ (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_and)( \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \
+ Vv)), \
+ -1)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Qx4|=vcmp.eq(Vu32.sf,Vv32.sf)
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVsfVsf(HVX_VectorPred
+ Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
+ Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Q_vcmp_eqor_QVsfVsf(Qx, Vu, Vv) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \
+ (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_or)( \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \
+ Vv)), \
+ -1)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Qx4^=vcmp.eq(Vu32.sf,Vv32.sf)
+ C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVsfVsf(HVX_VectorPred
+ Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type: CVI_VA Execution
+ Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Q_vcmp_eqxacc_QVsfVsf(Qx, Vu, Vv) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)( \
+ (__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqsf_xor)( \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx), -1), Vu, \
+ Vv)), \
+ -1)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.w=vilog2(Vu32.hf)
+ C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vhf(HVX_Vector Vu)
+ Instruction Type: CVI_VS
+ Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Vw_vilog2_Vhf(Vu) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_hf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.w=vilog2(Vu32.qf16)
+ C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vqf16(HVX_Vector Vu)
+ Instruction Type: CVI_VS
+ Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Vw_vilog2_Vqf16(Vu) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf16)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.w=vilog2(Vu32.qf32)
+ C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vqf32(HVX_Vector Vu)
+ Instruction Type: CVI_VS
+ Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Vw_vilog2_Vqf32(Vu) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_qf32)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.w=vilog2(Vu32.sf)
+ C Intrinsic Prototype: HVX_Vector Q6_Vw_vilog2_Vsf(HVX_Vector Vu)
+ Instruction Type: CVI_VS
+ Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Vw_vilog2_Vsf(Vu) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vilog2_sf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.qf16=vneg(Vu32.hf)
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vneg_Vhf(HVX_Vector Vu)
+ Instruction Type: CVI_VS
+ Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Vqf16_vneg_Vhf(Vu) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_hf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.qf16=vneg(Vu32.qf16)
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vneg_Vqf16(HVX_Vector Vu)
+ Instruction Type: CVI_VS
+ Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Vqf16_vneg_Vqf16(Vu) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf16_qf16)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.qf32=vneg(Vu32.qf32)
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vneg_Vqf32(HVX_Vector Vu)
+ Instruction Type: CVI_VS
+ Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Vqf32_vneg_Vqf32(Vu) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_qf32)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.qf32=vneg(Vu32.sf)
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vneg_Vsf(HVX_Vector Vu)
+ Instruction Type: CVI_VS
+ Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Vqf32_vneg_Vsf(Vu) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vneg_qf32_sf)(Vu)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.qf16=vsub(Vu32.hf,Vv32.qf16)
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVqf16(HVX_Vector Vu,
+ HVX_Vector Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Vqf16_vsub_VhfVqf16(Vu, Vv) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_mix)(Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
+#if __HVX_ARCH__ >= 81
+/* ==========================================================================
+ Assembly Syntax: Vd32.qf32=vsub(Vu32.sf,Vv32.qf32)
+ C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVqf32(HVX_Vector Vu,
+ HVX_Vector Vv) Instruction Type: CVI_VS Execution Slots: SLOT0123
+ ========================================================================== */
+
+#define Q6_Vqf32_vsub_VsfVqf32(Vu, Vv) \
+ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_mix)(Vu, Vv)
+#endif /* __HEXAGON_ARCH___ >= 81 */
+
#endif /* __HVX__ */
#endif
diff --git a/clang/lib/Tooling/DependencyScanning/DependencyScannerImpl.cpp b/clang/lib/Tooling/DependencyScanning/DependencyScannerImpl.cpp
index 42f52d0..eebecdb 100644
--- a/clang/lib/Tooling/DependencyScanning/DependencyScannerImpl.cpp
+++ b/clang/lib/Tooling/DependencyScanning/DependencyScannerImpl.cpp
@@ -350,7 +350,7 @@ void sanitizeDiagOpts(DiagnosticOptions &DiagOpts) {
// See `test/ClangScanDeps/diagnostic-pragmas.c` for an example.
llvm::erase_if(DiagOpts.Warnings, [](StringRef Warning) {
return llvm::StringSwitch<bool>(Warning)
- .Cases("pch-vfs-diff", "error=pch-vfs-diff", false)
+ .Cases({"pch-vfs-diff", "error=pch-vfs-diff"}, false)
.StartsWith("no-error=", false)
.Default(true);
});
generated by cgit v1.1 at 2025-11-03 16:15:52 +0000