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n>}{c|}{SSIE} & \multicolumn{1}{c|}{0} \\ \hline 4 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1 \\ \end{tabular} \end{center} } \vspace{-0.1in} \caption{Standard portion (bits 15:0) of {\tt mie}.} \label{miereg-standard} \end{figure*} \begin{commentary} The machine-level interrupt registers handle a few root interrupt sources which are assigned a fixed service priority for simplicity, while separate external interrupt controllers can implement a more complex prioritization scheme over a much larger set of interrupts that are then muxed into the machine-level interrupt sources. \end{commentary} \begin{commentary} The non-maskable interrupt is not made visible via the {\tt mip} register as its presence is implicitly known when executing the NMI trap handler. \end{commentary} Bits {\tt mip}.MEIP and {\tt mie}.MEIE are the interrupt-pending and interrupt-enable bits for machine-level external interrupts. MEIP is read-only in {\tt mip}, and is set and cleared by a platform-specific interrupt controller. Bits {\tt mip}.MTIP and {\tt mie}.MTIE are the interrupt-pending and interrupt-enable bits for machine timer interrupts. MTIP is read-only in {\tt mip}, and is cleared by writing to the memory-mapped machine-mode timer compare register. Bits {\tt mip}.MSIP and {\tt mie}.MSIE are the interrupt-pending and interrupt-enable bits for machine-level software interrupts. MSIP is read-only in {\tt mip}, and is written by accesses to memory-mapped control registers, which are used by remote harts to provide machine-level interprocessor interrupts. A hart can write its own MSIP bit using the same memory-mapped control register. If supervisor mode is not implemented, bits SEIP, STIP, and SSIP of {\tt mip} and SEIE, STIE, and SSIE of {\tt mie} are hardwired to zeros. If supervisor mode is implemented, bits {\tt mip}.SEIP and {\tt mie}.SEIE are the interrupt-pending and interrupt-enable bits for supervisor-level external interrupts. SEIP is writable in {\tt mip}, and may be written by M-mode software to indicate to S-mode that an external interrupt is pending. Additionally, the platform-level interrupt controller may generate supervisor-level external interrupts. Supervisor-level external interrupts are made pending based on the logical-OR of the software-writable SEIP bit and the signal from the external interrupt controller. When {\tt mip} is read with a CSR instruction, the value of the SEIP bit returned in the {\tt rd} destination register is the logical-OR of the software-writable bit and the interrupt signal from the interrupt controller, but the signal from the interrupt controller is not used to calculate the value written to SEIP. Only the software-writable SEIP bit participates in the read-modify-write sequence of a CSRRS or CSRRC instruction. \begin{commentary} The SEIP field behavior is designed to allow a higher privilege layer to mimic external interrupts cleanly, without losing any real external interrupts. The behavior of the CSR instructions is slightly modified from regular CSR accesses as a result. \end{commentary} If supervisor mode is implemented, bits {\tt mip}.STIP and {\tt mie}.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts. STIP is writable in {\tt mip}, and may be written by M-mode software to deliver timer interrupts to S-mode. If supervisor mode is implemented, bits {\tt mip}.SSIP and {\tt mie}.SSIE are the interrupt-pending and interrupt-enable bits for supervisor-level software interrupts. SSIP is writable in {\tt mip}. \begin{commentary} Interprocessor interrupts at supervisor level are implemented through implementation-specific mechanisms, e.g., via calls to an SEE, which might ultimately result in a machine-mode write to the receiving hart's MSIP bit. We allow a hart to directly write only its own SSIP bit, not those of other harts, as other harts might be virtualized and possibly descheduled by higher privilege levels. We rely on calls to the SEE to provide interprocessor interrupts for this reason. Machine-mode harts are not virtualized and can directly interrupt other harts by setting their MSIP bits, typically using uncached I/O writes to memory-mapped control registers depending on the platform specification. \end{commentary} Multiple simultaneous interrupts destined for different privilege modes are handled in decreasing order of destined privilege mode. Multiple simultaneous interrupts destined for the same privilege mode are handled in the following decreasing priority order: MEI, MSI, MTI, SEI, SSI, STI. Synchronous exceptions are of lower priority than all interrupts. \begin{commentary} The machine-level interrupt fixed-priority ordering rules were developed with the following rationale. Interrupts for higher privilege modes must be serviced before interrupts for lower privilege modes to support preemption. The platform-specific machine-level interrupt sources in bits 16 and above have platform-specific priority, but are typically chosen to have the highest service priority to support very fast local vectored interrupts. External interrupts are handled before internal (timer/software) interrupts as external interrupts are usually generated by devices that might require low interrupt service times. Software interrupts are handled before internal timer interrupts, because internal timer interrupts are usually intended for time slicing, where time precision is less important, whereas software interrupts are used for inter-processor messaging. Software interrupts can be avoided when high-precision timing is required, or high-precision timer interrupts can be routed via a different interrupt path. Software interrupts are located in the lowest four bits of {\tt mip} as these are often written by software, and this position allows the use of a single CSR instruction with a five-bit immediate. Synchronous exceptions are given the lowest priority to minimize worst-case interrupt latency. \end{commentary} Restricted views of the {\tt mip} and {\tt mie} registers appear as the {\tt sip} and {\tt sie} registers for supervisor level. If an interrupt is delegated to S-mode by setting a bit in the {\tt mideleg} register, it becomes visible in the {\tt sip} register and is maskable using the {\tt sie} register. Otherwise, the corresponding bits in {\tt sip} and {\tt sie} appear to be hardwired to zero. \subsection{Hardware Performance Monitor} M-mode includes a basic hardware performance-monitoring facility. The {\tt mcycle} CSR counts the number of clock cycles executed by the processor core on which the hart is running. The {\tt minstret} CSR counts the number of instructions the hart has retired. The {\tt mcycle} and {\tt minstret} registers have 64-bit precision on all RV32 and RV64 systems. The counter registers have an arbitrary value after the hart is reset, and can be written with a given value. Any CSR write takes effect after the writing instruction has otherwise completed. The {\tt mcycle} CSR may be shared between harts on the same core, in which case writes to {\tt mcycle} will be visible to those harts. The platform should provide a mechanism to indicate which harts share an {\tt mcycle} CSR. The hardware performance monitor includes 29 additional 64-bit event counters, {\tt mhpmcounter3}--{\tt mhpmcounter31}. The event selector CSRs, {\tt mhpmevent3}--{\tt mhpmevent31}, are MXLEN-bit \warl\ registers that control which event causes the corresponding counter to increment. The meaning of these events is defined by the platform, but event 0 is defined to mean ``no event.'' All counters should be implemented, but a legal implementation is to hard-wire both the counter and its corresponding event selector to 0. \begin{figure}[h!] {\footnotesize \begin{center} \begin{tabular}{@{}K@{}W@{}K} \instbitrange{63}{0} \\ \cline{1-1} \multicolumn{1}{|c|}{\tt mcycle} \\ \cline{1-1} \multicolumn{1}{|c|}{\tt minstret} \\ \cline{1-1} & & \instbitrange{MXLEN-1}{0} \\ \cline{1-1}\cline{3-3} \multicolumn{1}{|c|}{\tt mhpmcounter3} & & \multicolumn{1}{|c|}{\tt mhpmevent3} \\ \cline{1-1}\cline{3-3} \multicolumn{1}{|c|}{\tt mhpmcounter4} & & \multicolumn{1}{|c|}{\tt mhpmevent4} \\ \cline{1-1}\cline{3-3} \multicolumn{1}{c}{\vdots} & & \multicolumn{1}{c}{\vdots} \\ \cline{1-1}\cline{3-3} \multicolumn{1}{|c|}{\tt mhpmcounter30} & & \multicolumn{1}{|c|}{\tt mhpmevent30} \\ \cline{1-1}\cline{3-3} \multicolumn{1}{|c|}{\tt mhpmcounter31} & & \multicolumn{1}{|c|}{\tt mhpmevent31} \\ \cline{1-1}\cline{3-3} 64 & & MXLEN \\ \end{tabular} \end{center} } \vspace{-0.1in} \caption{Hardware performance monitor counters.} \end{figure} The {\tt mhpmcounter}s are \warl\ registers that support up to 64 bits of precision on RV32 and RV64. \begin{commentary} A future revision of this specification will define a mechanism to generate an interrupt when a hardware performance monitor counter overflows. \end{commentary} On RV32 only, reads of the {\tt mcycle}, {\tt minstret}, and {\tt mhpmcounter{\em n}} CSRs return the low 32 bits, while reads of the {\tt mcycleh}, {\tt minstreth}, and {\tt mhpmcounter{\em n}h} CSRs return bits 63--32 of the corresponding counter. \begin{figure}[h!] {\footnotesize \begin{center} \begin{tabular}{@{}K} \instbitrange{31}{0} \\ \hline \multicolumn{1}{|c|}{\tt mcycleh} \\ \hline \multicolumn{1}{|c|}{\tt minstreth} \\ \hline \multicolumn{1}{|c|}{\tt mhpmcounter3h} \\ \hline \multicolumn{1}{|c|}{\tt mhpmcounter4h} \\ \hline \multicolumn{1}{c}{\vdots} \\ \hline \multicolumn{1}{|c|}{\tt mhpmcounter30h} \\ \hline \multicolumn{1}{|c|}{\tt mhpmcounter31h} \\ \hline 32 \\ \end{tabular} \end{center} } \vspace{-0.1in} \caption{Upper 32 bits of hardware performance monitor counters, RV32 only.} \end{figure} %On RV128 systems, the 64-bit values in {\tt mcycle}, {\tt minstret}, and %{\tt mhpmcounter{\em n}} are sign-extended to 128-bits when read. %\begin{commentary} %On RV128 systems, both signed and unsigned 64-bit values are held in a %canonical form with bit 63 repeated in all higher bit positions. The %counters are 64-bit values even in RV128, and so the counter CSR reads %preserve the sign-extension invariant. Implementations may choose to %implement fewer bits of the counters, provided software would be unlikely %to experience wraparound (e.g., $2^{63}$ instructions executed) %and thereby avoid having to actually implement the sign-extension %circuitry. %\end{commentary} \subsection{Machine Counter-Enable Register ({\tt mcounteren})} \label{sec:mcounteren} The counter-enable register {\tt mcounteren} is a 32-bit register that controls the availability of the hardware performance-monitoring counters to the next-lowest privileged mode. \begin{figure*}[h!] {\footnotesize \begin{center} \setlength{\tabcolsep}{4pt} \begin{tabular}{cccMcccccc} \instbit{31} & \instbit{30} & \instbit{29} & \instbitrange{28}{6} & \instbit{5} & \instbit{4} & \instbit{3} & \instbit{2} & \instbit{1} & \instbit{0} \\ \hline \multicolumn{1}{|c|}{HPM31} & \multicolumn{1}{c|}{HPM30} & \multicolumn{1}{c|}{HPM29} & \multicolumn{1}{c|}{...} & \multicolumn{1}{c|}{HPM5} & \multicolumn{1}{c|}{HPM4} & \multicolumn{1}{c|}{HPM3} & \multicolumn{1}{c|}{IR} & \multicolumn{1}{c|}{TM} & \multicolumn{1}{c|}{CY} \\ \hline 1 & 1 & 1 & 23 & 1 & 1 & 1 & 1 & 1 & 1 \\ \end{tabular} \end{center} } \vspace{-0.1in} \caption{Counter-enable register ({\tt mcounteren}).} \label{mcounteren} \end{figure*} The settings in this register only control accessibility. The act of reading or writing this register does not affect the underlying counters, which continue to increment even when not accessible. When the CY, TM, IR, or HPM{\em n} bit in the {\tt mcounteren} register is clear, attempts to read the {\tt cycle}, {\tt time}, {\tt instret}, or {\tt hpmcounter{\em n}} register while executing in S-mode or U-mode will cause an illegal instruction exception. When one of these bits is set, access to the corresponding register is permitted in the next implemented privilege mode (S-mode if implemented, otherwise U-mode). \begin{commentary} The counter-enable bits support two common use cases with minimal hardware. For systems that do not need high-performance timers and counters, machine-mode software can trap accesses and implement all features in software. For systems that need high-performance timers and counters but are not concerned with obfuscating the underlying hardware counters, the counters can be directly exposed to lower privilege modes. \end{commentary} The {\tt cycle}, {\tt instret}, and {\tt hpmcounter{\em n}} CSRs are read-only shadows of {\tt mcycle}, {\tt minstret}, and {\tt mhpmcounter{\em n}}, respectively. The {\tt time} CSR is a read-only shadow of the memory-mapped {\tt mtime} register. Analogously, on RV32I the {\tt cycleh}, {\tt instreth} and {\tt hpmcounter{\em n}} CSRs are read-only shadows of {\tt mcycleh}, {\tt minstreth} and {\tt mhpmcounter{\em n}h}, respectively. On RV32I the {\tt timeh} CSR is a read-only shadow of the upper 32 bits of the memory-mapped {\tt mtime} register, while {\tt time} shadows only the lower 32 bits of {\tt mtime}. \begin{commentary} Implementations can convert reads of the {\tt time} and {\tt timeh} CSRs into loads to the memory-mapped {\tt mtime} register, or emulate this functionality in M-mode software. \end{commentary} In systems with U-mode, the {\tt mcounteren} must be implemented, but all fields are \warl\ and may be hardwired to zero, indicating reads to the corresponding counter will cause an illegal instruction exception when executing in a less-privileged mode. In systems without U-mode, the {\tt mcounteren} register should not exist. \subsection{Machine Counter-Inhibit CSR ({\tt mcountinhibit})} \begin{figure*}[h!] {\footnotesize \begin{center} \setlength{\tabcolsep}{4pt} \begin{tabular}{cccMcccccc} \instbit{31} & \instbit{30} & \instbit{29} & \instbitrange{28}{6} & \instbit{5} & \instbit{4} & \instbit{3} & \instbit{2} & \instbit{1} & \instbit{0} \\ \hline \multicolumn{1}{|c|}{HPM31} & \multicolumn{1}{c|}{HPM30} & \multicolumn{1}{c|}{HPM29} & \multicolumn{1}{c|}{...} & \multicolumn{1}{c|}{HPM5} & \multicolumn{1}{c|}{HPM4} & \multicolumn{1}{c|}{HPM3} & \multicolumn{1}{c|}{IR} & \multicolumn{1}{c|}{0} & \multicolumn{1}{c|}{CY} \\ \hline 1 & 1 & 1 & 23 & 1 & 1 & 1 & 1 & 1 & 1 \\ \end{tabular} \end{center} } \vspace{-0.1in} \caption{Counter-inhibit register {\tt mcountinhibit}.} \label{mcountinhibit} \end{figure*} The counter-inhibit register {\tt mcountinhibit} is a 32-bit \warl\ register that controls which of the hardware performance-monitoring counters increment. The settings in this register only control whether the counters increment; their accessibility is not affected by the setting of this register. When the CY, IR, or HPM{\em n} bit in the {\tt mcountinhibit} register is clear, the {\tt cycle}, {\tt instret}, or {\tt hpmcounter{\em n}} register increments as usual. When the CY, IR, or HPM{\em n} bit is set, the corresponding counter does not increment. The {\tt mcycle} CSR may be shared between harts on the same core, in which case the {\tt mcountinhibit}.CY field is also shared between those harts, and so writes to {\tt mcountinhibit}.CY will be visible to those harts. If the {\tt mcountinhibit} register is not implemented, the implementation behaves as though the register were set to zero. \begin{commentary} When the {\tt cycle} and {\tt instret} counters are not needed, it is desirable to conditionally inhibit them to reduce energy consumption. Providing a single CSR to inhibit all counters also allows the counters to be atomically sampled. Because the {\tt time} counter can be shared between multiple cores, it cannot be inhibited with the {\tt mcountinhibit} mechanism. \end{commentary} \subsection{Machine Scratch Register ({\tt mscratch})} The {\tt mscratch} register is an MXLEN-bit read/write register dedicated for use by machine mode. Typically, it is used to hold a pointer to a machine-mode hart-local context space and swapped with a user register upon entry to an M-mode trap handler. \begin{figure}[h!] {\footnotesize \begin{center} \begin{tabular}{@{}J} \instbitrange{MXLEN-1}{0} \\ \hline \multicolumn{1}{|c|}{\tt mscratch} \\ \hline MXLEN \\ \end{tabular} \end{center} } \vspace{-0.1in} \caption{Machine-mode scratch register.} \label{mscratchreg} \end{figure} \begin{commentary} The MIPS ISA allocated two user registers ({\tt k0}/{\tt k1}) for use by the operating system. Although the MIPS scheme provides a fast and simple implementation, it also reduces available user registers, and does not scale to further privilege levels, or nested traps. It can also require both registers are cleared before returning to user level to avoid a potential security hole and to provide deterministic debugging behavior. The RISC-V user ISA was designed to support many possible privileged system environments and so we did not want to infect the user-level ISA with any OS-dependent features. The RISC-V CSR swap instructions can quickly save/restore values to the {\tt mscratch} register. Unlike the MIPS design, the OS can rely on holding a value in the {\tt mscratch} register while the user context is running. \end{commentary} \subsection{Machine Exception Program Counter ({\tt mepc})} {\tt mepc} is an MXLEN-bit read/write register formatted as shown in Figure~\ref{mepcreg}. The low bit of {\tt mepc} ({\tt mepc[0]}) is always zero. On implementations that support only IALIGN=32, the two low bits ({\tt mepc[1:0]}) are always zero. If an implementation allows IALIGN to be either 16 or 32 (by changing CSR {\tt misa}, for example), then, whenever IALIGN=32, bit {\tt mepc[1]} is masked on reads so that it appears to be 0. This masking occurs also for the implicit read by the MRET instruction. Though masked, {\tt mepc[1]} remains writable when IALIGN=32. {\tt mepc} is a \warl\ register that must be able to hold all valid virtual addresses. It need not be capable of holding all possible invalid addresses. Implementations may convert some invalid address patterns into other invalid addresses prior to writing them to {\tt mepc}. \begin{commentary} When address translation is not in effect, virtual addresses and physical addresses are equal. Hence, the set of addresses {\tt mepc} must be able to represent includes the set of physical addresses that can be used as a valid {\tt pc} or effective address. \end{commentary} When a trap is taken into M-mode, {\tt mepc} is written with the virtual address of the instruction that was interrupted or that encountered the exception. Otherwise, {\tt mepc} is never written by the implementation, though it may be explicitly written by software. \begin{figure}[h!] {\footnotesize \begin{center} \begin{tabular}{@{}J} \instbitrange{MXLEN-1}{0} \\ \hline \multicolumn{1}{|c|}{\tt mepc} \\ \hline MXLEN \\ \end{tabular} \end{center} } \vspace{-0.1in} \caption{Machine exception program counter register.} \label{mepcreg} \end{figure} \subsection{Machine Cause Register ({\tt mcause})} \label{sec:mcause} The {\tt mcause} register is an MXLEN-bit read-write register formatted as shown in Figure~\ref{mcausereg}. When a trap is taken into M-mode, {\tt mcause} is written with a code indicating the event that caused the trap. Otherwise, {\tt mcause} is never written by the implementation, though it may be explicitly written by software. The Interrupt bit in the {\tt mcause} register is set if the trap was caused by an interrupt. The Exception Code field contains a code identifying the last exception or interrupt. Table~\ref{mcauses} lists the possible machine-level exception codes. The Exception Code is a \wlrl\ field, so is only guaranteed to hold supported exception codes. \begin{figure*}[h!] {\footnotesize \begin{center} \begin{tabular}{c@{}U} \instbit{MXLEN-1} & \instbitrange{MXLEN-2}{0} \\ \hline \multicolumn{1}{|c|}{Interrupt} & \multicolumn{1}{c|}{Exception Code (\wlrl)} \\ \hline 1 & MXLEN-1 \\ \end{tabular} \end{center} } \vspace{-0.1in} \caption{Machine Cause register {\tt mcause}.} \label{mcausereg} \end{figure*} \begin{table*}[htbp] \begin{center} \begin{tabular}{|r|r|l|l|} \hline Interrupt & Exception Code & Description \\ \hline 1 & 0 & {\em Reserved} \\ 1 & 1 & Supervisor software interrupt \\ 1 & 2 & {\em Reserved} \\ 1 & 3 & Machine software interrupt \\ \hline 1 & 4 & {\em Reserved} \\ 1 & 5 & Supervisor timer interrupt \\ 1 & 6 & {\em Reserved} \\ 1 & 7 & Machine timer interrupt \\ \hline 1 & 8 & {\em Reserved} \\ 1 & 9 & Supervisor external interrupt \\ 1 & 10 & {\em Reserved} \\ 1 & 11 & Machine external interrupt \\ \hline 1 & 12--15 & {\em Reserved} \\ 1 & $\ge$16 & {\em Designated for platform use} \\ \hline 0 & 0 & Instruction address misaligned \\ 0 & 1 & Instruction access fault \\ 0 & 2 & Illegal instruction \\ 0 & 3 & Breakpoint \\ 0 & 4 & Load address misaligned \\ 0 & 5 & Load access fault \\ 0 & 6 & Store/AMO address misaligned \\ 0 & 7 & Store/AMO access fault \\ 0 & 8 & Environment call from U-mode\\ 0 & 9 & Environment call from S-mode \\ 0 & 10 & {\em Reserved} \\ 0 & 11 & Environment call from M-mode \\ 0 & 12 & Instruction page fault \\ 0 & 13 & Load page fault \\ 0 & 14 & {\em Reserved} \\ 0 & 15 & Store/AMO page fault \\ 0 & 16--23 & {\em Reserved} \\ 0 & 24--31 & {\em Designated for custom use} \\ 0 & 32--47 & {\em Reserved} \\ 0 & 48--63 & {\em Designated for custom use} \\ 0 & $\ge$64 & {\em Reserved} \\ \hline \end{tabular} \end{center} \caption{Machine cause register ({\tt mcause}) values after trap.} \label{mcauses} \end{table*} Note that load and load-reserved instructions generate load exceptions, whereas store, store-conditional, and AMO instructions generate store/AMO exceptions. \begin{commentary} Interrupts can be separated from other traps with a single branch on the sign of the {\tt mcause} register value. A shift left can remove the interrupt bit and scale the exception codes to index into a trap vector table. \end{commentary} \begin{commentary} We do not distinguish privileged instruction exceptions from illegal opcode exceptions. This simplifies the architecture and also hides details of which higher-privilege instructions are supported by an implementation. The privilege level servicing the trap can implement a policy on whether these need to be distinguished, and if so, whether a given opcode should be treated as illegal or privileged. \end{commentary} If an instruction raises multiple synchronous exceptions, the decreasing priority order of Table~\ref{exception-priority} indicates which exception is taken and reported in {\tt mcause}. The priority of any custom synchronous exceptions is implementation-defined. \begin{table*}[htbp] \begin{center} \begin{tabular}{|l|r|l|} \hline Priority & Exception Code & Description \\ \hline {\em Highest} & 3 & Instruction address breakpoint \\ \hline & 12 & Instruction page fault \\ \hline & 1 & Instruction access fault \\ \hline & 2 & Illegal instruction \\ & 0 & Instruction address misaligned \\ & 8, 9, 11 & Environment call \\ & 3 & Environment break \\ & 3 & Load/Store/AMO address breakpoint \\ \hline {\em Optionally, these may have} & 6 & Store/AMO address misaligned \\ {\em lowest priority instead.} & 4 & Load address misaligned \\ \hline & 15 & Store/AMO page fault \\ & 13 & Load page fault \\ \hline & 7 & Store/AMO access fault \\ & 5 & Load access fault \\ \hline \end{tabular} \end{center} \caption{Synchronous exception priority in decreasing priority order.} \label{exception-priority} \end{table*} Note that load/store/AMO address-misaligned exceptions may have either higher or lower priority than load/store/AMO page-fault and access-fault exceptions. \begin{commentary} The relative priority of load/store/AMO address-misaligned and page-fault exceptions is implementation-defined to flexibly cater to two design points. Implementations that never support misaligned accesses can unconditionally raise the misaligned-address exception without performing address translation or protection checks. Implementations that support misaligned accesses only to some physical addresses must translate and check the address before determining whether the misaligned access may proceed, in which case raising the page-fault exception or access is more appropriate. \end{commentary} \begin{commentary} Instruction address breakpoints have the same cause value as, but different priority than, data address breakpoints (a.k.a. watchpoints) and environment break exceptions (which are raised by the EBREAK instruction). \end{commentary} \begin{commentary} Instruction address misaligned exceptions are raised by control-flow instructions with misaligned targets, rather than by the act of fetching an instruction. Therefore, these exceptions have lower priority than other instruction address exceptions. \end{commentary} \FloatBarrier \subsection{Machine Trap Value Register ({\tt mtval})} The {\tt mtval} register is an MXLEN-bit read-write register formatted as shown in Figure~\ref{mtvalreg}. When a trap is taken into M-mode, {\tt mtval} is either set to zero or written with exception-specific information to assist software in handling the trap. Otherwise, {\tt mtval} is never written by the implementation, though it may be explicitly written by software. The hardware platform will specify which exceptions must set {\tt mtval} informatively and which may unconditionally set it to zero. If the hardware platform specifies that no exceptions set {\tt mtval} to a nonzero value, then {\tt mtval} is hardwired to zero. If {\tt mtval} is not hardwired to zero, then when a breakpoint, address-misaligned, access-fault, or page-fault exception occurs on an instruction fetch, load, or store, {\tt mtval} is written with the faulting virtual address. On an illegal instruction trap, {\tt mtval} may be written with the first XLEN or ILEN bits of the faulting instruction as described below. For other traps, {\tt mtval} is set to zero, but a future standard may redefine {\tt mtval}'s setting for other traps. \begin{commentary} The {\tt mtval} register replaces the {\tt mbadaddr} register in the previous specification. In addition to providing bad addresses, the register can now provide the bad instruction that triggered an illegal instruction trap (and may in future be used to return other information). Returning the instruction bits accelerates instruction emulation and also removes some races that might be present when trying to emulate illegal instructions. \end{commentary} \begin{commentary} When page-based virtual memory is enabled, {\tt mtval} is written with the faulting virtual address, even for physical-memory access-fault exceptions. This design reduces datapath cost for most implementations, particularly those with hardware page-table walkers. \end{commentary} \begin{figure}[h!] {\footnotesize \begin{center} \begin{tabular}{@{}J} \instbitrange{MXLEN-1}{0} \\ \hline \multicolumn{1}{|c|}{\tt mtval} \\ \hline MXLEN \\ \end{tabular} \end{center} } \vspace{-0.1in} \caption{Machine Trap Value register.} \label{mtvalreg} \end{figure} For misaligned loads and stores that cause access-fault or page-fault exceptions, {\tt mtval} will contain the virtual address of the portion of the access that caused the fault (unless {\tt mtval} is hardwired to zero). For instruction access-fault or page-fault exceptions on systems with variable-length instructions, {\tt mtval} will contain the virtual address of the portion of the instruction that caused the fault (unless {\tt mtval} is hardwired to zero). {\tt mepc} will point to the beginning of the instruction. The {\tt mtval} register can optionally also be used to return the faulting instruction bits on an illegal instruction exception ({\tt mepc} points to the faulting instruction in memory). If this feature is not provided, then {\tt mtval} is set to zero on an illegal instruction fault. If this feature is provided, after an illegal instruction trap, {\tt mtval} will contain the shortest of: \begin{compactitem} \item the actual faulting instruction \item the first ILEN bits of the faulting instruction \item the first XLEN bits of the faulting instruction \end{compactitem} The value loaded into {\tt mtval} is right-justified and all unused upper bits are cleared to zero. \begin{commentary} Capturing the faulting instruction in {\tt mtval} reduces the overhead of instruction emulation, potentially avoiding several partial instruction loads if the instruction is misaligned, and likely data cache misses or slow uncached accesses when loads are used to fetch the instruction into a data register. There is also a problem of atomicity if another agent is manipulating the instruction memory, as might occur in a dynamic translation system. A requirement is that the entire instruction (or at least the first XLEN bits) are fetched into {\tt mtval} before taking the trap. This should not constrain implementations, which would typically fetch the entire instruction before attempting to decode the instruction, and avoids complicating software handlers. A value of zero in {\tt mtval} signifies either that the feature is not supported, or an illegal zero instruction was fetched. A load from the instruction memory pointed to by {\tt mepc} can be used to distinguish these two cases (or alternatively, the system configuration information can be interrogated to install the appropriate trap handling before runtime). \end{commentary} If {\tt mtval} is not hardwired to zero, it is a \warl\ register that must be able to hold all valid virtual addresses and the value zero. It need not be capable of holding all possible invalid addresses. Implementations may convert some invalid address patterns into other invalid addresses prior to writing them to {\tt mtval}. If the feature to return the faulting instruction bits is implemented, {\tt mtval} must also be able to hold all values less than $2^N$, where $N$ is the smaller of XLEN and ILEN. \section{Machine-Level Memory-Mapped Registers} \subsection{Machine Timer Registers ({\tt mtime} and {\tt mtimecmp})} Platforms provide a real-time counter, exposed as a memory-mapped machine-mode read-write register, {\tt mtime}. {\tt mtime} must increment at constant frequency, and the platform must provide a mechanism for determining the timebase of {\tt mtime}. The {\tt mtime} register will wrap around if the count overflows. The {\tt mtime} register has a 64-bit precision on all RV32 and RV64 systems. Platforms provide a 64-bit memory-mapped machine-mode timer compare register ({\tt mtimecmp}). A machine timer interrupt becomes pending whenever {\tt mtime} contains a value greater than or equal to {\tt mtimecmp}, treating the values as unsigned integers. The interrupt remains posted until {\tt mtimecmp} becomes greater than {\tt mtime} (typically as a result of writing {\tt mtimecmp}). The interrupt will only be taken if interrupts are enabled and the MTIE bit is set in the {\tt mie} register. \begin{figure}[h!] {\footnotesize \begin{center} \begin{tabular}{@{}J} \instbitrange{63}{0} \\ \hline \multicolumn{1}{|c|}{\tt mtime} \\ \hline 64 \\ \end{tabular} \end{center} } \vspace{-0.1in} \caption{Machine time register (memory-mapped control register).} \end{figure} \begin{figure}[h!] {\footnotesize \begin{center} \begin{tabular}{@{}J} \instbitrange{63}{0} \\ \hline \multicolumn{1}{|c|}{\tt mtimecmp} \\ \hline 64 \\ \end{tabular} \end{center} } \vspace{-0.1in} \caption{Machine time compare register (memory-mapped control register).} \end{figure} \begin{commentary} The timer facility is defined to use wall-clock time rather than a cycle counter to support modern processors that run with a highly variable clock frequency to save energy through dynamic voltage and frequency scaling. Accurate real-time clocks (RTCs) are relatively expensive to provide (requiring a crystal or MEMS oscillator) and have to run even when the rest of system is powered down, and so there is usually only one in a system located in a different frequency/voltage domain from the processors. Hence, the RTC must be shared by all the harts in a system and accesses to the RTC will potentially incur the penalty of a voltage-level-shifter and clock-domain crossing. It is thus more natural to expose {\tt mtime} as a memory-mapped register than as a CSR. Lower privilege levels do not have their own {\tt timecmp} registers. Instead, machine-mode software can implement any number of virtual timers on a hart by multiplexing the next timer interrupt into the {\tt mtimecmp} register. Simple fixed-frequency systems can use a single clock for both cycle counting and wall-clock time. \end{commentary} Writes to {\tt mtime} and {\tt mtimecmp} are guaranteed to be reflected in MTIP eventually, but not necessarily immediately. \begin{commentary} A spurious timer interrupt might occur if an interrupt handler increments {\tt mtimecmp} then immediately returns, because MTIP might not yet have fallen in the interim. All software should be written to assume this event is possible, but most software should assume this event is extremely unlikely. It is almost always more performant to incur an occasional spurious timer interrupt than to poll MTIP until it falls. \end{commentary} In RV32, memory-mapped writes to {\tt mtimecmp} modify only one 32-bit part of the register. The following code sequence sets a 64-bit {\tt mtimecmp} value without spuriously generating a timer interrupt due to the intermediate value of the comparand: \begin{figure}[h!] \begin{center} \begin{verbatim} # New comparand is in a1:a0. li t0, -1 la t1, mtimecmp sw t0, 0(t1) # No smaller than old value. sw a1, 4(t1) # No smaller than new value. sw a0, 0(t1) # New value. \end{verbatim} \end{center} \caption{Sample code for setting the 64-bit time comparand in RV32, assuming a little-endian memory system and that the registers live in a strongly ordered I/O region. Storing -1 to the low-order bits of {\tt mtimecmp} prevents {\tt mtimecmp} from temporarily becoming smaller than the lesser of the old and new values.} \label{mtimecmph} \end{figure} For RV64, naturally aligned 64-bit memory accesses to the {\tt mtime} and {\tt mtimecmp} registers are atomic. \section{Machine-Mode Privileged Instructions} \subsection{Environment Call and Breakpoint} \vspace{-0.2in} \begin{center} \begin{tabular}{M@{}R@{}F@{}R@{}S} \\ \instbitrange{31}{20} & \instbitrange{19}{15} & \instbitrange{14}{12} & \instbitrange{11}{7} & \instbitrange{6}{0} \\ \hline \multicolumn{1}{|c|}{funct12} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{funct3} & \multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{opcode} \\ \hline 12 & 5 & 3 & 5 & 7 \\ ECALL & 0 & PRIV & 0 & SYSTEM \\ EBREAK & 0 & PRIV & 0 & SYSTEM \\ \end{tabular} \end{center} The ECALL instruction is used to make a request to the supporting execution environment. When executed in U-mode, S-mode, or M-mode, it generates an environment-call-from-U-mode exception, environment-call-from-S-mode exception, or environment-call-from-M-mode exception, respectively, and performs no other operation. \begin{commentary} ECALL generates a different exception for each originating privilege mode so that environment call exceptions can be selectively delegated. A typical use case for Unix-like operating systems is to delegate to S-mode the environment-call-from-U-mode exception but not the others. \end{commentary} The EBREAK instruction is used by debuggers to cause control to be transferred back to a debugging environment. It generates a breakpoint exception and performs no other operation. \begin{commentary} As described in the ``C'' Standard Extension for Compressed Instructions in Volume I of this manual, the C.EBREAK instruction performs the same operation as the EBREAK instruction. \end{commentary} ECALL and EBREAK cause the receiving privilege mode's {\tt epc} register to be set to the address of the ECALL or EBREAK instruction itself, {\em not} the address of the following instruction. As ECALL and EBREAK cause synchronous exceptions, they are not considered to retire, and should not increment the {\tt minstret} CSR. \subsection{Trap-Return Instructions} \label{otherpriv} Instructions to return from trap are encoded under the PRIV minor opcode. \vspace{-0.2in} \begin{center} \begin{tabular}{M@{}R@{}F@{}R@{}S} \\ \instbitrange{31}{20} & \instbitrange{19}{15} & \instbitrange{14}{12} & \instbitrange{11}{7} & \instbitrange{6}{0} \\ \hline \multicolumn{1}{|c|}{funct12} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{funct3} & \multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{opcode} \\ \hline 12 & 5 & 3 & 5 & 7 \\ MRET/SRET & 0 & PRIV & 0 & SYSTEM \\ \end{tabular} \end{center} To return after handling a trap, there are separate trap return instructions per privilege level, MRET and SRET. MRET is always provided. SRET must be provided if supervisor mode is supported, and should raise an illegal instruction exception otherwise. SRET should also raise an illegal instruction exception when TSR=1 in {\tt mstatus}, as described in Section~\ref{virt-control}. An {\em x}\/RET instruction can be executed in privilege mode {\em x} or higher, where executing a lower-privilege {\em x}\/RET instruction will pop the relevant lower-privilege interrupt enable and privilege mode stack. In addition to manipulating the privilege stack as described in Section~\ref{privstack}, {\em x}\/RET sets the {\tt pc} to the value stored in the {\em x}\/{\tt epc} register. \begin{commentary} Previously, there was only a single ERET instruction (which was also earlier known as SRET). To support the addition of user-level interrupts, we needed to add a separate URET instruction to continue to allow classic virtualization of OS code using the ERET instruction. It then became more orthogonal to support a different {\em x}\/RET instruction per privilege level. \end{commentary} If the A extension is supported, the {\em x}\/RET instruction is allowed to clear any outstanding LR address reservation but is not required to. Trap handlers should explicitly clear the reservation if required (e.g., by using a dummy SC) before executing the {\em x}\/RET. \begin{commentary} If {\em x}\/RET instructions always cleared LR reservations, it would be impossible to single-step through LR/SC sequences using a debugger. \end{commentary} \subsection{Wait for Interrupt} \label{wfi} The Wait for Interrupt instruction (WFI) provides a hint to the implementation that the current hart can be stalled until an interrupt might need servicing. Execution of the WFI instruction can also be used to inform the hardware platform that suitable interrupts should preferentially be routed to this hart. WFI is available in all privileged modes, and optionally available to U-mode. This instruction may raise an illegal instruction exception when TW=1 in {\tt mstatus}, as described in Section~\ref{virt-control}. \vspace{-0.2in} \begin{center} \begin{tabular}{M@{}R@{}F@{}R@{}S} \\ \instbitrange{31}{20} & \instbitrange{19}{15} & \instbitrange{14}{12} & \instbitrange{11}{7} & \instbitrange{6}{0} \\ \hline \multicolumn{1}{|c|}{funct12} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{funct3} & \multicolumn{1}{c|}{rd} & \multicolumn{1}{c|}{opcode} \\ \hline 12 & 5 & 3 & 5 & 7 \\ WFI & 0 & PRIV & 0 & SYSTEM \\ \end{tabular} \end{center} If an enabled interrupt is present or later becomes present while the hart is stalled, the interrupt exception will be taken on the following instruction, i.e., execution resumes in the trap handler and {\tt mepc} = {\tt pc} + 4. \begin{commentary} The following instruction takes the interrupt exception and trap, so that a simple return from the trap handler will execute code after the WFI instruction. \end{commentary} The purpose of the WFI instruction is to provide a hint to the implementation, and so a legal implementation is to simply implement WFI as a NOP. \begin{commentary} If the implementation does not stall the hart on execution of the instruction, then the interrupt will be taken on some instruction in the idle loop containing the WFI, and on a simple return from the handler, the idle loop will resume execution. \end{commentary} The WFI instruction can also be executed when interrupts are disabled. The operation of WFI must be unaffected by the global interrupt bits in {\tt mstatus} (MIE and SIE) and the delegation register {\tt mideleg} (i.e., the hart must resume if a locally enabled interrupt becomes pending, even if it has been delegated to a less-privileged mode), but should honor the individual interrupt enables (e.g, MTIE) (i.e., implementations should avoid resuming the hart if the interrupt is pending but not individually enabled). WFI is also required to resume execution for locally enabled interrupts pending at any privilege level, regardless of the global interrupt enable at each privilege level. If the event that causes the hart to resume execution does not cause an interrupt to be taken, execution will resume at {\tt pc} + 4, and software must determine what action to take, including looping back to repeat the WFI if there was no actionable event. \begin{commentary} By allowing wakeup when interrupts are disabled, an alternate entry point to an interrupt handler can be called that does not require saving the current context, as the current context can be saved or discarded before the WFI is executed. As implementations are free to implement WFI as a NOP, software must explicitly check for any relevant pending but disabled interrupts in the code following an WFI, and should loop back to the WFI if no suitable interrupt was detected. The {\tt mip} or {\tt sip} registers can be interrogated to determine the presence of any interrupt in machine or supervisor mode respectively. The operation of WFI is unaffected by the delegation register settings. WFI is defined so that an implementation can trap into a higher privilege mode, either immediately on encountering the WFI or after some interval to initiate a machine-mode transition to a lower power state, for example. \end{commentary} \begin{commentary} The same ``wait-for-event'' template might be used for possible future extensions that wait on memory locations changing, or message arrival. \end{commentary} \section{Reset} \label{sec:reset} Upon reset, a hart's privilege mode is set to M. The {\tt mstatus} fields MIE and MPRV are reset to 0. If little-endian memory accesses are supported, the {\tt mstatus}/{\tt mstatush} field MBE is reset to 0. The {\tt misa} register is reset to enable the maximal set of supported extensions and widest MXLEN, as described in Section~\ref{sec:misa}. The {\tt pc} is set to an implementation-defined reset vector. The {\tt mcause} register is set to a value indicating the cause of the reset. Writable PMP registers' A and L fields are set to 0, unless the platform mandates a different reset value for some PMP registers' A and L fields. All other hart state is \unspecified. The {\tt mcause} values after reset have implementation-specific interpretation, but the value 0 should be returned on implementations that do not distinguish different reset conditions. Implementations that distinguish different reset conditions should only use 0 to indicate the most complete reset. \begin{commentary} Some designs may have multiple causes of reset (e.g., power-on reset, external hard reset, brownout detected, watchdog timer elapse, sleep-mode wakeup), which machine-mode software and debuggers may wish to distinguish. {\tt mcause} reset values may alias {\tt mcause} values following synchronous exceptions. There should be no ambiguity in this overlap, since on reset the {\tt pc} is typically set to a different value than on other traps. \end{commentary} \section{Non-Maskable Interrupts} \label{sec:nmi} Non-maskable interrupts (NMIs) are only used for hardware error conditions, and cause an immediate jump to an implementation-defined NMI vector running in M-mode regardless of the state of a hart's interrupt enable bits. The {\tt mepc} register is written with the virtual address of the instruction that was interrupted, and {\tt mcause} is set to a value indicating the source of the NMI. The NMI can thus overwrite state in an active machine-mode interrupt handler. The values written to {\tt mcause} on an NMI are implementation-defined. The high Interrupt bit of {\tt mcause} should be set to indicate that this was an interrupt. An Exception Code of 0 is reserved to mean ``unknown cause'' and implementations that do not distinguish sources of NMIs via the {\tt mcause} register should return 0 in the Exception Code. Unlike resets, NMIs do not reset processor state, enabling diagnosis, reporting, and possible containment of the hardware error. \section{Physical Memory Attributes} \label{sec:pma} The physical memory map for a complete system includes various address ranges, some corresponding to memory regions, some to memory-mapped control registers, and some to vacant holes in the address space. Some memory regions might not support reads, writes, or execution; some might not support subword or subblock accesses; some might not support atomic operations; and some might not support cache coherence or might have different memory models. Similarly, memory-mapped control registers vary in their supported access widths, support for atomic operations, and whether read and write accesses have associated side effects. In RISC-V systems, these properties and capabilities of each region of the machine's physical address space are termed {\em physical memory attributes} (PMAs). This section describes RISC-V PMA terminology and how RISC-V systems implement and check PMAs. PMAs are inherent properties of the underlying hardware and rarely change during system operation. Unlike physical memory protection values described in Section~\ref{sec:pmp}, PMAs do not vary by execution context. The PMAs of some memory regions are fixed at chip design time---for example, for an on-chip ROM. Others are fixed at board design time, depending, for example, on which other chips are connected to off-chip buses. Off-chip buses might also support