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-rw-r--r--clang/lib/Basic/Targets/AArch64.cpp1
-rw-r--r--clang/lib/Basic/Targets/AMDGPU.cpp4
-rw-r--r--clang/lib/Basic/Targets/AVR.cpp30
-rw-r--r--clang/lib/Basic/Targets/DirectX.h5
-rw-r--r--clang/lib/Basic/Targets/Mips.cpp7
-rw-r--r--clang/lib/Basic/Targets/Mips.h3
-rw-r--r--clang/lib/Basic/Targets/OSTargets.h17
-rw-r--r--clang/lib/Basic/Targets/SystemZ.cpp13
-rw-r--r--clang/lib/Basic/Targets/SystemZ.h6
-rw-r--r--clang/lib/Basic/Targets/WebAssembly.h21
-rw-r--r--clang/lib/Basic/Targets/X86.cpp5
11 files changed, 85 insertions, 27 deletions
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index 9e03a08..18641a9 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -1568,6 +1568,7 @@ bool AArch64TargetInfo::validateAsmConstraint(
if (const unsigned Len = matchAsmCCConstraint(Name)) {
Name += Len - 1;
Info.setAllowsRegister();
+ Info.setOutputOperandBounds(0, 2);
return true;
}
}
diff --git a/clang/lib/Basic/Targets/AMDGPU.cpp b/clang/lib/Basic/Targets/AMDGPU.cpp
index 87de9e6..d4de704 100644
--- a/clang/lib/Basic/Targets/AMDGPU.cpp
+++ b/clang/lib/Basic/Targets/AMDGPU.cpp
@@ -27,11 +27,11 @@ namespace targets {
// getPointerWidthV().
static const char *const DataLayoutStringR600 =
- "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
+ "e-m:e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1";
static const char *const DataLayoutStringAMDGCN =
- "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
+ "e-m:e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32"
"-p7:160:256:256:32-p8:128:128:128:48-p9:192:256:256:32-i64:64-"
"v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-"
"v2048:2048-n32:64-S32-A5-G1-ni:7:8:9";
diff --git a/clang/lib/Basic/Targets/AVR.cpp b/clang/lib/Basic/Targets/AVR.cpp
index bbe7b01..2673669 100644
--- a/clang/lib/Basic/Targets/AVR.cpp
+++ b/clang/lib/Basic/Targets/AVR.cpp
@@ -420,23 +420,23 @@ static MCUInfo AVRMcus[] = {
static bool ArchHasELPM(StringRef Arch) {
return llvm::StringSwitch<bool>(Arch)
- .Cases("31", "51", "6", true)
- .Cases("102", "104", "105", "106", "107", true)
- .Default(false);
+ .Cases({"31", "51", "6"}, true)
+ .Cases({"102", "104", "105", "106", "107"}, true)
+ .Default(false);
}
static bool ArchHasELPMX(StringRef Arch) {
return llvm::StringSwitch<bool>(Arch)
- .Cases("51", "6", true)
- .Cases("102", "104", "105", "106", "107", true)
- .Default(false);
+ .Cases({"51", "6"}, true)
+ .Cases({"102", "104", "105", "106", "107"}, true)
+ .Default(false);
}
static bool ArchHasMOVW(StringRef Arch) {
return llvm::StringSwitch<bool>(Arch)
- .Cases("25", "35", "4", "5", "51", "6", true)
- .Cases("102", "103", "104", "105", "106", "107", true)
- .Default(false);
+ .Cases({"25", "35", "4", "5", "51", "6"}, true)
+ .Cases({"102", "103", "104", "105", "106", "107"}, true)
+ .Default(false);
}
static bool ArchHasLPMX(StringRef Arch) {
@@ -445,16 +445,16 @@ static bool ArchHasLPMX(StringRef Arch) {
static bool ArchHasMUL(StringRef Arch) {
return llvm::StringSwitch<bool>(Arch)
- .Cases("4", "5", "51", "6", true)
- .Cases("102", "103", "104", "105", "106", "107", true)
- .Default(false);
+ .Cases({"4", "5", "51", "6"}, true)
+ .Cases({"102", "103", "104", "105", "106", "107"}, true)
+ .Default(false);
}
static bool ArchHasJMPCALL(StringRef Arch) {
return llvm::StringSwitch<bool>(Arch)
- .Cases("3", "31", "35", "5", "51", "6", true)
- .Cases("102", "103", "104", "105", "106", "107", true)
- .Default(false);
+ .Cases({"3", "31", "35", "5", "51", "6"}, true)
+ .Cases({"102", "103", "104", "105", "106", "107"}, true)
+ .Default(false);
}
static bool ArchHas3BytePC(StringRef Arch) {
diff --git a/clang/lib/Basic/Targets/DirectX.h b/clang/lib/Basic/Targets/DirectX.h
index bd13c9e..a21a593 100644
--- a/clang/lib/Basic/Targets/DirectX.h
+++ b/clang/lib/Basic/Targets/DirectX.h
@@ -64,8 +64,11 @@ public:
NoAsmVariants = true;
PlatformMinVersion = Triple.getOSVersion();
PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
+ // TODO: We need to align vectors on the element size generally, but for now
+ // we hard code this for 3-element 32- and 64-bit vectors as a workaround.
+ // See https://github.com/llvm/llvm-project/issues/123968
resetDataLayout("e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-f32:"
- "32-f64:64-n8:16:32:64");
+ "32-f64:64-n8:16:32:64-v48:16:16-v96:32:32-v192:64:64");
TheCXXABI.set(TargetCXXABI::GenericItanium);
}
bool useFP16ConversionIntrinsics() const override { return false; }
diff --git a/clang/lib/Basic/Targets/Mips.cpp b/clang/lib/Basic/Targets/Mips.cpp
index 34837cc..de6ccff 100644
--- a/clang/lib/Basic/Targets/Mips.cpp
+++ b/clang/lib/Basic/Targets/Mips.cpp
@@ -72,7 +72,7 @@ unsigned MipsTargetInfo::getISARev() const {
.Cases("mips32r2", "mips64r2", "octeon", "octeon+", 2)
.Cases("mips32r3", "mips64r3", 3)
.Cases("mips32r5", "mips64r5", "p5600", 5)
- .Cases("mips32r6", "mips64r6", 6)
+ .Cases("mips32r6", "mips64r6", "i6400", "i6500", 6)
.Default(0);
}
@@ -270,8 +270,9 @@ bool MipsTargetInfo::validateTarget(DiagnosticsEngine &Diags) const {
return false;
}
// Mips revision 6 and -mfp32 are incompatible
- if (FPMode != FP64 && FPMode != FPXX && (CPU == "mips32r6" ||
- CPU == "mips64r6")) {
+ if (FPMode != FP64 && FPMode != FPXX &&
+ (CPU == "mips32r6" || CPU == "mips64r6" || CPU == "i6400" ||
+ CPU == "i6500")) {
Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfp32" << CPU;
return false;
}
diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h
index e199df3..930271c 100644
--- a/clang/lib/Basic/Targets/Mips.h
+++ b/clang/lib/Basic/Targets/Mips.h
@@ -83,7 +83,8 @@ public:
}
bool isIEEE754_2008Default() const {
- return CPU == "mips32r6" || CPU == "mips64r6";
+ return CPU == "mips32r6" || CPU == "mips64r6" || CPU == "i6400" ||
+ CPU == "i6500";
}
enum FPModeEnum getDefaultFPMode() const {
diff --git a/clang/lib/Basic/Targets/OSTargets.h b/clang/lib/Basic/Targets/OSTargets.h
index 6c49a09..bd6ffcf 100644
--- a/clang/lib/Basic/Targets/OSTargets.h
+++ b/clang/lib/Basic/Targets/OSTargets.h
@@ -948,6 +948,23 @@ public:
using WebAssemblyOSTargetInfo<Target>::WebAssemblyOSTargetInfo;
};
+// WALI target
+template <typename Target>
+class LLVM_LIBRARY_VISIBILITY WALITargetInfo
+ : public WebAssemblyOSTargetInfo<Target> {
+ void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
+ MacroBuilder &Builder) const final {
+ WebAssemblyOSTargetInfo<Target>::getOSDefines(Opts, Triple, Builder);
+ // Linux defines; list based off of gcc output
+ DefineStd(Builder, "unix", Opts);
+ DefineStd(Builder, "linux", Opts);
+ Builder.defineMacro("__wali__");
+ }
+
+public:
+ using WebAssemblyOSTargetInfo<Target>::WebAssemblyOSTargetInfo;
+};
+
// Emscripten target
template <typename Target>
class LLVM_LIBRARY_VISIBILITY EmscriptenTargetInfo
diff --git a/clang/lib/Basic/Targets/SystemZ.cpp b/clang/lib/Basic/Targets/SystemZ.cpp
index 13b8623..30f846c 100644
--- a/clang/lib/Basic/Targets/SystemZ.cpp
+++ b/clang/lib/Basic/Targets/SystemZ.cpp
@@ -99,6 +99,16 @@ bool SystemZTargetInfo::validateAsmConstraint(
case 'T': // Likewise, plus an index
Info.setAllowsMemory();
return true;
+ case '@':
+ // CC condition changes.
+ if (StringRef(Name) == "@cc") {
+ Name += 2;
+ Info.setAllowsRegister();
+ // SystemZ has 2-bits CC, and hence Interval [0, 4).
+ Info.setOutputOperandBounds(0, 4);
+ return true;
+ }
+ return false;
}
}
@@ -161,6 +171,9 @@ unsigned SystemZTargetInfo::getMinGlobalAlign(uint64_t Size,
void SystemZTargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
+ // Inline assembly supports SystemZ flag outputs.
+ Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
+
Builder.defineMacro("__s390__");
Builder.defineMacro("__s390x__");
Builder.defineMacro("__zarch__");
diff --git a/clang/lib/Basic/Targets/SystemZ.h b/clang/lib/Basic/Targets/SystemZ.h
index dc2185e..4e15d5a 100644
--- a/clang/lib/Basic/Targets/SystemZ.h
+++ b/clang/lib/Basic/Targets/SystemZ.h
@@ -136,6 +136,12 @@ public:
std::string convertConstraint(const char *&Constraint) const override {
switch (Constraint[0]) {
+ case '@': // Flag output operand.
+ if (llvm::StringRef(Constraint) == "@cc") {
+ Constraint += 2;
+ return std::string("{@cc}");
+ }
+ break;
case 'p': // Keep 'p' constraint.
return std::string("p");
case 'Z':
diff --git a/clang/lib/Basic/Targets/WebAssembly.h b/clang/lib/Basic/Targets/WebAssembly.h
index eba7422..4de6ce6 100644
--- a/clang/lib/Basic/Targets/WebAssembly.h
+++ b/clang/lib/Basic/Targets/WebAssembly.h
@@ -88,12 +88,23 @@ public:
LongDoubleWidth = LongDoubleAlign = 128;
LongDoubleFormat = &llvm::APFloat::IEEEquad();
MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
- // size_t being unsigned long for both wasm32 and wasm64 makes mangled names
- // more consistent between the two.
- SizeType = UnsignedLong;
- PtrDiffType = SignedLong;
- IntPtrType = SignedLong;
HasUnalignedAccess = true;
+ if (T.isWALI()) {
+ // The WALI ABI is documented here:
+ // https://doc.rust-lang.org/rustc/platform-support/wasm32-wali-linux.html
+ // Currently, this ABI only applies to wasm32 targets and notably requires
+ // 64-bit longs
+ LongAlign = LongWidth = 64;
+ SizeType = UnsignedInt;
+ PtrDiffType = SignedInt;
+ IntPtrType = SignedInt;
+ } else {
+ // size_t being unsigned long for both wasm32 and wasm64 makes mangled
+ // names more consistent between the two.
+ SizeType = UnsignedLong;
+ PtrDiffType = SignedLong;
+ IntPtrType = SignedLong;
+ }
}
StringRef getABI() const override;
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 6eb4db5..e71f10c 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -625,6 +625,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
case CK_ArrowlakeS:
case CK_Lunarlake:
case CK_Pantherlake:
+ case CK_Wildcatlake:
+ case CK_Novalake:
case CK_Sierraforest:
case CK_Grandridge:
case CK_Graniterapids:
@@ -1516,6 +1518,7 @@ bool X86TargetInfo::validateAsmConstraint(
if (auto Len = matchAsmCCConstraint(Name)) {
Name += Len - 1;
Info.setAllowsRegister();
+ Info.setOutputOperandBounds(0, 2);
return true;
}
return false;
@@ -1612,6 +1615,8 @@ std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
case CK_ArrowlakeS:
case CK_Lunarlake:
case CK_Pantherlake:
+ case CK_Wildcatlake:
+ case CK_Novalake:
case CK_Sierraforest:
case CK_Grandridge:
case CK_Graniterapids:
generated by cgit v1.1 at 2025-10-19 10:30:06 +0000