diff options
Diffstat (limited to 'clang/lib/Basic/Targets')
| -rw-r--r-- | clang/lib/Basic/Targets/AArch64.cpp | 12 | ||||
| -rw-r--r-- | clang/lib/Basic/Targets/Hexagon.cpp | 6 | ||||
| -rw-r--r-- | clang/lib/Basic/Targets/PPC.h | 30 |
3 files changed, 25 insertions, 23 deletions
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp index c2d1bc1..a97e934 100644 --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -811,10 +811,10 @@ bool AArch64TargetInfo::validateCpuSupports(StringRef FeatureStr) const { bool AArch64TargetInfo::hasFeature(StringRef Feature) const { return llvm::StringSwitch<bool>(Feature) - .Cases("aarch64", "arm64", "arm", true) + .Cases({"aarch64", "arm64", "arm"}, true) .Case("fmv", HasFMV) .Case("fp", FPU & FPUMode) - .Cases("neon", "simd", FPU & NeonMode) + .Cases({"neon", "simd"}, FPU & NeonMode) .Case("jscvt", HasJSCVT) .Case("fcma", HasFCMA) .Case("rng", HasRandGen) @@ -829,8 +829,8 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const { .Case("cssc", HasCSSC) .Case("sha2", HasSHA2) .Case("sha3", HasSHA3) - .Cases("aes", "pmull", HasAES) - .Cases("fp16", "fullfp16", HasFullFP16) + .Cases({"aes", "pmull"}, HasAES) + .Cases({"fp16", "fullfp16"}, HasFullFP16) .Case("dit", HasDIT) .Case("dpb", HasCCPP) .Case("dpb2", HasCCDP) @@ -859,9 +859,9 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const { .Case("memtag", HasMTE) .Case("sb", HasSB) .Case("predres", HasPredRes) - .Cases("ssbs", "ssbs2", HasSSBS) + .Cases({"ssbs", "ssbs2"}, HasSSBS) .Case("bti", HasBTI) - .Cases("ls64", "ls64_v", "ls64_accdata", HasLS64) + .Cases({"ls64", "ls64_v", "ls64_accdata"}, HasLS64) .Case("wfxt", HasWFxT) .Case("rcpc3", HasRCPC3) .Case("fp8", HasFP8) diff --git a/clang/lib/Basic/Targets/Hexagon.cpp b/clang/lib/Basic/Targets/Hexagon.cpp index cea64f9..d5b413cb 100644 --- a/clang/lib/Basic/Targets/Hexagon.cpp +++ b/clang/lib/Basic/Targets/Hexagon.cpp @@ -83,6 +83,9 @@ void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, } else if (CPU == "hexagonv79") { Builder.defineMacro("__HEXAGON_V79__"); Builder.defineMacro("__HEXAGON_ARCH__", "79"); + } else if (CPU == "hexagonv81") { + Builder.defineMacro("__HEXAGON_V81__"); + Builder.defineMacro("__HEXAGON_ARCH__", "81"); } if (hasFeature("hvx-length64b")) { @@ -252,8 +255,7 @@ static constexpr CPUSuffix Suffixes[] = { {{"hexagonv68"}, {"68"}}, {{"hexagonv69"}, {"69"}}, {{"hexagonv71"}, {"71"}}, {{"hexagonv71t"}, {"71t"}}, {{"hexagonv73"}, {"73"}}, {{"hexagonv75"}, {"75"}}, - {{"hexagonv79"}, {"79"}}, -}; + {{"hexagonv79"}, {"79"}}, {{"hexagonv81"}, {"81"}}}; std::optional<unsigned> HexagonTargetInfo::getHexagonCPURev(StringRef Name) { StringRef Arch = Name; diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h index 9f3a4cd..846b240 100644 --- a/clang/lib/Basic/Targets/PPC.h +++ b/clang/lib/Basic/Targets/PPC.h @@ -122,41 +122,41 @@ public: .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) .Case("a2", ArchDefineA2) - .Cases("power3", "pwr3", ArchDefinePpcgr) - .Cases("power4", "pwr4", + .Cases({"power3", "pwr3"}, ArchDefinePpcgr) + .Cases({"power4", "pwr4"}, ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) .Cases("power5", "pwr5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) - .Cases("power5x", "pwr5x", + .Cases({"power5x", "pwr5x"}, ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) - .Cases("power6", "pwr6", - ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | - ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) - .Cases("power6x", "pwr6x", + .Cases({"power6", "pwr6"}, ArchDefinePwr6 | ArchDefinePwr5x | + ArchDefinePwr5 | ArchDefinePwr4 | + ArchDefinePpcgr | ArchDefinePpcsq) + .Cases({"power6x", "pwr6x"}, ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) - .Cases("power7", "pwr7", - ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | - ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | - ArchDefinePpcsq) + .Cases({"power7", "pwr7"}, ArchDefinePwr7 | ArchDefinePwr6 | + ArchDefinePwr5x | ArchDefinePwr5 | + ArchDefinePwr4 | ArchDefinePpcgr | + ArchDefinePpcsq) // powerpc64le automatically defaults to at least power8. - .Cases("power8", "pwr8", "ppc64le", + .Cases({"power8", "pwr8", "ppc64le"}, ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) - .Cases("power9", "pwr9", + .Cases({"power9", "pwr9"}, ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) - .Cases("power10", "pwr10", + .Cases({"power10", "pwr10"}, ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) - .Cases("power11", "pwr11", + .Cases({"power11", "pwr11"}, ArchDefinePwr11 | ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | |