diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIDefines.h | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/MC/AMDGPU/gfx1250_asm_operands.s | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_operands.txt | 3 |
4 files changed, 9 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h index 2d0102f..3aaf670 100644 --- a/llvm/lib/Target/AMDGPU/SIDefines.h +++ b/llvm/lib/Target/AMDGPU/SIDefines.h @@ -513,6 +513,7 @@ enum Id { // HwRegCode, (6) [5:0] ID_HW_ID2 = 24, ID_POPS_PACKER = 25, ID_PERF_SNAPSHOT_DATA_gfx11 = 27, + ID_IB_STS2 = 28, ID_SHADER_CYCLES = 29, ID_SHADER_CYCLES_HI = 30, ID_DVGPR_ALLOC_LO = 31, diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp index 3d9455f..363ee23 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp @@ -195,7 +195,7 @@ static constexpr CustomOperand Operands[] = { {{"HW_REG_POPS_PACKER"}, ID_POPS_PACKER, isGFX10}, {{""}}, {{"HW_REG_PERF_SNAPSHOT_DATA"}, ID_PERF_SNAPSHOT_DATA_gfx11, isGFX11}, - {{""}}, + {{"HW_REG_IB_STS2"}, ID_IB_STS2, isGFX1250}, {{"HW_REG_SHADER_CYCLES"}, ID_SHADER_CYCLES, isGFX10_3_GFX11}, {{"HW_REG_SHADER_CYCLES_HI"}, ID_SHADER_CYCLES_HI, isGFX12Plus}, {{"HW_REG_DVGPR_ALLOC_LO"}, ID_DVGPR_ALLOC_LO, isGFX12Plus}, diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_operands.s b/llvm/test/MC/AMDGPU/gfx1250_asm_operands.s index 100fc98..91b3fcb 100644 --- a/llvm/test/MC/AMDGPU/gfx1250_asm_operands.s +++ b/llvm/test/MC/AMDGPU/gfx1250_asm_operands.s @@ -52,3 +52,7 @@ s_setreg_b32 hwreg(34), s1 s_setreg_b32 hwreg(HW_REG_XNACK_MASK), s1 // GFX1200-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid hardware register: not supported on this GPU // GFX1250: encoding: [0x22,0xf8,0x01,0xb9] + +s_setreg_b32 hwreg(HW_REG_IB_STS2), s1 +// GFX1200-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid hardware register: not supported on this GPU +// GFX1250: encoding: [0x1c,0xf8,0x01,0xb9] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_operands.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_operands.txt index d72009b..361c49b 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_operands.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_operands.txt @@ -32,3 +32,6 @@ # GFX1250: s_setreg_b32 hwreg(HW_REG_XNACK_MASK), s1 ; encoding: [0x22,0xf8,0x01,0xb9] 0x22,0xf8,0x01,0xb9 + +# GFX1250: s_setreg_b32 hwreg(HW_REG_IB_STS2), s1 ; encoding: [0x1c,0xf8,0x01,0xb9] +0x1c,0xf8,0x01,0xb9 |