diff options
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVSubtarget.h | 5 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/bfloat.ll | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/half-convert.ll | 14 |
4 files changed, 9 insertions, 19 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index e853251..f701022 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -15988,9 +15988,9 @@ Register RISCVTargetLowering::getExceptionSelectorRegister( bool RISCVTargetLowering::shouldExtendTypeInLibCall(EVT Type) const { // Return false to suppress the unnecessary extensions if the LibCall - // arguments or return value is f32 type for LP64 ABI. - RISCVABI::ABI ABI = Subtarget.getTargetABI(); - if (ABI == RISCVABI::ABI_LP64 && (Type == MVT::f32)) + // arguments or return value is a float narrower than XLEN on a soft FP ABI. + if (Subtarget.isSoftFPABI() && (Type.isFloatingPoint() && !Type.isVector() && + Type.getSizeInBits() < Subtarget.getXLen())) return false; return true; diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index 4b72062..55cfeb9 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -152,6 +152,11 @@ public: return VLen == 0 ? 65536 : VLen; } RISCVABI::ABI getTargetABI() const { return TargetABI; } + bool isSoftFPABI() const { + return TargetABI == RISCVABI::ABI_LP64 || + TargetABI == RISCVABI::ABI_ILP32 || + TargetABI == RISCVABI::ABI_ILP32E; + } bool isRegisterReservedByUser(Register i) const { assert(i < RISCV::NUM_TARGET_REGS && "Register out of range"); return UserReservedRegister[i]; diff --git a/llvm/test/CodeGen/RISCV/bfloat.ll b/llvm/test/CodeGen/RISCV/bfloat.ll index ae05425..4589e79 100644 --- a/llvm/test/CodeGen/RISCV/bfloat.ll +++ b/llvm/test/CodeGen/RISCV/bfloat.ll @@ -77,8 +77,7 @@ define double @bfloat_to_double(bfloat %a) nounwind { ; RV64I-LP64: # %bb.0: ; RV64I-LP64-NEXT: addi sp, sp, -16 ; RV64I-LP64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-LP64-NEXT: slli a0, a0, 48 -; RV64I-LP64-NEXT: srli a0, a0, 32 +; RV64I-LP64-NEXT: slliw a0, a0, 16 ; RV64I-LP64-NEXT: call __extendsfdf2@plt ; RV64I-LP64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-LP64-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll index 4135d02..197dc30 100644 --- a/llvm/test/CodeGen/RISCV/half-convert.ll +++ b/llvm/test/CodeGen/RISCV/half-convert.ll @@ -1828,8 +1828,6 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: slli a0, a0, 16 -; RV32I-NEXT: srli a0, a0, 16 ; RV32I-NEXT: call __extendhfsf2@plt ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lui a1, 913408 @@ -2393,8 +2391,6 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind { ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill -; RV32I-NEXT: slli a0, a0, 16 -; RV32I-NEXT: srli a0, a0, 16 ; RV32I-NEXT: call __extendhfsf2@plt ; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: lui a1, 391168 @@ -3748,8 +3744,6 @@ define float @fcvt_s_h(half %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: slli a0, a0, 16 -; RV32I-NEXT: srli a0, a0, 16 ; RV32I-NEXT: call __extendhfsf2@plt ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -3759,8 +3753,6 @@ define float @fcvt_s_h(half %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: slli a0, a0, 48 -; RV64I-NEXT: srli a0, a0, 48 ; RV64I-NEXT: call __extendhfsf2@plt ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -4016,8 +4008,6 @@ define double @fcvt_d_h(half %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: slli a0, a0, 16 -; RV32I-NEXT: srli a0, a0, 16 ; RV32I-NEXT: call __extendhfsf2@plt ; RV32I-NEXT: call __extendsfdf2@plt ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -4028,11 +4018,7 @@ define double @fcvt_d_h(half %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: slli a0, a0, 48 -; RV64I-NEXT: srli a0, a0, 48 ; RV64I-NEXT: call __extendhfsf2@plt -; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: call __extendsfdf2@plt ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 |