diff options
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index d46a08a..8f95a86 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -19087,7 +19087,7 @@ static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1, State.getMachineFunction().getSubtarget<RISCVSubtarget>(); ArrayRef<MCPhysReg> ArgGPRs = RISCV::getArgGPRs(STI.getTargetABI()); - if (Register Reg = State.AllocateReg(ArgGPRs)) { + if (MCRegister Reg = State.AllocateReg(ArgGPRs)) { // At least one half can be passed via register. State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg, VA1.getLocVT(), CCValAssign::Full)); @@ -19108,7 +19108,7 @@ static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1, return false; } - if (Register Reg = State.AllocateReg(ArgGPRs)) { + if (MCRegister Reg = State.AllocateReg(ArgGPRs)) { // The second half can also be passed via register. State.addLoc( CCValAssign::getReg(ValNo2, ValVT2, Reg, LocVT2, CCValAssign::Full)); @@ -19230,7 +19230,7 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, if (UseGPRForF16_F32 && (ValVT == MVT::f16 || ValVT == MVT::bf16 || (ValVT == MVT::f32 && XLen == 64))) { - Register Reg = State.AllocateReg(ArgGPRs); + MCRegister Reg = State.AllocateReg(ArgGPRs); if (Reg) { LocVT = XLenVT; State.addLoc( @@ -19283,7 +19283,7 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, // GPRs, split between a GPR and the stack, or passed completely on the // stack. LowerCall/LowerFormalArguments/LowerReturn must recognise these // cases. - Register Reg = State.AllocateReg(ArgGPRs); + MCRegister Reg = State.AllocateReg(ArgGPRs); if (!Reg) { unsigned StackOffset = State.AllocateStack(8, Align(8)); State.addLoc( @@ -19292,7 +19292,7 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, } LocVT = MVT::i32; State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); - Register HiReg = State.AllocateReg(ArgGPRs); + MCRegister HiReg = State.AllocateReg(ArgGPRs); if (HiReg) { State.addLoc( CCValAssign::getCustomReg(ValNo, ValVT, HiReg, LocVT, LocInfo)); @@ -19340,7 +19340,7 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, } // Allocate to a register if possible, or else a stack slot. - Register Reg; + MCRegister Reg; unsigned StoreSizeBytes = XLen / 8; Align StackAlign = Align(XLen / 8); |