diff options
| -rw-r--r-- | llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVGISel.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVMoveMerger.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVPushPopOptimizer.cpp | 2 |
7 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp index 708ebd7..1bb1297 100644 --- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp +++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp @@ -223,7 +223,7 @@ unsigned RISCVInstrumentManager::getSchedClassID( unsigned short Opcode = MCI.getOpcode(); unsigned SchedClassID = MCII.get(Opcode).getSchedClass(); - // Unpack all possible RISCV instruments from IVec. + // Unpack all possible RISC-V instruments from IVec. RISCVLMULInstrument *LI = nullptr; RISCVSEWInstrument *SI = nullptr; for (auto &I : IVec) { diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp index 765d44c..731c644 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp @@ -1,4 +1,4 @@ -//===-- RISCVAsmBackend.cpp - RISCV Assembler Backend ---------------------===// +//===-- RISCVAsmBackend.cpp - RISC-V Assembler Backend --------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h index f3d0841..74bd939 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h @@ -1,4 +1,4 @@ -//===-- RISCVFixupKinds.h - RISCV Specific Fixup Entries --------*- C++ -*-===// +//===-- RISCVFixupKinds.h - RISC-V Specific Fixup Entries -------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td index 56910c9..8d0d088 100644 --- a/llvm/lib/Target/RISCV/RISCVGISel.td +++ b/llvm/lib/Target/RISCV/RISCVGISel.td @@ -1,4 +1,4 @@ -//===-- RISCVGIsel.td - RISCV GlobalISel Patterns ----------*- tablegen -*-===// +//===-- RISCVGIsel.td - RISC-V GlobalISel Patterns ---------*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index b5b69cf..af52e01c 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -5232,7 +5232,7 @@ static SDValue lowerFMAXIMUM_FMINIMUM(SDValue Op, SelectionDAG &DAG, return Res; } -/// Get a RISCV target specified VL op for a given SDNode. +/// Get a RISC-V target specified VL op for a given SDNode. static unsigned getRISCVVLOp(SDValue Op) { #define OP_CASE(NODE) \ case ISD::NODE: \ diff --git a/llvm/lib/Target/RISCV/RISCVMoveMerger.cpp b/llvm/lib/Target/RISCV/RISCVMoveMerger.cpp index 6c1b0cf..934a2a0 100644 --- a/llvm/lib/Target/RISCV/RISCVMoveMerger.cpp +++ b/llvm/lib/Target/RISCV/RISCVMoveMerger.cpp @@ -1,4 +1,4 @@ -//===-- RISCVMoveMerger.cpp - RISCV move merge pass -----------------------===// +//===-- RISCVMoveMerger.cpp - RISC-V move merge pass ----------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/llvm/lib/Target/RISCV/RISCVPushPopOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVPushPopOptimizer.cpp index 5e8a4a3..c2c795ec 100644 --- a/llvm/lib/Target/RISCV/RISCVPushPopOptimizer.cpp +++ b/llvm/lib/Target/RISCV/RISCVPushPopOptimizer.cpp @@ -1,4 +1,4 @@ -//===------- RISCVPushPopOptimizer.cpp - RISCV Push/Pop opt. pass ---------===// +//===------- RISCVPushPopOptimizer.cpp - RISC-V Push/Pop opt. pass --------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. |
