diff options
| -rw-r--r-- | lld/test/ELF/riscv-relax-align.s | 10 | ||||
| -rw-r--r-- | lld/test/ELF/riscv-relax-emit-relocs.s | 4 | ||||
| -rw-r--r-- | llvm/include/llvm/MC/MCSection.h | 13 | ||||
| -rw-r--r-- | llvm/lib/MC/MCObjectStreamer.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/MC/MCSection.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 30 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/Relocations/align-after-relax.s | 50 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/Relocations/align-norvc.s | 23 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/Relocations/mc-dump.s | 8 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/align-option-relax.s | 23 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/align.s | 45 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/cfi-advance.s | 28 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/nop-slide.s | 16 |
14 files changed, 172 insertions, 85 deletions
diff --git a/lld/test/ELF/riscv-relax-align.s b/lld/test/ELF/riscv-relax-align.s index 3efc774f..b3db2c94 100644 --- a/lld/test/ELF/riscv-relax-align.s +++ b/lld/test/ELF/riscv-relax-align.s @@ -10,7 +10,7 @@ # RUN: ld.lld -Ttext=0x10000 --no-relax 32.o -o 32.norelax # RUN: llvm-objdump -td --no-show-raw-insn -M no-aliases 32.norelax | FileCheck %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax %s -o 64.o +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax %s -riscv-align-rvc=0 -o 64.o # RUN: ld.lld -Ttext=0x10000 64.o -o 64 # RUN: llvm-objdump -td --no-show-raw-insn -M no-aliases 64 | FileCheck %s # RUN: ld.lld -Ttext=0x10000 --no-relax 64.o -o 64.norelax @@ -29,7 +29,7 @@ # CHECK-DAG: 00010000 g .text {{0*}}38 _start # CHECK: <_start>: -# CHECK-NEXT: addi a0, a0, 0x1 +# CHECK-NEXT: lui a0, 0x10 # CHECK-EMPTY: # CHECK-NEXT: <a>: # CHECK-NEXT: addi a0, a0, 0x2 @@ -82,7 +82,9 @@ # GC-NOT: <d>: # CHECKR: <_start>: -# CHECKR-NEXT: addi a0, a0, 0x1 +# CHECKR-NEXT: lui a0, 0x0 +# CHECKR-NEXT: 0000000000000000: R_RISCV_HI20 _start +# CHECKR-NEXT: 0000000000000000: R_RISCV_RELAX *ABS* # CHECKR-EMPTY: # CHECKR-NEXT: <a>: # CHECKR-NEXT: addi a0, a0, 0x2 @@ -116,7 +118,7 @@ .global _start _start: - addi a0, a0, 0x1 + lui a0, %hi(_start) a: addi a0, a0, 0x2 b: diff --git a/lld/test/ELF/riscv-relax-emit-relocs.s b/lld/test/ELF/riscv-relax-emit-relocs.s index 26ea0d1..358a288 100644 --- a/lld/test/ELF/riscv-relax-emit-relocs.s +++ b/lld/test/ELF/riscv-relax-emit-relocs.s @@ -3,11 +3,11 @@ # RUN: rm -rf %t && mkdir %t && cd %t -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+relax %s -o 32.o +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+relax %s -o 32.o -riscv-align-rvc=0 # RUN: ld.lld -Ttext=0x10000 --emit-relocs 32.o -o 32 # RUN: llvm-objdump -dr --no-show-raw-insn -M no-aliases 32 | FileCheck %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax %s -o 64.o +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax %s -o 64.o -riscv-align-rvc=0 # RUN: ld.lld -Ttext=0x10000 --emit-relocs 64.o -o 64 # RUN: llvm-objdump -dr --no-show-raw-insn -M no-aliases 64 | FileCheck %s diff --git a/llvm/include/llvm/MC/MCSection.h b/llvm/include/llvm/MC/MCSection.h index e976f47..a1762fc 100644 --- a/llvm/include/llvm/MC/MCSection.h +++ b/llvm/include/llvm/MC/MCSection.h @@ -534,6 +534,10 @@ private: Align Alignment; /// The section index in the assemblers section list. unsigned Ordinal = 0; + // If not -1u, the first linker-relaxable fragment's order within the + // subsection. When present, the offset between two locations crossing this + // fragment may not be fully resolved. + unsigned FirstLinkerRelaxable = -1u; /// Whether this section has had instructions emitted into it. bool HasInstructions : 1; @@ -543,10 +547,6 @@ private: bool IsText : 1; bool IsBss : 1; - /// Whether the section contains linker-relaxable fragments. If true, the - /// offset between two locations may not be fully resolved. - bool LinkerRelaxable : 1; - MCFragment DummyFragment; // Mapping from subsection number to fragment list. At layout time, the @@ -601,8 +601,9 @@ public: bool isRegistered() const { return IsRegistered; } void setIsRegistered(bool Value) { IsRegistered = Value; } - bool isLinkerRelaxable() const { return LinkerRelaxable; } - void setLinkerRelaxable() { LinkerRelaxable = true; } + unsigned firstLinkerRelaxable() const { return FirstLinkerRelaxable; } + bool isLinkerRelaxable() const { return FirstLinkerRelaxable != -1u; } + void setFirstLinkerRelaxable(unsigned Order) { FirstLinkerRelaxable = Order; } MCFragment &getDummyFragment() { return DummyFragment; } diff --git a/llvm/lib/MC/MCObjectStreamer.cpp b/llvm/lib/MC/MCObjectStreamer.cpp index 8c27958..d0c6144 100644 --- a/llvm/lib/MC/MCObjectStreamer.cpp +++ b/llvm/lib/MC/MCObjectStreamer.cpp @@ -443,7 +443,7 @@ void MCObjectStreamer::emitInstToData(const MCInst &Inst, // MCAssembler::relaxAlign. auto *Sec = F->getParent(); if (!Sec->isLinkerRelaxable()) - Sec->setLinkerRelaxable(); + Sec->setFirstLinkerRelaxable(F->getLayoutOrder()); // Do not add data after a linker-relaxable instruction. The difference // between a new label and a label at or before the linker-relaxable // instruction cannot be resolved at assemble-time. diff --git a/llvm/lib/MC/MCSection.cpp b/llvm/lib/MC/MCSection.cpp index 27ca131..9ed6fd1 100644 --- a/llvm/lib/MC/MCSection.cpp +++ b/llvm/lib/MC/MCSection.cpp @@ -20,7 +20,7 @@ using namespace llvm; MCSection::MCSection(StringRef Name, bool IsText, bool IsBss, MCSymbol *Begin) : Begin(Begin), HasInstructions(false), IsRegistered(false), IsText(IsText), - IsBss(IsBss), LinkerRelaxable(false), Name(Name) { + IsBss(IsBss), Name(Name) { DummyFragment.setParent(this); } diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp index fda9d97..ca5d27d 100644 --- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp +++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp @@ -254,7 +254,8 @@ bool LoongArchAsmBackend::relaxAlign(MCFragment &F, unsigned &Size) { MCFixup::create(0, Expr, FirstLiteralRelocationKind + ELF::R_LARCH_ALIGN); F.setVarFixups({Fixup}); F.setLinkerRelaxable(); - F.getParent()->setLinkerRelaxable(); + if (!F.getParent()->isLinkerRelaxable()) + F.getParent()->setFirstLinkerRelaxable(F.getLayoutOrder()); return true; } diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp index a997ea5..8d956ce 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp @@ -32,6 +32,11 @@ static cl::opt<bool> ULEB128Reloc( "riscv-uleb128-reloc", cl::init(true), cl::Hidden, cl::desc("Emit R_RISCV_SET_ULEB128/E_RISCV_SUB_ULEB128 if appropriate")); +static cl::opt<bool> + AlignRvc("riscv-align-rvc", cl::init(true), cl::Hidden, + cl::desc("When generating R_RISCV_ALIGN, insert $alignment-2 " + "bytes of NOPs even in norvc code")); + RISCVAsmBackend::RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit, const MCTargetOptions &Options) : MCAsmBackend(llvm::endianness::little), STI(STI), OSABI(OSABI), @@ -306,12 +311,21 @@ void RISCVAsmBackend::relaxInstruction(MCInst &Inst, // If conditions are met, compute the padding size and create a fixup encoding // the padding size in the addend. bool RISCVAsmBackend::relaxAlign(MCFragment &F, unsigned &Size) { - // Use default handling unless linker relaxation is enabled and the alignment - // is larger than the nop size. - const MCSubtargetInfo *STI = F.getSubtargetInfo(); - if (!STI->hasFeature(RISCV::FeatureRelax)) + // Alignments before the first linker-relaxable instruction have fixed sizes + // and do not require relocations. Alignments after a linker-relaxable + // instruction require a relocation, even if the STI specifies norelax. + // + // firstLinkerRelaxable is the layout order within the subsection, which may + // be smaller than the section's order. Therefore, alignments in a + // lower-numbered subsection may be unnecessarily treated as linker-relaxable. + auto *Sec = F.getParent(); + if (F.getLayoutOrder() <= Sec->firstLinkerRelaxable()) return false; - unsigned MinNopLen = STI->hasFeature(RISCV::FeatureStdExtZca) ? 2 : 4; + + // Use default handling unless the alignment is larger than the nop size. + const MCSubtargetInfo *STI = F.getSubtargetInfo(); + unsigned MinNopLen = + AlignRvc || STI->hasFeature(RISCV::FeatureStdExtZca) ? 2 : 4; if (F.getAlignment() <= MinNopLen) return false; @@ -321,7 +335,6 @@ bool RISCVAsmBackend::relaxAlign(MCFragment &F, unsigned &Size) { MCFixup::create(0, Expr, FirstLiteralRelocationKind + ELF::R_RISCV_ALIGN); F.setVarFixups({Fixup}); F.setLinkerRelaxable(); - F.getParent()->setLinkerRelaxable(); return true; } @@ -474,8 +487,9 @@ bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count, // TODO: emit a mapping symbol right here if (Count % 4 == 2) { - // The canonical nop with Zca is c.nop. - OS.write(STI->hasFeature(RISCV::FeatureStdExtZca) ? "\x01\0" : "\0\0", 2); + // The canonical nop with Zca is c.nop. For .balign 4, we generate a 2-byte + // c.nop even in a norvc region. + OS.write("\x01\0", 2); Count -= 2; } diff --git a/llvm/test/MC/RISCV/Relocations/align-after-relax.s b/llvm/test/MC/RISCV/Relocations/align-after-relax.s new file mode 100644 index 0000000..95bef51 --- /dev/null +++ b/llvm/test/MC/RISCV/Relocations/align-after-relax.s @@ -0,0 +1,50 @@ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+relax %s --defsym LATE=1 -o %t1 +# RUN: llvm-objdump -dr --no-show-raw-insn -M no-aliases %t1 | FileCheck %s + +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+relax %s -o %t0 +# RUN: llvm-objdump -dr --no-show-raw-insn -M no-aliases %t0 | FileCheck %s --check-prefix=CHECK0 + +# CHECK: 4: 00 00 01 00 .word 0x00010000 +# CHECK-EMPTY: +# CHECK: 8: 78 56 34 12 .word 0x12345678 +# CHECK-NEXT: c: 00 00 00 00 .word 0x00000000 +# CHECK: 10: auipc ra, 0x0 +# CHECK-NEXT: R_RISCV_CALL_PLT foo +# CHECK-NEXT: R_RISCV_RELAX *ABS* +# CHECK: 18: c.nop +# CHECK-NEXT: R_RISCV_ALIGN *ABS*+0x6 + +## Alignment directives in a lower-numbered subsection may be conservatively treated as linker-relaxable. +# CHECK0: 4: 00 00 01 00 .word 0x00010000 +# CHECK0-NEXT: 000000006: R_RISCV_ALIGN *ABS*+0x6 +# CHECK0-NEXT: 8: 13 00 00 00 .word 0x00000013 +# CHECK0: 14: auipc ra, 0x0 +# CHECK0: 1c: c.nop +# CHECK0-NEXT: R_RISCV_ALIGN *ABS*+0x6 + +.text 2 +.option push +.option norelax +## R_RISCV_ALIGN is required even if norelax, because it is after a linker-relaxable instruction. +.balign 8 +l2: + .word 0x12345678 +.option pop + +.text 1 + .org .+1 + .org .+3 +.ifdef LATE + .org .+0 +.endif + call foo + +.text 0 +_start: + .space 6 +.option push +.option norelax +.balign 8 +l0: + .word 0x12345678 +.option pop diff --git a/llvm/test/MC/RISCV/Relocations/align-norvc.s b/llvm/test/MC/RISCV/Relocations/align-norvc.s new file mode 100644 index 0000000..c3fe71e --- /dev/null +++ b/llvm/test/MC/RISCV/Relocations/align-norvc.s @@ -0,0 +1,23 @@ +## To ensure ALIGN relocations in norvc code can adapt to shrinking of preceding rvc code, +## we generate $alignment-2 bytes of NOPs regardless of rvc. +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax %s -o %t +# RUN: llvm-objdump -dr -M no-aliases %t | FileCheck %s + +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax -riscv-align-rvc=0 %s -o %t0 +# RUN: llvm-objdump -dr -M no-aliases %t0 | FileCheck %s --check-prefix=CHECK0 + +# CHECK: 00000000: R_RISCV_RELAX *ABS* +# CHECK-NEXT: 4: 0001 <unknown> +# CHECK-NEXT: 00000004: R_RISCV_ALIGN *ABS*+0x6 +# CHECK-NEXT: 6: 00000013 addi zero, zero, 0x0 +# CHECK-NEXT: a: 00000537 lui a0, 0x0 + +# CHECK0: 00000000: R_RISCV_RELAX *ABS* +# CHECK0-NEXT: 4: 00000013 addi zero, zero, 0x0 +# CHECK0-NEXT: 00000004: R_RISCV_ALIGN *ABS*+0x4 +# CHECK0-NEXT: 8: 00000537 lui a0, 0x0 + + lui a0, %hi(foo) + .option norvc +.balign 8 + lui a0, %hi(foo) diff --git a/llvm/test/MC/RISCV/Relocations/mc-dump.s b/llvm/test/MC/RISCV/Relocations/mc-dump.s index ddc0c7d..99d34b5 100644 --- a/llvm/test/MC/RISCV/Relocations/mc-dump.s +++ b/llvm/test/MC/RISCV/Relocations/mc-dump.s @@ -9,12 +9,12 @@ # CHECK-NEXT:0 Data LinkerRelaxable Size:8 [97,00,00,00,e7,80,00,00] # CHECK-NEXT: Fixup @0 Value:specifier(19,ext) Kind:4023 # CHECK-NEXT: Symbol @0 $x -# CHECK-NEXT:8 Align LinkerRelaxable Size:0+4 [] +# CHECK-NEXT:8 Align LinkerRelaxable Size:0+6 [] # CHECK-NEXT: Align:8 Fill:0 FillLen:1 MaxBytesToEmit:8 Nops -# CHECK-NEXT: Fixup @0 Value:4 Kind:[[#]] -# CHECK-NEXT:12 Align LinkerRelaxable Size:4+4 [13,05,30,00] +# CHECK-NEXT: Fixup @0 Value:6 Kind:[[#]] +# CHECK-NEXT:14 Align LinkerRelaxable Size:4+6 [13,05,30,00] # CHECK-NEXT: Align:8 Fill:0 FillLen:1 MaxBytesToEmit:8 Nops -# CHECK-NEXT: Fixup @4 Value:4 Kind:[[#]] +# CHECK-NEXT: Fixup @4 Value:6 Kind:[[#]] # CHECK-NEXT:] call ext diff --git a/llvm/test/MC/RISCV/align-option-relax.s b/llvm/test/MC/RISCV/align-option-relax.s index 890e1e7..60cd55f 100644 --- a/llvm/test/MC/RISCV/align-option-relax.s +++ b/llvm/test/MC/RISCV/align-option-relax.s @@ -1,8 +1,21 @@ # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-relax < %s \ # RUN: | llvm-readobj -r - | FileCheck %s -# Check that .option relax overrides -mno-relax and enables R_RISCV_ALIGN -# relocations. -# CHECK: R_RISCV_ALIGN - .option relax - .align 4 +## .option relax overrides -mno-relax and enables R_RISCV_ALIGN/R_RISCV_RELAX relocations. +# CHECK: .rela.text +# CHECK: R_RISCV_CALL_PLT +# CHECK-NEXT: R_RISCV_RELAX +# CHECK-NEXT: R_RISCV_ALIGN +.option relax +call foo +.align 4 + +## Alignments before the first linker-relaxable instruction do not need relocations. +# CHECK-NOT: .rela.text1 +.section .text1,"ax" +.align 4 +nop + +# CHECK: .rela.text2 +.section .text2,"ax" +call foo diff --git a/llvm/test/MC/RISCV/align.s b/llvm/test/MC/RISCV/align.s index da3b1aa..4d4d998 100644 --- a/llvm/test/MC/RISCV/align.s +++ b/llvm/test/MC/RISCV/align.s @@ -46,20 +46,21 @@ # type for .align N directive when linker relaxation enabled. # Linker could satisfy alignment by removing NOPs after linker relaxation. -# The first R_RISCV_ALIGN come from -# MCELFStreamer::InitSections() emitCodeAlignment(getTextSectionAligntment()). -# C-OR-ZCA-EXT-RELAX-RELOC: R_RISCV_ALIGN - 0x2 -# C-OR-ZCA-EXT-RELAX-INST: c.nop test: +## Start with a linker-relaxable instruction so that the following alignment can be relaxable. + call foo +# NORELAX-RELOC: R_RISCV_CALL_PLT +# C-OR-ZCA-EXT-NORELAX-RELOC: R_RISCV_CALL_PLT + .p2align 2 # If the +c extension is enabled, the text section will be 2-byte aligned, so # one c.nop instruction is sufficient. -# C-OR-ZCA-EXT-RELAX-RELOC-NOT: R_RISCV_ALIGN - 0x2 -# C-OR-ZCA-EXT-RELAX-INST-NOT: c.nop +# C-OR-ZCA-EXT-RELAX-RELOC: R_RISCV_ALIGN - 0x2 +# C-OR-ZCA-EXT-RELAX-INST: c.nop bne zero, a0, .LBB0_2 mv a0, zero .p2align 3 -# RELAX-RELOC: R_RISCV_ALIGN - 0x4 +# RELAX-RELOC: R_RISCV_ALIGN - 0x6 # RELAX-INST: addi zero, zero, 0 # C-OR-ZCA-EXT-RELAX-RELOC: R_RISCV_ALIGN - 0x6 # C-OR-ZCA-EXT-RELAX-INST: c.nop @@ -68,7 +69,7 @@ test: add a0, a0, a1 .align 4 .LBB0_2: -# RELAX-RELOC: R_RISCV_ALIGN - 0xC +# RELAX-RELOC: R_RISCV_ALIGN - 0xE # RELAX-INST: addi zero, zero, 0 # RELAX-INST: addi zero, zero, 0 # RELAX-INST: addi zero, zero, 0 @@ -84,7 +85,7 @@ test: .p2align 3 .constant_pool: .long 3126770193 -# RELAX-RELOC: R_RISCV_ALIGN - 0x4 +# RELAX-RELOC: R_RISCV_ALIGN - 0x6 # RELAX-INST: addi zero, zero, 0 # NORELAX-INST: addi zero, zero, 0 # C-OR-ZCA-EXT-RELAX-RELOC: R_RISCV_ALIGN - 0x6 @@ -136,16 +137,8 @@ data2: add a0, a0, a1 ## Branches crossing the linker-relaxable R_RISCV_ALIGN need relocations. -# RELAX-RELOC: .rela.text3 { -# RELAX-RELOC-NEXT: 0x4 R_RISCV_BRANCH .Ltmp[[#]] 0x0 -# RELAX-RELOC-NEXT: 0x8 R_RISCV_ALIGN - 0x4 -# RELAX-RELOC-NEXT: 0xC R_RISCV_BRANCH .Ltmp[[#]] 0x0 -# RELAX-RELOC-NEXT: } -# C-OR-ZCA-EXT-RELAX-RELOC: .rela.text3 { -# C-OR-ZCA-EXT-RELAX-RELOC-NEXT: 0x4 R_RISCV_BRANCH .Ltmp[[#]] 0x0 -# C-OR-ZCA-EXT-RELAX-RELOC-NEXT: 0x8 R_RISCV_ALIGN - 0x4 -# C-OR-ZCA-EXT-RELAX-RELOC-NEXT: 0xC R_RISCV_BRANCH .Ltmp[[#]] 0x0 -# C-OR-ZCA-EXT-RELAX-RELOC-NEXT: } +# RELAX-RELOC-NOT: .rela.text3 { +# C-OR-ZCA-EXT-RELAX-RELOC-NOT: .rela.text3 { .section .text3, "ax" bnez t1, 1f bnez t2, 2f @@ -157,14 +150,15 @@ data2: ## .text3 with a call at the start # NORELAX-RELOC: .rela.text3a -# C-OR-ZCA-EXT-NORELAX-RELOC: .rela.text3a # RELAX-RELOC: .rela.text3a { # RELAX-RELOC-NEXT: 0x0 R_RISCV_CALL_PLT foo 0x0 # RELAX-RELOC-NEXT: 0x0 R_RISCV_RELAX - 0x0 # RELAX-RELOC-NEXT: 0xC R_RISCV_BRANCH .Ltmp[[#]] 0x0 -# RELAX-RELOC-NEXT: 0x10 R_RISCV_ALIGN - 0x4 -# RELAX-RELOC-NEXT: 0x14 R_RISCV_BRANCH .Ltmp[[#]] 0x0 +# RELAX-RELOC-NEXT: 0x10 R_RISCV_ALIGN - 0x6 +# RELAX-RELOC-NEXT: 0x16 R_RISCV_BRANCH .Ltmp[[#]] 0x0 # RELAX-RELOC-NEXT: } +# C-OR-ZCA-EXT-NORELAX-RELOC: .rela.text3a +# C-OR-ZCA-EXT-RELAX-RELOC: .rela.text3a .section .text3a, "ax" call foo bnez t1, 1f @@ -177,11 +171,8 @@ bnez t1, 2b ## .text3 with a call at the end # RELAX-RELOC: .rela.text3b { -# RELAX-RELOC-NEXT: 0x4 R_RISCV_BRANCH .Ltmp[[#]] 0x0 -# RELAX-RELOC-NEXT: 0x8 R_RISCV_ALIGN - 0x4 -# RELAX-RELOC-NEXT: 0xC R_RISCV_BRANCH .Ltmp[[#]] 0x0 -# RELAX-RELOC-NEXT: 0x14 R_RISCV_CALL_PLT foo 0x0 -# RELAX-RELOC-NEXT: 0x14 R_RISCV_RELAX - 0x0 +# RELAX-RELOC-NEXT: 0x10 R_RISCV_CALL_PLT foo 0x0 +# RELAX-RELOC-NEXT: 0x10 R_RISCV_RELAX - 0x0 # RELAX-RELOC-NEXT: } .section .text3b, "ax" bnez t1, 1f diff --git a/llvm/test/MC/RISCV/cfi-advance.s b/llvm/test/MC/RISCV/cfi-advance.s index f3f8530..7643e01 100644 --- a/llvm/test/MC/RISCV/cfi-advance.s +++ b/llvm/test/MC/RISCV/cfi-advance.s @@ -7,7 +7,7 @@ # NORELAX: Relocation section '.rela.text1' at offset {{.*}} contains 1 entries: # NORELAX-NEXT: Offset Info Type Sym. Value Symbol's Name + Addend -# NORELAX-NEXT: 00000000 00000313 R_RISCV_CALL_PLT 00000004 .L0 + 0 +# NORELAX-NEXT: 00000000 00000313 R_RISCV_CALL_PLT 00000008 .L0 + 0 # NORELAX-EMPTY: # RELAX: Relocation section '.rela.text1' at offset {{.*}} contains 2 entries: # RELAX: R_RISCV_CALL_PLT @@ -16,23 +16,25 @@ # NORELAX-NEXT: Relocation section '.rela.eh_frame' at offset {{.*}} contains 1 entries: # NORELAX: Offset Info Type Sym. Value Symbol's Name + Addend # NORELAX-NEXT: 0000001c 00000139 R_RISCV_32_PCREL 00000000 .L0 + 0 -# RELAX-NEXT: Relocation section '.rela.eh_frame' at offset {{.*}} contains 5 entries: +# RELAX-NEXT: Relocation section '.rela.eh_frame' at offset {{.*}} contains 7 entries: # RELAX: Offset Info Type Sym. Value Symbol's Name + Addend # RELAX-NEXT: 0000001c 00000139 R_RISCV_32_PCREL 00000000 .L0 + 0 -# RELAX-NEXT: 00000020 00000c23 R_RISCV_ADD32 0001017a .L0 + 0 +# RELAX-NEXT: 00000020 00000d23 R_RISCV_ADD32 0001017c .L0 + 0 # RELAX-NEXT: 00000020 00000127 R_RISCV_SUB32 00000000 .L0 + 0 -# RELAX-NEXT: 00000035 00000b35 R_RISCV_SET6 00010176 .L0 + 0 -# RELAX-NEXT: 00000035 00000934 R_RISCV_SUB6 0001016e .L0 + 0 +# RELAX-NEXT: 00000026 00000536 R_RISCV_SET8 00000068 .L0 + 0 +# RELAX-NEXT: 00000026 00000125 R_RISCV_SUB8 00000000 .L0 + 0 +# RELAX-NEXT: 00000035 00000c35 R_RISCV_SET6 00010178 .L0 + 0 +# RELAX-NEXT: 00000035 00000a34 R_RISCV_SUB6 0001016e .L0 + 0 # CHECK-EMPTY: -# NORELAX: Symbol table '.symtab' contains 13 entries: -# RELAX: Symbol table '.symtab' contains 16 entries: +# NORELAX: Symbol table '.symtab' contains 14 entries: +# RELAX: Symbol table '.symtab' contains 18 entries: # RELAX-NEXT: Num: Value Size Type Bind Vis Ndx Name # RELAX-NEXT: 0: 00000000 0 NOTYPE LOCAL DEFAULT UND # RELAX-NEXT: 1: 00000000 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}} -# RELAX: 3: 00000004 0 NOTYPE LOCAL DEFAULT 2 .L0{{$}} -# RELAX: 9: 0001016e 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}} -# RELAX: 11: 00010176 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}} -# RELAX: 12: 0001017a 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}} +# RELAX: 3: 00000008 0 NOTYPE LOCAL DEFAULT 2 .L0{{$}} +# RELAX: 10: 0001016e 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}} +# RELAX: 12: 00010178 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}} +# RELAX: 13: 0001017c 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}} # CHECK-DWARFDUMP: DW_CFA_advance_loc1: 104 # CHECK-DWARFDUMP-NEXT: DW_CFA_def_cfa_offset: +8 @@ -48,11 +50,11 @@ .type test,@function test: .cfi_startproc - nop + call foo ## This looks similar to fake label names ".L0 ". Even if this is ".L0 ", ## the assembler will not conflate it with fake labels. .L0: - .zero 100, 0x90 + .zero 96, 0x90 .cfi_def_cfa_offset 8 nop .zero 255, 0x90 diff --git a/llvm/test/MC/RISCV/nop-slide.s b/llvm/test/MC/RISCV/nop-slide.s index a49ffdc..9e7401d 100644 --- a/llvm/test/MC/RISCV/nop-slide.s +++ b/llvm/test/MC/RISCV/nop-slide.s @@ -1,5 +1,5 @@ -# RUN: llvm-mc -triple riscv64 -mattr +c,-relax -filetype obj -o - %s | llvm-objdump -d - | FileCheck %s -check-prefix CHECK-RVC-NORELAX -# RUN: llvm-mc -triple riscv64 -mattr +c,+relax -filetype obj -o - %s | llvm-objdump -d - | FileCheck %s -check-prefix CHECK-RVC-RELAX +# RUN: llvm-mc -triple riscv64 -mattr +c,-relax -filetype obj -o - %s | llvm-objdump -d - | FileCheck %s +# RUN: llvm-mc -triple riscv64 -mattr +c,+relax -filetype obj -o - %s | llvm-objdump -d - | FileCheck %s # RUN: llvm-mc -triple riscv64 -mattr -c,-relax -filetype obj -o - %s | llvm-objdump -d - | FileCheck %s # RUN: llvm-mc -triple riscv64 -mattr -c,+relax -filetype obj -o - %s | llvm-objdump -d - | FileCheck %s @@ -9,16 +9,6 @@ .balign 4 auipc a0, 0 -# CHECK-RVC-NORELAX: 0000000000000000 <.text>: -# CHECK-RVC-NORELAX-NEXT: 0: 00 00 01 00 .word 0x00010000 -# CHECK-RVC-NORELAX-NEXT: 4: 00000517 auipc a0, 0x0 - -# CHECK-RVC-RELAX: 0000000000000000 <.text>: -# CHECK-RVC-RELAX-NEXT: 0: 0001 nop -# CHECK-RVC-RELAX-NEXT: 2: 00 01 .short 0x0100 -# CHECK-RVC-RELAX-NEXT: 4: 00 .byte 0x00 -# CHECK-RVC-RELAX-NEXT: 5: 00000517 auipc a0, 0x0 - # CHECK: 0000000000000000 <.text>: -# CHECK-NEXT: 0: 00 00 00 00 .word 0x00000000 +# CHECK-NEXT: 0: 00 00 01 00 .word 0x00010000 # CHECK-NEXT: 4: 00000517 auipc a0, 0x0 |