diff options
| -rw-r--r-- | llvm/include/llvm/Target/Target.td | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/valu-i1.ll | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td index 654a008..7c55442 100644 --- a/llvm/include/llvm/Target/Target.td +++ b/llvm/include/llvm/Target/Target.td @@ -773,7 +773,7 @@ class InstrInfo { let isCodeGenOnly = 1, isPseudo = 1, hasNoSchedulingInfo = 1, Namespace = "TargetOpcode" in { def PHI : Instruction { - let OutOperandList = (outs); + let OutOperandList = (outs unknown:$dst); let InOperandList = (ins variable_ops); let AsmString = "PHINODE"; } diff --git a/llvm/test/CodeGen/AMDGPU/valu-i1.ll b/llvm/test/CodeGen/AMDGPU/valu-i1.ll index 4c79dc48..ffa0110 100644 --- a/llvm/test/CodeGen/AMDGPU/valu-i1.ll +++ b/llvm/test/CodeGen/AMDGPU/valu-i1.ll @@ -138,11 +138,11 @@ exit: ; SI: BB#4: ; SI: buffer_store_dword ; SI: v_cmp_ge_i64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]] -; SI: s_or_b64 [[COND_STATE]], [[CMP]], [[COND_STATE]] +; SI: s_or_b64 [[TMP:s\[[0-9]+:[0-9]+\]]], [[CMP]], [[COND_STATE]] ; SI: BB3_5: ; SI: s_or_b64 exec, exec, [[ORNEG2]] -; SI: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[COND_STATE]] +; SI: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[TMP]] ; SI: s_andn2_b64 exec, exec, [[COND_STATE]] ; SI: s_cbranch_execnz BB3_3 |