diff options
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 11 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Thumb2/mve-blockplacement.ll | 10 |
3 files changed, 13 insertions, 16 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 11f8734..ffa9998 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -3631,15 +3631,6 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts, // All bits are zero except the low bit. Known.Zero.setBitsFrom(1); break; - case ISD::ADD: - case ISD::SUB: { - SDNodeFlags Flags = Op.getNode()->getFlags(); - Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); - Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1); - Known = KnownBits::computeForAddSub(Op.getOpcode() == ISD::ADD, - Flags.hasNoSignedWrap(), Known, Known2); - break; - } case ISD::USUBO: case ISD::SSUBO: case ISD::USUBO_CARRY: @@ -3653,6 +3644,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts, break; } [[fallthrough]]; + case ISD::SUB: case ISD::SUBC: { assert(Op.getResNo() == 0 && "We only compute knownbits for the difference here."); @@ -3680,6 +3672,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts, break; } [[fallthrough]]; + case ISD::ADD: case ISD::ADDC: case ISD::ADDE: { assert(Op.getResNo() == 0 && "We only compute knownbits for the sum here."); diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 58f6e2a..35197dc 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -2694,9 +2694,11 @@ bool TargetLowering::SimplifyDemandedBits( if (Op.getOpcode() == ISD::MUL) { Known = KnownBits::mul(KnownOp0, KnownOp1); } else { // Op.getOpcode() is either ISD::ADD or ISD::SUB. - Known = KnownBits::computeForAddSub(Op.getOpcode() == ISD::ADD, - Flags.hasNoSignedWrap(), KnownOp0, - KnownOp1); + // TODO: Update `computeForAddCarry` to handle the NSW flag as well so + // that `Flags.hasNoSignedWrap()` can be passed through here + // instead of false. + Known = KnownBits::computeForAddSub(Op.getOpcode() == ISD::ADD, false, + KnownOp0, KnownOp1); } break; } diff --git a/llvm/test/CodeGen/Thumb2/mve-blockplacement.ll b/llvm/test/CodeGen/Thumb2/mve-blockplacement.ll index 41fd74d..2d7126d 100644 --- a/llvm/test/CodeGen/Thumb2/mve-blockplacement.ll +++ b/llvm/test/CodeGen/Thumb2/mve-blockplacement.ll @@ -366,16 +366,18 @@ define i32 @d(i64 %e, i32 %f, i64 %g, i32 %h) { ; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill ; CHECK-NEXT: movs r1, #4 ; CHECK-NEXT: strd r2, r12, [sp, #4] @ 8-byte Folded Spill -; CHECK-NEXT: add.w r1, r1, r4, lsr #1 ; CHECK-NEXT: add.w r3, r3, r4, lsr #1 -; CHECK-NEXT: bic r7, r1, #3 +; CHECK-NEXT: add.w r1, r1, r4, lsr #1 +; CHECK-NEXT: movw r4, #65532 +; CHECK-NEXT: vdup.32 q6, r3 +; CHECK-NEXT: movt r4, #32767 +; CHECK-NEXT: and.w r7, r1, r4 ; CHECK-NEXT: adr r1, .LCPI1_0 +; CHECK-NEXT: vdup.32 q7, r3 ; CHECK-NEXT: vldrw.u32 q0, [r1] ; CHECK-NEXT: adr r1, .LCPI1_1 ; CHECK-NEXT: vldrw.u32 q5, [r1] -; CHECK-NEXT: vdup.32 q6, r3 ; CHECK-NEXT: vadd.i32 q4, q0, lr -; CHECK-NEXT: vdup.32 q7, r3 ; CHECK-NEXT: b .LBB1_4 ; CHECK-NEXT: .LBB1_2: @ %for.body6.preheader ; CHECK-NEXT: @ in Loop: Header=BB1_4 Depth=1 |