diff options
273 files changed, 40442 insertions, 8236 deletions
diff --git a/.ci/all_requirements.txt b/.ci/all_requirements.txt index 313ab107..ac9682a 100644 --- a/.ci/all_requirements.txt +++ b/.ci/all_requirements.txt @@ -194,6 +194,10 @@ ml-dtypes==0.5.1 ; python_version < "3.13" \ --hash=sha256:d13755f8e8445b3870114e5b6240facaa7cb0c3361e54beba3e07fa912a6e12b \ --hash=sha256:fd918d4e6a4e0c110e2e05be7a7814d10dc1b95872accbf6512b80a109b71ae1 # via -r mlir/python/requirements.txt +nanobind==2.9.2 \ + --hash=sha256:c37957ffd5eac7eda349cff3622ecd32e5ee1244ecc912c99b5bc8188bafd16e \ + --hash=sha256:e7608472de99d375759814cab3e2c94aba3f9ec80e62cfef8ced495ca5c27d6e + # via -r mlir/python/requirements.txt numpy==2.0.2 \ --hash=sha256:0123ffdaa88fa4ab64835dcbde75dcdf89c453c922f18dced6e27c90d1d0ec5a \ --hash=sha256:11a76c372d1d37437857280aa142086476136a8c0f373b2e648ab2c8f18fb195 \ @@ -295,6 +299,10 @@ pyasn1-modules==0.4.2 \ --hash=sha256:29253a9207ce32b64c3ac6600edc75368f98473906e8fd1043bd6b5b1de2c14a \ --hash=sha256:677091de870a80aae844b1ca6134f54652fa2c8c5a52aa396440ac3106e941e6 # via google-auth +pybind11==2.13.6 \ + --hash=sha256:237c41e29157b962835d356b370ededd57594a26d5894a795960f0047cb5caf5 \ + --hash=sha256:ba6af10348c12b24e92fa086b39cfba0eff619b61ac77c406167d813b096d39a + # via -r mlir/python/requirements.txt pyyaml==6.0.1 \ --hash=sha256:04ac92ad1925b2cff1db0cfebffb6ffc43457495c9b3c39d3fcae417d7125dc5 \ --hash=sha256:062582fca9fabdd2c8b54a3ef1c978d786e0f6b3a1510e0ac93ef59e0ddae2bc \ diff --git a/.ci/cache_lit_timing_files.py b/.ci/cache_lit_timing_files.py index 2f43e46..27a5cf6 100644 --- a/.ci/cache_lit_timing_files.py +++ b/.ci/cache_lit_timing_files.py @@ -17,6 +17,7 @@ import pathlib import glob from google.cloud import storage +from google.api_core import exceptions GCS_PARALLELISM = 100 @@ -50,7 +51,14 @@ def _maybe_download_timing_file(blob): def download_timing_files(storage_client, bucket_name: str): bucket = storage_client.bucket(bucket_name) - blobs = bucket.list_blobs(prefix="lit_timing") + try: + blobs = bucket.list_blobs(prefix="lit_timing") + except exceptions.ClientError as client_error: + print( + "::warning file=cache_lit_timing_files.py::Failed to list blobs " + "in bucket." + ) + sys.exit(0) with multiprocessing.pool.ThreadPool(GCS_PARALLELISM) as thread_pool: futures = [] for timing_file_blob in blobs: @@ -60,7 +68,13 @@ def download_timing_files(storage_client, bucket_name: str): ) ) for future in futures: - future.get() + future.wait() + if not future.successful(): + print( + "::warning file=cache_lit_timing_files.py::Failed to " + "download lit timing file." + ) + continue print("Done downloading") diff --git a/.github/new-prs-labeler.yml b/.github/new-prs-labeler.yml index da1d1ca..c49fd1d 100644 --- a/.github/new-prs-labeler.yml +++ b/.github/new-prs-labeler.yml @@ -722,7 +722,12 @@ mlgo: - llvm/include/llvm/Analysis/IR2Vec.h - llvm/lib/Analysis/IR2Vec.cpp - llvm/lib/Analysis/models/** + - llvm/include/llvm/CodeGen/MIR2Vec.h + - llvm/lib/CodeGen/MIR2Vec.cpp - llvm/test/Analysis/IR2Vec/** + - llvm/test/CodeGen/MIR2Vec/** + - llvm/unittests/Analysis/IR2VecTest.cpp + - llvm/unittests/CodeGen/MIR2VecTest.cpp - llvm/tools/llvm-ir2vec/** - llvm/docs/CommandGuide/llvm-ir2vec.rst diff --git a/bolt/docs/PacRetDesign.md b/bolt/docs/PacRetDesign.md deleted file mode 100644 index f3fe5fb..0000000 --- a/bolt/docs/PacRetDesign.md +++ /dev/null @@ -1,228 +0,0 @@ -# Optimizing binaries with pac-ret hardening - -This is a design document about processing the `DW_CFA_AARCH64_negate_ra_state` -DWARF instruction in BOLT. As it describes internal design decisions, the -intended audience is BOLT developers. The document is an updated version of the -[RFC posted on the LLVM Discourse](https://discourse.llvm.org/t/rfc-bolt-aarch64-handle-opnegaterastate-to-enable-optimizing-binaries-with-pac-ret-hardening/86594). - - -`DW_CFA_AARCH64_negate_ra_state` is also referred to as `.cfi_negate_ra_state` -in assembly, or `OpNegateRAState` in BOLT sources. In this document, I will use -**negate-ra-state** as a shorthand. - -## Introduction - -### Pointer Authentication - -For more information, see the [pac-ret section of the BOLT-binary-analysis document](BinaryAnalysis.md#pac-ret-analysis). - -### DW_CFA_AARCH64_negate_ra_state - -The negate-ra-state CFI is a vendor-specific Call Frame Instruction defined in -the [Arm ABI](https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst#id1). - -``` -The DW_CFA_AARCH64_negate_ra_state operation negates bit[0] of the RA_SIGN_STATE pseudo-register. -``` - -This bit indicates to the unwinder whether the current return address is signed -or not (hence the name). The unwinder uses this information to authenticate the -pointer, and remove the Pointer Authentication Code (PAC) bits. -Incorrect placement of negate-ra-state CFIs causes the unwinder to either attempt -to authenticate an unsigned pointer (resulting in a segmentation fault), or skip -authentication on a signed pointer, which can also cause a fault. - -Note: some unwinders use the `xpac` instruction to strip the PAC bits without -authenticating the pointer. This is an incorrect (incomplete) implementation, -as it allows control-flow modification in the case of unwinding. - -There are no DWARF instructions to directly set or clear the RA State. However, -two other CFIs can also affect the RA state: -- `DW_CFA_remember_state`: this CFI stores register rules onto an implicit stack. -- `DW_CFA_restore_state`: this CFI pops rules from this stack. - -Example: - -| CFI | Effect on RA state | -| ------------------------------ | ------------------------------ | -| (default) | 0 | -| DW_CFA_AARCH64_negate_ra_state | 0 -> 1 | -| DW_CFA_remember_state | 1 pushed to the stack | -| DW_CFA_AARCH64_negate_ra_state | 1 -> 0 | -| DW_CFA_restore_state | 0 -> 1 (popped from the stack) | - -The Arm ABI also defines the DW_CFA_AARCH64_negate_ra_state_with_pc CFI, but it -is not widely used, and is [likely to become deprecated](https://github.com/ARM-software/abi-aa/issues/327). - -### Where are these CFIs needed? - -Whenever two consecutive instructions have different RA states, the unwinder must -be informed of the change. This typically occurs during pointer signing or -authentication. If adjacent instructions differ in RA state but neither signs -nor authenticates the return address, they must belong to different control flow -paths. One is part of an execution path with signed RA, the other is part of a -path with an unsigned RA. - -In the example below, the first BasicBlock ends in a conditional branch, and -jumps to two different BasicBlocks, each with their own authentication, and -return. The instructions on the border of the second and third BasicBlock have -different RA states. The `ret` at the end of the second BasicBlock is in unsigned -state. The start of the third BasicBlock is after the `paciasp` in the control -flow, but before the authentication. In this case, a negate-ra-state is needed -at the end of the second BasicBlock. - -``` - +----------------+ - | paciasp | - | | - | b.cc | - +--------+-------+ - | -+----------------+ -| | -| +--------v-------+ -| | | -| | autiasp | -| | ret | // RA: unsigned -| +----------------+ -+----------------+ - | - +--------v-------+ // RA: signed - | | - | autiasp | - | ret | - +----------------+ -``` - -> [!important] -> The unwinder does not follow the control flow graph. It reads unwind -> information in the layout order. - -Because these locations are dependent on how the function layout looks, -negate-ra-state CFIs will become invalid during BasicBlock reordering. - -## Solution design - -The implementation introduces two new passes: -1. `MarkRAStatesPass`: assigns the RA state to each instruction based on the CFIs - in the input binary -2. `InsertNegateRAStatePass`: reads those assigned instruction RA states after - optimizations, and emits `DW_CFA_AARCH64_negate_ra_state` CFIs at the correct - places: wherever there is a state change between two consecutive instructions - in the layout order. - -To track metadata on individual instructions, the `MCAnnotation` class was -extended. These also have helper functions in `MCPlusBuilder`. - -### Saving annotations at CFI reading - -CFIs are read and added to BinaryFunctions in `CFIReaderWriter::FillCFIInfoFor`. -At this point, we add MCAnnotations about negate-ra-state, remember-state and -restore-state CFIs to the instructions they refer to. This is to not interfere -with the CFI processing that already happens in BOLT (e.g. remember-state and -restore-state CFIs are removed in `normalizeCFIState` for reasons unrelated to PAC). - -As we add the MCAnnotations *to instructions*, we have to account for the case -where the function starts with a CFI altering the RA state. As CFIs modify the RA -state of the instructions before them, we cannot add the annotation to the first -instruction. -This special case is handled by adding an `initialRAState` bool to each BinaryFunction. -If the `Offset` the CFI refers to is zero, we don't store an annotation, but set -the `initialRAState` in `FillCFIInfoFor`. This information is then used in -`MarkRAStates`. - -### Binaries without DWARF info - -In some cases, the DWARF tables are stripped from the binary. These programs -usually have some other unwind-mechanism. -These passes only run on functions that include at least one negate-ra-state CFI. -This avoids processing functions that do not use Pointer Authentication, or on -functions that use Pointer Authentication, but do not have DWARF info. - -In summary: -- pointer auth is not used: no change, the new passes do not run. -- pointer auth is used, but DWARF info is stripped: no change, the new passes - do not run. -- pointer auth is used, and we have DWARF CFIs: passes run, and rewrite the - negate-ra-state CFI. - -### MarkRAStates pass - -This pass runs before optimizations reorder anything. - -It processes MCAnnotations generated during the CFI reading stage to check if -instructions have either of the three CFIs that can modify RA state: -- negate-ra-state, -- remember-state, -- restore-state. - -Then it adds new MCAnnotations to each instruction, indicating their RA state. -Those annotations are: -- Signed, -- Unsigned. - -Below is a simple example, that shows the two different type of annotations: -what we have before the pass, and after it. - -| Instruction | Before | After | -| ----------------------------- | --------------- | -------- | -| paciasp | negate-ra-state | unsigned | -| stp x29, x30, [sp, #-0x10]! | | signed | -| mov x29, sp | | signed | -| ldp x29, x30, [sp], #0x10 | | signed | -| autiasp | negate-ra-state | signed | -| ret | | unsigned | - -##### Error handling in MarkRAState Pass: - -Whenever the MarkRAStates pass finds inconsistencies in the current -BinaryFunction, it marks the function as ignored using `BF.setIgnored()`. BOLT -will not optimize this function but will emit it unchanged in the original section -(`.bolt.org.text`). - -The inconsistencies are as follows: -- finding a `pac*` instruction when already in signed state -- finding an `aut*` instruction when already in unsigned state -- finding `pac*` and `aut*` instructions without `.cfi_negate_ra_state`. - -Users will be informed about the number of ignored functions in the pass, the -exact functions ignored, and the found inconsistency. - -### InsertNegateRAStatePass - -This pass runs after optimizations. It performns the _inverse_ of MarkRAState pa s: -1. it reads the RA state annotations attached to the instructions, and -2. whenever the state changes, it adds a PseudoInstruction that holds an - OpNegateRAState CFI. - -##### Covering newly generated instructions: - -Some BOLT passes can add new Instructions. In InsertNegateRAStatePass, we have -to know what RA state these have. - -The current solution has the `inferUnknownStates` function to cover these, using -a fairly simple strategy: unknown states inherit the last known state. - -This will be updated to a more robust solution. - -> [!important] -> As issue #160989 describes, unwind info is incorrect in stubs with multiple callers. -> For this same reason, we cannot generate correct pac-specific unwind info: the signess -> of the _incorrect_ return address is meaningless. - -### Optimizations requiring special attention - -Marking states before optimizations ensure that instructions can be moved around -freely. The only special case is function splitting. When a function is split, -the split part becomes a new function in the emitted binary. For unwinding to -work, it needs to "replay" all CFIs that lead up to the split point. BOLT does -this for other CFIs. As negate-ra-state is not read (only stored as an Annotation), -we have to do this manually in InsertNegateRAStatePass. Here, if the split part -starts with an instruction that has Signed RA state, we add a negate-ra-state CFI -to indicate this. - -## Option to disallow the feature - -The feature can be guarded with the `--update-branch-prediction` flag, which is -on by default. If the flag is set to false, and a function -`containedNegateRAState()` after `FillCFIInfoFor()`, BOLT exits with an error. diff --git a/bolt/include/bolt/Core/BinaryFunction.h b/bolt/include/bolt/Core/BinaryFunction.h index f5e9887..7e0e3bf 100644 --- a/bolt/include/bolt/Core/BinaryFunction.h +++ b/bolt/include/bolt/Core/BinaryFunction.h @@ -148,11 +148,6 @@ public: PF_MEMEVENT = 4, /// Profile has mem events. }; - void setContainedNegateRAState() { HadNegateRAState = true; } - bool containedNegateRAState() const { return HadNegateRAState; } - void setInitialRAState(bool State) { InitialRAState = State; } - bool getInitialRAState() { return InitialRAState; } - /// Struct for tracking exception handling ranges. struct CallSite { const MCSymbol *Start; @@ -223,12 +218,6 @@ private: /// Current state of the function. State CurrentState{State::Empty}; - /// Indicates if the Function contained .cfi-negate-ra-state. These are not - /// read from the binary. This boolean is used when deciding to run the - /// .cfi-negate-ra-state rewriting passes on a function or not. - bool HadNegateRAState{false}; - bool InitialRAState{false}; - /// A list of symbols associated with the function entry point. /// /// Multiple symbols would typically result from identical code-folding @@ -1651,51 +1640,6 @@ public: void setHasInferredProfile(bool Inferred) { HasInferredProfile = Inferred; } - /// Find corrected offset the same way addCFIInstruction does it to skip NOPs. - std::optional<uint64_t> getCorrectedCFIOffset(uint64_t Offset) { - assert(!Instructions.empty()); - auto I = Instructions.lower_bound(Offset); - if (Offset == getSize()) { - assert(I == Instructions.end() && "unexpected iterator value"); - // Sometimes compiler issues restore_state after all instructions - // in the function (even after nop). - --I; - Offset = I->first; - } - assert(I->first == Offset && "CFI pointing to unknown instruction"); - if (I == Instructions.begin()) - return {}; - - --I; - while (I != Instructions.begin() && BC.MIB->isNoop(I->second)) { - Offset = I->first; - --I; - } - return Offset; - } - - void setInstModifiesRAState(uint8_t CFIOpcode, uint64_t Offset) { - std::optional<uint64_t> CorrectedOffset = getCorrectedCFIOffset(Offset); - if (CorrectedOffset) { - auto I = Instructions.lower_bound(*CorrectedOffset); - I--; - - switch (CFIOpcode) { - case dwarf::DW_CFA_AARCH64_negate_ra_state: - BC.MIB->setNegateRAState(I->second); - break; - case dwarf::DW_CFA_remember_state: - BC.MIB->setRememberState(I->second); - break; - case dwarf::DW_CFA_restore_state: - BC.MIB->setRestoreState(I->second); - break; - default: - assert(0 && "CFI Opcode not covered by function"); - } - } - } - void addCFIInstruction(uint64_t Offset, MCCFIInstruction &&Inst) { assert(!Instructions.empty()); diff --git a/bolt/include/bolt/Core/MCPlus.h b/bolt/include/bolt/Core/MCPlus.h index ead6ba1..601d709 100644 --- a/bolt/include/bolt/Core/MCPlus.h +++ b/bolt/include/bolt/Core/MCPlus.h @@ -72,12 +72,7 @@ public: kLabel, /// MCSymbol pointing to this instruction. kSize, /// Size of the instruction. kDynamicBranch, /// Jit instruction patched at runtime. - kRASigned, /// Inst is in a range where RA is signed. - kRAUnsigned, /// Inst is in a range where RA is unsigned. - kRememberState, /// Inst has rememberState CFI. - kRestoreState, /// Inst has restoreState CFI. - kNegateState, /// Inst has OpNegateRAState CFI. - kGeneric, /// First generic annotation. + kGeneric /// First generic annotation. }; virtual void print(raw_ostream &OS) const = 0; diff --git a/bolt/include/bolt/Core/MCPlusBuilder.h b/bolt/include/bolt/Core/MCPlusBuilder.h index 2772de7..5b711b0 100644 --- a/bolt/include/bolt/Core/MCPlusBuilder.h +++ b/bolt/include/bolt/Core/MCPlusBuilder.h @@ -70,20 +70,6 @@ class MCPlusBuilder { public: using AllocatorIdTy = uint16_t; - std::optional<int64_t> getAnnotationAtOpIndex(const MCInst &Inst, - unsigned OpIndex) const { - std::optional<unsigned> FirstAnnotationOp = getFirstAnnotationOpIndex(Inst); - if (!FirstAnnotationOp) - return std::nullopt; - - if (*FirstAnnotationOp > OpIndex || Inst.getNumOperands() < OpIndex) - return std::nullopt; - - const auto *Op = Inst.begin() + OpIndex; - const int64_t ImmValue = Op->getImm(); - return extractAnnotationIndex(ImmValue); - } - private: /// A struct that represents a single annotation allocator struct AnnotationAllocator { @@ -617,21 +603,6 @@ public: return std::nullopt; } - virtual bool isPSignOnLR(const MCInst &Inst) const { - llvm_unreachable("not implemented"); - return false; - } - - virtual bool isPAuthOnLR(const MCInst &Inst) const { - llvm_unreachable("not implemented"); - return false; - } - - virtual bool isPAuthAndRet(const MCInst &Inst) const { - llvm_unreachable("not implemented"); - return false; - } - /// Returns the register used as a return address. Returns std::nullopt if /// not applicable, such as reading the return address from a system register /// or from the stack. @@ -1343,39 +1314,6 @@ public: /// Return true if the instruction is a tail call. bool isTailCall(const MCInst &Inst) const; - /// Stores NegateRAState annotation on \p Inst. - void setNegateRAState(MCInst &Inst) const; - - /// Return true if \p Inst has NegateRAState annotation. - bool hasNegateRAState(const MCInst &Inst) const; - - /// Sets RememberState annotation on \p Inst. - void setRememberState(MCInst &Inst) const; - - /// Return true if \p Inst has RememberState annotation. - bool hasRememberState(const MCInst &Inst) const; - - /// Stores RestoreState annotation on \p Inst. - void setRestoreState(MCInst &Inst) const; - - /// Return true if \p Inst has RestoreState annotation. - bool hasRestoreState(const MCInst &Inst) const; - - /// Stores RA Signed annotation on \p Inst. - void setRASigned(MCInst &Inst) const; - - /// Return true if \p Inst has Signed RA annotation. - bool isRASigned(const MCInst &Inst) const; - - /// Stores RA Unsigned annotation on \p Inst. - void setRAUnsigned(MCInst &Inst) const; - - /// Return true if \p Inst has Unsigned RA annotation. - bool isRAUnsigned(const MCInst &Inst) const; - - /// Return true if \p Inst doesn't have any annotation related to RA state. - bool isRAStateUnknown(const MCInst &Inst) const; - /// Return true if the instruction is a call with an exception handling info. virtual bool isInvoke(const MCInst &Inst) const { return isCall(Inst) && getEHInfo(Inst); diff --git a/bolt/include/bolt/Passes/InsertNegateRAStatePass.h b/bolt/include/bolt/Passes/InsertNegateRAStatePass.h deleted file mode 100644 index 836948b..0000000 --- a/bolt/include/bolt/Passes/InsertNegateRAStatePass.h +++ /dev/null @@ -1,46 +0,0 @@ -//===- bolt/Passes/InsertNegateRAStatePass.cpp ----------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file implements the InsertNegateRAStatePass class. -// -//===----------------------------------------------------------------------===// -#ifndef BOLT_PASSES_INSERT_NEGATE_RA_STATE_PASS -#define BOLT_PASSES_INSERT_NEGATE_RA_STATE_PASS - -#include "bolt/Passes/BinaryPasses.h" - -namespace llvm { -namespace bolt { - -class InsertNegateRAState : public BinaryFunctionPass { -public: - explicit InsertNegateRAState() : BinaryFunctionPass(false) {} - - const char *getName() const override { return "insert-negate-ra-state-pass"; } - - /// Pass entry point - Error runOnFunctions(BinaryContext &BC) override; - void runOnFunction(BinaryFunction &BF); - -private: - /// Because states are tracked as MCAnnotations on individual instructions, - /// newly inserted instructions do not have a state associated with them. - /// New states are "inherited" from the last known state. - void inferUnknownStates(BinaryFunction &BF); - - /// Support for function splitting: - /// if two consecutive BBs with Signed state are going to end up in different - /// functions (so are held by different FunctionFragments), we have to add a - /// OpNegateRAState to the beginning of the newly split function, so it starts - /// with a Signed state. - void coverFunctionFragmentStart(BinaryFunction &BF, FunctionFragment &FF); -}; - -} // namespace bolt -} // namespace llvm -#endif diff --git a/bolt/include/bolt/Passes/MarkRAStates.h b/bolt/include/bolt/Passes/MarkRAStates.h deleted file mode 100644 index 675ab97..0000000 --- a/bolt/include/bolt/Passes/MarkRAStates.h +++ /dev/null @@ -1,33 +0,0 @@ -//===- bolt/Passes/MarkRAStates.cpp ---------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file implements the MarkRAStates class. -// -//===----------------------------------------------------------------------===// -#ifndef BOLT_PASSES_MARK_RA_STATES -#define BOLT_PASSES_MARK_RA_STATES - -#include "bolt/Passes/BinaryPasses.h" - -namespace llvm { -namespace bolt { - -class MarkRAStates : public BinaryFunctionPass { -public: - explicit MarkRAStates() : BinaryFunctionPass(false) {} - - const char *getName() const override { return "mark-ra-states"; } - - /// Pass entry point - Error runOnFunctions(BinaryContext &BC) override; - bool runOnFunction(BinaryFunction &BF); -}; - -} // namespace bolt -} // namespace llvm -#endif diff --git a/bolt/include/bolt/Utils/CommandLineOpts.h b/bolt/include/bolt/Utils/CommandLineOpts.h index 5c7f1b9..0964c2c 100644 --- a/bolt/include/bolt/Utils/CommandLineOpts.h +++ b/bolt/include/bolt/Utils/CommandLineOpts.h @@ -97,7 +97,6 @@ extern llvm::cl::opt<std::string> OutputFilename; extern llvm::cl::opt<std::string> PerfData; extern llvm::cl::opt<bool> PrintCacheMetrics; extern llvm::cl::opt<bool> PrintSections; -extern llvm::cl::opt<bool> UpdateBranchProtection; extern llvm::cl::opt<SplitFunctionsStrategy> SplitStrategy; // The format to use with -o in aggregation mode (perf2bolt) diff --git a/bolt/lib/Core/BinaryBasicBlock.cpp b/bolt/lib/Core/BinaryBasicBlock.cpp index d680850..eeab1ed 100644 --- a/bolt/lib/Core/BinaryBasicBlock.cpp +++ b/bolt/lib/Core/BinaryBasicBlock.cpp @@ -210,11 +210,7 @@ int32_t BinaryBasicBlock::getCFIStateAtInstr(const MCInst *Instr) const { InstrSeen = (&Inst == Instr); continue; } - // Ignoring OpNegateRAState CFIs here, as they dont have a "State" - // number associated with them. - if (Function->getBinaryContext().MIB->isCFI(Inst) && - (Function->getCFIFor(Inst)->getOperation() != - MCCFIInstruction::OpNegateRAState)) { + if (Function->getBinaryContext().MIB->isCFI(Inst)) { LastCFI = &Inst; break; } diff --git a/bolt/lib/Core/BinaryContext.cpp b/bolt/lib/Core/BinaryContext.cpp index 206d8eef..b7ded6b 100644 --- a/bolt/lib/Core/BinaryContext.cpp +++ b/bolt/lib/Core/BinaryContext.cpp @@ -1905,9 +1905,6 @@ void BinaryContext::printCFI(raw_ostream &OS, const MCCFIInstruction &Inst) { case MCCFIInstruction::OpGnuArgsSize: OS << "OpGnuArgsSize"; break; - case MCCFIInstruction::OpNegateRAState: - OS << "OpNegateRAState"; - break; default: OS << "Op#" << Operation; break; diff --git a/bolt/lib/Core/BinaryFunction.cpp b/bolt/lib/Core/BinaryFunction.cpp index 9687892..07bc71e 100644 --- a/bolt/lib/Core/BinaryFunction.cpp +++ b/bolt/lib/Core/BinaryFunction.cpp @@ -2814,9 +2814,15 @@ private: case MCCFIInstruction::OpLLVMDefAspaceCfa: case MCCFIInstruction::OpLabel: case MCCFIInstruction::OpValOffset: - case MCCFIInstruction::OpNegateRAState: llvm_unreachable("unsupported CFI opcode"); break; + case MCCFIInstruction::OpNegateRAState: + if (!(opts::BinaryAnalysisMode || opts::HeatmapMode)) { + llvm_unreachable("BOLT-ERROR: binaries using pac-ret hardening (e.g. " + "as produced by '-mbranch-protection=pac-ret') are " + "currently not supported by BOLT."); + } + break; case MCCFIInstruction::OpRememberState: case MCCFIInstruction::OpRestoreState: case MCCFIInstruction::OpGnuArgsSize: @@ -2830,7 +2836,6 @@ public: void advanceTo(int32_t State) { for (int32_t I = CurState, E = State; I != E; ++I) { const MCCFIInstruction &Instr = FDE[I]; - assert(Instr.getOperation() != MCCFIInstruction::OpNegateRAState); if (Instr.getOperation() != MCCFIInstruction::OpRestoreState) { update(Instr, I); continue; @@ -2955,9 +2960,15 @@ struct CFISnapshotDiff : public CFISnapshot { case MCCFIInstruction::OpLLVMDefAspaceCfa: case MCCFIInstruction::OpLabel: case MCCFIInstruction::OpValOffset: - case MCCFIInstruction::OpNegateRAState: llvm_unreachable("unsupported CFI opcode"); return false; + case MCCFIInstruction::OpNegateRAState: + if (!(opts::BinaryAnalysisMode || opts::HeatmapMode)) { + llvm_unreachable("BOLT-ERROR: binaries using pac-ret hardening (e.g. " + "as produced by '-mbranch-protection=pac-ret') are " + "currently not supported by BOLT."); + } + break; case MCCFIInstruction::OpRememberState: case MCCFIInstruction::OpRestoreState: case MCCFIInstruction::OpGnuArgsSize: @@ -3106,9 +3117,15 @@ BinaryFunction::unwindCFIState(int32_t FromState, int32_t ToState, case MCCFIInstruction::OpLLVMDefAspaceCfa: case MCCFIInstruction::OpLabel: case MCCFIInstruction::OpValOffset: - case MCCFIInstruction::OpNegateRAState: llvm_unreachable("unsupported CFI opcode"); break; + case MCCFIInstruction::OpNegateRAState: + if (!(opts::BinaryAnalysisMode || opts::HeatmapMode)) { + llvm_unreachable("BOLT-ERROR: binaries using pac-ret hardening (e.g. " + "as produced by '-mbranch-protection=pac-ret') are " + "currently not supported by BOLT."); + } + break; case MCCFIInstruction::OpGnuArgsSize: // do not affect CFI state break; diff --git a/bolt/lib/Core/Exceptions.cpp b/bolt/lib/Core/Exceptions.cpp index 27656c7..874419f 100644 --- a/bolt/lib/Core/Exceptions.cpp +++ b/bolt/lib/Core/Exceptions.cpp @@ -568,25 +568,10 @@ bool CFIReaderWriter::fillCFIInfoFor(BinaryFunction &Function) const { case DW_CFA_remember_state: Function.addCFIInstruction( Offset, MCCFIInstruction::createRememberState(nullptr)); - - if (Function.getBinaryContext().isAArch64()) { - // Support for pointer authentication: - // We need to annotate instructions that modify the RA State, to work - // out the state of each instruction in MarkRAStates Pass. - if (Offset != 0) - Function.setInstModifiesRAState(DW_CFA_remember_state, Offset); - } break; case DW_CFA_restore_state: Function.addCFIInstruction(Offset, MCCFIInstruction::createRestoreState(nullptr)); - if (Function.getBinaryContext().isAArch64()) { - // Support for pointer authentication: - // We need to annotate instructions that modify the RA State, to work - // out the state of each instruction in MarkRAStates Pass. - if (Offset != 0) - Function.setInstModifiesRAState(DW_CFA_restore_state, Offset); - } break; case DW_CFA_def_cfa: Function.addCFIInstruction( @@ -644,24 +629,11 @@ bool CFIReaderWriter::fillCFIInfoFor(BinaryFunction &Function) const { BC.errs() << "BOLT-WARNING: DW_CFA_MIPS_advance_loc unimplemented\n"; return false; case DW_CFA_GNU_window_save: - // DW_CFA_GNU_window_save and DW_CFA_AARCH64_negate_ra_state just use the - // same id but mean different things. The latter is used in AArch64. + // DW_CFA_GNU_window_save and DW_CFA_GNU_NegateRAState just use the same + // id but mean different things. The latter is used in AArch64. if (Function.getBinaryContext().isAArch64()) { - Function.setContainedNegateRAState(); - // The location OpNegateRAState CFIs are needed depends on the order of - // BasicBlocks, which changes during optimizations. Instead of adding - // OpNegateRAState CFIs, an annotation is added to the instruction, to - // mark that the instruction modifies the RA State. The actual state for - // instructions are worked out in MarkRAStates based on these - // annotations. - if (Offset != 0) - Function.setInstModifiesRAState(DW_CFA_AARCH64_negate_ra_state, - Offset); - else - // We cannot Annotate an instruction at Offset == 0. - // Instead, we save the initial (Signed) state, and push it to - // MarkRAStates' RAStateStack. - Function.setInitialRAState(true); + Function.addCFIInstruction( + Offset, MCCFIInstruction::createNegateRAState(nullptr)); break; } if (opts::Verbosity >= 1) diff --git a/bolt/lib/Core/MCPlusBuilder.cpp b/bolt/lib/Core/MCPlusBuilder.cpp index e96de80..5247522 100644 --- a/bolt/lib/Core/MCPlusBuilder.cpp +++ b/bolt/lib/Core/MCPlusBuilder.cpp @@ -159,55 +159,6 @@ bool MCPlusBuilder::isTailCall(const MCInst &Inst) const { return false; } -void MCPlusBuilder::setNegateRAState(MCInst &Inst) const { - assert(!hasAnnotation(Inst, MCAnnotation::kNegateState)); - setAnnotationOpValue(Inst, MCAnnotation::kNegateState, true); -} - -bool MCPlusBuilder::hasNegateRAState(const MCInst &Inst) const { - return hasAnnotation(Inst, MCAnnotation::kNegateState); -} - -void MCPlusBuilder::setRememberState(MCInst &Inst) const { - assert(!hasAnnotation(Inst, MCAnnotation::kRememberState)); - setAnnotationOpValue(Inst, MCAnnotation::kRememberState, true); -} - -bool MCPlusBuilder::hasRememberState(const MCInst &Inst) const { - return hasAnnotation(Inst, MCAnnotation::kRememberState); -} - -void MCPlusBuilder::setRestoreState(MCInst &Inst) const { - assert(!hasAnnotation(Inst, MCAnnotation::kRestoreState)); - setAnnotationOpValue(Inst, MCAnnotation::kRestoreState, true); -} - -bool MCPlusBuilder::hasRestoreState(const MCInst &Inst) const { - return hasAnnotation(Inst, MCAnnotation::kRestoreState); -} - -void MCPlusBuilder::setRASigned(MCInst &Inst) const { - assert(!hasAnnotation(Inst, MCAnnotation::kRASigned)); - setAnnotationOpValue(Inst, MCAnnotation::kRASigned, true); -} - -bool MCPlusBuilder::isRASigned(const MCInst &Inst) const { - return hasAnnotation(Inst, MCAnnotation::kRASigned); -} - -void MCPlusBuilder::setRAUnsigned(MCInst &Inst) const { - assert(!hasAnnotation(Inst, MCAnnotation::kRAUnsigned)); - setAnnotationOpValue(Inst, MCAnnotation::kRAUnsigned, true); -} - -bool MCPlusBuilder::isRAUnsigned(const MCInst &Inst) const { - return hasAnnotation(Inst, MCAnnotation::kRAUnsigned); -} - -bool MCPlusBuilder::isRAStateUnknown(const MCInst &Inst) const { - return !(isRAUnsigned(Inst) || isRASigned(Inst)); -} - std::optional<MCLandingPad> MCPlusBuilder::getEHInfo(const MCInst &Inst) const { if (!isCall(Inst)) return std::nullopt; diff --git a/bolt/lib/Passes/CMakeLists.txt b/bolt/lib/Passes/CMakeLists.txt index d751951..77d2bb9 100644 --- a/bolt/lib/Passes/CMakeLists.txt +++ b/bolt/lib/Passes/CMakeLists.txt @@ -17,14 +17,12 @@ add_llvm_library(LLVMBOLTPasses IdenticalCodeFolding.cpp IndirectCallPromotion.cpp Inliner.cpp - InsertNegateRAStatePass.cpp Instrumentation.cpp JTFootprintReduction.cpp LongJmp.cpp LoopInversionPass.cpp LivenessAnalysis.cpp MCF.cpp - MarkRAStates.cpp PatchEntries.cpp PAuthGadgetScanner.cpp PettisAndHansen.cpp diff --git a/bolt/lib/Passes/InsertNegateRAStatePass.cpp b/bolt/lib/Passes/InsertNegateRAStatePass.cpp deleted file mode 100644 index 33664e1..0000000 --- a/bolt/lib/Passes/InsertNegateRAStatePass.cpp +++ /dev/null @@ -1,142 +0,0 @@ -//===- bolt/Passes/InsertNegateRAStatePass.cpp ----------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file implements the InsertNegateRAStatePass class. It inserts -// OpNegateRAState CFIs to places where the state of two consecutive -// instructions are different. -// -//===----------------------------------------------------------------------===// -#include "bolt/Passes/InsertNegateRAStatePass.h" -#include "bolt/Core/BinaryFunction.h" -#include "bolt/Core/ParallelUtilities.h" -#include <cstdlib> - -using namespace llvm; - -namespace llvm { -namespace bolt { - -void InsertNegateRAState::runOnFunction(BinaryFunction &BF) { - BinaryContext &BC = BF.getBinaryContext(); - - if (BF.getState() == BinaryFunction::State::Empty) - return; - - if (BF.getState() != BinaryFunction::State::CFG && - BF.getState() != BinaryFunction::State::CFG_Finalized) { - BC.outs() << "BOLT-INFO: no CFG for " << BF.getPrintName() - << " in InsertNegateRAStatePass\n"; - return; - } - - inferUnknownStates(BF); - - for (FunctionFragment &FF : BF.getLayout().fragments()) { - coverFunctionFragmentStart(BF, FF); - bool FirstIter = true; - MCInst PrevInst; - // As this pass runs after function splitting, we should only check - // consecutive instructions inside FunctionFragments. - for (BinaryBasicBlock *BB : FF) { - for (auto It = BB->begin(); It != BB->end(); ++It) { - MCInst &Inst = *It; - if (BC.MIB->isCFI(Inst)) - continue; - if (!FirstIter) { - // Consecutive instructions with different RAState means we need to - // add a OpNegateRAState. - if ((BC.MIB->isRASigned(PrevInst) && BC.MIB->isRAUnsigned(Inst)) || - (BC.MIB->isRAUnsigned(PrevInst) && BC.MIB->isRASigned(Inst))) { - It = BF.addCFIInstruction( - BB, It, MCCFIInstruction::createNegateRAState(nullptr)); - } - } else { - FirstIter = false; - } - PrevInst = *It; - } - } - } -} - -void InsertNegateRAState::coverFunctionFragmentStart(BinaryFunction &BF, - FunctionFragment &FF) { - BinaryContext &BC = BF.getBinaryContext(); - if (FF.empty()) - return; - // Find the first BB in the FF which has Instructions. - // BOLT can generate empty BBs at function splitting which are only used as - // target labels. We should add the negate-ra-state CFI to the first - // non-empty BB. - auto *FirstNonEmpty = - std::find_if(FF.begin(), FF.end(), [](BinaryBasicBlock *BB) { - // getFirstNonPseudo returns BB.end() if it does not find any - // Instructions. - return BB->getFirstNonPseudo() != BB->end(); - }); - // If a function is already split in the input, the first FF can also start - // with Signed state. This covers that scenario as well. - if (BC.MIB->isRASigned(*((*FirstNonEmpty)->begin()))) { - BF.addCFIInstruction(*FirstNonEmpty, (*FirstNonEmpty)->begin(), - MCCFIInstruction::createNegateRAState(nullptr)); - } -} - -void InsertNegateRAState::inferUnknownStates(BinaryFunction &BF) { - BinaryContext &BC = BF.getBinaryContext(); - bool FirstIter = true; - MCInst PrevInst; - for (BinaryBasicBlock &BB : BF) { - for (MCInst &Inst : BB) { - if (BC.MIB->isCFI(Inst)) - continue; - - if (!FirstIter && BC.MIB->isRAStateUnknown(Inst)) { - if (BC.MIB->isRASigned(PrevInst) || BC.MIB->isPSignOnLR(PrevInst)) { - BC.MIB->setRASigned(Inst); - } else if (BC.MIB->isRAUnsigned(PrevInst) || - BC.MIB->isPAuthOnLR(PrevInst)) { - BC.MIB->setRAUnsigned(Inst); - } - } else { - FirstIter = false; - } - PrevInst = Inst; - } - } -} - -Error InsertNegateRAState::runOnFunctions(BinaryContext &BC) { - std::atomic<uint64_t> FunctionsModified{0}; - ParallelUtilities::WorkFuncTy WorkFun = [&](BinaryFunction &BF) { - FunctionsModified++; - runOnFunction(BF); - }; - - ParallelUtilities::PredicateTy SkipPredicate = [&](const BinaryFunction &BF) { - // We can skip functions which did not include negate-ra-state CFIs. This - // includes code using pac-ret hardening as well, if the binary is - // compiled with `-fno-exceptions -fno-unwind-tables - // -fno-asynchronous-unwind-tables` - return !BF.containedNegateRAState() || BF.isIgnored(); - }; - - ParallelUtilities::runOnEachFunction( - BC, ParallelUtilities::SchedulingPolicy::SP_INST_LINEAR, WorkFun, - SkipPredicate, "InsertNegateRAStatePass"); - - BC.outs() << "BOLT-INFO: rewritten pac-ret DWARF info in " - << FunctionsModified << " out of " << BC.getBinaryFunctions().size() - << " functions " - << format("(%.2lf%%).\n", (100.0 * FunctionsModified) / - BC.getBinaryFunctions().size()); - return Error::success(); -} - -} // end namespace bolt -} // end namespace llvm diff --git a/bolt/lib/Passes/MarkRAStates.cpp b/bolt/lib/Passes/MarkRAStates.cpp deleted file mode 100644 index 2c5ce4a..0000000 --- a/bolt/lib/Passes/MarkRAStates.cpp +++ /dev/null @@ -1,152 +0,0 @@ -//===- bolt/Passes/MarkRAStates.cpp ---------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file implements the MarkRAStates class. -// Three CFIs have an influence on the RA State of an instruction: -// - NegateRAState flips the RA State, -// - RememberState pushes the RA State to a stack, -// - RestoreState pops the RA State from the stack. -// These are saved as MCAnnotations on instructions they refer to at CFI -// reading (in CFIReaderWriter::fillCFIInfoFor). In this pass, we can work out -// the RA State of each instruction, and save it as new MCAnnotations. The new -// annotations are Signing, Signed, Authenticating and Unsigned. After -// optimizations, .cfi_negate_ra_state CFIs are added to the places where the -// state changes in InsertNegateRAStatePass. -// -//===----------------------------------------------------------------------===// -#include "bolt/Passes/MarkRAStates.h" -#include "bolt/Core/BinaryFunction.h" -#include "bolt/Core/ParallelUtilities.h" -#include <cstdlib> -#include <optional> -#include <stack> - -using namespace llvm; - -namespace llvm { -namespace bolt { - -bool MarkRAStates::runOnFunction(BinaryFunction &BF) { - - BinaryContext &BC = BF.getBinaryContext(); - - for (const BinaryBasicBlock &BB : BF) { - for (const MCInst &Inst : BB) { - if ((BC.MIB->isPSignOnLR(Inst) || - (BC.MIB->isPAuthOnLR(Inst) && !BC.MIB->isPAuthAndRet(Inst))) && - !BC.MIB->hasNegateRAState(Inst)) { - // Not all functions have .cfi_negate_ra_state in them. But if one does, - // we expect psign/pauth instructions to have the hasNegateRAState - // annotation. - BF.setIgnored(); - BC.outs() << "BOLT-INFO: inconsistent RAStates in function " - << BF.getPrintName() - << ": ptr sign/auth inst without .cfi_negate_ra_state\n"; - return false; - } - } - } - - bool RAState = BF.getInitialRAState(); - std::stack<bool> RAStateStack; - RAStateStack.push(RAState); - - for (BinaryBasicBlock &BB : BF) { - for (MCInst &Inst : BB) { - if (BC.MIB->isCFI(Inst)) - continue; - - if (BC.MIB->isPSignOnLR(Inst)) { - if (RAState) { - // RA signing instructions should only follow unsigned RA state. - BC.outs() << "BOLT-INFO: inconsistent RAStates in function " - << BF.getPrintName() - << ": ptr signing inst encountered in Signed RA state\n"; - BF.setIgnored(); - return false; - } - // The signing instruction itself is unsigned, the next will be - // signed. - BC.MIB->setRAUnsigned(Inst); - } else if (BC.MIB->isPAuthOnLR(Inst)) { - if (!RAState) { - // RA authenticating instructions should only follow signed RA state. - BC.outs() << "BOLT-INFO: inconsistent RAStates in function " - << BF.getPrintName() - << ": ptr authenticating inst encountered in Unsigned RA " - "state\n"; - BF.setIgnored(); - return false; - } - // The authenticating instruction itself is signed, but the next will be - // unsigned. - BC.MIB->setRASigned(Inst); - } else if (RAState) { - BC.MIB->setRASigned(Inst); - } else { - BC.MIB->setRAUnsigned(Inst); - } - - // Updating RAState. All updates are valid from the next instruction. - // Because the same instruction can have remember and restore, the order - // here is relevant. This is the reason to loop over Annotations instead - // of just checking each in a predefined order. - for (unsigned int Idx = 0; Idx < Inst.getNumOperands(); Idx++) { - std::optional<int64_t> Annotation = - BC.MIB->getAnnotationAtOpIndex(Inst, Idx); - if (!Annotation) - continue; - if (Annotation == MCPlus::MCAnnotation::kNegateState) - RAState = !RAState; - else if (Annotation == MCPlus::MCAnnotation::kRememberState) - RAStateStack.push(RAState); - else if (Annotation == MCPlus::MCAnnotation::kRestoreState) { - RAState = RAStateStack.top(); - RAStateStack.pop(); - } - } - } - } - return true; -} - -Error MarkRAStates::runOnFunctions(BinaryContext &BC) { - std::atomic<uint64_t> FunctionsIgnored{0}; - ParallelUtilities::WorkFuncTy WorkFun = [&](BinaryFunction &BF) { - if (!runOnFunction(BF)) { - FunctionsIgnored++; - } - }; - - ParallelUtilities::PredicateTy SkipPredicate = [&](const BinaryFunction &BF) { - // We can skip functions which did not include negate-ra-state CFIs. This - // includes code using pac-ret hardening as well, if the binary is - // compiled with `-fno-exceptions -fno-unwind-tables - // -fno-asynchronous-unwind-tables` - return !BF.containedNegateRAState() || BF.isIgnored(); - }; - - int Total = llvm::count_if( - BC.getBinaryFunctions(), - [&](std::pair<const unsigned long, BinaryFunction> &P) { - return P.second.containedNegateRAState() && !P.second.isIgnored(); - }); - - ParallelUtilities::runOnEachFunction( - BC, ParallelUtilities::SchedulingPolicy::SP_INST_LINEAR, WorkFun, - SkipPredicate, "MarkRAStates"); - BC.outs() << "BOLT-INFO: MarkRAStates ran on " << Total - << " functions. Ignored " << FunctionsIgnored << " functions " - << format("(%.2lf%%)", (100.0 * FunctionsIgnored) / Total) - << " because of CFI inconsistencies\n"; - - return Error::success(); -} - -} // end namespace bolt -} // end namespace llvm diff --git a/bolt/lib/Rewrite/BinaryPassManager.cpp b/bolt/lib/Rewrite/BinaryPassManager.cpp index 782137e..d9b7a2bd 100644 --- a/bolt/lib/Rewrite/BinaryPassManager.cpp +++ b/bolt/lib/Rewrite/BinaryPassManager.cpp @@ -19,13 +19,11 @@ #include "bolt/Passes/IdenticalCodeFolding.h" #include "bolt/Passes/IndirectCallPromotion.h" #include "bolt/Passes/Inliner.h" -#include "bolt/Passes/InsertNegateRAStatePass.h" #include "bolt/Passes/Instrumentation.h" #include "bolt/Passes/JTFootprintReduction.h" #include "bolt/Passes/LongJmp.h" #include "bolt/Passes/LoopInversionPass.h" #include "bolt/Passes/MCF.h" -#include "bolt/Passes/MarkRAStates.h" #include "bolt/Passes/PLTCall.h" #include "bolt/Passes/PatchEntries.h" #include "bolt/Passes/ProfileQualityStats.h" @@ -278,12 +276,6 @@ static cl::opt<bool> ShortenInstructions("shorten-instructions", cl::desc("shorten instructions"), cl::init(true), cl::cat(BoltOptCategory)); - -cl::opt<bool> - UpdateBranchProtection("update-branch-protection", - cl::desc("Rewrites pac-ret DWARF CFI instructions " - "(AArch64-only, on by default)"), - cl::init(true), cl::Hidden, cl::cat(BoltCategory)); } // namespace opts namespace llvm { @@ -361,9 +353,6 @@ Error BinaryFunctionPassManager::runPasses() { Error BinaryFunctionPassManager::runAllPasses(BinaryContext &BC) { BinaryFunctionPassManager Manager(BC); - if (BC.isAArch64()) - Manager.registerPass(std::make_unique<MarkRAStates>()); - Manager.registerPass( std::make_unique<EstimateEdgeCounts>(PrintEstimateEdgeCounts)); @@ -523,8 +512,6 @@ Error BinaryFunctionPassManager::runAllPasses(BinaryContext &BC) { // targets. No extra instructions after this pass, otherwise we may have // relocations out of range and crash during linking. Manager.registerPass(std::make_unique<LongJmpPass>(PrintLongJmp)); - - Manager.registerPass(std::make_unique<InsertNegateRAState>()); } // This pass should always run last.* diff --git a/bolt/lib/Rewrite/RewriteInstance.cpp b/bolt/lib/Rewrite/RewriteInstance.cpp index c428828..ddf9347 100644 --- a/bolt/lib/Rewrite/RewriteInstance.cpp +++ b/bolt/lib/Rewrite/RewriteInstance.cpp @@ -3524,17 +3524,6 @@ void RewriteInstance::disassembleFunctions() { } } - // Check if fillCFIInfoFor removed any OpNegateRAState CFIs from the - // function. - if (Function.containedNegateRAState()) { - if (!opts::UpdateBranchProtection) { - BC->errs() - << "BOLT-ERROR: --update-branch-protection is set to false, but " - << Function.getPrintName() << " contains .cfi-negate-ra-state\n"; - exit(1); - } - } - // Parse LSDA. if (Function.getLSDAAddress() != 0 && !BC->getFragmentsToSkip().count(&Function)) { diff --git a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp index df4f421..f271867 100644 --- a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp +++ b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp @@ -244,28 +244,6 @@ public: } } - bool isPSignOnLR(const MCInst &Inst) const override { - std::optional<MCPhysReg> SignReg = getSignedReg(Inst); - return SignReg && *SignReg == AArch64::LR; - } - - bool isPAuthOnLR(const MCInst &Inst) const override { - // LDR(A|B) should not be covered. - bool IsChecked; - std::optional<MCPhysReg> AuthReg = - getWrittenAuthenticatedReg(Inst, IsChecked); - return !IsChecked && AuthReg && *AuthReg == AArch64::LR; - } - - bool isPAuthAndRet(const MCInst &Inst) const override { - return Inst.getOpcode() == AArch64::RETAA || - Inst.getOpcode() == AArch64::RETAB || - Inst.getOpcode() == AArch64::RETAASPPCi || - Inst.getOpcode() == AArch64::RETABSPPCi || - Inst.getOpcode() == AArch64::RETAASPPCr || - Inst.getOpcode() == AArch64::RETABSPPCr; - } - std::optional<MCPhysReg> getSignedReg(const MCInst &Inst) const override { switch (Inst.getOpcode()) { case AArch64::PACIA: diff --git a/bolt/test/AArch64/negate-ra-state-disallow.s b/bolt/test/AArch64/negate-ra-state-disallow.s deleted file mode 100644 index 95adb71..0000000 --- a/bolt/test/AArch64/negate-ra-state-disallow.s +++ /dev/null @@ -1,25 +0,0 @@ -# RUN: llvm-mc -filetype=obj -triple aarch64-unknown-unknown %s -o %t.o -# RUN: %clang %cflags %t.o -o %t.exe -Wl,-q -# RUN: not llvm-bolt %t.exe -o %t.exe.bolt --update-branch-protection=false 2>&1 | FileCheck %s - -# CHECK: BOLT-ERROR: --update-branch-protection is set to false, but foo contains .cfi-negate-ra-state - - .text - .globl foo - .p2align 2 - .type foo,@function -foo: - .cfi_startproc - hint #25 - .cfi_negate_ra_state - mov x1, #0 - hint #29 - .cfi_negate_ra_state - ret - .cfi_endproc - .size foo, .-foo - - .global _start - .type _start, %function -_start: - b foo diff --git a/bolt/test/AArch64/negate-ra-state-incorrect.s b/bolt/test/AArch64/negate-ra-state-incorrect.s deleted file mode 100644 index 14d2c38..0000000 --- a/bolt/test/AArch64/negate-ra-state-incorrect.s +++ /dev/null @@ -1,78 +0,0 @@ -# This test checks that MarkRAStates pass ignores functions with -# malformed .cfi_negate_ra_state sequences in the input binary. - -# The cases checked are: -# - extra .cfi_negate_ra_state in Signed state: checked in foo, -# - extra .cfi_negate_ra_state in Unsigned state: checked in bar, -# - missing .cfi_negate_ra_state from PSign or PAuth instructions: checked in baz. - -# RUN: llvm-mc -filetype=obj -triple aarch64-unknown-unknown %s -o %t.o -# RUN: %clang %cflags %t.o -o %t.exe -Wl,-q -# RUN: llvm-bolt %t.exe -o %t.exe.bolt --no-threads | FileCheck %s --check-prefix=CHECK-BOLT - -# CHECK-BOLT: BOLT-INFO: inconsistent RAStates in function foo: ptr authenticating inst encountered in Unsigned RA state -# CHECK-BOLT: BOLT-INFO: inconsistent RAStates in function bar: ptr signing inst encountered in Signed RA state -# CHECK-BOLT: BOLT-INFO: inconsistent RAStates in function baz: ptr sign/auth inst without .cfi_negate_ra_state - -# Check that the incorrect functions got ignored, so they are not in the new .text section -# RUN: llvm-objdump %t.exe.bolt -d -j .text | FileCheck %s --check-prefix=CHECK-OBJDUMP -# CHECK-OBJDUMP-NOT: <foo>: -# CHECK-OBJDUMP-NOT: <bar>: -# CHECK-OBJDUMP-NOT: <baz>: - - - .text - .globl foo - .p2align 2 - .type foo,@function -foo: - .cfi_startproc - hint #25 - .cfi_negate_ra_state - mov x1, #0 - .cfi_negate_ra_state // Incorrect CFI in signed state - hint #29 - .cfi_negate_ra_state - ret - .cfi_endproc - .size foo, .-foo - - .text - .globl bar - .p2align 2 - .type bar,@function -bar: - .cfi_startproc - mov x1, #0 - .cfi_negate_ra_state // Incorrect CFI in unsigned state - hint #25 - .cfi_negate_ra_state - mov x1, #0 - hint #29 - .cfi_negate_ra_state - ret - .cfi_endproc - .size bar, .-bar - - .text - .globl baz - .p2align 2 - .type baz,@function -baz: - .cfi_startproc - mov x1, #0 - hint #25 - .cfi_negate_ra_state - mov x1, #0 - hint #29 - // Missing .cfi_negate_ra_state - ret - .cfi_endproc - .size baz, .-baz - - .global _start - .type _start, %function -_start: - b foo - b bar - b baz diff --git a/bolt/test/AArch64/negate-ra-state-reorder.s b/bolt/test/AArch64/negate-ra-state-reorder.s deleted file mode 100644 index 2659f75..0000000 --- a/bolt/test/AArch64/negate-ra-state-reorder.s +++ /dev/null @@ -1,73 +0,0 @@ -# Checking that after reordering BasicBlocks, the generated OpNegateRAState instructions -# are placed where the RA state is different between two consecutive instructions. -# This case demonstrates, that the input might have a different amount than the output: -# input has 4, but output only has 3. - -# RUN: llvm-mc -filetype=obj -triple aarch64-unknown-unknown %s -o %t.o -# RUN: %clang %cflags %t.o -o %t.exe -Wl,-q -# RUN: llvm-bolt %t.exe -o %t.exe.bolt --no-threads --reorder-blocks=reverse \ -# RUN: --print-cfg --print-after-lowering --print-only foo | FileCheck %s - -# Check that the reordering succeeded. -# CHECK: Binary Function "foo" after building cfg { -# CHECK: BB Layout : .LBB00, .Ltmp2, .Ltmp0, .Ltmp1 -# CHECK: Binary Function "foo" after inst-lowering { -# CHECK: BB Layout : .LBB00, .Ltmp1, .Ltmp0, .Ltmp2 - - -# Check the generated CFIs. -# CHECK: OpNegateRAState -# CHECK-NEXT: mov x2, #0x6 - -# CHECK: autiasp -# CHECK-NEXT: OpNegateRAState -# CHECK-NEXT: ret - -# CHECK: paciasp -# CHECK-NEXT: OpNegateRAState - -# CHECK: DWARF CFI Instructions: -# CHECK-NEXT: 0: OpNegateRAState -# CHECK-NEXT: 1: OpNegateRAState -# CHECK-NEXT: 2: OpNegateRAState -# CHECK-NEXT: End of Function "foo" - - .text - .globl foo - .p2align 2 - .type foo,@function -foo: - .cfi_startproc - // RA is unsigned - mov x1, #0 - mov x1, #1 - mov x1, #2 - // jump into the signed "range" - b .Lmiddle -.Lback: -// sign RA - paciasp - .cfi_negate_ra_state - mov x2, #3 - mov x2, #4 - // skip unsigned instructions - b .Lcont - .cfi_negate_ra_state -.Lmiddle: -// RA is unsigned - mov x4, #5 - b .Lback - .cfi_negate_ra_state -.Lcont: -// continue in signed state - mov x2, #6 - autiasp - .cfi_negate_ra_state - ret - .cfi_endproc - .size foo, .-foo - - .global _start - .type _start, %function -_start: - b foo diff --git a/bolt/test/AArch64/negate-ra-state.s b/bolt/test/AArch64/negate-ra-state.s deleted file mode 100644 index 30786d4..0000000 --- a/bolt/test/AArch64/negate-ra-state.s +++ /dev/null @@ -1,76 +0,0 @@ -# Checking that .cfi-negate_ra_state directives are emitted in the same location as in the input in the case of no optimizations. - -# The foo and bar functions are a pair, with the first signing the return address, -# and the second authenticating it. We have a tailcall between the two. -# This is testing that BOLT can handle functions starting in signed RA state. - -# RUN: llvm-mc -filetype=obj -triple aarch64-unknown-unknown %s -o %t.o -# RUN: %clang %cflags %t.o -o %t.exe -Wl,-q -# RUN: llvm-bolt %t.exe -o %t.exe.bolt --no-threads --print-all | FileCheck %s --check-prefix=CHECK-BOLT - -# Check that the negate-ra-state at the start of bar is not discarded. -# If it was discarded, MarkRAState would report bar as having inconsistent RAStates. -# This is testing the handling of initialRAState on the BinaryFunction. -# CHECK-BOLT-NOT: BOLT-INFO: inconsistent RAStates in function foo -# CHECK-BOLT-NOT: BOLT-INFO: inconsistent RAStates in function bar - -# Check that OpNegateRAState CFIs are generated correctly. -# CHECK-BOLT: Binary Function "foo" after insert-negate-ra-state-pass { -# CHECK-BOLT: paciasp -# CHECK-BOLT-NEXT: OpNegateRAState - -# CHECK-BOLT: DWARF CFI Instructions: -# CHECK-BOLT-NEXT: 0: OpNegateRAState -# CHECK-BOLT-NEXT: End of Function "foo" - -# CHECK-BOLT: Binary Function "bar" after insert-negate-ra-state-pass { -# CHECK-BOLT: OpNegateRAState -# CHECK-BOLT-NEXT: mov x1, #0x0 -# CHECK-BOLT-NEXT: mov x1, #0x1 -# CHECK-BOLT-NEXT: autiasp -# CHECK-BOLT-NEXT: OpNegateRAState -# CHECK-BOLT-NEXT: ret - -# CHECK-BOLT: DWARF CFI Instructions: -# CHECK-BOLT-NEXT: 0: OpNegateRAState -# CHECK-BOLT-NEXT: 1: OpNegateRAState -# CHECK-BOLT-NEXT: End of Function "bar" - -# End of negate-ra-state insertion logs for foo and bar. -# CHECK: Binary Function "_start" after insert-negate-ra-state-pass { - -# Check that the functions are in the new .text section -# RUN: llvm-objdump %t.exe.bolt -d -j .text | FileCheck %s --check-prefix=CHECK-OBJDUMP -# CHECK-OBJDUMP: <foo>: -# CHECK-OBJDUMP: <bar>: - - - .text - .globl foo - .p2align 2 - .type foo,@function -foo: - .cfi_startproc - paciasp - .cfi_negate_ra_state - mov x1, #0 - b bar - .cfi_endproc - .size foo, .-foo - - - - .text - .globl bar - .p2align 2 - .type bar,@function -bar: - .cfi_startproc - .cfi_negate_ra_state // Indicating that RA is signed from the start of bar. - mov x1, #0 - mov x1, #1 - autiasp - .cfi_negate_ra_state - ret - .cfi_endproc - .size bar, .-bar diff --git a/bolt/test/AArch64/pacret-split-funcs.s b/bolt/test/AArch64/pacret-split-funcs.s deleted file mode 100644 index 27b34710..0000000 --- a/bolt/test/AArch64/pacret-split-funcs.s +++ /dev/null @@ -1,54 +0,0 @@ -# Checking that we generate an OpNegateRAState CFI after the split point, -# when splitting a region with signed RA state. -# We split at the fallthrough label. - -# REQUIRES: system-linux - -# RUN: %clang %s %cflags -march=armv8.3-a -Wl,-q -o %t -# RUN: link_fdata --no-lbr %s %t %t.fdata -# RUN: llvm-bolt %t -o %t.bolt --data %t.fdata -split-functions \ -# RUN: --print-only foo --print-split --print-all 2>&1 | FileCheck %s - -# Checking that we don't see any OpNegateRAState CFIs before the insertion pass. -# CHECK-NOT: OpNegateRAState -# CHECK: Binary Function "foo" after insert-negate-ra-state-pass - -# CHECK: paciasp -# CHECK-NEXT: OpNegateRAState - -# CHECK: ------- HOT-COLD SPLIT POINT ------- - -# CHECK: OpNegateRAState -# CHECK-NEXT: mov x0, #0x1 -# CHECK-NEXT: autiasp -# CHECK-NEXT: OpNegateRAState -# CHECK-NEXT: ret - -# End of the insert-negate-ra-state-pass logs -# CHECK: Binary Function "foo" after finalize-functions - - .text - .globl foo - .type foo, %function -foo: -.cfi_startproc -.entry_bb: -# FDATA: 1 foo #.entry_bb# 10 - paciasp - .cfi_negate_ra_state // indicating that paciasp changed the RA state to signed - cmp x0, #0 - b.eq .Lcold_bb1 -.Lfallthrough: // split point - mov x0, #1 - autiasp - .cfi_negate_ra_state // indicating that autiasp changed the RA state to unsigned - ret -.Lcold_bb1: // Instructions below are not important, they are just here so the cold block is not empty. - .cfi_negate_ra_state // ret has unsigned RA state, but the next inst (autiasp) has signed RA state - mov x0, #2 - retaa -.cfi_endproc - .size foo, .-foo - -## Force relocation mode. -.reloc 0, R_AARCH64_NONE diff --git a/bolt/test/runtime/AArch64/negate-ra-state.cpp b/bolt/test/runtime/AArch64/negate-ra-state.cpp deleted file mode 100644 index 60b0b08..0000000 --- a/bolt/test/runtime/AArch64/negate-ra-state.cpp +++ /dev/null @@ -1,26 +0,0 @@ -// REQUIRES: system-linux,bolt-runtime - -// RUN: %clangxx --target=aarch64-unknown-linux-gnu \ -// RUN: -mbranch-protection=pac-ret -Wl,-q %s -o %t.exe -// RUN: llvm-bolt %t.exe -o %t.bolt.exe -// RUN: %t.bolt.exe | FileCheck %s - -// CHECK: Exception caught: Exception from bar(). - -#include <cstdio> -#include <stdexcept> - -void bar() { throw std::runtime_error("Exception from bar()."); } - -void foo() { - try { - bar(); - } catch (const std::exception &e) { - printf("Exception caught: %s\n", e.what()); - } -} - -int main() { - foo(); - return 0; -} diff --git a/bolt/test/runtime/AArch64/pacret-function-split.cpp b/bolt/test/runtime/AArch64/pacret-function-split.cpp deleted file mode 100644 index 208fc5c..0000000 --- a/bolt/test/runtime/AArch64/pacret-function-split.cpp +++ /dev/null @@ -1,42 +0,0 @@ -/* This test check that the negate-ra-state CFIs are properly emitted in case of - function splitting. The test checks two things: - - we split at the correct location: to test the feature, - we need to split *before* the bl __cxa_throw@PLT call is made, - so the unwinder has to unwind from the split (cold) part. - - - the BOLTed binary runs, and returns the string from foo. - -# REQUIRES: system-linux,bolt-runtime - -# FDATA: 1 main #split# 1 _Z3foov 0 0 1 - -# RUN: %clangxx --target=aarch64-unknown-linux-gnu \ -# RUN: -mbranch-protection=pac-ret %s -o %t.exe -Wl,-q -# RUN: link_fdata %s %t.exe %t.fdata -# RUN: llvm-bolt %t.exe -o %t.bolt --split-functions --split-eh \ -# RUN: --split-strategy=profile2 --split-all-cold --print-split \ -# RUN: --print-only=_Z3foov --data=%t.fdata 2>&1 | FileCheck \ -# RUN: --check-prefix=BOLT-CHECK %s -# RUN: %t.bolt | FileCheck %s --check-prefix=RUN-CHECK - -# BOLT-CHECK-NOT: bl __cxa_throw@PLT -# BOLT-CHECK: ------- HOT-COLD SPLIT POINT ------- -# BOLT-CHECK: bl __cxa_throw@PLT - -# RUN-CHECK: Exception caught: Exception from foo(). -*/ - -#include <cstdio> -#include <stdexcept> - -void foo() { throw std::runtime_error("Exception from foo()."); } - -int main() { - try { - __asm__ __volatile__("split:"); - foo(); - } catch (const std::exception &e) { - printf("Exception caught: %s\n", e.what()); - } - return 0; -} diff --git a/clang/docs/ClangLinkerWrapper.rst b/clang/docs/ClangLinkerWrapper.rst index eb38d2b..28f48fc 100644 --- a/clang/docs/ClangLinkerWrapper.rst +++ b/clang/docs/ClangLinkerWrapper.rst @@ -14,10 +14,10 @@ This tool works as a wrapper of the normal host linking job. This tool is used to create linked device images for offloading and the necessary runtime calls to register them. It works by first scanning the linker's input for embedded device offloading data stored at the ``.llvm.offloading`` section. This section -contains binary data created by the :doc:`ClangOffloadPackager`. The extracted -device files will then be linked. The linked modules will then be wrapped into a -new object file containing the code necessary to register it with the offloading -runtime. +contains binary data created by the ``llvm-offload-binary`` utility. The +extracted device files will then be linked. The linked modules will then be +wrapped into a new object file containing the code necessary to register it with +the offloading runtime. Usage ===== diff --git a/clang/docs/OpenMPSupport.rst b/clang/docs/OpenMPSupport.rst index cf89e31a..90c0186 100644 --- a/clang/docs/OpenMPSupport.rst +++ b/clang/docs/OpenMPSupport.rst @@ -550,7 +550,7 @@ implementation. +-------------------------------------------------------------+---------------------------+---------------------------+--------------------------------------------------------------------------+
| OMP_AVAILABLE_DEVICES envirable | :none:`unclaimed` | :none:`unclaimed` | |
+-------------------------------------------------------------+---------------------------+---------------------------+--------------------------------------------------------------------------+
-| Traits for default device envirable | :none:`unclaimed` | :none:`unclaimed` | |
+| Traits for default device envirable | :part:`in progress` | :none:`unclaimed` | ro-i |
+-------------------------------------------------------------+---------------------------+---------------------------+--------------------------------------------------------------------------+
| Optionally omit array length expression | :good:`done` | :none:`unclaimed` | (Parse) https://github.com/llvm/llvm-project/pull/148048, |
| | | | (Sema) https://github.com/llvm/llvm-project/pull/152786 |
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 390e0fa..5e9a71e 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -126,6 +126,8 @@ AST Dumping Potentially Breaking Changes - Pretty-printing of templates with inherited (i.e. specified in a previous redeclaration) default arguments has been fixed. +- Default arguments of template template parameters are pretty-printed now. + Clang Frontend Potentially Breaking Changes ------------------------------------------- - Members of anonymous unions/structs are now injected as ``IndirectFieldDecl`` diff --git a/clang/docs/index.rst b/clang/docs/index.rst index be654af..e238518 100644 --- a/clang/docs/index.rst +++ b/clang/docs/index.rst @@ -101,7 +101,6 @@ Using Clang Tools ClangLinkerWrapper ClangNVLinkWrapper ClangOffloadBundler - ClangOffloadPackager ClangRepl ClangSYCLLinker diff --git a/clang/include/clang/AST/HLSLResource.h b/clang/include/clang/AST/HLSLResource.h index 9cdd81b..7440050 100644 --- a/clang/include/clang/AST/HLSLResource.h +++ b/clang/include/clang/AST/HLSLResource.h @@ -69,6 +69,11 @@ struct ResourceBindingAttrs { assert(hasImplicitOrderID()); return RegBinding->getImplicitBindingOrderID(); } + + void setImplicitOrderID(unsigned Value) const { + assert(hasBinding() && !isExplicit() && !hasImplicitOrderID()); + RegBinding->setImplicitBindingOrderID(Value); + } }; } // namespace hlsl diff --git a/clang/include/clang/Analysis/Analyses/LifetimeSafety.h b/clang/include/clang/Analysis/Analyses/LifetimeSafety.h index 512cb76..e54fc26 100644 --- a/clang/include/clang/Analysis/Analyses/LifetimeSafety.h +++ b/clang/include/clang/Analysis/Analyses/LifetimeSafety.h @@ -29,12 +29,18 @@ namespace clang::lifetimes { /// Enum to track the confidence level of a potential error. -enum class Confidence { +enum class Confidence : uint8_t { None, Maybe, // Reported as a potential error (-Wlifetime-safety-strict) Definite // Reported as a definite error (-Wlifetime-safety-permissive) }; +enum class LivenessKind : uint8_t { + Dead, // Not alive + Maybe, // Live on some path but not all paths (may-be-live) + Must // Live on all paths (must-be-live) +}; + class LifetimeSafetyReporter { public: LifetimeSafetyReporter() = default; @@ -55,6 +61,7 @@ class Fact; class FactManager; class LoanPropagationAnalysis; class ExpiredLoansAnalysis; +class LiveOriginAnalysis; struct LifetimeFactory; /// A generic, type-safe wrapper for an ID, distinguished by its `Tag` type. @@ -89,6 +96,7 @@ inline llvm::raw_ostream &operator<<(llvm::raw_ostream &OS, OriginID ID) { // TODO(opt): Consider using a bitset to represent the set of loans. using LoanSet = llvm::ImmutableSet<LoanID>; using OriginSet = llvm::ImmutableSet<OriginID>; +using OriginLoanMap = llvm::ImmutableMap<OriginID, LoanSet>; /// A `ProgramPoint` identifies a location in the CFG by pointing to a specific /// `Fact`. identified by a lifetime-related event (`Fact`). @@ -110,8 +118,16 @@ public: /// Returns the set of loans an origin holds at a specific program point. LoanSet getLoansAtPoint(OriginID OID, ProgramPoint PP) const; - /// Returns the set of loans that have expired at a specific program point. - std::vector<LoanID> getExpiredLoansAtPoint(ProgramPoint PP) const; + /// Returns the set of origins that are live at a specific program point, + /// along with the confidence level of their liveness. + /// + /// An origin is considered live if there are potential future uses of that + /// origin after the given program point. The confidence level indicates + /// whether the origin is definitely live (Definite) due to being domintated + /// by a set of uses or only possibly live (Maybe) only on some but not all + /// control flow paths. + std::vector<std::pair<OriginID, LivenessKind>> + getLiveOriginsAtPoint(ProgramPoint PP) const; /// Finds the OriginID for a given declaration. /// Returns a null optional if not found. @@ -138,7 +154,7 @@ private: std::unique_ptr<LifetimeFactory> Factory; std::unique_ptr<FactManager> FactMgr; std::unique_ptr<LoanPropagationAnalysis> LoanPropagation; - std::unique_ptr<ExpiredLoansAnalysis> ExpiredLoans; + std::unique_ptr<LiveOriginAnalysis> LiveOrigins; }; } // namespace internal } // namespace clang::lifetimes diff --git a/clang/include/clang/Basic/SanitizerSpecialCaseList.h b/clang/include/clang/Basic/SanitizerSpecialCaseList.h index cf74859..a05da4c 100644 --- a/clang/include/clang/Basic/SanitizerSpecialCaseList.h +++ b/clang/include/clang/Basic/SanitizerSpecialCaseList.h @@ -57,12 +57,10 @@ protected: void createSanitizerSections(); struct SanitizerSection { - SanitizerSection(SanitizerMask SM, SectionEntries &E, unsigned idx) - : Mask(SM), Entries(E), FileIdx(idx) {}; + SanitizerSection(SanitizerMask SM, const Section &S) : Mask(SM), S(S) {}; SanitizerMask Mask; - SectionEntries &Entries; - unsigned FileIdx; + const Section &S; }; std::vector<SanitizerSection> SanitizerSections; diff --git a/clang/include/clang/Basic/Sanitizers.def b/clang/include/clang/Basic/Sanitizers.def index 1d0e97c..da85431 100644 --- a/clang/include/clang/Basic/Sanitizers.def +++ b/clang/include/clang/Basic/Sanitizers.def @@ -195,6 +195,9 @@ SANITIZER_GROUP("bounds", Bounds, ArrayBounds | LocalBounds) // Scudo hardened allocator SANITIZER("scudo", Scudo) +// AllocToken +SANITIZER("alloc-token", AllocToken) + // Magic group, containing all sanitizers. For example, "-fno-sanitize=all" // can be used to disable all the sanitizers. SANITIZER_GROUP("all", All, ~SanitizerMask()) diff --git a/clang/include/clang/CIR/Dialect/IR/CIRAttrs.td b/clang/include/clang/CIR/Dialect/IR/CIRAttrs.td index 7714750..43832b7 100644 --- a/clang/include/clang/CIR/Dialect/IR/CIRAttrs.td +++ b/clang/include/clang/CIR/Dialect/IR/CIRAttrs.td @@ -602,6 +602,63 @@ def CIR_VTableAttr : CIR_Attr<"VTable", "vtable", [TypedAttrInterface]> { } //===----------------------------------------------------------------------===// +// DynamicCastInfoAttr +//===----------------------------------------------------------------------===// + +def CIR_DynamicCastInfoAttr : CIR_Attr<"DynamicCastInfo", "dyn_cast_info"> { + let summary = "ABI specific information about a dynamic cast"; + let description = [{ + Provide ABI specific information about a dynamic cast operation. + + The `src_rtti` and the `dest_rtti` parameters give the RTTI of the source + record type and the destination record type, respectively. + + The `runtime_func` parameter gives the `__dynamic_cast` function which is + provided by the runtime. The `bad_cast_func` parameter gives the + `__cxa_bad_cast` function which is also provided by the runtime. + + The `offset_hint` parameter gives the hint value that should be passed to + the `__dynamic_cast` runtime function. + }]; + + let parameters = (ins + CIR_GlobalViewAttr:$src_rtti, + CIR_GlobalViewAttr:$dest_rtti, + "mlir::FlatSymbolRefAttr":$runtime_func, + "mlir::FlatSymbolRefAttr":$bad_cast_func, + CIR_IntAttr:$offset_hint + ); + + let builders = [ + AttrBuilderWithInferredContext<(ins + "GlobalViewAttr":$src_rtti, + "GlobalViewAttr":$dest_rtti, + "mlir::FlatSymbolRefAttr":$runtime_func, + "mlir::FlatSymbolRefAttr":$bad_cast_func, + "IntAttr":$offset_hint), [{ + return $_get(src_rtti.getContext(), src_rtti, dest_rtti, runtime_func, + bad_cast_func, offset_hint); + }]>, + ]; + + let genVerifyDecl = 1; + let assemblyFormat = [{ + `<` + struct(qualified($src_rtti), + qualified($dest_rtti), + $runtime_func, + $bad_cast_func, + qualified($offset_hint)) + `>` + }]; + + let extraClassDeclaration = [{ + /// Get attribute alias name for this attribute. + std::string getAlias() const; + }]; +} + +//===----------------------------------------------------------------------===// // TargetAddressSpaceAttr //===----------------------------------------------------------------------===// diff --git a/clang/include/clang/CIR/Dialect/IR/CIROps.td b/clang/include/clang/CIR/Dialect/IR/CIROps.td index 66c4c04..27fe0cc 100644 --- a/clang/include/clang/CIR/Dialect/IR/CIROps.td +++ b/clang/include/clang/CIR/Dialect/IR/CIROps.td @@ -232,6 +232,100 @@ def CIR_CastOp : CIR_Op<"cast", [ }]; } +//===----------------------------------------------------------------------===// +// DynamicCastOp +//===----------------------------------------------------------------------===// + +def CIR_DynamicCastKind : CIR_I32EnumAttr< + "DynamicCastKind", "dynamic cast kind", [ + I32EnumAttrCase<"Ptr", 0, "ptr">, + I32EnumAttrCase<"Ref", 1, "ref"> +]>; + +def CIR_DynamicCastOp : CIR_Op<"dyn_cast"> { + let summary = "Perform dynamic cast on record pointers"; + let description = [{ + The `cir.dyn_cast` operation models part of the semantics of the + `dynamic_cast` operator in C++. It can be used to perform 3 kinds of casts + on record pointers: + + - Down-cast, which casts a base class pointer to a derived class pointer; + - Side-cast, which casts a class pointer to a sibling class pointer; + - Cast-to-complete, which casts a class pointer to a void pointer. + + The input of the operation must be a record pointer. The result of the + operation is either a record pointer or a void pointer. + + The parameter `kind` specifies the semantics of this operation. If its value + is `ptr`, then the operation models dynamic casts on pointers. Otherwise, if + its value is `ref`, the operation models dynamic casts on references. + Specifically: + + - When the input pointer is a null pointer value: + - If `kind` is `ref`, the operation will invoke undefined behavior. A + sanitizer check will be emitted if sanitizer is on. + - Otherwise, the operation will return a null pointer value as its result. + - When the runtime type check fails: + - If `kind` is `ref`, the operation will throw a `bad_cast` exception. + - Otherwise, the operation will return a null pointer value as its result. + + The `info` argument gives detailed information about the requested dynamic + cast operation. It is an optional `#cir.dyn_cast_info` attribute that is + only present when the operation models a down-cast or a side-cast. + + The `relative_layout` argument specifies whether the Itanium C++ ABI vtable + uses relative layout. It is only meaningful when the operation models a + cast-to-complete operation. + + Examples: + + ```mlir + %0 = cir.dyn_cast ptr %p : !cir.ptr<!rec_Base> -> !cir.ptr<!rec_Derived> + %1 = cir.dyn_cast ptr relative_layout %p : !cir.ptr<!rec_Base> + -> !cir.ptr<!rec_Derived> + %2 = cir.dyn_cast ref %r : !cir.ptr<!rec_Base> -> !cir.ptr<!rec_Derived> + #cir.dyn_cast_info< + srcRtti = #cir.global_view<@_ZTI4Base> : !cir.ptr<!u8i>, + destRtti = #cir.global_view<@_ZTI7Derived> : !cir.ptr<!u8i>, + runtimeFunc = @__dynamic_cast, + badCastFunc = @__cxa_bad_cast, + offsetHint = #cir.int<0> : !s64i + > + ``` + }]; + + let arguments = (ins + CIR_DynamicCastKind:$kind, + CIR_PtrToRecordType:$src, + OptionalAttr<CIR_DynamicCastInfoAttr>:$info, + UnitAttr:$relative_layout + ); + + let results = (outs + CIR_PtrToAnyOf<[CIR_VoidType, CIR_RecordType]>:$result + ); + + let assemblyFormat = [{ + $kind (`relative_layout` $relative_layout^)? $src + `:` qualified(type($src)) `->` qualified(type($result)) + (qualified($info)^)? attr-dict + }]; + + let extraClassDeclaration = [{ + /// Determine whether this operation models reference casting in C++. + bool isRefCast() { + return getKind() == ::cir::DynamicCastKind::Ref; + } + + /// Determine whether this operation represents a dynamic cast to a void + /// pointer. + bool isCastToVoid() { + return getType().isVoidPtr(); + } + }]; + + let hasLLVMLowering = false; +} //===----------------------------------------------------------------------===// // PtrStrideOp diff --git a/clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td b/clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td index a1ebd6c..b2c146c 100644 --- a/clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td +++ b/clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td @@ -178,6 +178,12 @@ def CIR_AnyComplexOrIntOrBoolOrFloatType } //===----------------------------------------------------------------------===// +// Record Type predicates +//===----------------------------------------------------------------------===// + +def CIR_AnyRecordType : CIR_TypeBase<"::cir::RecordType", "record type">; + +//===----------------------------------------------------------------------===// // Array Type predicates //===----------------------------------------------------------------------===// @@ -234,6 +240,8 @@ def CIR_PtrToIntOrFloatType : CIR_PtrToType<CIR_AnyIntOrFloatType>; def CIR_PtrToComplexType : CIR_PtrToType<CIR_AnyComplexType>; +def CIR_PtrToRecordType : CIR_PtrToType<CIR_AnyRecordType>; + def CIR_PtrToArray : CIR_PtrToType<CIR_AnyArrayType>; //===----------------------------------------------------------------------===// diff --git a/clang/lib/AST/DeclPrinter.cpp b/clang/lib/AST/DeclPrinter.cpp index 7001ade..7f3dcca 100644 --- a/clang/lib/AST/DeclPrinter.cpp +++ b/clang/lib/AST/DeclPrinter.cpp @@ -111,6 +111,7 @@ namespace { void VisitOMPCapturedExprDecl(OMPCapturedExprDecl *D); void VisitTemplateTypeParmDecl(const TemplateTypeParmDecl *TTP); void VisitNonTypeTemplateParmDecl(const NonTypeTemplateParmDecl *NTTP); + void VisitTemplateTemplateParmDecl(const TemplateTemplateParmDecl *); void VisitHLSLBufferDecl(HLSLBufferDecl *D); void VisitOpenACCDeclareDecl(OpenACCDeclareDecl *D); @@ -1189,8 +1190,7 @@ void DeclPrinter::printTemplateParameters(const TemplateParameterList *Params, } else if (auto NTTP = dyn_cast<NonTypeTemplateParmDecl>(Param)) { VisitNonTypeTemplateParmDecl(NTTP); } else if (auto TTPD = dyn_cast<TemplateTemplateParmDecl>(Param)) { - VisitTemplateDecl(TTPD); - // FIXME: print the default argument, if present. + VisitTemplateTemplateParmDecl(TTPD); } } @@ -1916,6 +1916,16 @@ void DeclPrinter::VisitNonTypeTemplateParmDecl( } } +void DeclPrinter::VisitTemplateTemplateParmDecl( + const TemplateTemplateParmDecl *TTPD) { + VisitTemplateDecl(TTPD); + if (TTPD->hasDefaultArgument() && !TTPD->defaultArgumentWasInherited()) { + Out << " = "; + TTPD->getDefaultArgument().getArgument().print(Policy, Out, + /*IncludeType=*/false); + } +} + void DeclPrinter::VisitOpenACCDeclareDecl(OpenACCDeclareDecl *D) { if (!D->isInvalidDecl()) { Out << "#pragma acc declare"; diff --git a/clang/lib/Analysis/LifetimeSafety.cpp b/clang/lib/Analysis/LifetimeSafety.cpp index c18b8fb..6196ec3 100644 --- a/clang/lib/Analysis/LifetimeSafety.cpp +++ b/clang/lib/Analysis/LifetimeSafety.cpp @@ -19,12 +19,13 @@ #include "llvm/ADT/ImmutableMap.h" #include "llvm/ADT/ImmutableSet.h" #include "llvm/ADT/PointerUnion.h" -#include "llvm/ADT/SmallBitVector.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TimeProfiler.h" #include <cstdint> #include <memory> +#include <optional> namespace clang::lifetimes { namespace internal { @@ -872,22 +873,19 @@ public: InStates[Start] = D.getInitialState(); W.enqueueBlock(Start); - llvm::SmallBitVector Visited(Cfg.getNumBlockIDs() + 1); - while (const CFGBlock *B = W.dequeue()) { - Lattice StateIn = getInState(B); + Lattice StateIn = *getInState(B); Lattice StateOut = transferBlock(B, StateIn); OutStates[B] = StateOut; - Visited.set(B->getBlockID()); for (const CFGBlock *AdjacentB : isForward() ? B->succs() : B->preds()) { if (!AdjacentB) continue; - Lattice OldInState = getInState(AdjacentB); - Lattice NewInState = D.join(OldInState, StateOut); + std::optional<Lattice> OldInState = getInState(AdjacentB); + Lattice NewInState = + !OldInState ? StateOut : D.join(*OldInState, StateOut); // Enqueue the adjacent block if its in-state has changed or if we have - // never visited it. - if (!Visited.test(AdjacentB->getBlockID()) || - NewInState != OldInState) { + // never seen it. + if (!OldInState || NewInState != *OldInState) { InStates[AdjacentB] = NewInState; W.enqueueBlock(AdjacentB); } @@ -898,7 +896,12 @@ public: protected: Lattice getState(ProgramPoint P) const { return PerPointStates.lookup(P); } - Lattice getInState(const CFGBlock *B) const { return InStates.lookup(B); } + std::optional<Lattice> getInState(const CFGBlock *B) const { + auto It = InStates.find(B); + if (It == InStates.end()) + return std::nullopt; + return It->second; + } Lattice getOutState(const CFGBlock *B) const { return OutStates.lookup(B); } @@ -974,19 +977,21 @@ static llvm::ImmutableSet<T> join(llvm::ImmutableSet<T> A, return A; } -/// Checks if set A is a subset of set B. -template <typename T> -static bool isSubsetOf(const llvm::ImmutableSet<T> &A, - const llvm::ImmutableSet<T> &B) { - // Empty set is a subset of all sets. - if (A.isEmpty()) - return true; - - for (const T &Elem : A) - if (!B.contains(Elem)) - return false; - return true; -} +/// Describes the strategy for joining two `ImmutableMap` instances, primarily +/// differing in how they handle keys that are unique to one of the maps. +/// +/// A `Symmetric` join is universally correct, while an `Asymmetric` join +/// serves as a performance optimization. The latter is applicable only when the +/// join operation possesses a left identity element, allowing for a more +/// efficient, one-sided merge. +enum class JoinKind { + /// A symmetric join applies the `JoinValues` operation to keys unique to + /// either map, ensuring that values from both maps contribute to the result. + Symmetric, + /// An asymmetric join preserves keys unique to the first map as-is, while + /// applying the `JoinValues` operation only to keys unique to the second map. + Asymmetric, +}; /// Computes the key-wise union of two ImmutableMaps. // TODO(opt): This key-wise join is a performance bottleneck. A more @@ -994,22 +999,29 @@ static bool isSubsetOf(const llvm::ImmutableSet<T> &A, // instead of the current AVL-tree-based ImmutableMap. template <typename K, typename V, typename Joiner> static llvm::ImmutableMap<K, V> -join(llvm::ImmutableMap<K, V> A, llvm::ImmutableMap<K, V> B, - typename llvm::ImmutableMap<K, V>::Factory &F, Joiner JoinValues) { +join(const llvm::ImmutableMap<K, V> &A, const llvm::ImmutableMap<K, V> &B, + typename llvm::ImmutableMap<K, V>::Factory &F, Joiner JoinValues, + JoinKind Kind) { if (A.getHeight() < B.getHeight()) - std::swap(A, B); + return join(B, A, F, JoinValues, Kind); // For each element in B, join it with the corresponding element in A // (or with an empty value if it doesn't exist in A). + llvm::ImmutableMap<K, V> Res = A; for (const auto &Entry : B) { const K &Key = Entry.first; const V &ValB = Entry.second; - if (const V *ValA = A.lookup(Key)) - A = F.add(A, Key, JoinValues(*ValA, ValB)); - else - A = F.add(A, Key, ValB); + Res = F.add(Res, Key, JoinValues(A.lookup(Key), &ValB)); + } + if (Kind == JoinKind::Symmetric) { + for (const auto &Entry : A) { + const K &Key = Entry.first; + const V &ValA = Entry.second; + if (!B.contains(Key)) + Res = F.add(Res, Key, JoinValues(&ValA, nullptr)); + } } - return A; + return Res; } } // namespace utils @@ -1017,19 +1029,6 @@ join(llvm::ImmutableMap<K, V> A, llvm::ImmutableMap<K, V> B, // Loan Propagation Analysis // ========================================================================= // -using OriginLoanMap = llvm::ImmutableMap<OriginID, LoanSet>; -using ExpiredLoanMap = llvm::ImmutableMap<LoanID, const ExpireFact *>; - -/// An object to hold the factories for immutable collections, ensuring -/// that all created states share the same underlying memory management. -struct LifetimeFactory { - llvm::BumpPtrAllocator Allocator; - OriginLoanMap::Factory OriginMapFactory{Allocator, /*canonicalize=*/false}; - LoanSet::Factory LoanSetFactory{Allocator, /*canonicalize=*/false}; - ExpiredLoanMap::Factory ExpiredLoanMapFactory{Allocator, - /*canonicalize=*/false}; -}; - /// Represents the dataflow lattice for loan propagation. /// /// This lattice tracks which loans each origin may hold at a given program @@ -1073,10 +1072,10 @@ class LoanPropagationAnalysis public: LoanPropagationAnalysis(const CFG &C, AnalysisDeclContext &AC, FactManager &F, - LifetimeFactory &LFactory) - : DataflowAnalysis(C, AC, F), - OriginLoanMapFactory(LFactory.OriginMapFactory), - LoanSetFactory(LFactory.LoanSetFactory) {} + OriginLoanMap::Factory &OriginLoanMapFactory, + LoanSet::Factory &LoanSetFactory) + : DataflowAnalysis(C, AC, F), OriginLoanMapFactory(OriginLoanMapFactory), + LoanSetFactory(LoanSetFactory) {} using Base::transfer; @@ -1087,11 +1086,19 @@ public: /// Merges two lattices by taking the union of loans for each origin. // TODO(opt): Keep the state small by removing origins which become dead. Lattice join(Lattice A, Lattice B) { - OriginLoanMap JoinedOrigins = - utils::join(A.Origins, B.Origins, OriginLoanMapFactory, - [&](LoanSet S1, LoanSet S2) { - return utils::join(S1, S2, LoanSetFactory); - }); + OriginLoanMap JoinedOrigins = utils::join( + A.Origins, B.Origins, OriginLoanMapFactory, + [&](const LoanSet *S1, const LoanSet *S2) { + assert((S1 || S2) && "unexpectedly merging 2 empty sets"); + if (!S1) + return *S2; + if (!S2) + return *S1; + return utils::join(*S1, *S2, LoanSetFactory); + }, + // Asymmetric join is a performance win. For origins present only on one + // branch, the loan set can be carried over as-is. + utils::JoinKind::Asymmetric); return Lattice(JoinedOrigins); } @@ -1120,12 +1127,12 @@ public: OriginLoanMapFactory.add(In.Origins, DestOID, MergedLoans)); } - LoanSet getLoans(OriginID OID, ProgramPoint P) { + LoanSet getLoans(OriginID OID, ProgramPoint P) const { return getLoans(getState(P), OID); } private: - LoanSet getLoans(Lattice L, OriginID OID) { + LoanSet getLoans(Lattice L, OriginID OID) const { if (auto *Loans = L.Origins.lookup(OID)) return *Loans; return LoanSetFactory.getEmptySet(); @@ -1133,96 +1140,195 @@ private: }; // ========================================================================= // -// Expired Loans Analysis +// Live Origins Analysis +// ========================================================================= // +// +// A backward dataflow analysis that determines which origins are "live" at each +// program point. An origin is "live" at a program point if there's a potential +// future use of the pointer it represents. Liveness is "generated" by a read of +// origin's loan set (e.g., a `UseFact`) and is "killed" (i.e., it stops being +// live) when its loan set is overwritten (e.g. a OriginFlow killing the +// destination origin). +// +// This information is used for detecting use-after-free errors, as it allows us +// to check if a live origin holds a loan to an object that has already expired. // ========================================================================= // -/// The dataflow lattice for tracking the set of expired loans. -struct ExpiredLattice { - /// Map from an expired `LoanID` to the `ExpireFact` that made it expire. - ExpiredLoanMap Expired; +/// Information about why an origin is live at a program point. +struct LivenessInfo { + /// The use that makes the origin live. If liveness is propagated from + /// multiple uses along different paths, this will point to the use appearing + /// earlier in the translation unit. + /// This is 'null' when the origin is not live. + const UseFact *CausingUseFact; + /// The kind of liveness of the origin. + /// `Must`: The origin is live on all control-flow paths from the current + /// point to the function's exit (i.e. the current point is dominated by a set + /// of uses). + /// `Maybe`: indicates it is live on some but not all paths. + /// + /// This determines the diagnostic's confidence level. + /// `Must`-be-alive at expiration implies a definite use-after-free, + /// while `Maybe`-be-alive suggests a potential one on some paths. + LivenessKind Kind; + + LivenessInfo() : CausingUseFact(nullptr), Kind(LivenessKind::Dead) {} + LivenessInfo(const UseFact *UF, LivenessKind K) + : CausingUseFact(UF), Kind(K) {} + + bool operator==(const LivenessInfo &Other) const { + return CausingUseFact == Other.CausingUseFact && Kind == Other.Kind; + } + bool operator!=(const LivenessInfo &Other) const { return !(*this == Other); } + + void Profile(llvm::FoldingSetNodeID &IDBuilder) const { + IDBuilder.AddPointer(CausingUseFact); + IDBuilder.Add(Kind); + } +}; + +using LivenessMap = llvm::ImmutableMap<OriginID, LivenessInfo>; - ExpiredLattice() : Expired(nullptr) {}; - explicit ExpiredLattice(ExpiredLoanMap M) : Expired(M) {} +/// The dataflow lattice for origin liveness analysis. +/// It tracks which origins are live, why they're live (which UseFact), +/// and the confidence level of that liveness. +struct LivenessLattice { + LivenessMap LiveOrigins; - bool operator==(const ExpiredLattice &Other) const { - return Expired == Other.Expired; + LivenessLattice() : LiveOrigins(nullptr) {}; + + explicit LivenessLattice(LivenessMap L) : LiveOrigins(L) {} + + bool operator==(const LivenessLattice &Other) const { + return LiveOrigins == Other.LiveOrigins; } - bool operator!=(const ExpiredLattice &Other) const { + + bool operator!=(const LivenessLattice &Other) const { return !(*this == Other); } - void dump(llvm::raw_ostream &OS) const { - OS << "ExpiredLattice State:\n"; - if (Expired.isEmpty()) + void dump(llvm::raw_ostream &OS, const OriginManager &OM) const { + if (LiveOrigins.isEmpty()) OS << " <empty>\n"; - for (const auto &[ID, _] : Expired) - OS << " Loan " << ID << " is expired\n"; + for (const auto &Entry : LiveOrigins) { + OriginID OID = Entry.first; + const LivenessInfo &Info = Entry.second; + OS << " "; + OM.dump(OID, OS); + OS << " is "; + switch (Info.Kind) { + case LivenessKind::Must: + OS << "definitely"; + break; + case LivenessKind::Maybe: + OS << "maybe"; + break; + case LivenessKind::Dead: + llvm_unreachable("liveness kind of live origins should not be dead."); + } + OS << " live at this point\n"; + } } }; -/// The analysis that tracks which loans have expired. -class ExpiredLoansAnalysis - : public DataflowAnalysis<ExpiredLoansAnalysis, ExpiredLattice, - Direction::Forward> { - - ExpiredLoanMap::Factory &Factory; +/// The analysis that tracks which origins are live, with granular information +/// about the causing use fact and confidence level. This is a backward +/// analysis. +class LiveOriginAnalysis + : public DataflowAnalysis<LiveOriginAnalysis, LivenessLattice, + Direction::Backward> { + FactManager &FactMgr; + LivenessMap::Factory &Factory; public: - ExpiredLoansAnalysis(const CFG &C, AnalysisDeclContext &AC, FactManager &F, - LifetimeFactory &Factory) - : DataflowAnalysis(C, AC, F), Factory(Factory.ExpiredLoanMapFactory) {} - - using Base::transfer; + LiveOriginAnalysis(const CFG &C, AnalysisDeclContext &AC, FactManager &F, + LivenessMap::Factory &SF) + : DataflowAnalysis(C, AC, F), FactMgr(F), Factory(SF) {} + using DataflowAnalysis<LiveOriginAnalysis, Lattice, + Direction::Backward>::transfer; - StringRef getAnalysisName() const { return "ExpiredLoans"; } + StringRef getAnalysisName() const { return "LiveOrigins"; } Lattice getInitialState() { return Lattice(Factory.getEmptyMap()); } - /// Merges two lattices by taking the union of the two expired loans. - Lattice join(Lattice L1, Lattice L2) { - return Lattice( - utils::join(L1.Expired, L2.Expired, Factory, - // Take the last expiry fact to make this hermetic. - [](const ExpireFact *F1, const ExpireFact *F2) { - return F1->getExpiryLoc() > F2->getExpiryLoc() ? F1 : F2; - })); - } - - Lattice transfer(Lattice In, const ExpireFact &F) { - return Lattice(Factory.add(In.Expired, F.getLoanID(), &F)); - } - - // Removes the loan from the set of expired loans. - // - // When a loan is re-issued (e.g., in a loop), it is no longer considered - // expired. A loan can be in the expired set at the point of issue due to - // the dataflow state from a previous loop iteration being propagated along - // a backedge in the CFG. - // - // Note: This has a subtle false-negative though where a loan from previous - // iteration is not overwritten by a reissue. This needs careful tracking - // of loans "across iterations" which can be considered for future - // enhancements. - // - // void foo(int safe) { - // int* p = &safe; - // int* q = &safe; - // while (condition()) { - // int x = 1; - // p = &x; // A loan to 'x' is issued to 'p' in every iteration. - // if (condition()) { - // q = p; - // } - // (void)*p; // OK — 'p' points to 'x' from new iteration. - // (void)*q; // UaF - 'q' still points to 'x' from previous iteration - // // which is now destroyed. - // } - // } - Lattice transfer(Lattice In, const IssueFact &F) { - return Lattice(Factory.remove(In.Expired, F.getLoanID())); + /// Merges two lattices by combining liveness information. + /// When the same origin has different confidence levels, we take the lower + /// one. + Lattice join(Lattice L1, Lattice L2) const { + LivenessMap Merged = L1.LiveOrigins; + // Take the earliest UseFact to make the join hermetic and commutative. + auto CombineUseFact = [](const UseFact &A, + const UseFact &B) -> const UseFact * { + return A.getUseExpr()->getExprLoc() < B.getUseExpr()->getExprLoc() ? &A + : &B; + }; + auto CombineLivenessKind = [](LivenessKind K1, + LivenessKind K2) -> LivenessKind { + assert(K1 != LivenessKind::Dead && "LivenessKind should not be dead."); + assert(K2 != LivenessKind::Dead && "LivenessKind should not be dead."); + // Only return "Must" if both paths are "Must", otherwise Maybe. + if (K1 == LivenessKind::Must && K2 == LivenessKind::Must) + return LivenessKind::Must; + return LivenessKind::Maybe; + }; + auto CombineLivenessInfo = [&](const LivenessInfo *L1, + const LivenessInfo *L2) -> LivenessInfo { + assert((L1 || L2) && "unexpectedly merging 2 empty sets"); + if (!L1) + return LivenessInfo(L2->CausingUseFact, LivenessKind::Maybe); + if (!L2) + return LivenessInfo(L1->CausingUseFact, LivenessKind::Maybe); + return LivenessInfo( + CombineUseFact(*L1->CausingUseFact, *L2->CausingUseFact), + CombineLivenessKind(L1->Kind, L2->Kind)); + }; + return Lattice(utils::join( + L1.LiveOrigins, L2.LiveOrigins, Factory, CombineLivenessInfo, + // A symmetric join is required here. If an origin is live on one + // branch but not the other, its confidence must be demoted to `Maybe`. + utils::JoinKind::Symmetric)); + } + + /// A read operation makes the origin live with definite confidence, as it + /// dominates this program point. A write operation kills the liveness of + /// the origin since it overwrites the value. + Lattice transfer(Lattice In, const UseFact &UF) { + OriginID OID = UF.getUsedOrigin(FactMgr.getOriginMgr()); + // Write kills liveness. + if (UF.isWritten()) + return Lattice(Factory.remove(In.LiveOrigins, OID)); + // Read makes origin live with definite confidence (dominates this point). + return Lattice(Factory.add(In.LiveOrigins, OID, + LivenessInfo(&UF, LivenessKind::Must))); + } + + /// Issuing a new loan to an origin kills its liveness. + Lattice transfer(Lattice In, const IssueFact &IF) { + return Lattice(Factory.remove(In.LiveOrigins, IF.getOriginID())); } - ExpiredLoanMap getExpiredLoans(ProgramPoint P) { return getState(P).Expired; } + /// An OriginFlow kills the liveness of the destination origin if `KillDest` + /// is true. Otherwise, it propagates liveness from destination to source. + Lattice transfer(Lattice In, const OriginFlowFact &OF) { + if (!OF.getKillDest()) + return In; + return Lattice(Factory.remove(In.LiveOrigins, OF.getDestOriginID())); + } + + LivenessMap getLiveOrigins(ProgramPoint P) const { + return getState(P).LiveOrigins; + } + + // Dump liveness values on all test points in the program. + void dump(llvm::raw_ostream &OS, const LifetimeSafetyAnalysis &LSA) const { + llvm::dbgs() << "==========================================\n"; + llvm::dbgs() << getAnalysisName() << " results:\n"; + llvm::dbgs() << "==========================================\n"; + for (const auto &Entry : LSA.getTestPoints()) { + OS << "TestPoint: " << Entry.getKey() << "\n"; + getState(Entry.getValue()).dump(OS, FactMgr.getOriginMgr()); + } + } }; // ========================================================================= // @@ -1240,84 +1346,75 @@ class LifetimeChecker { private: llvm::DenseMap<LoanID, PendingWarning> FinalWarningsMap; LoanPropagationAnalysis &LoanPropagation; - ExpiredLoansAnalysis &ExpiredLoans; + LiveOriginAnalysis &LiveOrigins; FactManager &FactMgr; AnalysisDeclContext &ADC; LifetimeSafetyReporter *Reporter; public: - LifetimeChecker(LoanPropagationAnalysis &LPA, ExpiredLoansAnalysis &ELA, + LifetimeChecker(LoanPropagationAnalysis &LPA, LiveOriginAnalysis &LOA, FactManager &FM, AnalysisDeclContext &ADC, LifetimeSafetyReporter *Reporter) - : LoanPropagation(LPA), ExpiredLoans(ELA), FactMgr(FM), ADC(ADC), + : LoanPropagation(LPA), LiveOrigins(LOA), FactMgr(FM), ADC(ADC), Reporter(Reporter) {} void run() { llvm::TimeTraceScope TimeProfile("LifetimeChecker"); for (const CFGBlock *B : *ADC.getAnalysis<PostOrderCFGView>()) for (const Fact *F : FactMgr.getFacts(B)) - if (const auto *UF = F->getAs<UseFact>()) - checkUse(UF); + if (const auto *EF = F->getAs<ExpireFact>()) + checkExpiry(EF); issuePendingWarnings(); } - /// Checks for use-after-free errors for a given use of an Origin. + /// Checks for use-after-free errors when a loan expires. /// - /// This method is called for each 'UseFact' identified in the control flow - /// graph. It determines if the loans held by the used origin have expired - /// at the point of use. - void checkUse(const UseFact *UF) { - if (UF->isWritten()) - return; - OriginID O = UF->getUsedOrigin(FactMgr.getOriginMgr()); - - // Get the set of loans that the origin might hold at this program point. - LoanSet HeldLoans = LoanPropagation.getLoans(O, UF); - - // Get the set of all loans that have expired at this program point. - ExpiredLoanMap AllExpiredLoans = ExpiredLoans.getExpiredLoans(UF); - - // If the pointer holds no loans or no loans have expired, there's nothing - // to check. - if (HeldLoans.isEmpty() || AllExpiredLoans.isEmpty()) - return; - - // Identify loans that which have expired but are held by the pointer. Using - // them is a use-after-free. - llvm::SmallVector<LoanID> DefaultedLoans; - // A definite UaF error occurs if all loans the origin might hold have - // expired. - bool IsDefiniteError = true; - for (LoanID L : HeldLoans) { - if (AllExpiredLoans.contains(L)) - DefaultedLoans.push_back(L); - else - // If at least one loan is not expired, this use is not a definite UaF. - IsDefiniteError = false; + /// This method examines all live origins at the expiry point and determines + /// if any of them hold the expiring loan. If so, it creates a pending + /// warning with the appropriate confidence level based on the liveness + /// information. The confidence reflects whether the origin is definitely + /// or maybe live at this point. + /// + /// Note: This implementation considers only the confidence of origin + /// liveness. Future enhancements could also consider the confidence of loan + /// propagation (e.g., a loan may only be held on some execution paths). + void checkExpiry(const ExpireFact *EF) { + LoanID ExpiredLoan = EF->getLoanID(); + LivenessMap Origins = LiveOrigins.getLiveOrigins(EF); + Confidence CurConfidence = Confidence::None; + const UseFact *BadUse = nullptr; + for (auto &[OID, LiveInfo] : Origins) { + LoanSet HeldLoans = LoanPropagation.getLoans(OID, EF); + if (!HeldLoans.contains(ExpiredLoan)) + continue; + // Loan is defaulted. + Confidence NewConfidence = livenessKindToConfidence(LiveInfo.Kind); + if (CurConfidence < NewConfidence) { + CurConfidence = NewConfidence; + BadUse = LiveInfo.CausingUseFact; + } } - // If there are no defaulted loans, the use is safe. - if (DefaultedLoans.empty()) + if (!BadUse) return; - - // Determine the confidence level of the error (definite or maybe). - Confidence CurrentConfidence = - IsDefiniteError ? Confidence::Definite : Confidence::Maybe; - - // For each expired loan, create a pending warning. - for (LoanID DefaultedLoan : DefaultedLoans) { - // If we already have a warning for this loan with a higher or equal - // confidence, skip this one. - if (FinalWarningsMap.count(DefaultedLoan) && - CurrentConfidence <= FinalWarningsMap[DefaultedLoan].ConfidenceLevel) - continue; - - auto *EF = AllExpiredLoans.lookup(DefaultedLoan); - assert(EF && "Could not find ExpireFact for an expired loan."); - - FinalWarningsMap[DefaultedLoan] = {/*ExpiryLoc=*/(*EF)->getExpiryLoc(), - /*UseExpr=*/UF->getUseExpr(), - /*ConfidenceLevel=*/CurrentConfidence}; + // We have a use-after-free. + Confidence LastConf = FinalWarningsMap.lookup(ExpiredLoan).ConfidenceLevel; + if (LastConf >= CurConfidence) + return; + FinalWarningsMap[ExpiredLoan] = {/*ExpiryLoc=*/EF->getExpiryLoc(), + /*UseExpr=*/BadUse->getUseExpr(), + /*ConfidenceLevel=*/CurConfidence}; + } + + static Confidence livenessKindToConfidence(LivenessKind K) { + switch (K) { + case LivenessKind::Must: + return Confidence::Definite; + case LivenessKind::Maybe: + return Confidence::Maybe; + case LivenessKind::Dead: + return Confidence::None; } + llvm_unreachable("unknown liveness kind"); } void issuePendingWarnings() { @@ -1336,6 +1433,15 @@ public: // LifetimeSafetyAnalysis Class Implementation // ========================================================================= // +/// An object to hold the factories for immutable collections, ensuring +/// that all created states share the same underlying memory management. +struct LifetimeFactory { + llvm::BumpPtrAllocator Allocator; + OriginLoanMap::Factory OriginMapFactory{Allocator, /*canonicalize=*/false}; + LoanSet::Factory LoanSetFactory{Allocator, /*canonicalize=*/false}; + LivenessMap::Factory LivenessMapFactory{Allocator, /*canonicalize=*/false}; +}; + // We need this here for unique_ptr with forward declared class. LifetimeSafetyAnalysis::~LifetimeSafetyAnalysis() = default; @@ -1366,15 +1472,16 @@ void LifetimeSafetyAnalysis::run() { /// the analysis. /// 3. Collapse ExpireFacts belonging to same source location into a single /// Fact. - LoanPropagation = - std::make_unique<LoanPropagationAnalysis>(Cfg, AC, *FactMgr, *Factory); + LoanPropagation = std::make_unique<LoanPropagationAnalysis>( + Cfg, AC, *FactMgr, Factory->OriginMapFactory, Factory->LoanSetFactory); LoanPropagation->run(); - ExpiredLoans = - std::make_unique<ExpiredLoansAnalysis>(Cfg, AC, *FactMgr, *Factory); - ExpiredLoans->run(); + LiveOrigins = std::make_unique<LiveOriginAnalysis>( + Cfg, AC, *FactMgr, Factory->LivenessMapFactory); + LiveOrigins->run(); + DEBUG_WITH_TYPE("LiveOrigins", LiveOrigins->dump(llvm::dbgs(), *this)); - LifetimeChecker Checker(*LoanPropagation, *ExpiredLoans, *FactMgr, AC, + LifetimeChecker Checker(*LoanPropagation, *LiveOrigins, *FactMgr, AC, Reporter); Checker.run(); } @@ -1385,15 +1492,6 @@ LoanSet LifetimeSafetyAnalysis::getLoansAtPoint(OriginID OID, return LoanPropagation->getLoans(OID, PP); } -std::vector<LoanID> -LifetimeSafetyAnalysis::getExpiredLoansAtPoint(ProgramPoint PP) const { - assert(ExpiredLoans && "ExpiredLoansAnalysis has not been run."); - std::vector<LoanID> Result; - for (const auto &pair : ExpiredLoans->getExpiredLoans(PP)) - Result.push_back(pair.first); - return Result; -} - std::optional<OriginID> LifetimeSafetyAnalysis::getOriginIDForDecl(const ValueDecl *D) const { assert(FactMgr && "FactManager not initialized"); @@ -1413,6 +1511,15 @@ LifetimeSafetyAnalysis::getLoanIDForVar(const VarDecl *VD) const { return Result; } +std::vector<std::pair<OriginID, LivenessKind>> +LifetimeSafetyAnalysis::getLiveOriginsAtPoint(ProgramPoint PP) const { + assert(LiveOrigins && "LiveOriginAnalysis has not been run."); + std::vector<std::pair<OriginID, LivenessKind>> Result; + for (auto &[OID, Info] : LiveOrigins->getLiveOrigins(PP)) + Result.push_back({OID, Info.Kind}); + return Result; +} + llvm::StringMap<ProgramPoint> LifetimeSafetyAnalysis::getTestPoints() const { assert(FactMgr && "FactManager not initialized"); llvm::StringMap<ProgramPoint> AnnotationToPointMap; diff --git a/clang/lib/Analysis/LifetimeSafety.md b/clang/lib/Analysis/LifetimeSafety.md new file mode 100644 index 0000000..3f3d03d --- /dev/null +++ b/clang/lib/Analysis/LifetimeSafety.md @@ -0,0 +1,230 @@ +Excellent! This is a very strong and logical structure for the white paper. It follows a clear narrative, starting from the high-level problem and progressively diving into the specifics of your solution. The sections on why a traditional borrow checker doesn't fit C++ and the open questions are particularly good, as they show a deep engagement with the problem space. + +Here is a draft of the white paper following your new skeleton, with the details filled in based on my analysis of your implementation and the provided reference documents. I've also incorporated some of my own suggestions to enhance the flow and clarity. + +*** + +<Disclaimer: Public document. This work is licensed under the Apache License v2.0 with LLVM Exceptions. See [https://llvm.org/LICENSE.txt](https://llvm.org/LICENSE.txt) for license information.> + +# Lifetime Safety: An Intuitive Approach for Temporal Safety in C++ +**Author:** +[Utkarsh Saxena](mailto:usx@google.com) + +**Purpose:** This document serves as a live RFC for a new lifetime safety analysis in C++, with the ultimate goal of publication as a white paper. + +## Intended Audience + +This document is intended for C++ compiler developers (especially those working on Clang), developers of other systems languages with advanced memory safety models (like Rust and Carbon), and all C++ users interested in writing safer code. + +## Goal + +* To describe a new lifetime model for C++ that aims to maximize the compile-time detection of temporal memory safety issues. +* To explore a path toward incremental safety in C++, offering a spectrum of checks that can be adopted without requiring a full plunge into a restrictive ownership model. + +**Out of Scope** + +* **Rigorous Temporal Memory Safety:** This analysis aims to detect a large class of common errors, but it does not formally prove the absence of all temporal safety bugs. +* **Runtime Solutions:** This paper focuses exclusively on static, compile-time analysis and does not cover runtime solutions like MTE or AddressSanitizer. + +# Paper: C++ Lifetimes Safety Analysis + +**Subtitle: A Flow-Sensitive, Alias-based Approach to Preventing Dangling Pointers** + +## Abstract + +This paper introduces a new intra-procedural, flow-sensitive lifetime analysis for C++ implemented in Clang. The analysis is designed to detect a significant class of temporal memory safety violations, such as use-after-free and use-after-return, at compile time. It is based on a model of "Loans" and "Origins," inspired by the Polonius borrow checker in Rust, but adapted for the semantics and flexibility of C++. + +The analysis works by translating the Clang CFG into a series of lifetime-relevant "Facts." These facts are then processed by dataflow analyses to precisely determine the validity of pointers and references at each program point. This fact-based approach, combined with a configurable strictness model, allows for both high-confidence error reporting and the detection of more subtle, potential bugs, without requiring extensive new annotations. The ultimate goal is to provide a powerful, low-overhead tool that makes C++ safer by default. + +## The Anatomy of a Temporal Safety Error + +At its core, a temporal safety error is a bug where an operation is performed on an object at a time when it is no longer valid to do so ([source](http://docs.google.com/document/d/19vbfAiV1yQu3xSMRWjyPUdzyB_LDdVUcKat_HWI1l3g?content_ref=at+its+core+a+temporal+safety+error+is+a+bug+where+an+operation+is+performed+on+an+object+at+a+time+when+it+is+no+longer+valid+to+do+so)). These bugs are notoriously difficult to debug because they often manifest as unpredictable crashes or silent data corruption far from the root cause. However, we can argue that this wide and varied class of errors—from use-after-free to iterator invalidation—all stem from a single, canonical pattern. + +**Conjecture: Any temporal safety issue is a form of Use-After-Free.** + +All sub-categories of temporal safety issues, such as returning a reference to a stack variable (`return-stack-addr`), using a variable after its scope has ended (`use-after-scope`), using heap memory after it has been deleted (`heap-use-after-free`), or using an iterator after its container has been modified (`use-after-invalidation`), can be described by a single sequence of events. + +In C++, an *object* is a region of storage, and pointers and references are the mechanisms we use to refer to them. A use-after-free occurs when we access an object after its lifetime has ended. But how can an object be accessed after it has been destroyed? This is only possible through an **alias**—a pointer or reference—that was created while the object was alive and that survived the object's destruction. + +This insight allows us to define a canonical use-after-free with four distinct events that happen in a specific order: + +1. **`t0`: Creation.** An object `M` is created in some region of storage (on the stack, on the heap, etc.). +2. **`t1`: Alias Creation.** An alias `P` (a pointer or reference) is created that refers to the object `M`. +3. **`t2`: End of Lifetime.** The lifetime of object `M` ends (e.g., it is deallocated, or it goes out of scope). +4. **`t3`: Use of Alias.** The alias `P`, which now dangles, is used to access the memory where `M` once resided. + +Let's examine this with a simple piece of C++ code: + +```cpp +void use_after_scope_example() { + int* p; + { + int s = 10; // t0: Object `s` is created on the stack. + p = &s; // t1: Alias `p` is made to refer to object `s`. + } // t2: The lifetime of `s` ends. `p` now dangles. + *p = 42; // t3: The dangling alias `p` is used. This is a use-after-free. +} +``` + +The fundamental problem is that the alias `p` outlived the object `s` it referred to. The challenge for a static analysis is therefore clear: to prevent temporal safety errors, the compiler must be able to track aliases and understand the lifetime of the objects they refer to. It needs to know the "points-to" set for every alias at every point in the program and verify that, at the moment of use, the alias does not point to an object whose lifetime has ended. + +This alias-based perspective is powerful because it generalizes beautifully. The "end of lifetime" event at `t2` doesn't have to be a variable going out of scope. It could be: + +* A call to `delete`, which ends the lifetime of a heap object. +* A function `return`, which ends the lifetime of all its local variables. +* A container modification, like `std::vector::push_back()`, which may reallocate storage, ending the lifetime of the objects in the old buffer and invalidating all existing iterators (aliases). + +By focusing on tracking aliases and their validity, we can build a unified model to detect a wide range of temporal safety errors without imposing the heavy "aliasing XOR mutability" restrictions of a traditional borrow checker ([source](https://gist.github.com/nmsmith/cdaa94aa74e8e0611221e65db8e41f7b?content_ref=the+major+advancement+is+to+eliminate+the+aliasing+xor+mutability+restriction+amongst+references+and+replace+it+with+a+similar+restriction+applied+to+lifetime+parameters)). This provides a more intuitive and C++-idiomatic path to memory safety. + +## Relation with Thread safety + +This analysis does not address Thread Safety. Thread safety is concerned with data races that occur across multiple threads. While it is possible to create temporal safety issues in multi-threaded scenarios, this analysis is focused on the sequential lifetime of objects within a single function. + +## Quest for Safer Aliasing + +Is it possible to achieve memory safety without a restrictive model like Rust's borrow checker? We believe the answer is yes. The key is to shift our focus from *restricting aliases* to *understanding them*. Instead of forbidding programs that have aliased mutable pointers, we can build a model that understands what each pointer can point to at any given time. This approach, similar to the one proposed in P1179 for C++ and explored in modern lifetime systems like Mojo's, allows us to directly detect the root cause of the problem: using a pointer after its target has ceased to exist ([source](http://docs.google.com/document/d/19vbfAiV1yQu3xSMRWjyPUdzyB_LDdVUcKat_HWI1l3g?content_ref=this+approach+similar+to+the+one+proposed+in+p1179+for+c+and+explored+in+modern+lifetime+systems+like+mojo+s+allows+us+to+directly+detect+the+root+cause+of+the+problem+using+a+pointer+after+its+target+has+ceased+to+exist)). + +This paper proposes such a model for C++. Let's begin with a simple, yet illustrative, dangling pointer bug: + +```cpp +// Example 1: A simple use-after-free +void definite_simple_case() { + MyObj* p; + { + MyObj s; + p = &s; // 'p' now points to 's' + } // 's' is destroyed, 'p' is now dangling + (void)*p; // Use-after-free +} +``` + +How can a compiler understand that the use of `p` is an error? It needs to answer a series of questions: + +1. What does `p` point to? +2. When does the object `p` points to cease to be valid? +3. Is `p` used after that point? + +Our model is designed to answer precisely these questions. + +## Core Concepts + +Our model is built on a few core concepts that allow us to formally track the relationships between pointers and the data they point to. + +### Access Paths + +An **Access Path** is a symbolic representation of a storage location in the program ([source](https://raw.githubusercontent.com/llvm/llvm-project/0e7c1732a9a7d28549fe5d690083daeb0e5de6b2/clang/lib/Analysis/LifetimeSafety.cpp?content_ref=struct+accesspath+const+clang+valuedecl+d+accesspath+const+clang+valuedecl+d+d+d)). It provides a way to uniquely identify a variable or a sub-object. For now, we will consider simple paths that refer to top-level variables, but the model can be extended to include field accesses (`a.b`), array elements (`a[i]`), and pointer indirections (`p->field`). + +### Loans: The Act of Borrowing + +A **Loan** is created whenever a reference or pointer to an object is created. It represents the act of "borrowing" that object's storage location ([source](https://raw.githubusercontent.com/llvm/llvm-project/0e7c1732a9a7d28549fe5d690083daeb0e5de6b2/clang/lib/Analysis/LifetimeSafety.cpp?content_ref=information+about+a+single+borrow+or+loan+a+loan+is+created+when+a+reference+or+pointer+is+created)). Each loan is associated with a unique ID and the `AccessPath` of the object being borrowed. + +In our `definite_simple_case` example, the expression `&s` creates a loan. The `AccessPath` for this loan is the variable `s`. + +### Origins: The Provenance of a Pointer + +An **Origin** is a symbolic identifier that represents the *set of possible loans* a pointer-like object could hold at any given time ([source](http://docs.google.com/document/d/1JpJ3M9yeXX-BnC4oKXBvRWzxoFrwziN1RzI4DrMrSp8?content_ref=ime+is+a+symbolic+identifier+representing+a+set+of+loans+from+which+a+pointer+or+reference+could+have+originated)). Every pointer-like variable or expression in the program is associated with an origin. + +* A variable declaration like `MyObj* p` introduces an origin for `p`. +* An expression like `&s` also has an origin. +* The complexity of origins can grow with type complexity. For example: + * `int* p;` has a single origin. + * `int** p;` has two origins: one for the outer pointer and one for the inner pointer. This allows us to distinguish between `p` itself being modified and what `*p` points to being modified. + * `struct S { int* p; };` also has an origin associated with the member `p`. + +The central goal of our analysis is to determine, for each origin at each point in the program, which loans it might contain. + +## Subtyping Rules and Subset Constraints + +The relationships between origins are established through the program's semantics, particularly assignments. When a pointer is assigned to another, as in `p = q`, the set of loans that `q` holds must be a subset of the loans that `p` can now hold. This is a fundamental subtyping rule: for `T*'a` to be a subtype of `T*'b`, the set of loans represented by `'a` must be a subset of the loans represented by `'b`. + +This leads to the concept of **subset constraints**. An assignment `p = q` generates a constraint `Origin(q) ⊆ Origin(p)`. The analysis doesn't solve these as a global system of equations. Instead, as we will see, it propagates the *consequences* of these constraints—the loans themselves—through the control-flow graph. This is a key departure from the Polonius model, which focuses on propagating the constraints (`'a: 'b`) themselves. + +## Invalidations: When Loans Expire + +A loan expires when the object it refers to is no longer valid. In our model, this is an **invalidation** event. The most common invalidation is deallocation, which in C++ can mean: +* A stack variable going out of scope. +* A `delete` call on a heap-allocated object. +* A container modification that reallocates its internal storage. + +## An Event-Based Representation of the Function + +To analyze a function, we first transform its CFG into a sequence of atomic, lifetime-relevant **Events**, which we call **Facts**. These facts abstract away the complexities of C++ syntax and provide a clean input for our analysis. The main facts are: + +* `Issue(LoanID, OriginID)`: A new loan is created. For example, `&s` generates an `Issue` fact. +* `Expire(LoanID)`: A loan expires. This is generated at the end of a variable's scope. +* `OriginFlow(Dest, Src, Kill)`: Loans from a source origin flow to a destination origin, as in an assignment. `Kill` indicates whether the destination's old loans are cleared. +* `Use(OriginID)`: An origin is used, such as in a pointer dereference. + +Let's trace our `definite_simple_case` example with these facts: + +```cpp +void definite_simple_case() { + MyObj* p; // Origin for p is O_p + { + MyObj s; + // The expression `&s` generates: + // - IssueFact(L1, O_&s) (A new loan L1 on 's' is created) + // The assignment `p = &s` generates: + // - OriginFlowFact(O_p, O_&s, Kill=true) + p = &s; + } // The end of the scope for 's' generates: + // - ExpireFact(L1) + // The dereference `*p` generates: + // - UseFact(O_p) + (void)*p; +} +``` + +## Flow-Sensitive Lifetime Policy + +With the program represented as a stream of facts, we can now define a flow-sensitive policy to answer our three core questions. We do this by maintaining a map from `Origin` to `Set<Loan>` at each program point. This map represents the state of our analysis. + +The analysis proceeds as follows: +1. **Forward Propagation of Loans:** We perform a forward dataflow analysis. + * When we encounter an `Issue` fact, we add the new loan to its origin's loan set. + * When we see an `OriginFlow` fact, we update the destination origin's loan set with the loans from the source. + * At control-flow merge points, we take the *union* of the loan sets from all incoming branches. + +2. **Backward Propagation of Liveness:** We then perform a backward dataflow analysis, starting from `Use` facts. + * A `Use` of an origin marks it as "live." + * This liveness information is propagated backward. If an origin `O_p` is live, and it received its loans from `O_q`, then `O_q` is also considered live at that point. + +3. **Error Detection:** An error is flagged when the analysis determines that a **live** origin contains a loan that has **expired**. + +In our `definite_simple_case` example: +* The forward analysis determines that at the point of use, `Origin(p)` contains `Loan(s)`. +* The backward analysis determines that at the point where `s` is destroyed, `Origin(p)` is live. +* The `ExpireFact` for `Loan(s)` occurs before the `UseFact`. +* The combination of these three conditions triggers a use-after-free error. + +## Without Functions, Our Work is Done Here! + +The model described so far works perfectly for a single, monolithic function. However, the moment we introduce function calls, the problem becomes more complex. How do we reason about lifetimes across function boundaries, especially when we can't see the implementation of the called function? + +### Effects of a Function Call + +A function call has inputs and outputs. From a lifetime perspective, the key challenge is to understand how the lifetimes of the outputs relate to the lifetimes of the inputs. + +### Outlives Constraints and Placeholder Origins + +When analyzing a function like `const char* get_prefix(const string& s, int len)`, we don't know the specific lifetime of the `s` that will be passed by the caller. To handle this, we introduce **placeholder origins** for the input parameters. These placeholders act as variables in our analysis. + +If a function returns a pointer or reference, its lifetime must be tied to one of its inputs. This is an **outlives constraint**. For example, the return value of `get_prefix` must "outlive" the input `s`. In our model, this means the origin of the return value will contain the placeholder loan associated with `s`. + +### Opaque Functions + +What if a function's implementation is not visible (e.g., it's in a separate translation unit), and it has no lifetime annotations? In this case, we must be conservative. If we pass a pointer to an opaque function, we have to assume it might have been invalidated. Our model handles this by associating a special **OPAQUE loan** with the pointer after the call, signifying that its lifetime is now unknown. + +## Why a Borrow Checker is Not the Right Fit for C++ + +The "aliasing XOR mutability" rule, while powerful, is fundamentally at odds with many idiomatic C++ patterns. +* **Observer Patterns:** It's common to have multiple non-owning pointers observing a mutable object. +* **Intrusive Data Structures:** Data structures like intrusive linked lists require objects to hold pointers to one another, creating cycles that are difficult for a traditional borrow checker to handle. +* **Iterator Invalidation:** The core problem in C++ is often not aliasing itself, but the fact that a mutation can invalidate an alias (e.g., resizing a vector). An alias-based analysis, like the one proposed here, directly models this problem, whereas a borrow checker can feel like an indirect and overly restrictive solution. + +By focusing on tracking what pointers can point to, our model avoids rejecting these safe and useful patterns, making it a more natural fit for the existing C++ ecosystem. + +## Open Questions + +* **When and if to introduce the term "lifetime"?** The term "lifetime" is heavily associated with Rust's model. This paper has intentionally focused on "Origins" and "Loans" to avoid confusion. Is there a point where introducing "lifetime" would be helpful, or should we stick to the new terminology? +* **Syntax for Annotations:** While this model is designed to work with minimal annotations, some will be necessary for complex cases. What should the syntax for these annotations look like? Can we build on existing attributes like `[[clang::lifetimebound]]`? diff --git a/clang/lib/Basic/SanitizerSpecialCaseList.cpp b/clang/lib/Basic/SanitizerSpecialCaseList.cpp index f7bc1d5..a1dc4a7 100644 --- a/clang/lib/Basic/SanitizerSpecialCaseList.cpp +++ b/clang/lib/Basic/SanitizerSpecialCaseList.cpp @@ -38,11 +38,11 @@ SanitizerSpecialCaseList::createOrDie(const std::vector<std::string> &Paths, } void SanitizerSpecialCaseList::createSanitizerSections() { - for (auto &S : Sections) { + for (const auto &S : Sections) { SanitizerMask Mask; #define SANITIZER(NAME, ID) \ - if (S.SectionMatcher->match(NAME)) \ + if (S.SectionMatcher.match(NAME)) \ Mask |= SanitizerKind::ID; #define SANITIZER_GROUP(NAME, ID, ALIAS) SANITIZER(NAME, ID) @@ -50,7 +50,7 @@ void SanitizerSpecialCaseList::createSanitizerSections() { #undef SANITIZER #undef SANITIZER_GROUP - SanitizerSections.emplace_back(Mask, S.Entries, S.FileIdx); + SanitizerSections.emplace_back(Mask, S); } } @@ -66,10 +66,9 @@ SanitizerSpecialCaseList::inSectionBlame(SanitizerMask Mask, StringRef Prefix, StringRef Category) const { for (const auto &S : llvm::reverse(SanitizerSections)) { if (S.Mask & Mask) { - unsigned LineNum = - SpecialCaseList::inSectionBlame(S.Entries, Prefix, Query, Category); + unsigned LineNum = S.S.getLastMatch(Prefix, Query, Category); if (LineNum > 0) - return {S.FileIdx, LineNum}; + return {S.S.FileIdx, LineNum}; } } return NotFound; diff --git a/clang/lib/CIR/CodeGen/CIRGenCXXABI.cpp b/clang/lib/CIR/CodeGen/CIRGenCXXABI.cpp index 5f1faab..df42af8 100644 --- a/clang/lib/CIR/CodeGen/CIRGenCXXABI.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenCXXABI.cpp @@ -15,6 +15,7 @@ #include "CIRGenFunction.h" #include "clang/AST/Decl.h" +#include "clang/AST/ExprCXX.h" #include "clang/AST/GlobalDecl.h" using namespace clang; @@ -75,3 +76,20 @@ void CIRGenCXXABI::setCXXABIThisValue(CIRGenFunction &cgf, assert(getThisDecl(cgf) && "no 'this' variable for function"); cgf.cxxabiThisValue = thisPtr; } + +CharUnits CIRGenCXXABI::getArrayCookieSize(const CXXNewExpr *e) { + if (!requiresArrayCookie(e)) + return CharUnits::Zero(); + + cgm.errorNYI(e->getSourceRange(), "CIRGenCXXABI::getArrayCookieSize"); + return CharUnits::Zero(); +} + +bool CIRGenCXXABI::requiresArrayCookie(const CXXNewExpr *e) { + // If the class's usual deallocation function takes two arguments, + // it needs a cookie. + if (e->doesUsualArrayDeleteWantSize()) + return true; + + return e->getAllocatedType().isDestructedType(); +} diff --git a/clang/lib/CIR/CodeGen/CIRGenCXXABI.h b/clang/lib/CIR/CodeGen/CIRGenCXXABI.h index be66240..2465a68 100644 --- a/clang/lib/CIR/CodeGen/CIRGenCXXABI.h +++ b/clang/lib/CIR/CodeGen/CIRGenCXXABI.h @@ -28,6 +28,8 @@ protected: CIRGenModule &cgm; std::unique_ptr<clang::MangleContext> mangleContext; + virtual bool requiresArrayCookie(const CXXNewExpr *e); + public: // TODO(cir): make this protected when target-specific CIRGenCXXABIs are // implemented. @@ -245,6 +247,19 @@ public: void setStructorImplicitParamValue(CIRGenFunction &cgf, mlir::Value val) { cgf.cxxStructorImplicitParamValue = val; } + + /**************************** Array cookies ******************************/ + + /// Returns the extra size required in order to store the array + /// cookie for the given new-expression. May return 0 to indicate that no + /// array cookie is required. + /// + /// Several cases are filtered out before this method is called: + /// - non-array allocations never need a cookie + /// - calls to \::operator new(size_t, void*) never need a cookie + /// + /// \param E - the new-expression being allocated. + virtual CharUnits getArrayCookieSize(const CXXNewExpr *e); }; /// Creates and Itanium-family ABI diff --git a/clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp b/clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp index 7989ad2..4eb8ca8 100644 --- a/clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp @@ -11,6 +11,7 @@ //===----------------------------------------------------------------------===// #include "CIRGenCXXABI.h" +#include "CIRGenConstantEmitter.h" #include "CIRGenFunction.h" #include "clang/AST/DeclCXX.h" @@ -210,6 +211,19 @@ RValue CIRGenFunction::emitCXXMemberOrOperatorCall( return emitCall(fnInfo, callee, returnValue, args, nullptr, loc); } +static CharUnits calculateCookiePadding(CIRGenFunction &cgf, + const CXXNewExpr *e) { + if (!e->isArray()) + return CharUnits::Zero(); + + // No cookie is required if the operator new[] being used is the + // reserved placement operator new[]. + if (e->getOperatorNew()->isReservedGlobalPlacementOperator()) + return CharUnits::Zero(); + + return cgf.cgm.getCXXABI().getArrayCookieSize(e); +} + static mlir::Value emitCXXNewAllocSize(CIRGenFunction &cgf, const CXXNewExpr *e, unsigned minElements, mlir::Value &numElements, @@ -224,8 +238,98 @@ static mlir::Value emitCXXNewAllocSize(CIRGenFunction &cgf, const CXXNewExpr *e, return sizeWithoutCookie; } - cgf.cgm.errorNYI(e->getSourceRange(), "emitCXXNewAllocSize: array"); - return {}; + // The width of size_t. + unsigned sizeWidth = cgf.cgm.getDataLayout().getTypeSizeInBits(cgf.SizeTy); + + // The number of elements can be have an arbitrary integer type; + // essentially, we need to multiply it by a constant factor, add a + // cookie size, and verify that the result is representable as a + // size_t. That's just a gloss, though, and it's wrong in one + // important way: if the count is negative, it's an error even if + // the cookie size would bring the total size >= 0. + // + // If the array size is constant, Sema will have prevented negative + // values and size overflow. + + // Compute the constant factor. + llvm::APInt arraySizeMultiplier(sizeWidth, 1); + while (const ConstantArrayType *cat = + cgf.getContext().getAsConstantArrayType(type)) { + type = cat->getElementType(); + arraySizeMultiplier *= cat->getSize(); + } + + CharUnits typeSize = cgf.getContext().getTypeSizeInChars(type); + llvm::APInt typeSizeMultiplier(sizeWidth, typeSize.getQuantity()); + typeSizeMultiplier *= arraySizeMultiplier; + + // Figure out the cookie size. + llvm::APInt cookieSize(sizeWidth, + calculateCookiePadding(cgf, e).getQuantity()); + + // This will be a size_t. + mlir::Value size; + + // Emit the array size expression. + // We multiply the size of all dimensions for NumElements. + // e.g for 'int[2][3]', ElemType is 'int' and NumElements is 6. + const Expr *arraySize = *e->getArraySize(); + mlir::Attribute constNumElements = + ConstantEmitter(cgf.cgm, &cgf) + .emitAbstract(arraySize, arraySize->getType()); + if (constNumElements) { + // Get an APInt from the constant + const llvm::APInt &count = + mlir::cast<cir::IntAttr>(constNumElements).getValue(); + + unsigned numElementsWidth = count.getBitWidth(); + + // The equivalent code in CodeGen/CGExprCXX.cpp handles these cases as + // overflow, but that should never happen. The size argument is implicitly + // cast to a size_t, so it can never be negative and numElementsWidth will + // always equal sizeWidth. + assert(!count.isNegative() && "Expected non-negative array size"); + assert(numElementsWidth == sizeWidth && + "Expected a size_t array size constant"); + + // Okay, compute a count at the right width. + llvm::APInt adjustedCount = count.zextOrTrunc(sizeWidth); + + // Scale numElements by that. This might overflow, but we don't + // care because it only overflows if allocationSize does too, and + // if that overflows then we shouldn't use this. + // This emits a constant that may not be used, but we can't tell here + // whether it will be needed or not. + numElements = + cgf.getBuilder().getConstInt(loc, adjustedCount * arraySizeMultiplier); + + // Compute the size before cookie, and track whether it overflowed. + bool overflow; + llvm::APInt allocationSize = + adjustedCount.umul_ov(typeSizeMultiplier, overflow); + + // Sema prevents us from hitting this case + assert(!overflow && "Overflow in array allocation size"); + + // Add in the cookie, and check whether it's overflowed. + if (cookieSize != 0) { + cgf.cgm.errorNYI(e->getSourceRange(), + "emitCXXNewAllocSize: array cookie"); + } + + size = cgf.getBuilder().getConstInt(loc, allocationSize); + } else { + // TODO: Handle the variable size case + cgf.cgm.errorNYI(e->getSourceRange(), + "emitCXXNewAllocSize: variable array size"); + } + + if (cookieSize == 0) + sizeWithoutCookie = size; + else + assert(sizeWithoutCookie && "didn't set sizeWithoutCookie?"); + + return size; } static void storeAnyExprIntoOneUnit(CIRGenFunction &cgf, const Expr *init, @@ -254,13 +358,26 @@ static void storeAnyExprIntoOneUnit(CIRGenFunction &cgf, const Expr *init, llvm_unreachable("bad evaluation kind"); } +void CIRGenFunction::emitNewArrayInitializer( + const CXXNewExpr *e, QualType elementType, mlir::Type elementTy, + Address beginPtr, mlir::Value numElements, + mlir::Value allocSizeWithoutCookie) { + // If we have a type with trivial initialization and no initializer, + // there's nothing to do. + if (!e->hasInitializer()) + return; + + cgm.errorNYI(e->getSourceRange(), "emitNewArrayInitializer"); +} + static void emitNewInitializer(CIRGenFunction &cgf, const CXXNewExpr *e, QualType elementType, mlir::Type elementTy, Address newPtr, mlir::Value numElements, mlir::Value allocSizeWithoutCookie) { assert(!cir::MissingFeatures::generateDebugInfo()); if (e->isArray()) { - cgf.cgm.errorNYI(e->getSourceRange(), "emitNewInitializer: array"); + cgf.emitNewArrayInitializer(e, elementType, elementTy, newPtr, numElements, + allocSizeWithoutCookie); } else if (const Expr *init = e->getInitializer()) { storeAnyExprIntoOneUnit(cgf, init, e->getAllocatedType(), newPtr, AggValueSlot::DoesNotOverlap); @@ -536,7 +653,14 @@ mlir::Value CIRGenFunction::emitCXXNewExpr(const CXXNewExpr *e) { if (allocSize != allocSizeWithoutCookie) cgm.errorNYI(e->getSourceRange(), "emitCXXNewExpr: array with cookies"); - mlir::Type elementTy = convertTypeForMem(allocType); + mlir::Type elementTy; + if (e->isArray()) { + // For array new, use the allocated type to handle multidimensional arrays + // correctly + elementTy = convertTypeForMem(e->getAllocatedType()); + } else { + elementTy = convertTypeForMem(allocType); + } Address result = builder.createElementBitCast(getLoc(e->getSourceRange()), allocation, elementTy); diff --git a/clang/lib/CIR/CodeGen/CIRGenFunction.h b/clang/lib/CIR/CodeGen/CIRGenFunction.h index d10d058..a60efe1 100644 --- a/clang/lib/CIR/CodeGen/CIRGenFunction.h +++ b/clang/lib/CIR/CodeGen/CIRGenFunction.h @@ -1254,6 +1254,11 @@ public: mlir::Value emitCXXNewExpr(const CXXNewExpr *e); + void emitNewArrayInitializer(const CXXNewExpr *E, QualType ElementType, + mlir::Type ElementTy, Address BeginPtr, + mlir::Value NumElements, + mlir::Value AllocSizeWithoutCookie); + RValue emitCXXOperatorMemberCallExpr(const CXXOperatorCallExpr *e, const CXXMethodDecl *md, ReturnValueSlot returnValue); diff --git a/clang/lib/CIR/Dialect/IR/CIRAttrs.cpp b/clang/lib/CIR/Dialect/IR/CIRAttrs.cpp index 3484c59..64ac970 100644 --- a/clang/lib/CIR/Dialect/IR/CIRAttrs.cpp +++ b/clang/lib/CIR/Dialect/IR/CIRAttrs.cpp @@ -473,6 +473,49 @@ LogicalResult cir::VTableAttr::verify( } //===----------------------------------------------------------------------===// +// DynamicCastInfoAtttr definitions +//===----------------------------------------------------------------------===// + +std::string DynamicCastInfoAttr::getAlias() const { + // The alias looks like: `dyn_cast_info_<src>_<dest>` + + std::string alias = "dyn_cast_info_"; + + alias.append(getSrcRtti().getSymbol().getValue()); + alias.push_back('_'); + alias.append(getDestRtti().getSymbol().getValue()); + + return alias; +} + +LogicalResult DynamicCastInfoAttr::verify( + function_ref<InFlightDiagnostic()> emitError, cir::GlobalViewAttr srcRtti, + cir::GlobalViewAttr destRtti, mlir::FlatSymbolRefAttr runtimeFunc, + mlir::FlatSymbolRefAttr badCastFunc, cir::IntAttr offsetHint) { + auto isRttiPtr = [](mlir::Type ty) { + // RTTI pointers are !cir.ptr<!u8i>. + + auto ptrTy = mlir::dyn_cast<cir::PointerType>(ty); + if (!ptrTy) + return false; + + auto pointeeIntTy = mlir::dyn_cast<cir::IntType>(ptrTy.getPointee()); + if (!pointeeIntTy) + return false; + + return pointeeIntTy.isUnsigned() && pointeeIntTy.getWidth() == 8; + }; + + if (!isRttiPtr(srcRtti.getType())) + return emitError() << "srcRtti must be an RTTI pointer"; + + if (!isRttiPtr(destRtti.getType())) + return emitError() << "destRtti must be an RTTI pointer"; + + return success(); +} + +//===----------------------------------------------------------------------===// // CIR Dialect //===----------------------------------------------------------------------===// diff --git a/clang/lib/CIR/Dialect/IR/CIRDialect.cpp b/clang/lib/CIR/Dialect/IR/CIRDialect.cpp index cdd4e3c..5f88590 100644 --- a/clang/lib/CIR/Dialect/IR/CIRDialect.cpp +++ b/clang/lib/CIR/Dialect/IR/CIRDialect.cpp @@ -71,6 +71,10 @@ struct CIROpAsmDialectInterface : public OpAsmDialectInterface { os << "bfi_" << bitfield.getName().str(); return AliasResult::FinalAlias; } + if (auto dynCastInfoAttr = mlir::dyn_cast<cir::DynamicCastInfoAttr>(attr)) { + os << dynCastInfoAttr.getAlias(); + return AliasResult::FinalAlias; + } return AliasResult::NoAlias; } }; diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp index 9f30287..a071e80 100644 --- a/clang/lib/CodeGen/CGExpr.cpp +++ b/clang/lib/CodeGen/CGExpr.cpp @@ -1272,6 +1272,23 @@ void CodeGenFunction::EmitBoundsCheckImpl(const Expr *E, llvm::Value *Bound, EmitCheck(std::make_pair(Check, CheckKind), CheckHandler, StaticData, Index); } +void CodeGenFunction::EmitAllocToken(llvm::CallBase *CB, QualType AllocType) { + assert(SanOpts.has(SanitizerKind::AllocToken) && + "Only needed with -fsanitize=alloc-token"); + + PrintingPolicy Policy(CGM.getContext().getLangOpts()); + Policy.SuppressTagKeyword = true; + Policy.FullyQualifiedName = true; + SmallString<64> TypeName; + llvm::raw_svector_ostream TypeNameOS(TypeName); + AllocType.getCanonicalType().print(TypeNameOS, Policy); + auto *TypeMDS = llvm::MDString::get(CGM.getLLVMContext(), TypeNameOS.str()); + + // Format: !{<type-name>} + auto *MDN = llvm::MDNode::get(CGM.getLLVMContext(), {TypeMDS}); + CB->setMetadata(llvm::LLVMContext::MD_alloc_token, MDN); +} + CodeGenFunction::ComplexPairTy CodeGenFunction:: EmitComplexPrePostIncDec(const UnaryOperator *E, LValue LV, bool isInc, bool isPre) { diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp index c52526c..290c2e0 100644 --- a/clang/lib/CodeGen/CGExprCXX.cpp +++ b/clang/lib/CodeGen/CGExprCXX.cpp @@ -1655,11 +1655,16 @@ llvm::Value *CodeGenFunction::EmitCXXNewExpr(const CXXNewExpr *E) { RValue RV = EmitNewDeleteCall(*this, allocator, allocatorType, allocatorArgs); - // Set !heapallocsite metadata on the call to operator new. - if (getDebugInfo()) - if (auto *newCall = dyn_cast<llvm::CallBase>(RV.getScalarVal())) - getDebugInfo()->addHeapAllocSiteMetadata(newCall, allocType, - E->getExprLoc()); + if (auto *newCall = dyn_cast<llvm::CallBase>(RV.getScalarVal())) { + if (auto *CGDI = getDebugInfo()) { + // Set !heapallocsite metadata on the call to operator new. + CGDI->addHeapAllocSiteMetadata(newCall, allocType, E->getExprLoc()); + } + if (SanOpts.has(SanitizerKind::AllocToken)) { + // Set !alloc_token metadata. + EmitAllocToken(newCall, allocType); + } + } // If this was a call to a global replaceable allocation function that does // not take an alignment argument, the allocator is known to produce diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp index b2fe917..acf8de4 100644 --- a/clang/lib/CodeGen/CodeGenFunction.cpp +++ b/clang/lib/CodeGen/CodeGenFunction.cpp @@ -846,6 +846,8 @@ void CodeGenFunction::StartFunction(GlobalDecl GD, QualType RetTy, Fn->addFnAttr(llvm::Attribute::SanitizeNumericalStability); if (SanOpts.hasOneOf(SanitizerKind::Memory | SanitizerKind::KernelMemory)) Fn->addFnAttr(llvm::Attribute::SanitizeMemory); + if (SanOpts.has(SanitizerKind::AllocToken)) + Fn->addFnAttr(llvm::Attribute::SanitizeAllocToken); } if (SanOpts.has(SanitizerKind::SafeStack)) Fn->addFnAttr(llvm::Attribute::SafeStack); diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index 99de6e1..e14e60c 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -3348,6 +3348,9 @@ public: SanitizerAnnotateDebugInfo(ArrayRef<SanitizerKind::SanitizerOrdinal> Ordinals, SanitizerHandler Handler); + /// Emit additional metadata used by the AllocToken instrumentation. + void EmitAllocToken(llvm::CallBase *CB, QualType AllocType); + llvm::Value *GetCountedByFieldExprGEP(const Expr *Base, const FieldDecl *FD, const FieldDecl *CountDecl); diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp index 98f5efb..eb5d542 100644 --- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp +++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp @@ -57,6 +57,9 @@ std::string aarch64::getAArch64TargetCPU(const ArgList &Args, // iOS 26 only runs on apple-a12 and later CPUs. if (!Triple.isOSVersionLT(26)) return "apple-a12"; + // arm64 (non-e) iOS 18 only runs on apple-a10 and later CPUs. + if (!Triple.isOSVersionLT(18) && !Triple.isArm64e()) + return "apple-a10"; } if (Triple.isWatchOS()) { @@ -64,8 +67,8 @@ std::string aarch64::getAArch64TargetCPU(const ArgList &Args, // arm64_32/arm64e watchOS requires S4 before watchOS 26, S6 after. if (Triple.getArch() == llvm::Triple::aarch64_32 || Triple.isArm64e()) return Triple.isOSVersionLT(26) ? "apple-s4" : "apple-s6"; - // arm64 (non-e, non-32) watchOS comes later, and requires S6 anyway. - return "apple-s6"; + // arm64 (non-e, non-32) watchOS comes later, and requires S9 anyway. + return "apple-s9"; } if (Triple.isXROS()) { diff --git a/clang/lib/Sema/SemaHLSL.cpp b/clang/lib/Sema/SemaHLSL.cpp index a662b72..09e5d69 100644 --- a/clang/lib/Sema/SemaHLSL.cpp +++ b/clang/lib/Sema/SemaHLSL.cpp @@ -598,18 +598,17 @@ void SemaHLSL::ActOnFinishBuffer(Decl *Dcl, SourceLocation RBrace) { validatePackoffset(SemaRef, BufDecl); - // create buffer layout struct createHostLayoutStructForBuffer(SemaRef, BufDecl); - HLSLVkBindingAttr *VkBinding = Dcl->getAttr<HLSLVkBindingAttr>(); - HLSLResourceBindingAttr *RBA = Dcl->getAttr<HLSLResourceBindingAttr>(); - if (!VkBinding && (!RBA || !RBA->hasRegisterSlot())) { + // Handle implicit binding if needed. + ResourceBindingAttrs ResourceAttrs(Dcl); + if (!ResourceAttrs.isExplicit()) { SemaRef.Diag(Dcl->getLocation(), diag::warn_hlsl_implicit_binding); // Use HLSLResourceBindingAttr to transfer implicit binding order_ID // to codegen. If it does not exist, create an implicit attribute. uint32_t OrderID = getNextImplicitBindingOrderID(); - if (RBA) - RBA->setImplicitBindingOrderID(OrderID); + if (ResourceAttrs.hasBinding()) + ResourceAttrs.setImplicitOrderID(OrderID); else addImplicitBindingAttrToDecl(SemaRef, BufDecl, BufDecl->isCBuffer() ? RegisterType::CBuffer @@ -1590,10 +1589,6 @@ void SemaHLSL::handleVkConstantIdAttr(Decl *D, const ParsedAttr &AL) { } void SemaHLSL::handleVkBindingAttr(Decl *D, const ParsedAttr &AL) { - // The vk::binding attribute only applies to SPIR-V. - if (!getASTContext().getTargetInfo().getTriple().isSPIRV()) - return; - uint32_t Binding = 0; if (!SemaRef.checkUInt32Argument(AL, AL.getArgAsExpr(0), Binding)) return; @@ -3780,17 +3775,15 @@ void SemaHLSL::ActOnVariableDeclarator(VarDecl *VD) { // If the resource array does not have an explicit binding attribute, // create an implicit one. It will be used to transfer implicit binding // order_ID to codegen. - if (!VD->hasAttr<HLSLVkBindingAttr>()) { - HLSLResourceBindingAttr *RBA = VD->getAttr<HLSLResourceBindingAttr>(); - if (!RBA || !RBA->hasRegisterSlot()) { - uint32_t OrderID = getNextImplicitBindingOrderID(); - if (RBA) - RBA->setImplicitBindingOrderID(OrderID); - else - addImplicitBindingAttrToDecl( - SemaRef, VD, getRegisterType(getResourceArrayHandleType(VD)), - OrderID); - } + ResourceBindingAttrs Binding(VD); + if (!Binding.isExplicit()) { + uint32_t OrderID = getNextImplicitBindingOrderID(); + if (Binding.hasBinding()) + Binding.setImplicitOrderID(OrderID); + else + addImplicitBindingAttrToDecl( + SemaRef, VD, getRegisterType(getResourceArrayHandleType(VD)), + OrderID); } } } diff --git a/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp b/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp index 00a1b8b..66cfccb 100644 --- a/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp @@ -31,9 +31,9 @@ bool tryToFindPtrOrigin( if (auto *DRE = dyn_cast<DeclRefExpr>(E)) { if (auto *VD = dyn_cast_or_null<VarDecl>(DRE->getDecl())) { auto QT = VD->getType(); - if (VD->hasGlobalStorage() && QT.isConstQualified()) { + auto IsImmortal = safeGetName(VD) == "NSApp"; + if (VD->hasGlobalStorage() && (IsImmortal || QT.isConstQualified())) return callback(E, true); - } } } if (auto *tempExpr = dyn_cast<MaterializeTemporaryExpr>(E)) { @@ -208,6 +208,8 @@ bool tryToFindPtrOrigin( continue; } if (auto *BoxedExpr = dyn_cast<ObjCBoxedExpr>(E)) { + if (StopAtFirstRefCountedObj) + return callback(BoxedExpr, true); E = BoxedExpr->getSubExpr(); continue; } diff --git a/clang/test/AST/HLSL/resource_binding_attr.hlsl b/clang/test/AST/HLSL/resource_binding_attr.hlsl index c6d93b9..2de0674 100644 --- a/clang/test/AST/HLSL/resource_binding_attr.hlsl +++ b/clang/test/AST/HLSL/resource_binding_attr.hlsl @@ -92,9 +92,8 @@ cbuffer CB3 { StructuredBuffer<float> SB[10]; // CHECK: VarDecl {{.*}} SB2 'StructuredBuffer<float>[10]' +// CHECK: HLSLVkBindingAttr {{.*}} 2 0 // DXIL: HLSLResourceBindingAttr {{.*}} Implicit -// DXIL-NOT: HLSLVkBindingAttr -// SPV: HLSLVkBindingAttr {{.*}} 2 0 // SPV-NOT: HLSLResourceBindingAttr {{.*}} Implicit [[vk::binding(2)]] StructuredBuffer<float> SB2[10]; diff --git a/clang/test/AST/HLSL/vk_binding_attr.hlsl b/clang/test/AST/HLSL/vk_binding_attr.hlsl index d08165d..13e7544 100644 --- a/clang/test/AST/HLSL/vk_binding_attr.hlsl +++ b/clang/test/AST/HLSL/vk_binding_attr.hlsl @@ -10,8 +10,7 @@ // SPV-NEXT: IntegerLiteral {{.*}} 'unsigned int' 102 // DXIL-NEXT: IntegerLiteral {{.*}} 'unsigned int' 0 // DXIL-NEXT: IntegerLiteral {{.*}} 'unsigned int' 0 -// SPV: HLSLVkBindingAttr {{.*}} 23 102 -// DXIL-NOT: HLSLVkBindingAttr +// CHECK: HLSLVkBindingAttr {{.*}} 23 102 [[vk::binding(23, 102)]] StructuredBuffer<float> Buf; // CHECK: VarDecl {{.*}} Buf2 'StructuredBuffer<float>':'hlsl::StructuredBuffer<float>' @@ -23,8 +22,7 @@ // SPV-NEXT: IntegerLiteral {{.*}} 'unsigned int' 1 // DXIL-NEXT: IntegerLiteral {{.*}} 'unsigned int' 23 // DXIL-NEXT: IntegerLiteral {{.*}} 'unsigned int' 102 -// SPV: HLSLVkBindingAttr {{.*}} 14 1 -// DXIL-NOT: HLSLVkBindingAttr +// CHECK: HLSLVkBindingAttr {{.*}} 14 1 // CHECK: HLSLResourceBindingAttr {{.*}} "t23" "space102" [[vk::binding(14, 1)]] StructuredBuffer<float> Buf2 : register(t23, space102); @@ -37,15 +35,13 @@ // SPV-NEXT: IntegerLiteral {{.*}} 'unsigned int' 0 // DXIL-NEXT: IntegerLiteral {{.*}} 'unsigned int' 23 // DXIL-NEXT: IntegerLiteral {{.*}} 'unsigned int' 102 -// SPV: HLSLVkBindingAttr {{.*}} 14 0 -// DXIL-NOT: HLSLVkBindingAttr +// CHECK: HLSLVkBindingAttr {{.*}} 14 0 // CHECK: HLSLResourceBindingAttr {{.*}} "t23" "space102" [[vk::binding(14)]] StructuredBuffer<float> Buf3 : register(t23, space102); // CHECK: HLSLBufferDecl {{.*}} cbuffer CB // CHECK-NEXT: HLSLResourceClassAttr {{.*}} Implicit CBuffer -// SPV-NEXT: HLSLVkBindingAttr {{.*}} 1 2 -// DXIL-NOT: HLSLVkBindingAttr +// CHECK: HLSLVkBindingAttr {{.*}} 1 2 [[vk::binding(1, 2)]] cbuffer CB { float a; } @@ -54,15 +50,14 @@ // CHECK-NEXT: CallExpr {{.*}} 'Buffer<int>':'hlsl::Buffer<int>' // CHECK-NEXT: ImplicitCastExpr {{.*}} 'hlsl::Buffer<int> (*)(unsigned int, unsigned int, int, unsigned int, const char *)' <FunctionToPointerDecay> // SPV-NEXT: DeclRefExpr {{.*}} 'hlsl::Buffer<int> (unsigned int, unsigned int, int, unsigned int, const char *)' -// SPV-NEXT-SAME: CXXMethod {{.*}} '__createFromBinding' 'Buffer<int> (unsigned int, unsigned int, int, unsigned int, const char *)' +// SPV-NEXT-SAME: CXXMethod {{.*}} '__createFromBinding' 'hlsl::Buffer<int> (unsigned int, unsigned int, int, unsigned int, const char *)' // SPV-NEXT: IntegerLiteral {{.*}} 'unsigned int' 24 // SPV-NEXT: IntegerLiteral {{.*}} 'unsigned int' 103 -// DXIL-NEXT: DeclRefExpr {{.*}} 'hlsl::Buffer<int> (unsigned int, unsigned int, int, unsigned int, const char *)' -// DXIL-NEXT-SAME: CXXMethod {{.*}} '__createFromImplicitBinding' 'Buffer<int> (unsigned int, unsigned int, int, unsigned int, const char *)' +// DXIL-NEXT: DeclRefExpr {{.*}} 'hlsl::Buffer<int> (unsigned int, unsigned int, int, unsigned int, const char *)' +// DXIL-NEXT-SAME: CXXMethod {{.*}} '__createFromImplicitBinding' 'hlsl::Buffer<int> (unsigned int, unsigned int, int, unsigned int, const char *)' // DXIL-NEXT: IntegerLiteral {{.*}} 'unsigned int' 2 // DXIL-NEXT: IntegerLiteral {{.*}} 'unsigned int' 0 -// SPV: HLSLVkBindingAttr {{.*}} 24 103 -// DXIL-NOT: HLSLVkBindingAttr +// CHECK: HLSLVkBindingAttr {{.*}} 24 103 [[vk::binding(24, 103)]] Buffer<int> Buf4; // CHECK: VarDecl {{.*}} Buf5 'RWBuffer<int2>':'hlsl::RWBuffer<vector<int, 2>>' @@ -76,8 +71,7 @@ // DXIL-NEXT-SAME: CXXMethod {{.*}} '__createFromImplicitBinding' 'Buffer<int2> (unsigned int, unsigned int, int, unsigned int, const char *)' // DXIL-NEXT: IntegerLiteral {{.*}} 'unsigned int' 3 // DXIL-NEXT: IntegerLiteral {{.*}} 'unsigned int' 0 -// SPV: HLSLVkBindingAttr {{.*}} 25 104 -// DXIL-NOT: HLSLVkBindingAttr +// CHECK: HLSLVkBindingAttr {{.*}} 25 104 [[vk::binding(25, 104)]] RWBuffer<int2> Buf5; // CHECK: VarDecl {{.*}} Buf6 'RWStructuredBuffer<int>':'hlsl::RWStructuredBuffer<int>' @@ -91,6 +85,5 @@ // DXIL-NEXT-SAME: CXXMethod {{.*}} '__createFromBinding' 'hlsl::RWStructuredBuffer<int> (unsigned int, unsigned int, int, unsigned int, const char *)' // DXIL-NEXT: IntegerLiteral {{.*}} 'unsigned int' 4 // DXIL-NEXT: IntegerLiteral {{.*}} 'unsigned int' 0 -// SPV: HLSLVkBindingAttr {{.*}} 26 105 -// DXIL-NOT: HLSLVkBindingAttr +// CHECK: HLSLVkBindingAttr {{.*}} 26 105 [[vk::binding(26, 105)]] RWStructuredBuffer<int> Buf6; diff --git a/clang/test/AST/ast-print-record-decl.c b/clang/test/AST/ast-print-record-decl.c index fd81588..394f837 100644 --- a/clang/test/AST/ast-print-record-decl.c +++ b/clang/test/AST/ast-print-record-decl.c @@ -315,4 +315,11 @@ template <int, int = 0> KW SmearedNTTPDefArgs; // PRINT-CXX-NEXT: template <int = 0, int> [[KW]] SmearedNTTPDefArgs; template <int = 0, int> KW SmearedNTTPDefArgs; +// PRINT-CXX-LABEL: Tpl +template <int> KW Tpl; +// PRINT-CXX-NEXT: template <template <int> class, template <int> class = Tpl> [[KW]] SmearedTplDefArgs; +template <template <int> class, template <int> class = Tpl> KW SmearedTplDefArgs; +// PRINT-CXX-NEXT: template <template <int> class = Tpl, template <int> class> [[KW]] SmearedTplDefArgs; +template <template <int> class = Tpl, template <int> class> KW SmearedTplDefArgs; + #endif diff --git a/clang/test/Analysis/Checkers/WebKit/objc-mock-types.h b/clang/test/Analysis/Checkers/WebKit/objc-mock-types.h index dacb713..a5fc3d7 100644 --- a/clang/test/Analysis/Checkers/WebKit/objc-mock-types.h +++ b/clang/test/Analysis/Checkers/WebKit/objc-mock-types.h @@ -178,6 +178,22 @@ __attribute__((objc_root_class)) + (NSNumber *)numberWithBool:(BOOL)value; @end +@interface NSResponder : NSObject +@end + +@interface NSApplication : NSResponder + +extern NSApplication * NSApp; + +@property (class, readonly, strong) NSApplication *sharedApplication; + +- (void)finishLaunching; +- (void)run; +- (void)stop:(id)sender; +- (void)terminate:(id)sender; + +@end + @interface SomeObj : NSObject - (instancetype)_init; - (SomeObj *)mutableCopy; diff --git a/clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm b/clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm index c9d2fe8..a517dbc 100644 --- a/clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm +++ b/clang/test/Analysis/Checkers/WebKit/unretained-call-args.mm @@ -398,12 +398,18 @@ namespace call_with_cf_constant { void baz(const NSDictionary *); void boo(NSNumber *); void boo(CFTypeRef); - void foo() { + + struct Details { + int value; + }; + + void foo(Details* details) { CFArrayCreateMutable(kCFAllocatorDefault, 10); bar(@[@"hello"]); baz(@{@"hello": @3}); boo(@YES); boo(@NO); + boo(@(details->value)); } } @@ -582,6 +588,7 @@ struct Derived : Base { [self doWork:@"hello", RetainPtr<SomeObj> { provide() }.get(), RetainPtr<CFMutableArrayRef> { provide_cf() }.get(), OSObjectPtr { provide_dispatch() }.get()]; [self doWork:__null]; [self doWork:nil]; + [NSApp run]; } - (SomeObj *)getSomeObj { diff --git a/clang/test/Analysis/LifetimeSafety/benchmark.py b/clang/test/Analysis/LifetimeSafety/benchmark.py index d2e5f0b..cd5b3081 100644 --- a/clang/test/Analysis/LifetimeSafety/benchmark.py +++ b/clang/test/Analysis/LifetimeSafety/benchmark.py @@ -145,6 +145,60 @@ def generate_cpp_nested_loop_test(n: int) -> str: return cpp_code +def generate_cpp_switch_fan_out_test(n: int) -> str: + """ + Generates C++ code with a switch statement with N branches. + Each branch 'i' 'uses' (reads) a single, unique pointer 'pi'. + This pattern creates a "fan-in" join point for the backward + liveness analysis, stressing the LivenessMap::join operation + by forcing it to merge N disjoint, single-element sets of live origins. + The resulting complexity for LiveOrigins should be O(n log n) or higher. + + Example (n=3): + struct MyObj { int id; ~MyObj() {} }; + + void switch_fan_out_3(int condition) { + MyObj v1{1}; MyObj v2{1}; MyObj v3{1}; + MyObj* p1 = &v1; MyObj* p2 = &v2; MyObj* p3 = &v3; + + switch (condition % 3) { + case 0: + p1->id = 1; + break; + case 1: + p2->id = 1; + break; + case 2: + p3->id = 1; + break; + } + } + """ + if n <= 0: + return "// Number of variables must be positive." + + cpp_code = "struct MyObj { int id; ~MyObj() {} };\n\n" + cpp_code += f"void switch_fan_out{n}(int condition) {{\n" + # Generate N distinct objects + for i in range(1, n + 1): + cpp_code += f" MyObj v{i}{{1}};\n" + cpp_code += "\n" + # Generate N distinct pointers, each as a separate variable + for i in range(1, n + 1): + cpp_code += f" MyObj* p{i} = &v{i};\n" + cpp_code += "\n" + + cpp_code += f" switch (condition % {n}) {{\n" + for case_num in range(n): + cpp_code += f" case {case_num}:\n" + cpp_code += f" p{case_num + 1}->id = 1;\n" + cpp_code += " break;\n" + + cpp_code += " }\n}\n" + cpp_code += f"\nint main() {{ switch_fan_out{n}(0); return 0; }}\n" + return cpp_code + + def analyze_trace_file(trace_path: str) -> dict: """ Parses the -ftime-trace JSON output to find durations for the lifetime @@ -156,14 +210,14 @@ def analyze_trace_file(trace_path: str) -> dict: "total_us": 0.0, "fact_gen_us": 0.0, "loan_prop_us": 0.0, - "expired_loans_us": 0.0, + "live_origins_us": 0.0, } event_name_map = { "LifetimeSafetyAnalysis": "lifetime_us", "ExecuteCompiler": "total_us", "FactGenerator": "fact_gen_us", "LoanPropagation": "loan_prop_us", - "ExpiredLoans": "expired_loans_us", + "LiveOrigins": "live_origins_us", } try: with open(trace_path, "r") as f: @@ -227,7 +281,7 @@ def generate_markdown_report(results: dict) -> str: # Table header report.append( - "| N (Input Size) | Total Time | Analysis Time (%) | Fact Generator (%) | Loan Propagation (%) | Expired Loans (%) |" + "| N (Input Size) | Total Time | Analysis Time (%) | Fact Generator (%) | Loan Propagation (%) | Live Origins (%) |" ) report.append( "|:---------------|-----------:|------------------:|-------------------:|---------------------:|------------------:|" @@ -247,7 +301,7 @@ def generate_markdown_report(results: dict) -> str: f"{data['lifetime_ms'][i] / total_t * 100:>17.2f}% |", f"{data['fact_gen_ms'][i] / total_t * 100:>18.2f}% |", f"{data['loan_prop_ms'][i] / total_t * 100:>20.2f}% |", - f"{data['expired_loans_ms'][i] / total_t * 100:>17.2f}% |", + f"{data['live_origins_ms'][i] / total_t * 100:>17.2f}% |", ] report.append(" ".join(row)) @@ -259,7 +313,7 @@ def generate_markdown_report(results: dict) -> str: "Total Analysis": data["lifetime_ms"], "FactGenerator": data["fact_gen_ms"], "LoanPropagation": data["loan_prop_ms"], - "ExpiredLoans": data["expired_loans_ms"], + "LiveOrigins": data["live_origins_ms"], } for phase_name, y_data in analysis_phases.items(): @@ -302,7 +356,13 @@ def run_single_test( source_file, ] - result = subprocess.run(clang_command, capture_output=True, text=True, timeout=60) + try: + result = subprocess.run( + clang_command, capture_output=True, text=True, timeout=60 + ) + except subprocess.TimeoutExpired: + print(f"Compilation timed out for N={n}!", file=sys.stderr) + return {} if result.returncode != 0: print(f"Compilation failed for N={n}!", file=sys.stderr) @@ -354,6 +414,12 @@ if __name__ == "__main__": "generator_func": generate_cpp_nested_loop_test, "n_values": [50, 100, 150, 200], }, + { + "name": "switch_fan_out", + "title": "Switch Fan-out", + "generator_func": generate_cpp_switch_fan_out_test, + "n_values": [500, 1000, 2000, 4000], + }, ] results = {} @@ -368,7 +434,7 @@ if __name__ == "__main__": "total_ms": [], "fact_gen_ms": [], "loan_prop_ms": [], - "expired_loans_ms": [], + "live_origins_ms": [], } for n in config["n_values"]: durations_ms = run_single_test( @@ -387,7 +453,7 @@ if __name__ == "__main__": f" Total Analysis: {human_readable_time(durations_ms['lifetime_ms'])} | " f"FactGen: {human_readable_time(durations_ms['fact_gen_ms'])} | " f"LoanProp: {human_readable_time(durations_ms['loan_prop_ms'])} | " - f"ExpiredLoans: {human_readable_time(durations_ms['expired_loans_ms'])}" + f"LiveOrigins: {human_readable_time(durations_ms['live_origins_ms'])}" ) print("\n\n" + "=" * 80) diff --git a/clang/test/CIR/CodeGen/new.cpp b/clang/test/CIR/CodeGen/new.cpp index 3dcf7af..000ea5b 100644 --- a/clang/test/CIR/CodeGen/new.cpp +++ b/clang/test/CIR/CodeGen/new.cpp @@ -180,3 +180,56 @@ void test_new_with_complex_type() { // OGCG: store float 1.000000e+00, ptr %[[COMPLEX_REAL_PTR]], align 8 // OGCG: store float 2.000000e+00, ptr %[[COMPLEX_IMAG_PTR]], align 4 // OGCG: store ptr %[[NEW_COMPLEX]], ptr %[[A_ADDR]], align 8 + +void t_new_constant_size() { + auto p = new double[16]; +} + +// In this test, NUM_ELEMENTS isn't used because no cookie is needed and there +// are no constructor calls needed. + +// CHECK: cir.func{{.*}} @_Z19t_new_constant_sizev() +// CHECK: %[[P_ADDR:.*]] = cir.alloca !cir.ptr<!cir.double>, !cir.ptr<!cir.ptr<!cir.double>>, ["p", init] {alignment = 8 : i64} +// CHECK: %[[#NUM_ELEMENTS:]] = cir.const #cir.int<16> : !u64i +// CHECK: %[[#ALLOCATION_SIZE:]] = cir.const #cir.int<128> : !u64i +// CHECK: %[[RAW_PTR:.*]] = cir.call @_Znam(%[[#ALLOCATION_SIZE]]) : (!u64i) -> !cir.ptr<!void> +// CHECK: %[[TYPED_PTR:.*]] = cir.cast bitcast %[[RAW_PTR]] : !cir.ptr<!void> -> !cir.ptr<!cir.double> +// CHECK: cir.store align(8) %[[TYPED_PTR]], %[[P_ADDR]] : !cir.ptr<!cir.double>, !cir.ptr<!cir.ptr<!cir.double>> +// CHECK: cir.return +// CHECK: } + +// LLVM: define{{.*}} void @_Z19t_new_constant_sizev +// LLVM: %[[P_ADDR:.*]] = alloca ptr, i64 1, align 8 +// LLVM: %[[CALL:.*]] = call ptr @_Znam(i64 128) +// LLVM: store ptr %[[CALL]], ptr %[[P_ADDR]], align 8 + +// OGCG: define{{.*}} void @_Z19t_new_constant_sizev +// OGCG: %[[P_ADDR:.*]] = alloca ptr, align 8 +// OGCG: %[[CALL:.*]] = call noalias noundef nonnull ptr @_Znam(i64 noundef 128) +// OGCG: store ptr %[[CALL]], ptr %[[P_ADDR]], align 8 + + +void t_new_multidim_constant_size() { + auto p = new double[2][3][4]; +} + +// As above, NUM_ELEMENTS isn't used. + +// CHECK: cir.func{{.*}} @_Z28t_new_multidim_constant_sizev() +// CHECK: %[[P_ADDR:.*]] = cir.alloca !cir.ptr<!cir.array<!cir.array<!cir.double x 4> x 3>>, !cir.ptr<!cir.ptr<!cir.array<!cir.array<!cir.double x 4> x 3>>>, ["p", init] {alignment = 8 : i64} +// CHECK: %[[#NUM_ELEMENTS:]] = cir.const #cir.int<24> : !u64i +// CHECK: %[[#ALLOCATION_SIZE:]] = cir.const #cir.int<192> : !u64i +// CHECK: %[[RAW_PTR:.*]] = cir.call @_Znam(%[[#ALLOCATION_SIZE]]) : (!u64i) -> !cir.ptr<!void> +// CHECK: %[[TYPED_PTR:.*]] = cir.cast bitcast %[[RAW_PTR]] : !cir.ptr<!void> -> !cir.ptr<!cir.array<!cir.array<!cir.double x 4> x 3>> +// CHECK: cir.store align(8) %[[TYPED_PTR]], %[[P_ADDR]] : !cir.ptr<!cir.array<!cir.array<!cir.double x 4> x 3>>, !cir.ptr<!cir.ptr<!cir.array<!cir.array<!cir.double x 4> x 3>>> +// CHECK: } + +// LLVM: define{{.*}} void @_Z28t_new_multidim_constant_sizev +// LLVM: %[[P_ADDR:.*]] = alloca ptr, i64 1, align 8 +// LLVM: %[[CALL:.*]] = call ptr @_Znam(i64 192) +// LLVM: store ptr %[[CALL]], ptr %[[P_ADDR]], align 8 + +// OGCG: define{{.*}} void @_Z28t_new_multidim_constant_sizev +// OGCG: %[[P_ADDR:.*]] = alloca ptr, align 8 +// OGCG: %[[CALL:.*]] = call noalias noundef nonnull ptr @_Znam(i64 noundef 192) +// OGCG: store ptr %[[CALL]], ptr %[[P_ADDR]], align 8 diff --git a/clang/test/CIR/IR/dynamic-cast.cir b/clang/test/CIR/IR/dynamic-cast.cir new file mode 100644 index 0000000..283f11e --- /dev/null +++ b/clang/test/CIR/IR/dynamic-cast.cir @@ -0,0 +1,59 @@ +// RUN: cir-opt --verify-roundtrip %s | FileCheck %s + +!s64i = !cir.int<s, 64> +!u8i = !cir.int<u, 8> +!void = !cir.void + +!rec_Base = !cir.record<struct "Base" {!cir.vptr}> +!rec_Derived = !cir.record<struct "Derived" {!rec_Base}> + +#dyn_cast_info__ZTI4Base__ZTI7Derived = #cir.dyn_cast_info<src_rtti = #cir.global_view<@_ZTI4Base> : !cir.ptr<!u8i>, dest_rtti = #cir.global_view<@_ZTI7Derived> : !cir.ptr<!u8i>, runtime_func = @__dynamic_cast, bad_cast_func = @__cxa_bad_cast, offset_hint = #cir.int<0> : !s64i> + +// CHECK: #dyn_cast_info__ZTI4Base__ZTI7Derived = #cir.dyn_cast_info<src_rtti = #cir.global_view<@_ZTI4Base> : !cir.ptr<!u8i>, dest_rtti = #cir.global_view<@_ZTI7Derived> : !cir.ptr<!u8i>, runtime_func = @__dynamic_cast, bad_cast_func = @__cxa_bad_cast, offset_hint = #cir.int<0> : !s64i> + +module { + cir.global "private" constant external @_ZTI4Base : !cir.ptr<!u8i> + cir.global "private" constant external @_ZTI7Derived : !cir.ptr<!u8i> + cir.func private @__dynamic_cast(!cir.ptr<!void>, !cir.ptr<!u8i>, !cir.ptr<!u8i>, !s64i) -> !cir.ptr<!void> + cir.func private @__cxa_bad_cast() + + cir.func @test_ptr_cast(%arg0: !cir.ptr<!rec_Base>) -> !cir.ptr<!rec_Derived> { + %0 = cir.dyn_cast ptr %arg0 : !cir.ptr<!rec_Base> -> !cir.ptr<!rec_Derived> #dyn_cast_info__ZTI4Base__ZTI7Derived + cir.return %0 : !cir.ptr<!rec_Derived> + } + + // CHECK: cir.func @test_ptr_cast(%arg0: !cir.ptr<!rec_Base>) -> !cir.ptr<!rec_Derived> { + // CHECK: %0 = cir.dyn_cast ptr %arg0 : !cir.ptr<!rec_Base> -> !cir.ptr<!rec_Derived> #dyn_cast_info__ZTI4Base__ZTI7Derived + // CHECK: cir.return %0 : !cir.ptr<!rec_Derived> + // CHECK: } + + cir.func @test_ref_cast(%arg0: !cir.ptr<!rec_Base>) -> !cir.ptr<!rec_Derived> { + %0 = cir.dyn_cast ref %arg0 : !cir.ptr<!rec_Base> -> !cir.ptr<!rec_Derived> #dyn_cast_info__ZTI4Base__ZTI7Derived + cir.return %0 : !cir.ptr<!rec_Derived> + } + + // CHECK: cir.func @test_ref_cast(%arg0: !cir.ptr<!rec_Base>) -> !cir.ptr<!rec_Derived> { + // CHECK: %0 = cir.dyn_cast ref %arg0 : !cir.ptr<!rec_Base> -> !cir.ptr<!rec_Derived> #dyn_cast_info__ZTI4Base__ZTI7Derived + // CHECK: cir.return %0 : !cir.ptr<!rec_Derived> + // CHECK: } + + cir.func dso_local @test_cast_to_void(%arg0: !cir.ptr<!rec_Base>) -> !cir.ptr<!void> { + %0 = cir.dyn_cast ptr %arg0 : !cir.ptr<!rec_Base> -> !cir.ptr<!void> + cir.return %0 : !cir.ptr<!void> + } + + // CHECK: cir.func dso_local @test_cast_to_void(%arg0: !cir.ptr<!rec_Base>) -> !cir.ptr<!void> { + // CHECK: %0 = cir.dyn_cast ptr %arg0 : !cir.ptr<!rec_Base> -> !cir.ptr<!void> + // CHECK: cir.return %0 : !cir.ptr<!void> + // CHECK: } + + cir.func dso_local @test_relative_layout_cast(%arg0: !cir.ptr<!rec_Base>) -> !cir.ptr<!void> { + %0 = cir.dyn_cast ptr relative_layout %arg0 : !cir.ptr<!rec_Base> -> !cir.ptr<!void> + cir.return %0 : !cir.ptr<!void> + } + + // CHECK: cir.func dso_local @test_relative_layout_cast(%arg0: !cir.ptr<!rec_Base>) -> !cir.ptr<!void> { + // CHECK: %0 = cir.dyn_cast ptr relative_layout %arg0 : !cir.ptr<!rec_Base> -> !cir.ptr<!void> + // CHECK: cir.return %0 : !cir.ptr<!void> + // CHECK: } +} diff --git a/clang/test/CIR/IR/invalid-dyn-cast.cir b/clang/test/CIR/IR/invalid-dyn-cast.cir new file mode 100644 index 0000000..65c7fc1 --- /dev/null +++ b/clang/test/CIR/IR/invalid-dyn-cast.cir @@ -0,0 +1,43 @@ +// RUN: cir-opt %s -verify-diagnostics -split-input-file + +!s64i = !cir.int<s, 64> +!s8i = !cir.int<s, 8> +!u32i = !cir.int<u, 32> +!u8i = !cir.int<u, 8> +!void = !cir.void + +!Base = !cir.record<struct "Base" {!cir.ptr<!cir.ptr<!cir.func<() -> !cir.int<u, 32>>>>}> +!Derived = !cir.record<struct "Derived" {!cir.record<struct "Base" {!cir.ptr<!cir.ptr<!cir.func<() -> !cir.int<u, 32>>>>}>}> + +module { + cir.global "private" constant external @_ZTI4Base : !cir.ptr<!u32i> + cir.global "private" constant external @_ZTI7Derived : !cir.ptr<!u8i> + cir.func private @__dynamic_cast(!cir.ptr<!void>, !cir.ptr<!u8i>, !cir.ptr<!u8i>, !s64i) -> !cir.ptr<!void> + cir.func private @__cxa_bad_cast() + cir.func @test(%arg0 : !cir.ptr<!Base>) { + // expected-error@+1 {{srcRtti must be an RTTI pointer}} + %0 = cir.dyn_cast ptr %arg0 : !cir.ptr<!Base> -> !cir.ptr<!Derived> #cir.dyn_cast_info<src_rtti = #cir.global_view<@_ZTI4Base> : !cir.ptr<!u32i>, dest_rtti = #cir.global_view<@_ZTI7Derived> : !cir.ptr<!u8i>, runtime_func = @__dynamic_cast, bad_cast_func = @__cxa_bad_cast, offset_hint = #cir.int<0> : !s64i> + } +} + +// ----- + +!s64i = !cir.int<s, 64> +!s8i = !cir.int<s, 8> +!u32i = !cir.int<u, 32> +!u8i = !cir.int<u, 8> +!void = !cir.void + +!Base = !cir.record<struct "Base" {!cir.ptr<!cir.ptr<!cir.func<() -> !cir.int<u, 32>>>>}> +!Derived = !cir.record<struct "Derived" {!cir.record<struct "Base" {!cir.ptr<!cir.ptr<!cir.func<() -> !cir.int<u, 32>>>>}>}> + +module { + cir.global "private" constant external @_ZTI4Base : !cir.ptr<!u8i> + cir.global "private" constant external @_ZTI7Derived : !cir.ptr<!u32i> + cir.func private @__dynamic_cast(!cir.ptr<!void>, !cir.ptr<!u8i>, !cir.ptr<!u8i>, !s64i) -> !cir.ptr<!void> + cir.func private @__cxa_bad_cast() + cir.func @test(%arg0 : !cir.ptr<!Base>) { + // expected-error@+1 {{destRtti must be an RTTI pointer}} + %0 = cir.dyn_cast ptr %arg0 : !cir.ptr<!Base> -> !cir.ptr<!Derived> #cir.dyn_cast_info<src_rtti = #cir.global_view<@_ZTI4Base> : !cir.ptr<!u8i>, dest_rtti = #cir.global_view<@_ZTI7Derived> : !cir.ptr<!u32i>, runtime_func = @__dynamic_cast, bad_cast_func = @__cxa_bad_cast, offset_hint = #cir.int<0> : !s64i> + } +} diff --git a/clang/test/Driver/aarch64-cpu-defaults-appleos26.c b/clang/test/Driver/aarch64-cpu-defaults-appleos26.c index 9917605..fe468a5 100644 --- a/clang/test/Driver/aarch64-cpu-defaults-appleos26.c +++ b/clang/test/Driver/aarch64-cpu-defaults-appleos26.c @@ -4,12 +4,16 @@ // RUN: %clang -target arm64-apple-ios26 -### -c %s 2>&1 | FileCheck %s --check-prefix=A12 // RUN: %clang -target arm64e-apple-ios26 -### -c %s 2>&1 | FileCheck %s --check-prefix=A12 +/// iOS 18 came before iOS 26, compare its defaults. +// RUN: %clang -target arm64-apple-ios18 -### -c %s 2>&1 | FileCheck %s --check-prefix=A10 +// RUN: %clang -target arm64e-apple-ios18 -### -c %s 2>&1 | FileCheck %s --check-prefix=A12 + /// arm64e/arm64_32 watchOS 26 default to apple-s6. // RUN: %clang -target arm64e-apple-watchos26 -### -c %s 2>&1 | FileCheck %s --check-prefix=S6 // RUN: %clang -target arm64_32-apple-watchos26 -### -c %s 2>&1 | FileCheck %s --check-prefix=S6 -/// arm64 is new in watchOS 26, and defaults to apple-s6. -// RUN: %clang -target arm64-apple-watchos26 -### -c %s 2>&1 | FileCheck %s --check-prefix=S6 +/// arm64 is new in watchOS 26, and defaults to apple-s9. +// RUN: %clang -target arm64-apple-watchos26 -### -c %s 2>&1 | FileCheck %s --check-prefix=S9 /// llvm usually treats tvOS like iOS, but it runs on different hardware. // RUN: %clang -target arm64-apple-tvos26 -### -c %s 2>&1 | FileCheck %s --check-prefix=A7 @@ -18,5 +22,7 @@ /// Simulators are tested with other Mac-like targets in aarch64-mac-cpus.c. // A12: "-target-cpu" "apple-a12" +// A10: "-target-cpu" "apple-a10" // S6: "-target-cpu" "apple-s6" +// S9: "-target-cpu" "apple-s9" // A7: "-target-cpu" "apple-a7" diff --git a/clang/test/Driver/darwin-maccatalyst-error.c b/clang/test/Driver/darwin-maccatalyst-error.c new file mode 100644 index 0000000..009249b --- /dev/null +++ b/clang/test/Driver/darwin-maccatalyst-error.c @@ -0,0 +1,6 @@ +// RUN: not %clang -target x86_64-apple-ios13.0-macabi -c %s -### 2>&1 | \ +// RUN: FileCheck --check-prefix=CHECK-ERROR %s +// RUN: not %clang -target x86_64-apple-ios12.0-macabi -c %s -### 2>&1 | \ +// RUN: FileCheck --check-prefix=CHECK-ERROR %s + +// CHECK-ERROR: error: invalid version number in '-target x86_64-apple-ios diff --git a/clang/test/Driver/darwin-maccatalyst.c b/clang/test/Driver/darwin-maccatalyst.c index 74a02ed..a8d53df 100644 --- a/clang/test/Driver/darwin-maccatalyst.c +++ b/clang/test/Driver/darwin-maccatalyst.c @@ -2,11 +2,6 @@ // RUN: FileCheck --check-prefix=CHECK-VERSION1 %s // RUN: %clang -target x86_64-apple-ios-macabi -c %s -### 2>&1 | \ // RUN: FileCheck --check-prefix=CHECK-VERSION1 %s -// RUN: not %clang -target x86_64-apple-ios13.0-macabi -c %s -### 2>&1 | \ -// RUN: FileCheck --check-prefix=CHECK-ERROR %s -// RUN: not %clang -target x86_64-apple-ios12.0-macabi -c %s -### 2>&1 | \ -// RUN: FileCheck --check-prefix=CHECK-ERROR %s // CHECK-VERSION1-NOT: error: // CHECK-VERSION1: "x86_64-apple-ios13.1.0-macabi" -// CHECK-ERROR: error: invalid version number in '-target x86_64-apple-ios diff --git a/clang/test/Driver/env.c b/clang/test/Driver/env.c index 56c037c..d1267c0 100644 --- a/clang/test/Driver/env.c +++ b/clang/test/Driver/env.c @@ -1,5 +1,7 @@ // Some assertions in this test use Linux style (/) file paths. -// UNSUPPORTED: system-windows +// TODO: Use LIBPATH on AIX +// UNSUPPORTED: system-windows, system-aix + // RUN: bash -c env | grep LD_LIBRARY_PATH | sed -ne 's/^.*=//p' | tr -d '\n' > %t.ld_library_path // The PATH variable is heavily used when trying to find a linker. // RUN: env -i LC_ALL=C LD_LIBRARY_PATH="%{readfile:%t.ld_library_path}" CLANG_NO_DEFAULT_CONFIG=1 \ diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index c44a0e8..7972b9e 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -216,7 +216,7 @@ // CHECK-NEXT: zibi 0.1 'Zibi' (Branch with Immediate) // CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad) // CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack) -// CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions) +// CHECK-NEXT: zalasr 0.9 'Zalasr' (Load-Acquire and Store-Release Instructions) // CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements) // CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support) // CHECK-NEXT: zvfofp8min 0.2 'Zvfofp8min' (Vector OFP8 Converts) diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c index 1da8311..37fe7a0 100644 --- a/clang/test/Driver/riscv-arch.c +++ b/clang/test/Driver/riscv-arch.c @@ -384,9 +384,9 @@ // RUN: not %clang --target=riscv32-unknown-elf -march=rv32izalasr0p7 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-BADVERS %s // RV32-EXPERIMENTAL-BADVERS: error: invalid arch name 'rv32izalasr0p7' -// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental extension 'zalasr' (this compiler supports 0.1) +// RV32-EXPERIMENTAL-BADVERS: unsupported version number 0.7 for experimental extension 'zalasr' (this compiler supports 0.9) -// RUN: %clang --target=riscv32-unknown-elf -march=rv32izalasr0p1 -menable-experimental-extensions -### %s \ +// RUN: %clang --target=riscv32-unknown-elf -march=rv32izalasr0p9 -menable-experimental-extensions -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EXPERIMENTAL-GOODVERS %s // RV32-EXPERIMENTAL-GOODVERS: "-target-feature" "+experimental-zalasr" diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 71d8453..77731a9 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -1531,12 +1531,12 @@ // Experimental extensions // RUN: %clang --target=riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32i_zalasr0p1 -E -dM %s \ +// RUN: -march=rv32i_zalasr0p9 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s // RUN: %clang --target=riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64i_zalasr0p1 -E -dM %s \ +// RUN: -march=rv64i_zalasr0p9 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s -// CHECK-ZALASR-EXT: __riscv_zalasr 1000{{$}} +// CHECK-ZALASR-EXT: __riscv_zalasr 9000{{$}} // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32izfbfmin1p0 -E -dM %s \ diff --git a/clang/test/Sema/warn-lifetime-safety.cpp b/clang/test/Sema/warn-lifetime-safety.cpp index f6bec6e..4f234f0 100644 --- a/clang/test/Sema/warn-lifetime-safety.cpp +++ b/clang/test/Sema/warn-lifetime-safety.cpp @@ -126,11 +126,15 @@ void definite_single_pointer_multiple_loans_gsl(bool cond) { v.use(); // expected-note 2 {{later used here}} } - -//===----------------------------------------------------------------------===// -// Potential (Maybe) Use-After-Free (-W...strict) -// These are cases where the pointer *may* become dangling, depending on the path taken. -//===----------------------------------------------------------------------===// +void definite_if_branch(bool cond) { + MyObj safe; + MyObj* p = &safe; + if (cond) { + MyObj temp; + p = &temp; // expected-warning {{object whose reference is captured does not live long enough}} + } // expected-note {{destroyed here}} + (void)*p; // expected-note {{later used here}} +} void potential_if_branch(bool cond) { MyObj safe; @@ -139,15 +143,18 @@ void potential_if_branch(bool cond) { MyObj temp; p = &temp; // expected-warning {{object whose reference is captured may not live long enough}} } // expected-note {{destroyed here}} - (void)*p; // expected-note {{later used here}} + if (!cond) + (void)*p; // expected-note {{later used here}} + else + p = &safe; } -void potential_if_branch_gsl(bool cond) { +void definite_if_branch_gsl(bool cond) { MyObj safe; View v = safe; if (cond) { MyObj temp; - v = temp; // expected-warning {{object whose reference is captured may not live long enough}} + v = temp; // expected-warning {{object whose reference is captured does not live long enough}} } // expected-note {{destroyed here}} v.use(); // expected-note {{later used here}} } @@ -159,13 +166,14 @@ void definite_potential_together(bool cond) { { MyObj s; - p_definite = &s; // expected-warning {{does not live long enough}} - if (cond) { - p_maybe = &s; // expected-warning {{may not live long enough}} - } - } // expected-note 2 {{destroyed here}} - (void)*p_definite; // expected-note {{later used here}} - (void)*p_maybe; // expected-note {{later used here}} + if (cond) + p_definite = &s; // expected-warning {{does not live long enough}} + if (cond) + p_maybe = &s; // expected-warning {{may not live long enough}} + } // expected-note 2 {{destroyed here}} + (void)*p_definite; // expected-note {{later used here}} + if (!cond) + (void)*p_maybe; // expected-note {{later used here}} } void definite_overrides_potential(bool cond) { @@ -189,10 +197,19 @@ void definite_overrides_potential(bool cond) { (void)*q; } - -//===----------------------------------------------------------------------===// -// Control Flow Tests -//===----------------------------------------------------------------------===// +void potential_due_to_conditional_killing(bool cond) { + MyObj safe; + MyObj* q; + { + MyObj s; + q = &s; // expected-warning {{may not live long enough}} + } // expected-note {{destroyed here}} + if (cond) { + // 'q' is conditionally "rescued". 'p' is not. + q = &safe; + } + (void)*q; // expected-note {{later used here}} +} void potential_for_loop_use_after_loop_body(MyObj safe) { MyObj* p = &safe; @@ -215,34 +232,35 @@ void potential_for_loop_gsl() { void potential_for_loop_use_before_loop_body(MyObj safe) { MyObj* p = &safe; + // Prefer the earlier use for diagnsotics. for (int i = 0; i < 1; ++i) { (void)*p; // expected-note {{later used here}} MyObj s; - p = &s; // expected-warning {{may not live long enough}} + p = &s; // expected-warning {{does not live long enough}} } // expected-note {{destroyed here}} (void)*p; } -void potential_loop_with_break(bool cond) { +void definite_loop_with_break(bool cond) { MyObj safe; MyObj* p = &safe; for (int i = 0; i < 10; ++i) { if (cond) { MyObj temp; - p = &temp; // expected-warning {{may not live long enough}} + p = &temp; // expected-warning {{does not live long enough}} break; // expected-note {{destroyed here}} } } (void)*p; // expected-note {{later used here}} } -void potential_loop_with_break_gsl(bool cond) { +void definite_loop_with_break_gsl(bool cond) { MyObj safe; View v = safe; for (int i = 0; i < 10; ++i) { if (cond) { MyObj temp; - v = temp; // expected-warning {{object whose reference is captured may not live long enough}} + v = temp; // expected-warning {{object whose reference is captured does not live long enough}} break; // expected-note {{destroyed here}} } } @@ -250,37 +268,52 @@ void potential_loop_with_break_gsl(bool cond) { } void potential_multiple_expiry_of_same_loan(bool cond) { - // Choose the last expiry location for the loan. + // Choose the last expiry location for the loan (e.g., through scope-ends and break statements). MyObj safe; MyObj* p = &safe; for (int i = 0; i < 10; ++i) { MyObj unsafe; if (cond) { - p = &unsafe; // expected-warning {{may not live long enough}} - break; + p = &unsafe; // expected-warning {{does not live long enough}} + break; // expected-note {{destroyed here}} } - } // expected-note {{destroyed here}} + } (void)*p; // expected-note {{later used here}} p = &safe; for (int i = 0; i < 10; ++i) { MyObj unsafe; if (cond) { - p = &unsafe; // expected-warning {{may not live long enough}} + p = &unsafe; // expected-warning {{does not live long enough}} if (cond) - break; + break; // expected-note {{destroyed here}} } - } // expected-note {{destroyed here}} + } (void)*p; // expected-note {{later used here}} p = &safe; for (int i = 0; i < 10; ++i) { if (cond) { MyObj unsafe2; - p = &unsafe2; // expected-warning {{may not live long enough}} + p = &unsafe2; // expected-warning {{does not live long enough}} break; // expected-note {{destroyed here}} } } + + // TODO: This can be argued to be a "maybe" warning. This is because + // we only check for confidence of liveness and not the confidence of + // the loan contained in an origin. To deal with this, we can introduce + // a confidence in loan propagation analysis as well like liveness. + (void)*p; // expected-note {{later used here}} + + p = &safe; + for (int i = 0; i < 10; ++i) { + MyObj unsafe; + if (cond) + p = &unsafe; // expected-warning {{does not live long enough}} + if (cond) + break; // expected-note {{destroyed here}} + } (void)*p; // expected-note {{later used here}} } @@ -298,13 +331,14 @@ void potential_switch(int mode) { break; } } - (void)*p; // expected-note {{later used here}} + if (mode == 2) + (void)*p; // expected-note {{later used here}} } void definite_switch(int mode) { MyObj safe; MyObj* p = &safe; - // All cases are UaF --> Definite error. + // A use domintates all the loan expires --> all definite error. switch (mode) { case 1: { MyObj temp1; @@ -347,6 +381,21 @@ void definite_switch_gsl(int mode) { v.use(); // expected-note 3 {{later used here}} } +void loan_from_previous_iteration(MyObj safe, bool condition) { + MyObj* p = &safe; + MyObj* q = &safe; + + while (condition) { + MyObj x; + p = &x; // expected-warning {{may not live long enough}} + + if (condition) + q = p; + (void)*p; + (void)*q; // expected-note {{later used here}} + } // expected-note {{destroyed here}} +} + //===----------------------------------------------------------------------===// // No-Error Cases //===----------------------------------------------------------------------===// @@ -372,6 +421,19 @@ void no_error_if_dangle_then_rescue_gsl() { v.use(); // This is safe. } +void no_error_loan_from_current_iteration(bool cond) { + // See https://github.com/llvm/llvm-project/issues/156959. + MyObj b; + while (cond) { + MyObj a; + View p = b; + if (cond) { + p = a; + } + (void)p; + } +} + //===----------------------------------------------------------------------===// // Lifetimebound Attribute Tests @@ -415,9 +477,9 @@ void lifetimebound_multiple_args_potential(bool cond) { MyObj obj1; if (cond) { MyObj obj2; - v = Choose(true, - obj1, // expected-warning {{object whose reference is captured may not live long enough}} - obj2); // expected-warning {{object whose reference is captured may not live long enough}} + v = Choose(true, + obj1, // expected-warning {{object whose reference is captured does not live long enough}} + obj2); // expected-warning {{object whose reference is captured does not live long enough}} } // expected-note {{destroyed here}} } // expected-note {{destroyed here}} v.use(); // expected-note 2 {{later used here}} @@ -488,7 +550,7 @@ void lifetimebound_partial_safety(bool cond) { MyObj temp_obj; v = Choose(true, safe_obj, - temp_obj); // expected-warning {{object whose reference is captured may not live long enough}} + temp_obj); // expected-warning {{object whose reference is captured does not live long enough}} } // expected-note {{destroyed here}} v.use(); // expected-note {{later used here}} } diff --git a/clang/unittests/AST/DeclPrinterTest.cpp b/clang/unittests/AST/DeclPrinterTest.cpp index 1a1b707..a412a98 100644 --- a/clang/unittests/AST/DeclPrinterTest.cpp +++ b/clang/unittests/AST/DeclPrinterTest.cpp @@ -1090,7 +1090,7 @@ TEST(DeclPrinter, TestClassTemplateDecl9) { "template<typename T> struct Z { };" "template<template<typename U> class T = Z> struct A { };", classTemplateDecl(hasName("A")).bind("id"), - "template <template <typename U> class T> struct A {}")); + "template <template <typename U> class T = Z> struct A {}")); } TEST(DeclPrinter, TestClassTemplateDecl10) { diff --git a/clang/unittests/Analysis/LifetimeSafetyTest.cpp b/clang/unittests/Analysis/LifetimeSafetyTest.cpp index 3821015..169b2d2 100644 --- a/clang/unittests/Analysis/LifetimeSafetyTest.cpp +++ b/clang/unittests/Analysis/LifetimeSafetyTest.cpp @@ -126,12 +126,12 @@ public: return Analysis.getLoansAtPoint(OID, PP); } - std::optional<std::vector<LoanID>> - getExpiredLoansAtPoint(llvm::StringRef Annotation) { + std::optional<std::vector<std::pair<OriginID, LivenessKind>>> + getLiveOriginsAtPoint(llvm::StringRef Annotation) { ProgramPoint PP = Runner.getProgramPoint(Annotation); if (!PP) return std::nullopt; - return Analysis.getExpiredLoansAtPoint(PP); + return Analysis.getLiveOriginsAtPoint(PP); } private: @@ -180,6 +180,15 @@ public: LifetimeTestHelper &Helper; }; +// A helper class to represent a set of origins, identified by variable names. +class OriginsInfo { +public: + OriginsInfo(const std::vector<std::string> &Vars, LifetimeTestHelper &H) + : OriginVars(Vars), Helper(H) {} + std::vector<std::string> OriginVars; + LifetimeTestHelper &Helper; +}; + /// Matcher to verify the set of loans held by an origin at a specific /// program point. /// @@ -221,14 +230,15 @@ MATCHER_P2(HasLoansToImpl, LoanVars, Annotation, "") { std::sort(ExpectedLoans.begin(), ExpectedLoans.end()); std::sort(ActualLoans.begin(), ActualLoans.end()); if (ExpectedLoans != ActualLoans) { - *result_listener << "Expected: "; + *result_listener << "Expected: {"; for (const auto &LoanID : ExpectedLoans) { *result_listener << LoanID.Value << ", "; } - *result_listener << "Actual: "; + *result_listener << "} Actual: {"; for (const auto &LoanID : ActualLoans) { *result_listener << LoanID.Value << ", "; } + *result_listener << "}"; return false; } @@ -236,32 +246,71 @@ MATCHER_P2(HasLoansToImpl, LoanVars, Annotation, "") { ActualLoans, result_listener); } -/// Matcher to verify that the complete set of expired loans at a program point -/// matches the expected loan set. -MATCHER_P(AreExpiredAt, Annotation, "") { - const LoanSetInfo &Info = arg; - auto &Helper = Info.Helper; +enum class LivenessKindFilter { Maybe, Must, All }; - auto ActualExpiredSetOpt = Helper.getExpiredLoansAtPoint(Annotation); - if (!ActualExpiredSetOpt) { - *result_listener << "could not get a valid expired loan set at point '" +/// Matcher to verify the complete set of live origins at a program point. +MATCHER_P2(AreLiveAtImpl, Annotation, ConfFilter, "") { + const OriginsInfo &Info = arg; + auto &Helper = Info.Helper; + auto ActualLiveSetOpt = Helper.getLiveOriginsAtPoint(Annotation); + if (!ActualLiveSetOpt) { + *result_listener << "could not get a valid live origin set at point '" << Annotation << "'"; return false; } - std::vector<LoanID> ActualExpiredLoans = *ActualExpiredSetOpt; - std::vector<LoanID> ExpectedExpiredLoans; - for (const auto &VarName : Info.LoanVars) { - auto LoanIDs = Helper.getLoansForVar(VarName); - if (LoanIDs.empty()) { - *result_listener << "could not find a loan for variable '" << VarName + std::vector<OriginID> ActualLiveOrigins; + for (const auto [OID, ActualConfidence] : ActualLiveSetOpt.value()) { + if (ConfFilter == LivenessKindFilter::All) + ActualLiveOrigins.push_back(OID); + if (ActualConfidence == LivenessKind::Maybe && + ConfFilter == LivenessKindFilter::Maybe) + ActualLiveOrigins.push_back(OID); + if (ActualConfidence == LivenessKind::Must && + ConfFilter == LivenessKindFilter::Must) + ActualLiveOrigins.push_back(OID); + } + + std::vector<OriginID> ExpectedLiveOrigins; + for (const auto &VarName : Info.OriginVars) { + auto OriginIDOpt = Helper.getOriginForDecl(VarName); + if (!OriginIDOpt) { + *result_listener << "could not find an origin for variable '" << VarName << "'"; return false; } - ExpectedExpiredLoans.insert(ExpectedExpiredLoans.end(), LoanIDs.begin(), - LoanIDs.end()); + ExpectedLiveOrigins.push_back(*OriginIDOpt); } - return ExplainMatchResult(UnorderedElementsAreArray(ExpectedExpiredLoans), - ActualExpiredLoans, result_listener); + std::sort(ExpectedLiveOrigins.begin(), ExpectedLiveOrigins.end()); + std::sort(ActualLiveOrigins.begin(), ActualLiveOrigins.end()); + if (ExpectedLiveOrigins != ActualLiveOrigins) { + *result_listener << "Expected: {"; + for (const auto &OriginID : ExpectedLiveOrigins) { + *result_listener << OriginID.Value << ", "; + } + *result_listener << "} Actual: {"; + for (const auto &OriginID : ActualLiveOrigins) { + *result_listener << OriginID.Value << ", "; + } + *result_listener << "}"; + return false; + } + return true; +} + +MATCHER_P(MustBeLiveAt, Annotation, "") { + return ExplainMatchResult(AreLiveAtImpl(Annotation, LivenessKindFilter::Must), + arg, result_listener); +} + +MATCHER_P(MaybeLiveAt, Annotation, "") { + return ExplainMatchResult( + AreLiveAtImpl(Annotation, LivenessKindFilter::Maybe), arg, + result_listener); +} + +MATCHER_P(AreLiveAt, Annotation, "") { + return ExplainMatchResult(AreLiveAtImpl(Annotation, LivenessKindFilter::All), + arg, result_listener); } // Base test fixture to manage the runner and helper. @@ -277,6 +326,13 @@ protected: } /// Factory function that hides the std::vector creation. + OriginsInfo Origins(std::initializer_list<std::string> OriginVars) { + return OriginsInfo({OriginVars}, *Helper); + } + + OriginsInfo NoOrigins() { return Origins({}); } + + /// Factory function that hides the std::vector creation. LoanSetInfo LoansTo(std::initializer_list<std::string> LoanVars) { return LoanSetInfo({LoanVars}, *Helper); } @@ -428,29 +484,6 @@ TEST_F(LifetimeAnalysisTest, AssignInSwitch) { EXPECT_THAT(Origin("p"), HasLoansTo({"s1", "s2", "s3"}, "after_switch")); } -TEST_F(LifetimeAnalysisTest, LoanInLoop) { - SetupTest(R"( - void target(bool condition) { - MyObj* p = nullptr; - while (condition) { - POINT(start_loop); - MyObj inner; - p = &inner; - POINT(end_loop); - } - POINT(after_loop); - } - )"); - EXPECT_THAT(Origin("p"), HasLoansTo({"inner"}, "start_loop")); - EXPECT_THAT(LoansTo({"inner"}), AreExpiredAt("start_loop")); - - EXPECT_THAT(Origin("p"), HasLoansTo({"inner"}, "end_loop")); - EXPECT_THAT(NoLoans(), AreExpiredAt("end_loop")); - - EXPECT_THAT(Origin("p"), HasLoansTo({"inner"}, "after_loop")); - EXPECT_THAT(LoansTo({"inner"}), AreExpiredAt("after_loop")); -} - TEST_F(LifetimeAnalysisTest, LoopWithBreak) { SetupTest(R"( void target(int count) { @@ -528,20 +561,16 @@ TEST_F(LifetimeAnalysisTest, PointersAndExpirationInACycle) { )"); EXPECT_THAT(Origin("p1"), HasLoansTo({"v1"}, "before_while")); EXPECT_THAT(Origin("p2"), HasLoansTo({"v2"}, "before_while")); - EXPECT_THAT(NoLoans(), AreExpiredAt("before_while")); EXPECT_THAT(Origin("p1"), HasLoansTo({"v1", "v2", "temp"}, "in_loop_before_temp")); EXPECT_THAT(Origin("p2"), HasLoansTo({"v2", "temp"}, "in_loop_before_temp")); - EXPECT_THAT(LoansTo({"temp"}), AreExpiredAt("in_loop_before_temp")); EXPECT_THAT(Origin("p1"), HasLoansTo({"temp"}, "in_loop_after_temp")); EXPECT_THAT(Origin("p2"), HasLoansTo({"v2", "temp"}, "in_loop_after_temp")); - EXPECT_THAT(NoLoans(), AreExpiredAt("in_loop_after_temp")); EXPECT_THAT(Origin("p1"), HasLoansTo({"v1", "v2", "temp"}, "after_loop")); EXPECT_THAT(Origin("p2"), HasLoansTo({"v2", "temp"}, "after_loop")); - EXPECT_THAT(LoansTo({"temp"}), AreExpiredAt("after_loop")); } TEST_F(LifetimeAnalysisTest, InfiniteLoopPrunesEdges) { @@ -585,178 +614,6 @@ TEST_F(LifetimeAnalysisTest, NestedScopes) { EXPECT_THAT(Origin("p"), HasLoansTo({"inner"}, "after_inner_scope")); } -TEST_F(LifetimeAnalysisTest, SimpleExpiry) { - SetupTest(R"( - void target() { - MyObj* p = nullptr; - { - MyObj s; - p = &s; - POINT(before_expiry); - } // s goes out of scope here - POINT(after_expiry); - } - )"); - EXPECT_THAT(NoLoans(), AreExpiredAt("before_expiry")); - EXPECT_THAT(LoansTo({"s"}), AreExpiredAt("after_expiry")); -} - -TEST_F(LifetimeAnalysisTest, NestedExpiry) { - SetupTest(R"( - void target() { - MyObj s1; - MyObj* p = &s1; - POINT(before_inner); - { - MyObj s2; - p = &s2; - POINT(in_inner); - } // s2 expires - POINT(after_inner); - } - )"); - EXPECT_THAT(NoLoans(), AreExpiredAt("before_inner")); - EXPECT_THAT(NoLoans(), AreExpiredAt("in_inner")); - EXPECT_THAT(LoansTo({"s2"}), AreExpiredAt("after_inner")); -} - -TEST_F(LifetimeAnalysisTest, ConditionalExpiry) { - SetupTest(R"( - void target(bool cond) { - MyObj s1; - MyObj* p = &s1; - POINT(before_if); - if (cond) { - MyObj s2; - p = &s2; - POINT(then_block); - } // s2 expires here - POINT(after_if); - } - )"); - EXPECT_THAT(NoLoans(), AreExpiredAt("before_if")); - EXPECT_THAT(NoLoans(), AreExpiredAt("then_block")); - EXPECT_THAT(LoansTo({"s2"}), AreExpiredAt("after_if")); -} - -TEST_F(LifetimeAnalysisTest, LoopExpiry) { - SetupTest(R"( - void target() { - MyObj *p = nullptr; - for (int i = 0; i < 2; ++i) { - POINT(start_loop); - MyObj s; - p = &s; - POINT(end_loop); - } // s expires here on each iteration - POINT(after_loop); - } - )"); - EXPECT_THAT(LoansTo({"s"}), AreExpiredAt("start_loop")); - EXPECT_THAT(NoLoans(), AreExpiredAt("end_loop")); - EXPECT_THAT(LoansTo({"s"}), AreExpiredAt("after_loop")); -} - -TEST_F(LifetimeAnalysisTest, MultipleExpiredLoans) { - SetupTest(R"( - void target() { - MyObj *p1, *p2, *p3; - { - MyObj s1; - p1 = &s1; - POINT(p1); - } // s1 expires - POINT(p2); - { - MyObj s2; - p2 = &s2; - MyObj s3; - p3 = &s3; - POINT(p3); - } // s2, s3 expire - POINT(p4); - } - )"); - EXPECT_THAT(NoLoans(), AreExpiredAt("p1")); - EXPECT_THAT(LoansTo({"s1"}), AreExpiredAt("p2")); - EXPECT_THAT(LoansTo({"s1"}), AreExpiredAt("p3")); - EXPECT_THAT(LoansTo({"s1", "s2", "s3"}), AreExpiredAt("p4")); -} - -TEST_F(LifetimeAnalysisTest, GotoJumpsOutOfScope) { - SetupTest(R"( - void target(bool cond) { - MyObj *p = nullptr; - { - MyObj s; - p = &s; - POINT(before_goto); - if (cond) { - goto end; - } - } // `s` expires here on the path that doesn't jump - POINT(after_scope); - end: - POINT(after_goto); - } - )"); - EXPECT_THAT(NoLoans(), AreExpiredAt("before_goto")); - EXPECT_THAT(LoansTo({"s"}), AreExpiredAt("after_scope")); - EXPECT_THAT(LoansTo({"s"}), AreExpiredAt("after_goto")); -} - -TEST_F(LifetimeAnalysisTest, ContinueInLoop) { - SetupTest(R"( - void target(int count) { - MyObj *p = nullptr; - MyObj outer; - p = &outer; - POINT(before_loop); - - for (int i = 0; i < count; ++i) { - if (i % 2 == 0) { - MyObj s_even; - p = &s_even; - POINT(in_even_iter); - continue; - } - MyObj s_odd; - p = &s_odd; - POINT(in_odd_iter); - } - POINT(after_loop); - } - )"); - EXPECT_THAT(NoLoans(), AreExpiredAt("before_loop")); - EXPECT_THAT(LoansTo({"s_odd"}), AreExpiredAt("in_even_iter")); - EXPECT_THAT(LoansTo({"s_even"}), AreExpiredAt("in_odd_iter")); - EXPECT_THAT(LoansTo({"s_even", "s_odd"}), AreExpiredAt("after_loop")); -} - -TEST_F(LifetimeAnalysisTest, ReassignedPointerThenOriginalExpires) { - SetupTest(R"( - void target() { - MyObj* p = nullptr; - { - MyObj s1; - p = &s1; - POINT(p_has_s1); - { - MyObj s2; - p = &s2; - POINT(p_has_s2); - } - POINT(p_after_s2_expires); - } // s1 expires here. - POINT(p_after_s1_expires); - } - )"); - EXPECT_THAT(NoLoans(), AreExpiredAt("p_has_s1")); - EXPECT_THAT(NoLoans(), AreExpiredAt("p_has_s2")); - EXPECT_THAT(LoansTo({"s2"}), AreExpiredAt("p_after_s2_expires")); - EXPECT_THAT(LoansTo({"s1", "s2"}), AreExpiredAt("p_after_s1_expires")); -} - TEST_F(LifetimeAnalysisTest, NoDuplicateLoansForImplicitCastToConst) { SetupTest(R"( void target() { @@ -880,23 +737,6 @@ TEST_F(LifetimeAnalysisTest, GslPointerPropagation) { EXPECT_THAT(Origin("z"), HasLoansTo({"a"}, "p3")); } -TEST_F(LifetimeAnalysisTest, GslPointerLoanExpiration) { - SetupTest(R"( - void target() { - View x; - { - MyObj a; - x = a; - POINT(before_expiry); - } // `a` is destroyed here. - POINT(after_expiry); - } - )"); - - EXPECT_THAT(NoLoans(), AreExpiredAt("before_expiry")); - EXPECT_THAT(LoansTo({"a"}), AreExpiredAt("after_expiry")); -} - TEST_F(LifetimeAnalysisTest, GslPointerReassignment) { SetupTest(R"( void target() { @@ -916,7 +756,6 @@ TEST_F(LifetimeAnalysisTest, GslPointerReassignment) { EXPECT_THAT(Origin("v"), HasLoansTo({"safe"}, "p1")); EXPECT_THAT(Origin("v"), HasLoansTo({"unsafe"}, "p2")); EXPECT_THAT(Origin("v"), HasLoansTo({"unsafe"}, "p3")); - EXPECT_THAT(LoansTo({"unsafe"}), AreExpiredAt("p3")); } TEST_F(LifetimeAnalysisTest, GslPointerConversionOperator) { @@ -1174,5 +1013,187 @@ TEST_F(LifetimeAnalysisTest, LifetimeboundConversionOperator) { )"); EXPECT_THAT(Origin("v"), HasLoansTo({"owner"}, "p1")); } + +TEST_F(LifetimeAnalysisTest, LivenessDeadPointer) { + SetupTest(R"( + void target() { + POINT(p1); + MyObj s; + MyObj* p = &s; + POINT(p2); + } + )"); + EXPECT_THAT(NoOrigins(), AreLiveAt("p2")); + EXPECT_THAT(NoOrigins(), AreLiveAt("p1")); +} + +TEST_F(LifetimeAnalysisTest, LivenessSimpleReturn) { + SetupTest(R"( + MyObj* target() { + MyObj s; + MyObj* p = &s; + POINT(p1); + return p; + } + )"); + EXPECT_THAT(Origins({"p"}), MustBeLiveAt("p1")); +} + +TEST_F(LifetimeAnalysisTest, LivenessKilledByReassignment) { + SetupTest(R"( + MyObj* target() { + MyObj s1, s2; + MyObj* p = &s1; + POINT(p1); + p = &s2; + POINT(p2); + return p; + } + )"); + EXPECT_THAT(Origins({"p"}), MustBeLiveAt("p2")); + EXPECT_THAT(NoOrigins(), AreLiveAt("p1")); +} + +TEST_F(LifetimeAnalysisTest, LivenessAcrossBranches) { + SetupTest(R"( + MyObj* target(bool c) { + MyObj x, y; + MyObj* p = nullptr; + POINT(p1); + if (c) { + p = &x; + POINT(p2); + } else { + p = &y; + POINT(p3); + } + return p; + } + )"); + EXPECT_THAT(Origins({"p"}), MustBeLiveAt("p2")); + EXPECT_THAT(Origins({"p"}), MustBeLiveAt("p3")); + // Before the `if`, the value of `p` (`nullptr`) is always overwritten before. + EXPECT_THAT(NoOrigins(), AreLiveAt("p1")); +} + +TEST_F(LifetimeAnalysisTest, LivenessInLoop) { + SetupTest(R"( + MyObj* target(bool c) { + MyObj s1, s2; + MyObj* p = &s1; + MyObj* q = &s2; + POINT(p1); + while(c) { + POINT(p2); + + p = q; + POINT(p3); + } + POINT(p4); + return p; + } + )"); + + EXPECT_THAT(Origins({"p"}), MustBeLiveAt("p4")); + EXPECT_THAT(NoOrigins(), MaybeLiveAt("p4")); + + EXPECT_THAT(Origins({"p", "q"}), MaybeLiveAt("p3")); + + EXPECT_THAT(Origins({"q"}), MustBeLiveAt("p2")); + EXPECT_THAT(NoOrigins(), MaybeLiveAt("p2")); + + EXPECT_THAT(Origins({"p", "q"}), MaybeLiveAt("p1")); +} + +TEST_F(LifetimeAnalysisTest, LivenessInLoopAndIf) { + // See https://github.com/llvm/llvm-project/issues/156959. + SetupTest(R"( + void target(bool cond) { + MyObj b; + while (cond) { + POINT(p1); + + MyObj a; + View p = b; + + POINT(p2); + + if (cond) { + POINT(p3); + p = a; + } + POINT(p4); + (void)p; + POINT(p5); + } + } + )"); + EXPECT_THAT(NoOrigins(), AreLiveAt("p5")); + EXPECT_THAT(Origins({"p"}), MustBeLiveAt("p4")); + EXPECT_THAT(NoOrigins(), AreLiveAt("p3")); + EXPECT_THAT(Origins({"p"}), MaybeLiveAt("p2")); + EXPECT_THAT(NoOrigins(), AreLiveAt("p1")); +} + +TEST_F(LifetimeAnalysisTest, LivenessInLoopAndIf2) { + SetupTest(R"( + void target(MyObj safe, bool condition) { + MyObj* p = &safe; + MyObj* q = &safe; + POINT(p1); + + while (condition) { + POINT(p2); + MyObj x; + p = &x; + + POINT(p3); + + if (condition) { + q = p; + POINT(p4); + } + + POINT(p5); + (void)*p; + (void)*q; + POINT(p6); + } + } + )"); + EXPECT_THAT(Origins({"q"}), MaybeLiveAt("p6")); + EXPECT_THAT(NoOrigins(), MustBeLiveAt("p6")); + + EXPECT_THAT(Origins({"p", "q"}), MustBeLiveAt("p5")); + + EXPECT_THAT(Origins({"p", "q"}), MustBeLiveAt("p4")); + + EXPECT_THAT(Origins({"p"}), MustBeLiveAt("p3")); + EXPECT_THAT(Origins({"q"}), MaybeLiveAt("p3")); + + EXPECT_THAT(Origins({"q"}), MaybeLiveAt("p2")); + EXPECT_THAT(NoOrigins(), MustBeLiveAt("p2")); + + EXPECT_THAT(Origins({"q"}), MaybeLiveAt("p1")); + EXPECT_THAT(NoOrigins(), MustBeLiveAt("p1")); +} + +TEST_F(LifetimeAnalysisTest, LivenessOutsideLoop) { + SetupTest(R"( + void target(MyObj safe) { + MyObj* p = &safe; + for (int i = 0; i < 1; ++i) { + MyObj s; + p = &s; + POINT(p1); + } + POINT(p2); + (void)*p; + } + )"); + EXPECT_THAT(Origins({"p"}), MustBeLiveAt("p2")); + EXPECT_THAT(Origins({"p"}), MaybeLiveAt("p1")); +} + } // anonymous namespace } // namespace clang::lifetimes::internal diff --git a/compiler-rt/lib/builtins/cpu_model/aarch64.c b/compiler-rt/lib/builtins/cpu_model/aarch64.c index 8af736d..be29c90 100644 --- a/compiler-rt/lib/builtins/cpu_model/aarch64.c +++ b/compiler-rt/lib/builtins/cpu_model/aarch64.c @@ -19,15 +19,13 @@ #error This file is intended only for aarch64-based targets #endif -#if __has_include(<sys/ifunc.h>) -#include <sys/ifunc.h> -#else typedef struct __ifunc_arg_t { unsigned long _size; unsigned long _hwcap; unsigned long _hwcap2; + unsigned long _hwcap3; + unsigned long _hwcap4; } __ifunc_arg_t; -#endif // __has_include(<sys/ifunc.h>) // LSE support detection for out-of-line atomics // using HWCAP and Auxiliary vector diff --git a/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/android.inc b/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/android.inc index a9e3594..d19beca 100644 --- a/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/android.inc +++ b/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/android.inc @@ -27,10 +27,14 @@ void CONSTRUCTOR_ATTRIBUTE __init_cpu_features(void) { unsigned long hwcap = getauxval(AT_HWCAP); unsigned long hwcap2 = getauxval(AT_HWCAP2); + unsigned long hwcap3 = getauxval(AT_HWCAP3); + unsigned long hwcap4 = getauxval(AT_HWCAP4); __ifunc_arg_t arg; arg._size = sizeof(__ifunc_arg_t); arg._hwcap = hwcap; arg._hwcap2 = hwcap2; + arg._hwcap3 = hwcap3; + arg._hwcap4 = hwcap4; __init_cpu_features_constructor(hwcap | _IFUNC_ARG_HWCAP, &arg); } diff --git a/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/elf_aux_info.inc b/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/elf_aux_info.inc index aa975dc..1ada7b6 100644 --- a/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/elf_aux_info.inc +++ b/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/elf_aux_info.inc @@ -7,21 +7,21 @@ void __init_cpu_features_resolver(unsigned long hwcap, } void CONSTRUCTOR_ATTRIBUTE __init_cpu_features(void) { - unsigned long hwcap = 0; - unsigned long hwcap2 = 0; + unsigned long hwcap, hwcap2, hwcap3, hwcap4 = 0; // CPU features already initialized. if (__atomic_load_n(&__aarch64_cpu_features.features, __ATOMIC_RELAXED)) return; - int res = 0; - res = elf_aux_info(AT_HWCAP, &hwcap, sizeof hwcap); - res |= elf_aux_info(AT_HWCAP2, &hwcap2, sizeof hwcap2); - if (res) - return; + elf_aux_info(AT_HWCAP, &hwcap, sizeof hwcap); + elf_aux_info(AT_HWCAP2, &hwcap2, sizeof hwcap2); + elf_aux_info(AT_HWCAP3, &hwcap3, sizeof hwcap3); + elf_aux_info(AT_HWCAP4, &hwcap4, sizeof hwcap4); __ifunc_arg_t arg; arg._size = sizeof(__ifunc_arg_t); arg._hwcap = hwcap; arg._hwcap2 = hwcap2; + arg._hwcap3 = hwcap3; + arg._hwcap4 = hwcap4; __init_cpu_features_constructor(hwcap | _IFUNC_ARG_HWCAP, &arg); } diff --git a/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/getauxval.inc b/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/getauxval.inc index 486f77a..6c52c53 100644 --- a/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/getauxval.inc +++ b/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/getauxval.inc @@ -12,10 +12,14 @@ void CONSTRUCTOR_ATTRIBUTE __init_cpu_features(void) { unsigned long hwcap = getauxval(AT_HWCAP); unsigned long hwcap2 = getauxval(AT_HWCAP2); + unsigned long hwcap3 = getauxval(AT_HWCAP3); + unsigned long hwcap4 = getauxval(AT_HWCAP4); __ifunc_arg_t arg; arg._size = sizeof(__ifunc_arg_t); arg._hwcap = hwcap; arg._hwcap2 = hwcap2; + arg._hwcap3 = hwcap3; + arg._hwcap4 = hwcap4; __init_cpu_features_constructor(hwcap | _IFUNC_ARG_HWCAP, &arg); } diff --git a/compiler-rt/lib/builtins/cpu_model/aarch64/hwcap.inc b/compiler-rt/lib/builtins/cpu_model/aarch64/hwcap.inc index 2f44e9e..159c617 100644 --- a/compiler-rt/lib/builtins/cpu_model/aarch64/hwcap.inc +++ b/compiler-rt/lib/builtins/cpu_model/aarch64/hwcap.inc @@ -7,7 +7,7 @@ #define _IFUNC_ARG_HWCAP (1ULL << 62) #endif #ifndef AT_HWCAP -#define AT_HWCAP 16 +#define AT_HWCAP 16 // Linux value #endif #ifndef HWCAP_CPUID #define HWCAP_CPUID (1 << 11) @@ -95,7 +95,7 @@ #endif #ifndef AT_HWCAP2 -#define AT_HWCAP2 26 +#define AT_HWCAP2 26 // Linux value #endif #ifndef HWCAP2_DCPODP #define HWCAP2_DCPODP (1 << 0) @@ -190,3 +190,19 @@ #ifndef HWCAP2_CSSC #define HWCAP2_CSSC (1UL << 34) #endif + +#ifndef AT_HWCAP3 +#ifdef __linux__ +#define AT_HWCAP3 29 // Linux value +#else +#define AT_HWCAP3 38 // BSD value +#endif +#endif + +#ifndef AT_HWCAP4 +#ifdef __linux__ +#define AT_HWCAP4 30 // Linux value +#else +#define AT_HWCAP4 39 // BSD value +#endif +#endif diff --git a/compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp b/compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp index 6b65387..61c9bbb 100644 --- a/compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp +++ b/compiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp @@ -680,7 +680,8 @@ ThreadState *cur_thread() { // significant bit of TLS_SLOT_SANITIZER to 1. Scudo allocator uses this bit // as a flag to disable memory initialization. This is a workaround to get the // correct ThreadState pointer. - reinterpret_cast<ThreadState*>(addr & ~1ULL); + uptr addr = reinterpret_cast<uptr>(thr); + return reinterpret_cast<ThreadState*>(addr & ~1ULL); } void set_cur_thread(ThreadState *thr) { diff --git a/compiler-rt/test/sanitizer_common/TestCases/Linux/getpwnam_r_invalid_user.cpp b/compiler-rt/test/sanitizer_common/TestCases/Linux/getpwnam_r_invalid_user.cpp index c0d6cfe..4c6cffe 100644 --- a/compiler-rt/test/sanitizer_common/TestCases/Linux/getpwnam_r_invalid_user.cpp +++ b/compiler-rt/test/sanitizer_common/TestCases/Linux/getpwnam_r_invalid_user.cpp @@ -14,6 +14,8 @@ int main(void) { struct passwd *pwdres; char buf[10000]; int res = getpwnam_r("no-such-user", &pwd, buf, sizeof(buf), &pwdres); + fprintf(stderr, "Result: %d\n", res); + fflush(stderr); assert(res == 0 || res == ENOENT); assert(pwdres == 0); return 0; diff --git a/flang/test/Lower/OpenMP/atomic-control-options.f90 b/flang/test/Lower/OpenMP/atomic-control-options.f90 index 407f83b..6654305 100644 --- a/flang/test/Lower/OpenMP/atomic-control-options.f90 +++ b/flang/test/Lower/OpenMP/atomic-control-options.f90 @@ -8,25 +8,17 @@ program test threads = 128 A = 0 B = 0 - !UNSAFE-FP-ATOMICS: omp.atomic.update %{{.*}} : !fir.ref<i32> { !UNSAFE-FP-ATOMICS: } {atomic_control = #omp.atomic_control<ignore_denormal_mode = true>} - !IGNORE-DENORMAL: omp.atomic.update %{{.*}} : !fir.ref<i32> { !IGNORE-DENORMAL: } {atomic_control = #omp.atomic_control<ignore_denormal_mode = true>} - !FINE-GRAINED-MEMORY: omp.atomic.update %{{.*}} : !fir.ref<i32> { !FINE-GRAINED-MEMORY: } {atomic_control = #omp.atomic_control<fine_grained_memory = true>} - !REMOTE-MEMORY: omp.atomic.update %{{.*}} : !fir.ref<i32> { !REMOTE-MEMORY: } {atomic_control = #omp.atomic_control<remote_memory = true>} !$omp target parallel num_threads(threads) !$omp atomic A = A + 1 !$omp end target parallel - !UNSAFE-FP-ATOMICS: omp.atomic.update %{{.*}} : !fir.ref<i32> { !UNSAFE-FP-ATOMICS: } {atomic_control = #omp.atomic_control<ignore_denormal_mode = true>} - !IGNORE-DENORMAL: omp.atomic.update %{{.*}} : !fir.ref<i32> { !IGNORE-DENORMAL: } {atomic_control = #omp.atomic_control<ignore_denormal_mode = true>} - !FINE-GRAINED-MEMORY: omp.atomic.update %{{.*}} : !fir.ref<i32> { !FINE-GRAINED-MEMORY: } {atomic_control = #omp.atomic_control<fine_grained_memory = true>} - !REMOTE-MEMORY: omp.atomic.update %{{.*}} : !fir.ref<i32> { !REMOTE-MEMORY: } {atomic_control = #omp.atomic_control<remote_memory = true>} !$omp target parallel num_threads(threads) !$omp atomic capture diff --git a/libc/src/__support/RPC/rpc_server.h b/libc/src/__support/RPC/rpc_server.h index 4bd8a93..4c8242a 100644 --- a/libc/src/__support/RPC/rpc_server.h +++ b/libc/src/__support/RPC/rpc_server.h @@ -395,7 +395,9 @@ LIBC_INLINE static rpc::Status handle_port_impl(rpc::Server::Port &port) { port.recv([](rpc::Buffer *buffer, uint32_t) { int status = 0; __builtin_memcpy(&status, buffer->data, sizeof(int)); - exit(status); + // We want a quick exit to avoid conflicts with offloading library + // teardowns when called from the GPU. + quick_exit(status); }); break; } diff --git a/libcxx/src/system_error.cpp b/libcxx/src/system_error.cpp index 164fb72..6397a94 100644 --- a/libcxx/src/system_error.cpp +++ b/libcxx/src/system_error.cpp @@ -95,6 +95,8 @@ std::optional<errc> __win_err_to_errc(int err) { return errc::no_lock_available; case ERROR_NEGATIVE_SEEK: return errc::invalid_argument; + case ERROR_NETNAME_DELETED: + return errc::no_such_file_or_directory; case ERROR_NOACCESS: return errc::permission_denied; case ERROR_NOT_ENOUGH_MEMORY: diff --git a/lldb/include/lldb/API/SBDebugger.h b/lldb/include/lldb/API/SBDebugger.h index f77b0c1..7a08a08 100644 --- a/lldb/include/lldb/API/SBDebugger.h +++ b/lldb/include/lldb/API/SBDebugger.h @@ -359,6 +359,9 @@ public: lldb::SBTarget FindTargetWithFileAndArch(const char *filename, const char *arch); + /// Find a target with the specified unique ID. + lldb::SBTarget FindTargetByGloballyUniqueID(lldb::user_id_t id); + /// Get the number of targets in the debugger. uint32_t GetNumTargets(); diff --git a/lldb/include/lldb/API/SBTarget.h b/lldb/include/lldb/API/SBTarget.h index 62cdd34..173fd05 100644 --- a/lldb/include/lldb/API/SBTarget.h +++ b/lldb/include/lldb/API/SBTarget.h @@ -357,6 +357,14 @@ public: const char *GetLabel() const; + /// Get the globally unique ID for this target. This ID is unique + /// across all debugger instances within the same lldb process. + /// + /// \return + /// The globally unique ID for this target, or + /// LLDB_INVALID_GLOBALLY_UNIQUE_TARGET_ID if the target is invalid. + lldb::user_id_t GetGloballyUniqueID() const; + SBError SetLabel(const char *label); /// Architecture opcode byte size width accessor diff --git a/lldb/include/lldb/Target/Target.h b/lldb/include/lldb/Target/Target.h index 14a09f2..f4a0923 100644 --- a/lldb/include/lldb/Target/Target.h +++ b/lldb/include/lldb/Target/Target.h @@ -600,6 +600,17 @@ public: bool IsDummyTarget() const { return m_is_dummy_target; } + /// Get the globally unique ID for this target. + /// + /// This ID is unique across all debugger instances and all targets, + /// within the same lldb process. The ID is assigned + /// during target construction and remains constant for the target's lifetime. + /// The first target created (typically the dummy target) gets ID 1. + /// + /// \return + /// The globally unique ID for this target. + lldb::user_id_t GetGloballyUniqueID() const { return m_target_unique_id; } + const std::string &GetLabel() const { return m_label; } /// Set a label for a target. @@ -1651,6 +1662,9 @@ protected: bool m_suppress_stop_hooks; /// Used to not run stop hooks for expressions bool m_is_dummy_target; unsigned m_next_persistent_variable_index = 0; + lldb::user_id_t m_target_unique_id = + LLDB_INVALID_GLOBALLY_UNIQUE_TARGET_ID; /// The globally unique ID + /// assigned to this target /// An optional \a lldb_private::Trace object containing processor trace /// information of this target. lldb::TraceSP m_trace_sp; diff --git a/lldb/include/lldb/Target/TargetList.h b/lldb/include/lldb/Target/TargetList.h index 080a603..8827251 100644 --- a/lldb/include/lldb/Target/TargetList.h +++ b/lldb/include/lldb/Target/TargetList.h @@ -159,6 +159,17 @@ public: lldb::TargetSP FindTargetWithProcess(lldb_private::Process *process) const; + /// Find the target that has a globally unique ID that matches ID \a id. + /// + /// \param[in] id + /// The globally unique target ID to search our target list for. + /// + /// \return + /// A shared pointer to a target object. The returned shared + /// pointer will contain nullptr if no target objects has a + /// matching target ID. + lldb::TargetSP FindTargetByGloballyUniqueID(lldb::user_id_t id) const; + lldb::TargetSP GetTargetSP(Target *target) const; /// Send an async interrupt to one or all processes. diff --git a/lldb/include/lldb/lldb-defines.h b/lldb/include/lldb/lldb-defines.h index c7bd019..c54ef88 100644 --- a/lldb/include/lldb/lldb-defines.h +++ b/lldb/include/lldb/lldb-defines.h @@ -96,6 +96,7 @@ #define LLDB_INVALID_QUEUE_ID 0 #define LLDB_INVALID_CPU_ID UINT32_MAX #define LLDB_INVALID_WATCHPOINT_RESOURCE_ID UINT32_MAX +#define LLDB_INVALID_GLOBALLY_UNIQUE_TARGET_ID 0 /// CPU Type definitions #define LLDB_ARCH_DEFAULT "systemArch" diff --git a/lldb/source/API/SBDebugger.cpp b/lldb/source/API/SBDebugger.cpp index 603e306..5c4c653 100644 --- a/lldb/source/API/SBDebugger.cpp +++ b/lldb/source/API/SBDebugger.cpp @@ -983,6 +983,17 @@ uint32_t SBDebugger::GetIndexOfTarget(lldb::SBTarget target) { return m_opaque_sp->GetTargetList().GetIndexOfTarget(target.GetSP()); } +SBTarget SBDebugger::FindTargetByGloballyUniqueID(lldb::user_id_t id) { + LLDB_INSTRUMENT_VA(this, id); + SBTarget sb_target; + if (m_opaque_sp) { + // No need to lock, the target list is thread safe + sb_target.SetSP( + m_opaque_sp->GetTargetList().FindTargetByGloballyUniqueID(id)); + } + return sb_target; +} + SBTarget SBDebugger::FindTargetWithProcessID(lldb::pid_t pid) { LLDB_INSTRUMENT_VA(this, pid); diff --git a/lldb/source/API/SBTarget.cpp b/lldb/source/API/SBTarget.cpp index 0d03250..98d10aa 100644 --- a/lldb/source/API/SBTarget.cpp +++ b/lldb/source/API/SBTarget.cpp @@ -1633,6 +1633,14 @@ const char *SBTarget::GetLabel() const { return nullptr; } +lldb::user_id_t SBTarget::GetGloballyUniqueID() const { + LLDB_INSTRUMENT_VA(this); + + if (TargetSP target_sp = GetSP()) + return target_sp->GetGloballyUniqueID(); + return LLDB_INVALID_GLOBALLY_UNIQUE_TARGET_ID; +} + SBError SBTarget::SetLabel(const char *label) { LLDB_INSTRUMENT_VA(this, label); diff --git a/lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp b/lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp index 51bdcc9..e7fddf0 100644 --- a/lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp +++ b/lldb/source/Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp @@ -38,16 +38,18 @@ struct CreateMethodDecl : public TypeVisitorCallbacks { TypeIndex func_type_index, clang::FunctionDecl *&function_decl, lldb::opaque_compiler_type_t parent_ty, - llvm::StringRef proc_name, CompilerType func_ct) + llvm::StringRef proc_name, ConstString mangled_name, + CompilerType func_ct) : m_index(m_index), m_clang(m_clang), func_type_index(func_type_index), function_decl(function_decl), parent_ty(parent_ty), - proc_name(proc_name), func_ct(func_ct) {} + proc_name(proc_name), mangled_name(mangled_name), func_ct(func_ct) {} PdbIndex &m_index; TypeSystemClang &m_clang; TypeIndex func_type_index; clang::FunctionDecl *&function_decl; lldb::opaque_compiler_type_t parent_ty; llvm::StringRef proc_name; + ConstString mangled_name; CompilerType func_ct; llvm::Error visitKnownMember(CVMemberRecord &cvr, @@ -87,8 +89,7 @@ struct CreateMethodDecl : public TypeVisitorCallbacks { bool is_artificial = (options & MethodOptions::CompilerGenerated) == MethodOptions::CompilerGenerated; function_decl = m_clang.AddMethodToCXXRecordType( - parent_ty, proc_name, - /*asm_label=*/{}, func_ct, /*access=*/access_type, + parent_ty, proc_name, mangled_name, func_ct, /*access=*/access_type, /*is_virtual=*/is_virtual, /*is_static=*/is_static, /*is_inline=*/false, /*is_explicit=*/false, /*is_attr_used=*/false, /*is_artificial=*/is_artificial); @@ -892,6 +893,10 @@ PdbAstBuilder::CreateFunctionDecl(PdbCompilandSymId func_id, tag_record = CVTagRecord::create(index.tpi().getType(*eti)).asTag(); } } + + ConstString mangled_name( + pdb->FindMangledFunctionName(func_id).value_or(llvm::StringRef())); + if (!tag_record.FieldList.isSimple()) { CVType field_list_cvt = index.tpi().getType(tag_record.FieldList); FieldListRecord field_list; @@ -899,15 +904,15 @@ PdbAstBuilder::CreateFunctionDecl(PdbCompilandSymId func_id, field_list_cvt, field_list)) llvm::consumeError(std::move(error)); CreateMethodDecl process(index, m_clang, func_ti, function_decl, - parent_opaque_ty, func_name, func_ct); + parent_opaque_ty, func_name, mangled_name, + func_ct); if (llvm::Error err = visitMemberRecordStream(field_list.Data, process)) llvm::consumeError(std::move(err)); } if (!function_decl) { function_decl = m_clang.AddMethodToCXXRecordType( - parent_opaque_ty, func_name, - /*asm_label=*/{}, func_ct, + parent_opaque_ty, func_name, mangled_name, func_ct, /*access=*/lldb::AccessType::eAccessPublic, /*is_virtual=*/false, /*is_static=*/false, /*is_inline=*/false, /*is_explicit=*/false, diff --git a/lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp b/lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp index 8b3d775..75a8189 100644 --- a/lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp +++ b/lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp @@ -501,7 +501,11 @@ lldb::FunctionSP SymbolFileNativePDB::CreateFunction(PdbCompilandSymId func_id, return nullptr; PdbTypeSymId sig_id(proc.FunctionType, false); - Mangled mangled(proc.Name); + + std::optional<llvm::StringRef> mangled_opt = FindMangledSymbol( + SegmentOffset(proc.Segment, proc.CodeOffset), proc.FunctionType); + Mangled mangled(mangled_opt.value_or(proc.Name)); + FunctionSP func_sp = std::make_shared<Function>( &comp_unit, toOpaqueUid(func_id), toOpaqueUid(sig_id), mangled, func_type.get(), func_addr, @@ -2662,6 +2666,83 @@ SymbolFileNativePDB::GetContextForType(TypeIndex ti) { return ctx; } +std::optional<llvm::StringRef> +SymbolFileNativePDB::FindMangledFunctionName(PdbCompilandSymId func_id) { + const CompilandIndexItem *cci = + m_index->compilands().GetCompiland(func_id.modi); + if (!cci) + return std::nullopt; + + CVSymbol sym_record = cci->m_debug_stream.readSymbolAtOffset(func_id.offset); + if (sym_record.kind() != S_LPROC32 && sym_record.kind() != S_GPROC32) + return std::nullopt; + + ProcSym proc(static_cast<SymbolRecordKind>(sym_record.kind())); + cantFail(SymbolDeserializer::deserializeAs<ProcSym>(sym_record, proc)); + + return FindMangledSymbol(SegmentOffset(proc.Segment, proc.CodeOffset), + proc.FunctionType); +} + +std::optional<llvm::StringRef> +SymbolFileNativePDB::FindMangledSymbol(SegmentOffset so, + TypeIndex function_type) { + auto symbol = m_index->publics().findByAddress(m_index->symrecords(), + so.segment, so.offset); + if (!symbol) + return std::nullopt; + + llvm::StringRef name = symbol->first.Name; + // For functions, we might need to strip the mangled name. See + // StripMangledFunctionName for more info. + if (!function_type.isNoneType() && + (symbol->first.Flags & PublicSymFlags::Function) != PublicSymFlags::None) + name = StripMangledFunctionName(name, function_type); + + return name; +} + +llvm::StringRef +SymbolFileNativePDB::StripMangledFunctionName(const llvm::StringRef mangled, + PdbTypeSymId func_ty) { + // "In non-64 bit environments" (on x86 in pactice), __cdecl functions get + // prefixed with an underscore. For compilers using LLVM, this happens in LLVM + // (as opposed to the compiler frontend). Because of this, DWARF doesn't + // contain the "full" mangled name in DW_AT_linkage_name for these functions. + // We strip the mangling here for compatibility with DWARF. See + // llvm.org/pr161676 and + // https://learn.microsoft.com/en-us/cpp/build/reference/decorated-names#FormatC + + if (!mangled.starts_with('_') || + m_index->dbi().getMachineType() != PDB_Machine::x86) + return mangled; + + CVType cvt = m_index->tpi().getType(func_ty.index); + PDB_CallingConv cc = PDB_CallingConv::NearC; + if (cvt.kind() == LF_PROCEDURE) { + ProcedureRecord proc; + if (llvm::Error error = + TypeDeserializer::deserializeAs<ProcedureRecord>(cvt, proc)) + llvm::consumeError(std::move(error)); + cc = proc.CallConv; + } else if (cvt.kind() == LF_MFUNCTION) { + MemberFunctionRecord mfunc; + if (llvm::Error error = + TypeDeserializer::deserializeAs<MemberFunctionRecord>(cvt, mfunc)) + llvm::consumeError(std::move(error)); + cc = mfunc.CallConv; + } else { + LLDB_LOG(GetLog(LLDBLog::Symbols), "Unexpected function type, got {0}", + cvt.kind()); + return mangled; + } + + if (cc == PDB_CallingConv::NearC || cc == PDB_CallingConv::FarC) + return mangled.drop_front(); + + return mangled; +} + void SymbolFileNativePDB::CacheUdtDeclarations() { for (CVType cvt : m_index->ipi().typeArray()) { switch (cvt.kind()) { diff --git a/lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.h b/lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.h index 2405f8b..a5fef35 100644 --- a/lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.h +++ b/lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.h @@ -140,6 +140,12 @@ public: std::optional<PdbCompilandSymId> FindSymbolScope(PdbCompilandSymId id); + /// Find the mangled name for a function + /// + /// \param id A symbol ID of a S_LPROC32/S_GPROC32 record + /// \returns The mangled name of the function (if available) + std::optional<llvm::StringRef> FindMangledFunctionName(PdbCompilandSymId id); + void FindTypes(const lldb_private::TypeQuery &match, lldb_private::TypeResults &results) override; @@ -269,6 +275,20 @@ private: void CacheUdtDeclarations(); llvm::Expected<Declaration> ResolveUdtDeclaration(PdbTypeSymId type_id); + /// Find a symbol name at a specific address (`so`). + /// + /// \param[in] so The segment and offset where the symbol is located. + /// \param[in] function_type If the symbol is expected to be a function, this + /// has to be the type of the function. It's used to strip the name of + /// __cdecl functions on x86. + /// \returns The mangled symbol name if found, otherwise `std::nullopt`. + std::optional<llvm::StringRef> FindMangledSymbol( + SegmentOffset so, + llvm::codeview::TypeIndex function_type = llvm::codeview::TypeIndex()); + + llvm::StringRef StripMangledFunctionName(llvm::StringRef mangled, + PdbTypeSymId func_ty); + llvm::BumpPtrAllocator m_allocator; lldb::addr_t m_obj_load_address = 0; diff --git a/lldb/source/Target/Target.cpp b/lldb/source/Target/Target.cpp index fa98c24..e0286c4 100644 --- a/lldb/source/Target/Target.cpp +++ b/lldb/source/Target/Target.cpp @@ -139,6 +139,8 @@ private: }; } // namespace +static std::atomic<lldb::user_id_t> g_target_unique_id{1}; + template <typename Installer> static Status installExecutable(const Installer &installer) { if (!installer.m_local_file || !installer.m_remote_file) @@ -183,6 +185,7 @@ Target::Target(Debugger &debugger, const ArchSpec &target_arch, m_source_manager_up(), m_stop_hooks(), m_stop_hook_next_id(0), m_latest_stop_hook_id(0), m_valid(true), m_suppress_stop_hooks(false), m_is_dummy_target(is_dummy_target), + m_target_unique_id(g_target_unique_id++), m_frame_recognizer_manager_up( std::make_unique<StackFrameRecognizerManager>()) { SetEventName(eBroadcastBitBreakpointChanged, "breakpoint-changed"); diff --git a/lldb/source/Target/TargetList.cpp b/lldb/source/Target/TargetList.cpp index 7037dc2..188c250 100644 --- a/lldb/source/Target/TargetList.cpp +++ b/lldb/source/Target/TargetList.cpp @@ -428,6 +428,18 @@ TargetSP TargetList::FindTargetWithProcess(Process *process) const { return target_sp; } +TargetSP TargetList::FindTargetByGloballyUniqueID(lldb::user_id_t id) const { + std::lock_guard<std::recursive_mutex> guard(m_target_list_mutex); + auto it = llvm::find_if(m_target_list, [id](const TargetSP &item) { + return item->GetGloballyUniqueID() == id; + }); + + if (it != m_target_list.end()) + return *it; + + return TargetSP(); +} + TargetSP TargetList::GetTargetSP(Target *target) const { TargetSP target_sp; if (!target) diff --git a/lldb/test/API/functionalities/unwind/cortex-m-exception/TestCortexMExceptionUnwind.py b/lldb/test/API/functionalities/unwind/cortex-m-exception/TestCortexMExceptionUnwind.py index 768dd6f..6535f89 100644 --- a/lldb/test/API/functionalities/unwind/cortex-m-exception/TestCortexMExceptionUnwind.py +++ b/lldb/test/API/functionalities/unwind/cortex-m-exception/TestCortexMExceptionUnwind.py @@ -12,21 +12,6 @@ from lldbsuite.test import lldbutil class TestCortexMExceptionUnwind(TestBase): NO_DEBUG_INFO_TESTCASE = True - # on the lldb-remote-linux-ubuntu CI, the binary.json's triple of - # armv7m-apple is not being set in the Target triple, and we're - # picking the wrong ABI plugin, ABISysV_arm. - # ABISysV_arm::CreateDefaultUnwindPlan() doesn't have a way to detect - # arm/thumb for a stack frame, or even the Target's triple for a - # Cortex-M part that is always thumb. It hardcodes r11 as the frame - # pointer register, which is correct for arm code but not thumb. - # It is never correct # on a Cortex-M target. - # The Darwin ABIMacOSX_arm diverges from AAPCS and always uses r7 for - # the frame pointer -- the thumb convention -- whether executing arm or - # thumb. So its CreateDefaultUnwindPlan picks the correct register for - # the frame pointer, and we can walk the stack. - # ABISysV_arm::CreateDefaultUnwindPlan will only get one frame and - # not be able to continue. - @skipIfRemote def test_no_fpu(self): """Test that we can backtrace correctly through an ARM Cortex-M Exception return stack""" @@ -59,10 +44,9 @@ class TestCortexMExceptionUnwind(TestBase): # frames above that. The topmost two stack frames # were not interesting for this test, so I didn't # create symbols for them. - self.assertEqual(thread.GetNumFrames(), 6) + self.assertEqual(thread.GetNumFrames(), 3) stackframe_names = [ "exception_catcher", - "exception_catcher", "exception_thrower", "main", ] diff --git a/lldb/test/API/functionalities/unwind/cortex-m-exception/armv7m-nofpu-exception.yaml b/lldb/test/API/functionalities/unwind/cortex-m-exception/armv7m-nofpu-exception.yaml index 9ce5ff4..0b4e1f8 100644 --- a/lldb/test/API/functionalities/unwind/cortex-m-exception/armv7m-nofpu-exception.yaml +++ b/lldb/test/API/functionalities/unwind/cortex-m-exception/armv7m-nofpu-exception.yaml @@ -2,8 +2,8 @@ cpu: armv7m threads: - regsets: - flavor: gpr - registers: [{name: sp, value: 0x2000fe70}, {name: r7, value: 0x2000fe80}, - {name: pc, value: 0x0020392c}, {name: lr, value: 0x0020392d}] + registers: [{name: sp, value: 0x2000fe88}, {name: r7, value: 0x2000fe88}, + {name: pc, value: 0x00203916}, {name: lr, value: 0x0020392d}] memory-regions: # stack memory fetched via # (lldb) p/x $sp @@ -14,7 +14,7 @@ memory-regions: 0x0000002a, 0x20010e58, 0x00203923, 0x00000001, 0x2000fe88, 0x00203911, 0x2000ffdc, 0xfffffff9, 0x00000102, 0x00000002, 0x000003f0, 0x0000002a, - 0x20012620, 0x00203215, 0x00203366, 0x81000200, + 0x20012620, 0x00203215, 0x00202a92, 0x81000200, 0x00203215, 0x200128b0, 0x0024928d, 0x2000fecc, 0x002491ed, 0x20010e58, 0x20010e4c, 0x2000ffa0, 0x200107a0, 0x0000003c, 0x200116e8, 0x200108b0, @@ -62,3 +62,26 @@ memory-regions: 0x98, 0xae, 0x28, 0x00 ] + # exception_thrower + # (lldb) disass -b -c 12 -n exception_thrower + # 0x202a88 <+0>: 0xb5f0 push {r4, r5, r6, r7, lr} + # 0x202a8a <+2>: 0xaf03 add r7, sp, #0xc + # 0x202a8c <+4>: 0xe92d0f00 push.w {r8, r9, r10, r11} + # 0x202a90 <+8>: 0xb0c3 sub sp, #0x10c + # 0x202a92 <+10>: 0xf7ffffd9 bl 0x202a48 + - addr: 0x202a88 + UInt8: [ + 0xf0, 0xb5, 0x03, 0xaf, 0x2d, 0xe9, 0x00, 0x0f, + 0xc3, 0xb0, 0xff, 0xf7, 0xd9, 0xff, 0xff, 0xf7 + ] + + # main: + # 0x202a7e <+0>: push {r7, lr} + # 0x202a80 <+2>: mov r7, sp + # 0x202a82 <+4>: bl 0x202a88 ; exception_thrower + # 0x202a86 <+8>: nop + - addr: 0x202a7e + UInt8: [ + 0x80, 0xb5, 0x6f, 0x46, 0x00, 0xf0, 0x01, 0xf8, + 0x00, 0xbf + ] diff --git a/lldb/test/API/functionalities/unwind/cortex-m-exception/binary.json b/lldb/test/API/functionalities/unwind/cortex-m-exception/binary.json index 8fcd530..0de0169 100644 --- a/lldb/test/API/functionalities/unwind/cortex-m-exception/binary.json +++ b/lldb/test/API/functionalities/unwind/cortex-m-exception/binary.json @@ -1,5 +1,5 @@ { - "triple": "armv7m-apple", + "triple": "armv7m--", "uuid": "2D157DBA-53C9-3AC7-B5A1-9D336EC831CB", "type": "executable", "sections": [ @@ -28,13 +28,13 @@ { "name": "exception_catcher", "type": "code", - "size": 44, + "size": 32, "address": 2111760 }, { "name": "exception_thrower", "type": "code", - "size": 2652, + "size": 16, "address": 2108040 } ] diff --git a/lldb/test/API/python_api/debugger/TestDebuggerAPI.py b/lldb/test/API/python_api/debugger/TestDebuggerAPI.py index 43f45f3..44b1183 100644 --- a/lldb/test/API/python_api/debugger/TestDebuggerAPI.py +++ b/lldb/test/API/python_api/debugger/TestDebuggerAPI.py @@ -294,3 +294,150 @@ class DebuggerAPITestCase(TestBase): self.assertEqual(instance_str, class_str) self.assertEqual(class_str, property_str) + + def test_find_target_with_unique_id(self): + """Test SBDebugger.FindTargetByGloballyUniqueID() functionality.""" + + # Test with invalid ID - should return invalid target + invalid_target = self.dbg.FindTargetByGloballyUniqueID(999999) + self.assertFalse(invalid_target.IsValid()) + + # Test with ID 0 - should return invalid target + zero_target = self.dbg.FindTargetByGloballyUniqueID(0) + self.assertFalse(zero_target.IsValid()) + + # Build a real executable and create target with it + self.build() + exe = self.getBuildArtifact("a.out") + target = self.dbg.CreateTarget(exe) + self.assertTrue(target.IsValid()) + + # Find the target using its unique ID + unique_id = target.GetGloballyUniqueID() + self.assertNotEqual(unique_id, lldb.LLDB_INVALID_GLOBALLY_UNIQUE_TARGET_ID) + found_target = self.dbg.FindTargetByGloballyUniqueID(unique_id) + self.assertTrue(found_target.IsValid()) + self.assertEqual( + self.dbg.GetIndexOfTarget(target), self.dbg.GetIndexOfTarget(found_target) + ) + self.assertEqual(found_target.GetGloballyUniqueID(), unique_id) + + def test_target_unique_id_uniqueness(self): + """Test that Target.GetGloballyUniqueID() returns unique values across multiple targets.""" + + # Create multiple targets and verify they all have unique IDs + self.build() + exe = self.getBuildArtifact("a.out") + targets = [] + unique_ids = set() + + for i in range(10): + target = self.dbg.CreateTarget(exe) + self.assertTrue(target.IsValid()) + + unique_id = target.GetGloballyUniqueID() + self.assertNotEqual(unique_id, 0) + + # Verify this ID hasn't been used before + self.assertNotIn( + unique_id, unique_ids, f"Duplicate unique ID found: {unique_id}" + ) + + unique_ids.add(unique_id) + targets.append(target) + + # Verify all targets can still be found by their IDs + for target in targets: + unique_id = target.GetGloballyUniqueID() + found = self.dbg.FindTargetByGloballyUniqueID(unique_id) + self.assertTrue(found.IsValid()) + self.assertEqual(found.GetGloballyUniqueID(), unique_id) + + def test_target_unique_id_uniqueness_after_deletion(self): + """Test finding targets have unique ID after target deletion.""" + # Create two targets + self.build() + exe = self.getBuildArtifact("a.out") + target1 = self.dbg.CreateTarget(exe) + target2 = self.dbg.CreateTarget(exe) + self.assertTrue(target1.IsValid()) + self.assertTrue(target2.IsValid()) + + unique_id1 = target1.GetGloballyUniqueID() + unique_id2 = target2.GetGloballyUniqueID() + self.assertNotEqual(unique_id1, 0) + self.assertNotEqual(unique_id2, 0) + self.assertNotEqual(unique_id1, unique_id2) + + # Verify we can find them initially + found_target1 = self.dbg.FindTargetByGloballyUniqueID(unique_id1) + found_target2 = self.dbg.FindTargetByGloballyUniqueID(unique_id2) + self.assertTrue(found_target1.IsValid()) + self.assertTrue(found_target2.IsValid()) + target2_index = self.dbg.GetIndexOfTarget(target2) + + # Delete target 2 + deleted = self.dbg.DeleteTarget(target2) + self.assertTrue(deleted) + + # Try to find the deleted target - should not be found + not_found_target = self.dbg.FindTargetByGloballyUniqueID(unique_id2) + self.assertFalse(not_found_target.IsValid()) + + # Create a new target + target3 = self.dbg.CreateTarget(exe) + self.assertTrue(target3.IsValid()) + # Target list index of target3 should be the same as target2's + # since it was deleted, but it should have a distinct unique ID + target3_index = self.dbg.GetIndexOfTarget(target3) + unique_id3 = target3.GetGloballyUniqueID() + self.assertEqual(target3_index, target2_index) + self.assertNotEqual(unique_id3, unique_id2) + self.assertNotEqual(unique_id3, unique_id1) + # Make sure we can find the new target + found_target3 = self.dbg.FindTargetByGloballyUniqueID( + target3.GetGloballyUniqueID() + ) + self.assertTrue(found_target3.IsValid()) + + def test_target_globally_unique_id_across_debuggers(self): + """Test that target IDs are globally unique across multiple debuggers.""" + self.build() + exe = self.getBuildArtifact("a.out") + + # Create two debuggers with targets each + debugger1 = lldb.SBDebugger.Create() + debugger2 = lldb.SBDebugger.Create() + self.addTearDownHook(lambda: lldb.SBDebugger.Destroy(debugger1)) + self.addTearDownHook(lambda: lldb.SBDebugger.Destroy(debugger2)) + + # Create 2 targets per debugger + targets_d1 = [debugger1.CreateTarget(exe), debugger1.CreateTarget(exe)] + targets_d2 = [debugger2.CreateTarget(exe), debugger2.CreateTarget(exe)] + targets = targets_d1 + targets_d2 + + # Get all IDs and verify they're unique + ids = [target.GetGloballyUniqueID() for target in targets] + self.assertEqual( + len(set(ids)), len(ids), f"IDs should be globally unique: {ids}" + ) + self.assertTrue( + all(uid != lldb.LLDB_INVALID_GLOBALLY_UNIQUE_TARGET_ID for uid in ids), + "All IDs should be valid", + ) + + # Verify targets can be found by their IDs in respective debuggers + for debugger, target_pair in [ + (debugger1, targets[:2]), + (debugger2, targets[2:]), + ]: + for target in target_pair: + found = debugger.FindTargetByGloballyUniqueID( + target.GetGloballyUniqueID() + ) + self.assertTrue( + found.IsValid(), "Target should be found by its unique ID" + ) + self.assertEqual( + found.GetGloballyUniqueID(), target.GetGloballyUniqueID() + ) diff --git a/lldb/test/Shell/SymbolFile/NativePDB/break-by-function.cpp b/lldb/test/Shell/SymbolFile/NativePDB/break-by-function.cpp index a580d57..d449937 100644 --- a/lldb/test/Shell/SymbolFile/NativePDB/break-by-function.cpp +++ b/lldb/test/Shell/SymbolFile/NativePDB/break-by-function.cpp @@ -50,9 +50,9 @@ int main(int argc, char **argv) { // CHECK: 1: name = 'main', locations = 1 // CHECK: 1.1: where = break-by-function.cpp.tmp.exe`main + {{[0-9]+}} // CHECK: 2: name = 'OvlGlobalFn', locations = 3 -// CHECK: 2.1: where = break-by-function.cpp.tmp.exe`OvlGlobalFn + {{[0-9]+}} -// CHECK: 2.2: where = break-by-function.cpp.tmp.exe`OvlGlobalFn -// CHECK: 2.3: where = break-by-function.cpp.tmp.exe`OvlGlobalFn + {{[0-9]+}} +// CHECK: 2.1: where = break-by-function.cpp.tmp.exe`int OvlGlobalFn(int) + {{[0-9]+}} +// CHECK: 2.2: where = break-by-function.cpp.tmp.exe`int OvlGlobalFn(int, int) +// CHECK: 2.3: where = break-by-function.cpp.tmp.exe`int OvlGlobalFn(int, int, int) + {{[0-9]+}} // CHECK: 3: name = 'StaticFn', locations = 1 // CHECK: 3.1: where = break-by-function.cpp.tmp.exe`StaticFn + {{[0-9]+}} // CHECK: 4: name = 'DoesntExist', locations = 0 (pending) diff --git a/lldb/test/Shell/SymbolFile/NativePDB/break-by-line.cpp b/lldb/test/Shell/SymbolFile/NativePDB/break-by-line.cpp index 90ac633..3d7de32 100644 --- a/lldb/test/Shell/SymbolFile/NativePDB/break-by-line.cpp +++ b/lldb/test/Shell/SymbolFile/NativePDB/break-by-line.cpp @@ -24,4 +24,4 @@ int main(int argc, char **argv) { // CHECK: (lldb) target create "{{.*}}break-by-line.cpp.tmp.exe" // CHECK: Current executable set to '{{.*}}break-by-line.cpp.tmp.exe' // CHECK: (lldb) break set -f break-by-line.cpp -l 15 -// CHECK: Breakpoint 1: where = break-by-line.cpp.tmp.exe`NS::NamespaceFn + {{[0-9]+}} at break-by-line.cpp:15 +// CHECK: Breakpoint 1: where = break-by-line.cpp.tmp.exe`int NS::NamespaceFn(int) + {{[0-9]+}} at break-by-line.cpp:15 diff --git a/lldb/test/Shell/SymbolFile/NativePDB/c-calling-conventions.cpp b/lldb/test/Shell/SymbolFile/NativePDB/c-calling-conventions.cpp new file mode 100644 index 0000000..d1d0bb0 --- /dev/null +++ b/lldb/test/Shell/SymbolFile/NativePDB/c-calling-conventions.cpp @@ -0,0 +1,51 @@ +// clang-format off +// REQUIRES: lld, (target-x86 || target-x86_64) + +// RUN: %build --compiler=clang-cl --arch=32 --nodefaultlib --output=%t-32.exe %s +// RUN: lldb-test symbols %t-32.exe | FileCheck --check-prefixes CHECK-32,CHECK-BOTH %s +// RUN: %build --compiler=clang-cl --arch=64 --nodefaultlib --output=%t-64.exe %s +// RUN: lldb-test symbols %t-64.exe | FileCheck --check-prefixes CHECK-64,CHECK-BOTH %s + +extern "C" { +int FuncCCall() { return 0; } +int __stdcall FuncStdCall() { return 0; } +int __fastcall FuncFastCall() { return 0; } +int __vectorcall FuncVectorCall() { return 0; } + +int __cdecl _underscoreCdecl() { return 0; } +int __stdcall _underscoreStdcall() { return 0; } +int __fastcall _underscoreFastcall() { return 0; } +int __vectorcall _underscoreVectorcall() { return 0; } +} + +int main() { + FuncCCall(); + FuncStdCall(); + FuncFastCall(); + FuncVectorCall(); + _underscoreCdecl(); + _underscoreStdcall(); + _underscoreFastcall(); + _underscoreVectorcall(); + return 0; +} + +// CHECK-BOTH-DAG: Function{{.*}}, demangled = FuncCCall, +// CHECK-BOTH-DAG: Function{{.*}}, demangled = FuncVectorCall@@0, +// CHECK-BOTH-DAG: Function{{.*}}, demangled = _underscoreCdecl, +// CHECK-BOTH-DAG: Function{{.*}}, demangled = _underscoreVectorcall@@0, +// CHECK-BOTH-DAG: Function{{.*}}, demangled = main, + +// __stdcall and __fastcall aren't available on 64 bit + +// CHECK-32-DAG: Function{{.*}}, demangled = _FuncStdCall@0, +// CHECK-64-DAG: Function{{.*}}, demangled = FuncStdCall, + +// CHECK-32-DAG: Function{{.*}}, demangled = @FuncFastCall@0, +// CHECK-64-DAG: Function{{.*}}, demangled = FuncFastCall, + +// CHECK-32-DAG: Function{{.*}}, demangled = __underscoreStdcall@0, +// CHECK-64-DAG: Function{{.*}}, demangled = _underscoreStdcall, + +// CHECK-32-DAG: Function{{.*}}, demangled = @_underscoreFastcall@0, +// CHECK-64-DAG: Function{{.*}}, demangled = _underscoreFastcall, diff --git a/lldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp b/lldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp index b3f7b09..05074aa 100644 --- a/lldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp +++ b/lldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp @@ -25,7 +25,7 @@ int main(int argc, char **argv) { // CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+12>: mov qword ptr [rsp + 0x28], rdx // CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+17>: mov dword ptr [rsp + 0x24], ecx // CHECK: ** 15 foo(); -// CHECK: disassembly.cpp.tmp.exe[{{.*}}] <+21>: call {{.*}} ; foo at disassembly.cpp:12 +// CHECK: disassembly.cpp.tmp.exe[{{.*}}] <+21>: call {{.*}} ; int foo(void) at disassembly.cpp:12 // CHECK: ** 16 return 0; // CHECK-NEXT: 17 } // CHECK-NEXT: 18 diff --git a/lldb/test/Shell/SymbolFile/NativePDB/find-functions.cpp b/lldb/test/Shell/SymbolFile/NativePDB/find-functions.cpp index 3ef7a4c..6204cbd 100644 --- a/lldb/test/Shell/SymbolFile/NativePDB/find-functions.cpp +++ b/lldb/test/Shell/SymbolFile/NativePDB/find-functions.cpp @@ -148,11 +148,12 @@ int main(int argc, char **argv) { // FIND-OVERLOAD-BASE-DAG: FuncType: id = {{.*}}, compiler_type = "int (void)" // FIND-OVERLOAD-BASE-DAG: FuncType: id = {{.*}}, compiler_type = "int (char)" // FIND-OVERLOAD-BASE-DAG: FuncType: id = {{.*}}, compiler_type = "int (char, int, ...)" -// FIND-OVERLOAD-BASE-DAG: Function: id = {{.*}}, name = "Class::overloaded_method" +// FIND-OVERLOAD-BASE-DAG: Function: id = {{.*}}, name = "int Class::overloaded_method(bool)" // FIND-OVERLOAD-BASE-DAG: FuncType: id = {{.*}}, compiler_type = "_Bool (void)" // FIND-OVERLOAD-BASE-DAG: FuncType: id = {{.*}}, compiler_type = "_Bool (int)" // FIND-OVERLOAD-BASE-DAG: FuncType: id = {{.*}}, compiler_type = "int (_Bool)" -// FIND-OVERLOAD-BASE-DAG: Function: id = {{.*}}, name = "overloaded_method" +// FIND-OVERLOAD-BASE-DAG: Function: id = {{.*}}, name = "char overloaded_method(void)" +// FIND-OVERLOAD-BASE-DAG: Function: id = {{.*}}, name = "char overloaded_method(int)" // FIND-OVERLOAD-BASE-DAG: FuncType: id = {{.*}}, compiler_type = "char (void)" // FIND-OVERLOAD-BASE-DAG: FuncType: id = {{.*}}, compiler_type = "char (int)" @@ -160,6 +161,6 @@ int main(int argc, char **argv) { // FIND-OVERLOAD-METHOD-DAG: Function: id = {{.*}}, name = "{{.*}}Struct::overloaded_method{{.*}}" // FIND-OVERLOAD-METHOD-DAG: FuncType: id = {{.*}}, compiler_type = "int (void)" // FIND-OVERLOAD-METHOD-DAG: FuncType: id = {{.*}}, compiler_type = "int (char)" -// FIND-OVERLOAD-METHOD-DAG: Function: id = {{.*}}, name = "Class::overloaded_method" +// FIND-OVERLOAD-METHOD-DAG: Function: id = {{.*}}, name = "bool Class::overloaded_method(void)" // FIND-OVERLOAD-METHOD-DAG: FuncType: id = {{.*}}, compiler_type = "_Bool (void)" // FIND-OVERLOAD-METHOD-DAG: FuncType: id = {{.*}}, compiler_type = "_Bool (int)" diff --git a/lldb/test/Shell/SymbolFile/NativePDB/local-variables.cpp b/lldb/test/Shell/SymbolFile/NativePDB/local-variables.cpp index 44a8dc1..f44a5b9 100644 --- a/lldb/test/Shell/SymbolFile/NativePDB/local-variables.cpp +++ b/lldb/test/Shell/SymbolFile/NativePDB/local-variables.cpp @@ -55,7 +55,7 @@ int main(int argc, char **argv) { // CHECK-NEXT: (lldb) step // CHECK-NEXT: Process {{.*}} stopped // CHECK-NEXT: * thread #1, stop reason = step in -// CHECK-NEXT: frame #0: {{.*}} local-variables.cpp.tmp.exe`Function(Param1=16, Param2='a') at local-variables.cpp:{{.*}} +// CHECK-NEXT: frame #0: {{.*}} local-variables.cpp.tmp.exe`int Function(Param1=16, Param2='a') at local-variables.cpp:{{.*}} // CHECK-NEXT: 6 // CHECK-NEXT: 7 // CHECK-NEXT: 8 int Function(int Param1, char Param2) { @@ -71,7 +71,7 @@ int main(int argc, char **argv) { // CHECK-NEXT: (lldb) step // CHECK-NEXT: Process {{.*}} stopped // CHECK-NEXT: * thread #1, stop reason = step in -// CHECK-NEXT: frame #0: {{.*}} local-variables.cpp.tmp.exe`Function(Param1=16, Param2='a') at local-variables.cpp:{{.*}} +// CHECK-NEXT: frame #0: {{.*}} local-variables.cpp.tmp.exe`int Function(Param1=16, Param2='a') at local-variables.cpp:{{.*}} // CHECK-NEXT: 7 // CHECK-NEXT: 8 int Function(int Param1, char Param2) { // CHECK-NEXT: 9 unsigned Local1 = Param1 + 1; @@ -89,7 +89,7 @@ int main(int argc, char **argv) { // CHECK-NEXT: (lldb) step // CHECK-NEXT: Process {{.*}} stopped // CHECK-NEXT: * thread #1, stop reason = step in -// CHECK-NEXT: frame #0: {{.*}} local-variables.cpp.tmp.exe`Function(Param1=16, Param2='a') at local-variables.cpp:{{.*}} +// CHECK-NEXT: frame #0: {{.*}} local-variables.cpp.tmp.exe`int Function(Param1=16, Param2='a') at local-variables.cpp:{{.*}} // CHECK-NEXT: 8 int Function(int Param1, char Param2) { // CHECK-NEXT: 9 unsigned Local1 = Param1 + 1; // CHECK-NEXT: 10 char Local2 = Param2 + 1; @@ -109,7 +109,7 @@ int main(int argc, char **argv) { // CHECK-NEXT: (lldb) step // CHECK-NEXT: Process {{.*}} stopped // CHECK-NEXT: * thread #1, stop reason = step in -// CHECK-NEXT: frame #0: {{.*}} local-variables.cpp.tmp.exe`Function(Param1=16, Param2='a') at local-variables.cpp:{{.*}} +// CHECK-NEXT: frame #0: {{.*}} local-variables.cpp.tmp.exe`int Function(Param1=16, Param2='a') at local-variables.cpp:{{.*}} // CHECK-NEXT: 9 unsigned Local1 = Param1 + 1; // CHECK-NEXT: 10 char Local2 = Param2 + 1; // CHECK-NEXT: 11 ++Local1; @@ -129,7 +129,7 @@ int main(int argc, char **argv) { // CHECK-NEXT: (lldb) step // CHECK-NEXT: Process {{.*}} stopped // CHECK-NEXT: * thread #1, stop reason = step in -// CHECK-NEXT: frame #0: {{.*}} local-variables.cpp.tmp.exe`Function(Param1=16, Param2='a') at local-variables.cpp:{{.*}} +// CHECK-NEXT: frame #0: {{.*}} local-variables.cpp.tmp.exe`int Function(Param1=16, Param2='a') at local-variables.cpp:{{.*}} // CHECK-NEXT: 10 char Local2 = Param2 + 1; // CHECK-NEXT: 11 ++Local1; // CHECK-NEXT: 12 ++Local2; diff --git a/lldb/test/Shell/SymbolFile/NativePDB/stack_unwinding01.cpp b/lldb/test/Shell/SymbolFile/NativePDB/stack_unwinding01.cpp index 596a826..87eeebe7 100644 --- a/lldb/test/Shell/SymbolFile/NativePDB/stack_unwinding01.cpp +++ b/lldb/test/Shell/SymbolFile/NativePDB/stack_unwinding01.cpp @@ -24,19 +24,19 @@ int main(int argc, char **argv) { // CHECK: (lldb) thread backtrace // CHECK-NEXT: * thread #1, stop reason = breakpoint 1.1 -// CHECK-NEXT: * frame #0: {{.*}} stack_unwinding01.cpp.tmp.exe`Struct::simple_method(this={{.*}}, a=2, b=2) at stack_unwinding01.cpp:12 +// CHECK-NEXT: * frame #0: {{.*}} stack_unwinding01.cpp.tmp.exe`void Struct::simple_method(this={{.*}}, a=2, b=2) at stack_unwinding01.cpp:12 // CHECK-NEXT: frame #1: {{.*}} stack_unwinding01.cpp.tmp.exe`main(argc={{.*}}, argv={{.*}}) at stack_unwinding01.cpp:20 // CHECK: (lldb) thread backtrace // CHECK-NEXT: * thread #1, stop reason = breakpoint 1.1 -// CHECK-NEXT: * frame #0: {{.*}} stack_unwinding01.cpp.tmp.exe`Struct::simple_method(this={{.*}}, a=3, b=2) at stack_unwinding01.cpp:12 -// CHECK-NEXT: frame #1: {{.*}} stack_unwinding01.cpp.tmp.exe`Struct::simple_method(this={{.*}}, a=2, b=2) at stack_unwinding01.cpp:12 +// CHECK-NEXT: * frame #0: {{.*}} stack_unwinding01.cpp.tmp.exe`void Struct::simple_method(this={{.*}}, a=3, b=2) at stack_unwinding01.cpp:12 +// CHECK-NEXT: frame #1: {{.*}} stack_unwinding01.cpp.tmp.exe`void Struct::simple_method(this={{.*}}, a=2, b=2) at stack_unwinding01.cpp:12 // CHECK-NEXT: frame #2: {{.*}} stack_unwinding01.cpp.tmp.exe`main(argc={{.*}}, argv={{.*}}) at stack_unwinding01.cpp:20 // CHECK: (lldb) thread backtrace // CHECK-NEXT: * thread #1, stop reason = breakpoint 1.1 -// CHECK-NEXT: * frame #0: {{.*}} stack_unwinding01.cpp.tmp.exe`Struct::simple_method(this={{.*}}, a=4, b=2) at stack_unwinding01.cpp:12 -// CHECK-NEXT: frame #1: {{.*}} stack_unwinding01.cpp.tmp.exe`Struct::simple_method(this={{.*}}, a=3, b=2) at stack_unwinding01.cpp:12 -// CHECK-NEXT: frame #2: {{.*}} stack_unwinding01.cpp.tmp.exe`Struct::simple_method(this={{.*}}, a=2, b=2) at stack_unwinding01.cpp:12 +// CHECK-NEXT: * frame #0: {{.*}} stack_unwinding01.cpp.tmp.exe`void Struct::simple_method(this={{.*}}, a=4, b=2) at stack_unwinding01.cpp:12 +// CHECK-NEXT: frame #1: {{.*}} stack_unwinding01.cpp.tmp.exe`void Struct::simple_method(this={{.*}}, a=3, b=2) at stack_unwinding01.cpp:12 +// CHECK-NEXT: frame #2: {{.*}} stack_unwinding01.cpp.tmp.exe`void Struct::simple_method(this={{.*}}, a=2, b=2) at stack_unwinding01.cpp:12 // CHECK-NEXT: frame #3: {{.*}} stack_unwinding01.cpp.tmp.exe`main(argc={{.*}}, argv={{.*}}) at stack_unwinding01.cpp:20 diff --git a/lldb/test/Shell/SymbolFile/PDB/function-nested-block.test b/lldb/test/Shell/SymbolFile/PDB/function-nested-block.test index 9057d01..4a2355b 100644 --- a/lldb/test/Shell/SymbolFile/PDB/function-nested-block.test +++ b/lldb/test/Shell/SymbolFile/PDB/function-nested-block.test @@ -4,7 +4,7 @@ RUN: lldb-test symbols -find=function -file FunctionNestedBlockTest.cpp -line 4 RUN: lldb-test symbols -find=block -file FunctionNestedBlockTest.cpp -line 4 %t.exe | FileCheck --check-prefix=CHECK-BLOCK %s CHECK-FUNCTION: Found 1 functions: -CHECK-FUNCTION: name = "{{.*}}", mangled = "{{_?}}main" +CHECK-FUNCTION: name = "main" CHECK-BLOCK: Found 1 blocks: CHECK-BLOCK: Blocks: id = {{.*}}, range = {{.*}} diff --git a/lldb/test/Shell/SymbolFile/PDB/variables.test b/lldb/test/Shell/SymbolFile/PDB/variables.test index 970d714..cb761de 100644 --- a/lldb/test/Shell/SymbolFile/PDB/variables.test +++ b/lldb/test/Shell/SymbolFile/PDB/variables.test @@ -42,7 +42,7 @@ GLOBALS-DAG: Variable{{.*}}, name = "g_Const" GLOBALS-SAME: scope = ??? (2) GLOBALS: Function -FUNC-F: Function{{.*}}, {{mangled = \?f@@YAHHH@Z|demangled = f}} +FUNC-F: Function{{.*}}, mangled = ?f@@YAHHH@Z FUNC-F-NEXT: Block FUNC-F-NEXT: Variable{{.*}}, name = "var_arg1" FUNC-F-SAME: scope = parameter @@ -64,14 +64,14 @@ FUNC-MAIN-SAME: scope = local FUNC-MAIN-NEXT: Variable{{.*}}, name = "a" FUNC-MAIN-SAME: scope = local -FUNC-CONSTRUCTOR: Function{{.*}}, {{(de)?}}mangled = {{.*}}Class::Class{{.*}} +FUNC-CONSTRUCTOR: Function{{.*}}, {{mangled = \?\?0Class@@QEAA@H@Z|demangled = .*Class::Class}} FUNC-CONSTRUCTOR-NEXT: Block FUNC-CONSTRUCTOR-NEXT: Variable{{.*}}, name = "this" FUNC-CONSTRUCTOR-SAME: scope = parameter FUNC-CONSTRUCTOR-NEXT: Variable{{.*}}, name = "a" FUNC-CONSTRUCTOR-SAME: scope = parameter -FUNC-MEMBER: Function{{.*}}, {{(de)?}}mangled = {{.*}}{{(Class::)?}}Func{{.*}} +FUNC-MEMBER: Function{{.*}}, {{mangled = \?Func@Class@@QEAAXXZ|demangled = .*Class::Func}} FUNC-MEMBER-NEXT: Block FUNC-MEMBER-NEXT: Variable{{.*}}, name = "this" FUNC-MEMBER-SAME: scope = parameter diff --git a/lldb/tools/debugserver/source/RNBRemote.cpp b/lldb/tools/debugserver/source/RNBRemote.cpp index 434e9cf..b06c6bf 100644 --- a/lldb/tools/debugserver/source/RNBRemote.cpp +++ b/lldb/tools/debugserver/source/RNBRemote.cpp @@ -93,11 +93,34 @@ static const std::string JSON_ASYNC_TYPE_KEY_NAME("type"); std::setfill(' ') << std::setw((iword_idx)) << "" #define INDENT_WITH_TABS(iword_idx) \ std::setfill('\t') << std::setw((iword_idx)) << "" -// Class to handle communications via gdb remote protocol. -// Prototypes +// If `ch` is a meta character as per the binary packet convention in the +// gdb-remote protocol, quote it and write it into `stream`, otherwise write it +// as is. +static void binary_encode_char(std::ostringstream &stream, char ch) { + if (ch == '#' || ch == '$' || ch == '}' || ch == '*') { + stream.put('}'); + stream.put(ch ^ 0x20); + } else { + stream.put(ch); + } +} -static std::string binary_encode_string(const std::string &s); +// Equivalent to calling binary_encode_char for every element of `data`. +static void binary_encode_data_vector(std::ostringstream &stream, + std::vector<uint8_t> data) { + for (auto ch : data) + binary_encode_char(stream, ch); +} + +// Quote any meta characters in a std::string as per the binary +// packet convention in the gdb-remote protocol. +static std::string binary_encode_string(const std::string &s) { + std::ostringstream stream; + for (char ch : s) + binary_encode_char(stream, ch); + return stream.str(); +} // Decode a single hex character and return the hex value as a number or // -1 if "ch" is not a hex character. @@ -139,16 +162,16 @@ static std::string decode_hex_ascii_string(const char *p, return arg; } -uint64_t decode_uint64(const char *p, int base, char **end = nullptr, - uint64_t fail_value = 0) { +static uint64_t decode_uint64(const char *p, int base, char **end = nullptr, + uint64_t fail_value = 0) { nub_addr_t addr = strtoull(p, end, 16); if (addr == 0 && errno != 0) return fail_value; return addr; } -void append_hex_value(std::ostream &ostrm, const void *buf, size_t buf_size, - bool swap) { +static void append_hex_value(std::ostream &ostrm, const void *buf, + size_t buf_size, bool swap) { int i; const uint8_t *p = (const uint8_t *)buf; if (swap) { @@ -160,7 +183,7 @@ void append_hex_value(std::ostream &ostrm, const void *buf, size_t buf_size, } } -std::string cstring_to_asciihex_string(const char *str) { +static std::string cstring_to_asciihex_string(const char *str) { std::string hex_str; hex_str.reserve(strlen(str) * 2); while (str && *str) { @@ -172,7 +195,8 @@ std::string cstring_to_asciihex_string(const char *str) { return hex_str; } -void append_hexified_string(std::ostream &ostrm, const std::string &string) { +static void append_hexified_string(std::ostream &ostrm, + const std::string &string) { size_t string_size = string.size(); const char *string_buf = string.c_str(); for (size_t i = 0; i < string_size; i++) { @@ -1027,8 +1051,6 @@ rnb_err_t RNBRemote::HandleAsyncPacket(PacketEnum *type) { rnb_err_t RNBRemote::HandleReceivedPacket(PacketEnum *type) { static DNBTimer g_packetTimer(true); - // DNBLogThreadedIf (LOG_RNB_REMOTE, "%8u RNBRemote::%s", - // (uint32_t)m_comm.Timer().ElapsedMicroSeconds(true), __FUNCTION__); rnb_err_t err = rnb_err; std::string packet_data; RNBRemote::Packet packet_info; @@ -1284,8 +1306,7 @@ static cpu_type_t best_guess_cpu_type() { LEN is the number of bytes to be processed. If a character is escaped, it is 2 characters for LEN. A LEN of -1 means decode-until-nul-byte (end of string). */ - -std::vector<uint8_t> decode_binary_data(const char *str, size_t len) { +static std::vector<uint8_t> decode_binary_data(const char *str, size_t len) { std::vector<uint8_t> bytes; if (len == 0) { return bytes; @@ -1304,31 +1325,10 @@ std::vector<uint8_t> decode_binary_data(const char *str, size_t len) { return bytes; } -// Quote any meta characters in a std::string as per the binary -// packet convention in the gdb-remote protocol. - -static std::string binary_encode_string(const std::string &s) { - std::string output; - const size_t s_size = s.size(); - const char *s_chars = s.c_str(); - - for (size_t i = 0; i < s_size; i++) { - unsigned char ch = *(s_chars + i); - if (ch == '#' || ch == '$' || ch == '}' || ch == '*') { - output.push_back('}'); // 0x7d - output.push_back(ch ^ 0x20); - } else { - output.push_back(ch); - } - } - return output; -} - // If the value side of a key-value pair in JSON is a string, // and that string has a " character in it, the " character must // be escaped. - -std::string json_string_quote_metachars(const std::string &s) { +static std::string json_string_quote_metachars(const std::string &s) { if (s.find('"') == std::string::npos) return s; @@ -1462,15 +1462,6 @@ bool RNBRemote::InitializeRegisters(bool force) { } } - // for (auto ®_entry: g_dynamic_register_map) - // { - // DNBLogThreaded("%4i: size = %3u, pseudo = %i, name = %s", - // reg_entry.offset, - // reg_entry.nub_info.size, - // reg_entry.nub_info.value_regs != NULL, - // reg_entry.nub_info.name); - // } - g_reg_entries = g_dynamic_register_map.data(); g_num_reg_entries = g_dynamic_register_map.size(); } @@ -1719,7 +1710,7 @@ rnb_err_t RNBRemote::HandlePacket_qThreadExtraInfo(const char *p) { return SendPacket(""); } -const char *k_space_delimiters = " \t"; +static const char *k_space_delimiters = " \t"; static void skip_spaces(std::string &line) { if (!line.empty()) { size_t space_pos = line.find_first_not_of(k_space_delimiters); @@ -2024,7 +2015,7 @@ rnb_err_t RNBRemote::HandlePacket_qRegisterInfo(const char *p) { QSetLogging:bitmask=LOG_ALL;mode=asl; */ -rnb_err_t set_logging(const char *p) { +static rnb_err_t set_logging(const char *p) { int bitmask = 0; while (p && *p != '\0') { if (strncmp(p, "bitmask=", sizeof("bitmask=") - 1) == 0) { @@ -2568,11 +2559,10 @@ rnb_err_t RNBRemote::HandlePacket_QSetProcessEvent(const char *p) { // If a fail_value is provided, a correct-length reply is always provided, // even if the register cannot be read right now on this thread. -bool register_value_in_hex_fixed_width(std::ostream &ostrm, nub_process_t pid, - nub_thread_t tid, - const register_map_entry_t *reg, - const DNBRegisterValue *reg_value_ptr, - std::optional<uint8_t> fail_value) { +static bool register_value_in_hex_fixed_width( + std::ostream &ostrm, nub_process_t pid, nub_thread_t tid, + const register_map_entry_t *reg, const DNBRegisterValue *reg_value_ptr, + std::optional<uint8_t> fail_value) { if (reg != NULL) { std::unique_ptr<DNBRegisterValue> reg_value = std::make_unique<DNBRegisterValue>(); @@ -2599,7 +2589,7 @@ bool register_value_in_hex_fixed_width(std::ostream &ostrm, nub_process_t pid, return false; } -void debugserver_regnum_with_fixed_width_hex_register_value( +static void debugserver_regnum_with_fixed_width_hex_register_value( std::ostream &ostrm, nub_process_t pid, nub_thread_t tid, const register_map_entry_t *reg, const DNBRegisterValue *reg_value_ptr, std::optional<uint8_t> fail_value) { @@ -3216,21 +3206,9 @@ rnb_err_t RNBRemote::HandlePacket_x(const char *p) { return SendErrorPacket("E80"); } - std::vector<uint8_t> buf_quoted; - buf_quoted.reserve(bytes_read + 30); - for (nub_size_t i = 0; i < bytes_read; i++) { - if (buf[i] == '#' || buf[i] == '$' || buf[i] == '}' || buf[i] == '*') { - buf_quoted.push_back(0x7d); - buf_quoted.push_back(buf[i] ^ 0x20); - } else { - buf_quoted.push_back(buf[i]); - } - } - length = buf_quoted.size(); - + buf.resize(bytes_read); std::ostringstream ostrm; - for (unsigned long i = 0; i < length; i++) - ostrm << buf_quoted[i]; + binary_encode_data_vector(ostrm, buf); return SendPacket(ostrm.str()); } @@ -4902,8 +4880,8 @@ rnb_err_t RNBRemote::HandlePacket_qHostInfo(const char *p) { return SendPacket(strm.str()); } -void XMLElementStart(std::ostringstream &s, uint32_t indent, const char *name, - bool has_attributes) { +static void XMLElementStart(std::ostringstream &s, uint32_t indent, + const char *name, bool has_attributes) { if (indent) s << INDENT_WITH_SPACES(indent); s << '<' << name; @@ -4911,43 +4889,22 @@ void XMLElementStart(std::ostringstream &s, uint32_t indent, const char *name, s << '>' << std::endl; } -void XMLElementStartEndAttributes(std::ostringstream &s, bool empty) { +static void XMLElementStartEndAttributes(std::ostringstream &s, bool empty) { if (empty) s << '/'; s << '>' << std::endl; } -void XMLElementEnd(std::ostringstream &s, uint32_t indent, const char *name) { +static void XMLElementEnd(std::ostringstream &s, uint32_t indent, + const char *name) { if (indent) s << INDENT_WITH_SPACES(indent); s << '<' << '/' << name << '>' << std::endl; } -void XMLElementWithStringValue(std::ostringstream &s, uint32_t indent, - const char *name, const char *value, - bool close = true) { - if (value) { - if (indent) - s << INDENT_WITH_SPACES(indent); - s << '<' << name << '>' << value; - if (close) - XMLElementEnd(s, 0, name); - } -} - -void XMLElementWithUnsignedValue(std::ostringstream &s, uint32_t indent, - const char *name, uint64_t value, - bool close = true) { - if (indent) - s << INDENT_WITH_SPACES(indent); - - s << '<' << name << '>' << DECIMAL << value; - if (close) - XMLElementEnd(s, 0, name); -} - -void XMLAttributeString(std::ostringstream &s, const char *name, - const char *value, const char *default_value = NULL) { +static void XMLAttributeString(std::ostringstream &s, const char *name, + const char *value, + const char *default_value = NULL) { if (value) { if (default_value && strcmp(value, default_value) == 0) return; // No need to emit the attribute because it matches the default @@ -4956,15 +4913,16 @@ void XMLAttributeString(std::ostringstream &s, const char *name, } } -void XMLAttributeUnsignedDecimal(std::ostringstream &s, const char *name, - uint64_t value) { +static void XMLAttributeUnsignedDecimal(std::ostringstream &s, const char *name, + uint64_t value) { s << ' ' << name << "=\"" << DECIMAL << value << "\""; } -void GenerateTargetXMLRegister(std::ostringstream &s, const uint32_t reg_num, - nub_size_t num_reg_sets, - const DNBRegisterSetInfo *reg_set_info, - const register_map_entry_t ®) { +static void GenerateTargetXMLRegister(std::ostringstream &s, + const uint32_t reg_num, + nub_size_t num_reg_sets, + const DNBRegisterSetInfo *reg_set_info, + const register_map_entry_t ®) { const char *default_lldb_encoding = "uint"; const char *lldb_encoding = default_lldb_encoding; const char *gdb_group = "general"; @@ -5135,7 +5093,7 @@ void GenerateTargetXMLRegister(std::ostringstream &s, const uint32_t reg_num, XMLElementStartEndAttributes(s, true); } -void GenerateTargetXMLRegisters(std::ostringstream &s) { +static void GenerateTargetXMLRegisters(std::ostringstream &s) { nub_size_t num_reg_sets = 0; const DNBRegisterSetInfo *reg_sets = DNBGetRegisterSetInfo(&num_reg_sets); @@ -5174,7 +5132,7 @@ static const char *g_target_xml_footer = "</target>"; static std::string g_target_xml; -void UpdateTargetXML() { +static void UpdateTargetXML() { std::ostringstream s; s << g_target_xml_header << std::endl; @@ -5309,8 +5267,9 @@ rnb_err_t RNBRemote::HandlePacket_jGetDyldProcessState(const char *p) { // a one-level-deep JSON dictionary of key-value pairs. e.g. // jThreadExtendedInfo:{"plo_pthread_tsd_base_address_offset":0,"plo_pthread_tsd_base_offset":224,"plo_pthread_tsd_entry_size":8,"thread":144305}] // -uint64_t get_integer_value_for_key_name_from_json(const char *key, - const char *json_string) { +static uint64_t +get_integer_value_for_key_name_from_json(const char *key, + const char *json_string) { uint64_t retval = INVALID_NUB_ADDRESS; std::string key_with_quotes = "\""; key_with_quotes += key; @@ -5346,9 +5305,9 @@ uint64_t get_integer_value_for_key_name_from_json(const char *key, // Returns true if it was able to find the key name, and sets the 'value' // argument to the value found. -bool get_boolean_value_for_key_name_from_json(const char *key, - const char *json_string, - bool &value) { +static bool get_boolean_value_for_key_name_from_json(const char *key, + const char *json_string, + bool &value) { std::string key_with_quotes = "\""; key_with_quotes += key; key_with_quotes += "\""; @@ -5385,7 +5344,7 @@ bool get_boolean_value_for_key_name_from_json(const char *key, // Returns true if it was able to find the key name, false if it did not. // "ints" will have all integers found in the array appended to it. -bool get_array_of_ints_value_for_key_name_from_json( +static bool get_array_of_ints_value_for_key_name_from_json( const char *key, const char *json_string, std::vector<uint64_t> &ints) { std::string key_with_quotes = "\""; key_with_quotes += key; diff --git a/lldb/unittests/Host/MainLoopTest.cpp b/lldb/unittests/Host/MainLoopTest.cpp index 0bc291c..ae16d02 100644 --- a/lldb/unittests/Host/MainLoopTest.cpp +++ b/lldb/unittests/Host/MainLoopTest.cpp @@ -424,9 +424,9 @@ TEST_F(MainLoopTest, ManyPendingCallbacks) { TEST_F(MainLoopTest, CallbackWithTimeout) { MainLoop loop; + auto start = std::chrono::steady_clock::now(); loop.AddCallback([](MainLoopBase &loop) { loop.RequestTermination(); }, std::chrono::seconds(2)); - auto start = std::chrono::steady_clock::now(); ASSERT_THAT_ERROR(loop.Run().takeError(), llvm::Succeeded()); EXPECT_GE(std::chrono::steady_clock::now() - start, std::chrono::seconds(2)); } diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index f9e2e4a..49184e3 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -334,7 +334,7 @@ LLVM supports (to various degrees) a number of experimental extensions. All exp The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases. Experimental extensions are expected to either transition to ratified status, or be eventually removed. The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised. ``experimental-zalasr`` - LLVM implements the `0.0.5 draft specification <https://github.com/mehnadnerd/riscv-zalasr>`__. + LLVM implements the `0.9 draft specification <https://github.com/riscv/riscv-zalasr/releases/tag/v0.9>`__. ``experimental-zibi`` LLVM implements the `0.1 release specification <https://github.com/riscv/zibi/releases/tag/v0.1.0>`__. diff --git a/llvm/include/llvm/ADT/EquivalenceClasses.h b/llvm/include/llvm/ADT/EquivalenceClasses.h index 90d8948..5e8c2fa 100644 --- a/llvm/include/llvm/ADT/EquivalenceClasses.h +++ b/llvm/include/llvm/ADT/EquivalenceClasses.h @@ -128,7 +128,7 @@ private: /// ECValues, it just keeps the key as part of the value. DenseMap<ElemTy, ECValue *> TheMapping; - /// List of all members, used to provide a determinstic iteration order. + /// List of all members, used to provide a deterministic iteration order. SmallVector<const ECValue *> Members; mutable BumpPtrAllocator ECValueAllocator; diff --git a/llvm/include/llvm/Analysis/HeatUtils.h b/llvm/include/llvm/Analysis/HeatUtils.h index 179862c..2391086 100644 --- a/llvm/include/llvm/Analysis/HeatUtils.h +++ b/llvm/include/llvm/Analysis/HeatUtils.h @@ -23,17 +23,17 @@ class BlockFrequencyInfo; class Function; // Returns number of calls of calledFunction by callerFunction. -LLVM_ABI uint64_t getNumOfCalls(Function &callerFunction, - Function &calledFunction); +LLVM_ABI uint64_t getNumOfCalls(const Function &CallerFunction, + const Function &CalledFunction); // Returns the maximum frequency of a BB in a function. LLVM_ABI uint64_t getMaxFreq(const Function &F, const BlockFrequencyInfo *BFI); // Calculates heat color based on current and maximum frequencies. -LLVM_ABI std::string getHeatColor(uint64_t freq, uint64_t maxFreq); +LLVM_ABI std::string getHeatColor(uint64_t Freq, uint64_t MaxFreq); // Calculates heat color based on percent of "hotness". -LLVM_ABI std::string getHeatColor(double percent); +LLVM_ABI std::string getHeatColor(double Percent); } // namespace llvm diff --git a/llvm/include/llvm/Analysis/IR2Vec.h b/llvm/include/llvm/Analysis/IR2Vec.h index ed43f19..81409df 100644 --- a/llvm/include/llvm/Analysis/IR2Vec.h +++ b/llvm/include/llvm/Analysis/IR2Vec.h @@ -153,8 +153,11 @@ private: /// Section-based storage std::vector<std::vector<Embedding>> Sections; - const size_t TotalSize; - const unsigned Dimension; + // Fixme: Check if these members can be made const (and delete move + // assignment) after changing Vocabulary creation by using static factory + // methods. + size_t TotalSize = 0; + unsigned Dimension = 0; public: /// Default constructor creates empty storage (invalid state) @@ -164,7 +167,7 @@ public: VocabStorage(std::vector<std::vector<Embedding>> &&SectionData); VocabStorage(VocabStorage &&) = default; - VocabStorage &operator=(VocabStorage &&) = delete; + VocabStorage &operator=(VocabStorage &&) = default; VocabStorage(const VocabStorage &) = delete; VocabStorage &operator=(const VocabStorage &) = delete; diff --git a/llvm/include/llvm/CodeGen/MIR2Vec.h b/llvm/include/llvm/CodeGen/MIR2Vec.h new file mode 100644 index 0000000..ea68b45 --- /dev/null +++ b/llvm/include/llvm/CodeGen/MIR2Vec.h @@ -0,0 +1,186 @@ +//===- MIR2Vec.h - Implementation of MIR2Vec ------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM +// Exceptions. See the LICENSE file for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file defines the MIR2Vec vocabulary +/// analysis(MIR2VecVocabLegacyAnalysis), the core mir2vec::MIREmbedder +/// interface for generating Machine IR embeddings, and related utilities. +/// +/// MIR2Vec extends IR2Vec to support Machine IR embeddings. It represents the +/// LLVM Machine IR as embeddings which can be used as input to machine learning +/// algorithms. +/// +/// The original idea of MIR2Vec is described in the following paper: +/// +/// RL4ReAl: Reinforcement Learning for Register Allocation. S. VenkataKeerthy, +/// Siddharth Jain, Anilava Kundu, Rohit Aggarwal, Albert Cohen, and Ramakrishna +/// Upadrasta. 2023. RL4ReAl: Reinforcement Learning for Register Allocation. +/// Proceedings of the 32nd ACM SIGPLAN International Conference on Compiler +/// Construction (CC 2023). https://doi.org/10.1145/3578360.3580273. +/// https://arxiv.org/abs/2204.02013 +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_MIR2VEC_H +#define LLVM_CODEGEN_MIR2VEC_H + +#include "llvm/Analysis/IR2Vec.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/IR/PassManager.h" +#include "llvm/Pass.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/ErrorOr.h" +#include <map> +#include <set> +#include <string> + +namespace llvm { + +class Module; +class raw_ostream; +class LLVMContext; +class MIR2VecVocabLegacyAnalysis; +class TargetInstrInfo; + +namespace mir2vec { +extern llvm::cl::OptionCategory MIR2VecCategory; +extern cl::opt<float> OpcWeight; + +using Embedding = ir2vec::Embedding; + +/// Class for storing and accessing the MIR2Vec vocabulary. +/// The MIRVocabulary class manages seed embeddings for LLVM Machine IR +class MIRVocabulary { + friend class llvm::MIR2VecVocabLegacyAnalysis; + using VocabMap = std::map<std::string, ir2vec::Embedding>; + +private: + // Define vocabulary layout - adapted for MIR + struct { + size_t OpcodeBase = 0; + size_t OperandBase = 0; + size_t TotalEntries = 0; + } Layout; + + enum class Section : unsigned { Opcodes = 0, MaxSections }; + + ir2vec::VocabStorage Storage; + mutable std::set<std::string> UniqueBaseOpcodeNames; + const TargetInstrInfo &TII; + void generateStorage(const VocabMap &OpcodeMap); + void buildCanonicalOpcodeMapping(); + + /// Get canonical index for a machine opcode + unsigned getCanonicalOpcodeIndex(unsigned Opcode) const; + +public: + /// Static method for extracting base opcode names (public for testing) + static std::string extractBaseOpcodeName(StringRef InstrName); + + /// Get canonical index for base name (public for testing) + unsigned getCanonicalIndexForBaseName(StringRef BaseName) const; + + /// Get the string key for a vocabulary entry at the given position + std::string getStringKey(unsigned Pos) const; + + MIRVocabulary() = delete; + MIRVocabulary(VocabMap &&Entries, const TargetInstrInfo *TII); + MIRVocabulary(ir2vec::VocabStorage &&Storage, const TargetInstrInfo &TII) + : Storage(std::move(Storage)), TII(TII) {} + + bool isValid() const { + return UniqueBaseOpcodeNames.size() > 0 && + Layout.TotalEntries == Storage.size() && Storage.isValid(); + } + + unsigned getDimension() const { + if (!isValid()) + return 0; + return Storage.getDimension(); + } + + // Accessor methods + const Embedding &operator[](unsigned Opcode) const { + assert(isValid() && "MIR2Vec Vocabulary is invalid"); + unsigned LocalIndex = getCanonicalOpcodeIndex(Opcode); + return Storage[static_cast<unsigned>(Section::Opcodes)][LocalIndex]; + } + + // Iterator access + using const_iterator = ir2vec::VocabStorage::const_iterator; + const_iterator begin() const { + assert(isValid() && "MIR2Vec Vocabulary is invalid"); + return Storage.begin(); + } + + const_iterator end() const { + assert(isValid() && "MIR2Vec Vocabulary is invalid"); + return Storage.end(); + } + + /// Total number of entries in the vocabulary + size_t getCanonicalSize() const { + assert(isValid() && "Invalid vocabulary"); + return Storage.size(); + } +}; + +} // namespace mir2vec + +/// Pass to analyze and populate MIR2Vec vocabulary from a module +class MIR2VecVocabLegacyAnalysis : public ImmutablePass { + using VocabVector = std::vector<mir2vec::Embedding>; + using VocabMap = std::map<std::string, mir2vec::Embedding>; + VocabMap StrVocabMap; + VocabVector Vocab; + + StringRef getPassName() const override; + Error readVocabulary(); + void emitError(Error Err, LLVMContext &Ctx); + +protected: + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired<MachineModuleInfoWrapperPass>(); + AU.setPreservesAll(); + } + +public: + static char ID; + MIR2VecVocabLegacyAnalysis() : ImmutablePass(ID) {} + mir2vec::MIRVocabulary getMIR2VecVocabulary(const Module &M); +}; + +/// This pass prints the embeddings in the MIR2Vec vocabulary +class MIR2VecVocabPrinterLegacyPass : public MachineFunctionPass { + raw_ostream &OS; + +public: + static char ID; + explicit MIR2VecVocabPrinterLegacyPass(raw_ostream &OS) + : MachineFunctionPass(ID), OS(OS) {} + + bool runOnMachineFunction(MachineFunction &MF) override; + bool doFinalization(Module &M) override; + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired<MIR2VecVocabLegacyAnalysis>(); + AU.setPreservesAll(); + MachineFunctionPass::getAnalysisUsage(AU); + } + + StringRef getPassName() const override { + return "MIR2Vec Vocabulary Printer Pass"; + } +}; + +} // namespace llvm + +#endif // LLVM_CODEGEN_MIR2VEC_H
\ No newline at end of file diff --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h index f17d550..272b4ac 100644 --- a/llvm/include/llvm/CodeGen/Passes.h +++ b/llvm/include/llvm/CodeGen/Passes.h @@ -88,6 +88,11 @@ LLVM_ABI MachineFunctionPass * createMachineFunctionPrinterPass(raw_ostream &OS, const std::string &Banner = ""); +/// MIR2VecVocabPrinter pass - This pass prints out the MIR2Vec vocabulary +/// contents to the given stream as a debugging tool. +LLVM_ABI MachineFunctionPass * +createMIR2VecVocabPrinterLegacyPass(raw_ostream &OS); + /// StackFramePrinter pass - This pass prints out the machine function's /// stack frame to the given stream as a debugging tool. LLVM_ABI MachineFunctionPass *createStackFrameLayoutAnalysisPass(); diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h index 88272f0..cd774e7 100644 --- a/llvm/include/llvm/InitializePasses.h +++ b/llvm/include/llvm/InitializePasses.h @@ -220,6 +220,8 @@ LLVM_ABI void initializeMachinePostDominatorTreeWrapperPassPass(PassRegistry &); LLVM_ABI void initializeMachineRegionInfoPassPass(PassRegistry &); LLVM_ABI void initializeMachineSanitizerBinaryMetadataLegacyPass(PassRegistry &); +LLVM_ABI void initializeMIR2VecVocabLegacyAnalysisPass(PassRegistry &); +LLVM_ABI void initializeMIR2VecVocabPrinterLegacyPassPass(PassRegistry &); LLVM_ABI void initializeMachineSchedulerLegacyPass(PassRegistry &); LLVM_ABI void initializeMachineSinkingLegacyPass(PassRegistry &); LLVM_ABI void initializeMachineTraceMetricsWrapperPassPass(PassRegistry &); diff --git a/llvm/include/llvm/Support/SpecialCaseList.h b/llvm/include/llvm/Support/SpecialCaseList.h index 22a62ea..55d3d12 100644 --- a/llvm/include/llvm/Support/SpecialCaseList.h +++ b/llvm/include/llvm/Support/SpecialCaseList.h @@ -147,10 +147,17 @@ protected: Section(StringRef Str, unsigned FileIdx) : SectionStr(Str), FileIdx(FileIdx) {}; - std::unique_ptr<Matcher> SectionMatcher = std::make_unique<Matcher>(); + Section(Section &&) = default; + + Matcher SectionMatcher; SectionEntries Entries; std::string SectionStr; unsigned FileIdx; + + // Helper method to search by Prefix, Query, and Category. Returns + // 1-based line number on which rule is defined, or 0 if there is no match. + LLVM_ABI unsigned getLastMatch(StringRef Prefix, StringRef Query, + StringRef Category) const; }; std::vector<Section> Sections; @@ -162,12 +169,6 @@ protected: /// Parses just-constructed SpecialCaseList entries from a memory buffer. LLVM_ABI bool parse(unsigned FileIdx, const MemoryBuffer *MB, std::string &Error); - - // Helper method for derived classes to search by Prefix, Query, and Category - // once they have already resolved a section entry. - LLVM_ABI unsigned inSectionBlame(const SectionEntries &Entries, - StringRef Prefix, StringRef Query, - StringRef Category) const; }; } // namespace llvm diff --git a/llvm/lib/Analysis/HeatUtils.cpp b/llvm/lib/Analysis/HeatUtils.cpp index b6a0d58..a1cc707 100644 --- a/llvm/lib/Analysis/HeatUtils.cpp +++ b/llvm/lib/Analysis/HeatUtils.cpp @@ -17,10 +17,10 @@ #include <cmath> -namespace llvm { +using namespace llvm; -static const unsigned heatSize = 100; -static const char heatPalette[heatSize][8] = { +static constexpr unsigned HeatSize = 100; +static constexpr char HeatPalette[HeatSize][8] = { "#3d50c3", "#4055c8", "#4358cb", "#465ecf", "#4961d2", "#4c66d6", "#4f69d9", "#536edd", "#5572df", "#5977e3", "#5b7ae5", "#5f7fe8", "#6282ea", "#6687ed", "#6a8bef", "#6c8ff1", "#7093f3", "#7396f5", "#779af7", "#7a9df8", "#7ea1fa", @@ -37,43 +37,37 @@ static const char heatPalette[heatSize][8] = { "#d24b40", "#d0473d", "#cc403a", "#ca3b37", "#c53334", "#c32e31", "#be242e", "#bb1b2c", "#b70d28"}; -uint64_t -getNumOfCalls(Function &callerFunction, Function &calledFunction) { - uint64_t counter = 0; - for (User *U : calledFunction.users()) { - if (auto CI = dyn_cast<CallInst>(U)) { - if (CI->getCaller() == (&callerFunction)) { - counter += 1; - } - } - } - return counter; +uint64_t llvm::getNumOfCalls(const Function &CallerFunction, + const Function &CalledFunction) { + uint64_t Counter = 0; + for (const User *U : CalledFunction.users()) + if (auto CI = dyn_cast<CallInst>(U)) + Counter += CI->getCaller() == &CallerFunction; + return Counter; } -uint64_t getMaxFreq(const Function &F, const BlockFrequencyInfo *BFI) { - uint64_t maxFreq = 0; +uint64_t llvm::getMaxFreq(const Function &F, const BlockFrequencyInfo *BFI) { + uint64_t MaxFreq = 0; for (const BasicBlock &BB : F) { - uint64_t freqVal = BFI->getBlockFreq(&BB).getFrequency(); - if (freqVal >= maxFreq) - maxFreq = freqVal; + uint64_t FreqVal = BFI->getBlockFreq(&BB).getFrequency(); + if (FreqVal >= MaxFreq) + MaxFreq = FreqVal; } - return maxFreq; + return MaxFreq; } -std::string getHeatColor(uint64_t freq, uint64_t maxFreq) { - if (freq > maxFreq) - freq = maxFreq; - double percent = (freq > 0) ? log2(double(freq)) / log2(maxFreq) : 0; - return getHeatColor(percent); +std::string llvm::getHeatColor(uint64_t Freq, uint64_t MaxFreq) { + if (Freq > MaxFreq) + Freq = MaxFreq; + double Percent = (Freq > 0) ? log2(double(Freq)) / log2(MaxFreq) : 0; + return getHeatColor(Percent); } -std::string getHeatColor(double percent) { - if (percent > 1.0) - percent = 1.0; - if (percent < 0.0) - percent = 0.0; - unsigned colorId = unsigned(round(percent * (heatSize - 1.0))); - return heatPalette[colorId]; +std::string llvm::getHeatColor(double Percent) { + if (Percent > 1.0) + Percent = 1.0; + if (Percent < 0.0) + Percent = 0.0; + unsigned ColorID = unsigned(round(Percent * (HeatSize - 1.0))); + return HeatPalette[ColorID]; } - -} // namespace llvm diff --git a/llvm/lib/Analysis/models/x86SeedEmbeddingVocab100D.json b/llvm/lib/Analysis/models/x86SeedEmbeddingVocab100D.json new file mode 100644 index 0000000..0afe5c7 --- /dev/null +++ b/llvm/lib/Analysis/models/x86SeedEmbeddingVocab100D.json @@ -0,0 +1,677 @@ +{ + "entities" : { + "ABS_Fp":[0.07323841750621796, -0.006006906274706125, 0.09751169383525848, -0.011089739389717579, 0.06642112135887146, -0.015824640169739723, -0.021592319011688232, -0.0035401300992816687, 0.06047678738832474, -0.007392085622996092, 0.07134906202554703, -0.019624482840299606, -0.10975595563650131, -0.007685789838433266, 0.07451746612787247, 0.06384266912937164, -0.08230067789554596, 0.050922468304634094, 0.013724055141210556, 0.015687907114624977, -0.018451329320669174, 0.046987198293209076, -0.037734340876340866, -0.07235030829906464, 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\ No newline at end of file diff --git a/llvm/lib/CodeGen/CMakeLists.txt b/llvm/lib/CodeGen/CMakeLists.txt index f8f9bbb..b6872605 100644 --- a/llvm/lib/CodeGen/CMakeLists.txt +++ b/llvm/lib/CodeGen/CMakeLists.txt @@ -155,6 +155,7 @@ add_llvm_component_library(LLVMCodeGen MIRFSDiscriminator.cpp MIRSampleProfile.cpp MIRYamlMapping.cpp + MIR2Vec.cpp MLRegAllocEvictAdvisor.cpp MLRegAllocPriorityAdvisor.cpp ModuloSchedule.cpp diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp index 9e0cb3b..c438eae 100644 --- a/llvm/lib/CodeGen/CodeGen.cpp +++ b/llvm/lib/CodeGen/CodeGen.cpp @@ -96,6 +96,8 @@ void llvm::initializeCodeGen(PassRegistry &Registry) { initializeMachineSchedulerLegacyPass(Registry); initializeMachineSinkingLegacyPass(Registry); initializeMachineUniformityAnalysisPassPass(Registry); + initializeMIR2VecVocabLegacyAnalysisPass(Registry); + initializeMIR2VecVocabPrinterLegacyPassPass(Registry); initializeMachineUniformityInfoPrinterPassPass(Registry); initializeMachineVerifierLegacyPassPass(Registry); initializeObjCARCContractLegacyPassPass(Registry); diff --git a/llvm/lib/CodeGen/MIR2Vec.cpp b/llvm/lib/CodeGen/MIR2Vec.cpp new file mode 100644 index 0000000..87565c0 --- /dev/null +++ b/llvm/lib/CodeGen/MIR2Vec.cpp @@ -0,0 +1,306 @@ +//===- MIR2Vec.cpp - Implementation of MIR2Vec ---------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM +// Exceptions. See the LICENSE file for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements the MIR2Vec algorithm for Machine IR embeddings. +/// +//===----------------------------------------------------------------------===// + +#include "llvm/CodeGen/MIR2Vec.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/CodeGen/TargetInstrInfo.h" +#include "llvm/IR/Module.h" +#include "llvm/InitializePasses.h" +#include "llvm/Pass.h" +#include "llvm/Support/Errc.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/Regex.h" + +using namespace llvm; +using namespace mir2vec; + +#define DEBUG_TYPE "mir2vec" + +STATISTIC(MIRVocabMissCounter, + "Number of lookups to MIR entities not present in the vocabulary"); + +namespace llvm { +namespace mir2vec { +cl::OptionCategory MIR2VecCategory("MIR2Vec Options"); + +// FIXME: Use a default vocab when not specified +static cl::opt<std::string> + VocabFile("mir2vec-vocab-path", cl::Optional, + cl::desc("Path to the vocabulary file for MIR2Vec"), cl::init(""), + cl::cat(MIR2VecCategory)); +cl::opt<float> OpcWeight("mir2vec-opc-weight", cl::Optional, cl::init(1.0), + cl::desc("Weight for machine opcode embeddings"), + cl::cat(MIR2VecCategory)); +} // namespace mir2vec +} // namespace llvm + +//===----------------------------------------------------------------------===// +// Vocabulary Implementation +//===----------------------------------------------------------------------===// + +MIRVocabulary::MIRVocabulary(VocabMap &&OpcodeEntries, + const TargetInstrInfo *TII) + : TII(*TII) { + // Fixme: Use static factory methods for creating vocabularies instead of + // public constructors + // Early return for invalid inputs - creates empty/invalid vocabulary + if (!TII || OpcodeEntries.empty()) + return; + + buildCanonicalOpcodeMapping(); + + unsigned CanonicalOpcodeCount = UniqueBaseOpcodeNames.size(); + assert(CanonicalOpcodeCount > 0 && + "No canonical opcodes found for target - invalid vocabulary"); + Layout.OperandBase = CanonicalOpcodeCount; + generateStorage(OpcodeEntries); + Layout.TotalEntries = Storage.size(); +} + +std::string MIRVocabulary::extractBaseOpcodeName(StringRef InstrName) { + // Extract base instruction name using regex to capture letters and + // underscores Examples: "ADD32rr" -> "ADD", "ARITH_FENCE" -> "ARITH_FENCE" + // + // TODO: Consider more sophisticated extraction: + // - Handle complex prefixes like "AVX1_SETALLONES" correctly (Currently, it + // would naively map to "AVX") + // - Extract width suffixes (8,16,32,64) as separate features + // - Capture addressing mode suffixes (r,i,m,ri,etc.) for better analysis + // (Currently, instances like "MOV32mi" map to "MOV", but "ADDPDrr" would map + // to "ADDPDrr") + + assert(!InstrName.empty() && "Instruction name should not be empty"); + + // Use regex to extract initial sequence of letters and underscores + static const Regex BaseOpcodeRegex("([a-zA-Z_]+)"); + SmallVector<StringRef, 2> Matches; + + if (BaseOpcodeRegex.match(InstrName, &Matches) && Matches.size() > 1) { + StringRef Match = Matches[1]; + // Trim trailing underscores + while (!Match.empty() && Match.back() == '_') + Match = Match.drop_back(); + return Match.str(); + } + + // Fallback to original name if no pattern matches + return InstrName.str(); +} + +unsigned MIRVocabulary::getCanonicalIndexForBaseName(StringRef BaseName) const { + assert(!UniqueBaseOpcodeNames.empty() && "Canonical mapping not built"); + auto It = std::find(UniqueBaseOpcodeNames.begin(), + UniqueBaseOpcodeNames.end(), BaseName.str()); + assert(It != UniqueBaseOpcodeNames.end() && + "Base name not found in unique opcodes"); + return std::distance(UniqueBaseOpcodeNames.begin(), It); +} + +unsigned MIRVocabulary::getCanonicalOpcodeIndex(unsigned Opcode) const { + assert(isValid() && "MIR2Vec Vocabulary is invalid"); + auto BaseOpcode = extractBaseOpcodeName(TII.getName(Opcode)); + return getCanonicalIndexForBaseName(BaseOpcode); +} + +std::string MIRVocabulary::getStringKey(unsigned Pos) const { + assert(isValid() && "MIR2Vec Vocabulary is invalid"); + assert(Pos < Layout.TotalEntries && "Position out of bounds in vocabulary"); + + // For now, all entries are opcodes since we only have one section + if (Pos < Layout.OperandBase && Pos < UniqueBaseOpcodeNames.size()) { + // Convert canonical index back to base opcode name + auto It = UniqueBaseOpcodeNames.begin(); + std::advance(It, Pos); + return *It; + } + + llvm_unreachable("Invalid position in vocabulary"); + return ""; +} + +void MIRVocabulary::generateStorage(const VocabMap &OpcodeMap) { + + // Helper for handling missing entities in the vocabulary. + // Currently, we use a zero vector. In the future, we will throw an error to + // ensure that *all* known entities are present in the vocabulary. + auto handleMissingEntity = [](StringRef Key) { + LLVM_DEBUG(errs() << "MIR2Vec: Missing vocabulary entry for " << Key + << "; using zero vector. This will result in an error " + "in the future.\n"); + ++MIRVocabMissCounter; + }; + + // Initialize opcode embeddings section + unsigned EmbeddingDim = OpcodeMap.begin()->second.size(); + std::vector<Embedding> OpcodeEmbeddings(Layout.OperandBase, + Embedding(EmbeddingDim)); + + // Populate opcode embeddings using canonical mapping + for (auto COpcodeName : UniqueBaseOpcodeNames) { + if (auto It = OpcodeMap.find(COpcodeName); It != OpcodeMap.end()) { + auto COpcodeIndex = getCanonicalIndexForBaseName(COpcodeName); + assert(COpcodeIndex < Layout.OperandBase && + "Canonical index out of bounds"); + OpcodeEmbeddings[COpcodeIndex] = It->second; + } else { + handleMissingEntity(COpcodeName); + } + } + + // TODO: Add operand/argument embeddings as additional sections + // This will require extending the vocabulary format and layout + + // Scale the vocabulary sections based on the provided weights + auto scaleVocabSection = [](std::vector<Embedding> &Embeddings, + double Weight) { + for (auto &Embedding : Embeddings) + Embedding *= Weight; + }; + scaleVocabSection(OpcodeEmbeddings, OpcWeight); + + std::vector<std::vector<Embedding>> Sections(1); + Sections[0] = std::move(OpcodeEmbeddings); + + Storage = ir2vec::VocabStorage(std::move(Sections)); +} + +void MIRVocabulary::buildCanonicalOpcodeMapping() { + // Check if already built + if (!UniqueBaseOpcodeNames.empty()) + return; + + // Build mapping from opcodes to canonical base opcode indices + for (unsigned Opcode = 0; Opcode < TII.getNumOpcodes(); ++Opcode) { + std::string BaseOpcode = extractBaseOpcodeName(TII.getName(Opcode)); + UniqueBaseOpcodeNames.insert(BaseOpcode); + } + + LLVM_DEBUG(dbgs() << "MIR2Vec: Built canonical mapping for target with " + << UniqueBaseOpcodeNames.size() + << " unique base opcodes\n"); +} + +//===----------------------------------------------------------------------===// +// MIR2VecVocabLegacyAnalysis Implementation +//===----------------------------------------------------------------------===// + +char MIR2VecVocabLegacyAnalysis::ID = 0; +INITIALIZE_PASS_BEGIN(MIR2VecVocabLegacyAnalysis, "mir2vec-vocab-analysis", + "MIR2Vec Vocabulary Analysis", false, true) +INITIALIZE_PASS_DEPENDENCY(MachineModuleInfoWrapperPass) +INITIALIZE_PASS_END(MIR2VecVocabLegacyAnalysis, "mir2vec-vocab-analysis", + "MIR2Vec Vocabulary Analysis", false, true) + +StringRef MIR2VecVocabLegacyAnalysis::getPassName() const { + return "MIR2Vec Vocabulary Analysis"; +} + +Error MIR2VecVocabLegacyAnalysis::readVocabulary() { + // TODO: Extend vocabulary format to support multiple sections + // (opcodes, operands, etc.) similar to IR2Vec structure + if (VocabFile.empty()) + return createStringError( + errc::invalid_argument, + "MIR2Vec vocabulary file path not specified; set it " + "using --mir2vec-vocab-path"); + + auto BufOrError = MemoryBuffer::getFileOrSTDIN(VocabFile, /*IsText=*/true); + if (!BufOrError) + return createFileError(VocabFile, BufOrError.getError()); + + auto Content = BufOrError.get()->getBuffer(); + + Expected<json::Value> ParsedVocabValue = json::parse(Content); + if (!ParsedVocabValue) + return ParsedVocabValue.takeError(); + + unsigned Dim = 0; + if (auto Err = ir2vec::VocabStorage::parseVocabSection( + "entities", *ParsedVocabValue, StrVocabMap, Dim)) + return Err; + + return Error::success(); +} + +void MIR2VecVocabLegacyAnalysis::emitError(Error Err, LLVMContext &Ctx) { + Ctx.emitError(toString(std::move(Err))); +} + +mir2vec::MIRVocabulary +MIR2VecVocabLegacyAnalysis::getMIR2VecVocabulary(const Module &M) { + if (StrVocabMap.empty()) { + if (Error Err = readVocabulary()) { + emitError(std::move(Err), M.getContext()); + return mir2vec::MIRVocabulary(std::move(StrVocabMap), nullptr); + } + } + + // Get machine module info to access machine functions and target info + MachineModuleInfo &MMI = getAnalysis<MachineModuleInfoWrapperPass>().getMMI(); + + // Find first available machine function to get target instruction info + for (const auto &F : M) { + if (F.isDeclaration()) + continue; + + if (auto *MF = MMI.getMachineFunction(F)) { + const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); + return mir2vec::MIRVocabulary(std::move(StrVocabMap), TII); + } + } + + // No machine functions available - return invalid vocabulary + emitError(make_error<StringError>("No machine functions found in module", + inconvertibleErrorCode()), + M.getContext()); + return mir2vec::MIRVocabulary(std::move(StrVocabMap), nullptr); +} + +//===----------------------------------------------------------------------===// +// Printer Passes Implementation +//===----------------------------------------------------------------------===// + +char MIR2VecVocabPrinterLegacyPass::ID = 0; +INITIALIZE_PASS_BEGIN(MIR2VecVocabPrinterLegacyPass, "print-mir2vec-vocab", + "MIR2Vec Vocabulary Printer Pass", false, true) +INITIALIZE_PASS_DEPENDENCY(MIR2VecVocabLegacyAnalysis) +INITIALIZE_PASS_DEPENDENCY(MachineModuleInfoWrapperPass) +INITIALIZE_PASS_END(MIR2VecVocabPrinterLegacyPass, "print-mir2vec-vocab", + "MIR2Vec Vocabulary Printer Pass", false, true) + +bool MIR2VecVocabPrinterLegacyPass::runOnMachineFunction(MachineFunction &MF) { + return false; +} + +bool MIR2VecVocabPrinterLegacyPass::doFinalization(Module &M) { + auto &Analysis = getAnalysis<MIR2VecVocabLegacyAnalysis>(); + auto MIR2VecVocab = Analysis.getMIR2VecVocabulary(M); + + if (!MIR2VecVocab.isValid()) { + OS << "MIR2Vec Vocabulary Printer: Invalid vocabulary\n"; + return false; + } + + unsigned Pos = 0; + for (const auto &Entry : MIR2VecVocab) { + OS << "Key: " << MIR2VecVocab.getStringKey(Pos++) << ": "; + Entry.print(OS); + } + + return false; +} + +MachineFunctionPass * +llvm::createMIR2VecVocabPrinterLegacyPass(raw_ostream &OS) { + return new MIR2VecVocabPrinterLegacyPass(OS); +} diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index 83bb1df..b5f8a61 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -3740,7 +3740,11 @@ bool DAGTypeLegalizer::SoftPromoteHalfOperand(SDNode *N, unsigned OpNo) { case ISD::STRICT_FP_TO_SINT: case ISD::STRICT_FP_TO_UINT: case ISD::FP_TO_SINT: - case ISD::FP_TO_UINT: Res = SoftPromoteHalfOp_FP_TO_XINT(N); break; + case ISD::FP_TO_UINT: + case ISD::LRINT: + case ISD::LLRINT: + Res = SoftPromoteHalfOp_Op0WithStrict(N); + break; case ISD::FP_TO_SINT_SAT: case ISD::FP_TO_UINT_SAT: Res = SoftPromoteHalfOp_FP_TO_XINT_SAT(N); break; @@ -3819,7 +3823,7 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FP_EXTEND(SDNode *N) { return DAG.getNode(GetPromotionOpcode(SVT, RVT), SDLoc(N), RVT, Op); } -SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FP_TO_XINT(SDNode *N) { +SDValue DAGTypeLegalizer::SoftPromoteHalfOp_Op0WithStrict(SDNode *N) { EVT RVT = N->getValueType(0); bool IsStrict = N->isStrictFPOpcode(); SDValue Op = N->getOperand(IsStrict ? 1 : 0); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h index 586c341..d580ce0 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -843,7 +843,7 @@ private: SDValue SoftPromoteHalfOp_FAKE_USE(SDNode *N, unsigned OpNo); SDValue SoftPromoteHalfOp_FCOPYSIGN(SDNode *N, unsigned OpNo); SDValue SoftPromoteHalfOp_FP_EXTEND(SDNode *N); - SDValue SoftPromoteHalfOp_FP_TO_XINT(SDNode *N); + SDValue SoftPromoteHalfOp_Op0WithStrict(SDNode *N); SDValue SoftPromoteHalfOp_FP_TO_XINT_SAT(SDNode *N); SDValue SoftPromoteHalfOp_SETCC(SDNode *N); SDValue SoftPromoteHalfOp_SELECT_CC(SDNode *N, unsigned OpNo); diff --git a/llvm/lib/Support/SpecialCaseList.cpp b/llvm/lib/Support/SpecialCaseList.cpp index 8d4e043..04f092b 100644 --- a/llvm/lib/Support/SpecialCaseList.cpp +++ b/llvm/lib/Support/SpecialCaseList.cpp @@ -15,9 +15,12 @@ #include "llvm/Support/SpecialCaseList.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/ADT/StringRef.h" #include "llvm/Support/LineIterator.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/VirtualFileSystem.h" +#include <limits> #include <stdio.h> #include <string> #include <system_error> @@ -135,7 +138,7 @@ SpecialCaseList::addSection(StringRef SectionStr, unsigned FileNo, Sections.emplace_back(SectionStr, FileNo); auto &Section = Sections.back(); - if (auto Err = Section.SectionMatcher->insert(SectionStr, LineNo, UseGlobs)) { + if (auto Err = Section.SectionMatcher.insert(SectionStr, LineNo, UseGlobs)) { return createStringError(errc::invalid_argument, "malformed section at line " + Twine(LineNo) + ": '" + SectionStr + @@ -147,19 +150,25 @@ SpecialCaseList::addSection(StringRef SectionStr, unsigned FileNo, bool SpecialCaseList::parse(unsigned FileIdx, const MemoryBuffer *MB, std::string &Error) { + unsigned long long Version = 2; + + StringRef Header = MB->getBuffer(); + if (Header.consume_front("#!special-case-list-v")) + consumeUnsignedInteger(Header, 10, Version); + + // In https://reviews.llvm.org/D154014 we added glob support and planned + // to remove regex support in patterns. We temporarily support the + // original behavior using regexes if "#!special-case-list-v1" is the + // first line of the file. For more details, see + // https://discourse.llvm.org/t/use-glob-instead-of-regex-for-specialcaselists/71666 + bool UseGlobs = Version > 1; + Section *CurrentSection; if (auto Err = addSection("*", FileIdx, 1).moveInto(CurrentSection)) { Error = toString(std::move(Err)); return false; } - // In https://reviews.llvm.org/D154014 we added glob support and planned to - // remove regex support in patterns. We temporarily support the original - // behavior using regexes if "#!special-case-list-v1" is the first line of the - // file. For more details, see - // https://discourse.llvm.org/t/use-glob-instead-of-regex-for-specialcaselists/71666 - bool UseGlobs = !MB->getBuffer().starts_with("#!special-case-list-v1\n"); - for (line_iterator LineIt(*MB, /*SkipBlanks=*/true, /*CommentMarker=*/'#'); !LineIt.is_at_eof(); LineIt++) { unsigned LineNo = LineIt.line_number(); @@ -218,8 +227,8 @@ std::pair<unsigned, unsigned> SpecialCaseList::inSectionBlame(StringRef Section, StringRef Prefix, StringRef Query, StringRef Category) const { for (const auto &S : reverse(Sections)) { - if (S.SectionMatcher->match(Section)) { - unsigned Blame = inSectionBlame(S.Entries, Prefix, Query, Category); + if (S.SectionMatcher.match(Section)) { + unsigned Blame = S.getLastMatch(Prefix, Query, Category); if (Blame) return {S.FileIdx, Blame}; } @@ -227,9 +236,9 @@ SpecialCaseList::inSectionBlame(StringRef Section, StringRef Prefix, return NotFound; } -unsigned SpecialCaseList::inSectionBlame(const SectionEntries &Entries, - StringRef Prefix, StringRef Query, - StringRef Category) const { +unsigned SpecialCaseList::Section::getLastMatch(StringRef Prefix, + StringRef Query, + StringRef Category) const { SectionEntries::const_iterator I = Entries.find(Prefix); if (I == Entries.end()) return 0; diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp index f90bcc7..830a35bb 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp @@ -590,6 +590,8 @@ bool AArch64RegisterBankInfo::onlyDefinesFP(const MachineInstr &MI, unsigned Depth) const { switch (MI.getOpcode()) { case AArch64::G_DUP: + case AArch64::G_SADDLP: + case AArch64::G_UADDLP: case TargetOpcode::G_SITOFP: case TargetOpcode::G_UITOFP: case TargetOpcode::G_EXTRACT_VECTOR_ELT: @@ -798,6 +800,8 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { if (Ty.isVector()) OpRegBankIdx[Idx] = PMI_FirstFPR; else if (isPreISelGenericFloatingPointOpcode(Opc) || + (MO.isDef() && onlyDefinesFP(MI, MRI, TRI)) || + (MO.isUse() && onlyUsesFP(MI, MRI, TRI)) || Ty.getSizeInBits() > 64) OpRegBankIdx[Idx] = PMI_FirstFPR; else diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td index 1a697f7..502a8e8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.td +++ b/llvm/lib/Target/AMDGPU/AMDGPU.td @@ -2592,6 +2592,9 @@ def UseFakeTrue16Insts : True16PredicateClass<"Subtarget->hasTrue16BitInsts() && // FIXME When we default to RealTrue16 instead of Fake, change the line as follows. // AssemblerPredicate<(all_of FeatureTrue16BitInsts, (not FeatureRealTrue16Insts))>; +def UseTrue16WithSramECC : True16PredicateClass<"Subtarget->useRealTrue16Insts() && " + "!Subtarget->d16PreservesUnusedBits()">; + def HasD16Writes32BitVgpr: Predicate<"Subtarget->hasD16Writes32BitVgpr()">, AssemblerPredicate<(all_of FeatureTrue16BitInsts, FeatureRealTrue16Insts, FeatureD16Writes32BitVgpr)>; def NotHasD16Writes32BitVgpr: Predicate<"!Subtarget->hasD16Writes32BitVgpr()">, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp index cb49936..65d049e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp @@ -1504,7 +1504,6 @@ static bool runImpl(Module &M, AnalysisGetter &AG, TargetMachine &TM, A.getOrCreateAAFor<AAAMDAttributes>(IRPosition::function(*F)); A.getOrCreateAAFor<AAUniformWorkGroupSize>(IRPosition::function(*F)); A.getOrCreateAAFor<AAAMDMaxNumWorkgroups>(IRPosition::function(*F)); - A.getOrCreateAAFor<AAAMDGPUNoAGPR>(IRPosition::function(*F)); CallingConv::ID CC = F->getCallingConv(); if (!AMDGPU::isEntryFunctionCC(CC)) { A.getOrCreateAAFor<AAAMDFlatWorkGroupSize>(IRPosition::function(*F)); @@ -1515,6 +1514,9 @@ static bool runImpl(Module &M, AnalysisGetter &AG, TargetMachine &TM, if (!F->isDeclaration() && ST.hasClusters()) A.getOrCreateAAFor<AAAMDGPUClusterDims>(IRPosition::function(*F)); + if (ST.hasGFX90AInsts()) + A.getOrCreateAAFor<AAAMDGPUNoAGPR>(IRPosition::function(*F)); + for (auto &I : instructions(F)) { Value *Ptr = nullptr; if (auto *LI = dyn_cast<LoadInst>(&I)) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 280fbe2..723d07e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -929,8 +929,10 @@ void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { ThinOrFullLTOPhase Phase) { if (Level != OptimizationLevel::O0) { if (!isLTOPreLink(Phase)) { - AMDGPUAttributorOptions Opts; - MPM.addPass(AMDGPUAttributorPass(*this, Opts, Phase)); + if (getTargetTriple().isAMDGCN()) { + AMDGPUAttributorOptions Opts; + MPM.addPass(AMDGPUAttributorPass(*this, Opts, Phase)); + } } } }); @@ -1296,7 +1298,8 @@ void AMDGPUPassConfig::addIRPasses() { if (LowerCtorDtor) addPass(createAMDGPUCtorDtorLoweringLegacyPass()); - if (isPassEnabled(EnableImageIntrinsicOptimizer)) + if (TM.getTargetTriple().isAMDGCN() && + isPassEnabled(EnableImageIntrinsicOptimizer)) addPass(createAMDGPUImageIntrinsicOptimizerPass(&TM)); // This can be disabled by passing ::Disable here or on the command line diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td index b2ff5a1..18582ed 100644 --- a/llvm/lib/Target/AMDGPU/DSInstructions.td +++ b/llvm/lib/Target/AMDGPU/DSInstructions.td @@ -951,6 +951,11 @@ class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat (inst $ptr, Offset:$offset, (i1 gds)) >; +class DSReadPat_t16 <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat < + (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))), + (EXTRACT_SUBREG (inst $ptr, Offset:$offset, (i1 gds)), lo16) +>; + multiclass DSReadPat_mc<DS_Pseudo inst, ValueType vt, string frag> { let OtherPredicates = [LDSRequiresM0Init] in { @@ -968,13 +973,14 @@ multiclass DSReadPat_t16<DS_Pseudo inst, ValueType vt, string frag> { def : DSReadPat<inst, vt, !cast<PatFrag>(frag#"_m0")>; } - let OtherPredicates = [NotLDSRequiresM0Init] in { - let True16Predicate = NotUseRealTrue16Insts in { - def : DSReadPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>; - } - let True16Predicate = UseRealTrue16Insts in { - def : DSReadPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_t16"), vt, !cast<PatFrag>(frag)>; - } + let OtherPredicates = [NotLDSRequiresM0Init], True16Predicate = NotUseRealTrue16Insts in { + def : DSReadPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>; + } + let OtherPredicates = [NotLDSRequiresM0Init, D16PreservesUnusedBits], True16Predicate = UseRealTrue16Insts in { + def : DSReadPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_t16"), vt, !cast<PatFrag>(frag)>; + } + let OtherPredicates = [NotLDSRequiresM0Init], True16Predicate = UseTrue16WithSramECC in { + def : DSReadPat_t16<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>; } } diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td index 5a22b23..e86816d 100644 --- a/llvm/lib/Target/AMDGPU/FLATInstructions.td +++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td @@ -1383,6 +1383,11 @@ class FlatLoadPat_D16_t16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType v (inst $vaddr, $offset, (i32 0)) >; +class FlatLoadPat_t16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < + (vt (node (FlatOffset i64:$vaddr, i32:$offset))), + (EXTRACT_SUBREG (inst $vaddr, $offset), lo16) +>; + class FlatSignedLoadPat_D16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < (node (GlobalOffset (i64 VReg_64:$vaddr), i32:$offset), vt:$in), (inst $vaddr, $offset, 0, $in) @@ -1393,6 +1398,11 @@ class FlatSignedLoadPat_D16_t16 <FLAT_Pseudo inst, SDPatternOperator node, Value (inst $vaddr, $offset, (i32 0)) >; +class FlatSignedLoadPat_t16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < + (vt (node (GlobalOffset (i64 VReg_64:$vaddr), i32:$offset))), + (EXTRACT_SUBREG (inst $vaddr, $offset, (i32 0)), lo16) +>; + class GlobalLoadSaddrPat_D16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < (vt (node (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i32:$offset, CPol:$cpol), vt:$in)), (inst $saddr, $voffset, $offset, $cpol, $in) @@ -1408,6 +1418,11 @@ class FlatLoadSaddrPat_D16_t16 <FLAT_Pseudo inst, SDPatternOperator node, ValueT (inst $saddr, $voffset, $offset, $cpol) >; +class FlatLoadSaddrPat_t16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < + (vt (node (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i32:$offset, CPol:$cpol))), + (EXTRACT_SUBREG (inst $saddr, $voffset, $offset, $cpol), lo16) +>; + class FlatLoadLDSSignedPat_M0 <FLAT_Pseudo inst, SDPatternOperator node> : GCNPat < (node (i64 VReg_64:$vaddr), (i32 VGPR_32:$dsaddr), (i32 timm:$offset), (i32 timm:$cpol), M0), (inst $dsaddr, $vaddr, $offset, $cpol) @@ -1443,6 +1458,11 @@ class GlobalLoadSaddrPat_D16_t16 <FLAT_Pseudo inst, SDPatternOperator node, Valu (inst $saddr, $voffset, $offset, $cpol) >; +class GlobalLoadSaddrPat_t16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < + (vt (node (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i32:$offset, CPol:$cpol))), + (EXTRACT_SUBREG (inst $saddr, $voffset, $offset, $cpol), lo16) +>; + class FlatLoadSignedPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < (vt (node (GlobalOffset (i64 VReg_64:$vaddr), i32:$offset))), (inst $vaddr, $offset) @@ -1625,6 +1645,11 @@ class ScratchLoadSignedPat_D16_t16 <FLAT_Pseudo inst, SDPatternOperator node, Va (inst $vaddr, $offset, 0) >; +class ScratchLoadSignedPat_t16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < + (vt (node (ScratchOffset (i32 VGPR_32:$vaddr), i32:$offset))), + (EXTRACT_SUBREG (inst $vaddr, $offset), lo16) +>; + class ScratchStoreSignedPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < (node vt:$data, (ScratchOffset (i32 VGPR_32:$vaddr), i32:$offset)), (inst getVregSrcForVT<vt>.ret:$data, $vaddr, $offset) @@ -1645,6 +1670,11 @@ class ScratchLoadSaddrPat_D16_t16 <FLAT_Pseudo inst, SDPatternOperator node, Val (inst $saddr, $offset, 0) >; +class ScratchLoadSaddrPat_t16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < + (vt (node (ScratchSAddr (i32 SGPR_32:$saddr), i32:$offset))), + (EXTRACT_SUBREG (inst $saddr, $offset), lo16) +>; + class ScratchStoreSaddrPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < (node vt:$data, (ScratchSAddr (i32 SGPR_32:$saddr), i32:$offset)), @@ -1672,6 +1702,11 @@ class ScratchLoadSVaddrPat_D16_t16 <FLAT_Pseudo inst, SDPatternOperator node, Va (inst $vaddr, $saddr, $offset, $cpol) >; +class ScratchLoadSVaddrPat_t16 <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : GCNPat < + (vt (node (ScratchSVAddr (i32 VGPR_32:$vaddr), (i32 SGPR_32:$saddr), i32:$offset, CPol:$cpol))), + (EXTRACT_SUBREG (inst $vaddr, $saddr, $offset, $cpol), lo16) +>; + multiclass GlobalLoadLDSPats_M0<FLAT_Pseudo inst, SDPatternOperator node> { def : FlatLoadLDSSignedPat_M0 <inst, node> { let AddedComplexity = 10; @@ -1764,6 +1799,16 @@ multiclass GlobalFLATLoadPats_D16_t16<string inst, SDPatternOperator node, Value } } +multiclass GlobalFLATLoadPats_t16<FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> { + def : FlatSignedLoadPat_t16<inst, node, vt> { + let AddedComplexity = 10; + } + + def : GlobalLoadSaddrPat_t16<!cast<FLAT_Pseudo>(!cast<string>(inst)#"_SADDR"), node, vt> { + let AddedComplexity = 11; + } +} + multiclass GlobalFLATStorePats<FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> { def : FlatStoreSignedPat <inst, node, vt> { @@ -1872,8 +1917,8 @@ multiclass ScratchFLATStorePats<FLAT_Pseudo inst, SDPatternOperator node, } } -multiclass ScratchFLATStorePats_t16<string inst, SDPatternOperator node, - ValueType vt> { +multiclass ScratchFLATStorePats_D16_t16<string inst, SDPatternOperator node, + ValueType vt> { def : ScratchStoreSignedPat <!cast<FLAT_Pseudo>(inst#"_t16"), node, vt> { let AddedComplexity = 25; } @@ -1918,6 +1963,21 @@ multiclass ScratchFLATLoadPats_D16_t16<string inst, SDPatternOperator node, Valu } } +multiclass ScratchFLATLoadPats_t16<FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> { + def : ScratchLoadSignedPat_t16 <inst, node, vt> { + let AddedComplexity = 25; + } + + def : ScratchLoadSaddrPat_t16<!cast<FLAT_Pseudo>(!cast<string>(inst)#"_SADDR"), node, vt> { + let AddedComplexity = 26; + } + + def : ScratchLoadSVaddrPat_t16<!cast<FLAT_Pseudo>(!cast<string>(inst)#"_SVS"), node, vt> { + let SubtargetPredicate = HasFlatScratchSVSMode; + let AddedComplexity = 27; + } +} + multiclass FlatLoadPats<FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> { def : FlatLoadPat <inst, node, vt> { let OtherPredicates = [HasFlatAddressSpace]; @@ -1947,6 +2007,17 @@ multiclass FlatLoadPats_D16_t16<FLAT_Pseudo inst, SDPatternOperator node, ValueT } } +multiclass FlatLoadPats_t16<FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> { + def : FlatLoadPat_t16 <inst, node, vt> { + let OtherPredicates = [HasFlatAddressSpace]; + } + + def : FlatLoadSaddrPat_t16<!cast<FLAT_Pseudo>(!cast<string>(inst)#"_SADDR"), node, vt> { + let AddedComplexity = 9; + let SubtargetPredicate = HasFlatGVSMode; + } +} + multiclass FlatStorePats<FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> { def : FlatStorePat <inst, node, vt> { let OtherPredicates = [HasFlatAddressSpace]; @@ -1997,6 +2068,17 @@ let True16Predicate = NotUseRealTrue16Insts in { defm : FlatStorePats <FLAT_STORE_SHORT, atomic_store_16_flat, i16>; } +let True16Predicate = UseTrue16WithSramECC in { + defm : FlatLoadPats_t16 <FLAT_LOAD_UBYTE, extloadi8_flat, i16>; + defm : FlatLoadPats_t16 <FLAT_LOAD_UBYTE, zextloadi8_flat, i16>; + defm : FlatLoadPats_t16 <FLAT_LOAD_SBYTE, sextloadi8_flat, i16>; + defm : FlatLoadPats_t16 <FLAT_LOAD_USHORT, load_flat, i16>; + defm : FlatLoadPats_t16 <FLAT_LOAD_UBYTE, atomic_load_aext_8_flat, i16>; + defm : FlatLoadPats_t16 <FLAT_LOAD_UBYTE, atomic_load_zext_8_flat, i16>; + defm : FlatLoadPats_t16 <FLAT_LOAD_USHORT, atomic_load_nonext_16_flat, i16>; + defm : FlatLoadPats_t16 <FLAT_LOAD_SBYTE, atomic_load_sext_8_flat, i16>; +} + let OtherPredicates = [D16PreservesUnusedBits, HasFlatAddressSpace], True16Predicate = UseRealTrue16Insts in { defm : FlatLoadPats_D16_t16<FLAT_LOAD_UBYTE_D16_t16, extloadi8_flat, i16>; defm : FlatLoadPats_D16_t16<FLAT_LOAD_UBYTE_D16_t16, zextloadi8_flat, i16>; @@ -2006,11 +2088,14 @@ let OtherPredicates = [D16PreservesUnusedBits, HasFlatAddressSpace], True16Predi defm : FlatLoadPats_D16_t16<FLAT_LOAD_UBYTE_D16_t16, atomic_load_zext_8_flat, i16>; defm : FlatLoadPats_D16_t16<FLAT_LOAD_SHORT_D16_t16, atomic_load_nonext_16_flat, i16>; defm : FlatLoadPats_D16_t16<FLAT_LOAD_SBYTE_D16_t16, atomic_load_sext_8_flat, i16>; +} // End let OtherPredicates = [D16PreservesUnusedBits, HasFlatAddressSpace], True16Predicate = UseRealTrue16Insts + +let OtherPredicates = [D16PreservesUnusedBits], True16Predicate = UseRealTrue16Insts in { defm : FlatStorePats_t16 <FLAT_STORE_BYTE, truncstorei8_flat, i16>; defm : FlatStorePats_t16 <FLAT_STORE_SHORT, store_flat, i16>; defm : FlatStorePats_t16 <FLAT_STORE_BYTE, atomic_store_8_flat, i16>; defm : FlatStorePats_t16 <FLAT_STORE_SHORT, atomic_store_16_flat, i16>; -} // End let OtherPredicates = [D16PreservesUnusedBits, HasFlatAddressSpace], True16Predicate = UseRealTrue16Insts +} defm : FlatLoadPats <FLAT_LOAD_DWORD, atomic_load_nonext_32_flat, i32>; defm : FlatLoadPats <FLAT_LOAD_DWORDX2, atomic_load_nonext_64_flat, i64>; @@ -2140,6 +2225,20 @@ defm : GlobalFLATLoadPats <GLOBAL_LOAD_USHORT, atomic_load_nonext_16_global, i16 defm : GlobalFLATLoadPats <GLOBAL_LOAD_USHORT, atomic_load_zext_16_global, i16>; } +let True16Predicate = UseTrue16WithSramECC in { +defm : GlobalFLATLoadPats_t16 <GLOBAL_LOAD_UBYTE, extloadi8_global, i16>; +defm : GlobalFLATLoadPats_t16 <GLOBAL_LOAD_UBYTE, zextloadi8_global, i16>; +defm : GlobalFLATLoadPats_t16 <GLOBAL_LOAD_SBYTE, sextloadi8_global, i16>; +defm : GlobalFLATLoadPats_t16 <GLOBAL_LOAD_SSHORT, atomic_load_sext_16_global, i32>; +defm : GlobalFLATLoadPats_t16 <GLOBAL_LOAD_USHORT, atomic_load_zext_16_global, i32>; +defm : GlobalFLATLoadPats_t16 <GLOBAL_LOAD_USHORT, load_global, i16>; +defm : GlobalFLATLoadPats_t16 <GLOBAL_LOAD_UBYTE, atomic_load_aext_8_global, i16>; +defm : GlobalFLATLoadPats_t16 <GLOBAL_LOAD_UBYTE, atomic_load_zext_8_global, i16>; +defm : GlobalFLATLoadPats_t16 <GLOBAL_LOAD_SBYTE, atomic_load_sext_8_global, i16>; +defm : GlobalFLATLoadPats_t16 <GLOBAL_LOAD_USHORT, atomic_load_nonext_16_global, i16>; +defm : GlobalFLATLoadPats_t16 <GLOBAL_LOAD_USHORT, atomic_load_zext_16_global, i16>; +} + let OtherPredicates = [D16PreservesUnusedBits], True16Predicate = UseRealTrue16Insts in { defm : GlobalFLATLoadPats_D16_t16<"GLOBAL_LOAD_UBYTE_D16", extloadi8_global, i16>; defm : GlobalFLATLoadPats_D16_t16<"GLOBAL_LOAD_UBYTE_D16", zextloadi8_global, i16>; @@ -2192,6 +2291,13 @@ defm : GlobalFLATStorePats <GLOBAL_STORE_BYTE, atomic_store_8_global, i16>; defm : GlobalFLATStorePats <GLOBAL_STORE_SHORT, atomic_store_16_global, i16>; } +let OtherPredicates = [HasFlatGlobalInsts], True16Predicate = UseRealTrue16Insts in { +defm : GlobalFLATStorePats_D16_t16 <"GLOBAL_STORE_BYTE", truncstorei8_global, i16>; +defm : GlobalFLATStorePats_D16_t16 <"GLOBAL_STORE_SHORT", store_global, i16>; +defm : GlobalFLATStorePats_D16_t16 <"GLOBAL_STORE_BYTE", atomic_store_8_global, i16>; +defm : GlobalFLATStorePats_D16_t16 <"GLOBAL_STORE_SHORT", atomic_store_16_global, i16>; +} + let OtherPredicates = [HasD16LoadStore] in { defm : GlobalFLATStorePats <GLOBAL_STORE_SHORT_D16_HI, truncstorei16_hi16_global, i32>; defm : GlobalFLATStorePats <GLOBAL_STORE_BYTE_D16_HI, truncstorei8_hi16_global, i32>; @@ -2362,14 +2468,24 @@ defm : ScratchFLATStorePats <SCRATCH_STORE_SHORT, store_private, i16>; defm : ScratchFLATStorePats <SCRATCH_STORE_BYTE, truncstorei8_private, i16>; } -let True16Predicate = UseRealTrue16Insts in { +let True16Predicate = UseTrue16WithSramECC in { +defm : ScratchFLATLoadPats_t16 <SCRATCH_LOAD_UBYTE, extloadi8_private, i16>; +defm : ScratchFLATLoadPats_t16 <SCRATCH_LOAD_UBYTE, zextloadi8_private, i16>; +defm : ScratchFLATLoadPats_t16 <SCRATCH_LOAD_SBYTE, sextloadi8_private, i16>; +defm : ScratchFLATLoadPats_t16 <SCRATCH_LOAD_USHORT, load_private, i16>; +} + +let OtherPredicates = [D16PreservesUnusedBits], True16Predicate = UseRealTrue16Insts in { defm : ScratchFLATLoadPats_D16_t16<"SCRATCH_LOAD_UBYTE_D16", extloadi8_private, i16>; defm : ScratchFLATLoadPats_D16_t16<"SCRATCH_LOAD_UBYTE_D16", zextloadi8_private, i16>; defm : ScratchFLATLoadPats_D16_t16<"SCRATCH_LOAD_SBYTE_D16", sextloadi8_private, i16>; defm : ScratchFLATLoadPats_D16_t16<"SCRATCH_LOAD_SHORT_D16", load_private, i16>; -defm : ScratchFLATStorePats_t16 <"SCRATCH_STORE_SHORT", store_private, i16>; -defm : ScratchFLATStorePats_t16 <"SCRATCH_STORE_BYTE", truncstorei8_private, i16>; -} // End True16Predicate = UseRealTrue16Insts +} // End OtherPredicates = [D16PreservesUnusedBits], True16Predicate = UseRealTrue16Insts + +let True16Predicate = UseRealTrue16Insts in { +defm : ScratchFLATStorePats_D16_t16 <"SCRATCH_STORE_SHORT", store_private, i16>; +defm : ScratchFLATStorePats_D16_t16 <"SCRATCH_STORE_BYTE", truncstorei8_private, i16>; +} foreach vt = Reg32Types.types in { defm : ScratchFLATLoadPats <SCRATCH_LOAD_DWORD, load_private, vt>; diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 2e8a676..ce1cdb3 100644 --- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -232,6 +232,7 @@ getReservedRegs(const MachineFunction &MF) const { markSuperRegs(Reserved, ARM::SP); markSuperRegs(Reserved, ARM::PC); markSuperRegs(Reserved, ARM::FPSCR); + markSuperRegs(Reserved, ARM::FPSCR_RM); markSuperRegs(Reserved, ARM::APSR_NZCV); if (TFI->isFPReserved(MF)) markSuperRegs(Reserved, STI.getFramePointerReg()); diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index f4ac6bb..2a40fb9 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -1353,6 +1353,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_, setOperationAction(ISD::FLOG, MVT::f16, Promote); setOperationAction(ISD::FLOG10, MVT::f16, Promote); setOperationAction(ISD::FLOG2, MVT::f16, Promote); + setOperationAction(ISD::LRINT, MVT::f16, Expand); setOperationAction(ISD::FROUND, MVT::f16, Legal); setOperationAction(ISD::FROUNDEVEN, MVT::f16, Legal); diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td index 31650e0..6771106 100644 --- a/llvm/lib/Target/ARM/ARMInstrVFP.td +++ b/llvm/lib/Target/ARM/ARMInstrVFP.td @@ -435,14 +435,14 @@ def : VFP2MnemonicAlias<"fstmfdx", "fstmdbx">; // FP Binary Operations. // -let TwoOperandAliasConstraint = "$Dn = $Dd" in +let TwoOperandAliasConstraint = "$Dn = $Dd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VADDD : ADbI<0b11100, 0b11, 0, 0, (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm", [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>, Sched<[WriteFPALU64]>; -let TwoOperandAliasConstraint = "$Sn = $Sd" in +let TwoOperandAliasConstraint = "$Sn = $Sd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VADDS : ASbIn<0b11100, 0b11, 0, 0, (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm", @@ -453,21 +453,21 @@ def VADDS : ASbIn<0b11100, 0b11, 0, 0, let D = VFPNeonA8Domain; } -let TwoOperandAliasConstraint = "$Sn = $Sd" in +let TwoOperandAliasConstraint = "$Sn = $Sd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VADDH : AHbI<0b11100, 0b11, 0, 0, (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), IIC_fpALU16, "vadd", ".f16\t$Sd, $Sn, $Sm", [(set (f16 HPR:$Sd), (fadd (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, Sched<[WriteFPALU32]>; -let TwoOperandAliasConstraint = "$Dn = $Dd" in +let TwoOperandAliasConstraint = "$Dn = $Dd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VSUBD : ADbI<0b11100, 0b11, 1, 0, (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm", [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>, Sched<[WriteFPALU64]>; -let TwoOperandAliasConstraint = "$Sn = $Sd" in +let TwoOperandAliasConstraint = "$Sn = $Sd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VSUBS : ASbIn<0b11100, 0b11, 1, 0, (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm", @@ -478,42 +478,42 @@ def VSUBS : ASbIn<0b11100, 0b11, 1, 0, let D = VFPNeonA8Domain; } -let TwoOperandAliasConstraint = "$Sn = $Sd" in +let TwoOperandAliasConstraint = "$Sn = $Sd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VSUBH : AHbI<0b11100, 0b11, 1, 0, (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), IIC_fpALU16, "vsub", ".f16\t$Sd, $Sn, $Sm", [(set (f16 HPR:$Sd), (fsub (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, Sched<[WriteFPALU32]>; -let TwoOperandAliasConstraint = "$Dn = $Dd" in +let TwoOperandAliasConstraint = "$Dn = $Dd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VDIVD : ADbI<0b11101, 0b00, 0, 0, (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm", [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>, Sched<[WriteFPDIV64]>; -let TwoOperandAliasConstraint = "$Sn = $Sd" in +let TwoOperandAliasConstraint = "$Sn = $Sd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VDIVS : ASbI<0b11101, 0b00, 0, 0, (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm", [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>, Sched<[WriteFPDIV32]>; -let TwoOperandAliasConstraint = "$Sn = $Sd" in +let TwoOperandAliasConstraint = "$Sn = $Sd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VDIVH : AHbI<0b11101, 0b00, 0, 0, (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), IIC_fpDIV16, "vdiv", ".f16\t$Sd, $Sn, $Sm", [(set (f16 HPR:$Sd), (fdiv (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, Sched<[WriteFPDIV32]>; -let TwoOperandAliasConstraint = "$Dn = $Dd" in +let TwoOperandAliasConstraint = "$Dn = $Dd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VMULD : ADbI<0b11100, 0b10, 0, 0, (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm", [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>, Sched<[WriteFPMUL64, ReadFPMUL, ReadFPMUL]>; -let TwoOperandAliasConstraint = "$Sn = $Sd" in +let TwoOperandAliasConstraint = "$Sn = $Sd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VMULS : ASbIn<0b11100, 0b10, 0, 0, (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm", @@ -524,21 +524,21 @@ def VMULS : ASbIn<0b11100, 0b10, 0, 0, let D = VFPNeonA8Domain; } -let TwoOperandAliasConstraint = "$Sn = $Sd" in +let TwoOperandAliasConstraint = "$Sn = $Sd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VMULH : AHbI<0b11100, 0b10, 0, 0, (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), IIC_fpMUL16, "vmul", ".f16\t$Sd, $Sn, $Sm", [(set (f16 HPR:$Sd), (fmul (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]>; -let TwoOperandAliasConstraint = "$Dn = $Dd" in +let TwoOperandAliasConstraint = "$Dn = $Dd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VNMULD : ADbI<0b11100, 0b10, 1, 0, (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm", [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>, Sched<[WriteFPMUL64, ReadFPMUL, ReadFPMUL]>; -let TwoOperandAliasConstraint = "$Sn = $Sd" in +let TwoOperandAliasConstraint = "$Sn = $Sd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VNMULS : ASbI<0b11100, 0b10, 1, 0, (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm", @@ -549,7 +549,7 @@ def VNMULS : ASbI<0b11100, 0b10, 1, 0, let D = VFPNeonA8Domain; } -let TwoOperandAliasConstraint = "$Sn = $Sd" in +let TwoOperandAliasConstraint = "$Sn = $Sd", mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VNMULH : AHbI<0b11100, 0b10, 1, 0, (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), IIC_fpMUL16, "vnmul", ".f16\t$Sd, $Sn, $Sm", @@ -589,7 +589,7 @@ defm VSELVS : vsel_inst<"vs", 0b01, 6>; multiclass vmaxmin_inst<string op, bit opc, SDNode SD> { let DecoderNamespace = "VFPV8", PostEncoderMethod = "", - isUnpredicable = 1 in { + isUnpredicable = 1, mayRaiseFPException = 1 in { def H : AHbInp<0b11101, 0b00, opc, (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), NoItinerary, !strconcat(op, ".f16\t$Sd, $Sn, $Sm"), @@ -621,7 +621,7 @@ def : Pat<(fmul (fneg SPR:$a), SPR:$b), (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>; // These are encoded as unary instructions. -let Defs = [FPSCR_NZCV] in { +let Defs = [FPSCR_NZCV], mayRaiseFPException = 1, Uses = [FPSCR_RM] in { def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0, (outs), (ins DPR:$Dd, DPR:$Dm), IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm", "", @@ -684,7 +684,7 @@ def VABSH : AHuI<0b11101, 0b11, 0b0000, 0b11, 0, IIC_fpUNA16, "vabs", ".f16\t$Sd, $Sm", [(set (f16 HPR:$Sd), (fabs (f16 HPR:$Sm)))]>; -let Defs = [FPSCR_NZCV] in { +let Defs = [FPSCR_NZCV], mayRaiseFPException = 1, Uses = [FPSCR_RM] in { def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0, (outs), (ins DPR:$Dd), IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0", "", @@ -742,6 +742,7 @@ def VCMPZH : AHuI<0b11101, 0b11, 0b0101, 0b01, 0, } } // Defs = [FPSCR_NZCV] +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0, (outs DPR:$Dd), (ins SPR:$Sm), IIC_fpCVTDS, "vcvt", ".f64.f32\t$Dd, $Sm", "", @@ -762,6 +763,7 @@ def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0, } // Special case encoding: bits 11-8 is 0b1011. +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm, IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm", "", [(set SPR:$Sd, (fpround DPR:$Dm))]>, @@ -787,7 +789,7 @@ def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm, } // Between half, single and double-precision. -let hasSideEffects = 0 in +let hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm", "", [/* Intentionally left blank, see patterns below */]>, @@ -799,7 +801,7 @@ def : FP16Pat<(f32 (fpextend (f16 HPR:$Sm))), def : FP16Pat<(f16_to_fp GPR:$a), (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>; -let hasSideEffects = 0 in +let hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm), /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm", "$Sd = $Sda", [/* Intentionally left blank, see patterns below */]>, @@ -821,7 +823,7 @@ def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm SPR:$src2), (SSubReg_f16_reg imm:$lane)))>; -let hasSideEffects = 0 in +let hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm", "", [/* Intentionally left blank, see patterns below */]>, @@ -835,7 +837,7 @@ def : FP16Pat<(f32 (fpextend (extractelt (v4f16 DPR:$src), imm_odd:$lane))), (v2f32 (COPY_TO_REGCLASS (v4f16 DPR:$src), DPR_VFP2)), (SSubReg_f16_reg imm_odd:$lane)))>; -let hasSideEffects = 0 in +let hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm), /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", "$Sd = $Sda", [/* Intentionally left blank, see patterns below */]>, @@ -853,6 +855,7 @@ def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm SPR:$src2), (SSubReg_f16_reg imm:$lane)))>; +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs DPR:$Dd), (ins SPR:$Sm), NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm", "", @@ -876,6 +879,7 @@ def : FP16Pat<(f64 (f16_to_fp GPR:$a)), (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>, Requires<[HasFPARMv8, HasDPVFP]>; +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sda, DPR:$Dm), NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm", "$Sd = $Sda", @@ -901,6 +905,7 @@ def : FP16Pat<(fp_to_f16 (f64 DPR:$a)), (i32 (COPY_TO_REGCLASS (VCVTBDH (IMPLICIT_DEF), DPR:$a), GPR))>, Requires<[HasFPARMv8, HasDPVFP]>; +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs DPR:$Dd), (ins SPR:$Sm), NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm", "", @@ -915,6 +920,7 @@ def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0, let hasSideEffects = 0; } +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sda, DPR:$Dm), NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm", "$Sd = $Sda", @@ -934,7 +940,8 @@ def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0, multiclass vcvt_inst<string opc, bits<2> rm, SDPatternOperator node = null_frag> { - let PostEncoderMethod = "", DecoderNamespace = "VFPV8", hasSideEffects = 0 in { + let PostEncoderMethod = "", DecoderNamespace = "VFPV8", hasSideEffects = 0, + mayRaiseFPException = 1 in { def SH : AHuInp<0b11101, 0b11, 0b1100, 0b11, 0, (outs SPR:$Sd), (ins HPR:$Sm), NoItinerary, !strconcat("vcvt", opc, ".s32.f16\t$Sd, $Sm"), @@ -1055,7 +1062,9 @@ def VNEGH : AHuI<0b11101, 0b11, 0b0001, 0b01, 0, IIC_fpUNA16, "vneg", ".f16\t$Sd, $Sm", [(set (f16 HPR:$Sd), (fneg (f16 HPR:$Sm)))]>; -multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> { +multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node, + list<Register> uses = [], bit fpexc = 0> { + let Uses = uses, mayRaiseFPException = fpexc in { def H : AHuI<0b11101, 0b11, 0b0110, 0b11, 0, (outs HPR:$Sd), (ins HPR:$Sm), NoItinerary, !strconcat("vrint", opc), ".f16\t$Sd, $Sm", @@ -1081,6 +1090,7 @@ multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> { let Inst{7} = op2; let Inst{16} = op; } + } def : InstAlias<!strconcat("vrint", opc, "$p.f16.f16\t$Sd, $Sm"), (!cast<Instruction>(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p), 0>, @@ -1093,9 +1103,9 @@ multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> { Requires<[HasFPARMv8,HasDPVFP]>; } -defm VRINTZ : vrint_inst_zrx<"z", 0, 1, ftrunc>; -defm VRINTR : vrint_inst_zrx<"r", 0, 0, fnearbyint>; -defm VRINTX : vrint_inst_zrx<"x", 1, 0, frint>; +defm VRINTZ : vrint_inst_zrx<"z", 0, 1, ftrunc, [], 0>; +defm VRINTR : vrint_inst_zrx<"r", 0, 0, fnearbyint, [FPSCR_RM], 0>; +defm VRINTX : vrint_inst_zrx<"x", 1, 0, frint, [FPSCR_RM], 1>; multiclass vrint_inst_anpm<string opc, bits<2> rm, SDPatternOperator node = null_frag> { @@ -1140,18 +1150,21 @@ defm VRINTN : vrint_inst_anpm<"n", 0b01, froundeven>; defm VRINTP : vrint_inst_anpm<"p", 0b10, fceil>; defm VRINTM : vrint_inst_anpm<"m", 0b11, ffloor>; +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0, (outs DPR:$Dd), (ins DPR:$Dm), IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm", "", [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>, Sched<[WriteFPSQRT64]>; +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm", "", [(set SPR:$Sd, (fsqrt SPR:$Sm))]>, Sched<[WriteFPSQRT32]>; +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VSQRTH : AHuI<0b11101, 0b11, 0b0001, 0b11, 0, (outs HPR:$Sd), (ins HPR:$Sm), IIC_fpSQRT16, "vsqrt", ".f16\t$Sd, $Sm", @@ -1486,6 +1499,7 @@ class AVConv1IHs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, let hasSideEffects = 0; } +let mayRaiseFPException = 1 in def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, (outs DPR:$Dd), (ins SPR:$Sm), IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm", @@ -1502,6 +1516,7 @@ let Predicates=[HasVFP2, HasDPVFP] in { (VSITOD (VLDRS addrmode5:$a))>; } +let mayRaiseFPException = 1 in def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, (outs SPR:$Sd),(ins SPR:$Sm), IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm", @@ -1520,6 +1535,7 @@ def : VFPNoNEONPat<(f32 (sint_to_fp GPR:$a)), def : VFPNoNEONPat<(f32 (sint_to_fp (i32 (alignedload32 addrmode5:$a)))), (VSITOS (VLDRS addrmode5:$a))>; +let mayRaiseFPException = 1 in def VSITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001, (outs HPR:$Sd), (ins SPR:$Sm), IIC_fpCVTIH, "vcvt", ".f16.s32\t$Sd, $Sm", @@ -1532,6 +1548,7 @@ def VSITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001, def : VFPNoNEONPat<(f16 (sint_to_fp GPR:$a)), (VSITOH (COPY_TO_REGCLASS GPR:$a, SPR))>; +let mayRaiseFPException = 1 in def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011, (outs DPR:$Dd), (ins SPR:$Sm), IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm", @@ -1548,6 +1565,7 @@ let Predicates=[HasVFP2, HasDPVFP] in { (VUITOD (VLDRS addrmode5:$a))>; } +let mayRaiseFPException = 1 in def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010, (outs SPR:$Sd), (ins SPR:$Sm), IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm", @@ -1566,6 +1584,7 @@ def : VFPNoNEONPat<(f32 (uint_to_fp GPR:$a)), def : VFPNoNEONPat<(f32 (uint_to_fp (i32 (alignedload32 addrmode5:$a)))), (VUITOS (VLDRS addrmode5:$a))>; +let mayRaiseFPException = 1 in def VUITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001, (outs HPR:$Sd), (ins SPR:$Sm), IIC_fpCVTIH, "vcvt", ".f16.u32\t$Sd, $Sm", @@ -1640,6 +1659,7 @@ class AVConv1IsH_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, } // Always set Z bit in the instruction, i.e. "round towards zero" variants. +let mayRaiseFPException = 1 in def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, (outs SPR:$Sd), (ins DPR:$Dm), IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm", @@ -1660,6 +1680,7 @@ let Predicates=[HasVFP2, HasDPVFP] in { (VSTRS (VTOSIZD DPR:$a), addrmode5:$ptr)>; } +let mayRaiseFPException = 1 in def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010, (outs SPR:$Sd), (ins SPR:$Sm), IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm", @@ -1684,6 +1705,7 @@ def : VFPPat<(alignedstore32 (i32 (fp_to_sint_sat (f32 SPR:$a), i32)), addrmode5:$ptr), (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>; +let mayRaiseFPException = 1 in def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001, (outs SPR:$Sd), (ins HPR:$Sm), IIC_fpCVTHI, "vcvt", ".s32.f16\t$Sd, $Sm", @@ -1698,6 +1720,7 @@ def : VFPNoNEONPat<(i32 (fp_to_sint (f16 HPR:$a))), def : VFPPat<(i32 (fp_to_sint_sat (f16 HPR:$a), i32)), (COPY_TO_REGCLASS (VTOSIZH (f16 HPR:$a)), GPR)>; +let mayRaiseFPException = 1 in def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011, (outs SPR:$Sd), (ins DPR:$Dm), IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm", @@ -1718,6 +1741,7 @@ let Predicates=[HasVFP2, HasDPVFP] in { (VSTRS (VTOUIZD DPR:$a), addrmode5:$ptr)>; } +let mayRaiseFPException = 1 in def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010, (outs SPR:$Sd), (ins SPR:$Sm), IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm", @@ -1742,6 +1766,7 @@ def : VFPPat<(alignedstore32 (i32 (fp_to_uint_sat (f32 SPR:$a), i32)), addrmode5:$ptr), (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>; +let mayRaiseFPException = 1 in def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001, (outs SPR:$Sd), (ins HPR:$Sm), IIC_fpCVTHI, "vcvt", ".u32.f16\t$Sd, $Sm", @@ -1757,7 +1782,7 @@ def : VFPPat<(i32 (fp_to_uint_sat (f16 HPR:$a), i32)), (COPY_TO_REGCLASS (VTOUIZH (f16 HPR:$a)), GPR)>; // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR. -let Uses = [FPSCR] in { +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in { def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, (outs SPR:$Sd), (ins DPR:$Dm), IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm", @@ -1807,7 +1832,7 @@ def VTOUIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001, let Inst{7} = 0; // Z bit let isUnpredicable = 1; } -} +} // mayRaiseFPException = 1, Uses = [FPSCR_RM] // v8.3-a Javascript Convert to Signed fixed-point def VJCVT : AVConv1IsD_Encode<0b11101, 0b11, 0b1001, 0b1011, @@ -1825,7 +1850,7 @@ def VJCVT : AVConv1IsD_Encode<0b11101, 0b11, 0b1001, 0b1011, // S32 (U=0, sx=1) -> SL // U32 (U=1, sx=1) -> UL -let Constraints = "$a = $dst" in { +let Constraints = "$a = $dst", mayRaiseFPException = 1 in { // FP to Fixed-Point: @@ -2026,9 +2051,10 @@ def VULTOD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1011, 0b1011, 1, IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a, $fbits", []>, Sched<[WriteFPCVT]>; -} // End of 'let Constraints = "$a = $dst" in' +} // End of 'let Constraints = "$a = $dst", mayRaiseFPException = 1 in' // BFloat16 - Single precision, unary, predicated +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in class BF16_VCVT<string opc, bits<2> op7_6> : VFPAI<(outs SPR:$Sd), (ins SPR:$dst, SPR:$Sm), VFPUnaryFrm, NoItinerary, @@ -2063,6 +2089,7 @@ def BF16_VCVTT : BF16_VCVT<"vcvtt", 0b11>; // FP Multiply-Accumulate Operations. // +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VMLAD : ADbI<0b11100, 0b00, 0, 0, (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm", @@ -2072,6 +2099,7 @@ def VMLAD : ADbI<0b11100, 0b00, 0, 0, Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>, Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VMLAS : ASbIn<0b11100, 0b00, 0, 0, (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm", @@ -2085,6 +2113,7 @@ def VMLAS : ASbIn<0b11100, 0b00, 0, 0, let D = VFPNeonA8Domain; } +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VMLAH : AHbI<0b11100, 0b00, 0, 0, (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), IIC_fpMAC16, "vmla", ".f16\t$Sd, $Sn, $Sm", @@ -2104,6 +2133,7 @@ def : Pat<(fadd_mlx HPR:$dstin, (fmul_su (f16 HPR:$a), HPR:$b)), Requires<[HasFullFP16,DontUseNEONForFP, UseFPVMLx]>; +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VMLSD : ADbI<0b11100, 0b00, 1, 0, (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm", @@ -2113,6 +2143,7 @@ def VMLSD : ADbI<0b11100, 0b00, 1, 0, Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>, Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VMLSS : ASbIn<0b11100, 0b00, 1, 0, (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm", @@ -2126,6 +2157,7 @@ def VMLSS : ASbIn<0b11100, 0b00, 1, 0, let D = VFPNeonA8Domain; } +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VMLSH : AHbI<0b11100, 0b00, 1, 0, (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), IIC_fpMAC16, "vmls", ".f16\t$Sd, $Sn, $Sm", @@ -2144,6 +2176,7 @@ def : Pat<(fsub_mlx HPR:$dstin, (fmul_su (f16 HPR:$a), HPR:$b)), (VMLSH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>; +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VNMLAD : ADbI<0b11100, 0b01, 1, 0, (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm", @@ -2153,6 +2186,7 @@ def VNMLAD : ADbI<0b11100, 0b01, 1, 0, Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>, Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VNMLAS : ASbI<0b11100, 0b01, 1, 0, (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm", @@ -2166,6 +2200,7 @@ def VNMLAS : ASbI<0b11100, 0b01, 1, 0, let D = VFPNeonA8Domain; } +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VNMLAH : AHbI<0b11100, 0b01, 1, 0, (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), IIC_fpMAC16, "vnmla", ".f16\t$Sd, $Sn, $Sm", @@ -2196,6 +2231,7 @@ def : Pat<(fsub_mlx (fneg HPR:$dstin), (fmul_su (f16 HPR:$a), HPR:$b)), (VNMLAH HPR:$dstin, (f16 HPR:$a), HPR:$b)>, Requires<[HasFullFP16,DontUseNEONForFP,UseFPVMLx]>; +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VNMLSD : ADbI<0b11100, 0b01, 0, 0, (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm", @@ -2205,6 +2241,7 @@ def VNMLSD : ADbI<0b11100, 0b01, 0, 0, Requires<[HasVFP2,HasDPVFP,UseFPVMLx]>, Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VNMLSS : ASbI<0b11100, 0b01, 0, 0, (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm", @@ -2217,6 +2254,7 @@ def VNMLSS : ASbI<0b11100, 0b01, 0, 0, let D = VFPNeonA8Domain; } +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VNMLSH : AHbI<0b11100, 0b01, 0, 0, (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), IIC_fpMAC16, "vnmls", ".f16\t$Sd, $Sn, $Sm", @@ -2237,6 +2275,7 @@ def : Pat<(fsub_mlx (fmul_su (f16 HPR:$a), HPR:$b), HPR:$dstin), //===----------------------------------------------------------------------===// // Fused FP Multiply-Accumulate Operations. // +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VFMAD : ADbI<0b11101, 0b10, 0, 0, (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm", @@ -2246,6 +2285,7 @@ def VFMAD : ADbI<0b11101, 0b10, 0, 0, Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VFMAS : ASbIn<0b11101, 0b10, 0, 0, (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm", @@ -2258,6 +2298,7 @@ def VFMAS : ASbIn<0b11101, 0b10, 0, 0, // VFP pipelines. } +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VFMAH : AHbI<0b11101, 0b10, 0, 0, (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), IIC_fpFMAC16, "vfma", ".f16\t$Sd, $Sn, $Sm", @@ -2289,6 +2330,7 @@ def : Pat<(f16 (fma HPR:$Sn, HPR:$Sm, (f16 HPR:$Sdin))), (VFMAH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, Requires<[HasFullFP16]>; +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VFMSD : ADbI<0b11101, 0b10, 1, 0, (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm", @@ -2298,6 +2340,7 @@ def VFMSD : ADbI<0b11101, 0b10, 1, 0, Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VFMSS : ASbIn<0b11101, 0b10, 1, 0, (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm", @@ -2310,6 +2353,7 @@ def VFMSS : ASbIn<0b11101, 0b10, 1, 0, // VFP pipelines. } +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VFMSH : AHbI<0b11101, 0b10, 1, 0, (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), IIC_fpFMAC16, "vfms", ".f16\t$Sd, $Sn, $Sm", @@ -2341,6 +2385,7 @@ def : Pat<(f16 (fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (f16 HPR:$Sdin))), (VFMSH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, Requires<[HasFullFP16]>; +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VFNMAD : ADbI<0b11101, 0b01, 1, 0, (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm", @@ -2350,6 +2395,7 @@ def VFNMAD : ADbI<0b11101, 0b01, 1, 0, Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VFNMAS : ASbI<0b11101, 0b01, 1, 0, (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm", @@ -2362,6 +2408,7 @@ def VFNMAS : ASbI<0b11101, 0b01, 1, 0, // VFP pipelines. } +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VFNMAH : AHbI<0b11101, 0b01, 1, 0, (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), IIC_fpFMAC16, "vfnma", ".f16\t$Sd, $Sn, $Sm", @@ -2400,6 +2447,7 @@ def : Pat<(f16 (fma (fneg (f16 HPR:$Sn)), (f16 HPR:$Sm), (fneg (f16 HPR:$Sdin))) (VFNMAH (f16 HPR:$Sdin), (f16 HPR:$Sn), (f16 HPR:$Sm))>, Requires<[HasFullFP16]>; +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VFNMSD : ADbI<0b11101, 0b01, 0, 0, (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm), IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm", @@ -2409,6 +2457,7 @@ def VFNMSD : ADbI<0b11101, 0b01, 0, 0, Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>, Sched<[WriteFPMAC64, ReadFPMAC, ReadFPMUL, ReadFPMUL]>; +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VFNMSS : ASbI<0b11101, 0b01, 0, 0, (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm), IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm", @@ -2420,6 +2469,7 @@ def VFNMSS : ASbI<0b11101, 0b01, 0, 0, // VFP pipelines. } +let mayRaiseFPException = 1, Uses = [FPSCR_RM] in def VFNMSH : AHbI<0b11101, 0b01, 0, 0, (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm), IIC_fpFMAC16, "vfnms", ".f16\t$Sd, $Sn, $Sm", diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.td b/llvm/lib/Target/ARM/ARMRegisterInfo.td index 5a31b88..de42195 100644 --- a/llvm/lib/Target/ARM/ARMRegisterInfo.td +++ b/llvm/lib/Target/ARM/ARMRegisterInfo.td @@ -177,8 +177,9 @@ def Q15 : ARMReg<15, "q15", [D30, D31]>; } // Current Program Status Register. -// We model fpscr with two registers: FPSCR models the control bits and will be -// reserved. FPSCR_NZCV models the flag bits and will be unreserved. APSR_NZCV +// We model fpscr with three registers. FPSCR models the control bits and will be +// reserved. FPSCR_RM models rounding mode control bits and will be reserved. +// FPSCR_NZCV models the flag bits and will be unreserved. APSR_NZCV // models the APSR when it's accessed by some special instructions. In such cases // it has the same encoding as PC. def CPSR : ARMReg<0, "cpsr">; @@ -189,6 +190,9 @@ def FPSCR : ARMReg<3, "fpscr">; def FPSCR_NZCV : ARMReg<3, "fpscr_nzcv"> { let Aliases = [FPSCR]; } +def FPSCR_RM : ARMReg<3, "fpscr_rm"> { + let Aliases = [FPSCR]; +} def ITSTATE : ARMReg<4, "itstate">; // Special Registers - only available in privileged mode. diff --git a/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp b/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp index b202b202..e3c39a1 100644 --- a/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp +++ b/llvm/lib/Target/BPF/BPFCheckAndAdjustIR.cpp @@ -26,6 +26,7 @@ #include "llvm/IR/IRBuilder.h" #include "llvm/IR/Instruction.h" #include "llvm/IR/Instructions.h" +#include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/IntrinsicsBPF.h" #include "llvm/IR/Module.h" #include "llvm/IR/Type.h" @@ -478,9 +479,95 @@ static void aspaceWrapOperand(DenseMap<Value *, Value *> &Cache, Instruction *I, } } +static Value *wrapPtrIfASNotZero(DenseMap<Value *, Value *> &Cache, + CallInst *CI, Value *P) { + if (auto *PTy = dyn_cast<PointerType>(P->getType())) { + if (PTy->getAddressSpace() == 0) + return P; + } + return aspaceWrapValue(Cache, CI->getFunction(), P); +} + +static Instruction *aspaceMemSet(Intrinsic::ID ID, + DenseMap<Value *, Value *> &Cache, + CallInst *CI) { + auto *MI = cast<MemIntrinsic>(CI); + IRBuilder<> B(CI); + + Value *OldDst = CI->getArgOperand(0); + Value *NewDst = wrapPtrIfASNotZero(Cache, CI, OldDst); + if (OldDst == NewDst) + return nullptr; + + // memset(new_dst, val, len, align, isvolatile, md) + Value *Val = CI->getArgOperand(1); + Value *Len = CI->getArgOperand(2); + + auto *MS = cast<MemSetInst>(CI); + MaybeAlign Align = MS->getDestAlign(); + bool IsVolatile = MS->isVolatile(); + + if (ID == Intrinsic::memset) + return B.CreateMemSet(NewDst, Val, Len, Align, IsVolatile, + MI->getAAMetadata()); + else + return B.CreateMemSetInline(NewDst, Align, Val, Len, IsVolatile, + MI->getAAMetadata()); +} + +static Instruction *aspaceMemCpy(Intrinsic::ID ID, + DenseMap<Value *, Value *> &Cache, + CallInst *CI) { + auto *MI = cast<MemIntrinsic>(CI); + IRBuilder<> B(CI); + + Value *OldDst = CI->getArgOperand(0); + Value *OldSrc = CI->getArgOperand(1); + Value *NewDst = wrapPtrIfASNotZero(Cache, CI, OldDst); + Value *NewSrc = wrapPtrIfASNotZero(Cache, CI, OldSrc); + if (OldDst == NewDst && OldSrc == NewSrc) + return nullptr; + + // memcpy(new_dst, dst_align, new_src, src_align, len, isvolatile, md) + Value *Len = CI->getArgOperand(2); + + auto *MT = cast<MemTransferInst>(CI); + MaybeAlign DstAlign = MT->getDestAlign(); + MaybeAlign SrcAlign = MT->getSourceAlign(); + bool IsVolatile = MT->isVolatile(); + + return B.CreateMemTransferInst(ID, NewDst, DstAlign, NewSrc, SrcAlign, Len, + IsVolatile, MI->getAAMetadata()); +} + +static Instruction *aspaceMemMove(DenseMap<Value *, Value *> &Cache, + CallInst *CI) { + auto *MI = cast<MemIntrinsic>(CI); + IRBuilder<> B(CI); + + Value *OldDst = CI->getArgOperand(0); + Value *OldSrc = CI->getArgOperand(1); + Value *NewDst = wrapPtrIfASNotZero(Cache, CI, OldDst); + Value *NewSrc = wrapPtrIfASNotZero(Cache, CI, OldSrc); + if (OldDst == NewDst && OldSrc == NewSrc) + return nullptr; + + // memmove(new_dst, dst_align, new_src, src_align, len, isvolatile, md) + Value *Len = CI->getArgOperand(2); + + auto *MT = cast<MemTransferInst>(CI); + MaybeAlign DstAlign = MT->getDestAlign(); + MaybeAlign SrcAlign = MT->getSourceAlign(); + bool IsVolatile = MT->isVolatile(); + + return B.CreateMemMove(NewDst, DstAlign, NewSrc, SrcAlign, Len, IsVolatile, + MI->getAAMetadata()); +} + // Support for BPF address spaces: // - for each function in the module M, update pointer operand of // each memory access instruction (load/store/cmpxchg/atomicrmw) +// or intrinsic call insns (memset/memcpy/memmove) // by casting it from non-zero address space to zero address space, e.g: // // (load (ptr addrspace (N) %p) ...) @@ -493,21 +580,60 @@ bool BPFCheckAndAdjustIR::insertASpaceCasts(Module &M) { for (Function &F : M) { DenseMap<Value *, Value *> CastsCache; for (BasicBlock &BB : F) { - for (Instruction &I : BB) { + for (Instruction &I : llvm::make_early_inc_range(BB)) { unsigned PtrOpNum; - if (auto *LD = dyn_cast<LoadInst>(&I)) + if (auto *LD = dyn_cast<LoadInst>(&I)) { PtrOpNum = LD->getPointerOperandIndex(); - else if (auto *ST = dyn_cast<StoreInst>(&I)) + aspaceWrapOperand(CastsCache, &I, PtrOpNum); + continue; + } + if (auto *ST = dyn_cast<StoreInst>(&I)) { PtrOpNum = ST->getPointerOperandIndex(); - else if (auto *CmpXchg = dyn_cast<AtomicCmpXchgInst>(&I)) + aspaceWrapOperand(CastsCache, &I, PtrOpNum); + continue; + } + if (auto *CmpXchg = dyn_cast<AtomicCmpXchgInst>(&I)) { PtrOpNum = CmpXchg->getPointerOperandIndex(); - else if (auto *RMW = dyn_cast<AtomicRMWInst>(&I)) + aspaceWrapOperand(CastsCache, &I, PtrOpNum); + continue; + } + if (auto *RMW = dyn_cast<AtomicRMWInst>(&I)) { PtrOpNum = RMW->getPointerOperandIndex(); + aspaceWrapOperand(CastsCache, &I, PtrOpNum); + continue; + } + + auto *CI = dyn_cast<CallInst>(&I); + if (!CI) + continue; + + Function *Callee = CI->getCalledFunction(); + if (!Callee || !Callee->isIntrinsic()) + continue; + + // Check memset/memcpy/memmove + Intrinsic::ID ID = Callee->getIntrinsicID(); + bool IsSet = ID == Intrinsic::memset || ID == Intrinsic::memset_inline; + bool IsCpy = ID == Intrinsic::memcpy || ID == Intrinsic::memcpy_inline; + bool IsMove = ID == Intrinsic::memmove; + if (!IsSet && !IsCpy && !IsMove) + continue; + + Instruction *New; + if (IsSet) + New = aspaceMemSet(ID, CastsCache, CI); + else if (IsCpy) + New = aspaceMemCpy(ID, CastsCache, CI); else + New = aspaceMemMove(CastsCache, CI); + + if (!New) continue; - aspaceWrapOperand(CastsCache, &I, PtrOpNum); + I.replaceAllUsesWith(New); + New->takeName(&I); + I.eraseFromParent(); } } Changed |= !CastsCache.empty(); diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp index 71c21e4..186fdd1 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp @@ -736,6 +736,62 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) { MI.eraseFromParent(); return true; } + case TargetOpcode::G_ZEXT: + case TargetOpcode::G_SEXT: { + bool IsSigned = Opc != TargetOpcode::G_ZEXT; + Register DstReg = MI.getOperand(0).getReg(); + Register SrcReg = MI.getOperand(1).getReg(); + LLT SrcTy = MRI->getType(SrcReg); + unsigned SrcSize = SrcTy.getSizeInBits(); + + if (SrcTy.isVector()) + return false; // Should be handled by imported patterns. + + assert((*RBI.getRegBank(DstReg, *MRI, TRI)).getID() == + RISCV::GPRBRegBankID && + "Unexpected ext regbank"); + + // Use addiw SrcReg, 0 (sext.w) for i32. + if (IsSigned && SrcSize == 32) { + MI.setDesc(TII.get(RISCV::ADDIW)); + MI.addOperand(MachineOperand::CreateImm(0)); + return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + } + + // Use add.uw SrcReg, X0 (zext.w) for i32 with Zba. + if (!IsSigned && SrcSize == 32 && STI.hasStdExtZba()) { + MI.setDesc(TII.get(RISCV::ADD_UW)); + MI.addOperand(MachineOperand::CreateReg(RISCV::X0, /*isDef=*/false)); + return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + } + + // Use sext.h/zext.h for i16 with Zbb. + if (SrcSize == 16 && STI.hasStdExtZbb()) { + MI.setDesc(TII.get(IsSigned ? RISCV::SEXT_H + : STI.isRV64() ? RISCV::ZEXT_H_RV64 + : RISCV::ZEXT_H_RV32)); + return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + } + + // Use pack(w) SrcReg, X0 for i16 zext with Zbkb. + if (!IsSigned && SrcSize == 16 && STI.hasStdExtZbkb()) { + MI.setDesc(TII.get(STI.is64Bit() ? RISCV::PACKW : RISCV::PACK)); + MI.addOperand(MachineOperand::CreateReg(RISCV::X0, /*isDef=*/false)); + return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); + } + + // Fall back to shift pair. + auto ShiftLeft = + MIB.buildInstr(RISCV::SLLI, {&RISCV::GPRRegClass}, {SrcReg}) + .addImm(STI.getXLen() - SrcSize); + constrainSelectedInstRegOperands(*ShiftLeft, TII, TRI, RBI); + auto ShiftRight = MIB.buildInstr(IsSigned ? RISCV::SRAI : RISCV::SRLI, + {DstReg}, {ShiftLeft}) + .addImm(STI.getXLen() - SrcSize); + constrainSelectedInstRegOperands(*ShiftRight, TII, TRI, RBI); + MI.eraseFromParent(); + return true; + } case TargetOpcode::G_FCONSTANT: { // TODO: Use constant pool for complex constants. Register DstReg = MI.getOperand(0).getReg(); diff --git a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp index a537904..1c7cbb9 100644 --- a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp +++ b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp @@ -166,7 +166,7 @@ static unsigned getLRForRMW32(AtomicOrdering Ordering, return RISCV::LR_W; return RISCV::LR_W_AQ; case AtomicOrdering::SequentiallyConsistent: - return RISCV::LR_W_AQ_RL; + return RISCV::LR_W_AQRL; } } @@ -210,7 +210,7 @@ static unsigned getLRForRMW64(AtomicOrdering Ordering, return RISCV::LR_D; return RISCV::LR_D_AQ; case AtomicOrdering::SequentiallyConsistent: - return RISCV::LR_D_AQ_RL; + return RISCV::LR_D_AQRL; } } diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 27cf057..40c05e8 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -265,7 +265,7 @@ def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">, def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">; def FeatureStdExtZalasr - : RISCVExperimentalExtension<0, 1, "Load-Acquire and Store-Release Instructions">; + : RISCVExperimentalExtension<0, 9, "Load-Acquire and Store-Release Instructions">; def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">, AssemblerPredicate<(all_of FeatureStdExtZalasr), "'Zalasr' (Load-Acquire and Store-Release Instructions)">; diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td index 6d01250..7dd3385 100644 --- a/llvm/lib/Target/RISCV/RISCVGISel.td +++ b/llvm/lib/Target/RISCV/RISCVGISel.td @@ -133,64 +133,10 @@ def : LdPat<extloadi16, LH, i32>; def : StPat<truncstorei8, SB, GPR, i32>; def : StPat<truncstorei16, SH, GPR, i32>; -def : Pat<(sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>; - def : Pat<(sext_inreg (i64 (add GPR:$rs1, simm12_lo:$imm)), i32), (ADDIW GPR:$rs1, simm12_lo:$imm)>; } -let Predicates = [IsRV64, NoStdExtZba] in -def : Pat<(zext (i32 GPR:$src)), (SRLI (i64 (SLLI GPR:$src, 32)), 32)>; - -let Predicates = [IsRV32, NoStdExtZbb, NoStdExtZbkb] in -def : Pat<(XLenVT (zext (i16 GPR:$src))), - (SRLI (XLenVT (SLLI GPR:$src, 16)), 16)>; - -let Predicates = [IsRV64, NoStdExtZbb, NoStdExtZbkb] in { -def : Pat<(i64 (zext (i16 GPR:$src))), - (SRLI (XLenVT (SLLI GPR:$src, 48)), 48)>; -def : Pat<(i32 (zext (i16 GPR:$src))), - (SRLI (XLenVT (SLLI GPR:$src, 48)), 48)>; -} - -let Predicates = [IsRV32, NoStdExtZbb] in -def : Pat<(XLenVT (sext (i16 GPR:$src))), - (SRAI (XLenVT (SLLI GPR:$src, 16)), 16)>; - -let Predicates = [IsRV64, NoStdExtZbb] in { -def : Pat<(i64 (sext (i16 GPR:$src))), - (SRAI (XLenVT (SLLI GPR:$src, 48)), 48)>; -def : Pat<(i32 (sext (i16 GPR:$src))), - (SRAI (XLenVT (SLLI GPR:$src, 48)), 48)>; -} - -//===----------------------------------------------------------------------===// -// Zb* RV64 patterns not used by SelectionDAG. -//===----------------------------------------------------------------------===// - -let Predicates = [HasStdExtZba, IsRV64] in { -def : Pat<(zext (i32 GPR:$src)), (ADD_UW GPR:$src, (XLenVT X0))>; -} - -let Predicates = [HasStdExtZbb] in -def : Pat<(i32 (sext (i16 GPR:$rs))), (SEXT_H GPR:$rs)>; -let Predicates = [HasStdExtZbb, IsRV64] in -def : Pat<(i64 (sext (i16 GPR:$rs))), (SEXT_H GPR:$rs)>; - -let Predicates = [HasStdExtZbb, IsRV32] in -def : Pat<(i32 (zext (i16 GPR:$rs))), (ZEXT_H_RV32 GPR:$rs)>; -let Predicates = [HasStdExtZbb, IsRV64] in { -def : Pat<(i64 (zext (i16 GPR:$rs))), (ZEXT_H_RV64 GPR:$rs)>; -def : Pat<(i32 (zext (i16 GPR:$rs))), (ZEXT_H_RV64 GPR:$rs)>; -} - -let Predicates = [HasStdExtZbkb, NoStdExtZbb, IsRV32] in -def : Pat<(i32 (zext (i16 GPR:$rs))), (PACK GPR:$rs, (XLenVT X0))>; -let Predicates = [HasStdExtZbkb, NoStdExtZbb, IsRV64] in { -def : Pat<(i64 (zext (i16 GPR:$rs))), (PACKW GPR:$rs, (XLenVT X0))>; -def : Pat<(i32 (zext (i16 GPR:$rs))), (PACKW GPR:$rs, (XLenVT X0))>; -} - //===----------------------------------------------------------------------===// // Zalasr patterns not used by SelectionDAG //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td index 25accd9..2e4326f 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td @@ -24,10 +24,10 @@ class LR_r<bit aq, bit rl, bits<3> funct3, string opcodestr> } multiclass LR_r_aq_rl<bits<3> funct3, string opcodestr> { - def "" : LR_r<0, 0, funct3, opcodestr>; - def _AQ : LR_r<1, 0, funct3, opcodestr # ".aq">; - def _RL : LR_r<0, 1, funct3, opcodestr # ".rl">; - def _AQ_RL : LR_r<1, 1, funct3, opcodestr # ".aqrl">; + def "" : LR_r<0, 0, funct3, opcodestr>; + def _AQ : LR_r<1, 0, funct3, opcodestr # ".aq">; + def _RL : LR_r<0, 1, funct3, opcodestr # ".rl">; + def _AQRL : LR_r<1, 1, funct3, opcodestr # ".aqrl">; } let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in @@ -37,10 +37,10 @@ class SC_r<bit aq, bit rl, bits<3> funct3, string opcodestr> opcodestr, "$rd, $rs2, $rs1">; multiclass SC_r_aq_rl<bits<3> funct3, string opcodestr> { - def "" : SC_r<0, 0, funct3, opcodestr>; - def _AQ : SC_r<1, 0, funct3, opcodestr # ".aq">; - def _RL : SC_r<0, 1, funct3, opcodestr # ".rl">; - def _AQ_RL : SC_r<1, 1, funct3, opcodestr # ".aqrl">; + def "" : SC_r<0, 0, funct3, opcodestr>; + def _AQ : SC_r<1, 0, funct3, opcodestr # ".aq">; + def _RL : SC_r<0, 1, funct3, opcodestr # ".rl">; + def _AQRL : SC_r<1, 1, funct3, opcodestr # ".aqrl">; } let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in @@ -50,10 +50,10 @@ class AMO_rr<bits<5> funct5, bit aq, bit rl, bits<3> funct3, string opcodestr> opcodestr, "$rd, $rs2, $rs1">; multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> { - def "" : AMO_rr<funct5, 0, 0, funct3, opcodestr>; - def _AQ : AMO_rr<funct5, 1, 0, funct3, opcodestr # ".aq">; - def _RL : AMO_rr<funct5, 0, 1, funct3, opcodestr # ".rl">; - def _AQ_RL : AMO_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl">; + def "" : AMO_rr<funct5, 0, 0, funct3, opcodestr>; + def _AQ : AMO_rr<funct5, 1, 0, funct3, opcodestr # ".aq">; + def _RL : AMO_rr<funct5, 0, 1, funct3, opcodestr # ".rl">; + def _AQRL : AMO_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl">; } //===----------------------------------------------------------------------===// @@ -198,9 +198,9 @@ let Predicates = !listconcat([HasStdExtA, NoStdExtZtso], ExtraPreds) in { def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_release"), !cast<RVInst>(BaseInst#"_RL"), vt>; def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_acq_rel"), - !cast<RVInst>(BaseInst#"_AQ_RL"), vt>; + !cast<RVInst>(BaseInst#"_AQRL"), vt>; def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_seq_cst"), - !cast<RVInst>(BaseInst#"_AQ_RL"), vt>; + !cast<RVInst>(BaseInst#"_AQRL"), vt>; } let Predicates = !listconcat([HasStdExtA, HasStdExtZtso], ExtraPreds) in { def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_monotonic"), diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td index 7cf6d5f..c691aa6 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td @@ -9,8 +9,8 @@ // This file describes the RISC-V instructions from the standard atomic 'Za*' // extensions: // - Zawrs (v1.0) : Wait-on-Reservation-Set. -// - Zacas (v1.0-rc1) : Atomic Compare-and-Swap. -// - Zabha (v1.0-rc1) : Byte and Halfword Atomic Memory Operations. +// - Zacas (v1.0) : Atomic Compare-and-Swap. +// - Zabha (v1.0) : Byte and Halfword Atomic Memory Operations. // //===----------------------------------------------------------------------===// @@ -49,10 +49,10 @@ class AMO_cas<bits<5> funct5, bit aq, bit rl, bits<3> funct3, string opcodestr, multiclass AMO_cas_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr, DAGOperand RC> { - def "" : AMO_cas<funct5, 0, 0, funct3, opcodestr, RC>; - def _AQ : AMO_cas<funct5, 1, 0, funct3, opcodestr # ".aq", RC>; - def _RL : AMO_cas<funct5, 0, 1, funct3, opcodestr # ".rl", RC>; - def _AQ_RL : AMO_cas<funct5, 1, 1, funct3, opcodestr # ".aqrl", RC>; + def "" : AMO_cas<funct5, 0, 0, funct3, opcodestr, RC>; + def _AQ : AMO_cas<funct5, 1, 0, funct3, opcodestr # ".aq", RC>; + def _RL : AMO_cas<funct5, 0, 1, funct3, opcodestr # ".rl", RC>; + def _AQRL : AMO_cas<funct5, 1, 1, funct3, opcodestr # ".aqrl", RC>; } let Predicates = [HasStdExtZacas], IsSignExtendingOpW = 1 in { @@ -86,11 +86,11 @@ multiclass AMOCASPat<string AtomicOp, string BaseInst, ValueType vt = XLenVT, def : Pat<(!cast<PatFrag>(AtomicOp#"_acq_rel") (vt GPR:$addr), (vt GPR:$cmp), (vt GPR:$new)), - (!cast<RVInst>(BaseInst#"_AQ_RL") GPR:$cmp, GPR:$addr, GPR:$new)>; + (!cast<RVInst>(BaseInst#"_AQRL") GPR:$cmp, GPR:$addr, GPR:$new)>; def : Pat<(!cast<PatFrag>(AtomicOp#"_seq_cst") (vt GPR:$addr), (vt GPR:$cmp), (vt GPR:$new)), - (!cast<RVInst>(BaseInst#"_AQ_RL") GPR:$cmp, GPR:$addr, GPR:$new)>; + (!cast<RVInst>(BaseInst#"_AQRL") GPR:$cmp, GPR:$addr, GPR:$new)>; } // Predicates = !listconcat([HasStdExtZacas, NoStdExtZtso], ExtraPreds) let Predicates = !listconcat([HasStdExtZacas, HasStdExtZtso], ExtraPreds) in { def : Pat<(!cast<PatFrag>(AtomicOp#"_monotonic") (vt GPR:$addr), @@ -140,7 +140,7 @@ def WRS_STO : WRSInst<0b000000011101, "wrs.sto">, Sched<[]>; // Zabha (Byte and Halfword Atomic Memory Operations) //===----------------------------------------------------------------------===// -let Predicates = [HasStdExtZabha] in { +let Predicates = [HasStdExtZabha], IsSignExtendingOpW = 1 in { defm AMOSWAP_B : AMO_rr_aq_rl<0b00001, 0b000, "amoswap.b">, Sched<[WriteAtomicB, ReadAtomicBA, ReadAtomicBD]>; defm AMOADD_B : AMO_rr_aq_rl<0b00000, 0b000, "amoadd.b">, @@ -181,7 +181,7 @@ defm AMOMAXU_H : AMO_rr_aq_rl<0b11100, 0b001, "amomaxu.h">, } // If Zacas extension is also implemented, Zabha further provides AMOCAS.[B|H]. -let Predicates = [HasStdExtZabha, HasStdExtZacas] in { +let Predicates = [HasStdExtZabha, HasStdExtZacas], IsSignExtendingOpW = 1 in { defm AMOCAS_B : AMO_cas_aq_rl<0b00101, 0b000, "amocas.b", GPR>; defm AMOCAS_H : AMO_cas_aq_rl<0b00101, 0b001, "amocas.h", GPR>; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td index 1deecd2..f7ceb0d 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td @@ -30,21 +30,22 @@ class SRL_r<bit aq, bit rl, bits<3> funct3, string opcodestr> opcodestr, "$rs2, $rs1"> { let rd = 0; } + multiclass LAQ_r_aq_rl<bits<3> funct3, string opcodestr> { - def _AQ : LAQ_r<1, 0, funct3, opcodestr # ".aq">; - def _AQ_RL : LAQ_r<1, 1, funct3, opcodestr # ".aqrl">; + def _AQ : LAQ_r<1, 0, funct3, opcodestr # ".aq">; + def _AQRL : LAQ_r<1, 1, funct3, opcodestr # ".aqrl">; } multiclass SRL_r_aq_rl<bits<3> funct3, string opcodestr> { - def _RL : SRL_r<0, 1, funct3, opcodestr # ".rl">; - def _AQ_RL : SRL_r<1, 1, funct3, opcodestr # ".aqrl">; + def _RL : SRL_r<0, 1, funct3, opcodestr # ".rl">; + def _AQRL : SRL_r<1, 1, funct3, opcodestr # ".aqrl">; } //===----------------------------------------------------------------------===// // Instructions //===----------------------------------------------------------------------===// -let Predicates = [HasStdExtZalasr] in { +let Predicates = [HasStdExtZalasr], IsSignExtendingOpW = 1 in { defm LB : LAQ_r_aq_rl<0b000, "lb">; defm LH : LAQ_r_aq_rl<0b001, "lh">; defm LW : LAQ_r_aq_rl<0b010, "lw">; diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td index 3f2e7db..3e07eff 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -567,9 +567,12 @@ multiclass SiFive7WriteResBase<int VLEN, defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c; defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 8, VLEN>.c; defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c; - defm : LMULWriteResMXVariant<"WriteVLDS8", VLDSX0Pred, [VCQ, VL], - 4, [0, 1], [1, !add(1, VLDSX0Cycles)], !add(3, Cycles), - [0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>; + defm : LMULWriteResMXVariant<"WriteVLDS8", VLDSX0Pred, + // Predicated + [VCQ, VL], 4, [0, 1], [1, !add(1, VLDSX0Cycles)], + // Not Predicated + [VCQ, VL], !add(3, Cycles), [0, 1], [1, !add(1, Cycles)], + mx, IsWorstCase>; let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { defm : LMULWriteResMX<"WriteVLDUX8", [VCQ, VL], mx, IsWorstCase>; defm : LMULWriteResMX<"WriteVLDOX8", [VCQ, VL], mx, IsWorstCase>; @@ -587,9 +590,12 @@ multiclass SiFive7WriteResBase<int VLEN, defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c; defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 16, VLEN>.c; defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c; - defm : LMULWriteResMXVariant<"WriteVLDS16", VLDSX0Pred, [VCQ, VL], - 4, [0, 1], [1, !add(1, VLDSX0Cycles)], !add(3, Cycles), - [0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>; + defm : LMULWriteResMXVariant<"WriteVLDS16", VLDSX0Pred, + // Predicated + [VCQ, VL], 4, [0, 1], [1, !add(1, VLDSX0Cycles)], + // Not Predicated + [VCQ, VL], !add(3, Cycles), [0, 1], [1, !add(1, Cycles)], + mx, IsWorstCase>; let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { defm : LMULWriteResMX<"WriteVLDUX16", [VCQ, VL], mx, IsWorstCase>; defm : LMULWriteResMX<"WriteVLDOX16", [VCQ, VL], mx, IsWorstCase>; @@ -604,9 +610,12 @@ multiclass SiFive7WriteResBase<int VLEN, defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c; defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 32, VLEN>.c; defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c; - defm : LMULWriteResMXVariant<"WriteVLDS32", VLDSX0Pred, [VCQ, VL], - 4, [0, 1], [1, !add(1, VLDSX0Cycles)], !add(3, Cycles), - [0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>; + defm : LMULWriteResMXVariant<"WriteVLDS32", VLDSX0Pred, + // Predicated + [VCQ, VL], 4, [0, 1], [1, !add(1, VLDSX0Cycles)], + // Not Predicated + [VCQ, VL], !add(3, Cycles), [0, 1], [1, !add(1, Cycles)], + mx, IsWorstCase>; let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { defm : LMULWriteResMX<"WriteVLDUX32", [VCQ, VL], mx, IsWorstCase>; defm : LMULWriteResMX<"WriteVLDOX32", [VCQ, VL], mx, IsWorstCase>; @@ -621,9 +630,12 @@ multiclass SiFive7WriteResBase<int VLEN, defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c; defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 64, VLEN>.c; defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c; - defm : LMULWriteResMXVariant<"WriteVLDS64", VLDSX0Pred, [VCQ, VL], - 4, [0, 1], [1, !add(1, VLDSX0Cycles)], !add(3, Cycles), - [0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>; + defm : LMULWriteResMXVariant<"WriteVLDS64", VLDSX0Pred, + // Predicated + [VCQ, VL], 4, [0, 1], [1, !add(1, VLDSX0Cycles)], + // Not Predicated + [VCQ, VL], !add(3, Cycles), [0, 1], [1, !add(1, Cycles)], + mx, IsWorstCase>; let Latency = !add(3, Cycles), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { defm : LMULWriteResMX<"WriteVLDUX64", [VCQ, VL], mx, IsWorstCase>; defm : LMULWriteResMX<"WriteVLDOX64", [VCQ, VL], mx, IsWorstCase>; diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td index 6c7658c..01a4308 100644 --- a/llvm/lib/Target/RISCV/RISCVScheduleV.td +++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td @@ -67,42 +67,41 @@ multiclass LMULSEWWriteResMXSEW<string name, list<ProcResourceKind> resources, // ReleaseAtCycles predCycles if the SchedPredicate Pred is true, otherwise has // Latency noPredLat and ReleaseAtCycles noPredCycles. The WorstCase SchedWrite // is created similarly if IsWorstCase is true. -multiclass LMULWriteResMXVariant<string name, SchedPredicateBase Pred, - list<ProcResourceKind> resources, - int predLat, list<int> predAcquireCycles, - list<int> predReleaseCycles, int noPredLat, - list<int> noPredAcquireCycles, - list<int> noPredReleaseCycles, - string mx, bit IsWorstCase> { - defvar nameMX = name # "_" # mx; - +multiclass LMULWriteResVariantImpl<string name, string writeResName, SchedPredicateBase Pred, + list<ProcResourceKind> predResources, + int predLat, list<int> predAcquireCycles, + list<int> predReleaseCycles, + list<ProcResourceKind> noPredResources, + int noPredLat, list<int> noPredAcquireCycles, + list<int> noPredReleaseCycles, + bit IsWorstCase> { // Define the different behaviors - def nameMX # "_Pred" : SchedWriteRes<resources>{ + def writeResName # "_Pred" : SchedWriteRes<predResources>{ let Latency = predLat; let AcquireAtCycles = predAcquireCycles; let ReleaseAtCycles = predReleaseCycles; } - def nameMX # "_NoPred" : SchedWriteRes<resources> { + def writeResName # "_NoPred" : SchedWriteRes<noPredResources> { let Latency = noPredLat; let AcquireAtCycles = noPredAcquireCycles; let ReleaseAtCycles = noPredReleaseCycles; } // Define SchedVars - def nameMX # PredSchedVar - : SchedVar<Pred, [!cast<SchedWriteRes>(NAME # nameMX # "_Pred")]>; - def nameMX # NoPredSchedVar - : SchedVar<NoSchedPred, [!cast<SchedWriteRes>(NAME # nameMX #"_NoPred")]>; + def writeResName # PredSchedVar + : SchedVar<Pred, [!cast<SchedWriteRes>(NAME # writeResName # "_Pred")]>; + def writeResName # NoPredSchedVar + : SchedVar<NoSchedPred, [!cast<SchedWriteRes>(NAME # writeResName #"_NoPred")]>; // Allow multiclass to refer to SchedVars -- need to have NAME prefix. - defvar PredSchedVar = !cast<SchedVar>(NAME # nameMX # PredSchedVar); - defvar NoPredSchedVar = !cast<SchedVar>(NAME # nameMX # NoPredSchedVar); + defvar PredSchedVar = !cast<SchedVar>(NAME # writeResName # PredSchedVar); + defvar NoPredSchedVar = !cast<SchedVar>(NAME # writeResName # NoPredSchedVar); // Tie behavior to predicate - def NAME # nameMX # "_Variant" + def NAME # writeResName # "_Variant" : SchedWriteVariant<[PredSchedVar, NoPredSchedVar]>; def : SchedAlias< - !cast<SchedReadWrite>(nameMX), - !cast<SchedReadWrite>(NAME # nameMX # "_Variant")>; + !cast<SchedReadWrite>(writeResName), + !cast<SchedReadWrite>(NAME # writeResName # "_Variant")>; if IsWorstCase then { def NAME # name # "_WorstCase_Variant" @@ -113,6 +112,22 @@ multiclass LMULWriteResMXVariant<string name, SchedPredicateBase Pred, } } +multiclass LMULWriteResMXVariant<string name, SchedPredicateBase Pred, + list<ProcResourceKind> predResources, + int predLat, list<int> predAcquireCycles, + list<int> predReleaseCycles, + list<ProcResourceKind> noPredResources, + int noPredLat, list<int> noPredAcquireCycles, + list<int> noPredReleaseCycles, + string mx, bit IsWorstCase> { + defm "" : LMULWriteResVariantImpl<name, name # "_" # mx, Pred, predResources, + predLat, predAcquireCycles, + predReleaseCycles, noPredResources, + noPredLat, noPredAcquireCycles, + noPredReleaseCycles, + IsWorstCase>; +} + // Define multiclasses to define SchedWrite, SchedRead, WriteRes, and // ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the // SchedMxList variants above. Each multiclass is responsible for defining diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp index 163bf9b..6472334 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -3209,7 +3209,8 @@ static SDValue performAnyAllCombine(SDNode *N, SelectionDAG &DAG) { using namespace llvm::SDPatternMatch; SDValue LHS; - if (!sd_match(N->getOperand(1), + if (N->getNumOperands() < 2 || + !sd_match(N->getOperand(1), m_c_SetCC(m_Value(LHS), m_Zero(), m_CondCode()))) return SDValue(); EVT LT = LHS.getValueType(); diff --git a/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp b/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp index ae34b4e..584cdad 100644 --- a/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp +++ b/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp @@ -120,6 +120,9 @@ static cl::opt<unsigned> CostThreshold("dfa-cost-threshold", cl::desc("Maximum cost accepted for the transformation"), cl::Hidden, cl::init(50)); + +extern cl::opt<bool> ProfcheckDisableMetadataFixes; + } // namespace llvm static cl::opt<double> MaxClonedRate( @@ -260,7 +263,11 @@ void DFAJumpThreading::unfold(DomTreeUpdater *DTU, LoopInfo *LI, // Insert the real conditional branch based on the original condition. StartBlockTerm->eraseFromParent(); - BranchInst::Create(EndBlock, NewBlock, SI->getCondition(), StartBlock); + auto *BI = + BranchInst::Create(EndBlock, NewBlock, SI->getCondition(), StartBlock); + if (!ProfcheckDisableMetadataFixes) + BI->setMetadata(LLVMContext::MD_prof, + SI->getMetadata(LLVMContext::MD_prof)); DTU->applyUpdates({{DominatorTree::Insert, StartBlock, EndBlock}, {DominatorTree::Insert, StartBlock, NewBlock}}); } else { @@ -295,7 +302,11 @@ void DFAJumpThreading::unfold(DomTreeUpdater *DTU, LoopInfo *LI, // (Use) BranchInst::Create(EndBlock, NewBlockF); // Insert the real conditional branch based on the original condition. - BranchInst::Create(EndBlock, NewBlockF, SI->getCondition(), NewBlockT); + auto *BI = + BranchInst::Create(EndBlock, NewBlockF, SI->getCondition(), NewBlockT); + if (!ProfcheckDisableMetadataFixes) + BI->setMetadata(LLVMContext::MD_prof, + SI->getMetadata(LLVMContext::MD_prof)); DTU->applyUpdates({{DominatorTree::Insert, NewBlockT, NewBlockF}, {DominatorTree::Insert, NewBlockT, EndBlock}, {DominatorTree::Insert, NewBlockF, EndBlock}}); diff --git a/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp b/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp index c8212af..b36298f 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp @@ -763,6 +763,8 @@ void VPlanTransforms::addMinimumVectorEpilogueIterationCheck( // Add the minimum iteration check for the epilogue vector loop. VPValue *TC = Plan.getOrAddLiveIn(TripCount); VPBuilder Builder(cast<VPBasicBlock>(Plan.getEntry())); + VPValue *VFxUF = Builder.createExpandSCEV(SE.getElementCount( + TripCount->getType(), (EpilogueVF * EpilogueUF), SCEV::FlagNUW)); VPValue *Count = Builder.createNaryOp( Instruction::Sub, {TC, Plan.getOrAddLiveIn(VectorTripCount)}, DebugLoc::getUnknown(), "n.vec.remaining"); @@ -770,9 +772,6 @@ void VPlanTransforms::addMinimumVectorEpilogueIterationCheck( // Generate code to check if the loop's trip count is less than VF * UF of // the vector epilogue loop. auto P = RequiresScalarEpilogue ? ICmpInst::ICMP_ULE : ICmpInst::ICMP_ULT; - VPValue *VFxUF = Builder.createExpandSCEV(SE.getElementCount( - TripCount->getType(), (EpilogueVF * EpilogueUF), SCEV::FlagNUW)); - auto *CheckMinIters = Builder.createICmp( P, Count, VFxUF, DebugLoc::getUnknown(), "min.epilog.iters.check"); VPInstruction *Branch = diff --git a/llvm/test/CodeGen/AArch64/arm64-saddlp1d-uaddlp1d.mir b/llvm/test/CodeGen/AArch64/arm64-saddlp1d-uaddlp1d.mir new file mode 100644 index 0000000..074f75a --- /dev/null +++ b/llvm/test/CodeGen/AArch64/arm64-saddlp1d-uaddlp1d.mir @@ -0,0 +1,50 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: saddlp1d +legalized: true +regBankSelected: false +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $x0 + + ; CHECK-LABEL: name: saddlp1d + ; CHECK: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fpr(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<2 x s32>)) + ; CHECK-NEXT: [[SADDLP:%[0-9]+]]:fpr(s64) = G_SADDLP [[LOAD]] + ; CHECK-NEXT: $d0 = COPY [[SADDLP]](s64) + ; CHECK-NEXT: RET_ReallyLR implicit $d0 + %0:_(p0) = COPY $x0 + %1:_(<2 x s32>) = G_LOAD %0(p0) :: (load (<2 x s32>)) + %2:_(s64) = G_SADDLP %1 + $d0 = COPY %2(s64) + RET_ReallyLR implicit $d0 +... +--- +name: uaddlp1d +legalized: true +regBankSelected: false +failedISel: false +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $x0 + + ; CHECK-LABEL: name: uaddlp1d + ; CHECK: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0 + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fpr(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<2 x s32>)) + ; CHECK-NEXT: [[UADDLP:%[0-9]+]]:fpr(s64) = G_UADDLP [[LOAD]] + ; CHECK-NEXT: $d0 = COPY [[UADDLP]](s64) + ; CHECK-NEXT: RET_ReallyLR implicit $d0 + %0:_(p0) = COPY $x0 + %1:_(<2 x s32>) = G_LOAD %0(p0) :: (load (<2 x s32>)) + %2:_(s64) = G_UADDLP %1 + $d0 = COPY %2(s64) + RET_ReallyLR implicit $d0 +... diff --git a/llvm/test/CodeGen/AArch64/arm64-vadd.ll b/llvm/test/CodeGen/AArch64/arm64-vadd.ll index 938712a..3cf0115 100644 --- a/llvm/test/CodeGen/AArch64/arm64-vadd.ll +++ b/llvm/test/CodeGen/AArch64/arm64-vadd.ll @@ -1,9 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s --check-prefixes=CHECK,CHECK-SD -; RUN: llc < %s -mtriple=arm64-eabi -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI - -; CHECK-GI: warning: Instruction selection used fallback path for saddlp1d -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uaddlp1d +; RUN: llc < %s -mtriple=arm64-eabi -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI define <8 x i8> @addhn8b(ptr %A, ptr %B) nounwind { ; CHECK-LABEL: addhn8b: diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll index 2d7ef2c..98fbbe1 100644 --- a/llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll +++ b/llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll @@ -169,6 +169,6 @@ attributes #1 = { nounwind } ;. ; HSA: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) } -; HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } ;. diff --git a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll index fb566e5..9283bd5 100644 --- a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll +++ b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll @@ -691,29 +691,29 @@ attributes #6 = { "enqueued-block" } ;. ; ATTRIBUTOR_HSA: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -; ATTRIBUTOR_HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } -; ATTRIBUTOR_HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } -; ATTRIBUTOR_HSA: attributes #[[ATTR3]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "target-cpu"="fiji" "uniform-work-group-size"="false" } -; ATTRIBUTOR_HSA: attributes #[[ATTR4]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } -; ATTRIBUTOR_HSA: attributes #[[ATTR5]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } -; ATTRIBUTOR_HSA: attributes #[[ATTR6]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } -; ATTRIBUTOR_HSA: attributes #[[ATTR7]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } -; ATTRIBUTOR_HSA: attributes #[[ATTR8]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } -; ATTRIBUTOR_HSA: attributes #[[ATTR9]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } -; ATTRIBUTOR_HSA: attributes #[[ATTR10]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } -; ATTRIBUTOR_HSA: attributes #[[ATTR11]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } -; ATTRIBUTOR_HSA: attributes #[[ATTR12]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } -; ATTRIBUTOR_HSA: attributes #[[ATTR13]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx900" "uniform-work-group-size"="false" } -; ATTRIBUTOR_HSA: attributes #[[ATTR14]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx900" "uniform-work-group-size"="false" } -; ATTRIBUTOR_HSA: attributes #[[ATTR15:[0-9]+]] = { nounwind "uniform-work-group-size"="false" } -; ATTRIBUTOR_HSA: attributes #[[ATTR16]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; ATTRIBUTOR_HSA: attributes #[[ATTR17]] = { nounwind sanitize_address "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; ATTRIBUTOR_HSA: attributes #[[ATTR18]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; ATTRIBUTOR_HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } +; ATTRIBUTOR_HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } +; ATTRIBUTOR_HSA: attributes #[[ATTR3]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "target-cpu"="fiji" "uniform-work-group-size"="false" } +; ATTRIBUTOR_HSA: attributes #[[ATTR4]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } +; ATTRIBUTOR_HSA: attributes #[[ATTR5]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } +; ATTRIBUTOR_HSA: attributes #[[ATTR6]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } +; ATTRIBUTOR_HSA: attributes #[[ATTR7]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } +; ATTRIBUTOR_HSA: attributes #[[ATTR8]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } +; ATTRIBUTOR_HSA: attributes #[[ATTR9]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } +; ATTRIBUTOR_HSA: attributes #[[ATTR10]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } +; ATTRIBUTOR_HSA: attributes #[[ATTR11]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } +; ATTRIBUTOR_HSA: attributes #[[ATTR12]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } +; ATTRIBUTOR_HSA: attributes #[[ATTR13]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx900" "uniform-work-group-size"="false" } +; ATTRIBUTOR_HSA: attributes #[[ATTR14]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx900" "uniform-work-group-size"="false" } +; ATTRIBUTOR_HSA: attributes #[[ATTR15]] = { nounwind "uniform-work-group-size"="false" } +; ATTRIBUTOR_HSA: attributes #[[ATTR16]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; ATTRIBUTOR_HSA: attributes #[[ATTR17]] = { nounwind sanitize_address "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; ATTRIBUTOR_HSA: attributes #[[ATTR18]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } ; ATTRIBUTOR_HSA: attributes #[[ATTR19:[0-9]+]] = { nounwind sanitize_address "amdgpu-no-implicitarg-ptr" "uniform-work-group-size"="false" } ; ATTRIBUTOR_HSA: attributes #[[ATTR20:[0-9]+]] = { "enqueued-block" "uniform-work-group-size"="false" } -; ATTRIBUTOR_HSA: attributes #[[ATTR21]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "enqueued-block" "uniform-work-group-size"="false" } +; ATTRIBUTOR_HSA: attributes #[[ATTR21]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "enqueued-block" "uniform-work-group-size"="false" } ; ATTRIBUTOR_HSA: attributes #[[ATTR22]] = { "uniform-work-group-size"="false" } -; ATTRIBUTOR_HSA: attributes #[[ATTR23]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; ATTRIBUTOR_HSA: attributes #[[ATTR23]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } ; ATTRIBUTOR_HSA: attributes #[[ATTR24]] = { nounwind } ; ATTRIBUTOR_HSA: attributes #[[ATTR25]] = { "enqueued-block" } ;. diff --git a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll index 484ff77..8554485 100644 --- a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll +++ b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll @@ -474,19 +474,19 @@ attributes #1 = { nounwind } ; AKF_HSA: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 500} ;. ; HSA: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -; HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; HSA: attributes #[[ATTR3]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; HSA: attributes #[[ATTR4]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; HSA: attributes #[[ATTR5]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; HSA: attributes #[[ATTR6]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "uniform-work-group-size"="false" } -; HSA: attributes #[[ATTR7]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; HSA: attributes #[[ATTR8]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" } -; HSA: attributes #[[ATTR9]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" } -; HSA: attributes #[[ATTR10]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; HSA: attributes #[[ATTR11]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; HSA: attributes #[[ATTR12]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; HSA: attributes #[[ATTR13]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; HSA: attributes #[[ATTR3]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; HSA: attributes #[[ATTR4]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; HSA: attributes #[[ATTR5]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; HSA: attributes #[[ATTR6]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "uniform-work-group-size"="false" } +; HSA: attributes #[[ATTR7]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; HSA: attributes #[[ATTR8]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" } +; HSA: attributes #[[ATTR9]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" } +; HSA: attributes #[[ATTR10]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; HSA: attributes #[[ATTR11]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; HSA: attributes #[[ATTR12]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; HSA: attributes #[[ATTR13]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } ;. ; HSA: [[META0]] = !{i32 1, i32 3, i32 4, i32 10} ; HSA: [[META1]] = !{i32 1, i32 5, i32 6, i32 10} diff --git a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features.ll b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features.ll index 2efe024..e2a2deb 100644 --- a/llvm/test/CodeGen/AMDGPU/annotate-kernel-features.ll +++ b/llvm/test/CodeGen/AMDGPU/annotate-kernel-features.ll @@ -294,13 +294,13 @@ attributes #1 = { nounwind } ;. ; CHECK: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -; CHECK: attributes #[[ATTR1]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR2]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR3]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR4]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR5]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR6]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR7]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR8]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR9]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR1]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR2]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR3]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR4]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR5]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR6]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR7]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR8]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR9]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" } ;. diff --git a/llvm/test/CodeGen/AMDGPU/atomic_load_local.ll b/llvm/test/CodeGen/AMDGPU/atomic_load_local.ll index aaedb85..e67d7fdb 100644 --- a/llvm/test/CodeGen/AMDGPU/atomic_load_local.ll +++ b/llvm/test/CodeGen/AMDGPU/atomic_load_local.ll @@ -3,6 +3,8 @@ ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-TRUE16 %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s define i8 @atomic_load_monotonic_i8(ptr addrspace(3) %ptr) { ; CI-LABEL: atomic_load_monotonic_i8: @@ -33,6 +35,14 @@ define i8 @atomic_load_monotonic_i8(ptr addrspace(3) %ptr) { ; GFX11-FAKE16-NEXT: ds_load_u8 v0, v0 ; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: atomic_load_monotonic_i8: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: ds_load_u8 v0, v0 +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %load = load atomic i8, ptr addrspace(3) %ptr monotonic, align 1 ret i8 %load } @@ -66,6 +76,14 @@ define i8 @atomic_load_monotonic_i8_offset(ptr addrspace(3) %ptr) { ; GFX11-FAKE16-NEXT: ds_load_u8 v0, v0 offset:16 ; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: atomic_load_monotonic_i8_offset: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: ds_load_u8 v0, v0 offset:16 +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %gep = getelementptr inbounds i8, ptr addrspace(3) %ptr, i8 16 %load = load atomic i8, ptr addrspace(3) %gep monotonic, align 1 ret i8 %load @@ -100,6 +118,14 @@ define i16 @atomic_load_monotonic_i16(ptr addrspace(3) %ptr) { ; GFX11-FAKE16-NEXT: ds_load_u16 v0, v0 ; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: atomic_load_monotonic_i16: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: ds_load_u16 v0, v0 +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %load = load atomic i16, ptr addrspace(3) %ptr monotonic, align 2 ret i16 %load } @@ -133,6 +159,14 @@ define i16 @atomic_load_monotonic_i16_offset(ptr addrspace(3) %ptr) { ; GFX11-FAKE16-NEXT: ds_load_u16 v0, v0 offset:32 ; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: atomic_load_monotonic_i16_offset: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: ds_load_u16 v0, v0 offset:32 +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %gep = getelementptr inbounds i16, ptr addrspace(3) %ptr, i16 16 %load = load atomic i16, ptr addrspace(3) %gep monotonic, align 2 ret i16 %load @@ -160,6 +194,14 @@ define i32 @atomic_load_monotonic_i32(ptr addrspace(3) %ptr) { ; GFX11-NEXT: ds_load_b32 v0, v0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: atomic_load_monotonic_i32: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: ds_load_b32 v0, v0 +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %load = load atomic i32, ptr addrspace(3) %ptr monotonic, align 4 ret i32 %load } @@ -186,6 +228,14 @@ define i32 @atomic_load_monotonic_i32_offset(ptr addrspace(3) %ptr) { ; GFX11-NEXT: ds_load_b32 v0, v0 offset:64 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: atomic_load_monotonic_i32_offset: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: ds_load_b32 v0, v0 offset:64 +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %gep = getelementptr inbounds i32, ptr addrspace(3) %ptr, i32 16 %load = load atomic i32, ptr addrspace(3) %gep monotonic, align 4 ret i32 %load @@ -213,6 +263,14 @@ define i64 @atomic_load_monotonic_i64(ptr addrspace(3) %ptr) { ; GFX11-NEXT: ds_load_b64 v[0:1], v0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: atomic_load_monotonic_i64: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: ds_load_b64 v[0:1], v0 +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %load = load atomic i64, ptr addrspace(3) %ptr monotonic, align 8 ret i64 %load } @@ -239,6 +297,14 @@ define i64 @atomic_load_monotonic_i64_offset(ptr addrspace(3) %ptr) { ; GFX11-NEXT: ds_load_b64 v[0:1], v0 offset:128 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: atomic_load_monotonic_i64_offset: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: ds_load_b64 v[0:1], v0 offset:128 +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %gep = getelementptr inbounds i64, ptr addrspace(3) %ptr, i32 16 %load = load atomic i64, ptr addrspace(3) %gep monotonic, align 8 ret i64 %load @@ -266,6 +332,14 @@ define float @atomic_load_monotonic_f32_offset(ptr addrspace(3) %ptr) { ; GFX11-NEXT: ds_load_b32 v0, v0 offset:64 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: atomic_load_monotonic_f32_offset: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: ds_load_b32 v0, v0 offset:64 +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %gep = getelementptr inbounds float, ptr addrspace(3) %ptr, i32 16 %load = load atomic float, ptr addrspace(3) %gep monotonic, align 4 ret float %load @@ -293,6 +367,14 @@ define double @atomic_load_monotonic_f64_offset(ptr addrspace(3) %ptr) { ; GFX11-NEXT: ds_load_b64 v[0:1], v0 offset:128 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: atomic_load_monotonic_f64_offset: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: ds_load_b64 v[0:1], v0 offset:128 +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %gep = getelementptr inbounds double, ptr addrspace(3) %ptr, i32 16 %load = load atomic double, ptr addrspace(3) %gep monotonic, align 8 ret double %load @@ -320,6 +402,14 @@ define ptr @atomic_load_monotonic_p0i8_offset(ptr addrspace(3) %ptr) { ; GFX11-NEXT: ds_load_b64 v[0:1], v0 offset:128 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: atomic_load_monotonic_p0i8_offset: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: ds_load_b64 v[0:1], v0 offset:128 +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %gep = getelementptr inbounds ptr, ptr addrspace(3) %ptr, i32 16 %load = load atomic ptr, ptr addrspace(3) %gep monotonic, align 8 ret ptr %load @@ -347,6 +437,14 @@ define ptr addrspace(3) @atomic_load_monotonic_p3i8_offset(ptr addrspace(3) %ptr ; GFX11-NEXT: ds_load_b32 v0, v0 offset:64 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: atomic_load_monotonic_p3i8_offset: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: ds_load_b32 v0, v0 offset:64 +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %gep = getelementptr inbounds ptr addrspace(3), ptr addrspace(3) %ptr, i32 16 %load = load atomic ptr addrspace(3), ptr addrspace(3) %gep monotonic, align 4 ret ptr addrspace(3) %load @@ -381,6 +479,14 @@ define i16 @atomic_load_monotonic_f16(ptr addrspace(3) %ptr) { ; GFX11-FAKE16-NEXT: ds_load_u16 v0, v0 ; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: atomic_load_monotonic_f16: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: ds_load_u16 v0, v0 +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %load = load atomic half, ptr addrspace(3) %ptr monotonic, align 2 %ret = bitcast half %load to i16 ret i16 %ret @@ -415,6 +521,14 @@ define i16 @atomic_load_monotonic_f16_offset(ptr addrspace(3) %ptr) { ; GFX11-FAKE16-NEXT: ds_load_u16 v0, v0 offset:32 ; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: atomic_load_monotonic_f16_offset: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: ds_load_u16 v0, v0 offset:32 +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %gep = getelementptr inbounds half, ptr addrspace(3) %ptr, i32 16 %load = load atomic half, ptr addrspace(3) %gep monotonic, align 2 %ret = bitcast half %load to i16 @@ -450,6 +564,14 @@ define i16 @atomic_load_monotonic_bf16(ptr addrspace(3) %ptr) { ; GFX11-FAKE16-NEXT: ds_load_u16 v0, v0 ; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: atomic_load_monotonic_bf16: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: ds_load_u16 v0, v0 +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %load = load atomic bfloat, ptr addrspace(3) %ptr monotonic, align 2 %ret = bitcast bfloat %load to i16 ret i16 %ret @@ -484,6 +606,14 @@ define i16 @atomic_load_monotonic_bf16_offset(ptr addrspace(3) %ptr) { ; GFX11-FAKE16-NEXT: ds_load_u16 v0, v0 offset:32 ; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: atomic_load_monotonic_bf16_offset: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: ds_load_u16 v0, v0 offset:32 +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %gep = getelementptr inbounds bfloat, ptr addrspace(3) %ptr, i32 16 %load = load atomic bfloat, ptr addrspace(3) %gep monotonic, align 2 %ret = bitcast bfloat %load to i16 @@ -491,3 +621,5 @@ define i16 @atomic_load_monotonic_bf16_offset(ptr addrspace(3) %ptr) { } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GCN: {{.*}} +; GFX1250-FAKE16: {{.*}} +; GFX1250-TRUE16: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/atomic_store_local.ll b/llvm/test/CodeGen/AMDGPU/atomic_store_local.ll index c2bb4f00..31065f2 100644 --- a/llvm/test/CodeGen/AMDGPU/atomic_store_local.ll +++ b/llvm/test/CodeGen/AMDGPU/atomic_store_local.ll @@ -3,6 +3,8 @@ ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-TRUE16 %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s define void @atomic_store_monotonic_i8(ptr addrspace(3) %ptr, i8 %val) { ; CI-LABEL: atomic_store_monotonic_i8: @@ -41,6 +43,26 @@ define void @atomic_store_monotonic_i8(ptr addrspace(3) %ptr, i8 %val) { ; GFX11-FAKE16-NEXT: ds_store_b8 v0, v2 ; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-TRUE16-LABEL: atomic_store_monotonic_i8: +; GFX1250-TRUE16: ; %bb.0: +; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.h, v1.l, 2 +; GFX1250-TRUE16-NEXT: ds_store_b8 v0, v1 +; GFX1250-TRUE16-NEXT: ds_store_b8_d16_hi v0, v1 +; GFX1250-TRUE16-NEXT: s_wait_dscnt 0x0 +; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250-FAKE16-LABEL: atomic_store_monotonic_i8: +; GFX1250-FAKE16: ; %bb.0: +; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-FAKE16-NEXT: v_add_nc_u16 v2, v1, 2 +; GFX1250-FAKE16-NEXT: ds_store_b8 v0, v1 +; GFX1250-FAKE16-NEXT: ds_store_b8 v0, v2 +; GFX1250-FAKE16-NEXT: s_wait_dscnt 0x0 +; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31] %val1 = add i8 %val, 2 store atomic i8 %val, ptr addrspace(3) %ptr monotonic, align 1 store atomic i8 %val1, ptr addrspace(3) %ptr monotonic, align 1 @@ -84,6 +106,26 @@ define void @atomic_store_monotonic_offset_i8(ptr addrspace(3) %ptr, i8 %val) { ; GFX11-FAKE16-NEXT: ds_store_b8 v0, v2 offset:16 ; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-TRUE16-LABEL: atomic_store_monotonic_offset_i8: +; GFX1250-TRUE16: ; %bb.0: +; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.h, v1.l, 2 +; GFX1250-TRUE16-NEXT: ds_store_b8 v0, v1 offset:8 +; GFX1250-TRUE16-NEXT: ds_store_b8_d16_hi v0, v1 offset:16 +; GFX1250-TRUE16-NEXT: s_wait_dscnt 0x0 +; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250-FAKE16-LABEL: atomic_store_monotonic_offset_i8: +; GFX1250-FAKE16: ; %bb.0: +; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-FAKE16-NEXT: v_add_nc_u16 v2, v1, 2 +; GFX1250-FAKE16-NEXT: ds_store_b8 v0, v1 offset:8 +; GFX1250-FAKE16-NEXT: ds_store_b8 v0, v2 offset:16 +; GFX1250-FAKE16-NEXT: s_wait_dscnt 0x0 +; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31] %val1 = add i8 %val, 2 %gep_1 = getelementptr inbounds i8, ptr addrspace(3) %ptr, i8 8 %gep_2 = getelementptr inbounds i8, ptr addrspace(3) %ptr, i8 16 @@ -129,6 +171,26 @@ define void @atomic_store_monotonic_i16(ptr addrspace(3) %ptr, i16 %val) { ; GFX11-FAKE16-NEXT: ds_store_b16 v0, v2 ; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-TRUE16-LABEL: atomic_store_monotonic_i16: +; GFX1250-TRUE16: ; %bb.0: +; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.h, v1.l, 2 +; GFX1250-TRUE16-NEXT: ds_store_b16 v0, v1 +; GFX1250-TRUE16-NEXT: ds_store_b16_d16_hi v0, v1 +; GFX1250-TRUE16-NEXT: s_wait_dscnt 0x0 +; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250-FAKE16-LABEL: atomic_store_monotonic_i16: +; GFX1250-FAKE16: ; %bb.0: +; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-FAKE16-NEXT: v_add_nc_u16 v2, v1, 2 +; GFX1250-FAKE16-NEXT: ds_store_b16 v0, v1 +; GFX1250-FAKE16-NEXT: ds_store_b16 v0, v2 +; GFX1250-FAKE16-NEXT: s_wait_dscnt 0x0 +; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31] %val1 = add i16 %val, 2 store atomic i16 %val, ptr addrspace(3) %ptr monotonic, align 2 store atomic i16 %val1, ptr addrspace(3) %ptr monotonic, align 2 @@ -172,6 +234,26 @@ define void @atomic_store_monotonic_offset_i16(ptr addrspace(3) %ptr, i16 %val) ; GFX11-FAKE16-NEXT: ds_store_b16 v0, v2 offset:32 ; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-TRUE16-LABEL: atomic_store_monotonic_offset_i16: +; GFX1250-TRUE16: ; %bb.0: +; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.h, v1.l, 2 +; GFX1250-TRUE16-NEXT: ds_store_b16 v0, v1 offset:32 +; GFX1250-TRUE16-NEXT: ds_store_b16_d16_hi v0, v1 offset:32 +; GFX1250-TRUE16-NEXT: s_wait_dscnt 0x0 +; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250-FAKE16-LABEL: atomic_store_monotonic_offset_i16: +; GFX1250-FAKE16: ; %bb.0: +; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-FAKE16-NEXT: v_add_nc_u16 v2, v1, 2 +; GFX1250-FAKE16-NEXT: ds_store_b16 v0, v1 offset:32 +; GFX1250-FAKE16-NEXT: ds_store_b16 v0, v2 offset:32 +; GFX1250-FAKE16-NEXT: s_wait_dscnt 0x0 +; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31] %val1 = add i16 %val, 2 %gep = getelementptr inbounds i16, ptr addrspace(3) %ptr, i16 16 store atomic i16 %val, ptr addrspace(3) %gep monotonic, align 2 @@ -201,6 +283,14 @@ define void @atomic_store_monotonic_i32(ptr addrspace(3) %ptr, i32 %val) { ; GFX11-NEXT: ds_store_b32 v0, v1 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: atomic_store_monotonic_i32: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: ds_store_b32 v0, v1 +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] store atomic i32 %val, ptr addrspace(3) %ptr monotonic, align 4 ret void } @@ -227,6 +317,14 @@ define void @atomic_store_monotonic_offset_i32(ptr addrspace(3) %ptr, i32 %val) ; GFX11-NEXT: ds_store_b32 v0, v1 offset:64 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: atomic_store_monotonic_offset_i32: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: ds_store_b32 v0, v1 offset:64 +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %gep = getelementptr inbounds i32, ptr addrspace(3) %ptr, i32 16 store atomic i32 %val, ptr addrspace(3) %gep monotonic, align 4 ret void @@ -254,6 +352,15 @@ define void @atomic_store_monotonic_i64(ptr addrspace(3) %ptr, i64 %val) { ; GFX11-NEXT: ds_store_b64 v0, v[1:2] ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: atomic_store_monotonic_i64: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 +; GFX1250-NEXT: ds_store_b64 v0, v[2:3] +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] store atomic i64 %val, ptr addrspace(3) %ptr monotonic, align 8 ret void } @@ -280,6 +387,15 @@ define void @atomic_store_monotonic_offset_i64(ptr addrspace(3) %ptr, i64 %val) ; GFX11-NEXT: ds_store_b64 v0, v[1:2] offset:128 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: atomic_store_monotonic_offset_i64: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 +; GFX1250-NEXT: ds_store_b64 v0, v[2:3] offset:128 +; GFX1250-NEXT: s_wait_dscnt 0x0 +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %gep = getelementptr inbounds i64, ptr addrspace(3) %ptr, i64 16 store atomic i64 %val, ptr addrspace(3) %gep monotonic, align 8 ret void @@ -322,6 +438,26 @@ define void @atomic_store_monotonic_f16(ptr addrspace(3) %ptr, i16 %arg.val) { ; GFX11-FAKE16-NEXT: ds_store_b16 v0, v2 ; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-TRUE16-LABEL: atomic_store_monotonic_f16: +; GFX1250-TRUE16: ; %bb.0: +; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.h, v1.l, 2 +; GFX1250-TRUE16-NEXT: ds_store_b16 v0, v1 +; GFX1250-TRUE16-NEXT: ds_store_b16_d16_hi v0, v1 +; GFX1250-TRUE16-NEXT: s_wait_dscnt 0x0 +; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250-FAKE16-LABEL: atomic_store_monotonic_f16: +; GFX1250-FAKE16: ; %bb.0: +; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-FAKE16-NEXT: v_add_nc_u16 v2, v1, 2 +; GFX1250-FAKE16-NEXT: ds_store_b16 v0, v1 +; GFX1250-FAKE16-NEXT: ds_store_b16 v0, v2 +; GFX1250-FAKE16-NEXT: s_wait_dscnt 0x0 +; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31] %arg.val1 = add i16 %arg.val, 2 %val = bitcast i16 %arg.val to half %val1 = bitcast i16 %arg.val1 to half @@ -367,6 +503,26 @@ define void @atomic_store_monotonic_offset_f16(ptr addrspace(3) %ptr, i16 %arg.v ; GFX11-FAKE16-NEXT: ds_store_b16 v0, v2 offset:32 ; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-TRUE16-LABEL: atomic_store_monotonic_offset_f16: +; GFX1250-TRUE16: ; %bb.0: +; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.h, v1.l, 2 +; GFX1250-TRUE16-NEXT: ds_store_b16 v0, v1 offset:32 +; GFX1250-TRUE16-NEXT: ds_store_b16_d16_hi v0, v1 offset:32 +; GFX1250-TRUE16-NEXT: s_wait_dscnt 0x0 +; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250-FAKE16-LABEL: atomic_store_monotonic_offset_f16: +; GFX1250-FAKE16: ; %bb.0: +; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-FAKE16-NEXT: v_add_nc_u16 v2, v1, 2 +; GFX1250-FAKE16-NEXT: ds_store_b16 v0, v1 offset:32 +; GFX1250-FAKE16-NEXT: ds_store_b16 v0, v2 offset:32 +; GFX1250-FAKE16-NEXT: s_wait_dscnt 0x0 +; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31] %arg.val1 = add i16 %arg.val, 2 %val1 = bitcast i16 %arg.val1 to half %val = bitcast i16 %arg.val to half @@ -413,6 +569,26 @@ define void @atomic_store_monotonic_bf16(ptr addrspace(3) %ptr, i16 %arg.val) { ; GFX11-FAKE16-NEXT: ds_store_b16 v0, v2 ; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-TRUE16-LABEL: atomic_store_monotonic_bf16: +; GFX1250-TRUE16: ; %bb.0: +; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.h, v1.l, 2 +; GFX1250-TRUE16-NEXT: ds_store_b16 v0, v1 +; GFX1250-TRUE16-NEXT: ds_store_b16_d16_hi v0, v1 +; GFX1250-TRUE16-NEXT: s_wait_dscnt 0x0 +; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250-FAKE16-LABEL: atomic_store_monotonic_bf16: +; GFX1250-FAKE16: ; %bb.0: +; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-FAKE16-NEXT: v_add_nc_u16 v2, v1, 2 +; GFX1250-FAKE16-NEXT: ds_store_b16 v0, v1 +; GFX1250-FAKE16-NEXT: ds_store_b16 v0, v2 +; GFX1250-FAKE16-NEXT: s_wait_dscnt 0x0 +; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31] %arg.val1 = add i16 %arg.val, 2 %val1 = bitcast i16 %arg.val1 to bfloat %val = bitcast i16 %arg.val to bfloat @@ -458,6 +634,26 @@ define void @atomic_store_monotonic_offset_bf16(ptr addrspace(3) %ptr, i16 %arg. ; GFX11-FAKE16-NEXT: ds_store_b16 v0, v2 offset:32 ; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-TRUE16-LABEL: atomic_store_monotonic_offset_bf16: +; GFX1250-TRUE16: ; %bb.0: +; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-TRUE16-NEXT: v_add_nc_u16 v1.h, v1.l, 2 +; GFX1250-TRUE16-NEXT: ds_store_b16 v0, v1 offset:32 +; GFX1250-TRUE16-NEXT: ds_store_b16_d16_hi v0, v1 offset:32 +; GFX1250-TRUE16-NEXT: s_wait_dscnt 0x0 +; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250-FAKE16-LABEL: atomic_store_monotonic_offset_bf16: +; GFX1250-FAKE16: ; %bb.0: +; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-FAKE16-NEXT: v_add_nc_u16 v2, v1, 2 +; GFX1250-FAKE16-NEXT: ds_store_b16 v0, v1 offset:32 +; GFX1250-FAKE16-NEXT: ds_store_b16 v0, v2 offset:32 +; GFX1250-FAKE16-NEXT: s_wait_dscnt 0x0 +; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31] %arg.val1 = add i16 %arg.val, 2 %val1 = bitcast i16 %arg.val1 to bfloat %val = bitcast i16 %arg.val to bfloat diff --git a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll index f63dd6e..c90611f 100644 --- a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll +++ b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior.ll @@ -147,10 +147,10 @@ define amdgpu_kernel void @call_calls_intrin_ascast_cc_kernel(ptr addrspace(3) % attributes #0 = { "amdgpu-no-flat-scratch-init" } ;. -; GFX9: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx900" "uniform-work-group-size"="false" } +; GFX9: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx900" "uniform-work-group-size"="false" } ; GFX9: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx900" } ;. -; GFX10: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx1010" "uniform-work-group-size"="false" } +; GFX10: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx1010" "uniform-work-group-size"="false" } ; GFX10: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx1010" } ;. ; GFX9: [[META0]] = !{i32 1, i32 5, i32 6, i32 10} diff --git a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll index 60cd252..c005695a 100644 --- a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll +++ b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit.ll @@ -723,7 +723,7 @@ define void @also_empty() { define amdgpu_kernel void @indirect_call_known_callees(i1 %cond) { ; GFX9-LABEL: define amdgpu_kernel void @indirect_call_known_callees( -; GFX9-SAME: i1 [[COND:%.*]]) #[[ATTR3:[0-9]+]] { +; GFX9-SAME: i1 [[COND:%.*]]) #[[ATTR0]] { ; GFX9-NEXT: [[FPTR:%.*]] = select i1 [[COND]], ptr @empty, ptr @also_empty ; GFX9-NEXT: [[TMP1:%.*]] = icmp eq ptr [[FPTR]], @also_empty ; GFX9-NEXT: br i1 [[TMP1]], label %[[BB2:.*]], label %[[BB3:.*]] @@ -741,7 +741,7 @@ define amdgpu_kernel void @indirect_call_known_callees(i1 %cond) { ; GFX9-NEXT: ret void ; ; GFX10-LABEL: define amdgpu_kernel void @indirect_call_known_callees( -; GFX10-SAME: i1 [[COND:%.*]]) #[[ATTR3:[0-9]+]] { +; GFX10-SAME: i1 [[COND:%.*]]) #[[ATTR0]] { ; GFX10-NEXT: [[FPTR:%.*]] = select i1 [[COND]], ptr @empty, ptr @also_empty ; GFX10-NEXT: [[TMP1:%.*]] = icmp eq ptr [[FPTR]], @also_empty ; GFX10-NEXT: br i1 [[TMP1]], label %[[BB2:.*]], label %[[BB3:.*]] @@ -767,13 +767,13 @@ declare i32 @llvm.amdgcn.workgroup.id.x() define void @use_intrinsic_workitem_id_x() { ; GFX9-LABEL: define void @use_intrinsic_workitem_id_x( -; GFX9-SAME: ) #[[ATTR5:[0-9]+]] { +; GFX9-SAME: ) #[[ATTR4:[0-9]+]] { ; GFX9-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() ; GFX9-NEXT: store volatile i32 [[VAL]], ptr addrspace(1) null, align 4 ; GFX9-NEXT: ret void ; ; GFX10-LABEL: define void @use_intrinsic_workitem_id_x( -; GFX10-SAME: ) #[[ATTR5:[0-9]+]] { +; GFX10-SAME: ) #[[ATTR4:[0-9]+]] { ; GFX10-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() ; GFX10-NEXT: store volatile i32 [[VAL]], ptr addrspace(1) null, align 4 ; GFX10-NEXT: ret void @@ -803,12 +803,12 @@ define amdgpu_kernel void @use_intrinsic_workitem_id_x_cc_kernel() { define void @call_use_intrinsic_workitem_id_x() { ; GFX9-LABEL: define void @call_use_intrinsic_workitem_id_x( -; GFX9-SAME: ) #[[ATTR5]] { +; GFX9-SAME: ) #[[ATTR4]] { ; GFX9-NEXT: call void @use_intrinsic_workitem_id_x() ; GFX9-NEXT: ret void ; ; GFX10-LABEL: define void @call_use_intrinsic_workitem_id_x( -; GFX10-SAME: ) #[[ATTR5]] { +; GFX10-SAME: ) #[[ATTR4]] { ; GFX10-NEXT: call void @use_intrinsic_workitem_id_x() ; GFX10-NEXT: ret void ; @@ -818,12 +818,12 @@ define void @call_use_intrinsic_workitem_id_x() { define amdgpu_kernel void @call_use_intrinsic_workitem_id_x_cc_kernel() { ; GFX9-LABEL: define amdgpu_kernel void @call_use_intrinsic_workitem_id_x_cc_kernel( -; GFX9-SAME: ) #[[ATTR5]] { +; GFX9-SAME: ) #[[ATTR4]] { ; GFX9-NEXT: call void @use_intrinsic_workitem_id_x() ; GFX9-NEXT: ret void ; ; GFX10-LABEL: define amdgpu_kernel void @call_use_intrinsic_workitem_id_x_cc_kernel( -; GFX10-SAME: ) #[[ATTR5]] { +; GFX10-SAME: ) #[[ATTR4]] { ; GFX10-NEXT: call void @use_intrinsic_workitem_id_x() ; GFX10-NEXT: ret void ; @@ -851,12 +851,12 @@ define amdgpu_kernel void @calls_intrin_ascast_cc_kernel(ptr addrspace(3) %ptr) define amdgpu_kernel void @with_inline_asm() { ; GFX9-LABEL: define amdgpu_kernel void @with_inline_asm( -; GFX9-SAME: ) #[[ATTR3]] { +; GFX9-SAME: ) #[[ATTR0]] { ; GFX9-NEXT: call void asm sideeffect " ; GFX9-NEXT: ret void ; ; GFX10-LABEL: define amdgpu_kernel void @with_inline_asm( -; GFX10-SAME: ) #[[ATTR3]] { +; GFX10-SAME: ) #[[ATTR0]] { ; GFX10-NEXT: call void asm sideeffect " ; GFX10-NEXT: ret void ; @@ -865,19 +865,17 @@ define amdgpu_kernel void @with_inline_asm() { } ;. -; GFX9: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx900" "uniform-work-group-size"="false" } -; GFX9: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx900" "uniform-work-group-size"="false" } +; GFX9: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx900" "uniform-work-group-size"="false" } +; GFX9: attributes #[[ATTR1]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx900" "uniform-work-group-size"="false" } ; GFX9: attributes #[[ATTR2]] = { "target-cpu"="gfx900" "uniform-work-group-size"="false" } -; GFX9: attributes #[[ATTR3]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx900" "uniform-work-group-size"="false" } -; GFX9: attributes #[[ATTR4:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx900" } -; GFX9: attributes #[[ATTR5]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx900" "uniform-work-group-size"="false" } +; GFX9: attributes #[[ATTR3:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx900" } +; GFX9: attributes #[[ATTR4]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx900" "uniform-work-group-size"="false" } ;. -; GFX10: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx1010" "uniform-work-group-size"="false" } -; GFX10: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx1010" "uniform-work-group-size"="false" } +; GFX10: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx1010" "uniform-work-group-size"="false" } +; GFX10: attributes #[[ATTR1]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx1010" "uniform-work-group-size"="false" } ; GFX10: attributes #[[ATTR2]] = { "target-cpu"="gfx1010" "uniform-work-group-size"="false" } -; GFX10: attributes #[[ATTR3]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx1010" "uniform-work-group-size"="false" } -; GFX10: attributes #[[ATTR4:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx1010" } -; GFX10: attributes #[[ATTR5]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx1010" "uniform-work-group-size"="false" } +; GFX10: attributes #[[ATTR3:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx1010" } +; GFX10: attributes #[[ATTR4]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx1010" "uniform-work-group-size"="false" } ;. ; GFX9: [[META0]] = !{i32 2, i32 10} ; GFX9: [[META1]] = !{i32 1, i32 2, i32 3, i32 10} diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll index 6b5647e..4b14dc6 100644 --- a/llvm/test/CodeGen/AMDGPU/bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/bf16.ll @@ -7,11 +7,9 @@ ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 | FileCheck %s -check-prefixes=GFX10 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 | FileCheck %s -check-prefixes=GFX11,GFX11TRUE16 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 | FileCheck %s -check-prefixes=GFX11,GFX11FAKE16 -; xUN: llc < %s -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 | FileCheck %s -check-prefixes=GFX1250,GFX1250TRUE16 +; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 | FileCheck %s -check-prefixes=GFX1250,GFX1250TRUE16 ; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 | FileCheck %s -check-prefixes=GFX1250,GFX1250FAKE16 -; FIXME: real-true16 version of gfx1250 test fails - define void @test_load_store(ptr addrspace(1) %in, ptr addrspace(1) %out) { ; GCN-LABEL: test_load_store: ; GCN: ; %bb.0: @@ -2393,15 +2391,25 @@ define void @test_store_fpimm(ptr addrspace(1) %ptr0, ptr addrspace(1) %ptr1) { ; GFX11FAKE16-NEXT: global_store_b16 v[2:3], v5, off ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: test_store_fpimm: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_mov_b32_e32 v4, 0x3f80 -; GFX1250-NEXT: v_mov_b32_e32 v5, 0x4228 -; GFX1250-NEXT: global_store_b16 v[0:1], v4, off -; GFX1250-NEXT: global_store_b16 v[2:3], v5, off -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: test_store_fpimm: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v4.l, 0x3f80 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v4.h, 0x4228 +; GFX1250TRUE16-NEXT: global_store_b16 v[0:1], v4, off +; GFX1250TRUE16-NEXT: global_store_d16_hi_b16 v[2:3], v4, off +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: test_store_fpimm: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_mov_b32_e32 v4, 0x3f80 +; GFX1250FAKE16-NEXT: v_mov_b32_e32 v5, 0x4228 +; GFX1250FAKE16-NEXT: global_store_b16 v[0:1], v4, off +; GFX1250FAKE16-NEXT: global_store_b16 v[2:3], v5, off +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] store bfloat 1.0, ptr addrspace(1) %ptr0 store bfloat 42.0, ptr addrspace(1) %ptr1 ret void @@ -3796,13 +3804,21 @@ define amdgpu_gfx void @test_inreg_arg_store(bfloat inreg %in, ptr addrspace(1) ; GFX11FAKE16-NEXT: global_store_b16 v[0:1], v2, off ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: test_inreg_arg_store: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_mov_b32_e32 v2, s4 -; GFX1250-NEXT: global_store_b16 v[0:1], v2, off -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: test_inreg_arg_store: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, s4 +; GFX1250TRUE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: test_inreg_arg_store: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_mov_b32_e32 v2, s4 +; GFX1250FAKE16-NEXT: global_store_b16 v[0:1], v2, off +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] store bfloat %in, ptr addrspace(1) %out ret void } @@ -3866,12 +3882,20 @@ define bfloat @test_byval(ptr addrspace(5) byval(bfloat) %bv, bfloat %val) { ; GFX11FAKE16-NEXT: scratch_store_b16 off, v0, s32 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: test_byval: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: scratch_store_b16 off, v0, s32 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: test_byval: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l +; GFX1250TRUE16-NEXT: scratch_store_b16 off, v1, s32 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: test_byval: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: scratch_store_b16 off, v0, s32 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] store bfloat %val, ptr addrspace(5) %bv %retval = load bfloat, ptr addrspace(5) %bv ret bfloat %retval @@ -6708,27 +6732,50 @@ define { <32 x i32>, bfloat } @test_overflow_stack(bfloat %a, <32 x i32> %b) { ; GFX11FAKE16-NEXT: scratch_store_b16 v0, v1, off offset:128 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: test_overflow_stack: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: s_clause 0x2 -; GFX1250-NEXT: scratch_load_b32 v33, off, s32 offset:8 -; GFX1250-NEXT: scratch_load_b32 v32, off, s32 offset:4 -; GFX1250-NEXT: scratch_load_b32 v31, off, s32 -; GFX1250-NEXT: s_clause 0x5 -; GFX1250-NEXT: scratch_store_b128 v0, v[22:25], off offset:80 -; GFX1250-NEXT: scratch_store_b128 v0, v[18:21], off offset:64 -; GFX1250-NEXT: scratch_store_b128 v0, v[14:17], off offset:48 -; GFX1250-NEXT: scratch_store_b128 v0, v[10:13], off offset:32 -; GFX1250-NEXT: scratch_store_b128 v0, v[6:9], off offset:16 -; GFX1250-NEXT: scratch_store_b128 v0, v[2:5], off -; GFX1250-NEXT: s_wait_loadcnt 0x0 -; GFX1250-NEXT: s_clause 0x2 -; GFX1250-NEXT: scratch_store_b128 v0, v[30:33], off offset:112 -; GFX1250-NEXT: scratch_store_b128 v0, v[26:29], off offset:96 -; GFX1250-NEXT: scratch_store_b16 v0, v1, off offset:128 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: test_overflow_stack: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: s_clause 0x2 +; GFX1250TRUE16-NEXT: scratch_load_b32 v33, off, s32 offset:8 +; GFX1250TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:4 +; GFX1250TRUE16-NEXT: scratch_load_b32 v31, off, s32 +; GFX1250TRUE16-NEXT: s_clause 0x3 +; GFX1250TRUE16-NEXT: scratch_store_b128 v0, v[22:25], off offset:80 +; GFX1250TRUE16-NEXT: scratch_store_b128 v0, v[18:21], off offset:64 +; GFX1250TRUE16-NEXT: scratch_store_b128 v0, v[14:17], off offset:48 +; GFX1250TRUE16-NEXT: scratch_store_b128 v0, v[10:13], off offset:32 +; GFX1250TRUE16-NEXT: s_clause 0x1 +; GFX1250TRUE16-NEXT: scratch_store_b128 v0, v[6:9], off offset:16 +; GFX1250TRUE16-NEXT: scratch_store_b128 v0, v[2:5], off +; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250TRUE16-NEXT: s_clause 0x2 +; GFX1250TRUE16-NEXT: scratch_store_b128 v0, v[30:33], off offset:112 +; GFX1250TRUE16-NEXT: scratch_store_b128 v0, v[26:29], off offset:96 +; GFX1250TRUE16-NEXT: scratch_store_b16 v0, v1, off offset:128 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: test_overflow_stack: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: s_clause 0x2 +; GFX1250FAKE16-NEXT: scratch_load_b32 v33, off, s32 offset:8 +; GFX1250FAKE16-NEXT: scratch_load_b32 v32, off, s32 offset:4 +; GFX1250FAKE16-NEXT: scratch_load_b32 v31, off, s32 +; GFX1250FAKE16-NEXT: s_clause 0x5 +; GFX1250FAKE16-NEXT: scratch_store_b128 v0, v[22:25], off offset:80 +; GFX1250FAKE16-NEXT: scratch_store_b128 v0, v[18:21], off offset:64 +; GFX1250FAKE16-NEXT: scratch_store_b128 v0, v[14:17], off offset:48 +; GFX1250FAKE16-NEXT: scratch_store_b128 v0, v[10:13], off offset:32 +; GFX1250FAKE16-NEXT: scratch_store_b128 v0, v[6:9], off offset:16 +; GFX1250FAKE16-NEXT: scratch_store_b128 v0, v[2:5], off +; GFX1250FAKE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250FAKE16-NEXT: s_clause 0x2 +; GFX1250FAKE16-NEXT: scratch_store_b128 v0, v[30:33], off offset:112 +; GFX1250FAKE16-NEXT: scratch_store_b128 v0, v[26:29], off offset:96 +; GFX1250FAKE16-NEXT: scratch_store_b16 v0, v1, off offset:128 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %ins.0 = insertvalue { <32 x i32>, bfloat } poison, <32 x i32> %b, 0 %ins.1 = insertvalue { <32 x i32>, bfloat } %ins.0 ,bfloat %a, 1 ret { <32 x i32>, bfloat } %ins.1 @@ -10726,15 +10773,29 @@ define bfloat @v_fadd_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fadd_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_add_f32_e32 v0, v0, v1 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fadd_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX1250TRUE16-NEXT: v_add_f32_e32 v0, v1, v2 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fadd_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fadd bfloat %a, %b ret bfloat %op } @@ -15268,15 +15329,26 @@ define bfloat @v_fadd_bf16_fpimm_0(bfloat %arg0) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fadd_bf16_fpimm_0: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_add_f32_e32 v0, 1.0, v0 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fadd_bf16_fpimm_0: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_add_f32_e32 v0, 1.0, v1 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fadd_bf16_fpimm_0: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_add_f32_e32 v0, 1.0, v0 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %add = fadd bfloat %arg0, 1.0 ret bfloat %add } @@ -15382,15 +15454,26 @@ define bfloat @v_fadd_bf16_fpimm_1(bfloat %arg0) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fadd_bf16_fpimm_1: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_add_f32_e32 v0, 0x42280000, v0 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fadd_bf16_fpimm_1: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_add_f32_e32 v0, 0x42280000, v1 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fadd_bf16_fpimm_1: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_add_f32_e32 v0, 0x42280000, v0 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %add = fadd bfloat %arg0, 42.0 ret bfloat %add } @@ -15507,15 +15590,29 @@ define bfloat @v_fsub_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fsub_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fsub_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX1250TRUE16-NEXT: v_sub_f32_e32 v0, v1, v2 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fsub_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fsub bfloat %a, %b ret bfloat %op } @@ -15931,21 +16028,37 @@ define <3 x bfloat> @v_fsub_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) { ; GFX11FAKE16-NEXT: v_alignbit_b32 v1, s0, v1, 16 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fsub_v3bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GFX1250-NEXT: v_and_b32_e32 v4, 0xffff0000, v2 -; GFX1250-NEXT: v_and_b32_e32 v5, 0xffff0000, v0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v2, 16, v2 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_dual_sub_f32 v4, v5, v4 :: v_dual_lshlrev_b32 v1, 16, v1 -; GFX1250-NEXT: v_dual_sub_f32 v0, v0, v2 :: v_dual_sub_f32 v1, v1, v3 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, v4 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fsub_v3bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_dual_lshlrev_b32 v3, 16, v3 :: v_dual_lshlrev_b32 v1, 16, v1 +; GFX1250TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2 +; GFX1250TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0 +; GFX1250TRUE16-NEXT: v_dual_lshlrev_b32 v2, 16, v2 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_sub_f32_e32 v1, v1, v3 +; GFX1250TRUE16-NEXT: v_dual_sub_f32 v3, v5, v4 :: v_dual_sub_f32 v0, v0, v2 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v3 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fsub_v3bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v2, 16, v2 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_dual_sub_f32 v4, v5, v4 :: v_dual_lshlrev_b32 v1, 16, v1 +; GFX1250FAKE16-NEXT: v_dual_sub_f32 v0, v0, v2 :: v_dual_sub_f32 v1, v1, v3 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v4 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fsub <3 x bfloat> %a, %b ret <3 x bfloat> %op } @@ -16371,12 +16484,26 @@ define bfloat @v_fmul_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fmul_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_fma_mixlo_bf16 v0, v0, v1, 0 op_sel_hi:[1,1,0] -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fmul_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX1250TRUE16-NEXT: v_mul_f32_e32 v0, v1, v2 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fmul_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, 0 op_sel_hi:[1,1,0] +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fmul bfloat %a, %b ret bfloat %op } @@ -21012,31 +21139,60 @@ define bfloat @v_fdiv_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fdiv_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_div_scale_f32 v2, null, v1, v1, v0 -; GFX1250-NEXT: v_rcp_f32_e32 v3, v2 -; GFX1250-NEXT: v_nop -; GFX1250-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_fma_f32 v4, -v2, v3, 1.0 -; GFX1250-NEXT: v_fmac_f32_e32 v3, v4, v3 -; GFX1250-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_mul_f32_e32 v5, v4, v3 -; GFX1250-NEXT: v_fma_f32 v6, -v2, v5, v4 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_fmac_f32_e32 v5, v6, v3 -; GFX1250-NEXT: v_fma_f32 v2, -v2, v5, v4 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_div_fmas_f32 v2, v2, v3, v5 -; GFX1250-NEXT: v_div_fixup_f32 v0, v2, v1, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fdiv_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l +; GFX1250TRUE16-NEXT: v_div_scale_f32 v1, null, v0, v0, v2 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1) +; GFX1250TRUE16-NEXT: v_rcp_f32_e32 v3, v1 +; GFX1250TRUE16-NEXT: v_nop +; GFX1250TRUE16-NEXT: v_fma_f32 v4, -v1, v3, 1.0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_fmac_f32_e32 v3, v4, v3 +; GFX1250TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, v2, v0, v2 +; GFX1250TRUE16-NEXT: v_mul_f32_e32 v5, v4, v3 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_fma_f32 v6, -v1, v5, v4 +; GFX1250TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v3 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_fma_f32 v1, -v1, v5, v4 +; GFX1250TRUE16-NEXT: v_div_fmas_f32 v1, v1, v3, v5 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_div_fixup_f32 v0, v1, v0, v2 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fdiv_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_div_scale_f32 v2, null, v1, v1, v0 +; GFX1250FAKE16-NEXT: v_rcp_f32_e32 v3, v2 +; GFX1250FAKE16-NEXT: v_nop +; GFX1250FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_fma_f32 v4, -v2, v3, 1.0 +; GFX1250FAKE16-NEXT: v_fmac_f32_e32 v3, v4, v3 +; GFX1250FAKE16-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_mul_f32_e32 v5, v4, v3 +; GFX1250FAKE16-NEXT: v_fma_f32 v6, -v2, v5, v4 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_fmac_f32_e32 v5, v6, v3 +; GFX1250FAKE16-NEXT: v_fma_f32 v2, -v2, v5, v4 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_div_fmas_f32 v2, v2, v3, v5 +; GFX1250FAKE16-NEXT: v_div_fixup_f32 v0, v2, v1, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fdiv bfloat %a, %b ret bfloat %op } @@ -21092,12 +21248,19 @@ define bfloat @v_fabs_bf16(bfloat %a) { ; GFX11FAKE16-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fabs_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_and_b32_e32 v0, 0x7fff, v0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fabs_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fabs_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v0, 0x7fff, v0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.fabs.bf16(bfloat %a) ret bfloat %op } @@ -21198,12 +21361,19 @@ define bfloat @v_fneg_bf16(bfloat %a) { ; GFX11FAKE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fneg_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_xor_b32_e32 v0, 0x8000, v0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fneg_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fneg_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fneg bfloat %a ret bfloat %op } @@ -21317,12 +21487,19 @@ define bfloat @v_fneg_fabs_bf16(bfloat %a) { ; GFX11FAKE16-NEXT: v_or_b32_e32 v0, 0x8000, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fneg_fabs_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_or_b32_e32 v0, 0x8000, v0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fneg_fabs_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v0.l +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fneg_fabs_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_or_b32_e32 v0, 0x8000, v0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %fabs = call bfloat @llvm.fabs.bf16(bfloat %a) %op = fneg bfloat %fabs ret bfloat %op @@ -21511,15 +21688,29 @@ define bfloat @v_minnum_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_minnum_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_min_num_f32_e32 v0, v0, v1 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_minnum_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX1250TRUE16-NEXT: v_min_num_f32_e32 v0, v1, v2 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_minnum_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_min_num_f32_e32 v0, v0, v1 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.minnum.bf16(bfloat %a, bfloat %b) ret bfloat %op } @@ -26073,15 +26264,29 @@ define bfloat @v_maxnum_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_maxnum_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_max_num_f32_e32 v0, v0, v1 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_maxnum_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX1250TRUE16-NEXT: v_max_num_f32_e32 v0, v1, v2 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_maxnum_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_max_num_f32_e32 v0, v0, v1 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.maxnum.bf16(bfloat %a, bfloat %b) ret bfloat %op } @@ -30764,12 +30969,19 @@ define bfloat @v_sqrt_bf16(bfloat %a) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_sqrt_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_sqrt_bf16_e32 v0, v0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_sqrt_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_sqrt_bf16_e32 v0.l, v0.l +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_sqrt_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_sqrt_bf16_e32 v0, v0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.sqrt.bf16(bfloat %a) ret bfloat %op } @@ -30877,15 +31089,26 @@ define bfloat @v_ldexp_bf16_i32(bfloat %a, i32 %b) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_ldexp_bf16_i32: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_ldexp_f32 v0, v0, v1 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_ldexp_bf16_i32: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_ldexp_f32 v0, v2, v1 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_ldexp_bf16_i32: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.ldexp.bf16.i32(bfloat %a, i32 %b) ret bfloat %op } @@ -31005,16 +31228,28 @@ define { bfloat, i16 } @v_frexp_bf16_i16(bfloat %a) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_frexp_bf16_i16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v1, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_frexp_mant_f32_e32 v0, v1 -; GFX1250-NEXT: v_frexp_exp_i32_f32_e32 v1, v1 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_frexp_bf16_i16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_frexp_mant_f32_e32 v0, v1 +; GFX1250TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v1, v1 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_frexp_bf16_i16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_frexp_mant_f32_e32 v0, v1 +; GFX1250FAKE16-NEXT: v_frexp_exp_i32_f32_e32 v1, v1 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call { bfloat, i16 } @llvm.frexp.bf16.i16(bfloat %a) ret { bfloat, i16 } %op } @@ -31254,31 +31489,58 @@ define bfloat @v_log_bf16(bfloat %a) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_log_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo -; GFX1250-NEXT: v_ldexp_f32 v0, v0, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1) -; GFX1250-NEXT: v_log_f32_e32 v0, v0 -; GFX1250-NEXT: v_nop -; GFX1250-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0 -; GFX1250-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0| -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1 -; GFX1250-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_add_f32_e32 v1, v1, v2 -; GFX1250-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0 -; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_log_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v1 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 32, vcc_lo +; GFX1250TRUE16-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1) +; GFX1250TRUE16-NEXT: v_log_f32_e32 v0, v0 +; GFX1250TRUE16-NEXT: v_nop +; GFX1250TRUE16-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0 +; GFX1250TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0| +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1 +; GFX1250TRUE16-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_add_f32_e32 v1, v1, v2 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_log_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo +; GFX1250FAKE16-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1) +; GFX1250FAKE16-NEXT: v_log_f32_e32 v0, v0 +; GFX1250FAKE16-NEXT: v_nop +; GFX1250FAKE16-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0 +; GFX1250FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0| +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1 +; GFX1250FAKE16-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_add_f32_e32 v1, v1, v2 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.log.bf16(bfloat %a) ret bfloat %op } @@ -31439,12 +31701,19 @@ define bfloat @v_log2_bf16(bfloat %a) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_log2_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_log_bf16_e32 v0, v0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_log2_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_log_bf16_e32 v0.l, v0.l +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_log2_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_log_bf16_e32 v0, v0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.log2.bf16(bfloat %a) ret bfloat %op } @@ -31679,31 +31948,58 @@ define bfloat @v_log10_bf16(bfloat %a) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_log10_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 -; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo -; GFX1250-NEXT: v_ldexp_f32 v0, v0, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1) -; GFX1250-NEXT: v_log_f32_e32 v0, v0 -; GFX1250-NEXT: v_nop -; GFX1250-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0 -; GFX1250-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0| -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1 -; GFX1250-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_add_f32_e32 v1, v1, v2 -; GFX1250-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0 -; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_sub_f32_e32 v0, v0, v1 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_log10_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v1 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 32, vcc_lo +; GFX1250TRUE16-NEXT: v_ldexp_f32 v0, v1, v0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1) +; GFX1250TRUE16-NEXT: v_log_f32_e32 v0, v0 +; GFX1250TRUE16-NEXT: v_nop +; GFX1250TRUE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0 +; GFX1250TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0| +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1 +; GFX1250TRUE16-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_add_f32_e32 v1, v1, v2 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_log10_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo +; GFX1250FAKE16-NEXT: v_ldexp_f32 v0, v0, v1 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1) +; GFX1250FAKE16-NEXT: v_log_f32_e32 v0, v0 +; GFX1250FAKE16-NEXT: v_nop +; GFX1250FAKE16-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0 +; GFX1250FAKE16-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0| +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1 +; GFX1250FAKE16-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_add_f32_e32 v1, v1, v2 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_sub_f32_e32 v0, v0, v1 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.log10.bf16(bfloat %a) ret bfloat %op } @@ -31946,34 +32242,65 @@ define bfloat @v_exp_bf16(bfloat %a) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_exp_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v1, 16, v0 -; GFX1250-NEXT: s_mov_b32 s0, 0x3fb8aa3b -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v1 -; GFX1250-NEXT: v_rndne_f32_e32 v3, v2 -; GFX1250-NEXT: v_fma_mix_f32_bf16 v4, v0, s0, -v2 op_sel_hi:[1,0,0] -; GFX1250-NEXT: s_mov_b32 s0, 0x32a5705f -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_sub_f32_e32 v2, v2, v3 -; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, s0, v4 op_sel_hi:[1,0,0] -; GFX1250-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_add_f32_e32 v0, v2, v0 -; GFX1250-NEXT: v_cvt_i32_f32_e32 v2, v3 -; GFX1250-NEXT: v_exp_f32_e32 v0, v0 -; GFX1250-NEXT: v_nop -; GFX1250-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_ldexp_f32 v0, v0, v2 -; GFX1250-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo -; GFX1250-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_cndmask_b32_e32 v0, 0x7f800000, v0, vcc_lo -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_exp_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_mov_b32 s0, 0x3fb8aa3b +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v1 +; GFX1250TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v1 +; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v3, v0, s0, -v2 op_sel_hi:[1,0,0] +; GFX1250TRUE16-NEXT: v_rndne_f32_e32 v4, v2 +; GFX1250TRUE16-NEXT: s_mov_b32 s0, 0x32a5705f +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1) +; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v0, v0, s0, v3 op_sel_hi:[1,0,0] +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_sub_f32_e32 v2, v2, v4 +; GFX1250TRUE16-NEXT: v_add_f32_e32 v0, v2, v0 +; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v4 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1) +; GFX1250TRUE16-NEXT: v_exp_f32_e32 v0, v0 +; GFX1250TRUE16-NEXT: v_nop +; GFX1250TRUE16-NEXT: v_ldexp_f32 v0, v0, v2 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo +; GFX1250TRUE16-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v1 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e32 v0, 0x7f800000, v0, vcc_lo +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_exp_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0 +; GFX1250FAKE16-NEXT: s_mov_b32 s0, 0x3fb8aa3b +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_mul_f32_e32 v2, 0x3fb8aa3b, v1 +; GFX1250FAKE16-NEXT: v_rndne_f32_e32 v3, v2 +; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v4, v0, s0, -v2 op_sel_hi:[1,0,0] +; GFX1250FAKE16-NEXT: s_mov_b32 s0, 0x32a5705f +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_sub_f32_e32 v2, v2, v3 +; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, s0, v4 op_sel_hi:[1,0,0] +; GFX1250FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v1 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_add_f32_e32 v0, v2, v0 +; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v3 +; GFX1250FAKE16-NEXT: v_exp_f32_e32 v0, v0 +; GFX1250FAKE16-NEXT: v_nop +; GFX1250FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_ldexp_f32 v0, v0, v2 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v1 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7f800000, v0, vcc_lo +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.exp.bf16(bfloat %a) ret bfloat %op } @@ -32138,12 +32465,19 @@ define bfloat @v_exp2_bf16(bfloat %a) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_exp2_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_exp_bf16_e32 v0, v0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_exp2_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_exp_bf16_e32 v0.l, v0.l +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_exp2_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_exp_bf16_e32 v0, v0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.exp2.bf16(bfloat %a) ret bfloat %op } @@ -32382,34 +32716,65 @@ define bfloat @v_exp10_bf16(bfloat %a) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_exp10_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v1, 16, v0 -; GFX1250-NEXT: s_mov_b32 s0, 0x40549a78 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_mul_f32_e32 v2, 0x40549a78, v1 -; GFX1250-NEXT: v_rndne_f32_e32 v3, v2 -; GFX1250-NEXT: v_fma_mix_f32_bf16 v4, v0, s0, -v2 op_sel_hi:[1,0,0] -; GFX1250-NEXT: s_mov_b32 s0, 0x33979a37 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_sub_f32_e32 v2, v2, v3 -; GFX1250-NEXT: v_fma_mix_f32_bf16 v0, v0, s0, v4 op_sel_hi:[1,0,0] -; GFX1250-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc23369f4, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_add_f32_e32 v0, v2, v0 -; GFX1250-NEXT: v_cvt_i32_f32_e32 v2, v3 -; GFX1250-NEXT: v_exp_f32_e32 v0, v0 -; GFX1250-NEXT: v_nop -; GFX1250-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_ldexp_f32 v0, v0, v2 -; GFX1250-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo -; GFX1250-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0x421a209b, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_cndmask_b32_e32 v0, 0x7f800000, v0, vcc_lo -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_exp10_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_mov_b32 s0, 0x40549a78 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_mul_f32_e32 v2, 0x40549a78, v1 +; GFX1250TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc23369f4, v1 +; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v3, v0, s0, -v2 op_sel_hi:[1,0,0] +; GFX1250TRUE16-NEXT: v_rndne_f32_e32 v4, v2 +; GFX1250TRUE16-NEXT: s_mov_b32 s0, 0x33979a37 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1) +; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v0, v0, s0, v3 op_sel_hi:[1,0,0] +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_sub_f32_e32 v2, v2, v4 +; GFX1250TRUE16-NEXT: v_add_f32_e32 v0, v2, v0 +; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v4 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1) +; GFX1250TRUE16-NEXT: v_exp_f32_e32 v0, v0 +; GFX1250TRUE16-NEXT: v_nop +; GFX1250TRUE16-NEXT: v_ldexp_f32 v0, v0, v2 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo +; GFX1250TRUE16-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0x421a209b, v1 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e32 v0, 0x7f800000, v0, vcc_lo +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_exp10_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0 +; GFX1250FAKE16-NEXT: s_mov_b32 s0, 0x40549a78 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_mul_f32_e32 v2, 0x40549a78, v1 +; GFX1250FAKE16-NEXT: v_rndne_f32_e32 v3, v2 +; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v4, v0, s0, -v2 op_sel_hi:[1,0,0] +; GFX1250FAKE16-NEXT: s_mov_b32 s0, 0x33979a37 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_sub_f32_e32 v2, v2, v3 +; GFX1250FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, s0, v4 op_sel_hi:[1,0,0] +; GFX1250FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, 0xc23369f4, v1 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_add_f32_e32 v0, v2, v0 +; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v3 +; GFX1250FAKE16-NEXT: v_exp_f32_e32 v0, v0 +; GFX1250FAKE16-NEXT: v_nop +; GFX1250FAKE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_ldexp_f32 v0, v0, v2 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_nlt_f32_e32 vcc_lo, 0x421a209b, v1 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x7f800000, v0, vcc_lo +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.exp10.bf16(bfloat %a) ret bfloat %op } @@ -32517,15 +32882,26 @@ define bfloat @v_ceil_bf16(bfloat %a) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_ceil_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_ceil_f32_e32 v0, v0 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_ceil_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_ceil_f32_e32 v0, v1 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_ceil_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_ceil_f32_e32 v0, v0 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.ceil.bf16(bfloat %a) ret bfloat %op } @@ -32633,15 +33009,26 @@ define bfloat @v_trunc_bf16(bfloat %a) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_trunc_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_trunc_f32_e32 v0, v0 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_trunc_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_trunc_f32_e32 v0, v1 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_trunc_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_trunc_f32_e32 v0, v0 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.trunc.bf16(bfloat %a) ret bfloat %op } @@ -32749,15 +33136,26 @@ define bfloat @v_rint_bf16(bfloat %a) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_rint_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_rndne_f32_e32 v0, v0 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_rint_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_rndne_f32_e32 v0, v1 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_rint_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_rndne_f32_e32 v0, v0 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.rint.bf16(bfloat %a) ret bfloat %op } @@ -32865,15 +33263,26 @@ define bfloat @v_nearbyint_bf16(bfloat %a) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_nearbyint_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_rndne_f32_e32 v0, v0 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_nearbyint_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_rndne_f32_e32 v0, v1 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_nearbyint_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_rndne_f32_e32 v0, v0 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.nearbyint.bf16(bfloat %a) ret bfloat %op } @@ -33031,23 +33440,42 @@ define bfloat @v_round_bf16(bfloat %a) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_round_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_trunc_f32_e32 v1, v0 -; GFX1250-NEXT: v_sub_f32_e32 v2, v0, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_cmp_ge_f32_e64 s0, |v2|, 0.5 -; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v0 -; GFX1250-NEXT: v_add_f32_e32 v0, v1, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_round_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_trunc_f32_e32 v0, v1 +; GFX1250TRUE16-NEXT: v_sub_f32_e32 v2, v1, v0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cmp_ge_f32_e64 s0, |v2|, 0.5 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, v2, v1 +; GFX1250TRUE16-NEXT: v_add_f32_e32 v0, v0, v1 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_round_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_trunc_f32_e32 v1, v0 +; GFX1250FAKE16-NEXT: v_sub_f32_e32 v2, v0, v1 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cmp_ge_f32_e64 s0, |v2|, 0.5 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_bfi_b32 v0, 0x7fffffff, v2, v0 +; GFX1250FAKE16-NEXT: v_add_f32_e32 v0, v1, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.round.bf16(bfloat %a) ret bfloat %op } @@ -33155,15 +33583,26 @@ define bfloat @v_roundeven_bf16(bfloat %a) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_roundeven_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_rndne_f32_e32 v0, v0 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_roundeven_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_rndne_f32_e32 v0, v1 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_roundeven_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_rndne_f32_e32 v0, v0 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.roundeven.bf16(bfloat %a) ret bfloat %op } @@ -33271,15 +33710,26 @@ define bfloat @v_floor_bf16(bfloat %a) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_floor_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_floor_f32_e32 v0, v0 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_floor_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_floor_f32_e32 v0, v1 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_floor_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_floor_f32_e32 v0, v0 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.floor.bf16(bfloat %a) ret bfloat %op } @@ -33385,15 +33835,26 @@ define bfloat @v_canonicalize_bf16(bfloat %a) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_canonicalize_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_max_num_f32_e32 v0, v0, v0 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_canonicalize_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_max_num_f32_e32 v0, v1, v1 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_canonicalize_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_max_num_f32_e32 v0, v0, v0 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.canonicalize.bf16(bfloat %a) ret bfloat %op } @@ -33535,15 +33996,28 @@ define i1 @v_fcmp_oeq_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fcmp_oeq_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_cmp_eq_f32_e32 vcc_lo, v0, v1 -; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fcmp_oeq_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX1250TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v1, v2 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fcmp_oeq_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v0, v1 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fcmp oeq bfloat %a, %b ret i1 %op } @@ -33630,15 +34104,28 @@ define i1 @v_fcmp_ogt_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fcmp_ogt_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_cmp_gt_f32_e32 vcc_lo, v0, v1 -; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fcmp_ogt_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX1250TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v1, v2 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fcmp_ogt_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v0, v1 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fcmp ogt bfloat %a, %b ret i1 %op } @@ -33725,15 +34212,28 @@ define i1 @v_fcmp_oge_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fcmp_oge_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v1 -; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fcmp_oge_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX1250TRUE16-NEXT: v_cmp_ge_f32_e32 vcc_lo, v1, v2 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fcmp_oge_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cmp_ge_f32_e32 vcc_lo, v0, v1 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fcmp oge bfloat %a, %b ret i1 %op } @@ -33820,15 +34320,28 @@ define i1 @v_fcmp_olt_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fcmp_olt_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v1 -; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fcmp_olt_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX1250TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v1, v2 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fcmp_olt_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v0, v1 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fcmp olt bfloat %a, %b ret i1 %op } @@ -33915,15 +34428,28 @@ define i1 @v_fcmp_ole_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fcmp_ole_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v1 -; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fcmp_ole_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX1250TRUE16-NEXT: v_cmp_le_f32_e32 vcc_lo, v1, v2 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fcmp_ole_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cmp_le_f32_e32 vcc_lo, v0, v1 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fcmp ole bfloat %a, %b ret i1 %op } @@ -34010,15 +34536,28 @@ define i1 @v_fcmp_one_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fcmp_one_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_cmp_lg_f32_e32 vcc_lo, v0, v1 -; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fcmp_one_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX1250TRUE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v1, v2 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fcmp_one_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cmp_lg_f32_e32 vcc_lo, v0, v1 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fcmp one bfloat %a, %b ret i1 %op } @@ -34105,15 +34644,28 @@ define i1 @v_fcmp_uno_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fcmp_uno_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v1 -; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fcmp_uno_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX1250TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v2 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fcmp_uno_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v1 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fcmp uno bfloat %a, %b ret i1 %op } @@ -34200,15 +34752,28 @@ define i1 @v_fcmp_ueq_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fcmp_ueq_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_cmp_nlg_f32_e32 vcc_lo, v0, v1 -; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fcmp_ueq_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX1250TRUE16-NEXT: v_cmp_nlg_f32_e32 vcc_lo, v1, v2 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fcmp_ueq_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cmp_nlg_f32_e32 vcc_lo, v0, v1 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fcmp ueq bfloat %a, %b ret i1 %op } @@ -34295,15 +34860,28 @@ define i1 @v_fcmp_ugt_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fcmp_ugt_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_cmp_nle_f32_e32 vcc_lo, v0, v1 -; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fcmp_ugt_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX1250TRUE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, v1, v2 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fcmp_ugt_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cmp_nle_f32_e32 vcc_lo, v0, v1 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fcmp ugt bfloat %a, %b ret i1 %op } @@ -34390,15 +34968,28 @@ define i1 @v_fcmp_uge_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fcmp_uge_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v1 -; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fcmp_uge_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX1250TRUE16-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v1, v2 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fcmp_uge_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v1 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fcmp uge bfloat %a, %b ret i1 %op } @@ -34485,15 +35076,28 @@ define i1 @v_fcmp_ult_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fcmp_ult_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v1 -; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fcmp_ult_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX1250TRUE16-NEXT: v_cmp_nge_f32_e32 vcc_lo, v1, v2 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fcmp_ult_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cmp_nge_f32_e32 vcc_lo, v0, v1 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fcmp ult bfloat %a, %b ret i1 %op } @@ -34580,15 +35184,28 @@ define i1 @v_fcmp_ule_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fcmp_ule_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v1 -; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fcmp_ule_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX1250TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v1, v2 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fcmp_ule_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v1 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fcmp ule bfloat %a, %b ret i1 %op } @@ -34675,15 +35292,28 @@ define i1 @v_fcmp_une_bf16(bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fcmp_une_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_cmp_neq_f32_e32 vcc_lo, v0, v1 -; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fcmp_une_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX1250TRUE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v1, v2 +; GFX1250TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fcmp_une_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cmp_neq_f32_e32 vcc_lo, v0, v1 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fcmp une bfloat %a, %b ret i1 %op } @@ -34790,14 +35420,24 @@ define i16 @v_fptosi_bf16_to_i16(bfloat %x) { ; GFX11FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fptosi_bf16_to_i16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_cvt_i32_f32_e32 v0, v0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fptosi_bf16_to_i16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v1 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fptosi_bf16_to_i16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fptosi bfloat %x to i16 ret i16 %op } @@ -34899,18 +35539,31 @@ define <2 x i16> @v_fptosi_v2bf16_to_v2i16(<2 x bfloat> %x) { ; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x5040100 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fptosi_v2bf16_to_v2i16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v1, 16, v0 -; GFX1250-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_cvt_i32_f32_e32 v1, v1 -; GFX1250-NEXT: v_cvt_i32_f32_e32 v0, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_perm_b32 v0, v0, v1, 0x5040100 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fptosi_v2bf16_to_v2i16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v0 +; GFX1250TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v1 +; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fptosi_v2bf16_to_v2i16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v1, v1 +; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x5040100 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fptosi <2 x bfloat> %x to <2 x i16> ret <2 x i16> %op } @@ -35032,19 +35685,33 @@ define <3 x i16> @v_fptosi_v3bf16_to_v3i16(<3 x bfloat> %x) { ; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x5040100 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fptosi_v3bf16_to_v3i16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v2, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1 -; GFX1250-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GFX1250-NEXT: v_cvt_i32_f32_e32 v1, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_cvt_i32_f32_e32 v0, v0 -; GFX1250-NEXT: v_perm_b32 v0, v0, v2, 0x5040100 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fptosi_v3bf16_to_v3i16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0 +; GFX1250TRUE16-NEXT: v_dual_lshlrev_b32 v0, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v1 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fptosi_v3bf16_to_v3i16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v2, 16, v0 :: v_dual_lshlrev_b32 v1, 16, v1 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v1, v1 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0 +; GFX1250FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x5040100 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fptosi <3 x bfloat> %x to <3 x i16> ret <3 x i16> %op } @@ -35198,23 +35865,41 @@ define <4 x i16> @v_fptosi_v4bf16_to_v4i16(<4 x bfloat> %x) { ; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v2, 0x5040100 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fptosi_v4bf16_to_v4i16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshlrev_b32 v2, 16, v1 :: v_dual_lshlrev_b32 v3, 16, v0 -; GFX1250-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 -; GFX1250-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX1250-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GFX1250-NEXT: v_cvt_i32_f32_e32 v3, v3 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX1250-NEXT: v_cvt_i32_f32_e32 v0, v0 -; GFX1250-NEXT: v_cvt_i32_f32_e32 v1, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_perm_b32 v0, v0, v3, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v1, v1, v2, 0x5040100 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fptosi_v4bf16_to_v4i16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v0 +; GFX1250TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1 +; GFX1250TRUE16-NEXT: v_dual_lshlrev_b32 v1, 16, v1 :: v_dual_lshlrev_b32 v0, 16, v0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v3, v3 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v1 +; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fptosi_v4bf16_to_v4i16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshlrev_b32 v2, 16, v1 :: v_dual_lshlrev_b32 v3, 16, v0 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v3, v3 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0 +; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v1, v1 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_perm_b32 v0, v0, v3, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v1, v1, v2, 0x5040100 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fptosi <4 x bfloat> %x to <4 x i16> ret <4 x i16> %op } @@ -35274,14 +35959,24 @@ define i32 @v_fptosi_bf16_to_i32(bfloat %x) { ; GFX11FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fptosi_bf16_to_i32: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_cvt_i32_f32_e32 v0, v0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fptosi_bf16_to_i32: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v1 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fptosi_bf16_to_i32: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fptosi bfloat %x to i32 ret i32 %op } @@ -35729,26 +36424,48 @@ define i64 @v_fptosi_bf16_to_i64(bfloat %x) { ; GFX11FAKE16-NEXT: v_sub_co_ci_u32_e64 v1, null, v1, v3, vcc_lo ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fptosi_bf16_to_i64: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshlrev_b32_e32 v0, 16, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_trunc_f32_e32 v0, v0 -; GFX1250-NEXT: v_mul_f32_e64 v1, 0x2f800000, |v0| -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_floor_f32_e32 v1, v1 -; GFX1250-NEXT: v_fma_f32 v2, 0xcf800000, v1, |v0| -; GFX1250-NEXT: v_ashrrev_i32_e32 v0, 31, v0 -; GFX1250-NEXT: v_cvt_u32_f32_e32 v3, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GFX1250-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_bitop2_b32 v3, v3, v0 bitop3:0x14 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_xor_b32_e32 v2, v2, v0 -; GFX1250-NEXT: v_sub_nc_u64_e32 v[0:1], v[2:3], v[0:1] -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fptosi_bf16_to_i64: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_trunc_f32_e32 v0, v1 +; GFX1250TRUE16-NEXT: v_mul_f32_e64 v1, 0x2f800000, |v0| +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_floor_f32_e32 v1, v1 +; GFX1250TRUE16-NEXT: v_fma_f32 v2, 0xcf800000, v1, |v0| +; GFX1250TRUE16-NEXT: v_ashrrev_i32_e32 v0, 31, v0 +; GFX1250TRUE16-NEXT: v_cvt_u32_f32_e32 v3, v1 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v2 +; GFX1250TRUE16-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_bitop2_b32 v3, v3, v0 bitop3:0x14 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_xor_b32_e32 v2, v2, v0 +; GFX1250TRUE16-NEXT: v_sub_nc_u64_e32 v[0:1], v[2:3], v[0:1] +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fptosi_bf16_to_i64: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_trunc_f32_e32 v0, v0 +; GFX1250FAKE16-NEXT: v_mul_f32_e64 v1, 0x2f800000, |v0| +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_floor_f32_e32 v1, v1 +; GFX1250FAKE16-NEXT: v_fma_f32 v2, 0xcf800000, v1, |v0| +; GFX1250FAKE16-NEXT: v_ashrrev_i32_e32 v0, 31, v0 +; GFX1250FAKE16-NEXT: v_cvt_u32_f32_e32 v3, v1 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_cvt_u32_f32_e32 v2, v2 +; GFX1250FAKE16-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_bitop2_b32 v3, v3, v0 bitop3:0x14 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_xor_b32_e32 v2, v2, v0 +; GFX1250FAKE16-NEXT: v_sub_nc_u64_e32 v[0:1], v[2:3], v[0:1] +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = fptosi bfloat %x to i64 ret i64 %op } @@ -37293,22 +38010,39 @@ define <3 x bfloat> @v_sitofp_v3i16_to_v3bf16(<3 x i16> %x) { ; GFX11FAKE16-NEXT: v_alignbit_b32 v1, s0, v1, 16 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_sitofp_v3i16_to_v3bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_ashrrev_i32_e32 v2, 16, v0 -; GFX1250-NEXT: v_bfe_i32 v0, v0, 0, 16 -; GFX1250-NEXT: v_bfe_i32 v1, v1, 0, 16 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_cvt_f32_i32_e32 v2, v2 -; GFX1250-NEXT: v_cvt_f32_i32_e32 v0, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_cvt_f32_i32_e32 v1, v1 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, v2 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_sitofp_v3i16_to_v3bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16 +; GFX1250TRUE16-NEXT: v_ashrrev_i32_e32 v2, 16, v0 +; GFX1250TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1 +; GFX1250TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v2 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_sitofp_v3i16_to_v3bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_ashrrev_i32_e32 v2, 16, v0 +; GFX1250FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GFX1250FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 16 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_cvt_f32_i32_e32 v2, v2 +; GFX1250FAKE16-NEXT: v_cvt_f32_i32_e32 v0, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_cvt_f32_i32_e32 v1, v1 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v2 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = sitofp <3 x i16> %x to <3 x bfloat> ret <3 x bfloat> %op } @@ -37972,17 +38706,31 @@ define <3 x bfloat> @v_sitofp_v3i32_to_v3bf16(<3 x i32> %x) { ; GFX11FAKE16-NEXT: v_alignbit_b32 v1, s0, v2, 16 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_sitofp_v3i32_to_v3bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_cvt_f32_i32_e32 v1, v1 -; GFX1250-NEXT: v_cvt_f32_i32_e32 v0, v0 -; GFX1250-NEXT: v_cvt_f32_i32_e32 v2, v2 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, v1 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v1, v2, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_sitofp_v3i32_to_v3bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2 +; GFX1250TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1 +; GFX1250TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v1 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_sitofp_v3i32_to_v3bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_cvt_f32_i32_e32 v1, v1 +; GFX1250FAKE16-NEXT: v_cvt_f32_i32_e32 v0, v0 +; GFX1250FAKE16-NEXT: v_cvt_f32_i32_e32 v2, v2 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v1 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v1, v2, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = sitofp <3 x i32> %x to <3 x bfloat> ret <3 x bfloat> %op } @@ -39232,52 +39980,101 @@ define <3 x bfloat> @v_sitofp_v3i64_to_v3bf16(<3 x i64> %x) { ; GFX11FAKE16-NEXT: v_alignbit_b32 v1, s0, v1, 16 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_sitofp_v3i64_to_v3bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_xor_b32_e32 v8, v4, v5 -; GFX1250-NEXT: v_xor_b32_e32 v6, v2, v3 -; GFX1250-NEXT: v_cls_i32_e32 v10, v3 -; GFX1250-NEXT: v_cls_i32_e32 v9, v5 -; GFX1250-NEXT: v_cls_i32_e32 v11, v1 -; GFX1250-NEXT: v_dual_ashrrev_i32 v8, 31, v8 :: v_dual_bitop2_b32 v7, v0, v1 bitop3:0x14 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_dual_ashrrev_i32 v6, 31, v6 :: v_dual_ashrrev_i32 v7, 31, v7 -; GFX1250-NEXT: v_dual_add_nc_u32 v6, 32, v6 :: v_dual_add_nc_u32 v7, 32, v7 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_add_min_u32_e64 v6, v10, -1, v6 -; GFX1250-NEXT: v_add_min_u32_e64 v7, v11, -1, v7 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_lshlrev_b64_e32 v[2:3], v6, v[2:3] -; GFX1250-NEXT: v_lshlrev_b64_e32 v[0:1], v7, v[0:1] -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_min_u32_e32 v2, 1, v2 -; GFX1250-NEXT: v_add_nc_u32_e32 v8, 32, v8 -; GFX1250-NEXT: v_min_u32_e32 v0, 1, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_or_b32_e32 v2, v3, v2 -; GFX1250-NEXT: v_add_min_u32_e64 v8, v9, -1, v8 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_dual_sub_nc_u32 v3, 32, v6 :: v_dual_bitop2_b32 v0, v1, v0 bitop3:0x54 -; GFX1250-NEXT: v_cvt_f32_i32_e32 v2, v2 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_lshlrev_b64_e32 v[4:5], v8, v[4:5] -; GFX1250-NEXT: v_sub_nc_u32_e32 v8, 32, v8 -; GFX1250-NEXT: v_ldexp_f32 v2, v2, v3 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_min_u32_e32 v4, 1, v4 -; GFX1250-NEXT: v_dual_sub_nc_u32 v4, 32, v7 :: v_dual_bitop2_b32 v1, v5, v4 bitop3:0x54 -; GFX1250-NEXT: v_cvt_f32_i32_e32 v0, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_cvt_f32_i32_e32 v1, v1 -; GFX1250-NEXT: v_ldexp_f32 v0, v0, v4 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_ldexp_f32 v1, v1, v8 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, v2 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_sitofp_v3i64_to_v3bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_xor_b32_e32 v7, v2, v3 +; GFX1250TRUE16-NEXT: v_xor_b32_e32 v6, v4, v5 +; GFX1250TRUE16-NEXT: v_cls_i32_e32 v10, v3 +; GFX1250TRUE16-NEXT: v_cls_i32_e32 v9, v5 +; GFX1250TRUE16-NEXT: v_cls_i32_e32 v11, v1 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_dual_ashrrev_i32 v7, 31, v7 :: v_dual_ashrrev_i32 v6, 31, v6 +; GFX1250TRUE16-NEXT: v_xor_b32_e32 v8, v0, v1 +; GFX1250TRUE16-NEXT: v_dual_add_nc_u32 v7, 32, v7 :: v_dual_add_nc_u32 v6, 32, v6 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_ashrrev_i32_e32 v8, 31, v8 +; GFX1250TRUE16-NEXT: v_add_min_u32_e64 v7, v10, -1, v7 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_add_min_u32_e64 v6, v9, -1, v6 +; GFX1250TRUE16-NEXT: v_lshlrev_b64_e32 v[2:3], v7, v[2:3] +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_lshlrev_b64_e32 v[4:5], v6, v[4:5] +; GFX1250TRUE16-NEXT: v_min_u32_e32 v2, 1, v2 +; GFX1250TRUE16-NEXT: v_add_nc_u32_e32 v8, 32, v8 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_min_u32_e32 v4, 1, v4 +; GFX1250TRUE16-NEXT: v_or_b32_e32 v2, v3, v2 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_add_min_u32_e64 v8, v11, -1, v8 +; GFX1250TRUE16-NEXT: v_dual_sub_nc_u32 v3, 32, v6 :: v_dual_bitop2_b32 v4, v5, v4 bitop3:0x54 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_cvt_f32_i32_e32 v2, v2 +; GFX1250TRUE16-NEXT: v_lshlrev_b64_e32 v[0:1], v8, v[0:1] +; GFX1250TRUE16-NEXT: v_sub_nc_u32_e32 v5, 32, v8 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_min_u32_e32 v0, 1, v0 +; GFX1250TRUE16-NEXT: v_or_b32_e32 v0, v1, v0 +; GFX1250TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v4 +; GFX1250TRUE16-NEXT: v_sub_nc_u32_e32 v4, 32, v7 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_cvt_f32_i32_e32 v0, v0 +; GFX1250TRUE16-NEXT: v_ldexp_f32 v1, v1, v3 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_ldexp_f32 v2, v2, v4 +; GFX1250TRUE16-NEXT: v_ldexp_f32 v0, v0, v5 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v2 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_sitofp_v3i64_to_v3bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_xor_b32_e32 v8, v4, v5 +; GFX1250FAKE16-NEXT: v_xor_b32_e32 v6, v2, v3 +; GFX1250FAKE16-NEXT: v_cls_i32_e32 v10, v3 +; GFX1250FAKE16-NEXT: v_cls_i32_e32 v9, v5 +; GFX1250FAKE16-NEXT: v_cls_i32_e32 v11, v1 +; GFX1250FAKE16-NEXT: v_dual_ashrrev_i32 v8, 31, v8 :: v_dual_bitop2_b32 v7, v0, v1 bitop3:0x14 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_dual_ashrrev_i32 v6, 31, v6 :: v_dual_ashrrev_i32 v7, 31, v7 +; GFX1250FAKE16-NEXT: v_dual_add_nc_u32 v6, 32, v6 :: v_dual_add_nc_u32 v7, 32, v7 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_add_min_u32_e64 v6, v10, -1, v6 +; GFX1250FAKE16-NEXT: v_add_min_u32_e64 v7, v11, -1, v7 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_lshlrev_b64_e32 v[2:3], v6, v[2:3] +; GFX1250FAKE16-NEXT: v_lshlrev_b64_e32 v[0:1], v7, v[0:1] +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_min_u32_e32 v2, 1, v2 +; GFX1250FAKE16-NEXT: v_add_nc_u32_e32 v8, 32, v8 +; GFX1250FAKE16-NEXT: v_min_u32_e32 v0, 1, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_or_b32_e32 v2, v3, v2 +; GFX1250FAKE16-NEXT: v_add_min_u32_e64 v8, v9, -1, v8 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_dual_sub_nc_u32 v3, 32, v6 :: v_dual_bitop2_b32 v0, v1, v0 bitop3:0x54 +; GFX1250FAKE16-NEXT: v_cvt_f32_i32_e32 v2, v2 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_lshlrev_b64_e32 v[4:5], v8, v[4:5] +; GFX1250FAKE16-NEXT: v_sub_nc_u32_e32 v8, 32, v8 +; GFX1250FAKE16-NEXT: v_ldexp_f32 v2, v2, v3 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_min_u32_e32 v4, 1, v4 +; GFX1250FAKE16-NEXT: v_dual_sub_nc_u32 v4, 32, v7 :: v_dual_bitop2_b32 v1, v5, v4 bitop3:0x54 +; GFX1250FAKE16-NEXT: v_cvt_f32_i32_e32 v0, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_cvt_f32_i32_e32 v1, v1 +; GFX1250FAKE16-NEXT: v_ldexp_f32 v0, v0, v4 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_ldexp_f32 v1, v1, v8 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v2 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = sitofp <3 x i64> %x to <3 x bfloat> ret <3 x bfloat> %op } @@ -40015,15 +40812,26 @@ define bfloat @v_uitofp_i16_to_bf16(i16 %x) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_uitofp_i16_to_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_cvt_f32_u32_e32 v0, v0 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_uitofp_i16_to_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v1 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_uitofp_i16_to_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cvt_f32_u32_e32 v0, v0 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = uitofp i16 %x to bfloat ret bfloat %op } @@ -40167,18 +40975,32 @@ define <2 x bfloat> @v_uitofp_v2i16_to_v2bf16(<2 x i16> %x) { ; GFX11FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x7060302 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_uitofp_v2i16_to_v2bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshrrev_b32_e32 v1, 16, v0 -; GFX1250-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_cvt_f32_u32_e32 v1, v1 -; GFX1250-NEXT: v_cvt_f32_u32_e32 v0, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, v1 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_uitofp_v2i16_to_v2bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, 0 +; GFX1250TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.h +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v2 +; GFX1250TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v1 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_uitofp_v2i16_to_v2bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_cvt_f32_u32_e32 v1, v1 +; GFX1250FAKE16-NEXT: v_cvt_f32_u32_e32 v0, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v1 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = uitofp <2 x i16> %x to <2 x bfloat> ret <2 x bfloat> %op } @@ -40373,22 +41195,41 @@ define <3 x bfloat> @v_uitofp_v3i16_to_v3bf16(<3 x i16> %x) { ; GFX11FAKE16-NEXT: v_alignbit_b32 v1, s0, v1, 16 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_uitofp_v3i16_to_v3bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_lshrrev_b32_e32 v2, 16, v0 -; GFX1250-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX1250-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_cvt_f32_u32_e32 v2, v2 -; GFX1250-NEXT: v_cvt_f32_u32_e32 v0, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_cvt_f32_u32_e32 v1, v1 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, v2 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_uitofp_v3i16_to_v3bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; GFX1250TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v3.h, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.h +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX1250TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v1 +; GFX1250TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v2 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v3 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v3, v0, s0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v1, v2 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_uitofp_v3i16_to_v3bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_cvt_f32_u32_e32 v2, v2 +; GFX1250FAKE16-NEXT: v_cvt_f32_u32_e32 v0, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_cvt_f32_u32_e32 v1, v1 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v2 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = uitofp <3 x i16> %x to <3 x bfloat> ret <3 x bfloat> %op } @@ -40626,23 +41467,43 @@ define <4 x bfloat> @v_uitofp_v4i16_to_v4bf16(<4 x i16> %x) { ; GFX11FAKE16-NEXT: v_perm_b32 v1, v1, v2, 0x7060302 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_uitofp_v4i16_to_v4bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshrrev_b32 v2, 16, v1 :: v_dual_lshrrev_b32 v3, 16, v0 -; GFX1250-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX1250-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX1250-NEXT: v_cvt_f32_u32_e32 v2, v2 -; GFX1250-NEXT: v_cvt_f32_u32_e32 v3, v3 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX1250-NEXT: v_cvt_f32_u32_e32 v0, v0 -; GFX1250-NEXT: v_cvt_f32_u32_e32 v1, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, v3 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v1, v1, v2 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_uitofp_v4i16_to_v4bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.h, 0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.h +; GFX1250TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX1250TRUE16-NEXT: v_cvt_f32_u32_e32 v4, v2 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.h +; GFX1250TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v1 +; GFX1250TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v3 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2 +; GFX1250TRUE16-NEXT: v_cvt_f32_u32_e32 v3, v0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v1, v2 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v1, v3, v4 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_uitofp_v4i16_to_v4bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v2, 16, v1 :: v_dual_lshrrev_b32 v3, 16, v0 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX1250FAKE16-NEXT: v_cvt_f32_u32_e32 v2, v2 +; GFX1250FAKE16-NEXT: v_cvt_f32_u32_e32 v3, v3 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX1250FAKE16-NEXT: v_cvt_f32_u32_e32 v0, v0 +; GFX1250FAKE16-NEXT: v_cvt_f32_u32_e32 v1, v1 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v3 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v1, v1, v2 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = uitofp <4 x i16> %x to <4 x bfloat> ret <4 x bfloat> %op } @@ -41058,17 +41919,31 @@ define <3 x bfloat> @v_uitofp_v3i32_to_v3bf16(<3 x i32> %x) { ; GFX11FAKE16-NEXT: v_alignbit_b32 v1, s0, v2, 16 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_uitofp_v3i32_to_v3bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_cvt_f32_u32_e32 v1, v1 -; GFX1250-NEXT: v_cvt_f32_u32_e32 v0, v0 -; GFX1250-NEXT: v_cvt_f32_u32_e32 v2, v2 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, v1 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v1, v2, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_uitofp_v3i32_to_v3bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2 +; GFX1250TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v1 +; GFX1250TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v2, v2, s0 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v1 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_uitofp_v3i32_to_v3bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_cvt_f32_u32_e32 v1, v1 +; GFX1250FAKE16-NEXT: v_cvt_f32_u32_e32 v0, v0 +; GFX1250FAKE16-NEXT: v_cvt_f32_u32_e32 v2, v2 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v1 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v1, v2, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = uitofp <3 x i32> %x to <3 x bfloat> ret <3 x bfloat> %op } @@ -42105,44 +42980,84 @@ define <3 x bfloat> @v_uitofp_v3i64_to_v3bf16(<3 x i64> %x) { ; GFX11FAKE16-NEXT: v_alignbit_b32 v1, s0, v1, 16 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_uitofp_v3i64_to_v3bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_clz_i32_u32_e32 v6, v3 -; GFX1250-NEXT: v_clz_i32_u32_e32 v7, v1 -; GFX1250-NEXT: v_clz_i32_u32_e32 v8, v5 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_min_u32_e32 v6, 32, v6 -; GFX1250-NEXT: v_min_u32_e32 v7, 32, v7 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_min_u32_e32 v8, 32, v8 -; GFX1250-NEXT: v_lshlrev_b64_e32 v[2:3], v6, v[2:3] -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_lshlrev_b64_e32 v[0:1], v7, v[0:1] -; GFX1250-NEXT: v_lshlrev_b64_e32 v[4:5], v8, v[4:5] -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_min_u32_e32 v2, 1, v2 -; GFX1250-NEXT: v_min_u32_e32 v0, 1, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_min_u32_e32 v4, 1, v4 -; GFX1250-NEXT: v_dual_sub_nc_u32 v8, 32, v8 :: v_dual_bitop2_b32 v2, v3, v2 bitop3:0x54 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_dual_sub_nc_u32 v3, 32, v6 :: v_dual_bitop2_b32 v0, v1, v0 bitop3:0x54 -; GFX1250-NEXT: v_dual_sub_nc_u32 v4, 32, v7 :: v_dual_bitop2_b32 v1, v5, v4 bitop3:0x54 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_cvt_f32_u32_e32 v2, v2 -; GFX1250-NEXT: v_cvt_f32_u32_e32 v0, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_cvt_f32_u32_e32 v1, v1 -; GFX1250-NEXT: v_ldexp_f32 v2, v2, v3 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_ldexp_f32 v0, v0, v4 -; GFX1250-NEXT: v_ldexp_f32 v1, v1, v8 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v0, v0, v2 -; GFX1250-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_uitofp_v3i64_to_v3bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_clz_i32_u32_e32 v6, v5 +; GFX1250TRUE16-NEXT: v_clz_i32_u32_e32 v7, v3 +; GFX1250TRUE16-NEXT: v_clz_i32_u32_e32 v8, v1 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_min_u32_e32 v6, 32, v6 +; GFX1250TRUE16-NEXT: v_min_u32_e32 v7, 32, v7 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_min_u32_e32 v8, 32, v8 +; GFX1250TRUE16-NEXT: v_lshlrev_b64_e32 v[4:5], v6, v[4:5] +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_lshlrev_b64_e32 v[2:3], v7, v[2:3] +; GFX1250TRUE16-NEXT: v_lshlrev_b64_e32 v[0:1], v8, v[0:1] +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_min_u32_e32 v4, 1, v4 +; GFX1250TRUE16-NEXT: v_min_u32_e32 v2, 1, v2 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_min_u32_e32 v0, 1, v0 +; GFX1250TRUE16-NEXT: v_or_b32_e32 v4, v5, v4 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_or_b32_e32 v2, v3, v2 +; GFX1250TRUE16-NEXT: v_dual_sub_nc_u32 v3, 32, v6 :: v_dual_bitop2_b32 v0, v1, v0 bitop3:0x54 +; GFX1250TRUE16-NEXT: v_sub_nc_u32_e32 v5, 32, v8 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4) +; GFX1250TRUE16-NEXT: v_cvt_f32_u32_e32 v1, v4 +; GFX1250TRUE16-NEXT: v_sub_nc_u32_e32 v4, 32, v7 +; GFX1250TRUE16-NEXT: v_cvt_f32_u32_e32 v2, v2 +; GFX1250TRUE16-NEXT: v_cvt_f32_u32_e32 v0, v0 +; GFX1250TRUE16-NEXT: v_ldexp_f32 v1, v1, v3 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250TRUE16-NEXT: v_ldexp_f32 v2, v2, v4 +; GFX1250TRUE16-NEXT: v_ldexp_f32 v0, v0, v5 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0 +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v2 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_uitofp_v3i64_to_v3bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_clz_i32_u32_e32 v6, v3 +; GFX1250FAKE16-NEXT: v_clz_i32_u32_e32 v7, v1 +; GFX1250FAKE16-NEXT: v_clz_i32_u32_e32 v8, v5 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_min_u32_e32 v6, 32, v6 +; GFX1250FAKE16-NEXT: v_min_u32_e32 v7, 32, v7 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_min_u32_e32 v8, 32, v8 +; GFX1250FAKE16-NEXT: v_lshlrev_b64_e32 v[2:3], v6, v[2:3] +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_lshlrev_b64_e32 v[0:1], v7, v[0:1] +; GFX1250FAKE16-NEXT: v_lshlrev_b64_e32 v[4:5], v8, v[4:5] +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_min_u32_e32 v2, 1, v2 +; GFX1250FAKE16-NEXT: v_min_u32_e32 v0, 1, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_min_u32_e32 v4, 1, v4 +; GFX1250FAKE16-NEXT: v_dual_sub_nc_u32 v8, 32, v8 :: v_dual_bitop2_b32 v2, v3, v2 bitop3:0x54 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_dual_sub_nc_u32 v3, 32, v6 :: v_dual_bitop2_b32 v0, v1, v0 bitop3:0x54 +; GFX1250FAKE16-NEXT: v_dual_sub_nc_u32 v4, 32, v7 :: v_dual_bitop2_b32 v1, v5, v4 bitop3:0x54 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_cvt_f32_u32_e32 v2, v2 +; GFX1250FAKE16-NEXT: v_cvt_f32_u32_e32 v0, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_cvt_f32_u32_e32 v1, v1 +; GFX1250FAKE16-NEXT: v_ldexp_f32 v2, v2, v3 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_ldexp_f32 v0, v0, v4 +; GFX1250FAKE16-NEXT: v_ldexp_f32 v1, v1, v8 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, v2 +; GFX1250FAKE16-NEXT: v_cvt_pk_bf16_f32 v1, v1, s0 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = uitofp <3 x i64> %x to <3 x bfloat> ret <3 x bfloat> %op } @@ -42717,15 +43632,25 @@ define bfloat @v_select_bf16(i1 %cond, bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_select_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX1250-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_select_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_select_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = select i1 %cond, bfloat %a, bfloat %b ret bfloat %op } @@ -42810,16 +43735,27 @@ define bfloat @v_select_fneg_lhs_bf16(i1 %cond, bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_select_fneg_lhs_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX1250-NEXT: v_xor_b32_e32 v1, 0x8000, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX1250-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_select_fneg_lhs_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX1250TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v1.l +; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, vcc_lo +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_select_fneg_lhs_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX1250FAKE16-NEXT: v_xor_b32_e32 v1, 0x8000, v1 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %neg.a = fneg bfloat %a %op = select i1 %cond, bfloat %neg.a, bfloat %b ret bfloat %op @@ -42905,16 +43841,27 @@ define bfloat @v_select_fneg_rhs_bf16(i1 %cond, bfloat %a, bfloat %b) { ; GFX11FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_select_fneg_rhs_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX1250-NEXT: v_xor_b32_e32 v2, 0x8000, v2 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX1250-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_select_fneg_rhs_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX1250TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v2.l +; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_select_fneg_rhs_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX1250FAKE16-NEXT: v_xor_b32_e32 v2, 0x8000, v2 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %neg.b = fneg bfloat %b %op = select i1 %cond, bfloat %a, bfloat %neg.b ret bfloat %op @@ -43025,18 +43972,29 @@ define <2 x bfloat> @v_select_v2bf16(i1 %cond, <2 x bfloat> %a, <2 x bfloat> %b) ; GFX11FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_select_v2bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshrrev_b32 v3, 16, v1 :: v_dual_bitop2_b32 v0, 1, v0 bitop3:0x40 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX1250-NEXT: v_dual_lshrrev_b32 v4, 16, v2 :: v_dual_cndmask_b32 v0, v2, v1, vcc_lo -; GFX1250-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_select_v2bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_and_b32_e32 v0, 1, v0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, vcc_lo +; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v1.h, vcc_lo +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_select_v2bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v3, 16, v1 :: v_dual_bitop2_b32 v0, 1, v0 bitop3:0x40 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v4, 16, v2 :: v_dual_cndmask_b32 v0, v2, v1, vcc_lo +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = select i1 %cond, <2 x bfloat> %a, <2 x bfloat> %b ret <2 x bfloat> %op } @@ -43155,20 +44113,34 @@ define <2 x bfloat> @v_vselect_v2bf16(<2 x i1> %cond, <2 x bfloat> %a, <2 x bflo ; GFX11FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_vselect_v2bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_dual_lshrrev_b32 v4, 16, v2 :: v_dual_bitop2_b32 v0, 1, v0 bitop3:0x40 -; GFX1250-NEXT: v_dual_lshrrev_b32 v5, 16, v3 :: v_dual_bitop2_b32 v1, 1, v1 bitop3:0x40 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX1250-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc_lo -; GFX1250-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_vselect_v2bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l +; GFX1250TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.h +; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, vcc_lo +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, v2.h, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_vselect_v2bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v4, 16, v2 :: v_dual_bitop2_b32 v0, 1, v0 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v5, 16, v3 :: v_dual_bitop2_b32 v1, 1, v1 bitop3:0x40 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc_lo +; GFX1250FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = select <2 x i1> %cond, <2 x bfloat> %a, <2 x bfloat> %b ret <2 x bfloat> %op } @@ -43256,16 +44228,26 @@ define amdgpu_ps i32 @s_select_bf16(bfloat inreg %a, bfloat inreg %b, i32 %c) { ; GFX11FAKE16-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11FAKE16-NEXT: ; return to shader part epilog ; -; GFX1250-LABEL: s_select_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: v_mov_b32_e32 v1, s0 -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_cndmask_b32_e32 v0, s1, v1, vcc_lo -; GFX1250-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1250-NEXT: ; return to shader part epilog +; GFX1250TRUE16-LABEL: s_select_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, s0 +; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.h, 0 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, s1, v1.l, vcc_lo +; GFX1250TRUE16-NEXT: v_readfirstlane_b32 s0, v0 +; GFX1250TRUE16-NEXT: ; return to shader part epilog +; +; GFX1250FAKE16-LABEL: s_select_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: v_mov_b32_e32 v1, s0 +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, s1, v1, vcc_lo +; GFX1250FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_readfirstlane_b32 s0, v0 +; GFX1250FAKE16-NEXT: ; return to shader part epilog %cond = icmp eq i32 %c, 0 %op = select i1 %cond, bfloat %a, bfloat %b %cast = bitcast bfloat %op to i16 @@ -43402,20 +44384,34 @@ define amdgpu_ps i32 @s_select_v2bf16(<2 x bfloat> inreg %a, <2 x bfloat> inreg ; GFX11FAKE16-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11FAKE16-NEXT: ; return to shader part epilog ; -; GFX1250-LABEL: s_select_v2bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_lshr_b32 s2, s0, 16 -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX1250-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s0 -; GFX1250-NEXT: s_lshr_b32 s3, s1, 16 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX1250-NEXT: v_cndmask_b32_e32 v0, s3, v1, vcc_lo -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_cndmask_b32_e32 v1, s1, v2, vcc_lo -; GFX1250-NEXT: v_perm_b32 v0, v0, v1, 0x5040100 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1250-NEXT: ; return to shader part epilog +; GFX1250TRUE16-LABEL: s_select_v2bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_lshr_b32 s2, s0, 16 +; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, s2 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.l, s0 +; GFX1250TRUE16-NEXT: s_lshr_b32 s0, s1, 16 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1) +; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, s0, v1.l, vcc_lo +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, s1, v0.l, vcc_lo +; GFX1250TRUE16-NEXT: v_readfirstlane_b32 s0, v0 +; GFX1250TRUE16-NEXT: ; return to shader part epilog +; +; GFX1250FAKE16-LABEL: s_select_v2bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_lshr_b32 s2, s0, 16 +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1250FAKE16-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s0 +; GFX1250FAKE16-NEXT: s_lshr_b32 s3, s1, 16 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, s3, v1, vcc_lo +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v1, s1, v2, vcc_lo +; GFX1250FAKE16-NEXT: v_perm_b32 v0, v0, v1, 0x5040100 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_readfirstlane_b32 s0, v0 +; GFX1250FAKE16-NEXT: ; return to shader part epilog %cond = icmp eq i32 %c, 0 %op = select i1 %cond, <2 x bfloat> %a, <2 x bfloat> %b %cast = bitcast <2 x bfloat> %op to i32 @@ -43554,21 +44550,36 @@ define amdgpu_ps i32 @s_vselect_v2bf16(<2 x bfloat> inreg %a, <2 x bfloat> inreg ; GFX11FAKE16-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11FAKE16-NEXT: ; return to shader part epilog ; -; GFX1250-LABEL: s_vselect_v2bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_lshr_b32 s2, s0, 16 -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX1250-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s0 -; GFX1250-NEXT: s_lshr_b32 s0, s1, 16 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX1250-NEXT: v_cndmask_b32_e32 v1, s0, v2, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_cndmask_b32_e32 v0, s1, v3, vcc_lo -; GFX1250-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1250-NEXT: ; return to shader part epilog +; GFX1250TRUE16-LABEL: s_vselect_v2bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_lshr_b32 s3, s0, 16 +; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 0, v1 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.l, s3 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.h, s0 +; GFX1250TRUE16-NEXT: s_lshr_b32 s0, s1, 16 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1) +; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.h, s0, v0.l, s2 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.l, s1, v0.h, vcc_lo +; GFX1250TRUE16-NEXT: v_readfirstlane_b32 s0, v1 +; GFX1250TRUE16-NEXT: ; return to shader part epilog +; +; GFX1250FAKE16-LABEL: s_vselect_v2bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_lshr_b32 s2, s0, 16 +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX1250FAKE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s0 +; GFX1250FAKE16-NEXT: s_lshr_b32 s0, s1, 16 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v1, s0, v2, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, s1, v3, vcc_lo +; GFX1250FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_readfirstlane_b32 s0, v0 +; GFX1250FAKE16-NEXT: ; return to shader part epilog %cond = icmp eq <2 x i32> %c, zeroinitializer %op = select <2 x i1> %cond, <2 x bfloat> %a, <2 x bfloat> %b %cast = bitcast <2 x bfloat> %op to i32 @@ -45557,32 +46568,55 @@ define amdgpu_ps <2 x i32> @s_vselect_v4bf16(<4 x bfloat> inreg %a, <4 x bfloat> ; GFX11FAKE16-NEXT: v_readfirstlane_b32 s1, v1 ; GFX11FAKE16-NEXT: ; return to shader part epilog ; -; GFX1250-LABEL: s_vselect_v4bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_lshr_b32 s4, s1, 16 -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v3 -; GFX1250-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s1 -; GFX1250-NEXT: s_lshr_b32 s4, s3, 16 -; GFX1250-NEXT: s_lshr_b32 s5, s0, 16 -; GFX1250-NEXT: v_mov_b32_e32 v6, s0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX1250-NEXT: v_cndmask_b32_e32 v3, s4, v4, vcc_lo -; GFX1250-NEXT: v_mov_b32_e32 v4, s5 -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX1250-NEXT: s_lshr_b32 s0, s2, 16 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1) -; GFX1250-NEXT: v_cndmask_b32_e32 v1, s0, v4, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX1250-NEXT: v_cndmask_b32_e32 v0, s2, v6, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX1250-NEXT: v_cndmask_b32_e32 v2, s3, v5, vcc_lo -; GFX1250-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_perm_b32 v1, v3, v2, 0x5040100 -; GFX1250-NEXT: v_readfirstlane_b32 s1, v1 -; GFX1250-NEXT: ; return to shader part epilog +; GFX1250TRUE16-LABEL: s_vselect_v4bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_lshr_b32 s7, s1, 16 +; GFX1250TRUE16-NEXT: s_lshr_b32 s9, s0, 16 +; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e64 s4, 0, v1 +; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e64 s5, 0, v2 +; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e64 s6, 0, v3 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.l, s7 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.h, s9 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, s0 +; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, s1 +; GFX1250TRUE16-NEXT: s_lshr_b32 s8, s3, 16 +; GFX1250TRUE16-NEXT: s_lshr_b32 s0, s2, 16 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.h, s8, v0.l, s6 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, s0, v0.h, s4 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, s2, v1.l, vcc_lo +; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.l, s3, v1.h, s5 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250TRUE16-NEXT: v_readfirstlane_b32 s0, v0 +; GFX1250TRUE16-NEXT: v_readfirstlane_b32 s1, v2 +; GFX1250TRUE16-NEXT: ; return to shader part epilog +; +; GFX1250FAKE16-LABEL: s_vselect_v4bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_lshr_b32 s4, s1, 16 +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v3 +; GFX1250FAKE16-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s1 +; GFX1250FAKE16-NEXT: s_lshr_b32 s4, s3, 16 +; GFX1250FAKE16-NEXT: s_lshr_b32 s5, s0, 16 +; GFX1250FAKE16-NEXT: v_mov_b32_e32 v6, s0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v3, s4, v4, vcc_lo +; GFX1250FAKE16-NEXT: v_mov_b32_e32 v4, s5 +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX1250FAKE16-NEXT: s_lshr_b32 s0, s2, 16 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1) +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v1, s0, v4, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, s2, v6, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v2, s3, v5, vcc_lo +; GFX1250FAKE16-NEXT: v_readfirstlane_b32 s0, v0 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x5040100 +; GFX1250FAKE16-NEXT: v_readfirstlane_b32 s1, v1 +; GFX1250FAKE16-NEXT: ; return to shader part epilog %cond = icmp eq <4 x i32> %c, zeroinitializer %op = select <4 x i1> %cond, <4 x bfloat> %a, <4 x bfloat> %b %cast = bitcast <4 x bfloat> %op to <2 x i32> @@ -45787,27 +46821,49 @@ define <4 x bfloat> @v_vselect_v4bf16(<4 x i1> %cond, <4 x bfloat> %a, <4 x bflo ; GFX11FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x5040100 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_vselect_v4bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX1250-NEXT: v_dual_lshrrev_b32 v8, 16, v4 :: v_dual_bitop2_b32 v1, 1, v1 bitop3:0x40 -; GFX1250-NEXT: v_dual_lshrrev_b32 v9, 16, v6 :: v_dual_bitop2_b32 v3, 1, v3 bitop3:0x40 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2 -; GFX1250-NEXT: v_dual_cndmask_b32 v2, v7, v5, vcc_lo :: v_dual_bitop2_b32 v0, 1, v0 bitop3:0x40 -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX1250-NEXT: v_dual_lshrrev_b32 v7, 16, v7 :: v_dual_lshrrev_b32 v5, 16, v5 -; GFX1250-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX1250-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3 -; GFX1250-NEXT: v_cndmask_b32_e32 v3, v7, v5, vcc_lo -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v1, v3, v2, 0x5040100 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_vselect_v4bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_and_b16 v0.h, 1, v2.l +; GFX1250TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l +; GFX1250TRUE16-NEXT: v_and_b16 v1.l, 1, v1.l +; GFX1250TRUE16-NEXT: v_and_b16 v1.h, 1, v3.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 1, v1.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 1, v1.h +; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.l, v7.l, v5.l, vcc_lo +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, v6.l, v4.l, s0 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, v6.h, v4.h, s1 +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.h, v7.h, v5.h, s2 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_vselect_v4bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v2, 1, v2 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v8, 16, v4 :: v_dual_bitop2_b32 v1, 1, v1 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v9, 16, v6 :: v_dual_bitop2_b32 v3, 1, v3 bitop3:0x40 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2 +; GFX1250FAKE16-NEXT: v_dual_cndmask_b32 v2, v7, v5, vcc_lo :: v_dual_bitop2_b32 v0, 1, v0 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v7, 16, v7 :: v_dual_lshrrev_b32 v5, 16, v5 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v3, v7, v5, vcc_lo +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x5040100 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = select <4 x i1> %cond, <4 x bfloat> %a, <4 x bfloat> %b ret <4 x bfloat> %op } @@ -46161,45 +47217,77 @@ define <8 x bfloat> @v_vselect_v8bf16(<8 x i1> %cond, <8 x bfloat> %a, <8 x bflo ; GFX11FAKE16-NEXT: v_perm_b32 v3, v7, v6, 0x5040100 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_vselect_v8bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_and_b32_e32 v6, 1, v6 -; GFX1250-NEXT: v_and_b32_e32 v4, 1, v4 -; GFX1250-NEXT: v_dual_lshrrev_b32 v17, 16, v14 :: v_dual_bitop2_b32 v5, 1, v5 bitop3:0x40 -; GFX1250-NEXT: v_dual_lshrrev_b32 v16, 16, v10 :: v_dual_bitop2_b32 v3, 1, v3 bitop3:0x40 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6 -; GFX1250-NEXT: v_and_b32_e32 v1, 1, v1 -; GFX1250-NEXT: v_dual_cndmask_b32 v6, v15, v11, vcc_lo :: v_dual_bitop2_b32 v0, 1, v0 bitop3:0x40 -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4 -; GFX1250-NEXT: v_and_b32_e32 v7, 1, v7 -; GFX1250-NEXT: v_lshrrev_b32_e32 v11, 16, v11 -; GFX1250-NEXT: v_dual_cndmask_b32 v4, v14, v10 :: v_dual_lshrrev_b32 v15, 16, v15 -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5 -; GFX1250-NEXT: v_dual_lshrrev_b32 v14, 16, v12 :: v_dual_bitop2_b32 v2, 1, v2 bitop3:0x40 -; GFX1250-NEXT: v_lshrrev_b32_e32 v10, 16, v8 -; GFX1250-NEXT: v_cndmask_b32_e32 v5, v17, v16, vcc_lo -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2 -; GFX1250-NEXT: v_cndmask_b32_e32 v2, v13, v9, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX1250-NEXT: v_lshrrev_b32_e32 v9, 16, v9 -; GFX1250-NEXT: v_dual_cndmask_b32 v0, v12, v8 :: v_dual_lshrrev_b32 v13, 16, v13 -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX1250-NEXT: v_cndmask_b32_e32 v1, v14, v10, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX1250-NEXT: v_cndmask_b32_e32 v3, v13, v9, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7 -; GFX1250-NEXT: v_cndmask_b32_e32 v7, v15, v11, vcc_lo -; GFX1250-NEXT: v_perm_b32 v1, v3, v2, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v2, v5, v4, 0x5040100 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX1250-NEXT: v_perm_b32 v3, v7, v6, 0x5040100 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_vselect_v8bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l +; GFX1250TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l +; GFX1250TRUE16-NEXT: v_and_b16 v1.l, 1, v3.l +; GFX1250TRUE16-NEXT: v_and_b16 v1.h, 1, v5.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.l +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 1, v1.l +; GFX1250TRUE16-NEXT: v_and_b16 v0.l, 1, v6.l +; GFX1250TRUE16-NEXT: v_and_b16 v0.h, 1, v4.l +; GFX1250TRUE16-NEXT: v_and_b16 v1.l, 1, v2.l +; GFX1250TRUE16-NEXT: v_and_b16 v2.l, 1, v7.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 1, v1.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 1, v0.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 1, v0.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 1, v1.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 1, v2.l +; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, v12.l, v8.l, s0 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v3.l, v15.l, v11.l, s2 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.l, v14.l, v10.l, s3 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.l, v13.l, v9.l, s4 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, v12.h, v8.h, vcc_lo +; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.h, v13.h, v9.h, s1 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.h, v14.h, v10.h, s5 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v3.h, v15.h, v11.h, s6 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_vselect_v8bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v6, 1, v6 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v4, 1, v4 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v17, 16, v14 :: v_dual_bitop2_b32 v5, 1, v5 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v16, 16, v10 :: v_dual_bitop2_b32 v3, 1, v3 bitop3:0x40 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v1, 1, v1 +; GFX1250FAKE16-NEXT: v_dual_cndmask_b32 v6, v15, v11, vcc_lo :: v_dual_bitop2_b32 v0, 1, v0 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v7, 1, v7 +; GFX1250FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11 +; GFX1250FAKE16-NEXT: v_dual_cndmask_b32 v4, v14, v10 :: v_dual_lshrrev_b32 v15, 16, v15 +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v14, 16, v12 :: v_dual_bitop2_b32 v2, 1, v2 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v8 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v5, v17, v16, vcc_lo +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v2, v13, v9, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX1250FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9 +; GFX1250FAKE16-NEXT: v_dual_cndmask_b32 v0, v12, v8 :: v_dual_lshrrev_b32 v13, 16, v13 +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v1, v14, v10, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v3, v13, v9, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v7, v15, v11, vcc_lo +; GFX1250FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v2, v5, v4, 0x5040100 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_perm_b32 v3, v7, v6, 0x5040100 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = select <8 x i1> %cond, <8 x bfloat> %a, <8 x bfloat> %b ret <8 x bfloat> %op } @@ -46939,73 +48027,129 @@ define <16 x bfloat> @v_vselect_v16bf16(<16 x i1> %cond, <16 x bfloat> %a, <16 x ; GFX11FAKE16-NEXT: v_perm_b32 v7, v15, v14, 0x5040100 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_vselect_v16bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: scratch_load_b32 v31, off, s32 -; GFX1250-NEXT: v_dual_lshrrev_b32 v52, 16, v25 :: v_dual_bitop2_b32 v12, 1, v12 bitop3:0x40 -; GFX1250-NEXT: v_dual_lshrrev_b32 v53, 16, v16 :: v_dual_bitop2_b32 v13, 1, v13 bitop3:0x40 -; GFX1250-NEXT: v_dual_lshrrev_b32 v33, 16, v22 :: v_dual_bitop2_b32 v0, 1, v0 bitop3:0x40 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12 -; GFX1250-NEXT: v_dual_lshrrev_b32 v34, 16, v30 :: v_dual_bitop2_b32 v3, 1, v3 bitop3:0x40 -; GFX1250-NEXT: v_dual_lshrrev_b32 v51, 16, v17 :: v_dual_bitop2_b32 v10, 1, v10 bitop3:0x40 -; GFX1250-NEXT: v_cndmask_b32_e32 v12, v30, v22, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13 -; GFX1250-NEXT: v_dual_lshrrev_b32 v50, 16, v26 :: v_dual_bitop2_b32 v11, 1, v11 bitop3:0x40 -; GFX1250-NEXT: v_and_b32_e32 v14, 1, v14 -; GFX1250-NEXT: v_dual_lshrrev_b32 v35, 16, v21 :: v_dual_bitop2_b32 v2, 1, v2 bitop3:0x40 -; GFX1250-NEXT: v_cndmask_b32_e32 v13, v34, v33, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10 -; GFX1250-NEXT: v_dual_lshrrev_b32 v36, 16, v29 :: v_dual_bitop2_b32 v4, 1, v4 bitop3:0x40 -; GFX1250-NEXT: v_dual_lshrrev_b32 v49, 16, v18 :: v_dual_bitop2_b32 v8, 1, v8 bitop3:0x40 -; GFX1250-NEXT: v_cndmask_b32_e32 v10, v29, v21, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11 -; GFX1250-NEXT: v_dual_lshrrev_b32 v37, 16, v20 :: v_dual_bitop2_b32 v5, 1, v5 bitop3:0x40 -; GFX1250-NEXT: v_dual_lshrrev_b32 v38, 16, v28 :: v_dual_bitop2_b32 v7, 1, v7 bitop3:0x40 -; GFX1250-NEXT: v_dual_lshrrev_b32 v48, 16, v27 :: v_dual_bitop2_b32 v9, 1, v9 bitop3:0x40 -; GFX1250-NEXT: v_cndmask_b32_e32 v11, v36, v35, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8 -; GFX1250-NEXT: v_dual_lshrrev_b32 v39, 16, v19 :: v_dual_bitop2_b32 v6, 1, v6 bitop3:0x40 -; GFX1250-NEXT: v_dual_lshrrev_b32 v32, 16, v23 :: v_dual_bitop2_b32 v1, 1, v1 bitop3:0x40 -; GFX1250-NEXT: v_cndmask_b32_e32 v8, v28, v20, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9 -; GFX1250-NEXT: v_dual_lshrrev_b32 v54, 16, v24 :: v_dual_bitop2_b32 v15, 1, v15 bitop3:0x40 -; GFX1250-NEXT: v_cndmask_b32_e32 v9, v38, v37, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6 -; GFX1250-NEXT: v_cndmask_b32_e32 v6, v27, v19, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4 -; GFX1250-NEXT: v_cndmask_b32_e32 v4, v26, v18, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2 -; GFX1250-NEXT: v_cndmask_b32_e32 v2, v25, v17, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3 -; GFX1250-NEXT: v_cndmask_b32_e32 v3, v52, v51, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX1250-NEXT: v_cndmask_b32_e32 v0, v24, v16, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX1250-NEXT: v_cndmask_b32_e32 v1, v54, v53, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5 -; GFX1250-NEXT: v_cndmask_b32_e32 v5, v50, v49, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX1250-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v1, v3, v2, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v2, v5, v4, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v4, v9, v8, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v5, v11, v10, 0x5040100 -; GFX1250-NEXT: s_wait_loadcnt 0x0 -; GFX1250-NEXT: v_lshrrev_b32_e32 v3, 16, v31 -; GFX1250-NEXT: v_cndmask_b32_e32 v7, v48, v39, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14 -; GFX1250-NEXT: v_cndmask_b32_e32 v14, v31, v23, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v15 -; GFX1250-NEXT: v_cndmask_b32_e32 v15, v3, v32, vcc_lo -; GFX1250-NEXT: v_perm_b32 v3, v7, v6, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v6, v13, v12, 0x5040100 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX1250-NEXT: v_perm_b32 v7, v15, v14, 0x5040100 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_vselect_v16bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: scratch_load_b32 v31, off, s32 +; GFX1250TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l +; GFX1250TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l +; GFX1250TRUE16-NEXT: v_and_b16 v1.l, 1, v3.l +; GFX1250TRUE16-NEXT: v_and_b16 v1.h, 1, v2.l +; GFX1250TRUE16-NEXT: v_and_b16 v2.l, 1, v5.l +; GFX1250TRUE16-NEXT: v_and_b16 v2.h, 1, v4.l +; GFX1250TRUE16-NEXT: v_and_b16 v3.l, 1, v7.l +; GFX1250TRUE16-NEXT: v_and_b16 v3.h, 1, v6.l +; GFX1250TRUE16-NEXT: v_and_b16 v4.l, 1, v9.l +; GFX1250TRUE16-NEXT: v_and_b16 v4.h, 1, v8.l +; GFX1250TRUE16-NEXT: v_and_b16 v5.l, 1, v11.l +; GFX1250TRUE16-NEXT: v_and_b16 v5.h, 1, v10.l +; GFX1250TRUE16-NEXT: v_and_b16 v6.l, 1, v13.l +; GFX1250TRUE16-NEXT: v_and_b16 v6.h, 1, v12.l +; GFX1250TRUE16-NEXT: v_and_b16 v7.l, 1, v15.l +; GFX1250TRUE16-NEXT: v_and_b16 v7.h, 1, v14.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v0.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 1, v1.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 1, v1.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 1, v2.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 1, v2.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 1, v3.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 1, v3.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 1, v4.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 1, v4.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 1, v5.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 1, v6.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 1, v6.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 1, v5.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 1, v7.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 1, v7.h +; GFX1250TRUE16-NEXT: v_cndmask_b16 v6.l, v30.l, v22.l, s10 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v6.h, v30.h, v22.h, s11 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v5.l, v29.l, v21.l, s12 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v5.h, v29.h, v21.h, s9 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v4.l, v28.l, v20.l, s8 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v4.h, v28.h, v20.h, s7 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v3.l, v27.l, v19.l, s6 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v3.h, v27.h, v19.h, s5 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.l, v26.l, v18.l, s4 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.l, v25.l, v17.l, s2 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, v24.l, v16.l, s0 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, v24.h, v16.h, vcc_lo +; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.h, v25.h, v17.h, s1 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.h, v26.h, v18.h, s3 +; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v7.l, v31.l, v23.l, s14 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v7.h, v31.h, v23.h, s13 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_vselect_v16bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: scratch_load_b32 v31, off, s32 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v52, 16, v25 :: v_dual_bitop2_b32 v12, 1, v12 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v53, 16, v16 :: v_dual_bitop2_b32 v13, 1, v13 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v33, 16, v22 :: v_dual_bitop2_b32 v0, 1, v0 bitop3:0x40 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v34, 16, v30 :: v_dual_bitop2_b32 v3, 1, v3 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v51, 16, v17 :: v_dual_bitop2_b32 v10, 1, v10 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v12, v30, v22, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v50, 16, v26 :: v_dual_bitop2_b32 v11, 1, v11 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v14, 1, v14 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v35, 16, v21 :: v_dual_bitop2_b32 v2, 1, v2 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v13, v34, v33, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v36, 16, v29 :: v_dual_bitop2_b32 v4, 1, v4 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v49, 16, v18 :: v_dual_bitop2_b32 v8, 1, v8 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v10, v29, v21, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v37, 16, v20 :: v_dual_bitop2_b32 v5, 1, v5 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v38, 16, v28 :: v_dual_bitop2_b32 v7, 1, v7 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v48, 16, v27 :: v_dual_bitop2_b32 v9, 1, v9 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v11, v36, v35, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v39, 16, v19 :: v_dual_bitop2_b32 v6, 1, v6 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v32, 16, v23 :: v_dual_bitop2_b32 v1, 1, v1 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v8, v28, v20, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v54, 16, v24 :: v_dual_bitop2_b32 v15, 1, v15 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v9, v38, v37, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v6, v27, v19, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v4, v26, v18, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v2, v25, v17, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v3, v52, v51, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v0, v24, v16, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v1, v54, v53, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v5, v50, v49, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX1250FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v2, v5, v4, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v4, v9, v8, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v5, v11, v10, 0x5040100 +; GFX1250FAKE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v31 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v7, v48, v39, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v14, v31, v23, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v15 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v15, v3, v32, vcc_lo +; GFX1250FAKE16-NEXT: v_perm_b32 v3, v7, v6, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v6, v13, v12, 0x5040100 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX1250FAKE16-NEXT: v_perm_b32 v7, v15, v14, 0x5040100 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = select <16 x i1> %cond, <16 x bfloat> %a, <16 x bfloat> %b ret <16 x bfloat> %op } @@ -48861,177 +50005,330 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x ; GFX11FAKE16-NEXT: v_perm_b32 v15, v31, v30, 0x5040100 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_vselect_v32bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: s_clause 0x1b -; GFX1250-NEXT: scratch_load_b32 v31, off, s32 offset:60 -; GFX1250-NEXT: scratch_load_b32 v32, off, s32 offset:124 -; GFX1250-NEXT: scratch_load_u16 v33, off, s32 -; GFX1250-NEXT: scratch_load_b32 v34, off, s32 offset:128 -; GFX1250-NEXT: scratch_load_b32 v35, off, s32 offset:64 -; GFX1250-NEXT: scratch_load_b32 v36, off, s32 offset:120 -; GFX1250-NEXT: scratch_load_b32 v37, off, s32 offset:56 -; GFX1250-NEXT: scratch_load_b32 v38, off, s32 offset:116 -; GFX1250-NEXT: scratch_load_b32 v39, off, s32 offset:52 -; GFX1250-NEXT: scratch_load_b32 v48, off, s32 offset:112 -; GFX1250-NEXT: scratch_load_b32 v49, off, s32 offset:48 -; GFX1250-NEXT: scratch_load_b32 v50, off, s32 offset:108 -; GFX1250-NEXT: scratch_load_b32 v51, off, s32 offset:44 -; GFX1250-NEXT: scratch_load_b32 v52, off, s32 offset:104 -; GFX1250-NEXT: scratch_load_b32 v53, off, s32 offset:40 -; GFX1250-NEXT: scratch_load_b32 v54, off, s32 offset:100 -; GFX1250-NEXT: scratch_load_b32 v55, off, s32 offset:36 -; GFX1250-NEXT: scratch_load_b32 v64, off, s32 offset:76 -; GFX1250-NEXT: scratch_load_b32 v65, off, s32 offset:12 -; GFX1250-NEXT: scratch_load_b32 v66, off, s32 offset:96 -; GFX1250-NEXT: scratch_load_b32 v67, off, s32 offset:32 -; GFX1250-NEXT: scratch_load_b32 v68, off, s32 offset:80 -; GFX1250-NEXT: scratch_load_b32 v69, off, s32 offset:84 -; GFX1250-NEXT: scratch_load_b32 v70, off, s32 offset:92 -; GFX1250-NEXT: scratch_load_b32 v71, off, s32 offset:28 -; GFX1250-NEXT: scratch_load_b32 v80, off, s32 offset:20 -; GFX1250-NEXT: scratch_load_b32 v81, off, s32 offset:88 -; GFX1250-NEXT: scratch_load_b32 v82, off, s32 offset:24 -; GFX1250-NEXT: v_and_b32_e32 v30, 1, v30 -; GFX1250-NEXT: v_and_b32_e32 v29, 1, v29 -; GFX1250-NEXT: v_and_b32_e32 v26, 1, v26 -; GFX1250-NEXT: v_and_b32_e32 v24, 1, v24 -; GFX1250-NEXT: v_and_b32_e32 v22, 1, v22 -; GFX1250-NEXT: v_and_b32_e32 v20, 1, v20 -; GFX1250-NEXT: v_and_b32_e32 v18, 1, v18 -; GFX1250-NEXT: v_and_b32_e32 v16, 1, v16 -; GFX1250-NEXT: v_and_b32_e32 v10, 1, v10 -; GFX1250-NEXT: v_and_b32_e32 v6, 1, v6 -; GFX1250-NEXT: v_and_b32_e32 v4, 1, v4 -; GFX1250-NEXT: v_and_b32_e32 v1, 1, v1 -; GFX1250-NEXT: v_and_b32_e32 v3, 1, v3 -; GFX1250-NEXT: v_and_b32_e32 v5, 1, v5 -; GFX1250-NEXT: v_and_b32_e32 v23, 1, v23 -; GFX1250-NEXT: v_and_b32_e32 v9, 1, v9 -; GFX1250-NEXT: v_and_b32_e32 v13, 1, v13 -; GFX1250-NEXT: v_and_b32_e32 v15, 1, v15 -; GFX1250-NEXT: v_and_b32_e32 v21, 1, v21 -; GFX1250-NEXT: v_and_b32_e32 v11, 1, v11 -; GFX1250-NEXT: v_and_b32_e32 v19, 1, v19 -; GFX1250-NEXT: s_wait_loadcnt 0x1a -; GFX1250-NEXT: v_dual_lshrrev_b32 v83, 16, v32 :: v_dual_bitop2_b32 v17, 1, v17 bitop3:0x40 -; GFX1250-NEXT: v_cmp_eq_u32_e64 s1, 1, v30 -; GFX1250-NEXT: v_and_b32_e32 v28, 1, v28 -; GFX1250-NEXT: s_wait_loadcnt 0x17 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX1250-NEXT: v_dual_cndmask_b32 v30, v34, v35, s1 :: v_dual_bitop2_b32 v33, 1, v33 bitop3:0x40 -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v28 -; GFX1250-NEXT: v_lshrrev_b32_e32 v28, 16, v31 -; GFX1250-NEXT: v_cmp_eq_u32_e64 s0, 1, v29 -; GFX1250-NEXT: scratch_load_b32 v29, off, s32 offset:16 -; GFX1250-NEXT: v_dual_lshrrev_b32 v35, 16, v35 :: v_dual_lshrrev_b32 v34, 16, v34 -; GFX1250-NEXT: v_cndmask_b32_e32 v31, v32, v31, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v33 -; GFX1250-NEXT: scratch_load_b32 v32, off, s32 offset:72 -; GFX1250-NEXT: v_cndmask_b32_e64 v28, v83, v28, s0 -; GFX1250-NEXT: scratch_load_b32 v83, off, s32 offset:4 -; GFX1250-NEXT: v_cndmask_b32_e32 v34, v34, v35, vcc_lo -; GFX1250-NEXT: s_clause 0x1 -; GFX1250-NEXT: scratch_load_b32 v35, off, s32 offset:68 -; GFX1250-NEXT: scratch_load_b32 v33, off, s32 offset:8 -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v26 -; GFX1250-NEXT: s_wait_loadcnt 0x1a -; GFX1250-NEXT: v_dual_cndmask_b32 v26, v36, v37, vcc_lo :: v_dual_bitop2_b32 v0, 1, v0 bitop3:0x40 -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v24 -; GFX1250-NEXT: v_dual_lshrrev_b32 v37, 16, v37 :: v_dual_bitop2_b32 v2, 1, v2 bitop3:0x40 -; GFX1250-NEXT: s_wait_loadcnt 0x18 -; GFX1250-NEXT: v_dual_lshrrev_b32 v36, 16, v36 :: v_dual_cndmask_b32 v24, v38, v39, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v22 -; GFX1250-NEXT: v_dual_lshrrev_b32 v38, 16, v38 :: v_dual_bitop2_b32 v7, 1, v7 bitop3:0x40 -; GFX1250-NEXT: s_wait_loadcnt 0x16 -; GFX1250-NEXT: v_dual_cndmask_b32 v22, v48, v49 :: v_dual_lshrrev_b32 v39, 16, v39 -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v20 -; GFX1250-NEXT: v_dual_lshrrev_b32 v49, 16, v49 :: v_dual_bitop2_b32 v8, 1, v8 bitop3:0x40 -; GFX1250-NEXT: s_wait_loadcnt 0x14 -; GFX1250-NEXT: v_dual_lshrrev_b32 v48, 16, v48 :: v_dual_cndmask_b32 v20, v50, v51, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v18 -; GFX1250-NEXT: v_dual_lshrrev_b32 v51, 16, v51 :: v_dual_bitop2_b32 v12, 1, v12 bitop3:0x40 -; GFX1250-NEXT: s_wait_loadcnt 0x12 -; GFX1250-NEXT: v_dual_lshrrev_b32 v50, 16, v50 :: v_dual_cndmask_b32 v18, v52, v53, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16 -; GFX1250-NEXT: v_dual_lshrrev_b32 v53, 16, v53 :: v_dual_bitop2_b32 v14, 1, v14 bitop3:0x40 -; GFX1250-NEXT: s_wait_loadcnt 0x10 -; GFX1250-NEXT: v_dual_lshrrev_b32 v52, 16, v52 :: v_dual_cndmask_b32 v16, v54, v55, vcc_lo -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14 -; GFX1250-NEXT: v_dual_lshrrev_b32 v55, 16, v55 :: v_dual_lshrrev_b32 v54, 16, v54 -; GFX1250-NEXT: s_wait_loadcnt 0xc -; GFX1250-NEXT: v_cndmask_b32_e32 v14, v66, v67, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12 -; GFX1250-NEXT: v_dual_lshrrev_b32 v67, 16, v67 :: v_dual_lshrrev_b32 v66, 16, v66 -; GFX1250-NEXT: s_wait_loadcnt 0x8 -; GFX1250-NEXT: v_cndmask_b32_e32 v12, v70, v71, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10 -; GFX1250-NEXT: v_dual_lshrrev_b32 v70, 16, v70 :: v_dual_bitop2_b32 v25, 1, v25 bitop3:0x40 -; GFX1250-NEXT: s_wait_loadcnt 0x5 -; GFX1250-NEXT: v_dual_cndmask_b32 v10, v81, v82 :: v_dual_lshrrev_b32 v71, 16, v71 -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8 -; GFX1250-NEXT: v_dual_lshrrev_b32 v82, 16, v82 :: v_dual_bitop2_b32 v27, 1, v27 bitop3:0x40 -; GFX1250-NEXT: v_dual_cndmask_b32 v8, v69, v80 :: v_dual_lshrrev_b32 v81, 16, v81 -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6 -; GFX1250-NEXT: v_dual_lshrrev_b32 v80, 16, v80 :: v_dual_lshrrev_b32 v69, 16, v69 -; GFX1250-NEXT: s_wait_loadcnt 0x4 -; GFX1250-NEXT: v_dual_cndmask_b32 v6, v68, v29 :: v_dual_lshrrev_b32 v29, 16, v29 -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4 -; GFX1250-NEXT: v_dual_lshrrev_b32 v68, 16, v68 :: v_dual_cndmask_b32 v4, v64, v65, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2 -; GFX1250-NEXT: v_dual_lshrrev_b32 v65, 16, v65 :: v_dual_lshrrev_b32 v64, 16, v64 -; GFX1250-NEXT: s_wait_loadcnt 0x0 -; GFX1250-NEXT: v_dual_cndmask_b32 v2, v32, v33 :: v_dual_lshrrev_b32 v33, 16, v33 -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX1250-NEXT: v_dual_lshrrev_b32 v32, 16, v32 :: v_dual_cndmask_b32 v0, v35, v83, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v27 -; GFX1250-NEXT: v_dual_lshrrev_b32 v83, 16, v83 :: v_dual_cndmask_b32 v27, v36, v37, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v25 -; GFX1250-NEXT: v_cndmask_b32_e32 v25, v38, v39, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v23 -; GFX1250-NEXT: v_dual_lshrrev_b32 v35, 16, v35 :: v_dual_cndmask_b32 v23, v48, v49, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v21 -; GFX1250-NEXT: v_cndmask_b32_e32 v21, v50, v51, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v19 -; GFX1250-NEXT: v_cndmask_b32_e32 v19, v52, v53, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v17 -; GFX1250-NEXT: v_cndmask_b32_e32 v17, v54, v55, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v15 -; GFX1250-NEXT: v_cndmask_b32_e32 v15, v66, v67, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13 -; GFX1250-NEXT: v_cndmask_b32_e32 v13, v70, v71, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11 -; GFX1250-NEXT: v_cndmask_b32_e32 v11, v81, v82, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7 -; GFX1250-NEXT: v_cndmask_b32_e32 v7, v68, v29, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3 -; GFX1250-NEXT: v_cndmask_b32_e32 v3, v32, v33, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX1250-NEXT: v_cndmask_b32_e32 v1, v35, v83, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5 -; GFX1250-NEXT: v_cndmask_b32_e32 v5, v64, v65, vcc_lo -; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9 -; GFX1250-NEXT: v_cndmask_b32_e32 v9, v69, v80, vcc_lo -; GFX1250-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v1, v3, v2, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v2, v5, v4, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v3, v7, v6, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v4, v9, v8, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v5, v11, v10, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v6, v13, v12, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v7, v15, v14, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v8, v17, v16, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v9, v19, v18, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v10, v21, v20, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v11, v23, v22, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v12, v25, v24, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v13, v27, v26, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v14, v28, v31, 0x5040100 -; GFX1250-NEXT: v_perm_b32 v15, v34, v30, 0x5040100 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_vselect_v32bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: s_clause 0x20 +; GFX1250TRUE16-NEXT: scratch_load_u16 v31, off, s32 +; GFX1250TRUE16-NEXT: scratch_load_b32 v32, off, s32 offset:68 +; GFX1250TRUE16-NEXT: scratch_load_b32 v33, off, s32 offset:72 +; GFX1250TRUE16-NEXT: scratch_load_b32 v34, off, s32 offset:76 +; GFX1250TRUE16-NEXT: scratch_load_b32 v35, off, s32 offset:124 +; GFX1250TRUE16-NEXT: scratch_load_b32 v36, off, s32 offset:128 +; GFX1250TRUE16-NEXT: scratch_load_b32 v37, off, s32 offset:64 +; GFX1250TRUE16-NEXT: scratch_load_b32 v38, off, s32 offset:60 +; GFX1250TRUE16-NEXT: scratch_load_b32 v39, off, s32 offset:120 +; GFX1250TRUE16-NEXT: scratch_load_b32 v48, off, s32 offset:56 +; GFX1250TRUE16-NEXT: scratch_load_b32 v49, off, s32 offset:116 +; GFX1250TRUE16-NEXT: scratch_load_b32 v50, off, s32 offset:52 +; GFX1250TRUE16-NEXT: scratch_load_b32 v51, off, s32 offset:112 +; GFX1250TRUE16-NEXT: scratch_load_b32 v52, off, s32 offset:48 +; GFX1250TRUE16-NEXT: scratch_load_b32 v53, off, s32 offset:108 +; GFX1250TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:44 +; GFX1250TRUE16-NEXT: scratch_load_b32 v55, off, s32 offset:104 +; GFX1250TRUE16-NEXT: scratch_load_b32 v64, off, s32 offset:40 +; GFX1250TRUE16-NEXT: scratch_load_b32 v65, off, s32 offset:100 +; GFX1250TRUE16-NEXT: scratch_load_b32 v66, off, s32 offset:36 +; GFX1250TRUE16-NEXT: scratch_load_b32 v67, off, s32 offset:96 +; GFX1250TRUE16-NEXT: scratch_load_b32 v68, off, s32 offset:32 +; GFX1250TRUE16-NEXT: scratch_load_b32 v69, off, s32 offset:92 +; GFX1250TRUE16-NEXT: scratch_load_b32 v70, off, s32 offset:28 +; GFX1250TRUE16-NEXT: scratch_load_b32 v71, off, s32 offset:88 +; GFX1250TRUE16-NEXT: scratch_load_b32 v80, off, s32 offset:24 +; GFX1250TRUE16-NEXT: scratch_load_b32 v81, off, s32 offset:84 +; GFX1250TRUE16-NEXT: scratch_load_b32 v82, off, s32 offset:20 +; GFX1250TRUE16-NEXT: scratch_load_b32 v83, off, s32 offset:80 +; GFX1250TRUE16-NEXT: scratch_load_b32 v84, off, s32 offset:16 +; GFX1250TRUE16-NEXT: scratch_load_b32 v85, off, s32 offset:12 +; GFX1250TRUE16-NEXT: scratch_load_b32 v86, off, s32 offset:8 +; GFX1250TRUE16-NEXT: scratch_load_b32 v87, off, s32 offset:4 +; GFX1250TRUE16-NEXT: v_and_b16 v0.h, 1, v1.l +; GFX1250TRUE16-NEXT: v_and_b16 v0.l, 1, v0.l +; GFX1250TRUE16-NEXT: v_and_b16 v1.l, 1, v3.l +; GFX1250TRUE16-NEXT: v_and_b16 v1.h, 1, v2.l +; GFX1250TRUE16-NEXT: v_and_b16 v2.l, 1, v9.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 1, v0.h +; GFX1250TRUE16-NEXT: v_and_b16 v0.h, 1, v4.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 1, v0.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 1, v1.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 1, v1.h +; GFX1250TRUE16-NEXT: v_and_b16 v0.l, 1, v5.l +; GFX1250TRUE16-NEXT: v_and_b16 v1.l, 1, v7.l +; GFX1250TRUE16-NEXT: v_and_b16 v1.h, 1, v6.l +; GFX1250TRUE16-NEXT: v_and_b16 v2.h, 1, v8.l +; GFX1250TRUE16-NEXT: v_and_b16 v3.l, 1, v11.l +; GFX1250TRUE16-NEXT: v_and_b16 v3.h, 1, v10.l +; GFX1250TRUE16-NEXT: v_and_b16 v4.l, 1, v13.l +; GFX1250TRUE16-NEXT: v_and_b16 v4.h, 1, v12.l +; GFX1250TRUE16-NEXT: v_and_b16 v5.l, 1, v15.l +; GFX1250TRUE16-NEXT: v_and_b16 v5.h, 1, v14.l +; GFX1250TRUE16-NEXT: v_and_b16 v6.l, 1, v17.l +; GFX1250TRUE16-NEXT: v_and_b16 v6.h, 1, v16.l +; GFX1250TRUE16-NEXT: v_and_b16 v7.l, 1, v19.l +; GFX1250TRUE16-NEXT: v_and_b16 v7.h, 1, v18.l +; GFX1250TRUE16-NEXT: v_and_b16 v8.l, 1, v21.l +; GFX1250TRUE16-NEXT: v_and_b16 v8.h, 1, v20.l +; GFX1250TRUE16-NEXT: v_and_b16 v9.l, 1, v23.l +; GFX1250TRUE16-NEXT: v_and_b16 v9.h, 1, v22.l +; GFX1250TRUE16-NEXT: v_and_b16 v10.l, 1, v25.l +; GFX1250TRUE16-NEXT: v_and_b16 v10.h, 1, v24.l +; GFX1250TRUE16-NEXT: v_and_b16 v11.l, 1, v27.l +; GFX1250TRUE16-NEXT: v_and_b16 v11.h, 1, v26.l +; GFX1250TRUE16-NEXT: v_and_b16 v12.l, 1, v29.l +; GFX1250TRUE16-NEXT: v_and_b16 v12.h, 1, v28.l +; GFX1250TRUE16-NEXT: v_and_b16 v13.l, 1, v30.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 1, v0.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 1, v0.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 1, v1.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 1, v1.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 1, v2.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 1, v2.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 1, v3.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 1, v3.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 1, v4.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 1, v4.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 1, v5.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 1, v5.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 1, v6.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 1, v6.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s17, 1, v7.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s18, 1, v7.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s19, 1, v8.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s20, 1, v8.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s21, 1, v9.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s22, 1, v9.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s23, 1, v10.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s24, 1, v10.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s25, 1, v11.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s26, 1, v13.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s27, 1, v12.h +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s28, 1, v12.l +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s29, 1, v11.h +; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x20 +; GFX1250TRUE16-NEXT: v_and_b16 v0.h, 1, v31.l +; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x1a +; GFX1250TRUE16-NEXT: v_cndmask_b16 v15.l, v36.l, v37.l, s26 +; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x19 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v14.l, v35.l, v38.l, s27 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v14.h, v35.h, v38.h, s28 +; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x17 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v13.l, v39.l, v48.l, s29 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v13.h, v39.h, v48.h, s25 +; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x15 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v12.l, v49.l, v50.l, s24 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v12.h, v49.h, v50.h, s23 +; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x13 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v11.l, v51.l, v52.l, s22 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v11.h, v51.h, v52.h, s21 +; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x11 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v10.l, v53.l, v54.l, s20 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v10.h, v53.h, v54.h, s19 +; GFX1250TRUE16-NEXT: s_wait_loadcnt 0xf +; GFX1250TRUE16-NEXT: v_cndmask_b16 v9.l, v55.l, v64.l, s18 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v9.h, v55.h, v64.h, s17 +; GFX1250TRUE16-NEXT: s_wait_loadcnt 0xd +; GFX1250TRUE16-NEXT: v_cndmask_b16 v8.l, v65.l, v66.l, s16 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v8.h, v65.h, v66.h, s15 +; GFX1250TRUE16-NEXT: s_wait_loadcnt 0xb +; GFX1250TRUE16-NEXT: v_cndmask_b16 v7.l, v67.l, v68.l, s14 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v7.h, v67.h, v68.h, s13 +; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x9 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v6.l, v69.l, v70.l, s12 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v6.h, v69.h, v70.h, s11 +; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x7 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v5.l, v71.l, v80.l, s10 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v5.h, v71.h, v80.h, s9 +; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x5 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v4.l, v81.l, v82.l, s8 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v4.h, v81.h, v82.h, s7 +; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x3 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v3.l, v83.l, v84.l, s6 +; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x2 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.l, v34.l, v85.l, s4 +; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x1 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.l, v33.l, v86.l, s2 +; GFX1250TRUE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, v32.l, v87.l, s1 +; GFX1250TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 1, v0.h +; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, v32.h, v87.h, vcc_lo +; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.h, v33.h, v86.h, s0 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.h, v34.h, v85.h, s3 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v3.h, v83.h, v84.h, s5 +; GFX1250TRUE16-NEXT: v_cndmask_b16 v15.h, v36.h, v37.h, s1 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_vselect_v32bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: s_clause 0x1b +; GFX1250FAKE16-NEXT: scratch_load_b32 v31, off, s32 offset:60 +; GFX1250FAKE16-NEXT: scratch_load_b32 v32, off, s32 offset:124 +; GFX1250FAKE16-NEXT: scratch_load_u16 v33, off, s32 +; GFX1250FAKE16-NEXT: scratch_load_b32 v34, off, s32 offset:128 +; GFX1250FAKE16-NEXT: scratch_load_b32 v35, off, s32 offset:64 +; GFX1250FAKE16-NEXT: scratch_load_b32 v36, off, s32 offset:120 +; GFX1250FAKE16-NEXT: scratch_load_b32 v37, off, s32 offset:56 +; GFX1250FAKE16-NEXT: scratch_load_b32 v38, off, s32 offset:116 +; GFX1250FAKE16-NEXT: scratch_load_b32 v39, off, s32 offset:52 +; GFX1250FAKE16-NEXT: scratch_load_b32 v48, off, s32 offset:112 +; GFX1250FAKE16-NEXT: scratch_load_b32 v49, off, s32 offset:48 +; GFX1250FAKE16-NEXT: scratch_load_b32 v50, off, s32 offset:108 +; GFX1250FAKE16-NEXT: scratch_load_b32 v51, off, s32 offset:44 +; GFX1250FAKE16-NEXT: scratch_load_b32 v52, off, s32 offset:104 +; GFX1250FAKE16-NEXT: scratch_load_b32 v53, off, s32 offset:40 +; GFX1250FAKE16-NEXT: scratch_load_b32 v54, off, s32 offset:100 +; GFX1250FAKE16-NEXT: scratch_load_b32 v55, off, s32 offset:36 +; GFX1250FAKE16-NEXT: scratch_load_b32 v64, off, s32 offset:76 +; GFX1250FAKE16-NEXT: scratch_load_b32 v65, off, s32 offset:12 +; GFX1250FAKE16-NEXT: scratch_load_b32 v66, off, s32 offset:96 +; GFX1250FAKE16-NEXT: scratch_load_b32 v67, off, s32 offset:32 +; GFX1250FAKE16-NEXT: scratch_load_b32 v68, off, s32 offset:80 +; GFX1250FAKE16-NEXT: scratch_load_b32 v69, off, s32 offset:84 +; GFX1250FAKE16-NEXT: scratch_load_b32 v70, off, s32 offset:92 +; GFX1250FAKE16-NEXT: scratch_load_b32 v71, off, s32 offset:28 +; GFX1250FAKE16-NEXT: scratch_load_b32 v80, off, s32 offset:20 +; GFX1250FAKE16-NEXT: scratch_load_b32 v81, off, s32 offset:88 +; GFX1250FAKE16-NEXT: scratch_load_b32 v82, off, s32 offset:24 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v30, 1, v30 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v29, 1, v29 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v26, 1, v26 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v24, 1, v24 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v22, 1, v22 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v20, 1, v20 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v18, 1, v18 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v16, 1, v16 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v10, 1, v10 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v6, 1, v6 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v4, 1, v4 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v1, 1, v1 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v3, 1, v3 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v5, 1, v5 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v23, 1, v23 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v9, 1, v9 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v13, 1, v13 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v15, 1, v15 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v21, 1, v21 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v11, 1, v11 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v19, 1, v19 +; GFX1250FAKE16-NEXT: s_wait_loadcnt 0x1a +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v83, 16, v32 :: v_dual_bitop2_b32 v17, 1, v17 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e64 s1, 1, v30 +; GFX1250FAKE16-NEXT: v_and_b32_e32 v28, 1, v28 +; GFX1250FAKE16-NEXT: s_wait_loadcnt 0x17 +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_dual_cndmask_b32 v30, v34, v35, s1 :: v_dual_bitop2_b32 v33, 1, v33 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v28 +; GFX1250FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v31 +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e64 s0, 1, v29 +; GFX1250FAKE16-NEXT: scratch_load_b32 v29, off, s32 offset:16 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v35, 16, v35 :: v_dual_lshrrev_b32 v34, 16, v34 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v31, v32, v31, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v33 +; GFX1250FAKE16-NEXT: scratch_load_b32 v32, off, s32 offset:72 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e64 v28, v83, v28, s0 +; GFX1250FAKE16-NEXT: scratch_load_b32 v83, off, s32 offset:4 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v34, v34, v35, vcc_lo +; GFX1250FAKE16-NEXT: s_clause 0x1 +; GFX1250FAKE16-NEXT: scratch_load_b32 v35, off, s32 offset:68 +; GFX1250FAKE16-NEXT: scratch_load_b32 v33, off, s32 offset:8 +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v26 +; GFX1250FAKE16-NEXT: s_wait_loadcnt 0x1a +; GFX1250FAKE16-NEXT: v_dual_cndmask_b32 v26, v36, v37, vcc_lo :: v_dual_bitop2_b32 v0, 1, v0 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v24 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v37, 16, v37 :: v_dual_bitop2_b32 v2, 1, v2 bitop3:0x40 +; GFX1250FAKE16-NEXT: s_wait_loadcnt 0x18 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v36, 16, v36 :: v_dual_cndmask_b32 v24, v38, v39, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v22 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v38, 16, v38 :: v_dual_bitop2_b32 v7, 1, v7 bitop3:0x40 +; GFX1250FAKE16-NEXT: s_wait_loadcnt 0x16 +; GFX1250FAKE16-NEXT: v_dual_cndmask_b32 v22, v48, v49 :: v_dual_lshrrev_b32 v39, 16, v39 +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v20 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v49, 16, v49 :: v_dual_bitop2_b32 v8, 1, v8 bitop3:0x40 +; GFX1250FAKE16-NEXT: s_wait_loadcnt 0x14 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v48, 16, v48 :: v_dual_cndmask_b32 v20, v50, v51, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v18 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v51, 16, v51 :: v_dual_bitop2_b32 v12, 1, v12 bitop3:0x40 +; GFX1250FAKE16-NEXT: s_wait_loadcnt 0x12 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v50, 16, v50 :: v_dual_cndmask_b32 v18, v52, v53, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v53, 16, v53 :: v_dual_bitop2_b32 v14, 1, v14 bitop3:0x40 +; GFX1250FAKE16-NEXT: s_wait_loadcnt 0x10 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v52, 16, v52 :: v_dual_cndmask_b32 v16, v54, v55, vcc_lo +; GFX1250FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v55, 16, v55 :: v_dual_lshrrev_b32 v54, 16, v54 +; GFX1250FAKE16-NEXT: s_wait_loadcnt 0xc +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v14, v66, v67, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v67, 16, v67 :: v_dual_lshrrev_b32 v66, 16, v66 +; GFX1250FAKE16-NEXT: s_wait_loadcnt 0x8 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v12, v70, v71, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v70, 16, v70 :: v_dual_bitop2_b32 v25, 1, v25 bitop3:0x40 +; GFX1250FAKE16-NEXT: s_wait_loadcnt 0x5 +; GFX1250FAKE16-NEXT: v_dual_cndmask_b32 v10, v81, v82 :: v_dual_lshrrev_b32 v71, 16, v71 +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v82, 16, v82 :: v_dual_bitop2_b32 v27, 1, v27 bitop3:0x40 +; GFX1250FAKE16-NEXT: v_dual_cndmask_b32 v8, v69, v80 :: v_dual_lshrrev_b32 v81, 16, v81 +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v80, 16, v80 :: v_dual_lshrrev_b32 v69, 16, v69 +; GFX1250FAKE16-NEXT: s_wait_loadcnt 0x4 +; GFX1250FAKE16-NEXT: v_dual_cndmask_b32 v6, v68, v29 :: v_dual_lshrrev_b32 v29, 16, v29 +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v68, 16, v68 :: v_dual_cndmask_b32 v4, v64, v65, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v65, 16, v65 :: v_dual_lshrrev_b32 v64, 16, v64 +; GFX1250FAKE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250FAKE16-NEXT: v_dual_cndmask_b32 v2, v32, v33 :: v_dual_lshrrev_b32 v33, 16, v33 +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v32, 16, v32 :: v_dual_cndmask_b32 v0, v35, v83, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v27 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v83, 16, v83 :: v_dual_cndmask_b32 v27, v36, v37, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v25 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v25, v38, v39, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v23 +; GFX1250FAKE16-NEXT: v_dual_lshrrev_b32 v35, 16, v35 :: v_dual_cndmask_b32 v23, v48, v49, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v21 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v21, v50, v51, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v19 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v19, v52, v53, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v17 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v17, v54, v55, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v15 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v15, v66, v67, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v13, v70, v71, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v11, v81, v82, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v7, v68, v29, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v3, v32, v33, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v1, v35, v83, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v5, v64, v65, vcc_lo +; GFX1250FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9 +; GFX1250FAKE16-NEXT: v_cndmask_b32_e32 v9, v69, v80, vcc_lo +; GFX1250FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v2, v5, v4, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v3, v7, v6, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v4, v9, v8, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v5, v11, v10, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v6, v13, v12, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v7, v15, v14, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v8, v17, v16, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v9, v19, v18, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v10, v21, v20, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v11, v23, v22, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v12, v25, v24, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v13, v27, v26, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v14, v28, v31, 0x5040100 +; GFX1250FAKE16-NEXT: v_perm_b32 v15, v34, v30, 0x5040100 +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = select <32 x i1> %cond, <32 x bfloat> %a, <32 x bfloat> %b ret <32 x bfloat> %op } @@ -49167,12 +50464,21 @@ define bfloat @v_fma_bf16(bfloat %a, bfloat %b, bfloat %c) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fma_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1] -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fma_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1] +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fma_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1] +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.fma.bf16(bfloat %a, bfloat %b, bfloat %c) ret bfloat %op } @@ -54791,12 +56097,21 @@ define bfloat @v_fmuladd_bf16(bfloat %a, bfloat %b, bfloat %c) { ; GFX11FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31] ; -; GFX1250-LABEL: v_fmuladd_bf16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1] -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250TRUE16-LABEL: v_fmuladd_bf16: +; GFX1250TRUE16: ; %bb.0: +; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250TRUE16-NEXT: v_fma_mix_f32_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1] +; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0 +; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250FAKE16-LABEL: v_fmuladd_bf16: +; GFX1250FAKE16: ; %bb.0: +; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250FAKE16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,1,1] +; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31] %op = call bfloat @llvm.fmuladd.bf16(bfloat %a, bfloat %b, bfloat %c) ret bfloat %op } @@ -55652,5 +56967,3 @@ define <4 x bfloat> @v_fmuladd_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, <4 x bfl %op = call <4 x bfloat> @llvm.fmuladd.v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, <4 x bfloat> %c) ret <4 x bfloat> %op } -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; GFX1250FAKE16: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll index 363a248..cbf6b66 100644 --- a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll +++ b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll @@ -1262,7 +1262,7 @@ define amdgpu_ps void @ps_mesa_i16(i16 %arg0) { ; GFX1250-TRUE16-LABEL: ps_mesa_i16: ; GFX1250-TRUE16: ; %bb.0: ; GFX1250-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v0.l -; GFX1250-TRUE16-NEXT: flat_store_b16 v[0:1], v0 +; GFX1250-TRUE16-NEXT: global_store_b16 v[0:1], v0, off ; GFX1250-TRUE16-NEXT: s_endpgm ; ; GFX1250-FAKE16-LABEL: ps_mesa_i16: @@ -3013,7 +3013,7 @@ define amdgpu_cs void @amdgpu_cs_v8i1(<8 x i1> %arg0) { ; GFX1250-TRUE16-NEXT: v_lshlrev_b16 v0.h, 4, v0.h ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v0.h, 15 bitop3:0xec -; GFX1250-TRUE16-NEXT: flat_store_b8 v[0:1], v0 +; GFX1250-TRUE16-NEXT: global_store_b8 v[0:1], v0, off ; GFX1250-TRUE16-NEXT: s_endpgm ; ; GFX1250-FAKE16-LABEL: amdgpu_cs_v8i1: @@ -3297,7 +3297,7 @@ define amdgpu_cs void @amdgpu_cs_v16i1(<16 x i1> %arg0) { ; GFX1250-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l ; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, v0.l, v0.h, 0xff bitop3:0xec -; GFX1250-TRUE16-NEXT: flat_store_b16 v[0:1], v0 +; GFX1250-TRUE16-NEXT: global_store_b16 v[0:1], v0, off ; GFX1250-TRUE16-NEXT: s_endpgm ; ; GFX1250-FAKE16-LABEL: amdgpu_cs_v16i1: diff --git a/llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll b/llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll index f706f53..eb40e5c 100644 --- a/llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll +++ b/llvm/test/CodeGen/AMDGPU/direct-indirect-call.ll @@ -35,6 +35,6 @@ define amdgpu_kernel void @test_direct_indirect_call() { ret void } ;. -; CHECK: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } ; CHECK: attributes #[[ATTR1]] = { "uniform-work-group-size"="false" } ;. diff --git a/llvm/test/CodeGen/AMDGPU/duplicate-attribute-indirect.ll b/llvm/test/CodeGen/AMDGPU/duplicate-attribute-indirect.ll index 8da204b..c02ff28 100644 --- a/llvm/test/CodeGen/AMDGPU/duplicate-attribute-indirect.ll +++ b/llvm/test/CodeGen/AMDGPU/duplicate-attribute-indirect.ll @@ -28,6 +28,6 @@ define amdgpu_kernel void @test_simple_indirect_call() #0 { attributes #0 = { "amdgpu-no-dispatch-id" } ;. -; ATTRIBUTOR_GCN: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; ATTRIBUTOR_GCN: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } ; ATTRIBUTOR_GCN: attributes #[[ATTR1]] = { "amdgpu-no-dispatch-id" "uniform-work-group-size"="false" } ;. diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll index 40d2765..b0dd187 100644 --- a/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll @@ -11,9 +11,9 @@ ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=-flat-for-global,-real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-SDAG-FAKE16 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=-flat-for-global,+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-GISEL-TRUE16 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=-flat-for-global,-real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-GISEL-FAKE16 %s -; TODO: FIXME-TRUE16 llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1250 -global-isel=0 -mattr=-flat-for-global,+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-SDAG-TRUE16 %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1250 -global-isel=0 -mattr=-flat-for-global,+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-SDAG-TRUE16 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1250 -global-isel=0 -mattr=-flat-for-global,-real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-SDAG-FAKE16 %s -; TODO: FIXME-TRUE16 llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1250 -global-isel=1 -mattr=-flat-for-global,+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-GISEL-TRUE16 %s +; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1250 -global-isel=1 -mattr=-flat-for-global,+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-GISEL-TRUE16 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1250 -global-isel=1 -mattr=-flat-for-global,-real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-GISEL-FAKE16 %s define amdgpu_kernel void @fptrunc_f32_to_f16( @@ -197,6 +197,24 @@ define amdgpu_kernel void @fptrunc_f32_to_f16( ; GFX11-GISEL-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; GFX11-GISEL-FAKE16-NEXT: s_endpgm ; +; GFX1250-SDAG-TRUE16-LABEL: fptrunc_f32_to_f16: +; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry +; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s10, s6 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s11, s7 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s8, s2 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s9, s3 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s4, s0 +; GFX1250-SDAG-TRUE16-NEXT: buffer_load_b32 v0, off, s[8:11], null +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 +; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], null +; GFX1250-SDAG-TRUE16-NEXT: s_endpgm +; ; GFX1250-SDAG-FAKE16-LABEL: fptrunc_f32_to_f16: ; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry ; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -215,6 +233,21 @@ define amdgpu_kernel void @fptrunc_f32_to_f16( ; GFX1250-SDAG-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], null ; GFX1250-SDAG-FAKE16-NEXT: s_endpgm ; +; GFX1250-GISEL-TRUE16-LABEL: fptrunc_f32_to_f16: +; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_xcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3) +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null +; GFX1250-GISEL-TRUE16-NEXT: s_endpgm +; ; GFX1250-GISEL-FAKE16-LABEL: fptrunc_f32_to_f16: ; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry ; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -419,6 +452,24 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_afn(ptr addrspace(1) %r, ; GFX11-GISEL-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; GFX11-GISEL-FAKE16-NEXT: s_endpgm ; +; GFX1250-SDAG-TRUE16-LABEL: fptrunc_f32_to_f16_afn: +; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry +; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s10, s6 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s11, s7 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s8, s2 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s9, s3 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s4, s0 +; GFX1250-SDAG-TRUE16-NEXT: buffer_load_b32 v0, off, s[8:11], null +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 +; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], null +; GFX1250-SDAG-TRUE16-NEXT: s_endpgm +; ; GFX1250-SDAG-FAKE16-LABEL: fptrunc_f32_to_f16_afn: ; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry ; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -437,6 +488,21 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_afn(ptr addrspace(1) %r, ; GFX1250-SDAG-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], null ; GFX1250-SDAG-FAKE16-NEXT: s_endpgm ; +; GFX1250-GISEL-TRUE16-LABEL: fptrunc_f32_to_f16_afn: +; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_xcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3) +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null +; GFX1250-GISEL-TRUE16-NEXT: s_endpgm +; ; GFX1250-GISEL-FAKE16-LABEL: fptrunc_f32_to_f16_afn: ; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry ; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -1160,6 +1226,73 @@ define amdgpu_kernel void @fptrunc_f64_to_f16( ; GFX11-GISEL-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; GFX11-GISEL-FAKE16-NEXT: s_endpgm ; +; GFX1250-SDAG-TRUE16-LABEL: fptrunc_f64_to_f16: +; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry +; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s10, s6 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s11, s7 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s8, s2 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s9, s3 +; GFX1250-SDAG-TRUE16-NEXT: buffer_load_b64 v[0:1], off, s[8:11], null +; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s2, v1 +; GFX1250-SDAG-TRUE16-NEXT: s_and_b32 s3, s2, 0x1ff +; GFX1250-SDAG-TRUE16-NEXT: s_lshr_b32 s5, s2, 8 +; GFX1250-SDAG-TRUE16-NEXT: v_or_b32_e32 v0, s3, v0 +; GFX1250-SDAG-TRUE16-NEXT: s_bfe_u32 s3, s2, 0xb0014 +; GFX1250-SDAG-TRUE16-NEXT: s_and_b32 s5, s5, 0xffe +; GFX1250-SDAG-TRUE16-NEXT: s_sub_co_i32 s4, 0x3f1, s3 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX1250-SDAG-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX1250-SDAG-TRUE16-NEXT: v_med3_i32 v1, s4, 0, 13 +; GFX1250-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s8, v1 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1250-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s4, v0 +; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s4, s5, s4 +; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s5, s4, 0x1000 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1250-SDAG-TRUE16-NEXT: s_lshr_b32 s9, s5, s8 +; GFX1250-SDAG-TRUE16-NEXT: s_lshl_b32 s8, s9, s8 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1) +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_lg_u32 s8, s5 +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s5, 1, 0 +; GFX1250-SDAG-TRUE16-NEXT: s_addk_co_i32 s3, 0xfc10 +; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s5, s9, s5 +; GFX1250-SDAG-TRUE16-NEXT: s_lshl_b32 s8, s3, 12 +; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s8, s4, s8 +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_lt_i32 s3, 1 +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s5, s5, s8 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1250-SDAG-TRUE16-NEXT: s_and_b32 s8, s5, 7 +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_gt_i32 s8, 5 +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s9, 1, 0 +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_eq_u32 s8, 3 +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s8, 1, 0 +; GFX1250-SDAG-TRUE16-NEXT: s_lshr_b32 s5, s5, 2 +; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s8, s8, s9 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1250-SDAG-TRUE16-NEXT: s_add_co_i32 s5, s5, s8 +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_lt_i32 s3, 31 +; GFX1250-SDAG-TRUE16-NEXT: s_movk_i32 s8, 0x7e00 +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s5, s5, 0x7c00 +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_lg_u32 s4, 0 +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s4, s8, 0x7c00 +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_eq_u32 s3, 0x40f +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s3, s4, s5 +; GFX1250-SDAG-TRUE16-NEXT: s_lshr_b32 s2, s2, 16 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s4, s0 +; GFX1250-SDAG-TRUE16-NEXT: s_and_b32 s2, s2, 0x8000 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1 +; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s2, s2, s3 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1250-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], null +; GFX1250-SDAG-TRUE16-NEXT: s_endpgm +; ; GFX1250-SDAG-FAKE16-LABEL: fptrunc_f64_to_f16: ; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry ; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -1227,6 +1360,63 @@ define amdgpu_kernel void @fptrunc_f64_to_f16( ; GFX1250-SDAG-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], null ; GFX1250-SDAG-FAKE16-NEXT: s_endpgm ; +; GFX1250-GISEL-TRUE16-LABEL: fptrunc_f64_to_f16: +; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_and_b32 s6, s3, 0x1ff +; GFX1250-GISEL-TRUE16-NEXT: s_bfe_u32 s4, s3, 0xb0014 +; GFX1250-GISEL-TRUE16-NEXT: s_lshr_b32 s5, s3, 8 +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s2, s6, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_addk_co_i32 s4, 0xfc10 +; GFX1250-GISEL-TRUE16-NEXT: s_and_b32 s5, s5, 0xffe +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_lg_u32 s2, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s2, 1, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s2, s5, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_lg_u32 s2, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s5, 1, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_sub_co_i32 s6, 1, s4 +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s8, s2, 0x1000 +; GFX1250-GISEL-TRUE16-NEXT: s_max_i32 s6, s6, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_lshl_b32 s7, s4, 12 +; GFX1250-GISEL-TRUE16-NEXT: s_min_i32 s6, s6, 13 +; GFX1250-GISEL-TRUE16-NEXT: s_lshl_b32 s5, s5, 9 +; GFX1250-GISEL-TRUE16-NEXT: s_lshr_b32 s9, s8, s6 +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s2, s2, s7 +; GFX1250-GISEL-TRUE16-NEXT: s_lshl_b32 s6, s9, s6 +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s5, s5, 0x7c00 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_lg_u32 s6, s8 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s6, 1, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s6, s9, s6 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_lt_i32 s4, 1 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s2, s6, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_and_b32 s6, s2, 7 +; GFX1250-GISEL-TRUE16-NEXT: s_lshr_b32 s2, s2, 2 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_eq_u32 s6, 3 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s7, 1, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_gt_i32 s6, 5 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s6, 1, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s6, s7, s6 +; GFX1250-GISEL-TRUE16-NEXT: s_add_co_i32 s2, s2, s6 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_gt_i32 s4, 30 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s2, 0x7c00, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_eq_u32 s4, 0x40f +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s2, s5, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_lshr_b32 s3, s3, 16 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1250-GISEL-TRUE16-NEXT: s_and_b32 s3, s3, 0x8000 +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s2, s3, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null +; GFX1250-GISEL-TRUE16-NEXT: s_endpgm +; ; GFX1250-GISEL-FAKE16-LABEL: fptrunc_f64_to_f16: ; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry ; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -1489,6 +1679,26 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn( ; GFX11-GISEL-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; GFX11-GISEL-FAKE16-NEXT: s_endpgm ; +; GFX1250-SDAG-TRUE16-LABEL: fptrunc_f64_to_f16_afn: +; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry +; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s10, s6 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s11, s7 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s8, s2 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s9, s3 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s4, s0 +; GFX1250-SDAG-TRUE16-NEXT: buffer_load_b64 v[0:1], off, s[8:11], null +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f32_f64_e32 v0, v[0:1] +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 +; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], null +; GFX1250-SDAG-TRUE16-NEXT: s_endpgm +; ; GFX1250-SDAG-FAKE16-LABEL: fptrunc_f64_to_f16_afn: ; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry ; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -1509,6 +1719,20 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn( ; GFX1250-SDAG-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], null ; GFX1250-SDAG-FAKE16-NEXT: s_endpgm ; +; GFX1250-GISEL-TRUE16-LABEL: fptrunc_f64_to_f16_afn: +; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: v_cvt_f32_f64_e32 v0, s[2:3] +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 +; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null +; GFX1250-GISEL-TRUE16-NEXT: s_endpgm +; ; GFX1250-GISEL-FAKE16-LABEL: fptrunc_f64_to_f16_afn: ; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry ; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -1740,6 +1964,24 @@ define amdgpu_kernel void @fptrunc_v2f32_to_v2f16( ; GFX11-GISEL-FAKE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0 ; GFX11-GISEL-FAKE16-NEXT: s_endpgm ; +; GFX1250-SDAG-TRUE16-LABEL: fptrunc_v2f32_to_v2f16: +; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry +; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s10, s6 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s11, s7 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s8, s2 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s9, s3 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s4, s0 +; GFX1250-SDAG-TRUE16-NEXT: buffer_load_b64 v[0:1], off, s[8:11], null +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: v_cvt_pk_f16_f32 v0, v0, v1 +; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b32 v0, off, s[4:7], null +; GFX1250-SDAG-TRUE16-NEXT: s_endpgm +; ; GFX1250-SDAG-FAKE16-LABEL: fptrunc_v2f32_to_v2f16: ; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry ; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -1758,6 +2000,20 @@ define amdgpu_kernel void @fptrunc_v2f32_to_v2f16( ; GFX1250-SDAG-FAKE16-NEXT: buffer_store_b32 v0, off, s[4:7], null ; GFX1250-SDAG-FAKE16-NEXT: s_endpgm ; +; GFX1250-GISEL-TRUE16-LABEL: fptrunc_v2f32_to_v2f16: +; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_load_b64 s[2:3], s[2:3], 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[0:1], s[2:3] +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-TRUE16-NEXT: v_cvt_pk_f16_f32 v0, v0, v1 +; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b32 v0, off, s[0:3], null +; GFX1250-GISEL-TRUE16-NEXT: s_endpgm +; ; GFX1250-GISEL-FAKE16-LABEL: fptrunc_v2f32_to_v2f16: ; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry ; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -3017,6 +3273,122 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16( ; GFX11-GISEL-FAKE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0 ; GFX11-GISEL-FAKE16-NEXT: s_endpgm ; +; GFX1250-SDAG-TRUE16-LABEL: fptrunc_v2f64_to_v2f16: +; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry +; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s10, s6 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s11, s7 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s8, s2 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s9, s3 +; GFX1250-SDAG-TRUE16-NEXT: buffer_load_b128 v[0:3], off, s[8:11], null +; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s2, v3 +; GFX1250-SDAG-TRUE16-NEXT: s_and_b32 s3, s2, 0x1ff +; GFX1250-SDAG-TRUE16-NEXT: s_lshr_b32 s5, s2, 8 +; GFX1250-SDAG-TRUE16-NEXT: v_or_b32_e32 v2, s3, v2 +; GFX1250-SDAG-TRUE16-NEXT: s_bfe_u32 s3, s2, 0xb0014 +; GFX1250-SDAG-TRUE16-NEXT: s_and_b32 s5, s5, 0xffe +; GFX1250-SDAG-TRUE16-NEXT: s_sub_co_i32 s4, 0x3f1, s3 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2) +; GFX1250-SDAG-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 +; GFX1250-SDAG-TRUE16-NEXT: v_med3_i32 v3, s4, 0, 13 +; GFX1250-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo +; GFX1250-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s8, v3 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1250-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s4, v2 +; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s4, s5, s4 +; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s5, s4, 0x1000 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1250-SDAG-TRUE16-NEXT: s_lshr_b32 s9, s5, s8 +; GFX1250-SDAG-TRUE16-NEXT: s_lshl_b32 s8, s9, s8 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1) +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_lg_u32 s8, s5 +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s5, 1, 0 +; GFX1250-SDAG-TRUE16-NEXT: s_addk_co_i32 s3, 0xfc10 +; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s5, s9, s5 +; GFX1250-SDAG-TRUE16-NEXT: s_lshl_b32 s8, s3, 12 +; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s8, s4, s8 +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_lt_i32 s3, 1 +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s5, s5, s8 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1250-SDAG-TRUE16-NEXT: s_and_b32 s8, s5, 7 +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_gt_i32 s8, 5 +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s9, 1, 0 +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_eq_u32 s8, 3 +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s8, 1, 0 +; GFX1250-SDAG-TRUE16-NEXT: s_lshr_b32 s5, s5, 2 +; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s8, s8, s9 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1250-SDAG-TRUE16-NEXT: s_add_co_i32 s5, s5, s8 +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_lt_i32 s3, 31 +; GFX1250-SDAG-TRUE16-NEXT: s_movk_i32 s8, 0x7e00 +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s5, s5, 0x7c00 +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_lg_u32 s4, 0 +; GFX1250-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s4, v1 +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s9, s8, 0x7c00 +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_eq_u32 s3, 0x40f +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s3, s9, s5 +; GFX1250-SDAG-TRUE16-NEXT: s_and_b32 s5, s4, 0x1ff +; GFX1250-SDAG-TRUE16-NEXT: s_lshr_b32 s10, s4, 8 +; GFX1250-SDAG-TRUE16-NEXT: v_or_b32_e32 v0, s5, v0 +; GFX1250-SDAG-TRUE16-NEXT: s_bfe_u32 s5, s4, 0xb0014 +; GFX1250-SDAG-TRUE16-NEXT: s_and_b32 s10, s10, 0xffe +; GFX1250-SDAG-TRUE16-NEXT: s_sub_co_i32 s9, 0x3f1, s5 +; GFX1250-SDAG-TRUE16-NEXT: s_lshr_b32 s2, s2, 16 +; GFX1250-SDAG-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX1250-SDAG-TRUE16-NEXT: v_med3_i32 v1, s9, 0, 13 +; GFX1250-SDAG-TRUE16-NEXT: s_and_b32 s2, s2, 0x8000 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s2, s2, s3 +; GFX1250-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo +; GFX1250-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s11, v1 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1250-SDAG-TRUE16-NEXT: v_readfirstlane_b32 s9, v0 +; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s9, s10, s9 +; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s10, s9, 0x1000 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1250-SDAG-TRUE16-NEXT: s_lshr_b32 s12, s10, s11 +; GFX1250-SDAG-TRUE16-NEXT: s_lshl_b32 s11, s12, s11 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1) +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_lg_u32 s11, s10 +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s3, 1, 0 +; GFX1250-SDAG-TRUE16-NEXT: s_addk_co_i32 s5, 0xfc10 +; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s3, s12, s3 +; GFX1250-SDAG-TRUE16-NEXT: s_lshl_b32 s10, s5, 12 +; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s10, s9, s10 +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_lt_i32 s5, 1 +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s3, s3, s10 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1250-SDAG-TRUE16-NEXT: s_and_b32 s10, s3, 7 +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_gt_i32 s10, 5 +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s11, 1, 0 +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_eq_u32 s10, 3 +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s10, 1, 0 +; GFX1250-SDAG-TRUE16-NEXT: s_lshr_b32 s3, s3, 2 +; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s10, s10, s11 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1250-SDAG-TRUE16-NEXT: s_add_co_i32 s3, s3, s10 +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_lt_i32 s5, 31 +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s3, s3, 0x7c00 +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_lg_u32 s9, 0 +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s8, s8, 0x7c00 +; GFX1250-SDAG-TRUE16-NEXT: s_cmp_eq_u32 s5, 0x40f +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1 +; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s3, s8, s3 +; GFX1250-SDAG-TRUE16-NEXT: s_lshr_b32 s4, s4, 16 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1250-SDAG-TRUE16-NEXT: s_and_b32 s4, s4, 0x8000 +; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s3, s4, s3 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s4, s0 +; GFX1250-SDAG-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s3, s2 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1250-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b32 v0, off, s[4:7], null +; GFX1250-SDAG-TRUE16-NEXT: s_endpgm +; ; GFX1250-SDAG-FAKE16-LABEL: fptrunc_v2f64_to_v2f16: ; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry ; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -3133,6 +3505,109 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16( ; GFX1250-SDAG-FAKE16-NEXT: buffer_store_b32 v0, off, s[4:7], null ; GFX1250-SDAG-FAKE16-NEXT: s_endpgm ; +; GFX1250-GISEL-TRUE16-LABEL: fptrunc_v2f64_to_v2f16: +; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[4:7], s[2:3], 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_and_b32 s8, s5, 0x1ff +; GFX1250-GISEL-TRUE16-NEXT: s_bfe_u32 s2, s5, 0xb0014 +; GFX1250-GISEL-TRUE16-NEXT: s_lshr_b32 s3, s5, 8 +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s4, s8, s4 +; GFX1250-GISEL-TRUE16-NEXT: s_addk_co_i32 s2, 0xfc10 +; GFX1250-GISEL-TRUE16-NEXT: s_and_b32 s3, s3, 0xffe +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_lg_u32 s4, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s4, 1, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s3, s3, s4 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_lg_u32 s3, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s4, 1, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_sub_co_i32 s8, 1, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s10, s3, 0x1000 +; GFX1250-GISEL-TRUE16-NEXT: s_max_i32 s8, s8, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_lshl_b32 s9, s2, 12 +; GFX1250-GISEL-TRUE16-NEXT: s_min_i32 s8, s8, 13 +; GFX1250-GISEL-TRUE16-NEXT: s_lshl_b32 s4, s4, 9 +; GFX1250-GISEL-TRUE16-NEXT: s_lshr_b32 s11, s10, s8 +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s3, s3, s9 +; GFX1250-GISEL-TRUE16-NEXT: s_lshl_b32 s8, s11, s8 +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s4, s4, 0x7c00 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_lg_u32 s8, s10 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s8, 1, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s8, s11, s8 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_lt_i32 s2, 1 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s3, s8, s3 +; GFX1250-GISEL-TRUE16-NEXT: s_and_b32 s8, s3, 7 +; GFX1250-GISEL-TRUE16-NEXT: s_lshr_b32 s3, s3, 2 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_eq_u32 s8, 3 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s9, 1, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_gt_i32 s8, 5 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s8, 1, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s8, s9, s8 +; GFX1250-GISEL-TRUE16-NEXT: s_add_co_i32 s3, s3, s8 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_gt_i32 s2, 30 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s3, 0x7c00, s3 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_eq_u32 s2, 0x40f +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s2, s4, s3 +; GFX1250-GISEL-TRUE16-NEXT: s_lshr_b32 s3, s5, 16 +; GFX1250-GISEL-TRUE16-NEXT: s_and_b32 s8, s7, 0x1ff +; GFX1250-GISEL-TRUE16-NEXT: s_bfe_u32 s4, s7, 0xb0014 +; GFX1250-GISEL-TRUE16-NEXT: s_lshr_b32 s5, s7, 8 +; GFX1250-GISEL-TRUE16-NEXT: s_and_b32 s3, s3, 0x8000 +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s6, s8, s6 +; GFX1250-GISEL-TRUE16-NEXT: s_addk_co_i32 s4, 0xfc10 +; GFX1250-GISEL-TRUE16-NEXT: s_and_b32 s5, s5, 0xffe +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s2, s3, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_lg_u32 s6, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s3, 1, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s3, s5, s3 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_lg_u32 s3, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s5, 1, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_sub_co_i32 s6, 1, s4 +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s9, s3, 0x1000 +; GFX1250-GISEL-TRUE16-NEXT: s_max_i32 s6, s6, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_lshl_b32 s8, s4, 12 +; GFX1250-GISEL-TRUE16-NEXT: s_min_i32 s6, s6, 13 +; GFX1250-GISEL-TRUE16-NEXT: s_lshl_b32 s5, s5, 9 +; GFX1250-GISEL-TRUE16-NEXT: s_lshr_b32 s10, s9, s6 +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s3, s3, s8 +; GFX1250-GISEL-TRUE16-NEXT: s_lshl_b32 s6, s10, s6 +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s5, s5, 0x7c00 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_lg_u32 s6, s9 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s6, 1, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s6, s10, s6 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_lt_i32 s4, 1 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s3, s6, s3 +; GFX1250-GISEL-TRUE16-NEXT: s_and_b32 s6, s3, 7 +; GFX1250-GISEL-TRUE16-NEXT: s_lshr_b32 s3, s3, 2 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_eq_u32 s6, 3 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s8, 1, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_gt_i32 s6, 5 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s6, 1, 0 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s6, s8, s6 +; GFX1250-GISEL-TRUE16-NEXT: s_add_co_i32 s3, s3, s6 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_gt_i32 s4, 30 +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s3, 0x7c00, s3 +; GFX1250-GISEL-TRUE16-NEXT: s_cmp_eq_u32 s4, 0x40f +; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s3, s5, s3 +; GFX1250-GISEL-TRUE16-NEXT: s_lshr_b32 s4, s7, 16 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1250-GISEL-TRUE16-NEXT: s_and_b32 s4, s4, 0x8000 +; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s3, s4, s3 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1250-GISEL-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s3 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b32 v0, off, s[0:3], null +; GFX1250-GISEL-TRUE16-NEXT: s_endpgm +; ; GFX1250-GISEL-FAKE16-LABEL: fptrunc_v2f64_to_v2f16: ; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry ; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -3481,6 +3956,27 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn( ; GFX11-GISEL-FAKE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0 ; GFX11-GISEL-FAKE16-NEXT: s_endpgm ; +; GFX1250-SDAG-TRUE16-LABEL: fptrunc_v2f64_to_v2f16_afn: +; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry +; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s10, s6 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s11, s7 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s8, s2 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s9, s3 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s4, s0 +; GFX1250-SDAG-TRUE16-NEXT: buffer_load_b128 v[0:3], off, s[8:11], null +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f32_f64_e32 v2, v[2:3] +; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f32_f64_e32 v0, v[0:1] +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-TRUE16-NEXT: v_cvt_pk_f16_f32 v0, v0, v2 +; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b32 v0, off, s[4:7], null +; GFX1250-SDAG-TRUE16-NEXT: s_endpgm +; ; GFX1250-SDAG-FAKE16-LABEL: fptrunc_v2f64_to_v2f16_afn: ; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry ; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -3502,6 +3998,25 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn( ; GFX1250-SDAG-FAKE16-NEXT: buffer_store_b32 v0, off, s[4:7], null ; GFX1250-SDAG-FAKE16-NEXT: s_endpgm ; +; GFX1250-GISEL-TRUE16-LABEL: fptrunc_v2f64_to_v2f16_afn: +; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[4:7], s[2:3], 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_xcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: v_cvt_f32_f64_e32 v0, s[4:5] +; GFX1250-GISEL-TRUE16-NEXT: v_cvt_f32_f64_e32 v1, s[6:7] +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX1250-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 +; GFX1250-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h +; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b32 v0, off, s[0:3], null +; GFX1250-GISEL-TRUE16-NEXT: s_endpgm +; ; GFX1250-GISEL-FAKE16-LABEL: fptrunc_v2f64_to_v2f16_afn: ; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry ; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -3710,6 +4225,26 @@ define amdgpu_kernel void @fneg_fptrunc_f32_to_f16( ; GFX11-GISEL-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; GFX11-GISEL-FAKE16-NEXT: s_endpgm ; +; GFX1250-SDAG-TRUE16-LABEL: fneg_fptrunc_f32_to_f16: +; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry +; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s10, s6 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s11, s7 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s8, s2 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s9, s3 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s4, s0 +; GFX1250-SDAG-TRUE16-NEXT: buffer_load_b32 v0, off, s[8:11], null +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: v_xor_b32_e32 v0, 0x80000000, v0 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 +; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], null +; GFX1250-SDAG-TRUE16-NEXT: s_endpgm +; ; GFX1250-SDAG-FAKE16-LABEL: fneg_fptrunc_f32_to_f16: ; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry ; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -3730,6 +4265,22 @@ define amdgpu_kernel void @fneg_fptrunc_f32_to_f16( ; GFX1250-SDAG-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], null ; GFX1250-SDAG-FAKE16-NEXT: s_endpgm ; +; GFX1250-GISEL-TRUE16-LABEL: fneg_fptrunc_f32_to_f16: +; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_xcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_xor_b32 s2, s2, 0x80000000 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3) +; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2 +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null +; GFX1250-GISEL-TRUE16-NEXT: s_endpgm +; ; GFX1250-GISEL-FAKE16-LABEL: fneg_fptrunc_f32_to_f16: ; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry ; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -3936,6 +4487,26 @@ define amdgpu_kernel void @fabs_fptrunc_f32_to_f16( ; GFX11-GISEL-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; GFX11-GISEL-FAKE16-NEXT: s_endpgm ; +; GFX1250-SDAG-TRUE16-LABEL: fabs_fptrunc_f32_to_f16: +; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry +; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s10, s6 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s11, s7 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s8, s2 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s9, s3 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s4, s0 +; GFX1250-SDAG-TRUE16-NEXT: buffer_load_b32 v0, off, s[8:11], null +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 +; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], null +; GFX1250-SDAG-TRUE16-NEXT: s_endpgm +; ; GFX1250-SDAG-FAKE16-LABEL: fabs_fptrunc_f32_to_f16: ; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry ; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -3956,6 +4527,22 @@ define amdgpu_kernel void @fabs_fptrunc_f32_to_f16( ; GFX1250-SDAG-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], null ; GFX1250-SDAG-FAKE16-NEXT: s_endpgm ; +; GFX1250-GISEL-TRUE16-LABEL: fabs_fptrunc_f32_to_f16: +; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_xcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_bitset0_b32 s2, 31 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3) +; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2 +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null +; GFX1250-GISEL-TRUE16-NEXT: s_endpgm +; ; GFX1250-GISEL-FAKE16-LABEL: fabs_fptrunc_f32_to_f16: ; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry ; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -4162,6 +4749,26 @@ define amdgpu_kernel void @fneg_fabs_fptrunc_f32_to_f16( ; GFX11-GISEL-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0 ; GFX11-GISEL-FAKE16-NEXT: s_endpgm ; +; GFX1250-SDAG-TRUE16-LABEL: fneg_fabs_fptrunc_f32_to_f16: +; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry +; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s10, s6 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s11, s7 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s8, s2 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s9, s3 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s4, s0 +; GFX1250-SDAG-TRUE16-NEXT: buffer_load_b32 v0, off, s[8:11], null +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: v_or_b32_e32 v0, 0x80000000, v0 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 +; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], null +; GFX1250-SDAG-TRUE16-NEXT: s_endpgm +; ; GFX1250-SDAG-FAKE16-LABEL: fneg_fabs_fptrunc_f32_to_f16: ; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry ; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -4182,6 +4789,22 @@ define amdgpu_kernel void @fneg_fabs_fptrunc_f32_to_f16( ; GFX1250-SDAG-FAKE16-NEXT: buffer_store_b16 v0, off, s[4:7], null ; GFX1250-SDAG-FAKE16-NEXT: s_endpgm ; +; GFX1250-GISEL-TRUE16-LABEL: fneg_fabs_fptrunc_f32_to_f16: +; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_xcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_bitset1_b32 s2, 31 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3) +; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2 +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null +; GFX1250-GISEL-TRUE16-NEXT: s_endpgm +; ; GFX1250-GISEL-FAKE16-LABEL: fneg_fabs_fptrunc_f32_to_f16: ; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry ; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -4396,6 +5019,26 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_zext_i32( ; GFX11-GISEL-FAKE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0 ; GFX11-GISEL-FAKE16-NEXT: s_endpgm ; +; GFX1250-SDAG-TRUE16-LABEL: fptrunc_f32_to_f16_zext_i32: +; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry +; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s10, s6 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s11, s7 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s8, s2 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s9, s3 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s4, s0 +; GFX1250-SDAG-TRUE16-NEXT: buffer_load_b32 v0, off, s[8:11], null +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b32 v0, off, s[4:7], null +; GFX1250-SDAG-TRUE16-NEXT: s_endpgm +; ; GFX1250-SDAG-FAKE16-LABEL: fptrunc_f32_to_f16_zext_i32: ; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry ; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -4416,6 +5059,22 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_zext_i32( ; GFX1250-SDAG-FAKE16-NEXT: buffer_store_b32 v0, off, s[4:7], null ; GFX1250-SDAG-FAKE16-NEXT: s_endpgm ; +; GFX1250-GISEL-TRUE16-LABEL: fptrunc_f32_to_f16_zext_i32: +; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_xcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1250-GISEL-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2 +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b32 v0, off, s[0:3], null +; GFX1250-GISEL-TRUE16-NEXT: s_endpgm +; ; GFX1250-GISEL-FAKE16-LABEL: fptrunc_f32_to_f16_zext_i32: ; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry ; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -4630,6 +5289,27 @@ define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32( ; GFX11-GISEL-FAKE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0 ; GFX11-GISEL-FAKE16-NEXT: s_endpgm ; +; GFX1250-SDAG-TRUE16-LABEL: fptrunc_fabs_f32_to_f16_zext_i32: +; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry +; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s10, s6 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s11, s7 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s8, s2 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s9, s3 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s4, s0 +; GFX1250-SDAG-TRUE16-NEXT: buffer_load_b32 v0, off, s[8:11], null +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 +; GFX1250-SDAG-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b32 v0, off, s[4:7], null +; GFX1250-SDAG-TRUE16-NEXT: s_endpgm +; ; GFX1250-SDAG-FAKE16-LABEL: fptrunc_fabs_f32_to_f16_zext_i32: ; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry ; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -4651,6 +5331,24 @@ define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32( ; GFX1250-SDAG-FAKE16-NEXT: buffer_store_b32 v0, off, s[4:7], null ; GFX1250-SDAG-FAKE16-NEXT: s_endpgm ; +; GFX1250-GISEL-TRUE16-LABEL: fptrunc_fabs_f32_to_f16_zext_i32: +; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_xcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_bitset0_b32 s2, 31 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3) +; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b32 v0, off, s[0:3], null +; GFX1250-GISEL-TRUE16-NEXT: s_endpgm +; ; GFX1250-GISEL-FAKE16-LABEL: fptrunc_fabs_f32_to_f16_zext_i32: ; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry ; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -4877,6 +5575,26 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_sext_i32( ; GFX11-GISEL-FAKE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0 ; GFX11-GISEL-FAKE16-NEXT: s_endpgm ; +; GFX1250-SDAG-TRUE16-LABEL: fptrunc_f32_to_f16_sext_i32: +; GFX1250-SDAG-TRUE16: ; %bb.0: ; %entry +; GFX1250-SDAG-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s6, -1 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s7, 0x31016000 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s10, s6 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s11, s7 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s8, s2 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s9, s3 +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s4, s0 +; GFX1250-SDAG-TRUE16-NEXT: buffer_load_b32 v0, off, s[8:11], null +; GFX1250-SDAG-TRUE16-NEXT: s_mov_b32 s5, s1 +; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250-SDAG-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0 +; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16 +; GFX1250-SDAG-TRUE16-NEXT: buffer_store_b32 v0, off, s[4:7], null +; GFX1250-SDAG-TRUE16-NEXT: s_endpgm +; ; GFX1250-SDAG-FAKE16-LABEL: fptrunc_f32_to_f16_sext_i32: ; GFX1250-SDAG-FAKE16: ; %bb.0: ; %entry ; GFX1250-SDAG-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 @@ -4897,6 +5615,22 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_sext_i32( ; GFX1250-SDAG-FAKE16-NEXT: buffer_store_b32 v0, off, s[4:7], null ; GFX1250-SDAG-FAKE16-NEXT: s_endpgm ; +; GFX1250-GISEL-TRUE16-LABEL: fptrunc_f32_to_f16_sext_i32: +; GFX1250-GISEL-TRUE16: ; %bb.0: ; %entry +; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_xcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX1250-GISEL-TRUE16-NEXT: s_sext_i32_i16 s2, s2 +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2 +; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1 +; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b32 v0, off, s[0:3], null +; GFX1250-GISEL-TRUE16-NEXT: s_endpgm +; ; GFX1250-GISEL-FAKE16-LABEL: fptrunc_f32_to_f16_sext_i32: ; GFX1250-GISEL-FAKE16: ; %bb.0: ; %entry ; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 diff --git a/llvm/test/CodeGen/AMDGPU/implicitarg-offset-attributes.ll b/llvm/test/CodeGen/AMDGPU/implicitarg-offset-attributes.ll index 3089054..32f7d6b 100644 --- a/llvm/test/CodeGen/AMDGPU/implicitarg-offset-attributes.ll +++ b/llvm/test/CodeGen/AMDGPU/implicitarg-offset-attributes.ll @@ -276,23 +276,23 @@ attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memo ;. ; V4: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -; V4: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } -; V4: attributes #[[ATTR2]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } -; V4: attributes #[[ATTR3]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } -; V4: attributes #[[ATTR4]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } -; V4: attributes #[[ATTR5]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } +; V4: attributes #[[ATTR1]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } +; V4: attributes #[[ATTR2]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } +; V4: attributes #[[ATTR3]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } +; V4: attributes #[[ATTR4]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } +; V4: attributes #[[ATTR5]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } ;. ; V5: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -; V5: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } -; V5: attributes #[[ATTR2]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } -; V5: attributes #[[ATTR3]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } -; V5: attributes #[[ATTR4]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } +; V5: attributes #[[ATTR1]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } +; V5: attributes #[[ATTR2]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } +; V5: attributes #[[ATTR3]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } +; V5: attributes #[[ATTR4]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } ;. ; V6: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -; V6: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } -; V6: attributes #[[ATTR2]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } -; V6: attributes #[[ATTR3]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } -; V6: attributes #[[ATTR4]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } +; V6: attributes #[[ATTR1]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } +; V6: attributes #[[ATTR2]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } +; V6: attributes #[[ATTR3]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-default-queue" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } +; V6: attributes #[[ATTR4]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-multigrid-sync-arg" "uniform-work-group-size"="false" } ;. ; V4: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 400} ;. diff --git a/llvm/test/CodeGen/AMDGPU/indirect-call-set-from-other-function.ll b/llvm/test/CodeGen/AMDGPU/indirect-call-set-from-other-function.ll index d3ef1b7..a0f5d2f 100644 --- a/llvm/test/CodeGen/AMDGPU/indirect-call-set-from-other-function.ll +++ b/llvm/test/CodeGen/AMDGPU/indirect-call-set-from-other-function.ll @@ -68,6 +68,6 @@ if.end: ret void } ;. -; CHECK: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } ; CHECK: attributes #[[ATTR1]] = { "uniform-work-group-size"="false" } ;. diff --git a/llvm/test/CodeGen/AMDGPU/issue120256-annotate-constexpr-addrspacecast.ll b/llvm/test/CodeGen/AMDGPU/issue120256-annotate-constexpr-addrspacecast.ll index 71a330e..4e952b6 100644 --- a/llvm/test/CodeGen/AMDGPU/issue120256-annotate-constexpr-addrspacecast.ll +++ b/llvm/test/CodeGen/AMDGPU/issue120256-annotate-constexpr-addrspacecast.ll @@ -55,8 +55,8 @@ define amdgpu_kernel void @issue120256_private(ptr addrspace(1) %out) { ; FIXME: Inference of amdgpu-no-queue-ptr should not depend on code object version. !0 = !{i32 1, !"amdhsa_code_object_version", i32 400} ;. -; CHECK: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx803" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx803" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx803" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR1]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx803" "uniform-work-group-size"="false" } ;. ; CHECK: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 400} ;. diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll index 6ccfad7..ff47563 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll @@ -14,7 +14,7 @@ define amdgpu_ps void @test_cvt_pk_bf8_f16_v(<2 x half> %a, ptr addrspace(1) %ou ; GFX1250-SDAG-REAL16: ; %bb.0: ; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_bf8_f16 v0.l, v0 -; GFX1250-SDAG-REAL16-NEXT: flat_store_b16 v[2:3], v0 +; GFX1250-SDAG-REAL16-NEXT: global_store_b16 v[2:3], v0, off ; GFX1250-SDAG-REAL16-NEXT: s_endpgm ; ; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_bf8_f16_v: @@ -28,7 +28,7 @@ define amdgpu_ps void @test_cvt_pk_bf8_f16_v(<2 x half> %a, ptr addrspace(1) %ou ; GFX1250-GISEL-REAL16: ; %bb.0: ; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 ; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_bf8_f16 v0.l, v0 -; GFX1250-GISEL-REAL16-NEXT: flat_store_b16 v[4:5], v0 +; GFX1250-GISEL-REAL16-NEXT: global_store_b16 v[4:5], v0, off ; GFX1250-GISEL-REAL16-NEXT: s_endpgm ; ; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_bf8_f16_v: @@ -46,7 +46,7 @@ define amdgpu_ps void @test_cvt_pk_bf8_f16_s(<2 x half> inreg %a, ptr addrspace( ; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_bf8_f16_s: ; GFX1250-SDAG-REAL16: ; %bb.0: ; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_bf8_f16 v2.l, s0 -; GFX1250-SDAG-REAL16-NEXT: flat_store_b16 v[0:1], v2 +; GFX1250-SDAG-REAL16-NEXT: global_store_b16 v[0:1], v2, off ; GFX1250-SDAG-REAL16-NEXT: s_endpgm ; ; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_bf8_f16_s: @@ -58,7 +58,7 @@ define amdgpu_ps void @test_cvt_pk_bf8_f16_s(<2 x half> inreg %a, ptr addrspace( ; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_bf8_f16_s: ; GFX1250-GISEL-REAL16: ; %bb.0: ; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_bf8_f16 v2.l, s0 -; GFX1250-GISEL-REAL16-NEXT: flat_store_b16 v[0:1], v2 +; GFX1250-GISEL-REAL16-NEXT: global_store_b16 v[0:1], v2, off ; GFX1250-GISEL-REAL16-NEXT: s_endpgm ; ; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_bf8_f16_s: @@ -75,7 +75,7 @@ define amdgpu_ps void @test_cvt_pk_bf8_f16_l(ptr addrspace(1) %out) { ; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_bf8_f16_l: ; GFX1250-SDAG-REAL16: ; %bb.0: ; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_bf8_f16 v2.l, 0x56400000 -; GFX1250-SDAG-REAL16-NEXT: flat_store_b16 v[0:1], v2 +; GFX1250-SDAG-REAL16-NEXT: global_store_b16 v[0:1], v2, off ; GFX1250-SDAG-REAL16-NEXT: s_endpgm ; ; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_bf8_f16_l: @@ -87,7 +87,7 @@ define amdgpu_ps void @test_cvt_pk_bf8_f16_l(ptr addrspace(1) %out) { ; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_bf8_f16_l: ; GFX1250-GISEL-REAL16: ; %bb.0: ; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_bf8_f16 v2.l, 0x56400000 -; GFX1250-GISEL-REAL16-NEXT: flat_store_b16 v[0:1], v2 +; GFX1250-GISEL-REAL16-NEXT: global_store_b16 v[0:1], v2, off ; GFX1250-GISEL-REAL16-NEXT: s_endpgm ; ; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_bf8_f16_l: @@ -105,7 +105,7 @@ define amdgpu_ps void @test_cvt_pk_fp8_f16_v(<2 x half> %a, ptr addrspace(1) %ou ; GFX1250-SDAG-REAL16: ; %bb.0: ; GFX1250-SDAG-REAL16-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_fp8_f16 v0.l, v0 -; GFX1250-SDAG-REAL16-NEXT: flat_store_b16 v[2:3], v0 +; GFX1250-SDAG-REAL16-NEXT: global_store_b16 v[2:3], v0, off ; GFX1250-SDAG-REAL16-NEXT: s_endpgm ; ; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_fp8_f16_v: @@ -119,7 +119,7 @@ define amdgpu_ps void @test_cvt_pk_fp8_f16_v(<2 x half> %a, ptr addrspace(1) %ou ; GFX1250-GISEL-REAL16: ; %bb.0: ; GFX1250-GISEL-REAL16-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 ; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_fp8_f16 v0.l, v0 -; GFX1250-GISEL-REAL16-NEXT: flat_store_b16 v[4:5], v0 +; GFX1250-GISEL-REAL16-NEXT: global_store_b16 v[4:5], v0, off ; GFX1250-GISEL-REAL16-NEXT: s_endpgm ; ; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_fp8_f16_v: @@ -137,7 +137,7 @@ define amdgpu_ps void @test_cvt_pk_fp8_f16_s(<2 x half> inreg %a, ptr addrspace( ; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_fp8_f16_s: ; GFX1250-SDAG-REAL16: ; %bb.0: ; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_fp8_f16 v2.l, s0 -; GFX1250-SDAG-REAL16-NEXT: flat_store_b16 v[0:1], v2 +; GFX1250-SDAG-REAL16-NEXT: global_store_b16 v[0:1], v2, off ; GFX1250-SDAG-REAL16-NEXT: s_endpgm ; ; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_fp8_f16_s: @@ -149,7 +149,7 @@ define amdgpu_ps void @test_cvt_pk_fp8_f16_s(<2 x half> inreg %a, ptr addrspace( ; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_fp8_f16_s: ; GFX1250-GISEL-REAL16: ; %bb.0: ; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_fp8_f16 v2.l, s0 -; GFX1250-GISEL-REAL16-NEXT: flat_store_b16 v[0:1], v2 +; GFX1250-GISEL-REAL16-NEXT: global_store_b16 v[0:1], v2, off ; GFX1250-GISEL-REAL16-NEXT: s_endpgm ; ; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_fp8_f16_s: @@ -166,7 +166,7 @@ define amdgpu_ps void @test_cvt_pk_fp8_f16_l(ptr addrspace(1) %out) { ; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_fp8_f16_l: ; GFX1250-SDAG-REAL16: ; %bb.0: ; GFX1250-SDAG-REAL16-NEXT: v_cvt_pk_fp8_f16 v2.l, 0x56400000 -; GFX1250-SDAG-REAL16-NEXT: flat_store_b16 v[0:1], v2 +; GFX1250-SDAG-REAL16-NEXT: global_store_b16 v[0:1], v2, off ; GFX1250-SDAG-REAL16-NEXT: s_endpgm ; ; GFX1250-SDAG-FAKE16-LABEL: test_cvt_pk_fp8_f16_l: @@ -178,7 +178,7 @@ define amdgpu_ps void @test_cvt_pk_fp8_f16_l(ptr addrspace(1) %out) { ; GFX1250-GISEL-REAL16-LABEL: test_cvt_pk_fp8_f16_l: ; GFX1250-GISEL-REAL16: ; %bb.0: ; GFX1250-GISEL-REAL16-NEXT: v_cvt_pk_fp8_f16 v2.l, 0x56400000 -; GFX1250-GISEL-REAL16-NEXT: flat_store_b16 v[0:1], v2 +; GFX1250-GISEL-REAL16-NEXT: global_store_b16 v[0:1], v2, off ; GFX1250-GISEL-REAL16-NEXT: s_endpgm ; ; GFX1250-GISEL-FAKE16-LABEL: test_cvt_pk_fp8_f16_l: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll index 1e44a09..dbea832 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll @@ -15,7 +15,7 @@ define amdgpu_kernel void @rcp_bf16(ptr addrspace(1) %out, bfloat %src) #1 { ; SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0 ; SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 ; SDAG-TRUE16-NEXT: v_rcp_bf16_e32 v0.l, s2 -; SDAG-TRUE16-NEXT: flat_store_b16 v1, v0, s[0:1] +; SDAG-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] ; SDAG-TRUE16-NEXT: s_endpgm ; ; SDAG-FAKE16-LABEL: rcp_bf16: @@ -35,10 +35,10 @@ define amdgpu_kernel void @rcp_bf16_constant_4(ptr addrspace(1) %out) #1 { ; SDAG-TRUE16-LABEL: rcp_bf16_constant_4: ; SDAG-TRUE16: ; %bb.0: ; SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 -; SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3e80 ; SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3e80 ; SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 -; SDAG-TRUE16-NEXT: flat_store_b16 v1, v0, s[0:1] +; SDAG-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] ; SDAG-TRUE16-NEXT: s_endpgm ; ; SDAG-FAKE16-LABEL: rcp_bf16_constant_4: @@ -57,10 +57,10 @@ define amdgpu_kernel void @rcp_bf16_constant_100(ptr addrspace(1) %out) #1 { ; SDAG-TRUE16-LABEL: rcp_bf16_constant_100: ; SDAG-TRUE16: ; %bb.0: ; SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 -; SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3c24 ; SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3c24 ; SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 -; SDAG-TRUE16-NEXT: flat_store_b16 v1, v0, s[0:1] +; SDAG-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] ; SDAG-TRUE16-NEXT: s_endpgm ; ; SDAG-FAKE16-LABEL: rcp_bf16_constant_100: @@ -79,10 +79,10 @@ define amdgpu_kernel void @rcp_undef_bf16(ptr addrspace(1) %out) #1 { ; SDAG-TRUE16-LABEL: rcp_undef_bf16: ; SDAG-TRUE16: ; %bb.0: ; SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 -; SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x7fc0 ; SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x7fc0 ; SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 -; SDAG-TRUE16-NEXT: flat_store_b16 v1, v0, s[0:1] +; SDAG-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] ; SDAG-TRUE16-NEXT: s_endpgm ; ; SDAG-FAKE16-LABEL: rcp_undef_bf16: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll index 42d12fd..662dc613 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll @@ -15,7 +15,7 @@ define amdgpu_kernel void @rsq_bf16(ptr addrspace(1) %out, bfloat %src) #1 { ; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0 ; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0 ; SDAG-REAL16-NEXT: v_rsq_bf16_e32 v0.l, s2 -; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] +; SDAG-REAL16-NEXT: global_store_b16 v1, v0, s[0:1] ; SDAG-REAL16-NEXT: s_endpgm ; ; SDAG-FAKE16-LABEL: rsq_bf16: @@ -38,7 +38,7 @@ define amdgpu_kernel void @rsq_bf16_constant_4(ptr addrspace(1) %out) #1 { ; SDAG-REAL16-NEXT: v_rsq_bf16_e32 v0.l, 4.0 ; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0 ; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0 -; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] +; SDAG-REAL16-NEXT: global_store_b16 v1, v0, s[0:1] ; SDAG-REAL16-NEXT: s_endpgm ; ; SDAG-FAKE16-LABEL: rsq_bf16_constant_4: @@ -61,7 +61,7 @@ define amdgpu_kernel void @rsq_bf16_constant_100(ptr addrspace(1) %out) #1 { ; SDAG-REAL16-NEXT: v_rsq_bf16_e32 v0.l, 0x42c8 ; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0 ; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0 -; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] +; SDAG-REAL16-NEXT: global_store_b16 v1, v0, s[0:1] ; SDAG-REAL16-NEXT: s_endpgm ; ; SDAG-FAKE16-LABEL: rsq_bf16_constant_100: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll index dd89f80..ba769ef 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll @@ -100,7 +100,7 @@ define amdgpu_kernel void @tanh_f16(ptr addrspace(1) %out, half %src) #1 { ; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0 ; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0 ; SDAG-REAL16-NEXT: v_tanh_f16_e32 v0.l, s2 -; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] +; SDAG-REAL16-NEXT: global_store_b16 v1, v0, s[0:1] ; SDAG-REAL16-NEXT: s_endpgm ; ; SDAG-FAKE16-LABEL: tanh_f16: @@ -123,7 +123,7 @@ define amdgpu_kernel void @tanh_f16_constant_4.0(ptr addrspace(1) %out) #1 { ; SDAG-REAL16-NEXT: v_tanh_f16_e32 v0.l, 4.0 ; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0 ; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0 -; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] +; SDAG-REAL16-NEXT: global_store_b16 v1, v0, s[0:1] ; SDAG-REAL16-NEXT: s_endpgm ; ; SDAG-FAKE16-LABEL: tanh_f16_constant_4.0: @@ -146,7 +146,7 @@ define amdgpu_kernel void @tanh_f16_constant_100.0(ptr addrspace(1) %out) #1 { ; SDAG-REAL16-NEXT: v_tanh_f16_e32 v0.l, 0x5640 ; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0 ; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0 -; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] +; SDAG-REAL16-NEXT: global_store_b16 v1, v0, s[0:1] ; SDAG-REAL16-NEXT: s_endpgm ; ; SDAG-FAKE16-LABEL: tanh_f16_constant_100.0: @@ -182,7 +182,7 @@ define amdgpu_kernel void @tanh_bf16(ptr addrspace(1) %out, bfloat %src) #1 { ; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0 ; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0 ; SDAG-REAL16-NEXT: v_tanh_bf16_e32 v0.l, s2 -; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] +; SDAG-REAL16-NEXT: global_store_b16 v1, v0, s[0:1] ; SDAG-REAL16-NEXT: s_endpgm ; ; SDAG-FAKE16-LABEL: tanh_bf16: @@ -205,7 +205,7 @@ define amdgpu_kernel void @tanh_bf16_constant_4(ptr addrspace(1) %out) #1 { ; SDAG-REAL16-NEXT: v_tanh_bf16_e32 v0.l, 4.0 ; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0 ; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0 -; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] +; SDAG-REAL16-NEXT: global_store_b16 v1, v0, s[0:1] ; SDAG-REAL16-NEXT: s_endpgm ; ; SDAG-FAKE16-LABEL: tanh_bf16_constant_4: @@ -228,7 +228,7 @@ define amdgpu_kernel void @tanh_bf16_constant_100(ptr addrspace(1) %out) #1 { ; SDAG-REAL16-NEXT: v_tanh_bf16_e32 v0.l, 0x42c8 ; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0 ; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0 -; SDAG-REAL16-NEXT: flat_store_b16 v1, v0, s[0:1] +; SDAG-REAL16-NEXT: global_store_b16 v1, v0, s[0:1] ; SDAG-REAL16-NEXT: s_endpgm ; ; SDAG-FAKE16-LABEL: tanh_bf16_constant_100: diff --git a/llvm/test/CodeGen/AMDGPU/min.ll b/llvm/test/CodeGen/AMDGPU/min.ll index 6a3d31f..0458a64 100644 --- a/llvm/test/CodeGen/AMDGPU/min.ll +++ b/llvm/test/CodeGen/AMDGPU/min.ll @@ -6,9 +6,7 @@ ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck --check-prefix=GFX10 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck --check-prefixes=GFX11,GFX11-TRUE16 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck --check-prefixes=GFX11,GFX11-FAKE16 %s -; TODO: FIXME-TRUE16 - Enable this llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-TRUE16 %s -; Crashing on v_test_imin_slt_i16 -; LLVM ERROR: Cannot select: 0x5f895f65b050: i16,ch = load<(load (s16) from %ir.b.gep, addrspace 1)> +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-TRUE16 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 -amdgpu-enable-vopd=0 < %s | FileCheck --check-prefixes=GFX1250,GFX1250-FAKE16 %s define amdgpu_kernel void @v_test_imin_sle_i32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) #0 { @@ -1482,20 +1480,35 @@ define amdgpu_kernel void @v_test_imin_slt_i16(ptr addrspace(1) %out, ptr addrsp ; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX11-FAKE16-NEXT: s_endpgm ; -; GFX1250-LABEL: v_test_imin_slt_i16: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_clause 0x1 -; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0 -; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x10 -; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: s_clause 0x1 -; GFX1250-NEXT: global_load_u16 v1, v0, s[2:3] scale_offset -; GFX1250-NEXT: global_load_u16 v2, v0, s[6:7] scale_offset -; GFX1250-NEXT: s_wait_loadcnt 0x0 -; GFX1250-NEXT: v_min_i16 v1, v1, v2 -; GFX1250-NEXT: global_store_b16 v0, v1, s[0:1] scale_offset -; GFX1250-NEXT: s_endpgm +; GFX1250-TRUE16-LABEL: v_test_imin_slt_i16: +; GFX1250-TRUE16: ; %bb.0: +; GFX1250-TRUE16-NEXT: s_clause 0x1 +; GFX1250-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0 +; GFX1250-TRUE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x10 +; GFX1250-TRUE16-NEXT: v_and_b32_e32 v1, 0x3ff, v0 +; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-TRUE16-NEXT: s_clause 0x1 +; GFX1250-TRUE16-NEXT: global_load_u16 v0, v1, s[2:3] scale_offset +; GFX1250-TRUE16-NEXT: global_load_u16 v2, v1, s[6:7] scale_offset +; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v2.l +; GFX1250-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] scale_offset +; GFX1250-TRUE16-NEXT: s_endpgm +; +; GFX1250-FAKE16-LABEL: v_test_imin_slt_i16: +; GFX1250-FAKE16: ; %bb.0: +; GFX1250-FAKE16-NEXT: s_clause 0x1 +; GFX1250-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0 +; GFX1250-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x10 +; GFX1250-FAKE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-FAKE16-NEXT: s_clause 0x1 +; GFX1250-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3] scale_offset +; GFX1250-FAKE16-NEXT: global_load_u16 v2, v0, s[6:7] scale_offset +; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250-FAKE16-NEXT: v_min_i16 v1, v1, v2 +; GFX1250-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1] scale_offset +; GFX1250-FAKE16-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %a.gep = getelementptr inbounds i16, ptr addrspace(1) %aptr, i32 %tid %b.gep = getelementptr inbounds i16, ptr addrspace(1) %bptr, i32 %tid @@ -2769,20 +2782,35 @@ define amdgpu_kernel void @v_test_umin_ult_i8(ptr addrspace(1) %out, ptr addrspa ; GFX11-FAKE16-NEXT: global_store_b8 v0, v1, s[0:1] ; GFX11-FAKE16-NEXT: s_endpgm ; -; GFX1250-LABEL: v_test_umin_ult_i8: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_clause 0x1 -; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x0 -; GFX1250-NEXT: s_load_b64 s[6:7], s[4:5], 0x10 -; GFX1250-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: s_clause 0x1 -; GFX1250-NEXT: global_load_u8 v1, v0, s[2:3] -; GFX1250-NEXT: global_load_u8 v2, v0, s[6:7] -; GFX1250-NEXT: s_wait_loadcnt 0x0 -; GFX1250-NEXT: v_min_u16 v1, v1, v2 -; GFX1250-NEXT: global_store_b8 v0, v1, s[0:1] -; GFX1250-NEXT: s_endpgm +; GFX1250-TRUE16-LABEL: v_test_umin_ult_i8: +; GFX1250-TRUE16: ; %bb.0: +; GFX1250-TRUE16-NEXT: s_clause 0x1 +; GFX1250-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0 +; GFX1250-TRUE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x10 +; GFX1250-TRUE16-NEXT: v_and_b32_e32 v1, 0x3ff, v0 +; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-TRUE16-NEXT: s_clause 0x1 +; GFX1250-TRUE16-NEXT: global_load_u8 v0, v1, s[2:3] +; GFX1250-TRUE16-NEXT: global_load_u8 v2, v1, s[6:7] +; GFX1250-TRUE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250-TRUE16-NEXT: v_min_u16 v0.l, v0.l, v2.l +; GFX1250-TRUE16-NEXT: global_store_b8 v1, v0, s[0:1] +; GFX1250-TRUE16-NEXT: s_endpgm +; +; GFX1250-FAKE16-LABEL: v_test_umin_ult_i8: +; GFX1250-FAKE16: ; %bb.0: +; GFX1250-FAKE16-NEXT: s_clause 0x1 +; GFX1250-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0 +; GFX1250-FAKE16-NEXT: s_load_b64 s[6:7], s[4:5], 0x10 +; GFX1250-FAKE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0 +; GFX1250-FAKE16-NEXT: s_clause 0x1 +; GFX1250-FAKE16-NEXT: global_load_u8 v1, v0, s[2:3] +; GFX1250-FAKE16-NEXT: global_load_u8 v2, v0, s[6:7] +; GFX1250-FAKE16-NEXT: s_wait_loadcnt 0x0 +; GFX1250-FAKE16-NEXT: v_min_u16 v1, v1, v2 +; GFX1250-FAKE16-NEXT: global_store_b8 v0, v1, s[0:1] +; GFX1250-FAKE16-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %a.gep = getelementptr inbounds i8, ptr addrspace(1) %a.ptr, i32 %tid %b.gep = getelementptr inbounds i8, ptr addrspace(1) %b.ptr, i32 %tid @@ -5069,5 +5097,3 @@ declare i32 @llvm.amdgcn.workitem.id.x() #1 attributes #0 = { nounwind } attributes #1 = { nounwind readnone } -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; GFX1250-FAKE16: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/minmax.ll b/llvm/test/CodeGen/AMDGPU/minmax.ll index 57e6943..56f9c5d 100644 --- a/llvm/test/CodeGen/AMDGPU/minmax.ll +++ b/llvm/test/CodeGen/AMDGPU/minmax.ll @@ -638,6 +638,14 @@ define void @test_med3_minimumnum_maximumnum_f32(ptr addrspace(1) %arg, float %x ; GFX12-NEXT: v_med3_num_f32 v2, v2, v3, v4 ; GFX12-NEXT: global_store_b32 v[0:1], v2, off ; GFX12-NEXT: s_setpc_b64 s[30:31] +; +; GFX1250-LABEL: test_med3_minimumnum_maximumnum_f32: +; GFX1250: ; %bb.0: +; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-NEXT: s_wait_kmcnt 0x0 +; GFX1250-NEXT: v_med3_num_f32 v2, v2, v3, v4 +; GFX1250-NEXT: global_store_b32 v[0:1], v2, off +; GFX1250-NEXT: s_set_pc_i64 s[30:31] %tmp0 = call float @llvm.minimumnum.f32(float %x, float %y) %tmp1 = call float @llvm.maximumnum.f32(float %x, float %y) %tmp2 = call float @llvm.minimumnum.f32(float %tmp1, float %z) @@ -798,7 +806,7 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b ; SDAG-GFX1250-TRUE16-NEXT: s_mov_b32 s5, s4 ; SDAG-GFX1250-TRUE16-NEXT: s_mov_b32 s4, s3 ; SDAG-GFX1250-TRUE16-NEXT: v_maxmin_num_f16 v0.l, s0, s1, v0.l -; SDAG-GFX1250-TRUE16-NEXT: flat_store_b16 v1, v0, s[4:5] +; SDAG-GFX1250-TRUE16-NEXT: global_store_b16 v1, v0, s[4:5] ; SDAG-GFX1250-TRUE16-NEXT: s_endpgm ; ; SDAG-GFX1250-FAKE16-LABEL: s_test_minmax_f16_ieee_false: @@ -813,12 +821,12 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b ; GISEL-GFX1250-TRUE16-LABEL: s_test_minmax_f16_ieee_false: ; GISEL-GFX1250-TRUE16: ; %bb.0: ; GISEL-GFX1250-TRUE16-NEXT: s_max_num_f16 s0, s0, s1 +; GISEL-GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, 0 ; GISEL-GFX1250-TRUE16-NEXT: s_mov_b32 s6, s3 ; GISEL-GFX1250-TRUE16-NEXT: s_mov_b32 s7, s4 -; GISEL-GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, 0 ; GISEL-GFX1250-TRUE16-NEXT: s_min_num_f16 s0, s0, s2 -; GISEL-GFX1250-TRUE16-NEXT: v_mov_b32_e32 v0, s0 -; GISEL-GFX1250-TRUE16-NEXT: flat_store_b16 v1, v0, s[6:7] +; GISEL-GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0 +; GISEL-GFX1250-TRUE16-NEXT: global_store_b16 v1, v0, s[6:7] ; GISEL-GFX1250-TRUE16-NEXT: s_endpgm ; ; GISEL-GFX1250-FAKE16-LABEL: s_test_minmax_f16_ieee_false: @@ -1246,7 +1254,7 @@ define void @test_med3_f16(ptr addrspace(1) %arg, half %x, half %y, half %z) #0 ; SDAG-GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; SDAG-GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0 ; SDAG-GFX1250-TRUE16-NEXT: v_med3_num_f16 v2.l, v2.l, v3.l, v4.l -; SDAG-GFX1250-TRUE16-NEXT: flat_store_b16 v[0:1], v2 +; SDAG-GFX1250-TRUE16-NEXT: global_store_b16 v[0:1], v2, off ; SDAG-GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31] ; ; SDAG-GFX1250-FAKE16-LABEL: test_med3_f16: @@ -1262,7 +1270,7 @@ define void @test_med3_f16(ptr addrspace(1) %arg, half %x, half %y, half %z) #0 ; GISEL-GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GISEL-GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0 ; GISEL-GFX1250-TRUE16-NEXT: v_med3_num_f16 v2.l, v2.l, v3.l, v4.l -; GISEL-GFX1250-TRUE16-NEXT: flat_store_b16 v[0:1], v2 +; GISEL-GFX1250-TRUE16-NEXT: global_store_b16 v[0:1], v2, off ; GISEL-GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31] ; ; GISEL-GFX1250-FAKE16-LABEL: test_med3_f16: diff --git a/llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll b/llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll index 42469c8..23e90b3 100644 --- a/llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll +++ b/llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll @@ -202,13 +202,13 @@ attributes #5 = { "amdgpu-flat-work-group-size"="128,512" } attributes #6 = { "amdgpu-flat-work-group-size"="512,512" } attributes #7 = { "amdgpu-flat-work-group-size"="64,256" } ;. -; CHECK: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="1,256" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="64,128" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR2]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="128,512" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR3]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="64,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR4]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="128,256" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR5]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="512,1024" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR6]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="512,512" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR7]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="64,256" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR8]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR0]] = { "amdgpu-flat-work-group-size"="1,256" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR1]] = { "amdgpu-flat-work-group-size"="64,128" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR2]] = { "amdgpu-flat-work-group-size"="128,512" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR3]] = { "amdgpu-flat-work-group-size"="64,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR4]] = { "amdgpu-flat-work-group-size"="128,256" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR5]] = { "amdgpu-flat-work-group-size"="512,1024" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR6]] = { "amdgpu-flat-work-group-size"="512,512" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR7]] = { "amdgpu-flat-work-group-size"="64,256" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR8]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } ;. diff --git a/llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll b/llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll index 06533b4..0be3147 100644 --- a/llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll +++ b/llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll @@ -399,25 +399,25 @@ attributes #17 = { "amdgpu-waves-per-eu"="5,8" } attributes #18 = { "amdgpu-waves-per-eu"="9,10" } attributes #19 = { "amdgpu-waves-per-eu"="8,9" } ;. -; CHECK: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="2,8" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="1,8" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR2]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="1,2" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR3]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="1,4" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR4]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="9,9" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR5]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="1,1" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR6]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="9,10" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR7]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="2,9" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR8]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="3,8" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR9]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR10]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR11]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="1,123" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR12]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="1,512" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR13]] = { "amdgpu-agpr-alloc"="0" "amdgpu-flat-work-group-size"="1,512" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="3,6" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR14]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="3,6" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR15]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,8" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR16]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="6,8" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR17]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="5,5" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR18]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="5,8" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR19]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="9,10" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR20]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="8,9" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR0]] = { "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="2,8" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR1]] = { "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="1,8" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR2]] = { "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="1,2" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR3]] = { "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="1,4" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR4]] = { "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="9,9" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR5]] = { "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="1,1" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR6]] = { "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="9,10" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR7]] = { "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="2,9" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR8]] = { "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="3,8" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR9]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR10]] = { "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR11]] = { "amdgpu-flat-work-group-size"="1,64" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="1,123" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR12]] = { "amdgpu-flat-work-group-size"="1,512" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR13]] = { "amdgpu-flat-work-group-size"="1,512" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="3,6" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR14]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="3,6" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR15]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,8" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR16]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="6,8" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR17]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="5,5" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR18]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="5,8" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR19]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="9,10" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR20]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="8,9" "uniform-work-group-size"="false" } ;. diff --git a/llvm/test/CodeGen/AMDGPU/recursive_global_initializer.ll b/llvm/test/CodeGen/AMDGPU/recursive_global_initializer.ll index 8930626..33da671 100644 --- a/llvm/test/CodeGen/AMDGPU/recursive_global_initializer.ll +++ b/llvm/test/CodeGen/AMDGPU/recursive_global_initializer.ll @@ -19,5 +19,5 @@ define void @hoge() { ret void } ;. -; CHECK: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } ;. diff --git a/llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll b/llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll index 3dfb0e1..f847d66 100644 --- a/llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll +++ b/llvm/test/CodeGen/AMDGPU/remove-no-kernel-id-attribute.ll @@ -191,12 +191,12 @@ define amdgpu_kernel void @kernel_lds_recursion() { !1 = !{i32 1, !"amdhsa_code_object_version", i32 400} ;. -; CHECK: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR2]] = { "amdgpu-agpr-alloc"="0" "amdgpu-lds-size"="2" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR1]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR2]] = { "amdgpu-lds-size"="2" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } ; CHECK: attributes #[[ATTR3]] = { "amdgpu-lds-size"="4" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR4]] = { "amdgpu-agpr-alloc"="0" "amdgpu-lds-size"="2" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR5]] = { "amdgpu-agpr-alloc"="0" "amdgpu-lds-size"="4" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR4]] = { "amdgpu-lds-size"="2" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR5]] = { "amdgpu-lds-size"="4" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } ; CHECK: attributes #[[ATTR6:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) } ; CHECK: attributes #[[ATTR7:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } ;. diff --git a/llvm/test/CodeGen/AMDGPU/simple-indirect-call-2.ll b/llvm/test/CodeGen/AMDGPU/simple-indirect-call-2.ll index f1cadea..0868148 100644 --- a/llvm/test/CodeGen/AMDGPU/simple-indirect-call-2.ll +++ b/llvm/test/CodeGen/AMDGPU/simple-indirect-call-2.ll @@ -63,7 +63,7 @@ define amdgpu_kernel void @foo(ptr noundef %fp) { ; OW-NEXT: ret void ; ; CW-LABEL: define {{[^@]+}}@foo -; CW-SAME: (ptr noundef [[FP:%.*]]) #[[ATTR1:[0-9]+]] { +; CW-SAME: (ptr noundef [[FP:%.*]]) #[[ATTR0]] { ; CW-NEXT: entry: ; CW-NEXT: [[FP_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; CW-NEXT: store ptr [[FP]], ptr addrspace(5) [[FP_ADDR]], align 8 @@ -84,7 +84,7 @@ define amdgpu_kernel void @foo(ptr noundef %fp) { ; CW-NEXT: ret void ; ; NO-LABEL: define {{[^@]+}}@foo -; NO-SAME: (ptr noundef [[FP:%.*]]) #[[ATTR1:[0-9]+]] { +; NO-SAME: (ptr noundef [[FP:%.*]]) #[[ATTR0]] { ; NO-NEXT: entry: ; NO-NEXT: [[FP_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) ; NO-NEXT: store ptr [[FP]], ptr addrspace(5) [[FP_ADDR]], align 8 @@ -101,14 +101,12 @@ entry: } ;. -; NO: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; NO: attributes #[[ATTR1]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; NO: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } ;. -; OW: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; OW: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } ; OW: attributes #[[ATTR1]] = { "uniform-work-group-size"="false" } ;. -; CW: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CW: attributes #[[ATTR1]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CW: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } ;. ; NO: [[META0]] = !{ptr @bar1, ptr @bar2} ;. diff --git a/llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll b/llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll index 775d2f9..8fcaf5e 100644 --- a/llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll +++ b/llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll @@ -58,7 +58,7 @@ define amdgpu_kernel void @test_simple_indirect_call() { ;. -; ATTRIBUTOR_GCN: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; ATTRIBUTOR_GCN: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } ; ATTRIBUTOR_GCN: attributes #[[ATTR1]] = { "uniform-work-group-size"="false" } ;. ; ATTRIBUTOR_GCN: [[META0]] = !{i32 1, i32 5, i32 6, i32 10} diff --git a/llvm/test/CodeGen/AMDGPU/uniform-work-group-attribute-missing.ll b/llvm/test/CodeGen/AMDGPU/uniform-work-group-attribute-missing.ll index a1557418..8dfd3b7 100644 --- a/llvm/test/CodeGen/AMDGPU/uniform-work-group-attribute-missing.ll +++ b/llvm/test/CodeGen/AMDGPU/uniform-work-group-attribute-missing.ll @@ -31,5 +31,5 @@ define amdgpu_kernel void @kernel1() #1 { attributes #0 = { "uniform-work-group-size"="true" } ;. -; CHECK: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } ;. diff --git a/llvm/test/CodeGen/AMDGPU/uniform-work-group-multistep.ll b/llvm/test/CodeGen/AMDGPU/uniform-work-group-multistep.ll index fb225a9..fa01ee9 100644 --- a/llvm/test/CodeGen/AMDGPU/uniform-work-group-multistep.ll +++ b/llvm/test/CodeGen/AMDGPU/uniform-work-group-multistep.ll @@ -98,7 +98,7 @@ define amdgpu_kernel void @kernel2() #0 { attributes #0 = { "uniform-work-group-size"="true" } ;. ; CHECK: attributes #[[ATTR0]] = { "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR1]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } ; CHECK: attributes #[[ATTR2]] = { "uniform-work-group-size"="true" } -; CHECK: attributes #[[ATTR3]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="true" } +; CHECK: attributes #[[ATTR3]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="true" } ;. diff --git a/llvm/test/CodeGen/AMDGPU/uniform-work-group-nested-function-calls.ll b/llvm/test/CodeGen/AMDGPU/uniform-work-group-nested-function-calls.ll index cfede0c..09001ca 100644 --- a/llvm/test/CodeGen/AMDGPU/uniform-work-group-nested-function-calls.ll +++ b/llvm/test/CodeGen/AMDGPU/uniform-work-group-nested-function-calls.ll @@ -41,6 +41,6 @@ define amdgpu_kernel void @kernel3() #2 { attributes #2 = { "uniform-work-group-size"="true" } ;. -; CHECK: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="true" } +; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR1]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="true" } ;. diff --git a/llvm/test/CodeGen/AMDGPU/uniform-work-group-prevent-attribute-propagation.ll b/llvm/test/CodeGen/AMDGPU/uniform-work-group-prevent-attribute-propagation.ll index 854b724..4dede21 100644 --- a/llvm/test/CodeGen/AMDGPU/uniform-work-group-prevent-attribute-propagation.ll +++ b/llvm/test/CodeGen/AMDGPU/uniform-work-group-prevent-attribute-propagation.ll @@ -41,6 +41,6 @@ define amdgpu_kernel void @kernel2() #2 { attributes #1 = { "uniform-work-group-size"="true" } ;. -; CHECK: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="true" } +; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR1]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="true" } ;. diff --git a/llvm/test/CodeGen/AMDGPU/uniform-work-group-propagate-attribute.ll b/llvm/test/CodeGen/AMDGPU/uniform-work-group-propagate-attribute.ll index c4e0a60..08e1556 100644 --- a/llvm/test/CodeGen/AMDGPU/uniform-work-group-propagate-attribute.ll +++ b/llvm/test/CodeGen/AMDGPU/uniform-work-group-propagate-attribute.ll @@ -52,8 +52,8 @@ attributes #0 = { nounwind } attributes #1 = { "uniform-work-group-size"="false" } attributes #2 = { "uniform-work-group-size"="true" } ;. -; CHECK: attributes #[[ATTR0]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR0]] = { nounwind "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR1]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } ; CHECK: attributes #[[ATTR2]] = { nounwind "uniform-work-group-size"="false" } ; CHECK: attributes #[[ATTR3]] = { "uniform-work-group-size"="true" } ;. diff --git a/llvm/test/CodeGen/AMDGPU/uniform-work-group-recursion-test.ll b/llvm/test/CodeGen/AMDGPU/uniform-work-group-recursion-test.ll index 05af74d..9090d605 100644 --- a/llvm/test/CodeGen/AMDGPU/uniform-work-group-recursion-test.ll +++ b/llvm/test/CodeGen/AMDGPU/uniform-work-group-recursion-test.ll @@ -101,7 +101,7 @@ define amdgpu_kernel void @kernel(ptr addrspace(1) %m) #1 { attributes #0 = { nounwind readnone } attributes #1 = { "uniform-work-group-size"="true" } ;. -; CHECK: attributes #[[ATTR0]] = { nounwind memory(none) "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } -; CHECK: attributes #[[ATTR1]] = { nounwind memory(none) "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="true" } -; CHECK: attributes #[[ATTR2]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="true" } +; CHECK: attributes #[[ATTR0]] = { nounwind memory(none) "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR1]] = { nounwind memory(none) "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="true" } +; CHECK: attributes #[[ATTR2]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="true" } ;. diff --git a/llvm/test/CodeGen/AMDGPU/uniform-work-group-test.ll b/llvm/test/CodeGen/AMDGPU/uniform-work-group-test.ll index cdbca7f..5e109f4 100644 --- a/llvm/test/CodeGen/AMDGPU/uniform-work-group-test.ll +++ b/llvm/test/CodeGen/AMDGPU/uniform-work-group-test.ll @@ -61,5 +61,5 @@ define amdgpu_kernel void @kernel3() #0 { attributes #0 = { "uniform-work-group-size"="false" } ;. -; CHECK: attributes #[[ATTR0]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } +; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-cluster-id-x" "amdgpu-no-cluster-id-y" "amdgpu-no-cluster-id-z" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" } ;. diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir index 77eeb34..4dd8af0 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir @@ -447,7 +447,7 @@ body: | ; CHECK-LABEL: name: test_vnmuls ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 - ; CHECK: [[VNMULS:%[0-9]+]]:spr = VNMULS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK: [[VNMULS:%[0-9]+]]:spr = nofpexcept VNMULS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK: $s0 = COPY [[VNMULS]] ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 @@ -477,7 +477,7 @@ body: | ; CHECK-LABEL: name: test_vnmuls_reassociate ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 - ; CHECK: [[VNMULS:%[0-9]+]]:spr = VNMULS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK: [[VNMULS:%[0-9]+]]:spr = nofpexcept VNMULS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK: $s0 = COPY [[VNMULS]] ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 @@ -507,7 +507,7 @@ body: | ; CHECK-LABEL: name: test_vnmuld ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 - ; CHECK: [[VNMULD:%[0-9]+]]:dpr = VNMULD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK: [[VNMULD:%[0-9]+]]:dpr = nofpexcept VNMULD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK: $d0 = COPY [[VNMULD]] ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s64) = COPY $d0 @@ -539,7 +539,7 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[COPY2:%[0-9]+]]:spr = COPY $s2 - ; CHECK: [[VFNMAS:%[0-9]+]]:spr = VFNMAS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK: [[VFNMAS:%[0-9]+]]:spr = nofpexcept VFNMAS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK: $s0 = COPY [[VFNMAS]] ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 @@ -573,7 +573,7 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2 - ; CHECK: [[VFNMAD:%[0-9]+]]:dpr = VFNMAD [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK: [[VFNMAD:%[0-9]+]]:dpr = nofpexcept VFNMAD [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK: $d0 = COPY [[VFNMAD]] ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s64) = COPY $d0 @@ -607,7 +607,7 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[COPY2:%[0-9]+]]:spr = COPY $s2 - ; CHECK: [[VFMSS:%[0-9]+]]:spr = VFMSS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK: [[VFMSS:%[0-9]+]]:spr = nofpexcept VFMSS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK: $s0 = COPY [[VFMSS]] ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 @@ -640,7 +640,7 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2 - ; CHECK: [[VFMSD:%[0-9]+]]:dpr = VFMSD [[COPY2]], [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg + ; CHECK: [[VFMSD:%[0-9]+]]:dpr = nofpexcept VFMSD [[COPY2]], [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK: $d0 = COPY [[VFMSD]] ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s64) = COPY $d0 @@ -673,7 +673,7 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 ; CHECK: [[COPY2:%[0-9]+]]:spr = COPY $s2 - ; CHECK: [[VFNMSS:%[0-9]+]]:spr = VFNMSS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK: [[VFNMSS:%[0-9]+]]:spr = nofpexcept VFNMSS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK: $s0 = COPY [[VFNMSS]] ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir index 45a846b..4cded13 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir @@ -19,7 +19,7 @@ body: | bb.1: ; CHECK-LABEL: name: test_fptosi ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 - ; CHECK: [[VTOSIZS:%[0-9]+]]:spr = VTOSIZS [[COPY]], 14 /* CC::al */, $noreg + ; CHECK: [[VTOSIZS:%[0-9]+]]:spr = nofpexcept VTOSIZS [[COPY]], 14 /* CC::al */, $noreg ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZS]] ; CHECK: $r0 = COPY [[COPY1]] ; CHECK: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 diff --git a/llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir b/llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir index ec834f1..4517fe6 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 # RUN: llc -O0 -mtriple arm-- -mattr=+vfp4,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+vfp4,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- | @@ -76,11 +77,9 @@ body: | ... --- name: test_fadd_s32 -# CHECK-LABEL: name: test_fadd_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -89,28 +88,29 @@ body: | bb.0: liveins: $s0, $s1 + ; CHECK-LABEL: name: test_fadd_s32 + ; CHECK: liveins: $s0, $s1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY $s1 + ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nofpexcept VADDS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $s0 = COPY [[VADDS]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 - ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s32) = COPY $s1 - ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 %2(s32) = G_FADD %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg $s0 = COPY %2(s32) - ; CHECK: $s0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 ... --- name: test_fadd_s64 -# CHECK-LABEL: name: test_fadd_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -119,28 +119,29 @@ body: | bb.0: liveins: $d0, $d1 + ; CHECK-LABEL: name: test_fadd_s64 + ; CHECK: liveins: $d0, $d1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:dpr = COPY $d1 + ; CHECK-NEXT: [[VADDD:%[0-9]+]]:dpr = nofpexcept VADDD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $d0 = COPY [[VADDD]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s64) = COPY $d0 - ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s64) = COPY $d1 - ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 %2(s64) = G_FADD %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg $d0 = COPY %2(s64) - ; CHECK: $d0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ... --- name: test_fsub_s32 -# CHECK-LABEL: name: test_fsub_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -149,28 +150,29 @@ body: | bb.0: liveins: $s0, $s1 + ; CHECK-LABEL: name: test_fsub_s32 + ; CHECK: liveins: $s0, $s1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY $s1 + ; CHECK-NEXT: [[VSUBS:%[0-9]+]]:spr = nofpexcept VSUBS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $s0 = COPY [[VSUBS]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 - ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s32) = COPY $s1 - ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 %2(s32) = G_FSUB %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg $s0 = COPY %2(s32) - ; CHECK: $s0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 ... --- name: test_fsub_s64 -# CHECK-LABEL: name: test_fsub_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -179,28 +181,29 @@ body: | bb.0: liveins: $d0, $d1 + ; CHECK-LABEL: name: test_fsub_s64 + ; CHECK: liveins: $d0, $d1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:dpr = COPY $d1 + ; CHECK-NEXT: [[VSUBD:%[0-9]+]]:dpr = nofpexcept VSUBD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $d0 = COPY [[VSUBD]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s64) = COPY $d0 - ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s64) = COPY $d1 - ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 %2(s64) = G_FSUB %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg $d0 = COPY %2(s64) - ; CHECK: $d0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ... --- name: test_fmul_s32 -# CHECK-LABEL: name: test_fmul_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -209,28 +212,29 @@ body: | bb.0: liveins: $s0, $s1 + ; CHECK-LABEL: name: test_fmul_s32 + ; CHECK: liveins: $s0, $s1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY $s1 + ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nofpexcept VMULS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $s0 = COPY [[VMULS]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 - ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s32) = COPY $s1 - ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 %2(s32) = G_FMUL %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg $s0 = COPY %2(s32) - ; CHECK: $s0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 ... --- name: test_fmul_s64 -# CHECK-LABEL: name: test_fmul_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -239,28 +243,29 @@ body: | bb.0: liveins: $d0, $d1 + ; CHECK-LABEL: name: test_fmul_s64 + ; CHECK: liveins: $d0, $d1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:dpr = COPY $d1 + ; CHECK-NEXT: [[VMULD:%[0-9]+]]:dpr = nofpexcept VMULD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $d0 = COPY [[VMULD]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s64) = COPY $d0 - ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s64) = COPY $d1 - ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 %2(s64) = G_FMUL %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg $d0 = COPY %2(s64) - ; CHECK: $d0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ... --- name: test_fdiv_s32 -# CHECK-LABEL: name: test_fdiv_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -269,28 +274,29 @@ body: | bb.0: liveins: $s0, $s1 + ; CHECK-LABEL: name: test_fdiv_s32 + ; CHECK: liveins: $s0, $s1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY $s1 + ; CHECK-NEXT: [[VDIVS:%[0-9]+]]:spr = nofpexcept VDIVS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $s0 = COPY [[VDIVS]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 - ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s32) = COPY $s1 - ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 %2(s32) = G_FDIV %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg $s0 = COPY %2(s32) - ; CHECK: $s0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 ... --- name: test_fdiv_s64 -# CHECK-LABEL: name: test_fdiv_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -299,28 +305,29 @@ body: | bb.0: liveins: $d0, $d1 + ; CHECK-LABEL: name: test_fdiv_s64 + ; CHECK: liveins: $d0, $d1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:dpr = COPY $d1 + ; CHECK-NEXT: [[VDIVD:%[0-9]+]]:dpr = nofpexcept VDIVD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $d0 = COPY [[VDIVD]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s64) = COPY $d0 - ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s64) = COPY $d1 - ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 %2(s64) = G_FDIV %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg $d0 = COPY %2(s64) - ; CHECK: $d0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ... --- name: test_fneg_s32 -# CHECK-LABEL: name: test_fneg_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -328,25 +335,26 @@ body: | bb.0: liveins: $s0 + ; CHECK-LABEL: name: test_fneg_s32 + ; CHECK: liveins: $s0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK-NEXT: [[VNEGS:%[0-9]+]]:spr = VNEGS [[COPY]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: $s0 = COPY [[VNEGS]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 - ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s32) = G_FNEG %0 - ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VNEGS [[VREGX]], 14 /* CC::al */, $noreg $s0 = COPY %1(s32) - ; CHECK: $s0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 ... --- name: test_fneg_s64 -# CHECK-LABEL: name: test_fneg_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -355,25 +363,26 @@ body: | bb.0: liveins: $d0 + ; CHECK-LABEL: name: test_fneg_s64 + ; CHECK: liveins: $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK-NEXT: [[VNEGD:%[0-9]+]]:dpr = VNEGD [[COPY]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: $d0 = COPY [[VNEGD]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s64) = COPY $d0 - ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s64) = G_FNEG %0 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VNEGD [[VREGX]], 14 /* CC::al */, $noreg $d0 = COPY %1(s64) - ; CHECK: $d0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ... --- name: test_fma_s32 -# CHECK-LABEL: name: test_fma_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -383,31 +392,32 @@ body: | bb.0: liveins: $s0, $s1, $s2 + ; CHECK-LABEL: name: test_fma_s32 + ; CHECK: liveins: $s0, $s1, $s2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY $s1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:spr = COPY $s2 + ; CHECK-NEXT: [[VFMAS:%[0-9]+]]:spr = nofpexcept VFMAS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $s0 = COPY [[VFMAS]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $s0 - ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s32) = COPY $s1 - ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 %2(s32) = COPY $s2 - ; CHECK: [[VREGZ:%[0-9]+]]:spr = COPY $s2 %3(s32) = G_FMA %0, %1, %2 - ; CHECK: [[VREGR:%[0-9]+]]:spr = VFMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg $s0 = COPY %3(s32) - ; CHECK: $s0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 ... --- name: test_fma_s64 -# CHECK-LABEL: name: test_fma_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -417,31 +427,32 @@ body: | bb.0: liveins: $d0, $d1, $d2 + ; CHECK-LABEL: name: test_fma_s64 + ; CHECK: liveins: $d0, $d1, $d2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:dpr = COPY $d1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:dpr = COPY $d2 + ; CHECK-NEXT: [[VFMAD:%[0-9]+]]:dpr = nofpexcept VFMAD [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $d0 = COPY [[VFMAD]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s64) = COPY $d0 - ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s64) = COPY $d1 - ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 %2(s64) = COPY $d2 - ; CHECK: [[VREGZ:%[0-9]+]]:dpr = COPY $d2 %3(s64) = G_FMA %0, %1, %2 - ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14 /* CC::al */, $noreg $d0 = COPY %3(s64) - ; CHECK: $d0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ... --- name: test_fpext_s32_to_s64 -# CHECK-LABEL: name: test_fpext_s32_to_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -449,25 +460,26 @@ body: | bb.0: liveins: $s0 + ; CHECK-LABEL: name: test_fpext_s32_to_s64 + ; CHECK: liveins: $s0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK-NEXT: [[VCVTDS:%[0-9]+]]:dpr = nofpexcept VCVTDS [[COPY]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $d0 = COPY [[VCVTDS]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s32) = COPY $s0 - ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s64) = G_FPEXT %0(s32) - ; CHECK: [[VREGR:%[0-9]+]]:dpr = VCVTDS [[VREGX]], 14 /* CC::al */, $noreg $d0 = COPY %1(s64) - ; CHECK: $d0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ... --- name: test_fptrunc_s64_to_s32 -# CHECK-LABEL: name: test_fptrunc_s64_to_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -475,25 +487,26 @@ body: | bb.0: liveins: $d0 + ; CHECK-LABEL: name: test_fptrunc_s64_to_s32 + ; CHECK: liveins: $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK-NEXT: [[VCVTSD:%[0-9]+]]:spr = nofpexcept VCVTSD [[COPY]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: $s0 = COPY [[VCVTSD]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s64) = COPY $d0 - ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s32) = G_FPTRUNC %0(s64) - ; CHECK: [[VREGR:%[0-9]+]]:spr = VCVTSD [[VREGX]], 14 /* CC::al */, $noreg $s0 = COPY %1(s32) - ; CHECK: $s0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 ... --- name: test_fptosi_s32 -# CHECK-LABEL: name: test_fptosi_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: gprb } @@ -501,26 +514,27 @@ body: | bb.0: liveins: $s0 + ; CHECK-LABEL: name: test_fptosi_s32 + ; CHECK: liveins: $s0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK-NEXT: [[VTOSIZS:%[0-9]+]]:spr = nofpexcept VTOSIZS [[COPY]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZS]] + ; CHECK-NEXT: $r0 = COPY [[COPY1]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0 %0(s32) = COPY $s0 - ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s32) = G_FPTOSI %0(s32) - ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZS [[VREGX]], 14 /* CC::al */, $noreg - ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] $r0 = COPY %1(s32) - ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0 ... --- name: test_fptosi_s64 -# CHECK-LABEL: name: test_fptosi_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: gprb } @@ -528,26 +542,27 @@ body: | bb.0: liveins: $d0 + ; CHECK-LABEL: name: test_fptosi_s64 + ; CHECK: liveins: $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK-NEXT: [[VTOSIZD:%[0-9]+]]:spr = nofpexcept VTOSIZD [[COPY]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZD]] + ; CHECK-NEXT: $r0 = COPY [[COPY1]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0 %0(s64) = COPY $d0 - ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s32) = G_FPTOSI %0(s64) - ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZD [[VREGX]], 14 /* CC::al */, $noreg - ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] $r0 = COPY %1(s32) - ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0 ... --- name: test_fptoui_s32 -# CHECK-LABEL: name: test_fptoui_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: gprb } @@ -555,26 +570,27 @@ body: | bb.0: liveins: $s0 + ; CHECK-LABEL: name: test_fptoui_s32 + ; CHECK: liveins: $s0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK-NEXT: [[VTOUIZS:%[0-9]+]]:spr = nofpexcept VTOUIZS [[COPY]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOUIZS]] + ; CHECK-NEXT: $r0 = COPY [[COPY1]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0 %0(s32) = COPY $s0 - ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s32) = G_FPTOUI %0(s32) - ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZS [[VREGX]], 14 /* CC::al */, $noreg - ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] $r0 = COPY %1(s32) - ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0 ... --- name: test_fptoui_s64 -# CHECK-LABEL: name: test_fptoui_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: gprb } @@ -582,26 +598,27 @@ body: | bb.0: liveins: $d0 + ; CHECK-LABEL: name: test_fptoui_s64 + ; CHECK: liveins: $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK-NEXT: [[VTOUIZD:%[0-9]+]]:spr = nofpexcept VTOUIZD [[COPY]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOUIZD]] + ; CHECK-NEXT: $r0 = COPY [[COPY1]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0 %0(s64) = COPY $d0 - ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s32) = G_FPTOUI %0(s64) - ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZD [[VREGX]], 14 /* CC::al */, $noreg - ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] $r0 = COPY %1(s32) - ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0 ... --- name: test_sitofp_s32 -# CHECK-LABEL: name: test_sitofp_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: fprb } @@ -609,26 +626,27 @@ body: | bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_sitofp_s32 + ; CHECK: liveins: $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY [[COPY]] + ; CHECK-NEXT: [[VSITOS:%[0-9]+]]:spr = nofpexcept VSITOS [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: $s0 = COPY [[VSITOS]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = G_SITOFP %0(s32) - ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] - ; CHECK: [[VREGR:%[0-9]+]]:spr = VSITOS [[VREGF]], 14 /* CC::al */, $noreg $s0 = COPY %1(s32) - ; CHECK: $s0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 ... --- name: test_sitofp_s64 -# CHECK-LABEL: name: test_sitofp_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: fprb } @@ -636,26 +654,27 @@ body: | bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_sitofp_s64 + ; CHECK: liveins: $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY [[COPY]] + ; CHECK-NEXT: [[VSITOD:%[0-9]+]]:dpr = nofpexcept VSITOD [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: $d0 = COPY [[VSITOD]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s64) = G_SITOFP %0(s32) - ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] - ; CHECK: [[VREGR:%[0-9]+]]:dpr = VSITOD [[VREGF]], 14 /* CC::al */, $noreg $d0 = COPY %1(s64) - ; CHECK: $d0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ... --- name: test_uitofp_s32 -# CHECK-LABEL: name: test_uitofp_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: fprb } @@ -663,26 +682,27 @@ body: | bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_uitofp_s32 + ; CHECK: liveins: $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY [[COPY]] + ; CHECK-NEXT: [[VUITOS:%[0-9]+]]:spr = nofpexcept VUITOS [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: $s0 = COPY [[VUITOS]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = G_UITOFP %0(s32) - ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] - ; CHECK: [[VREGR:%[0-9]+]]:spr = VUITOS [[VREGF]], 14 /* CC::al */, $noreg $s0 = COPY %1(s32) - ; CHECK: $s0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 ... --- name: test_uitofp_s64 -# CHECK-LABEL: name: test_uitofp_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: fprb } @@ -690,26 +710,27 @@ body: | bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_uitofp_s64 + ; CHECK: liveins: $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY [[COPY]] + ; CHECK-NEXT: [[VUITOD:%[0-9]+]]:dpr = nofpexcept VUITOD [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: $d0 = COPY [[VUITOD]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s64) = G_UITOFP %0(s32) - ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] - ; CHECK: [[VREGR:%[0-9]+]]:dpr = VUITOD [[VREGF]], 14 /* CC::al */, $noreg $d0 = COPY %1(s64) - ; CHECK: $d0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ... --- name: test_load_f32 -# CHECK-LABEL: name: test_load_f32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: fprb } @@ -717,25 +738,26 @@ body: | bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_load_f32 + ; CHECK: liveins: $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK-NEXT: [[VLDRS:%[0-9]+]]:spr = VLDRS [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s32)) + ; CHECK-NEXT: $s0 = COPY [[VLDRS]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0 %0(p0) = COPY $r0 - ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0 %1(s32) = G_LOAD %0(p0) :: (load (s32)) - ; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14 /* CC::al */, $noreg $s0 = COPY %1 - ; CHECK: $s0 = COPY %[[V]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0 ... --- name: test_load_f64 -# CHECK-LABEL: name: test_load_f64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: fprb } @@ -743,45 +765,50 @@ body: | bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_load_f64 + ; CHECK: liveins: $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK-NEXT: [[VLDRD:%[0-9]+]]:dpr = VLDRD [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s64)) + ; CHECK-NEXT: $d0 = COPY [[VLDRD]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0 %0(p0) = COPY $r0 - ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0 %1(s64) = G_LOAD %0(p0) :: (load (s64)) - ; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14 /* CC::al */, $noreg $d0 = COPY %1 - ; CHECK: $d0 = COPY %[[V]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0 ... --- name: test_stores -# CHECK-LABEL: name: test_stores legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: fprb } - { id: 2, class: fprb } -# CHECK: id: [[P:[0-9]+]], class: gpr -# CHECK: id: [[F32:[0-9]+]], class: spr -# CHECK: id: [[F64:[0-9]+]], class: dpr body: | bb.0: liveins: $r0, $s0, $d0 + ; CHECK-LABEL: name: test_stores + ; CHECK: liveins: $r0, $s0, $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY $s0 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:dpr = COPY $d2 + ; CHECK-NEXT: VSTRS [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32)) + ; CHECK-NEXT: VSTRD [[COPY2]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s64)) + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg %0(p0) = COPY $r0 %1(s32) = COPY $s0 %2(s64) = COPY $d2 G_STORE %1(s32), %0(p0) :: (store (s32)) - ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14 /* CC::al */, $noreg G_STORE %2(s64), %0(p0) :: (store (s64)) - ; CHECK: VSTRD %[[F64]], %[[P]], 0, 14 /* CC::al */, $noreg BX_RET 14, $noreg ... @@ -833,11 +860,9 @@ body: | ... --- name: test_soft_fp_double -# CHECK-LABEL: name: test_soft_fp_double legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -848,24 +873,27 @@ body: | bb.0: liveins: $r0, $r1, $r2, $r3 + ; CHECK-LABEL: name: test_soft_fp_double + ; CHECK: liveins: $r0, $r1, $r2, $r3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r3 + ; CHECK-NEXT: [[VMOVDRR:%[0-9]+]]:dpr = VMOVDRR [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMOVRRD:%[0-9]+]]:gpr, [[VMOVRRD1:%[0-9]+]]:gpr = VMOVRRD [[VMOVDRR]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: $r0 = COPY [[VMOVRRD]] + ; CHECK-NEXT: $r1 = COPY [[VMOVRRD1]] + ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1 %0(s32) = COPY $r2 - ; CHECK: [[IN1:%[0-9]+]]:gpr = COPY $r2 %1(s32) = COPY $r3 - ; CHECK: [[IN2:%[0-9]+]]:gpr = COPY $r3 %2(s64) = G_MERGE_VALUES %0(s32), %1(s32) - ; CHECK: %[[DREG:[0-9]+]]:dpr = VMOVDRR [[IN1]], [[IN2]] %3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64) - ; CHECK: [[OUT1:%[0-9]+]]:gpr, [[OUT2:%[0-9]+]]:gpr = VMOVRRD %[[DREG]] $r0 = COPY %3 - ; CHECK: $r0 = COPY [[OUT1]] $r1 = COPY %4 - ; CHECK: $r1 = COPY [[OUT2]] BX_RET 14, $noreg, implicit $r0, implicit $r1 - ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1 ... diff --git a/llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir b/llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir index a6fc4da..fa982d8 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir @@ -31,7 +31,7 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 ; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2 - ; CHECK: [[VFNMSD:%[0-9]+]]:dpr = VFNMSD [[COPY2]], [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg + ; CHECK: [[VFNMSD:%[0-9]+]]:dpr = nofpexcept VFNMSD [[COPY2]], [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK: $d0 = COPY [[VFNMSD]] ; CHECK: MOVPCLR 14 /* CC::al */, $noreg, implicit $d0 %0:fprb(s64) = COPY $d0 diff --git a/llvm/test/CodeGen/ARM/bf16_fast_math.ll b/llvm/test/CodeGen/ARM/bf16_fast_math.ll index 1b18ea6..5f7e1e6 100644 --- a/llvm/test/CodeGen/ARM/bf16_fast_math.ll +++ b/llvm/test/CodeGen/ARM/bf16_fast_math.ll @@ -17,7 +17,7 @@ define bfloat @normal_fadd(bfloat %x, bfloat %y) { ; CHECK-NOBF16-NEXT: [[VMOVSR:%[0-9]+]]:spr = VMOVSR killed [[MOVsi]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: [[MOVsi1:%[0-9]+]]:gpr = MOVsi [[COPY1]], 130, 14 /* CC::al */, $noreg, $noreg ; CHECK-NOBF16-NEXT: [[VMOVSR1:%[0-9]+]]:spr = VMOVSR killed [[MOVsi1]], 14 /* CC::al */, $noreg - ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg + ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = nofpexcept VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-NOBF16-NEXT: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS killed [[VADDS]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp ; CHECK-NOBF16-NEXT: $r0 = COPY [[VMOVRS]] @@ -44,7 +44,7 @@ define bfloat @fast_fadd(bfloat %x, bfloat %y) { ; CHECK-NOBF16-NEXT: [[VMOVSR:%[0-9]+]]:spr = VMOVSR killed [[MOVsi]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: [[MOVsi1:%[0-9]+]]:gpr = MOVsi [[COPY1]], 130, 14 /* CC::al */, $noreg, $noreg ; CHECK-NOBF16-NEXT: [[VMOVSR1:%[0-9]+]]:spr = VMOVSR killed [[MOVsi1]], 14 /* CC::al */, $noreg - ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg + ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc nofpexcept VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-NOBF16-NEXT: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS killed [[VADDS]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp ; CHECK-NOBF16-NEXT: $r0 = COPY [[VMOVRS]] @@ -71,7 +71,7 @@ define bfloat @ninf_fadd(bfloat %x, bfloat %y) { ; CHECK-NOBF16-NEXT: [[VMOVSR:%[0-9]+]]:spr = VMOVSR killed [[MOVsi]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: [[MOVsi1:%[0-9]+]]:gpr = MOVsi [[COPY1]], 130, 14 /* CC::al */, $noreg, $noreg ; CHECK-NOBF16-NEXT: [[VMOVSR1:%[0-9]+]]:spr = VMOVSR killed [[MOVsi1]], 14 /* CC::al */, $noreg - ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = ninf VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg + ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = ninf nofpexcept VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-NOBF16-NEXT: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS killed [[VADDS]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp ; CHECK-NOBF16-NEXT: $r0 = COPY [[VMOVRS]] @@ -102,7 +102,7 @@ define bfloat @normal_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) { ; CHECK-NOBF16-NEXT: [[VMOVSR:%[0-9]+]]:spr = VMOVSR killed [[MOVsi]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: [[MOVsi1:%[0-9]+]]:gpr = MOVsi [[COPY2]], 130, 14 /* CC::al */, $noreg, $noreg ; CHECK-NOBF16-NEXT: [[VMOVSR1:%[0-9]+]]:spr = VMOVSR killed [[MOVsi1]], 14 /* CC::al */, $noreg - ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg + ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = nofpexcept VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-NOBF16-NEXT: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS killed [[VADDS]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp ; CHECK-NOBF16-NEXT: $r0 = COPY [[VMOVRS]] @@ -113,7 +113,7 @@ define bfloat @normal_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) { ; CHECK-NOBF16-NEXT: [[VMOVSR2:%[0-9]+]]:spr = VMOVSR killed [[MOVsi2]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: [[MOVsi3:%[0-9]+]]:gpr = MOVsi [[COPY3]], 130, 14 /* CC::al */, $noreg, $noreg ; CHECK-NOBF16-NEXT: [[VMOVSR3:%[0-9]+]]:spr = VMOVSR killed [[MOVsi3]], 14 /* CC::al */, $noreg - ; CHECK-NOBF16-NEXT: [[VADDS1:%[0-9]+]]:spr = VADDS killed [[VMOVSR3]], killed [[VMOVSR2]], 14 /* CC::al */, $noreg + ; CHECK-NOBF16-NEXT: [[VADDS1:%[0-9]+]]:spr = nofpexcept VADDS killed [[VMOVSR3]], killed [[VMOVSR2]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-NOBF16-NEXT: [[VMOVRS1:%[0-9]+]]:gpr = VMOVRS killed [[VADDS1]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp ; CHECK-NOBF16-NEXT: $r0 = COPY [[VMOVRS1]] @@ -142,10 +142,10 @@ define bfloat @nnan_ninf_contract_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) ; CHECK-NOBF16-NEXT: [[VMOVSR:%[0-9]+]]:spr = VMOVSR killed [[MOVsi]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: [[MOVsi1:%[0-9]+]]:gpr = MOVsi [[COPY2]], 130, 14 /* CC::al */, $noreg, $noreg ; CHECK-NOBF16-NEXT: [[VMOVSR1:%[0-9]+]]:spr = VMOVSR killed [[MOVsi1]], 14 /* CC::al */, $noreg - ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf contract VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg + ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf contract nofpexcept VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-NOBF16-NEXT: [[MOVsi2:%[0-9]+]]:gpr = MOVsi [[COPY]], 130, 14 /* CC::al */, $noreg, $noreg ; CHECK-NOBF16-NEXT: [[VMOVSR2:%[0-9]+]]:spr = VMOVSR killed [[MOVsi2]], 14 /* CC::al */, $noreg - ; CHECK-NOBF16-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf contract VADDS killed [[VADDS]], killed [[VMOVSR2]], 14 /* CC::al */, $noreg + ; CHECK-NOBF16-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf contract nofpexcept VADDS killed [[VADDS]], killed [[VMOVSR2]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-NOBF16-NEXT: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS killed [[VADDS1]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp ; CHECK-NOBF16-NEXT: $r0 = COPY [[VMOVRS]] @@ -174,7 +174,7 @@ define bfloat @ninf_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) { ; CHECK-NOBF16-NEXT: [[VMOVSR:%[0-9]+]]:spr = VMOVSR killed [[MOVsi]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: [[MOVsi1:%[0-9]+]]:gpr = MOVsi [[COPY2]], 130, 14 /* CC::al */, $noreg, $noreg ; CHECK-NOBF16-NEXT: [[VMOVSR1:%[0-9]+]]:spr = VMOVSR killed [[MOVsi1]], 14 /* CC::al */, $noreg - ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = ninf VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg + ; CHECK-NOBF16-NEXT: [[VADDS:%[0-9]+]]:spr = ninf nofpexcept VADDS killed [[VMOVSR1]], killed [[VMOVSR]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-NOBF16-NEXT: [[VMOVRS:%[0-9]+]]:gpr = VMOVRS killed [[VADDS]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp ; CHECK-NOBF16-NEXT: $r0 = COPY [[VMOVRS]] @@ -185,7 +185,7 @@ define bfloat @ninf_fadd_sequence(bfloat %x, bfloat %y, bfloat %z) { ; CHECK-NOBF16-NEXT: [[VMOVSR2:%[0-9]+]]:spr = VMOVSR killed [[MOVsi2]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: [[MOVsi3:%[0-9]+]]:gpr = MOVsi [[COPY3]], 130, 14 /* CC::al */, $noreg, $noreg ; CHECK-NOBF16-NEXT: [[VMOVSR3:%[0-9]+]]:spr = VMOVSR killed [[MOVsi3]], 14 /* CC::al */, $noreg - ; CHECK-NOBF16-NEXT: [[VADDS1:%[0-9]+]]:spr = ninf VADDS killed [[VMOVSR3]], killed [[VMOVSR2]], 14 /* CC::al */, $noreg + ; CHECK-NOBF16-NEXT: [[VADDS1:%[0-9]+]]:spr = ninf nofpexcept VADDS killed [[VMOVSR3]], killed [[VMOVSR2]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-NOBF16-NEXT: [[VMOVRS1:%[0-9]+]]:gpr = VMOVRS killed [[VADDS1]], 14 /* CC::al */, $noreg ; CHECK-NOBF16-NEXT: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp ; CHECK-NOBF16-NEXT: $r0 = COPY [[VMOVRS1]] diff --git a/llvm/test/CodeGen/ARM/cortex-m7-wideops.mir b/llvm/test/CodeGen/ARM/cortex-m7-wideops.mir index 1bee32f..fe23e85 100644 --- a/llvm/test/CodeGen/ARM/cortex-m7-wideops.mir +++ b/llvm/test/CodeGen/ARM/cortex-m7-wideops.mir @@ -22,15 +22,16 @@ body: | ; CHECK-LABEL: name: test_groups ; CHECK: liveins: $d0, $r0, $r1, $r2, $r3, $r4 - ; CHECK: renamable $d0 = VADDD killed renamable $d0, renamable $d0, 14 /* CC::al */, $noreg - ; CHECK: renamable $r3 = t2ADDrr killed renamable $r3, renamable $r3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $s2 = VLDRS killed renamable $r0, 0, 14 /* CC::al */, $noreg - ; CHECK: VSTRS killed renamable $s2, killed renamable $r1, 0, 14 /* CC::al */, $noreg - ; CHECK: t2STRi12 killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg - ; CHECK: renamable $r4 = t2ADDrr killed renamable $r4, renamable $r4, 14 /* CC::al */, $noreg, $noreg - ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: renamable $s2 = VLDRS killed renamable $r0, 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: renamable $r3 = t2ADDrr killed renamable $r3, renamable $r3, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: renamable $d0 = VADDD killed renamable $d0, renamable $d0, 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: renamable $r4 = t2ADDrr killed renamable $r4, renamable $r4, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: VSTRS killed renamable $s2, killed renamable $r1, 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: t2STRi12 killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit killed $d0 renamable $s2 = VLDRS killed renamable $r0, 0, 14 /* CC::al */, $noreg - renamable $d0 = VADDD killed renamable $d0, renamable $d0, 14 /* CC::al */, $noreg + renamable $d0 = VADDD killed renamable $d0, renamable $d0, 14 /* CC::al */, $noreg, implicit $fpscr_rm VSTRS killed renamable $s2, killed renamable $r1, 0, 14 /* CC::al */, $noreg renamable $r3 = t2ADDrr killed renamable $r3, renamable $r3, 14 /* CC::al */, $noreg, $noreg t2STRi12 killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg diff --git a/llvm/test/CodeGen/ARM/fp16-litpool-arm.mir b/llvm/test/CodeGen/ARM/fp16-litpool-arm.mir index 8e671c9..f5b2e98 100644 --- a/llvm/test/CodeGen/ARM/fp16-litpool-arm.mir +++ b/llvm/test/CodeGen/ARM/fp16-litpool-arm.mir @@ -81,7 +81,7 @@ body: | STRi12 killed renamable $r1, killed renamable $r0, 0, 14, $noreg :: (volatile store (s32) into %ir.LL, align 8) dead renamable $r0 = SPACE 8920, undef renamable $r0 renamable $s2 = VLDRH $sp, 1, 14, $noreg :: (volatile dereferenceable load (s16) from %ir.S) - renamable $s0 = VADDH killed renamable $s2, killed renamable $s0, 14, $noreg + renamable $s0 = VADDH killed renamable $s2, killed renamable $s0, 14, $noreg, implicit $fpscr_rm VSTRH renamable $s0, $sp, 1, 14, $noreg :: (volatile store (s16) into %ir.S) renamable $r0 = VMOVRH killed renamable $s0, 14, $noreg dead renamable $r1 = SPACE 1350, undef renamable $r0 diff --git a/llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir b/llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir index 03ddd80..4b66476 100644 --- a/llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir +++ b/llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir @@ -72,7 +72,7 @@ body: | renamable $s2 = VLDRH $sp, 1, 14, $noreg :: (volatile dereferenceable load (s16) from %ir.S) renamable $s0 = VLDRH %const.1, 0, 14, $noreg :: (load (s16) from constant-pool) dead renamable $r0 = SPACE 1230, undef renamable $r0 - renamable $s0 = VADDH killed renamable $s2, killed renamable $s0, 14, $noreg + renamable $s0 = VADDH killed renamable $s2, killed renamable $s0, 14, $noreg, implicit $fpscr_rm VSTRH renamable $s0, $sp, 1, 14, $noreg :: (volatile store (s16) into %ir.S) renamable $r0 = VMOVRH killed renamable $s0, 14, $noreg dead renamable $r1 = SPACE 1330, undef renamable $r0 diff --git a/llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir b/llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir index 46f028b..c16a62a 100644 --- a/llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir +++ b/llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir @@ -89,7 +89,7 @@ body: | $sp = frame-setup SUBri $sp, 4, 14, $noreg, $noreg frame-setup CFI_INSTRUCTION def_cfa_offset 4 renamable $s0 = VLDRH %const.0, 0, 14, $noreg :: (load (s16) from constant-pool) - VCMPZH renamable $s0, 14, $noreg, implicit-def $fpscr_nzcv + VCMPZH renamable $s0, 14, $noreg, implicit-def $fpscr_nzcv, implicit $fpscr_rm VSTRH killed renamable $s0, $sp, 1, 14, $noreg :: (store (s16) into %ir.res) FMSTAT 14, $noreg, implicit-def $cpsr, implicit killed $fpscr_nzcv Bcc %bb.2, 0, killed $cpsr diff --git a/llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir b/llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir index 5a03fcd..049b7d9 100644 --- a/llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir +++ b/llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir @@ -95,7 +95,7 @@ body: | $sp = frame-setup SUBri $sp, 4, 14, $noreg, $noreg frame-setup CFI_INSTRUCTION def_cfa_offset 4 renamable $s0 = VLDRH %const.0, 0, 14, $noreg :: (load (s16) from constant-pool) - VCMPZH renamable $s0, 14, $noreg, implicit-def $fpscr_nzcv + VCMPZH renamable $s0, 14, $noreg, implicit-def $fpscr_nzcv, implicit $fpscr_rm VSTRH killed renamable $s0, $sp, 1, 14, $noreg :: (store (s16) into %ir.res) FMSTAT 14, $noreg, implicit-def $cpsr, implicit killed $fpscr_nzcv Bcc %bb.2, 0, killed $cpsr diff --git a/llvm/test/CodeGen/ARM/fp16_fast_math.ll b/llvm/test/CodeGen/ARM/fp16_fast_math.ll index 165eb4b..47e1f84f 100644 --- a/llvm/test/CodeGen/ARM/fp16_fast_math.ll +++ b/llvm/test/CodeGen/ARM/fp16_fast_math.ll @@ -16,11 +16,11 @@ define half @normal_fadd(half %x, half %y) { ; CHECK-CVT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r0 ; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:spr = COPY [[COPY1]] ; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY]] - ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = VCVTBHS killed [[COPY2]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = nofpexcept VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = nofpexcept VCVTBHS killed [[COPY2]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = nofpexcept VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF - ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = nofpexcept VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]] ; CHECK-CVT-NEXT: $r0 = COPY [[COPY4]] ; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 @@ -33,7 +33,7 @@ define half @normal_fadd(half %x, half %y) { ; CHECK-FP16-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 ; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg ; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg - ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg + ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = nofpexcept VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg, implicit $fpscr ; CHECK-FP16-NEXT: $r0 = COPY [[VADDH]] ; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 entry: @@ -50,11 +50,11 @@ define half @fast_fadd(half %x, half %y) { ; CHECK-CVT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r0 ; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:spr = COPY [[COPY1]] ; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY]] - ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VCVTBHS killed [[COPY2]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc nofpexcept VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc nofpexcept VCVTBHS killed [[COPY2]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc nofpexcept VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF - ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = nofpexcept VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]] ; CHECK-CVT-NEXT: $r0 = COPY [[COPY4]] ; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 @@ -67,7 +67,7 @@ define half @fast_fadd(half %x, half %y) { ; CHECK-FP16-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 ; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg ; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg - ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = nnan ninf nsz arcp contract afn reassoc VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg + ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = nnan ninf nsz arcp contract afn reassoc nofpexcept VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg, implicit $fpscr ; CHECK-FP16-NEXT: $r0 = COPY [[VADDH]] ; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 entry: @@ -84,11 +84,11 @@ define half @ninf_fadd(half %x, half %y) { ; CHECK-CVT-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r0 ; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:spr = COPY [[COPY1]] ; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY]] - ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY2]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = ninf VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = ninf nofpexcept VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = ninf nofpexcept VCVTBHS killed [[COPY2]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = ninf nofpexcept VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF - ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = nofpexcept VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]] ; CHECK-CVT-NEXT: $r0 = COPY [[COPY4]] ; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 @@ -101,7 +101,7 @@ define half @ninf_fadd(half %x, half %y) { ; CHECK-FP16-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 ; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg ; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg - ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = ninf VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg + ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = ninf nofpexcept VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg, implicit $fpscr ; CHECK-FP16-NEXT: $r0 = COPY [[VADDH]] ; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 entry: @@ -122,19 +122,19 @@ define half @normal_fadd_sequence(half %x, half %y, half %z) { ; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $r0 ; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY2]] ; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:spr = COPY [[COPY1]] - ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = VCVTBHS killed [[COPY4]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = nofpexcept VCVTBHS killed [[COPY4]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = nofpexcept VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = nofpexcept VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY5:%[0-9]+]]:spr = COPY [[COPY]] - ; CHECK-CVT-NEXT: [[VCVTBHS2:%[0-9]+]]:spr = VCVTBHS killed [[COPY5]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS2:%[0-9]+]]:spr = nofpexcept VCVTBHS killed [[COPY5]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF - ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = nofpexcept VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]] ; CHECK-CVT-NEXT: [[COPY7:%[0-9]+]]:spr = COPY killed [[COPY6]] - ; CHECK-CVT-NEXT: [[VCVTBHS3:%[0-9]+]]:spr = VCVTBHS killed [[COPY7]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = VADDS killed [[VCVTBHS3]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS3:%[0-9]+]]:spr = nofpexcept VCVTBHS killed [[COPY7]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = nofpexcept VADDS killed [[VCVTBHS3]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[DEF1:%[0-9]+]]:spr = IMPLICIT_DEF - ; CHECK-CVT-NEXT: [[VCVTBSH1:%[0-9]+]]:spr = VCVTBSH [[DEF1]], killed [[VADDS1]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBSH1:%[0-9]+]]:spr = nofpexcept VCVTBSH [[DEF1]], killed [[VADDS1]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY killed [[VCVTBSH1]] ; CHECK-CVT-NEXT: $r0 = COPY [[COPY8]] ; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 @@ -148,9 +148,9 @@ define half @normal_fadd_sequence(half %x, half %y, half %z) { ; CHECK-FP16-NEXT: [[COPY2:%[0-9]+]]:rgpr = COPY $r0 ; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg ; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY2]], 14, $noreg - ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg + ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = nofpexcept VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg, implicit $fpscr ; CHECK-FP16-NEXT: [[VMOVHR2:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg - ; CHECK-FP16-NEXT: [[VADDH1:%[0-9]+]]:hpr = VADDH killed [[VADDH]], killed [[VMOVHR2]], 14, $noreg + ; CHECK-FP16-NEXT: [[VADDH1:%[0-9]+]]:hpr = nofpexcept VADDH killed [[VADDH]], killed [[VMOVHR2]], 14, $noreg, implicit $fpscr ; CHECK-FP16-NEXT: $r0 = COPY [[VADDH1]] ; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 entry: @@ -169,14 +169,14 @@ define half @nnan_ninf_contract_fadd_sequence(half %x, half %y, half %z) { ; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $r0 ; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY2]] ; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:spr = COPY [[COPY1]] - ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = nnan ninf contract VCVTBHS killed [[COPY4]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = nnan ninf contract VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf contract VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = nnan ninf contract nofpexcept VCVTBHS killed [[COPY4]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = nnan ninf contract nofpexcept VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf contract nofpexcept VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY5:%[0-9]+]]:spr = COPY [[COPY]] - ; CHECK-CVT-NEXT: [[VCVTBHS2:%[0-9]+]]:spr = nnan ninf contract VCVTBHS killed [[COPY5]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf contract VADDS killed [[VADDS]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS2:%[0-9]+]]:spr = nnan ninf contract nofpexcept VCVTBHS killed [[COPY5]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf contract nofpexcept VADDS killed [[VADDS]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF - ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS1]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = nofpexcept VCVTBSH [[DEF]], killed [[VADDS1]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]] ; CHECK-CVT-NEXT: $r0 = COPY [[COPY6]] ; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 @@ -190,9 +190,9 @@ define half @nnan_ninf_contract_fadd_sequence(half %x, half %y, half %z) { ; CHECK-FP16-NEXT: [[COPY2:%[0-9]+]]:rgpr = COPY $r0 ; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg ; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY2]], 14, $noreg - ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = nnan ninf contract VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg + ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = nnan ninf contract nofpexcept VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg, implicit $fpscr ; CHECK-FP16-NEXT: [[VMOVHR2:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg - ; CHECK-FP16-NEXT: [[VADDH1:%[0-9]+]]:hpr = nnan ninf contract VADDH killed [[VADDH]], killed [[VMOVHR2]], 14, $noreg + ; CHECK-FP16-NEXT: [[VADDH1:%[0-9]+]]:hpr = nnan ninf contract nofpexcept VADDH killed [[VADDH]], killed [[VMOVHR2]], 14, $noreg, implicit $fpscr ; CHECK-FP16-NEXT: $r0 = COPY [[VADDH1]] ; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 entry: @@ -211,19 +211,19 @@ define half @ninf_fadd_sequence(half %x, half %y, half %z) { ; CHECK-CVT-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $r0 ; CHECK-CVT-NEXT: [[COPY3:%[0-9]+]]:spr = COPY [[COPY2]] ; CHECK-CVT-NEXT: [[COPY4:%[0-9]+]]:spr = COPY [[COPY1]] - ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY4]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = ninf VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS:%[0-9]+]]:spr = ninf nofpexcept VCVTBHS killed [[COPY4]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VCVTBHS1:%[0-9]+]]:spr = ninf nofpexcept VCVTBHS killed [[COPY3]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VADDS:%[0-9]+]]:spr = ninf nofpexcept VADDS killed [[VCVTBHS1]], killed [[VCVTBHS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY5:%[0-9]+]]:spr = COPY [[COPY]] - ; CHECK-CVT-NEXT: [[VCVTBHS2:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY5]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS2:%[0-9]+]]:spr = ninf nofpexcept VCVTBHS killed [[COPY5]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[DEF:%[0-9]+]]:spr = IMPLICIT_DEF - ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBSH:%[0-9]+]]:spr = nofpexcept VCVTBSH [[DEF]], killed [[VADDS]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY killed [[VCVTBSH]] ; CHECK-CVT-NEXT: [[COPY7:%[0-9]+]]:spr = COPY killed [[COPY6]] - ; CHECK-CVT-NEXT: [[VCVTBHS3:%[0-9]+]]:spr = ninf VCVTBHS killed [[COPY7]], 14 /* CC::al */, $noreg - ; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = ninf VADDS killed [[VCVTBHS3]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBHS3:%[0-9]+]]:spr = ninf nofpexcept VCVTBHS killed [[COPY7]], 14 /* CC::al */, $noreg, implicit $fpscr + ; CHECK-CVT-NEXT: [[VADDS1:%[0-9]+]]:spr = ninf nofpexcept VADDS killed [[VCVTBHS3]], killed [[VCVTBHS2]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[DEF1:%[0-9]+]]:spr = IMPLICIT_DEF - ; CHECK-CVT-NEXT: [[VCVTBSH1:%[0-9]+]]:spr = VCVTBSH [[DEF1]], killed [[VADDS1]], 14 /* CC::al */, $noreg + ; CHECK-CVT-NEXT: [[VCVTBSH1:%[0-9]+]]:spr = nofpexcept VCVTBSH [[DEF1]], killed [[VADDS1]], 14 /* CC::al */, $noreg, implicit $fpscr ; CHECK-CVT-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY killed [[VCVTBSH1]] ; CHECK-CVT-NEXT: $r0 = COPY [[COPY8]] ; CHECK-CVT-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 @@ -237,9 +237,9 @@ define half @ninf_fadd_sequence(half %x, half %y, half %z) { ; CHECK-FP16-NEXT: [[COPY2:%[0-9]+]]:rgpr = COPY $r0 ; CHECK-FP16-NEXT: [[VMOVHR:%[0-9]+]]:hpr = VMOVHR [[COPY1]], 14, $noreg ; CHECK-FP16-NEXT: [[VMOVHR1:%[0-9]+]]:hpr = VMOVHR [[COPY2]], 14, $noreg - ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = ninf VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg + ; CHECK-FP16-NEXT: [[VADDH:%[0-9]+]]:hpr = ninf nofpexcept VADDH killed [[VMOVHR1]], killed [[VMOVHR]], 14, $noreg, implicit $fpscr ; CHECK-FP16-NEXT: [[VMOVHR2:%[0-9]+]]:hpr = VMOVHR [[COPY]], 14, $noreg - ; CHECK-FP16-NEXT: [[VADDH1:%[0-9]+]]:hpr = ninf VADDH killed [[VADDH]], killed [[VMOVHR2]], 14, $noreg + ; CHECK-FP16-NEXT: [[VADDH1:%[0-9]+]]:hpr = ninf nofpexcept VADDH killed [[VADDH]], killed [[VMOVHR2]], 14, $noreg, implicit $fpscr ; CHECK-FP16-NEXT: $r0 = COPY [[VADDH1]] ; CHECK-FP16-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 entry: diff --git a/llvm/test/CodeGen/ARM/ipra-reg-usage.ll b/llvm/test/CodeGen/ARM/ipra-reg-usage.ll index c928390..90142cb 100644 --- a/llvm/test/CodeGen/ARM/ipra-reg-usage.ll +++ b/llvm/test/CodeGen/ARM/ipra-reg-usage.ll @@ -6,7 +6,7 @@ target triple = "armv7-eabi" declare void @bar1() define void @foo()#0 { -; CHECK: foo Clobbered Registers: $apsr $apsr_nzcv $cpsr $fpcxtns $fpcxts $fpexc $fpinst $fpscr $fpscr_nzcv $fpscr_nzcvqc $fpsid $itstate $pc $ra_auth_code $sp $spsr $vpr $zr $d0 $d1 $d2 $d3 $d4 $d5 $d6 $d7 $d16 $d17 $d18 $d19 $d20 $d21 $d22 $d23 $d24 $d25 $d26 $d27 $d28 $d29 $d30 $d31 $fpinst2 $mvfr0 $mvfr1 $mvfr2 $p0 $q0 $q1 $q2 $q3 $q8 $q9 $q10 $q11 $q12 $q13 $q14 $q15 $r0 $r1 $r2 $r3 $r12 $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7 $s8 $s9 $s10 $s11 $s12 $s13 $s14 $s15 $d0_d2 $d1_d3 $d2_d4 $d3_d5 $d4_d6 $d5_d7 $d6_d8 $d7_d9 $d14_d16 $d15_d17 $d16_d18 $d17_d19 $d18_d20 $d19_d21 $d20_d22 $d21_d23 $d22_d24 $d23_d25 $d24_d26 $d25_d27 $d26_d28 $d27_d29 $d28_d30 $d29_d31 $q0_q1 $q1_q2 $q2_q3 $q3_q4 $q7_q8 $q8_q9 $q9_q10 $q10_q11 $q11_q12 $q12_q13 $q13_q14 $q14_q15 $q0_q1_q2_q3 $q1_q2_q3_q4 $q2_q3_q4_q5 $q3_q4_q5_q6 $q5_q6_q7_q8 $q6_q7_q8_q9 $q7_q8_q9_q10 $q8_q9_q10_q11 $q9_q10_q11_q12 $q10_q11_q12_q13 $q11_q12_q13_q14 $q12_q13_q14_q15 $r0_r1 $r2_r3 $r12_sp $d0_d1_d2 $d1_d2_d3 $d2_d3_d4 $d3_d4_d5 $d4_d5_d6 $d5_d6_d7 $d6_d7_d8 $d7_d8_d9 $d14_d15_d16 $d15_d16_d17 $d16_d17_d18 $d17_d18_d19 $d18_d19_d20 $d19_d20_d21 $d20_d21_d22 $d21_d22_d23 $d22_d23_d24 $d23_d24_d25 $d24_d25_d26 $d25_d26_d27 $d26_d27_d28 $d27_d28_d29 $d28_d29_d30 $d29_d30_d31 $d0_d2_d4 $d1_d3_d5 $d2_d4_d6 $d3_d5_d7 $d4_d6_d8 $d5_d7_d9 $d6_d8_d10 $d7_d9_d11 $d12_d14_d16 $d13_d15_d17 $d14_d16_d18 $d15_d17_d19 $d16_d18_d20 $d17_d19_d21 $d18_d20_d22 $d19_d21_d23 $d20_d22_d24 $d21_d23_d25 $d22_d24_d26 $d23_d25_d27 $d24_d26_d28 $d25_d27_d29 $d26_d28_d30 $d27_d29_d31 $d0_d2_d4_d6 $d1_d3_d5_d7 $d2_d4_d6_d8 $d3_d5_d7_d9 $d4_d6_d8_d10 $d5_d7_d9_d11 $d6_d8_d10_d12 $d7_d9_d11_d13 $d10_d12_d14_d16 $d11_d13_d15_d17 $d12_d14_d16_d18 $d13_d15_d17_d19 $d14_d16_d18_d20 $d15_d17_d19_d21 $d16_d18_d20_d22 $d17_d19_d21_d23 $d18_d20_d22_d24 $d19_d21_d23_d25 $d20_d22_d24_d26 $d21_d23_d25_d27 $d22_d24_d26_d28 $d23_d25_d27_d29 $d24_d26_d28_d30 $d25_d27_d29_d31 $d1_d2 $d3_d4 $d5_d6 $d7_d8 $d15_d16 $d17_d18 $d19_d20 $d21_d22 $d23_d24 $d25_d26 $d27_d28 $d29_d30 $d1_d2_d3_d4 $d3_d4_d5_d6 $d5_d6_d7_d8 $d7_d8_d9_d10 $d13_d14_d15_d16 $d15_d16_d17_d18 $d17_d18_d19_d20 $d19_d20_d21_d22 $d21_d22_d23_d24 $d23_d24_d25_d26 $d25_d26_d27_d28 $d27_d28_d29_d30 +; CHECK: foo Clobbered Registers: $apsr $apsr_nzcv $cpsr $fpcxtns $fpcxts $fpexc $fpinst $fpscr $fpscr_nzcv $fpscr_nzcvqc $fpscr_rm $fpsid $itstate $pc $ra_auth_code $sp $spsr $vpr $zr $d0 $d1 $d2 $d3 $d4 $d5 $d6 $d7 $d16 $d17 $d18 $d19 $d20 $d21 $d22 $d23 $d24 $d25 $d26 $d27 $d28 $d29 $d30 $d31 $fpinst2 $mvfr0 $mvfr1 $mvfr2 $p0 $q0 $q1 $q2 $q3 $q8 $q9 $q10 $q11 $q12 $q13 $q14 $q15 $r0 $r1 $r2 $r3 $r12 $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7 $s8 $s9 $s10 $s11 $s12 $s13 $s14 $s15 $d0_d2 $d1_d3 $d2_d4 $d3_d5 $d4_d6 $d5_d7 $d6_d8 $d7_d9 $d14_d16 $d15_d17 $d16_d18 $d17_d19 $d18_d20 $d19_d21 $d20_d22 $d21_d23 $d22_d24 $d23_d25 $d24_d26 $d25_d27 $d26_d28 $d27_d29 $d28_d30 $d29_d31 $q0_q1 $q1_q2 $q2_q3 $q3_q4 $q7_q8 $q8_q9 $q9_q10 $q10_q11 $q11_q12 $q12_q13 $q13_q14 $q14_q15 $q0_q1_q2_q3 $q1_q2_q3_q4 $q2_q3_q4_q5 $q3_q4_q5_q6 $q5_q6_q7_q8 $q6_q7_q8_q9 $q7_q8_q9_q10 $q8_q9_q10_q11 $q9_q10_q11_q12 $q10_q11_q12_q13 $q11_q12_q13_q14 $q12_q13_q14_q15 $r0_r1 $r2_r3 $r12_sp $d0_d1_d2 $d1_d2_d3 $d2_d3_d4 $d3_d4_d5 $d4_d5_d6 $d5_d6_d7 $d6_d7_d8 $d7_d8_d9 $d14_d15_d16 $d15_d16_d17 $d16_d17_d18 $d17_d18_d19 $d18_d19_d20 $d19_d20_d21 $d20_d21_d22 $d21_d22_d23 $d22_d23_d24 $d23_d24_d25 $d24_d25_d26 $d25_d26_d27 $d26_d27_d28 $d27_d28_d29 $d28_d29_d30 $d29_d30_d31 $d0_d2_d4 $d1_d3_d5 $d2_d4_d6 $d3_d5_d7 $d4_d6_d8 $d5_d7_d9 $d6_d8_d10 $d7_d9_d11 $d12_d14_d16 $d13_d15_d17 $d14_d16_d18 $d15_d17_d19 $d16_d18_d20 $d17_d19_d21 $d18_d20_d22 $d19_d21_d23 $d20_d22_d24 $d21_d23_d25 $d22_d24_d26 $d23_d25_d27 $d24_d26_d28 $d25_d27_d29 $d26_d28_d30 $d27_d29_d31 $d0_d2_d4_d6 $d1_d3_d5_d7 $d2_d4_d6_d8 $d3_d5_d7_d9 $d4_d6_d8_d10 $d5_d7_d9_d11 $d6_d8_d10_d12 $d7_d9_d11_d13 $d10_d12_d14_d16 $d11_d13_d15_d17 $d12_d14_d16_d18 $d13_d15_d17_d19 $d14_d16_d18_d20 $d15_d17_d19_d21 $d16_d18_d20_d22 $d17_d19_d21_d23 $d18_d20_d22_d24 $d19_d21_d23_d25 $d20_d22_d24_d26 $d21_d23_d25_d27 $d22_d24_d26_d28 $d23_d25_d27_d29 $d24_d26_d28_d30 $d25_d27_d29_d31 $d1_d2 $d3_d4 $d5_d6 $d7_d8 $d15_d16 $d17_d18 $d19_d20 $d21_d22 $d23_d24 $d25_d26 $d27_d28 $d29_d30 $d1_d2_d3_d4 $d3_d4_d5_d6 $d5_d6_d7_d8 $d7_d8_d9_d10 $d13_d14_d15_d16 $d15_d16_d17_d18 $d17_d18_d19_d20 $d19_d20_d21_d22 $d21_d22_d23_d24 $d23_d24_d25_d26 $d25_d26_d27_d28 $d27_d28_d29_d30 call void @bar1() call void @bar2() ret void diff --git a/llvm/test/CodeGen/ARM/llrint-conv.ll b/llvm/test/CodeGen/ARM/llrint-conv.ll index a1a04db..7274a8b 100644 --- a/llvm/test/CodeGen/ARM/llrint-conv.ll +++ b/llvm/test/CodeGen/ARM/llrint-conv.ll @@ -1,7 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc < %s -mtriple=armv7-none-eabi -float-abi=soft | FileCheck %s --check-prefixes=CHECK,CHECK-SOFT ; RUN: llc < %s -mtriple=armv7-none-eabihf -mattr=+vfp2 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16 -; RUN: llc < %s -mtriple=armv7-none-eabihf -mattr=+vfp2,+fullfp16 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FP16 +; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FPv8 +; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8,+fullfp16 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FP16 define i64 @testmsxh_builtin(half %x) { ; CHECK-SOFT-LABEL: testmsxh_builtin: @@ -22,6 +23,14 @@ define i64 @testmsxh_builtin(half %x) { ; CHECK-NOFP16-NEXT: bl llrintf ; CHECK-NOFP16-NEXT: pop {r11, pc} ; +; CHECK-FPv8-LABEL: testmsxh_builtin: +; CHECK-FPv8: @ %bb.0: @ %entry +; CHECK-FPv8-NEXT: .save {r11, lr} +; CHECK-FPv8-NEXT: push {r11, lr} +; CHECK-FPv8-NEXT: vcvtb.f32.f16 s0, s0 +; CHECK-FPv8-NEXT: bl llrintf +; CHECK-FPv8-NEXT: pop {r11, pc} +; ; CHECK-FP16-LABEL: testmsxh_builtin: ; CHECK-FP16: @ %bb.0: @ %entry ; CHECK-FP16-NEXT: .save {r11, lr} diff --git a/llvm/test/CodeGen/ARM/lrint-conv.ll b/llvm/test/CodeGen/ARM/lrint-conv.ll index 23a2685..2de2349 100644 --- a/llvm/test/CodeGen/ARM/lrint-conv.ll +++ b/llvm/test/CodeGen/ARM/lrint-conv.ll @@ -1,14 +1,43 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc < %s -mtriple=armv7-none-eabi -float-abi=soft | FileCheck %s --check-prefixes=CHECK,CHECK-SOFT ; RUN: llc < %s -mtriple=armv7-none-eabihf -mattr=+vfp2 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16 -; RUN: llc < %s -mtriple=armv7-none-eabihf -mattr=+vfp2,+fullfp16 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FP16 +; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FPv8 +; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8,+fullfp16 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FP16 -; FIXME: crash -; define i32 @testmswh_builtin(half %x) { -; entry: -; %0 = tail call i32 @llvm.lrint.i32.f16(half %x) -; ret i32 %0 -; } +define i32 @testmswh_builtin(half %x) { +; CHECK-SOFT-LABEL: testmswh_builtin: +; CHECK-SOFT: @ %bb.0: @ %entry +; CHECK-SOFT-NEXT: .save {r11, lr} +; CHECK-SOFT-NEXT: push {r11, lr} +; CHECK-SOFT-NEXT: bl __aeabi_h2f +; CHECK-SOFT-NEXT: pop {r11, lr} +; CHECK-SOFT-NEXT: b lrintf +; +; CHECK-NOFP16-LABEL: testmswh_builtin: +; CHECK-NOFP16: @ %bb.0: @ %entry +; CHECK-NOFP16-NEXT: .save {r11, lr} +; CHECK-NOFP16-NEXT: push {r11, lr} +; CHECK-NOFP16-NEXT: vmov r0, s0 +; CHECK-NOFP16-NEXT: bl __aeabi_h2f +; CHECK-NOFP16-NEXT: vmov s0, r0 +; CHECK-NOFP16-NEXT: pop {r11, lr} +; CHECK-NOFP16-NEXT: b lrintf +; +; CHECK-FPv8-LABEL: testmswh_builtin: +; CHECK-FPv8: @ %bb.0: @ %entry +; CHECK-FPv8-NEXT: vcvtb.f32.f16 s0, s0 +; CHECK-FPv8-NEXT: b lrintf +; +; CHECK-FP16-LABEL: testmswh_builtin: +; CHECK-FP16: @ %bb.0: @ %entry +; CHECK-FP16-NEXT: vrintx.f16 s0, s0 +; CHECK-FP16-NEXT: vcvt.s32.f16 s0, s0 +; CHECK-FP16-NEXT: vmov r0, s0 +; CHECK-FP16-NEXT: bx lr +entry: + %0 = tail call i32 @llvm.lrint.i32.f16(half %x) + ret i32 %0 +} define i32 @testmsws_builtin(float %x) { ; CHECK-LABEL: testmsws_builtin: @@ -39,8 +68,3 @@ entry: %0 = tail call i32 @llvm.lrint.i32.f128(fp128 %x) ret i32 %0 } - -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; CHECK-FP16: {{.*}} -; CHECK-NOFP16: {{.*}} -; CHECK-SOFT: {{.*}} diff --git a/llvm/test/CodeGen/ARM/misched-prevent-erase-history-of-subunits.mir b/llvm/test/CodeGen/ARM/misched-prevent-erase-history-of-subunits.mir index 46f3e4b..17d6619 100644 --- a/llvm/test/CodeGen/ARM/misched-prevent-erase-history-of-subunits.mir +++ b/llvm/test/CodeGen/ARM/misched-prevent-erase-history-of-subunits.mir @@ -14,7 +14,7 @@ # CHECK: SU(1): %1:dpr = VABSD %0:dpr, 14, $noreg # CHECK: SU(2): %2:dpr = VLDRD %const.0, 0, 14, $noreg :: (load (s64) from constant-pool) # CHECK: SU(4): %3:rgpr = t2MOVi 0, 14, $noreg, $noreg -# CHECK: SU(3): VCMPD %1:dpr, %2:dpr, 14, $noreg, implicit-def $fpscr_nzcv +# CHECK: SU(3): VCMPD %1:dpr, %2:dpr, 14, $noreg, implicit-def $fpscr_nzcv, implicit $fpscr_rm # CHECK: SU(5): $r0 = COPY %3:rgpr --- name: test @@ -29,7 +29,7 @@ body: | %0:dpr = COPY $d0 %1:dpr = VABSD %0, 14 /* CC::al */, $noreg %2:dpr = VLDRD %const.0, 0, 14 /* CC::al */, $noreg :: (load (s64) from constant-pool) - VCMPD %1, %2, 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv + VCMPD %1, %2, 14 /* CC::al */, $noreg, implicit-def $fpscr_nzcv, implicit $fpscr_rm %4:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg $r0 = COPY %4 tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0 diff --git a/llvm/test/CodeGen/ARM/vector-lrint.ll b/llvm/test/CodeGen/ARM/vector-lrint.ll index c1159da..c3c8884 100644 --- a/llvm/test/CodeGen/ARM/vector-lrint.ll +++ b/llvm/test/CodeGen/ARM/vector-lrint.ll @@ -9,31 +9,1290 @@ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=armebv7-unknown-none-eabihf -mattr=+neon | FileCheck %s --check-prefixes=BE-I32 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=armebv7-unknown-none-eabihf -mattr=+neon | FileCheck %s --check-prefixes=BE-I64 -; FIXME: crash "Do not know how to soft promote this operator's operand!" -; define <1 x iXLen> @lrint_v1f16(<1 x half> %x) { -; %a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1f16(<1 x half> %x) -; ret <1 x iXLen> %a -; } +define <1 x iXLen> @lrint_v1f16(<1 x half> %x) { +; LE-I32-LABEL: lrint_v1f16: +; LE-I32: @ %bb.0: +; LE-I32-NEXT: .save {r11, lr} +; LE-I32-NEXT: push {r11, lr} +; LE-I32-NEXT: vmov r0, s0 +; LE-I32-NEXT: bl __aeabi_f2h +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: pop {r11, pc} +; +; LE-I64-LABEL: lrint_v1f16: +; LE-I64: @ %bb.0: +; LE-I64-NEXT: .save {r11, lr} +; LE-I64-NEXT: push {r11, lr} +; LE-I64-NEXT: vmov r0, s0 +; LE-I64-NEXT: bl __aeabi_f2h +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d0[0], r0 +; LE-I64-NEXT: vmov.32 d0[1], r1 +; LE-I64-NEXT: pop {r11, pc} +; +; BE-I32-LABEL: lrint_v1f16: +; BE-I32: @ %bb.0: +; BE-I32-NEXT: .save {r11, lr} +; BE-I32-NEXT: push {r11, lr} +; BE-I32-NEXT: vmov r0, s0 +; BE-I32-NEXT: bl __aeabi_f2h +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: pop {r11, pc} +; +; BE-I64-LABEL: lrint_v1f16: +; BE-I64: @ %bb.0: +; BE-I64-NEXT: .save {r11, lr} +; BE-I64-NEXT: push {r11, lr} +; BE-I64-NEXT: vmov r0, s0 +; BE-I64-NEXT: bl __aeabi_f2h +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d16[0], r0 +; BE-I64-NEXT: vmov.32 d16[1], r1 +; BE-I64-NEXT: vrev64.32 d0, d16 +; BE-I64-NEXT: pop {r11, pc} + %a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1f16(<1 x half> %x) + ret <1 x iXLen> %a +} -; define <2 x iXLen> @lrint_v2f16(<2 x half> %x) { -; %a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2f16(<2 x half> %x) -; ret <2 x iXLen> %a -; } +define <2 x iXLen> @lrint_v2f16(<2 x half> %x) { +; LE-I32-LABEL: lrint_v2f16: +; LE-I32: @ %bb.0: +; LE-I32-NEXT: .save {r11, lr} +; LE-I32-NEXT: push {r11, lr} +; LE-I32-NEXT: .vsave {d8} +; LE-I32-NEXT: vpush {d8} +; LE-I32-NEXT: vmov r0, s0 +; LE-I32-NEXT: vmov.f32 s16, s1 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov r1, s16 +; LE-I32-NEXT: vmov.32 d8[0], r0 +; LE-I32-NEXT: mov r0, r1 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d8[1], r0 +; LE-I32-NEXT: vorr d0, d8, d8 +; LE-I32-NEXT: vpop {d8} +; LE-I32-NEXT: pop {r11, pc} +; +; LE-I64-LABEL: lrint_v2f16: +; LE-I64: @ %bb.0: +; LE-I64-NEXT: .save {r4, r5, r11, lr} +; LE-I64-NEXT: push {r4, r5, r11, lr} +; LE-I64-NEXT: .vsave {d8, d9} +; LE-I64-NEXT: vpush {d8, d9} +; LE-I64-NEXT: vmov r0, s1 +; LE-I64-NEXT: vmov.f32 s16, s0 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: mov r4, r0 +; LE-I64-NEXT: vmov r0, s16 +; LE-I64-NEXT: mov r5, r1 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: vmov.32 d9[0], r4 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d8[0], r0 +; LE-I64-NEXT: vmov.32 d9[1], r5 +; LE-I64-NEXT: vmov.32 d8[1], r1 +; LE-I64-NEXT: vorr q0, q4, q4 +; LE-I64-NEXT: vpop {d8, d9} +; LE-I64-NEXT: pop {r4, r5, r11, pc} +; +; BE-I32-LABEL: lrint_v2f16: +; BE-I32: @ %bb.0: +; BE-I32-NEXT: .save {r11, lr} +; BE-I32-NEXT: push {r11, lr} +; BE-I32-NEXT: .vsave {d8} +; BE-I32-NEXT: vpush {d8} +; BE-I32-NEXT: vmov r0, s0 +; BE-I32-NEXT: vmov.f32 s16, s1 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov r1, s16 +; BE-I32-NEXT: vmov.32 d8[0], r0 +; BE-I32-NEXT: mov r0, r1 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov.32 d8[1], r0 +; BE-I32-NEXT: vrev64.32 d0, d8 +; BE-I32-NEXT: vpop {d8} +; BE-I32-NEXT: pop {r11, pc} +; +; BE-I64-LABEL: lrint_v2f16: +; BE-I64: @ %bb.0: +; BE-I64-NEXT: .save {r4, r5, r11, lr} +; BE-I64-NEXT: push {r4, r5, r11, lr} +; BE-I64-NEXT: .vsave {d8} +; BE-I64-NEXT: vpush {d8} +; BE-I64-NEXT: vmov r0, s1 +; BE-I64-NEXT: vmov.f32 s16, s0 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: mov r4, r0 +; BE-I64-NEXT: vmov r0, s16 +; BE-I64-NEXT: mov r5, r1 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: vmov.32 d8[0], r4 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d16[0], r0 +; BE-I64-NEXT: vmov.32 d8[1], r5 +; BE-I64-NEXT: vmov.32 d16[1], r1 +; BE-I64-NEXT: vrev64.32 d1, d8 +; BE-I64-NEXT: vrev64.32 d0, d16 +; BE-I64-NEXT: vpop {d8} +; BE-I64-NEXT: pop {r4, r5, r11, pc} + %a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2f16(<2 x half> %x) + ret <2 x iXLen> %a +} -; define <4 x iXLen> @lrint_v4f16(<4 x half> %x) { -; %a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f16(<4 x half> %x) -; ret <4 x iXLen> %a -; } +define <4 x iXLen> @lrint_v4f16(<4 x half> %x) { +; LE-I32-LABEL: lrint_v4f16: +; LE-I32: @ %bb.0: +; LE-I32-NEXT: .save {r4, r5, r11, lr} +; LE-I32-NEXT: push {r4, r5, r11, lr} +; LE-I32-NEXT: .vsave {d8, d9, d10, d11} +; LE-I32-NEXT: vpush {d8, d9, d10, d11} +; LE-I32-NEXT: vmov r0, s3 +; LE-I32-NEXT: vmov.f32 s16, s2 +; LE-I32-NEXT: vmov.f32 s18, s1 +; LE-I32-NEXT: vmov.f32 s20, s0 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: mov r4, r0 +; LE-I32-NEXT: vmov r0, s16 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r5, r0 +; LE-I32-NEXT: vmov r0, s20 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r5 +; LE-I32-NEXT: vmov.32 d10[0], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d11[0], r0 +; LE-I32-NEXT: vmov r0, s18 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: vmov.32 d11[1], r4 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d10[1], r0 +; LE-I32-NEXT: vorr q0, q5, q5 +; LE-I32-NEXT: vpop {d8, d9, d10, d11} +; LE-I32-NEXT: pop {r4, r5, r11, pc} +; +; LE-I64-LABEL: lrint_v4f16: +; LE-I64: @ %bb.0: +; LE-I64-NEXT: .save {r4, r5, r6, r7, r11, lr} +; LE-I64-NEXT: push {r4, r5, r6, r7, r11, lr} +; LE-I64-NEXT: .vsave {d12, d13} +; LE-I64-NEXT: vpush {d12, d13} +; LE-I64-NEXT: .vsave {d8, d9, d10} +; LE-I64-NEXT: vpush {d8, d9, d10} +; LE-I64-NEXT: vmov r0, s1 +; LE-I64-NEXT: vmov.f32 s16, s3 +; LE-I64-NEXT: vmov.f32 s20, s2 +; LE-I64-NEXT: vmov.f32 s18, s0 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: mov r5, r0 +; LE-I64-NEXT: vmov r0, s18 +; LE-I64-NEXT: mov r4, r1 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: mov r7, r0 +; LE-I64-NEXT: vmov r0, s16 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov s0, r7 +; LE-I64-NEXT: mov r6, r1 +; LE-I64-NEXT: vmov.32 d9[0], r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d12[0], r0 +; LE-I64-NEXT: vmov r0, s20 +; LE-I64-NEXT: mov r7, r1 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: vmov.32 d13[0], r5 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d8[0], r0 +; LE-I64-NEXT: vmov.32 d13[1], r4 +; LE-I64-NEXT: vmov.32 d9[1], r6 +; LE-I64-NEXT: vmov.32 d12[1], r7 +; LE-I64-NEXT: vmov.32 d8[1], r1 +; LE-I64-NEXT: vorr q0, q6, q6 +; LE-I64-NEXT: vorr q1, q4, q4 +; LE-I64-NEXT: vpop {d8, d9, d10} +; LE-I64-NEXT: vpop {d12, d13} +; LE-I64-NEXT: pop {r4, r5, r6, r7, r11, pc} +; +; BE-I32-LABEL: lrint_v4f16: +; BE-I32: @ %bb.0: +; BE-I32-NEXT: .save {r4, r5, r11, lr} +; BE-I32-NEXT: push {r4, r5, r11, lr} +; BE-I32-NEXT: .vsave {d8, d9, d10, d11} +; BE-I32-NEXT: vpush {d8, d9, d10, d11} +; BE-I32-NEXT: vmov r0, s3 +; BE-I32-NEXT: vmov.f32 s16, s2 +; BE-I32-NEXT: vmov.f32 s18, s1 +; BE-I32-NEXT: vmov.f32 s20, s0 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: mov r4, r0 +; BE-I32-NEXT: vmov r0, s16 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r5, r0 +; BE-I32-NEXT: vmov r0, s20 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r5 +; BE-I32-NEXT: vmov.32 d10[0], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov.32 d11[0], r0 +; BE-I32-NEXT: vmov r0, s18 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: vmov.32 d11[1], r4 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov.32 d10[1], r0 +; BE-I32-NEXT: vrev64.32 q0, q5 +; BE-I32-NEXT: vpop {d8, d9, d10, d11} +; BE-I32-NEXT: pop {r4, r5, r11, pc} +; +; BE-I64-LABEL: lrint_v4f16: +; BE-I64: @ %bb.0: +; BE-I64-NEXT: .save {r4, r5, r6, r7, r11, lr} +; BE-I64-NEXT: push {r4, r5, r6, r7, r11, lr} +; BE-I64-NEXT: .vsave {d8, d9, d10} +; BE-I64-NEXT: vpush {d8, d9, d10} +; BE-I64-NEXT: vmov r0, s1 +; BE-I64-NEXT: vmov.f32 s16, s3 +; BE-I64-NEXT: vmov.f32 s18, s2 +; BE-I64-NEXT: vmov.f32 s20, s0 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: mov r5, r0 +; BE-I64-NEXT: vmov r0, s20 +; BE-I64-NEXT: mov r4, r1 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r7, r0 +; BE-I64-NEXT: vmov r0, s16 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov s0, r7 +; BE-I64-NEXT: mov r6, r1 +; BE-I64-NEXT: vmov.32 d8[0], r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d10[0], r0 +; BE-I64-NEXT: vmov r0, s18 +; BE-I64-NEXT: mov r7, r1 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: vmov.32 d9[0], r5 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d16[0], r0 +; BE-I64-NEXT: vmov.32 d9[1], r4 +; BE-I64-NEXT: vmov.32 d8[1], r6 +; BE-I64-NEXT: vmov.32 d10[1], r7 +; BE-I64-NEXT: vmov.32 d16[1], r1 +; BE-I64-NEXT: vrev64.32 d1, d9 +; BE-I64-NEXT: vrev64.32 d3, d8 +; BE-I64-NEXT: vrev64.32 d0, d10 +; BE-I64-NEXT: vrev64.32 d2, d16 +; BE-I64-NEXT: vpop {d8, d9, d10} +; BE-I64-NEXT: pop {r4, r5, r6, r7, r11, pc} + %a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f16(<4 x half> %x) + ret <4 x iXLen> %a +} -; define <8 x iXLen> @lrint_v8f16(<8 x half> %x) { -; %a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f16(<8 x half> %x) -; ret <8 x iXLen> %a -; } +define <8 x iXLen> @lrint_v8f16(<8 x half> %x) { +; LE-I32-LABEL: lrint_v8f16: +; LE-I32: @ %bb.0: +; LE-I32-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr} +; LE-I32-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr} +; LE-I32-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14} +; LE-I32-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14} +; LE-I32-NEXT: vmov r0, s7 +; LE-I32-NEXT: vmov.f32 s18, s6 +; LE-I32-NEXT: vmov.f32 s16, s5 +; LE-I32-NEXT: vmov.f32 s20, s4 +; LE-I32-NEXT: vmov.f32 s22, s3 +; LE-I32-NEXT: vmov.f32 s24, s2 +; LE-I32-NEXT: vmov.f32 s26, s1 +; LE-I32-NEXT: vmov.f32 s28, s0 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: mov r8, r0 +; LE-I32-NEXT: vmov r0, s26 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r9, r0 +; LE-I32-NEXT: vmov r0, s22 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r6, r0 +; LE-I32-NEXT: vmov r0, s28 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r7, r0 +; LE-I32-NEXT: vmov r0, s24 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r4, r0 +; LE-I32-NEXT: vmov r0, s18 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r5, r0 +; LE-I32-NEXT: vmov r0, s20 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r5 +; LE-I32-NEXT: vmov.32 d10[0], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r4 +; LE-I32-NEXT: vmov.32 d11[0], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r7 +; LE-I32-NEXT: vmov.32 d13[0], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r6 +; LE-I32-NEXT: vmov.32 d12[0], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r9 +; LE-I32-NEXT: vmov.32 d13[1], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d12[1], r0 +; LE-I32-NEXT: vmov r0, s16 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: vmov.32 d11[1], r8 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d10[1], r0 +; LE-I32-NEXT: vorr q0, q6, q6 +; LE-I32-NEXT: vorr q1, q5, q5 +; LE-I32-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14} +; LE-I32-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc} +; +; LE-I64-LABEL: lrint_v8f16: +; LE-I64: @ %bb.0: +; LE-I64-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} +; LE-I64-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} +; LE-I64-NEXT: .pad #4 +; LE-I64-NEXT: sub sp, sp, #4 +; LE-I64-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} +; LE-I64-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} +; LE-I64-NEXT: .pad #8 +; LE-I64-NEXT: sub sp, sp, #8 +; LE-I64-NEXT: vmov r0, s1 +; LE-I64-NEXT: vstr s6, [sp, #4] @ 4-byte Spill +; LE-I64-NEXT: vmov.f32 s16, s7 +; LE-I64-NEXT: vmov.f32 s18, s5 +; LE-I64-NEXT: vmov.f32 s20, s4 +; LE-I64-NEXT: vmov.f32 s22, s3 +; LE-I64-NEXT: vmov.f32 s24, s2 +; LE-I64-NEXT: vmov.f32 s26, s0 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: mov r9, r0 +; LE-I64-NEXT: vmov r0, s26 +; LE-I64-NEXT: str r1, [sp] @ 4-byte Spill +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: mov r10, r0 +; LE-I64-NEXT: vmov r0, s22 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: mov r5, r0 +; LE-I64-NEXT: vmov r0, s24 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: mov r7, r0 +; LE-I64-NEXT: vmov r0, s18 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: mov r6, r0 +; LE-I64-NEXT: vmov r0, s20 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: mov r4, r0 +; LE-I64-NEXT: vmov r0, s16 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov s0, r4 +; LE-I64-NEXT: mov r11, r1 +; LE-I64-NEXT: vmov.32 d11[0], r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov s0, r6 +; LE-I64-NEXT: mov r8, r1 +; LE-I64-NEXT: vmov.32 d12[0], r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov s0, r7 +; LE-I64-NEXT: mov r6, r1 +; LE-I64-NEXT: vmov.32 d13[0], r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov s0, r5 +; LE-I64-NEXT: mov r7, r1 +; LE-I64-NEXT: vmov.32 d14[0], r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov s0, r10 +; LE-I64-NEXT: mov r5, r1 +; LE-I64-NEXT: vmov.32 d15[0], r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vldr s0, [sp, #4] @ 4-byte Reload +; LE-I64-NEXT: mov r4, r1 +; LE-I64-NEXT: vmov.32 d8[0], r0 +; LE-I64-NEXT: vmov r0, s0 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: vmov.32 d9[0], r9 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d10[0], r0 +; LE-I64-NEXT: ldr r0, [sp] @ 4-byte Reload +; LE-I64-NEXT: vmov.32 d15[1], r5 +; LE-I64-NEXT: vmov.32 d9[1], r0 +; LE-I64-NEXT: vmov.32 d13[1], r6 +; LE-I64-NEXT: vmov.32 d11[1], r11 +; LE-I64-NEXT: vmov.32 d8[1], r4 +; LE-I64-NEXT: vmov.32 d14[1], r7 +; LE-I64-NEXT: vorr q0, q4, q4 +; LE-I64-NEXT: vmov.32 d12[1], r8 +; LE-I64-NEXT: vorr q1, q7, q7 +; LE-I64-NEXT: vmov.32 d10[1], r1 +; LE-I64-NEXT: vorr q2, q6, q6 +; LE-I64-NEXT: vorr q3, q5, q5 +; LE-I64-NEXT: add sp, sp, #8 +; LE-I64-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} +; LE-I64-NEXT: add sp, sp, #4 +; LE-I64-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} +; +; BE-I32-LABEL: lrint_v8f16: +; BE-I32: @ %bb.0: +; BE-I32-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr} +; BE-I32-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr} +; BE-I32-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14} +; BE-I32-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14} +; BE-I32-NEXT: vmov r0, s1 +; BE-I32-NEXT: vmov.f32 s18, s7 +; BE-I32-NEXT: vmov.f32 s20, s6 +; BE-I32-NEXT: vmov.f32 s16, s5 +; BE-I32-NEXT: vmov.f32 s22, s4 +; BE-I32-NEXT: vmov.f32 s24, s3 +; BE-I32-NEXT: vmov.f32 s26, s2 +; BE-I32-NEXT: vmov.f32 s28, s0 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: mov r8, r0 +; BE-I32-NEXT: vmov r0, s24 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r9, r0 +; BE-I32-NEXT: vmov r0, s18 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r6, r0 +; BE-I32-NEXT: vmov r0, s26 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r7, r0 +; BE-I32-NEXT: vmov r0, s20 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r4, r0 +; BE-I32-NEXT: vmov r0, s28 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r5, r0 +; BE-I32-NEXT: vmov r0, s22 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r5 +; BE-I32-NEXT: vmov.32 d10[0], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r4 +; BE-I32-NEXT: vmov.32 d12[0], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r7 +; BE-I32-NEXT: vmov.32 d11[0], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r6 +; BE-I32-NEXT: vmov.32 d13[0], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r9 +; BE-I32-NEXT: vmov.32 d11[1], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov.32 d13[1], r0 +; BE-I32-NEXT: vmov r0, s16 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: vmov.32 d12[1], r8 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov.32 d10[1], r0 +; BE-I32-NEXT: vrev64.32 q0, q6 +; BE-I32-NEXT: vrev64.32 q1, q5 +; BE-I32-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14} +; BE-I32-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc} +; +; BE-I64-LABEL: lrint_v8f16: +; BE-I64: @ %bb.0: +; BE-I64-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} +; BE-I64-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} +; BE-I64-NEXT: .pad #4 +; BE-I64-NEXT: sub sp, sp, #4 +; BE-I64-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14} +; BE-I64-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14} +; BE-I64-NEXT: .pad #8 +; BE-I64-NEXT: sub sp, sp, #8 +; BE-I64-NEXT: vmov r0, s1 +; BE-I64-NEXT: vmov.f32 s18, s7 +; BE-I64-NEXT: vmov.f32 s16, s6 +; BE-I64-NEXT: vmov.f32 s20, s5 +; BE-I64-NEXT: vmov.f32 s22, s4 +; BE-I64-NEXT: vmov.f32 s24, s3 +; BE-I64-NEXT: vmov.f32 s26, s2 +; BE-I64-NEXT: vmov.f32 s28, s0 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: mov r9, r0 +; BE-I64-NEXT: vmov r0, s28 +; BE-I64-NEXT: str r1, [sp, #4] @ 4-byte Spill +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r10, r0 +; BE-I64-NEXT: vmov r0, s24 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r5, r0 +; BE-I64-NEXT: vmov r0, s26 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r7, r0 +; BE-I64-NEXT: vmov r0, s20 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r6, r0 +; BE-I64-NEXT: vmov r0, s22 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r4, r0 +; BE-I64-NEXT: vmov r0, s18 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov s0, r4 +; BE-I64-NEXT: mov r11, r1 +; BE-I64-NEXT: vmov.32 d9[0], r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov s0, r6 +; BE-I64-NEXT: mov r8, r1 +; BE-I64-NEXT: vmov.32 d10[0], r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov s0, r7 +; BE-I64-NEXT: mov r6, r1 +; BE-I64-NEXT: vmov.32 d11[0], r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov s0, r5 +; BE-I64-NEXT: mov r7, r1 +; BE-I64-NEXT: vmov.32 d12[0], r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov s0, r10 +; BE-I64-NEXT: mov r5, r1 +; BE-I64-NEXT: vmov.32 d13[0], r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d14[0], r0 +; BE-I64-NEXT: vmov r0, s16 +; BE-I64-NEXT: mov r4, r1 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: vmov.32 d8[0], r9 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d16[0], r0 +; BE-I64-NEXT: ldr r0, [sp, #4] @ 4-byte Reload +; BE-I64-NEXT: vmov.32 d13[1], r5 +; BE-I64-NEXT: vmov.32 d8[1], r0 +; BE-I64-NEXT: vmov.32 d11[1], r6 +; BE-I64-NEXT: vmov.32 d9[1], r11 +; BE-I64-NEXT: vmov.32 d14[1], r4 +; BE-I64-NEXT: vmov.32 d12[1], r7 +; BE-I64-NEXT: vmov.32 d10[1], r8 +; BE-I64-NEXT: vmov.32 d16[1], r1 +; BE-I64-NEXT: vrev64.32 d1, d8 +; BE-I64-NEXT: vrev64.32 d3, d13 +; BE-I64-NEXT: vrev64.32 d5, d11 +; BE-I64-NEXT: vrev64.32 d7, d9 +; BE-I64-NEXT: vrev64.32 d0, d14 +; BE-I64-NEXT: vrev64.32 d2, d12 +; BE-I64-NEXT: vrev64.32 d4, d10 +; BE-I64-NEXT: vrev64.32 d6, d16 +; BE-I64-NEXT: add sp, sp, #8 +; BE-I64-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14} +; BE-I64-NEXT: add sp, sp, #4 +; BE-I64-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} + %a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f16(<8 x half> %x) + ret <8 x iXLen> %a +} -; define <16 x iXLen> @lrint_v16f16(<16 x half> %x) { -; %a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f16(<16 x half> %x) -; ret <16 x iXLen> %a -; } +define <16 x iXLen> @lrint_v16f16(<16 x half> %x) { +; LE-I32-LABEL: lrint_v16f16: +; LE-I32: @ %bb.0: +; LE-I32-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} +; LE-I32-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr} +; LE-I32-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} +; LE-I32-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} +; LE-I32-NEXT: .pad #8 +; LE-I32-NEXT: sub sp, sp, #8 +; LE-I32-NEXT: vmov r0, s15 +; LE-I32-NEXT: vstr s13, [sp, #4] @ 4-byte Spill +; LE-I32-NEXT: vmov.f32 s26, s14 +; LE-I32-NEXT: vstr s0, [sp] @ 4-byte Spill +; LE-I32-NEXT: vmov.f32 s20, s12 +; LE-I32-NEXT: vmov.f32 s22, s11 +; LE-I32-NEXT: vmov.f32 s18, s10 +; LE-I32-NEXT: vmov.f32 s17, s9 +; LE-I32-NEXT: vmov.f32 s24, s8 +; LE-I32-NEXT: vmov.f32 s19, s7 +; LE-I32-NEXT: vmov.f32 s30, s6 +; LE-I32-NEXT: vmov.f32 s21, s5 +; LE-I32-NEXT: vmov.f32 s16, s4 +; LE-I32-NEXT: vmov.f32 s23, s3 +; LE-I32-NEXT: vmov.f32 s28, s2 +; LE-I32-NEXT: vmov.f32 s25, s1 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: mov r8, r0 +; LE-I32-NEXT: vmov r0, s17 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r9, r0 +; LE-I32-NEXT: vmov r0, s22 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r10, r0 +; LE-I32-NEXT: vmov r0, s21 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r7, r0 +; LE-I32-NEXT: vmov r0, s19 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r4, r0 +; LE-I32-NEXT: vmov r0, s25 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r5, r0 +; LE-I32-NEXT: vmov r0, s23 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: mov r6, r0 +; LE-I32-NEXT: vmov r0, s20 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d10[0], r0 +; LE-I32-NEXT: vmov r0, s26 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d11[0], r0 +; LE-I32-NEXT: vmov r0, s24 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d12[0], r0 +; LE-I32-NEXT: vmov r0, s18 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d13[0], r0 +; LE-I32-NEXT: vmov r0, s16 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d8[0], r0 +; LE-I32-NEXT: vmov r0, s30 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d9[0], r0 +; LE-I32-NEXT: vmov r0, s28 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vldr s0, [sp] @ 4-byte Reload +; LE-I32-NEXT: vmov.32 d15[0], r0 +; LE-I32-NEXT: vmov r0, s0 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r6 +; LE-I32-NEXT: vmov.32 d14[0], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r5 +; LE-I32-NEXT: vmov.32 d15[1], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r4 +; LE-I32-NEXT: vmov.32 d14[1], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r7 +; LE-I32-NEXT: vmov.32 d9[1], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r10 +; LE-I32-NEXT: vmov.32 d8[1], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov s0, r9 +; LE-I32-NEXT: vmov.32 d13[1], r0 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vldr s0, [sp, #4] @ 4-byte Reload +; LE-I32-NEXT: vmov.32 d12[1], r0 +; LE-I32-NEXT: vmov r0, s0 +; LE-I32-NEXT: bl __aeabi_h2f +; LE-I32-NEXT: vmov s0, r0 +; LE-I32-NEXT: vmov.32 d11[1], r8 +; LE-I32-NEXT: bl lrintf +; LE-I32-NEXT: vmov.32 d10[1], r0 +; LE-I32-NEXT: vorr q0, q7, q7 +; LE-I32-NEXT: vorr q1, q4, q4 +; LE-I32-NEXT: vorr q2, q6, q6 +; LE-I32-NEXT: vorr q3, q5, q5 +; LE-I32-NEXT: add sp, sp, #8 +; LE-I32-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} +; LE-I32-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc} +; +; LE-I64-LABEL: lrint_v16f16: +; LE-I64: @ %bb.0: +; LE-I64-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} +; LE-I64-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} +; LE-I64-NEXT: .pad #4 +; LE-I64-NEXT: sub sp, sp, #4 +; LE-I64-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} +; LE-I64-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} +; LE-I64-NEXT: .pad #120 +; LE-I64-NEXT: sub sp, sp, #120 +; LE-I64-NEXT: mov r11, r0 +; LE-I64-NEXT: vmov r0, s7 +; LE-I64-NEXT: vstr s15, [sp, #24] @ 4-byte Spill +; LE-I64-NEXT: vmov.f32 s23, s13 +; LE-I64-NEXT: vstr s14, [sp, #100] @ 4-byte Spill +; LE-I64-NEXT: vmov.f32 s25, s12 +; LE-I64-NEXT: vmov.f32 s27, s11 +; LE-I64-NEXT: vstr s10, [sp, #104] @ 4-byte Spill +; LE-I64-NEXT: vstr s9, [sp, #108] @ 4-byte Spill +; LE-I64-NEXT: vmov.f32 s24, s8 +; LE-I64-NEXT: vmov.f32 s19, s6 +; LE-I64-NEXT: vmov.f32 s29, s5 +; LE-I64-NEXT: vmov.f32 s17, s4 +; LE-I64-NEXT: vmov.f32 s16, s3 +; LE-I64-NEXT: vmov.f32 s21, s2 +; LE-I64-NEXT: vmov.f32 s26, s1 +; LE-I64-NEXT: vmov.f32 s18, s0 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: mov r7, r0 +; LE-I64-NEXT: vmov r0, s25 +; LE-I64-NEXT: str r1, [sp, #56] @ 4-byte Spill +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: mov r5, r0 +; LE-I64-NEXT: vmov r0, s27 +; LE-I64-NEXT: str r1, [sp, #116] @ 4-byte Spill +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: mov r6, r0 +; LE-I64-NEXT: vmov r0, s29 +; LE-I64-NEXT: str r1, [sp, #112] @ 4-byte Spill +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d15[0], r0 +; LE-I64-NEXT: vmov r0, s23 +; LE-I64-NEXT: mov r4, r1 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: add lr, sp, #80 +; LE-I64-NEXT: vmov.32 d17[0], r6 +; LE-I64-NEXT: vstmia lr, {d16, d17} @ 16-byte Spill +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: mov r6, r0 +; LE-I64-NEXT: vmov r0, s17 +; LE-I64-NEXT: vmov r8, s21 +; LE-I64-NEXT: str r1, [sp, #76] @ 4-byte Spill +; LE-I64-NEXT: vmov r10, s19 +; LE-I64-NEXT: vmov.32 d10[0], r5 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: add lr, sp, #40 +; LE-I64-NEXT: vmov.32 d11[0], r6 +; LE-I64-NEXT: vstmia lr, {d10, d11} @ 16-byte Spill +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d14[0], r0 +; LE-I64-NEXT: mov r0, r10 +; LE-I64-NEXT: mov r9, r1 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: vmov.32 d11[0], r7 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d10[0], r0 +; LE-I64-NEXT: mov r0, r8 +; LE-I64-NEXT: mov r7, r1 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: mov r6, r0 +; LE-I64-NEXT: ldr r0, [sp, #56] @ 4-byte Reload +; LE-I64-NEXT: vmov.32 d11[1], r0 +; LE-I64-NEXT: vmov r0, s18 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: mov r5, r0 +; LE-I64-NEXT: vmov r0, s16 +; LE-I64-NEXT: vmov.32 d10[1], r7 +; LE-I64-NEXT: add lr, sp, #56 +; LE-I64-NEXT: vstmia lr, {d10, d11} @ 16-byte Spill +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov s0, r0 +; LE-I64-NEXT: vmov.32 d15[1], r4 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d9[0], r0 +; LE-I64-NEXT: vmov r0, s26 +; LE-I64-NEXT: add lr, sp, #24 +; LE-I64-NEXT: vmov r8, s24 +; LE-I64-NEXT: vmov.32 d14[1], r9 +; LE-I64-NEXT: mov r10, r1 +; LE-I64-NEXT: vmov s24, r5 +; LE-I64-NEXT: vldr s0, [sp, #24] @ 4-byte Reload +; LE-I64-NEXT: vstmia lr, {d14, d15} @ 16-byte Spill +; LE-I64-NEXT: vmov r7, s0 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov.f32 s0, s24 +; LE-I64-NEXT: vmov s22, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.f32 s0, s22 +; LE-I64-NEXT: mov r5, r1 +; LE-I64-NEXT: vmov.32 d14[0], r0 +; LE-I64-NEXT: vmov s24, r6 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d15[0], r0 +; LE-I64-NEXT: mov r0, r7 +; LE-I64-NEXT: mov r6, r1 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov.f32 s0, s24 +; LE-I64-NEXT: vmov s22, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.f32 s0, s22 +; LE-I64-NEXT: vmov.32 d8[0], r0 +; LE-I64-NEXT: add lr, sp, #8 +; LE-I64-NEXT: mov r9, r1 +; LE-I64-NEXT: vmov.32 d15[1], r6 +; LE-I64-NEXT: vstmia lr, {d8, d9} @ 16-byte Spill +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d13[0], r0 +; LE-I64-NEXT: mov r0, r8 +; LE-I64-NEXT: mov r6, r1 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vldr s0, [sp, #100] @ 4-byte Reload +; LE-I64-NEXT: mov r7, r0 +; LE-I64-NEXT: vmov.32 d14[1], r5 +; LE-I64-NEXT: vmov r0, s0 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vldr s0, [sp, #104] @ 4-byte Reload +; LE-I64-NEXT: vmov s20, r0 +; LE-I64-NEXT: vmov.32 d13[1], r6 +; LE-I64-NEXT: vmov r4, s0 +; LE-I64-NEXT: vldr s0, [sp, #108] @ 4-byte Reload +; LE-I64-NEXT: vmov r0, s0 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov.f32 s0, s20 +; LE-I64-NEXT: vmov s16, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.f32 s0, s16 +; LE-I64-NEXT: mov r5, r1 +; LE-I64-NEXT: vmov.32 d12[0], r0 +; LE-I64-NEXT: vmov s18, r7 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.32 d11[0], r0 +; LE-I64-NEXT: mov r0, r4 +; LE-I64-NEXT: mov r6, r1 +; LE-I64-NEXT: bl __aeabi_h2f +; LE-I64-NEXT: vmov.f32 s0, s18 +; LE-I64-NEXT: vmov s16, r0 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: vmov.f32 s0, s16 +; LE-I64-NEXT: vmov.32 d10[0], r0 +; LE-I64-NEXT: mov r4, r1 +; LE-I64-NEXT: vmov.32 d11[1], r6 +; LE-I64-NEXT: bl lrintf +; LE-I64-NEXT: add lr, sp, #80 +; LE-I64-NEXT: vmov.32 d10[1], r4 +; LE-I64-NEXT: vldmia lr, {d16, d17} @ 16-byte Reload +; LE-I64-NEXT: add lr, sp, #40 +; LE-I64-NEXT: vldmia lr, {d18, d19} @ 16-byte Reload +; LE-I64-NEXT: add lr, sp, #8 +; LE-I64-NEXT: vmov.32 d16[0], r0 +; LE-I64-NEXT: ldr r0, [sp, #76] @ 4-byte Reload +; LE-I64-NEXT: vldmia lr, {d20, d21} @ 16-byte Reload +; LE-I64-NEXT: add lr, sp, #24 +; LE-I64-NEXT: vmov.32 d19[1], r0 +; LE-I64-NEXT: ldr r0, [sp, #116] @ 4-byte Reload +; LE-I64-NEXT: vmov.32 d21[1], r10 +; LE-I64-NEXT: vmov.32 d18[1], r0 +; LE-I64-NEXT: ldr r0, [sp, #112] @ 4-byte Reload +; LE-I64-NEXT: vmov.32 d12[1], r5 +; LE-I64-NEXT: vmov.32 d17[1], r0 +; LE-I64-NEXT: add r0, r11, #64 +; LE-I64-NEXT: vmov.32 d16[1], r1 +; LE-I64-NEXT: vst1.64 {d10, d11}, [r0:128]! +; LE-I64-NEXT: vst1.64 {d16, d17}, [r0:128]! +; LE-I64-NEXT: vst1.64 {d18, d19}, [r0:128]! +; LE-I64-NEXT: vmov.32 d20[1], r9 +; LE-I64-NEXT: vst1.64 {d12, d13}, [r0:128] +; LE-I64-NEXT: vst1.64 {d14, d15}, [r11:128]! +; LE-I64-NEXT: vst1.64 {d20, d21}, [r11:128]! +; LE-I64-NEXT: vldmia lr, {d16, d17} @ 16-byte Reload +; LE-I64-NEXT: add lr, sp, #56 +; LE-I64-NEXT: vst1.64 {d16, d17}, [r11:128]! +; LE-I64-NEXT: vldmia lr, {d16, d17} @ 16-byte Reload +; LE-I64-NEXT: vst1.64 {d16, d17}, [r11:128] +; LE-I64-NEXT: add sp, sp, #120 +; LE-I64-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} +; LE-I64-NEXT: add sp, sp, #4 +; LE-I64-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} +; +; BE-I32-LABEL: lrint_v16f16: +; BE-I32: @ %bb.0: +; BE-I32-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} +; BE-I32-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr} +; BE-I32-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} +; BE-I32-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} +; BE-I32-NEXT: .pad #16 +; BE-I32-NEXT: sub sp, sp, #16 +; BE-I32-NEXT: vmov r0, s1 +; BE-I32-NEXT: vstr s14, [sp, #4] @ 4-byte Spill +; BE-I32-NEXT: vmov.f32 s30, s15 +; BE-I32-NEXT: vstr s13, [sp, #12] @ 4-byte Spill +; BE-I32-NEXT: vmov.f32 s17, s12 +; BE-I32-NEXT: vstr s10, [sp, #8] @ 4-byte Spill +; BE-I32-NEXT: vmov.f32 s19, s11 +; BE-I32-NEXT: vstr s8, [sp] @ 4-byte Spill +; BE-I32-NEXT: vmov.f32 s21, s9 +; BE-I32-NEXT: vmov.f32 s23, s7 +; BE-I32-NEXT: vmov.f32 s24, s6 +; BE-I32-NEXT: vmov.f32 s25, s5 +; BE-I32-NEXT: vmov.f32 s26, s4 +; BE-I32-NEXT: vmov.f32 s27, s3 +; BE-I32-NEXT: vmov.f32 s28, s2 +; BE-I32-NEXT: vmov.f32 s29, s0 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: mov r8, r0 +; BE-I32-NEXT: vmov r0, s27 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r9, r0 +; BE-I32-NEXT: vmov r0, s25 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r10, r0 +; BE-I32-NEXT: vmov r0, s23 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r7, r0 +; BE-I32-NEXT: vmov r0, s21 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r4, r0 +; BE-I32-NEXT: vmov r0, s19 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r5, r0 +; BE-I32-NEXT: vmov r0, s30 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: mov r6, r0 +; BE-I32-NEXT: vmov r0, s17 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov.32 d8[0], r0 +; BE-I32-NEXT: vmov r0, s29 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov.32 d10[0], r0 +; BE-I32-NEXT: vmov r0, s28 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov.32 d11[0], r0 +; BE-I32-NEXT: vmov r0, s26 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov.32 d14[0], r0 +; BE-I32-NEXT: vmov r0, s24 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vldr s0, [sp] @ 4-byte Reload +; BE-I32-NEXT: vmov.32 d15[0], r0 +; BE-I32-NEXT: vmov r0, s0 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vldr s0, [sp, #4] @ 4-byte Reload +; BE-I32-NEXT: vmov.32 d12[0], r0 +; BE-I32-NEXT: vmov r0, s0 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vldr s0, [sp, #8] @ 4-byte Reload +; BE-I32-NEXT: vmov.32 d9[0], r0 +; BE-I32-NEXT: vmov r0, s0 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r6 +; BE-I32-NEXT: vmov.32 d13[0], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r5 +; BE-I32-NEXT: vmov.32 d9[1], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r4 +; BE-I32-NEXT: vmov.32 d13[1], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r7 +; BE-I32-NEXT: vmov.32 d12[1], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r10 +; BE-I32-NEXT: vmov.32 d15[1], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov s0, r9 +; BE-I32-NEXT: vmov.32 d14[1], r0 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vldr s0, [sp, #12] @ 4-byte Reload +; BE-I32-NEXT: vmov.32 d11[1], r0 +; BE-I32-NEXT: vmov r0, s0 +; BE-I32-NEXT: bl __aeabi_h2f +; BE-I32-NEXT: vmov s0, r0 +; BE-I32-NEXT: vmov.32 d10[1], r8 +; BE-I32-NEXT: bl lrintf +; BE-I32-NEXT: vmov.32 d8[1], r0 +; BE-I32-NEXT: vrev64.32 q0, q5 +; BE-I32-NEXT: vrev64.32 q1, q7 +; BE-I32-NEXT: vrev64.32 q2, q6 +; BE-I32-NEXT: vrev64.32 q3, q4 +; BE-I32-NEXT: add sp, sp, #16 +; BE-I32-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} +; BE-I32-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc} +; +; BE-I64-LABEL: lrint_v16f16: +; BE-I64: @ %bb.0: +; BE-I64-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} +; BE-I64-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} +; BE-I64-NEXT: .pad #4 +; BE-I64-NEXT: sub sp, sp, #4 +; BE-I64-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} +; BE-I64-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} +; BE-I64-NEXT: .pad #112 +; BE-I64-NEXT: sub sp, sp, #112 +; BE-I64-NEXT: mov r11, r0 +; BE-I64-NEXT: vmov r0, s14 +; BE-I64-NEXT: vmov.f32 s17, s15 +; BE-I64-NEXT: vstr s13, [sp, #52] @ 4-byte Spill +; BE-I64-NEXT: vmov.f32 s21, s12 +; BE-I64-NEXT: vstr s10, [sp, #68] @ 4-byte Spill +; BE-I64-NEXT: vmov.f32 s23, s11 +; BE-I64-NEXT: vstr s7, [sp, #72] @ 4-byte Spill +; BE-I64-NEXT: vmov.f32 s19, s9 +; BE-I64-NEXT: vstr s4, [sp, #28] @ 4-byte Spill +; BE-I64-NEXT: vmov.f32 s26, s8 +; BE-I64-NEXT: vmov.f32 s24, s6 +; BE-I64-NEXT: vmov.f32 s18, s5 +; BE-I64-NEXT: vmov.f32 s25, s3 +; BE-I64-NEXT: vmov.f32 s16, s2 +; BE-I64-NEXT: vmov.f32 s27, s1 +; BE-I64-NEXT: vmov.f32 s29, s0 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: mov r8, r0 +; BE-I64-NEXT: vmov r0, s29 +; BE-I64-NEXT: mov r4, r1 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r9, r0 +; BE-I64-NEXT: vmov r0, s27 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r7, r0 +; BE-I64-NEXT: vmov r0, s21 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r6, r0 +; BE-I64-NEXT: vmov r0, s25 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r5, r0 +; BE-I64-NEXT: vmov r0, s23 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d16[0], r0 +; BE-I64-NEXT: vmov s0, r5 +; BE-I64-NEXT: str r1, [sp, #108] @ 4-byte Spill +; BE-I64-NEXT: vstr d16, [sp, #96] @ 8-byte Spill +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d16[0], r0 +; BE-I64-NEXT: vmov s0, r6 +; BE-I64-NEXT: str r1, [sp, #92] @ 4-byte Spill +; BE-I64-NEXT: vstr d16, [sp, #80] @ 8-byte Spill +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d16[0], r0 +; BE-I64-NEXT: vmov s0, r7 +; BE-I64-NEXT: str r1, [sp, #76] @ 4-byte Spill +; BE-I64-NEXT: vstr d16, [sp, #56] @ 8-byte Spill +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov s0, r9 +; BE-I64-NEXT: mov r10, r1 +; BE-I64-NEXT: vmov.32 d14[0], r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d15[0], r0 +; BE-I64-NEXT: vmov r0, s17 +; BE-I64-NEXT: mov r5, r1 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: vmov.32 d10[0], r8 +; BE-I64-NEXT: vmov r6, s19 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d11[0], r0 +; BE-I64-NEXT: mov r0, r6 +; BE-I64-NEXT: mov r7, r1 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r6, r0 +; BE-I64-NEXT: vmov r0, s18 +; BE-I64-NEXT: vmov.32 d10[1], r4 +; BE-I64-NEXT: vstr d10, [sp, #40] @ 8-byte Spill +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: mov r4, r0 +; BE-I64-NEXT: vmov r0, s16 +; BE-I64-NEXT: vmov.32 d11[1], r7 +; BE-I64-NEXT: vstr d11, [sp, #32] @ 8-byte Spill +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov.32 d15[1], r5 +; BE-I64-NEXT: vmov s0, r0 +; BE-I64-NEXT: vstr d15, [sp, #16] @ 8-byte Spill +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vldr s0, [sp, #28] @ 4-byte Reload +; BE-I64-NEXT: vmov r5, s26 +; BE-I64-NEXT: vmov.32 d16[0], r0 +; BE-I64-NEXT: vmov s26, r4 +; BE-I64-NEXT: vmov r0, s0 +; BE-I64-NEXT: mov r8, r1 +; BE-I64-NEXT: vmov.32 d14[1], r10 +; BE-I64-NEXT: vmov r4, s24 +; BE-I64-NEXT: vstr d16, [sp] @ 8-byte Spill +; BE-I64-NEXT: vstr d14, [sp, #8] @ 8-byte Spill +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov.f32 s0, s26 +; BE-I64-NEXT: vmov s22, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.f32 s0, s22 +; BE-I64-NEXT: mov r7, r1 +; BE-I64-NEXT: vmov.32 d13[0], r0 +; BE-I64-NEXT: vmov s24, r6 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d14[0], r0 +; BE-I64-NEXT: mov r0, r4 +; BE-I64-NEXT: mov r6, r1 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov.f32 s0, s24 +; BE-I64-NEXT: vmov s22, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.f32 s0, s22 +; BE-I64-NEXT: mov r9, r1 +; BE-I64-NEXT: vmov.32 d12[0], r0 +; BE-I64-NEXT: vmov.32 d14[1], r6 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d11[0], r0 +; BE-I64-NEXT: mov r0, r5 +; BE-I64-NEXT: mov r6, r1 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vldr s0, [sp, #52] @ 4-byte Reload +; BE-I64-NEXT: mov r4, r0 +; BE-I64-NEXT: vmov.32 d13[1], r7 +; BE-I64-NEXT: vmov r0, s0 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vldr s0, [sp, #68] @ 4-byte Reload +; BE-I64-NEXT: vmov s20, r0 +; BE-I64-NEXT: vmov.32 d11[1], r6 +; BE-I64-NEXT: vmov r7, s0 +; BE-I64-NEXT: vldr s0, [sp, #72] @ 4-byte Reload +; BE-I64-NEXT: vmov r0, s0 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov.f32 s0, s20 +; BE-I64-NEXT: vmov s16, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.f32 s0, s16 +; BE-I64-NEXT: mov r5, r1 +; BE-I64-NEXT: vmov.32 d10[0], r0 +; BE-I64-NEXT: vmov s18, r4 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d15[0], r0 +; BE-I64-NEXT: mov r0, r7 +; BE-I64-NEXT: mov r4, r1 +; BE-I64-NEXT: bl __aeabi_h2f +; BE-I64-NEXT: vmov.f32 s0, s18 +; BE-I64-NEXT: vmov s16, r0 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.f32 s0, s16 +; BE-I64-NEXT: mov r6, r1 +; BE-I64-NEXT: vmov.32 d9[0], r0 +; BE-I64-NEXT: vmov.32 d15[1], r4 +; BE-I64-NEXT: bl lrintf +; BE-I64-NEXT: vmov.32 d24[0], r0 +; BE-I64-NEXT: ldr r0, [sp, #76] @ 4-byte Reload +; BE-I64-NEXT: vldr d23, [sp, #56] @ 8-byte Reload +; BE-I64-NEXT: vldr d20, [sp, #8] @ 8-byte Reload +; BE-I64-NEXT: vmov.32 d23[1], r0 +; BE-I64-NEXT: ldr r0, [sp, #92] @ 4-byte Reload +; BE-I64-NEXT: vldr d22, [sp, #80] @ 8-byte Reload +; BE-I64-NEXT: vldr d26, [sp, #16] @ 8-byte Reload +; BE-I64-NEXT: vrev64.32 d21, d20 +; BE-I64-NEXT: vmov.32 d22[1], r0 +; BE-I64-NEXT: ldr r0, [sp, #108] @ 4-byte Reload +; BE-I64-NEXT: vldr d30, [sp] @ 8-byte Reload +; BE-I64-NEXT: vldr d25, [sp, #96] @ 8-byte Reload +; BE-I64-NEXT: vrev64.32 d20, d26 +; BE-I64-NEXT: vldr d26, [sp, #32] @ 8-byte Reload +; BE-I64-NEXT: vmov.32 d10[1], r5 +; BE-I64-NEXT: vmov.32 d12[1], r9 +; BE-I64-NEXT: vldr d28, [sp, #40] @ 8-byte Reload +; BE-I64-NEXT: vrev64.32 d27, d26 +; BE-I64-NEXT: vmov.32 d25[1], r0 +; BE-I64-NEXT: add r0, r11, #64 +; BE-I64-NEXT: vmov.32 d30[1], r8 +; BE-I64-NEXT: vmov.32 d9[1], r6 +; BE-I64-NEXT: vrev64.32 d26, d28 +; BE-I64-NEXT: vrev64.32 d29, d10 +; BE-I64-NEXT: vmov.32 d24[1], r1 +; BE-I64-NEXT: vrev64.32 d1, d12 +; BE-I64-NEXT: vrev64.32 d28, d23 +; BE-I64-NEXT: vrev64.32 d23, d22 +; BE-I64-NEXT: vrev64.32 d22, d30 +; BE-I64-NEXT: vrev64.32 d31, d25 +; BE-I64-NEXT: vrev64.32 d0, d9 +; BE-I64-NEXT: vrev64.32 d30, d24 +; BE-I64-NEXT: vst1.64 {d0, d1}, [r0:128]! +; BE-I64-NEXT: vst1.64 {d30, d31}, [r0:128]! +; BE-I64-NEXT: vst1.64 {d28, d29}, [r0:128]! +; BE-I64-NEXT: vrev64.32 d19, d13 +; BE-I64-NEXT: vst1.64 {d26, d27}, [r0:128] +; BE-I64-NEXT: vst1.64 {d20, d21}, [r11:128]! +; BE-I64-NEXT: vrev64.32 d18, d14 +; BE-I64-NEXT: vst1.64 {d22, d23}, [r11:128]! +; BE-I64-NEXT: vrev64.32 d17, d15 +; BE-I64-NEXT: vrev64.32 d16, d11 +; BE-I64-NEXT: vst1.64 {d18, d19}, [r11:128]! +; BE-I64-NEXT: vst1.64 {d16, d17}, [r11:128] +; BE-I64-NEXT: add sp, sp, #112 +; BE-I64-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} +; BE-I64-NEXT: add sp, sp, #4 +; BE-I64-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} + %a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f16(<16 x half> %x) + ret <16 x iXLen> %a +} define <1 x iXLen> @lrint_v1f32(<1 x float> %x) { ; LE-I32-LABEL: lrint_v1f32: diff --git a/llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir b/llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir index 8fa9337..03cb8e3 100644 --- a/llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir +++ b/llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir @@ -60,9 +60,9 @@ body: | $sp = t2STMDB_UPD $sp, 14, $noreg, $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11 $r4 = t2BICri $r4, 1, 14, $noreg, $noreg $sp = tSUBspi $sp, 34, 14, $noreg - VLSTM $sp, 14 /* CC::al */, $noreg, 0, implicit-def $vpr, implicit-def $fpscr, implicit-def $fpscr_nzcv, implicit undef $vpr, implicit undef $fpscr, implicit undef $fpscr_nzcv, implicit undef $d0, implicit undef $d1, implicit undef $d2, implicit undef $d3, implicit undef $d4, implicit undef $d5, implicit undef $d6, implicit undef $d7, implicit $d8, implicit $d9, implicit $d10, implicit $d11, implicit $d12, implicit $d13, implicit $d14, implicit $d15 + VLSTM $sp, 14 /* CC::al */, $noreg, 0, implicit-def $vpr, implicit-def $fpscr, implicit-def $fpscr_nzcv, implicit-def $fpscr_rm, implicit undef $vpr, implicit undef $fpscr, implicit undef $fpscr_nzcv, implicit undef $fpscr_rm, implicit undef $d0, implicit undef $d1, implicit undef $d2, implicit undef $d3, implicit undef $d4, implicit undef $d5, implicit undef $d6, implicit undef $d7, implicit $d8, implicit $d9, implicit $d10, implicit $d11, implicit $d12, implicit $d13, implicit $d14, implicit $d15 tBLXNSr 14, $noreg, killed $r4, csr_aapcs, implicit-def $lr, implicit $sp, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $q0, implicit-def $q1, implicit-def $q2, implicit-def $q3, implicit-def $q4, implicit-def $q5, implicit-def $q6, implicit-def $q7 - VLLDM $sp, 14 /* CC::al */, $noreg, 0, implicit-def $vpr, implicit-def $fpscr, implicit-def $fpscr_nzcv, implicit-def $d0, implicit-def $d1, implicit-def $d2, implicit-def $d3, implicit-def $d4, implicit-def $d5, implicit-def $d6, implicit-def $d7, implicit-def $d8, implicit-def $d9, implicit-def $d10, implicit-def $d11, implicit-def $d12, implicit-def $d13, implicit-def $d14, implicit-def $d15 + VLLDM $sp, 14 /* CC::al */, $noreg, 0, implicit-def $vpr, implicit-def $fpscr, implicit-def $fpscr_nzcv, implicit-def $fpscr_rm, implicit-def $d0, implicit-def $d1, implicit-def $d2, implicit-def $d3, implicit-def $d4, implicit-def $d5, implicit-def $d6, implicit-def $d7, implicit-def $d8, implicit-def $d9, implicit-def $d10, implicit-def $d11, implicit-def $d12, implicit-def $d13, implicit-def $d14, implicit-def $d15 $sp = tADDspi $sp, 34, 14, $noreg $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11 $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $pc diff --git a/llvm/test/CodeGen/BPF/addr-space-memintrinsic-gep.ll b/llvm/test/CodeGen/BPF/addr-space-memintrinsic-gep.ll new file mode 100644 index 0000000..1db8391 --- /dev/null +++ b/llvm/test/CodeGen/BPF/addr-space-memintrinsic-gep.ll @@ -0,0 +1,60 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt --bpf-check-and-opt-ir -S -mtriple=bpf-pc-linux < %s | FileCheck %s + +@page1 = dso_local local_unnamed_addr addrspace(1) global [10 x ptr] zeroinitializer, align 8 +@page2 = dso_local local_unnamed_addr addrspace(1) global [10 x ptr] zeroinitializer, align 8 + +define dso_local void @test_memset() local_unnamed_addr { +; CHECK-LABEL: define dso_local void @test_memset() local_unnamed_addr { +; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 addrspacecast (ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @page1, i64 16) to ptr), i8 0, i64 16, i1 false) +; CHECK-NEXT: ret void +; + tail call void @llvm.memset.p1.i64(ptr addrspace(1) noundef nonnull align 8 dereferenceable(16) getelementptr inbounds nuw (i8, ptr addrspace(1) @page1, i64 16), i8 0, i64 16, i1 false) + ret void +} + +declare void @llvm.memset.p1.i64(ptr addrspace(1) writeonly captures(none), i8, i64, i1 immarg) + +define dso_local void @test_memcpy() local_unnamed_addr { +; CHECK-LABEL: define dso_local void @test_memcpy() local_unnamed_addr { +; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 addrspacecast (ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @page2, i64 8) to ptr), ptr align 8 addrspacecast (ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @page1, i64 8) to ptr), i64 16, i1 false) +; CHECK-NEXT: ret void +; + tail call void @llvm.memcpy.p1.p1.i64(ptr addrspace(1) noundef nonnull align 8 dereferenceable(16) getelementptr inbounds nuw (i8, ptr addrspace(1) @page2, i64 8), ptr addrspace(1) noundef nonnull align 8 dereferenceable(16) getelementptr inbounds nuw (i8, ptr addrspace(1) @page1, i64 8), i64 16, i1 false) + ret void +} + +declare void @llvm.memcpy.p1.p1.i64(ptr addrspace(1) noalias writeonly captures(none), ptr addrspace(1) noalias readonly captures(none), i64, i1 immarg) + +define dso_local void @test_memmove() local_unnamed_addr { +; CHECK-LABEL: define dso_local void @test_memmove() local_unnamed_addr { +; CHECK-NEXT: call void @llvm.memmove.p0.p0.i64(ptr align 8 addrspacecast (ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @page2, i64 16) to ptr), ptr align 8 addrspacecast (ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @page2, i64 8) to ptr), i64 16, i1 false) +; CHECK-NEXT: ret void +; + tail call void @llvm.memmove.p1.p1.i64(ptr addrspace(1) noundef nonnull align 8 dereferenceable(16) getelementptr inbounds nuw (i8, ptr addrspace(1) @page2, i64 16), ptr addrspace(1) noundef nonnull align 8 dereferenceable(16) getelementptr inbounds nuw (i8, ptr addrspace(1) @page2, i64 8), i64 16, i1 false) + ret void +} + +declare void @llvm.memmove.p1.p1.i64(ptr addrspace(1) writeonly captures(none), ptr addrspace(1) readonly captures(none), i64, i1 immarg) + +define dso_local void @test_memset_inline() local_unnamed_addr { +; CHECK-LABEL: define dso_local void @test_memset_inline() local_unnamed_addr { +; CHECK-NEXT: call void @llvm.memset.inline.p0.i64(ptr align 8 addrspacecast (ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @page1, i64 16) to ptr), i8 0, i64 16, i1 false) +; CHECK-NEXT: ret void +; + tail call void @llvm.memset.inline.p1.i64(ptr addrspace(1) nonnull align 8 getelementptr inbounds nuw (i8, ptr addrspace(1) @page1, i64 16), i8 0, i64 16, i1 false) + ret void +} + +declare void @llvm.memset.inline.p1.i64(ptr addrspace(1) writeonly captures(none), i8, i64, i1 immarg) + +define dso_local void @test_memcpy_inline() local_unnamed_addr { +; CHECK-LABEL: define dso_local void @test_memcpy_inline() local_unnamed_addr { +; CHECK-NEXT: call void @llvm.memcpy.inline.p0.p0.i64(ptr align 8 addrspacecast (ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @page2, i64 8) to ptr), ptr align 8 addrspacecast (ptr addrspace(1) getelementptr inbounds nuw (i8, ptr addrspace(1) @page1, i64 8) to ptr), i64 16, i1 false) +; CHECK-NEXT: ret void +; + tail call void @llvm.memcpy.inline.p1.p1.i64(ptr addrspace(1) nonnull align 8 getelementptr inbounds nuw (i8, ptr addrspace(1) @page2, i64 8), ptr addrspace(1) nonnull align 8 getelementptr inbounds nuw (i8, ptr addrspace(1) @page1, i64 8), i64 16, i1 false) + ret void +} + +declare void @llvm.memcpy.inline.p1.p1.i64(ptr addrspace(1) noalias writeonly captures(none), ptr addrspace(1) noalias readonly captures(none), i64, i1 immarg) diff --git a/llvm/test/CodeGen/BPF/addr-space-memintrinsic-no-gep.ll b/llvm/test/CodeGen/BPF/addr-space-memintrinsic-no-gep.ll new file mode 100644 index 0000000..62fa2e4 --- /dev/null +++ b/llvm/test/CodeGen/BPF/addr-space-memintrinsic-no-gep.ll @@ -0,0 +1,49 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6 +; RUN: opt --bpf-check-and-opt-ir -S -mtriple=bpf-pc-linux < %s | FileCheck %s + +@page1 = dso_local local_unnamed_addr addrspace(1) global [10 x ptr] zeroinitializer, align 8 +@page2 = dso_local local_unnamed_addr addrspace(1) global [10 x ptr] zeroinitializer, align 8 + +define dso_local void @test_memset() local_unnamed_addr { +; CHECK-LABEL: define dso_local void @test_memset() local_unnamed_addr { +; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 addrspacecast (ptr addrspace(1) @page1 to ptr), i8 0, i64 16, i1 false) +; CHECK-NEXT: ret void +; + tail call void @llvm.memset.p1.i64(ptr addrspace(1) noundef align 8 dereferenceable(16) @page1, i8 0, i64 16, i1 false) + ret void +} + +declare void @llvm.memset.p1.i64(ptr addrspace(1) writeonly captures(none), i8, i64, i1 immarg) + +define dso_local void @test_memcpy() local_unnamed_addr { +; CHECK-LABEL: define dso_local void @test_memcpy() local_unnamed_addr { +; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 addrspacecast (ptr addrspace(1) @page2 to ptr), ptr align 8 addrspacecast (ptr addrspace(1) @page1 to ptr), i64 16, i1 false) +; CHECK-NEXT: ret void +; + tail call void @llvm.memcpy.p1.p1.i64(ptr addrspace(1) noundef align 8 dereferenceable(16) @page2, ptr addrspace(1) noundef align 8 dereferenceable(16) @page1, i64 16, i1 false) + ret void +} + +declare void @llvm.memcpy.p1.p1.i64(ptr addrspace(1) noalias writeonly captures(none), ptr addrspace(1) noalias readonly captures(none), i64, i1 immarg) + +define dso_local void @test_memset_inline() local_unnamed_addr { +; CHECK-LABEL: define dso_local void @test_memset_inline() local_unnamed_addr { +; CHECK-NEXT: call void @llvm.memset.inline.p0.i64(ptr align 8 addrspacecast (ptr addrspace(1) @page1 to ptr), i8 0, i64 16, i1 false) +; CHECK-NEXT: ret void +; + tail call void @llvm.memset.inline.p1.i64(ptr addrspace(1) align 8 @page1, i8 0, i64 16, i1 false) + ret void +} + +declare void @llvm.memset.inline.p1.i64(ptr addrspace(1) writeonly captures(none), i8, i64, i1 immarg) + +define dso_local void @test_memcpy_inline() local_unnamed_addr { +; CHECK-LABEL: define dso_local void @test_memcpy_inline() local_unnamed_addr { +; CHECK-NEXT: call void @llvm.memcpy.inline.p0.p0.i64(ptr align 8 addrspacecast (ptr addrspace(1) @page2 to ptr), ptr align 8 addrspacecast (ptr addrspace(1) @page1 to ptr), i64 16, i1 false) +; CHECK-NEXT: ret void +; + tail call void @llvm.memcpy.inline.p1.p1.i64(ptr addrspace(1) align 8 @page2, ptr addrspace(1) align 8 @page1, i64 16, i1 false) + ret void +} + +declare void @llvm.memcpy.inline.p1.p1.i64(ptr addrspace(1) noalias writeonly captures(none), ptr addrspace(1) noalias readonly captures(none), i64, i1 immarg) diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_dummy_2D_vocab.json b/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_dummy_2D_vocab.json new file mode 100644 index 0000000..2894fff --- /dev/null +++ b/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_dummy_2D_vocab.json @@ -0,0 +1,11 @@ +{ + "entities" : { + "ABS_Fp":[1, 2], + "ADC":[3, 4], + "ADD":[5, 6], + "ADDPDrm":[7, 8], + "ADDPDrr":[9, 10], + "ADDPSrr":[11, 12], + "ADDSDrm":[13, 14] + } +}
\ No newline at end of file diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_inconsistent_dims.json b/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_inconsistent_dims.json new file mode 100644 index 0000000..bf04163 --- /dev/null +++ b/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_inconsistent_dims.json @@ -0,0 +1,7 @@ +{ + "entities": { + "ADD": [1.0, 2.0, 3.0], + "SUB": [1.5], + "MUL": [2.0, 3.0] + } +} diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_invalid_vocab.json b/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_invalid_vocab.json new file mode 100644 index 0000000..585a85e --- /dev/null +++ b/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_invalid_vocab.json @@ -0,0 +1,5 @@ +{ + "invalid_structure": { + "ADD": [ 1, 2, 3] + } +}
\ No newline at end of file diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_zero_vocab.json b/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_zero_vocab.json new file mode 100644 index 0000000..63e8ccbd --- /dev/null +++ b/llvm/test/CodeGen/MIR2Vec/Inputs/mir2vec_zero_vocab.json @@ -0,0 +1,12 @@ +{ + "entities": { + "ADD": [], + "SUB": [], + "MUL": [], + "MOV": [], + "CMP": [], + "JMP": [], + "CALL": [], + "RET": [] + } +}
\ No newline at end of file diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt new file mode 100644 index 0000000..6327cff --- /dev/null +++ b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_print.txt @@ -0,0 +1,6882 @@ +Key: AAA: [ 0.00 0.00 ] +Key: AAD: [ 0.00 0.00 ] +Key: AADD: [ 0.00 0.00 ] +Key: AAM: [ 0.00 0.00 ] +Key: AAND: [ 0.00 0.00 ] +Key: AAS: [ 0.00 0.00 ] +Key: ABS_F: [ 0.00 0.00 ] +Key: ABS_Fp: [ 1.00 2.00 ] +Key: ADC: [ 3.00 4.00 ] +Key: ADCX: [ 0.00 0.00 ] +Key: ADD: [ 5.00 6.00 ] +Key: ADDPDrm: [ 7.00 8.00 ] +Key: ADDPDrr: [ 9.00 10.00 ] +Key: ADDPSrm: [ 0.00 0.00 ] +Key: ADDPSrr: [ 11.00 12.00 ] +Key: ADDR: [ 0.00 0.00 ] +Key: ADDSDrm: [ 13.00 14.00 ] +Key: ADDSDrm_Int: [ 0.00 0.00 ] +Key: ADDSDrr: [ 0.00 0.00 ] +Key: ADDSDrr_Int: [ 0.00 0.00 ] +Key: ADDSSrm: [ 0.00 0.00 ] +Key: ADDSSrm_Int: [ 0.00 0.00 ] +Key: ADDSSrr: [ 0.00 0.00 ] +Key: ADDSSrr_Int: [ 0.00 0.00 ] +Key: ADDSUBPDrm: [ 0.00 0.00 ] +Key: ADDSUBPDrr: [ 0.00 0.00 ] +Key: ADDSUBPSrm: [ 0.00 0.00 ] +Key: ADDSUBPSrr: [ 0.00 0.00 ] +Key: ADD_F: [ 0.00 0.00 ] +Key: ADD_FI: [ 0.00 0.00 ] +Key: ADD_FPrST: [ 0.00 0.00 ] +Key: ADD_FST: [ 0.00 0.00 ] +Key: ADD_Fp: [ 0.00 0.00 ] +Key: ADD_FpI: [ 0.00 0.00 ] +Key: ADD_FrST: [ 0.00 0.00 ] +Key: ADJCALLSTACKDOWN: [ 0.00 0.00 ] +Key: ADJCALLSTACKUP: [ 0.00 0.00 ] +Key: ADOX: [ 0.00 0.00 ] +Key: AESDEC: [ 0.00 0.00 ] +Key: AESDECLASTrm: [ 0.00 0.00 ] +Key: AESDECLASTrr: [ 0.00 0.00 ] +Key: AESDECWIDE: [ 0.00 0.00 ] +Key: AESDECrm: [ 0.00 0.00 ] +Key: AESDECrr: [ 0.00 0.00 ] +Key: AESENC: [ 0.00 0.00 ] +Key: AESENCLASTrm: [ 0.00 0.00 ] +Key: AESENCLASTrr: [ 0.00 0.00 ] +Key: AESENCWIDE: [ 0.00 0.00 ] +Key: AESENCrm: [ 0.00 0.00 ] +Key: AESENCrr: [ 0.00 0.00 ] +Key: AESIMCrm: [ 0.00 0.00 ] +Key: AESIMCrr: [ 0.00 0.00 ] +Key: AESKEYGENASSISTrmi: [ 0.00 0.00 ] +Key: AESKEYGENASSISTrri: [ 0.00 0.00 ] +Key: AND: [ 0.00 0.00 ] +Key: ANDN: [ 0.00 0.00 ] +Key: ANDNPDrm: [ 0.00 0.00 ] +Key: ANDNPDrr: [ 0.00 0.00 ] +Key: ANDNPSrm: [ 0.00 0.00 ] +Key: ANDNPSrr: [ 0.00 0.00 ] +Key: ANDPDrm: [ 0.00 0.00 ] +Key: ANDPDrr: [ 0.00 0.00 ] +Key: ANDPSrm: [ 0.00 0.00 ] +Key: ANDPSrr: [ 0.00 0.00 ] +Key: ANNOTATION_LABEL: [ 0.00 0.00 ] +Key: AOR: [ 0.00 0.00 ] +Key: ARITH_FENCE: [ 0.00 0.00 ] +Key: ARPL: [ 0.00 0.00 ] +Key: ASAN_CHECK_MEMACCESS: [ 0.00 0.00 ] +Key: AVX: [ 0.00 0.00 ] +Key: AVX_SET: [ 0.00 0.00 ] +Key: AXOR: [ 0.00 0.00 ] +Key: BEXTR: [ 0.00 0.00 ] +Key: BEXTRI: [ 0.00 0.00 ] +Key: BLCFILL: [ 0.00 0.00 ] +Key: BLCI: [ 0.00 0.00 ] +Key: BLCIC: [ 0.00 0.00 ] +Key: BLCMSK: [ 0.00 0.00 ] +Key: BLCS: [ 0.00 0.00 ] +Key: BLENDPDrmi: [ 0.00 0.00 ] +Key: BLENDPDrri: [ 0.00 0.00 ] +Key: BLENDPSrmi: [ 0.00 0.00 ] +Key: BLENDPSrri: [ 0.00 0.00 ] +Key: BLENDVPDrm: [ 0.00 0.00 ] +Key: BLENDVPDrr: [ 0.00 0.00 ] +Key: BLENDVPSrm: [ 0.00 0.00 ] +Key: BLENDVPSrr: [ 0.00 0.00 ] +Key: BLSFILL: [ 0.00 0.00 ] +Key: BLSI: [ 0.00 0.00 ] +Key: BLSIC: [ 0.00 0.00 ] +Key: BLSMSK: [ 0.00 0.00 ] +Key: BLSR: [ 0.00 0.00 ] +Key: BOUNDS: [ 0.00 0.00 ] +Key: BSF: [ 0.00 0.00 ] +Key: BSR: [ 0.00 0.00 ] +Key: BSWAP: [ 0.00 0.00 ] +Key: BT: [ 0.00 0.00 ] +Key: BTC: [ 0.00 0.00 ] +Key: BTR: [ 0.00 0.00 ] +Key: BTS: [ 0.00 0.00 ] +Key: BUNDLE: [ 0.00 0.00 ] +Key: BZHI: [ 0.00 0.00 ] +Key: CALL: [ 0.00 0.00 ] +Key: CALLpcrel: [ 0.00 0.00 ] +Key: CATCHRET: [ 0.00 0.00 ] +Key: CBW: [ 0.00 0.00 ] +Key: CCMP: [ 0.00 0.00 ] +Key: CDQ: [ 0.00 0.00 ] +Key: CDQE: [ 0.00 0.00 ] +Key: CFCMOV: [ 0.00 0.00 ] +Key: CFI_INSTRUCTION: [ 0.00 0.00 ] +Key: CHS_F: [ 0.00 0.00 ] +Key: CHS_Fp: [ 0.00 0.00 ] +Key: CLAC: [ 0.00 0.00 ] +Key: CLC: [ 0.00 0.00 ] +Key: CLD: [ 0.00 0.00 ] +Key: CLDEMOTE: [ 0.00 0.00 ] +Key: CLEANUPRET: [ 0.00 0.00 ] +Key: CLFLUSH: [ 0.00 0.00 ] +Key: CLFLUSHOPT: [ 0.00 0.00 ] +Key: CLGI: [ 0.00 0.00 ] +Key: CLI: [ 0.00 0.00 ] +Key: CLRSSBSY: [ 0.00 0.00 ] +Key: CLTS: [ 0.00 0.00 ] +Key: CLUI: [ 0.00 0.00 ] +Key: CLWB: [ 0.00 0.00 ] +Key: CLZERO: [ 0.00 0.00 ] +Key: CMC: [ 0.00 0.00 ] +Key: CMOV: [ 0.00 0.00 ] +Key: CMOVBE_F: [ 0.00 0.00 ] +Key: CMOVBE_Fp: [ 0.00 0.00 ] +Key: CMOVB_F: [ 0.00 0.00 ] +Key: CMOVB_Fp: [ 0.00 0.00 ] +Key: CMOVE_F: [ 0.00 0.00 ] +Key: CMOVE_Fp: [ 0.00 0.00 ] +Key: CMOVNBE_F: [ 0.00 0.00 ] +Key: CMOVNBE_Fp: [ 0.00 0.00 ] +Key: CMOVNB_F: [ 0.00 0.00 ] +Key: CMOVNB_Fp: [ 0.00 0.00 ] +Key: CMOVNE_F: [ 0.00 0.00 ] +Key: CMOVNE_Fp: [ 0.00 0.00 ] +Key: CMOVNP_F: [ 0.00 0.00 ] +Key: CMOVNP_Fp: [ 0.00 0.00 ] +Key: CMOVP_F: [ 0.00 0.00 ] +Key: CMOVP_Fp: [ 0.00 0.00 ] +Key: CMOV_FR: [ 0.00 0.00 ] +Key: CMOV_GR: [ 0.00 0.00 ] +Key: CMOV_RFP: [ 0.00 0.00 ] +Key: CMOV_VK: [ 0.00 0.00 ] +Key: CMOV_VR: [ 0.00 0.00 ] +Key: CMP: [ 0.00 0.00 ] +Key: CMPCCXADDmr: [ 0.00 0.00 ] +Key: CMPPDrmi: [ 0.00 0.00 ] +Key: CMPPDrri: [ 0.00 0.00 ] +Key: CMPPSrmi: [ 0.00 0.00 ] +Key: CMPPSrri: [ 0.00 0.00 ] +Key: CMPSB: [ 0.00 0.00 ] +Key: CMPSDrmi: [ 0.00 0.00 ] +Key: CMPSDrmi_Int: [ 0.00 0.00 ] +Key: CMPSDrri: [ 0.00 0.00 ] +Key: CMPSDrri_Int: [ 0.00 0.00 ] +Key: CMPSL: [ 0.00 0.00 ] +Key: CMPSQ: [ 0.00 0.00 ] +Key: CMPSSrmi: [ 0.00 0.00 ] +Key: CMPSSrmi_Int: [ 0.00 0.00 ] +Key: CMPSSrri: [ 0.00 0.00 ] +Key: CMPSSrri_Int: [ 0.00 0.00 ] +Key: CMPSW: [ 0.00 0.00 ] +Key: CMPXCHG: [ 0.00 0.00 ] +Key: COMISDrm: [ 0.00 0.00 ] +Key: COMISDrm_Int: [ 0.00 0.00 ] +Key: COMISDrr: [ 0.00 0.00 ] +Key: COMISDrr_Int: [ 0.00 0.00 ] +Key: COMISSrm: [ 0.00 0.00 ] +Key: COMISSrm_Int: [ 0.00 0.00 ] +Key: COMISSrr: [ 0.00 0.00 ] +Key: COMISSrr_Int: [ 0.00 0.00 ] +Key: COMP_FST: [ 0.00 0.00 ] +Key: COM_FIPr: [ 0.00 0.00 ] +Key: COM_FIr: [ 0.00 0.00 ] +Key: COM_FST: [ 0.00 0.00 ] +Key: COM_FpIr: [ 0.00 0.00 ] +Key: COM_Fpr: [ 0.00 0.00 ] +Key: CONVERGENCECTRL_ANCHOR: [ 0.00 0.00 ] +Key: CONVERGENCECTRL_ENTRY: [ 0.00 0.00 ] +Key: CONVERGENCECTRL_GLUE: [ 0.00 0.00 ] +Key: CONVERGENCECTRL_LOOP: [ 0.00 0.00 ] +Key: COPY: [ 0.00 0.00 ] +Key: COPY_TO_REGCLASS: [ 0.00 0.00 ] +Key: CPUID: [ 0.00 0.00 ] +Key: CQO: [ 0.00 0.00 ] +Key: CRC: [ 0.00 0.00 ] +Key: CS_PREFIX: [ 0.00 0.00 ] +Key: CTEST: [ 0.00 0.00 ] +Key: CVTDQ: [ 0.00 0.00 ] +Key: CVTPD: [ 0.00 0.00 ] +Key: CVTPS: [ 0.00 0.00 ] +Key: CVTSD: [ 0.00 0.00 ] +Key: CVTSI: [ 0.00 0.00 ] +Key: CVTSS: [ 0.00 0.00 ] +Key: CVTTPD: [ 0.00 0.00 ] +Key: CVTTPS: [ 0.00 0.00 ] +Key: CVTTSD: [ 0.00 0.00 ] +Key: CVTTSS: [ 0.00 0.00 ] +Key: CWD: [ 0.00 0.00 ] +Key: CWDE: [ 0.00 0.00 ] +Key: DAA: [ 0.00 0.00 ] +Key: DAS: [ 0.00 0.00 ] +Key: DATA: [ 0.00 0.00 ] +Key: DBG_INSTR_REF: [ 0.00 0.00 ] +Key: DBG_LABEL: [ 0.00 0.00 ] +Key: DBG_PHI: [ 0.00 0.00 ] +Key: DBG_VALUE: [ 0.00 0.00 ] +Key: DBG_VALUE_LIST: [ 0.00 0.00 ] +Key: DEC: [ 0.00 0.00 ] +Key: DIV: [ 0.00 0.00 ] +Key: DIVPDrm: [ 0.00 0.00 ] +Key: DIVPDrr: [ 0.00 0.00 ] +Key: DIVPSrm: [ 0.00 0.00 ] +Key: DIVPSrr: [ 0.00 0.00 ] +Key: DIVR_F: [ 0.00 0.00 ] +Key: DIVR_FI: [ 0.00 0.00 ] +Key: DIVR_FPrST: [ 0.00 0.00 ] +Key: DIVR_FST: [ 0.00 0.00 ] +Key: DIVR_Fp: [ 0.00 0.00 ] +Key: DIVR_FpI: [ 0.00 0.00 ] +Key: DIVR_FrST: [ 0.00 0.00 ] +Key: DIVSDrm: [ 0.00 0.00 ] +Key: DIVSDrm_Int: [ 0.00 0.00 ] +Key: DIVSDrr: [ 0.00 0.00 ] +Key: DIVSDrr_Int: [ 0.00 0.00 ] +Key: DIVSSrm: [ 0.00 0.00 ] +Key: DIVSSrm_Int: [ 0.00 0.00 ] +Key: DIVSSrr: [ 0.00 0.00 ] +Key: DIVSSrr_Int: [ 0.00 0.00 ] +Key: DIV_F: [ 0.00 0.00 ] +Key: DIV_FI: [ 0.00 0.00 ] +Key: DIV_FPrST: [ 0.00 0.00 ] +Key: DIV_FST: [ 0.00 0.00 ] +Key: DIV_Fp: [ 0.00 0.00 ] +Key: DIV_FpI: [ 0.00 0.00 ] +Key: DIV_FrST: [ 0.00 0.00 ] +Key: DPPDrmi: [ 0.00 0.00 ] +Key: DPPDrri: [ 0.00 0.00 ] +Key: DPPSrmi: [ 0.00 0.00 ] +Key: DPPSrri: [ 0.00 0.00 ] +Key: DS_PREFIX: [ 0.00 0.00 ] +Key: DYN_ALLOCA: [ 0.00 0.00 ] +Key: EH_LABEL: [ 0.00 0.00 ] +Key: EH_RETURN: [ 0.00 0.00 ] +Key: EH_SjLj_LongJmp: [ 0.00 0.00 ] +Key: EH_SjLj_SetJmp: [ 0.00 0.00 ] +Key: EH_SjLj_Setup: [ 0.00 0.00 ] +Key: ENCLS: [ 0.00 0.00 ] +Key: ENCLU: [ 0.00 0.00 ] +Key: ENCLV: [ 0.00 0.00 ] +Key: ENCODEKEY: [ 0.00 0.00 ] +Key: ENDBR: [ 0.00 0.00 ] +Key: ENQCMD: [ 0.00 0.00 ] +Key: ENQCMDS: [ 0.00 0.00 ] +Key: ENTER: [ 0.00 0.00 ] +Key: ERETS: [ 0.00 0.00 ] +Key: ERETU: [ 0.00 0.00 ] +Key: ES_PREFIX: [ 0.00 0.00 ] +Key: EXTRACTPSmri: [ 0.00 0.00 ] +Key: EXTRACTPSrri: [ 0.00 0.00 ] +Key: EXTRACT_SUBREG: [ 0.00 0.00 ] +Key: EXTRQ: [ 0.00 0.00 ] +Key: EXTRQI: [ 0.00 0.00 ] +Key: F: [ 0.00 0.00 ] +Key: FAKE_USE: [ 0.00 0.00 ] +Key: FARCALL: [ 0.00 0.00 ] +Key: FARJMP: [ 0.00 0.00 ] +Key: FAULTING_OP: [ 0.00 0.00 ] +Key: FBLDm: [ 0.00 0.00 ] +Key: FBSTPm: [ 0.00 0.00 ] +Key: FCOM: [ 0.00 0.00 ] +Key: FCOMP: [ 0.00 0.00 ] +Key: FCOMPP: [ 0.00 0.00 ] +Key: FCOS: [ 0.00 0.00 ] +Key: FDECSTP: [ 0.00 0.00 ] +Key: FEMMS: [ 0.00 0.00 ] +Key: FENTRY_CALL: [ 0.00 0.00 ] +Key: FFREE: [ 0.00 0.00 ] +Key: FFREEP: [ 0.00 0.00 ] +Key: FICOM: [ 0.00 0.00 ] +Key: FICOMP: [ 0.00 0.00 ] +Key: FINCSTP: [ 0.00 0.00 ] +Key: FLDCW: [ 0.00 0.00 ] +Key: FLDENVm: [ 0.00 0.00 ] +Key: FLDL: [ 0.00 0.00 ] +Key: FLDLG: [ 0.00 0.00 ] +Key: FLDLN: [ 0.00 0.00 ] +Key: FLDPI: [ 0.00 0.00 ] +Key: FNCLEX: [ 0.00 0.00 ] +Key: FNINIT: [ 0.00 0.00 ] +Key: FNOP: [ 0.00 0.00 ] +Key: FNSTCW: [ 0.00 0.00 ] +Key: FNSTSW: [ 0.00 0.00 ] +Key: FNSTSWm: [ 0.00 0.00 ] +Key: FP: [ 0.00 0.00 ] +Key: FPATAN: [ 0.00 0.00 ] +Key: FPREM: [ 0.00 0.00 ] +Key: FPTAN: [ 0.00 0.00 ] +Key: FRNDINT: [ 0.00 0.00 ] +Key: FRSTORm: [ 0.00 0.00 ] +Key: FSAVEm: [ 0.00 0.00 ] +Key: FSCALE: [ 0.00 0.00 ] +Key: FSIN: [ 0.00 0.00 ] +Key: FSINCOS: [ 0.00 0.00 ] +Key: FSTENVm: [ 0.00 0.00 ] +Key: FS_PREFIX: [ 0.00 0.00 ] +Key: FXRSTOR: [ 0.00 0.00 ] +Key: FXSAVE: [ 0.00 0.00 ] +Key: FXTRACT: [ 0.00 0.00 ] +Key: FYL: [ 0.00 0.00 ] +Key: FsFLD: [ 0.00 0.00 ] +Key: GC_LABEL: [ 0.00 0.00 ] +Key: GETSEC: [ 0.00 0.00 ] +Key: GF: [ 0.00 0.00 ] +Key: GS_PREFIX: [ 0.00 0.00 ] +Key: G_ABDS: [ 0.00 0.00 ] +Key: G_ABDU: [ 0.00 0.00 ] +Key: G_ABS: [ 0.00 0.00 ] +Key: G_ADD: [ 0.00 0.00 ] +Key: G_ADDRSPACE_CAST: [ 0.00 0.00 ] +Key: G_AND: [ 0.00 0.00 ] +Key: G_ANYEXT: [ 0.00 0.00 ] +Key: G_ASHR: [ 0.00 0.00 ] +Key: G_ASSERT_ALIGN: [ 0.00 0.00 ] +Key: G_ASSERT_SEXT: [ 0.00 0.00 ] +Key: G_ASSERT_ZEXT: [ 0.00 0.00 ] +Key: G_ATOMICRMW_ADD: [ 0.00 0.00 ] +Key: G_ATOMICRMW_AND: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FADD: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FMAX: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FMAXIMUM: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FMIN: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FMINIMUM: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FSUB: [ 0.00 0.00 ] +Key: G_ATOMICRMW_MAX: [ 0.00 0.00 ] +Key: G_ATOMICRMW_MIN: [ 0.00 0.00 ] +Key: G_ATOMICRMW_NAND: [ 0.00 0.00 ] +Key: G_ATOMICRMW_OR: [ 0.00 0.00 ] +Key: G_ATOMICRMW_SUB: [ 0.00 0.00 ] +Key: G_ATOMICRMW_UDEC_WRAP: [ 0.00 0.00 ] +Key: G_ATOMICRMW_UINC_WRAP: [ 0.00 0.00 ] +Key: G_ATOMICRMW_UMAX: [ 0.00 0.00 ] +Key: G_ATOMICRMW_UMIN: [ 0.00 0.00 ] +Key: G_ATOMICRMW_USUB_COND: [ 0.00 0.00 ] +Key: G_ATOMICRMW_USUB_SAT: [ 0.00 0.00 ] +Key: G_ATOMICRMW_XCHG: [ 0.00 0.00 ] +Key: G_ATOMICRMW_XOR: [ 0.00 0.00 ] +Key: G_ATOMIC_CMPXCHG: [ 0.00 0.00 ] +Key: G_ATOMIC_CMPXCHG_WITH_SUCCESS: [ 0.00 0.00 ] +Key: G_BITCAST: [ 0.00 0.00 ] +Key: G_BITREVERSE: [ 0.00 0.00 ] +Key: G_BLOCK_ADDR: [ 0.00 0.00 ] +Key: G_BR: [ 0.00 0.00 ] +Key: G_BRCOND: [ 0.00 0.00 ] +Key: G_BRINDIRECT: [ 0.00 0.00 ] +Key: G_BRJT: [ 0.00 0.00 ] +Key: G_BSWAP: [ 0.00 0.00 ] +Key: G_BUILD_VECTOR: [ 0.00 0.00 ] +Key: G_BUILD_VECTOR_TRUNC: [ 0.00 0.00 ] +Key: G_BZERO: [ 0.00 0.00 ] +Key: G_CONCAT_VECTORS: [ 0.00 0.00 ] +Key: G_CONSTANT: [ 0.00 0.00 ] +Key: G_CONSTANT_FOLD_BARRIER: [ 0.00 0.00 ] +Key: G_CONSTANT_POOL: [ 0.00 0.00 ] +Key: G_CTLZ: [ 0.00 0.00 ] +Key: G_CTLZ_ZERO_UNDEF: [ 0.00 0.00 ] +Key: G_CTPOP: [ 0.00 0.00 ] +Key: G_CTTZ: [ 0.00 0.00 ] +Key: G_CTTZ_ZERO_UNDEF: [ 0.00 0.00 ] +Key: G_DEBUGTRAP: [ 0.00 0.00 ] +Key: G_DYN_STACKALLOC: [ 0.00 0.00 ] +Key: G_EXTRACT: [ 0.00 0.00 ] +Key: G_EXTRACT_SUBVECTOR: [ 0.00 0.00 ] +Key: G_EXTRACT_VECTOR_ELT: [ 0.00 0.00 ] +Key: G_FABS: [ 0.00 0.00 ] +Key: G_FACOS: [ 0.00 0.00 ] +Key: G_FADD: [ 0.00 0.00 ] +Key: G_FASIN: [ 0.00 0.00 ] +Key: G_FATAN: [ 0.00 0.00 ] +Key: G_FCANONICALIZE: [ 0.00 0.00 ] +Key: G_FCEIL: [ 0.00 0.00 ] +Key: G_FCMP: [ 0.00 0.00 ] +Key: G_FCONSTANT: [ 0.00 0.00 ] +Key: G_FCOPYSIGN: [ 0.00 0.00 ] +Key: G_FCOS: [ 0.00 0.00 ] +Key: G_FCOSH: [ 0.00 0.00 ] +Key: G_FDIV: [ 0.00 0.00 ] +Key: G_FENCE: [ 0.00 0.00 ] +Key: G_FEXP: [ 0.00 0.00 ] +Key: G_FFLOOR: [ 0.00 0.00 ] +Key: G_FFREXP: [ 0.00 0.00 ] +Key: G_FILD: [ 0.00 0.00 ] +Key: G_FIST: [ 0.00 0.00 ] +Key: G_FLDCW: [ 0.00 0.00 ] +Key: G_FLDEXP: [ 0.00 0.00 ] +Key: G_FLOG: [ 0.00 0.00 ] +Key: G_FMA: [ 0.00 0.00 ] +Key: G_FMAD: [ 0.00 0.00 ] +Key: G_FMAXIMUM: [ 0.00 0.00 ] +Key: G_FMAXIMUMNUM: [ 0.00 0.00 ] +Key: G_FMAXNUM: [ 0.00 0.00 ] +Key: G_FMAXNUM_IEEE: [ 0.00 0.00 ] +Key: G_FMINIMUM: [ 0.00 0.00 ] +Key: G_FMINIMUMNUM: [ 0.00 0.00 ] +Key: G_FMINNUM: [ 0.00 0.00 ] +Key: G_FMINNUM_IEEE: [ 0.00 0.00 ] +Key: G_FMODF: [ 0.00 0.00 ] +Key: G_FMUL: [ 0.00 0.00 ] +Key: G_FNEARBYINT: [ 0.00 0.00 ] +Key: G_FNEG: [ 0.00 0.00 ] +Key: G_FNSTCW: [ 0.00 0.00 ] +Key: G_FPEXT: [ 0.00 0.00 ] +Key: G_FPOW: [ 0.00 0.00 ] +Key: G_FPOWI: [ 0.00 0.00 ] +Key: G_FPTOSI: [ 0.00 0.00 ] +Key: G_FPTOSI_SAT: [ 0.00 0.00 ] +Key: G_FPTOUI: [ 0.00 0.00 ] +Key: G_FPTOUI_SAT: [ 0.00 0.00 ] +Key: G_FPTRUNC: [ 0.00 0.00 ] +Key: G_FRAME_INDEX: [ 0.00 0.00 ] +Key: G_FREEZE: [ 0.00 0.00 ] +Key: G_FREM: [ 0.00 0.00 ] +Key: G_FRINT: [ 0.00 0.00 ] +Key: G_FSHL: [ 0.00 0.00 ] +Key: G_FSHR: [ 0.00 0.00 ] +Key: G_FSIN: [ 0.00 0.00 ] +Key: G_FSINCOS: [ 0.00 0.00 ] +Key: G_FSINH: [ 0.00 0.00 ] +Key: G_FSQRT: [ 0.00 0.00 ] +Key: G_FSUB: [ 0.00 0.00 ] +Key: G_FTAN: [ 0.00 0.00 ] +Key: G_FTANH: [ 0.00 0.00 ] +Key: G_GET_FPENV: [ 0.00 0.00 ] +Key: G_GET_FPMODE: [ 0.00 0.00 ] +Key: G_GET_ROUNDING: [ 0.00 0.00 ] +Key: G_GLOBAL_VALUE: [ 0.00 0.00 ] +Key: G_ICMP: [ 0.00 0.00 ] +Key: G_IMPLICIT_DEF: [ 0.00 0.00 ] +Key: G_INDEXED_LOAD: [ 0.00 0.00 ] +Key: G_INDEXED_SEXTLOAD: [ 0.00 0.00 ] +Key: G_INDEXED_STORE: [ 0.00 0.00 ] +Key: G_INDEXED_ZEXTLOAD: [ 0.00 0.00 ] +Key: G_INSERT: [ 0.00 0.00 ] +Key: G_INSERT_SUBVECTOR: [ 0.00 0.00 ] +Key: G_INSERT_VECTOR_ELT: [ 0.00 0.00 ] +Key: G_INTRINSIC: [ 0.00 0.00 ] +Key: G_INTRINSIC_CONVERGENT: [ 0.00 0.00 ] +Key: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS: [ 0.00 0.00 ] +Key: G_INTRINSIC_FPTRUNC_ROUND: [ 0.00 0.00 ] +Key: G_INTRINSIC_LLRINT: [ 0.00 0.00 ] +Key: G_INTRINSIC_LRINT: [ 0.00 0.00 ] +Key: G_INTRINSIC_ROUND: [ 0.00 0.00 ] +Key: G_INTRINSIC_ROUNDEVEN: [ 0.00 0.00 ] +Key: G_INTRINSIC_TRUNC: [ 0.00 0.00 ] +Key: G_INTRINSIC_W_SIDE_EFFECTS: [ 0.00 0.00 ] +Key: G_INTTOPTR: [ 0.00 0.00 ] +Key: G_INVOKE_REGION_START: [ 0.00 0.00 ] +Key: G_IS_FPCLASS: [ 0.00 0.00 ] +Key: G_JUMP_TABLE: [ 0.00 0.00 ] +Key: G_LLROUND: [ 0.00 0.00 ] +Key: G_LOAD: [ 0.00 0.00 ] +Key: G_LROUND: [ 0.00 0.00 ] +Key: G_LSHR: [ 0.00 0.00 ] +Key: G_MEMCPY: [ 0.00 0.00 ] +Key: G_MEMCPY_INLINE: [ 0.00 0.00 ] +Key: G_MEMMOVE: [ 0.00 0.00 ] +Key: G_MEMSET: [ 0.00 0.00 ] +Key: G_MERGE_VALUES: [ 0.00 0.00 ] +Key: G_MUL: [ 0.00 0.00 ] +Key: G_OR: [ 0.00 0.00 ] +Key: G_PHI: [ 0.00 0.00 ] +Key: G_PREFETCH: [ 0.00 0.00 ] +Key: G_PTRAUTH_GLOBAL_VALUE: [ 0.00 0.00 ] +Key: G_PTRMASK: [ 0.00 0.00 ] +Key: G_PTRTOINT: [ 0.00 0.00 ] +Key: G_PTR_ADD: [ 0.00 0.00 ] +Key: G_READCYCLECOUNTER: [ 0.00 0.00 ] +Key: G_READSTEADYCOUNTER: [ 0.00 0.00 ] +Key: G_READ_REGISTER: [ 0.00 0.00 ] +Key: G_RESET_FPENV: [ 0.00 0.00 ] +Key: G_RESET_FPMODE: [ 0.00 0.00 ] +Key: G_ROTL: [ 0.00 0.00 ] +Key: G_ROTR: [ 0.00 0.00 ] +Key: G_SADDE: [ 0.00 0.00 ] +Key: G_SADDO: [ 0.00 0.00 ] +Key: G_SADDSAT: [ 0.00 0.00 ] +Key: G_SBFX: [ 0.00 0.00 ] +Key: G_SCMP: [ 0.00 0.00 ] +Key: G_SDIV: [ 0.00 0.00 ] +Key: G_SDIVFIX: [ 0.00 0.00 ] +Key: G_SDIVFIXSAT: [ 0.00 0.00 ] +Key: G_SDIVREM: [ 0.00 0.00 ] +Key: G_SELECT: [ 0.00 0.00 ] +Key: G_SET_FPENV: [ 0.00 0.00 ] +Key: G_SET_FPMODE: [ 0.00 0.00 ] +Key: G_SET_ROUNDING: [ 0.00 0.00 ] +Key: G_SEXT: [ 0.00 0.00 ] +Key: G_SEXTLOAD: [ 0.00 0.00 ] +Key: G_SEXT_INREG: [ 0.00 0.00 ] +Key: G_SHL: [ 0.00 0.00 ] +Key: G_SHUFFLE_VECTOR: [ 0.00 0.00 ] +Key: G_SITOFP: [ 0.00 0.00 ] +Key: G_SMAX: [ 0.00 0.00 ] +Key: G_SMIN: [ 0.00 0.00 ] +Key: G_SMULFIX: [ 0.00 0.00 ] +Key: G_SMULFIXSAT: [ 0.00 0.00 ] +Key: G_SMULH: [ 0.00 0.00 ] +Key: G_SMULO: [ 0.00 0.00 ] +Key: G_SPLAT_VECTOR: [ 0.00 0.00 ] +Key: G_SREM: [ 0.00 0.00 ] +Key: G_SSHLSAT: [ 0.00 0.00 ] +Key: G_SSUBE: [ 0.00 0.00 ] +Key: G_SSUBO: [ 0.00 0.00 ] +Key: G_SSUBSAT: [ 0.00 0.00 ] +Key: G_STACKRESTORE: [ 0.00 0.00 ] +Key: G_STACKSAVE: [ 0.00 0.00 ] +Key: G_STEP_VECTOR: [ 0.00 0.00 ] +Key: G_STORE: [ 0.00 0.00 ] +Key: G_STRICT_FADD: [ 0.00 0.00 ] +Key: G_STRICT_FDIV: [ 0.00 0.00 ] +Key: G_STRICT_FLDEXP: [ 0.00 0.00 ] +Key: G_STRICT_FMA: [ 0.00 0.00 ] +Key: G_STRICT_FMUL: [ 0.00 0.00 ] +Key: G_STRICT_FREM: [ 0.00 0.00 ] +Key: G_STRICT_FSQRT: [ 0.00 0.00 ] +Key: G_STRICT_FSUB: [ 0.00 0.00 ] +Key: G_SUB: [ 0.00 0.00 ] +Key: G_TRAP: [ 0.00 0.00 ] +Key: G_TRUNC: [ 0.00 0.00 ] +Key: G_TRUNC_SSAT_S: [ 0.00 0.00 ] +Key: G_TRUNC_SSAT_U: [ 0.00 0.00 ] +Key: G_TRUNC_USAT_U: [ 0.00 0.00 ] +Key: G_UADDE: [ 0.00 0.00 ] +Key: G_UADDO: [ 0.00 0.00 ] +Key: G_UADDSAT: [ 0.00 0.00 ] +Key: G_UBFX: [ 0.00 0.00 ] +Key: G_UBSANTRAP: [ 0.00 0.00 ] +Key: G_UCMP: [ 0.00 0.00 ] +Key: G_UDIV: [ 0.00 0.00 ] +Key: G_UDIVFIX: [ 0.00 0.00 ] +Key: G_UDIVFIXSAT: [ 0.00 0.00 ] +Key: G_UDIVREM: [ 0.00 0.00 ] +Key: G_UITOFP: [ 0.00 0.00 ] +Key: G_UMAX: [ 0.00 0.00 ] +Key: G_UMIN: [ 0.00 0.00 ] +Key: G_UMULFIX: [ 0.00 0.00 ] +Key: G_UMULFIXSAT: [ 0.00 0.00 ] +Key: G_UMULH: [ 0.00 0.00 ] +Key: G_UMULO: [ 0.00 0.00 ] +Key: G_UNMERGE_VALUES: [ 0.00 0.00 ] +Key: G_UREM: [ 0.00 0.00 ] +Key: G_USHLSAT: [ 0.00 0.00 ] +Key: G_USUBE: [ 0.00 0.00 ] +Key: G_USUBO: [ 0.00 0.00 ] +Key: G_USUBSAT: [ 0.00 0.00 ] +Key: G_VAARG: [ 0.00 0.00 ] +Key: G_VASTART: [ 0.00 0.00 ] +Key: G_VECREDUCE_ADD: [ 0.00 0.00 ] +Key: G_VECREDUCE_AND: [ 0.00 0.00 ] +Key: G_VECREDUCE_FADD: [ 0.00 0.00 ] +Key: G_VECREDUCE_FMAX: [ 0.00 0.00 ] +Key: G_VECREDUCE_FMAXIMUM: [ 0.00 0.00 ] +Key: G_VECREDUCE_FMIN: [ 0.00 0.00 ] +Key: G_VECREDUCE_FMINIMUM: [ 0.00 0.00 ] +Key: G_VECREDUCE_FMUL: [ 0.00 0.00 ] +Key: G_VECREDUCE_MUL: [ 0.00 0.00 ] +Key: G_VECREDUCE_OR: [ 0.00 0.00 ] +Key: G_VECREDUCE_SEQ_FADD: [ 0.00 0.00 ] +Key: G_VECREDUCE_SEQ_FMUL: [ 0.00 0.00 ] +Key: G_VECREDUCE_SMAX: [ 0.00 0.00 ] +Key: G_VECREDUCE_SMIN: [ 0.00 0.00 ] +Key: G_VECREDUCE_UMAX: [ 0.00 0.00 ] +Key: G_VECREDUCE_UMIN: [ 0.00 0.00 ] +Key: G_VECREDUCE_XOR: [ 0.00 0.00 ] +Key: G_VECTOR_COMPRESS: [ 0.00 0.00 ] +Key: G_VSCALE: [ 0.00 0.00 ] +Key: G_WRITE_REGISTER: [ 0.00 0.00 ] +Key: G_XOR: [ 0.00 0.00 ] +Key: G_ZEXT: [ 0.00 0.00 ] +Key: G_ZEXTLOAD: [ 0.00 0.00 ] +Key: HADDPDrm: [ 0.00 0.00 ] +Key: HADDPDrr: [ 0.00 0.00 ] +Key: HADDPSrm: [ 0.00 0.00 ] +Key: HADDPSrr: [ 0.00 0.00 ] +Key: HLT: [ 0.00 0.00 ] +Key: HRESET: [ 0.00 0.00 ] +Key: HSUBPDrm: [ 0.00 0.00 ] +Key: HSUBPDrr: [ 0.00 0.00 ] +Key: HSUBPSrm: [ 0.00 0.00 ] +Key: HSUBPSrr: [ 0.00 0.00 ] +Key: ICALL_BRANCH_FUNNEL: [ 0.00 0.00 ] +Key: IDIV: [ 0.00 0.00 ] +Key: ILD_F: [ 0.00 0.00 ] +Key: ILD_Fp: [ 0.00 0.00 ] +Key: IMPLICIT_DEF: [ 0.00 0.00 ] +Key: IMUL: [ 0.00 0.00 ] +Key: IMULZU: [ 0.00 0.00 ] +Key: IN: [ 0.00 0.00 ] +Key: INC: [ 0.00 0.00 ] +Key: INCSSPD: [ 0.00 0.00 ] +Key: INCSSPQ: [ 0.00 0.00 ] +Key: INDIRECT_THUNK_CALL: [ 0.00 0.00 ] +Key: INDIRECT_THUNK_TCRETURN: [ 0.00 0.00 ] +Key: INIT_UNDEF: [ 0.00 0.00 ] +Key: INLINEASM: [ 0.00 0.00 ] +Key: INLINEASM_BR: [ 0.00 0.00 ] +Key: INSB: [ 0.00 0.00 ] +Key: INSERTPSrmi: [ 0.00 0.00 ] +Key: INSERTPSrri: [ 0.00 0.00 ] +Key: INSERTQ: [ 0.00 0.00 ] +Key: INSERTQI: [ 0.00 0.00 ] +Key: INSERT_SUBREG: [ 0.00 0.00 ] +Key: INSL: [ 0.00 0.00 ] +Key: INSW: [ 0.00 0.00 ] +Key: INT: [ 0.00 0.00 ] +Key: INTO: [ 0.00 0.00 ] +Key: INVD: [ 0.00 0.00 ] +Key: INVEPT: [ 0.00 0.00 ] +Key: INVLPG: [ 0.00 0.00 ] +Key: INVLPGA: [ 0.00 0.00 ] +Key: INVLPGB: [ 0.00 0.00 ] +Key: INVPCID: [ 0.00 0.00 ] +Key: INVVPID: [ 0.00 0.00 ] +Key: IRET: [ 0.00 0.00 ] +Key: ISTT_FP: [ 0.00 0.00 ] +Key: ISTT_Fp: [ 0.00 0.00 ] +Key: IST_F: [ 0.00 0.00 ] +Key: IST_FP: [ 0.00 0.00 ] +Key: IST_Fp: [ 0.00 0.00 ] +Key: Int_eh_sjlj_setup_dispatch: [ 0.00 0.00 ] +Key: JCC: [ 0.00 0.00 ] +Key: JCXZ: [ 0.00 0.00 ] +Key: JECXZ: [ 0.00 0.00 ] +Key: JMP: [ 0.00 0.00 ] +Key: JMPABS: [ 0.00 0.00 ] +Key: JRCXZ: [ 0.00 0.00 ] +Key: JUMP_TABLE_DEBUG_INFO: [ 0.00 0.00 ] +Key: KADDBkk: [ 0.00 0.00 ] +Key: KADDDkk: [ 0.00 0.00 ] +Key: KADDQkk: [ 0.00 0.00 ] +Key: KADDWkk: [ 0.00 0.00 ] +Key: KANDBkk: [ 0.00 0.00 ] +Key: KANDDkk: [ 0.00 0.00 ] +Key: KANDNBkk: [ 0.00 0.00 ] +Key: KANDNDkk: [ 0.00 0.00 ] +Key: KANDNQkk: [ 0.00 0.00 ] +Key: KANDNWkk: [ 0.00 0.00 ] +Key: KANDQkk: [ 0.00 0.00 ] +Key: KANDWkk: [ 0.00 0.00 ] +Key: KCFI_CHECK: [ 0.00 0.00 ] +Key: KILL: [ 0.00 0.00 ] +Key: KMOVBkk: [ 0.00 0.00 ] +Key: KMOVBkk_EVEX: [ 0.00 0.00 ] +Key: KMOVBkm: [ 0.00 0.00 ] +Key: KMOVBkm_EVEX: [ 0.00 0.00 ] +Key: KMOVBkr: [ 0.00 0.00 ] +Key: KMOVBkr_EVEX: [ 0.00 0.00 ] +Key: KMOVBmk: [ 0.00 0.00 ] +Key: KMOVBmk_EVEX: [ 0.00 0.00 ] +Key: KMOVBrk: [ 0.00 0.00 ] +Key: KMOVBrk_EVEX: [ 0.00 0.00 ] +Key: KMOVDkk: [ 0.00 0.00 ] +Key: KMOVDkk_EVEX: [ 0.00 0.00 ] +Key: KMOVDkm: [ 0.00 0.00 ] +Key: KMOVDkm_EVEX: [ 0.00 0.00 ] +Key: KMOVDkr: [ 0.00 0.00 ] +Key: KMOVDkr_EVEX: [ 0.00 0.00 ] +Key: KMOVDmk: [ 0.00 0.00 ] +Key: KMOVDmk_EVEX: [ 0.00 0.00 ] +Key: KMOVDrk: [ 0.00 0.00 ] +Key: KMOVDrk_EVEX: [ 0.00 0.00 ] +Key: KMOVQkk: [ 0.00 0.00 ] +Key: KMOVQkk_EVEX: [ 0.00 0.00 ] +Key: KMOVQkm: [ 0.00 0.00 ] +Key: KMOVQkm_EVEX: [ 0.00 0.00 ] +Key: KMOVQkr: [ 0.00 0.00 ] +Key: KMOVQkr_EVEX: [ 0.00 0.00 ] +Key: KMOVQmk: [ 0.00 0.00 ] +Key: KMOVQmk_EVEX: [ 0.00 0.00 ] +Key: KMOVQrk: [ 0.00 0.00 ] +Key: KMOVQrk_EVEX: [ 0.00 0.00 ] +Key: KMOVWkk: [ 0.00 0.00 ] +Key: KMOVWkk_EVEX: [ 0.00 0.00 ] +Key: KMOVWkm: [ 0.00 0.00 ] +Key: KMOVWkm_EVEX: [ 0.00 0.00 ] +Key: KMOVWkr: [ 0.00 0.00 ] +Key: KMOVWkr_EVEX: [ 0.00 0.00 ] +Key: KMOVWmk: [ 0.00 0.00 ] +Key: KMOVWmk_EVEX: [ 0.00 0.00 ] +Key: KMOVWrk: [ 0.00 0.00 ] +Key: KMOVWrk_EVEX: [ 0.00 0.00 ] +Key: KNOTBkk: [ 0.00 0.00 ] +Key: KNOTDkk: [ 0.00 0.00 ] +Key: KNOTQkk: [ 0.00 0.00 ] +Key: KNOTWkk: [ 0.00 0.00 ] +Key: KORBkk: [ 0.00 0.00 ] +Key: KORDkk: [ 0.00 0.00 ] +Key: KORQkk: [ 0.00 0.00 ] +Key: KORTESTBkk: [ 0.00 0.00 ] +Key: KORTESTDkk: [ 0.00 0.00 ] +Key: KORTESTQkk: [ 0.00 0.00 ] +Key: KORTESTWkk: [ 0.00 0.00 ] +Key: KORWkk: [ 0.00 0.00 ] +Key: KSET: [ 0.00 0.00 ] +Key: KSHIFTLBki: [ 0.00 0.00 ] +Key: KSHIFTLDki: [ 0.00 0.00 ] +Key: KSHIFTLQki: [ 0.00 0.00 ] +Key: KSHIFTLWki: [ 0.00 0.00 ] +Key: KSHIFTRBki: [ 0.00 0.00 ] +Key: KSHIFTRDki: [ 0.00 0.00 ] +Key: KSHIFTRQki: [ 0.00 0.00 ] +Key: KSHIFTRWki: [ 0.00 0.00 ] +Key: KTESTBkk: [ 0.00 0.00 ] +Key: KTESTDkk: [ 0.00 0.00 ] +Key: KTESTQkk: [ 0.00 0.00 ] +Key: KTESTWkk: [ 0.00 0.00 ] +Key: KUNPCKBWkk: [ 0.00 0.00 ] +Key: KUNPCKDQkk: [ 0.00 0.00 ] +Key: KUNPCKWDkk: [ 0.00 0.00 ] +Key: KXNORBkk: [ 0.00 0.00 ] +Key: KXNORDkk: [ 0.00 0.00 ] +Key: KXNORQkk: [ 0.00 0.00 ] +Key: KXNORWkk: [ 0.00 0.00 ] +Key: KXORBkk: [ 0.00 0.00 ] +Key: KXORDkk: [ 0.00 0.00 ] +Key: KXORQkk: [ 0.00 0.00 ] +Key: KXORWkk: [ 0.00 0.00 ] +Key: LAHF: [ 0.00 0.00 ] +Key: LAR: [ 0.00 0.00 ] +Key: LCMPXCHG: [ 0.00 0.00 ] +Key: LDDQUrm: [ 0.00 0.00 ] +Key: LDMXCSR: [ 0.00 0.00 ] +Key: LDS: [ 0.00 0.00 ] +Key: LDTILECFG: [ 0.00 0.00 ] +Key: LDTILECFG_EVEX: [ 0.00 0.00 ] +Key: LD_F: [ 0.00 0.00 ] +Key: LD_Fp: [ 0.00 0.00 ] +Key: LD_Frr: [ 0.00 0.00 ] +Key: LEA: [ 0.00 0.00 ] +Key: LEAVE: [ 0.00 0.00 ] +Key: LES: [ 0.00 0.00 ] +Key: LFENCE: [ 0.00 0.00 ] +Key: LFS: [ 0.00 0.00 ] +Key: LGDT: [ 0.00 0.00 ] +Key: LGS: [ 0.00 0.00 ] +Key: LIDT: [ 0.00 0.00 ] +Key: LIFETIME_END: [ 0.00 0.00 ] +Key: LIFETIME_START: [ 0.00 0.00 ] +Key: LKGS: [ 0.00 0.00 ] +Key: LLDT: [ 0.00 0.00 ] +Key: LLWPCB: [ 0.00 0.00 ] +Key: LMSW: [ 0.00 0.00 ] +Key: LOADIWKEY: [ 0.00 0.00 ] +Key: LOAD_STACK_GUARD: [ 0.00 0.00 ] +Key: LOCAL_ESCAPE: [ 0.00 0.00 ] +Key: LOCK_ADD: [ 0.00 0.00 ] +Key: LOCK_AND: [ 0.00 0.00 ] +Key: LOCK_BTC: [ 0.00 0.00 ] +Key: LOCK_BTC_RM: [ 0.00 0.00 ] +Key: LOCK_BTR: [ 0.00 0.00 ] +Key: LOCK_BTR_RM: [ 0.00 0.00 ] +Key: LOCK_BTS: [ 0.00 0.00 ] +Key: LOCK_BTS_RM: [ 0.00 0.00 ] +Key: LOCK_DEC: [ 0.00 0.00 ] +Key: LOCK_INC: [ 0.00 0.00 ] +Key: LOCK_OR: [ 0.00 0.00 ] +Key: LOCK_PREFIX: [ 0.00 0.00 ] +Key: LOCK_SUB: [ 0.00 0.00 ] +Key: LOCK_XOR: [ 0.00 0.00 ] +Key: LODSB: [ 0.00 0.00 ] +Key: LODSL: [ 0.00 0.00 ] +Key: LODSQ: [ 0.00 0.00 ] +Key: LODSW: [ 0.00 0.00 ] +Key: LOOP: [ 0.00 0.00 ] +Key: LOOPE: [ 0.00 0.00 ] +Key: LOOPNE: [ 0.00 0.00 ] +Key: LRET: [ 0.00 0.00 ] +Key: LRETI: [ 0.00 0.00 ] +Key: LSL: [ 0.00 0.00 ] +Key: LSS: [ 0.00 0.00 ] +Key: LTRm: [ 0.00 0.00 ] +Key: LTRr: [ 0.00 0.00 ] +Key: LWPINS: [ 0.00 0.00 ] +Key: LWPVAL: [ 0.00 0.00 ] +Key: LXADD: [ 0.00 0.00 ] +Key: LZCNT: [ 0.00 0.00 ] +Key: MASKMOVDQU: [ 0.00 0.00 ] +Key: MASKPAIR: [ 0.00 0.00 ] +Key: MAXCPDrm: [ 0.00 0.00 ] +Key: MAXCPDrr: [ 0.00 0.00 ] +Key: MAXCPSrm: [ 0.00 0.00 ] +Key: MAXCPSrr: [ 0.00 0.00 ] +Key: MAXCSDrm: [ 0.00 0.00 ] +Key: MAXCSDrr: [ 0.00 0.00 ] +Key: MAXCSSrm: [ 0.00 0.00 ] +Key: MAXCSSrr: [ 0.00 0.00 ] +Key: MAXPDrm: [ 0.00 0.00 ] +Key: MAXPDrr: [ 0.00 0.00 ] +Key: MAXPSrm: [ 0.00 0.00 ] +Key: MAXPSrr: [ 0.00 0.00 ] +Key: MAXSDrm: [ 0.00 0.00 ] +Key: MAXSDrm_Int: [ 0.00 0.00 ] +Key: MAXSDrr: [ 0.00 0.00 ] +Key: MAXSDrr_Int: [ 0.00 0.00 ] +Key: MAXSSrm: [ 0.00 0.00 ] +Key: MAXSSrm_Int: [ 0.00 0.00 ] +Key: MAXSSrr: [ 0.00 0.00 ] +Key: MAXSSrr_Int: [ 0.00 0.00 ] +Key: MEMBARRIER: [ 0.00 0.00 ] +Key: MFENCE: [ 0.00 0.00 ] +Key: MINCPDrm: [ 0.00 0.00 ] +Key: MINCPDrr: [ 0.00 0.00 ] +Key: MINCPSrm: [ 0.00 0.00 ] +Key: MINCPSrr: [ 0.00 0.00 ] +Key: MINCSDrm: [ 0.00 0.00 ] +Key: MINCSDrr: [ 0.00 0.00 ] +Key: MINCSSrm: [ 0.00 0.00 ] +Key: MINCSSrr: [ 0.00 0.00 ] +Key: MINPDrm: [ 0.00 0.00 ] +Key: MINPDrr: [ 0.00 0.00 ] +Key: MINPSrm: [ 0.00 0.00 ] +Key: MINPSrr: [ 0.00 0.00 ] +Key: MINSDrm: [ 0.00 0.00 ] +Key: MINSDrm_Int: [ 0.00 0.00 ] +Key: MINSDrr: [ 0.00 0.00 ] +Key: MINSDrr_Int: [ 0.00 0.00 ] +Key: MINSSrm: [ 0.00 0.00 ] +Key: MINSSrm_Int: [ 0.00 0.00 ] +Key: MINSSrr: [ 0.00 0.00 ] +Key: MINSSrr_Int: [ 0.00 0.00 ] +Key: MMX_CVTPD: [ 0.00 0.00 ] +Key: MMX_CVTPI: [ 0.00 0.00 ] +Key: MMX_CVTPS: [ 0.00 0.00 ] +Key: MMX_CVTTPD: [ 0.00 0.00 ] +Key: MMX_CVTTPS: [ 0.00 0.00 ] +Key: MMX_EMMS: [ 0.00 0.00 ] +Key: MMX_MASKMOVQ: [ 0.00 0.00 ] +Key: MMX_MOVD: [ 0.00 0.00 ] +Key: MMX_MOVDQ: [ 0.00 0.00 ] +Key: MMX_MOVFR: [ 0.00 0.00 ] +Key: MMX_MOVNTQmr: [ 0.00 0.00 ] +Key: MMX_MOVQ: [ 0.00 0.00 ] +Key: MMX_PABSBrm: [ 0.00 0.00 ] +Key: MMX_PABSBrr: [ 0.00 0.00 ] +Key: MMX_PABSDrm: [ 0.00 0.00 ] +Key: MMX_PABSDrr: [ 0.00 0.00 ] +Key: MMX_PABSWrm: [ 0.00 0.00 ] +Key: MMX_PABSWrr: [ 0.00 0.00 ] +Key: MMX_PACKSSDWrm: [ 0.00 0.00 ] +Key: MMX_PACKSSDWrr: [ 0.00 0.00 ] +Key: MMX_PACKSSWBrm: [ 0.00 0.00 ] +Key: MMX_PACKSSWBrr: [ 0.00 0.00 ] +Key: MMX_PACKUSWBrm: [ 0.00 0.00 ] +Key: MMX_PACKUSWBrr: [ 0.00 0.00 ] +Key: MMX_PADDBrm: [ 0.00 0.00 ] +Key: MMX_PADDBrr: [ 0.00 0.00 ] +Key: MMX_PADDDrm: [ 0.00 0.00 ] +Key: MMX_PADDDrr: [ 0.00 0.00 ] +Key: MMX_PADDQrm: [ 0.00 0.00 ] +Key: MMX_PADDQrr: [ 0.00 0.00 ] +Key: MMX_PADDSBrm: [ 0.00 0.00 ] +Key: MMX_PADDSBrr: [ 0.00 0.00 ] +Key: MMX_PADDSWrm: [ 0.00 0.00 ] +Key: MMX_PADDSWrr: [ 0.00 0.00 ] +Key: MMX_PADDUSBrm: [ 0.00 0.00 ] +Key: MMX_PADDUSBrr: [ 0.00 0.00 ] +Key: MMX_PADDUSWrm: [ 0.00 0.00 ] +Key: MMX_PADDUSWrr: [ 0.00 0.00 ] +Key: MMX_PADDWrm: [ 0.00 0.00 ] +Key: MMX_PADDWrr: [ 0.00 0.00 ] +Key: MMX_PALIGNRrmi: [ 0.00 0.00 ] +Key: MMX_PALIGNRrri: [ 0.00 0.00 ] +Key: MMX_PANDNrm: [ 0.00 0.00 ] +Key: MMX_PANDNrr: [ 0.00 0.00 ] +Key: MMX_PANDrm: [ 0.00 0.00 ] +Key: MMX_PANDrr: [ 0.00 0.00 ] +Key: MMX_PAVGBrm: [ 0.00 0.00 ] +Key: MMX_PAVGBrr: [ 0.00 0.00 ] +Key: MMX_PAVGWrm: [ 0.00 0.00 ] +Key: MMX_PAVGWrr: [ 0.00 0.00 ] +Key: MMX_PCMPEQBrm: [ 0.00 0.00 ] +Key: MMX_PCMPEQBrr: [ 0.00 0.00 ] +Key: MMX_PCMPEQDrm: [ 0.00 0.00 ] +Key: MMX_PCMPEQDrr: [ 0.00 0.00 ] +Key: MMX_PCMPEQWrm: [ 0.00 0.00 ] +Key: MMX_PCMPEQWrr: [ 0.00 0.00 ] +Key: MMX_PCMPGTBrm: [ 0.00 0.00 ] +Key: MMX_PCMPGTBrr: [ 0.00 0.00 ] +Key: MMX_PCMPGTDrm: [ 0.00 0.00 ] +Key: MMX_PCMPGTDrr: [ 0.00 0.00 ] +Key: MMX_PCMPGTWrm: [ 0.00 0.00 ] +Key: MMX_PCMPGTWrr: [ 0.00 0.00 ] +Key: MMX_PEXTRWrri: [ 0.00 0.00 ] +Key: MMX_PHADDDrm: [ 0.00 0.00 ] +Key: MMX_PHADDDrr: [ 0.00 0.00 ] +Key: MMX_PHADDSWrm: [ 0.00 0.00 ] +Key: MMX_PHADDSWrr: [ 0.00 0.00 ] +Key: MMX_PHADDWrm: [ 0.00 0.00 ] +Key: MMX_PHADDWrr: [ 0.00 0.00 ] +Key: MMX_PHSUBDrm: [ 0.00 0.00 ] +Key: MMX_PHSUBDrr: [ 0.00 0.00 ] +Key: MMX_PHSUBSWrm: [ 0.00 0.00 ] +Key: MMX_PHSUBSWrr: [ 0.00 0.00 ] +Key: MMX_PHSUBWrm: [ 0.00 0.00 ] +Key: MMX_PHSUBWrr: [ 0.00 0.00 ] +Key: MMX_PINSRWrmi: [ 0.00 0.00 ] +Key: MMX_PINSRWrri: [ 0.00 0.00 ] +Key: MMX_PMADDUBSWrm: [ 0.00 0.00 ] +Key: MMX_PMADDUBSWrr: [ 0.00 0.00 ] +Key: MMX_PMADDWDrm: [ 0.00 0.00 ] +Key: MMX_PMADDWDrr: [ 0.00 0.00 ] +Key: MMX_PMAXSWrm: [ 0.00 0.00 ] +Key: MMX_PMAXSWrr: [ 0.00 0.00 ] +Key: MMX_PMAXUBrm: [ 0.00 0.00 ] +Key: MMX_PMAXUBrr: [ 0.00 0.00 ] +Key: MMX_PMINSWrm: [ 0.00 0.00 ] +Key: MMX_PMINSWrr: [ 0.00 0.00 ] +Key: MMX_PMINUBrm: [ 0.00 0.00 ] +Key: MMX_PMINUBrr: [ 0.00 0.00 ] +Key: MMX_PMOVMSKBrr: [ 0.00 0.00 ] +Key: MMX_PMULHRSWrm: [ 0.00 0.00 ] +Key: MMX_PMULHRSWrr: [ 0.00 0.00 ] +Key: MMX_PMULHUWrm: [ 0.00 0.00 ] +Key: MMX_PMULHUWrr: [ 0.00 0.00 ] +Key: MMX_PMULHWrm: [ 0.00 0.00 ] +Key: MMX_PMULHWrr: [ 0.00 0.00 ] +Key: MMX_PMULLWrm: [ 0.00 0.00 ] +Key: MMX_PMULLWrr: [ 0.00 0.00 ] +Key: MMX_PMULUDQrm: [ 0.00 0.00 ] +Key: MMX_PMULUDQrr: [ 0.00 0.00 ] +Key: MMX_PORrm: [ 0.00 0.00 ] +Key: MMX_PORrr: [ 0.00 0.00 ] +Key: MMX_PSADBWrm: [ 0.00 0.00 ] +Key: MMX_PSADBWrr: [ 0.00 0.00 ] +Key: MMX_PSHUFBrm: [ 0.00 0.00 ] +Key: MMX_PSHUFBrr: [ 0.00 0.00 ] +Key: MMX_PSHUFWmi: [ 0.00 0.00 ] +Key: MMX_PSHUFWri: [ 0.00 0.00 ] +Key: MMX_PSIGNBrm: [ 0.00 0.00 ] +Key: MMX_PSIGNBrr: [ 0.00 0.00 ] +Key: MMX_PSIGNDrm: [ 0.00 0.00 ] +Key: MMX_PSIGNDrr: [ 0.00 0.00 ] +Key: MMX_PSIGNWrm: [ 0.00 0.00 ] +Key: MMX_PSIGNWrr: [ 0.00 0.00 ] +Key: MMX_PSLLDri: [ 0.00 0.00 ] +Key: MMX_PSLLDrm: [ 0.00 0.00 ] +Key: MMX_PSLLDrr: [ 0.00 0.00 ] +Key: MMX_PSLLQri: [ 0.00 0.00 ] +Key: MMX_PSLLQrm: [ 0.00 0.00 ] +Key: MMX_PSLLQrr: [ 0.00 0.00 ] +Key: MMX_PSLLWri: [ 0.00 0.00 ] +Key: MMX_PSLLWrm: [ 0.00 0.00 ] +Key: MMX_PSLLWrr: [ 0.00 0.00 ] +Key: MMX_PSRADri: [ 0.00 0.00 ] +Key: MMX_PSRADrm: [ 0.00 0.00 ] +Key: MMX_PSRADrr: [ 0.00 0.00 ] +Key: MMX_PSRAWri: [ 0.00 0.00 ] +Key: MMX_PSRAWrm: [ 0.00 0.00 ] +Key: MMX_PSRAWrr: [ 0.00 0.00 ] +Key: MMX_PSRLDri: [ 0.00 0.00 ] +Key: MMX_PSRLDrm: [ 0.00 0.00 ] +Key: MMX_PSRLDrr: [ 0.00 0.00 ] +Key: MMX_PSRLQri: [ 0.00 0.00 ] +Key: MMX_PSRLQrm: [ 0.00 0.00 ] +Key: MMX_PSRLQrr: [ 0.00 0.00 ] +Key: MMX_PSRLWri: [ 0.00 0.00 ] +Key: MMX_PSRLWrm: [ 0.00 0.00 ] +Key: MMX_PSRLWrr: [ 0.00 0.00 ] +Key: MMX_PSUBBrm: [ 0.00 0.00 ] +Key: MMX_PSUBBrr: [ 0.00 0.00 ] +Key: MMX_PSUBDrm: [ 0.00 0.00 ] +Key: MMX_PSUBDrr: [ 0.00 0.00 ] +Key: MMX_PSUBQrm: [ 0.00 0.00 ] +Key: MMX_PSUBQrr: [ 0.00 0.00 ] +Key: MMX_PSUBSBrm: [ 0.00 0.00 ] +Key: MMX_PSUBSBrr: [ 0.00 0.00 ] +Key: MMX_PSUBSWrm: [ 0.00 0.00 ] +Key: MMX_PSUBSWrr: [ 0.00 0.00 ] +Key: MMX_PSUBUSBrm: [ 0.00 0.00 ] +Key: MMX_PSUBUSBrr: [ 0.00 0.00 ] +Key: MMX_PSUBUSWrm: [ 0.00 0.00 ] +Key: MMX_PSUBUSWrr: [ 0.00 0.00 ] +Key: MMX_PSUBWrm: [ 0.00 0.00 ] +Key: MMX_PSUBWrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKHBWrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKHBWrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKHDQrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKHDQrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKHWDrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKHWDrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKLBWrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKLBWrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKLDQrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKLDQrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKLWDrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKLWDrr: [ 0.00 0.00 ] +Key: MMX_PXORrm: [ 0.00 0.00 ] +Key: MMX_PXORrr: [ 0.00 0.00 ] +Key: MMX_SET: [ 0.00 0.00 ] +Key: MONITOR: [ 0.00 0.00 ] +Key: MONITORX: [ 0.00 0.00 ] +Key: MONTMUL: [ 0.00 0.00 ] +Key: MORESTACK_RET: [ 0.00 0.00 ] +Key: MORESTACK_RET_RESTORE_R: [ 0.00 0.00 ] +Key: MOV: [ 0.00 0.00 ] +Key: MOVAPDmr: [ 0.00 0.00 ] +Key: MOVAPDrm: [ 0.00 0.00 ] +Key: MOVAPDrr: [ 0.00 0.00 ] +Key: MOVAPDrr_REV: [ 0.00 0.00 ] +Key: MOVAPSmr: [ 0.00 0.00 ] +Key: MOVAPSrm: [ 0.00 0.00 ] +Key: MOVAPSrr: [ 0.00 0.00 ] +Key: MOVAPSrr_REV: [ 0.00 0.00 ] +Key: MOVBE: [ 0.00 0.00 ] +Key: MOVDDUPrm: [ 0.00 0.00 ] +Key: MOVDDUPrr: [ 0.00 0.00 ] +Key: MOVDI: [ 0.00 0.00 ] +Key: MOVDIR: [ 0.00 0.00 ] +Key: MOVDIRI: [ 0.00 0.00 ] +Key: MOVDQAmr: [ 0.00 0.00 ] +Key: MOVDQArm: [ 0.00 0.00 ] +Key: MOVDQArr: [ 0.00 0.00 ] +Key: MOVDQArr_REV: [ 0.00 0.00 ] +Key: MOVDQUmr: [ 0.00 0.00 ] +Key: MOVDQUrm: [ 0.00 0.00 ] +Key: MOVDQUrr: [ 0.00 0.00 ] +Key: MOVDQUrr_REV: [ 0.00 0.00 ] +Key: MOVHLPSrr: [ 0.00 0.00 ] +Key: MOVHPDmr: [ 0.00 0.00 ] +Key: MOVHPDrm: [ 0.00 0.00 ] +Key: MOVHPSmr: [ 0.00 0.00 ] +Key: MOVHPSrm: [ 0.00 0.00 ] +Key: MOVLHPSrr: [ 0.00 0.00 ] +Key: MOVLPDmr: [ 0.00 0.00 ] +Key: MOVLPDrm: [ 0.00 0.00 ] +Key: MOVLPSmr: [ 0.00 0.00 ] +Key: MOVLPSrm: [ 0.00 0.00 ] +Key: MOVMSKPDrr: [ 0.00 0.00 ] +Key: MOVMSKPSrr: [ 0.00 0.00 ] +Key: MOVNTDQArm: [ 0.00 0.00 ] +Key: MOVNTDQmr: [ 0.00 0.00 ] +Key: MOVNTI: [ 0.00 0.00 ] +Key: MOVNTImr: [ 0.00 0.00 ] +Key: MOVNTPDmr: [ 0.00 0.00 ] +Key: MOVNTPSmr: [ 0.00 0.00 ] +Key: MOVNTSD: [ 0.00 0.00 ] +Key: MOVNTSS: [ 0.00 0.00 ] +Key: MOVPC: [ 0.00 0.00 ] +Key: MOVPDI: [ 0.00 0.00 ] +Key: MOVPQI: [ 0.00 0.00 ] +Key: MOVPQIto: [ 0.00 0.00 ] +Key: MOVQI: [ 0.00 0.00 ] +Key: MOVRS: [ 0.00 0.00 ] +Key: MOVSB: [ 0.00 0.00 ] +Key: MOVSDmr: [ 0.00 0.00 ] +Key: MOVSDrm: [ 0.00 0.00 ] +Key: MOVSDrm_alt: [ 0.00 0.00 ] +Key: MOVSDrr: [ 0.00 0.00 ] +Key: MOVSDrr_REV: [ 0.00 0.00 ] +Key: MOVSDto: [ 0.00 0.00 ] +Key: MOVSHDUPrm: [ 0.00 0.00 ] +Key: MOVSHDUPrr: [ 0.00 0.00 ] +Key: MOVSHPmr: [ 0.00 0.00 ] +Key: MOVSHPrm: [ 0.00 0.00 ] +Key: MOVSL: [ 0.00 0.00 ] +Key: MOVSLDUPrm: [ 0.00 0.00 ] +Key: MOVSLDUPrr: [ 0.00 0.00 ] +Key: MOVSQ: [ 0.00 0.00 ] +Key: MOVSS: [ 0.00 0.00 ] +Key: MOVSSmr: [ 0.00 0.00 ] +Key: MOVSSrm: [ 0.00 0.00 ] +Key: MOVSSrm_alt: [ 0.00 0.00 ] +Key: MOVSSrr: [ 0.00 0.00 ] +Key: MOVSSrr_REV: [ 0.00 0.00 ] +Key: MOVSW: [ 0.00 0.00 ] +Key: MOVSX: [ 0.00 0.00 ] +Key: MOVUPDmr: [ 0.00 0.00 ] +Key: MOVUPDrm: [ 0.00 0.00 ] +Key: MOVUPDrr: [ 0.00 0.00 ] +Key: MOVUPDrr_REV: [ 0.00 0.00 ] +Key: MOVUPSmr: [ 0.00 0.00 ] +Key: MOVUPSrm: [ 0.00 0.00 ] +Key: MOVUPSrr: [ 0.00 0.00 ] +Key: MOVUPSrr_REV: [ 0.00 0.00 ] +Key: MOVZPQILo: [ 0.00 0.00 ] +Key: MOVZX: [ 0.00 0.00 ] +Key: MPSADBWrmi: [ 0.00 0.00 ] +Key: MPSADBWrri: [ 0.00 0.00 ] +Key: MUL: [ 0.00 0.00 ] +Key: MULPDrm: [ 0.00 0.00 ] +Key: MULPDrr: [ 0.00 0.00 ] +Key: MULPSrm: [ 0.00 0.00 ] +Key: MULPSrr: [ 0.00 0.00 ] +Key: MULSDrm: [ 0.00 0.00 ] +Key: MULSDrm_Int: [ 0.00 0.00 ] +Key: MULSDrr: [ 0.00 0.00 ] +Key: MULSDrr_Int: [ 0.00 0.00 ] +Key: MULSSrm: [ 0.00 0.00 ] +Key: MULSSrm_Int: [ 0.00 0.00 ] +Key: MULSSrr: [ 0.00 0.00 ] +Key: MULSSrr_Int: [ 0.00 0.00 ] +Key: MULX: [ 0.00 0.00 ] +Key: MUL_F: [ 0.00 0.00 ] +Key: MUL_FI: [ 0.00 0.00 ] +Key: MUL_FPrST: [ 0.00 0.00 ] +Key: MUL_FST: [ 0.00 0.00 ] +Key: MUL_Fp: [ 0.00 0.00 ] +Key: MUL_FpI: [ 0.00 0.00 ] +Key: MUL_FrST: [ 0.00 0.00 ] +Key: MWAITX: [ 0.00 0.00 ] +Key: MWAITX_SAVE_RBX: [ 0.00 0.00 ] +Key: MWAITXrrr: [ 0.00 0.00 ] +Key: MWAITrr: [ 0.00 0.00 ] +Key: NEG: [ 0.00 0.00 ] +Key: NOOP: [ 0.00 0.00 ] +Key: NOOPL: [ 0.00 0.00 ] +Key: NOOPLr: [ 0.00 0.00 ] +Key: NOOPQ: [ 0.00 0.00 ] +Key: NOOPQr: [ 0.00 0.00 ] +Key: NOOPW: [ 0.00 0.00 ] +Key: NOOPWr: [ 0.00 0.00 ] +Key: NOT: [ 0.00 0.00 ] +Key: OR: [ 0.00 0.00 ] +Key: ORPDrm: [ 0.00 0.00 ] +Key: ORPDrr: [ 0.00 0.00 ] +Key: ORPSrm: [ 0.00 0.00 ] +Key: ORPSrr: [ 0.00 0.00 ] +Key: OUT: [ 0.00 0.00 ] +Key: OUTSB: [ 0.00 0.00 ] +Key: OUTSL: [ 0.00 0.00 ] +Key: OUTSW: [ 0.00 0.00 ] +Key: PABSBrm: [ 0.00 0.00 ] +Key: PABSBrr: [ 0.00 0.00 ] +Key: PABSDrm: [ 0.00 0.00 ] +Key: PABSDrr: [ 0.00 0.00 ] +Key: PABSWrm: [ 0.00 0.00 ] +Key: PABSWrr: [ 0.00 0.00 ] +Key: PACKSSDWrm: [ 0.00 0.00 ] +Key: PACKSSDWrr: [ 0.00 0.00 ] +Key: PACKSSWBrm: [ 0.00 0.00 ] +Key: PACKSSWBrr: [ 0.00 0.00 ] +Key: PACKUSDWrm: [ 0.00 0.00 ] +Key: PACKUSDWrr: [ 0.00 0.00 ] +Key: PACKUSWBrm: [ 0.00 0.00 ] +Key: PACKUSWBrr: [ 0.00 0.00 ] +Key: PADDBrm: [ 0.00 0.00 ] +Key: PADDBrr: [ 0.00 0.00 ] +Key: PADDDrm: [ 0.00 0.00 ] +Key: PADDDrr: [ 0.00 0.00 ] +Key: PADDQrm: [ 0.00 0.00 ] +Key: PADDQrr: [ 0.00 0.00 ] +Key: PADDSBrm: [ 0.00 0.00 ] +Key: PADDSBrr: [ 0.00 0.00 ] +Key: PADDSWrm: [ 0.00 0.00 ] +Key: PADDSWrr: [ 0.00 0.00 ] +Key: PADDUSBrm: [ 0.00 0.00 ] +Key: PADDUSBrr: [ 0.00 0.00 ] +Key: PADDUSWrm: [ 0.00 0.00 ] +Key: PADDUSWrr: [ 0.00 0.00 ] +Key: PADDWrm: [ 0.00 0.00 ] +Key: PADDWrr: [ 0.00 0.00 ] +Key: PALIGNRrmi: [ 0.00 0.00 ] +Key: PALIGNRrri: [ 0.00 0.00 ] +Key: PANDNrm: [ 0.00 0.00 ] +Key: PANDNrr: [ 0.00 0.00 ] +Key: PANDrm: [ 0.00 0.00 ] +Key: PANDrr: [ 0.00 0.00 ] +Key: PATCHABLE_EVENT_CALL: [ 0.00 0.00 ] +Key: PATCHABLE_FUNCTION_ENTER: [ 0.00 0.00 ] +Key: PATCHABLE_FUNCTION_EXIT: [ 0.00 0.00 ] +Key: PATCHABLE_OP: [ 0.00 0.00 ] +Key: PATCHABLE_RET: [ 0.00 0.00 ] +Key: PATCHABLE_TAIL_CALL: [ 0.00 0.00 ] +Key: PATCHABLE_TYPED_EVENT_CALL: [ 0.00 0.00 ] +Key: PATCHPOINT: [ 0.00 0.00 ] +Key: PAUSE: [ 0.00 0.00 ] +Key: PAVGBrm: [ 0.00 0.00 ] +Key: PAVGBrr: [ 0.00 0.00 ] +Key: PAVGUSBrm: [ 0.00 0.00 ] +Key: PAVGUSBrr: [ 0.00 0.00 ] +Key: PAVGWrm: [ 0.00 0.00 ] +Key: PAVGWrr: [ 0.00 0.00 ] +Key: PBLENDVBrm: [ 0.00 0.00 ] +Key: PBLENDVBrr: [ 0.00 0.00 ] +Key: PBLENDWrmi: [ 0.00 0.00 ] +Key: PBLENDWrri: [ 0.00 0.00 ] +Key: PBNDKB: [ 0.00 0.00 ] +Key: PCLMULQDQrmi: [ 0.00 0.00 ] +Key: PCLMULQDQrri: [ 0.00 0.00 ] +Key: PCMPEQBrm: [ 0.00 0.00 ] +Key: PCMPEQBrr: [ 0.00 0.00 ] +Key: PCMPEQDrm: [ 0.00 0.00 ] +Key: PCMPEQDrr: [ 0.00 0.00 ] +Key: PCMPEQQrm: [ 0.00 0.00 ] +Key: PCMPEQQrr: [ 0.00 0.00 ] +Key: PCMPEQWrm: [ 0.00 0.00 ] +Key: PCMPEQWrr: [ 0.00 0.00 ] +Key: PCMPESTRIrmi: [ 0.00 0.00 ] +Key: PCMPESTRIrri: [ 0.00 0.00 ] +Key: PCMPESTRMrmi: [ 0.00 0.00 ] +Key: PCMPESTRMrri: [ 0.00 0.00 ] +Key: PCMPGTBrm: [ 0.00 0.00 ] +Key: PCMPGTBrr: [ 0.00 0.00 ] +Key: PCMPGTDrm: [ 0.00 0.00 ] +Key: PCMPGTDrr: [ 0.00 0.00 ] +Key: PCMPGTQrm: [ 0.00 0.00 ] +Key: PCMPGTQrr: [ 0.00 0.00 ] +Key: PCMPGTWrm: [ 0.00 0.00 ] +Key: PCMPGTWrr: [ 0.00 0.00 ] +Key: PCMPISTRIrmi: [ 0.00 0.00 ] +Key: PCMPISTRIrri: [ 0.00 0.00 ] +Key: PCMPISTRMrmi: [ 0.00 0.00 ] +Key: PCMPISTRMrri: [ 0.00 0.00 ] +Key: PCONFIG: [ 0.00 0.00 ] +Key: PDEP: [ 0.00 0.00 ] +Key: PEXT: [ 0.00 0.00 ] +Key: PEXTRBmri: [ 0.00 0.00 ] +Key: PEXTRBrri: [ 0.00 0.00 ] +Key: PEXTRDmri: [ 0.00 0.00 ] +Key: PEXTRDrri: [ 0.00 0.00 ] +Key: PEXTRQmri: [ 0.00 0.00 ] +Key: PEXTRQrri: [ 0.00 0.00 ] +Key: PEXTRWmri: [ 0.00 0.00 ] +Key: PEXTRWrri: [ 0.00 0.00 ] +Key: PEXTRWrri_REV: [ 0.00 0.00 ] +Key: PF: [ 0.00 0.00 ] +Key: PFACCrm: [ 0.00 0.00 ] +Key: PFACCrr: [ 0.00 0.00 ] +Key: PFADDrm: [ 0.00 0.00 ] +Key: PFADDrr: [ 0.00 0.00 ] +Key: PFCMPEQrm: [ 0.00 0.00 ] +Key: PFCMPEQrr: [ 0.00 0.00 ] +Key: PFCMPGErm: [ 0.00 0.00 ] +Key: PFCMPGErr: [ 0.00 0.00 ] +Key: PFCMPGTrm: [ 0.00 0.00 ] +Key: PFCMPGTrr: [ 0.00 0.00 ] +Key: PFMAXrm: [ 0.00 0.00 ] +Key: PFMAXrr: [ 0.00 0.00 ] +Key: PFMINrm: [ 0.00 0.00 ] +Key: PFMINrr: [ 0.00 0.00 ] +Key: PFMULrm: [ 0.00 0.00 ] +Key: PFMULrr: [ 0.00 0.00 ] +Key: PFNACCrm: [ 0.00 0.00 ] +Key: PFNACCrr: [ 0.00 0.00 ] +Key: PFPNACCrm: [ 0.00 0.00 ] +Key: PFPNACCrr: [ 0.00 0.00 ] +Key: PFRCPIT: [ 0.00 0.00 ] +Key: PFRCPrm: [ 0.00 0.00 ] +Key: PFRCPrr: [ 0.00 0.00 ] +Key: PFRSQIT: [ 0.00 0.00 ] +Key: PFRSQRTrm: [ 0.00 0.00 ] +Key: PFRSQRTrr: [ 0.00 0.00 ] +Key: PFSUBRrm: [ 0.00 0.00 ] +Key: PFSUBRrr: [ 0.00 0.00 ] +Key: PFSUBrm: [ 0.00 0.00 ] +Key: PFSUBrr: [ 0.00 0.00 ] +Key: PHADDDrm: [ 0.00 0.00 ] +Key: PHADDDrr: [ 0.00 0.00 ] +Key: PHADDSWrm: [ 0.00 0.00 ] +Key: PHADDSWrr: [ 0.00 0.00 ] +Key: PHADDWrm: [ 0.00 0.00 ] +Key: PHADDWrr: [ 0.00 0.00 ] +Key: PHI: [ 0.00 0.00 ] +Key: PHMINPOSUWrm: [ 0.00 0.00 ] +Key: PHMINPOSUWrr: [ 0.00 0.00 ] +Key: PHSUBDrm: [ 0.00 0.00 ] +Key: PHSUBDrr: [ 0.00 0.00 ] +Key: PHSUBSWrm: [ 0.00 0.00 ] +Key: PHSUBSWrr: [ 0.00 0.00 ] +Key: PHSUBWrm: [ 0.00 0.00 ] +Key: PHSUBWrr: [ 0.00 0.00 ] +Key: PI: [ 0.00 0.00 ] +Key: PINSRBrmi: [ 0.00 0.00 ] +Key: PINSRBrri: [ 0.00 0.00 ] +Key: PINSRDrmi: [ 0.00 0.00 ] +Key: PINSRDrri: [ 0.00 0.00 ] +Key: PINSRQrmi: [ 0.00 0.00 ] +Key: PINSRQrri: [ 0.00 0.00 ] +Key: PINSRWrmi: [ 0.00 0.00 ] +Key: PINSRWrri: [ 0.00 0.00 ] +Key: PLDTILECFGV: [ 0.00 0.00 ] +Key: PLEA: [ 0.00 0.00 ] +Key: PMADDUBSWrm: [ 0.00 0.00 ] +Key: PMADDUBSWrr: [ 0.00 0.00 ] +Key: PMADDWDrm: [ 0.00 0.00 ] +Key: PMADDWDrr: [ 0.00 0.00 ] +Key: PMAXSBrm: [ 0.00 0.00 ] +Key: PMAXSBrr: [ 0.00 0.00 ] +Key: PMAXSDrm: [ 0.00 0.00 ] +Key: PMAXSDrr: [ 0.00 0.00 ] +Key: PMAXSWrm: [ 0.00 0.00 ] +Key: PMAXSWrr: [ 0.00 0.00 ] +Key: PMAXUBrm: [ 0.00 0.00 ] +Key: PMAXUBrr: [ 0.00 0.00 ] +Key: PMAXUDrm: [ 0.00 0.00 ] +Key: PMAXUDrr: [ 0.00 0.00 ] +Key: PMAXUWrm: [ 0.00 0.00 ] +Key: PMAXUWrr: [ 0.00 0.00 ] +Key: PMINSBrm: [ 0.00 0.00 ] +Key: PMINSBrr: [ 0.00 0.00 ] +Key: PMINSDrm: [ 0.00 0.00 ] +Key: PMINSDrr: [ 0.00 0.00 ] +Key: PMINSWrm: [ 0.00 0.00 ] +Key: PMINSWrr: [ 0.00 0.00 ] +Key: PMINUBrm: [ 0.00 0.00 ] +Key: PMINUBrr: [ 0.00 0.00 ] +Key: PMINUDrm: [ 0.00 0.00 ] +Key: PMINUDrr: [ 0.00 0.00 ] +Key: PMINUWrm: [ 0.00 0.00 ] +Key: PMINUWrr: [ 0.00 0.00 ] +Key: PMOVMSKBrr: [ 0.00 0.00 ] +Key: PMOVSXBDrm: [ 0.00 0.00 ] +Key: PMOVSXBDrr: [ 0.00 0.00 ] +Key: PMOVSXBQrm: [ 0.00 0.00 ] +Key: PMOVSXBQrr: [ 0.00 0.00 ] +Key: PMOVSXBWrm: [ 0.00 0.00 ] +Key: PMOVSXBWrr: [ 0.00 0.00 ] +Key: PMOVSXDQrm: [ 0.00 0.00 ] +Key: PMOVSXDQrr: [ 0.00 0.00 ] +Key: PMOVSXWDrm: [ 0.00 0.00 ] +Key: PMOVSXWDrr: [ 0.00 0.00 ] +Key: PMOVSXWQrm: [ 0.00 0.00 ] +Key: PMOVSXWQrr: [ 0.00 0.00 ] +Key: PMOVZXBDrm: [ 0.00 0.00 ] +Key: PMOVZXBDrr: [ 0.00 0.00 ] +Key: PMOVZXBQrm: [ 0.00 0.00 ] +Key: PMOVZXBQrr: [ 0.00 0.00 ] +Key: PMOVZXBWrm: [ 0.00 0.00 ] +Key: PMOVZXBWrr: [ 0.00 0.00 ] +Key: PMOVZXDQrm: [ 0.00 0.00 ] +Key: PMOVZXDQrr: [ 0.00 0.00 ] +Key: PMOVZXWDrm: [ 0.00 0.00 ] +Key: PMOVZXWDrr: [ 0.00 0.00 ] +Key: PMOVZXWQrm: [ 0.00 0.00 ] +Key: PMOVZXWQrr: [ 0.00 0.00 ] +Key: PMULDQrm: [ 0.00 0.00 ] +Key: PMULDQrr: [ 0.00 0.00 ] +Key: PMULHRSWrm: [ 0.00 0.00 ] +Key: PMULHRSWrr: [ 0.00 0.00 ] +Key: PMULHRWrm: [ 0.00 0.00 ] +Key: PMULHRWrr: [ 0.00 0.00 ] +Key: PMULHUWrm: [ 0.00 0.00 ] +Key: PMULHUWrr: [ 0.00 0.00 ] +Key: PMULHWrm: [ 0.00 0.00 ] +Key: PMULHWrr: [ 0.00 0.00 ] +Key: PMULLDrm: [ 0.00 0.00 ] +Key: PMULLDrr: [ 0.00 0.00 ] +Key: PMULLWrm: [ 0.00 0.00 ] +Key: PMULLWrr: [ 0.00 0.00 ] +Key: PMULUDQrm: [ 0.00 0.00 ] +Key: PMULUDQrr: [ 0.00 0.00 ] +Key: POP: [ 0.00 0.00 ] +Key: POPA: [ 0.00 0.00 ] +Key: POPCNT: [ 0.00 0.00 ] +Key: POPDS: [ 0.00 0.00 ] +Key: POPES: [ 0.00 0.00 ] +Key: POPF: [ 0.00 0.00 ] +Key: POPFS: [ 0.00 0.00 ] +Key: POPGS: [ 0.00 0.00 ] +Key: POPP: [ 0.00 0.00 ] +Key: POPSS: [ 0.00 0.00 ] +Key: PORrm: [ 0.00 0.00 ] +Key: PORrr: [ 0.00 0.00 ] +Key: PREALLOCATED_ARG: [ 0.00 0.00 ] +Key: PREALLOCATED_SETUP: [ 0.00 0.00 ] +Key: PREFETCH: [ 0.00 0.00 ] +Key: PREFETCHIT: [ 0.00 0.00 ] +Key: PREFETCHNTA: [ 0.00 0.00 ] +Key: PREFETCHRST: [ 0.00 0.00 ] +Key: PREFETCHT: [ 0.00 0.00 ] +Key: PREFETCHW: [ 0.00 0.00 ] +Key: PREFETCHWT: [ 0.00 0.00 ] +Key: PROBED_ALLOCA: [ 0.00 0.00 ] +Key: PSADBWrm: [ 0.00 0.00 ] +Key: PSADBWrr: [ 0.00 0.00 ] +Key: PSEUDO_PROBE: [ 0.00 0.00 ] +Key: PSHUFBrm: [ 0.00 0.00 ] +Key: PSHUFBrr: [ 0.00 0.00 ] +Key: PSHUFDmi: [ 0.00 0.00 ] +Key: PSHUFDri: [ 0.00 0.00 ] +Key: PSHUFHWmi: [ 0.00 0.00 ] +Key: PSHUFHWri: [ 0.00 0.00 ] +Key: PSHUFLWmi: [ 0.00 0.00 ] +Key: PSHUFLWri: [ 0.00 0.00 ] +Key: PSIGNBrm: [ 0.00 0.00 ] +Key: PSIGNBrr: [ 0.00 0.00 ] +Key: PSIGNDrm: [ 0.00 0.00 ] +Key: PSIGNDrr: [ 0.00 0.00 ] +Key: PSIGNWrm: [ 0.00 0.00 ] +Key: PSIGNWrr: [ 0.00 0.00 ] +Key: PSLLDQri: [ 0.00 0.00 ] +Key: PSLLDri: [ 0.00 0.00 ] +Key: PSLLDrm: [ 0.00 0.00 ] +Key: PSLLDrr: [ 0.00 0.00 ] +Key: PSLLQri: [ 0.00 0.00 ] +Key: PSLLQrm: [ 0.00 0.00 ] +Key: PSLLQrr: [ 0.00 0.00 ] +Key: PSLLWri: [ 0.00 0.00 ] +Key: PSLLWrm: [ 0.00 0.00 ] +Key: PSLLWrr: [ 0.00 0.00 ] +Key: PSMASH: [ 0.00 0.00 ] +Key: PSRADri: [ 0.00 0.00 ] +Key: PSRADrm: [ 0.00 0.00 ] +Key: PSRADrr: [ 0.00 0.00 ] +Key: PSRAWri: [ 0.00 0.00 ] +Key: PSRAWrm: [ 0.00 0.00 ] +Key: PSRAWrr: [ 0.00 0.00 ] +Key: PSRLDQri: [ 0.00 0.00 ] +Key: PSRLDri: [ 0.00 0.00 ] +Key: PSRLDrm: [ 0.00 0.00 ] +Key: PSRLDrr: [ 0.00 0.00 ] +Key: PSRLQri: [ 0.00 0.00 ] +Key: PSRLQrm: [ 0.00 0.00 ] +Key: PSRLQrr: [ 0.00 0.00 ] +Key: PSRLWri: [ 0.00 0.00 ] +Key: PSRLWrm: [ 0.00 0.00 ] +Key: PSRLWrr: [ 0.00 0.00 ] +Key: PSUBBrm: [ 0.00 0.00 ] +Key: PSUBBrr: [ 0.00 0.00 ] +Key: PSUBDrm: [ 0.00 0.00 ] +Key: PSUBDrr: [ 0.00 0.00 ] +Key: PSUBQrm: [ 0.00 0.00 ] +Key: PSUBQrr: [ 0.00 0.00 ] +Key: PSUBSBrm: [ 0.00 0.00 ] +Key: PSUBSBrr: [ 0.00 0.00 ] +Key: PSUBSWrm: [ 0.00 0.00 ] +Key: PSUBSWrr: [ 0.00 0.00 ] +Key: PSUBUSBrm: [ 0.00 0.00 ] +Key: PSUBUSBrr: [ 0.00 0.00 ] +Key: PSUBUSWrm: [ 0.00 0.00 ] +Key: PSUBUSWrr: [ 0.00 0.00 ] +Key: PSUBWrm: [ 0.00 0.00 ] +Key: PSUBWrr: [ 0.00 0.00 ] +Key: PSWAPDrm: [ 0.00 0.00 ] +Key: PSWAPDrr: [ 0.00 0.00 ] +Key: PT: [ 0.00 0.00 ] +Key: PTCMMIMFP: [ 0.00 0.00 ] +Key: PTCMMRLFP: [ 0.00 0.00 ] +Key: PTCONJTCMMIMFP: [ 0.00 0.00 ] +Key: PTCONJTFP: [ 0.00 0.00 ] +Key: PTCVTROWD: [ 0.00 0.00 ] +Key: PTCVTROWPS: [ 0.00 0.00 ] +Key: PTDPBF: [ 0.00 0.00 ] +Key: PTDPBHF: [ 0.00 0.00 ] +Key: PTDPBSSD: [ 0.00 0.00 ] +Key: PTDPBSSDV: [ 0.00 0.00 ] +Key: PTDPBSUD: [ 0.00 0.00 ] +Key: PTDPBSUDV: [ 0.00 0.00 ] +Key: PTDPBUSD: [ 0.00 0.00 ] +Key: PTDPBUSDV: [ 0.00 0.00 ] +Key: PTDPBUUD: [ 0.00 0.00 ] +Key: PTDPBUUDV: [ 0.00 0.00 ] +Key: PTDPFP: [ 0.00 0.00 ] +Key: PTDPHBF: [ 0.00 0.00 ] +Key: PTDPHF: [ 0.00 0.00 ] +Key: PTESTrm: [ 0.00 0.00 ] +Key: PTESTrr: [ 0.00 0.00 ] +Key: PTILELOADD: [ 0.00 0.00 ] +Key: PTILELOADDRS: [ 0.00 0.00 ] +Key: PTILELOADDRST: [ 0.00 0.00 ] +Key: PTILELOADDRSV: [ 0.00 0.00 ] +Key: PTILELOADDT: [ 0.00 0.00 ] +Key: PTILELOADDV: [ 0.00 0.00 ] +Key: PTILEMOVROWrre: [ 0.00 0.00 ] +Key: PTILEMOVROWrreV: [ 0.00 0.00 ] +Key: PTILEMOVROWrri: [ 0.00 0.00 ] +Key: PTILEMOVROWrriV: [ 0.00 0.00 ] +Key: PTILEPAIRLOAD: [ 0.00 0.00 ] +Key: PTILEPAIRSTORE: [ 0.00 0.00 ] +Key: PTILESTORED: [ 0.00 0.00 ] +Key: PTILESTOREDV: [ 0.00 0.00 ] +Key: PTILEZERO: [ 0.00 0.00 ] +Key: PTILEZEROV: [ 0.00 0.00 ] +Key: PTMMULTF: [ 0.00 0.00 ] +Key: PTTCMMIMFP: [ 0.00 0.00 ] +Key: PTTCMMRLFP: [ 0.00 0.00 ] +Key: PTTDPBF: [ 0.00 0.00 ] +Key: PTTDPFP: [ 0.00 0.00 ] +Key: PTTMMULTF: [ 0.00 0.00 ] +Key: PTTRANSPOSED: [ 0.00 0.00 ] +Key: PTTRANSPOSEDV: [ 0.00 0.00 ] +Key: PTWRITE: [ 0.00 0.00 ] +Key: PTWRITEm: [ 0.00 0.00 ] +Key: PTWRITEr: [ 0.00 0.00 ] +Key: PUNPCKHBWrm: [ 0.00 0.00 ] +Key: PUNPCKHBWrr: [ 0.00 0.00 ] +Key: PUNPCKHDQrm: [ 0.00 0.00 ] +Key: PUNPCKHDQrr: [ 0.00 0.00 ] +Key: PUNPCKHQDQrm: [ 0.00 0.00 ] +Key: PUNPCKHQDQrr: [ 0.00 0.00 ] +Key: PUNPCKHWDrm: [ 0.00 0.00 ] +Key: PUNPCKHWDrr: [ 0.00 0.00 ] +Key: PUNPCKLBWrm: [ 0.00 0.00 ] +Key: PUNPCKLBWrr: [ 0.00 0.00 ] +Key: PUNPCKLDQrm: [ 0.00 0.00 ] +Key: PUNPCKLDQrr: [ 0.00 0.00 ] +Key: PUNPCKLQDQrm: [ 0.00 0.00 ] +Key: PUNPCKLQDQrr: [ 0.00 0.00 ] +Key: PUNPCKLWDrm: [ 0.00 0.00 ] +Key: PUNPCKLWDrr: [ 0.00 0.00 ] +Key: PUSH: [ 0.00 0.00 ] +Key: PUSHA: [ 0.00 0.00 ] +Key: PUSHCS: [ 0.00 0.00 ] +Key: PUSHDS: [ 0.00 0.00 ] +Key: PUSHES: [ 0.00 0.00 ] +Key: PUSHF: [ 0.00 0.00 ] +Key: PUSHFS: [ 0.00 0.00 ] +Key: PUSHGS: [ 0.00 0.00 ] +Key: PUSHP: [ 0.00 0.00 ] +Key: PUSHSS: [ 0.00 0.00 ] +Key: PVALIDATE: [ 0.00 0.00 ] +Key: PXORrm: [ 0.00 0.00 ] +Key: PXORrr: [ 0.00 0.00 ] +Key: RCL: [ 0.00 0.00 ] +Key: RCPPSm: [ 0.00 0.00 ] +Key: RCPPSr: [ 0.00 0.00 ] +Key: RCPSSm: [ 0.00 0.00 ] +Key: RCPSSm_Int: [ 0.00 0.00 ] +Key: RCPSSr: [ 0.00 0.00 ] +Key: RCPSSr_Int: [ 0.00 0.00 ] +Key: RCR: [ 0.00 0.00 ] +Key: RDFLAGS: [ 0.00 0.00 ] +Key: RDFSBASE: [ 0.00 0.00 ] +Key: RDGSBASE: [ 0.00 0.00 ] +Key: RDMSR: [ 0.00 0.00 ] +Key: RDMSRLIST: [ 0.00 0.00 ] +Key: RDMSRri: [ 0.00 0.00 ] +Key: RDMSRri_EVEX: [ 0.00 0.00 ] +Key: RDPID: [ 0.00 0.00 ] +Key: RDPKRUr: [ 0.00 0.00 ] +Key: RDPMC: [ 0.00 0.00 ] +Key: RDPRU: [ 0.00 0.00 ] +Key: RDRAND: [ 0.00 0.00 ] +Key: RDSEED: [ 0.00 0.00 ] +Key: RDSSPD: [ 0.00 0.00 ] +Key: RDSSPQ: [ 0.00 0.00 ] +Key: RDTSC: [ 0.00 0.00 ] +Key: RDTSCP: [ 0.00 0.00 ] +Key: REG_SEQUENCE: [ 0.00 0.00 ] +Key: REPNE_PREFIX: [ 0.00 0.00 ] +Key: REP_MOVSB: [ 0.00 0.00 ] +Key: REP_MOVSD: [ 0.00 0.00 ] +Key: REP_MOVSQ: [ 0.00 0.00 ] +Key: REP_MOVSW: [ 0.00 0.00 ] +Key: REP_PREFIX: [ 0.00 0.00 ] +Key: REP_STOSB: [ 0.00 0.00 ] +Key: REP_STOSD: [ 0.00 0.00 ] +Key: REP_STOSQ: [ 0.00 0.00 ] +Key: REP_STOSW: [ 0.00 0.00 ] +Key: RET: [ 0.00 0.00 ] +Key: RETI: [ 0.00 0.00 ] +Key: REX: [ 0.00 0.00 ] +Key: RMPADJUST: [ 0.00 0.00 ] +Key: RMPQUERY: [ 0.00 0.00 ] +Key: RMPUPDATE: [ 0.00 0.00 ] +Key: ROL: [ 0.00 0.00 ] +Key: ROR: [ 0.00 0.00 ] +Key: RORX: [ 0.00 0.00 ] +Key: ROUNDPDmi: [ 0.00 0.00 ] +Key: ROUNDPDri: [ 0.00 0.00 ] +Key: ROUNDPSmi: [ 0.00 0.00 ] +Key: ROUNDPSri: [ 0.00 0.00 ] +Key: ROUNDSDmi: [ 0.00 0.00 ] +Key: ROUNDSDmi_Int: [ 0.00 0.00 ] +Key: ROUNDSDri: [ 0.00 0.00 ] +Key: ROUNDSDri_Int: [ 0.00 0.00 ] +Key: ROUNDSSmi: [ 0.00 0.00 ] +Key: ROUNDSSmi_Int: [ 0.00 0.00 ] +Key: ROUNDSSri: [ 0.00 0.00 ] +Key: ROUNDSSri_Int: [ 0.00 0.00 ] +Key: RSM: [ 0.00 0.00 ] +Key: RSQRTPSm: [ 0.00 0.00 ] +Key: RSQRTPSr: [ 0.00 0.00 ] +Key: RSQRTSSm: [ 0.00 0.00 ] +Key: RSQRTSSm_Int: [ 0.00 0.00 ] +Key: RSQRTSSr: [ 0.00 0.00 ] +Key: RSQRTSSr_Int: [ 0.00 0.00 ] +Key: RSTORSSP: [ 0.00 0.00 ] +Key: SAHF: [ 0.00 0.00 ] +Key: SALC: [ 0.00 0.00 ] +Key: SAR: [ 0.00 0.00 ] +Key: SARX: [ 0.00 0.00 ] +Key: SAVEPREVSSP: [ 0.00 0.00 ] +Key: SBB: [ 0.00 0.00 ] +Key: SCASB: [ 0.00 0.00 ] +Key: SCASL: [ 0.00 0.00 ] +Key: SCASQ: [ 0.00 0.00 ] +Key: SCASW: [ 0.00 0.00 ] +Key: SEAMCALL: [ 0.00 0.00 ] +Key: SEAMOPS: [ 0.00 0.00 ] +Key: SEAMRET: [ 0.00 0.00 ] +Key: SEG_ALLOCA: [ 0.00 0.00 ] +Key: SEH_BeginEpilogue: [ 0.00 0.00 ] +Key: SEH_EndEpilogue: [ 0.00 0.00 ] +Key: SEH_EndPrologue: [ 0.00 0.00 ] +Key: SEH_PushFrame: [ 0.00 0.00 ] +Key: SEH_PushReg: [ 0.00 0.00 ] +Key: SEH_SaveReg: [ 0.00 0.00 ] +Key: SEH_SaveXMM: [ 0.00 0.00 ] +Key: SEH_SetFrame: [ 0.00 0.00 ] +Key: SEH_StackAlign: [ 0.00 0.00 ] +Key: SEH_StackAlloc: [ 0.00 0.00 ] +Key: SEH_UnwindV: [ 0.00 0.00 ] +Key: SEH_UnwindVersion: [ 0.00 0.00 ] +Key: SENDUIPI: [ 0.00 0.00 ] +Key: SERIALIZE: [ 0.00 0.00 ] +Key: SETB_C: [ 0.00 0.00 ] +Key: SETCCm: [ 0.00 0.00 ] +Key: SETCCm_EVEX: [ 0.00 0.00 ] +Key: SETCCr: [ 0.00 0.00 ] +Key: SETCCr_EVEX: [ 0.00 0.00 ] +Key: SETSSBSY: [ 0.00 0.00 ] +Key: SETZUCCm: [ 0.00 0.00 ] +Key: SETZUCCr: [ 0.00 0.00 ] +Key: SFENCE: [ 0.00 0.00 ] +Key: SGDT: [ 0.00 0.00 ] +Key: SHA: [ 0.00 0.00 ] +Key: SHL: [ 0.00 0.00 ] +Key: SHLD: [ 0.00 0.00 ] +Key: SHLDROT: [ 0.00 0.00 ] +Key: SHLX: [ 0.00 0.00 ] +Key: SHR: [ 0.00 0.00 ] +Key: SHRD: [ 0.00 0.00 ] +Key: SHRDROT: [ 0.00 0.00 ] +Key: SHRX: [ 0.00 0.00 ] +Key: SHUFPDrmi: [ 0.00 0.00 ] +Key: SHUFPDrri: [ 0.00 0.00 ] +Key: SHUFPSrmi: [ 0.00 0.00 ] +Key: SHUFPSrri: [ 0.00 0.00 ] +Key: SIDT: [ 0.00 0.00 ] +Key: SKINIT: [ 0.00 0.00 ] +Key: SLDT: [ 0.00 0.00 ] +Key: SLWPCB: [ 0.00 0.00 ] +Key: SMSW: [ 0.00 0.00 ] +Key: SQRTPDm: [ 0.00 0.00 ] +Key: SQRTPDr: [ 0.00 0.00 ] +Key: SQRTPSm: [ 0.00 0.00 ] +Key: SQRTPSr: [ 0.00 0.00 ] +Key: SQRTSDm: [ 0.00 0.00 ] +Key: SQRTSDm_Int: [ 0.00 0.00 ] +Key: SQRTSDr: [ 0.00 0.00 ] +Key: SQRTSDr_Int: [ 0.00 0.00 ] +Key: SQRTSSm: [ 0.00 0.00 ] +Key: SQRTSSm_Int: [ 0.00 0.00 ] +Key: SQRTSSr: [ 0.00 0.00 ] +Key: SQRTSSr_Int: [ 0.00 0.00 ] +Key: SQRT_F: [ 0.00 0.00 ] +Key: SQRT_Fp: [ 0.00 0.00 ] +Key: SS_PREFIX: [ 0.00 0.00 ] +Key: STAC: [ 0.00 0.00 ] +Key: STACKALLOC_W_PROBING: [ 0.00 0.00 ] +Key: STACKMAP: [ 0.00 0.00 ] +Key: STATEPOINT: [ 0.00 0.00 ] +Key: STC: [ 0.00 0.00 ] +Key: STD: [ 0.00 0.00 ] +Key: STGI: [ 0.00 0.00 ] +Key: STI: [ 0.00 0.00 ] +Key: STMXCSR: [ 0.00 0.00 ] +Key: STOSB: [ 0.00 0.00 ] +Key: STOSL: [ 0.00 0.00 ] +Key: STOSQ: [ 0.00 0.00 ] +Key: STOSW: [ 0.00 0.00 ] +Key: STR: [ 0.00 0.00 ] +Key: STRm: [ 0.00 0.00 ] +Key: STTILECFG: [ 0.00 0.00 ] +Key: STTILECFG_EVEX: [ 0.00 0.00 ] +Key: STUI: [ 0.00 0.00 ] +Key: ST_F: [ 0.00 0.00 ] +Key: ST_FP: [ 0.00 0.00 ] +Key: ST_FPrr: [ 0.00 0.00 ] +Key: ST_Fp: [ 0.00 0.00 ] +Key: ST_FpP: [ 0.00 0.00 ] +Key: ST_Frr: [ 0.00 0.00 ] +Key: SUB: [ 0.00 0.00 ] +Key: SUBPDrm: [ 0.00 0.00 ] +Key: SUBPDrr: [ 0.00 0.00 ] +Key: SUBPSrm: [ 0.00 0.00 ] +Key: SUBPSrr: [ 0.00 0.00 ] +Key: SUBREG_TO_REG: [ 0.00 0.00 ] +Key: SUBR_F: [ 0.00 0.00 ] +Key: SUBR_FI: [ 0.00 0.00 ] +Key: SUBR_FPrST: [ 0.00 0.00 ] +Key: SUBR_FST: [ 0.00 0.00 ] +Key: SUBR_Fp: [ 0.00 0.00 ] +Key: SUBR_FpI: [ 0.00 0.00 ] +Key: SUBR_FrST: [ 0.00 0.00 ] +Key: SUBSDrm: [ 0.00 0.00 ] +Key: SUBSDrm_Int: [ 0.00 0.00 ] +Key: SUBSDrr: [ 0.00 0.00 ] +Key: SUBSDrr_Int: [ 0.00 0.00 ] +Key: SUBSSrm: [ 0.00 0.00 ] +Key: SUBSSrm_Int: [ 0.00 0.00 ] +Key: SUBSSrr: [ 0.00 0.00 ] +Key: SUBSSrr_Int: [ 0.00 0.00 ] +Key: SUB_F: [ 0.00 0.00 ] +Key: SUB_FI: [ 0.00 0.00 ] +Key: SUB_FPrST: [ 0.00 0.00 ] +Key: SUB_FST: [ 0.00 0.00 ] +Key: SUB_Fp: [ 0.00 0.00 ] +Key: SUB_FpI: [ 0.00 0.00 ] +Key: SUB_FrST: [ 0.00 0.00 ] +Key: SWAPGS: [ 0.00 0.00 ] +Key: SYSCALL: [ 0.00 0.00 ] +Key: SYSENTER: [ 0.00 0.00 ] +Key: SYSEXIT: [ 0.00 0.00 ] +Key: SYSRET: [ 0.00 0.00 ] +Key: T: [ 0.00 0.00 ] +Key: TAILJMPd: [ 0.00 0.00 ] +Key: TAILJMPd_CC: [ 0.00 0.00 ] +Key: TAILJMPm: [ 0.00 0.00 ] +Key: TAILJMPr: [ 0.00 0.00 ] +Key: TCMMIMFP: [ 0.00 0.00 ] +Key: TCMMRLFP: [ 0.00 0.00 ] +Key: TCONJTCMMIMFP: [ 0.00 0.00 ] +Key: TCONJTFP: [ 0.00 0.00 ] +Key: TCRETURN_HIPE: [ 0.00 0.00 ] +Key: TCRETURN_WIN: [ 0.00 0.00 ] +Key: TCRETURN_WINmi: [ 0.00 0.00 ] +Key: TCRETURNdi: [ 0.00 0.00 ] +Key: TCRETURNdicc: [ 0.00 0.00 ] +Key: TCRETURNmi: [ 0.00 0.00 ] +Key: TCRETURNri: [ 0.00 0.00 ] +Key: TCVTROWD: [ 0.00 0.00 ] +Key: TCVTROWPS: [ 0.00 0.00 ] +Key: TDCALL: [ 0.00 0.00 ] +Key: TDPBF: [ 0.00 0.00 ] +Key: TDPBHF: [ 0.00 0.00 ] +Key: TDPBSSD: [ 0.00 0.00 ] +Key: TDPBSUD: [ 0.00 0.00 ] +Key: TDPBUSD: [ 0.00 0.00 ] +Key: TDPBUUD: [ 0.00 0.00 ] +Key: TDPFP: [ 0.00 0.00 ] +Key: TDPHBF: [ 0.00 0.00 ] +Key: TDPHF: [ 0.00 0.00 ] +Key: TEST: [ 0.00 0.00 ] +Key: TESTUI: [ 0.00 0.00 ] +Key: TILELOADD: [ 0.00 0.00 ] +Key: TILELOADDRS: [ 0.00 0.00 ] +Key: TILELOADDRST: [ 0.00 0.00 ] +Key: TILELOADDRS_EVEX: [ 0.00 0.00 ] +Key: TILELOADDT: [ 0.00 0.00 ] +Key: TILELOADD_EVEX: [ 0.00 0.00 ] +Key: TILEMOVROWrre: [ 0.00 0.00 ] +Key: TILEMOVROWrri: [ 0.00 0.00 ] +Key: TILERELEASE: [ 0.00 0.00 ] +Key: TILESTORED: [ 0.00 0.00 ] +Key: TILESTORED_EVEX: [ 0.00 0.00 ] +Key: TILEZERO: [ 0.00 0.00 ] +Key: TLBSYNC: [ 0.00 0.00 ] +Key: TLSCall: [ 0.00 0.00 ] +Key: TLS_addr: [ 0.00 0.00 ] +Key: TLS_addrX: [ 0.00 0.00 ] +Key: TLS_base_addr: [ 0.00 0.00 ] +Key: TLS_base_addrX: [ 0.00 0.00 ] +Key: TLS_desc: [ 0.00 0.00 ] +Key: TMMULTF: [ 0.00 0.00 ] +Key: TPAUSE: [ 0.00 0.00 ] +Key: TRAP: [ 0.00 0.00 ] +Key: TST_F: [ 0.00 0.00 ] +Key: TST_Fp: [ 0.00 0.00 ] +Key: TTCMMIMFP: [ 0.00 0.00 ] +Key: TTCMMRLFP: [ 0.00 0.00 ] +Key: TTDPBF: [ 0.00 0.00 ] +Key: TTDPFP: [ 0.00 0.00 ] +Key: TTMMULTF: [ 0.00 0.00 ] +Key: TTRANSPOSED: [ 0.00 0.00 ] +Key: TZCNT: [ 0.00 0.00 ] +Key: TZMSK: [ 0.00 0.00 ] +Key: UBSAN_UD: [ 0.00 0.00 ] +Key: UCOMISDrm: [ 0.00 0.00 ] +Key: UCOMISDrm_Int: [ 0.00 0.00 ] +Key: UCOMISDrr: [ 0.00 0.00 ] +Key: UCOMISDrr_Int: [ 0.00 0.00 ] +Key: UCOMISSrm: [ 0.00 0.00 ] +Key: UCOMISSrm_Int: [ 0.00 0.00 ] +Key: UCOMISSrr: [ 0.00 0.00 ] +Key: UCOMISSrr_Int: [ 0.00 0.00 ] +Key: UCOM_FIPr: [ 0.00 0.00 ] +Key: UCOM_FIr: [ 0.00 0.00 ] +Key: UCOM_FPPr: [ 0.00 0.00 ] +Key: UCOM_FPr: [ 0.00 0.00 ] +Key: UCOM_FpIr: [ 0.00 0.00 ] +Key: UCOM_Fpr: [ 0.00 0.00 ] +Key: UCOM_Fr: [ 0.00 0.00 ] +Key: UD: [ 0.00 0.00 ] +Key: UIRET: [ 0.00 0.00 ] +Key: UMONITOR: [ 0.00 0.00 ] +Key: UMWAIT: [ 0.00 0.00 ] +Key: UNPCKHPDrm: [ 0.00 0.00 ] +Key: UNPCKHPDrr: [ 0.00 0.00 ] +Key: UNPCKHPSrm: [ 0.00 0.00 ] +Key: UNPCKHPSrr: [ 0.00 0.00 ] +Key: UNPCKLPDrm: [ 0.00 0.00 ] +Key: UNPCKLPDrr: [ 0.00 0.00 ] +Key: UNPCKLPSrm: [ 0.00 0.00 ] +Key: UNPCKLPSrr: [ 0.00 0.00 ] +Key: URDMSRri: [ 0.00 0.00 ] +Key: URDMSRri_EVEX: [ 0.00 0.00 ] +Key: URDMSRrr: [ 0.00 0.00 ] +Key: URDMSRrr_EVEX: [ 0.00 0.00 ] +Key: UWRMSRir: [ 0.00 0.00 ] +Key: UWRMSRir_EVEX: [ 0.00 0.00 ] +Key: UWRMSRrr: [ 0.00 0.00 ] +Key: UWRMSRrr_EVEX: [ 0.00 0.00 ] +Key: V: [ 0.00 0.00 ] +Key: VAARG: [ 0.00 0.00 ] +Key: VAARG_X: [ 0.00 0.00 ] +Key: VADDBF: [ 0.00 0.00 ] +Key: VADDPDYrm: [ 0.00 0.00 ] +Key: VADDPDYrr: [ 0.00 0.00 ] +Key: VADDPDZ: [ 0.00 0.00 ] +Key: VADDPDZrm: [ 0.00 0.00 ] +Key: VADDPDZrmb: [ 0.00 0.00 ] +Key: VADDPDZrmbk: [ 0.00 0.00 ] +Key: VADDPDZrmbkz: [ 0.00 0.00 ] +Key: VADDPDZrmk: [ 0.00 0.00 ] +Key: VADDPDZrmkz: [ 0.00 0.00 ] +Key: VADDPDZrr: [ 0.00 0.00 ] +Key: VADDPDZrrb: [ 0.00 0.00 ] +Key: VADDPDZrrbk: [ 0.00 0.00 ] +Key: VADDPDZrrbkz: [ 0.00 0.00 ] +Key: VADDPDZrrk: [ 0.00 0.00 ] +Key: VADDPDZrrkz: [ 0.00 0.00 ] +Key: VADDPDrm: [ 0.00 0.00 ] +Key: VADDPDrr: [ 0.00 0.00 ] +Key: VADDPHZ: [ 0.00 0.00 ] +Key: VADDPHZrm: [ 0.00 0.00 ] +Key: VADDPHZrmb: [ 0.00 0.00 ] +Key: VADDPHZrmbk: [ 0.00 0.00 ] +Key: VADDPHZrmbkz: [ 0.00 0.00 ] +Key: VADDPHZrmk: [ 0.00 0.00 ] +Key: VADDPHZrmkz: [ 0.00 0.00 ] +Key: VADDPHZrr: [ 0.00 0.00 ] +Key: VADDPHZrrb: [ 0.00 0.00 ] +Key: VADDPHZrrbk: [ 0.00 0.00 ] +Key: VADDPHZrrbkz: [ 0.00 0.00 ] +Key: VADDPHZrrk: [ 0.00 0.00 ] +Key: VADDPHZrrkz: [ 0.00 0.00 ] +Key: VADDPSYrm: [ 0.00 0.00 ] +Key: VADDPSYrr: [ 0.00 0.00 ] +Key: VADDPSZ: [ 0.00 0.00 ] +Key: VADDPSZrm: [ 0.00 0.00 ] +Key: VADDPSZrmb: [ 0.00 0.00 ] +Key: VADDPSZrmbk: [ 0.00 0.00 ] +Key: VADDPSZrmbkz: [ 0.00 0.00 ] +Key: VADDPSZrmk: [ 0.00 0.00 ] +Key: VADDPSZrmkz: [ 0.00 0.00 ] +Key: VADDPSZrr: [ 0.00 0.00 ] +Key: VADDPSZrrb: [ 0.00 0.00 ] +Key: VADDPSZrrbk: [ 0.00 0.00 ] +Key: VADDPSZrrbkz: [ 0.00 0.00 ] +Key: VADDPSZrrk: [ 0.00 0.00 ] +Key: VADDPSZrrkz: [ 0.00 0.00 ] +Key: VADDPSrm: [ 0.00 0.00 ] +Key: VADDPSrr: [ 0.00 0.00 ] +Key: VADDSDZrm: [ 0.00 0.00 ] +Key: VADDSDZrm_Int: [ 0.00 0.00 ] +Key: VADDSDZrmk_Int: [ 0.00 0.00 ] +Key: VADDSDZrmkz_Int: [ 0.00 0.00 ] +Key: VADDSDZrr: [ 0.00 0.00 ] +Key: VADDSDZrr_Int: [ 0.00 0.00 ] +Key: VADDSDZrrb_Int: [ 0.00 0.00 ] +Key: VADDSDZrrbk_Int: [ 0.00 0.00 ] +Key: VADDSDZrrbkz_Int: [ 0.00 0.00 ] +Key: VADDSDZrrk_Int: [ 0.00 0.00 ] +Key: VADDSDZrrkz_Int: [ 0.00 0.00 ] +Key: VADDSDrm: [ 0.00 0.00 ] +Key: VADDSDrm_Int: [ 0.00 0.00 ] +Key: VADDSDrr: [ 0.00 0.00 ] +Key: VADDSDrr_Int: [ 0.00 0.00 ] +Key: VADDSHZrm: [ 0.00 0.00 ] +Key: VADDSHZrm_Int: [ 0.00 0.00 ] +Key: VADDSHZrmk_Int: [ 0.00 0.00 ] +Key: VADDSHZrmkz_Int: [ 0.00 0.00 ] +Key: VADDSHZrr: [ 0.00 0.00 ] +Key: VADDSHZrr_Int: [ 0.00 0.00 ] +Key: VADDSHZrrb_Int: [ 0.00 0.00 ] +Key: VADDSHZrrbk_Int: [ 0.00 0.00 ] +Key: VADDSHZrrbkz_Int: [ 0.00 0.00 ] +Key: VADDSHZrrk_Int: [ 0.00 0.00 ] +Key: VADDSHZrrkz_Int: [ 0.00 0.00 ] +Key: VADDSSZrm: [ 0.00 0.00 ] +Key: VADDSSZrm_Int: [ 0.00 0.00 ] +Key: VADDSSZrmk_Int: [ 0.00 0.00 ] +Key: VADDSSZrmkz_Int: [ 0.00 0.00 ] +Key: VADDSSZrr: [ 0.00 0.00 ] +Key: VADDSSZrr_Int: [ 0.00 0.00 ] +Key: VADDSSZrrb_Int: [ 0.00 0.00 ] +Key: VADDSSZrrbk_Int: [ 0.00 0.00 ] +Key: VADDSSZrrbkz_Int: [ 0.00 0.00 ] +Key: VADDSSZrrk_Int: [ 0.00 0.00 ] +Key: VADDSSZrrkz_Int: [ 0.00 0.00 ] +Key: VADDSSrm: [ 0.00 0.00 ] +Key: VADDSSrm_Int: [ 0.00 0.00 ] +Key: VADDSSrr: [ 0.00 0.00 ] +Key: VADDSSrr_Int: [ 0.00 0.00 ] +Key: VADDSUBPDYrm: [ 0.00 0.00 ] +Key: VADDSUBPDYrr: [ 0.00 0.00 ] +Key: VADDSUBPDrm: [ 0.00 0.00 ] +Key: VADDSUBPDrr: [ 0.00 0.00 ] +Key: VADDSUBPSYrm: [ 0.00 0.00 ] +Key: VADDSUBPSYrr: [ 0.00 0.00 ] +Key: VADDSUBPSrm: [ 0.00 0.00 ] +Key: VADDSUBPSrr: [ 0.00 0.00 ] +Key: VAESDECLASTYrm: [ 0.00 0.00 ] +Key: VAESDECLASTYrr: [ 0.00 0.00 ] +Key: VAESDECLASTZ: [ 0.00 0.00 ] +Key: VAESDECLASTZrm: [ 0.00 0.00 ] +Key: VAESDECLASTZrr: [ 0.00 0.00 ] +Key: VAESDECLASTrm: [ 0.00 0.00 ] +Key: VAESDECLASTrr: [ 0.00 0.00 ] +Key: VAESDECYrm: [ 0.00 0.00 ] +Key: VAESDECYrr: [ 0.00 0.00 ] +Key: VAESDECZ: [ 0.00 0.00 ] +Key: VAESDECZrm: [ 0.00 0.00 ] +Key: VAESDECZrr: [ 0.00 0.00 ] +Key: VAESDECrm: [ 0.00 0.00 ] +Key: VAESDECrr: [ 0.00 0.00 ] +Key: VAESENCLASTYrm: [ 0.00 0.00 ] +Key: VAESENCLASTYrr: [ 0.00 0.00 ] +Key: VAESENCLASTZ: [ 0.00 0.00 ] +Key: VAESENCLASTZrm: [ 0.00 0.00 ] +Key: VAESENCLASTZrr: [ 0.00 0.00 ] +Key: VAESENCLASTrm: [ 0.00 0.00 ] +Key: VAESENCLASTrr: [ 0.00 0.00 ] +Key: VAESENCYrm: [ 0.00 0.00 ] +Key: VAESENCYrr: [ 0.00 0.00 ] +Key: VAESENCZ: [ 0.00 0.00 ] +Key: VAESENCZrm: [ 0.00 0.00 ] +Key: VAESENCZrr: [ 0.00 0.00 ] +Key: VAESENCrm: [ 0.00 0.00 ] +Key: VAESENCrr: [ 0.00 0.00 ] +Key: VAESIMCrm: [ 0.00 0.00 ] +Key: VAESIMCrr: [ 0.00 0.00 ] +Key: VAESKEYGENASSISTrmi: [ 0.00 0.00 ] +Key: VAESKEYGENASSISTrri: [ 0.00 0.00 ] +Key: VALIGNDZ: [ 0.00 0.00 ] +Key: VALIGNDZrmbi: [ 0.00 0.00 ] +Key: VALIGNDZrmbik: [ 0.00 0.00 ] +Key: VALIGNDZrmbikz: [ 0.00 0.00 ] +Key: VALIGNDZrmi: [ 0.00 0.00 ] +Key: VALIGNDZrmik: [ 0.00 0.00 ] +Key: VALIGNDZrmikz: [ 0.00 0.00 ] +Key: VALIGNDZrri: [ 0.00 0.00 ] +Key: VALIGNDZrrik: [ 0.00 0.00 ] +Key: VALIGNDZrrikz: [ 0.00 0.00 ] +Key: VALIGNQZ: [ 0.00 0.00 ] +Key: VALIGNQZrmbi: [ 0.00 0.00 ] +Key: VALIGNQZrmbik: [ 0.00 0.00 ] +Key: VALIGNQZrmbikz: [ 0.00 0.00 ] +Key: VALIGNQZrmi: [ 0.00 0.00 ] +Key: VALIGNQZrmik: [ 0.00 0.00 ] +Key: VALIGNQZrmikz: [ 0.00 0.00 ] +Key: VALIGNQZrri: [ 0.00 0.00 ] +Key: VALIGNQZrrik: [ 0.00 0.00 ] +Key: VALIGNQZrrikz: [ 0.00 0.00 ] +Key: VANDNPDYrm: [ 0.00 0.00 ] +Key: VANDNPDYrr: [ 0.00 0.00 ] +Key: VANDNPDZ: [ 0.00 0.00 ] +Key: VANDNPDZrm: [ 0.00 0.00 ] +Key: VANDNPDZrmb: [ 0.00 0.00 ] +Key: VANDNPDZrmbk: [ 0.00 0.00 ] +Key: VANDNPDZrmbkz: [ 0.00 0.00 ] +Key: VANDNPDZrmk: [ 0.00 0.00 ] +Key: VANDNPDZrmkz: [ 0.00 0.00 ] +Key: VANDNPDZrr: [ 0.00 0.00 ] +Key: VANDNPDZrrk: [ 0.00 0.00 ] +Key: VANDNPDZrrkz: [ 0.00 0.00 ] +Key: VANDNPDrm: [ 0.00 0.00 ] +Key: VANDNPDrr: [ 0.00 0.00 ] +Key: VANDNPSYrm: [ 0.00 0.00 ] +Key: VANDNPSYrr: [ 0.00 0.00 ] +Key: VANDNPSZ: [ 0.00 0.00 ] +Key: VANDNPSZrm: [ 0.00 0.00 ] +Key: VANDNPSZrmb: [ 0.00 0.00 ] +Key: VANDNPSZrmbk: [ 0.00 0.00 ] +Key: VANDNPSZrmbkz: [ 0.00 0.00 ] +Key: VANDNPSZrmk: [ 0.00 0.00 ] +Key: VANDNPSZrmkz: [ 0.00 0.00 ] +Key: VANDNPSZrr: [ 0.00 0.00 ] +Key: VANDNPSZrrk: [ 0.00 0.00 ] +Key: VANDNPSZrrkz: [ 0.00 0.00 ] +Key: VANDNPSrm: [ 0.00 0.00 ] +Key: VANDNPSrr: [ 0.00 0.00 ] +Key: VANDPDYrm: [ 0.00 0.00 ] +Key: VANDPDYrr: [ 0.00 0.00 ] +Key: VANDPDZ: [ 0.00 0.00 ] +Key: VANDPDZrm: [ 0.00 0.00 ] +Key: VANDPDZrmb: [ 0.00 0.00 ] +Key: VANDPDZrmbk: [ 0.00 0.00 ] +Key: VANDPDZrmbkz: [ 0.00 0.00 ] +Key: VANDPDZrmk: [ 0.00 0.00 ] +Key: VANDPDZrmkz: [ 0.00 0.00 ] +Key: VANDPDZrr: [ 0.00 0.00 ] +Key: VANDPDZrrk: [ 0.00 0.00 ] +Key: VANDPDZrrkz: [ 0.00 0.00 ] +Key: VANDPDrm: [ 0.00 0.00 ] +Key: VANDPDrr: [ 0.00 0.00 ] +Key: VANDPSYrm: [ 0.00 0.00 ] +Key: VANDPSYrr: [ 0.00 0.00 ] +Key: VANDPSZ: [ 0.00 0.00 ] +Key: VANDPSZrm: [ 0.00 0.00 ] +Key: VANDPSZrmb: [ 0.00 0.00 ] +Key: VANDPSZrmbk: [ 0.00 0.00 ] +Key: VANDPSZrmbkz: [ 0.00 0.00 ] +Key: VANDPSZrmk: [ 0.00 0.00 ] +Key: VANDPSZrmkz: [ 0.00 0.00 ] +Key: VANDPSZrr: [ 0.00 0.00 ] +Key: VANDPSZrrk: [ 0.00 0.00 ] +Key: VANDPSZrrkz: [ 0.00 0.00 ] +Key: VANDPSrm: [ 0.00 0.00 ] +Key: VANDPSrr: [ 0.00 0.00 ] +Key: VASTART_SAVE_XMM_REGS: [ 0.00 0.00 ] +Key: VBCSTNEBF: [ 0.00 0.00 ] +Key: VBCSTNESH: [ 0.00 0.00 ] +Key: VBLENDMPDZ: [ 0.00 0.00 ] +Key: VBLENDMPDZrm: [ 0.00 0.00 ] +Key: VBLENDMPDZrmb: [ 0.00 0.00 ] +Key: VBLENDMPDZrmbk: [ 0.00 0.00 ] +Key: VBLENDMPDZrmbkz: [ 0.00 0.00 ] +Key: VBLENDMPDZrmk: [ 0.00 0.00 ] +Key: VBLENDMPDZrmkz: [ 0.00 0.00 ] +Key: VBLENDMPDZrr: [ 0.00 0.00 ] +Key: VBLENDMPDZrrk: [ 0.00 0.00 ] +Key: VBLENDMPDZrrkz: [ 0.00 0.00 ] +Key: VBLENDMPSZ: [ 0.00 0.00 ] +Key: VBLENDMPSZrm: [ 0.00 0.00 ] +Key: VBLENDMPSZrmb: [ 0.00 0.00 ] +Key: VBLENDMPSZrmbk: [ 0.00 0.00 ] +Key: VBLENDMPSZrmbkz: [ 0.00 0.00 ] +Key: VBLENDMPSZrmk: [ 0.00 0.00 ] +Key: VBLENDMPSZrmkz: [ 0.00 0.00 ] +Key: VBLENDMPSZrr: [ 0.00 0.00 ] +Key: VBLENDMPSZrrk: [ 0.00 0.00 ] +Key: VBLENDMPSZrrkz: [ 0.00 0.00 ] +Key: VBLENDPDYrmi: [ 0.00 0.00 ] +Key: VBLENDPDYrri: [ 0.00 0.00 ] +Key: VBLENDPDrmi: [ 0.00 0.00 ] +Key: VBLENDPDrri: [ 0.00 0.00 ] +Key: VBLENDPSYrmi: [ 0.00 0.00 ] +Key: VBLENDPSYrri: [ 0.00 0.00 ] +Key: VBLENDPSrmi: [ 0.00 0.00 ] +Key: VBLENDPSrri: [ 0.00 0.00 ] +Key: VBLENDVPDYrmr: [ 0.00 0.00 ] +Key: VBLENDVPDYrrr: [ 0.00 0.00 ] +Key: VBLENDVPDrmr: [ 0.00 0.00 ] +Key: VBLENDVPDrrr: [ 0.00 0.00 ] +Key: VBLENDVPSYrmr: [ 0.00 0.00 ] +Key: VBLENDVPSYrrr: [ 0.00 0.00 ] +Key: VBLENDVPSrmr: [ 0.00 0.00 ] +Key: VBLENDVPSrrr: [ 0.00 0.00 ] +Key: VBROADCASTF: [ 0.00 0.00 ] +Key: VBROADCASTI: [ 0.00 0.00 ] +Key: VBROADCASTSDYrm: [ 0.00 0.00 ] +Key: VBROADCASTSDYrr: [ 0.00 0.00 ] +Key: VBROADCASTSDZ: [ 0.00 0.00 ] +Key: VBROADCASTSDZrm: [ 0.00 0.00 ] +Key: VBROADCASTSDZrmk: [ 0.00 0.00 ] +Key: VBROADCASTSDZrmkz: [ 0.00 0.00 ] +Key: VBROADCASTSDZrr: [ 0.00 0.00 ] +Key: VBROADCASTSDZrrk: [ 0.00 0.00 ] +Key: VBROADCASTSDZrrkz: [ 0.00 0.00 ] +Key: VBROADCASTSSYrm: [ 0.00 0.00 ] +Key: VBROADCASTSSYrr: [ 0.00 0.00 ] +Key: VBROADCASTSSZ: [ 0.00 0.00 ] +Key: VBROADCASTSSZrm: [ 0.00 0.00 ] +Key: VBROADCASTSSZrmk: [ 0.00 0.00 ] +Key: VBROADCASTSSZrmkz: [ 0.00 0.00 ] +Key: VBROADCASTSSZrr: [ 0.00 0.00 ] +Key: VBROADCASTSSZrrk: [ 0.00 0.00 ] +Key: VBROADCASTSSZrrkz: [ 0.00 0.00 ] +Key: VBROADCASTSSrm: [ 0.00 0.00 ] +Key: VBROADCASTSSrr: [ 0.00 0.00 ] +Key: VCMPBF: [ 0.00 0.00 ] +Key: VCMPPDYrmi: [ 0.00 0.00 ] +Key: VCMPPDYrri: [ 0.00 0.00 ] +Key: VCMPPDZ: [ 0.00 0.00 ] +Key: VCMPPDZrmbi: [ 0.00 0.00 ] +Key: VCMPPDZrmbik: [ 0.00 0.00 ] +Key: VCMPPDZrmi: [ 0.00 0.00 ] +Key: VCMPPDZrmik: [ 0.00 0.00 ] +Key: VCMPPDZrri: [ 0.00 0.00 ] +Key: VCMPPDZrrib: [ 0.00 0.00 ] +Key: VCMPPDZrribk: [ 0.00 0.00 ] +Key: VCMPPDZrrik: [ 0.00 0.00 ] +Key: VCMPPDrmi: [ 0.00 0.00 ] +Key: VCMPPDrri: [ 0.00 0.00 ] +Key: VCMPPHZ: [ 0.00 0.00 ] +Key: VCMPPHZrmbi: [ 0.00 0.00 ] +Key: VCMPPHZrmbik: [ 0.00 0.00 ] +Key: VCMPPHZrmi: [ 0.00 0.00 ] +Key: VCMPPHZrmik: [ 0.00 0.00 ] +Key: VCMPPHZrri: [ 0.00 0.00 ] +Key: VCMPPHZrrib: [ 0.00 0.00 ] +Key: VCMPPHZrribk: [ 0.00 0.00 ] +Key: VCMPPHZrrik: [ 0.00 0.00 ] +Key: VCMPPSYrmi: [ 0.00 0.00 ] +Key: VCMPPSYrri: [ 0.00 0.00 ] +Key: VCMPPSZ: [ 0.00 0.00 ] +Key: VCMPPSZrmbi: [ 0.00 0.00 ] +Key: VCMPPSZrmbik: [ 0.00 0.00 ] +Key: VCMPPSZrmi: [ 0.00 0.00 ] +Key: VCMPPSZrmik: [ 0.00 0.00 ] +Key: VCMPPSZrri: [ 0.00 0.00 ] +Key: VCMPPSZrrib: [ 0.00 0.00 ] +Key: VCMPPSZrribk: [ 0.00 0.00 ] +Key: VCMPPSZrrik: [ 0.00 0.00 ] +Key: VCMPPSrmi: [ 0.00 0.00 ] +Key: VCMPPSrri: [ 0.00 0.00 ] +Key: VCMPSDZrmi: [ 0.00 0.00 ] +Key: VCMPSDZrmi_Int: [ 0.00 0.00 ] +Key: VCMPSDZrmik_Int: [ 0.00 0.00 ] +Key: VCMPSDZrri: [ 0.00 0.00 ] +Key: VCMPSDZrri_Int: [ 0.00 0.00 ] +Key: VCMPSDZrrib_Int: [ 0.00 0.00 ] +Key: VCMPSDZrribk_Int: [ 0.00 0.00 ] +Key: VCMPSDZrrik_Int: [ 0.00 0.00 ] +Key: VCMPSDrmi: [ 0.00 0.00 ] +Key: VCMPSDrmi_Int: [ 0.00 0.00 ] +Key: VCMPSDrri: [ 0.00 0.00 ] +Key: VCMPSDrri_Int: [ 0.00 0.00 ] +Key: VCMPSHZrmi: [ 0.00 0.00 ] +Key: VCMPSHZrmi_Int: [ 0.00 0.00 ] +Key: VCMPSHZrmik_Int: [ 0.00 0.00 ] +Key: VCMPSHZrri: [ 0.00 0.00 ] +Key: VCMPSHZrri_Int: [ 0.00 0.00 ] +Key: VCMPSHZrrib_Int: [ 0.00 0.00 ] +Key: VCMPSHZrribk_Int: [ 0.00 0.00 ] +Key: VCMPSHZrrik_Int: [ 0.00 0.00 ] +Key: VCMPSSZrmi: [ 0.00 0.00 ] +Key: VCMPSSZrmi_Int: [ 0.00 0.00 ] +Key: VCMPSSZrmik_Int: [ 0.00 0.00 ] +Key: VCMPSSZrri: [ 0.00 0.00 ] +Key: VCMPSSZrri_Int: [ 0.00 0.00 ] +Key: VCMPSSZrrib_Int: [ 0.00 0.00 ] +Key: VCMPSSZrribk_Int: [ 0.00 0.00 ] +Key: VCMPSSZrrik_Int: [ 0.00 0.00 ] +Key: VCMPSSrmi: [ 0.00 0.00 ] +Key: VCMPSSrmi_Int: [ 0.00 0.00 ] +Key: VCMPSSrri: [ 0.00 0.00 ] +Key: VCMPSSrri_Int: [ 0.00 0.00 ] +Key: VCOMISBF: [ 0.00 0.00 ] +Key: VCOMISDZrm: [ 0.00 0.00 ] +Key: VCOMISDZrm_Int: [ 0.00 0.00 ] +Key: VCOMISDZrr: [ 0.00 0.00 ] +Key: VCOMISDZrr_Int: [ 0.00 0.00 ] +Key: VCOMISDZrrb: [ 0.00 0.00 ] +Key: VCOMISDrm: [ 0.00 0.00 ] +Key: VCOMISDrm_Int: [ 0.00 0.00 ] +Key: VCOMISDrr: [ 0.00 0.00 ] +Key: VCOMISDrr_Int: [ 0.00 0.00 ] +Key: VCOMISHZrm: [ 0.00 0.00 ] +Key: VCOMISHZrm_Int: [ 0.00 0.00 ] +Key: VCOMISHZrr: [ 0.00 0.00 ] +Key: VCOMISHZrr_Int: [ 0.00 0.00 ] +Key: VCOMISHZrrb: [ 0.00 0.00 ] +Key: VCOMISSZrm: [ 0.00 0.00 ] +Key: VCOMISSZrm_Int: [ 0.00 0.00 ] +Key: VCOMISSZrr: [ 0.00 0.00 ] +Key: VCOMISSZrr_Int: [ 0.00 0.00 ] +Key: VCOMISSZrrb: [ 0.00 0.00 ] +Key: VCOMISSrm: [ 0.00 0.00 ] +Key: VCOMISSrm_Int: [ 0.00 0.00 ] +Key: VCOMISSrr: [ 0.00 0.00 ] +Key: VCOMISSrr_Int: [ 0.00 0.00 ] +Key: VCOMPRESSPDZ: [ 0.00 0.00 ] +Key: VCOMPRESSPDZmr: [ 0.00 0.00 ] +Key: VCOMPRESSPDZmrk: [ 0.00 0.00 ] +Key: VCOMPRESSPDZrr: [ 0.00 0.00 ] +Key: VCOMPRESSPDZrrk: [ 0.00 0.00 ] +Key: VCOMPRESSPDZrrkz: [ 0.00 0.00 ] +Key: VCOMPRESSPSZ: [ 0.00 0.00 ] +Key: VCOMPRESSPSZmr: [ 0.00 0.00 ] +Key: VCOMPRESSPSZmrk: [ 0.00 0.00 ] +Key: VCOMPRESSPSZrr: [ 0.00 0.00 ] +Key: VCOMPRESSPSZrrk: [ 0.00 0.00 ] +Key: VCOMPRESSPSZrrkz: [ 0.00 0.00 ] +Key: VCOMXSDZrm_Int: [ 0.00 0.00 ] +Key: VCOMXSDZrr_Int: [ 0.00 0.00 ] +Key: VCOMXSDZrrb_Int: [ 0.00 0.00 ] +Key: VCOMXSHZrm_Int: [ 0.00 0.00 ] +Key: VCOMXSHZrr_Int: [ 0.00 0.00 ] +Key: VCOMXSHZrrb_Int: [ 0.00 0.00 ] +Key: VCOMXSSZrm_Int: [ 0.00 0.00 ] +Key: VCOMXSSZrr_Int: [ 0.00 0.00 ] +Key: VCOMXSSZrrb_Int: [ 0.00 0.00 ] +Key: VCVT: [ 0.00 0.00 ] +Key: VCVTBF: [ 0.00 0.00 ] +Key: VCVTBIASPH: [ 0.00 0.00 ] +Key: VCVTDQ: [ 0.00 0.00 ] +Key: VCVTHF: [ 0.00 0.00 ] +Key: VCVTNE: [ 0.00 0.00 ] +Key: VCVTNEEBF: [ 0.00 0.00 ] +Key: VCVTNEEPH: [ 0.00 0.00 ] +Key: VCVTNEOBF: [ 0.00 0.00 ] +Key: VCVTNEOPH: [ 0.00 0.00 ] +Key: VCVTNEPS: [ 0.00 0.00 ] +Key: VCVTPD: [ 0.00 0.00 ] +Key: VCVTPH: [ 0.00 0.00 ] +Key: VCVTPS: [ 0.00 0.00 ] +Key: VCVTQQ: [ 0.00 0.00 ] +Key: VCVTSD: [ 0.00 0.00 ] +Key: VCVTSH: [ 0.00 0.00 ] +Key: VCVTSI: [ 0.00 0.00 ] +Key: VCVTSS: [ 0.00 0.00 ] +Key: VCVTTBF: [ 0.00 0.00 ] +Key: VCVTTPD: [ 0.00 0.00 ] +Key: VCVTTPH: [ 0.00 0.00 ] +Key: VCVTTPS: [ 0.00 0.00 ] +Key: VCVTTSD: [ 0.00 0.00 ] +Key: VCVTTSH: [ 0.00 0.00 ] +Key: VCVTTSS: [ 0.00 0.00 ] +Key: VCVTUDQ: [ 0.00 0.00 ] +Key: VCVTUQQ: [ 0.00 0.00 ] +Key: VCVTUSI: [ 0.00 0.00 ] +Key: VCVTUW: [ 0.00 0.00 ] +Key: VCVTW: [ 0.00 0.00 ] +Key: VDBPSADBWZ: [ 0.00 0.00 ] +Key: VDBPSADBWZrmi: [ 0.00 0.00 ] +Key: VDBPSADBWZrmik: [ 0.00 0.00 ] +Key: VDBPSADBWZrmikz: [ 0.00 0.00 ] +Key: VDBPSADBWZrri: [ 0.00 0.00 ] +Key: VDBPSADBWZrrik: [ 0.00 0.00 ] +Key: VDBPSADBWZrrikz: [ 0.00 0.00 ] +Key: VDIVBF: [ 0.00 0.00 ] +Key: VDIVPDYrm: [ 0.00 0.00 ] +Key: VDIVPDYrr: [ 0.00 0.00 ] +Key: VDIVPDZ: [ 0.00 0.00 ] +Key: VDIVPDZrm: [ 0.00 0.00 ] +Key: VDIVPDZrmb: [ 0.00 0.00 ] +Key: VDIVPDZrmbk: [ 0.00 0.00 ] +Key: VDIVPDZrmbkz: [ 0.00 0.00 ] +Key: VDIVPDZrmk: [ 0.00 0.00 ] +Key: VDIVPDZrmkz: [ 0.00 0.00 ] +Key: VDIVPDZrr: [ 0.00 0.00 ] +Key: VDIVPDZrrb: [ 0.00 0.00 ] +Key: VDIVPDZrrbk: [ 0.00 0.00 ] +Key: VDIVPDZrrbkz: [ 0.00 0.00 ] +Key: VDIVPDZrrk: [ 0.00 0.00 ] +Key: VDIVPDZrrkz: [ 0.00 0.00 ] +Key: VDIVPDrm: [ 0.00 0.00 ] +Key: VDIVPDrr: [ 0.00 0.00 ] +Key: VDIVPHZ: [ 0.00 0.00 ] +Key: VDIVPHZrm: [ 0.00 0.00 ] +Key: VDIVPHZrmb: [ 0.00 0.00 ] +Key: VDIVPHZrmbk: [ 0.00 0.00 ] +Key: VDIVPHZrmbkz: [ 0.00 0.00 ] +Key: VDIVPHZrmk: [ 0.00 0.00 ] +Key: VDIVPHZrmkz: [ 0.00 0.00 ] +Key: VDIVPHZrr: [ 0.00 0.00 ] +Key: VDIVPHZrrb: [ 0.00 0.00 ] +Key: VDIVPHZrrbk: [ 0.00 0.00 ] +Key: VDIVPHZrrbkz: [ 0.00 0.00 ] +Key: VDIVPHZrrk: [ 0.00 0.00 ] +Key: VDIVPHZrrkz: [ 0.00 0.00 ] +Key: VDIVPSYrm: [ 0.00 0.00 ] +Key: VDIVPSYrr: [ 0.00 0.00 ] +Key: VDIVPSZ: [ 0.00 0.00 ] +Key: VDIVPSZrm: [ 0.00 0.00 ] +Key: VDIVPSZrmb: [ 0.00 0.00 ] +Key: VDIVPSZrmbk: [ 0.00 0.00 ] +Key: VDIVPSZrmbkz: [ 0.00 0.00 ] +Key: VDIVPSZrmk: [ 0.00 0.00 ] +Key: VDIVPSZrmkz: [ 0.00 0.00 ] +Key: VDIVPSZrr: [ 0.00 0.00 ] +Key: VDIVPSZrrb: [ 0.00 0.00 ] +Key: VDIVPSZrrbk: [ 0.00 0.00 ] +Key: VDIVPSZrrbkz: [ 0.00 0.00 ] +Key: VDIVPSZrrk: [ 0.00 0.00 ] +Key: VDIVPSZrrkz: [ 0.00 0.00 ] +Key: VDIVPSrm: [ 0.00 0.00 ] +Key: VDIVPSrr: [ 0.00 0.00 ] +Key: VDIVSDZrm: [ 0.00 0.00 ] +Key: VDIVSDZrm_Int: [ 0.00 0.00 ] +Key: VDIVSDZrmk_Int: [ 0.00 0.00 ] +Key: VDIVSDZrmkz_Int: [ 0.00 0.00 ] +Key: VDIVSDZrr: [ 0.00 0.00 ] +Key: VDIVSDZrr_Int: [ 0.00 0.00 ] +Key: VDIVSDZrrb_Int: [ 0.00 0.00 ] +Key: VDIVSDZrrbk_Int: [ 0.00 0.00 ] +Key: VDIVSDZrrbkz_Int: [ 0.00 0.00 ] +Key: VDIVSDZrrk_Int: [ 0.00 0.00 ] +Key: VDIVSDZrrkz_Int: [ 0.00 0.00 ] +Key: VDIVSDrm: [ 0.00 0.00 ] +Key: VDIVSDrm_Int: [ 0.00 0.00 ] +Key: VDIVSDrr: [ 0.00 0.00 ] +Key: VDIVSDrr_Int: [ 0.00 0.00 ] +Key: VDIVSHZrm: [ 0.00 0.00 ] +Key: VDIVSHZrm_Int: [ 0.00 0.00 ] +Key: VDIVSHZrmk_Int: [ 0.00 0.00 ] +Key: VDIVSHZrmkz_Int: [ 0.00 0.00 ] +Key: VDIVSHZrr: [ 0.00 0.00 ] +Key: VDIVSHZrr_Int: [ 0.00 0.00 ] +Key: VDIVSHZrrb_Int: [ 0.00 0.00 ] +Key: VDIVSHZrrbk_Int: [ 0.00 0.00 ] +Key: VDIVSHZrrbkz_Int: [ 0.00 0.00 ] +Key: VDIVSHZrrk_Int: [ 0.00 0.00 ] +Key: VDIVSHZrrkz_Int: [ 0.00 0.00 ] +Key: VDIVSSZrm: [ 0.00 0.00 ] +Key: VDIVSSZrm_Int: [ 0.00 0.00 ] +Key: VDIVSSZrmk_Int: [ 0.00 0.00 ] +Key: VDIVSSZrmkz_Int: [ 0.00 0.00 ] +Key: VDIVSSZrr: [ 0.00 0.00 ] +Key: VDIVSSZrr_Int: [ 0.00 0.00 ] +Key: VDIVSSZrrb_Int: [ 0.00 0.00 ] +Key: VDIVSSZrrbk_Int: [ 0.00 0.00 ] +Key: VDIVSSZrrbkz_Int: [ 0.00 0.00 ] +Key: VDIVSSZrrk_Int: [ 0.00 0.00 ] +Key: VDIVSSZrrkz_Int: [ 0.00 0.00 ] +Key: VDIVSSrm: [ 0.00 0.00 ] +Key: VDIVSSrm_Int: [ 0.00 0.00 ] +Key: VDIVSSrr: [ 0.00 0.00 ] +Key: VDIVSSrr_Int: [ 0.00 0.00 ] +Key: VDPBF: [ 0.00 0.00 ] +Key: VDPPDrmi: [ 0.00 0.00 ] +Key: VDPPDrri: [ 0.00 0.00 ] +Key: VDPPHPSZ: [ 0.00 0.00 ] +Key: VDPPHPSZm: [ 0.00 0.00 ] +Key: VDPPHPSZmb: [ 0.00 0.00 ] +Key: VDPPHPSZmbk: [ 0.00 0.00 ] +Key: VDPPHPSZmbkz: [ 0.00 0.00 ] +Key: VDPPHPSZmk: [ 0.00 0.00 ] +Key: VDPPHPSZmkz: [ 0.00 0.00 ] +Key: VDPPHPSZr: [ 0.00 0.00 ] +Key: VDPPHPSZrk: [ 0.00 0.00 ] +Key: VDPPHPSZrkz: [ 0.00 0.00 ] +Key: VDPPSYrmi: [ 0.00 0.00 ] +Key: VDPPSYrri: [ 0.00 0.00 ] +Key: VDPPSrmi: [ 0.00 0.00 ] +Key: VDPPSrri: [ 0.00 0.00 ] +Key: VERRm: [ 0.00 0.00 ] +Key: VERRr: [ 0.00 0.00 ] +Key: VERWm: [ 0.00 0.00 ] +Key: VERWr: [ 0.00 0.00 ] +Key: VEXP: [ 0.00 0.00 ] +Key: VEXPANDPDZ: [ 0.00 0.00 ] +Key: VEXPANDPDZrm: [ 0.00 0.00 ] +Key: VEXPANDPDZrmk: [ 0.00 0.00 ] +Key: VEXPANDPDZrmkz: [ 0.00 0.00 ] +Key: VEXPANDPDZrr: [ 0.00 0.00 ] +Key: VEXPANDPDZrrk: [ 0.00 0.00 ] +Key: VEXPANDPDZrrkz: [ 0.00 0.00 ] +Key: VEXPANDPSZ: [ 0.00 0.00 ] +Key: VEXPANDPSZrm: [ 0.00 0.00 ] +Key: VEXPANDPSZrmk: [ 0.00 0.00 ] +Key: VEXPANDPSZrmkz: [ 0.00 0.00 ] +Key: VEXPANDPSZrr: [ 0.00 0.00 ] +Key: VEXPANDPSZrrk: [ 0.00 0.00 ] +Key: VEXPANDPSZrrkz: [ 0.00 0.00 ] +Key: VEXTRACTF: [ 0.00 0.00 ] +Key: VEXTRACTI: [ 0.00 0.00 ] +Key: VEXTRACTPSZmri: [ 0.00 0.00 ] +Key: VEXTRACTPSZrri: [ 0.00 0.00 ] +Key: VEXTRACTPSmri: [ 0.00 0.00 ] +Key: VEXTRACTPSrri: [ 0.00 0.00 ] +Key: VFCMADDCPHZ: [ 0.00 0.00 ] +Key: VFCMADDCPHZm: [ 0.00 0.00 ] +Key: VFCMADDCPHZmb: [ 0.00 0.00 ] +Key: VFCMADDCPHZmbk: [ 0.00 0.00 ] +Key: VFCMADDCPHZmbkz: [ 0.00 0.00 ] +Key: VFCMADDCPHZmk: [ 0.00 0.00 ] +Key: VFCMADDCPHZmkz: [ 0.00 0.00 ] +Key: VFCMADDCPHZr: [ 0.00 0.00 ] +Key: VFCMADDCPHZrb: [ 0.00 0.00 ] +Key: VFCMADDCPHZrbk: [ 0.00 0.00 ] +Key: VFCMADDCPHZrbkz: [ 0.00 0.00 ] +Key: VFCMADDCPHZrk: [ 0.00 0.00 ] +Key: VFCMADDCPHZrkz: [ 0.00 0.00 ] +Key: VFCMADDCSHZm: [ 0.00 0.00 ] +Key: VFCMADDCSHZmk: [ 0.00 0.00 ] +Key: VFCMADDCSHZmkz: [ 0.00 0.00 ] +Key: VFCMADDCSHZr: [ 0.00 0.00 ] +Key: VFCMADDCSHZrb: [ 0.00 0.00 ] +Key: VFCMADDCSHZrbk: [ 0.00 0.00 ] +Key: VFCMADDCSHZrbkz: [ 0.00 0.00 ] +Key: VFCMADDCSHZrk: [ 0.00 0.00 ] +Key: VFCMADDCSHZrkz: [ 0.00 0.00 ] +Key: VFCMULCPHZ: [ 0.00 0.00 ] +Key: VFCMULCPHZrm: [ 0.00 0.00 ] +Key: VFCMULCPHZrmb: [ 0.00 0.00 ] +Key: VFCMULCPHZrmbk: [ 0.00 0.00 ] +Key: VFCMULCPHZrmbkz: [ 0.00 0.00 ] +Key: VFCMULCPHZrmk: [ 0.00 0.00 ] +Key: VFCMULCPHZrmkz: [ 0.00 0.00 ] +Key: VFCMULCPHZrr: [ 0.00 0.00 ] +Key: VFCMULCPHZrrb: [ 0.00 0.00 ] +Key: VFCMULCPHZrrbk: [ 0.00 0.00 ] +Key: VFCMULCPHZrrbkz: [ 0.00 0.00 ] +Key: VFCMULCPHZrrk: [ 0.00 0.00 ] +Key: VFCMULCPHZrrkz: [ 0.00 0.00 ] +Key: VFCMULCSHZrm: [ 0.00 0.00 ] +Key: VFCMULCSHZrmk: [ 0.00 0.00 ] +Key: VFCMULCSHZrmkz: [ 0.00 0.00 ] +Key: VFCMULCSHZrr: [ 0.00 0.00 ] +Key: VFCMULCSHZrrb: [ 0.00 0.00 ] +Key: VFCMULCSHZrrbk: [ 0.00 0.00 ] +Key: VFCMULCSHZrrbkz: [ 0.00 0.00 ] +Key: VFCMULCSHZrrk: [ 0.00 0.00 ] +Key: VFCMULCSHZrrkz: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZ: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmbi: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmbik: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmbikz: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmi: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmik: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmikz: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrri: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrrib: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrribk: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrribkz: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrrik: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrrikz: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZ: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmbi: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmbik: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmbikz: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmi: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmik: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmikz: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrri: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrrib: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrribk: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrribkz: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrrik: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrrikz: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrmi: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrmik: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrmikz: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrri: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrrib: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrribk: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrribkz: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrrik: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrrikz: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrmi: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrmik: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrmikz: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrri: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrrib: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrribk: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrribkz: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrrik: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrrikz: [ 0.00 0.00 ] +Key: VFMADD: [ 0.00 0.00 ] +Key: VFMADDCPHZ: [ 0.00 0.00 ] +Key: VFMADDCPHZm: [ 0.00 0.00 ] +Key: VFMADDCPHZmb: [ 0.00 0.00 ] +Key: VFMADDCPHZmbk: [ 0.00 0.00 ] +Key: VFMADDCPHZmbkz: [ 0.00 0.00 ] +Key: VFMADDCPHZmk: [ 0.00 0.00 ] +Key: VFMADDCPHZmkz: [ 0.00 0.00 ] +Key: VFMADDCPHZr: [ 0.00 0.00 ] +Key: VFMADDCPHZrb: [ 0.00 0.00 ] +Key: VFMADDCPHZrbk: [ 0.00 0.00 ] +Key: VFMADDCPHZrbkz: [ 0.00 0.00 ] +Key: VFMADDCPHZrk: [ 0.00 0.00 ] +Key: VFMADDCPHZrkz: [ 0.00 0.00 ] +Key: VFMADDCSHZm: [ 0.00 0.00 ] +Key: VFMADDCSHZmk: [ 0.00 0.00 ] +Key: VFMADDCSHZmkz: [ 0.00 0.00 ] +Key: VFMADDCSHZr: [ 0.00 0.00 ] +Key: VFMADDCSHZrb: [ 0.00 0.00 ] +Key: VFMADDCSHZrbk: [ 0.00 0.00 ] +Key: VFMADDCSHZrbkz: [ 0.00 0.00 ] +Key: VFMADDCSHZrk: [ 0.00 0.00 ] +Key: VFMADDCSHZrkz: [ 0.00 0.00 ] +Key: VFMADDPD: [ 0.00 0.00 ] +Key: VFMADDPS: [ 0.00 0.00 ] +Key: VFMADDSD: [ 0.00 0.00 ] +Key: VFMADDSS: [ 0.00 0.00 ] +Key: VFMADDSUB: [ 0.00 0.00 ] +Key: VFMADDSUBPD: [ 0.00 0.00 ] +Key: VFMADDSUBPS: [ 0.00 0.00 ] +Key: VFMSUB: [ 0.00 0.00 ] +Key: VFMSUBADD: [ 0.00 0.00 ] +Key: VFMSUBADDPD: [ 0.00 0.00 ] +Key: VFMSUBADDPS: [ 0.00 0.00 ] +Key: VFMSUBPD: [ 0.00 0.00 ] +Key: VFMSUBPS: [ 0.00 0.00 ] +Key: VFMSUBSD: [ 0.00 0.00 ] +Key: VFMSUBSS: [ 0.00 0.00 ] +Key: VFMULCPHZ: [ 0.00 0.00 ] +Key: VFMULCPHZrm: [ 0.00 0.00 ] +Key: VFMULCPHZrmb: [ 0.00 0.00 ] +Key: VFMULCPHZrmbk: [ 0.00 0.00 ] +Key: VFMULCPHZrmbkz: [ 0.00 0.00 ] +Key: VFMULCPHZrmk: [ 0.00 0.00 ] +Key: VFMULCPHZrmkz: [ 0.00 0.00 ] +Key: VFMULCPHZrr: [ 0.00 0.00 ] +Key: VFMULCPHZrrb: [ 0.00 0.00 ] +Key: VFMULCPHZrrbk: [ 0.00 0.00 ] +Key: VFMULCPHZrrbkz: [ 0.00 0.00 ] +Key: VFMULCPHZrrk: [ 0.00 0.00 ] +Key: VFMULCPHZrrkz: [ 0.00 0.00 ] +Key: VFMULCSHZrm: [ 0.00 0.00 ] +Key: VFMULCSHZrmk: [ 0.00 0.00 ] +Key: VFMULCSHZrmkz: [ 0.00 0.00 ] +Key: VFMULCSHZrr: [ 0.00 0.00 ] +Key: VFMULCSHZrrb: [ 0.00 0.00 ] +Key: VFMULCSHZrrbk: [ 0.00 0.00 ] +Key: VFMULCSHZrrbkz: [ 0.00 0.00 ] +Key: VFMULCSHZrrk: [ 0.00 0.00 ] +Key: VFMULCSHZrrkz: [ 0.00 0.00 ] +Key: VFNMADD: [ 0.00 0.00 ] +Key: VFNMADDPD: [ 0.00 0.00 ] +Key: VFNMADDPS: [ 0.00 0.00 ] +Key: VFNMADDSD: [ 0.00 0.00 ] +Key: VFNMADDSS: [ 0.00 0.00 ] +Key: VFNMSUB: [ 0.00 0.00 ] +Key: VFNMSUBPD: [ 0.00 0.00 ] +Key: VFNMSUBPS: [ 0.00 0.00 ] +Key: VFNMSUBSD: [ 0.00 0.00 ] +Key: VFNMSUBSS: [ 0.00 0.00 ] +Key: VFPCLASSBF: [ 0.00 0.00 ] +Key: VFPCLASSPDZ: [ 0.00 0.00 ] +Key: VFPCLASSPDZmbi: [ 0.00 0.00 ] +Key: VFPCLASSPDZmbik: [ 0.00 0.00 ] +Key: VFPCLASSPDZmi: [ 0.00 0.00 ] +Key: VFPCLASSPDZmik: [ 0.00 0.00 ] +Key: VFPCLASSPDZri: [ 0.00 0.00 ] +Key: VFPCLASSPDZrik: [ 0.00 0.00 ] +Key: VFPCLASSPHZ: [ 0.00 0.00 ] +Key: VFPCLASSPHZmbi: [ 0.00 0.00 ] +Key: VFPCLASSPHZmbik: [ 0.00 0.00 ] +Key: VFPCLASSPHZmi: [ 0.00 0.00 ] +Key: VFPCLASSPHZmik: [ 0.00 0.00 ] +Key: VFPCLASSPHZri: [ 0.00 0.00 ] +Key: VFPCLASSPHZrik: [ 0.00 0.00 ] +Key: VFPCLASSPSZ: [ 0.00 0.00 ] +Key: VFPCLASSPSZmbi: [ 0.00 0.00 ] +Key: VFPCLASSPSZmbik: [ 0.00 0.00 ] +Key: VFPCLASSPSZmi: [ 0.00 0.00 ] +Key: VFPCLASSPSZmik: [ 0.00 0.00 ] +Key: VFPCLASSPSZri: [ 0.00 0.00 ] +Key: VFPCLASSPSZrik: [ 0.00 0.00 ] +Key: VFPCLASSSDZmi: [ 0.00 0.00 ] +Key: VFPCLASSSDZmik: [ 0.00 0.00 ] +Key: VFPCLASSSDZri: [ 0.00 0.00 ] +Key: VFPCLASSSDZrik: [ 0.00 0.00 ] +Key: VFPCLASSSHZmi: [ 0.00 0.00 ] +Key: VFPCLASSSHZmik: [ 0.00 0.00 ] +Key: VFPCLASSSHZri: [ 0.00 0.00 ] +Key: VFPCLASSSHZrik: [ 0.00 0.00 ] +Key: VFPCLASSSSZmi: [ 0.00 0.00 ] +Key: VFPCLASSSSZmik: [ 0.00 0.00 ] +Key: VFPCLASSSSZri: [ 0.00 0.00 ] +Key: VFPCLASSSSZrik: [ 0.00 0.00 ] +Key: VFRCZPDYrm: [ 0.00 0.00 ] +Key: VFRCZPDYrr: [ 0.00 0.00 ] +Key: VFRCZPDrm: [ 0.00 0.00 ] +Key: VFRCZPDrr: [ 0.00 0.00 ] +Key: VFRCZPSYrm: [ 0.00 0.00 ] +Key: VFRCZPSYrr: [ 0.00 0.00 ] +Key: VFRCZPSrm: [ 0.00 0.00 ] +Key: VFRCZPSrr: [ 0.00 0.00 ] +Key: VFRCZSDrm: [ 0.00 0.00 ] +Key: VFRCZSDrr: [ 0.00 0.00 ] +Key: VFRCZSSrm: [ 0.00 0.00 ] +Key: VFRCZSSrr: [ 0.00 0.00 ] +Key: VGATHERDPDYrm: [ 0.00 0.00 ] +Key: VGATHERDPDZ: [ 0.00 0.00 ] +Key: VGATHERDPDZrm: [ 0.00 0.00 ] +Key: VGATHERDPDrm: [ 0.00 0.00 ] +Key: VGATHERDPSYrm: [ 0.00 0.00 ] +Key: VGATHERDPSZ: [ 0.00 0.00 ] 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VGETEXPPHZmbkz: [ 0.00 0.00 ] +Key: VGETEXPPHZmk: [ 0.00 0.00 ] +Key: VGETEXPPHZmkz: [ 0.00 0.00 ] +Key: VGETEXPPHZr: [ 0.00 0.00 ] +Key: VGETEXPPHZrb: [ 0.00 0.00 ] +Key: VGETEXPPHZrbk: [ 0.00 0.00 ] +Key: VGETEXPPHZrbkz: [ 0.00 0.00 ] +Key: VGETEXPPHZrk: [ 0.00 0.00 ] +Key: VGETEXPPHZrkz: [ 0.00 0.00 ] +Key: VGETEXPPSZ: [ 0.00 0.00 ] +Key: VGETEXPPSZm: [ 0.00 0.00 ] +Key: VGETEXPPSZmb: [ 0.00 0.00 ] +Key: VGETEXPPSZmbk: [ 0.00 0.00 ] +Key: VGETEXPPSZmbkz: [ 0.00 0.00 ] +Key: VGETEXPPSZmk: [ 0.00 0.00 ] +Key: VGETEXPPSZmkz: [ 0.00 0.00 ] +Key: VGETEXPPSZr: [ 0.00 0.00 ] +Key: VGETEXPPSZrb: [ 0.00 0.00 ] +Key: VGETEXPPSZrbk: [ 0.00 0.00 ] +Key: VGETEXPPSZrbkz: [ 0.00 0.00 ] +Key: VGETEXPPSZrk: [ 0.00 0.00 ] +Key: VGETEXPPSZrkz: [ 0.00 0.00 ] +Key: VGETEXPSDZm: [ 0.00 0.00 ] +Key: VGETEXPSDZmk: [ 0.00 0.00 ] +Key: VGETEXPSDZmkz: [ 0.00 0.00 ] +Key: VGETEXPSDZr: [ 0.00 0.00 ] +Key: VGETEXPSDZrb: [ 0.00 0.00 ] +Key: VGETEXPSDZrbk: [ 0.00 0.00 ] +Key: VGETEXPSDZrbkz: [ 0.00 0.00 ] +Key: VGETEXPSDZrk: [ 0.00 0.00 ] +Key: VGETEXPSDZrkz: [ 0.00 0.00 ] +Key: VGETEXPSHZm: [ 0.00 0.00 ] +Key: VGETEXPSHZmk: [ 0.00 0.00 ] +Key: VGETEXPSHZmkz: [ 0.00 0.00 ] +Key: VGETEXPSHZr: [ 0.00 0.00 ] +Key: VGETEXPSHZrb: [ 0.00 0.00 ] +Key: VGETEXPSHZrbk: [ 0.00 0.00 ] +Key: VGETEXPSHZrbkz: [ 0.00 0.00 ] +Key: VGETEXPSHZrk: [ 0.00 0.00 ] +Key: VGETEXPSHZrkz: [ 0.00 0.00 ] +Key: VGETEXPSSZm: [ 0.00 0.00 ] +Key: VGETEXPSSZmk: [ 0.00 0.00 ] +Key: VGETEXPSSZmkz: [ 0.00 0.00 ] +Key: VGETEXPSSZr: [ 0.00 0.00 ] +Key: VGETEXPSSZrb: [ 0.00 0.00 ] +Key: VGETEXPSSZrbk: [ 0.00 0.00 ] +Key: VGETEXPSSZrbkz: [ 0.00 0.00 ] +Key: VGETEXPSSZrk: [ 0.00 0.00 ] +Key: VGETEXPSSZrkz: [ 0.00 0.00 ] +Key: VGETMANTBF: [ 0.00 0.00 ] +Key: VGETMANTPDZ: [ 0.00 0.00 ] +Key: VGETMANTPDZrmbi: [ 0.00 0.00 ] +Key: VGETMANTPDZrmbik: [ 0.00 0.00 ] +Key: VGETMANTPDZrmbikz: [ 0.00 0.00 ] +Key: VGETMANTPDZrmi: [ 0.00 0.00 ] +Key: VGETMANTPDZrmik: [ 0.00 0.00 ] +Key: VGETMANTPDZrmikz: [ 0.00 0.00 ] +Key: VGETMANTPDZrri: [ 0.00 0.00 ] +Key: VGETMANTPDZrrib: [ 0.00 0.00 ] +Key: VGETMANTPDZrribk: [ 0.00 0.00 ] +Key: VGETMANTPDZrribkz: [ 0.00 0.00 ] +Key: VGETMANTPDZrrik: [ 0.00 0.00 ] +Key: VGETMANTPDZrrikz: [ 0.00 0.00 ] +Key: VGETMANTPHZ: [ 0.00 0.00 ] +Key: VGETMANTPHZrmbi: [ 0.00 0.00 ] +Key: VGETMANTPHZrmbik: [ 0.00 0.00 ] +Key: VGETMANTPHZrmbikz: [ 0.00 0.00 ] +Key: VGETMANTPHZrmi: [ 0.00 0.00 ] +Key: VGETMANTPHZrmik: [ 0.00 0.00 ] +Key: VGETMANTPHZrmikz: [ 0.00 0.00 ] +Key: VGETMANTPHZrri: [ 0.00 0.00 ] +Key: VGETMANTPHZrrib: [ 0.00 0.00 ] +Key: VGETMANTPHZrribk: [ 0.00 0.00 ] +Key: VGETMANTPHZrribkz: [ 0.00 0.00 ] +Key: VGETMANTPHZrrik: [ 0.00 0.00 ] +Key: VGETMANTPHZrrikz: [ 0.00 0.00 ] +Key: VGETMANTPSZ: [ 0.00 0.00 ] +Key: VGETMANTPSZrmbi: [ 0.00 0.00 ] +Key: VGETMANTPSZrmbik: [ 0.00 0.00 ] +Key: VGETMANTPSZrmbikz: [ 0.00 0.00 ] +Key: VGETMANTPSZrmi: [ 0.00 0.00 ] +Key: VGETMANTPSZrmik: [ 0.00 0.00 ] +Key: VGETMANTPSZrmikz: [ 0.00 0.00 ] +Key: VGETMANTPSZrri: [ 0.00 0.00 ] +Key: VGETMANTPSZrrib: [ 0.00 0.00 ] +Key: VGETMANTPSZrribk: [ 0.00 0.00 ] +Key: VGETMANTPSZrribkz: [ 0.00 0.00 ] +Key: VGETMANTPSZrrik: [ 0.00 0.00 ] +Key: VGETMANTPSZrrikz: [ 0.00 0.00 ] +Key: VGETMANTSDZrmi: [ 0.00 0.00 ] +Key: VGETMANTSDZrmik: [ 0.00 0.00 ] +Key: VGETMANTSDZrmikz: [ 0.00 0.00 ] +Key: VGETMANTSDZrri: [ 0.00 0.00 ] +Key: VGETMANTSDZrrib: [ 0.00 0.00 ] +Key: VGETMANTSDZrribk: [ 0.00 0.00 ] +Key: VGETMANTSDZrribkz: [ 0.00 0.00 ] +Key: VGETMANTSDZrrik: [ 0.00 0.00 ] +Key: VGETMANTSDZrrikz: [ 0.00 0.00 ] +Key: VGETMANTSHZrmi: [ 0.00 0.00 ] +Key: VGETMANTSHZrmik: [ 0.00 0.00 ] +Key: VGETMANTSHZrmikz: [ 0.00 0.00 ] +Key: VGETMANTSHZrri: [ 0.00 0.00 ] +Key: VGETMANTSHZrrib: [ 0.00 0.00 ] +Key: VGETMANTSHZrribk: [ 0.00 0.00 ] +Key: VGETMANTSHZrribkz: [ 0.00 0.00 ] +Key: VGETMANTSHZrrik: [ 0.00 0.00 ] +Key: VGETMANTSHZrrikz: [ 0.00 0.00 ] +Key: VGETMANTSSZrmi: [ 0.00 0.00 ] +Key: VGETMANTSSZrmik: [ 0.00 0.00 ] +Key: VGETMANTSSZrmikz: [ 0.00 0.00 ] +Key: VGETMANTSSZrri: [ 0.00 0.00 ] +Key: VGETMANTSSZrrib: [ 0.00 0.00 ] +Key: VGETMANTSSZrribk: [ 0.00 0.00 ] +Key: VGETMANTSSZrribkz: [ 0.00 0.00 ] +Key: VGETMANTSSZrrik: [ 0.00 0.00 ] +Key: VGETMANTSSZrrikz: [ 0.00 0.00 ] +Key: VGF: [ 0.00 0.00 ] +Key: VHADDPDYrm: [ 0.00 0.00 ] +Key: VHADDPDYrr: [ 0.00 0.00 ] +Key: VHADDPDrm: [ 0.00 0.00 ] +Key: VHADDPDrr: [ 0.00 0.00 ] +Key: VHADDPSYrm: [ 0.00 0.00 ] +Key: VHADDPSYrr: [ 0.00 0.00 ] +Key: VHADDPSrm: [ 0.00 0.00 ] +Key: VHADDPSrr: [ 0.00 0.00 ] +Key: VHSUBPDYrm: [ 0.00 0.00 ] +Key: VHSUBPDYrr: [ 0.00 0.00 ] +Key: VHSUBPDrm: [ 0.00 0.00 ] +Key: VHSUBPDrr: [ 0.00 0.00 ] +Key: VHSUBPSYrm: [ 0.00 0.00 ] +Key: VHSUBPSYrr: [ 0.00 0.00 ] +Key: VHSUBPSrm: [ 0.00 0.00 ] +Key: VHSUBPSrr: [ 0.00 0.00 ] +Key: VINSERTF: [ 0.00 0.00 ] +Key: VINSERTI: [ 0.00 0.00 ] +Key: VINSERTPSZrmi: [ 0.00 0.00 ] +Key: VINSERTPSZrri: [ 0.00 0.00 ] +Key: VINSERTPSrmi: [ 0.00 0.00 ] +Key: VINSERTPSrri: [ 0.00 0.00 ] +Key: VLDDQUYrm: [ 0.00 0.00 ] +Key: VLDDQUrm: [ 0.00 0.00 ] +Key: VLDMXCSR: [ 0.00 0.00 ] +Key: VMASKMOVDQU: [ 0.00 0.00 ] +Key: VMASKMOVPDYmr: [ 0.00 0.00 ] +Key: VMASKMOVPDYrm: [ 0.00 0.00 ] +Key: VMASKMOVPDmr: [ 0.00 0.00 ] +Key: VMASKMOVPDrm: [ 0.00 0.00 ] +Key: VMASKMOVPSYmr: [ 0.00 0.00 ] +Key: VMASKMOVPSYrm: [ 0.00 0.00 ] +Key: VMASKMOVPSmr: [ 0.00 0.00 ] +Key: VMASKMOVPSrm: [ 0.00 0.00 ] +Key: VMAXBF: [ 0.00 0.00 ] +Key: VMAXCPDYrm: [ 0.00 0.00 ] +Key: VMAXCPDYrr: [ 0.00 0.00 ] +Key: VMAXCPDZ: [ 0.00 0.00 ] +Key: VMAXCPDZrm: [ 0.00 0.00 ] +Key: VMAXCPDZrmb: [ 0.00 0.00 ] +Key: VMAXCPDZrmbk: [ 0.00 0.00 ] +Key: VMAXCPDZrmbkz: [ 0.00 0.00 ] +Key: VMAXCPDZrmk: [ 0.00 0.00 ] +Key: VMAXCPDZrmkz: [ 0.00 0.00 ] +Key: VMAXCPDZrr: [ 0.00 0.00 ] +Key: VMAXCPDZrrk: [ 0.00 0.00 ] +Key: VMAXCPDZrrkz: [ 0.00 0.00 ] +Key: VMAXCPDrm: [ 0.00 0.00 ] +Key: VMAXCPDrr: [ 0.00 0.00 ] +Key: VMAXCPHZ: [ 0.00 0.00 ] +Key: VMAXCPHZrm: [ 0.00 0.00 ] +Key: VMAXCPHZrmb: [ 0.00 0.00 ] +Key: VMAXCPHZrmbk: [ 0.00 0.00 ] +Key: VMAXCPHZrmbkz: [ 0.00 0.00 ] +Key: VMAXCPHZrmk: [ 0.00 0.00 ] +Key: VMAXCPHZrmkz: [ 0.00 0.00 ] +Key: VMAXCPHZrr: [ 0.00 0.00 ] +Key: VMAXCPHZrrk: [ 0.00 0.00 ] +Key: VMAXCPHZrrkz: [ 0.00 0.00 ] +Key: VMAXCPSYrm: [ 0.00 0.00 ] +Key: VMAXCPSYrr: [ 0.00 0.00 ] +Key: VMAXCPSZ: [ 0.00 0.00 ] +Key: VMAXCPSZrm: [ 0.00 0.00 ] +Key: VMAXCPSZrmb: [ 0.00 0.00 ] +Key: VMAXCPSZrmbk: [ 0.00 0.00 ] +Key: VMAXCPSZrmbkz: [ 0.00 0.00 ] +Key: VMAXCPSZrmk: [ 0.00 0.00 ] +Key: VMAXCPSZrmkz: [ 0.00 0.00 ] +Key: VMAXCPSZrr: [ 0.00 0.00 ] +Key: VMAXCPSZrrk: [ 0.00 0.00 ] +Key: VMAXCPSZrrkz: [ 0.00 0.00 ] +Key: VMAXCPSrm: [ 0.00 0.00 ] +Key: VMAXCPSrr: [ 0.00 0.00 ] +Key: VMAXCSDZrm: [ 0.00 0.00 ] +Key: VMAXCSDZrr: [ 0.00 0.00 ] +Key: VMAXCSDrm: [ 0.00 0.00 ] +Key: VMAXCSDrr: [ 0.00 0.00 ] +Key: VMAXCSHZrm: [ 0.00 0.00 ] +Key: VMAXCSHZrr: [ 0.00 0.00 ] +Key: VMAXCSSZrm: [ 0.00 0.00 ] +Key: VMAXCSSZrr: [ 0.00 0.00 ] +Key: VMAXCSSrm: [ 0.00 0.00 ] +Key: VMAXCSSrr: [ 0.00 0.00 ] +Key: VMAXPDYrm: [ 0.00 0.00 ] +Key: VMAXPDYrr: [ 0.00 0.00 ] +Key: VMAXPDZ: [ 0.00 0.00 ] +Key: VMAXPDZrm: [ 0.00 0.00 ] +Key: VMAXPDZrmb: [ 0.00 0.00 ] +Key: VMAXPDZrmbk: [ 0.00 0.00 ] +Key: VMAXPDZrmbkz: [ 0.00 0.00 ] +Key: VMAXPDZrmk: [ 0.00 0.00 ] +Key: VMAXPDZrmkz: [ 0.00 0.00 ] +Key: VMAXPDZrr: [ 0.00 0.00 ] +Key: VMAXPDZrrb: [ 0.00 0.00 ] +Key: VMAXPDZrrbk: [ 0.00 0.00 ] +Key: VMAXPDZrrbkz: [ 0.00 0.00 ] +Key: VMAXPDZrrk: [ 0.00 0.00 ] +Key: VMAXPDZrrkz: [ 0.00 0.00 ] +Key: VMAXPDrm: [ 0.00 0.00 ] +Key: VMAXPDrr: [ 0.00 0.00 ] +Key: VMAXPHZ: [ 0.00 0.00 ] +Key: VMAXPHZrm: [ 0.00 0.00 ] +Key: VMAXPHZrmb: [ 0.00 0.00 ] +Key: VMAXPHZrmbk: [ 0.00 0.00 ] +Key: VMAXPHZrmbkz: [ 0.00 0.00 ] +Key: VMAXPHZrmk: [ 0.00 0.00 ] +Key: VMAXPHZrmkz: [ 0.00 0.00 ] +Key: VMAXPHZrr: [ 0.00 0.00 ] +Key: VMAXPHZrrb: [ 0.00 0.00 ] +Key: VMAXPHZrrbk: [ 0.00 0.00 ] +Key: VMAXPHZrrbkz: [ 0.00 0.00 ] +Key: VMAXPHZrrk: [ 0.00 0.00 ] +Key: VMAXPHZrrkz: [ 0.00 0.00 ] +Key: VMAXPSYrm: [ 0.00 0.00 ] +Key: VMAXPSYrr: [ 0.00 0.00 ] +Key: VMAXPSZ: [ 0.00 0.00 ] +Key: VMAXPSZrm: [ 0.00 0.00 ] +Key: VMAXPSZrmb: [ 0.00 0.00 ] +Key: VMAXPSZrmbk: [ 0.00 0.00 ] +Key: VMAXPSZrmbkz: [ 0.00 0.00 ] +Key: VMAXPSZrmk: [ 0.00 0.00 ] +Key: VMAXPSZrmkz: [ 0.00 0.00 ] +Key: VMAXPSZrr: [ 0.00 0.00 ] +Key: VMAXPSZrrb: [ 0.00 0.00 ] +Key: VMAXPSZrrbk: [ 0.00 0.00 ] +Key: VMAXPSZrrbkz: [ 0.00 0.00 ] +Key: VMAXPSZrrk: [ 0.00 0.00 ] +Key: VMAXPSZrrkz: [ 0.00 0.00 ] +Key: VMAXPSrm: [ 0.00 0.00 ] +Key: VMAXPSrr: [ 0.00 0.00 ] +Key: VMAXSDZrm: [ 0.00 0.00 ] +Key: VMAXSDZrm_Int: [ 0.00 0.00 ] +Key: VMAXSDZrmk_Int: [ 0.00 0.00 ] +Key: VMAXSDZrmkz_Int: [ 0.00 0.00 ] +Key: VMAXSDZrr: [ 0.00 0.00 ] +Key: VMAXSDZrr_Int: [ 0.00 0.00 ] +Key: VMAXSDZrrb_Int: [ 0.00 0.00 ] +Key: VMAXSDZrrbk_Int: [ 0.00 0.00 ] +Key: VMAXSDZrrbkz_Int: [ 0.00 0.00 ] +Key: VMAXSDZrrk_Int: [ 0.00 0.00 ] +Key: VMAXSDZrrkz_Int: [ 0.00 0.00 ] +Key: VMAXSDrm: [ 0.00 0.00 ] +Key: VMAXSDrm_Int: [ 0.00 0.00 ] +Key: VMAXSDrr: [ 0.00 0.00 ] +Key: VMAXSDrr_Int: [ 0.00 0.00 ] +Key: VMAXSHZrm: [ 0.00 0.00 ] +Key: VMAXSHZrm_Int: [ 0.00 0.00 ] +Key: VMAXSHZrmk_Int: [ 0.00 0.00 ] +Key: VMAXSHZrmkz_Int: [ 0.00 0.00 ] +Key: VMAXSHZrr: [ 0.00 0.00 ] +Key: VMAXSHZrr_Int: [ 0.00 0.00 ] +Key: VMAXSHZrrb_Int: [ 0.00 0.00 ] +Key: VMAXSHZrrbk_Int: [ 0.00 0.00 ] +Key: VMAXSHZrrbkz_Int: [ 0.00 0.00 ] +Key: VMAXSHZrrk_Int: [ 0.00 0.00 ] +Key: VMAXSHZrrkz_Int: [ 0.00 0.00 ] +Key: VMAXSSZrm: [ 0.00 0.00 ] +Key: VMAXSSZrm_Int: [ 0.00 0.00 ] +Key: VMAXSSZrmk_Int: [ 0.00 0.00 ] +Key: VMAXSSZrmkz_Int: [ 0.00 0.00 ] +Key: VMAXSSZrr: [ 0.00 0.00 ] +Key: VMAXSSZrr_Int: [ 0.00 0.00 ] +Key: VMAXSSZrrb_Int: [ 0.00 0.00 ] +Key: VMAXSSZrrbk_Int: [ 0.00 0.00 ] +Key: VMAXSSZrrbkz_Int: [ 0.00 0.00 ] +Key: VMAXSSZrrk_Int: [ 0.00 0.00 ] +Key: VMAXSSZrrkz_Int: [ 0.00 0.00 ] +Key: VMAXSSrm: [ 0.00 0.00 ] +Key: VMAXSSrm_Int: [ 0.00 0.00 ] +Key: VMAXSSrr: [ 0.00 0.00 ] +Key: VMAXSSrr_Int: [ 0.00 0.00 ] +Key: VMCALL: [ 0.00 0.00 ] +Key: VMCLEARm: [ 0.00 0.00 ] +Key: VMFUNC: [ 0.00 0.00 ] +Key: VMINBF: [ 0.00 0.00 ] +Key: VMINCPDYrm: [ 0.00 0.00 ] +Key: VMINCPDYrr: [ 0.00 0.00 ] +Key: VMINCPDZ: [ 0.00 0.00 ] +Key: VMINCPDZrm: [ 0.00 0.00 ] +Key: VMINCPDZrmb: [ 0.00 0.00 ] +Key: VMINCPDZrmbk: [ 0.00 0.00 ] +Key: VMINCPDZrmbkz: [ 0.00 0.00 ] +Key: VMINCPDZrmk: [ 0.00 0.00 ] +Key: VMINCPDZrmkz: [ 0.00 0.00 ] +Key: VMINCPDZrr: [ 0.00 0.00 ] +Key: VMINCPDZrrk: [ 0.00 0.00 ] +Key: VMINCPDZrrkz: [ 0.00 0.00 ] +Key: VMINCPDrm: [ 0.00 0.00 ] +Key: VMINCPDrr: [ 0.00 0.00 ] +Key: VMINCPHZ: [ 0.00 0.00 ] +Key: VMINCPHZrm: [ 0.00 0.00 ] +Key: VMINCPHZrmb: [ 0.00 0.00 ] +Key: VMINCPHZrmbk: [ 0.00 0.00 ] +Key: VMINCPHZrmbkz: [ 0.00 0.00 ] +Key: VMINCPHZrmk: [ 0.00 0.00 ] +Key: VMINCPHZrmkz: [ 0.00 0.00 ] +Key: VMINCPHZrr: [ 0.00 0.00 ] +Key: VMINCPHZrrk: [ 0.00 0.00 ] +Key: VMINCPHZrrkz: [ 0.00 0.00 ] +Key: VMINCPSYrm: [ 0.00 0.00 ] +Key: VMINCPSYrr: [ 0.00 0.00 ] +Key: VMINCPSZ: [ 0.00 0.00 ] +Key: VMINCPSZrm: [ 0.00 0.00 ] +Key: VMINCPSZrmb: [ 0.00 0.00 ] +Key: VMINCPSZrmbk: [ 0.00 0.00 ] +Key: VMINCPSZrmbkz: [ 0.00 0.00 ] +Key: VMINCPSZrmk: [ 0.00 0.00 ] +Key: VMINCPSZrmkz: [ 0.00 0.00 ] +Key: VMINCPSZrr: [ 0.00 0.00 ] +Key: VMINCPSZrrk: [ 0.00 0.00 ] +Key: VMINCPSZrrkz: [ 0.00 0.00 ] +Key: VMINCPSrm: [ 0.00 0.00 ] +Key: VMINCPSrr: [ 0.00 0.00 ] +Key: VMINCSDZrm: [ 0.00 0.00 ] +Key: VMINCSDZrr: [ 0.00 0.00 ] +Key: VMINCSDrm: [ 0.00 0.00 ] +Key: VMINCSDrr: [ 0.00 0.00 ] +Key: VMINCSHZrm: [ 0.00 0.00 ] +Key: VMINCSHZrr: [ 0.00 0.00 ] +Key: VMINCSSZrm: [ 0.00 0.00 ] +Key: VMINCSSZrr: [ 0.00 0.00 ] +Key: VMINCSSrm: [ 0.00 0.00 ] +Key: VMINCSSrr: [ 0.00 0.00 ] +Key: VMINMAXBF: [ 0.00 0.00 ] +Key: VMINMAXPDZ: [ 0.00 0.00 ] +Key: VMINMAXPDZrmbi: [ 0.00 0.00 ] +Key: VMINMAXPDZrmbik: [ 0.00 0.00 ] +Key: VMINMAXPDZrmbikz: [ 0.00 0.00 ] +Key: VMINMAXPDZrmi: [ 0.00 0.00 ] +Key: VMINMAXPDZrmik: [ 0.00 0.00 ] +Key: VMINMAXPDZrmikz: [ 0.00 0.00 ] +Key: VMINMAXPDZrri: [ 0.00 0.00 ] +Key: VMINMAXPDZrrib: [ 0.00 0.00 ] +Key: VMINMAXPDZrribk: [ 0.00 0.00 ] +Key: VMINMAXPDZrribkz: [ 0.00 0.00 ] +Key: VMINMAXPDZrrik: [ 0.00 0.00 ] +Key: VMINMAXPDZrrikz: [ 0.00 0.00 ] +Key: VMINMAXPHZ: [ 0.00 0.00 ] +Key: VMINMAXPHZrmbi: [ 0.00 0.00 ] +Key: VMINMAXPHZrmbik: [ 0.00 0.00 ] +Key: VMINMAXPHZrmbikz: [ 0.00 0.00 ] +Key: VMINMAXPHZrmi: [ 0.00 0.00 ] +Key: VMINMAXPHZrmik: [ 0.00 0.00 ] +Key: VMINMAXPHZrmikz: [ 0.00 0.00 ] +Key: VMINMAXPHZrri: [ 0.00 0.00 ] +Key: VMINMAXPHZrrib: [ 0.00 0.00 ] +Key: VMINMAXPHZrribk: [ 0.00 0.00 ] +Key: VMINMAXPHZrribkz: [ 0.00 0.00 ] +Key: VMINMAXPHZrrik: [ 0.00 0.00 ] +Key: VMINMAXPHZrrikz: [ 0.00 0.00 ] +Key: VMINMAXPSZ: [ 0.00 0.00 ] +Key: VMINMAXPSZrmbi: [ 0.00 0.00 ] +Key: VMINMAXPSZrmbik: [ 0.00 0.00 ] +Key: VMINMAXPSZrmbikz: [ 0.00 0.00 ] +Key: VMINMAXPSZrmi: [ 0.00 0.00 ] +Key: VMINMAXPSZrmik: [ 0.00 0.00 ] +Key: VMINMAXPSZrmikz: [ 0.00 0.00 ] +Key: VMINMAXPSZrri: [ 0.00 0.00 ] +Key: VMINMAXPSZrrib: [ 0.00 0.00 ] +Key: VMINMAXPSZrribk: [ 0.00 0.00 ] +Key: VMINMAXPSZrribkz: [ 0.00 0.00 ] +Key: VMINMAXPSZrrik: [ 0.00 0.00 ] +Key: VMINMAXPSZrrikz: [ 0.00 0.00 ] +Key: VMINMAXSDrmi: [ 0.00 0.00 ] +Key: VMINMAXSDrmi_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrmik_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrmikz_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrri: [ 0.00 0.00 ] +Key: VMINMAXSDrri_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrrib_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrribk_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrribkz_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrrik_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrrikz_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrmi: [ 0.00 0.00 ] +Key: VMINMAXSHrmi_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrmik_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrmikz_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrri: [ 0.00 0.00 ] +Key: VMINMAXSHrri_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrrib_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrribk_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrribkz_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrrik_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrrikz_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrmi: [ 0.00 0.00 ] +Key: VMINMAXSSrmi_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrmik_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrmikz_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrri: [ 0.00 0.00 ] +Key: VMINMAXSSrri_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrrib_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrribk_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrribkz_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrrik_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrrikz_Int: [ 0.00 0.00 ] +Key: VMINPDYrm: [ 0.00 0.00 ] +Key: VMINPDYrr: [ 0.00 0.00 ] +Key: VMINPDZ: [ 0.00 0.00 ] +Key: VMINPDZrm: [ 0.00 0.00 ] +Key: VMINPDZrmb: [ 0.00 0.00 ] +Key: VMINPDZrmbk: [ 0.00 0.00 ] +Key: VMINPDZrmbkz: [ 0.00 0.00 ] +Key: VMINPDZrmk: [ 0.00 0.00 ] +Key: VMINPDZrmkz: [ 0.00 0.00 ] +Key: VMINPDZrr: [ 0.00 0.00 ] +Key: VMINPDZrrb: [ 0.00 0.00 ] +Key: VMINPDZrrbk: [ 0.00 0.00 ] +Key: VMINPDZrrbkz: [ 0.00 0.00 ] +Key: VMINPDZrrk: [ 0.00 0.00 ] +Key: VMINPDZrrkz: [ 0.00 0.00 ] +Key: VMINPDrm: [ 0.00 0.00 ] +Key: VMINPDrr: [ 0.00 0.00 ] +Key: VMINPHZ: [ 0.00 0.00 ] +Key: VMINPHZrm: [ 0.00 0.00 ] +Key: VMINPHZrmb: [ 0.00 0.00 ] +Key: VMINPHZrmbk: [ 0.00 0.00 ] +Key: VMINPHZrmbkz: [ 0.00 0.00 ] +Key: VMINPHZrmk: [ 0.00 0.00 ] +Key: VMINPHZrmkz: [ 0.00 0.00 ] +Key: VMINPHZrr: [ 0.00 0.00 ] +Key: VMINPHZrrb: [ 0.00 0.00 ] +Key: VMINPHZrrbk: [ 0.00 0.00 ] +Key: VMINPHZrrbkz: [ 0.00 0.00 ] +Key: VMINPHZrrk: [ 0.00 0.00 ] +Key: VMINPHZrrkz: [ 0.00 0.00 ] +Key: VMINPSYrm: [ 0.00 0.00 ] +Key: VMINPSYrr: [ 0.00 0.00 ] +Key: VMINPSZ: [ 0.00 0.00 ] +Key: VMINPSZrm: [ 0.00 0.00 ] +Key: VMINPSZrmb: [ 0.00 0.00 ] +Key: VMINPSZrmbk: [ 0.00 0.00 ] +Key: VMINPSZrmbkz: [ 0.00 0.00 ] +Key: VMINPSZrmk: [ 0.00 0.00 ] +Key: VMINPSZrmkz: [ 0.00 0.00 ] +Key: VMINPSZrr: [ 0.00 0.00 ] +Key: VMINPSZrrb: [ 0.00 0.00 ] +Key: VMINPSZrrbk: [ 0.00 0.00 ] +Key: VMINPSZrrbkz: [ 0.00 0.00 ] +Key: VMINPSZrrk: [ 0.00 0.00 ] +Key: VMINPSZrrkz: [ 0.00 0.00 ] +Key: VMINPSrm: [ 0.00 0.00 ] +Key: VMINPSrr: [ 0.00 0.00 ] +Key: VMINSDZrm: [ 0.00 0.00 ] +Key: VMINSDZrm_Int: [ 0.00 0.00 ] +Key: VMINSDZrmk_Int: [ 0.00 0.00 ] +Key: VMINSDZrmkz_Int: [ 0.00 0.00 ] +Key: VMINSDZrr: [ 0.00 0.00 ] +Key: VMINSDZrr_Int: [ 0.00 0.00 ] +Key: VMINSDZrrb_Int: [ 0.00 0.00 ] +Key: VMINSDZrrbk_Int: [ 0.00 0.00 ] +Key: VMINSDZrrbkz_Int: [ 0.00 0.00 ] +Key: VMINSDZrrk_Int: [ 0.00 0.00 ] +Key: VMINSDZrrkz_Int: [ 0.00 0.00 ] +Key: VMINSDrm: [ 0.00 0.00 ] +Key: VMINSDrm_Int: [ 0.00 0.00 ] +Key: VMINSDrr: [ 0.00 0.00 ] +Key: VMINSDrr_Int: [ 0.00 0.00 ] +Key: VMINSHZrm: [ 0.00 0.00 ] +Key: VMINSHZrm_Int: [ 0.00 0.00 ] +Key: VMINSHZrmk_Int: [ 0.00 0.00 ] +Key: VMINSHZrmkz_Int: [ 0.00 0.00 ] +Key: VMINSHZrr: [ 0.00 0.00 ] +Key: VMINSHZrr_Int: [ 0.00 0.00 ] +Key: VMINSHZrrb_Int: [ 0.00 0.00 ] +Key: VMINSHZrrbk_Int: [ 0.00 0.00 ] +Key: VMINSHZrrbkz_Int: [ 0.00 0.00 ] +Key: VMINSHZrrk_Int: [ 0.00 0.00 ] +Key: VMINSHZrrkz_Int: [ 0.00 0.00 ] +Key: VMINSSZrm: [ 0.00 0.00 ] +Key: VMINSSZrm_Int: [ 0.00 0.00 ] +Key: VMINSSZrmk_Int: [ 0.00 0.00 ] +Key: VMINSSZrmkz_Int: [ 0.00 0.00 ] +Key: VMINSSZrr: [ 0.00 0.00 ] +Key: VMINSSZrr_Int: [ 0.00 0.00 ] +Key: VMINSSZrrb_Int: [ 0.00 0.00 ] +Key: VMINSSZrrbk_Int: [ 0.00 0.00 ] +Key: VMINSSZrrbkz_Int: [ 0.00 0.00 ] +Key: VMINSSZrrk_Int: [ 0.00 0.00 ] +Key: VMINSSZrrkz_Int: [ 0.00 0.00 ] +Key: VMINSSrm: [ 0.00 0.00 ] +Key: VMINSSrm_Int: [ 0.00 0.00 ] +Key: VMINSSrr: [ 0.00 0.00 ] +Key: VMINSSrr_Int: [ 0.00 0.00 ] +Key: VMLAUNCH: [ 0.00 0.00 ] +Key: VMLOAD: [ 0.00 0.00 ] +Key: VMMCALL: [ 0.00 0.00 ] +Key: VMOV: [ 0.00 0.00 ] +Key: VMOVAPDYmr: [ 0.00 0.00 ] +Key: VMOVAPDYrm: [ 0.00 0.00 ] +Key: VMOVAPDYrr: [ 0.00 0.00 ] +Key: VMOVAPDYrr_REV: [ 0.00 0.00 ] +Key: VMOVAPDZ: [ 0.00 0.00 ] +Key: VMOVAPDZmr: [ 0.00 0.00 ] +Key: VMOVAPDZmrk: [ 0.00 0.00 ] +Key: VMOVAPDZrm: [ 0.00 0.00 ] +Key: VMOVAPDZrmk: [ 0.00 0.00 ] +Key: VMOVAPDZrmkz: [ 0.00 0.00 ] +Key: VMOVAPDZrr: [ 0.00 0.00 ] +Key: VMOVAPDZrr_REV: [ 0.00 0.00 ] +Key: VMOVAPDZrrk: [ 0.00 0.00 ] +Key: VMOVAPDZrrk_REV: [ 0.00 0.00 ] +Key: VMOVAPDZrrkz: [ 0.00 0.00 ] +Key: VMOVAPDZrrkz_REV: [ 0.00 0.00 ] +Key: VMOVAPDmr: [ 0.00 0.00 ] +Key: VMOVAPDrm: [ 0.00 0.00 ] +Key: VMOVAPDrr: [ 0.00 0.00 ] +Key: VMOVAPDrr_REV: [ 0.00 0.00 ] +Key: VMOVAPSYmr: [ 0.00 0.00 ] +Key: VMOVAPSYrm: [ 0.00 0.00 ] +Key: VMOVAPSYrr: [ 0.00 0.00 ] +Key: VMOVAPSYrr_REV: [ 0.00 0.00 ] +Key: VMOVAPSZ: [ 0.00 0.00 ] +Key: VMOVAPSZmr: [ 0.00 0.00 ] +Key: VMOVAPSZmrk: [ 0.00 0.00 ] +Key: VMOVAPSZrm: [ 0.00 0.00 ] +Key: VMOVAPSZrmk: [ 0.00 0.00 ] +Key: VMOVAPSZrmkz: [ 0.00 0.00 ] +Key: VMOVAPSZrr: [ 0.00 0.00 ] +Key: VMOVAPSZrr_REV: [ 0.00 0.00 ] +Key: VMOVAPSZrrk: [ 0.00 0.00 ] +Key: VMOVAPSZrrk_REV: [ 0.00 0.00 ] +Key: VMOVAPSZrrkz: [ 0.00 0.00 ] +Key: VMOVAPSZrrkz_REV: [ 0.00 0.00 ] +Key: VMOVAPSmr: [ 0.00 0.00 ] +Key: VMOVAPSrm: [ 0.00 0.00 ] +Key: VMOVAPSrr: [ 0.00 0.00 ] +Key: VMOVAPSrr_REV: [ 0.00 0.00 ] +Key: VMOVDDUPYrm: [ 0.00 0.00 ] +Key: VMOVDDUPYrr: [ 0.00 0.00 ] +Key: VMOVDDUPZ: [ 0.00 0.00 ] +Key: VMOVDDUPZrm: [ 0.00 0.00 ] +Key: VMOVDDUPZrmk: [ 0.00 0.00 ] +Key: VMOVDDUPZrmkz: [ 0.00 0.00 ] +Key: VMOVDDUPZrr: [ 0.00 0.00 ] +Key: VMOVDDUPZrrk: [ 0.00 0.00 ] +Key: VMOVDDUPZrrkz: [ 0.00 0.00 ] +Key: VMOVDDUPrm: [ 0.00 0.00 ] +Key: VMOVDDUPrr: [ 0.00 0.00 ] +Key: VMOVDI: [ 0.00 0.00 ] +Key: VMOVDQA: [ 0.00 0.00 ] +Key: VMOVDQAYmr: [ 0.00 0.00 ] +Key: VMOVDQAYrm: [ 0.00 0.00 ] +Key: VMOVDQAYrr: [ 0.00 0.00 ] +Key: VMOVDQAYrr_REV: [ 0.00 0.00 ] +Key: VMOVDQAmr: [ 0.00 0.00 ] +Key: VMOVDQArm: [ 0.00 0.00 ] +Key: VMOVDQArr: [ 0.00 0.00 ] +Key: VMOVDQArr_REV: [ 0.00 0.00 ] +Key: VMOVDQU: [ 0.00 0.00 ] +Key: VMOVDQUYmr: [ 0.00 0.00 ] +Key: VMOVDQUYrm: [ 0.00 0.00 ] +Key: VMOVDQUYrr: [ 0.00 0.00 ] +Key: VMOVDQUYrr_REV: [ 0.00 0.00 ] +Key: VMOVDQUmr: [ 0.00 0.00 ] +Key: VMOVDQUrm: [ 0.00 0.00 ] +Key: VMOVDQUrr: [ 0.00 0.00 ] +Key: VMOVDQUrr_REV: [ 0.00 0.00 ] +Key: VMOVHLPSZrr: [ 0.00 0.00 ] +Key: VMOVHLPSrr: [ 0.00 0.00 ] +Key: VMOVHPDZ: [ 0.00 0.00 ] +Key: VMOVHPDmr: [ 0.00 0.00 ] +Key: VMOVHPDrm: [ 0.00 0.00 ] +Key: VMOVHPSZ: [ 0.00 0.00 ] +Key: VMOVHPSmr: [ 0.00 0.00 ] +Key: VMOVHPSrm: [ 0.00 0.00 ] +Key: VMOVLHPSZrr: [ 0.00 0.00 ] +Key: VMOVLHPSrr: [ 0.00 0.00 ] +Key: VMOVLPDZ: [ 0.00 0.00 ] +Key: VMOVLPDmr: [ 0.00 0.00 ] +Key: VMOVLPDrm: [ 0.00 0.00 ] +Key: VMOVLPSZ: [ 0.00 0.00 ] +Key: VMOVLPSmr: [ 0.00 0.00 ] +Key: VMOVLPSrm: [ 0.00 0.00 ] +Key: VMOVMSKPDYrr: [ 0.00 0.00 ] +Key: VMOVMSKPDrr: [ 0.00 0.00 ] +Key: VMOVMSKPSYrr: [ 0.00 0.00 ] +Key: VMOVMSKPSrr: [ 0.00 0.00 ] +Key: VMOVNTDQAYrm: [ 0.00 0.00 ] +Key: VMOVNTDQAZ: [ 0.00 0.00 ] +Key: VMOVNTDQAZrm: [ 0.00 0.00 ] +Key: VMOVNTDQArm: [ 0.00 0.00 ] +Key: VMOVNTDQYmr: [ 0.00 0.00 ] +Key: VMOVNTDQZ: [ 0.00 0.00 ] +Key: VMOVNTDQZmr: [ 0.00 0.00 ] +Key: VMOVNTDQmr: [ 0.00 0.00 ] +Key: VMOVNTPDYmr: [ 0.00 0.00 ] +Key: VMOVNTPDZ: [ 0.00 0.00 ] +Key: VMOVNTPDZmr: [ 0.00 0.00 ] +Key: VMOVNTPDmr: [ 0.00 0.00 ] +Key: VMOVNTPSYmr: [ 0.00 0.00 ] +Key: VMOVNTPSZ: [ 0.00 0.00 ] +Key: VMOVNTPSZmr: [ 0.00 0.00 ] +Key: VMOVNTPSmr: [ 0.00 0.00 ] +Key: VMOVPDI: [ 0.00 0.00 ] +Key: VMOVPQI: [ 0.00 0.00 ] +Key: VMOVPQIto: [ 0.00 0.00 ] +Key: VMOVQI: [ 0.00 0.00 ] +Key: VMOVRSBZ: [ 0.00 0.00 ] +Key: VMOVRSBZm: [ 0.00 0.00 ] +Key: VMOVRSBZmk: [ 0.00 0.00 ] +Key: VMOVRSBZmkz: [ 0.00 0.00 ] +Key: VMOVRSDZ: [ 0.00 0.00 ] +Key: VMOVRSDZm: [ 0.00 0.00 ] +Key: VMOVRSDZmk: [ 0.00 0.00 ] +Key: VMOVRSDZmkz: [ 0.00 0.00 ] +Key: VMOVRSQZ: [ 0.00 0.00 ] +Key: VMOVRSQZm: [ 0.00 0.00 ] +Key: VMOVRSQZmk: [ 0.00 0.00 ] +Key: VMOVRSQZmkz: [ 0.00 0.00 ] +Key: VMOVRSWZ: [ 0.00 0.00 ] +Key: VMOVRSWZm: [ 0.00 0.00 ] +Key: VMOVRSWZmk: [ 0.00 0.00 ] +Key: VMOVRSWZmkz: [ 0.00 0.00 ] +Key: VMOVSDZmr: [ 0.00 0.00 ] +Key: VMOVSDZmrk: [ 0.00 0.00 ] +Key: VMOVSDZrm: [ 0.00 0.00 ] +Key: VMOVSDZrm_alt: [ 0.00 0.00 ] +Key: VMOVSDZrmk: [ 0.00 0.00 ] +Key: VMOVSDZrmkz: [ 0.00 0.00 ] +Key: VMOVSDZrr: [ 0.00 0.00 ] +Key: VMOVSDZrr_REV: [ 0.00 0.00 ] +Key: VMOVSDZrrk: [ 0.00 0.00 ] +Key: VMOVSDZrrk_REV: [ 0.00 0.00 ] +Key: VMOVSDZrrkz: [ 0.00 0.00 ] +Key: VMOVSDZrrkz_REV: [ 0.00 0.00 ] +Key: VMOVSDmr: [ 0.00 0.00 ] +Key: VMOVSDrm: [ 0.00 0.00 ] +Key: VMOVSDrm_alt: [ 0.00 0.00 ] +Key: VMOVSDrr: [ 0.00 0.00 ] +Key: VMOVSDrr_REV: [ 0.00 0.00 ] +Key: VMOVSDto: [ 0.00 0.00 ] +Key: VMOVSH: [ 0.00 0.00 ] +Key: VMOVSHDUPYrm: [ 0.00 0.00 ] +Key: VMOVSHDUPYrr: [ 0.00 0.00 ] +Key: VMOVSHDUPZ: [ 0.00 0.00 ] +Key: VMOVSHDUPZrm: [ 0.00 0.00 ] +Key: VMOVSHDUPZrmk: [ 0.00 0.00 ] +Key: VMOVSHDUPZrmkz: [ 0.00 0.00 ] +Key: VMOVSHDUPZrr: [ 0.00 0.00 ] +Key: VMOVSHDUPZrrk: [ 0.00 0.00 ] +Key: VMOVSHDUPZrrkz: [ 0.00 0.00 ] +Key: VMOVSHDUPrm: [ 0.00 0.00 ] +Key: VMOVSHDUPrr: [ 0.00 0.00 ] +Key: VMOVSHZmr: [ 0.00 0.00 ] +Key: VMOVSHZmrk: [ 0.00 0.00 ] +Key: VMOVSHZrm: [ 0.00 0.00 ] +Key: VMOVSHZrm_alt: [ 0.00 0.00 ] +Key: VMOVSHZrmk: [ 0.00 0.00 ] +Key: VMOVSHZrmkz: [ 0.00 0.00 ] +Key: VMOVSHZrr: [ 0.00 0.00 ] +Key: VMOVSHZrr_REV: [ 0.00 0.00 ] +Key: VMOVSHZrrk: [ 0.00 0.00 ] +Key: VMOVSHZrrk_REV: [ 0.00 0.00 ] +Key: VMOVSHZrrkz: [ 0.00 0.00 ] +Key: VMOVSHZrrkz_REV: [ 0.00 0.00 ] +Key: VMOVSHtoW: [ 0.00 0.00 ] +Key: VMOVSLDUPYrm: [ 0.00 0.00 ] +Key: VMOVSLDUPYrr: [ 0.00 0.00 ] +Key: VMOVSLDUPZ: [ 0.00 0.00 ] +Key: VMOVSLDUPZrm: [ 0.00 0.00 ] +Key: VMOVSLDUPZrmk: [ 0.00 0.00 ] +Key: VMOVSLDUPZrmkz: [ 0.00 0.00 ] +Key: VMOVSLDUPZrr: [ 0.00 0.00 ] +Key: VMOVSLDUPZrrk: [ 0.00 0.00 ] +Key: VMOVSLDUPZrrkz: [ 0.00 0.00 ] +Key: VMOVSLDUPrm: [ 0.00 0.00 ] +Key: VMOVSLDUPrr: [ 0.00 0.00 ] +Key: VMOVSS: [ 0.00 0.00 ] +Key: VMOVSSZmr: [ 0.00 0.00 ] +Key: VMOVSSZmrk: [ 0.00 0.00 ] +Key: VMOVSSZrm: [ 0.00 0.00 ] +Key: VMOVSSZrm_alt: [ 0.00 0.00 ] +Key: VMOVSSZrmk: [ 0.00 0.00 ] +Key: VMOVSSZrmkz: [ 0.00 0.00 ] +Key: VMOVSSZrr: [ 0.00 0.00 ] +Key: VMOVSSZrr_REV: [ 0.00 0.00 ] +Key: VMOVSSZrrk: [ 0.00 0.00 ] +Key: VMOVSSZrrk_REV: [ 0.00 0.00 ] +Key: VMOVSSZrrkz: [ 0.00 0.00 ] +Key: VMOVSSZrrkz_REV: [ 0.00 0.00 ] +Key: VMOVSSmr: [ 0.00 0.00 ] +Key: VMOVSSrm: [ 0.00 0.00 ] +Key: VMOVSSrm_alt: [ 0.00 0.00 ] +Key: VMOVSSrr: [ 0.00 0.00 ] +Key: VMOVSSrr_REV: [ 0.00 0.00 ] +Key: VMOVUPDYmr: [ 0.00 0.00 ] +Key: VMOVUPDYrm: [ 0.00 0.00 ] +Key: VMOVUPDYrr: [ 0.00 0.00 ] +Key: VMOVUPDYrr_REV: [ 0.00 0.00 ] +Key: VMOVUPDZ: [ 0.00 0.00 ] +Key: VMOVUPDZmr: [ 0.00 0.00 ] +Key: VMOVUPDZmrk: [ 0.00 0.00 ] +Key: VMOVUPDZrm: [ 0.00 0.00 ] +Key: VMOVUPDZrmk: [ 0.00 0.00 ] +Key: VMOVUPDZrmkz: [ 0.00 0.00 ] +Key: VMOVUPDZrr: [ 0.00 0.00 ] +Key: VMOVUPDZrr_REV: [ 0.00 0.00 ] +Key: VMOVUPDZrrk: [ 0.00 0.00 ] +Key: VMOVUPDZrrk_REV: [ 0.00 0.00 ] +Key: VMOVUPDZrrkz: [ 0.00 0.00 ] +Key: VMOVUPDZrrkz_REV: [ 0.00 0.00 ] +Key: VMOVUPDmr: [ 0.00 0.00 ] +Key: VMOVUPDrm: [ 0.00 0.00 ] +Key: VMOVUPDrr: [ 0.00 0.00 ] +Key: VMOVUPDrr_REV: [ 0.00 0.00 ] +Key: VMOVUPSYmr: [ 0.00 0.00 ] +Key: VMOVUPSYrm: [ 0.00 0.00 ] +Key: VMOVUPSYrr: [ 0.00 0.00 ] +Key: VMOVUPSYrr_REV: [ 0.00 0.00 ] +Key: VMOVUPSZ: [ 0.00 0.00 ] +Key: VMOVUPSZmr: [ 0.00 0.00 ] +Key: VMOVUPSZmrk: [ 0.00 0.00 ] +Key: VMOVUPSZrm: [ 0.00 0.00 ] +Key: VMOVUPSZrmk: [ 0.00 0.00 ] +Key: VMOVUPSZrmkz: [ 0.00 0.00 ] +Key: VMOVUPSZrr: [ 0.00 0.00 ] +Key: VMOVUPSZrr_REV: [ 0.00 0.00 ] +Key: VMOVUPSZrrk: [ 0.00 0.00 ] +Key: VMOVUPSZrrk_REV: [ 0.00 0.00 ] +Key: VMOVUPSZrrkz: [ 0.00 0.00 ] +Key: VMOVUPSZrrkz_REV: [ 0.00 0.00 ] +Key: VMOVUPSmr: [ 0.00 0.00 ] +Key: VMOVUPSrm: [ 0.00 0.00 ] +Key: VMOVUPSrr: [ 0.00 0.00 ] +Key: VMOVUPSrr_REV: [ 0.00 0.00 ] +Key: VMOVW: [ 0.00 0.00 ] +Key: VMOVWmr: [ 0.00 0.00 ] +Key: VMOVWrm: [ 0.00 0.00 ] +Key: VMOVZPDILo: [ 0.00 0.00 ] +Key: VMOVZPQILo: [ 0.00 0.00 ] +Key: VMOVZPWILo: [ 0.00 0.00 ] +Key: VMPSADBWYrmi: [ 0.00 0.00 ] +Key: VMPSADBWYrri: [ 0.00 0.00 ] +Key: VMPSADBWZ: [ 0.00 0.00 ] +Key: VMPSADBWZrmi: [ 0.00 0.00 ] +Key: VMPSADBWZrmik: [ 0.00 0.00 ] +Key: VMPSADBWZrmikz: [ 0.00 0.00 ] +Key: VMPSADBWZrri: [ 0.00 0.00 ] +Key: VMPSADBWZrrik: [ 0.00 0.00 ] +Key: VMPSADBWZrrikz: [ 0.00 0.00 ] +Key: VMPSADBWrmi: [ 0.00 0.00 ] +Key: VMPSADBWrri: [ 0.00 0.00 ] +Key: VMPTRLDm: [ 0.00 0.00 ] +Key: VMPTRSTm: [ 0.00 0.00 ] +Key: VMREAD: [ 0.00 0.00 ] +Key: VMRESUME: [ 0.00 0.00 ] +Key: VMRUN: [ 0.00 0.00 ] +Key: VMSAVE: [ 0.00 0.00 ] +Key: VMULBF: [ 0.00 0.00 ] +Key: VMULPDYrm: [ 0.00 0.00 ] +Key: VMULPDYrr: [ 0.00 0.00 ] +Key: VMULPDZ: [ 0.00 0.00 ] +Key: VMULPDZrm: [ 0.00 0.00 ] +Key: VMULPDZrmb: [ 0.00 0.00 ] +Key: VMULPDZrmbk: [ 0.00 0.00 ] +Key: VMULPDZrmbkz: [ 0.00 0.00 ] +Key: VMULPDZrmk: [ 0.00 0.00 ] +Key: VMULPDZrmkz: [ 0.00 0.00 ] +Key: VMULPDZrr: [ 0.00 0.00 ] +Key: VMULPDZrrb: [ 0.00 0.00 ] +Key: VMULPDZrrbk: [ 0.00 0.00 ] +Key: VMULPDZrrbkz: [ 0.00 0.00 ] +Key: VMULPDZrrk: [ 0.00 0.00 ] +Key: VMULPDZrrkz: [ 0.00 0.00 ] +Key: VMULPDrm: [ 0.00 0.00 ] +Key: VMULPDrr: [ 0.00 0.00 ] +Key: VMULPHZ: [ 0.00 0.00 ] +Key: VMULPHZrm: [ 0.00 0.00 ] +Key: VMULPHZrmb: [ 0.00 0.00 ] +Key: VMULPHZrmbk: [ 0.00 0.00 ] +Key: VMULPHZrmbkz: [ 0.00 0.00 ] +Key: VMULPHZrmk: [ 0.00 0.00 ] +Key: VMULPHZrmkz: [ 0.00 0.00 ] +Key: VMULPHZrr: [ 0.00 0.00 ] +Key: VMULPHZrrb: [ 0.00 0.00 ] +Key: VMULPHZrrbk: [ 0.00 0.00 ] +Key: VMULPHZrrbkz: [ 0.00 0.00 ] +Key: VMULPHZrrk: [ 0.00 0.00 ] +Key: VMULPHZrrkz: [ 0.00 0.00 ] +Key: VMULPSYrm: [ 0.00 0.00 ] +Key: VMULPSYrr: [ 0.00 0.00 ] +Key: VMULPSZ: [ 0.00 0.00 ] +Key: VMULPSZrm: [ 0.00 0.00 ] +Key: VMULPSZrmb: [ 0.00 0.00 ] +Key: VMULPSZrmbk: [ 0.00 0.00 ] +Key: VMULPSZrmbkz: [ 0.00 0.00 ] +Key: VMULPSZrmk: [ 0.00 0.00 ] +Key: VMULPSZrmkz: [ 0.00 0.00 ] +Key: VMULPSZrr: [ 0.00 0.00 ] +Key: VMULPSZrrb: [ 0.00 0.00 ] +Key: VMULPSZrrbk: [ 0.00 0.00 ] +Key: VMULPSZrrbkz: [ 0.00 0.00 ] +Key: VMULPSZrrk: [ 0.00 0.00 ] +Key: VMULPSZrrkz: [ 0.00 0.00 ] +Key: VMULPSrm: [ 0.00 0.00 ] +Key: VMULPSrr: [ 0.00 0.00 ] +Key: VMULSDZrm: [ 0.00 0.00 ] +Key: VMULSDZrm_Int: [ 0.00 0.00 ] +Key: VMULSDZrmk_Int: [ 0.00 0.00 ] +Key: VMULSDZrmkz_Int: [ 0.00 0.00 ] +Key: VMULSDZrr: [ 0.00 0.00 ] +Key: VMULSDZrr_Int: [ 0.00 0.00 ] +Key: VMULSDZrrb_Int: [ 0.00 0.00 ] +Key: VMULSDZrrbk_Int: [ 0.00 0.00 ] +Key: VMULSDZrrbkz_Int: [ 0.00 0.00 ] +Key: VMULSDZrrk_Int: [ 0.00 0.00 ] +Key: VMULSDZrrkz_Int: [ 0.00 0.00 ] +Key: VMULSDrm: [ 0.00 0.00 ] +Key: VMULSDrm_Int: [ 0.00 0.00 ] +Key: VMULSDrr: [ 0.00 0.00 ] +Key: VMULSDrr_Int: [ 0.00 0.00 ] +Key: VMULSHZrm: [ 0.00 0.00 ] +Key: VMULSHZrm_Int: [ 0.00 0.00 ] +Key: VMULSHZrmk_Int: [ 0.00 0.00 ] +Key: VMULSHZrmkz_Int: [ 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VPCONFLICTDZrmk: [ 0.00 0.00 ] +Key: VPCONFLICTDZrmkz: [ 0.00 0.00 ] +Key: VPCONFLICTDZrr: [ 0.00 0.00 ] +Key: VPCONFLICTDZrrk: [ 0.00 0.00 ] +Key: VPCONFLICTDZrrkz: [ 0.00 0.00 ] +Key: VPCONFLICTQZ: [ 0.00 0.00 ] +Key: VPCONFLICTQZrm: [ 0.00 0.00 ] +Key: VPCONFLICTQZrmb: [ 0.00 0.00 ] +Key: VPCONFLICTQZrmbk: [ 0.00 0.00 ] +Key: VPCONFLICTQZrmbkz: [ 0.00 0.00 ] +Key: VPCONFLICTQZrmk: [ 0.00 0.00 ] +Key: VPCONFLICTQZrmkz: [ 0.00 0.00 ] +Key: VPCONFLICTQZrr: [ 0.00 0.00 ] +Key: VPCONFLICTQZrrk: [ 0.00 0.00 ] +Key: VPCONFLICTQZrrkz: [ 0.00 0.00 ] +Key: VPDPBSSDSYrm: [ 0.00 0.00 ] +Key: VPDPBSSDSYrr: [ 0.00 0.00 ] +Key: VPDPBSSDSZ: [ 0.00 0.00 ] +Key: VPDPBSSDSZrm: [ 0.00 0.00 ] +Key: VPDPBSSDSZrmb: [ 0.00 0.00 ] +Key: VPDPBSSDSZrmbk: [ 0.00 0.00 ] +Key: VPDPBSSDSZrmbkz: [ 0.00 0.00 ] +Key: VPDPBSSDSZrmk: [ 0.00 0.00 ] +Key: VPDPBSSDSZrmkz: [ 0.00 0.00 ] +Key: VPDPBSSDSZrr: [ 0.00 0.00 ] +Key: VPDPBSSDSZrrk: [ 0.00 0.00 ] +Key: VPDPBSSDSZrrkz: [ 0.00 0.00 ] +Key: VPDPBSSDSrm: [ 0.00 0.00 ] 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] +Key: VPHADDBQrm: [ 0.00 0.00 ] +Key: VPHADDBQrr: [ 0.00 0.00 ] +Key: VPHADDBWrm: [ 0.00 0.00 ] +Key: VPHADDBWrr: [ 0.00 0.00 ] +Key: VPHADDDQrm: [ 0.00 0.00 ] +Key: VPHADDDQrr: [ 0.00 0.00 ] +Key: VPHADDDYrm: [ 0.00 0.00 ] +Key: VPHADDDYrr: [ 0.00 0.00 ] +Key: VPHADDDrm: [ 0.00 0.00 ] +Key: VPHADDDrr: [ 0.00 0.00 ] +Key: VPHADDSWYrm: [ 0.00 0.00 ] +Key: VPHADDSWYrr: [ 0.00 0.00 ] +Key: VPHADDSWrm: [ 0.00 0.00 ] +Key: VPHADDSWrr: [ 0.00 0.00 ] +Key: VPHADDUBDrm: [ 0.00 0.00 ] +Key: VPHADDUBDrr: [ 0.00 0.00 ] +Key: VPHADDUBQrm: [ 0.00 0.00 ] +Key: VPHADDUBQrr: [ 0.00 0.00 ] +Key: VPHADDUBWrm: [ 0.00 0.00 ] +Key: VPHADDUBWrr: [ 0.00 0.00 ] +Key: VPHADDUDQrm: [ 0.00 0.00 ] +Key: VPHADDUDQrr: [ 0.00 0.00 ] +Key: VPHADDUWDrm: [ 0.00 0.00 ] +Key: VPHADDUWDrr: [ 0.00 0.00 ] +Key: VPHADDUWQrm: [ 0.00 0.00 ] +Key: VPHADDUWQrr: [ 0.00 0.00 ] +Key: VPHADDWDrm: [ 0.00 0.00 ] +Key: VPHADDWDrr: [ 0.00 0.00 ] +Key: VPHADDWQrm: [ 0.00 0.00 ] +Key: VPHADDWQrr: [ 0.00 0.00 ] +Key: VPHADDWYrm: [ 0.00 0.00 ] +Key: VPHADDWYrr: [ 0.00 0.00 ] +Key: VPHADDWrm: [ 0.00 0.00 ] +Key: VPHADDWrr: [ 0.00 0.00 ] +Key: VPHMINPOSUWrm: [ 0.00 0.00 ] +Key: VPHMINPOSUWrr: [ 0.00 0.00 ] +Key: VPHSUBBWrm: [ 0.00 0.00 ] +Key: VPHSUBBWrr: [ 0.00 0.00 ] +Key: VPHSUBDQrm: [ 0.00 0.00 ] +Key: VPHSUBDQrr: [ 0.00 0.00 ] +Key: VPHSUBDYrm: [ 0.00 0.00 ] +Key: VPHSUBDYrr: [ 0.00 0.00 ] +Key: VPHSUBDrm: [ 0.00 0.00 ] +Key: VPHSUBDrr: [ 0.00 0.00 ] +Key: VPHSUBSWYrm: [ 0.00 0.00 ] +Key: VPHSUBSWYrr: [ 0.00 0.00 ] +Key: VPHSUBSWrm: [ 0.00 0.00 ] +Key: VPHSUBSWrr: [ 0.00 0.00 ] +Key: VPHSUBWDrm: [ 0.00 0.00 ] +Key: VPHSUBWDrr: [ 0.00 0.00 ] +Key: VPHSUBWYrm: [ 0.00 0.00 ] +Key: VPHSUBWYrr: [ 0.00 0.00 ] +Key: VPHSUBWrm: [ 0.00 0.00 ] +Key: VPHSUBWrr: [ 0.00 0.00 ] +Key: VPINSRBZrmi: [ 0.00 0.00 ] +Key: VPINSRBZrri: [ 0.00 0.00 ] +Key: VPINSRBrmi: [ 0.00 0.00 ] +Key: VPINSRBrri: [ 0.00 0.00 ] +Key: VPINSRDZrmi: [ 0.00 0.00 ] +Key: VPINSRDZrri: [ 0.00 0.00 ] +Key: VPINSRDrmi: [ 0.00 0.00 ] +Key: VPINSRDrri: [ 0.00 0.00 ] +Key: VPINSRQZrmi: [ 0.00 0.00 ] +Key: VPINSRQZrri: [ 0.00 0.00 ] +Key: VPINSRQrmi: [ 0.00 0.00 ] +Key: VPINSRQrri: [ 0.00 0.00 ] +Key: VPINSRWZrmi: [ 0.00 0.00 ] +Key: VPINSRWZrri: [ 0.00 0.00 ] +Key: VPINSRWrmi: [ 0.00 0.00 ] +Key: VPINSRWrri: [ 0.00 0.00 ] +Key: VPLZCNTDZ: [ 0.00 0.00 ] +Key: VPLZCNTDZrm: [ 0.00 0.00 ] +Key: VPLZCNTDZrmb: [ 0.00 0.00 ] +Key: VPLZCNTDZrmbk: [ 0.00 0.00 ] +Key: VPLZCNTDZrmbkz: [ 0.00 0.00 ] +Key: VPLZCNTDZrmk: [ 0.00 0.00 ] +Key: VPLZCNTDZrmkz: [ 0.00 0.00 ] +Key: VPLZCNTDZrr: [ 0.00 0.00 ] +Key: VPLZCNTDZrrk: [ 0.00 0.00 ] +Key: VPLZCNTDZrrkz: [ 0.00 0.00 ] +Key: VPLZCNTQZ: [ 0.00 0.00 ] +Key: VPLZCNTQZrm: [ 0.00 0.00 ] +Key: VPLZCNTQZrmb: [ 0.00 0.00 ] +Key: VPLZCNTQZrmbk: [ 0.00 0.00 ] +Key: VPLZCNTQZrmbkz: [ 0.00 0.00 ] +Key: VPLZCNTQZrmk: [ 0.00 0.00 ] +Key: VPLZCNTQZrmkz: [ 0.00 0.00 ] +Key: VPLZCNTQZrr: [ 0.00 0.00 ] +Key: VPLZCNTQZrrk: [ 0.00 0.00 ] +Key: VPLZCNTQZrrkz: [ 0.00 0.00 ] +Key: VPMACSDDrm: [ 0.00 0.00 ] +Key: VPMACSDDrr: [ 0.00 0.00 ] +Key: VPMACSDQHrm: [ 0.00 0.00 ] +Key: VPMACSDQHrr: [ 0.00 0.00 ] +Key: VPMACSDQLrm: [ 0.00 0.00 ] +Key: VPMACSDQLrr: [ 0.00 0.00 ] +Key: VPMACSSDDrm: [ 0.00 0.00 ] +Key: VPMACSSDDrr: [ 0.00 0.00 ] +Key: VPMACSSDQHrm: [ 0.00 0.00 ] +Key: VPMACSSDQHrr: [ 0.00 0.00 ] +Key: VPMACSSDQLrm: [ 0.00 0.00 ] +Key: VPMACSSDQLrr: [ 0.00 0.00 ] +Key: VPMACSSWDrm: [ 0.00 0.00 ] +Key: VPMACSSWDrr: [ 0.00 0.00 ] +Key: VPMACSSWWrm: [ 0.00 0.00 ] +Key: VPMACSSWWrr: [ 0.00 0.00 ] +Key: VPMACSWDrm: [ 0.00 0.00 ] +Key: VPMACSWDrr: [ 0.00 0.00 ] +Key: VPMACSWWrm: [ 0.00 0.00 ] +Key: VPMACSWWrr: [ 0.00 0.00 ] +Key: VPMADCSSWDrm: [ 0.00 0.00 ] +Key: VPMADCSSWDrr: [ 0.00 0.00 ] +Key: VPMADCSWDrm: [ 0.00 0.00 ] +Key: VPMADCSWDrr: [ 0.00 0.00 ] +Key: VPMADD: [ 0.00 0.00 ] +Key: VPMADDUBSWYrm: [ 0.00 0.00 ] +Key: VPMADDUBSWYrr: [ 0.00 0.00 ] +Key: VPMADDUBSWZ: [ 0.00 0.00 ] +Key: VPMADDUBSWZrm: [ 0.00 0.00 ] +Key: VPMADDUBSWZrmk: [ 0.00 0.00 ] +Key: VPMADDUBSWZrmkz: [ 0.00 0.00 ] +Key: VPMADDUBSWZrr: [ 0.00 0.00 ] +Key: VPMADDUBSWZrrk: [ 0.00 0.00 ] +Key: VPMADDUBSWZrrkz: [ 0.00 0.00 ] +Key: VPMADDUBSWrm: [ 0.00 0.00 ] +Key: VPMADDUBSWrr: [ 0.00 0.00 ] +Key: VPMADDWDYrm: [ 0.00 0.00 ] +Key: VPMADDWDYrr: [ 0.00 0.00 ] +Key: VPMADDWDZ: [ 0.00 0.00 ] +Key: VPMADDWDZrm: [ 0.00 0.00 ] +Key: VPMADDWDZrmk: [ 0.00 0.00 ] +Key: VPMADDWDZrmkz: [ 0.00 0.00 ] +Key: VPMADDWDZrr: [ 0.00 0.00 ] +Key: VPMADDWDZrrk: [ 0.00 0.00 ] +Key: VPMADDWDZrrkz: [ 0.00 0.00 ] +Key: VPMADDWDrm: [ 0.00 0.00 ] +Key: VPMADDWDrr: [ 0.00 0.00 ] +Key: VPMASKMOVDYmr: [ 0.00 0.00 ] +Key: VPMASKMOVDYrm: [ 0.00 0.00 ] +Key: VPMASKMOVDmr: [ 0.00 0.00 ] +Key: VPMASKMOVDrm: [ 0.00 0.00 ] +Key: VPMASKMOVQYmr: [ 0.00 0.00 ] +Key: VPMASKMOVQYrm: [ 0.00 0.00 ] +Key: VPMASKMOVQmr: [ 0.00 0.00 ] +Key: VPMASKMOVQrm: [ 0.00 0.00 ] +Key: VPMAXSBYrm: [ 0.00 0.00 ] +Key: VPMAXSBYrr: [ 0.00 0.00 ] +Key: VPMAXSBZ: [ 0.00 0.00 ] +Key: VPMAXSBZrm: [ 0.00 0.00 ] +Key: VPMAXSBZrmk: [ 0.00 0.00 ] +Key: VPMAXSBZrmkz: [ 0.00 0.00 ] +Key: VPMAXSBZrr: [ 0.00 0.00 ] +Key: VPMAXSBZrrk: [ 0.00 0.00 ] +Key: VPMAXSBZrrkz: [ 0.00 0.00 ] +Key: VPMAXSBrm: [ 0.00 0.00 ] +Key: VPMAXSBrr: [ 0.00 0.00 ] +Key: VPMAXSDYrm: [ 0.00 0.00 ] +Key: VPMAXSDYrr: [ 0.00 0.00 ] +Key: VPMAXSDZ: [ 0.00 0.00 ] +Key: VPMAXSDZrm: [ 0.00 0.00 ] +Key: VPMAXSDZrmb: [ 0.00 0.00 ] +Key: VPMAXSDZrmbk: [ 0.00 0.00 ] +Key: VPMAXSDZrmbkz: [ 0.00 0.00 ] +Key: VPMAXSDZrmk: [ 0.00 0.00 ] +Key: VPMAXSDZrmkz: [ 0.00 0.00 ] +Key: VPMAXSDZrr: [ 0.00 0.00 ] +Key: VPMAXSDZrrk: [ 0.00 0.00 ] +Key: VPMAXSDZrrkz: [ 0.00 0.00 ] +Key: VPMAXSDrm: [ 0.00 0.00 ] +Key: VPMAXSDrr: [ 0.00 0.00 ] +Key: VPMAXSQZ: [ 0.00 0.00 ] +Key: VPMAXSQZrm: [ 0.00 0.00 ] +Key: VPMAXSQZrmb: [ 0.00 0.00 ] +Key: VPMAXSQZrmbk: [ 0.00 0.00 ] +Key: VPMAXSQZrmbkz: [ 0.00 0.00 ] +Key: VPMAXSQZrmk: [ 0.00 0.00 ] +Key: VPMAXSQZrmkz: [ 0.00 0.00 ] +Key: VPMAXSQZrr: [ 0.00 0.00 ] +Key: VPMAXSQZrrk: [ 0.00 0.00 ] +Key: VPMAXSQZrrkz: [ 0.00 0.00 ] +Key: VPMAXSWYrm: [ 0.00 0.00 ] +Key: VPMAXSWYrr: [ 0.00 0.00 ] +Key: VPMAXSWZ: [ 0.00 0.00 ] +Key: VPMAXSWZrm: [ 0.00 0.00 ] +Key: VPMAXSWZrmk: [ 0.00 0.00 ] +Key: VPMAXSWZrmkz: [ 0.00 0.00 ] +Key: VPMAXSWZrr: [ 0.00 0.00 ] +Key: VPMAXSWZrrk: [ 0.00 0.00 ] +Key: VPMAXSWZrrkz: [ 0.00 0.00 ] +Key: VPMAXSWrm: [ 0.00 0.00 ] +Key: VPMAXSWrr: [ 0.00 0.00 ] +Key: VPMAXUBYrm: [ 0.00 0.00 ] +Key: VPMAXUBYrr: [ 0.00 0.00 ] +Key: VPMAXUBZ: [ 0.00 0.00 ] +Key: VPMAXUBZrm: [ 0.00 0.00 ] +Key: VPMAXUBZrmk: [ 0.00 0.00 ] +Key: VPMAXUBZrmkz: [ 0.00 0.00 ] +Key: VPMAXUBZrr: [ 0.00 0.00 ] +Key: VPMAXUBZrrk: [ 0.00 0.00 ] +Key: VPMAXUBZrrkz: [ 0.00 0.00 ] +Key: VPMAXUBrm: [ 0.00 0.00 ] +Key: VPMAXUBrr: [ 0.00 0.00 ] +Key: VPMAXUDYrm: [ 0.00 0.00 ] +Key: VPMAXUDYrr: [ 0.00 0.00 ] +Key: VPMAXUDZ: [ 0.00 0.00 ] +Key: VPMAXUDZrm: [ 0.00 0.00 ] +Key: VPMAXUDZrmb: [ 0.00 0.00 ] +Key: VPMAXUDZrmbk: [ 0.00 0.00 ] +Key: VPMAXUDZrmbkz: [ 0.00 0.00 ] +Key: VPMAXUDZrmk: [ 0.00 0.00 ] +Key: VPMAXUDZrmkz: [ 0.00 0.00 ] +Key: VPMAXUDZrr: [ 0.00 0.00 ] +Key: VPMAXUDZrrk: [ 0.00 0.00 ] +Key: VPMAXUDZrrkz: [ 0.00 0.00 ] +Key: VPMAXUDrm: [ 0.00 0.00 ] +Key: VPMAXUDrr: [ 0.00 0.00 ] +Key: VPMAXUQZ: [ 0.00 0.00 ] +Key: VPMAXUQZrm: [ 0.00 0.00 ] +Key: VPMAXUQZrmb: [ 0.00 0.00 ] +Key: VPMAXUQZrmbk: [ 0.00 0.00 ] +Key: VPMAXUQZrmbkz: [ 0.00 0.00 ] +Key: VPMAXUQZrmk: [ 0.00 0.00 ] +Key: VPMAXUQZrmkz: [ 0.00 0.00 ] +Key: VPMAXUQZrr: [ 0.00 0.00 ] +Key: VPMAXUQZrrk: [ 0.00 0.00 ] +Key: VPMAXUQZrrkz: [ 0.00 0.00 ] +Key: VPMAXUWYrm: [ 0.00 0.00 ] +Key: VPMAXUWYrr: [ 0.00 0.00 ] +Key: VPMAXUWZ: [ 0.00 0.00 ] +Key: VPMAXUWZrm: [ 0.00 0.00 ] +Key: VPMAXUWZrmk: [ 0.00 0.00 ] +Key: VPMAXUWZrmkz: [ 0.00 0.00 ] +Key: VPMAXUWZrr: [ 0.00 0.00 ] +Key: VPMAXUWZrrk: [ 0.00 0.00 ] +Key: VPMAXUWZrrkz: [ 0.00 0.00 ] +Key: VPMAXUWrm: [ 0.00 0.00 ] +Key: VPMAXUWrr: [ 0.00 0.00 ] +Key: VPMINSBYrm: [ 0.00 0.00 ] +Key: VPMINSBYrr: [ 0.00 0.00 ] +Key: VPMINSBZ: [ 0.00 0.00 ] +Key: VPMINSBZrm: [ 0.00 0.00 ] +Key: VPMINSBZrmk: [ 0.00 0.00 ] +Key: VPMINSBZrmkz: [ 0.00 0.00 ] +Key: VPMINSBZrr: [ 0.00 0.00 ] +Key: VPMINSBZrrk: [ 0.00 0.00 ] +Key: VPMINSBZrrkz: [ 0.00 0.00 ] +Key: VPMINSBrm: [ 0.00 0.00 ] +Key: VPMINSBrr: [ 0.00 0.00 ] +Key: VPMINSDYrm: [ 0.00 0.00 ] +Key: VPMINSDYrr: [ 0.00 0.00 ] +Key: VPMINSDZ: [ 0.00 0.00 ] +Key: VPMINSDZrm: [ 0.00 0.00 ] +Key: VPMINSDZrmb: [ 0.00 0.00 ] +Key: VPMINSDZrmbk: [ 0.00 0.00 ] +Key: VPMINSDZrmbkz: [ 0.00 0.00 ] +Key: VPMINSDZrmk: [ 0.00 0.00 ] +Key: VPMINSDZrmkz: [ 0.00 0.00 ] +Key: VPMINSDZrr: [ 0.00 0.00 ] +Key: VPMINSDZrrk: [ 0.00 0.00 ] +Key: VPMINSDZrrkz: [ 0.00 0.00 ] +Key: VPMINSDrm: [ 0.00 0.00 ] +Key: VPMINSDrr: [ 0.00 0.00 ] +Key: VPMINSQZ: [ 0.00 0.00 ] +Key: VPMINSQZrm: [ 0.00 0.00 ] +Key: VPMINSQZrmb: [ 0.00 0.00 ] +Key: VPMINSQZrmbk: [ 0.00 0.00 ] +Key: VPMINSQZrmbkz: [ 0.00 0.00 ] +Key: VPMINSQZrmk: [ 0.00 0.00 ] +Key: VPMINSQZrmkz: [ 0.00 0.00 ] +Key: VPMINSQZrr: [ 0.00 0.00 ] +Key: VPMINSQZrrk: [ 0.00 0.00 ] +Key: VPMINSQZrrkz: [ 0.00 0.00 ] +Key: VPMINSWYrm: [ 0.00 0.00 ] +Key: VPMINSWYrr: [ 0.00 0.00 ] +Key: VPMINSWZ: [ 0.00 0.00 ] +Key: VPMINSWZrm: [ 0.00 0.00 ] +Key: VPMINSWZrmk: [ 0.00 0.00 ] +Key: VPMINSWZrmkz: [ 0.00 0.00 ] +Key: VPMINSWZrr: [ 0.00 0.00 ] +Key: VPMINSWZrrk: [ 0.00 0.00 ] +Key: VPMINSWZrrkz: [ 0.00 0.00 ] +Key: VPMINSWrm: [ 0.00 0.00 ] +Key: VPMINSWrr: [ 0.00 0.00 ] +Key: VPMINUBYrm: [ 0.00 0.00 ] +Key: VPMINUBYrr: [ 0.00 0.00 ] +Key: VPMINUBZ: [ 0.00 0.00 ] +Key: VPMINUBZrm: [ 0.00 0.00 ] +Key: VPMINUBZrmk: [ 0.00 0.00 ] +Key: VPMINUBZrmkz: [ 0.00 0.00 ] +Key: VPMINUBZrr: [ 0.00 0.00 ] +Key: VPMINUBZrrk: [ 0.00 0.00 ] +Key: VPMINUBZrrkz: [ 0.00 0.00 ] +Key: VPMINUBrm: [ 0.00 0.00 ] +Key: VPMINUBrr: [ 0.00 0.00 ] +Key: VPMINUDYrm: [ 0.00 0.00 ] +Key: VPMINUDYrr: [ 0.00 0.00 ] +Key: VPMINUDZ: [ 0.00 0.00 ] +Key: VPMINUDZrm: [ 0.00 0.00 ] +Key: VPMINUDZrmb: [ 0.00 0.00 ] +Key: VPMINUDZrmbk: [ 0.00 0.00 ] +Key: VPMINUDZrmbkz: [ 0.00 0.00 ] +Key: VPMINUDZrmk: [ 0.00 0.00 ] +Key: VPMINUDZrmkz: [ 0.00 0.00 ] +Key: VPMINUDZrr: [ 0.00 0.00 ] +Key: VPMINUDZrrk: [ 0.00 0.00 ] +Key: VPMINUDZrrkz: [ 0.00 0.00 ] +Key: VPMINUDrm: [ 0.00 0.00 ] +Key: VPMINUDrr: [ 0.00 0.00 ] +Key: VPMINUQZ: [ 0.00 0.00 ] +Key: VPMINUQZrm: [ 0.00 0.00 ] +Key: VPMINUQZrmb: [ 0.00 0.00 ] +Key: VPMINUQZrmbk: [ 0.00 0.00 ] +Key: VPMINUQZrmbkz: [ 0.00 0.00 ] +Key: VPMINUQZrmk: [ 0.00 0.00 ] +Key: VPMINUQZrmkz: [ 0.00 0.00 ] +Key: VPMINUQZrr: [ 0.00 0.00 ] +Key: VPMINUQZrrk: [ 0.00 0.00 ] +Key: VPMINUQZrrkz: [ 0.00 0.00 ] +Key: VPMINUWYrm: [ 0.00 0.00 ] +Key: VPMINUWYrr: [ 0.00 0.00 ] +Key: VPMINUWZ: [ 0.00 0.00 ] +Key: VPMINUWZrm: [ 0.00 0.00 ] +Key: VPMINUWZrmk: [ 0.00 0.00 ] +Key: VPMINUWZrmkz: [ 0.00 0.00 ] +Key: VPMINUWZrr: [ 0.00 0.00 ] +Key: VPMINUWZrrk: [ 0.00 0.00 ] +Key: VPMINUWZrrkz: [ 0.00 0.00 ] +Key: VPMINUWrm: [ 0.00 0.00 ] +Key: VPMINUWrr: [ 0.00 0.00 ] +Key: VPMOVB: [ 0.00 0.00 ] +Key: VPMOVD: [ 0.00 0.00 ] +Key: VPMOVDBZ: [ 0.00 0.00 ] +Key: VPMOVDBZmr: [ 0.00 0.00 ] +Key: VPMOVDBZmrk: [ 0.00 0.00 ] +Key: VPMOVDBZrr: [ 0.00 0.00 ] +Key: VPMOVDBZrrk: [ 0.00 0.00 ] +Key: VPMOVDBZrrkz: [ 0.00 0.00 ] +Key: VPMOVDWZ: [ 0.00 0.00 ] +Key: VPMOVDWZmr: [ 0.00 0.00 ] +Key: VPMOVDWZmrk: [ 0.00 0.00 ] +Key: VPMOVDWZrr: [ 0.00 0.00 ] +Key: VPMOVDWZrrk: [ 0.00 0.00 ] +Key: VPMOVDWZrrkz: [ 0.00 0.00 ] +Key: VPMOVM: [ 0.00 0.00 ] +Key: VPMOVMSKBYrr: [ 0.00 0.00 ] +Key: VPMOVMSKBrr: [ 0.00 0.00 ] +Key: VPMOVQ: [ 0.00 0.00 ] +Key: VPMOVQBZ: [ 0.00 0.00 ] +Key: VPMOVQBZmr: [ 0.00 0.00 ] +Key: VPMOVQBZmrk: [ 0.00 0.00 ] +Key: VPMOVQBZrr: [ 0.00 0.00 ] +Key: VPMOVQBZrrk: [ 0.00 0.00 ] +Key: VPMOVQBZrrkz: [ 0.00 0.00 ] +Key: VPMOVQDZ: [ 0.00 0.00 ] +Key: VPMOVQDZmr: [ 0.00 0.00 ] +Key: VPMOVQDZmrk: [ 0.00 0.00 ] +Key: VPMOVQDZrr: [ 0.00 0.00 ] +Key: VPMOVQDZrrk: [ 0.00 0.00 ] +Key: VPMOVQDZrrkz: [ 0.00 0.00 ] +Key: VPMOVQWZ: [ 0.00 0.00 ] +Key: VPMOVQWZmr: [ 0.00 0.00 ] +Key: VPMOVQWZmrk: [ 0.00 0.00 ] +Key: VPMOVQWZrr: [ 0.00 0.00 ] +Key: VPMOVQWZrrk: [ 0.00 0.00 ] +Key: VPMOVQWZrrkz: [ 0.00 0.00 ] +Key: VPMOVSDBZ: [ 0.00 0.00 ] +Key: VPMOVSDBZmr: [ 0.00 0.00 ] +Key: VPMOVSDBZmrk: [ 0.00 0.00 ] +Key: VPMOVSDBZrr: [ 0.00 0.00 ] +Key: VPMOVSDBZrrk: [ 0.00 0.00 ] +Key: VPMOVSDBZrrkz: [ 0.00 0.00 ] +Key: VPMOVSDWZ: [ 0.00 0.00 ] +Key: VPMOVSDWZmr: [ 0.00 0.00 ] +Key: VPMOVSDWZmrk: [ 0.00 0.00 ] +Key: VPMOVSDWZrr: [ 0.00 0.00 ] +Key: VPMOVSDWZrrk: [ 0.00 0.00 ] +Key: VPMOVSDWZrrkz: [ 0.00 0.00 ] +Key: VPMOVSQBZ: [ 0.00 0.00 ] +Key: VPMOVSQBZmr: [ 0.00 0.00 ] +Key: VPMOVSQBZmrk: [ 0.00 0.00 ] +Key: VPMOVSQBZrr: [ 0.00 0.00 ] +Key: VPMOVSQBZrrk: [ 0.00 0.00 ] +Key: VPMOVSQBZrrkz: [ 0.00 0.00 ] +Key: VPMOVSQDZ: [ 0.00 0.00 ] +Key: VPMOVSQDZmr: [ 0.00 0.00 ] +Key: VPMOVSQDZmrk: [ 0.00 0.00 ] +Key: VPMOVSQDZrr: [ 0.00 0.00 ] +Key: VPMOVSQDZrrk: [ 0.00 0.00 ] +Key: VPMOVSQDZrrkz: [ 0.00 0.00 ] +Key: VPMOVSQWZ: [ 0.00 0.00 ] +Key: VPMOVSQWZmr: [ 0.00 0.00 ] +Key: VPMOVSQWZmrk: [ 0.00 0.00 ] +Key: VPMOVSQWZrr: [ 0.00 0.00 ] +Key: VPMOVSQWZrrk: [ 0.00 0.00 ] +Key: VPMOVSQWZrrkz: [ 0.00 0.00 ] +Key: VPMOVSWBZ: [ 0.00 0.00 ] +Key: VPMOVSWBZmr: [ 0.00 0.00 ] +Key: VPMOVSWBZmrk: [ 0.00 0.00 ] +Key: VPMOVSWBZrr: [ 0.00 0.00 ] +Key: VPMOVSWBZrrk: [ 0.00 0.00 ] +Key: VPMOVSWBZrrkz: [ 0.00 0.00 ] +Key: VPMOVSXBDYrm: [ 0.00 0.00 ] +Key: VPMOVSXBDYrr: [ 0.00 0.00 ] +Key: VPMOVSXBDZ: [ 0.00 0.00 ] +Key: VPMOVSXBDZrm: [ 0.00 0.00 ] +Key: VPMOVSXBDZrmk: [ 0.00 0.00 ] +Key: VPMOVSXBDZrmkz: [ 0.00 0.00 ] +Key: VPMOVSXBDZrr: [ 0.00 0.00 ] +Key: VPMOVSXBDZrrk: [ 0.00 0.00 ] +Key: VPMOVSXBDZrrkz: [ 0.00 0.00 ] +Key: VPMOVSXBDrm: [ 0.00 0.00 ] +Key: VPMOVSXBDrr: [ 0.00 0.00 ] +Key: VPMOVSXBQYrm: [ 0.00 0.00 ] +Key: VPMOVSXBQYrr: [ 0.00 0.00 ] +Key: VPMOVSXBQZ: [ 0.00 0.00 ] +Key: VPMOVSXBQZrm: [ 0.00 0.00 ] +Key: VPMOVSXBQZrmk: [ 0.00 0.00 ] +Key: VPMOVSXBQZrmkz: [ 0.00 0.00 ] +Key: VPMOVSXBQZrr: [ 0.00 0.00 ] +Key: VPMOVSXBQZrrk: [ 0.00 0.00 ] +Key: VPMOVSXBQZrrkz: [ 0.00 0.00 ] +Key: VPMOVSXBQrm: [ 0.00 0.00 ] +Key: VPMOVSXBQrr: [ 0.00 0.00 ] +Key: VPMOVSXBWYrm: [ 0.00 0.00 ] +Key: VPMOVSXBWYrr: [ 0.00 0.00 ] +Key: VPMOVSXBWZ: [ 0.00 0.00 ] +Key: VPMOVSXBWZrm: [ 0.00 0.00 ] +Key: VPMOVSXBWZrmk: [ 0.00 0.00 ] +Key: VPMOVSXBWZrmkz: [ 0.00 0.00 ] +Key: VPMOVSXBWZrr: [ 0.00 0.00 ] +Key: VPMOVSXBWZrrk: [ 0.00 0.00 ] +Key: VPMOVSXBWZrrkz: [ 0.00 0.00 ] +Key: VPMOVSXBWrm: [ 0.00 0.00 ] +Key: VPMOVSXBWrr: [ 0.00 0.00 ] +Key: VPMOVSXDQYrm: [ 0.00 0.00 ] +Key: VPMOVSXDQYrr: [ 0.00 0.00 ] +Key: VPMOVSXDQZ: [ 0.00 0.00 ] +Key: VPMOVSXDQZrm: [ 0.00 0.00 ] +Key: VPMOVSXDQZrmk: [ 0.00 0.00 ] +Key: VPMOVSXDQZrmkz: [ 0.00 0.00 ] +Key: VPMOVSXDQZrr: [ 0.00 0.00 ] +Key: VPMOVSXDQZrrk: [ 0.00 0.00 ] +Key: VPMOVSXDQZrrkz: [ 0.00 0.00 ] +Key: VPMOVSXDQrm: [ 0.00 0.00 ] +Key: VPMOVSXDQrr: [ 0.00 0.00 ] +Key: VPMOVSXWDYrm: [ 0.00 0.00 ] +Key: VPMOVSXWDYrr: [ 0.00 0.00 ] +Key: VPMOVSXWDZ: [ 0.00 0.00 ] +Key: VPMOVSXWDZrm: [ 0.00 0.00 ] +Key: VPMOVSXWDZrmk: [ 0.00 0.00 ] +Key: VPMOVSXWDZrmkz: [ 0.00 0.00 ] +Key: VPMOVSXWDZrr: [ 0.00 0.00 ] +Key: VPMOVSXWDZrrk: [ 0.00 0.00 ] +Key: VPMOVSXWDZrrkz: [ 0.00 0.00 ] +Key: VPMOVSXWDrm: [ 0.00 0.00 ] +Key: VPMOVSXWDrr: [ 0.00 0.00 ] +Key: VPMOVSXWQYrm: [ 0.00 0.00 ] +Key: VPMOVSXWQYrr: [ 0.00 0.00 ] +Key: VPMOVSXWQZ: [ 0.00 0.00 ] +Key: VPMOVSXWQZrm: [ 0.00 0.00 ] +Key: VPMOVSXWQZrmk: [ 0.00 0.00 ] +Key: VPMOVSXWQZrmkz: [ 0.00 0.00 ] +Key: VPMOVSXWQZrr: [ 0.00 0.00 ] +Key: VPMOVSXWQZrrk: [ 0.00 0.00 ] +Key: VPMOVSXWQZrrkz: [ 0.00 0.00 ] +Key: VPMOVSXWQrm: [ 0.00 0.00 ] +Key: VPMOVSXWQrr: [ 0.00 0.00 ] +Key: VPMOVUSDBZ: [ 0.00 0.00 ] +Key: VPMOVUSDBZmr: [ 0.00 0.00 ] +Key: VPMOVUSDBZmrk: [ 0.00 0.00 ] +Key: VPMOVUSDBZrr: [ 0.00 0.00 ] +Key: VPMOVUSDBZrrk: [ 0.00 0.00 ] +Key: VPMOVUSDBZrrkz: [ 0.00 0.00 ] +Key: VPMOVUSDWZ: [ 0.00 0.00 ] +Key: VPMOVUSDWZmr: [ 0.00 0.00 ] +Key: VPMOVUSDWZmrk: [ 0.00 0.00 ] +Key: VPMOVUSDWZrr: [ 0.00 0.00 ] +Key: VPMOVUSDWZrrk: [ 0.00 0.00 ] +Key: VPMOVUSDWZrrkz: [ 0.00 0.00 ] +Key: VPMOVUSQBZ: [ 0.00 0.00 ] +Key: VPMOVUSQBZmr: [ 0.00 0.00 ] +Key: VPMOVUSQBZmrk: [ 0.00 0.00 ] +Key: VPMOVUSQBZrr: [ 0.00 0.00 ] +Key: VPMOVUSQBZrrk: [ 0.00 0.00 ] +Key: VPMOVUSQBZrrkz: [ 0.00 0.00 ] +Key: VPMOVUSQDZ: [ 0.00 0.00 ] +Key: VPMOVUSQDZmr: [ 0.00 0.00 ] +Key: VPMOVUSQDZmrk: [ 0.00 0.00 ] +Key: VPMOVUSQDZrr: [ 0.00 0.00 ] +Key: VPMOVUSQDZrrk: [ 0.00 0.00 ] +Key: VPMOVUSQDZrrkz: [ 0.00 0.00 ] +Key: VPMOVUSQWZ: [ 0.00 0.00 ] +Key: VPMOVUSQWZmr: [ 0.00 0.00 ] +Key: VPMOVUSQWZmrk: [ 0.00 0.00 ] +Key: VPMOVUSQWZrr: [ 0.00 0.00 ] +Key: VPMOVUSQWZrrk: [ 0.00 0.00 ] +Key: VPMOVUSQWZrrkz: [ 0.00 0.00 ] +Key: VPMOVUSWBZ: [ 0.00 0.00 ] +Key: VPMOVUSWBZmr: [ 0.00 0.00 ] +Key: VPMOVUSWBZmrk: [ 0.00 0.00 ] +Key: VPMOVUSWBZrr: [ 0.00 0.00 ] +Key: VPMOVUSWBZrrk: [ 0.00 0.00 ] +Key: VPMOVUSWBZrrkz: [ 0.00 0.00 ] +Key: VPMOVW: [ 0.00 0.00 ] +Key: VPMOVWBZ: [ 0.00 0.00 ] +Key: VPMOVWBZmr: [ 0.00 0.00 ] +Key: VPMOVWBZmrk: [ 0.00 0.00 ] +Key: VPMOVWBZrr: [ 0.00 0.00 ] +Key: VPMOVWBZrrk: [ 0.00 0.00 ] +Key: VPMOVWBZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXBDYrm: [ 0.00 0.00 ] +Key: VPMOVZXBDYrr: [ 0.00 0.00 ] +Key: VPMOVZXBDZ: [ 0.00 0.00 ] +Key: VPMOVZXBDZrm: [ 0.00 0.00 ] +Key: VPMOVZXBDZrmk: [ 0.00 0.00 ] +Key: VPMOVZXBDZrmkz: [ 0.00 0.00 ] +Key: VPMOVZXBDZrr: [ 0.00 0.00 ] +Key: VPMOVZXBDZrrk: [ 0.00 0.00 ] +Key: VPMOVZXBDZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXBDrm: [ 0.00 0.00 ] +Key: VPMOVZXBDrr: [ 0.00 0.00 ] +Key: VPMOVZXBQYrm: [ 0.00 0.00 ] +Key: VPMOVZXBQYrr: [ 0.00 0.00 ] +Key: VPMOVZXBQZ: [ 0.00 0.00 ] +Key: VPMOVZXBQZrm: [ 0.00 0.00 ] +Key: VPMOVZXBQZrmk: [ 0.00 0.00 ] +Key: VPMOVZXBQZrmkz: [ 0.00 0.00 ] +Key: VPMOVZXBQZrr: [ 0.00 0.00 ] +Key: VPMOVZXBQZrrk: [ 0.00 0.00 ] +Key: VPMOVZXBQZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXBQrm: [ 0.00 0.00 ] +Key: VPMOVZXBQrr: [ 0.00 0.00 ] +Key: VPMOVZXBWYrm: [ 0.00 0.00 ] +Key: VPMOVZXBWYrr: [ 0.00 0.00 ] +Key: VPMOVZXBWZ: [ 0.00 0.00 ] +Key: VPMOVZXBWZrm: [ 0.00 0.00 ] +Key: VPMOVZXBWZrmk: [ 0.00 0.00 ] +Key: VPMOVZXBWZrmkz: [ 0.00 0.00 ] +Key: VPMOVZXBWZrr: [ 0.00 0.00 ] +Key: VPMOVZXBWZrrk: [ 0.00 0.00 ] +Key: VPMOVZXBWZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXBWrm: [ 0.00 0.00 ] +Key: VPMOVZXBWrr: [ 0.00 0.00 ] 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VPMOVZXWQZrrk: [ 0.00 0.00 ] +Key: VPMOVZXWQZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXWQrm: [ 0.00 0.00 ] +Key: VPMOVZXWQrr: [ 0.00 0.00 ] +Key: VPMULDQYrm: [ 0.00 0.00 ] +Key: VPMULDQYrr: [ 0.00 0.00 ] +Key: VPMULDQZ: [ 0.00 0.00 ] +Key: VPMULDQZrm: [ 0.00 0.00 ] +Key: VPMULDQZrmb: [ 0.00 0.00 ] +Key: VPMULDQZrmbk: [ 0.00 0.00 ] +Key: VPMULDQZrmbkz: [ 0.00 0.00 ] +Key: VPMULDQZrmk: [ 0.00 0.00 ] +Key: VPMULDQZrmkz: [ 0.00 0.00 ] +Key: VPMULDQZrr: [ 0.00 0.00 ] +Key: VPMULDQZrrk: [ 0.00 0.00 ] +Key: VPMULDQZrrkz: [ 0.00 0.00 ] +Key: VPMULDQrm: [ 0.00 0.00 ] +Key: VPMULDQrr: [ 0.00 0.00 ] +Key: VPMULHRSWYrm: [ 0.00 0.00 ] +Key: VPMULHRSWYrr: [ 0.00 0.00 ] +Key: VPMULHRSWZ: [ 0.00 0.00 ] +Key: VPMULHRSWZrm: [ 0.00 0.00 ] +Key: VPMULHRSWZrmk: [ 0.00 0.00 ] +Key: VPMULHRSWZrmkz: [ 0.00 0.00 ] +Key: VPMULHRSWZrr: [ 0.00 0.00 ] +Key: VPMULHRSWZrrk: [ 0.00 0.00 ] +Key: VPMULHRSWZrrkz: [ 0.00 0.00 ] +Key: VPMULHRSWrm: [ 0.00 0.00 ] +Key: VPMULHRSWrr: [ 0.00 0.00 ] +Key: VPMULHUWYrm: [ 0.00 0.00 ] +Key: VPMULHUWYrr: [ 0.00 0.00 ] +Key: VPMULHUWZ: [ 0.00 0.00 ] +Key: VPMULHUWZrm: [ 0.00 0.00 ] +Key: VPMULHUWZrmk: [ 0.00 0.00 ] +Key: VPMULHUWZrmkz: [ 0.00 0.00 ] +Key: VPMULHUWZrr: [ 0.00 0.00 ] +Key: VPMULHUWZrrk: [ 0.00 0.00 ] +Key: VPMULHUWZrrkz: [ 0.00 0.00 ] +Key: VPMULHUWrm: [ 0.00 0.00 ] +Key: VPMULHUWrr: [ 0.00 0.00 ] +Key: VPMULHWYrm: [ 0.00 0.00 ] +Key: VPMULHWYrr: [ 0.00 0.00 ] +Key: VPMULHWZ: [ 0.00 0.00 ] +Key: VPMULHWZrm: [ 0.00 0.00 ] +Key: VPMULHWZrmk: [ 0.00 0.00 ] +Key: VPMULHWZrmkz: [ 0.00 0.00 ] +Key: VPMULHWZrr: [ 0.00 0.00 ] +Key: VPMULHWZrrk: [ 0.00 0.00 ] +Key: VPMULHWZrrkz: [ 0.00 0.00 ] +Key: VPMULHWrm: [ 0.00 0.00 ] +Key: VPMULHWrr: [ 0.00 0.00 ] +Key: VPMULLDYrm: [ 0.00 0.00 ] +Key: VPMULLDYrr: [ 0.00 0.00 ] +Key: VPMULLDZ: [ 0.00 0.00 ] +Key: VPMULLDZrm: [ 0.00 0.00 ] +Key: VPMULLDZrmb: [ 0.00 0.00 ] +Key: VPMULLDZrmbk: [ 0.00 0.00 ] +Key: VPMULLDZrmbkz: [ 0.00 0.00 ] +Key: VPMULLDZrmk: [ 0.00 0.00 ] +Key: VPMULLDZrmkz: [ 0.00 0.00 ] +Key: VPMULLDZrr: [ 0.00 0.00 ] +Key: VPMULLDZrrk: [ 0.00 0.00 ] +Key: VPMULLDZrrkz: [ 0.00 0.00 ] +Key: VPMULLDrm: [ 0.00 0.00 ] +Key: VPMULLDrr: [ 0.00 0.00 ] +Key: VPMULLQZ: [ 0.00 0.00 ] +Key: VPMULLQZrm: [ 0.00 0.00 ] +Key: VPMULLQZrmb: [ 0.00 0.00 ] +Key: VPMULLQZrmbk: [ 0.00 0.00 ] +Key: VPMULLQZrmbkz: [ 0.00 0.00 ] +Key: VPMULLQZrmk: [ 0.00 0.00 ] +Key: VPMULLQZrmkz: [ 0.00 0.00 ] +Key: VPMULLQZrr: [ 0.00 0.00 ] +Key: VPMULLQZrrk: [ 0.00 0.00 ] +Key: VPMULLQZrrkz: [ 0.00 0.00 ] +Key: VPMULLWYrm: [ 0.00 0.00 ] +Key: VPMULLWYrr: [ 0.00 0.00 ] +Key: VPMULLWZ: [ 0.00 0.00 ] +Key: VPMULLWZrm: [ 0.00 0.00 ] +Key: VPMULLWZrmk: [ 0.00 0.00 ] +Key: VPMULLWZrmkz: [ 0.00 0.00 ] +Key: VPMULLWZrr: [ 0.00 0.00 ] +Key: VPMULLWZrrk: [ 0.00 0.00 ] +Key: VPMULLWZrrkz: [ 0.00 0.00 ] +Key: VPMULLWrm: [ 0.00 0.00 ] +Key: VPMULLWrr: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZ: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrm: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrmb: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrmbk: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrmbkz: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrmk: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrmkz: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrr: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrrk: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrrkz: [ 0.00 0.00 ] +Key: VPMULUDQYrm: [ 0.00 0.00 ] +Key: VPMULUDQYrr: [ 0.00 0.00 ] +Key: VPMULUDQZ: [ 0.00 0.00 ] +Key: VPMULUDQZrm: [ 0.00 0.00 ] +Key: VPMULUDQZrmb: [ 0.00 0.00 ] +Key: VPMULUDQZrmbk: [ 0.00 0.00 ] +Key: VPMULUDQZrmbkz: [ 0.00 0.00 ] +Key: VPMULUDQZrmk: [ 0.00 0.00 ] +Key: VPMULUDQZrmkz: [ 0.00 0.00 ] +Key: VPMULUDQZrr: [ 0.00 0.00 ] +Key: VPMULUDQZrrk: [ 0.00 0.00 ] +Key: VPMULUDQZrrkz: [ 0.00 0.00 ] +Key: VPMULUDQrm: [ 0.00 0.00 ] +Key: VPMULUDQrr: [ 0.00 0.00 ] +Key: VPOPCNTBZ: [ 0.00 0.00 ] +Key: VPOPCNTBZrm: [ 0.00 0.00 ] +Key: VPOPCNTBZrmk: [ 0.00 0.00 ] +Key: VPOPCNTBZrmkz: [ 0.00 0.00 ] +Key: VPOPCNTBZrr: [ 0.00 0.00 ] +Key: VPOPCNTBZrrk: [ 0.00 0.00 ] +Key: VPOPCNTBZrrkz: [ 0.00 0.00 ] +Key: VPOPCNTDZ: [ 0.00 0.00 ] +Key: VPOPCNTDZrm: [ 0.00 0.00 ] +Key: VPOPCNTDZrmb: [ 0.00 0.00 ] +Key: VPOPCNTDZrmbk: [ 0.00 0.00 ] +Key: VPOPCNTDZrmbkz: [ 0.00 0.00 ] +Key: VPOPCNTDZrmk: [ 0.00 0.00 ] +Key: VPOPCNTDZrmkz: [ 0.00 0.00 ] +Key: VPOPCNTDZrr: [ 0.00 0.00 ] +Key: VPOPCNTDZrrk: [ 0.00 0.00 ] +Key: VPOPCNTDZrrkz: [ 0.00 0.00 ] +Key: VPOPCNTQZ: [ 0.00 0.00 ] +Key: VPOPCNTQZrm: [ 0.00 0.00 ] +Key: VPOPCNTQZrmb: [ 0.00 0.00 ] +Key: VPOPCNTQZrmbk: [ 0.00 0.00 ] +Key: VPOPCNTQZrmbkz: [ 0.00 0.00 ] +Key: VPOPCNTQZrmk: [ 0.00 0.00 ] +Key: VPOPCNTQZrmkz: [ 0.00 0.00 ] +Key: VPOPCNTQZrr: [ 0.00 0.00 ] +Key: VPOPCNTQZrrk: [ 0.00 0.00 ] +Key: VPOPCNTQZrrkz: [ 0.00 0.00 ] +Key: VPOPCNTWZ: [ 0.00 0.00 ] +Key: VPOPCNTWZrm: [ 0.00 0.00 ] +Key: VPOPCNTWZrmk: [ 0.00 0.00 ] +Key: VPOPCNTWZrmkz: [ 0.00 0.00 ] +Key: VPOPCNTWZrr: [ 0.00 0.00 ] +Key: VPOPCNTWZrrk: [ 0.00 0.00 ] +Key: VPOPCNTWZrrkz: [ 0.00 0.00 ] +Key: VPORDZ: [ 0.00 0.00 ] +Key: VPORDZrm: [ 0.00 0.00 ] +Key: VPORDZrmb: [ 0.00 0.00 ] +Key: VPORDZrmbk: [ 0.00 0.00 ] +Key: VPORDZrmbkz: [ 0.00 0.00 ] +Key: VPORDZrmk: [ 0.00 0.00 ] +Key: VPORDZrmkz: [ 0.00 0.00 ] +Key: VPORDZrr: [ 0.00 0.00 ] +Key: VPORDZrrk: [ 0.00 0.00 ] +Key: VPORDZrrkz: [ 0.00 0.00 ] +Key: VPORQZ: [ 0.00 0.00 ] +Key: VPORQZrm: [ 0.00 0.00 ] +Key: VPORQZrmb: [ 0.00 0.00 ] +Key: VPORQZrmbk: [ 0.00 0.00 ] +Key: VPORQZrmbkz: [ 0.00 0.00 ] +Key: VPORQZrmk: [ 0.00 0.00 ] +Key: VPORQZrmkz: [ 0.00 0.00 ] +Key: VPORQZrr: [ 0.00 0.00 ] +Key: VPORQZrrk: [ 0.00 0.00 ] +Key: VPORQZrrkz: [ 0.00 0.00 ] +Key: VPORYrm: [ 0.00 0.00 ] +Key: VPORYrr: [ 0.00 0.00 ] +Key: VPORrm: [ 0.00 0.00 ] +Key: VPORrr: [ 0.00 0.00 ] +Key: VPPERMrmr: [ 0.00 0.00 ] +Key: VPPERMrrm: [ 0.00 0.00 ] +Key: VPPERMrrr: [ 0.00 0.00 ] +Key: VPPERMrrr_REV: [ 0.00 0.00 ] +Key: VPROLDZ: [ 0.00 0.00 ] +Key: VPROLDZmbi: [ 0.00 0.00 ] +Key: VPROLDZmbik: [ 0.00 0.00 ] +Key: VPROLDZmbikz: [ 0.00 0.00 ] +Key: VPROLDZmi: [ 0.00 0.00 ] +Key: VPROLDZmik: [ 0.00 0.00 ] +Key: VPROLDZmikz: [ 0.00 0.00 ] +Key: VPROLDZri: [ 0.00 0.00 ] +Key: VPROLDZrik: [ 0.00 0.00 ] +Key: VPROLDZrikz: [ 0.00 0.00 ] +Key: VPROLQZ: [ 0.00 0.00 ] +Key: VPROLQZmbi: [ 0.00 0.00 ] +Key: VPROLQZmbik: [ 0.00 0.00 ] +Key: VPROLQZmbikz: [ 0.00 0.00 ] +Key: VPROLQZmi: [ 0.00 0.00 ] +Key: VPROLQZmik: [ 0.00 0.00 ] +Key: VPROLQZmikz: [ 0.00 0.00 ] +Key: VPROLQZri: [ 0.00 0.00 ] +Key: VPROLQZrik: [ 0.00 0.00 ] +Key: VPROLQZrikz: [ 0.00 0.00 ] +Key: VPROLVDZ: [ 0.00 0.00 ] +Key: VPROLVDZrm: [ 0.00 0.00 ] +Key: VPROLVDZrmb: [ 0.00 0.00 ] +Key: VPROLVDZrmbk: [ 0.00 0.00 ] +Key: VPROLVDZrmbkz: [ 0.00 0.00 ] +Key: VPROLVDZrmk: [ 0.00 0.00 ] +Key: VPROLVDZrmkz: [ 0.00 0.00 ] +Key: VPROLVDZrr: [ 0.00 0.00 ] +Key: VPROLVDZrrk: [ 0.00 0.00 ] +Key: VPROLVDZrrkz: [ 0.00 0.00 ] +Key: VPROLVQZ: [ 0.00 0.00 ] +Key: VPROLVQZrm: [ 0.00 0.00 ] +Key: VPROLVQZrmb: [ 0.00 0.00 ] +Key: VPROLVQZrmbk: [ 0.00 0.00 ] +Key: VPROLVQZrmbkz: [ 0.00 0.00 ] +Key: VPROLVQZrmk: [ 0.00 0.00 ] +Key: VPROLVQZrmkz: [ 0.00 0.00 ] +Key: VPROLVQZrr: [ 0.00 0.00 ] +Key: VPROLVQZrrk: [ 0.00 0.00 ] +Key: VPROLVQZrrkz: [ 0.00 0.00 ] +Key: VPRORDZ: [ 0.00 0.00 ] +Key: VPRORDZmbi: [ 0.00 0.00 ] +Key: VPRORDZmbik: [ 0.00 0.00 ] +Key: VPRORDZmbikz: [ 0.00 0.00 ] +Key: VPRORDZmi: [ 0.00 0.00 ] +Key: VPRORDZmik: [ 0.00 0.00 ] +Key: VPRORDZmikz: [ 0.00 0.00 ] +Key: VPRORDZri: [ 0.00 0.00 ] +Key: VPRORDZrik: [ 0.00 0.00 ] +Key: VPRORDZrikz: [ 0.00 0.00 ] +Key: VPRORQZ: [ 0.00 0.00 ] +Key: VPRORQZmbi: [ 0.00 0.00 ] +Key: VPRORQZmbik: [ 0.00 0.00 ] +Key: VPRORQZmbikz: [ 0.00 0.00 ] +Key: VPRORQZmi: [ 0.00 0.00 ] +Key: VPRORQZmik: [ 0.00 0.00 ] +Key: VPRORQZmikz: [ 0.00 0.00 ] +Key: VPRORQZri: [ 0.00 0.00 ] +Key: VPRORQZrik: [ 0.00 0.00 ] +Key: VPRORQZrikz: [ 0.00 0.00 ] +Key: VPRORVDZ: [ 0.00 0.00 ] +Key: VPRORVDZrm: [ 0.00 0.00 ] +Key: VPRORVDZrmb: [ 0.00 0.00 ] +Key: VPRORVDZrmbk: [ 0.00 0.00 ] +Key: VPRORVDZrmbkz: [ 0.00 0.00 ] +Key: VPRORVDZrmk: [ 0.00 0.00 ] +Key: VPRORVDZrmkz: [ 0.00 0.00 ] +Key: VPRORVDZrr: [ 0.00 0.00 ] +Key: VPRORVDZrrk: [ 0.00 0.00 ] +Key: VPRORVDZrrkz: [ 0.00 0.00 ] +Key: VPRORVQZ: [ 0.00 0.00 ] +Key: VPRORVQZrm: [ 0.00 0.00 ] +Key: VPRORVQZrmb: [ 0.00 0.00 ] +Key: VPRORVQZrmbk: [ 0.00 0.00 ] +Key: VPRORVQZrmbkz: [ 0.00 0.00 ] +Key: VPRORVQZrmk: [ 0.00 0.00 ] +Key: VPRORVQZrmkz: [ 0.00 0.00 ] +Key: VPRORVQZrr: [ 0.00 0.00 ] +Key: VPRORVQZrrk: [ 0.00 0.00 ] +Key: VPRORVQZrrkz: [ 0.00 0.00 ] +Key: VPROTBmi: [ 0.00 0.00 ] +Key: VPROTBmr: [ 0.00 0.00 ] +Key: VPROTBri: [ 0.00 0.00 ] +Key: VPROTBrm: [ 0.00 0.00 ] +Key: VPROTBrr: [ 0.00 0.00 ] +Key: VPROTBrr_REV: [ 0.00 0.00 ] +Key: VPROTDmi: [ 0.00 0.00 ] +Key: VPROTDmr: [ 0.00 0.00 ] +Key: VPROTDri: [ 0.00 0.00 ] +Key: VPROTDrm: [ 0.00 0.00 ] +Key: VPROTDrr: [ 0.00 0.00 ] +Key: VPROTDrr_REV: [ 0.00 0.00 ] +Key: VPROTQmi: [ 0.00 0.00 ] +Key: VPROTQmr: [ 0.00 0.00 ] +Key: VPROTQri: [ 0.00 0.00 ] +Key: VPROTQrm: [ 0.00 0.00 ] +Key: VPROTQrr: [ 0.00 0.00 ] +Key: VPROTQrr_REV: [ 0.00 0.00 ] +Key: VPROTWmi: [ 0.00 0.00 ] +Key: VPROTWmr: [ 0.00 0.00 ] +Key: VPROTWri: [ 0.00 0.00 ] +Key: VPROTWrm: [ 0.00 0.00 ] +Key: VPROTWrr: [ 0.00 0.00 ] +Key: VPROTWrr_REV: [ 0.00 0.00 ] +Key: VPSADBWYrm: [ 0.00 0.00 ] +Key: VPSADBWYrr: [ 0.00 0.00 ] +Key: VPSADBWZ: [ 0.00 0.00 ] +Key: VPSADBWZrm: [ 0.00 0.00 ] +Key: VPSADBWZrr: [ 0.00 0.00 ] +Key: VPSADBWrm: [ 0.00 0.00 ] +Key: VPSADBWrr: [ 0.00 0.00 ] +Key: VPSCATTERDDZ: [ 0.00 0.00 ] +Key: VPSCATTERDDZmr: [ 0.00 0.00 ] +Key: VPSCATTERDQZ: [ 0.00 0.00 ] +Key: VPSCATTERDQZmr: [ 0.00 0.00 ] +Key: VPSCATTERQDZ: [ 0.00 0.00 ] +Key: VPSCATTERQDZmr: [ 0.00 0.00 ] +Key: VPSCATTERQQZ: [ 0.00 0.00 ] +Key: VPSCATTERQQZmr: [ 0.00 0.00 ] +Key: VPSHABmr: [ 0.00 0.00 ] +Key: VPSHABrm: [ 0.00 0.00 ] +Key: VPSHABrr: [ 0.00 0.00 ] +Key: VPSHABrr_REV: [ 0.00 0.00 ] +Key: VPSHADmr: [ 0.00 0.00 ] +Key: VPSHADrm: [ 0.00 0.00 ] +Key: VPSHADrr: [ 0.00 0.00 ] +Key: VPSHADrr_REV: [ 0.00 0.00 ] +Key: VPSHAQmr: [ 0.00 0.00 ] +Key: VPSHAQrm: [ 0.00 0.00 ] +Key: VPSHAQrr: [ 0.00 0.00 ] +Key: VPSHAQrr_REV: [ 0.00 0.00 ] +Key: VPSHAWmr: [ 0.00 0.00 ] +Key: VPSHAWrm: [ 0.00 0.00 ] +Key: VPSHAWrr: [ 0.00 0.00 ] +Key: VPSHAWrr_REV: [ 0.00 0.00 ] +Key: VPSHLBmr: [ 0.00 0.00 ] +Key: VPSHLBrm: [ 0.00 0.00 ] +Key: VPSHLBrr: [ 0.00 0.00 ] +Key: VPSHLBrr_REV: [ 0.00 0.00 ] +Key: VPSHLDDZ: [ 0.00 0.00 ] +Key: VPSHLDDZrmbi: [ 0.00 0.00 ] +Key: VPSHLDDZrmbik: [ 0.00 0.00 ] +Key: VPSHLDDZrmbikz: [ 0.00 0.00 ] +Key: VPSHLDDZrmi: [ 0.00 0.00 ] +Key: VPSHLDDZrmik: [ 0.00 0.00 ] +Key: VPSHLDDZrmikz: [ 0.00 0.00 ] +Key: VPSHLDDZrri: [ 0.00 0.00 ] +Key: VPSHLDDZrrik: [ 0.00 0.00 ] +Key: VPSHLDDZrrikz: [ 0.00 0.00 ] +Key: VPSHLDQZ: [ 0.00 0.00 ] +Key: VPSHLDQZrmbi: [ 0.00 0.00 ] +Key: VPSHLDQZrmbik: [ 0.00 0.00 ] +Key: VPSHLDQZrmbikz: [ 0.00 0.00 ] +Key: VPSHLDQZrmi: [ 0.00 0.00 ] +Key: VPSHLDQZrmik: [ 0.00 0.00 ] +Key: VPSHLDQZrmikz: [ 0.00 0.00 ] +Key: VPSHLDQZrri: [ 0.00 0.00 ] +Key: VPSHLDQZrrik: [ 0.00 0.00 ] +Key: VPSHLDQZrrikz: [ 0.00 0.00 ] +Key: VPSHLDVDZ: [ 0.00 0.00 ] +Key: VPSHLDVDZm: [ 0.00 0.00 ] +Key: VPSHLDVDZmb: [ 0.00 0.00 ] +Key: VPSHLDVDZmbk: [ 0.00 0.00 ] +Key: VPSHLDVDZmbkz: [ 0.00 0.00 ] +Key: VPSHLDVDZmk: [ 0.00 0.00 ] +Key: VPSHLDVDZmkz: [ 0.00 0.00 ] +Key: VPSHLDVDZr: [ 0.00 0.00 ] +Key: VPSHLDVDZrk: [ 0.00 0.00 ] +Key: VPSHLDVDZrkz: [ 0.00 0.00 ] +Key: VPSHLDVQZ: [ 0.00 0.00 ] +Key: VPSHLDVQZm: [ 0.00 0.00 ] +Key: VPSHLDVQZmb: [ 0.00 0.00 ] +Key: VPSHLDVQZmbk: [ 0.00 0.00 ] +Key: VPSHLDVQZmbkz: [ 0.00 0.00 ] +Key: VPSHLDVQZmk: [ 0.00 0.00 ] +Key: VPSHLDVQZmkz: [ 0.00 0.00 ] +Key: VPSHLDVQZr: [ 0.00 0.00 ] +Key: VPSHLDVQZrk: [ 0.00 0.00 ] +Key: VPSHLDVQZrkz: [ 0.00 0.00 ] +Key: VPSHLDVWZ: [ 0.00 0.00 ] +Key: VPSHLDVWZm: [ 0.00 0.00 ] +Key: VPSHLDVWZmk: [ 0.00 0.00 ] +Key: VPSHLDVWZmkz: [ 0.00 0.00 ] +Key: VPSHLDVWZr: [ 0.00 0.00 ] +Key: VPSHLDVWZrk: [ 0.00 0.00 ] +Key: VPSHLDVWZrkz: [ 0.00 0.00 ] +Key: VPSHLDWZ: [ 0.00 0.00 ] +Key: VPSHLDWZrmi: [ 0.00 0.00 ] +Key: VPSHLDWZrmik: [ 0.00 0.00 ] +Key: VPSHLDWZrmikz: [ 0.00 0.00 ] +Key: VPSHLDWZrri: [ 0.00 0.00 ] +Key: VPSHLDWZrrik: [ 0.00 0.00 ] +Key: VPSHLDWZrrikz: [ 0.00 0.00 ] +Key: VPSHLDmr: [ 0.00 0.00 ] +Key: VPSHLDrm: [ 0.00 0.00 ] +Key: VPSHLDrr: [ 0.00 0.00 ] +Key: VPSHLDrr_REV: [ 0.00 0.00 ] +Key: VPSHLQmr: [ 0.00 0.00 ] +Key: VPSHLQrm: [ 0.00 0.00 ] +Key: VPSHLQrr: [ 0.00 0.00 ] +Key: VPSHLQrr_REV: [ 0.00 0.00 ] +Key: VPSHLWmr: [ 0.00 0.00 ] +Key: VPSHLWrm: [ 0.00 0.00 ] +Key: VPSHLWrr: [ 0.00 0.00 ] +Key: VPSHLWrr_REV: [ 0.00 0.00 ] +Key: VPSHRDDZ: [ 0.00 0.00 ] +Key: VPSHRDDZrmbi: [ 0.00 0.00 ] +Key: VPSHRDDZrmbik: [ 0.00 0.00 ] +Key: VPSHRDDZrmbikz: [ 0.00 0.00 ] +Key: VPSHRDDZrmi: [ 0.00 0.00 ] +Key: VPSHRDDZrmik: [ 0.00 0.00 ] +Key: VPSHRDDZrmikz: [ 0.00 0.00 ] +Key: VPSHRDDZrri: [ 0.00 0.00 ] +Key: VPSHRDDZrrik: [ 0.00 0.00 ] +Key: VPSHRDDZrrikz: [ 0.00 0.00 ] +Key: VPSHRDQZ: [ 0.00 0.00 ] +Key: VPSHRDQZrmbi: [ 0.00 0.00 ] +Key: VPSHRDQZrmbik: [ 0.00 0.00 ] +Key: VPSHRDQZrmbikz: [ 0.00 0.00 ] +Key: VPSHRDQZrmi: [ 0.00 0.00 ] +Key: VPSHRDQZrmik: [ 0.00 0.00 ] +Key: VPSHRDQZrmikz: [ 0.00 0.00 ] +Key: VPSHRDQZrri: [ 0.00 0.00 ] +Key: VPSHRDQZrrik: [ 0.00 0.00 ] +Key: VPSHRDQZrrikz: [ 0.00 0.00 ] +Key: VPSHRDVDZ: [ 0.00 0.00 ] +Key: VPSHRDVDZm: [ 0.00 0.00 ] +Key: VPSHRDVDZmb: [ 0.00 0.00 ] +Key: VPSHRDVDZmbk: [ 0.00 0.00 ] +Key: VPSHRDVDZmbkz: [ 0.00 0.00 ] +Key: VPSHRDVDZmk: [ 0.00 0.00 ] +Key: VPSHRDVDZmkz: [ 0.00 0.00 ] +Key: VPSHRDVDZr: [ 0.00 0.00 ] +Key: VPSHRDVDZrk: [ 0.00 0.00 ] +Key: VPSHRDVDZrkz: [ 0.00 0.00 ] +Key: VPSHRDVQZ: [ 0.00 0.00 ] +Key: VPSHRDVQZm: [ 0.00 0.00 ] +Key: VPSHRDVQZmb: [ 0.00 0.00 ] +Key: VPSHRDVQZmbk: [ 0.00 0.00 ] +Key: VPSHRDVQZmbkz: [ 0.00 0.00 ] +Key: VPSHRDVQZmk: [ 0.00 0.00 ] +Key: VPSHRDVQZmkz: [ 0.00 0.00 ] +Key: VPSHRDVQZr: [ 0.00 0.00 ] +Key: VPSHRDVQZrk: [ 0.00 0.00 ] +Key: VPSHRDVQZrkz: [ 0.00 0.00 ] +Key: VPSHRDVWZ: [ 0.00 0.00 ] +Key: VPSHRDVWZm: [ 0.00 0.00 ] +Key: VPSHRDVWZmk: [ 0.00 0.00 ] +Key: VPSHRDVWZmkz: [ 0.00 0.00 ] +Key: VPSHRDVWZr: [ 0.00 0.00 ] +Key: VPSHRDVWZrk: [ 0.00 0.00 ] +Key: VPSHRDVWZrkz: [ 0.00 0.00 ] +Key: VPSHRDWZ: [ 0.00 0.00 ] +Key: VPSHRDWZrmi: [ 0.00 0.00 ] +Key: VPSHRDWZrmik: [ 0.00 0.00 ] +Key: VPSHRDWZrmikz: [ 0.00 0.00 ] +Key: VPSHRDWZrri: [ 0.00 0.00 ] +Key: VPSHRDWZrrik: [ 0.00 0.00 ] +Key: VPSHRDWZrrikz: [ 0.00 0.00 ] +Key: VPSHUFBITQMBZ: [ 0.00 0.00 ] +Key: VPSHUFBITQMBZrm: [ 0.00 0.00 ] +Key: VPSHUFBITQMBZrmk: [ 0.00 0.00 ] +Key: VPSHUFBITQMBZrr: [ 0.00 0.00 ] +Key: VPSHUFBITQMBZrrk: [ 0.00 0.00 ] +Key: VPSHUFBYrm: [ 0.00 0.00 ] +Key: VPSHUFBYrr: [ 0.00 0.00 ] +Key: VPSHUFBZ: [ 0.00 0.00 ] +Key: VPSHUFBZrm: [ 0.00 0.00 ] +Key: VPSHUFBZrmk: [ 0.00 0.00 ] +Key: VPSHUFBZrmkz: [ 0.00 0.00 ] +Key: VPSHUFBZrr: [ 0.00 0.00 ] +Key: VPSHUFBZrrk: [ 0.00 0.00 ] +Key: VPSHUFBZrrkz: [ 0.00 0.00 ] +Key: VPSHUFBrm: [ 0.00 0.00 ] +Key: VPSHUFBrr: [ 0.00 0.00 ] +Key: VPSHUFDYmi: [ 0.00 0.00 ] +Key: VPSHUFDYri: [ 0.00 0.00 ] +Key: VPSHUFDZ: [ 0.00 0.00 ] +Key: VPSHUFDZmbi: [ 0.00 0.00 ] +Key: VPSHUFDZmbik: [ 0.00 0.00 ] +Key: VPSHUFDZmbikz: [ 0.00 0.00 ] +Key: VPSHUFDZmi: [ 0.00 0.00 ] +Key: VPSHUFDZmik: [ 0.00 0.00 ] +Key: VPSHUFDZmikz: [ 0.00 0.00 ] +Key: VPSHUFDZri: [ 0.00 0.00 ] +Key: VPSHUFDZrik: [ 0.00 0.00 ] +Key: VPSHUFDZrikz: [ 0.00 0.00 ] +Key: VPSHUFDmi: [ 0.00 0.00 ] +Key: VPSHUFDri: [ 0.00 0.00 ] +Key: VPSHUFHWYmi: [ 0.00 0.00 ] +Key: VPSHUFHWYri: [ 0.00 0.00 ] +Key: VPSHUFHWZ: [ 0.00 0.00 ] +Key: VPSHUFHWZmi: [ 0.00 0.00 ] +Key: VPSHUFHWZmik: [ 0.00 0.00 ] +Key: VPSHUFHWZmikz: [ 0.00 0.00 ] +Key: VPSHUFHWZri: [ 0.00 0.00 ] +Key: VPSHUFHWZrik: [ 0.00 0.00 ] +Key: VPSHUFHWZrikz: [ 0.00 0.00 ] +Key: VPSHUFHWmi: [ 0.00 0.00 ] +Key: VPSHUFHWri: [ 0.00 0.00 ] +Key: VPSHUFLWYmi: [ 0.00 0.00 ] +Key: VPSHUFLWYri: [ 0.00 0.00 ] +Key: VPSHUFLWZ: [ 0.00 0.00 ] +Key: VPSHUFLWZmi: [ 0.00 0.00 ] +Key: VPSHUFLWZmik: [ 0.00 0.00 ] +Key: VPSHUFLWZmikz: [ 0.00 0.00 ] +Key: VPSHUFLWZri: [ 0.00 0.00 ] +Key: VPSHUFLWZrik: [ 0.00 0.00 ] +Key: VPSHUFLWZrikz: [ 0.00 0.00 ] +Key: VPSHUFLWmi: [ 0.00 0.00 ] +Key: VPSHUFLWri: [ 0.00 0.00 ] +Key: VPSIGNBYrm: [ 0.00 0.00 ] +Key: VPSIGNBYrr: [ 0.00 0.00 ] +Key: VPSIGNBrm: [ 0.00 0.00 ] +Key: VPSIGNBrr: [ 0.00 0.00 ] +Key: VPSIGNDYrm: [ 0.00 0.00 ] +Key: VPSIGNDYrr: [ 0.00 0.00 ] +Key: VPSIGNDrm: [ 0.00 0.00 ] +Key: VPSIGNDrr: [ 0.00 0.00 ] +Key: VPSIGNWYrm: [ 0.00 0.00 ] +Key: VPSIGNWYrr: [ 0.00 0.00 ] +Key: VPSIGNWrm: [ 0.00 0.00 ] +Key: VPSIGNWrr: [ 0.00 0.00 ] +Key: VPSLLDQYri: [ 0.00 0.00 ] +Key: VPSLLDQZ: [ 0.00 0.00 ] +Key: VPSLLDQZmi: [ 0.00 0.00 ] +Key: VPSLLDQZri: [ 0.00 0.00 ] +Key: VPSLLDQri: [ 0.00 0.00 ] +Key: VPSLLDYri: [ 0.00 0.00 ] +Key: VPSLLDYrm: [ 0.00 0.00 ] +Key: VPSLLDYrr: [ 0.00 0.00 ] +Key: VPSLLDZ: [ 0.00 0.00 ] +Key: VPSLLDZmbi: [ 0.00 0.00 ] +Key: VPSLLDZmbik: [ 0.00 0.00 ] +Key: VPSLLDZmbikz: [ 0.00 0.00 ] +Key: VPSLLDZmi: [ 0.00 0.00 ] +Key: VPSLLDZmik: [ 0.00 0.00 ] +Key: VPSLLDZmikz: [ 0.00 0.00 ] +Key: VPSLLDZri: [ 0.00 0.00 ] +Key: VPSLLDZrik: [ 0.00 0.00 ] +Key: VPSLLDZrikz: [ 0.00 0.00 ] +Key: VPSLLDZrm: [ 0.00 0.00 ] +Key: VPSLLDZrmk: [ 0.00 0.00 ] +Key: VPSLLDZrmkz: [ 0.00 0.00 ] +Key: VPSLLDZrr: [ 0.00 0.00 ] +Key: VPSLLDZrrk: [ 0.00 0.00 ] +Key: VPSLLDZrrkz: [ 0.00 0.00 ] +Key: VPSLLDri: [ 0.00 0.00 ] +Key: VPSLLDrm: [ 0.00 0.00 ] +Key: VPSLLDrr: [ 0.00 0.00 ] +Key: VPSLLQYri: [ 0.00 0.00 ] +Key: VPSLLQYrm: [ 0.00 0.00 ] +Key: VPSLLQYrr: [ 0.00 0.00 ] +Key: VPSLLQZ: [ 0.00 0.00 ] +Key: VPSLLQZmbi: [ 0.00 0.00 ] +Key: VPSLLQZmbik: [ 0.00 0.00 ] +Key: VPSLLQZmbikz: [ 0.00 0.00 ] +Key: VPSLLQZmi: [ 0.00 0.00 ] +Key: VPSLLQZmik: [ 0.00 0.00 ] +Key: VPSLLQZmikz: [ 0.00 0.00 ] +Key: VPSLLQZri: [ 0.00 0.00 ] +Key: VPSLLQZrik: [ 0.00 0.00 ] +Key: VPSLLQZrikz: [ 0.00 0.00 ] +Key: VPSLLQZrm: [ 0.00 0.00 ] +Key: VPSLLQZrmk: [ 0.00 0.00 ] +Key: VPSLLQZrmkz: [ 0.00 0.00 ] +Key: VPSLLQZrr: [ 0.00 0.00 ] +Key: VPSLLQZrrk: [ 0.00 0.00 ] +Key: VPSLLQZrrkz: [ 0.00 0.00 ] +Key: VPSLLQri: [ 0.00 0.00 ] +Key: VPSLLQrm: [ 0.00 0.00 ] +Key: VPSLLQrr: [ 0.00 0.00 ] +Key: VPSLLVDYrm: [ 0.00 0.00 ] +Key: VPSLLVDYrr: [ 0.00 0.00 ] +Key: VPSLLVDZ: [ 0.00 0.00 ] +Key: VPSLLVDZrm: [ 0.00 0.00 ] +Key: VPSLLVDZrmb: [ 0.00 0.00 ] +Key: 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VRANGESSZrribkz: [ 0.00 0.00 ] +Key: VRANGESSZrrik: [ 0.00 0.00 ] +Key: VRANGESSZrrikz: [ 0.00 0.00 ] +Key: VRCP: [ 0.00 0.00 ] +Key: VRCPBF: [ 0.00 0.00 ] +Key: VRCPPHZ: [ 0.00 0.00 ] +Key: VRCPPHZm: [ 0.00 0.00 ] +Key: VRCPPHZmb: [ 0.00 0.00 ] +Key: VRCPPHZmbk: [ 0.00 0.00 ] +Key: VRCPPHZmbkz: [ 0.00 0.00 ] +Key: VRCPPHZmk: [ 0.00 0.00 ] +Key: VRCPPHZmkz: [ 0.00 0.00 ] +Key: VRCPPHZr: [ 0.00 0.00 ] +Key: VRCPPHZrk: [ 0.00 0.00 ] +Key: VRCPPHZrkz: [ 0.00 0.00 ] +Key: VRCPPSYm: [ 0.00 0.00 ] +Key: VRCPPSYr: [ 0.00 0.00 ] +Key: VRCPPSm: [ 0.00 0.00 ] +Key: VRCPPSr: [ 0.00 0.00 ] +Key: VRCPSHZrm: [ 0.00 0.00 ] +Key: VRCPSHZrmk: [ 0.00 0.00 ] +Key: VRCPSHZrmkz: [ 0.00 0.00 ] +Key: VRCPSHZrr: [ 0.00 0.00 ] +Key: VRCPSHZrrk: [ 0.00 0.00 ] +Key: VRCPSHZrrkz: [ 0.00 0.00 ] +Key: VRCPSSm: [ 0.00 0.00 ] +Key: VRCPSSm_Int: [ 0.00 0.00 ] +Key: VRCPSSr: [ 0.00 0.00 ] +Key: VRCPSSr_Int: [ 0.00 0.00 ] +Key: VREDUCEBF: [ 0.00 0.00 ] +Key: VREDUCEPDZ: [ 0.00 0.00 ] +Key: VREDUCEPDZrmbi: [ 0.00 0.00 ] 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VSUBSDZrmkz_Int: [ 0.00 0.00 ] +Key: VSUBSDZrr: [ 0.00 0.00 ] +Key: VSUBSDZrr_Int: [ 0.00 0.00 ] +Key: VSUBSDZrrb_Int: [ 0.00 0.00 ] +Key: VSUBSDZrrbk_Int: [ 0.00 0.00 ] +Key: VSUBSDZrrbkz_Int: [ 0.00 0.00 ] +Key: VSUBSDZrrk_Int: [ 0.00 0.00 ] +Key: VSUBSDZrrkz_Int: [ 0.00 0.00 ] +Key: VSUBSDrm: [ 0.00 0.00 ] +Key: VSUBSDrm_Int: [ 0.00 0.00 ] +Key: VSUBSDrr: [ 0.00 0.00 ] +Key: VSUBSDrr_Int: [ 0.00 0.00 ] +Key: VSUBSHZrm: [ 0.00 0.00 ] +Key: VSUBSHZrm_Int: [ 0.00 0.00 ] +Key: VSUBSHZrmk_Int: [ 0.00 0.00 ] +Key: VSUBSHZrmkz_Int: [ 0.00 0.00 ] +Key: VSUBSHZrr: [ 0.00 0.00 ] +Key: VSUBSHZrr_Int: [ 0.00 0.00 ] +Key: VSUBSHZrrb_Int: [ 0.00 0.00 ] +Key: VSUBSHZrrbk_Int: [ 0.00 0.00 ] +Key: VSUBSHZrrbkz_Int: [ 0.00 0.00 ] +Key: VSUBSHZrrk_Int: [ 0.00 0.00 ] +Key: VSUBSHZrrkz_Int: [ 0.00 0.00 ] +Key: VSUBSSZrm: [ 0.00 0.00 ] +Key: VSUBSSZrm_Int: [ 0.00 0.00 ] +Key: VSUBSSZrmk_Int: [ 0.00 0.00 ] +Key: VSUBSSZrmkz_Int: [ 0.00 0.00 ] +Key: VSUBSSZrr: [ 0.00 0.00 ] +Key: VSUBSSZrr_Int: [ 0.00 0.00 ] +Key: VSUBSSZrrb_Int: [ 0.00 0.00 ] +Key: VSUBSSZrrbk_Int: [ 0.00 0.00 ] +Key: VSUBSSZrrbkz_Int: [ 0.00 0.00 ] +Key: VSUBSSZrrk_Int: [ 0.00 0.00 ] +Key: VSUBSSZrrkz_Int: [ 0.00 0.00 ] +Key: VSUBSSrm: [ 0.00 0.00 ] +Key: VSUBSSrm_Int: [ 0.00 0.00 ] +Key: VSUBSSrr: [ 0.00 0.00 ] +Key: VSUBSSrr_Int: [ 0.00 0.00 ] +Key: VTESTPDYrm: [ 0.00 0.00 ] +Key: VTESTPDYrr: [ 0.00 0.00 ] +Key: VTESTPDrm: [ 0.00 0.00 ] +Key: VTESTPDrr: [ 0.00 0.00 ] +Key: VTESTPSYrm: [ 0.00 0.00 ] +Key: VTESTPSYrr: [ 0.00 0.00 ] +Key: VTESTPSrm: [ 0.00 0.00 ] +Key: VTESTPSrr: [ 0.00 0.00 ] +Key: VUCOMISDZrm: [ 0.00 0.00 ] +Key: VUCOMISDZrm_Int: [ 0.00 0.00 ] +Key: VUCOMISDZrr: [ 0.00 0.00 ] +Key: VUCOMISDZrr_Int: [ 0.00 0.00 ] +Key: VUCOMISDZrrb: [ 0.00 0.00 ] +Key: VUCOMISDrm: [ 0.00 0.00 ] +Key: VUCOMISDrm_Int: [ 0.00 0.00 ] +Key: VUCOMISDrr: [ 0.00 0.00 ] +Key: VUCOMISDrr_Int: [ 0.00 0.00 ] +Key: VUCOMISHZrm: [ 0.00 0.00 ] +Key: VUCOMISHZrm_Int: [ 0.00 0.00 ] +Key: VUCOMISHZrr: [ 0.00 0.00 ] +Key: VUCOMISHZrr_Int: [ 0.00 0.00 ] +Key: VUCOMISHZrrb: [ 0.00 0.00 ] +Key: VUCOMISSZrm: [ 0.00 0.00 ] +Key: VUCOMISSZrm_Int: [ 0.00 0.00 ] +Key: VUCOMISSZrr: [ 0.00 0.00 ] +Key: VUCOMISSZrr_Int: [ 0.00 0.00 ] +Key: VUCOMISSZrrb: [ 0.00 0.00 ] +Key: VUCOMISSrm: [ 0.00 0.00 ] +Key: VUCOMISSrm_Int: [ 0.00 0.00 ] +Key: VUCOMISSrr: [ 0.00 0.00 ] +Key: VUCOMISSrr_Int: [ 0.00 0.00 ] +Key: VUCOMXSDZrm: [ 0.00 0.00 ] +Key: VUCOMXSDZrm_Int: [ 0.00 0.00 ] +Key: VUCOMXSDZrr: [ 0.00 0.00 ] +Key: VUCOMXSDZrr_Int: [ 0.00 0.00 ] +Key: VUCOMXSDZrrb_Int: [ 0.00 0.00 ] +Key: VUCOMXSHZrm: [ 0.00 0.00 ] +Key: VUCOMXSHZrm_Int: [ 0.00 0.00 ] +Key: VUCOMXSHZrr: [ 0.00 0.00 ] +Key: VUCOMXSHZrr_Int: [ 0.00 0.00 ] +Key: VUCOMXSHZrrb_Int: [ 0.00 0.00 ] +Key: VUCOMXSSZrm: [ 0.00 0.00 ] +Key: VUCOMXSSZrm_Int: [ 0.00 0.00 ] +Key: VUCOMXSSZrr: [ 0.00 0.00 ] +Key: VUCOMXSSZrr_Int: [ 0.00 0.00 ] +Key: VUCOMXSSZrrb_Int: [ 0.00 0.00 ] +Key: VUNPCKHPDYrm: [ 0.00 0.00 ] +Key: VUNPCKHPDYrr: [ 0.00 0.00 ] +Key: VUNPCKHPDZ: [ 0.00 0.00 ] +Key: VUNPCKHPDZrm: [ 0.00 0.00 ] +Key: VUNPCKHPDZrmb: [ 0.00 0.00 ] +Key: VUNPCKHPDZrmbk: [ 0.00 0.00 ] +Key: VUNPCKHPDZrmbkz: [ 0.00 0.00 ] +Key: VUNPCKHPDZrmk: [ 0.00 0.00 ] +Key: VUNPCKHPDZrmkz: [ 0.00 0.00 ] +Key: VUNPCKHPDZrr: [ 0.00 0.00 ] +Key: VUNPCKHPDZrrk: [ 0.00 0.00 ] +Key: VUNPCKHPDZrrkz: [ 0.00 0.00 ] +Key: VUNPCKHPDrm: [ 0.00 0.00 ] +Key: VUNPCKHPDrr: [ 0.00 0.00 ] +Key: VUNPCKHPSYrm: [ 0.00 0.00 ] +Key: VUNPCKHPSYrr: [ 0.00 0.00 ] +Key: VUNPCKHPSZ: [ 0.00 0.00 ] +Key: VUNPCKHPSZrm: [ 0.00 0.00 ] +Key: VUNPCKHPSZrmb: [ 0.00 0.00 ] +Key: VUNPCKHPSZrmbk: [ 0.00 0.00 ] +Key: VUNPCKHPSZrmbkz: [ 0.00 0.00 ] +Key: VUNPCKHPSZrmk: [ 0.00 0.00 ] +Key: VUNPCKHPSZrmkz: [ 0.00 0.00 ] +Key: VUNPCKHPSZrr: [ 0.00 0.00 ] +Key: VUNPCKHPSZrrk: [ 0.00 0.00 ] +Key: VUNPCKHPSZrrkz: [ 0.00 0.00 ] +Key: VUNPCKHPSrm: [ 0.00 0.00 ] +Key: VUNPCKHPSrr: [ 0.00 0.00 ] +Key: VUNPCKLPDYrm: [ 0.00 0.00 ] +Key: VUNPCKLPDYrr: [ 0.00 0.00 ] +Key: VUNPCKLPDZ: [ 0.00 0.00 ] +Key: VUNPCKLPDZrm: [ 0.00 0.00 ] +Key: VUNPCKLPDZrmb: [ 0.00 0.00 ] +Key: VUNPCKLPDZrmbk: [ 0.00 0.00 ] +Key: VUNPCKLPDZrmbkz: [ 0.00 0.00 ] +Key: VUNPCKLPDZrmk: [ 0.00 0.00 ] +Key: VUNPCKLPDZrmkz: [ 0.00 0.00 ] +Key: VUNPCKLPDZrr: [ 0.00 0.00 ] +Key: VUNPCKLPDZrrk: [ 0.00 0.00 ] +Key: VUNPCKLPDZrrkz: [ 0.00 0.00 ] +Key: VUNPCKLPDrm: [ 0.00 0.00 ] +Key: VUNPCKLPDrr: [ 0.00 0.00 ] +Key: VUNPCKLPSYrm: [ 0.00 0.00 ] +Key: VUNPCKLPSYrr: [ 0.00 0.00 ] +Key: VUNPCKLPSZ: [ 0.00 0.00 ] +Key: VUNPCKLPSZrm: [ 0.00 0.00 ] +Key: VUNPCKLPSZrmb: [ 0.00 0.00 ] +Key: VUNPCKLPSZrmbk: [ 0.00 0.00 ] +Key: VUNPCKLPSZrmbkz: [ 0.00 0.00 ] +Key: VUNPCKLPSZrmk: [ 0.00 0.00 ] +Key: VUNPCKLPSZrmkz: [ 0.00 0.00 ] +Key: VUNPCKLPSZrr: [ 0.00 0.00 ] +Key: VUNPCKLPSZrrk: [ 0.00 0.00 ] +Key: VUNPCKLPSZrrkz: [ 0.00 0.00 ] +Key: VUNPCKLPSrm: [ 0.00 0.00 ] +Key: VUNPCKLPSrr: [ 0.00 0.00 ] +Key: VXORPDYrm: [ 0.00 0.00 ] +Key: VXORPDYrr: [ 0.00 0.00 ] +Key: VXORPDZ: [ 0.00 0.00 ] +Key: VXORPDZrm: [ 0.00 0.00 ] +Key: VXORPDZrmb: [ 0.00 0.00 ] +Key: VXORPDZrmbk: [ 0.00 0.00 ] +Key: VXORPDZrmbkz: [ 0.00 0.00 ] +Key: VXORPDZrmk: [ 0.00 0.00 ] +Key: VXORPDZrmkz: [ 0.00 0.00 ] +Key: VXORPDZrr: [ 0.00 0.00 ] +Key: VXORPDZrrk: [ 0.00 0.00 ] +Key: VXORPDZrrkz: [ 0.00 0.00 ] +Key: VXORPDrm: [ 0.00 0.00 ] +Key: VXORPDrr: [ 0.00 0.00 ] +Key: VXORPSYrm: [ 0.00 0.00 ] +Key: VXORPSYrr: [ 0.00 0.00 ] +Key: VXORPSZ: [ 0.00 0.00 ] +Key: VXORPSZrm: [ 0.00 0.00 ] +Key: VXORPSZrmb: [ 0.00 0.00 ] +Key: VXORPSZrmbk: [ 0.00 0.00 ] +Key: VXORPSZrmbkz: [ 0.00 0.00 ] +Key: VXORPSZrmk: [ 0.00 0.00 ] +Key: VXORPSZrmkz: [ 0.00 0.00 ] +Key: VXORPSZrr: [ 0.00 0.00 ] +Key: VXORPSZrrk: [ 0.00 0.00 ] +Key: VXORPSZrrkz: [ 0.00 0.00 ] +Key: VXORPSrm: [ 0.00 0.00 ] +Key: VXORPSrr: [ 0.00 0.00 ] +Key: VZEROALL: [ 0.00 0.00 ] +Key: VZEROUPPER: [ 0.00 0.00 ] +Key: V_SET: [ 0.00 0.00 ] +Key: V_SETALLONES: [ 0.00 0.00 ] +Key: WAIT: [ 0.00 0.00 ] +Key: WBINVD: [ 0.00 0.00 ] +Key: WBNOINVD: [ 0.00 0.00 ] +Key: WRFLAGS: [ 0.00 0.00 ] +Key: WRFSBASE: [ 0.00 0.00 ] +Key: WRGSBASE: [ 0.00 0.00 ] +Key: WRMSR: [ 0.00 0.00 ] +Key: WRMSRLIST: [ 0.00 0.00 ] +Key: WRMSRNS: [ 0.00 0.00 ] +Key: WRMSRNSir: [ 0.00 0.00 ] +Key: WRMSRNSir_EVEX: [ 0.00 0.00 ] +Key: WRPKRUr: [ 0.00 0.00 ] +Key: WRSSD: [ 0.00 0.00 ] +Key: WRSSD_EVEX: [ 0.00 0.00 ] +Key: WRSSQ: [ 0.00 0.00 ] +Key: WRSSQ_EVEX: [ 0.00 0.00 ] +Key: WRUSSD: [ 0.00 0.00 ] +Key: WRUSSD_EVEX: [ 0.00 0.00 ] +Key: WRUSSQ: [ 0.00 0.00 ] +Key: WRUSSQ_EVEX: [ 0.00 0.00 ] +Key: XABORT: [ 0.00 0.00 ] +Key: XABORT_DEF: [ 0.00 0.00 ] +Key: XACQUIRE_PREFIX: [ 0.00 0.00 ] +Key: XADD: [ 0.00 0.00 ] +Key: XAM_F: [ 0.00 0.00 ] +Key: XAM_Fp: [ 0.00 0.00 ] +Key: XBEGIN: [ 0.00 0.00 ] +Key: XCHG: [ 0.00 0.00 ] +Key: XCH_F: [ 0.00 0.00 ] +Key: XCRYPTCBC: [ 0.00 0.00 ] +Key: XCRYPTCFB: [ 0.00 0.00 ] +Key: XCRYPTCTR: [ 0.00 0.00 ] +Key: XCRYPTECB: [ 0.00 0.00 ] +Key: XCRYPTOFB: [ 0.00 0.00 ] +Key: XEND: [ 0.00 0.00 ] +Key: XGETBV: [ 0.00 0.00 ] +Key: XLAT: [ 0.00 0.00 ] +Key: XOR: [ 0.00 0.00 ] +Key: XORPDrm: [ 0.00 0.00 ] +Key: XORPDrr: [ 0.00 0.00 ] +Key: XORPSrm: [ 0.00 0.00 ] +Key: XORPSrr: [ 0.00 0.00 ] +Key: XRELEASE_PREFIX: [ 0.00 0.00 ] +Key: XRESLDTRK: [ 0.00 0.00 ] +Key: XRSTOR: [ 0.00 0.00 ] +Key: XRSTORS: [ 0.00 0.00 ] +Key: XSAVE: [ 0.00 0.00 ] +Key: XSAVEC: [ 0.00 0.00 ] +Key: XSAVEOPT: [ 0.00 0.00 ] +Key: XSAVES: [ 0.00 0.00 ] +Key: XSETBV: [ 0.00 0.00 ] +Key: XSHA: [ 0.00 0.00 ] +Key: XSTORE: [ 0.00 0.00 ] +Key: XSUSLDTRK: [ 0.00 0.00 ] +Key: XTEST: [ 0.00 0.00 ] diff --git a/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt new file mode 100644 index 0000000..4409e6d --- /dev/null +++ b/llvm/test/CodeGen/MIR2Vec/Inputs/reference_x86_vocab_wo=0.5_print.txt @@ -0,0 +1,6882 @@ +Key: AAA: [ 0.00 0.00 ] +Key: AAD: [ 0.00 0.00 ] +Key: AADD: [ 0.00 0.00 ] +Key: AAM: [ 0.00 0.00 ] +Key: AAND: [ 0.00 0.00 ] +Key: AAS: [ 0.00 0.00 ] +Key: ABS_F: [ 0.00 0.00 ] +Key: ABS_Fp: [ 0.50 1.00 ] +Key: ADC: [ 1.50 2.00 ] +Key: ADCX: [ 0.00 0.00 ] +Key: ADD: [ 2.50 3.00 ] +Key: ADDPDrm: [ 3.50 4.00 ] +Key: ADDPDrr: [ 4.50 5.00 ] +Key: ADDPSrm: [ 0.00 0.00 ] +Key: ADDPSrr: [ 5.50 6.00 ] +Key: ADDR: [ 0.00 0.00 ] +Key: ADDSDrm: [ 6.50 7.00 ] +Key: ADDSDrm_Int: [ 0.00 0.00 ] +Key: ADDSDrr: [ 0.00 0.00 ] +Key: ADDSDrr_Int: [ 0.00 0.00 ] +Key: ADDSSrm: [ 0.00 0.00 ] +Key: ADDSSrm_Int: [ 0.00 0.00 ] +Key: ADDSSrr: [ 0.00 0.00 ] +Key: ADDSSrr_Int: [ 0.00 0.00 ] +Key: ADDSUBPDrm: [ 0.00 0.00 ] +Key: ADDSUBPDrr: [ 0.00 0.00 ] +Key: ADDSUBPSrm: [ 0.00 0.00 ] +Key: ADDSUBPSrr: [ 0.00 0.00 ] +Key: ADD_F: [ 0.00 0.00 ] +Key: ADD_FI: [ 0.00 0.00 ] +Key: ADD_FPrST: [ 0.00 0.00 ] +Key: ADD_FST: [ 0.00 0.00 ] +Key: ADD_Fp: [ 0.00 0.00 ] +Key: ADD_FpI: [ 0.00 0.00 ] +Key: ADD_FrST: [ 0.00 0.00 ] +Key: ADJCALLSTACKDOWN: [ 0.00 0.00 ] +Key: ADJCALLSTACKUP: [ 0.00 0.00 ] +Key: ADOX: [ 0.00 0.00 ] +Key: AESDEC: [ 0.00 0.00 ] +Key: AESDECLASTrm: [ 0.00 0.00 ] +Key: AESDECLASTrr: [ 0.00 0.00 ] +Key: AESDECWIDE: [ 0.00 0.00 ] +Key: AESDECrm: [ 0.00 0.00 ] +Key: AESDECrr: [ 0.00 0.00 ] +Key: AESENC: [ 0.00 0.00 ] +Key: AESENCLASTrm: [ 0.00 0.00 ] +Key: AESENCLASTrr: [ 0.00 0.00 ] +Key: AESENCWIDE: [ 0.00 0.00 ] +Key: AESENCrm: [ 0.00 0.00 ] +Key: AESENCrr: [ 0.00 0.00 ] +Key: AESIMCrm: [ 0.00 0.00 ] +Key: AESIMCrr: [ 0.00 0.00 ] +Key: AESKEYGENASSISTrmi: [ 0.00 0.00 ] +Key: AESKEYGENASSISTrri: [ 0.00 0.00 ] +Key: AND: [ 0.00 0.00 ] +Key: ANDN: [ 0.00 0.00 ] +Key: ANDNPDrm: [ 0.00 0.00 ] +Key: ANDNPDrr: [ 0.00 0.00 ] +Key: ANDNPSrm: [ 0.00 0.00 ] +Key: ANDNPSrr: [ 0.00 0.00 ] +Key: ANDPDrm: [ 0.00 0.00 ] +Key: ANDPDrr: [ 0.00 0.00 ] +Key: ANDPSrm: [ 0.00 0.00 ] +Key: ANDPSrr: [ 0.00 0.00 ] +Key: ANNOTATION_LABEL: [ 0.00 0.00 ] +Key: AOR: [ 0.00 0.00 ] +Key: ARITH_FENCE: [ 0.00 0.00 ] +Key: ARPL: [ 0.00 0.00 ] +Key: ASAN_CHECK_MEMACCESS: [ 0.00 0.00 ] +Key: AVX: [ 0.00 0.00 ] +Key: AVX_SET: [ 0.00 0.00 ] +Key: AXOR: [ 0.00 0.00 ] +Key: BEXTR: [ 0.00 0.00 ] +Key: BEXTRI: [ 0.00 0.00 ] +Key: BLCFILL: [ 0.00 0.00 ] +Key: BLCI: [ 0.00 0.00 ] +Key: BLCIC: [ 0.00 0.00 ] +Key: BLCMSK: [ 0.00 0.00 ] +Key: BLCS: [ 0.00 0.00 ] +Key: BLENDPDrmi: [ 0.00 0.00 ] +Key: BLENDPDrri: [ 0.00 0.00 ] +Key: BLENDPSrmi: [ 0.00 0.00 ] +Key: BLENDPSrri: [ 0.00 0.00 ] +Key: BLENDVPDrm: [ 0.00 0.00 ] +Key: BLENDVPDrr: [ 0.00 0.00 ] +Key: BLENDVPSrm: [ 0.00 0.00 ] +Key: BLENDVPSrr: [ 0.00 0.00 ] +Key: BLSFILL: [ 0.00 0.00 ] +Key: BLSI: [ 0.00 0.00 ] +Key: BLSIC: [ 0.00 0.00 ] +Key: BLSMSK: [ 0.00 0.00 ] +Key: BLSR: [ 0.00 0.00 ] +Key: BOUNDS: [ 0.00 0.00 ] +Key: BSF: [ 0.00 0.00 ] +Key: BSR: [ 0.00 0.00 ] +Key: BSWAP: [ 0.00 0.00 ] +Key: BT: [ 0.00 0.00 ] +Key: BTC: [ 0.00 0.00 ] +Key: BTR: [ 0.00 0.00 ] +Key: BTS: [ 0.00 0.00 ] +Key: BUNDLE: [ 0.00 0.00 ] +Key: BZHI: [ 0.00 0.00 ] +Key: CALL: [ 0.00 0.00 ] +Key: CALLpcrel: [ 0.00 0.00 ] +Key: CATCHRET: [ 0.00 0.00 ] +Key: CBW: [ 0.00 0.00 ] +Key: CCMP: [ 0.00 0.00 ] +Key: CDQ: [ 0.00 0.00 ] +Key: CDQE: [ 0.00 0.00 ] +Key: CFCMOV: [ 0.00 0.00 ] +Key: CFI_INSTRUCTION: [ 0.00 0.00 ] +Key: CHS_F: [ 0.00 0.00 ] +Key: CHS_Fp: [ 0.00 0.00 ] +Key: CLAC: [ 0.00 0.00 ] +Key: CLC: [ 0.00 0.00 ] +Key: CLD: [ 0.00 0.00 ] +Key: CLDEMOTE: [ 0.00 0.00 ] +Key: CLEANUPRET: [ 0.00 0.00 ] +Key: CLFLUSH: [ 0.00 0.00 ] +Key: CLFLUSHOPT: [ 0.00 0.00 ] +Key: CLGI: [ 0.00 0.00 ] +Key: CLI: [ 0.00 0.00 ] +Key: CLRSSBSY: [ 0.00 0.00 ] +Key: CLTS: [ 0.00 0.00 ] +Key: CLUI: [ 0.00 0.00 ] +Key: CLWB: [ 0.00 0.00 ] +Key: CLZERO: [ 0.00 0.00 ] +Key: CMC: [ 0.00 0.00 ] +Key: CMOV: [ 0.00 0.00 ] +Key: CMOVBE_F: [ 0.00 0.00 ] +Key: CMOVBE_Fp: [ 0.00 0.00 ] +Key: CMOVB_F: [ 0.00 0.00 ] +Key: CMOVB_Fp: [ 0.00 0.00 ] +Key: CMOVE_F: [ 0.00 0.00 ] +Key: CMOVE_Fp: [ 0.00 0.00 ] +Key: CMOVNBE_F: [ 0.00 0.00 ] +Key: CMOVNBE_Fp: [ 0.00 0.00 ] +Key: CMOVNB_F: [ 0.00 0.00 ] +Key: CMOVNB_Fp: [ 0.00 0.00 ] +Key: CMOVNE_F: [ 0.00 0.00 ] +Key: CMOVNE_Fp: [ 0.00 0.00 ] +Key: CMOVNP_F: [ 0.00 0.00 ] +Key: CMOVNP_Fp: [ 0.00 0.00 ] +Key: CMOVP_F: [ 0.00 0.00 ] +Key: CMOVP_Fp: [ 0.00 0.00 ] +Key: CMOV_FR: [ 0.00 0.00 ] +Key: CMOV_GR: [ 0.00 0.00 ] +Key: CMOV_RFP: [ 0.00 0.00 ] +Key: CMOV_VK: [ 0.00 0.00 ] +Key: CMOV_VR: [ 0.00 0.00 ] +Key: CMP: [ 0.00 0.00 ] +Key: CMPCCXADDmr: [ 0.00 0.00 ] +Key: CMPPDrmi: [ 0.00 0.00 ] +Key: CMPPDrri: [ 0.00 0.00 ] +Key: CMPPSrmi: [ 0.00 0.00 ] +Key: CMPPSrri: [ 0.00 0.00 ] +Key: CMPSB: [ 0.00 0.00 ] +Key: CMPSDrmi: [ 0.00 0.00 ] +Key: CMPSDrmi_Int: [ 0.00 0.00 ] +Key: CMPSDrri: [ 0.00 0.00 ] +Key: CMPSDrri_Int: [ 0.00 0.00 ] +Key: CMPSL: [ 0.00 0.00 ] +Key: CMPSQ: [ 0.00 0.00 ] +Key: CMPSSrmi: [ 0.00 0.00 ] +Key: CMPSSrmi_Int: [ 0.00 0.00 ] +Key: CMPSSrri: [ 0.00 0.00 ] +Key: CMPSSrri_Int: [ 0.00 0.00 ] +Key: CMPSW: [ 0.00 0.00 ] +Key: CMPXCHG: [ 0.00 0.00 ] +Key: COMISDrm: [ 0.00 0.00 ] +Key: COMISDrm_Int: [ 0.00 0.00 ] +Key: COMISDrr: [ 0.00 0.00 ] +Key: COMISDrr_Int: [ 0.00 0.00 ] +Key: COMISSrm: [ 0.00 0.00 ] +Key: COMISSrm_Int: [ 0.00 0.00 ] +Key: COMISSrr: [ 0.00 0.00 ] +Key: COMISSrr_Int: [ 0.00 0.00 ] +Key: COMP_FST: [ 0.00 0.00 ] +Key: COM_FIPr: [ 0.00 0.00 ] +Key: COM_FIr: [ 0.00 0.00 ] +Key: COM_FST: [ 0.00 0.00 ] +Key: COM_FpIr: [ 0.00 0.00 ] +Key: COM_Fpr: [ 0.00 0.00 ] +Key: CONVERGENCECTRL_ANCHOR: [ 0.00 0.00 ] +Key: CONVERGENCECTRL_ENTRY: [ 0.00 0.00 ] +Key: CONVERGENCECTRL_GLUE: [ 0.00 0.00 ] +Key: CONVERGENCECTRL_LOOP: [ 0.00 0.00 ] +Key: COPY: [ 0.00 0.00 ] +Key: COPY_TO_REGCLASS: [ 0.00 0.00 ] +Key: CPUID: [ 0.00 0.00 ] +Key: CQO: [ 0.00 0.00 ] +Key: CRC: [ 0.00 0.00 ] +Key: CS_PREFIX: [ 0.00 0.00 ] +Key: CTEST: [ 0.00 0.00 ] +Key: CVTDQ: [ 0.00 0.00 ] +Key: CVTPD: [ 0.00 0.00 ] +Key: CVTPS: [ 0.00 0.00 ] +Key: CVTSD: [ 0.00 0.00 ] +Key: CVTSI: [ 0.00 0.00 ] +Key: CVTSS: [ 0.00 0.00 ] +Key: CVTTPD: [ 0.00 0.00 ] +Key: CVTTPS: [ 0.00 0.00 ] +Key: CVTTSD: [ 0.00 0.00 ] +Key: CVTTSS: [ 0.00 0.00 ] +Key: CWD: [ 0.00 0.00 ] +Key: CWDE: [ 0.00 0.00 ] +Key: DAA: [ 0.00 0.00 ] +Key: DAS: [ 0.00 0.00 ] +Key: DATA: [ 0.00 0.00 ] +Key: DBG_INSTR_REF: [ 0.00 0.00 ] +Key: DBG_LABEL: [ 0.00 0.00 ] +Key: DBG_PHI: [ 0.00 0.00 ] +Key: DBG_VALUE: [ 0.00 0.00 ] +Key: DBG_VALUE_LIST: [ 0.00 0.00 ] +Key: DEC: [ 0.00 0.00 ] +Key: DIV: [ 0.00 0.00 ] +Key: DIVPDrm: [ 0.00 0.00 ] +Key: DIVPDrr: [ 0.00 0.00 ] +Key: DIVPSrm: [ 0.00 0.00 ] +Key: DIVPSrr: [ 0.00 0.00 ] +Key: DIVR_F: [ 0.00 0.00 ] +Key: DIVR_FI: [ 0.00 0.00 ] +Key: DIVR_FPrST: [ 0.00 0.00 ] +Key: DIVR_FST: [ 0.00 0.00 ] +Key: DIVR_Fp: [ 0.00 0.00 ] +Key: DIVR_FpI: [ 0.00 0.00 ] +Key: DIVR_FrST: [ 0.00 0.00 ] +Key: DIVSDrm: [ 0.00 0.00 ] +Key: DIVSDrm_Int: [ 0.00 0.00 ] +Key: DIVSDrr: [ 0.00 0.00 ] +Key: DIVSDrr_Int: [ 0.00 0.00 ] +Key: DIVSSrm: [ 0.00 0.00 ] +Key: DIVSSrm_Int: [ 0.00 0.00 ] +Key: DIVSSrr: [ 0.00 0.00 ] +Key: DIVSSrr_Int: [ 0.00 0.00 ] +Key: DIV_F: [ 0.00 0.00 ] +Key: DIV_FI: [ 0.00 0.00 ] +Key: DIV_FPrST: [ 0.00 0.00 ] +Key: DIV_FST: [ 0.00 0.00 ] +Key: DIV_Fp: [ 0.00 0.00 ] +Key: DIV_FpI: [ 0.00 0.00 ] +Key: DIV_FrST: [ 0.00 0.00 ] +Key: DPPDrmi: [ 0.00 0.00 ] +Key: DPPDrri: [ 0.00 0.00 ] +Key: DPPSrmi: [ 0.00 0.00 ] +Key: DPPSrri: [ 0.00 0.00 ] +Key: DS_PREFIX: [ 0.00 0.00 ] +Key: DYN_ALLOCA: [ 0.00 0.00 ] +Key: EH_LABEL: [ 0.00 0.00 ] +Key: EH_RETURN: [ 0.00 0.00 ] +Key: EH_SjLj_LongJmp: [ 0.00 0.00 ] +Key: EH_SjLj_SetJmp: [ 0.00 0.00 ] +Key: EH_SjLj_Setup: [ 0.00 0.00 ] +Key: ENCLS: [ 0.00 0.00 ] +Key: ENCLU: [ 0.00 0.00 ] +Key: ENCLV: [ 0.00 0.00 ] +Key: ENCODEKEY: [ 0.00 0.00 ] +Key: ENDBR: [ 0.00 0.00 ] +Key: ENQCMD: [ 0.00 0.00 ] +Key: ENQCMDS: [ 0.00 0.00 ] +Key: ENTER: [ 0.00 0.00 ] +Key: ERETS: [ 0.00 0.00 ] +Key: ERETU: [ 0.00 0.00 ] +Key: ES_PREFIX: [ 0.00 0.00 ] +Key: EXTRACTPSmri: [ 0.00 0.00 ] +Key: EXTRACTPSrri: [ 0.00 0.00 ] +Key: EXTRACT_SUBREG: [ 0.00 0.00 ] +Key: EXTRQ: [ 0.00 0.00 ] +Key: EXTRQI: [ 0.00 0.00 ] +Key: F: [ 0.00 0.00 ] +Key: FAKE_USE: [ 0.00 0.00 ] +Key: FARCALL: [ 0.00 0.00 ] +Key: FARJMP: [ 0.00 0.00 ] +Key: FAULTING_OP: [ 0.00 0.00 ] +Key: FBLDm: [ 0.00 0.00 ] +Key: FBSTPm: [ 0.00 0.00 ] +Key: FCOM: [ 0.00 0.00 ] +Key: FCOMP: [ 0.00 0.00 ] +Key: FCOMPP: [ 0.00 0.00 ] +Key: FCOS: [ 0.00 0.00 ] +Key: FDECSTP: [ 0.00 0.00 ] +Key: FEMMS: [ 0.00 0.00 ] +Key: FENTRY_CALL: [ 0.00 0.00 ] +Key: FFREE: [ 0.00 0.00 ] +Key: FFREEP: [ 0.00 0.00 ] +Key: FICOM: [ 0.00 0.00 ] +Key: FICOMP: [ 0.00 0.00 ] +Key: FINCSTP: [ 0.00 0.00 ] +Key: FLDCW: [ 0.00 0.00 ] +Key: FLDENVm: [ 0.00 0.00 ] +Key: FLDL: [ 0.00 0.00 ] +Key: FLDLG: [ 0.00 0.00 ] +Key: FLDLN: [ 0.00 0.00 ] +Key: FLDPI: [ 0.00 0.00 ] +Key: FNCLEX: [ 0.00 0.00 ] +Key: FNINIT: [ 0.00 0.00 ] +Key: FNOP: [ 0.00 0.00 ] +Key: FNSTCW: [ 0.00 0.00 ] +Key: FNSTSW: [ 0.00 0.00 ] +Key: FNSTSWm: [ 0.00 0.00 ] +Key: FP: [ 0.00 0.00 ] +Key: FPATAN: [ 0.00 0.00 ] +Key: FPREM: [ 0.00 0.00 ] +Key: FPTAN: [ 0.00 0.00 ] +Key: FRNDINT: [ 0.00 0.00 ] +Key: FRSTORm: [ 0.00 0.00 ] +Key: FSAVEm: [ 0.00 0.00 ] +Key: FSCALE: [ 0.00 0.00 ] +Key: FSIN: [ 0.00 0.00 ] +Key: FSINCOS: [ 0.00 0.00 ] +Key: FSTENVm: [ 0.00 0.00 ] +Key: FS_PREFIX: [ 0.00 0.00 ] +Key: FXRSTOR: [ 0.00 0.00 ] +Key: FXSAVE: [ 0.00 0.00 ] +Key: FXTRACT: [ 0.00 0.00 ] +Key: FYL: [ 0.00 0.00 ] +Key: FsFLD: [ 0.00 0.00 ] +Key: GC_LABEL: [ 0.00 0.00 ] +Key: GETSEC: [ 0.00 0.00 ] +Key: GF: [ 0.00 0.00 ] +Key: GS_PREFIX: [ 0.00 0.00 ] +Key: G_ABDS: [ 0.00 0.00 ] +Key: G_ABDU: [ 0.00 0.00 ] +Key: G_ABS: [ 0.00 0.00 ] +Key: G_ADD: [ 0.00 0.00 ] +Key: G_ADDRSPACE_CAST: [ 0.00 0.00 ] +Key: G_AND: [ 0.00 0.00 ] +Key: G_ANYEXT: [ 0.00 0.00 ] +Key: G_ASHR: [ 0.00 0.00 ] +Key: G_ASSERT_ALIGN: [ 0.00 0.00 ] +Key: G_ASSERT_SEXT: [ 0.00 0.00 ] +Key: G_ASSERT_ZEXT: [ 0.00 0.00 ] +Key: G_ATOMICRMW_ADD: [ 0.00 0.00 ] +Key: G_ATOMICRMW_AND: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FADD: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FMAX: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FMAXIMUM: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FMIN: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FMINIMUM: [ 0.00 0.00 ] +Key: G_ATOMICRMW_FSUB: [ 0.00 0.00 ] +Key: G_ATOMICRMW_MAX: [ 0.00 0.00 ] +Key: G_ATOMICRMW_MIN: [ 0.00 0.00 ] +Key: G_ATOMICRMW_NAND: [ 0.00 0.00 ] +Key: G_ATOMICRMW_OR: [ 0.00 0.00 ] +Key: G_ATOMICRMW_SUB: [ 0.00 0.00 ] +Key: G_ATOMICRMW_UDEC_WRAP: [ 0.00 0.00 ] +Key: G_ATOMICRMW_UINC_WRAP: [ 0.00 0.00 ] +Key: G_ATOMICRMW_UMAX: [ 0.00 0.00 ] +Key: G_ATOMICRMW_UMIN: [ 0.00 0.00 ] +Key: G_ATOMICRMW_USUB_COND: [ 0.00 0.00 ] +Key: G_ATOMICRMW_USUB_SAT: [ 0.00 0.00 ] +Key: G_ATOMICRMW_XCHG: [ 0.00 0.00 ] +Key: G_ATOMICRMW_XOR: [ 0.00 0.00 ] +Key: G_ATOMIC_CMPXCHG: [ 0.00 0.00 ] +Key: G_ATOMIC_CMPXCHG_WITH_SUCCESS: [ 0.00 0.00 ] +Key: G_BITCAST: [ 0.00 0.00 ] +Key: G_BITREVERSE: [ 0.00 0.00 ] +Key: G_BLOCK_ADDR: [ 0.00 0.00 ] +Key: G_BR: [ 0.00 0.00 ] +Key: G_BRCOND: [ 0.00 0.00 ] +Key: G_BRINDIRECT: [ 0.00 0.00 ] +Key: G_BRJT: [ 0.00 0.00 ] +Key: G_BSWAP: [ 0.00 0.00 ] +Key: G_BUILD_VECTOR: [ 0.00 0.00 ] +Key: G_BUILD_VECTOR_TRUNC: [ 0.00 0.00 ] +Key: G_BZERO: [ 0.00 0.00 ] +Key: G_CONCAT_VECTORS: [ 0.00 0.00 ] +Key: G_CONSTANT: [ 0.00 0.00 ] +Key: G_CONSTANT_FOLD_BARRIER: [ 0.00 0.00 ] +Key: G_CONSTANT_POOL: [ 0.00 0.00 ] +Key: G_CTLZ: [ 0.00 0.00 ] +Key: G_CTLZ_ZERO_UNDEF: [ 0.00 0.00 ] +Key: G_CTPOP: [ 0.00 0.00 ] +Key: G_CTTZ: [ 0.00 0.00 ] +Key: G_CTTZ_ZERO_UNDEF: [ 0.00 0.00 ] +Key: G_DEBUGTRAP: [ 0.00 0.00 ] +Key: G_DYN_STACKALLOC: [ 0.00 0.00 ] +Key: G_EXTRACT: [ 0.00 0.00 ] +Key: G_EXTRACT_SUBVECTOR: [ 0.00 0.00 ] +Key: G_EXTRACT_VECTOR_ELT: [ 0.00 0.00 ] +Key: G_FABS: [ 0.00 0.00 ] +Key: G_FACOS: [ 0.00 0.00 ] +Key: G_FADD: [ 0.00 0.00 ] +Key: G_FASIN: [ 0.00 0.00 ] +Key: G_FATAN: [ 0.00 0.00 ] +Key: G_FCANONICALIZE: [ 0.00 0.00 ] +Key: G_FCEIL: [ 0.00 0.00 ] +Key: G_FCMP: [ 0.00 0.00 ] +Key: G_FCONSTANT: [ 0.00 0.00 ] +Key: G_FCOPYSIGN: [ 0.00 0.00 ] +Key: G_FCOS: [ 0.00 0.00 ] +Key: G_FCOSH: [ 0.00 0.00 ] +Key: G_FDIV: [ 0.00 0.00 ] +Key: G_FENCE: [ 0.00 0.00 ] +Key: G_FEXP: [ 0.00 0.00 ] +Key: G_FFLOOR: [ 0.00 0.00 ] +Key: G_FFREXP: [ 0.00 0.00 ] +Key: G_FILD: [ 0.00 0.00 ] +Key: G_FIST: [ 0.00 0.00 ] +Key: G_FLDCW: [ 0.00 0.00 ] +Key: G_FLDEXP: [ 0.00 0.00 ] +Key: G_FLOG: [ 0.00 0.00 ] +Key: G_FMA: [ 0.00 0.00 ] +Key: G_FMAD: [ 0.00 0.00 ] +Key: G_FMAXIMUM: [ 0.00 0.00 ] +Key: G_FMAXIMUMNUM: [ 0.00 0.00 ] +Key: G_FMAXNUM: [ 0.00 0.00 ] +Key: G_FMAXNUM_IEEE: [ 0.00 0.00 ] +Key: G_FMINIMUM: [ 0.00 0.00 ] +Key: G_FMINIMUMNUM: [ 0.00 0.00 ] +Key: G_FMINNUM: [ 0.00 0.00 ] +Key: G_FMINNUM_IEEE: [ 0.00 0.00 ] +Key: G_FMODF: [ 0.00 0.00 ] +Key: G_FMUL: [ 0.00 0.00 ] +Key: G_FNEARBYINT: [ 0.00 0.00 ] +Key: G_FNEG: [ 0.00 0.00 ] +Key: G_FNSTCW: [ 0.00 0.00 ] +Key: G_FPEXT: [ 0.00 0.00 ] +Key: G_FPOW: [ 0.00 0.00 ] +Key: G_FPOWI: [ 0.00 0.00 ] +Key: G_FPTOSI: [ 0.00 0.00 ] +Key: G_FPTOSI_SAT: [ 0.00 0.00 ] +Key: G_FPTOUI: [ 0.00 0.00 ] +Key: G_FPTOUI_SAT: [ 0.00 0.00 ] +Key: G_FPTRUNC: [ 0.00 0.00 ] +Key: G_FRAME_INDEX: [ 0.00 0.00 ] +Key: G_FREEZE: [ 0.00 0.00 ] +Key: G_FREM: [ 0.00 0.00 ] +Key: G_FRINT: [ 0.00 0.00 ] +Key: G_FSHL: [ 0.00 0.00 ] +Key: G_FSHR: [ 0.00 0.00 ] +Key: G_FSIN: [ 0.00 0.00 ] +Key: G_FSINCOS: [ 0.00 0.00 ] +Key: G_FSINH: [ 0.00 0.00 ] +Key: G_FSQRT: [ 0.00 0.00 ] +Key: G_FSUB: [ 0.00 0.00 ] +Key: G_FTAN: [ 0.00 0.00 ] +Key: G_FTANH: [ 0.00 0.00 ] +Key: G_GET_FPENV: [ 0.00 0.00 ] +Key: G_GET_FPMODE: [ 0.00 0.00 ] +Key: G_GET_ROUNDING: [ 0.00 0.00 ] +Key: G_GLOBAL_VALUE: [ 0.00 0.00 ] +Key: G_ICMP: [ 0.00 0.00 ] +Key: G_IMPLICIT_DEF: [ 0.00 0.00 ] +Key: G_INDEXED_LOAD: [ 0.00 0.00 ] +Key: G_INDEXED_SEXTLOAD: [ 0.00 0.00 ] +Key: G_INDEXED_STORE: [ 0.00 0.00 ] +Key: G_INDEXED_ZEXTLOAD: [ 0.00 0.00 ] +Key: G_INSERT: [ 0.00 0.00 ] +Key: G_INSERT_SUBVECTOR: [ 0.00 0.00 ] +Key: G_INSERT_VECTOR_ELT: [ 0.00 0.00 ] +Key: G_INTRINSIC: [ 0.00 0.00 ] +Key: G_INTRINSIC_CONVERGENT: [ 0.00 0.00 ] +Key: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS: [ 0.00 0.00 ] +Key: G_INTRINSIC_FPTRUNC_ROUND: [ 0.00 0.00 ] +Key: G_INTRINSIC_LLRINT: [ 0.00 0.00 ] +Key: G_INTRINSIC_LRINT: [ 0.00 0.00 ] +Key: G_INTRINSIC_ROUND: [ 0.00 0.00 ] +Key: G_INTRINSIC_ROUNDEVEN: [ 0.00 0.00 ] +Key: G_INTRINSIC_TRUNC: [ 0.00 0.00 ] +Key: G_INTRINSIC_W_SIDE_EFFECTS: [ 0.00 0.00 ] +Key: G_INTTOPTR: [ 0.00 0.00 ] +Key: G_INVOKE_REGION_START: [ 0.00 0.00 ] +Key: G_IS_FPCLASS: [ 0.00 0.00 ] +Key: G_JUMP_TABLE: [ 0.00 0.00 ] +Key: G_LLROUND: [ 0.00 0.00 ] +Key: G_LOAD: [ 0.00 0.00 ] +Key: G_LROUND: [ 0.00 0.00 ] +Key: G_LSHR: [ 0.00 0.00 ] +Key: G_MEMCPY: [ 0.00 0.00 ] +Key: G_MEMCPY_INLINE: [ 0.00 0.00 ] +Key: G_MEMMOVE: [ 0.00 0.00 ] +Key: G_MEMSET: [ 0.00 0.00 ] +Key: G_MERGE_VALUES: [ 0.00 0.00 ] +Key: G_MUL: [ 0.00 0.00 ] +Key: G_OR: [ 0.00 0.00 ] +Key: G_PHI: [ 0.00 0.00 ] +Key: G_PREFETCH: [ 0.00 0.00 ] +Key: G_PTRAUTH_GLOBAL_VALUE: [ 0.00 0.00 ] +Key: G_PTRMASK: [ 0.00 0.00 ] +Key: G_PTRTOINT: [ 0.00 0.00 ] +Key: G_PTR_ADD: [ 0.00 0.00 ] +Key: G_READCYCLECOUNTER: [ 0.00 0.00 ] +Key: G_READSTEADYCOUNTER: [ 0.00 0.00 ] +Key: G_READ_REGISTER: [ 0.00 0.00 ] +Key: G_RESET_FPENV: [ 0.00 0.00 ] +Key: G_RESET_FPMODE: [ 0.00 0.00 ] +Key: G_ROTL: [ 0.00 0.00 ] +Key: G_ROTR: [ 0.00 0.00 ] +Key: G_SADDE: [ 0.00 0.00 ] +Key: G_SADDO: [ 0.00 0.00 ] +Key: G_SADDSAT: [ 0.00 0.00 ] +Key: G_SBFX: [ 0.00 0.00 ] +Key: G_SCMP: [ 0.00 0.00 ] +Key: G_SDIV: [ 0.00 0.00 ] +Key: G_SDIVFIX: [ 0.00 0.00 ] +Key: G_SDIVFIXSAT: [ 0.00 0.00 ] +Key: G_SDIVREM: [ 0.00 0.00 ] +Key: G_SELECT: [ 0.00 0.00 ] +Key: G_SET_FPENV: [ 0.00 0.00 ] +Key: G_SET_FPMODE: [ 0.00 0.00 ] +Key: G_SET_ROUNDING: [ 0.00 0.00 ] +Key: G_SEXT: [ 0.00 0.00 ] +Key: G_SEXTLOAD: [ 0.00 0.00 ] +Key: G_SEXT_INREG: [ 0.00 0.00 ] +Key: G_SHL: [ 0.00 0.00 ] +Key: G_SHUFFLE_VECTOR: [ 0.00 0.00 ] +Key: G_SITOFP: [ 0.00 0.00 ] +Key: G_SMAX: [ 0.00 0.00 ] +Key: G_SMIN: [ 0.00 0.00 ] +Key: G_SMULFIX: [ 0.00 0.00 ] +Key: G_SMULFIXSAT: [ 0.00 0.00 ] +Key: G_SMULH: [ 0.00 0.00 ] +Key: G_SMULO: [ 0.00 0.00 ] +Key: G_SPLAT_VECTOR: [ 0.00 0.00 ] +Key: G_SREM: [ 0.00 0.00 ] +Key: G_SSHLSAT: [ 0.00 0.00 ] +Key: G_SSUBE: [ 0.00 0.00 ] +Key: G_SSUBO: [ 0.00 0.00 ] +Key: G_SSUBSAT: [ 0.00 0.00 ] +Key: G_STACKRESTORE: [ 0.00 0.00 ] +Key: G_STACKSAVE: [ 0.00 0.00 ] +Key: G_STEP_VECTOR: [ 0.00 0.00 ] +Key: G_STORE: [ 0.00 0.00 ] +Key: G_STRICT_FADD: [ 0.00 0.00 ] +Key: G_STRICT_FDIV: [ 0.00 0.00 ] +Key: G_STRICT_FLDEXP: [ 0.00 0.00 ] +Key: G_STRICT_FMA: [ 0.00 0.00 ] +Key: G_STRICT_FMUL: [ 0.00 0.00 ] +Key: G_STRICT_FREM: [ 0.00 0.00 ] +Key: G_STRICT_FSQRT: [ 0.00 0.00 ] +Key: G_STRICT_FSUB: [ 0.00 0.00 ] +Key: G_SUB: [ 0.00 0.00 ] +Key: G_TRAP: [ 0.00 0.00 ] +Key: G_TRUNC: [ 0.00 0.00 ] +Key: G_TRUNC_SSAT_S: [ 0.00 0.00 ] +Key: G_TRUNC_SSAT_U: [ 0.00 0.00 ] +Key: G_TRUNC_USAT_U: [ 0.00 0.00 ] +Key: G_UADDE: [ 0.00 0.00 ] +Key: G_UADDO: [ 0.00 0.00 ] +Key: G_UADDSAT: [ 0.00 0.00 ] +Key: G_UBFX: [ 0.00 0.00 ] +Key: G_UBSANTRAP: [ 0.00 0.00 ] +Key: G_UCMP: [ 0.00 0.00 ] +Key: G_UDIV: [ 0.00 0.00 ] +Key: G_UDIVFIX: [ 0.00 0.00 ] +Key: G_UDIVFIXSAT: [ 0.00 0.00 ] +Key: G_UDIVREM: [ 0.00 0.00 ] +Key: G_UITOFP: [ 0.00 0.00 ] +Key: G_UMAX: [ 0.00 0.00 ] +Key: G_UMIN: [ 0.00 0.00 ] +Key: G_UMULFIX: [ 0.00 0.00 ] +Key: G_UMULFIXSAT: [ 0.00 0.00 ] +Key: G_UMULH: [ 0.00 0.00 ] +Key: G_UMULO: [ 0.00 0.00 ] +Key: G_UNMERGE_VALUES: [ 0.00 0.00 ] +Key: G_UREM: [ 0.00 0.00 ] +Key: G_USHLSAT: [ 0.00 0.00 ] +Key: G_USUBE: [ 0.00 0.00 ] +Key: G_USUBO: [ 0.00 0.00 ] +Key: G_USUBSAT: [ 0.00 0.00 ] +Key: G_VAARG: [ 0.00 0.00 ] +Key: G_VASTART: [ 0.00 0.00 ] +Key: G_VECREDUCE_ADD: [ 0.00 0.00 ] +Key: G_VECREDUCE_AND: [ 0.00 0.00 ] +Key: G_VECREDUCE_FADD: [ 0.00 0.00 ] +Key: G_VECREDUCE_FMAX: [ 0.00 0.00 ] +Key: G_VECREDUCE_FMAXIMUM: [ 0.00 0.00 ] +Key: G_VECREDUCE_FMIN: [ 0.00 0.00 ] +Key: G_VECREDUCE_FMINIMUM: [ 0.00 0.00 ] +Key: G_VECREDUCE_FMUL: [ 0.00 0.00 ] +Key: G_VECREDUCE_MUL: [ 0.00 0.00 ] +Key: G_VECREDUCE_OR: [ 0.00 0.00 ] +Key: G_VECREDUCE_SEQ_FADD: [ 0.00 0.00 ] +Key: G_VECREDUCE_SEQ_FMUL: [ 0.00 0.00 ] +Key: G_VECREDUCE_SMAX: [ 0.00 0.00 ] +Key: G_VECREDUCE_SMIN: [ 0.00 0.00 ] +Key: G_VECREDUCE_UMAX: [ 0.00 0.00 ] +Key: G_VECREDUCE_UMIN: [ 0.00 0.00 ] +Key: G_VECREDUCE_XOR: [ 0.00 0.00 ] +Key: G_VECTOR_COMPRESS: [ 0.00 0.00 ] +Key: G_VSCALE: [ 0.00 0.00 ] +Key: G_WRITE_REGISTER: [ 0.00 0.00 ] +Key: G_XOR: [ 0.00 0.00 ] +Key: G_ZEXT: [ 0.00 0.00 ] +Key: G_ZEXTLOAD: [ 0.00 0.00 ] +Key: HADDPDrm: [ 0.00 0.00 ] +Key: HADDPDrr: [ 0.00 0.00 ] +Key: HADDPSrm: [ 0.00 0.00 ] +Key: HADDPSrr: [ 0.00 0.00 ] +Key: HLT: [ 0.00 0.00 ] +Key: HRESET: [ 0.00 0.00 ] +Key: HSUBPDrm: [ 0.00 0.00 ] +Key: HSUBPDrr: [ 0.00 0.00 ] +Key: HSUBPSrm: [ 0.00 0.00 ] +Key: HSUBPSrr: [ 0.00 0.00 ] +Key: ICALL_BRANCH_FUNNEL: [ 0.00 0.00 ] +Key: IDIV: [ 0.00 0.00 ] +Key: ILD_F: [ 0.00 0.00 ] +Key: ILD_Fp: [ 0.00 0.00 ] +Key: IMPLICIT_DEF: [ 0.00 0.00 ] +Key: IMUL: [ 0.00 0.00 ] +Key: IMULZU: [ 0.00 0.00 ] +Key: IN: [ 0.00 0.00 ] +Key: INC: [ 0.00 0.00 ] +Key: INCSSPD: [ 0.00 0.00 ] +Key: INCSSPQ: [ 0.00 0.00 ] +Key: INDIRECT_THUNK_CALL: [ 0.00 0.00 ] +Key: INDIRECT_THUNK_TCRETURN: [ 0.00 0.00 ] +Key: INIT_UNDEF: [ 0.00 0.00 ] +Key: INLINEASM: [ 0.00 0.00 ] +Key: INLINEASM_BR: [ 0.00 0.00 ] +Key: INSB: [ 0.00 0.00 ] +Key: INSERTPSrmi: [ 0.00 0.00 ] +Key: INSERTPSrri: [ 0.00 0.00 ] +Key: INSERTQ: [ 0.00 0.00 ] +Key: INSERTQI: [ 0.00 0.00 ] +Key: INSERT_SUBREG: [ 0.00 0.00 ] +Key: INSL: [ 0.00 0.00 ] +Key: INSW: [ 0.00 0.00 ] +Key: INT: [ 0.00 0.00 ] +Key: INTO: [ 0.00 0.00 ] +Key: INVD: [ 0.00 0.00 ] +Key: INVEPT: [ 0.00 0.00 ] +Key: INVLPG: [ 0.00 0.00 ] +Key: INVLPGA: [ 0.00 0.00 ] +Key: INVLPGB: [ 0.00 0.00 ] +Key: INVPCID: [ 0.00 0.00 ] +Key: INVVPID: [ 0.00 0.00 ] +Key: IRET: [ 0.00 0.00 ] +Key: ISTT_FP: [ 0.00 0.00 ] +Key: ISTT_Fp: [ 0.00 0.00 ] +Key: IST_F: [ 0.00 0.00 ] +Key: IST_FP: [ 0.00 0.00 ] +Key: IST_Fp: [ 0.00 0.00 ] +Key: Int_eh_sjlj_setup_dispatch: [ 0.00 0.00 ] +Key: JCC: [ 0.00 0.00 ] +Key: JCXZ: [ 0.00 0.00 ] +Key: JECXZ: [ 0.00 0.00 ] +Key: JMP: [ 0.00 0.00 ] +Key: JMPABS: [ 0.00 0.00 ] +Key: JRCXZ: [ 0.00 0.00 ] +Key: JUMP_TABLE_DEBUG_INFO: [ 0.00 0.00 ] +Key: KADDBkk: [ 0.00 0.00 ] +Key: KADDDkk: [ 0.00 0.00 ] +Key: KADDQkk: [ 0.00 0.00 ] +Key: KADDWkk: [ 0.00 0.00 ] +Key: KANDBkk: [ 0.00 0.00 ] +Key: KANDDkk: [ 0.00 0.00 ] +Key: KANDNBkk: [ 0.00 0.00 ] +Key: KANDNDkk: [ 0.00 0.00 ] +Key: KANDNQkk: [ 0.00 0.00 ] +Key: KANDNWkk: [ 0.00 0.00 ] +Key: KANDQkk: [ 0.00 0.00 ] +Key: KANDWkk: [ 0.00 0.00 ] +Key: KCFI_CHECK: [ 0.00 0.00 ] +Key: KILL: [ 0.00 0.00 ] +Key: KMOVBkk: [ 0.00 0.00 ] +Key: KMOVBkk_EVEX: [ 0.00 0.00 ] +Key: KMOVBkm: [ 0.00 0.00 ] +Key: KMOVBkm_EVEX: [ 0.00 0.00 ] +Key: KMOVBkr: [ 0.00 0.00 ] +Key: KMOVBkr_EVEX: [ 0.00 0.00 ] +Key: KMOVBmk: [ 0.00 0.00 ] +Key: KMOVBmk_EVEX: [ 0.00 0.00 ] +Key: KMOVBrk: [ 0.00 0.00 ] +Key: KMOVBrk_EVEX: [ 0.00 0.00 ] +Key: KMOVDkk: [ 0.00 0.00 ] +Key: KMOVDkk_EVEX: [ 0.00 0.00 ] +Key: KMOVDkm: [ 0.00 0.00 ] +Key: KMOVDkm_EVEX: [ 0.00 0.00 ] +Key: KMOVDkr: [ 0.00 0.00 ] +Key: KMOVDkr_EVEX: [ 0.00 0.00 ] +Key: KMOVDmk: [ 0.00 0.00 ] +Key: KMOVDmk_EVEX: [ 0.00 0.00 ] +Key: KMOVDrk: [ 0.00 0.00 ] +Key: KMOVDrk_EVEX: [ 0.00 0.00 ] +Key: KMOVQkk: [ 0.00 0.00 ] +Key: KMOVQkk_EVEX: [ 0.00 0.00 ] +Key: KMOVQkm: [ 0.00 0.00 ] +Key: KMOVQkm_EVEX: [ 0.00 0.00 ] +Key: KMOVQkr: [ 0.00 0.00 ] +Key: KMOVQkr_EVEX: [ 0.00 0.00 ] +Key: KMOVQmk: [ 0.00 0.00 ] +Key: KMOVQmk_EVEX: [ 0.00 0.00 ] +Key: KMOVQrk: [ 0.00 0.00 ] +Key: KMOVQrk_EVEX: [ 0.00 0.00 ] +Key: KMOVWkk: [ 0.00 0.00 ] +Key: KMOVWkk_EVEX: [ 0.00 0.00 ] +Key: KMOVWkm: [ 0.00 0.00 ] +Key: KMOVWkm_EVEX: [ 0.00 0.00 ] +Key: KMOVWkr: [ 0.00 0.00 ] +Key: KMOVWkr_EVEX: [ 0.00 0.00 ] +Key: KMOVWmk: [ 0.00 0.00 ] +Key: KMOVWmk_EVEX: [ 0.00 0.00 ] +Key: KMOVWrk: [ 0.00 0.00 ] +Key: KMOVWrk_EVEX: [ 0.00 0.00 ] +Key: KNOTBkk: [ 0.00 0.00 ] +Key: KNOTDkk: [ 0.00 0.00 ] +Key: KNOTQkk: [ 0.00 0.00 ] +Key: KNOTWkk: [ 0.00 0.00 ] +Key: KORBkk: [ 0.00 0.00 ] +Key: KORDkk: [ 0.00 0.00 ] +Key: KORQkk: [ 0.00 0.00 ] +Key: KORTESTBkk: [ 0.00 0.00 ] +Key: KORTESTDkk: [ 0.00 0.00 ] +Key: KORTESTQkk: [ 0.00 0.00 ] +Key: KORTESTWkk: [ 0.00 0.00 ] +Key: KORWkk: [ 0.00 0.00 ] +Key: KSET: [ 0.00 0.00 ] +Key: KSHIFTLBki: [ 0.00 0.00 ] +Key: KSHIFTLDki: [ 0.00 0.00 ] +Key: KSHIFTLQki: [ 0.00 0.00 ] +Key: KSHIFTLWki: [ 0.00 0.00 ] +Key: KSHIFTRBki: [ 0.00 0.00 ] +Key: KSHIFTRDki: [ 0.00 0.00 ] +Key: KSHIFTRQki: [ 0.00 0.00 ] +Key: KSHIFTRWki: [ 0.00 0.00 ] +Key: KTESTBkk: [ 0.00 0.00 ] +Key: KTESTDkk: [ 0.00 0.00 ] +Key: KTESTQkk: [ 0.00 0.00 ] +Key: KTESTWkk: [ 0.00 0.00 ] +Key: KUNPCKBWkk: [ 0.00 0.00 ] +Key: KUNPCKDQkk: [ 0.00 0.00 ] +Key: KUNPCKWDkk: [ 0.00 0.00 ] +Key: KXNORBkk: [ 0.00 0.00 ] +Key: KXNORDkk: [ 0.00 0.00 ] +Key: KXNORQkk: [ 0.00 0.00 ] +Key: KXNORWkk: [ 0.00 0.00 ] +Key: KXORBkk: [ 0.00 0.00 ] +Key: KXORDkk: [ 0.00 0.00 ] +Key: KXORQkk: [ 0.00 0.00 ] +Key: KXORWkk: [ 0.00 0.00 ] +Key: LAHF: [ 0.00 0.00 ] +Key: LAR: [ 0.00 0.00 ] +Key: LCMPXCHG: [ 0.00 0.00 ] +Key: LDDQUrm: [ 0.00 0.00 ] +Key: LDMXCSR: [ 0.00 0.00 ] +Key: LDS: [ 0.00 0.00 ] +Key: LDTILECFG: [ 0.00 0.00 ] +Key: LDTILECFG_EVEX: [ 0.00 0.00 ] +Key: LD_F: [ 0.00 0.00 ] +Key: LD_Fp: [ 0.00 0.00 ] +Key: LD_Frr: [ 0.00 0.00 ] +Key: LEA: [ 0.00 0.00 ] +Key: LEAVE: [ 0.00 0.00 ] +Key: LES: [ 0.00 0.00 ] +Key: LFENCE: [ 0.00 0.00 ] +Key: LFS: [ 0.00 0.00 ] +Key: LGDT: [ 0.00 0.00 ] +Key: LGS: [ 0.00 0.00 ] +Key: LIDT: [ 0.00 0.00 ] +Key: LIFETIME_END: [ 0.00 0.00 ] +Key: LIFETIME_START: [ 0.00 0.00 ] +Key: LKGS: [ 0.00 0.00 ] +Key: LLDT: [ 0.00 0.00 ] +Key: LLWPCB: [ 0.00 0.00 ] +Key: LMSW: [ 0.00 0.00 ] +Key: LOADIWKEY: [ 0.00 0.00 ] +Key: LOAD_STACK_GUARD: [ 0.00 0.00 ] +Key: LOCAL_ESCAPE: [ 0.00 0.00 ] +Key: LOCK_ADD: [ 0.00 0.00 ] +Key: LOCK_AND: [ 0.00 0.00 ] +Key: LOCK_BTC: [ 0.00 0.00 ] +Key: LOCK_BTC_RM: [ 0.00 0.00 ] +Key: LOCK_BTR: [ 0.00 0.00 ] +Key: LOCK_BTR_RM: [ 0.00 0.00 ] +Key: LOCK_BTS: [ 0.00 0.00 ] +Key: LOCK_BTS_RM: [ 0.00 0.00 ] +Key: LOCK_DEC: [ 0.00 0.00 ] +Key: LOCK_INC: [ 0.00 0.00 ] +Key: LOCK_OR: [ 0.00 0.00 ] +Key: LOCK_PREFIX: [ 0.00 0.00 ] +Key: LOCK_SUB: [ 0.00 0.00 ] +Key: LOCK_XOR: [ 0.00 0.00 ] +Key: LODSB: [ 0.00 0.00 ] +Key: LODSL: [ 0.00 0.00 ] +Key: LODSQ: [ 0.00 0.00 ] +Key: LODSW: [ 0.00 0.00 ] +Key: LOOP: [ 0.00 0.00 ] +Key: LOOPE: [ 0.00 0.00 ] +Key: LOOPNE: [ 0.00 0.00 ] +Key: LRET: [ 0.00 0.00 ] +Key: LRETI: [ 0.00 0.00 ] +Key: LSL: [ 0.00 0.00 ] +Key: LSS: [ 0.00 0.00 ] +Key: LTRm: [ 0.00 0.00 ] +Key: LTRr: [ 0.00 0.00 ] +Key: LWPINS: [ 0.00 0.00 ] +Key: LWPVAL: [ 0.00 0.00 ] +Key: LXADD: [ 0.00 0.00 ] +Key: LZCNT: [ 0.00 0.00 ] +Key: MASKMOVDQU: [ 0.00 0.00 ] +Key: MASKPAIR: [ 0.00 0.00 ] +Key: MAXCPDrm: [ 0.00 0.00 ] +Key: MAXCPDrr: [ 0.00 0.00 ] +Key: MAXCPSrm: [ 0.00 0.00 ] +Key: MAXCPSrr: [ 0.00 0.00 ] +Key: MAXCSDrm: [ 0.00 0.00 ] +Key: MAXCSDrr: [ 0.00 0.00 ] +Key: MAXCSSrm: [ 0.00 0.00 ] +Key: MAXCSSrr: [ 0.00 0.00 ] +Key: MAXPDrm: [ 0.00 0.00 ] +Key: MAXPDrr: [ 0.00 0.00 ] +Key: MAXPSrm: [ 0.00 0.00 ] +Key: MAXPSrr: [ 0.00 0.00 ] +Key: MAXSDrm: [ 0.00 0.00 ] +Key: MAXSDrm_Int: [ 0.00 0.00 ] +Key: MAXSDrr: [ 0.00 0.00 ] +Key: MAXSDrr_Int: [ 0.00 0.00 ] +Key: MAXSSrm: [ 0.00 0.00 ] +Key: MAXSSrm_Int: [ 0.00 0.00 ] +Key: MAXSSrr: [ 0.00 0.00 ] +Key: MAXSSrr_Int: [ 0.00 0.00 ] +Key: MEMBARRIER: [ 0.00 0.00 ] +Key: MFENCE: [ 0.00 0.00 ] +Key: MINCPDrm: [ 0.00 0.00 ] +Key: MINCPDrr: [ 0.00 0.00 ] +Key: MINCPSrm: [ 0.00 0.00 ] +Key: MINCPSrr: [ 0.00 0.00 ] +Key: MINCSDrm: [ 0.00 0.00 ] +Key: MINCSDrr: [ 0.00 0.00 ] +Key: MINCSSrm: [ 0.00 0.00 ] +Key: MINCSSrr: [ 0.00 0.00 ] +Key: MINPDrm: [ 0.00 0.00 ] +Key: MINPDrr: [ 0.00 0.00 ] +Key: MINPSrm: [ 0.00 0.00 ] +Key: MINPSrr: [ 0.00 0.00 ] +Key: MINSDrm: [ 0.00 0.00 ] +Key: MINSDrm_Int: [ 0.00 0.00 ] +Key: MINSDrr: [ 0.00 0.00 ] +Key: MINSDrr_Int: [ 0.00 0.00 ] +Key: MINSSrm: [ 0.00 0.00 ] +Key: MINSSrm_Int: [ 0.00 0.00 ] +Key: MINSSrr: [ 0.00 0.00 ] +Key: MINSSrr_Int: [ 0.00 0.00 ] +Key: MMX_CVTPD: [ 0.00 0.00 ] +Key: MMX_CVTPI: [ 0.00 0.00 ] +Key: MMX_CVTPS: [ 0.00 0.00 ] +Key: MMX_CVTTPD: [ 0.00 0.00 ] +Key: MMX_CVTTPS: [ 0.00 0.00 ] +Key: MMX_EMMS: [ 0.00 0.00 ] +Key: MMX_MASKMOVQ: [ 0.00 0.00 ] +Key: MMX_MOVD: [ 0.00 0.00 ] +Key: MMX_MOVDQ: [ 0.00 0.00 ] +Key: MMX_MOVFR: [ 0.00 0.00 ] +Key: MMX_MOVNTQmr: [ 0.00 0.00 ] +Key: MMX_MOVQ: [ 0.00 0.00 ] +Key: MMX_PABSBrm: [ 0.00 0.00 ] +Key: MMX_PABSBrr: [ 0.00 0.00 ] +Key: MMX_PABSDrm: [ 0.00 0.00 ] +Key: MMX_PABSDrr: [ 0.00 0.00 ] +Key: MMX_PABSWrm: [ 0.00 0.00 ] +Key: MMX_PABSWrr: [ 0.00 0.00 ] +Key: MMX_PACKSSDWrm: [ 0.00 0.00 ] +Key: MMX_PACKSSDWrr: [ 0.00 0.00 ] +Key: MMX_PACKSSWBrm: [ 0.00 0.00 ] +Key: MMX_PACKSSWBrr: [ 0.00 0.00 ] +Key: MMX_PACKUSWBrm: [ 0.00 0.00 ] +Key: MMX_PACKUSWBrr: [ 0.00 0.00 ] +Key: MMX_PADDBrm: [ 0.00 0.00 ] +Key: MMX_PADDBrr: [ 0.00 0.00 ] +Key: MMX_PADDDrm: [ 0.00 0.00 ] +Key: MMX_PADDDrr: [ 0.00 0.00 ] +Key: MMX_PADDQrm: [ 0.00 0.00 ] +Key: MMX_PADDQrr: [ 0.00 0.00 ] +Key: MMX_PADDSBrm: [ 0.00 0.00 ] +Key: MMX_PADDSBrr: [ 0.00 0.00 ] +Key: MMX_PADDSWrm: [ 0.00 0.00 ] +Key: MMX_PADDSWrr: [ 0.00 0.00 ] +Key: MMX_PADDUSBrm: [ 0.00 0.00 ] +Key: MMX_PADDUSBrr: [ 0.00 0.00 ] +Key: MMX_PADDUSWrm: [ 0.00 0.00 ] +Key: MMX_PADDUSWrr: [ 0.00 0.00 ] +Key: MMX_PADDWrm: [ 0.00 0.00 ] +Key: MMX_PADDWrr: [ 0.00 0.00 ] +Key: MMX_PALIGNRrmi: [ 0.00 0.00 ] +Key: MMX_PALIGNRrri: [ 0.00 0.00 ] +Key: MMX_PANDNrm: [ 0.00 0.00 ] +Key: MMX_PANDNrr: [ 0.00 0.00 ] +Key: MMX_PANDrm: [ 0.00 0.00 ] +Key: MMX_PANDrr: [ 0.00 0.00 ] +Key: MMX_PAVGBrm: [ 0.00 0.00 ] +Key: MMX_PAVGBrr: [ 0.00 0.00 ] +Key: MMX_PAVGWrm: [ 0.00 0.00 ] +Key: MMX_PAVGWrr: [ 0.00 0.00 ] +Key: MMX_PCMPEQBrm: [ 0.00 0.00 ] +Key: MMX_PCMPEQBrr: [ 0.00 0.00 ] +Key: MMX_PCMPEQDrm: [ 0.00 0.00 ] +Key: MMX_PCMPEQDrr: [ 0.00 0.00 ] +Key: MMX_PCMPEQWrm: [ 0.00 0.00 ] +Key: MMX_PCMPEQWrr: [ 0.00 0.00 ] +Key: MMX_PCMPGTBrm: [ 0.00 0.00 ] +Key: MMX_PCMPGTBrr: [ 0.00 0.00 ] +Key: MMX_PCMPGTDrm: [ 0.00 0.00 ] +Key: MMX_PCMPGTDrr: [ 0.00 0.00 ] +Key: MMX_PCMPGTWrm: [ 0.00 0.00 ] +Key: MMX_PCMPGTWrr: [ 0.00 0.00 ] +Key: MMX_PEXTRWrri: [ 0.00 0.00 ] +Key: MMX_PHADDDrm: [ 0.00 0.00 ] +Key: MMX_PHADDDrr: [ 0.00 0.00 ] +Key: MMX_PHADDSWrm: [ 0.00 0.00 ] +Key: MMX_PHADDSWrr: [ 0.00 0.00 ] +Key: MMX_PHADDWrm: [ 0.00 0.00 ] +Key: MMX_PHADDWrr: [ 0.00 0.00 ] +Key: MMX_PHSUBDrm: [ 0.00 0.00 ] +Key: MMX_PHSUBDrr: [ 0.00 0.00 ] +Key: MMX_PHSUBSWrm: [ 0.00 0.00 ] +Key: MMX_PHSUBSWrr: [ 0.00 0.00 ] +Key: MMX_PHSUBWrm: [ 0.00 0.00 ] +Key: MMX_PHSUBWrr: [ 0.00 0.00 ] +Key: MMX_PINSRWrmi: [ 0.00 0.00 ] +Key: MMX_PINSRWrri: [ 0.00 0.00 ] +Key: MMX_PMADDUBSWrm: [ 0.00 0.00 ] +Key: MMX_PMADDUBSWrr: [ 0.00 0.00 ] +Key: MMX_PMADDWDrm: [ 0.00 0.00 ] +Key: MMX_PMADDWDrr: [ 0.00 0.00 ] +Key: MMX_PMAXSWrm: [ 0.00 0.00 ] +Key: MMX_PMAXSWrr: [ 0.00 0.00 ] +Key: MMX_PMAXUBrm: [ 0.00 0.00 ] +Key: MMX_PMAXUBrr: [ 0.00 0.00 ] +Key: MMX_PMINSWrm: [ 0.00 0.00 ] +Key: MMX_PMINSWrr: [ 0.00 0.00 ] +Key: MMX_PMINUBrm: [ 0.00 0.00 ] +Key: MMX_PMINUBrr: [ 0.00 0.00 ] +Key: MMX_PMOVMSKBrr: [ 0.00 0.00 ] +Key: MMX_PMULHRSWrm: [ 0.00 0.00 ] +Key: MMX_PMULHRSWrr: [ 0.00 0.00 ] +Key: MMX_PMULHUWrm: [ 0.00 0.00 ] +Key: MMX_PMULHUWrr: [ 0.00 0.00 ] +Key: MMX_PMULHWrm: [ 0.00 0.00 ] +Key: MMX_PMULHWrr: [ 0.00 0.00 ] +Key: MMX_PMULLWrm: [ 0.00 0.00 ] +Key: MMX_PMULLWrr: [ 0.00 0.00 ] +Key: MMX_PMULUDQrm: [ 0.00 0.00 ] +Key: MMX_PMULUDQrr: [ 0.00 0.00 ] +Key: MMX_PORrm: [ 0.00 0.00 ] +Key: MMX_PORrr: [ 0.00 0.00 ] +Key: MMX_PSADBWrm: [ 0.00 0.00 ] +Key: MMX_PSADBWrr: [ 0.00 0.00 ] +Key: MMX_PSHUFBrm: [ 0.00 0.00 ] +Key: MMX_PSHUFBrr: [ 0.00 0.00 ] +Key: MMX_PSHUFWmi: [ 0.00 0.00 ] +Key: MMX_PSHUFWri: [ 0.00 0.00 ] +Key: MMX_PSIGNBrm: [ 0.00 0.00 ] +Key: MMX_PSIGNBrr: [ 0.00 0.00 ] +Key: MMX_PSIGNDrm: [ 0.00 0.00 ] +Key: MMX_PSIGNDrr: [ 0.00 0.00 ] +Key: MMX_PSIGNWrm: [ 0.00 0.00 ] +Key: MMX_PSIGNWrr: [ 0.00 0.00 ] +Key: MMX_PSLLDri: [ 0.00 0.00 ] +Key: MMX_PSLLDrm: [ 0.00 0.00 ] +Key: MMX_PSLLDrr: [ 0.00 0.00 ] +Key: MMX_PSLLQri: [ 0.00 0.00 ] +Key: MMX_PSLLQrm: [ 0.00 0.00 ] +Key: MMX_PSLLQrr: [ 0.00 0.00 ] +Key: MMX_PSLLWri: [ 0.00 0.00 ] +Key: MMX_PSLLWrm: [ 0.00 0.00 ] +Key: MMX_PSLLWrr: [ 0.00 0.00 ] +Key: MMX_PSRADri: [ 0.00 0.00 ] +Key: MMX_PSRADrm: [ 0.00 0.00 ] +Key: MMX_PSRADrr: [ 0.00 0.00 ] +Key: MMX_PSRAWri: [ 0.00 0.00 ] +Key: MMX_PSRAWrm: [ 0.00 0.00 ] +Key: MMX_PSRAWrr: [ 0.00 0.00 ] +Key: MMX_PSRLDri: [ 0.00 0.00 ] +Key: MMX_PSRLDrm: [ 0.00 0.00 ] +Key: MMX_PSRLDrr: [ 0.00 0.00 ] +Key: MMX_PSRLQri: [ 0.00 0.00 ] +Key: MMX_PSRLQrm: [ 0.00 0.00 ] +Key: MMX_PSRLQrr: [ 0.00 0.00 ] +Key: MMX_PSRLWri: [ 0.00 0.00 ] +Key: MMX_PSRLWrm: [ 0.00 0.00 ] +Key: MMX_PSRLWrr: [ 0.00 0.00 ] +Key: MMX_PSUBBrm: [ 0.00 0.00 ] +Key: MMX_PSUBBrr: [ 0.00 0.00 ] +Key: MMX_PSUBDrm: [ 0.00 0.00 ] +Key: MMX_PSUBDrr: [ 0.00 0.00 ] +Key: MMX_PSUBQrm: [ 0.00 0.00 ] +Key: MMX_PSUBQrr: [ 0.00 0.00 ] +Key: MMX_PSUBSBrm: [ 0.00 0.00 ] +Key: MMX_PSUBSBrr: [ 0.00 0.00 ] +Key: MMX_PSUBSWrm: [ 0.00 0.00 ] +Key: MMX_PSUBSWrr: [ 0.00 0.00 ] +Key: MMX_PSUBUSBrm: [ 0.00 0.00 ] +Key: MMX_PSUBUSBrr: [ 0.00 0.00 ] +Key: MMX_PSUBUSWrm: [ 0.00 0.00 ] +Key: MMX_PSUBUSWrr: [ 0.00 0.00 ] +Key: MMX_PSUBWrm: [ 0.00 0.00 ] +Key: MMX_PSUBWrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKHBWrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKHBWrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKHDQrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKHDQrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKHWDrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKHWDrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKLBWrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKLBWrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKLDQrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKLDQrr: [ 0.00 0.00 ] +Key: MMX_PUNPCKLWDrm: [ 0.00 0.00 ] +Key: MMX_PUNPCKLWDrr: [ 0.00 0.00 ] +Key: MMX_PXORrm: [ 0.00 0.00 ] +Key: MMX_PXORrr: [ 0.00 0.00 ] +Key: MMX_SET: [ 0.00 0.00 ] +Key: MONITOR: [ 0.00 0.00 ] +Key: MONITORX: [ 0.00 0.00 ] +Key: MONTMUL: [ 0.00 0.00 ] +Key: MORESTACK_RET: [ 0.00 0.00 ] +Key: MORESTACK_RET_RESTORE_R: [ 0.00 0.00 ] +Key: MOV: [ 0.00 0.00 ] +Key: MOVAPDmr: [ 0.00 0.00 ] +Key: MOVAPDrm: [ 0.00 0.00 ] +Key: MOVAPDrr: [ 0.00 0.00 ] +Key: MOVAPDrr_REV: [ 0.00 0.00 ] +Key: MOVAPSmr: [ 0.00 0.00 ] +Key: MOVAPSrm: [ 0.00 0.00 ] +Key: MOVAPSrr: [ 0.00 0.00 ] +Key: MOVAPSrr_REV: [ 0.00 0.00 ] +Key: MOVBE: [ 0.00 0.00 ] +Key: MOVDDUPrm: [ 0.00 0.00 ] +Key: MOVDDUPrr: [ 0.00 0.00 ] +Key: MOVDI: [ 0.00 0.00 ] +Key: MOVDIR: [ 0.00 0.00 ] +Key: MOVDIRI: [ 0.00 0.00 ] +Key: MOVDQAmr: [ 0.00 0.00 ] +Key: MOVDQArm: [ 0.00 0.00 ] +Key: MOVDQArr: [ 0.00 0.00 ] +Key: MOVDQArr_REV: [ 0.00 0.00 ] +Key: MOVDQUmr: [ 0.00 0.00 ] +Key: MOVDQUrm: [ 0.00 0.00 ] +Key: MOVDQUrr: [ 0.00 0.00 ] +Key: MOVDQUrr_REV: [ 0.00 0.00 ] +Key: MOVHLPSrr: [ 0.00 0.00 ] +Key: MOVHPDmr: [ 0.00 0.00 ] +Key: MOVHPDrm: [ 0.00 0.00 ] +Key: MOVHPSmr: [ 0.00 0.00 ] +Key: MOVHPSrm: [ 0.00 0.00 ] +Key: MOVLHPSrr: [ 0.00 0.00 ] +Key: MOVLPDmr: [ 0.00 0.00 ] +Key: MOVLPDrm: [ 0.00 0.00 ] +Key: MOVLPSmr: [ 0.00 0.00 ] +Key: MOVLPSrm: [ 0.00 0.00 ] +Key: MOVMSKPDrr: [ 0.00 0.00 ] +Key: MOVMSKPSrr: [ 0.00 0.00 ] +Key: MOVNTDQArm: [ 0.00 0.00 ] +Key: MOVNTDQmr: [ 0.00 0.00 ] +Key: MOVNTI: [ 0.00 0.00 ] +Key: MOVNTImr: [ 0.00 0.00 ] +Key: MOVNTPDmr: [ 0.00 0.00 ] +Key: MOVNTPSmr: [ 0.00 0.00 ] +Key: MOVNTSD: [ 0.00 0.00 ] +Key: MOVNTSS: [ 0.00 0.00 ] +Key: MOVPC: [ 0.00 0.00 ] +Key: MOVPDI: [ 0.00 0.00 ] +Key: MOVPQI: [ 0.00 0.00 ] +Key: MOVPQIto: [ 0.00 0.00 ] +Key: MOVQI: [ 0.00 0.00 ] +Key: MOVRS: [ 0.00 0.00 ] +Key: MOVSB: [ 0.00 0.00 ] +Key: MOVSDmr: [ 0.00 0.00 ] +Key: MOVSDrm: [ 0.00 0.00 ] +Key: MOVSDrm_alt: [ 0.00 0.00 ] +Key: MOVSDrr: [ 0.00 0.00 ] +Key: MOVSDrr_REV: [ 0.00 0.00 ] +Key: MOVSDto: [ 0.00 0.00 ] +Key: MOVSHDUPrm: [ 0.00 0.00 ] +Key: MOVSHDUPrr: [ 0.00 0.00 ] +Key: MOVSHPmr: [ 0.00 0.00 ] +Key: MOVSHPrm: [ 0.00 0.00 ] +Key: MOVSL: [ 0.00 0.00 ] +Key: MOVSLDUPrm: [ 0.00 0.00 ] +Key: MOVSLDUPrr: [ 0.00 0.00 ] +Key: MOVSQ: [ 0.00 0.00 ] +Key: MOVSS: [ 0.00 0.00 ] +Key: MOVSSmr: [ 0.00 0.00 ] +Key: MOVSSrm: [ 0.00 0.00 ] +Key: MOVSSrm_alt: [ 0.00 0.00 ] +Key: MOVSSrr: [ 0.00 0.00 ] +Key: MOVSSrr_REV: [ 0.00 0.00 ] +Key: MOVSW: [ 0.00 0.00 ] +Key: MOVSX: [ 0.00 0.00 ] +Key: MOVUPDmr: [ 0.00 0.00 ] +Key: MOVUPDrm: [ 0.00 0.00 ] +Key: MOVUPDrr: [ 0.00 0.00 ] +Key: MOVUPDrr_REV: [ 0.00 0.00 ] +Key: MOVUPSmr: [ 0.00 0.00 ] +Key: MOVUPSrm: [ 0.00 0.00 ] +Key: MOVUPSrr: [ 0.00 0.00 ] +Key: MOVUPSrr_REV: [ 0.00 0.00 ] +Key: MOVZPQILo: [ 0.00 0.00 ] +Key: MOVZX: [ 0.00 0.00 ] +Key: MPSADBWrmi: [ 0.00 0.00 ] +Key: MPSADBWrri: [ 0.00 0.00 ] +Key: MUL: [ 0.00 0.00 ] +Key: MULPDrm: [ 0.00 0.00 ] +Key: MULPDrr: [ 0.00 0.00 ] +Key: MULPSrm: [ 0.00 0.00 ] +Key: MULPSrr: [ 0.00 0.00 ] +Key: MULSDrm: [ 0.00 0.00 ] +Key: MULSDrm_Int: [ 0.00 0.00 ] +Key: MULSDrr: [ 0.00 0.00 ] +Key: MULSDrr_Int: [ 0.00 0.00 ] +Key: MULSSrm: [ 0.00 0.00 ] +Key: MULSSrm_Int: [ 0.00 0.00 ] +Key: MULSSrr: [ 0.00 0.00 ] +Key: MULSSrr_Int: [ 0.00 0.00 ] +Key: MULX: [ 0.00 0.00 ] +Key: MUL_F: [ 0.00 0.00 ] +Key: MUL_FI: [ 0.00 0.00 ] +Key: MUL_FPrST: [ 0.00 0.00 ] +Key: MUL_FST: [ 0.00 0.00 ] +Key: MUL_Fp: [ 0.00 0.00 ] +Key: MUL_FpI: [ 0.00 0.00 ] +Key: MUL_FrST: [ 0.00 0.00 ] +Key: MWAITX: [ 0.00 0.00 ] +Key: MWAITX_SAVE_RBX: [ 0.00 0.00 ] +Key: MWAITXrrr: [ 0.00 0.00 ] +Key: MWAITrr: [ 0.00 0.00 ] +Key: NEG: [ 0.00 0.00 ] +Key: NOOP: [ 0.00 0.00 ] +Key: NOOPL: [ 0.00 0.00 ] +Key: NOOPLr: [ 0.00 0.00 ] +Key: NOOPQ: [ 0.00 0.00 ] +Key: NOOPQr: [ 0.00 0.00 ] +Key: NOOPW: [ 0.00 0.00 ] +Key: NOOPWr: [ 0.00 0.00 ] +Key: NOT: [ 0.00 0.00 ] +Key: OR: [ 0.00 0.00 ] +Key: ORPDrm: [ 0.00 0.00 ] +Key: ORPDrr: [ 0.00 0.00 ] +Key: ORPSrm: [ 0.00 0.00 ] +Key: ORPSrr: [ 0.00 0.00 ] +Key: OUT: [ 0.00 0.00 ] +Key: OUTSB: [ 0.00 0.00 ] +Key: OUTSL: [ 0.00 0.00 ] +Key: OUTSW: [ 0.00 0.00 ] +Key: PABSBrm: [ 0.00 0.00 ] +Key: PABSBrr: [ 0.00 0.00 ] +Key: PABSDrm: [ 0.00 0.00 ] +Key: PABSDrr: [ 0.00 0.00 ] +Key: PABSWrm: [ 0.00 0.00 ] +Key: PABSWrr: [ 0.00 0.00 ] +Key: PACKSSDWrm: [ 0.00 0.00 ] +Key: PACKSSDWrr: [ 0.00 0.00 ] +Key: PACKSSWBrm: [ 0.00 0.00 ] +Key: PACKSSWBrr: [ 0.00 0.00 ] +Key: PACKUSDWrm: [ 0.00 0.00 ] +Key: PACKUSDWrr: [ 0.00 0.00 ] +Key: PACKUSWBrm: [ 0.00 0.00 ] +Key: PACKUSWBrr: [ 0.00 0.00 ] +Key: PADDBrm: [ 0.00 0.00 ] +Key: PADDBrr: [ 0.00 0.00 ] +Key: PADDDrm: [ 0.00 0.00 ] +Key: PADDDrr: [ 0.00 0.00 ] +Key: PADDQrm: [ 0.00 0.00 ] +Key: PADDQrr: [ 0.00 0.00 ] +Key: PADDSBrm: [ 0.00 0.00 ] +Key: PADDSBrr: [ 0.00 0.00 ] +Key: PADDSWrm: [ 0.00 0.00 ] +Key: PADDSWrr: [ 0.00 0.00 ] +Key: PADDUSBrm: [ 0.00 0.00 ] +Key: PADDUSBrr: [ 0.00 0.00 ] +Key: PADDUSWrm: [ 0.00 0.00 ] +Key: PADDUSWrr: [ 0.00 0.00 ] +Key: PADDWrm: [ 0.00 0.00 ] +Key: PADDWrr: [ 0.00 0.00 ] +Key: PALIGNRrmi: [ 0.00 0.00 ] +Key: PALIGNRrri: [ 0.00 0.00 ] +Key: PANDNrm: [ 0.00 0.00 ] +Key: PANDNrr: [ 0.00 0.00 ] +Key: PANDrm: [ 0.00 0.00 ] +Key: PANDrr: [ 0.00 0.00 ] +Key: PATCHABLE_EVENT_CALL: [ 0.00 0.00 ] +Key: PATCHABLE_FUNCTION_ENTER: [ 0.00 0.00 ] +Key: PATCHABLE_FUNCTION_EXIT: [ 0.00 0.00 ] +Key: PATCHABLE_OP: [ 0.00 0.00 ] +Key: PATCHABLE_RET: [ 0.00 0.00 ] +Key: PATCHABLE_TAIL_CALL: [ 0.00 0.00 ] +Key: PATCHABLE_TYPED_EVENT_CALL: [ 0.00 0.00 ] +Key: PATCHPOINT: [ 0.00 0.00 ] +Key: PAUSE: [ 0.00 0.00 ] +Key: PAVGBrm: [ 0.00 0.00 ] +Key: PAVGBrr: [ 0.00 0.00 ] +Key: PAVGUSBrm: [ 0.00 0.00 ] +Key: PAVGUSBrr: [ 0.00 0.00 ] +Key: PAVGWrm: [ 0.00 0.00 ] +Key: PAVGWrr: [ 0.00 0.00 ] +Key: PBLENDVBrm: [ 0.00 0.00 ] +Key: PBLENDVBrr: [ 0.00 0.00 ] +Key: PBLENDWrmi: [ 0.00 0.00 ] +Key: PBLENDWrri: [ 0.00 0.00 ] +Key: PBNDKB: [ 0.00 0.00 ] +Key: PCLMULQDQrmi: [ 0.00 0.00 ] +Key: PCLMULQDQrri: [ 0.00 0.00 ] +Key: PCMPEQBrm: [ 0.00 0.00 ] +Key: PCMPEQBrr: [ 0.00 0.00 ] +Key: PCMPEQDrm: [ 0.00 0.00 ] +Key: PCMPEQDrr: [ 0.00 0.00 ] +Key: PCMPEQQrm: [ 0.00 0.00 ] +Key: PCMPEQQrr: [ 0.00 0.00 ] +Key: PCMPEQWrm: [ 0.00 0.00 ] +Key: PCMPEQWrr: [ 0.00 0.00 ] +Key: PCMPESTRIrmi: [ 0.00 0.00 ] +Key: PCMPESTRIrri: [ 0.00 0.00 ] +Key: PCMPESTRMrmi: [ 0.00 0.00 ] +Key: PCMPESTRMrri: [ 0.00 0.00 ] +Key: PCMPGTBrm: [ 0.00 0.00 ] +Key: PCMPGTBrr: [ 0.00 0.00 ] +Key: PCMPGTDrm: [ 0.00 0.00 ] +Key: PCMPGTDrr: [ 0.00 0.00 ] +Key: PCMPGTQrm: [ 0.00 0.00 ] +Key: PCMPGTQrr: [ 0.00 0.00 ] +Key: PCMPGTWrm: [ 0.00 0.00 ] +Key: PCMPGTWrr: [ 0.00 0.00 ] +Key: PCMPISTRIrmi: [ 0.00 0.00 ] +Key: PCMPISTRIrri: [ 0.00 0.00 ] +Key: PCMPISTRMrmi: [ 0.00 0.00 ] +Key: PCMPISTRMrri: [ 0.00 0.00 ] +Key: PCONFIG: [ 0.00 0.00 ] +Key: PDEP: [ 0.00 0.00 ] +Key: PEXT: [ 0.00 0.00 ] +Key: PEXTRBmri: [ 0.00 0.00 ] +Key: PEXTRBrri: [ 0.00 0.00 ] +Key: PEXTRDmri: [ 0.00 0.00 ] +Key: PEXTRDrri: [ 0.00 0.00 ] +Key: PEXTRQmri: [ 0.00 0.00 ] +Key: PEXTRQrri: [ 0.00 0.00 ] +Key: PEXTRWmri: [ 0.00 0.00 ] +Key: PEXTRWrri: [ 0.00 0.00 ] +Key: PEXTRWrri_REV: [ 0.00 0.00 ] +Key: PF: [ 0.00 0.00 ] +Key: PFACCrm: [ 0.00 0.00 ] +Key: PFACCrr: [ 0.00 0.00 ] +Key: PFADDrm: [ 0.00 0.00 ] +Key: PFADDrr: [ 0.00 0.00 ] +Key: PFCMPEQrm: [ 0.00 0.00 ] +Key: PFCMPEQrr: [ 0.00 0.00 ] +Key: PFCMPGErm: [ 0.00 0.00 ] +Key: PFCMPGErr: [ 0.00 0.00 ] +Key: PFCMPGTrm: [ 0.00 0.00 ] +Key: PFCMPGTrr: [ 0.00 0.00 ] +Key: PFMAXrm: [ 0.00 0.00 ] +Key: PFMAXrr: [ 0.00 0.00 ] +Key: PFMINrm: [ 0.00 0.00 ] +Key: PFMINrr: [ 0.00 0.00 ] +Key: PFMULrm: [ 0.00 0.00 ] +Key: PFMULrr: [ 0.00 0.00 ] +Key: PFNACCrm: [ 0.00 0.00 ] +Key: PFNACCrr: [ 0.00 0.00 ] +Key: PFPNACCrm: [ 0.00 0.00 ] +Key: PFPNACCrr: [ 0.00 0.00 ] +Key: PFRCPIT: [ 0.00 0.00 ] +Key: PFRCPrm: [ 0.00 0.00 ] +Key: PFRCPrr: [ 0.00 0.00 ] +Key: PFRSQIT: [ 0.00 0.00 ] +Key: PFRSQRTrm: [ 0.00 0.00 ] +Key: PFRSQRTrr: [ 0.00 0.00 ] +Key: PFSUBRrm: [ 0.00 0.00 ] +Key: PFSUBRrr: [ 0.00 0.00 ] +Key: PFSUBrm: [ 0.00 0.00 ] +Key: PFSUBrr: [ 0.00 0.00 ] +Key: PHADDDrm: [ 0.00 0.00 ] +Key: PHADDDrr: [ 0.00 0.00 ] +Key: PHADDSWrm: [ 0.00 0.00 ] +Key: PHADDSWrr: [ 0.00 0.00 ] +Key: PHADDWrm: [ 0.00 0.00 ] +Key: PHADDWrr: [ 0.00 0.00 ] +Key: PHI: [ 0.00 0.00 ] +Key: PHMINPOSUWrm: [ 0.00 0.00 ] +Key: PHMINPOSUWrr: [ 0.00 0.00 ] +Key: PHSUBDrm: [ 0.00 0.00 ] +Key: PHSUBDrr: [ 0.00 0.00 ] +Key: PHSUBSWrm: [ 0.00 0.00 ] +Key: PHSUBSWrr: [ 0.00 0.00 ] +Key: PHSUBWrm: [ 0.00 0.00 ] +Key: PHSUBWrr: [ 0.00 0.00 ] +Key: PI: [ 0.00 0.00 ] +Key: PINSRBrmi: [ 0.00 0.00 ] +Key: PINSRBrri: [ 0.00 0.00 ] +Key: PINSRDrmi: [ 0.00 0.00 ] +Key: PINSRDrri: [ 0.00 0.00 ] +Key: PINSRQrmi: [ 0.00 0.00 ] +Key: PINSRQrri: [ 0.00 0.00 ] +Key: PINSRWrmi: [ 0.00 0.00 ] +Key: PINSRWrri: [ 0.00 0.00 ] +Key: PLDTILECFGV: [ 0.00 0.00 ] +Key: PLEA: [ 0.00 0.00 ] +Key: PMADDUBSWrm: [ 0.00 0.00 ] +Key: PMADDUBSWrr: [ 0.00 0.00 ] +Key: PMADDWDrm: [ 0.00 0.00 ] +Key: PMADDWDrr: [ 0.00 0.00 ] +Key: PMAXSBrm: [ 0.00 0.00 ] +Key: PMAXSBrr: [ 0.00 0.00 ] +Key: PMAXSDrm: [ 0.00 0.00 ] +Key: PMAXSDrr: [ 0.00 0.00 ] +Key: PMAXSWrm: [ 0.00 0.00 ] +Key: PMAXSWrr: [ 0.00 0.00 ] +Key: PMAXUBrm: [ 0.00 0.00 ] +Key: PMAXUBrr: [ 0.00 0.00 ] +Key: PMAXUDrm: [ 0.00 0.00 ] +Key: PMAXUDrr: [ 0.00 0.00 ] +Key: PMAXUWrm: [ 0.00 0.00 ] +Key: PMAXUWrr: [ 0.00 0.00 ] +Key: PMINSBrm: [ 0.00 0.00 ] +Key: PMINSBrr: [ 0.00 0.00 ] +Key: PMINSDrm: [ 0.00 0.00 ] +Key: PMINSDrr: [ 0.00 0.00 ] +Key: PMINSWrm: [ 0.00 0.00 ] +Key: PMINSWrr: [ 0.00 0.00 ] +Key: PMINUBrm: [ 0.00 0.00 ] +Key: PMINUBrr: [ 0.00 0.00 ] +Key: PMINUDrm: [ 0.00 0.00 ] +Key: PMINUDrr: [ 0.00 0.00 ] +Key: PMINUWrm: [ 0.00 0.00 ] +Key: PMINUWrr: [ 0.00 0.00 ] +Key: PMOVMSKBrr: [ 0.00 0.00 ] +Key: PMOVSXBDrm: [ 0.00 0.00 ] +Key: PMOVSXBDrr: [ 0.00 0.00 ] +Key: PMOVSXBQrm: [ 0.00 0.00 ] +Key: PMOVSXBQrr: [ 0.00 0.00 ] +Key: PMOVSXBWrm: [ 0.00 0.00 ] +Key: PMOVSXBWrr: [ 0.00 0.00 ] +Key: PMOVSXDQrm: [ 0.00 0.00 ] +Key: PMOVSXDQrr: [ 0.00 0.00 ] +Key: PMOVSXWDrm: [ 0.00 0.00 ] +Key: PMOVSXWDrr: [ 0.00 0.00 ] +Key: PMOVSXWQrm: [ 0.00 0.00 ] +Key: PMOVSXWQrr: [ 0.00 0.00 ] +Key: PMOVZXBDrm: [ 0.00 0.00 ] +Key: PMOVZXBDrr: [ 0.00 0.00 ] +Key: PMOVZXBQrm: [ 0.00 0.00 ] +Key: PMOVZXBQrr: [ 0.00 0.00 ] +Key: PMOVZXBWrm: [ 0.00 0.00 ] +Key: PMOVZXBWrr: [ 0.00 0.00 ] +Key: PMOVZXDQrm: [ 0.00 0.00 ] +Key: PMOVZXDQrr: [ 0.00 0.00 ] +Key: PMOVZXWDrm: [ 0.00 0.00 ] +Key: PMOVZXWDrr: [ 0.00 0.00 ] +Key: PMOVZXWQrm: [ 0.00 0.00 ] +Key: PMOVZXWQrr: [ 0.00 0.00 ] +Key: PMULDQrm: [ 0.00 0.00 ] +Key: PMULDQrr: [ 0.00 0.00 ] +Key: PMULHRSWrm: [ 0.00 0.00 ] +Key: PMULHRSWrr: [ 0.00 0.00 ] +Key: PMULHRWrm: [ 0.00 0.00 ] +Key: PMULHRWrr: [ 0.00 0.00 ] +Key: PMULHUWrm: [ 0.00 0.00 ] +Key: PMULHUWrr: [ 0.00 0.00 ] +Key: PMULHWrm: [ 0.00 0.00 ] +Key: PMULHWrr: [ 0.00 0.00 ] +Key: PMULLDrm: [ 0.00 0.00 ] +Key: PMULLDrr: [ 0.00 0.00 ] +Key: PMULLWrm: [ 0.00 0.00 ] +Key: PMULLWrr: [ 0.00 0.00 ] +Key: PMULUDQrm: [ 0.00 0.00 ] +Key: PMULUDQrr: [ 0.00 0.00 ] +Key: POP: [ 0.00 0.00 ] +Key: POPA: [ 0.00 0.00 ] +Key: POPCNT: [ 0.00 0.00 ] +Key: POPDS: [ 0.00 0.00 ] +Key: POPES: [ 0.00 0.00 ] +Key: POPF: [ 0.00 0.00 ] +Key: POPFS: [ 0.00 0.00 ] +Key: POPGS: [ 0.00 0.00 ] +Key: POPP: [ 0.00 0.00 ] +Key: POPSS: [ 0.00 0.00 ] +Key: PORrm: [ 0.00 0.00 ] +Key: PORrr: [ 0.00 0.00 ] +Key: PREALLOCATED_ARG: [ 0.00 0.00 ] +Key: PREALLOCATED_SETUP: [ 0.00 0.00 ] +Key: PREFETCH: [ 0.00 0.00 ] +Key: PREFETCHIT: [ 0.00 0.00 ] +Key: PREFETCHNTA: [ 0.00 0.00 ] +Key: PREFETCHRST: [ 0.00 0.00 ] +Key: PREFETCHT: [ 0.00 0.00 ] +Key: PREFETCHW: [ 0.00 0.00 ] +Key: PREFETCHWT: [ 0.00 0.00 ] +Key: PROBED_ALLOCA: [ 0.00 0.00 ] +Key: PSADBWrm: [ 0.00 0.00 ] +Key: PSADBWrr: [ 0.00 0.00 ] +Key: PSEUDO_PROBE: [ 0.00 0.00 ] +Key: PSHUFBrm: [ 0.00 0.00 ] +Key: PSHUFBrr: [ 0.00 0.00 ] +Key: PSHUFDmi: [ 0.00 0.00 ] +Key: PSHUFDri: [ 0.00 0.00 ] +Key: PSHUFHWmi: [ 0.00 0.00 ] +Key: PSHUFHWri: [ 0.00 0.00 ] +Key: PSHUFLWmi: [ 0.00 0.00 ] +Key: PSHUFLWri: [ 0.00 0.00 ] +Key: PSIGNBrm: [ 0.00 0.00 ] +Key: PSIGNBrr: [ 0.00 0.00 ] +Key: PSIGNDrm: [ 0.00 0.00 ] +Key: PSIGNDrr: [ 0.00 0.00 ] +Key: PSIGNWrm: [ 0.00 0.00 ] +Key: PSIGNWrr: [ 0.00 0.00 ] +Key: PSLLDQri: [ 0.00 0.00 ] +Key: PSLLDri: [ 0.00 0.00 ] +Key: PSLLDrm: [ 0.00 0.00 ] +Key: PSLLDrr: [ 0.00 0.00 ] +Key: PSLLQri: [ 0.00 0.00 ] +Key: PSLLQrm: [ 0.00 0.00 ] +Key: PSLLQrr: [ 0.00 0.00 ] +Key: PSLLWri: [ 0.00 0.00 ] +Key: PSLLWrm: [ 0.00 0.00 ] +Key: PSLLWrr: [ 0.00 0.00 ] +Key: PSMASH: [ 0.00 0.00 ] +Key: PSRADri: [ 0.00 0.00 ] +Key: PSRADrm: [ 0.00 0.00 ] +Key: PSRADrr: [ 0.00 0.00 ] +Key: PSRAWri: [ 0.00 0.00 ] +Key: PSRAWrm: [ 0.00 0.00 ] +Key: PSRAWrr: [ 0.00 0.00 ] +Key: PSRLDQri: [ 0.00 0.00 ] +Key: PSRLDri: [ 0.00 0.00 ] +Key: PSRLDrm: [ 0.00 0.00 ] +Key: PSRLDrr: [ 0.00 0.00 ] +Key: PSRLQri: [ 0.00 0.00 ] +Key: PSRLQrm: [ 0.00 0.00 ] +Key: PSRLQrr: [ 0.00 0.00 ] +Key: PSRLWri: [ 0.00 0.00 ] +Key: PSRLWrm: [ 0.00 0.00 ] +Key: PSRLWrr: [ 0.00 0.00 ] +Key: PSUBBrm: [ 0.00 0.00 ] +Key: PSUBBrr: [ 0.00 0.00 ] +Key: PSUBDrm: [ 0.00 0.00 ] +Key: PSUBDrr: [ 0.00 0.00 ] +Key: PSUBQrm: [ 0.00 0.00 ] +Key: PSUBQrr: [ 0.00 0.00 ] +Key: PSUBSBrm: [ 0.00 0.00 ] +Key: PSUBSBrr: [ 0.00 0.00 ] +Key: PSUBSWrm: [ 0.00 0.00 ] +Key: PSUBSWrr: [ 0.00 0.00 ] +Key: PSUBUSBrm: [ 0.00 0.00 ] +Key: PSUBUSBrr: [ 0.00 0.00 ] +Key: PSUBUSWrm: [ 0.00 0.00 ] +Key: PSUBUSWrr: [ 0.00 0.00 ] +Key: PSUBWrm: [ 0.00 0.00 ] +Key: PSUBWrr: [ 0.00 0.00 ] +Key: PSWAPDrm: [ 0.00 0.00 ] +Key: PSWAPDrr: [ 0.00 0.00 ] +Key: PT: [ 0.00 0.00 ] +Key: PTCMMIMFP: [ 0.00 0.00 ] +Key: PTCMMRLFP: [ 0.00 0.00 ] +Key: PTCONJTCMMIMFP: [ 0.00 0.00 ] +Key: PTCONJTFP: [ 0.00 0.00 ] +Key: PTCVTROWD: [ 0.00 0.00 ] +Key: PTCVTROWPS: [ 0.00 0.00 ] +Key: PTDPBF: [ 0.00 0.00 ] +Key: PTDPBHF: [ 0.00 0.00 ] +Key: PTDPBSSD: [ 0.00 0.00 ] +Key: PTDPBSSDV: [ 0.00 0.00 ] +Key: PTDPBSUD: [ 0.00 0.00 ] +Key: PTDPBSUDV: [ 0.00 0.00 ] +Key: PTDPBUSD: [ 0.00 0.00 ] +Key: PTDPBUSDV: [ 0.00 0.00 ] +Key: PTDPBUUD: [ 0.00 0.00 ] +Key: PTDPBUUDV: [ 0.00 0.00 ] +Key: PTDPFP: [ 0.00 0.00 ] +Key: PTDPHBF: [ 0.00 0.00 ] +Key: PTDPHF: [ 0.00 0.00 ] +Key: PTESTrm: [ 0.00 0.00 ] +Key: PTESTrr: [ 0.00 0.00 ] +Key: PTILELOADD: [ 0.00 0.00 ] +Key: PTILELOADDRS: [ 0.00 0.00 ] +Key: PTILELOADDRST: [ 0.00 0.00 ] +Key: PTILELOADDRSV: [ 0.00 0.00 ] +Key: PTILELOADDT: [ 0.00 0.00 ] +Key: PTILELOADDV: [ 0.00 0.00 ] +Key: PTILEMOVROWrre: [ 0.00 0.00 ] +Key: PTILEMOVROWrreV: [ 0.00 0.00 ] +Key: PTILEMOVROWrri: [ 0.00 0.00 ] +Key: PTILEMOVROWrriV: [ 0.00 0.00 ] +Key: PTILEPAIRLOAD: [ 0.00 0.00 ] +Key: PTILEPAIRSTORE: [ 0.00 0.00 ] +Key: PTILESTORED: [ 0.00 0.00 ] +Key: PTILESTOREDV: [ 0.00 0.00 ] +Key: PTILEZERO: [ 0.00 0.00 ] +Key: PTILEZEROV: [ 0.00 0.00 ] +Key: PTMMULTF: [ 0.00 0.00 ] +Key: PTTCMMIMFP: [ 0.00 0.00 ] +Key: PTTCMMRLFP: [ 0.00 0.00 ] +Key: PTTDPBF: [ 0.00 0.00 ] +Key: PTTDPFP: [ 0.00 0.00 ] +Key: PTTMMULTF: [ 0.00 0.00 ] +Key: PTTRANSPOSED: [ 0.00 0.00 ] +Key: PTTRANSPOSEDV: [ 0.00 0.00 ] +Key: PTWRITE: [ 0.00 0.00 ] +Key: PTWRITEm: [ 0.00 0.00 ] +Key: PTWRITEr: [ 0.00 0.00 ] +Key: PUNPCKHBWrm: [ 0.00 0.00 ] +Key: PUNPCKHBWrr: [ 0.00 0.00 ] +Key: PUNPCKHDQrm: [ 0.00 0.00 ] +Key: PUNPCKHDQrr: [ 0.00 0.00 ] +Key: PUNPCKHQDQrm: [ 0.00 0.00 ] +Key: PUNPCKHQDQrr: [ 0.00 0.00 ] +Key: PUNPCKHWDrm: [ 0.00 0.00 ] +Key: PUNPCKHWDrr: [ 0.00 0.00 ] +Key: PUNPCKLBWrm: [ 0.00 0.00 ] +Key: PUNPCKLBWrr: [ 0.00 0.00 ] +Key: PUNPCKLDQrm: [ 0.00 0.00 ] +Key: PUNPCKLDQrr: [ 0.00 0.00 ] +Key: PUNPCKLQDQrm: [ 0.00 0.00 ] +Key: PUNPCKLQDQrr: [ 0.00 0.00 ] +Key: PUNPCKLWDrm: [ 0.00 0.00 ] +Key: PUNPCKLWDrr: [ 0.00 0.00 ] +Key: PUSH: [ 0.00 0.00 ] +Key: PUSHA: [ 0.00 0.00 ] +Key: PUSHCS: [ 0.00 0.00 ] +Key: PUSHDS: [ 0.00 0.00 ] +Key: PUSHES: [ 0.00 0.00 ] +Key: PUSHF: [ 0.00 0.00 ] +Key: PUSHFS: [ 0.00 0.00 ] +Key: PUSHGS: [ 0.00 0.00 ] +Key: PUSHP: [ 0.00 0.00 ] +Key: PUSHSS: [ 0.00 0.00 ] +Key: PVALIDATE: [ 0.00 0.00 ] +Key: PXORrm: [ 0.00 0.00 ] +Key: PXORrr: [ 0.00 0.00 ] +Key: RCL: [ 0.00 0.00 ] +Key: RCPPSm: [ 0.00 0.00 ] +Key: RCPPSr: [ 0.00 0.00 ] +Key: RCPSSm: [ 0.00 0.00 ] +Key: RCPSSm_Int: [ 0.00 0.00 ] +Key: RCPSSr: [ 0.00 0.00 ] +Key: RCPSSr_Int: [ 0.00 0.00 ] +Key: RCR: [ 0.00 0.00 ] +Key: RDFLAGS: [ 0.00 0.00 ] +Key: RDFSBASE: [ 0.00 0.00 ] +Key: RDGSBASE: [ 0.00 0.00 ] +Key: RDMSR: [ 0.00 0.00 ] +Key: RDMSRLIST: [ 0.00 0.00 ] +Key: RDMSRri: [ 0.00 0.00 ] +Key: RDMSRri_EVEX: [ 0.00 0.00 ] +Key: RDPID: [ 0.00 0.00 ] +Key: RDPKRUr: [ 0.00 0.00 ] +Key: RDPMC: [ 0.00 0.00 ] +Key: RDPRU: [ 0.00 0.00 ] +Key: RDRAND: [ 0.00 0.00 ] +Key: RDSEED: [ 0.00 0.00 ] +Key: RDSSPD: [ 0.00 0.00 ] +Key: RDSSPQ: [ 0.00 0.00 ] +Key: RDTSC: [ 0.00 0.00 ] +Key: RDTSCP: [ 0.00 0.00 ] +Key: REG_SEQUENCE: [ 0.00 0.00 ] +Key: REPNE_PREFIX: [ 0.00 0.00 ] +Key: REP_MOVSB: [ 0.00 0.00 ] +Key: REP_MOVSD: [ 0.00 0.00 ] +Key: REP_MOVSQ: [ 0.00 0.00 ] +Key: REP_MOVSW: [ 0.00 0.00 ] +Key: REP_PREFIX: [ 0.00 0.00 ] +Key: REP_STOSB: [ 0.00 0.00 ] +Key: REP_STOSD: [ 0.00 0.00 ] +Key: REP_STOSQ: [ 0.00 0.00 ] +Key: REP_STOSW: [ 0.00 0.00 ] +Key: RET: [ 0.00 0.00 ] +Key: RETI: [ 0.00 0.00 ] +Key: REX: [ 0.00 0.00 ] +Key: RMPADJUST: [ 0.00 0.00 ] +Key: RMPQUERY: [ 0.00 0.00 ] +Key: RMPUPDATE: [ 0.00 0.00 ] +Key: ROL: [ 0.00 0.00 ] +Key: ROR: [ 0.00 0.00 ] +Key: RORX: [ 0.00 0.00 ] +Key: ROUNDPDmi: [ 0.00 0.00 ] +Key: ROUNDPDri: [ 0.00 0.00 ] +Key: ROUNDPSmi: [ 0.00 0.00 ] +Key: ROUNDPSri: [ 0.00 0.00 ] +Key: ROUNDSDmi: [ 0.00 0.00 ] +Key: ROUNDSDmi_Int: [ 0.00 0.00 ] +Key: ROUNDSDri: [ 0.00 0.00 ] +Key: ROUNDSDri_Int: [ 0.00 0.00 ] +Key: ROUNDSSmi: [ 0.00 0.00 ] +Key: ROUNDSSmi_Int: [ 0.00 0.00 ] +Key: ROUNDSSri: [ 0.00 0.00 ] +Key: ROUNDSSri_Int: [ 0.00 0.00 ] +Key: RSM: [ 0.00 0.00 ] +Key: RSQRTPSm: [ 0.00 0.00 ] +Key: RSQRTPSr: [ 0.00 0.00 ] +Key: RSQRTSSm: [ 0.00 0.00 ] +Key: RSQRTSSm_Int: [ 0.00 0.00 ] +Key: RSQRTSSr: [ 0.00 0.00 ] +Key: RSQRTSSr_Int: [ 0.00 0.00 ] +Key: RSTORSSP: [ 0.00 0.00 ] +Key: SAHF: [ 0.00 0.00 ] +Key: SALC: [ 0.00 0.00 ] +Key: SAR: [ 0.00 0.00 ] +Key: SARX: [ 0.00 0.00 ] +Key: SAVEPREVSSP: [ 0.00 0.00 ] +Key: SBB: [ 0.00 0.00 ] +Key: SCASB: [ 0.00 0.00 ] +Key: SCASL: [ 0.00 0.00 ] +Key: SCASQ: [ 0.00 0.00 ] +Key: SCASW: [ 0.00 0.00 ] +Key: SEAMCALL: [ 0.00 0.00 ] +Key: SEAMOPS: [ 0.00 0.00 ] +Key: SEAMRET: [ 0.00 0.00 ] +Key: SEG_ALLOCA: [ 0.00 0.00 ] +Key: SEH_BeginEpilogue: [ 0.00 0.00 ] +Key: SEH_EndEpilogue: [ 0.00 0.00 ] +Key: SEH_EndPrologue: [ 0.00 0.00 ] +Key: SEH_PushFrame: [ 0.00 0.00 ] +Key: SEH_PushReg: [ 0.00 0.00 ] +Key: SEH_SaveReg: [ 0.00 0.00 ] +Key: SEH_SaveXMM: [ 0.00 0.00 ] +Key: SEH_SetFrame: [ 0.00 0.00 ] +Key: SEH_StackAlign: [ 0.00 0.00 ] +Key: SEH_StackAlloc: [ 0.00 0.00 ] +Key: SEH_UnwindV: [ 0.00 0.00 ] +Key: SEH_UnwindVersion: [ 0.00 0.00 ] +Key: SENDUIPI: [ 0.00 0.00 ] +Key: SERIALIZE: [ 0.00 0.00 ] +Key: SETB_C: [ 0.00 0.00 ] +Key: SETCCm: [ 0.00 0.00 ] +Key: SETCCm_EVEX: [ 0.00 0.00 ] +Key: SETCCr: [ 0.00 0.00 ] +Key: SETCCr_EVEX: [ 0.00 0.00 ] +Key: SETSSBSY: [ 0.00 0.00 ] +Key: SETZUCCm: [ 0.00 0.00 ] +Key: SETZUCCr: [ 0.00 0.00 ] +Key: SFENCE: [ 0.00 0.00 ] +Key: SGDT: [ 0.00 0.00 ] +Key: SHA: [ 0.00 0.00 ] +Key: SHL: [ 0.00 0.00 ] +Key: SHLD: [ 0.00 0.00 ] +Key: SHLDROT: [ 0.00 0.00 ] +Key: SHLX: [ 0.00 0.00 ] +Key: SHR: [ 0.00 0.00 ] +Key: SHRD: [ 0.00 0.00 ] +Key: SHRDROT: [ 0.00 0.00 ] +Key: SHRX: [ 0.00 0.00 ] +Key: SHUFPDrmi: [ 0.00 0.00 ] +Key: SHUFPDrri: [ 0.00 0.00 ] +Key: SHUFPSrmi: [ 0.00 0.00 ] +Key: SHUFPSrri: [ 0.00 0.00 ] +Key: SIDT: [ 0.00 0.00 ] +Key: SKINIT: [ 0.00 0.00 ] +Key: SLDT: [ 0.00 0.00 ] +Key: SLWPCB: [ 0.00 0.00 ] +Key: SMSW: [ 0.00 0.00 ] +Key: SQRTPDm: [ 0.00 0.00 ] +Key: SQRTPDr: [ 0.00 0.00 ] +Key: SQRTPSm: [ 0.00 0.00 ] +Key: SQRTPSr: [ 0.00 0.00 ] +Key: SQRTSDm: [ 0.00 0.00 ] +Key: SQRTSDm_Int: [ 0.00 0.00 ] +Key: SQRTSDr: [ 0.00 0.00 ] +Key: SQRTSDr_Int: [ 0.00 0.00 ] +Key: SQRTSSm: [ 0.00 0.00 ] +Key: SQRTSSm_Int: [ 0.00 0.00 ] +Key: SQRTSSr: [ 0.00 0.00 ] +Key: SQRTSSr_Int: [ 0.00 0.00 ] +Key: SQRT_F: [ 0.00 0.00 ] +Key: SQRT_Fp: [ 0.00 0.00 ] +Key: SS_PREFIX: [ 0.00 0.00 ] +Key: STAC: [ 0.00 0.00 ] +Key: STACKALLOC_W_PROBING: [ 0.00 0.00 ] +Key: STACKMAP: [ 0.00 0.00 ] +Key: STATEPOINT: [ 0.00 0.00 ] +Key: STC: [ 0.00 0.00 ] +Key: STD: [ 0.00 0.00 ] +Key: STGI: [ 0.00 0.00 ] +Key: STI: [ 0.00 0.00 ] +Key: STMXCSR: [ 0.00 0.00 ] +Key: STOSB: [ 0.00 0.00 ] +Key: STOSL: [ 0.00 0.00 ] +Key: STOSQ: [ 0.00 0.00 ] +Key: STOSW: [ 0.00 0.00 ] +Key: STR: [ 0.00 0.00 ] +Key: STRm: [ 0.00 0.00 ] +Key: STTILECFG: [ 0.00 0.00 ] +Key: STTILECFG_EVEX: [ 0.00 0.00 ] +Key: STUI: [ 0.00 0.00 ] +Key: ST_F: [ 0.00 0.00 ] +Key: ST_FP: [ 0.00 0.00 ] +Key: ST_FPrr: [ 0.00 0.00 ] +Key: ST_Fp: [ 0.00 0.00 ] +Key: ST_FpP: [ 0.00 0.00 ] +Key: ST_Frr: [ 0.00 0.00 ] +Key: SUB: [ 0.00 0.00 ] +Key: SUBPDrm: [ 0.00 0.00 ] +Key: SUBPDrr: [ 0.00 0.00 ] +Key: SUBPSrm: [ 0.00 0.00 ] +Key: SUBPSrr: [ 0.00 0.00 ] +Key: SUBREG_TO_REG: [ 0.00 0.00 ] +Key: SUBR_F: [ 0.00 0.00 ] +Key: SUBR_FI: [ 0.00 0.00 ] +Key: SUBR_FPrST: [ 0.00 0.00 ] +Key: SUBR_FST: [ 0.00 0.00 ] +Key: SUBR_Fp: [ 0.00 0.00 ] +Key: SUBR_FpI: [ 0.00 0.00 ] +Key: SUBR_FrST: [ 0.00 0.00 ] +Key: SUBSDrm: [ 0.00 0.00 ] +Key: SUBSDrm_Int: [ 0.00 0.00 ] +Key: SUBSDrr: [ 0.00 0.00 ] +Key: SUBSDrr_Int: [ 0.00 0.00 ] +Key: SUBSSrm: [ 0.00 0.00 ] +Key: SUBSSrm_Int: [ 0.00 0.00 ] +Key: SUBSSrr: [ 0.00 0.00 ] +Key: SUBSSrr_Int: [ 0.00 0.00 ] +Key: SUB_F: [ 0.00 0.00 ] +Key: SUB_FI: [ 0.00 0.00 ] +Key: SUB_FPrST: [ 0.00 0.00 ] +Key: SUB_FST: [ 0.00 0.00 ] +Key: SUB_Fp: [ 0.00 0.00 ] +Key: SUB_FpI: [ 0.00 0.00 ] +Key: SUB_FrST: [ 0.00 0.00 ] +Key: SWAPGS: [ 0.00 0.00 ] +Key: SYSCALL: [ 0.00 0.00 ] +Key: SYSENTER: [ 0.00 0.00 ] +Key: SYSEXIT: [ 0.00 0.00 ] +Key: SYSRET: [ 0.00 0.00 ] +Key: T: [ 0.00 0.00 ] +Key: TAILJMPd: [ 0.00 0.00 ] +Key: TAILJMPd_CC: [ 0.00 0.00 ] +Key: TAILJMPm: [ 0.00 0.00 ] +Key: TAILJMPr: [ 0.00 0.00 ] +Key: TCMMIMFP: [ 0.00 0.00 ] +Key: TCMMRLFP: [ 0.00 0.00 ] +Key: TCONJTCMMIMFP: [ 0.00 0.00 ] +Key: TCONJTFP: [ 0.00 0.00 ] +Key: TCRETURN_HIPE: [ 0.00 0.00 ] +Key: TCRETURN_WIN: [ 0.00 0.00 ] +Key: TCRETURN_WINmi: [ 0.00 0.00 ] +Key: TCRETURNdi: [ 0.00 0.00 ] +Key: TCRETURNdicc: [ 0.00 0.00 ] +Key: TCRETURNmi: [ 0.00 0.00 ] +Key: TCRETURNri: [ 0.00 0.00 ] +Key: TCVTROWD: [ 0.00 0.00 ] +Key: TCVTROWPS: [ 0.00 0.00 ] +Key: TDCALL: [ 0.00 0.00 ] +Key: TDPBF: [ 0.00 0.00 ] +Key: TDPBHF: [ 0.00 0.00 ] +Key: TDPBSSD: [ 0.00 0.00 ] +Key: TDPBSUD: [ 0.00 0.00 ] +Key: TDPBUSD: [ 0.00 0.00 ] +Key: TDPBUUD: [ 0.00 0.00 ] +Key: TDPFP: [ 0.00 0.00 ] +Key: TDPHBF: [ 0.00 0.00 ] +Key: TDPHF: [ 0.00 0.00 ] +Key: TEST: [ 0.00 0.00 ] +Key: TESTUI: [ 0.00 0.00 ] +Key: TILELOADD: [ 0.00 0.00 ] +Key: TILELOADDRS: [ 0.00 0.00 ] +Key: TILELOADDRST: [ 0.00 0.00 ] +Key: TILELOADDRS_EVEX: [ 0.00 0.00 ] +Key: TILELOADDT: [ 0.00 0.00 ] +Key: TILELOADD_EVEX: [ 0.00 0.00 ] +Key: TILEMOVROWrre: [ 0.00 0.00 ] +Key: TILEMOVROWrri: [ 0.00 0.00 ] +Key: TILERELEASE: [ 0.00 0.00 ] +Key: TILESTORED: [ 0.00 0.00 ] +Key: TILESTORED_EVEX: [ 0.00 0.00 ] +Key: TILEZERO: [ 0.00 0.00 ] +Key: TLBSYNC: [ 0.00 0.00 ] +Key: TLSCall: [ 0.00 0.00 ] +Key: TLS_addr: [ 0.00 0.00 ] +Key: TLS_addrX: [ 0.00 0.00 ] +Key: TLS_base_addr: [ 0.00 0.00 ] +Key: TLS_base_addrX: [ 0.00 0.00 ] +Key: TLS_desc: [ 0.00 0.00 ] +Key: TMMULTF: [ 0.00 0.00 ] +Key: TPAUSE: [ 0.00 0.00 ] +Key: TRAP: [ 0.00 0.00 ] +Key: TST_F: [ 0.00 0.00 ] +Key: TST_Fp: [ 0.00 0.00 ] +Key: TTCMMIMFP: [ 0.00 0.00 ] +Key: TTCMMRLFP: [ 0.00 0.00 ] +Key: TTDPBF: [ 0.00 0.00 ] +Key: TTDPFP: [ 0.00 0.00 ] +Key: TTMMULTF: [ 0.00 0.00 ] +Key: TTRANSPOSED: [ 0.00 0.00 ] +Key: TZCNT: [ 0.00 0.00 ] +Key: TZMSK: [ 0.00 0.00 ] +Key: UBSAN_UD: [ 0.00 0.00 ] +Key: UCOMISDrm: [ 0.00 0.00 ] +Key: UCOMISDrm_Int: [ 0.00 0.00 ] +Key: UCOMISDrr: [ 0.00 0.00 ] +Key: UCOMISDrr_Int: [ 0.00 0.00 ] +Key: UCOMISSrm: [ 0.00 0.00 ] +Key: UCOMISSrm_Int: [ 0.00 0.00 ] +Key: UCOMISSrr: [ 0.00 0.00 ] +Key: UCOMISSrr_Int: [ 0.00 0.00 ] +Key: UCOM_FIPr: [ 0.00 0.00 ] +Key: UCOM_FIr: [ 0.00 0.00 ] +Key: UCOM_FPPr: [ 0.00 0.00 ] +Key: UCOM_FPr: [ 0.00 0.00 ] +Key: UCOM_FpIr: [ 0.00 0.00 ] +Key: UCOM_Fpr: [ 0.00 0.00 ] +Key: UCOM_Fr: [ 0.00 0.00 ] +Key: UD: [ 0.00 0.00 ] +Key: UIRET: [ 0.00 0.00 ] +Key: UMONITOR: [ 0.00 0.00 ] +Key: UMWAIT: [ 0.00 0.00 ] +Key: UNPCKHPDrm: [ 0.00 0.00 ] +Key: UNPCKHPDrr: [ 0.00 0.00 ] +Key: UNPCKHPSrm: [ 0.00 0.00 ] +Key: UNPCKHPSrr: [ 0.00 0.00 ] +Key: UNPCKLPDrm: [ 0.00 0.00 ] +Key: UNPCKLPDrr: [ 0.00 0.00 ] +Key: UNPCKLPSrm: [ 0.00 0.00 ] +Key: UNPCKLPSrr: [ 0.00 0.00 ] +Key: URDMSRri: [ 0.00 0.00 ] +Key: URDMSRri_EVEX: [ 0.00 0.00 ] +Key: URDMSRrr: [ 0.00 0.00 ] +Key: URDMSRrr_EVEX: [ 0.00 0.00 ] +Key: UWRMSRir: [ 0.00 0.00 ] +Key: UWRMSRir_EVEX: [ 0.00 0.00 ] +Key: UWRMSRrr: [ 0.00 0.00 ] +Key: UWRMSRrr_EVEX: [ 0.00 0.00 ] +Key: V: [ 0.00 0.00 ] +Key: VAARG: [ 0.00 0.00 ] +Key: VAARG_X: [ 0.00 0.00 ] +Key: VADDBF: [ 0.00 0.00 ] +Key: VADDPDYrm: [ 0.00 0.00 ] +Key: VADDPDYrr: [ 0.00 0.00 ] +Key: VADDPDZ: [ 0.00 0.00 ] +Key: VADDPDZrm: [ 0.00 0.00 ] +Key: VADDPDZrmb: [ 0.00 0.00 ] +Key: VADDPDZrmbk: [ 0.00 0.00 ] +Key: VADDPDZrmbkz: [ 0.00 0.00 ] +Key: VADDPDZrmk: [ 0.00 0.00 ] +Key: VADDPDZrmkz: [ 0.00 0.00 ] +Key: VADDPDZrr: [ 0.00 0.00 ] +Key: VADDPDZrrb: [ 0.00 0.00 ] +Key: VADDPDZrrbk: [ 0.00 0.00 ] +Key: VADDPDZrrbkz: [ 0.00 0.00 ] +Key: VADDPDZrrk: [ 0.00 0.00 ] +Key: VADDPDZrrkz: [ 0.00 0.00 ] +Key: VADDPDrm: [ 0.00 0.00 ] +Key: VADDPDrr: [ 0.00 0.00 ] +Key: VADDPHZ: [ 0.00 0.00 ] +Key: VADDPHZrm: [ 0.00 0.00 ] +Key: VADDPHZrmb: [ 0.00 0.00 ] +Key: VADDPHZrmbk: [ 0.00 0.00 ] +Key: VADDPHZrmbkz: [ 0.00 0.00 ] +Key: VADDPHZrmk: [ 0.00 0.00 ] +Key: VADDPHZrmkz: [ 0.00 0.00 ] +Key: VADDPHZrr: [ 0.00 0.00 ] +Key: VADDPHZrrb: [ 0.00 0.00 ] +Key: VADDPHZrrbk: [ 0.00 0.00 ] +Key: VADDPHZrrbkz: [ 0.00 0.00 ] +Key: VADDPHZrrk: [ 0.00 0.00 ] +Key: VADDPHZrrkz: [ 0.00 0.00 ] +Key: VADDPSYrm: [ 0.00 0.00 ] +Key: VADDPSYrr: [ 0.00 0.00 ] +Key: VADDPSZ: [ 0.00 0.00 ] +Key: VADDPSZrm: [ 0.00 0.00 ] +Key: VADDPSZrmb: [ 0.00 0.00 ] +Key: VADDPSZrmbk: [ 0.00 0.00 ] +Key: VADDPSZrmbkz: [ 0.00 0.00 ] +Key: VADDPSZrmk: [ 0.00 0.00 ] +Key: VADDPSZrmkz: [ 0.00 0.00 ] +Key: VADDPSZrr: [ 0.00 0.00 ] +Key: VADDPSZrrb: [ 0.00 0.00 ] +Key: VADDPSZrrbk: [ 0.00 0.00 ] +Key: VADDPSZrrbkz: [ 0.00 0.00 ] +Key: VADDPSZrrk: [ 0.00 0.00 ] +Key: VADDPSZrrkz: [ 0.00 0.00 ] +Key: VADDPSrm: [ 0.00 0.00 ] +Key: VADDPSrr: [ 0.00 0.00 ] +Key: VADDSDZrm: [ 0.00 0.00 ] +Key: VADDSDZrm_Int: [ 0.00 0.00 ] +Key: VADDSDZrmk_Int: [ 0.00 0.00 ] +Key: VADDSDZrmkz_Int: [ 0.00 0.00 ] +Key: VADDSDZrr: [ 0.00 0.00 ] +Key: VADDSDZrr_Int: [ 0.00 0.00 ] +Key: VADDSDZrrb_Int: [ 0.00 0.00 ] +Key: VADDSDZrrbk_Int: [ 0.00 0.00 ] +Key: VADDSDZrrbkz_Int: [ 0.00 0.00 ] +Key: VADDSDZrrk_Int: [ 0.00 0.00 ] +Key: VADDSDZrrkz_Int: [ 0.00 0.00 ] +Key: VADDSDrm: [ 0.00 0.00 ] +Key: VADDSDrm_Int: [ 0.00 0.00 ] +Key: VADDSDrr: [ 0.00 0.00 ] +Key: VADDSDrr_Int: [ 0.00 0.00 ] +Key: VADDSHZrm: [ 0.00 0.00 ] +Key: VADDSHZrm_Int: [ 0.00 0.00 ] +Key: VADDSHZrmk_Int: [ 0.00 0.00 ] +Key: VADDSHZrmkz_Int: [ 0.00 0.00 ] +Key: VADDSHZrr: [ 0.00 0.00 ] +Key: VADDSHZrr_Int: [ 0.00 0.00 ] +Key: VADDSHZrrb_Int: [ 0.00 0.00 ] +Key: VADDSHZrrbk_Int: [ 0.00 0.00 ] +Key: VADDSHZrrbkz_Int: [ 0.00 0.00 ] +Key: VADDSHZrrk_Int: [ 0.00 0.00 ] +Key: VADDSHZrrkz_Int: [ 0.00 0.00 ] +Key: VADDSSZrm: [ 0.00 0.00 ] +Key: VADDSSZrm_Int: [ 0.00 0.00 ] +Key: VADDSSZrmk_Int: [ 0.00 0.00 ] +Key: VADDSSZrmkz_Int: [ 0.00 0.00 ] +Key: VADDSSZrr: [ 0.00 0.00 ] +Key: VADDSSZrr_Int: [ 0.00 0.00 ] +Key: VADDSSZrrb_Int: [ 0.00 0.00 ] +Key: VADDSSZrrbk_Int: [ 0.00 0.00 ] +Key: VADDSSZrrbkz_Int: [ 0.00 0.00 ] +Key: VADDSSZrrk_Int: [ 0.00 0.00 ] +Key: VADDSSZrrkz_Int: [ 0.00 0.00 ] +Key: VADDSSrm: [ 0.00 0.00 ] +Key: VADDSSrm_Int: [ 0.00 0.00 ] +Key: VADDSSrr: [ 0.00 0.00 ] +Key: VADDSSrr_Int: [ 0.00 0.00 ] +Key: VADDSUBPDYrm: [ 0.00 0.00 ] +Key: VADDSUBPDYrr: [ 0.00 0.00 ] +Key: VADDSUBPDrm: [ 0.00 0.00 ] +Key: VADDSUBPDrr: [ 0.00 0.00 ] +Key: VADDSUBPSYrm: [ 0.00 0.00 ] +Key: VADDSUBPSYrr: [ 0.00 0.00 ] +Key: VADDSUBPSrm: [ 0.00 0.00 ] +Key: VADDSUBPSrr: [ 0.00 0.00 ] +Key: VAESDECLASTYrm: [ 0.00 0.00 ] +Key: VAESDECLASTYrr: [ 0.00 0.00 ] +Key: VAESDECLASTZ: [ 0.00 0.00 ] +Key: VAESDECLASTZrm: [ 0.00 0.00 ] +Key: VAESDECLASTZrr: [ 0.00 0.00 ] +Key: VAESDECLASTrm: [ 0.00 0.00 ] +Key: VAESDECLASTrr: [ 0.00 0.00 ] +Key: VAESDECYrm: [ 0.00 0.00 ] +Key: VAESDECYrr: [ 0.00 0.00 ] +Key: VAESDECZ: [ 0.00 0.00 ] +Key: VAESDECZrm: [ 0.00 0.00 ] +Key: VAESDECZrr: [ 0.00 0.00 ] +Key: VAESDECrm: [ 0.00 0.00 ] +Key: VAESDECrr: [ 0.00 0.00 ] +Key: VAESENCLASTYrm: [ 0.00 0.00 ] +Key: VAESENCLASTYrr: [ 0.00 0.00 ] +Key: VAESENCLASTZ: [ 0.00 0.00 ] +Key: VAESENCLASTZrm: [ 0.00 0.00 ] +Key: VAESENCLASTZrr: [ 0.00 0.00 ] +Key: VAESENCLASTrm: [ 0.00 0.00 ] +Key: VAESENCLASTrr: [ 0.00 0.00 ] +Key: VAESENCYrm: [ 0.00 0.00 ] +Key: VAESENCYrr: [ 0.00 0.00 ] +Key: VAESENCZ: [ 0.00 0.00 ] +Key: VAESENCZrm: [ 0.00 0.00 ] +Key: VAESENCZrr: [ 0.00 0.00 ] +Key: VAESENCrm: [ 0.00 0.00 ] +Key: VAESENCrr: [ 0.00 0.00 ] +Key: VAESIMCrm: [ 0.00 0.00 ] +Key: VAESIMCrr: [ 0.00 0.00 ] +Key: VAESKEYGENASSISTrmi: [ 0.00 0.00 ] +Key: VAESKEYGENASSISTrri: [ 0.00 0.00 ] +Key: VALIGNDZ: [ 0.00 0.00 ] +Key: VALIGNDZrmbi: [ 0.00 0.00 ] +Key: VALIGNDZrmbik: [ 0.00 0.00 ] +Key: VALIGNDZrmbikz: [ 0.00 0.00 ] +Key: VALIGNDZrmi: [ 0.00 0.00 ] +Key: VALIGNDZrmik: [ 0.00 0.00 ] +Key: VALIGNDZrmikz: [ 0.00 0.00 ] +Key: VALIGNDZrri: [ 0.00 0.00 ] +Key: VALIGNDZrrik: [ 0.00 0.00 ] +Key: VALIGNDZrrikz: [ 0.00 0.00 ] +Key: VALIGNQZ: [ 0.00 0.00 ] +Key: VALIGNQZrmbi: [ 0.00 0.00 ] +Key: VALIGNQZrmbik: [ 0.00 0.00 ] +Key: VALIGNQZrmbikz: [ 0.00 0.00 ] +Key: VALIGNQZrmi: [ 0.00 0.00 ] +Key: VALIGNQZrmik: [ 0.00 0.00 ] +Key: VALIGNQZrmikz: [ 0.00 0.00 ] +Key: VALIGNQZrri: [ 0.00 0.00 ] +Key: VALIGNQZrrik: [ 0.00 0.00 ] +Key: VALIGNQZrrikz: [ 0.00 0.00 ] +Key: VANDNPDYrm: [ 0.00 0.00 ] +Key: VANDNPDYrr: [ 0.00 0.00 ] +Key: VANDNPDZ: [ 0.00 0.00 ] +Key: VANDNPDZrm: [ 0.00 0.00 ] +Key: VANDNPDZrmb: [ 0.00 0.00 ] +Key: VANDNPDZrmbk: [ 0.00 0.00 ] +Key: VANDNPDZrmbkz: [ 0.00 0.00 ] +Key: VANDNPDZrmk: [ 0.00 0.00 ] +Key: VANDNPDZrmkz: [ 0.00 0.00 ] +Key: VANDNPDZrr: [ 0.00 0.00 ] +Key: VANDNPDZrrk: [ 0.00 0.00 ] +Key: VANDNPDZrrkz: [ 0.00 0.00 ] +Key: VANDNPDrm: [ 0.00 0.00 ] +Key: VANDNPDrr: [ 0.00 0.00 ] +Key: VANDNPSYrm: [ 0.00 0.00 ] +Key: VANDNPSYrr: [ 0.00 0.00 ] +Key: VANDNPSZ: [ 0.00 0.00 ] +Key: VANDNPSZrm: [ 0.00 0.00 ] +Key: VANDNPSZrmb: [ 0.00 0.00 ] +Key: VANDNPSZrmbk: [ 0.00 0.00 ] +Key: VANDNPSZrmbkz: [ 0.00 0.00 ] +Key: VANDNPSZrmk: [ 0.00 0.00 ] +Key: VANDNPSZrmkz: [ 0.00 0.00 ] +Key: VANDNPSZrr: [ 0.00 0.00 ] +Key: VANDNPSZrrk: [ 0.00 0.00 ] +Key: VANDNPSZrrkz: [ 0.00 0.00 ] +Key: VANDNPSrm: [ 0.00 0.00 ] +Key: VANDNPSrr: [ 0.00 0.00 ] +Key: VANDPDYrm: [ 0.00 0.00 ] +Key: VANDPDYrr: [ 0.00 0.00 ] +Key: VANDPDZ: [ 0.00 0.00 ] +Key: VANDPDZrm: [ 0.00 0.00 ] +Key: VANDPDZrmb: [ 0.00 0.00 ] +Key: VANDPDZrmbk: [ 0.00 0.00 ] +Key: VANDPDZrmbkz: [ 0.00 0.00 ] +Key: VANDPDZrmk: [ 0.00 0.00 ] +Key: VANDPDZrmkz: [ 0.00 0.00 ] +Key: VANDPDZrr: [ 0.00 0.00 ] +Key: VANDPDZrrk: [ 0.00 0.00 ] +Key: VANDPDZrrkz: [ 0.00 0.00 ] +Key: VANDPDrm: [ 0.00 0.00 ] +Key: VANDPDrr: [ 0.00 0.00 ] +Key: VANDPSYrm: [ 0.00 0.00 ] +Key: VANDPSYrr: [ 0.00 0.00 ] +Key: VANDPSZ: [ 0.00 0.00 ] +Key: VANDPSZrm: [ 0.00 0.00 ] +Key: VANDPSZrmb: [ 0.00 0.00 ] +Key: VANDPSZrmbk: [ 0.00 0.00 ] +Key: VANDPSZrmbkz: [ 0.00 0.00 ] +Key: VANDPSZrmk: [ 0.00 0.00 ] +Key: VANDPSZrmkz: [ 0.00 0.00 ] +Key: VANDPSZrr: [ 0.00 0.00 ] +Key: VANDPSZrrk: [ 0.00 0.00 ] +Key: VANDPSZrrkz: [ 0.00 0.00 ] +Key: VANDPSrm: [ 0.00 0.00 ] +Key: VANDPSrr: [ 0.00 0.00 ] +Key: VASTART_SAVE_XMM_REGS: [ 0.00 0.00 ] +Key: VBCSTNEBF: [ 0.00 0.00 ] +Key: VBCSTNESH: [ 0.00 0.00 ] +Key: VBLENDMPDZ: [ 0.00 0.00 ] +Key: VBLENDMPDZrm: [ 0.00 0.00 ] +Key: VBLENDMPDZrmb: [ 0.00 0.00 ] +Key: VBLENDMPDZrmbk: [ 0.00 0.00 ] +Key: VBLENDMPDZrmbkz: [ 0.00 0.00 ] +Key: VBLENDMPDZrmk: [ 0.00 0.00 ] +Key: VBLENDMPDZrmkz: [ 0.00 0.00 ] +Key: VBLENDMPDZrr: [ 0.00 0.00 ] +Key: VBLENDMPDZrrk: [ 0.00 0.00 ] +Key: VBLENDMPDZrrkz: [ 0.00 0.00 ] +Key: VBLENDMPSZ: [ 0.00 0.00 ] +Key: VBLENDMPSZrm: [ 0.00 0.00 ] +Key: VBLENDMPSZrmb: [ 0.00 0.00 ] +Key: VBLENDMPSZrmbk: [ 0.00 0.00 ] +Key: VBLENDMPSZrmbkz: [ 0.00 0.00 ] +Key: VBLENDMPSZrmk: [ 0.00 0.00 ] +Key: VBLENDMPSZrmkz: [ 0.00 0.00 ] +Key: VBLENDMPSZrr: [ 0.00 0.00 ] +Key: VBLENDMPSZrrk: [ 0.00 0.00 ] +Key: VBLENDMPSZrrkz: [ 0.00 0.00 ] +Key: VBLENDPDYrmi: [ 0.00 0.00 ] +Key: VBLENDPDYrri: [ 0.00 0.00 ] +Key: VBLENDPDrmi: [ 0.00 0.00 ] +Key: VBLENDPDrri: [ 0.00 0.00 ] +Key: VBLENDPSYrmi: [ 0.00 0.00 ] +Key: VBLENDPSYrri: [ 0.00 0.00 ] +Key: VBLENDPSrmi: [ 0.00 0.00 ] +Key: VBLENDPSrri: [ 0.00 0.00 ] +Key: VBLENDVPDYrmr: [ 0.00 0.00 ] +Key: VBLENDVPDYrrr: [ 0.00 0.00 ] +Key: VBLENDVPDrmr: [ 0.00 0.00 ] +Key: VBLENDVPDrrr: [ 0.00 0.00 ] +Key: VBLENDVPSYrmr: [ 0.00 0.00 ] +Key: VBLENDVPSYrrr: [ 0.00 0.00 ] +Key: VBLENDVPSrmr: [ 0.00 0.00 ] +Key: VBLENDVPSrrr: [ 0.00 0.00 ] +Key: VBROADCASTF: [ 0.00 0.00 ] +Key: VBROADCASTI: [ 0.00 0.00 ] +Key: VBROADCASTSDYrm: [ 0.00 0.00 ] +Key: VBROADCASTSDYrr: [ 0.00 0.00 ] +Key: VBROADCASTSDZ: [ 0.00 0.00 ] +Key: VBROADCASTSDZrm: [ 0.00 0.00 ] +Key: VBROADCASTSDZrmk: [ 0.00 0.00 ] +Key: VBROADCASTSDZrmkz: [ 0.00 0.00 ] +Key: VBROADCASTSDZrr: [ 0.00 0.00 ] +Key: VBROADCASTSDZrrk: [ 0.00 0.00 ] +Key: VBROADCASTSDZrrkz: [ 0.00 0.00 ] +Key: VBROADCASTSSYrm: [ 0.00 0.00 ] +Key: VBROADCASTSSYrr: [ 0.00 0.00 ] +Key: VBROADCASTSSZ: [ 0.00 0.00 ] +Key: VBROADCASTSSZrm: [ 0.00 0.00 ] +Key: VBROADCASTSSZrmk: [ 0.00 0.00 ] +Key: VBROADCASTSSZrmkz: [ 0.00 0.00 ] +Key: VBROADCASTSSZrr: [ 0.00 0.00 ] +Key: VBROADCASTSSZrrk: [ 0.00 0.00 ] +Key: VBROADCASTSSZrrkz: [ 0.00 0.00 ] +Key: VBROADCASTSSrm: [ 0.00 0.00 ] +Key: VBROADCASTSSrr: [ 0.00 0.00 ] +Key: VCMPBF: [ 0.00 0.00 ] +Key: VCMPPDYrmi: [ 0.00 0.00 ] +Key: VCMPPDYrri: [ 0.00 0.00 ] +Key: VCMPPDZ: [ 0.00 0.00 ] +Key: VCMPPDZrmbi: [ 0.00 0.00 ] +Key: VCMPPDZrmbik: [ 0.00 0.00 ] +Key: VCMPPDZrmi: [ 0.00 0.00 ] +Key: VCMPPDZrmik: [ 0.00 0.00 ] +Key: VCMPPDZrri: [ 0.00 0.00 ] +Key: VCMPPDZrrib: [ 0.00 0.00 ] +Key: VCMPPDZrribk: [ 0.00 0.00 ] +Key: VCMPPDZrrik: [ 0.00 0.00 ] +Key: VCMPPDrmi: [ 0.00 0.00 ] +Key: VCMPPDrri: [ 0.00 0.00 ] +Key: VCMPPHZ: [ 0.00 0.00 ] +Key: VCMPPHZrmbi: [ 0.00 0.00 ] +Key: VCMPPHZrmbik: [ 0.00 0.00 ] +Key: VCMPPHZrmi: [ 0.00 0.00 ] +Key: VCMPPHZrmik: [ 0.00 0.00 ] +Key: VCMPPHZrri: [ 0.00 0.00 ] +Key: VCMPPHZrrib: [ 0.00 0.00 ] +Key: VCMPPHZrribk: [ 0.00 0.00 ] +Key: VCMPPHZrrik: [ 0.00 0.00 ] +Key: VCMPPSYrmi: [ 0.00 0.00 ] +Key: VCMPPSYrri: [ 0.00 0.00 ] +Key: VCMPPSZ: [ 0.00 0.00 ] +Key: VCMPPSZrmbi: [ 0.00 0.00 ] +Key: VCMPPSZrmbik: [ 0.00 0.00 ] +Key: VCMPPSZrmi: [ 0.00 0.00 ] +Key: VCMPPSZrmik: [ 0.00 0.00 ] +Key: VCMPPSZrri: [ 0.00 0.00 ] +Key: VCMPPSZrrib: [ 0.00 0.00 ] +Key: VCMPPSZrribk: [ 0.00 0.00 ] +Key: VCMPPSZrrik: [ 0.00 0.00 ] +Key: VCMPPSrmi: [ 0.00 0.00 ] +Key: VCMPPSrri: [ 0.00 0.00 ] +Key: VCMPSDZrmi: [ 0.00 0.00 ] +Key: VCMPSDZrmi_Int: [ 0.00 0.00 ] +Key: VCMPSDZrmik_Int: [ 0.00 0.00 ] +Key: VCMPSDZrri: [ 0.00 0.00 ] +Key: VCMPSDZrri_Int: [ 0.00 0.00 ] +Key: VCMPSDZrrib_Int: [ 0.00 0.00 ] +Key: VCMPSDZrribk_Int: [ 0.00 0.00 ] +Key: VCMPSDZrrik_Int: [ 0.00 0.00 ] +Key: VCMPSDrmi: [ 0.00 0.00 ] +Key: VCMPSDrmi_Int: [ 0.00 0.00 ] +Key: VCMPSDrri: [ 0.00 0.00 ] +Key: VCMPSDrri_Int: [ 0.00 0.00 ] +Key: VCMPSHZrmi: [ 0.00 0.00 ] +Key: VCMPSHZrmi_Int: [ 0.00 0.00 ] +Key: VCMPSHZrmik_Int: [ 0.00 0.00 ] +Key: VCMPSHZrri: [ 0.00 0.00 ] +Key: VCMPSHZrri_Int: [ 0.00 0.00 ] +Key: VCMPSHZrrib_Int: [ 0.00 0.00 ] +Key: VCMPSHZrribk_Int: [ 0.00 0.00 ] +Key: VCMPSHZrrik_Int: [ 0.00 0.00 ] +Key: VCMPSSZrmi: [ 0.00 0.00 ] +Key: VCMPSSZrmi_Int: [ 0.00 0.00 ] +Key: VCMPSSZrmik_Int: [ 0.00 0.00 ] +Key: VCMPSSZrri: [ 0.00 0.00 ] +Key: VCMPSSZrri_Int: [ 0.00 0.00 ] +Key: VCMPSSZrrib_Int: [ 0.00 0.00 ] +Key: VCMPSSZrribk_Int: [ 0.00 0.00 ] +Key: VCMPSSZrrik_Int: [ 0.00 0.00 ] +Key: VCMPSSrmi: [ 0.00 0.00 ] +Key: VCMPSSrmi_Int: [ 0.00 0.00 ] +Key: VCMPSSrri: [ 0.00 0.00 ] +Key: VCMPSSrri_Int: [ 0.00 0.00 ] +Key: VCOMISBF: [ 0.00 0.00 ] +Key: VCOMISDZrm: [ 0.00 0.00 ] +Key: VCOMISDZrm_Int: [ 0.00 0.00 ] +Key: VCOMISDZrr: [ 0.00 0.00 ] +Key: VCOMISDZrr_Int: [ 0.00 0.00 ] +Key: VCOMISDZrrb: [ 0.00 0.00 ] +Key: VCOMISDrm: [ 0.00 0.00 ] +Key: VCOMISDrm_Int: [ 0.00 0.00 ] +Key: VCOMISDrr: [ 0.00 0.00 ] +Key: VCOMISDrr_Int: [ 0.00 0.00 ] +Key: VCOMISHZrm: [ 0.00 0.00 ] +Key: VCOMISHZrm_Int: [ 0.00 0.00 ] +Key: VCOMISHZrr: [ 0.00 0.00 ] +Key: VCOMISHZrr_Int: [ 0.00 0.00 ] +Key: VCOMISHZrrb: [ 0.00 0.00 ] +Key: VCOMISSZrm: [ 0.00 0.00 ] +Key: VCOMISSZrm_Int: [ 0.00 0.00 ] +Key: VCOMISSZrr: [ 0.00 0.00 ] +Key: VCOMISSZrr_Int: [ 0.00 0.00 ] +Key: VCOMISSZrrb: [ 0.00 0.00 ] +Key: VCOMISSrm: [ 0.00 0.00 ] +Key: VCOMISSrm_Int: [ 0.00 0.00 ] +Key: VCOMISSrr: [ 0.00 0.00 ] +Key: VCOMISSrr_Int: [ 0.00 0.00 ] +Key: VCOMPRESSPDZ: [ 0.00 0.00 ] +Key: VCOMPRESSPDZmr: [ 0.00 0.00 ] +Key: VCOMPRESSPDZmrk: [ 0.00 0.00 ] +Key: VCOMPRESSPDZrr: [ 0.00 0.00 ] +Key: VCOMPRESSPDZrrk: [ 0.00 0.00 ] +Key: VCOMPRESSPDZrrkz: [ 0.00 0.00 ] +Key: VCOMPRESSPSZ: [ 0.00 0.00 ] +Key: VCOMPRESSPSZmr: [ 0.00 0.00 ] +Key: VCOMPRESSPSZmrk: [ 0.00 0.00 ] +Key: VCOMPRESSPSZrr: [ 0.00 0.00 ] +Key: VCOMPRESSPSZrrk: [ 0.00 0.00 ] +Key: VCOMPRESSPSZrrkz: [ 0.00 0.00 ] +Key: VCOMXSDZrm_Int: [ 0.00 0.00 ] +Key: VCOMXSDZrr_Int: [ 0.00 0.00 ] +Key: VCOMXSDZrrb_Int: [ 0.00 0.00 ] +Key: VCOMXSHZrm_Int: [ 0.00 0.00 ] +Key: VCOMXSHZrr_Int: [ 0.00 0.00 ] +Key: VCOMXSHZrrb_Int: [ 0.00 0.00 ] +Key: VCOMXSSZrm_Int: [ 0.00 0.00 ] +Key: VCOMXSSZrr_Int: [ 0.00 0.00 ] +Key: VCOMXSSZrrb_Int: [ 0.00 0.00 ] +Key: VCVT: [ 0.00 0.00 ] +Key: VCVTBF: [ 0.00 0.00 ] +Key: VCVTBIASPH: [ 0.00 0.00 ] +Key: VCVTDQ: [ 0.00 0.00 ] +Key: VCVTHF: [ 0.00 0.00 ] +Key: VCVTNE: [ 0.00 0.00 ] +Key: VCVTNEEBF: [ 0.00 0.00 ] +Key: VCVTNEEPH: [ 0.00 0.00 ] +Key: VCVTNEOBF: [ 0.00 0.00 ] +Key: VCVTNEOPH: [ 0.00 0.00 ] +Key: VCVTNEPS: [ 0.00 0.00 ] +Key: VCVTPD: [ 0.00 0.00 ] +Key: VCVTPH: [ 0.00 0.00 ] +Key: VCVTPS: [ 0.00 0.00 ] +Key: VCVTQQ: [ 0.00 0.00 ] +Key: VCVTSD: [ 0.00 0.00 ] +Key: VCVTSH: [ 0.00 0.00 ] +Key: VCVTSI: [ 0.00 0.00 ] +Key: VCVTSS: [ 0.00 0.00 ] +Key: VCVTTBF: [ 0.00 0.00 ] +Key: VCVTTPD: [ 0.00 0.00 ] +Key: VCVTTPH: [ 0.00 0.00 ] +Key: VCVTTPS: [ 0.00 0.00 ] +Key: VCVTTSD: [ 0.00 0.00 ] +Key: VCVTTSH: [ 0.00 0.00 ] +Key: VCVTTSS: [ 0.00 0.00 ] +Key: VCVTUDQ: [ 0.00 0.00 ] +Key: VCVTUQQ: [ 0.00 0.00 ] +Key: VCVTUSI: [ 0.00 0.00 ] +Key: VCVTUW: [ 0.00 0.00 ] +Key: VCVTW: [ 0.00 0.00 ] +Key: VDBPSADBWZ: [ 0.00 0.00 ] +Key: VDBPSADBWZrmi: [ 0.00 0.00 ] +Key: VDBPSADBWZrmik: [ 0.00 0.00 ] +Key: VDBPSADBWZrmikz: [ 0.00 0.00 ] +Key: VDBPSADBWZrri: [ 0.00 0.00 ] +Key: VDBPSADBWZrrik: [ 0.00 0.00 ] +Key: VDBPSADBWZrrikz: [ 0.00 0.00 ] +Key: VDIVBF: [ 0.00 0.00 ] +Key: VDIVPDYrm: [ 0.00 0.00 ] +Key: VDIVPDYrr: [ 0.00 0.00 ] +Key: VDIVPDZ: [ 0.00 0.00 ] +Key: VDIVPDZrm: [ 0.00 0.00 ] +Key: VDIVPDZrmb: [ 0.00 0.00 ] +Key: VDIVPDZrmbk: [ 0.00 0.00 ] +Key: VDIVPDZrmbkz: [ 0.00 0.00 ] +Key: VDIVPDZrmk: [ 0.00 0.00 ] +Key: VDIVPDZrmkz: [ 0.00 0.00 ] +Key: VDIVPDZrr: [ 0.00 0.00 ] +Key: VDIVPDZrrb: [ 0.00 0.00 ] +Key: VDIVPDZrrbk: [ 0.00 0.00 ] +Key: VDIVPDZrrbkz: [ 0.00 0.00 ] +Key: VDIVPDZrrk: [ 0.00 0.00 ] +Key: VDIVPDZrrkz: [ 0.00 0.00 ] +Key: VDIVPDrm: [ 0.00 0.00 ] +Key: VDIVPDrr: [ 0.00 0.00 ] +Key: VDIVPHZ: [ 0.00 0.00 ] +Key: VDIVPHZrm: [ 0.00 0.00 ] +Key: VDIVPHZrmb: [ 0.00 0.00 ] +Key: VDIVPHZrmbk: [ 0.00 0.00 ] +Key: VDIVPHZrmbkz: [ 0.00 0.00 ] +Key: VDIVPHZrmk: [ 0.00 0.00 ] +Key: VDIVPHZrmkz: [ 0.00 0.00 ] +Key: VDIVPHZrr: [ 0.00 0.00 ] +Key: VDIVPHZrrb: [ 0.00 0.00 ] +Key: VDIVPHZrrbk: [ 0.00 0.00 ] +Key: VDIVPHZrrbkz: [ 0.00 0.00 ] +Key: VDIVPHZrrk: [ 0.00 0.00 ] +Key: VDIVPHZrrkz: [ 0.00 0.00 ] +Key: VDIVPSYrm: [ 0.00 0.00 ] +Key: VDIVPSYrr: [ 0.00 0.00 ] +Key: VDIVPSZ: [ 0.00 0.00 ] +Key: VDIVPSZrm: [ 0.00 0.00 ] +Key: VDIVPSZrmb: [ 0.00 0.00 ] +Key: VDIVPSZrmbk: [ 0.00 0.00 ] +Key: VDIVPSZrmbkz: [ 0.00 0.00 ] +Key: VDIVPSZrmk: [ 0.00 0.00 ] +Key: VDIVPSZrmkz: [ 0.00 0.00 ] +Key: VDIVPSZrr: [ 0.00 0.00 ] +Key: VDIVPSZrrb: [ 0.00 0.00 ] +Key: VDIVPSZrrbk: [ 0.00 0.00 ] +Key: VDIVPSZrrbkz: [ 0.00 0.00 ] +Key: VDIVPSZrrk: [ 0.00 0.00 ] +Key: VDIVPSZrrkz: [ 0.00 0.00 ] +Key: VDIVPSrm: [ 0.00 0.00 ] +Key: VDIVPSrr: [ 0.00 0.00 ] +Key: VDIVSDZrm: [ 0.00 0.00 ] +Key: VDIVSDZrm_Int: [ 0.00 0.00 ] +Key: VDIVSDZrmk_Int: [ 0.00 0.00 ] +Key: VDIVSDZrmkz_Int: [ 0.00 0.00 ] +Key: VDIVSDZrr: [ 0.00 0.00 ] +Key: VDIVSDZrr_Int: [ 0.00 0.00 ] +Key: VDIVSDZrrb_Int: [ 0.00 0.00 ] +Key: VDIVSDZrrbk_Int: [ 0.00 0.00 ] +Key: VDIVSDZrrbkz_Int: [ 0.00 0.00 ] +Key: VDIVSDZrrk_Int: [ 0.00 0.00 ] +Key: VDIVSDZrrkz_Int: [ 0.00 0.00 ] +Key: VDIVSDrm: [ 0.00 0.00 ] +Key: VDIVSDrm_Int: [ 0.00 0.00 ] +Key: VDIVSDrr: [ 0.00 0.00 ] +Key: VDIVSDrr_Int: [ 0.00 0.00 ] +Key: VDIVSHZrm: [ 0.00 0.00 ] +Key: VDIVSHZrm_Int: [ 0.00 0.00 ] +Key: VDIVSHZrmk_Int: [ 0.00 0.00 ] +Key: VDIVSHZrmkz_Int: [ 0.00 0.00 ] +Key: VDIVSHZrr: [ 0.00 0.00 ] +Key: VDIVSHZrr_Int: [ 0.00 0.00 ] +Key: VDIVSHZrrb_Int: [ 0.00 0.00 ] +Key: VDIVSHZrrbk_Int: [ 0.00 0.00 ] +Key: VDIVSHZrrbkz_Int: [ 0.00 0.00 ] +Key: VDIVSHZrrk_Int: [ 0.00 0.00 ] +Key: VDIVSHZrrkz_Int: [ 0.00 0.00 ] +Key: VDIVSSZrm: [ 0.00 0.00 ] +Key: VDIVSSZrm_Int: [ 0.00 0.00 ] +Key: VDIVSSZrmk_Int: [ 0.00 0.00 ] +Key: VDIVSSZrmkz_Int: [ 0.00 0.00 ] +Key: VDIVSSZrr: [ 0.00 0.00 ] +Key: VDIVSSZrr_Int: [ 0.00 0.00 ] +Key: VDIVSSZrrb_Int: [ 0.00 0.00 ] +Key: VDIVSSZrrbk_Int: [ 0.00 0.00 ] +Key: VDIVSSZrrbkz_Int: [ 0.00 0.00 ] +Key: VDIVSSZrrk_Int: [ 0.00 0.00 ] +Key: VDIVSSZrrkz_Int: [ 0.00 0.00 ] +Key: VDIVSSrm: [ 0.00 0.00 ] +Key: VDIVSSrm_Int: [ 0.00 0.00 ] +Key: VDIVSSrr: [ 0.00 0.00 ] +Key: VDIVSSrr_Int: [ 0.00 0.00 ] +Key: VDPBF: [ 0.00 0.00 ] +Key: VDPPDrmi: [ 0.00 0.00 ] +Key: VDPPDrri: [ 0.00 0.00 ] +Key: VDPPHPSZ: [ 0.00 0.00 ] +Key: VDPPHPSZm: [ 0.00 0.00 ] +Key: VDPPHPSZmb: [ 0.00 0.00 ] +Key: VDPPHPSZmbk: [ 0.00 0.00 ] +Key: VDPPHPSZmbkz: [ 0.00 0.00 ] +Key: VDPPHPSZmk: [ 0.00 0.00 ] +Key: VDPPHPSZmkz: [ 0.00 0.00 ] +Key: VDPPHPSZr: [ 0.00 0.00 ] +Key: VDPPHPSZrk: [ 0.00 0.00 ] +Key: VDPPHPSZrkz: [ 0.00 0.00 ] +Key: VDPPSYrmi: [ 0.00 0.00 ] +Key: VDPPSYrri: [ 0.00 0.00 ] +Key: VDPPSrmi: [ 0.00 0.00 ] +Key: VDPPSrri: [ 0.00 0.00 ] +Key: VERRm: [ 0.00 0.00 ] +Key: VERRr: [ 0.00 0.00 ] +Key: VERWm: [ 0.00 0.00 ] +Key: VERWr: [ 0.00 0.00 ] +Key: VEXP: [ 0.00 0.00 ] +Key: VEXPANDPDZ: [ 0.00 0.00 ] +Key: VEXPANDPDZrm: [ 0.00 0.00 ] +Key: VEXPANDPDZrmk: [ 0.00 0.00 ] +Key: VEXPANDPDZrmkz: [ 0.00 0.00 ] +Key: VEXPANDPDZrr: [ 0.00 0.00 ] +Key: VEXPANDPDZrrk: [ 0.00 0.00 ] +Key: VEXPANDPDZrrkz: [ 0.00 0.00 ] +Key: VEXPANDPSZ: [ 0.00 0.00 ] +Key: VEXPANDPSZrm: [ 0.00 0.00 ] +Key: VEXPANDPSZrmk: [ 0.00 0.00 ] +Key: VEXPANDPSZrmkz: [ 0.00 0.00 ] +Key: VEXPANDPSZrr: [ 0.00 0.00 ] +Key: VEXPANDPSZrrk: [ 0.00 0.00 ] +Key: VEXPANDPSZrrkz: [ 0.00 0.00 ] +Key: VEXTRACTF: [ 0.00 0.00 ] +Key: VEXTRACTI: [ 0.00 0.00 ] +Key: VEXTRACTPSZmri: [ 0.00 0.00 ] +Key: VEXTRACTPSZrri: [ 0.00 0.00 ] +Key: VEXTRACTPSmri: [ 0.00 0.00 ] +Key: VEXTRACTPSrri: [ 0.00 0.00 ] +Key: VFCMADDCPHZ: [ 0.00 0.00 ] +Key: VFCMADDCPHZm: [ 0.00 0.00 ] +Key: VFCMADDCPHZmb: [ 0.00 0.00 ] +Key: VFCMADDCPHZmbk: [ 0.00 0.00 ] +Key: VFCMADDCPHZmbkz: [ 0.00 0.00 ] +Key: VFCMADDCPHZmk: [ 0.00 0.00 ] +Key: VFCMADDCPHZmkz: [ 0.00 0.00 ] +Key: VFCMADDCPHZr: [ 0.00 0.00 ] +Key: VFCMADDCPHZrb: [ 0.00 0.00 ] +Key: VFCMADDCPHZrbk: [ 0.00 0.00 ] +Key: VFCMADDCPHZrbkz: [ 0.00 0.00 ] +Key: VFCMADDCPHZrk: [ 0.00 0.00 ] +Key: VFCMADDCPHZrkz: [ 0.00 0.00 ] +Key: VFCMADDCSHZm: [ 0.00 0.00 ] +Key: VFCMADDCSHZmk: [ 0.00 0.00 ] +Key: VFCMADDCSHZmkz: [ 0.00 0.00 ] +Key: VFCMADDCSHZr: [ 0.00 0.00 ] +Key: VFCMADDCSHZrb: [ 0.00 0.00 ] +Key: VFCMADDCSHZrbk: [ 0.00 0.00 ] +Key: VFCMADDCSHZrbkz: [ 0.00 0.00 ] +Key: VFCMADDCSHZrk: [ 0.00 0.00 ] +Key: VFCMADDCSHZrkz: [ 0.00 0.00 ] +Key: VFCMULCPHZ: [ 0.00 0.00 ] +Key: VFCMULCPHZrm: [ 0.00 0.00 ] +Key: VFCMULCPHZrmb: [ 0.00 0.00 ] +Key: VFCMULCPHZrmbk: [ 0.00 0.00 ] +Key: VFCMULCPHZrmbkz: [ 0.00 0.00 ] +Key: VFCMULCPHZrmk: [ 0.00 0.00 ] +Key: VFCMULCPHZrmkz: [ 0.00 0.00 ] +Key: VFCMULCPHZrr: [ 0.00 0.00 ] +Key: VFCMULCPHZrrb: [ 0.00 0.00 ] +Key: VFCMULCPHZrrbk: [ 0.00 0.00 ] +Key: VFCMULCPHZrrbkz: [ 0.00 0.00 ] +Key: VFCMULCPHZrrk: [ 0.00 0.00 ] +Key: VFCMULCPHZrrkz: [ 0.00 0.00 ] +Key: VFCMULCSHZrm: [ 0.00 0.00 ] +Key: VFCMULCSHZrmk: [ 0.00 0.00 ] +Key: VFCMULCSHZrmkz: [ 0.00 0.00 ] +Key: VFCMULCSHZrr: [ 0.00 0.00 ] +Key: VFCMULCSHZrrb: [ 0.00 0.00 ] +Key: VFCMULCSHZrrbk: [ 0.00 0.00 ] +Key: VFCMULCSHZrrbkz: [ 0.00 0.00 ] +Key: VFCMULCSHZrrk: [ 0.00 0.00 ] +Key: VFCMULCSHZrrkz: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZ: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmbi: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmbik: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmbikz: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmi: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmik: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrmikz: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrri: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrrib: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrribk: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrribkz: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrrik: [ 0.00 0.00 ] +Key: VFIXUPIMMPDZrrikz: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZ: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmbi: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmbik: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmbikz: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmi: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmik: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrmikz: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrri: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrrib: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrribk: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrribkz: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrrik: [ 0.00 0.00 ] +Key: VFIXUPIMMPSZrrikz: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrmi: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrmik: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrmikz: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrri: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrrib: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrribk: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrribkz: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrrik: [ 0.00 0.00 ] +Key: VFIXUPIMMSDZrrikz: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrmi: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrmik: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrmikz: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrri: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrrib: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrribk: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrribkz: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrrik: [ 0.00 0.00 ] +Key: VFIXUPIMMSSZrrikz: [ 0.00 0.00 ] +Key: VFMADD: [ 0.00 0.00 ] +Key: VFMADDCPHZ: [ 0.00 0.00 ] +Key: VFMADDCPHZm: [ 0.00 0.00 ] +Key: VFMADDCPHZmb: [ 0.00 0.00 ] +Key: VFMADDCPHZmbk: [ 0.00 0.00 ] +Key: VFMADDCPHZmbkz: [ 0.00 0.00 ] +Key: VFMADDCPHZmk: [ 0.00 0.00 ] +Key: VFMADDCPHZmkz: [ 0.00 0.00 ] +Key: VFMADDCPHZr: [ 0.00 0.00 ] +Key: VFMADDCPHZrb: [ 0.00 0.00 ] +Key: VFMADDCPHZrbk: [ 0.00 0.00 ] +Key: VFMADDCPHZrbkz: [ 0.00 0.00 ] +Key: VFMADDCPHZrk: [ 0.00 0.00 ] +Key: VFMADDCPHZrkz: [ 0.00 0.00 ] +Key: VFMADDCSHZm: [ 0.00 0.00 ] +Key: VFMADDCSHZmk: [ 0.00 0.00 ] +Key: VFMADDCSHZmkz: [ 0.00 0.00 ] +Key: VFMADDCSHZr: [ 0.00 0.00 ] +Key: VFMADDCSHZrb: [ 0.00 0.00 ] +Key: VFMADDCSHZrbk: [ 0.00 0.00 ] +Key: VFMADDCSHZrbkz: [ 0.00 0.00 ] +Key: VFMADDCSHZrk: [ 0.00 0.00 ] +Key: VFMADDCSHZrkz: [ 0.00 0.00 ] +Key: VFMADDPD: [ 0.00 0.00 ] +Key: VFMADDPS: [ 0.00 0.00 ] +Key: VFMADDSD: [ 0.00 0.00 ] +Key: VFMADDSS: [ 0.00 0.00 ] +Key: VFMADDSUB: [ 0.00 0.00 ] +Key: VFMADDSUBPD: [ 0.00 0.00 ] +Key: VFMADDSUBPS: [ 0.00 0.00 ] +Key: VFMSUB: [ 0.00 0.00 ] +Key: VFMSUBADD: [ 0.00 0.00 ] +Key: VFMSUBADDPD: [ 0.00 0.00 ] +Key: VFMSUBADDPS: [ 0.00 0.00 ] +Key: VFMSUBPD: [ 0.00 0.00 ] +Key: VFMSUBPS: [ 0.00 0.00 ] +Key: VFMSUBSD: [ 0.00 0.00 ] +Key: VFMSUBSS: [ 0.00 0.00 ] +Key: VFMULCPHZ: [ 0.00 0.00 ] +Key: VFMULCPHZrm: [ 0.00 0.00 ] +Key: VFMULCPHZrmb: [ 0.00 0.00 ] +Key: VFMULCPHZrmbk: [ 0.00 0.00 ] +Key: VFMULCPHZrmbkz: [ 0.00 0.00 ] +Key: VFMULCPHZrmk: [ 0.00 0.00 ] +Key: VFMULCPHZrmkz: [ 0.00 0.00 ] +Key: VFMULCPHZrr: [ 0.00 0.00 ] +Key: VFMULCPHZrrb: [ 0.00 0.00 ] +Key: VFMULCPHZrrbk: [ 0.00 0.00 ] +Key: VFMULCPHZrrbkz: [ 0.00 0.00 ] +Key: VFMULCPHZrrk: [ 0.00 0.00 ] +Key: VFMULCPHZrrkz: [ 0.00 0.00 ] +Key: VFMULCSHZrm: [ 0.00 0.00 ] +Key: VFMULCSHZrmk: [ 0.00 0.00 ] +Key: VFMULCSHZrmkz: [ 0.00 0.00 ] +Key: VFMULCSHZrr: [ 0.00 0.00 ] +Key: VFMULCSHZrrb: [ 0.00 0.00 ] +Key: VFMULCSHZrrbk: [ 0.00 0.00 ] +Key: VFMULCSHZrrbkz: [ 0.00 0.00 ] +Key: VFMULCSHZrrk: [ 0.00 0.00 ] +Key: VFMULCSHZrrkz: [ 0.00 0.00 ] +Key: VFNMADD: [ 0.00 0.00 ] +Key: VFNMADDPD: [ 0.00 0.00 ] +Key: VFNMADDPS: [ 0.00 0.00 ] +Key: VFNMADDSD: [ 0.00 0.00 ] +Key: VFNMADDSS: [ 0.00 0.00 ] +Key: VFNMSUB: [ 0.00 0.00 ] +Key: VFNMSUBPD: [ 0.00 0.00 ] +Key: VFNMSUBPS: [ 0.00 0.00 ] +Key: VFNMSUBSD: [ 0.00 0.00 ] +Key: VFNMSUBSS: [ 0.00 0.00 ] +Key: VFPCLASSBF: [ 0.00 0.00 ] +Key: VFPCLASSPDZ: [ 0.00 0.00 ] +Key: VFPCLASSPDZmbi: [ 0.00 0.00 ] +Key: VFPCLASSPDZmbik: [ 0.00 0.00 ] +Key: VFPCLASSPDZmi: [ 0.00 0.00 ] +Key: VFPCLASSPDZmik: [ 0.00 0.00 ] +Key: VFPCLASSPDZri: [ 0.00 0.00 ] +Key: VFPCLASSPDZrik: [ 0.00 0.00 ] +Key: VFPCLASSPHZ: [ 0.00 0.00 ] +Key: VFPCLASSPHZmbi: [ 0.00 0.00 ] +Key: VFPCLASSPHZmbik: [ 0.00 0.00 ] +Key: VFPCLASSPHZmi: [ 0.00 0.00 ] +Key: VFPCLASSPHZmik: [ 0.00 0.00 ] +Key: VFPCLASSPHZri: [ 0.00 0.00 ] +Key: VFPCLASSPHZrik: [ 0.00 0.00 ] +Key: VFPCLASSPSZ: [ 0.00 0.00 ] +Key: VFPCLASSPSZmbi: [ 0.00 0.00 ] +Key: VFPCLASSPSZmbik: [ 0.00 0.00 ] +Key: VFPCLASSPSZmi: [ 0.00 0.00 ] +Key: VFPCLASSPSZmik: [ 0.00 0.00 ] +Key: VFPCLASSPSZri: [ 0.00 0.00 ] +Key: VFPCLASSPSZrik: [ 0.00 0.00 ] +Key: VFPCLASSSDZmi: [ 0.00 0.00 ] +Key: VFPCLASSSDZmik: [ 0.00 0.00 ] +Key: VFPCLASSSDZri: [ 0.00 0.00 ] +Key: VFPCLASSSDZrik: [ 0.00 0.00 ] +Key: VFPCLASSSHZmi: [ 0.00 0.00 ] +Key: VFPCLASSSHZmik: [ 0.00 0.00 ] +Key: VFPCLASSSHZri: [ 0.00 0.00 ] +Key: VFPCLASSSHZrik: [ 0.00 0.00 ] +Key: VFPCLASSSSZmi: [ 0.00 0.00 ] +Key: VFPCLASSSSZmik: [ 0.00 0.00 ] +Key: VFPCLASSSSZri: [ 0.00 0.00 ] +Key: VFPCLASSSSZrik: [ 0.00 0.00 ] +Key: VFRCZPDYrm: [ 0.00 0.00 ] +Key: VFRCZPDYrr: [ 0.00 0.00 ] +Key: VFRCZPDrm: [ 0.00 0.00 ] +Key: VFRCZPDrr: [ 0.00 0.00 ] +Key: VFRCZPSYrm: [ 0.00 0.00 ] +Key: VFRCZPSYrr: [ 0.00 0.00 ] +Key: VFRCZPSrm: [ 0.00 0.00 ] +Key: VFRCZPSrr: [ 0.00 0.00 ] +Key: VFRCZSDrm: [ 0.00 0.00 ] +Key: VFRCZSDrr: [ 0.00 0.00 ] +Key: VFRCZSSrm: [ 0.00 0.00 ] +Key: VFRCZSSrr: [ 0.00 0.00 ] +Key: VGATHERDPDYrm: [ 0.00 0.00 ] +Key: VGATHERDPDZ: [ 0.00 0.00 ] +Key: VGATHERDPDZrm: [ 0.00 0.00 ] +Key: VGATHERDPDrm: [ 0.00 0.00 ] +Key: VGATHERDPSYrm: [ 0.00 0.00 ] +Key: VGATHERDPSZ: [ 0.00 0.00 ] +Key: VGATHERDPSZrm: [ 0.00 0.00 ] +Key: VGATHERDPSrm: [ 0.00 0.00 ] +Key: VGATHERPF: [ 0.00 0.00 ] +Key: VGATHERQPDYrm: [ 0.00 0.00 ] +Key: VGATHERQPDZ: [ 0.00 0.00 ] +Key: VGATHERQPDZrm: [ 0.00 0.00 ] +Key: VGATHERQPDrm: [ 0.00 0.00 ] +Key: VGATHERQPSYrm: [ 0.00 0.00 ] +Key: VGATHERQPSZ: [ 0.00 0.00 ] +Key: VGATHERQPSZrm: [ 0.00 0.00 ] +Key: VGATHERQPSrm: [ 0.00 0.00 ] +Key: VGETEXPBF: [ 0.00 0.00 ] +Key: VGETEXPPDZ: [ 0.00 0.00 ] +Key: VGETEXPPDZm: [ 0.00 0.00 ] +Key: VGETEXPPDZmb: [ 0.00 0.00 ] +Key: VGETEXPPDZmbk: [ 0.00 0.00 ] +Key: VGETEXPPDZmbkz: [ 0.00 0.00 ] +Key: VGETEXPPDZmk: [ 0.00 0.00 ] +Key: VGETEXPPDZmkz: [ 0.00 0.00 ] +Key: VGETEXPPDZr: [ 0.00 0.00 ] +Key: VGETEXPPDZrb: [ 0.00 0.00 ] +Key: VGETEXPPDZrbk: [ 0.00 0.00 ] +Key: VGETEXPPDZrbkz: [ 0.00 0.00 ] +Key: VGETEXPPDZrk: [ 0.00 0.00 ] +Key: VGETEXPPDZrkz: [ 0.00 0.00 ] +Key: VGETEXPPHZ: [ 0.00 0.00 ] +Key: VGETEXPPHZm: [ 0.00 0.00 ] +Key: VGETEXPPHZmb: [ 0.00 0.00 ] +Key: VGETEXPPHZmbk: [ 0.00 0.00 ] +Key: VGETEXPPHZmbkz: [ 0.00 0.00 ] +Key: VGETEXPPHZmk: [ 0.00 0.00 ] +Key: VGETEXPPHZmkz: [ 0.00 0.00 ] +Key: VGETEXPPHZr: [ 0.00 0.00 ] +Key: VGETEXPPHZrb: [ 0.00 0.00 ] +Key: VGETEXPPHZrbk: [ 0.00 0.00 ] +Key: VGETEXPPHZrbkz: [ 0.00 0.00 ] +Key: VGETEXPPHZrk: [ 0.00 0.00 ] +Key: VGETEXPPHZrkz: [ 0.00 0.00 ] +Key: VGETEXPPSZ: [ 0.00 0.00 ] +Key: VGETEXPPSZm: [ 0.00 0.00 ] +Key: VGETEXPPSZmb: [ 0.00 0.00 ] +Key: VGETEXPPSZmbk: [ 0.00 0.00 ] +Key: VGETEXPPSZmbkz: [ 0.00 0.00 ] +Key: VGETEXPPSZmk: [ 0.00 0.00 ] +Key: VGETEXPPSZmkz: [ 0.00 0.00 ] +Key: VGETEXPPSZr: [ 0.00 0.00 ] +Key: VGETEXPPSZrb: [ 0.00 0.00 ] +Key: VGETEXPPSZrbk: [ 0.00 0.00 ] +Key: VGETEXPPSZrbkz: [ 0.00 0.00 ] +Key: VGETEXPPSZrk: [ 0.00 0.00 ] +Key: VGETEXPPSZrkz: [ 0.00 0.00 ] +Key: VGETEXPSDZm: [ 0.00 0.00 ] +Key: VGETEXPSDZmk: [ 0.00 0.00 ] +Key: VGETEXPSDZmkz: [ 0.00 0.00 ] +Key: VGETEXPSDZr: [ 0.00 0.00 ] +Key: VGETEXPSDZrb: [ 0.00 0.00 ] +Key: VGETEXPSDZrbk: [ 0.00 0.00 ] +Key: VGETEXPSDZrbkz: [ 0.00 0.00 ] +Key: VGETEXPSDZrk: [ 0.00 0.00 ] +Key: VGETEXPSDZrkz: [ 0.00 0.00 ] +Key: VGETEXPSHZm: [ 0.00 0.00 ] +Key: VGETEXPSHZmk: [ 0.00 0.00 ] +Key: VGETEXPSHZmkz: [ 0.00 0.00 ] +Key: VGETEXPSHZr: [ 0.00 0.00 ] +Key: VGETEXPSHZrb: [ 0.00 0.00 ] +Key: VGETEXPSHZrbk: [ 0.00 0.00 ] +Key: VGETEXPSHZrbkz: [ 0.00 0.00 ] +Key: VGETEXPSHZrk: [ 0.00 0.00 ] +Key: VGETEXPSHZrkz: [ 0.00 0.00 ] +Key: VGETEXPSSZm: [ 0.00 0.00 ] +Key: VGETEXPSSZmk: [ 0.00 0.00 ] +Key: VGETEXPSSZmkz: [ 0.00 0.00 ] +Key: VGETEXPSSZr: [ 0.00 0.00 ] +Key: VGETEXPSSZrb: [ 0.00 0.00 ] +Key: VGETEXPSSZrbk: [ 0.00 0.00 ] +Key: VGETEXPSSZrbkz: [ 0.00 0.00 ] +Key: VGETEXPSSZrk: [ 0.00 0.00 ] +Key: VGETEXPSSZrkz: [ 0.00 0.00 ] +Key: VGETMANTBF: [ 0.00 0.00 ] +Key: VGETMANTPDZ: [ 0.00 0.00 ] +Key: VGETMANTPDZrmbi: [ 0.00 0.00 ] +Key: VGETMANTPDZrmbik: [ 0.00 0.00 ] +Key: VGETMANTPDZrmbikz: [ 0.00 0.00 ] +Key: VGETMANTPDZrmi: [ 0.00 0.00 ] +Key: VGETMANTPDZrmik: [ 0.00 0.00 ] +Key: VGETMANTPDZrmikz: [ 0.00 0.00 ] +Key: VGETMANTPDZrri: [ 0.00 0.00 ] +Key: VGETMANTPDZrrib: [ 0.00 0.00 ] +Key: VGETMANTPDZrribk: [ 0.00 0.00 ] +Key: VGETMANTPDZrribkz: [ 0.00 0.00 ] +Key: VGETMANTPDZrrik: [ 0.00 0.00 ] +Key: VGETMANTPDZrrikz: [ 0.00 0.00 ] +Key: VGETMANTPHZ: [ 0.00 0.00 ] +Key: VGETMANTPHZrmbi: [ 0.00 0.00 ] +Key: VGETMANTPHZrmbik: [ 0.00 0.00 ] +Key: VGETMANTPHZrmbikz: [ 0.00 0.00 ] +Key: VGETMANTPHZrmi: [ 0.00 0.00 ] +Key: VGETMANTPHZrmik: [ 0.00 0.00 ] +Key: VGETMANTPHZrmikz: [ 0.00 0.00 ] +Key: VGETMANTPHZrri: [ 0.00 0.00 ] +Key: VGETMANTPHZrrib: [ 0.00 0.00 ] +Key: VGETMANTPHZrribk: [ 0.00 0.00 ] +Key: VGETMANTPHZrribkz: [ 0.00 0.00 ] +Key: VGETMANTPHZrrik: [ 0.00 0.00 ] +Key: VGETMANTPHZrrikz: [ 0.00 0.00 ] +Key: VGETMANTPSZ: [ 0.00 0.00 ] +Key: VGETMANTPSZrmbi: [ 0.00 0.00 ] +Key: VGETMANTPSZrmbik: [ 0.00 0.00 ] +Key: VGETMANTPSZrmbikz: [ 0.00 0.00 ] +Key: VGETMANTPSZrmi: [ 0.00 0.00 ] +Key: VGETMANTPSZrmik: [ 0.00 0.00 ] +Key: VGETMANTPSZrmikz: [ 0.00 0.00 ] +Key: VGETMANTPSZrri: [ 0.00 0.00 ] +Key: VGETMANTPSZrrib: [ 0.00 0.00 ] +Key: VGETMANTPSZrribk: [ 0.00 0.00 ] +Key: VGETMANTPSZrribkz: [ 0.00 0.00 ] +Key: VGETMANTPSZrrik: [ 0.00 0.00 ] +Key: VGETMANTPSZrrikz: [ 0.00 0.00 ] +Key: VGETMANTSDZrmi: [ 0.00 0.00 ] +Key: VGETMANTSDZrmik: [ 0.00 0.00 ] +Key: VGETMANTSDZrmikz: [ 0.00 0.00 ] +Key: VGETMANTSDZrri: [ 0.00 0.00 ] +Key: VGETMANTSDZrrib: [ 0.00 0.00 ] +Key: VGETMANTSDZrribk: [ 0.00 0.00 ] +Key: VGETMANTSDZrribkz: [ 0.00 0.00 ] +Key: VGETMANTSDZrrik: [ 0.00 0.00 ] +Key: VGETMANTSDZrrikz: [ 0.00 0.00 ] +Key: VGETMANTSHZrmi: [ 0.00 0.00 ] +Key: VGETMANTSHZrmik: [ 0.00 0.00 ] +Key: VGETMANTSHZrmikz: [ 0.00 0.00 ] +Key: VGETMANTSHZrri: [ 0.00 0.00 ] +Key: VGETMANTSHZrrib: [ 0.00 0.00 ] +Key: VGETMANTSHZrribk: [ 0.00 0.00 ] +Key: VGETMANTSHZrribkz: [ 0.00 0.00 ] +Key: VGETMANTSHZrrik: [ 0.00 0.00 ] +Key: VGETMANTSHZrrikz: [ 0.00 0.00 ] +Key: VGETMANTSSZrmi: [ 0.00 0.00 ] +Key: VGETMANTSSZrmik: [ 0.00 0.00 ] +Key: VGETMANTSSZrmikz: [ 0.00 0.00 ] +Key: VGETMANTSSZrri: [ 0.00 0.00 ] +Key: VGETMANTSSZrrib: [ 0.00 0.00 ] +Key: VGETMANTSSZrribk: [ 0.00 0.00 ] +Key: VGETMANTSSZrribkz: [ 0.00 0.00 ] +Key: VGETMANTSSZrrik: [ 0.00 0.00 ] +Key: VGETMANTSSZrrikz: [ 0.00 0.00 ] +Key: VGF: [ 0.00 0.00 ] +Key: VHADDPDYrm: [ 0.00 0.00 ] +Key: VHADDPDYrr: [ 0.00 0.00 ] +Key: VHADDPDrm: [ 0.00 0.00 ] +Key: VHADDPDrr: [ 0.00 0.00 ] +Key: VHADDPSYrm: [ 0.00 0.00 ] +Key: VHADDPSYrr: [ 0.00 0.00 ] +Key: VHADDPSrm: [ 0.00 0.00 ] +Key: VHADDPSrr: [ 0.00 0.00 ] +Key: VHSUBPDYrm: [ 0.00 0.00 ] +Key: VHSUBPDYrr: [ 0.00 0.00 ] +Key: VHSUBPDrm: [ 0.00 0.00 ] +Key: VHSUBPDrr: [ 0.00 0.00 ] +Key: VHSUBPSYrm: [ 0.00 0.00 ] +Key: VHSUBPSYrr: [ 0.00 0.00 ] +Key: VHSUBPSrm: [ 0.00 0.00 ] +Key: VHSUBPSrr: [ 0.00 0.00 ] +Key: VINSERTF: [ 0.00 0.00 ] +Key: VINSERTI: [ 0.00 0.00 ] +Key: VINSERTPSZrmi: [ 0.00 0.00 ] +Key: VINSERTPSZrri: [ 0.00 0.00 ] +Key: VINSERTPSrmi: [ 0.00 0.00 ] +Key: VINSERTPSrri: [ 0.00 0.00 ] +Key: VLDDQUYrm: [ 0.00 0.00 ] +Key: VLDDQUrm: [ 0.00 0.00 ] +Key: VLDMXCSR: [ 0.00 0.00 ] +Key: VMASKMOVDQU: [ 0.00 0.00 ] +Key: VMASKMOVPDYmr: [ 0.00 0.00 ] +Key: VMASKMOVPDYrm: [ 0.00 0.00 ] +Key: VMASKMOVPDmr: [ 0.00 0.00 ] +Key: VMASKMOVPDrm: [ 0.00 0.00 ] +Key: VMASKMOVPSYmr: [ 0.00 0.00 ] +Key: VMASKMOVPSYrm: [ 0.00 0.00 ] +Key: VMASKMOVPSmr: [ 0.00 0.00 ] +Key: VMASKMOVPSrm: [ 0.00 0.00 ] +Key: VMAXBF: [ 0.00 0.00 ] +Key: VMAXCPDYrm: [ 0.00 0.00 ] +Key: VMAXCPDYrr: [ 0.00 0.00 ] +Key: VMAXCPDZ: [ 0.00 0.00 ] +Key: VMAXCPDZrm: [ 0.00 0.00 ] +Key: VMAXCPDZrmb: [ 0.00 0.00 ] +Key: VMAXCPDZrmbk: [ 0.00 0.00 ] +Key: VMAXCPDZrmbkz: [ 0.00 0.00 ] +Key: VMAXCPDZrmk: [ 0.00 0.00 ] +Key: VMAXCPDZrmkz: [ 0.00 0.00 ] +Key: VMAXCPDZrr: [ 0.00 0.00 ] +Key: VMAXCPDZrrk: [ 0.00 0.00 ] +Key: VMAXCPDZrrkz: [ 0.00 0.00 ] +Key: VMAXCPDrm: [ 0.00 0.00 ] +Key: VMAXCPDrr: [ 0.00 0.00 ] +Key: VMAXCPHZ: [ 0.00 0.00 ] +Key: VMAXCPHZrm: [ 0.00 0.00 ] +Key: VMAXCPHZrmb: [ 0.00 0.00 ] +Key: VMAXCPHZrmbk: [ 0.00 0.00 ] +Key: VMAXCPHZrmbkz: [ 0.00 0.00 ] +Key: VMAXCPHZrmk: [ 0.00 0.00 ] +Key: VMAXCPHZrmkz: [ 0.00 0.00 ] +Key: VMAXCPHZrr: [ 0.00 0.00 ] +Key: VMAXCPHZrrk: [ 0.00 0.00 ] +Key: VMAXCPHZrrkz: [ 0.00 0.00 ] +Key: VMAXCPSYrm: [ 0.00 0.00 ] +Key: VMAXCPSYrr: [ 0.00 0.00 ] +Key: VMAXCPSZ: [ 0.00 0.00 ] +Key: VMAXCPSZrm: [ 0.00 0.00 ] +Key: VMAXCPSZrmb: [ 0.00 0.00 ] +Key: VMAXCPSZrmbk: [ 0.00 0.00 ] +Key: VMAXCPSZrmbkz: [ 0.00 0.00 ] +Key: VMAXCPSZrmk: [ 0.00 0.00 ] +Key: VMAXCPSZrmkz: [ 0.00 0.00 ] +Key: VMAXCPSZrr: [ 0.00 0.00 ] +Key: VMAXCPSZrrk: [ 0.00 0.00 ] +Key: VMAXCPSZrrkz: [ 0.00 0.00 ] +Key: VMAXCPSrm: [ 0.00 0.00 ] +Key: VMAXCPSrr: [ 0.00 0.00 ] +Key: VMAXCSDZrm: [ 0.00 0.00 ] +Key: VMAXCSDZrr: [ 0.00 0.00 ] +Key: VMAXCSDrm: [ 0.00 0.00 ] +Key: VMAXCSDrr: [ 0.00 0.00 ] +Key: VMAXCSHZrm: [ 0.00 0.00 ] +Key: VMAXCSHZrr: [ 0.00 0.00 ] +Key: VMAXCSSZrm: [ 0.00 0.00 ] +Key: VMAXCSSZrr: [ 0.00 0.00 ] +Key: VMAXCSSrm: [ 0.00 0.00 ] +Key: VMAXCSSrr: [ 0.00 0.00 ] +Key: VMAXPDYrm: [ 0.00 0.00 ] +Key: VMAXPDYrr: [ 0.00 0.00 ] +Key: VMAXPDZ: [ 0.00 0.00 ] +Key: VMAXPDZrm: [ 0.00 0.00 ] +Key: VMAXPDZrmb: [ 0.00 0.00 ] +Key: VMAXPDZrmbk: [ 0.00 0.00 ] +Key: VMAXPDZrmbkz: [ 0.00 0.00 ] +Key: VMAXPDZrmk: [ 0.00 0.00 ] +Key: VMAXPDZrmkz: [ 0.00 0.00 ] +Key: VMAXPDZrr: [ 0.00 0.00 ] +Key: VMAXPDZrrb: [ 0.00 0.00 ] +Key: VMAXPDZrrbk: [ 0.00 0.00 ] +Key: VMAXPDZrrbkz: [ 0.00 0.00 ] +Key: VMAXPDZrrk: [ 0.00 0.00 ] +Key: VMAXPDZrrkz: [ 0.00 0.00 ] +Key: VMAXPDrm: [ 0.00 0.00 ] +Key: VMAXPDrr: [ 0.00 0.00 ] +Key: VMAXPHZ: [ 0.00 0.00 ] +Key: VMAXPHZrm: [ 0.00 0.00 ] +Key: VMAXPHZrmb: [ 0.00 0.00 ] +Key: VMAXPHZrmbk: [ 0.00 0.00 ] +Key: VMAXPHZrmbkz: [ 0.00 0.00 ] +Key: VMAXPHZrmk: [ 0.00 0.00 ] +Key: VMAXPHZrmkz: [ 0.00 0.00 ] +Key: VMAXPHZrr: [ 0.00 0.00 ] +Key: VMAXPHZrrb: [ 0.00 0.00 ] +Key: VMAXPHZrrbk: [ 0.00 0.00 ] +Key: VMAXPHZrrbkz: [ 0.00 0.00 ] +Key: VMAXPHZrrk: [ 0.00 0.00 ] +Key: VMAXPHZrrkz: [ 0.00 0.00 ] +Key: VMAXPSYrm: [ 0.00 0.00 ] +Key: VMAXPSYrr: [ 0.00 0.00 ] +Key: VMAXPSZ: [ 0.00 0.00 ] +Key: VMAXPSZrm: [ 0.00 0.00 ] +Key: VMAXPSZrmb: [ 0.00 0.00 ] +Key: VMAXPSZrmbk: [ 0.00 0.00 ] +Key: VMAXPSZrmbkz: [ 0.00 0.00 ] +Key: VMAXPSZrmk: [ 0.00 0.00 ] +Key: VMAXPSZrmkz: [ 0.00 0.00 ] +Key: VMAXPSZrr: [ 0.00 0.00 ] +Key: VMAXPSZrrb: [ 0.00 0.00 ] +Key: VMAXPSZrrbk: [ 0.00 0.00 ] +Key: VMAXPSZrrbkz: [ 0.00 0.00 ] +Key: VMAXPSZrrk: [ 0.00 0.00 ] +Key: VMAXPSZrrkz: [ 0.00 0.00 ] +Key: VMAXPSrm: [ 0.00 0.00 ] +Key: VMAXPSrr: [ 0.00 0.00 ] +Key: VMAXSDZrm: [ 0.00 0.00 ] +Key: VMAXSDZrm_Int: [ 0.00 0.00 ] +Key: VMAXSDZrmk_Int: [ 0.00 0.00 ] +Key: VMAXSDZrmkz_Int: [ 0.00 0.00 ] +Key: VMAXSDZrr: [ 0.00 0.00 ] +Key: VMAXSDZrr_Int: [ 0.00 0.00 ] +Key: VMAXSDZrrb_Int: [ 0.00 0.00 ] +Key: VMAXSDZrrbk_Int: [ 0.00 0.00 ] +Key: VMAXSDZrrbkz_Int: [ 0.00 0.00 ] +Key: VMAXSDZrrk_Int: [ 0.00 0.00 ] +Key: VMAXSDZrrkz_Int: [ 0.00 0.00 ] +Key: VMAXSDrm: [ 0.00 0.00 ] +Key: VMAXSDrm_Int: [ 0.00 0.00 ] +Key: VMAXSDrr: [ 0.00 0.00 ] +Key: VMAXSDrr_Int: [ 0.00 0.00 ] +Key: VMAXSHZrm: [ 0.00 0.00 ] +Key: VMAXSHZrm_Int: [ 0.00 0.00 ] +Key: VMAXSHZrmk_Int: [ 0.00 0.00 ] +Key: VMAXSHZrmkz_Int: [ 0.00 0.00 ] +Key: VMAXSHZrr: [ 0.00 0.00 ] +Key: VMAXSHZrr_Int: [ 0.00 0.00 ] +Key: VMAXSHZrrb_Int: [ 0.00 0.00 ] +Key: VMAXSHZrrbk_Int: [ 0.00 0.00 ] +Key: VMAXSHZrrbkz_Int: [ 0.00 0.00 ] +Key: VMAXSHZrrk_Int: [ 0.00 0.00 ] +Key: VMAXSHZrrkz_Int: [ 0.00 0.00 ] +Key: VMAXSSZrm: [ 0.00 0.00 ] +Key: VMAXSSZrm_Int: [ 0.00 0.00 ] +Key: VMAXSSZrmk_Int: [ 0.00 0.00 ] +Key: VMAXSSZrmkz_Int: [ 0.00 0.00 ] +Key: VMAXSSZrr: [ 0.00 0.00 ] +Key: VMAXSSZrr_Int: [ 0.00 0.00 ] +Key: VMAXSSZrrb_Int: [ 0.00 0.00 ] +Key: VMAXSSZrrbk_Int: [ 0.00 0.00 ] +Key: VMAXSSZrrbkz_Int: [ 0.00 0.00 ] +Key: VMAXSSZrrk_Int: [ 0.00 0.00 ] +Key: VMAXSSZrrkz_Int: [ 0.00 0.00 ] +Key: VMAXSSrm: [ 0.00 0.00 ] +Key: VMAXSSrm_Int: [ 0.00 0.00 ] +Key: VMAXSSrr: [ 0.00 0.00 ] +Key: VMAXSSrr_Int: [ 0.00 0.00 ] +Key: VMCALL: [ 0.00 0.00 ] +Key: VMCLEARm: [ 0.00 0.00 ] +Key: VMFUNC: [ 0.00 0.00 ] +Key: VMINBF: [ 0.00 0.00 ] +Key: VMINCPDYrm: [ 0.00 0.00 ] +Key: VMINCPDYrr: [ 0.00 0.00 ] +Key: VMINCPDZ: [ 0.00 0.00 ] +Key: VMINCPDZrm: [ 0.00 0.00 ] +Key: VMINCPDZrmb: [ 0.00 0.00 ] +Key: VMINCPDZrmbk: [ 0.00 0.00 ] +Key: VMINCPDZrmbkz: [ 0.00 0.00 ] +Key: VMINCPDZrmk: [ 0.00 0.00 ] +Key: VMINCPDZrmkz: [ 0.00 0.00 ] +Key: VMINCPDZrr: [ 0.00 0.00 ] +Key: VMINCPDZrrk: [ 0.00 0.00 ] +Key: VMINCPDZrrkz: [ 0.00 0.00 ] +Key: VMINCPDrm: [ 0.00 0.00 ] +Key: VMINCPDrr: [ 0.00 0.00 ] +Key: VMINCPHZ: [ 0.00 0.00 ] +Key: VMINCPHZrm: [ 0.00 0.00 ] +Key: VMINCPHZrmb: [ 0.00 0.00 ] +Key: VMINCPHZrmbk: [ 0.00 0.00 ] +Key: VMINCPHZrmbkz: [ 0.00 0.00 ] +Key: VMINCPHZrmk: [ 0.00 0.00 ] +Key: VMINCPHZrmkz: [ 0.00 0.00 ] +Key: VMINCPHZrr: [ 0.00 0.00 ] +Key: VMINCPHZrrk: [ 0.00 0.00 ] +Key: VMINCPHZrrkz: [ 0.00 0.00 ] +Key: VMINCPSYrm: [ 0.00 0.00 ] +Key: VMINCPSYrr: [ 0.00 0.00 ] +Key: VMINCPSZ: [ 0.00 0.00 ] +Key: VMINCPSZrm: [ 0.00 0.00 ] +Key: VMINCPSZrmb: [ 0.00 0.00 ] +Key: VMINCPSZrmbk: [ 0.00 0.00 ] +Key: VMINCPSZrmbkz: [ 0.00 0.00 ] +Key: VMINCPSZrmk: [ 0.00 0.00 ] +Key: VMINCPSZrmkz: [ 0.00 0.00 ] +Key: VMINCPSZrr: [ 0.00 0.00 ] +Key: VMINCPSZrrk: [ 0.00 0.00 ] +Key: VMINCPSZrrkz: [ 0.00 0.00 ] +Key: VMINCPSrm: [ 0.00 0.00 ] +Key: VMINCPSrr: [ 0.00 0.00 ] +Key: VMINCSDZrm: [ 0.00 0.00 ] +Key: VMINCSDZrr: [ 0.00 0.00 ] +Key: VMINCSDrm: [ 0.00 0.00 ] +Key: VMINCSDrr: [ 0.00 0.00 ] +Key: VMINCSHZrm: [ 0.00 0.00 ] +Key: VMINCSHZrr: [ 0.00 0.00 ] +Key: VMINCSSZrm: [ 0.00 0.00 ] +Key: VMINCSSZrr: [ 0.00 0.00 ] +Key: VMINCSSrm: [ 0.00 0.00 ] +Key: VMINCSSrr: [ 0.00 0.00 ] +Key: VMINMAXBF: [ 0.00 0.00 ] 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0.00 ] +Key: VMINMAXPSZrmbik: [ 0.00 0.00 ] +Key: VMINMAXPSZrmbikz: [ 0.00 0.00 ] +Key: VMINMAXPSZrmi: [ 0.00 0.00 ] +Key: VMINMAXPSZrmik: [ 0.00 0.00 ] +Key: VMINMAXPSZrmikz: [ 0.00 0.00 ] +Key: VMINMAXPSZrri: [ 0.00 0.00 ] +Key: VMINMAXPSZrrib: [ 0.00 0.00 ] +Key: VMINMAXPSZrribk: [ 0.00 0.00 ] +Key: VMINMAXPSZrribkz: [ 0.00 0.00 ] +Key: VMINMAXPSZrrik: [ 0.00 0.00 ] +Key: VMINMAXPSZrrikz: [ 0.00 0.00 ] +Key: VMINMAXSDrmi: [ 0.00 0.00 ] +Key: VMINMAXSDrmi_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrmik_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrmikz_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrri: [ 0.00 0.00 ] +Key: VMINMAXSDrri_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrrib_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrribk_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrribkz_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrrik_Int: [ 0.00 0.00 ] +Key: VMINMAXSDrrikz_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrmi: [ 0.00 0.00 ] +Key: VMINMAXSHrmi_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrmik_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrmikz_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrri: [ 0.00 0.00 ] +Key: VMINMAXSHrri_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrrib_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrribk_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrribkz_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrrik_Int: [ 0.00 0.00 ] +Key: VMINMAXSHrrikz_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrmi: [ 0.00 0.00 ] +Key: VMINMAXSSrmi_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrmik_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrmikz_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrri: [ 0.00 0.00 ] +Key: VMINMAXSSrri_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrrib_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrribk_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrribkz_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrrik_Int: [ 0.00 0.00 ] +Key: VMINMAXSSrrikz_Int: [ 0.00 0.00 ] +Key: VMINPDYrm: [ 0.00 0.00 ] +Key: VMINPDYrr: [ 0.00 0.00 ] +Key: VMINPDZ: [ 0.00 0.00 ] +Key: VMINPDZrm: [ 0.00 0.00 ] +Key: VMINPDZrmb: [ 0.00 0.00 ] +Key: VMINPDZrmbk: [ 0.00 0.00 ] +Key: VMINPDZrmbkz: [ 0.00 0.00 ] +Key: VMINPDZrmk: [ 0.00 0.00 ] +Key: VMINPDZrmkz: [ 0.00 0.00 ] +Key: VMINPDZrr: [ 0.00 0.00 ] +Key: VMINPDZrrb: [ 0.00 0.00 ] +Key: VMINPDZrrbk: [ 0.00 0.00 ] +Key: VMINPDZrrbkz: [ 0.00 0.00 ] +Key: VMINPDZrrk: [ 0.00 0.00 ] +Key: VMINPDZrrkz: [ 0.00 0.00 ] +Key: VMINPDrm: [ 0.00 0.00 ] +Key: VMINPDrr: [ 0.00 0.00 ] +Key: VMINPHZ: [ 0.00 0.00 ] +Key: VMINPHZrm: [ 0.00 0.00 ] +Key: VMINPHZrmb: [ 0.00 0.00 ] +Key: VMINPHZrmbk: [ 0.00 0.00 ] +Key: VMINPHZrmbkz: [ 0.00 0.00 ] +Key: VMINPHZrmk: [ 0.00 0.00 ] +Key: VMINPHZrmkz: [ 0.00 0.00 ] +Key: VMINPHZrr: [ 0.00 0.00 ] +Key: VMINPHZrrb: [ 0.00 0.00 ] +Key: VMINPHZrrbk: [ 0.00 0.00 ] +Key: VMINPHZrrbkz: [ 0.00 0.00 ] +Key: VMINPHZrrk: [ 0.00 0.00 ] +Key: VMINPHZrrkz: [ 0.00 0.00 ] +Key: VMINPSYrm: [ 0.00 0.00 ] +Key: VMINPSYrr: [ 0.00 0.00 ] +Key: VMINPSZ: [ 0.00 0.00 ] +Key: VMINPSZrm: [ 0.00 0.00 ] +Key: VMINPSZrmb: [ 0.00 0.00 ] +Key: VMINPSZrmbk: [ 0.00 0.00 ] +Key: VMINPSZrmbkz: [ 0.00 0.00 ] +Key: VMINPSZrmk: [ 0.00 0.00 ] +Key: VMINPSZrmkz: [ 0.00 0.00 ] +Key: VMINPSZrr: [ 0.00 0.00 ] +Key: VMINPSZrrb: [ 0.00 0.00 ] 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VMINSHZrrbkz_Int: [ 0.00 0.00 ] +Key: VMINSHZrrk_Int: [ 0.00 0.00 ] +Key: VMINSHZrrkz_Int: [ 0.00 0.00 ] +Key: VMINSSZrm: [ 0.00 0.00 ] +Key: VMINSSZrm_Int: [ 0.00 0.00 ] +Key: VMINSSZrmk_Int: [ 0.00 0.00 ] +Key: VMINSSZrmkz_Int: [ 0.00 0.00 ] +Key: VMINSSZrr: [ 0.00 0.00 ] +Key: VMINSSZrr_Int: [ 0.00 0.00 ] +Key: VMINSSZrrb_Int: [ 0.00 0.00 ] +Key: VMINSSZrrbk_Int: [ 0.00 0.00 ] +Key: VMINSSZrrbkz_Int: [ 0.00 0.00 ] +Key: VMINSSZrrk_Int: [ 0.00 0.00 ] +Key: VMINSSZrrkz_Int: [ 0.00 0.00 ] +Key: VMINSSrm: [ 0.00 0.00 ] +Key: VMINSSrm_Int: [ 0.00 0.00 ] +Key: VMINSSrr: [ 0.00 0.00 ] +Key: VMINSSrr_Int: [ 0.00 0.00 ] +Key: VMLAUNCH: [ 0.00 0.00 ] +Key: VMLOAD: [ 0.00 0.00 ] +Key: VMMCALL: [ 0.00 0.00 ] +Key: VMOV: [ 0.00 0.00 ] +Key: VMOVAPDYmr: [ 0.00 0.00 ] +Key: VMOVAPDYrm: [ 0.00 0.00 ] +Key: VMOVAPDYrr: [ 0.00 0.00 ] +Key: VMOVAPDYrr_REV: [ 0.00 0.00 ] +Key: VMOVAPDZ: [ 0.00 0.00 ] +Key: VMOVAPDZmr: [ 0.00 0.00 ] +Key: VMOVAPDZmrk: [ 0.00 0.00 ] +Key: VMOVAPDZrm: [ 0.00 0.00 ] +Key: VMOVAPDZrmk: [ 0.00 0.00 ] +Key: VMOVAPDZrmkz: [ 0.00 0.00 ] +Key: VMOVAPDZrr: [ 0.00 0.00 ] +Key: VMOVAPDZrr_REV: [ 0.00 0.00 ] +Key: VMOVAPDZrrk: [ 0.00 0.00 ] +Key: VMOVAPDZrrk_REV: [ 0.00 0.00 ] +Key: VMOVAPDZrrkz: [ 0.00 0.00 ] +Key: VMOVAPDZrrkz_REV: [ 0.00 0.00 ] +Key: VMOVAPDmr: [ 0.00 0.00 ] +Key: VMOVAPDrm: [ 0.00 0.00 ] +Key: VMOVAPDrr: [ 0.00 0.00 ] +Key: VMOVAPDrr_REV: [ 0.00 0.00 ] +Key: VMOVAPSYmr: [ 0.00 0.00 ] +Key: VMOVAPSYrm: [ 0.00 0.00 ] +Key: VMOVAPSYrr: [ 0.00 0.00 ] +Key: VMOVAPSYrr_REV: [ 0.00 0.00 ] +Key: VMOVAPSZ: [ 0.00 0.00 ] +Key: VMOVAPSZmr: [ 0.00 0.00 ] +Key: VMOVAPSZmrk: [ 0.00 0.00 ] +Key: VMOVAPSZrm: [ 0.00 0.00 ] +Key: VMOVAPSZrmk: [ 0.00 0.00 ] +Key: VMOVAPSZrmkz: [ 0.00 0.00 ] +Key: VMOVAPSZrr: [ 0.00 0.00 ] +Key: VMOVAPSZrr_REV: [ 0.00 0.00 ] +Key: VMOVAPSZrrk: [ 0.00 0.00 ] +Key: VMOVAPSZrrk_REV: [ 0.00 0.00 ] +Key: VMOVAPSZrrkz: [ 0.00 0.00 ] +Key: VMOVAPSZrrkz_REV: [ 0.00 0.00 ] +Key: VMOVAPSmr: [ 0.00 0.00 ] +Key: VMOVAPSrm: [ 0.00 0.00 ] +Key: VMOVAPSrr: [ 0.00 0.00 ] +Key: VMOVAPSrr_REV: [ 0.00 0.00 ] +Key: VMOVDDUPYrm: [ 0.00 0.00 ] +Key: VMOVDDUPYrr: [ 0.00 0.00 ] +Key: VMOVDDUPZ: [ 0.00 0.00 ] +Key: VMOVDDUPZrm: [ 0.00 0.00 ] +Key: VMOVDDUPZrmk: [ 0.00 0.00 ] +Key: VMOVDDUPZrmkz: [ 0.00 0.00 ] +Key: VMOVDDUPZrr: [ 0.00 0.00 ] +Key: VMOVDDUPZrrk: [ 0.00 0.00 ] +Key: VMOVDDUPZrrkz: [ 0.00 0.00 ] +Key: VMOVDDUPrm: [ 0.00 0.00 ] +Key: VMOVDDUPrr: [ 0.00 0.00 ] +Key: VMOVDI: [ 0.00 0.00 ] +Key: VMOVDQA: [ 0.00 0.00 ] +Key: VMOVDQAYmr: [ 0.00 0.00 ] +Key: VMOVDQAYrm: [ 0.00 0.00 ] +Key: VMOVDQAYrr: [ 0.00 0.00 ] +Key: VMOVDQAYrr_REV: [ 0.00 0.00 ] +Key: VMOVDQAmr: [ 0.00 0.00 ] +Key: VMOVDQArm: [ 0.00 0.00 ] +Key: VMOVDQArr: [ 0.00 0.00 ] +Key: VMOVDQArr_REV: [ 0.00 0.00 ] +Key: VMOVDQU: [ 0.00 0.00 ] +Key: VMOVDQUYmr: [ 0.00 0.00 ] +Key: VMOVDQUYrm: [ 0.00 0.00 ] +Key: VMOVDQUYrr: [ 0.00 0.00 ] +Key: VMOVDQUYrr_REV: [ 0.00 0.00 ] +Key: VMOVDQUmr: [ 0.00 0.00 ] +Key: VMOVDQUrm: [ 0.00 0.00 ] +Key: VMOVDQUrr: [ 0.00 0.00 ] +Key: VMOVDQUrr_REV: [ 0.00 0.00 ] +Key: VMOVHLPSZrr: [ 0.00 0.00 ] +Key: VMOVHLPSrr: [ 0.00 0.00 ] +Key: VMOVHPDZ: [ 0.00 0.00 ] +Key: VMOVHPDmr: [ 0.00 0.00 ] +Key: VMOVHPDrm: [ 0.00 0.00 ] +Key: VMOVHPSZ: [ 0.00 0.00 ] +Key: VMOVHPSmr: [ 0.00 0.00 ] +Key: VMOVHPSrm: [ 0.00 0.00 ] +Key: VMOVLHPSZrr: [ 0.00 0.00 ] +Key: VMOVLHPSrr: [ 0.00 0.00 ] +Key: VMOVLPDZ: [ 0.00 0.00 ] +Key: VMOVLPDmr: [ 0.00 0.00 ] +Key: VMOVLPDrm: [ 0.00 0.00 ] +Key: VMOVLPSZ: [ 0.00 0.00 ] +Key: VMOVLPSmr: [ 0.00 0.00 ] +Key: VMOVLPSrm: [ 0.00 0.00 ] +Key: VMOVMSKPDYrr: [ 0.00 0.00 ] +Key: VMOVMSKPDrr: [ 0.00 0.00 ] +Key: VMOVMSKPSYrr: [ 0.00 0.00 ] +Key: VMOVMSKPSrr: [ 0.00 0.00 ] +Key: VMOVNTDQAYrm: [ 0.00 0.00 ] +Key: VMOVNTDQAZ: [ 0.00 0.00 ] +Key: VMOVNTDQAZrm: [ 0.00 0.00 ] +Key: VMOVNTDQArm: [ 0.00 0.00 ] +Key: VMOVNTDQYmr: [ 0.00 0.00 ] +Key: VMOVNTDQZ: [ 0.00 0.00 ] +Key: VMOVNTDQZmr: [ 0.00 0.00 ] +Key: VMOVNTDQmr: [ 0.00 0.00 ] +Key: VMOVNTPDYmr: [ 0.00 0.00 ] +Key: VMOVNTPDZ: [ 0.00 0.00 ] +Key: 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VPERMDYrr: [ 0.00 0.00 ] +Key: VPERMDZ: [ 0.00 0.00 ] +Key: VPERMDZrm: [ 0.00 0.00 ] +Key: VPERMDZrmb: [ 0.00 0.00 ] +Key: VPERMDZrmbk: [ 0.00 0.00 ] +Key: VPERMDZrmbkz: [ 0.00 0.00 ] +Key: VPERMDZrmk: [ 0.00 0.00 ] +Key: VPERMDZrmkz: [ 0.00 0.00 ] +Key: VPERMDZrr: [ 0.00 0.00 ] +Key: VPERMDZrrk: [ 0.00 0.00 ] +Key: VPERMDZrrkz: [ 0.00 0.00 ] +Key: VPERMI: [ 0.00 0.00 ] +Key: VPERMIL: [ 0.00 0.00 ] +Key: VPERMILPDYmi: [ 0.00 0.00 ] +Key: VPERMILPDYri: [ 0.00 0.00 ] +Key: VPERMILPDYrm: [ 0.00 0.00 ] +Key: VPERMILPDYrr: [ 0.00 0.00 ] +Key: VPERMILPDZ: [ 0.00 0.00 ] +Key: VPERMILPDZmbi: [ 0.00 0.00 ] +Key: VPERMILPDZmbik: [ 0.00 0.00 ] +Key: VPERMILPDZmbikz: [ 0.00 0.00 ] +Key: VPERMILPDZmi: [ 0.00 0.00 ] +Key: VPERMILPDZmik: [ 0.00 0.00 ] +Key: VPERMILPDZmikz: [ 0.00 0.00 ] +Key: VPERMILPDZri: [ 0.00 0.00 ] +Key: VPERMILPDZrik: [ 0.00 0.00 ] +Key: VPERMILPDZrikz: [ 0.00 0.00 ] +Key: VPERMILPDZrm: [ 0.00 0.00 ] +Key: VPERMILPDZrmb: [ 0.00 0.00 ] +Key: VPERMILPDZrmbk: [ 0.00 0.00 ] +Key: VPERMILPDZrmbkz: [ 0.00 0.00 ] +Key: VPERMILPDZrmk: [ 0.00 0.00 ] +Key: VPERMILPDZrmkz: [ 0.00 0.00 ] +Key: VPERMILPDZrr: [ 0.00 0.00 ] +Key: VPERMILPDZrrk: [ 0.00 0.00 ] +Key: VPERMILPDZrrkz: [ 0.00 0.00 ] +Key: VPERMILPDmi: [ 0.00 0.00 ] +Key: VPERMILPDri: [ 0.00 0.00 ] +Key: VPERMILPDrm: [ 0.00 0.00 ] +Key: VPERMILPDrr: [ 0.00 0.00 ] +Key: VPERMILPSYmi: [ 0.00 0.00 ] +Key: VPERMILPSYri: [ 0.00 0.00 ] +Key: VPERMILPSYrm: [ 0.00 0.00 ] +Key: VPERMILPSYrr: [ 0.00 0.00 ] +Key: VPERMILPSZ: [ 0.00 0.00 ] +Key: VPERMILPSZmbi: [ 0.00 0.00 ] +Key: VPERMILPSZmbik: [ 0.00 0.00 ] +Key: VPERMILPSZmbikz: [ 0.00 0.00 ] +Key: VPERMILPSZmi: [ 0.00 0.00 ] +Key: VPERMILPSZmik: [ 0.00 0.00 ] +Key: VPERMILPSZmikz: [ 0.00 0.00 ] +Key: VPERMILPSZri: [ 0.00 0.00 ] +Key: VPERMILPSZrik: [ 0.00 0.00 ] +Key: VPERMILPSZrikz: [ 0.00 0.00 ] +Key: VPERMILPSZrm: [ 0.00 0.00 ] +Key: VPERMILPSZrmb: [ 0.00 0.00 ] +Key: VPERMILPSZrmbk: [ 0.00 0.00 ] +Key: VPERMILPSZrmbkz: [ 0.00 0.00 ] +Key: VPERMILPSZrmk: [ 0.00 0.00 ] +Key: VPERMILPSZrmkz: [ 0.00 0.00 ] +Key: VPERMILPSZrr: [ 0.00 0.00 ] +Key: VPERMILPSZrrk: [ 0.00 0.00 ] +Key: VPERMILPSZrrkz: [ 0.00 0.00 ] +Key: VPERMILPSmi: [ 0.00 0.00 ] +Key: VPERMILPSri: [ 0.00 0.00 ] +Key: VPERMILPSrm: [ 0.00 0.00 ] +Key: VPERMILPSrr: [ 0.00 0.00 ] +Key: VPERMPDYmi: [ 0.00 0.00 ] +Key: VPERMPDYri: [ 0.00 0.00 ] +Key: VPERMPDZ: [ 0.00 0.00 ] +Key: VPERMPDZmbi: [ 0.00 0.00 ] +Key: VPERMPDZmbik: [ 0.00 0.00 ] +Key: VPERMPDZmbikz: [ 0.00 0.00 ] +Key: VPERMPDZmi: [ 0.00 0.00 ] +Key: VPERMPDZmik: [ 0.00 0.00 ] +Key: VPERMPDZmikz: [ 0.00 0.00 ] +Key: VPERMPDZri: [ 0.00 0.00 ] +Key: VPERMPDZrik: [ 0.00 0.00 ] +Key: VPERMPDZrikz: [ 0.00 0.00 ] +Key: VPERMPDZrm: [ 0.00 0.00 ] +Key: VPERMPDZrmb: [ 0.00 0.00 ] +Key: VPERMPDZrmbk: [ 0.00 0.00 ] +Key: VPERMPDZrmbkz: [ 0.00 0.00 ] +Key: VPERMPDZrmk: [ 0.00 0.00 ] +Key: VPERMPDZrmkz: [ 0.00 0.00 ] +Key: VPERMPDZrr: [ 0.00 0.00 ] +Key: VPERMPDZrrk: [ 0.00 0.00 ] +Key: VPERMPDZrrkz: [ 0.00 0.00 ] +Key: VPERMPSYrm: [ 0.00 0.00 ] +Key: VPERMPSYrr: [ 0.00 0.00 ] +Key: VPERMPSZ: [ 0.00 0.00 ] +Key: VPERMPSZrm: [ 0.00 0.00 ] +Key: VPERMPSZrmb: [ 0.00 0.00 ] +Key: VPERMPSZrmbk: [ 0.00 0.00 ] +Key: VPERMPSZrmbkz: [ 0.00 0.00 ] +Key: VPERMPSZrmk: [ 0.00 0.00 ] +Key: VPERMPSZrmkz: [ 0.00 0.00 ] +Key: VPERMPSZrr: [ 0.00 0.00 ] +Key: VPERMPSZrrk: [ 0.00 0.00 ] +Key: VPERMPSZrrkz: [ 0.00 0.00 ] +Key: VPERMQYmi: [ 0.00 0.00 ] +Key: VPERMQYri: [ 0.00 0.00 ] +Key: VPERMQZ: [ 0.00 0.00 ] +Key: VPERMQZmbi: [ 0.00 0.00 ] +Key: VPERMQZmbik: [ 0.00 0.00 ] +Key: VPERMQZmbikz: [ 0.00 0.00 ] +Key: VPERMQZmi: [ 0.00 0.00 ] +Key: VPERMQZmik: [ 0.00 0.00 ] +Key: VPERMQZmikz: [ 0.00 0.00 ] +Key: VPERMQZri: [ 0.00 0.00 ] +Key: VPERMQZrik: [ 0.00 0.00 ] +Key: VPERMQZrikz: [ 0.00 0.00 ] +Key: VPERMQZrm: [ 0.00 0.00 ] +Key: VPERMQZrmb: [ 0.00 0.00 ] +Key: VPERMQZrmbk: [ 0.00 0.00 ] +Key: VPERMQZrmbkz: [ 0.00 0.00 ] +Key: VPERMQZrmk: [ 0.00 0.00 ] +Key: VPERMQZrmkz: [ 0.00 0.00 ] +Key: VPERMQZrr: [ 0.00 0.00 ] +Key: VPERMQZrrk: [ 0.00 0.00 ] +Key: VPERMQZrrkz: [ 0.00 0.00 ] +Key: VPERMT: [ 0.00 0.00 ] +Key: VPERMWZ: [ 0.00 0.00 ] +Key: VPERMWZrm: [ 0.00 0.00 ] +Key: VPERMWZrmk: [ 0.00 0.00 ] +Key: VPERMWZrmkz: [ 0.00 0.00 ] +Key: VPERMWZrr: [ 0.00 0.00 ] +Key: VPERMWZrrk: [ 0.00 0.00 ] +Key: VPERMWZrrkz: [ 0.00 0.00 ] +Key: VPEXPANDBZ: [ 0.00 0.00 ] +Key: VPEXPANDBZrm: [ 0.00 0.00 ] +Key: VPEXPANDBZrmk: [ 0.00 0.00 ] +Key: VPEXPANDBZrmkz: [ 0.00 0.00 ] +Key: VPEXPANDBZrr: [ 0.00 0.00 ] +Key: VPEXPANDBZrrk: [ 0.00 0.00 ] +Key: VPEXPANDBZrrkz: [ 0.00 0.00 ] +Key: VPEXPANDDZ: [ 0.00 0.00 ] +Key: VPEXPANDDZrm: [ 0.00 0.00 ] +Key: VPEXPANDDZrmk: [ 0.00 0.00 ] +Key: VPEXPANDDZrmkz: [ 0.00 0.00 ] +Key: VPEXPANDDZrr: [ 0.00 0.00 ] +Key: VPEXPANDDZrrk: [ 0.00 0.00 ] +Key: VPEXPANDDZrrkz: [ 0.00 0.00 ] +Key: VPEXPANDQZ: [ 0.00 0.00 ] +Key: VPEXPANDQZrm: [ 0.00 0.00 ] +Key: VPEXPANDQZrmk: [ 0.00 0.00 ] +Key: VPEXPANDQZrmkz: [ 0.00 0.00 ] +Key: VPEXPANDQZrr: [ 0.00 0.00 ] +Key: VPEXPANDQZrrk: [ 0.00 0.00 ] +Key: VPEXPANDQZrrkz: [ 0.00 0.00 ] +Key: VPEXPANDWZ: [ 0.00 0.00 ] +Key: VPEXPANDWZrm: [ 0.00 0.00 ] +Key: VPEXPANDWZrmk: [ 0.00 0.00 ] +Key: VPEXPANDWZrmkz: [ 0.00 0.00 ] +Key: VPEXPANDWZrr: [ 0.00 0.00 ] +Key: VPEXPANDWZrrk: [ 0.00 0.00 ] +Key: VPEXPANDWZrrkz: [ 0.00 0.00 ] +Key: VPEXTRBZmri: [ 0.00 0.00 ] +Key: VPEXTRBZrri: [ 0.00 0.00 ] +Key: VPEXTRBmri: [ 0.00 0.00 ] +Key: VPEXTRBrri: [ 0.00 0.00 ] +Key: VPEXTRDZmri: [ 0.00 0.00 ] +Key: VPEXTRDZrri: [ 0.00 0.00 ] +Key: VPEXTRDmri: [ 0.00 0.00 ] +Key: VPEXTRDrri: [ 0.00 0.00 ] +Key: VPEXTRQZmri: [ 0.00 0.00 ] +Key: VPEXTRQZrri: [ 0.00 0.00 ] +Key: VPEXTRQmri: [ 0.00 0.00 ] +Key: VPEXTRQrri: [ 0.00 0.00 ] +Key: VPEXTRWZmri: [ 0.00 0.00 ] +Key: VPEXTRWZrri: [ 0.00 0.00 ] +Key: VPEXTRWZrri_REV: [ 0.00 0.00 ] +Key: VPEXTRWmri: [ 0.00 0.00 ] +Key: VPEXTRWrri: [ 0.00 0.00 ] +Key: VPEXTRWrri_REV: [ 0.00 0.00 ] +Key: VPGATHERDDYrm: [ 0.00 0.00 ] +Key: VPGATHERDDZ: [ 0.00 0.00 ] +Key: VPGATHERDDZrm: [ 0.00 0.00 ] +Key: VPGATHERDDrm: [ 0.00 0.00 ] +Key: VPGATHERDQYrm: [ 0.00 0.00 ] +Key: VPGATHERDQZ: [ 0.00 0.00 ] +Key: VPGATHERDQZrm: [ 0.00 0.00 ] +Key: VPGATHERDQrm: [ 0.00 0.00 ] +Key: VPGATHERQDYrm: [ 0.00 0.00 ] +Key: VPGATHERQDZ: [ 0.00 0.00 ] +Key: VPGATHERQDZrm: [ 0.00 0.00 ] +Key: VPGATHERQDrm: [ 0.00 0.00 ] +Key: VPGATHERQQYrm: [ 0.00 0.00 ] +Key: VPGATHERQQZ: [ 0.00 0.00 ] +Key: VPGATHERQQZrm: [ 0.00 0.00 ] +Key: VPGATHERQQrm: [ 0.00 0.00 ] +Key: VPHADDBDrm: [ 0.00 0.00 ] +Key: VPHADDBDrr: [ 0.00 0.00 ] +Key: VPHADDBQrm: [ 0.00 0.00 ] +Key: VPHADDBQrr: [ 0.00 0.00 ] +Key: VPHADDBWrm: [ 0.00 0.00 ] +Key: VPHADDBWrr: [ 0.00 0.00 ] +Key: VPHADDDQrm: [ 0.00 0.00 ] +Key: VPHADDDQrr: [ 0.00 0.00 ] +Key: VPHADDDYrm: [ 0.00 0.00 ] +Key: VPHADDDYrr: [ 0.00 0.00 ] +Key: VPHADDDrm: [ 0.00 0.00 ] +Key: VPHADDDrr: [ 0.00 0.00 ] +Key: VPHADDSWYrm: [ 0.00 0.00 ] +Key: VPHADDSWYrr: [ 0.00 0.00 ] +Key: VPHADDSWrm: [ 0.00 0.00 ] +Key: VPHADDSWrr: [ 0.00 0.00 ] +Key: VPHADDUBDrm: [ 0.00 0.00 ] +Key: VPHADDUBDrr: [ 0.00 0.00 ] +Key: VPHADDUBQrm: [ 0.00 0.00 ] +Key: VPHADDUBQrr: [ 0.00 0.00 ] +Key: VPHADDUBWrm: [ 0.00 0.00 ] +Key: VPHADDUBWrr: [ 0.00 0.00 ] +Key: VPHADDUDQrm: [ 0.00 0.00 ] +Key: VPHADDUDQrr: [ 0.00 0.00 ] +Key: VPHADDUWDrm: [ 0.00 0.00 ] +Key: VPHADDUWDrr: [ 0.00 0.00 ] +Key: VPHADDUWQrm: [ 0.00 0.00 ] +Key: VPHADDUWQrr: [ 0.00 0.00 ] +Key: VPHADDWDrm: [ 0.00 0.00 ] +Key: VPHADDWDrr: [ 0.00 0.00 ] +Key: VPHADDWQrm: [ 0.00 0.00 ] +Key: VPHADDWQrr: [ 0.00 0.00 ] +Key: VPHADDWYrm: [ 0.00 0.00 ] +Key: VPHADDWYrr: [ 0.00 0.00 ] +Key: VPHADDWrm: [ 0.00 0.00 ] +Key: VPHADDWrr: [ 0.00 0.00 ] +Key: VPHMINPOSUWrm: [ 0.00 0.00 ] +Key: VPHMINPOSUWrr: [ 0.00 0.00 ] +Key: VPHSUBBWrm: [ 0.00 0.00 ] +Key: VPHSUBBWrr: [ 0.00 0.00 ] +Key: VPHSUBDQrm: [ 0.00 0.00 ] +Key: VPHSUBDQrr: [ 0.00 0.00 ] +Key: VPHSUBDYrm: [ 0.00 0.00 ] +Key: VPHSUBDYrr: [ 0.00 0.00 ] +Key: VPHSUBDrm: [ 0.00 0.00 ] +Key: VPHSUBDrr: [ 0.00 0.00 ] +Key: VPHSUBSWYrm: [ 0.00 0.00 ] +Key: VPHSUBSWYrr: [ 0.00 0.00 ] +Key: VPHSUBSWrm: [ 0.00 0.00 ] +Key: VPHSUBSWrr: [ 0.00 0.00 ] +Key: VPHSUBWDrm: [ 0.00 0.00 ] +Key: VPHSUBWDrr: [ 0.00 0.00 ] +Key: VPHSUBWYrm: [ 0.00 0.00 ] +Key: VPHSUBWYrr: [ 0.00 0.00 ] +Key: VPHSUBWrm: [ 0.00 0.00 ] +Key: VPHSUBWrr: [ 0.00 0.00 ] +Key: VPINSRBZrmi: [ 0.00 0.00 ] +Key: VPINSRBZrri: [ 0.00 0.00 ] +Key: VPINSRBrmi: [ 0.00 0.00 ] +Key: VPINSRBrri: [ 0.00 0.00 ] +Key: VPINSRDZrmi: [ 0.00 0.00 ] +Key: VPINSRDZrri: [ 0.00 0.00 ] +Key: VPINSRDrmi: [ 0.00 0.00 ] +Key: VPINSRDrri: [ 0.00 0.00 ] +Key: VPINSRQZrmi: [ 0.00 0.00 ] +Key: VPINSRQZrri: [ 0.00 0.00 ] +Key: VPINSRQrmi: [ 0.00 0.00 ] +Key: VPINSRQrri: [ 0.00 0.00 ] +Key: VPINSRWZrmi: [ 0.00 0.00 ] +Key: VPINSRWZrri: [ 0.00 0.00 ] +Key: VPINSRWrmi: [ 0.00 0.00 ] +Key: VPINSRWrri: [ 0.00 0.00 ] +Key: VPLZCNTDZ: [ 0.00 0.00 ] +Key: VPLZCNTDZrm: [ 0.00 0.00 ] +Key: VPLZCNTDZrmb: [ 0.00 0.00 ] +Key: VPLZCNTDZrmbk: [ 0.00 0.00 ] +Key: VPLZCNTDZrmbkz: [ 0.00 0.00 ] +Key: VPLZCNTDZrmk: [ 0.00 0.00 ] +Key: VPLZCNTDZrmkz: [ 0.00 0.00 ] +Key: VPLZCNTDZrr: [ 0.00 0.00 ] +Key: VPLZCNTDZrrk: [ 0.00 0.00 ] +Key: VPLZCNTDZrrkz: [ 0.00 0.00 ] +Key: VPLZCNTQZ: [ 0.00 0.00 ] +Key: VPLZCNTQZrm: [ 0.00 0.00 ] +Key: VPLZCNTQZrmb: [ 0.00 0.00 ] +Key: VPLZCNTQZrmbk: [ 0.00 0.00 ] +Key: VPLZCNTQZrmbkz: [ 0.00 0.00 ] +Key: VPLZCNTQZrmk: [ 0.00 0.00 ] +Key: VPLZCNTQZrmkz: [ 0.00 0.00 ] +Key: VPLZCNTQZrr: [ 0.00 0.00 ] +Key: VPLZCNTQZrrk: [ 0.00 0.00 ] +Key: VPLZCNTQZrrkz: [ 0.00 0.00 ] +Key: VPMACSDDrm: [ 0.00 0.00 ] +Key: VPMACSDDrr: [ 0.00 0.00 ] +Key: VPMACSDQHrm: [ 0.00 0.00 ] +Key: VPMACSDQHrr: [ 0.00 0.00 ] +Key: VPMACSDQLrm: [ 0.00 0.00 ] +Key: VPMACSDQLrr: [ 0.00 0.00 ] +Key: VPMACSSDDrm: [ 0.00 0.00 ] +Key: VPMACSSDDrr: [ 0.00 0.00 ] +Key: VPMACSSDQHrm: [ 0.00 0.00 ] +Key: VPMACSSDQHrr: [ 0.00 0.00 ] +Key: VPMACSSDQLrm: [ 0.00 0.00 ] +Key: VPMACSSDQLrr: [ 0.00 0.00 ] +Key: VPMACSSWDrm: [ 0.00 0.00 ] +Key: VPMACSSWDrr: [ 0.00 0.00 ] +Key: VPMACSSWWrm: [ 0.00 0.00 ] +Key: VPMACSSWWrr: [ 0.00 0.00 ] +Key: VPMACSWDrm: [ 0.00 0.00 ] +Key: VPMACSWDrr: [ 0.00 0.00 ] +Key: VPMACSWWrm: [ 0.00 0.00 ] +Key: VPMACSWWrr: [ 0.00 0.00 ] +Key: VPMADCSSWDrm: [ 0.00 0.00 ] +Key: VPMADCSSWDrr: [ 0.00 0.00 ] +Key: VPMADCSWDrm: [ 0.00 0.00 ] +Key: VPMADCSWDrr: [ 0.00 0.00 ] +Key: VPMADD: [ 0.00 0.00 ] +Key: VPMADDUBSWYrm: [ 0.00 0.00 ] +Key: VPMADDUBSWYrr: [ 0.00 0.00 ] +Key: VPMADDUBSWZ: [ 0.00 0.00 ] +Key: VPMADDUBSWZrm: [ 0.00 0.00 ] +Key: VPMADDUBSWZrmk: [ 0.00 0.00 ] +Key: VPMADDUBSWZrmkz: [ 0.00 0.00 ] +Key: VPMADDUBSWZrr: [ 0.00 0.00 ] +Key: VPMADDUBSWZrrk: [ 0.00 0.00 ] +Key: VPMADDUBSWZrrkz: [ 0.00 0.00 ] +Key: VPMADDUBSWrm: [ 0.00 0.00 ] +Key: VPMADDUBSWrr: [ 0.00 0.00 ] +Key: VPMADDWDYrm: [ 0.00 0.00 ] +Key: VPMADDWDYrr: [ 0.00 0.00 ] +Key: VPMADDWDZ: [ 0.00 0.00 ] +Key: VPMADDWDZrm: [ 0.00 0.00 ] +Key: VPMADDWDZrmk: [ 0.00 0.00 ] +Key: VPMADDWDZrmkz: [ 0.00 0.00 ] +Key: VPMADDWDZrr: [ 0.00 0.00 ] +Key: VPMADDWDZrrk: [ 0.00 0.00 ] +Key: VPMADDWDZrrkz: [ 0.00 0.00 ] +Key: VPMADDWDrm: [ 0.00 0.00 ] +Key: VPMADDWDrr: [ 0.00 0.00 ] +Key: VPMASKMOVDYmr: [ 0.00 0.00 ] +Key: VPMASKMOVDYrm: [ 0.00 0.00 ] +Key: VPMASKMOVDmr: [ 0.00 0.00 ] +Key: VPMASKMOVDrm: [ 0.00 0.00 ] +Key: VPMASKMOVQYmr: [ 0.00 0.00 ] +Key: VPMASKMOVQYrm: [ 0.00 0.00 ] +Key: VPMASKMOVQmr: [ 0.00 0.00 ] +Key: VPMASKMOVQrm: [ 0.00 0.00 ] +Key: VPMAXSBYrm: [ 0.00 0.00 ] +Key: VPMAXSBYrr: [ 0.00 0.00 ] +Key: VPMAXSBZ: [ 0.00 0.00 ] +Key: VPMAXSBZrm: [ 0.00 0.00 ] +Key: VPMAXSBZrmk: [ 0.00 0.00 ] +Key: VPMAXSBZrmkz: [ 0.00 0.00 ] +Key: VPMAXSBZrr: [ 0.00 0.00 ] +Key: VPMAXSBZrrk: [ 0.00 0.00 ] +Key: VPMAXSBZrrkz: [ 0.00 0.00 ] +Key: VPMAXSBrm: [ 0.00 0.00 ] +Key: VPMAXSBrr: [ 0.00 0.00 ] +Key: VPMAXSDYrm: [ 0.00 0.00 ] +Key: VPMAXSDYrr: [ 0.00 0.00 ] +Key: VPMAXSDZ: [ 0.00 0.00 ] +Key: VPMAXSDZrm: [ 0.00 0.00 ] +Key: VPMAXSDZrmb: [ 0.00 0.00 ] +Key: VPMAXSDZrmbk: [ 0.00 0.00 ] +Key: VPMAXSDZrmbkz: [ 0.00 0.00 ] +Key: VPMAXSDZrmk: [ 0.00 0.00 ] +Key: VPMAXSDZrmkz: [ 0.00 0.00 ] +Key: VPMAXSDZrr: [ 0.00 0.00 ] +Key: VPMAXSDZrrk: [ 0.00 0.00 ] +Key: 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VPMOVUSDBZrr: [ 0.00 0.00 ] +Key: VPMOVUSDBZrrk: [ 0.00 0.00 ] +Key: VPMOVUSDBZrrkz: [ 0.00 0.00 ] +Key: VPMOVUSDWZ: [ 0.00 0.00 ] +Key: VPMOVUSDWZmr: [ 0.00 0.00 ] +Key: VPMOVUSDWZmrk: [ 0.00 0.00 ] +Key: VPMOVUSDWZrr: [ 0.00 0.00 ] +Key: VPMOVUSDWZrrk: [ 0.00 0.00 ] +Key: VPMOVUSDWZrrkz: [ 0.00 0.00 ] +Key: VPMOVUSQBZ: [ 0.00 0.00 ] +Key: VPMOVUSQBZmr: [ 0.00 0.00 ] +Key: VPMOVUSQBZmrk: [ 0.00 0.00 ] +Key: VPMOVUSQBZrr: [ 0.00 0.00 ] +Key: VPMOVUSQBZrrk: [ 0.00 0.00 ] +Key: VPMOVUSQBZrrkz: [ 0.00 0.00 ] +Key: VPMOVUSQDZ: [ 0.00 0.00 ] +Key: VPMOVUSQDZmr: [ 0.00 0.00 ] +Key: VPMOVUSQDZmrk: [ 0.00 0.00 ] +Key: VPMOVUSQDZrr: [ 0.00 0.00 ] +Key: VPMOVUSQDZrrk: [ 0.00 0.00 ] +Key: VPMOVUSQDZrrkz: [ 0.00 0.00 ] +Key: VPMOVUSQWZ: [ 0.00 0.00 ] +Key: VPMOVUSQWZmr: [ 0.00 0.00 ] +Key: VPMOVUSQWZmrk: [ 0.00 0.00 ] +Key: VPMOVUSQWZrr: [ 0.00 0.00 ] +Key: VPMOVUSQWZrrk: [ 0.00 0.00 ] +Key: VPMOVUSQWZrrkz: [ 0.00 0.00 ] +Key: VPMOVUSWBZ: [ 0.00 0.00 ] +Key: VPMOVUSWBZmr: [ 0.00 0.00 ] +Key: VPMOVUSWBZmrk: [ 0.00 0.00 ] +Key: VPMOVUSWBZrr: [ 0.00 0.00 ] +Key: VPMOVUSWBZrrk: [ 0.00 0.00 ] +Key: VPMOVUSWBZrrkz: [ 0.00 0.00 ] +Key: VPMOVW: [ 0.00 0.00 ] +Key: VPMOVWBZ: [ 0.00 0.00 ] +Key: VPMOVWBZmr: [ 0.00 0.00 ] +Key: VPMOVWBZmrk: [ 0.00 0.00 ] +Key: VPMOVWBZrr: [ 0.00 0.00 ] +Key: VPMOVWBZrrk: [ 0.00 0.00 ] +Key: VPMOVWBZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXBDYrm: [ 0.00 0.00 ] +Key: VPMOVZXBDYrr: [ 0.00 0.00 ] +Key: VPMOVZXBDZ: [ 0.00 0.00 ] +Key: VPMOVZXBDZrm: [ 0.00 0.00 ] +Key: VPMOVZXBDZrmk: [ 0.00 0.00 ] +Key: VPMOVZXBDZrmkz: [ 0.00 0.00 ] +Key: VPMOVZXBDZrr: [ 0.00 0.00 ] +Key: VPMOVZXBDZrrk: [ 0.00 0.00 ] +Key: VPMOVZXBDZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXBDrm: [ 0.00 0.00 ] +Key: VPMOVZXBDrr: [ 0.00 0.00 ] +Key: VPMOVZXBQYrm: [ 0.00 0.00 ] +Key: VPMOVZXBQYrr: [ 0.00 0.00 ] +Key: VPMOVZXBQZ: [ 0.00 0.00 ] +Key: VPMOVZXBQZrm: [ 0.00 0.00 ] +Key: VPMOVZXBQZrmk: [ 0.00 0.00 ] +Key: VPMOVZXBQZrmkz: [ 0.00 0.00 ] +Key: VPMOVZXBQZrr: [ 0.00 0.00 ] +Key: VPMOVZXBQZrrk: [ 0.00 0.00 ] +Key: VPMOVZXBQZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXBQrm: [ 0.00 0.00 ] +Key: VPMOVZXBQrr: [ 0.00 0.00 ] +Key: VPMOVZXBWYrm: [ 0.00 0.00 ] +Key: VPMOVZXBWYrr: [ 0.00 0.00 ] +Key: VPMOVZXBWZ: [ 0.00 0.00 ] +Key: VPMOVZXBWZrm: [ 0.00 0.00 ] +Key: VPMOVZXBWZrmk: [ 0.00 0.00 ] +Key: VPMOVZXBWZrmkz: [ 0.00 0.00 ] +Key: VPMOVZXBWZrr: [ 0.00 0.00 ] +Key: VPMOVZXBWZrrk: [ 0.00 0.00 ] +Key: VPMOVZXBWZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXBWrm: [ 0.00 0.00 ] +Key: VPMOVZXBWrr: [ 0.00 0.00 ] +Key: VPMOVZXDQYrm: [ 0.00 0.00 ] +Key: VPMOVZXDQYrr: [ 0.00 0.00 ] +Key: VPMOVZXDQZ: [ 0.00 0.00 ] +Key: VPMOVZXDQZrm: [ 0.00 0.00 ] +Key: VPMOVZXDQZrmk: [ 0.00 0.00 ] +Key: VPMOVZXDQZrmkz: [ 0.00 0.00 ] +Key: VPMOVZXDQZrr: [ 0.00 0.00 ] +Key: VPMOVZXDQZrrk: [ 0.00 0.00 ] +Key: VPMOVZXDQZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXDQrm: [ 0.00 0.00 ] +Key: VPMOVZXDQrr: [ 0.00 0.00 ] +Key: VPMOVZXWDYrm: [ 0.00 0.00 ] +Key: VPMOVZXWDYrr: [ 0.00 0.00 ] +Key: VPMOVZXWDZ: [ 0.00 0.00 ] +Key: VPMOVZXWDZrm: [ 0.00 0.00 ] +Key: VPMOVZXWDZrmk: [ 0.00 0.00 ] +Key: VPMOVZXWDZrmkz: [ 0.00 0.00 ] +Key: VPMOVZXWDZrr: [ 0.00 0.00 ] +Key: VPMOVZXWDZrrk: [ 0.00 0.00 ] +Key: VPMOVZXWDZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXWDrm: [ 0.00 0.00 ] +Key: VPMOVZXWDrr: [ 0.00 0.00 ] +Key: VPMOVZXWQYrm: [ 0.00 0.00 ] +Key: VPMOVZXWQYrr: [ 0.00 0.00 ] +Key: VPMOVZXWQZ: [ 0.00 0.00 ] +Key: VPMOVZXWQZrm: [ 0.00 0.00 ] +Key: VPMOVZXWQZrmk: [ 0.00 0.00 ] +Key: VPMOVZXWQZrmkz: [ 0.00 0.00 ] +Key: VPMOVZXWQZrr: [ 0.00 0.00 ] +Key: VPMOVZXWQZrrk: [ 0.00 0.00 ] +Key: VPMOVZXWQZrrkz: [ 0.00 0.00 ] +Key: VPMOVZXWQrm: [ 0.00 0.00 ] +Key: VPMOVZXWQrr: [ 0.00 0.00 ] +Key: VPMULDQYrm: [ 0.00 0.00 ] +Key: VPMULDQYrr: [ 0.00 0.00 ] +Key: VPMULDQZ: [ 0.00 0.00 ] +Key: VPMULDQZrm: [ 0.00 0.00 ] +Key: VPMULDQZrmb: [ 0.00 0.00 ] +Key: VPMULDQZrmbk: [ 0.00 0.00 ] +Key: VPMULDQZrmbkz: [ 0.00 0.00 ] +Key: VPMULDQZrmk: [ 0.00 0.00 ] +Key: VPMULDQZrmkz: [ 0.00 0.00 ] +Key: VPMULDQZrr: [ 0.00 0.00 ] +Key: VPMULDQZrrk: [ 0.00 0.00 ] +Key: VPMULDQZrrkz: [ 0.00 0.00 ] +Key: VPMULDQrm: [ 0.00 0.00 ] +Key: VPMULDQrr: [ 0.00 0.00 ] +Key: VPMULHRSWYrm: [ 0.00 0.00 ] +Key: VPMULHRSWYrr: [ 0.00 0.00 ] +Key: VPMULHRSWZ: [ 0.00 0.00 ] +Key: VPMULHRSWZrm: [ 0.00 0.00 ] +Key: VPMULHRSWZrmk: [ 0.00 0.00 ] +Key: VPMULHRSWZrmkz: [ 0.00 0.00 ] +Key: VPMULHRSWZrr: [ 0.00 0.00 ] +Key: VPMULHRSWZrrk: [ 0.00 0.00 ] +Key: VPMULHRSWZrrkz: [ 0.00 0.00 ] +Key: VPMULHRSWrm: [ 0.00 0.00 ] +Key: VPMULHRSWrr: [ 0.00 0.00 ] +Key: VPMULHUWYrm: [ 0.00 0.00 ] +Key: VPMULHUWYrr: [ 0.00 0.00 ] +Key: VPMULHUWZ: [ 0.00 0.00 ] +Key: VPMULHUWZrm: [ 0.00 0.00 ] +Key: VPMULHUWZrmk: [ 0.00 0.00 ] +Key: VPMULHUWZrmkz: [ 0.00 0.00 ] +Key: VPMULHUWZrr: [ 0.00 0.00 ] +Key: VPMULHUWZrrk: [ 0.00 0.00 ] +Key: VPMULHUWZrrkz: [ 0.00 0.00 ] +Key: VPMULHUWrm: [ 0.00 0.00 ] +Key: VPMULHUWrr: [ 0.00 0.00 ] +Key: VPMULHWYrm: [ 0.00 0.00 ] +Key: VPMULHWYrr: [ 0.00 0.00 ] +Key: VPMULHWZ: [ 0.00 0.00 ] +Key: VPMULHWZrm: [ 0.00 0.00 ] +Key: VPMULHWZrmk: [ 0.00 0.00 ] +Key: VPMULHWZrmkz: [ 0.00 0.00 ] +Key: VPMULHWZrr: [ 0.00 0.00 ] +Key: VPMULHWZrrk: [ 0.00 0.00 ] +Key: VPMULHWZrrkz: [ 0.00 0.00 ] +Key: VPMULHWrm: [ 0.00 0.00 ] +Key: VPMULHWrr: [ 0.00 0.00 ] +Key: VPMULLDYrm: [ 0.00 0.00 ] +Key: VPMULLDYrr: [ 0.00 0.00 ] +Key: VPMULLDZ: [ 0.00 0.00 ] +Key: VPMULLDZrm: [ 0.00 0.00 ] +Key: VPMULLDZrmb: [ 0.00 0.00 ] +Key: VPMULLDZrmbk: [ 0.00 0.00 ] +Key: VPMULLDZrmbkz: [ 0.00 0.00 ] +Key: VPMULLDZrmk: [ 0.00 0.00 ] +Key: VPMULLDZrmkz: [ 0.00 0.00 ] +Key: VPMULLDZrr: [ 0.00 0.00 ] +Key: VPMULLDZrrk: [ 0.00 0.00 ] +Key: VPMULLDZrrkz: [ 0.00 0.00 ] +Key: VPMULLDrm: [ 0.00 0.00 ] +Key: VPMULLDrr: [ 0.00 0.00 ] +Key: VPMULLQZ: [ 0.00 0.00 ] +Key: VPMULLQZrm: [ 0.00 0.00 ] +Key: VPMULLQZrmb: [ 0.00 0.00 ] +Key: VPMULLQZrmbk: [ 0.00 0.00 ] +Key: VPMULLQZrmbkz: [ 0.00 0.00 ] +Key: VPMULLQZrmk: [ 0.00 0.00 ] +Key: VPMULLQZrmkz: [ 0.00 0.00 ] +Key: VPMULLQZrr: [ 0.00 0.00 ] +Key: VPMULLQZrrk: [ 0.00 0.00 ] +Key: VPMULLQZrrkz: [ 0.00 0.00 ] +Key: VPMULLWYrm: [ 0.00 0.00 ] +Key: VPMULLWYrr: [ 0.00 0.00 ] +Key: VPMULLWZ: [ 0.00 0.00 ] +Key: VPMULLWZrm: [ 0.00 0.00 ] +Key: VPMULLWZrmk: [ 0.00 0.00 ] +Key: VPMULLWZrmkz: [ 0.00 0.00 ] +Key: VPMULLWZrr: [ 0.00 0.00 ] +Key: VPMULLWZrrk: [ 0.00 0.00 ] +Key: VPMULLWZrrkz: [ 0.00 0.00 ] +Key: VPMULLWrm: [ 0.00 0.00 ] +Key: VPMULLWrr: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZ: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrm: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrmb: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrmbk: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrmbkz: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrmk: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrmkz: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrr: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrrk: [ 0.00 0.00 ] +Key: VPMULTISHIFTQBZrrkz: [ 0.00 0.00 ] +Key: VPMULUDQYrm: [ 0.00 0.00 ] +Key: VPMULUDQYrr: [ 0.00 0.00 ] +Key: VPMULUDQZ: [ 0.00 0.00 ] +Key: VPMULUDQZrm: [ 0.00 0.00 ] +Key: VPMULUDQZrmb: [ 0.00 0.00 ] +Key: VPMULUDQZrmbk: [ 0.00 0.00 ] +Key: VPMULUDQZrmbkz: [ 0.00 0.00 ] +Key: VPMULUDQZrmk: [ 0.00 0.00 ] +Key: VPMULUDQZrmkz: [ 0.00 0.00 ] +Key: VPMULUDQZrr: [ 0.00 0.00 ] +Key: VPMULUDQZrrk: [ 0.00 0.00 ] +Key: VPMULUDQZrrkz: [ 0.00 0.00 ] +Key: VPMULUDQrm: [ 0.00 0.00 ] +Key: VPMULUDQrr: [ 0.00 0.00 ] +Key: VPOPCNTBZ: [ 0.00 0.00 ] +Key: VPOPCNTBZrm: [ 0.00 0.00 ] +Key: VPOPCNTBZrmk: [ 0.00 0.00 ] +Key: VPOPCNTBZrmkz: [ 0.00 0.00 ] +Key: VPOPCNTBZrr: [ 0.00 0.00 ] +Key: VPOPCNTBZrrk: [ 0.00 0.00 ] +Key: VPOPCNTBZrrkz: [ 0.00 0.00 ] +Key: VPOPCNTDZ: [ 0.00 0.00 ] +Key: VPOPCNTDZrm: [ 0.00 0.00 ] +Key: VPOPCNTDZrmb: [ 0.00 0.00 ] +Key: VPOPCNTDZrmbk: [ 0.00 0.00 ] +Key: VPOPCNTDZrmbkz: [ 0.00 0.00 ] +Key: VPOPCNTDZrmk: [ 0.00 0.00 ] +Key: VPOPCNTDZrmkz: [ 0.00 0.00 ] +Key: VPOPCNTDZrr: [ 0.00 0.00 ] +Key: VPOPCNTDZrrk: [ 0.00 0.00 ] +Key: VPOPCNTDZrrkz: [ 0.00 0.00 ] +Key: VPOPCNTQZ: [ 0.00 0.00 ] +Key: VPOPCNTQZrm: [ 0.00 0.00 ] +Key: VPOPCNTQZrmb: [ 0.00 0.00 ] +Key: VPOPCNTQZrmbk: [ 0.00 0.00 ] +Key: VPOPCNTQZrmbkz: [ 0.00 0.00 ] +Key: VPOPCNTQZrmk: [ 0.00 0.00 ] +Key: VPOPCNTQZrmkz: [ 0.00 0.00 ] +Key: VPOPCNTQZrr: [ 0.00 0.00 ] +Key: VPOPCNTQZrrk: [ 0.00 0.00 ] +Key: VPOPCNTQZrrkz: [ 0.00 0.00 ] +Key: VPOPCNTWZ: [ 0.00 0.00 ] +Key: VPOPCNTWZrm: [ 0.00 0.00 ] +Key: VPOPCNTWZrmk: [ 0.00 0.00 ] +Key: VPOPCNTWZrmkz: [ 0.00 0.00 ] +Key: VPOPCNTWZrr: [ 0.00 0.00 ] +Key: VPOPCNTWZrrk: [ 0.00 0.00 ] +Key: VPOPCNTWZrrkz: [ 0.00 0.00 ] +Key: VPORDZ: [ 0.00 0.00 ] +Key: VPORDZrm: [ 0.00 0.00 ] +Key: VPORDZrmb: [ 0.00 0.00 ] +Key: VPORDZrmbk: [ 0.00 0.00 ] +Key: VPORDZrmbkz: [ 0.00 0.00 ] +Key: VPORDZrmk: [ 0.00 0.00 ] +Key: VPORDZrmkz: [ 0.00 0.00 ] +Key: VPORDZrr: [ 0.00 0.00 ] +Key: VPORDZrrk: [ 0.00 0.00 ] +Key: VPORDZrrkz: [ 0.00 0.00 ] +Key: VPORQZ: [ 0.00 0.00 ] +Key: VPORQZrm: [ 0.00 0.00 ] +Key: VPORQZrmb: [ 0.00 0.00 ] +Key: VPORQZrmbk: [ 0.00 0.00 ] +Key: VPORQZrmbkz: [ 0.00 0.00 ] +Key: VPORQZrmk: [ 0.00 0.00 ] +Key: VPORQZrmkz: [ 0.00 0.00 ] +Key: VPORQZrr: [ 0.00 0.00 ] +Key: VPORQZrrk: [ 0.00 0.00 ] +Key: VPORQZrrkz: [ 0.00 0.00 ] +Key: VPORYrm: [ 0.00 0.00 ] +Key: VPORYrr: [ 0.00 0.00 ] +Key: VPORrm: [ 0.00 0.00 ] +Key: VPORrr: [ 0.00 0.00 ] +Key: VPPERMrmr: [ 0.00 0.00 ] +Key: VPPERMrrm: [ 0.00 0.00 ] +Key: VPPERMrrr: [ 0.00 0.00 ] +Key: VPPERMrrr_REV: [ 0.00 0.00 ] +Key: VPROLDZ: [ 0.00 0.00 ] +Key: VPROLDZmbi: [ 0.00 0.00 ] +Key: VPROLDZmbik: [ 0.00 0.00 ] +Key: VPROLDZmbikz: [ 0.00 0.00 ] +Key: VPROLDZmi: [ 0.00 0.00 ] +Key: VPROLDZmik: [ 0.00 0.00 ] +Key: VPROLDZmikz: [ 0.00 0.00 ] +Key: VPROLDZri: [ 0.00 0.00 ] +Key: VPROLDZrik: [ 0.00 0.00 ] +Key: VPROLDZrikz: [ 0.00 0.00 ] +Key: VPROLQZ: [ 0.00 0.00 ] +Key: VPROLQZmbi: [ 0.00 0.00 ] +Key: VPROLQZmbik: [ 0.00 0.00 ] +Key: VPROLQZmbikz: [ 0.00 0.00 ] +Key: VPROLQZmi: [ 0.00 0.00 ] +Key: VPROLQZmik: [ 0.00 0.00 ] +Key: VPROLQZmikz: [ 0.00 0.00 ] +Key: VPROLQZri: [ 0.00 0.00 ] +Key: VPROLQZrik: [ 0.00 0.00 ] +Key: VPROLQZrikz: [ 0.00 0.00 ] +Key: VPROLVDZ: [ 0.00 0.00 ] +Key: VPROLVDZrm: [ 0.00 0.00 ] +Key: VPROLVDZrmb: [ 0.00 0.00 ] +Key: VPROLVDZrmbk: [ 0.00 0.00 ] +Key: VPROLVDZrmbkz: [ 0.00 0.00 ] +Key: VPROLVDZrmk: [ 0.00 0.00 ] +Key: VPROLVDZrmkz: [ 0.00 0.00 ] +Key: VPROLVDZrr: [ 0.00 0.00 ] +Key: VPROLVDZrrk: [ 0.00 0.00 ] +Key: VPROLVDZrrkz: [ 0.00 0.00 ] +Key: VPROLVQZ: [ 0.00 0.00 ] +Key: VPROLVQZrm: [ 0.00 0.00 ] +Key: VPROLVQZrmb: [ 0.00 0.00 ] +Key: VPROLVQZrmbk: [ 0.00 0.00 ] +Key: VPROLVQZrmbkz: [ 0.00 0.00 ] +Key: VPROLVQZrmk: [ 0.00 0.00 ] +Key: VPROLVQZrmkz: [ 0.00 0.00 ] +Key: VPROLVQZrr: [ 0.00 0.00 ] +Key: VPROLVQZrrk: [ 0.00 0.00 ] +Key: VPROLVQZrrkz: [ 0.00 0.00 ] +Key: VPRORDZ: [ 0.00 0.00 ] +Key: VPRORDZmbi: [ 0.00 0.00 ] +Key: VPRORDZmbik: [ 0.00 0.00 ] +Key: VPRORDZmbikz: [ 0.00 0.00 ] +Key: VPRORDZmi: [ 0.00 0.00 ] +Key: VPRORDZmik: [ 0.00 0.00 ] +Key: VPRORDZmikz: [ 0.00 0.00 ] +Key: VPRORDZri: [ 0.00 0.00 ] +Key: VPRORDZrik: [ 0.00 0.00 ] +Key: VPRORDZrikz: [ 0.00 0.00 ] +Key: VPRORQZ: [ 0.00 0.00 ] +Key: VPRORQZmbi: [ 0.00 0.00 ] +Key: VPRORQZmbik: [ 0.00 0.00 ] +Key: VPRORQZmbikz: [ 0.00 0.00 ] +Key: VPRORQZmi: [ 0.00 0.00 ] +Key: VPRORQZmik: [ 0.00 0.00 ] +Key: VPRORQZmikz: [ 0.00 0.00 ] +Key: VPRORQZri: [ 0.00 0.00 ] +Key: VPRORQZrik: [ 0.00 0.00 ] +Key: VPRORQZrikz: [ 0.00 0.00 ] +Key: VPRORVDZ: [ 0.00 0.00 ] +Key: VPRORVDZrm: [ 0.00 0.00 ] +Key: VPRORVDZrmb: [ 0.00 0.00 ] +Key: VPRORVDZrmbk: [ 0.00 0.00 ] +Key: VPRORVDZrmbkz: [ 0.00 0.00 ] +Key: VPRORVDZrmk: [ 0.00 0.00 ] +Key: VPRORVDZrmkz: [ 0.00 0.00 ] +Key: VPRORVDZrr: [ 0.00 0.00 ] +Key: VPRORVDZrrk: [ 0.00 0.00 ] +Key: VPRORVDZrrkz: [ 0.00 0.00 ] +Key: VPRORVQZ: [ 0.00 0.00 ] +Key: VPRORVQZrm: [ 0.00 0.00 ] +Key: VPRORVQZrmb: [ 0.00 0.00 ] +Key: VPRORVQZrmbk: [ 0.00 0.00 ] +Key: VPRORVQZrmbkz: [ 0.00 0.00 ] +Key: VPRORVQZrmk: [ 0.00 0.00 ] +Key: VPRORVQZrmkz: [ 0.00 0.00 ] +Key: VPRORVQZrr: [ 0.00 0.00 ] +Key: VPRORVQZrrk: [ 0.00 0.00 ] +Key: VPRORVQZrrkz: [ 0.00 0.00 ] +Key: VPROTBmi: [ 0.00 0.00 ] +Key: VPROTBmr: [ 0.00 0.00 ] +Key: VPROTBri: [ 0.00 0.00 ] +Key: VPROTBrm: [ 0.00 0.00 ] +Key: VPROTBrr: [ 0.00 0.00 ] +Key: VPROTBrr_REV: [ 0.00 0.00 ] +Key: VPROTDmi: [ 0.00 0.00 ] +Key: VPROTDmr: [ 0.00 0.00 ] +Key: VPROTDri: [ 0.00 0.00 ] +Key: VPROTDrm: [ 0.00 0.00 ] +Key: VPROTDrr: [ 0.00 0.00 ] +Key: VPROTDrr_REV: [ 0.00 0.00 ] +Key: VPROTQmi: [ 0.00 0.00 ] +Key: VPROTQmr: [ 0.00 0.00 ] +Key: VPROTQri: [ 0.00 0.00 ] +Key: VPROTQrm: [ 0.00 0.00 ] +Key: VPROTQrr: [ 0.00 0.00 ] +Key: VPROTQrr_REV: [ 0.00 0.00 ] +Key: VPROTWmi: [ 0.00 0.00 ] +Key: VPROTWmr: [ 0.00 0.00 ] +Key: VPROTWri: [ 0.00 0.00 ] +Key: VPROTWrm: [ 0.00 0.00 ] +Key: VPROTWrr: [ 0.00 0.00 ] +Key: VPROTWrr_REV: [ 0.00 0.00 ] +Key: VPSADBWYrm: [ 0.00 0.00 ] +Key: VPSADBWYrr: [ 0.00 0.00 ] +Key: VPSADBWZ: [ 0.00 0.00 ] +Key: VPSADBWZrm: [ 0.00 0.00 ] +Key: VPSADBWZrr: [ 0.00 0.00 ] +Key: VPSADBWrm: [ 0.00 0.00 ] +Key: VPSADBWrr: [ 0.00 0.00 ] +Key: VPSCATTERDDZ: [ 0.00 0.00 ] +Key: VPSCATTERDDZmr: [ 0.00 0.00 ] +Key: VPSCATTERDQZ: [ 0.00 0.00 ] +Key: VPSCATTERDQZmr: [ 0.00 0.00 ] +Key: VPSCATTERQDZ: [ 0.00 0.00 ] +Key: VPSCATTERQDZmr: [ 0.00 0.00 ] +Key: VPSCATTERQQZ: [ 0.00 0.00 ] +Key: VPSCATTERQQZmr: [ 0.00 0.00 ] +Key: VPSHABmr: [ 0.00 0.00 ] +Key: VPSHABrm: [ 0.00 0.00 ] +Key: VPSHABrr: [ 0.00 0.00 ] +Key: VPSHABrr_REV: [ 0.00 0.00 ] +Key: VPSHADmr: [ 0.00 0.00 ] +Key: VPSHADrm: [ 0.00 0.00 ] +Key: VPSHADrr: [ 0.00 0.00 ] +Key: VPSHADrr_REV: [ 0.00 0.00 ] +Key: VPSHAQmr: [ 0.00 0.00 ] +Key: VPSHAQrm: [ 0.00 0.00 ] +Key: VPSHAQrr: [ 0.00 0.00 ] +Key: VPSHAQrr_REV: [ 0.00 0.00 ] +Key: VPSHAWmr: [ 0.00 0.00 ] +Key: VPSHAWrm: [ 0.00 0.00 ] +Key: VPSHAWrr: [ 0.00 0.00 ] +Key: VPSHAWrr_REV: [ 0.00 0.00 ] +Key: VPSHLBmr: [ 0.00 0.00 ] +Key: VPSHLBrm: [ 0.00 0.00 ] +Key: VPSHLBrr: [ 0.00 0.00 ] +Key: VPSHLBrr_REV: [ 0.00 0.00 ] +Key: VPSHLDDZ: [ 0.00 0.00 ] +Key: VPSHLDDZrmbi: [ 0.00 0.00 ] +Key: VPSHLDDZrmbik: [ 0.00 0.00 ] +Key: VPSHLDDZrmbikz: [ 0.00 0.00 ] +Key: VPSHLDDZrmi: [ 0.00 0.00 ] +Key: VPSHLDDZrmik: [ 0.00 0.00 ] +Key: VPSHLDDZrmikz: [ 0.00 0.00 ] +Key: VPSHLDDZrri: [ 0.00 0.00 ] +Key: VPSHLDDZrrik: [ 0.00 0.00 ] +Key: VPSHLDDZrrikz: [ 0.00 0.00 ] +Key: VPSHLDQZ: [ 0.00 0.00 ] +Key: VPSHLDQZrmbi: [ 0.00 0.00 ] +Key: VPSHLDQZrmbik: [ 0.00 0.00 ] +Key: VPSHLDQZrmbikz: [ 0.00 0.00 ] +Key: VPSHLDQZrmi: [ 0.00 0.00 ] +Key: VPSHLDQZrmik: [ 0.00 0.00 ] +Key: VPSHLDQZrmikz: [ 0.00 0.00 ] +Key: VPSHLDQZrri: [ 0.00 0.00 ] +Key: VPSHLDQZrrik: [ 0.00 0.00 ] +Key: VPSHLDQZrrikz: [ 0.00 0.00 ] +Key: VPSHLDVDZ: [ 0.00 0.00 ] +Key: VPSHLDVDZm: [ 0.00 0.00 ] +Key: VPSHLDVDZmb: [ 0.00 0.00 ] +Key: VPSHLDVDZmbk: [ 0.00 0.00 ] +Key: VPSHLDVDZmbkz: [ 0.00 0.00 ] +Key: VPSHLDVDZmk: [ 0.00 0.00 ] +Key: VPSHLDVDZmkz: [ 0.00 0.00 ] +Key: VPSHLDVDZr: [ 0.00 0.00 ] +Key: VPSHLDVDZrk: [ 0.00 0.00 ] +Key: VPSHLDVDZrkz: [ 0.00 0.00 ] +Key: VPSHLDVQZ: [ 0.00 0.00 ] +Key: VPSHLDVQZm: [ 0.00 0.00 ] +Key: VPSHLDVQZmb: [ 0.00 0.00 ] +Key: VPSHLDVQZmbk: [ 0.00 0.00 ] +Key: VPSHLDVQZmbkz: [ 0.00 0.00 ] +Key: VPSHLDVQZmk: [ 0.00 0.00 ] +Key: VPSHLDVQZmkz: [ 0.00 0.00 ] +Key: VPSHLDVQZr: [ 0.00 0.00 ] +Key: VPSHLDVQZrk: [ 0.00 0.00 ] +Key: VPSHLDVQZrkz: [ 0.00 0.00 ] +Key: VPSHLDVWZ: [ 0.00 0.00 ] +Key: VPSHLDVWZm: [ 0.00 0.00 ] +Key: VPSHLDVWZmk: [ 0.00 0.00 ] +Key: VPSHLDVWZmkz: [ 0.00 0.00 ] +Key: VPSHLDVWZr: [ 0.00 0.00 ] +Key: VPSHLDVWZrk: [ 0.00 0.00 ] +Key: VPSHLDVWZrkz: [ 0.00 0.00 ] +Key: VPSHLDWZ: [ 0.00 0.00 ] +Key: VPSHLDWZrmi: [ 0.00 0.00 ] +Key: VPSHLDWZrmik: [ 0.00 0.00 ] +Key: VPSHLDWZrmikz: [ 0.00 0.00 ] +Key: VPSHLDWZrri: [ 0.00 0.00 ] +Key: VPSHLDWZrrik: [ 0.00 0.00 ] +Key: VPSHLDWZrrikz: [ 0.00 0.00 ] +Key: VPSHLDmr: [ 0.00 0.00 ] +Key: VPSHLDrm: [ 0.00 0.00 ] +Key: VPSHLDrr: [ 0.00 0.00 ] +Key: VPSHLDrr_REV: [ 0.00 0.00 ] +Key: VPSHLQmr: [ 0.00 0.00 ] +Key: VPSHLQrm: [ 0.00 0.00 ] +Key: VPSHLQrr: [ 0.00 0.00 ] +Key: VPSHLQrr_REV: [ 0.00 0.00 ] +Key: VPSHLWmr: [ 0.00 0.00 ] +Key: VPSHLWrm: [ 0.00 0.00 ] +Key: VPSHLWrr: [ 0.00 0.00 ] +Key: VPSHLWrr_REV: [ 0.00 0.00 ] +Key: VPSHRDDZ: [ 0.00 0.00 ] +Key: VPSHRDDZrmbi: [ 0.00 0.00 ] +Key: VPSHRDDZrmbik: [ 0.00 0.00 ] +Key: VPSHRDDZrmbikz: [ 0.00 0.00 ] +Key: VPSHRDDZrmi: [ 0.00 0.00 ] +Key: VPSHRDDZrmik: [ 0.00 0.00 ] +Key: VPSHRDDZrmikz: [ 0.00 0.00 ] +Key: VPSHRDDZrri: [ 0.00 0.00 ] +Key: VPSHRDDZrrik: [ 0.00 0.00 ] +Key: VPSHRDDZrrikz: [ 0.00 0.00 ] +Key: VPSHRDQZ: [ 0.00 0.00 ] +Key: VPSHRDQZrmbi: [ 0.00 0.00 ] +Key: VPSHRDQZrmbik: [ 0.00 0.00 ] +Key: VPSHRDQZrmbikz: [ 0.00 0.00 ] +Key: VPSHRDQZrmi: [ 0.00 0.00 ] +Key: VPSHRDQZrmik: [ 0.00 0.00 ] +Key: VPSHRDQZrmikz: [ 0.00 0.00 ] +Key: VPSHRDQZrri: [ 0.00 0.00 ] +Key: VPSHRDQZrrik: [ 0.00 0.00 ] +Key: VPSHRDQZrrikz: [ 0.00 0.00 ] +Key: VPSHRDVDZ: [ 0.00 0.00 ] +Key: VPSHRDVDZm: [ 0.00 0.00 ] +Key: VPSHRDVDZmb: [ 0.00 0.00 ] +Key: VPSHRDVDZmbk: [ 0.00 0.00 ] +Key: VPSHRDVDZmbkz: [ 0.00 0.00 ] +Key: VPSHRDVDZmk: [ 0.00 0.00 ] +Key: VPSHRDVDZmkz: [ 0.00 0.00 ] +Key: VPSHRDVDZr: [ 0.00 0.00 ] +Key: VPSHRDVDZrk: [ 0.00 0.00 ] +Key: VPSHRDVDZrkz: [ 0.00 0.00 ] +Key: VPSHRDVQZ: [ 0.00 0.00 ] +Key: VPSHRDVQZm: [ 0.00 0.00 ] +Key: VPSHRDVQZmb: [ 0.00 0.00 ] +Key: VPSHRDVQZmbk: [ 0.00 0.00 ] +Key: VPSHRDVQZmbkz: [ 0.00 0.00 ] +Key: VPSHRDVQZmk: [ 0.00 0.00 ] +Key: VPSHRDVQZmkz: [ 0.00 0.00 ] +Key: VPSHRDVQZr: [ 0.00 0.00 ] +Key: VPSHRDVQZrk: [ 0.00 0.00 ] +Key: VPSHRDVQZrkz: [ 0.00 0.00 ] +Key: VPSHRDVWZ: [ 0.00 0.00 ] +Key: VPSHRDVWZm: [ 0.00 0.00 ] +Key: VPSHRDVWZmk: [ 0.00 0.00 ] +Key: VPSHRDVWZmkz: [ 0.00 0.00 ] +Key: VPSHRDVWZr: [ 0.00 0.00 ] +Key: VPSHRDVWZrk: [ 0.00 0.00 ] +Key: VPSHRDVWZrkz: [ 0.00 0.00 ] +Key: VPSHRDWZ: [ 0.00 0.00 ] +Key: VPSHRDWZrmi: [ 0.00 0.00 ] +Key: VPSHRDWZrmik: [ 0.00 0.00 ] +Key: VPSHRDWZrmikz: [ 0.00 0.00 ] +Key: VPSHRDWZrri: [ 0.00 0.00 ] +Key: VPSHRDWZrrik: [ 0.00 0.00 ] +Key: VPSHRDWZrrikz: [ 0.00 0.00 ] +Key: VPSHUFBITQMBZ: [ 0.00 0.00 ] +Key: VPSHUFBITQMBZrm: [ 0.00 0.00 ] +Key: VPSHUFBITQMBZrmk: [ 0.00 0.00 ] +Key: VPSHUFBITQMBZrr: [ 0.00 0.00 ] +Key: VPSHUFBITQMBZrrk: [ 0.00 0.00 ] +Key: VPSHUFBYrm: [ 0.00 0.00 ] +Key: VPSHUFBYrr: [ 0.00 0.00 ] +Key: VPSHUFBZ: [ 0.00 0.00 ] +Key: VPSHUFBZrm: [ 0.00 0.00 ] +Key: VPSHUFBZrmk: [ 0.00 0.00 ] +Key: VPSHUFBZrmkz: [ 0.00 0.00 ] +Key: VPSHUFBZrr: [ 0.00 0.00 ] +Key: VPSHUFBZrrk: [ 0.00 0.00 ] +Key: VPSHUFBZrrkz: [ 0.00 0.00 ] +Key: VPSHUFBrm: [ 0.00 0.00 ] +Key: VPSHUFBrr: [ 0.00 0.00 ] +Key: VPSHUFDYmi: [ 0.00 0.00 ] +Key: VPSHUFDYri: [ 0.00 0.00 ] +Key: VPSHUFDZ: [ 0.00 0.00 ] +Key: VPSHUFDZmbi: [ 0.00 0.00 ] +Key: VPSHUFDZmbik: [ 0.00 0.00 ] +Key: VPSHUFDZmbikz: [ 0.00 0.00 ] +Key: VPSHUFDZmi: [ 0.00 0.00 ] +Key: VPSHUFDZmik: [ 0.00 0.00 ] +Key: VPSHUFDZmikz: [ 0.00 0.00 ] +Key: VPSHUFDZri: [ 0.00 0.00 ] +Key: VPSHUFDZrik: [ 0.00 0.00 ] +Key: VPSHUFDZrikz: [ 0.00 0.00 ] +Key: VPSHUFDmi: [ 0.00 0.00 ] +Key: VPSHUFDri: [ 0.00 0.00 ] +Key: VPSHUFHWYmi: [ 0.00 0.00 ] +Key: VPSHUFHWYri: [ 0.00 0.00 ] +Key: VPSHUFHWZ: [ 0.00 0.00 ] +Key: VPSHUFHWZmi: [ 0.00 0.00 ] +Key: VPSHUFHWZmik: [ 0.00 0.00 ] +Key: VPSHUFHWZmikz: [ 0.00 0.00 ] +Key: VPSHUFHWZri: [ 0.00 0.00 ] +Key: VPSHUFHWZrik: [ 0.00 0.00 ] +Key: VPSHUFHWZrikz: [ 0.00 0.00 ] +Key: VPSHUFHWmi: [ 0.00 0.00 ] +Key: VPSHUFHWri: [ 0.00 0.00 ] +Key: VPSHUFLWYmi: [ 0.00 0.00 ] +Key: VPSHUFLWYri: [ 0.00 0.00 ] +Key: VPSHUFLWZ: [ 0.00 0.00 ] +Key: VPSHUFLWZmi: [ 0.00 0.00 ] +Key: VPSHUFLWZmik: [ 0.00 0.00 ] +Key: VPSHUFLWZmikz: [ 0.00 0.00 ] +Key: VPSHUFLWZri: [ 0.00 0.00 ] +Key: VPSHUFLWZrik: [ 0.00 0.00 ] +Key: VPSHUFLWZrikz: [ 0.00 0.00 ] +Key: VPSHUFLWmi: [ 0.00 0.00 ] +Key: VPSHUFLWri: [ 0.00 0.00 ] +Key: VPSIGNBYrm: [ 0.00 0.00 ] +Key: VPSIGNBYrr: [ 0.00 0.00 ] +Key: VPSIGNBrm: [ 0.00 0.00 ] +Key: VPSIGNBrr: [ 0.00 0.00 ] +Key: VPSIGNDYrm: [ 0.00 0.00 ] +Key: VPSIGNDYrr: [ 0.00 0.00 ] +Key: VPSIGNDrm: [ 0.00 0.00 ] +Key: VPSIGNDrr: [ 0.00 0.00 ] +Key: VPSIGNWYrm: [ 0.00 0.00 ] +Key: VPSIGNWYrr: [ 0.00 0.00 ] +Key: VPSIGNWrm: [ 0.00 0.00 ] +Key: VPSIGNWrr: [ 0.00 0.00 ] +Key: VPSLLDQYri: [ 0.00 0.00 ] +Key: VPSLLDQZ: [ 0.00 0.00 ] +Key: VPSLLDQZmi: [ 0.00 0.00 ] +Key: VPSLLDQZri: [ 0.00 0.00 ] +Key: VPSLLDQri: [ 0.00 0.00 ] +Key: VPSLLDYri: [ 0.00 0.00 ] +Key: VPSLLDYrm: [ 0.00 0.00 ] +Key: VPSLLDYrr: [ 0.00 0.00 ] +Key: VPSLLDZ: [ 0.00 0.00 ] +Key: VPSLLDZmbi: [ 0.00 0.00 ] +Key: VPSLLDZmbik: [ 0.00 0.00 ] +Key: VPSLLDZmbikz: [ 0.00 0.00 ] +Key: VPSLLDZmi: [ 0.00 0.00 ] +Key: VPSLLDZmik: [ 0.00 0.00 ] +Key: VPSLLDZmikz: [ 0.00 0.00 ] +Key: VPSLLDZri: [ 0.00 0.00 ] +Key: VPSLLDZrik: [ 0.00 0.00 ] +Key: VPSLLDZrikz: [ 0.00 0.00 ] +Key: VPSLLDZrm: [ 0.00 0.00 ] +Key: VPSLLDZrmk: [ 0.00 0.00 ] +Key: VPSLLDZrmkz: [ 0.00 0.00 ] +Key: VPSLLDZrr: [ 0.00 0.00 ] +Key: VPSLLDZrrk: [ 0.00 0.00 ] +Key: VPSLLDZrrkz: [ 0.00 0.00 ] +Key: VPSLLDri: [ 0.00 0.00 ] +Key: VPSLLDrm: [ 0.00 0.00 ] +Key: VPSLLDrr: [ 0.00 0.00 ] +Key: VPSLLQYri: [ 0.00 0.00 ] +Key: VPSLLQYrm: [ 0.00 0.00 ] +Key: VPSLLQYrr: [ 0.00 0.00 ] +Key: VPSLLQZ: [ 0.00 0.00 ] +Key: VPSLLQZmbi: [ 0.00 0.00 ] +Key: VPSLLQZmbik: [ 0.00 0.00 ] +Key: VPSLLQZmbikz: [ 0.00 0.00 ] +Key: VPSLLQZmi: [ 0.00 0.00 ] +Key: VPSLLQZmik: [ 0.00 0.00 ] +Key: VPSLLQZmikz: [ 0.00 0.00 ] +Key: VPSLLQZri: [ 0.00 0.00 ] +Key: VPSLLQZrik: [ 0.00 0.00 ] +Key: VPSLLQZrikz: [ 0.00 0.00 ] +Key: VPSLLQZrm: [ 0.00 0.00 ] +Key: VPSLLQZrmk: [ 0.00 0.00 ] +Key: VPSLLQZrmkz: [ 0.00 0.00 ] +Key: VPSLLQZrr: [ 0.00 0.00 ] +Key: VPSLLQZrrk: [ 0.00 0.00 ] +Key: VPSLLQZrrkz: [ 0.00 0.00 ] +Key: VPSLLQri: [ 0.00 0.00 ] +Key: VPSLLQrm: [ 0.00 0.00 ] +Key: VPSLLQrr: [ 0.00 0.00 ] +Key: VPSLLVDYrm: [ 0.00 0.00 ] +Key: VPSLLVDYrr: [ 0.00 0.00 ] +Key: VPSLLVDZ: [ 0.00 0.00 ] +Key: VPSLLVDZrm: [ 0.00 0.00 ] +Key: VPSLLVDZrmb: [ 0.00 0.00 ] +Key: VPSLLVDZrmbk: [ 0.00 0.00 ] +Key: VPSLLVDZrmbkz: [ 0.00 0.00 ] +Key: VPSLLVDZrmk: [ 0.00 0.00 ] +Key: VPSLLVDZrmkz: [ 0.00 0.00 ] +Key: VPSLLVDZrr: [ 0.00 0.00 ] +Key: VPSLLVDZrrk: [ 0.00 0.00 ] +Key: VPSLLVDZrrkz: [ 0.00 0.00 ] +Key: VPSLLVDrm: [ 0.00 0.00 ] +Key: VPSLLVDrr: [ 0.00 0.00 ] +Key: VPSLLVQYrm: [ 0.00 0.00 ] +Key: VPSLLVQYrr: [ 0.00 0.00 ] +Key: VPSLLVQZ: [ 0.00 0.00 ] +Key: VPSLLVQZrm: [ 0.00 0.00 ] +Key: VPSLLVQZrmb: [ 0.00 0.00 ] +Key: VPSLLVQZrmbk: [ 0.00 0.00 ] +Key: VPSLLVQZrmbkz: [ 0.00 0.00 ] +Key: VPSLLVQZrmk: [ 0.00 0.00 ] +Key: VPSLLVQZrmkz: [ 0.00 0.00 ] +Key: VPSLLVQZrr: [ 0.00 0.00 ] +Key: VPSLLVQZrrk: [ 0.00 0.00 ] +Key: VPSLLVQZrrkz: [ 0.00 0.00 ] +Key: VPSLLVQrm: [ 0.00 0.00 ] +Key: VPSLLVQrr: [ 0.00 0.00 ] +Key: VPSLLVWZ: [ 0.00 0.00 ] +Key: VPSLLVWZrm: [ 0.00 0.00 ] +Key: VPSLLVWZrmk: [ 0.00 0.00 ] +Key: VPSLLVWZrmkz: [ 0.00 0.00 ] +Key: VPSLLVWZrr: [ 0.00 0.00 ] +Key: VPSLLVWZrrk: [ 0.00 0.00 ] +Key: VPSLLVWZrrkz: [ 0.00 0.00 ] +Key: VPSLLWYri: [ 0.00 0.00 ] +Key: VPSLLWYrm: [ 0.00 0.00 ] +Key: VPSLLWYrr: [ 0.00 0.00 ] +Key: VPSLLWZ: [ 0.00 0.00 ] +Key: VPSLLWZmi: [ 0.00 0.00 ] +Key: VPSLLWZmik: [ 0.00 0.00 ] +Key: VPSLLWZmikz: [ 0.00 0.00 ] +Key: VPSLLWZri: [ 0.00 0.00 ] +Key: VPSLLWZrik: [ 0.00 0.00 ] +Key: VPSLLWZrikz: [ 0.00 0.00 ] +Key: VPSLLWZrm: [ 0.00 0.00 ] +Key: VPSLLWZrmk: [ 0.00 0.00 ] +Key: VPSLLWZrmkz: [ 0.00 0.00 ] +Key: VPSLLWZrr: [ 0.00 0.00 ] +Key: VPSLLWZrrk: [ 0.00 0.00 ] +Key: VPSLLWZrrkz: [ 0.00 0.00 ] +Key: VPSLLWri: [ 0.00 0.00 ] +Key: VPSLLWrm: [ 0.00 0.00 ] +Key: VPSLLWrr: [ 0.00 0.00 ] +Key: VPSRADYri: [ 0.00 0.00 ] +Key: VPSRADYrm: [ 0.00 0.00 ] +Key: VPSRADYrr: [ 0.00 0.00 ] +Key: VPSRADZ: [ 0.00 0.00 ] +Key: VPSRADZmbi: [ 0.00 0.00 ] +Key: VPSRADZmbik: [ 0.00 0.00 ] +Key: VPSRADZmbikz: [ 0.00 0.00 ] +Key: VPSRADZmi: [ 0.00 0.00 ] +Key: VPSRADZmik: [ 0.00 0.00 ] +Key: VPSRADZmikz: [ 0.00 0.00 ] +Key: VPSRADZri: [ 0.00 0.00 ] +Key: VPSRADZrik: [ 0.00 0.00 ] +Key: VPSRADZrikz: [ 0.00 0.00 ] +Key: VPSRADZrm: [ 0.00 0.00 ] +Key: VPSRADZrmk: [ 0.00 0.00 ] +Key: VPSRADZrmkz: [ 0.00 0.00 ] +Key: VPSRADZrr: [ 0.00 0.00 ] +Key: VPSRADZrrk: [ 0.00 0.00 ] +Key: VPSRADZrrkz: [ 0.00 0.00 ] +Key: VPSRADri: [ 0.00 0.00 ] +Key: VPSRADrm: [ 0.00 0.00 ] +Key: VPSRADrr: [ 0.00 0.00 ] +Key: VPSRAQZ: [ 0.00 0.00 ] +Key: VPSRAQZmbi: [ 0.00 0.00 ] +Key: VPSRAQZmbik: [ 0.00 0.00 ] +Key: VPSRAQZmbikz: [ 0.00 0.00 ] +Key: VPSRAQZmi: [ 0.00 0.00 ] +Key: VPSRAQZmik: [ 0.00 0.00 ] +Key: VPSRAQZmikz: [ 0.00 0.00 ] +Key: VPSRAQZri: [ 0.00 0.00 ] +Key: VPSRAQZrik: [ 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VREDUCESDZrribkz: [ 0.00 0.00 ] +Key: VREDUCESDZrrik: [ 0.00 0.00 ] +Key: VREDUCESDZrrikz: [ 0.00 0.00 ] +Key: VREDUCESHZrmi: [ 0.00 0.00 ] +Key: VREDUCESHZrmik: [ 0.00 0.00 ] +Key: VREDUCESHZrmikz: [ 0.00 0.00 ] +Key: VREDUCESHZrri: [ 0.00 0.00 ] +Key: VREDUCESHZrrib: [ 0.00 0.00 ] +Key: VREDUCESHZrribk: [ 0.00 0.00 ] +Key: VREDUCESHZrribkz: [ 0.00 0.00 ] +Key: VREDUCESHZrrik: [ 0.00 0.00 ] +Key: VREDUCESHZrrikz: [ 0.00 0.00 ] +Key: VREDUCESSZrmi: [ 0.00 0.00 ] +Key: VREDUCESSZrmik: [ 0.00 0.00 ] +Key: VREDUCESSZrmikz: [ 0.00 0.00 ] +Key: VREDUCESSZrri: [ 0.00 0.00 ] +Key: VREDUCESSZrrib: [ 0.00 0.00 ] +Key: VREDUCESSZrribk: [ 0.00 0.00 ] +Key: VREDUCESSZrribkz: [ 0.00 0.00 ] +Key: VREDUCESSZrrik: [ 0.00 0.00 ] +Key: VREDUCESSZrrikz: [ 0.00 0.00 ] +Key: VRNDSCALEBF: [ 0.00 0.00 ] +Key: VRNDSCALEPDZ: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrmbi: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrmbik: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrmbikz: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrmi: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrmik: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrmikz: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrri: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrrib: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrribk: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrribkz: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrrik: [ 0.00 0.00 ] +Key: VRNDSCALEPDZrrikz: [ 0.00 0.00 ] +Key: VRNDSCALEPHZ: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrmbi: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrmbik: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrmbikz: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrmi: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrmik: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrmikz: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrri: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrrib: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrribk: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrribkz: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrrik: [ 0.00 0.00 ] +Key: VRNDSCALEPHZrrikz: [ 0.00 0.00 ] +Key: VRNDSCALEPSZ: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrmbi: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrmbik: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrmbikz: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrmi: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrmik: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrmikz: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrri: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrrib: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrribk: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrribkz: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrrik: [ 0.00 0.00 ] +Key: VRNDSCALEPSZrrikz: [ 0.00 0.00 ] +Key: VRNDSCALESDZrmi: [ 0.00 0.00 ] +Key: VRNDSCALESDZrmi_Int: [ 0.00 0.00 ] +Key: VRNDSCALESDZrmik_Int: [ 0.00 0.00 ] +Key: VRNDSCALESDZrmikz_Int: [ 0.00 0.00 ] +Key: VRNDSCALESDZrri: [ 0.00 0.00 ] +Key: VRNDSCALESDZrri_Int: [ 0.00 0.00 ] +Key: VRNDSCALESDZrrib_Int: [ 0.00 0.00 ] +Key: VRNDSCALESDZrribk_Int: [ 0.00 0.00 ] +Key: VRNDSCALESDZrribkz_Int: [ 0.00 0.00 ] +Key: VRNDSCALESDZrrik_Int: [ 0.00 0.00 ] +Key: VRNDSCALESDZrrikz_Int: [ 0.00 0.00 ] +Key: VRNDSCALESHZrmi: [ 0.00 0.00 ] +Key: VRNDSCALESHZrmi_Int: [ 0.00 0.00 ] +Key: VRNDSCALESHZrmik_Int: [ 0.00 0.00 ] +Key: VRNDSCALESHZrmikz_Int: [ 0.00 0.00 ] +Key: VRNDSCALESHZrri: [ 0.00 0.00 ] +Key: VRNDSCALESHZrri_Int: [ 0.00 0.00 ] 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0.00 ] +Key: VXORPSZrmkz: [ 0.00 0.00 ] +Key: VXORPSZrr: [ 0.00 0.00 ] +Key: VXORPSZrrk: [ 0.00 0.00 ] +Key: VXORPSZrrkz: [ 0.00 0.00 ] +Key: VXORPSrm: [ 0.00 0.00 ] +Key: VXORPSrr: [ 0.00 0.00 ] +Key: VZEROALL: [ 0.00 0.00 ] +Key: VZEROUPPER: [ 0.00 0.00 ] +Key: V_SET: [ 0.00 0.00 ] +Key: V_SETALLONES: [ 0.00 0.00 ] +Key: WAIT: [ 0.00 0.00 ] +Key: WBINVD: [ 0.00 0.00 ] +Key: WBNOINVD: [ 0.00 0.00 ] +Key: WRFLAGS: [ 0.00 0.00 ] +Key: WRFSBASE: [ 0.00 0.00 ] +Key: WRGSBASE: [ 0.00 0.00 ] +Key: WRMSR: [ 0.00 0.00 ] +Key: WRMSRLIST: [ 0.00 0.00 ] +Key: WRMSRNS: [ 0.00 0.00 ] +Key: WRMSRNSir: [ 0.00 0.00 ] +Key: WRMSRNSir_EVEX: [ 0.00 0.00 ] +Key: WRPKRUr: [ 0.00 0.00 ] +Key: WRSSD: [ 0.00 0.00 ] +Key: WRSSD_EVEX: [ 0.00 0.00 ] +Key: WRSSQ: [ 0.00 0.00 ] +Key: WRSSQ_EVEX: [ 0.00 0.00 ] +Key: WRUSSD: [ 0.00 0.00 ] +Key: WRUSSD_EVEX: [ 0.00 0.00 ] +Key: WRUSSQ: [ 0.00 0.00 ] +Key: WRUSSQ_EVEX: [ 0.00 0.00 ] +Key: XABORT: [ 0.00 0.00 ] +Key: XABORT_DEF: [ 0.00 0.00 ] +Key: XACQUIRE_PREFIX: [ 0.00 0.00 ] +Key: XADD: [ 0.00 0.00 ] +Key: XAM_F: [ 0.00 0.00 ] +Key: XAM_Fp: [ 0.00 0.00 ] +Key: XBEGIN: [ 0.00 0.00 ] +Key: XCHG: [ 0.00 0.00 ] +Key: XCH_F: [ 0.00 0.00 ] +Key: XCRYPTCBC: [ 0.00 0.00 ] +Key: XCRYPTCFB: [ 0.00 0.00 ] +Key: XCRYPTCTR: [ 0.00 0.00 ] +Key: XCRYPTECB: [ 0.00 0.00 ] +Key: XCRYPTOFB: [ 0.00 0.00 ] +Key: XEND: [ 0.00 0.00 ] +Key: XGETBV: [ 0.00 0.00 ] +Key: XLAT: [ 0.00 0.00 ] +Key: XOR: [ 0.00 0.00 ] +Key: XORPDrm: [ 0.00 0.00 ] +Key: XORPDrr: [ 0.00 0.00 ] +Key: XORPSrm: [ 0.00 0.00 ] +Key: XORPSrr: [ 0.00 0.00 ] +Key: XRELEASE_PREFIX: [ 0.00 0.00 ] +Key: XRESLDTRK: [ 0.00 0.00 ] +Key: XRSTOR: [ 0.00 0.00 ] +Key: XRSTORS: [ 0.00 0.00 ] +Key: XSAVE: [ 0.00 0.00 ] +Key: XSAVEC: [ 0.00 0.00 ] +Key: XSAVEOPT: [ 0.00 0.00 ] +Key: XSAVES: [ 0.00 0.00 ] +Key: XSETBV: [ 0.00 0.00 ] +Key: XSHA: [ 0.00 0.00 ] +Key: XSTORE: [ 0.00 0.00 ] +Key: XSUSLDTRK: [ 0.00 0.00 ] +Key: XTEST: [ 0.00 0.00 ] diff --git a/llvm/test/CodeGen/MIR2Vec/vocab-basic.ll b/llvm/test/CodeGen/MIR2Vec/vocab-basic.ll new file mode 100644 index 0000000..a57dd0b --- /dev/null +++ b/llvm/test/CodeGen/MIR2Vec/vocab-basic.ll @@ -0,0 +1,14 @@ +; REQUIRES: x86_64-linux +; RUN: llc -o /dev/null -print-mir2vec-vocab -mir2vec-vocab-path=%S/Inputs/mir2vec_dummy_2D_vocab.json %s 2> %t1.log +; RUN: diff %S/Inputs/reference_x86_vocab_print.txt %t1.log + +; RUN: llc -o /dev/null -print-mir2vec-vocab -mir2vec-opc-weight=1 -mir2vec-vocab-path=%S/Inputs/mir2vec_dummy_2D_vocab.json %s 2> %t1.log +; RUN: diff %S/Inputs/reference_x86_vocab_print.txt %t1.log + +; RUN: llc -o /dev/null -print-mir2vec-vocab -mir2vec-opc-weight=0.5 -mir2vec-vocab-path=%S/Inputs/mir2vec_dummy_2D_vocab.json %s 2> %t1.log +; RUN: diff %S/Inputs/reference_x86_vocab_wo=0.5_print.txt %t1.log + +define dso_local void @test() { + entry: + ret void +} diff --git a/llvm/test/CodeGen/MIR2Vec/vocab-error-handling.ll b/llvm/test/CodeGen/MIR2Vec/vocab-error-handling.ll new file mode 100644 index 0000000..1da516a --- /dev/null +++ b/llvm/test/CodeGen/MIR2Vec/vocab-error-handling.ll @@ -0,0 +1,15 @@ +; REQUIRES: x86_64-linux +; RUN: not llc -o /dev/null -print-mir2vec-vocab %s 2>&1 | FileCheck %s --check-prefix=CHECK-INVALID +; RUN: not llc -o /dev/null -print-mir2vec-vocab -mir2vec-vocab-path=%S/Inputs/mir2vec_zero_vocab.json %s 2>&1 | FileCheck %s --check-prefix=CHECK-ZERO-DIM +; RUN: not llc -o /dev/null -print-mir2vec-vocab -mir2vec-vocab-path=%S/Inputs/mir2vec_invalid_vocab.json %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ENTITIES +; RUN: not llc -o /dev/null -print-mir2vec-vocab -mir2vec-vocab-path=%S/Inputs/mir2vec_inconsistent_dims.json %s 2>&1 | FileCheck %s --check-prefix=CHECK-INCONSISTENT-DIMS + +define dso_local void @test() { + entry: + ret void +} + +; CHECK-INVALID: error: MIR2Vec vocabulary file path not specified; set it using --mir2vec-vocab-path +; CHECK-ZERO-DIM: error: Dimension of 'entities' section of the vocabulary is zero +; CHECK-NO-ENTITIES: error: Missing 'entities' section in vocabulary file +; CHECK-INCONSISTENT-DIMS: error: All vectors in the 'entities' section of the vocabulary are not of the same dimension diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll b/llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll index 4ad2d2c..4914357 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/atomic-load-store-fp.ll @@ -23,6 +23,16 @@ ; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d,+a,+ztso -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO-TRAILING-FENCE %s +; RUN: llc -mtriple=riscv32 -global-isel -mattr=+d,+a,+experimental-zalasr -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZALASR,RV32IA-ZALASR-WMO %s +; RUN: llc -mtriple=riscv32 -global-isel -mattr=+d,+a,+experimental-zalasr,+ztso -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-ZALASR,RV32IA-ZALASR-TSO %s + +; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d,+a,+experimental-zalasr -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZALASR,RV64IA-ZALASR-WMO %s +; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d,+a,+experimental-zalasr,+ztso -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZALASR,RV64IA-ZALASR-TSO %s + define float @atomic_load_f32_unordered(ptr %a) nounwind { ; RV32I-LABEL: atomic_load_f32_unordered: @@ -171,6 +181,30 @@ define float @atomic_load_f32_acquire(ptr %a) nounwind { ; RV64IA-TSO-TRAILING-FENCE-NEXT: lw a0, 0(a0) ; RV64IA-TSO-TRAILING-FENCE-NEXT: fmv.w.x fa0, a0 ; RV64IA-TSO-TRAILING-FENCE-NEXT: ret +; +; RV32IA-ZALASR-WMO-LABEL: atomic_load_f32_acquire: +; RV32IA-ZALASR-WMO: # %bb.0: +; RV32IA-ZALASR-WMO-NEXT: lw.aq a0, (a0) +; RV32IA-ZALASR-WMO-NEXT: fmv.w.x fa0, a0 +; RV32IA-ZALASR-WMO-NEXT: ret +; +; RV32IA-ZALASR-TSO-LABEL: atomic_load_f32_acquire: +; RV32IA-ZALASR-TSO: # %bb.0: +; RV32IA-ZALASR-TSO-NEXT: lw a0, 0(a0) +; RV32IA-ZALASR-TSO-NEXT: fmv.w.x fa0, a0 +; RV32IA-ZALASR-TSO-NEXT: ret +; +; RV64IA-ZALASR-WMO-LABEL: atomic_load_f32_acquire: +; RV64IA-ZALASR-WMO: # %bb.0: +; RV64IA-ZALASR-WMO-NEXT: lw.aq a0, (a0) +; RV64IA-ZALASR-WMO-NEXT: fmv.w.x fa0, a0 +; RV64IA-ZALASR-WMO-NEXT: ret +; +; RV64IA-ZALASR-TSO-LABEL: atomic_load_f32_acquire: +; RV64IA-ZALASR-TSO: # %bb.0: +; RV64IA-ZALASR-TSO-NEXT: lw a0, 0(a0) +; RV64IA-ZALASR-TSO-NEXT: fmv.w.x fa0, a0 +; RV64IA-ZALASR-TSO-NEXT: ret %1 = load atomic float, ptr %a acquire, align 4 ret float %1 } @@ -256,6 +290,18 @@ define float @atomic_load_f32_seq_cst(ptr %a) nounwind { ; RV64IA-TSO-TRAILING-FENCE-NEXT: lw a0, 0(a0) ; RV64IA-TSO-TRAILING-FENCE-NEXT: fmv.w.x fa0, a0 ; RV64IA-TSO-TRAILING-FENCE-NEXT: ret +; +; RV32IA-ZALASR-LABEL: atomic_load_f32_seq_cst: +; RV32IA-ZALASR: # %bb.0: +; RV32IA-ZALASR-NEXT: lw.aq a0, (a0) +; RV32IA-ZALASR-NEXT: fmv.w.x fa0, a0 +; RV32IA-ZALASR-NEXT: ret +; +; RV64IA-ZALASR-LABEL: atomic_load_f32_seq_cst: +; RV64IA-ZALASR: # %bb.0: +; RV64IA-ZALASR-NEXT: lw.aq a0, (a0) +; RV64IA-ZALASR-NEXT: fmv.w.x fa0, a0 +; RV64IA-ZALASR-NEXT: ret %1 = load atomic float, ptr %a seq_cst, align 4 ret float %1 } @@ -414,6 +460,18 @@ define double @atomic_load_f64_acquire(ptr %a) nounwind { ; RV64IA-TSO-TRAILING-FENCE-NEXT: ld a0, 0(a0) ; RV64IA-TSO-TRAILING-FENCE-NEXT: fmv.d.x fa0, a0 ; RV64IA-TSO-TRAILING-FENCE-NEXT: ret +; +; RV64IA-ZALASR-WMO-LABEL: atomic_load_f64_acquire: +; RV64IA-ZALASR-WMO: # %bb.0: +; RV64IA-ZALASR-WMO-NEXT: ld.aq a0, (a0) +; RV64IA-ZALASR-WMO-NEXT: fmv.d.x fa0, a0 +; RV64IA-ZALASR-WMO-NEXT: ret +; +; RV64IA-ZALASR-TSO-LABEL: atomic_load_f64_acquire: +; RV64IA-ZALASR-TSO: # %bb.0: +; RV64IA-ZALASR-TSO-NEXT: ld a0, 0(a0) +; RV64IA-ZALASR-TSO-NEXT: fmv.d.x fa0, a0 +; RV64IA-ZALASR-TSO-NEXT: ret %1 = load atomic double, ptr %a acquire, align 8 ret double %1 } @@ -484,6 +542,12 @@ define double @atomic_load_f64_seq_cst(ptr %a) nounwind { ; RV64IA-TSO-TRAILING-FENCE-NEXT: ld a0, 0(a0) ; RV64IA-TSO-TRAILING-FENCE-NEXT: fmv.d.x fa0, a0 ; RV64IA-TSO-TRAILING-FENCE-NEXT: ret +; +; RV64IA-ZALASR-LABEL: atomic_load_f64_seq_cst: +; RV64IA-ZALASR: # %bb.0: +; RV64IA-ZALASR-NEXT: ld.aq a0, (a0) +; RV64IA-ZALASR-NEXT: fmv.d.x fa0, a0 +; RV64IA-ZALASR-NEXT: ret %1 = load atomic double, ptr %a seq_cst, align 8 ret double %1 } @@ -635,6 +699,30 @@ define void @atomic_store_f32_release(ptr %a, float %b) nounwind { ; RV64IA-TSO-TRAILING-FENCE-NEXT: fmv.x.w a1, fa0 ; RV64IA-TSO-TRAILING-FENCE-NEXT: sw a1, 0(a0) ; RV64IA-TSO-TRAILING-FENCE-NEXT: ret +; +; RV32IA-ZALASR-WMO-LABEL: atomic_store_f32_release: +; RV32IA-ZALASR-WMO: # %bb.0: +; RV32IA-ZALASR-WMO-NEXT: fmv.x.w a1, fa0 +; RV32IA-ZALASR-WMO-NEXT: sw.rl a1, (a0) +; RV32IA-ZALASR-WMO-NEXT: ret +; +; RV32IA-ZALASR-TSO-LABEL: atomic_store_f32_release: +; RV32IA-ZALASR-TSO: # %bb.0: +; RV32IA-ZALASR-TSO-NEXT: fmv.x.w a1, fa0 +; RV32IA-ZALASR-TSO-NEXT: sw a1, 0(a0) +; RV32IA-ZALASR-TSO-NEXT: ret +; +; RV64IA-ZALASR-WMO-LABEL: atomic_store_f32_release: +; RV64IA-ZALASR-WMO: # %bb.0: +; RV64IA-ZALASR-WMO-NEXT: fmv.x.w a1, fa0 +; RV64IA-ZALASR-WMO-NEXT: sw.rl a1, (a0) +; RV64IA-ZALASR-WMO-NEXT: ret +; +; RV64IA-ZALASR-TSO-LABEL: atomic_store_f32_release: +; RV64IA-ZALASR-TSO: # %bb.0: +; RV64IA-ZALASR-TSO-NEXT: fmv.x.w a1, fa0 +; RV64IA-ZALASR-TSO-NEXT: sw a1, 0(a0) +; RV64IA-ZALASR-TSO-NEXT: ret store atomic float %b, ptr %a release, align 4 ret void } @@ -718,6 +806,18 @@ define void @atomic_store_f32_seq_cst(ptr %a, float %b) nounwind { ; RV64IA-TSO-TRAILING-FENCE-NEXT: sw a1, 0(a0) ; RV64IA-TSO-TRAILING-FENCE-NEXT: fence rw, rw ; RV64IA-TSO-TRAILING-FENCE-NEXT: ret +; +; RV32IA-ZALASR-LABEL: atomic_store_f32_seq_cst: +; RV32IA-ZALASR: # %bb.0: +; RV32IA-ZALASR-NEXT: fmv.x.w a1, fa0 +; RV32IA-ZALASR-NEXT: sw.rl a1, (a0) +; RV32IA-ZALASR-NEXT: ret +; +; RV64IA-ZALASR-LABEL: atomic_store_f32_seq_cst: +; RV64IA-ZALASR: # %bb.0: +; RV64IA-ZALASR-NEXT: fmv.x.w a1, fa0 +; RV64IA-ZALASR-NEXT: sw.rl a1, (a0) +; RV64IA-ZALASR-NEXT: ret store atomic float %b, ptr %a seq_cst, align 4 ret void } @@ -876,6 +976,18 @@ define void @atomic_store_f64_release(ptr %a, double %b) nounwind { ; RV64IA-TSO-TRAILING-FENCE-NEXT: fmv.x.d a1, fa0 ; RV64IA-TSO-TRAILING-FENCE-NEXT: sd a1, 0(a0) ; RV64IA-TSO-TRAILING-FENCE-NEXT: ret +; +; RV64IA-ZALASR-WMO-LABEL: atomic_store_f64_release: +; RV64IA-ZALASR-WMO: # %bb.0: +; RV64IA-ZALASR-WMO-NEXT: fmv.x.d a1, fa0 +; RV64IA-ZALASR-WMO-NEXT: sd.rl a1, (a0) +; RV64IA-ZALASR-WMO-NEXT: ret +; +; RV64IA-ZALASR-TSO-LABEL: atomic_store_f64_release: +; RV64IA-ZALASR-TSO: # %bb.0: +; RV64IA-ZALASR-TSO-NEXT: fmv.x.d a1, fa0 +; RV64IA-ZALASR-TSO-NEXT: sd a1, 0(a0) +; RV64IA-ZALASR-TSO-NEXT: ret store atomic double %b, ptr %a release, align 8 ret void } @@ -945,6 +1057,12 @@ define void @atomic_store_f64_seq_cst(ptr %a, double %b) nounwind { ; RV64IA-TSO-TRAILING-FENCE-NEXT: sd a1, 0(a0) ; RV64IA-TSO-TRAILING-FENCE-NEXT: fence rw, rw ; RV64IA-TSO-TRAILING-FENCE-NEXT: ret +; +; RV64IA-ZALASR-LABEL: atomic_store_f64_seq_cst: +; RV64IA-ZALASR: # %bb.0: +; RV64IA-ZALASR-NEXT: fmv.x.d a1, fa0 +; RV64IA-ZALASR-NEXT: sd.rl a1, (a0) +; RV64IA-ZALASR-NEXT: ret store atomic double %b, ptr %a seq_cst, align 8 ret void } diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll index b0510f8..1213256 100644 --- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll +++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll @@ -21,10 +21,19 @@ ; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso,+zacas -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-ZACAS,RV64IA-TSO,RV64IA-TSO-ZACAS %s +; RUN: llc -mtriple=riscv32 -mattr=+a,+zabha -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-WMO,RV32IA-WMO-ZABHA,RV32IA-WMO-ZABHA-NOZACAS %s +; RUN: llc -mtriple=riscv32 -mattr=+a,+ztso,+zabha -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-TSO,RV32IA-TSO-ZABHA,RV32IA-TSO-ZABHA-NOZACAS %s ; RUN: llc -mtriple=riscv64 -mattr=+a,+zabha -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO,RV64IA-WMO-ZABHA,RV64IA-WMO-ZABHA-NOZACAS %s ; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso,+zabha -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO,RV64IA-TSO-ZABHA,RV64IA-TSO-ZABHA-NOZACAS %s + +; RUN: llc -mtriple=riscv32 -mattr=+a,+zabha,+zacas -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-WMO,RV32IA-WMO-ZABHA,RV32IA-WMO-ZABHA-ZACAS %s +; RUN: llc -mtriple=riscv32 -mattr=+a,+ztso,+zabha,+zacas -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-TSO,RV32IA-TSO-ZABHA,RV32IA-TSO-ZABHA-ZACAS %s ; RUN: llc -mtriple=riscv64 -mattr=+a,+zabha,+zacas -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO,RV64IA-WMO-ZABHA,RV64IA-WMO-ZABHA-ZACAS %s ; RUN: llc -mtriple=riscv64 -mattr=+a,+ztso,+zabha,+zacas -verify-machineinstrs < %s \ @@ -41,25 +50,25 @@ define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_xchg_i8_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: li a3, 255 -; RV32IA-NEXT: zext.b a1, a1 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a4, (a2) -; RV32IA-NEXT: mv a5, a1 -; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: and a5, a5, a3 -; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB0_1 -; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_i8_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: li a3, 255 +; RV32IA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-NOZACAS-NEXT: mv a5, a1 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB0_1 +; RV32IA-NOZACAS-NEXT: # %bb.2: +; RV32IA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_i8_monotonic: ; RV64I: # %bb.0: @@ -91,6 +100,26 @@ define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_xchg_i8_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: li a3, 255 +; RV32IA-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-ZACAS-NEXT: mv a5, a1 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB0_1 +; RV32IA-ZACAS-NEXT: # %bb.2: +; RV32IA-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_xchg_i8_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -111,6 +140,16 @@ define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i8_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoswap.b a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i8_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i8_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoswap.b a0, a1, (a0) @@ -135,45 +174,45 @@ define i8 @atomicrmw_xchg_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_i8_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a4, (a2) -; RV32IA-WMO-NEXT: mv a5, a1 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: and a5, a5, a3 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: sc.w a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB1_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a4, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-NOZACAS-NEXT: mv a5, a1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB1_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_i8_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a4, (a2) -; RV32IA-TSO-NEXT: mv a5, a1 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: and a5, a5, a3 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB1_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a4, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_i8_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-NOZACAS-NEXT: mv a5, a1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB1_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_i8_acquire: ; RV64I: # %bb.0: @@ -225,6 +264,46 @@ define i8 @atomicrmw_xchg_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i8_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-ZACAS-NEXT: mv a5, a1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB1_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_i8_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZACAS-NEXT: mv a5, a1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB1_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i8_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -265,6 +344,16 @@ define i8 @atomicrmw_xchg_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i8_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoswap.b.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i8_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i8_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aq a0, a1, (a0) @@ -289,45 +378,45 @@ define i8 @atomicrmw_xchg_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_i8_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w a4, (a2) -; RV32IA-WMO-NEXT: mv a5, a1 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: and a5, a5, a3 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB2_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a4, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-WMO-NOZACAS-NEXT: mv a5, a1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB2_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_i8_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a4, (a2) -; RV32IA-TSO-NEXT: mv a5, a1 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: and a5, a5, a3 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB2_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a4, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_i8_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-NOZACAS-NEXT: mv a5, a1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB2_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_i8_release: ; RV64I: # %bb.0: @@ -379,6 +468,46 @@ define i8 @atomicrmw_xchg_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i8_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-WMO-ZACAS-NEXT: mv a5, a1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB2_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_i8_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZACAS-NEXT: mv a5, a1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB2_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i8_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -419,6 +548,16 @@ define i8 @atomicrmw_xchg_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i8_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoswap.b.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i8_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i8_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoswap.b.rl a0, a1, (a0) @@ -443,45 +582,45 @@ define i8 @atomicrmw_xchg_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_i8_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a4, (a2) -; RV32IA-WMO-NEXT: mv a5, a1 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: and a5, a5, a3 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB3_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a4, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i8_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-NOZACAS-NEXT: mv a5, a1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB3_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_i8_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a4, (a2) -; RV32IA-TSO-NEXT: mv a5, a1 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: and a5, a5, a3 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB3_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a4, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_i8_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-NOZACAS-NEXT: mv a5, a1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB3_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_i8_acq_rel: ; RV64I: # %bb.0: @@ -533,6 +672,46 @@ define i8 @atomicrmw_xchg_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i8_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-ZACAS-NEXT: mv a5, a1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB3_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_i8_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZACAS-NEXT: mv a5, a1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB3_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i8_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -573,6 +752,16 @@ define i8 @atomicrmw_xchg_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i8_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i8_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i8_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, a1, (a0) @@ -597,25 +786,25 @@ define i8 @atomicrmw_xchg_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_xchg_i8_seq_cst: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: li a3, 255 -; RV32IA-NEXT: zext.b a1, a1 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a4, (a2) -; RV32IA-NEXT: mv a5, a1 -; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: and a5, a5, a3 -; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB4_1 -; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_i8_seq_cst: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: li a3, 255 +; RV32IA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w.aqrl a4, (a2) +; RV32IA-NOZACAS-NEXT: mv a5, a1 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB4_1 +; RV32IA-NOZACAS-NEXT: # %bb.2: +; RV32IA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV64I: # %bb.0: @@ -647,6 +836,26 @@ define i8 @atomicrmw_xchg_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_xchg_i8_seq_cst: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: li a3, 255 +; RV32IA-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w.aqrl a4, (a2) +; RV32IA-ZACAS-NEXT: mv a5, a1 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB4_1 +; RV32IA-ZACAS-NEXT: # %bb.2: +; RV32IA-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -667,6 +876,16 @@ define i8 @atomicrmw_xchg_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i8_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i8_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i8_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, a1, (a0) @@ -695,16 +914,16 @@ define i8 @atomicrmw_xchg_0_i8_monotonic(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_xchg_0_i8_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a1, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: li a2, 255 -; RV32IA-NEXT: sll a2, a2, a0 -; RV32IA-NEXT: not a2, a2 -; RV32IA-NEXT: amoand.w a1, a2, (a1) -; RV32IA-NEXT: srl a0, a1, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_0_i8_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: li a2, 255 +; RV32IA-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-NOZACAS-NEXT: not a2, a2 +; RV32IA-NOZACAS-NEXT: amoand.w a1, a2, (a1) +; RV32IA-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_0_i8_monotonic: ; RV64I: # %bb.0: @@ -728,6 +947,17 @@ define i8 @atomicrmw_xchg_0_i8_monotonic(ptr %a) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_xchg_0_i8_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: li a2, 255 +; RV32IA-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-ZACAS-NEXT: not a2, a2 +; RV32IA-ZACAS-NEXT: amoand.w a1, a2, (a1) +; RV32IA-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_xchg_0_i8_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a1, a0, -4 @@ -739,6 +969,16 @@ define i8 @atomicrmw_xchg_0_i8_monotonic(ptr %a) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i8_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoswap.b a0, zero, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i8_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoswap.b a0, zero, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i8_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoswap.b a0, zero, (a0) @@ -764,27 +1004,27 @@ define i8 @atomicrmw_xchg_0_i8_acquire(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_0_i8_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a1, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a2, 255 -; RV32IA-WMO-NEXT: sll a2, a2, a0 -; RV32IA-WMO-NEXT: not a2, a2 -; RV32IA-WMO-NEXT: amoand.w.aq a1, a2, (a1) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a2, 255 +; RV32IA-WMO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-NOZACAS-NEXT: not a2, a2 +; RV32IA-WMO-NOZACAS-NEXT: amoand.w.aq a1, a2, (a1) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_0_i8_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a1, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a2, 255 -; RV32IA-TSO-NEXT: sll a2, a2, a0 -; RV32IA-TSO-NEXT: not a2, a2 -; RV32IA-TSO-NEXT: amoand.w a1, a2, (a1) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a2, 255 +; RV32IA-TSO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-NOZACAS-NEXT: not a2, a2 +; RV32IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_0_i8_acquire: ; RV64I: # %bb.0: @@ -819,6 +1059,28 @@ define i8 @atomicrmw_xchg_0_i8_acquire(ptr %a) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i8_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a2, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: not a2, a2 +; RV32IA-WMO-ZACAS-NEXT: amoand.w.aq a1, a2, (a1) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i8_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a2, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: not a2, a2 +; RV32IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i8_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4 @@ -841,6 +1103,16 @@ define i8 @atomicrmw_xchg_0_i8_acquire(ptr %a) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i8_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoswap.b.aq a0, zero, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i8_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoswap.b a0, zero, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i8_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aq a0, zero, (a0) @@ -866,27 +1138,27 @@ define i8 @atomicrmw_xchg_0_i8_release(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_0_i8_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a1, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a2, 255 -; RV32IA-WMO-NEXT: sll a2, a2, a0 -; RV32IA-WMO-NEXT: not a2, a2 -; RV32IA-WMO-NEXT: amoand.w.rl a1, a2, (a1) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a2, 255 +; RV32IA-WMO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-NOZACAS-NEXT: not a2, a2 +; RV32IA-WMO-NOZACAS-NEXT: amoand.w.rl a1, a2, (a1) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_0_i8_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a1, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a2, 255 -; RV32IA-TSO-NEXT: sll a2, a2, a0 -; RV32IA-TSO-NEXT: not a2, a2 -; RV32IA-TSO-NEXT: amoand.w a1, a2, (a1) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a2, 255 +; RV32IA-TSO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-NOZACAS-NEXT: not a2, a2 +; RV32IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_0_i8_release: ; RV64I: # %bb.0: @@ -921,6 +1193,28 @@ define i8 @atomicrmw_xchg_0_i8_release(ptr %a) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i8_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a2, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: not a2, a2 +; RV32IA-WMO-ZACAS-NEXT: amoand.w.rl a1, a2, (a1) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i8_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a2, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: not a2, a2 +; RV32IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i8_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4 @@ -943,6 +1237,16 @@ define i8 @atomicrmw_xchg_0_i8_release(ptr %a) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i8_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoswap.b.rl a0, zero, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i8_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoswap.b a0, zero, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i8_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoswap.b.rl a0, zero, (a0) @@ -968,27 +1272,27 @@ define i8 @atomicrmw_xchg_0_i8_acq_rel(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_0_i8_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a1, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a2, 255 -; RV32IA-WMO-NEXT: sll a2, a2, a0 -; RV32IA-WMO-NEXT: not a2, a2 -; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a2, 255 +; RV32IA-WMO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-NOZACAS-NEXT: not a2, a2 +; RV32IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a2, (a1) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_0_i8_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a1, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a2, 255 -; RV32IA-TSO-NEXT: sll a2, a2, a0 -; RV32IA-TSO-NEXT: not a2, a2 -; RV32IA-TSO-NEXT: amoand.w a1, a2, (a1) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a2, 255 +; RV32IA-TSO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-NOZACAS-NEXT: not a2, a2 +; RV32IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_0_i8_acq_rel: ; RV64I: # %bb.0: @@ -1023,6 +1327,28 @@ define i8 @atomicrmw_xchg_0_i8_acq_rel(ptr %a) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i8_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a2, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: not a2, a2 +; RV32IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a2, (a1) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i8_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a2, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: not a2, a2 +; RV32IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i8_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4 @@ -1045,6 +1371,16 @@ define i8 @atomicrmw_xchg_0_i8_acq_rel(ptr %a) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i8_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, zero, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i8_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoswap.b a0, zero, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i8_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, zero, (a0) @@ -1070,27 +1406,27 @@ define i8 @atomicrmw_xchg_0_i8_seq_cst(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_0_i8_seq_cst: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a1, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a2, 255 -; RV32IA-WMO-NEXT: sll a2, a2, a0 -; RV32IA-WMO-NEXT: not a2, a2 -; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_seq_cst: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a2, 255 +; RV32IA-WMO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-NOZACAS-NEXT: not a2, a2 +; RV32IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a2, (a1) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_0_i8_seq_cst: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a1, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a2, 255 -; RV32IA-TSO-NEXT: sll a2, a2, a0 -; RV32IA-TSO-NEXT: not a2, a2 -; RV32IA-TSO-NEXT: amoand.w a1, a2, (a1) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i8_seq_cst: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a2, 255 +; RV32IA-TSO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-NOZACAS-NEXT: not a2, a2 +; RV32IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_0_i8_seq_cst: ; RV64I: # %bb.0: @@ -1125,6 +1461,28 @@ define i8 @atomicrmw_xchg_0_i8_seq_cst(ptr %a) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i8_seq_cst: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a2, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: not a2, a2 +; RV32IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a2, (a1) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i8_seq_cst: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a2, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: not a2, a2 +; RV32IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i8_seq_cst: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4 @@ -1147,6 +1505,16 @@ define i8 @atomicrmw_xchg_0_i8_seq_cst(ptr %a) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i8_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, zero, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i8_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoswap.b a0, zero, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i8_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, zero, (a0) @@ -1172,15 +1540,15 @@ define i8 @atomicrmw_xchg_minus_1_i8_monotonic(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_xchg_minus_1_i8_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a1, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: li a2, 255 -; RV32IA-NEXT: sll a2, a2, a0 -; RV32IA-NEXT: amoor.w a1, a2, (a1) -; RV32IA-NEXT: srl a0, a1, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: li a2, 255 +; RV32IA-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-NOZACAS-NEXT: amoor.w a1, a2, (a1) +; RV32IA-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_minus_1_i8_monotonic: ; RV64I: # %bb.0: @@ -1203,6 +1571,16 @@ define i8 @atomicrmw_xchg_minus_1_i8_monotonic(ptr %a) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: li a2, 255 +; RV32IA-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-ZACAS-NEXT: amoor.w a1, a2, (a1) +; RV32IA-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a1, a0, -4 @@ -1213,6 +1591,18 @@ define i8 @atomicrmw_xchg_minus_1_i8_monotonic(ptr %a) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: li a1, -1 +; RV32IA-WMO-ZABHA-NEXT: amoswap.b a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: li a1, -1 +; RV32IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: li a1, -1 @@ -1240,25 +1630,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_acquire(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a1, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a2, 255 -; RV32IA-WMO-NEXT: sll a2, a2, a0 -; RV32IA-WMO-NEXT: amoor.w.aq a1, a2, (a1) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a2, 255 +; RV32IA-WMO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoor.w.aq a1, a2, (a1) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a1, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a2, 255 -; RV32IA-TSO-NEXT: sll a2, a2, a0 -; RV32IA-TSO-NEXT: amoor.w a1, a2, (a1) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a2, 255 +; RV32IA-TSO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_minus_1_i8_acquire: ; RV64I: # %bb.0: @@ -1291,6 +1681,26 @@ define i8 @atomicrmw_xchg_minus_1_i8_acquire(ptr %a) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a2, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: amoor.w.aq a1, a2, (a1) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a2, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4 @@ -1311,6 +1721,18 @@ define i8 @atomicrmw_xchg_minus_1_i8_acquire(ptr %a) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: li a1, -1 +; RV32IA-WMO-ZABHA-NEXT: amoswap.b.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: li a1, -1 +; RV32IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: li a1, -1 @@ -1338,25 +1760,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_release(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a1, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a2, 255 -; RV32IA-WMO-NEXT: sll a2, a2, a0 -; RV32IA-WMO-NEXT: amoor.w.rl a1, a2, (a1) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a2, 255 +; RV32IA-WMO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoor.w.rl a1, a2, (a1) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a1, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a2, 255 -; RV32IA-TSO-NEXT: sll a2, a2, a0 -; RV32IA-TSO-NEXT: amoor.w a1, a2, (a1) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a2, 255 +; RV32IA-TSO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_minus_1_i8_release: ; RV64I: # %bb.0: @@ -1389,6 +1811,26 @@ define i8 @atomicrmw_xchg_minus_1_i8_release(ptr %a) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a2, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: amoor.w.rl a1, a2, (a1) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a2, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4 @@ -1409,6 +1851,18 @@ define i8 @atomicrmw_xchg_minus_1_i8_release(ptr %a) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: li a1, -1 +; RV32IA-WMO-ZABHA-NEXT: amoswap.b.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: li a1, -1 +; RV32IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: li a1, -1 @@ -1436,25 +1890,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_acq_rel(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a1, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a2, 255 -; RV32IA-WMO-NEXT: sll a2, a2, a0 -; RV32IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a2, 255 +; RV32IA-WMO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a2, (a1) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a1, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a2, 255 -; RV32IA-TSO-NEXT: sll a2, a2, a0 -; RV32IA-TSO-NEXT: amoor.w a1, a2, (a1) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a2, 255 +; RV32IA-TSO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel: ; RV64I: # %bb.0: @@ -1487,6 +1941,26 @@ define i8 @atomicrmw_xchg_minus_1_i8_acq_rel(ptr %a) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a2, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a2, (a1) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a2, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4 @@ -1507,6 +1981,18 @@ define i8 @atomicrmw_xchg_minus_1_i8_acq_rel(ptr %a) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: li a1, -1 +; RV32IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: li a1, -1 +; RV32IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: li a1, -1 @@ -1534,25 +2020,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_seq_cst(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a1, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a2, 255 -; RV32IA-WMO-NEXT: sll a2, a2, a0 -; RV32IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a2, 255 +; RV32IA-WMO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a2, (a1) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a1, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a2, 255 -; RV32IA-TSO-NEXT: sll a2, a2, a0 -; RV32IA-TSO-NEXT: amoor.w a1, a2, (a1) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a2, 255 +; RV32IA-TSO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst: ; RV64I: # %bb.0: @@ -1585,6 +2071,26 @@ define i8 @atomicrmw_xchg_minus_1_i8_seq_cst(ptr %a) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a2, 255 +; RV32IA-WMO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a2, (a1) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a2, 255 +; RV32IA-TSO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4 @@ -1605,6 +2111,18 @@ define i8 @atomicrmw_xchg_minus_1_i8_seq_cst(ptr %a) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: li a1, -1 +; RV32IA-WMO-ZABHA-NEXT: amoswap.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: li a1, -1 +; RV32IA-TSO-ZABHA-NEXT: amoswap.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: li a1, -1 @@ -1631,25 +2149,25 @@ define i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_add_i8_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: li a3, 255 -; RV32IA-NEXT: zext.b a1, a1 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a4, (a2) -; RV32IA-NEXT: add a5, a4, a1 -; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: and a5, a5, a3 -; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB15_1 -; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_add_i8_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: li a3, 255 +; RV32IA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-NOZACAS-NEXT: add a5, a4, a1 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB15_1 +; RV32IA-NOZACAS-NEXT: # %bb.2: +; RV32IA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_add_i8_monotonic: ; RV64I: # %bb.0: @@ -1681,6 +2199,26 @@ define i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_add_i8_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: li a3, 255 +; RV32IA-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-ZACAS-NEXT: add a5, a4, a1 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB15_1 +; RV32IA-ZACAS-NEXT: # %bb.2: +; RV32IA-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_add_i8_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -1701,6 +2239,16 @@ define i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_add_i8_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoadd.b a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_add_i8_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i8_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoadd.b a0, a1, (a0) @@ -1725,45 +2273,45 @@ define i8 @atomicrmw_add_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_add_i8_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a4, (a2) -; RV32IA-WMO-NEXT: add a5, a4, a1 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: and a5, a5, a3 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: sc.w a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB16_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a4, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-NOZACAS-NEXT: add a5, a4, a1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB16_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_add_i8_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a4, (a2) -; RV32IA-TSO-NEXT: add a5, a4, a1 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: and a5, a5, a3 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB16_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a4, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_add_i8_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-NOZACAS-NEXT: add a5, a4, a1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB16_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_add_i8_acquire: ; RV64I: # %bb.0: @@ -1815,6 +2363,46 @@ define i8 @atomicrmw_add_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_add_i8_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-ZACAS-NEXT: add a5, a4, a1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB16_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_add_i8_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZACAS-NEXT: add a5, a4, a1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB16_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_add_i8_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -1855,6 +2443,16 @@ define i8 @atomicrmw_add_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_add_i8_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoadd.b.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_add_i8_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i8_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoadd.b.aq a0, a1, (a0) @@ -1879,45 +2477,45 @@ define i8 @atomicrmw_add_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_add_i8_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w a4, (a2) -; RV32IA-WMO-NEXT: add a5, a4, a1 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: and a5, a5, a3 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB17_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a4, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-WMO-NOZACAS-NEXT: add a5, a4, a1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB17_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_add_i8_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a4, (a2) -; RV32IA-TSO-NEXT: add a5, a4, a1 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: and a5, a5, a3 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB17_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a4, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_add_i8_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-NOZACAS-NEXT: add a5, a4, a1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB17_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_add_i8_release: ; RV64I: # %bb.0: @@ -1969,6 +2567,46 @@ define i8 @atomicrmw_add_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_add_i8_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-WMO-ZACAS-NEXT: add a5, a4, a1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB17_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_add_i8_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZACAS-NEXT: add a5, a4, a1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB17_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_add_i8_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -2009,6 +2647,16 @@ define i8 @atomicrmw_add_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_add_i8_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoadd.b.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_add_i8_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i8_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoadd.b.rl a0, a1, (a0) @@ -2033,45 +2681,45 @@ define i8 @atomicrmw_add_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_add_i8_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a4, (a2) -; RV32IA-WMO-NEXT: add a5, a4, a1 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: and a5, a5, a3 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB18_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a4, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_add_i8_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-NOZACAS-NEXT: add a5, a4, a1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB18_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_add_i8_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a4, (a2) -; RV32IA-TSO-NEXT: add a5, a4, a1 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: and a5, a5, a3 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB18_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a4, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_add_i8_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-NOZACAS-NEXT: add a5, a4, a1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB18_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_add_i8_acq_rel: ; RV64I: # %bb.0: @@ -2123,6 +2771,46 @@ define i8 @atomicrmw_add_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_add_i8_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-ZACAS-NEXT: add a5, a4, a1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB18_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_add_i8_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZACAS-NEXT: add a5, a4, a1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB18_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_add_i8_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -2163,6 +2851,16 @@ define i8 @atomicrmw_add_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_add_i8_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoadd.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_add_i8_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i8_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoadd.b.aqrl a0, a1, (a0) @@ -2187,25 +2885,25 @@ define i8 @atomicrmw_add_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_add_i8_seq_cst: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: li a3, 255 -; RV32IA-NEXT: zext.b a1, a1 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a4, (a2) -; RV32IA-NEXT: add a5, a4, a1 -; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: and a5, a5, a3 -; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB19_1 -; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_add_i8_seq_cst: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: li a3, 255 +; RV32IA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w.aqrl a4, (a2) +; RV32IA-NOZACAS-NEXT: add a5, a4, a1 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB19_1 +; RV32IA-NOZACAS-NEXT: # %bb.2: +; RV32IA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_add_i8_seq_cst: ; RV64I: # %bb.0: @@ -2237,6 +2935,26 @@ define i8 @atomicrmw_add_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_add_i8_seq_cst: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: li a3, 255 +; RV32IA-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w.aqrl a4, (a2) +; RV32IA-ZACAS-NEXT: add a5, a4, a1 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB19_1 +; RV32IA-ZACAS-NEXT: # %bb.2: +; RV32IA-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_add_i8_seq_cst: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -2257,6 +2975,16 @@ define i8 @atomicrmw_add_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_add_i8_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoadd.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_add_i8_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i8_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoadd.b.aqrl a0, a1, (a0) @@ -2281,25 +3009,25 @@ define i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_sub_i8_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: li a3, 255 -; RV32IA-NEXT: zext.b a1, a1 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a4, (a2) -; RV32IA-NEXT: sub a5, a4, a1 -; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: and a5, a5, a3 -; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB20_1 -; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_sub_i8_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: li a3, 255 +; RV32IA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-NOZACAS-NEXT: sub a5, a4, a1 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB20_1 +; RV32IA-NOZACAS-NEXT: # %bb.2: +; RV32IA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_sub_i8_monotonic: ; RV64I: # %bb.0: @@ -2331,6 +3059,26 @@ define i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_sub_i8_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: li a3, 255 +; RV32IA-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-ZACAS-NEXT: sub a5, a4, a1 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB20_1 +; RV32IA-ZACAS-NEXT: # %bb.2: +; RV32IA-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_sub_i8_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -2351,6 +3099,18 @@ define i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_sub_i8_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: neg a1, a1 +; RV32IA-WMO-ZABHA-NEXT: amoadd.b a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_sub_i8_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: neg a1, a1 +; RV32IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i8_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: neg a1, a1 @@ -2377,45 +3137,45 @@ define i8 @atomicrmw_sub_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_sub_i8_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a4, (a2) -; RV32IA-WMO-NEXT: sub a5, a4, a1 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: and a5, a5, a3 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: sc.w a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB21_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a4, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-NOZACAS-NEXT: sub a5, a4, a1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB21_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_sub_i8_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a4, (a2) -; RV32IA-TSO-NEXT: sub a5, a4, a1 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: and a5, a5, a3 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB21_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a4, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_sub_i8_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-NOZACAS-NEXT: sub a5, a4, a1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB21_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_sub_i8_acquire: ; RV64I: # %bb.0: @@ -2467,6 +3227,46 @@ define i8 @atomicrmw_sub_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_sub_i8_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-ZACAS-NEXT: sub a5, a4, a1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB21_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_sub_i8_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZACAS-NEXT: sub a5, a4, a1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB21_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_sub_i8_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -2507,6 +3307,18 @@ define i8 @atomicrmw_sub_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_sub_i8_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: neg a1, a1 +; RV32IA-WMO-ZABHA-NEXT: amoadd.b.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_sub_i8_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: neg a1, a1 +; RV32IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i8_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: neg a1, a1 @@ -2533,45 +3345,45 @@ define i8 @atomicrmw_sub_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_sub_i8_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w a4, (a2) -; RV32IA-WMO-NEXT: sub a5, a4, a1 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: and a5, a5, a3 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB22_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a4, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-WMO-NOZACAS-NEXT: sub a5, a4, a1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB22_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_sub_i8_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a4, (a2) -; RV32IA-TSO-NEXT: sub a5, a4, a1 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: and a5, a5, a3 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB22_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a4, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_sub_i8_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-NOZACAS-NEXT: sub a5, a4, a1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB22_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_sub_i8_release: ; RV64I: # %bb.0: @@ -2623,6 +3435,46 @@ define i8 @atomicrmw_sub_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_sub_i8_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-WMO-ZACAS-NEXT: sub a5, a4, a1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB22_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_sub_i8_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZACAS-NEXT: sub a5, a4, a1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB22_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_sub_i8_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -2663,6 +3515,18 @@ define i8 @atomicrmw_sub_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_sub_i8_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: neg a1, a1 +; RV32IA-WMO-ZABHA-NEXT: amoadd.b.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_sub_i8_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: neg a1, a1 +; RV32IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i8_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: neg a1, a1 @@ -2689,45 +3553,45 @@ define i8 @atomicrmw_sub_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_sub_i8_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a4, (a2) -; RV32IA-WMO-NEXT: sub a5, a4, a1 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: and a5, a5, a3 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB23_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a4, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i8_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-NOZACAS-NEXT: sub a5, a4, a1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB23_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_sub_i8_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a4, (a2) -; RV32IA-TSO-NEXT: sub a5, a4, a1 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: and a5, a5, a3 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB23_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a4, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_sub_i8_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-NOZACAS-NEXT: sub a5, a4, a1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB23_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_sub_i8_acq_rel: ; RV64I: # %bb.0: @@ -2779,6 +3643,46 @@ define i8 @atomicrmw_sub_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_sub_i8_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-ZACAS-NEXT: sub a5, a4, a1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB23_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_sub_i8_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZACAS-NEXT: sub a5, a4, a1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB23_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_sub_i8_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -2819,6 +3723,18 @@ define i8 @atomicrmw_sub_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_sub_i8_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: neg a1, a1 +; RV32IA-WMO-ZABHA-NEXT: amoadd.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_sub_i8_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: neg a1, a1 +; RV32IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i8_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: neg a1, a1 @@ -2845,25 +3761,25 @@ define i8 @atomicrmw_sub_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_sub_i8_seq_cst: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: li a3, 255 -; RV32IA-NEXT: zext.b a1, a1 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a4, (a2) -; RV32IA-NEXT: sub a5, a4, a1 -; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: and a5, a5, a3 -; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB24_1 -; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_sub_i8_seq_cst: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: li a3, 255 +; RV32IA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w.aqrl a4, (a2) +; RV32IA-NOZACAS-NEXT: sub a5, a4, a1 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB24_1 +; RV32IA-NOZACAS-NEXT: # %bb.2: +; RV32IA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_sub_i8_seq_cst: ; RV64I: # %bb.0: @@ -2895,6 +3811,26 @@ define i8 @atomicrmw_sub_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_sub_i8_seq_cst: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: li a3, 255 +; RV32IA-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w.aqrl a4, (a2) +; RV32IA-ZACAS-NEXT: sub a5, a4, a1 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB24_1 +; RV32IA-ZACAS-NEXT: # %bb.2: +; RV32IA-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_sub_i8_seq_cst: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -2915,6 +3851,18 @@ define i8 @atomicrmw_sub_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_sub_i8_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: neg a1, a1 +; RV32IA-WMO-ZABHA-NEXT: amoadd.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_sub_i8_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: neg a1, a1 +; RV32IA-TSO-ZABHA-NEXT: amoadd.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i8_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: neg a1, a1 @@ -2941,19 +3889,19 @@ define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_and_i8_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: li a3, 255 -; RV32IA-NEXT: zext.b a1, a1 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: not a3, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: or a1, a1, a3 -; RV32IA-NEXT: amoand.w a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_and_i8_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: li a3, 255 +; RV32IA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: not a3, a3 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: or a1, a1, a3 +; RV32IA-NOZACAS-NEXT: amoand.w a1, a1, (a2) +; RV32IA-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_and_i8_monotonic: ; RV64I: # %bb.0: @@ -2979,6 +3927,20 @@ define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_and_i8_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: li a3, 255 +; RV32IA-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: not a3, a3 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: or a1, a1, a3 +; RV32IA-ZACAS-NEXT: amoand.w a1, a1, (a2) +; RV32IA-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_and_i8_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -2993,6 +3955,16 @@ define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_and_i8_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoand.b a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_and_i8_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoand.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i8_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoand.b a0, a1, (a0) @@ -3017,33 +3989,33 @@ define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_and_i8_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: not a3, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: or a1, a1, a3 -; RV32IA-WMO-NEXT: amoand.w.aq a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: not a3, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: or a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: amoand.w.aq a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_and_i8_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: not a3, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: or a1, a1, a3 -; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_and_i8_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: not a3, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: or a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_and_i8_acquire: ; RV64I: # %bb.0: @@ -3083,6 +4055,34 @@ define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_and_i8_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: not a3, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: or a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: amoand.w.aq a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_and_i8_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: not a3, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: or a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i8_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -3111,6 +4111,16 @@ define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_and_i8_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoand.b.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_and_i8_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoand.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i8_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoand.b.aq a0, a1, (a0) @@ -3135,33 +4145,33 @@ define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_and_i8_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: not a3, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: or a1, a1, a3 -; RV32IA-WMO-NEXT: amoand.w.rl a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: not a3, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: or a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: amoand.w.rl a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_and_i8_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: not a3, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: or a1, a1, a3 -; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_and_i8_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: not a3, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: or a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_and_i8_release: ; RV64I: # %bb.0: @@ -3201,6 +4211,34 @@ define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_and_i8_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: not a3, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: or a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: amoand.w.rl a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_and_i8_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: not a3, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: or a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i8_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -3229,6 +4267,16 @@ define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_and_i8_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoand.b.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_and_i8_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoand.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i8_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoand.b.rl a0, a1, (a0) @@ -3253,33 +4301,33 @@ define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_and_i8_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: not a3, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: or a1, a1, a3 -; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: not a3, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: or a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_and_i8_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: not a3, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: or a1, a1, a3 -; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_and_i8_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: not a3, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: or a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_and_i8_acq_rel: ; RV64I: # %bb.0: @@ -3319,6 +4367,34 @@ define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_and_i8_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: not a3, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: or a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_and_i8_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: not a3, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: or a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i8_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -3347,6 +4423,16 @@ define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_and_i8_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoand.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_and_i8_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoand.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i8_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoand.b.aqrl a0, a1, (a0) @@ -3371,33 +4457,33 @@ define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_and_i8_seq_cst: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: not a3, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: or a1, a1, a3 -; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i8_seq_cst: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: not a3, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: or a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_and_i8_seq_cst: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: not a3, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: or a1, a1, a3 -; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_and_i8_seq_cst: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: not a3, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: or a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_and_i8_seq_cst: ; RV64I: # %bb.0: @@ -3437,6 +4523,34 @@ define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_and_i8_seq_cst: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: not a3, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: or a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_and_i8_seq_cst: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: not a3, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: or a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i8_seq_cst: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -3465,6 +4579,16 @@ define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_and_i8_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoand.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_and_i8_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoand.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i8_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoand.b.aqrl a0, a1, (a0) @@ -3489,26 +4613,26 @@ define i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_nand_i8_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: li a3, 255 -; RV32IA-NEXT: zext.b a1, a1 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a4, (a2) -; RV32IA-NEXT: and a5, a4, a1 -; RV32IA-NEXT: not a5, a5 -; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: and a5, a5, a3 -; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB30_1 -; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_nand_i8_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: li a3, 255 +; RV32IA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-NOZACAS-NEXT: and a5, a4, a1 +; RV32IA-NOZACAS-NEXT: not a5, a5 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB30_1 +; RV32IA-NOZACAS-NEXT: # %bb.2: +; RV32IA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_nand_i8_monotonic: ; RV64I: # %bb.0: @@ -3541,6 +4665,27 @@ define i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_nand_i8_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: li a3, 255 +; RV32IA-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-ZACAS-NEXT: and a5, a4, a1 +; RV32IA-ZACAS-NEXT: not a5, a5 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB30_1 +; RV32IA-ZACAS-NEXT: # %bb.2: +; RV32IA-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_nand_i8_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -3562,6 +4707,48 @@ define i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_monotonic: +; RV32IA-WMO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a4, a1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB30_1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_monotonic: +; RV32IA-TSO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a4, a1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB30_1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_monotonic: ; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 @@ -3604,6 +4791,36 @@ define i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_monotonic: +; RV32IA-WMO-ZABHA-ZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: .LBB30_1: # %atomicrmw.start +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 24 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: amocas.b a0, a3, (a2) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 24 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB30_1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-WMO-ZABHA-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_monotonic: +; RV32IA-TSO-ZABHA-ZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: .LBB30_1: # %atomicrmw.start +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 24 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: amocas.b a0, a3, (a2) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 24 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB30_1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-TSO-ZABHA-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_monotonic: ; RV64IA-WMO-ZABHA-ZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 @@ -3648,47 +4865,47 @@ define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_nand_i8_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a4, (a2) -; RV32IA-WMO-NEXT: and a5, a4, a1 -; RV32IA-WMO-NEXT: not a5, a5 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: and a5, a5, a3 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: sc.w a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB31_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a4, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a5, a4, a1 +; RV32IA-WMO-NOZACAS-NEXT: not a5, a5 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB31_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_nand_i8_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a4, (a2) -; RV32IA-TSO-NEXT: and a5, a4, a1 -; RV32IA-TSO-NEXT: not a5, a5 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: and a5, a5, a3 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB31_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a4, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_nand_i8_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a5, a4, a1 +; RV32IA-TSO-NOZACAS-NEXT: not a5, a5 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB31_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_nand_i8_acquire: ; RV64I: # %bb.0: @@ -3742,6 +4959,48 @@ define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_nand_i8_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a5, a4, a1 +; RV32IA-WMO-ZACAS-NEXT: not a5, a5 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB31_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_nand_i8_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a5, a4, a1 +; RV32IA-TSO-ZACAS-NEXT: not a5, a5 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB31_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_nand_i8_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -3784,6 +5043,48 @@ define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_acquire: +; RV32IA-WMO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a4, a1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB31_1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_acquire: +; RV32IA-TSO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a4, a1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB31_1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_acquire: ; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 @@ -3826,6 +5127,36 @@ define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_acquire: +; RV32IA-WMO-ZABHA-ZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: .LBB31_1: # %atomicrmw.start +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 24 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: amocas.b.aq a0, a3, (a2) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 24 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB31_1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-WMO-ZABHA-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_acquire: +; RV32IA-TSO-ZABHA-ZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: .LBB31_1: # %atomicrmw.start +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 24 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: amocas.b a0, a3, (a2) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 24 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB31_1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-TSO-ZABHA-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_acquire: ; RV64IA-WMO-ZABHA-ZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 @@ -3870,47 +5201,47 @@ define i8 @atomicrmw_nand_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_nand_i8_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w a4, (a2) -; RV32IA-WMO-NEXT: and a5, a4, a1 -; RV32IA-WMO-NEXT: not a5, a5 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: and a5, a5, a3 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB32_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a4, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a5, a4, a1 +; RV32IA-WMO-NOZACAS-NEXT: not a5, a5 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB32_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_nand_i8_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a4, (a2) -; RV32IA-TSO-NEXT: and a5, a4, a1 -; RV32IA-TSO-NEXT: not a5, a5 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: and a5, a5, a3 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB32_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a4, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_nand_i8_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a5, a4, a1 +; RV32IA-TSO-NOZACAS-NEXT: not a5, a5 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB32_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_nand_i8_release: ; RV64I: # %bb.0: @@ -3964,6 +5295,48 @@ define i8 @atomicrmw_nand_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_nand_i8_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a5, a4, a1 +; RV32IA-WMO-ZACAS-NEXT: not a5, a5 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB32_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_nand_i8_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a5, a4, a1 +; RV32IA-TSO-ZACAS-NEXT: not a5, a5 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB32_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_nand_i8_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -4006,6 +5379,48 @@ define i8 @atomicrmw_nand_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_release: +; RV32IA-WMO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a4, a1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB32_1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_release: +; RV32IA-TSO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a4, a1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB32_1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_release: ; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 @@ -4048,6 +5463,36 @@ define i8 @atomicrmw_nand_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_release: +; RV32IA-WMO-ZABHA-ZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: .LBB32_1: # %atomicrmw.start +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 24 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: amocas.b.rl a0, a3, (a2) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 24 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB32_1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-WMO-ZABHA-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_release: +; RV32IA-TSO-ZABHA-ZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: .LBB32_1: # %atomicrmw.start +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 24 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: amocas.b a0, a3, (a2) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 24 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB32_1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-TSO-ZABHA-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_release: ; RV64IA-WMO-ZABHA-ZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 @@ -4092,47 +5537,47 @@ define i8 @atomicrmw_nand_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_nand_i8_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a4, (a2) -; RV32IA-WMO-NEXT: and a5, a4, a1 -; RV32IA-WMO-NEXT: not a5, a5 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: and a5, a5, a3 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB33_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a4, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i8_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a5, a4, a1 +; RV32IA-WMO-NOZACAS-NEXT: not a5, a5 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB33_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_nand_i8_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a4, (a2) -; RV32IA-TSO-NEXT: and a5, a4, a1 -; RV32IA-TSO-NEXT: not a5, a5 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: and a5, a5, a3 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB33_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a4, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_nand_i8_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a5, a4, a1 +; RV32IA-TSO-NOZACAS-NEXT: not a5, a5 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB33_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_nand_i8_acq_rel: ; RV64I: # %bb.0: @@ -4186,6 +5631,48 @@ define i8 @atomicrmw_nand_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_nand_i8_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a5, a4, a1 +; RV32IA-WMO-ZACAS-NEXT: not a5, a5 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB33_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_nand_i8_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a5, a4, a1 +; RV32IA-TSO-ZACAS-NEXT: not a5, a5 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB33_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_nand_i8_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -4228,6 +5715,48 @@ define i8 @atomicrmw_nand_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_acq_rel: +; RV32IA-WMO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a4, a1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB33_1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_acq_rel: +; RV32IA-TSO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a4, a1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB33_1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_acq_rel: ; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 @@ -4270,6 +5799,36 @@ define i8 @atomicrmw_nand_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_acq_rel: +; RV32IA-WMO-ZABHA-ZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: .LBB33_1: # %atomicrmw.start +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 24 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: amocas.b.aqrl a0, a3, (a2) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 24 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB33_1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-WMO-ZABHA-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_acq_rel: +; RV32IA-TSO-ZABHA-ZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: .LBB33_1: # %atomicrmw.start +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 24 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: amocas.b a0, a3, (a2) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 24 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB33_1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-TSO-ZABHA-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_acq_rel: ; RV64IA-WMO-ZABHA-ZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 @@ -4314,26 +5873,26 @@ define i8 @atomicrmw_nand_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_nand_i8_seq_cst: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: li a3, 255 -; RV32IA-NEXT: zext.b a1, a1 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a4, (a2) -; RV32IA-NEXT: and a5, a4, a1 -; RV32IA-NEXT: not a5, a5 -; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: and a5, a5, a3 -; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB34_1 -; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a4, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_nand_i8_seq_cst: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: li a3, 255 +; RV32IA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w.aqrl a4, (a2) +; RV32IA-NOZACAS-NEXT: and a5, a4, a1 +; RV32IA-NOZACAS-NEXT: not a5, a5 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB34_1 +; RV32IA-NOZACAS-NEXT: # %bb.2: +; RV32IA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_nand_i8_seq_cst: ; RV64I: # %bb.0: @@ -4366,6 +5925,27 @@ define i8 @atomicrmw_nand_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_nand_i8_seq_cst: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: li a3, 255 +; RV32IA-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w.aqrl a4, (a2) +; RV32IA-ZACAS-NEXT: and a5, a4, a1 +; RV32IA-ZACAS-NEXT: not a5, a5 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB34_1 +; RV32IA-ZACAS-NEXT: # %bb.2: +; RV32IA-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_nand_i8_seq_cst: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -4387,6 +5967,48 @@ define i8 @atomicrmw_nand_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_seq_cst: +; RV32IA-WMO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aqrl a4, (a2) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a4, a1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB34_1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_seq_cst: +; RV32IA-TSO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: lr.w.aqrl a4, (a2) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a4, a1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB34_1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i8_seq_cst: ; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 @@ -4429,6 +6051,38 @@ define i8 @atomicrmw_nand_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_seq_cst: +; RV32IA-WMO-ZABHA-ZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: .LBB34_1: # %atomicrmw.start +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: fence rw, rw +; RV32IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 24 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: amocas.b.aqrl a0, a3, (a2) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 24 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB34_1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-WMO-ZABHA-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_seq_cst: +; RV32IA-TSO-ZABHA-ZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: lbu a0, 0(a0) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: .LBB34_1: # %atomicrmw.start +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: fence rw, rw +; RV32IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 24 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: amocas.b a0, a3, (a2) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 24 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB34_1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-TSO-ZABHA-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i8_seq_cst: ; RV64IA-WMO-ZABHA-ZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 @@ -4475,15 +6129,15 @@ define i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_or_i8_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: zext.b a1, a1 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoor.w a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_or_i8_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: amoor.w a1, a1, (a2) +; RV32IA-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_or_i8_monotonic: ; RV64I: # %bb.0: @@ -4505,6 +6159,16 @@ define i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_or_i8_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: amoor.w a1, a1, (a2) +; RV32IA-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_or_i8_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -4515,6 +6179,16 @@ define i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_or_i8_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoor.b a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_or_i8_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoor.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i8_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoor.b a0, a1, (a0) @@ -4539,25 +6213,25 @@ define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_or_i8_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: amoor.w.aq a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoor.w.aq a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_or_i8_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: amoor.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_or_i8_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_or_i8_acquire: ; RV64I: # %bb.0: @@ -4589,6 +6263,26 @@ define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_or_i8_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: amoor.w.aq a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_or_i8_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i8_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -4609,6 +6303,16 @@ define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_or_i8_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoor.b.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_or_i8_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoor.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i8_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoor.b.aq a0, a1, (a0) @@ -4633,25 +6337,25 @@ define i8 @atomicrmw_or_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_or_i8_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: amoor.w.rl a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoor.w.rl a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_or_i8_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: amoor.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_or_i8_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_or_i8_release: ; RV64I: # %bb.0: @@ -4683,6 +6387,26 @@ define i8 @atomicrmw_or_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_or_i8_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: amoor.w.rl a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_or_i8_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i8_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -4703,6 +6427,16 @@ define i8 @atomicrmw_or_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_or_i8_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoor.b.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_or_i8_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoor.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i8_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoor.b.rl a0, a1, (a0) @@ -4727,25 +6461,25 @@ define i8 @atomicrmw_or_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_or_i8_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: amoor.w.aqrl a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_or_i8_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: amoor.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_or_i8_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_or_i8_acq_rel: ; RV64I: # %bb.0: @@ -4777,6 +6511,26 @@ define i8 @atomicrmw_or_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_or_i8_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_or_i8_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i8_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -4797,6 +6551,16 @@ define i8 @atomicrmw_or_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_or_i8_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoor.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_or_i8_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoor.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i8_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoor.b.aqrl a0, a1, (a0) @@ -4821,25 +6585,25 @@ define i8 @atomicrmw_or_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_or_i8_seq_cst: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: amoor.w.aqrl a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i8_seq_cst: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_or_i8_seq_cst: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: amoor.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_or_i8_seq_cst: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_or_i8_seq_cst: ; RV64I: # %bb.0: @@ -4871,6 +6635,26 @@ define i8 @atomicrmw_or_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_or_i8_seq_cst: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_or_i8_seq_cst: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i8_seq_cst: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -4891,6 +6675,16 @@ define i8 @atomicrmw_or_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_or_i8_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoor.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_or_i8_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoor.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i8_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoor.b.aqrl a0, a1, (a0) @@ -4915,15 +6709,15 @@ define i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_xor_i8_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: zext.b a1, a1 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoxor.w a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_xor_i8_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: amoxor.w a1, a1, (a2) +; RV32IA-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xor_i8_monotonic: ; RV64I: # %bb.0: @@ -4945,6 +6739,16 @@ define i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_xor_i8_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: amoxor.w a1, a1, (a2) +; RV32IA-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_xor_i8_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -4955,6 +6759,16 @@ define i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xor_i8_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoxor.b a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xor_i8_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoxor.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i8_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoxor.b a0, a1, (a0) @@ -4979,25 +6793,25 @@ define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xor_i8_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: amoxor.w.aq a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoxor.w.aq a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xor_i8_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: amoxor.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i8_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xor_i8_acquire: ; RV64I: # %bb.0: @@ -5029,6 +6843,26 @@ define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xor_i8_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: amoxor.w.aq a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xor_i8_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i8_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -5049,6 +6883,16 @@ define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xor_i8_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoxor.b.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xor_i8_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoxor.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i8_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoxor.b.aq a0, a1, (a0) @@ -5073,25 +6917,25 @@ define i8 @atomicrmw_xor_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xor_i8_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: amoxor.w.rl a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoxor.w.rl a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xor_i8_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: amoxor.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i8_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xor_i8_release: ; RV64I: # %bb.0: @@ -5123,6 +6967,26 @@ define i8 @atomicrmw_xor_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xor_i8_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: amoxor.w.rl a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xor_i8_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i8_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -5143,6 +7007,16 @@ define i8 @atomicrmw_xor_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xor_i8_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoxor.b.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xor_i8_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoxor.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i8_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoxor.b.rl a0, a1, (a0) @@ -5167,25 +7041,25 @@ define i8 @atomicrmw_xor_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xor_i8_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: amoxor.w.aqrl a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xor_i8_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: amoxor.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i8_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xor_i8_acq_rel: ; RV64I: # %bb.0: @@ -5217,6 +7091,26 @@ define i8 @atomicrmw_xor_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xor_i8_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xor_i8_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i8_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -5237,6 +7131,16 @@ define i8 @atomicrmw_xor_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xor_i8_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoxor.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xor_i8_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoxor.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i8_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoxor.b.aqrl a0, a1, (a0) @@ -5261,25 +7165,25 @@ define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xor_i8_seq_cst: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: amoxor.w.aqrl a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i8_seq_cst: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xor_i8_seq_cst: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: amoxor.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i8_seq_cst: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xor_i8_seq_cst: ; RV64I: # %bb.0: @@ -5311,6 +7215,26 @@ define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xor_i8_seq_cst: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xor_i8_seq_cst: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i8_seq_cst: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -5331,6 +7255,16 @@ define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xor_i8_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoxor.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xor_i8_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoxor.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i8_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoxor.b.aqrl a0, a1, (a0) @@ -5387,34 +7321,34 @@ define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_max_i8_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: li a3, 255 -; RV32IA-NEXT: slli a1, a1, 24 -; RV32IA-NEXT: andi a4, a0, 24 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: srai a1, a1, 24 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: xori a4, a4, 24 -; RV32IA-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a5, (a2) -; RV32IA-NEXT: and a7, a5, a3 -; RV32IA-NEXT: mv a6, a5 -; RV32IA-NEXT: sll a7, a7, a4 -; RV32IA-NEXT: sra a7, a7, a4 -; RV32IA-NEXT: bge a7, a1, .LBB45_3 -; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1 -; RV32IA-NEXT: xor a6, a5, a1 -; RV32IA-NEXT: and a6, a6, a3 -; RV32IA-NEXT: xor a6, a5, a6 -; RV32IA-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1 -; RV32IA-NEXT: sc.w a6, a6, (a2) -; RV32IA-NEXT: bnez a6, .LBB45_1 -; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_max_i8_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: li a3, 255 +; RV32IA-NOZACAS-NEXT: slli a1, a1, 24 +; RV32IA-NOZACAS-NEXT: andi a4, a0, 24 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: srai a1, a1, 24 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: xori a4, a4, 24 +; RV32IA-NOZACAS-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w a5, (a2) +; RV32IA-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-NOZACAS-NEXT: mv a6, a5 +; RV32IA-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-NOZACAS-NEXT: bge a7, a1, .LBB45_3 +; RV32IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1 +; RV32IA-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-NOZACAS-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1 +; RV32IA-NOZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-NOZACAS-NEXT: bnez a6, .LBB45_1 +; RV32IA-NOZACAS-NEXT: # %bb.4: +; RV32IA-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i8_monotonic: ; RV64I: # %bb.0: @@ -5487,6 +7421,35 @@ define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_max_i8_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: li a3, 255 +; RV32IA-ZACAS-NEXT: slli a1, a1, 24 +; RV32IA-ZACAS-NEXT: andi a4, a0, 24 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: srai a1, a1, 24 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: xori a4, a4, 24 +; RV32IA-ZACAS-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w a5, (a2) +; RV32IA-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-ZACAS-NEXT: mv a6, a5 +; RV32IA-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-ZACAS-NEXT: bge a7, a1, .LBB45_3 +; RV32IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1 +; RV32IA-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-ZACAS-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1 +; RV32IA-ZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-ZACAS-NEXT: bnez a6, .LBB45_1 +; RV32IA-ZACAS-NEXT: # %bb.4: +; RV32IA-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_max_i8_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -5516,6 +7479,16 @@ define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_max_i8_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomax.b a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_max_i8_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomax.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i8_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomax.b a0, a1, (a0) @@ -5572,63 +7545,63 @@ define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_max_i8_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: slli a1, a1, 24 -; RV32IA-WMO-NEXT: andi a4, a0, 24 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: srai a1, a1, 24 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: xori a4, a4, 24 -; RV32IA-WMO-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a5, (a2) -; RV32IA-WMO-NEXT: and a7, a5, a3 -; RV32IA-WMO-NEXT: mv a6, a5 -; RV32IA-WMO-NEXT: sll a7, a7, a4 -; RV32IA-WMO-NEXT: sra a7, a7, a4 -; RV32IA-WMO-NEXT: bge a7, a1, .LBB46_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1 -; RV32IA-WMO-NEXT: xor a6, a5, a1 -; RV32IA-WMO-NEXT: and a6, a6, a3 -; RV32IA-WMO-NEXT: xor a6, a5, a6 -; RV32IA-WMO-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w a6, a6, (a2) -; RV32IA-WMO-NEXT: bnez a6, .LBB46_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a5, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: slli a1, a1, 24 +; RV32IA-WMO-NOZACAS-NEXT: andi a4, a0, 24 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: srai a1, a1, 24 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: xori a4, a4, 24 +; RV32IA-WMO-NOZACAS-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: bge a7, a1, .LBB46_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-NOZACAS-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a6, .LBB46_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_max_i8_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: slli a1, a1, 24 -; RV32IA-TSO-NEXT: andi a4, a0, 24 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: srai a1, a1, 24 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: xori a4, a4, 24 -; RV32IA-TSO-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a5, (a2) -; RV32IA-TSO-NEXT: and a7, a5, a3 -; RV32IA-TSO-NEXT: mv a6, a5 -; RV32IA-TSO-NEXT: sll a7, a7, a4 -; RV32IA-TSO-NEXT: sra a7, a7, a4 -; RV32IA-TSO-NEXT: bge a7, a1, .LBB46_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1 -; RV32IA-TSO-NEXT: xor a6, a5, a1 -; RV32IA-TSO-NEXT: and a6, a6, a3 -; RV32IA-TSO-NEXT: xor a6, a5, a6 -; RV32IA-TSO-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a6, a6, (a2) -; RV32IA-TSO-NEXT: bnez a6, .LBB46_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a5, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_max_i8_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: slli a1, a1, 24 +; RV32IA-TSO-NOZACAS-NEXT: andi a4, a0, 24 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: srai a1, a1, 24 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: xori a4, a4, 24 +; RV32IA-TSO-NOZACAS-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: bge a7, a1, .LBB46_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-NOZACAS-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a6, .LBB46_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i8_acquire: ; RV64I: # %bb.0: @@ -5730,6 +7703,64 @@ define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_max_i8_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: slli a1, a1, 24 +; RV32IA-WMO-ZACAS-NEXT: andi a4, a0, 24 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: srai a1, a1, 24 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: xori a4, a4, 24 +; RV32IA-WMO-ZACAS-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: bge a7, a1, .LBB46_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-ZACAS-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a6, .LBB46_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_max_i8_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: slli a1, a1, 24 +; RV32IA-TSO-ZACAS-NEXT: andi a4, a0, 24 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: srai a1, a1, 24 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: xori a4, a4, 24 +; RV32IA-TSO-ZACAS-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: bge a7, a1, .LBB46_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-ZACAS-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a6, .LBB46_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_max_i8_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -5788,6 +7819,16 @@ define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_max_i8_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomax.b.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_max_i8_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomax.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i8_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomax.b.aq a0, a1, (a0) @@ -5844,63 +7885,63 @@ define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_max_i8_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: slli a1, a1, 24 -; RV32IA-WMO-NEXT: andi a4, a0, 24 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: srai a1, a1, 24 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: xori a4, a4, 24 -; RV32IA-WMO-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w a5, (a2) -; RV32IA-WMO-NEXT: and a7, a5, a3 -; RV32IA-WMO-NEXT: mv a6, a5 -; RV32IA-WMO-NEXT: sll a7, a7, a4 -; RV32IA-WMO-NEXT: sra a7, a7, a4 -; RV32IA-WMO-NEXT: bge a7, a1, .LBB47_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1 -; RV32IA-WMO-NEXT: xor a6, a5, a1 -; RV32IA-WMO-NEXT: and a6, a6, a3 -; RV32IA-WMO-NEXT: xor a6, a5, a6 -; RV32IA-WMO-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w.rl a6, a6, (a2) -; RV32IA-WMO-NEXT: bnez a6, .LBB47_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a5, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: slli a1, a1, 24 +; RV32IA-WMO-NOZACAS-NEXT: andi a4, a0, 24 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: srai a1, a1, 24 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: xori a4, a4, 24 +; RV32IA-WMO-NOZACAS-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: bge a7, a1, .LBB47_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-NOZACAS-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a6, .LBB47_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_max_i8_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: slli a1, a1, 24 -; RV32IA-TSO-NEXT: andi a4, a0, 24 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: srai a1, a1, 24 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: xori a4, a4, 24 -; RV32IA-TSO-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a5, (a2) -; RV32IA-TSO-NEXT: and a7, a5, a3 -; RV32IA-TSO-NEXT: mv a6, a5 -; RV32IA-TSO-NEXT: sll a7, a7, a4 -; RV32IA-TSO-NEXT: sra a7, a7, a4 -; RV32IA-TSO-NEXT: bge a7, a1, .LBB47_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1 -; RV32IA-TSO-NEXT: xor a6, a5, a1 -; RV32IA-TSO-NEXT: and a6, a6, a3 -; RV32IA-TSO-NEXT: xor a6, a5, a6 -; RV32IA-TSO-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a6, a6, (a2) -; RV32IA-TSO-NEXT: bnez a6, .LBB47_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a5, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_max_i8_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: slli a1, a1, 24 +; RV32IA-TSO-NOZACAS-NEXT: andi a4, a0, 24 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: srai a1, a1, 24 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: xori a4, a4, 24 +; RV32IA-TSO-NOZACAS-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: bge a7, a1, .LBB47_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-NOZACAS-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a6, .LBB47_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i8_release: ; RV64I: # %bb.0: @@ -6002,6 +8043,64 @@ define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_max_i8_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: slli a1, a1, 24 +; RV32IA-WMO-ZACAS-NEXT: andi a4, a0, 24 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: srai a1, a1, 24 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: xori a4, a4, 24 +; RV32IA-WMO-ZACAS-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: bge a7, a1, .LBB47_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-ZACAS-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a6, .LBB47_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_max_i8_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: slli a1, a1, 24 +; RV32IA-TSO-ZACAS-NEXT: andi a4, a0, 24 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: srai a1, a1, 24 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: xori a4, a4, 24 +; RV32IA-TSO-ZACAS-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: bge a7, a1, .LBB47_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-ZACAS-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a6, .LBB47_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_max_i8_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -6060,6 +8159,16 @@ define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_max_i8_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomax.b.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_max_i8_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomax.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i8_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomax.b.rl a0, a1, (a0) @@ -6116,63 +8225,63 @@ define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_max_i8_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: slli a1, a1, 24 -; RV32IA-WMO-NEXT: andi a4, a0, 24 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: srai a1, a1, 24 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: xori a4, a4, 24 -; RV32IA-WMO-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a5, (a2) -; RV32IA-WMO-NEXT: and a7, a5, a3 -; RV32IA-WMO-NEXT: mv a6, a5 -; RV32IA-WMO-NEXT: sll a7, a7, a4 -; RV32IA-WMO-NEXT: sra a7, a7, a4 -; RV32IA-WMO-NEXT: bge a7, a1, .LBB48_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1 -; RV32IA-WMO-NEXT: xor a6, a5, a1 -; RV32IA-WMO-NEXT: and a6, a6, a3 -; RV32IA-WMO-NEXT: xor a6, a5, a6 -; RV32IA-WMO-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w.rl a6, a6, (a2) -; RV32IA-WMO-NEXT: bnez a6, .LBB48_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a5, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_max_i8_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: slli a1, a1, 24 +; RV32IA-WMO-NOZACAS-NEXT: andi a4, a0, 24 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: srai a1, a1, 24 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: xori a4, a4, 24 +; RV32IA-WMO-NOZACAS-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: bge a7, a1, .LBB48_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-NOZACAS-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a6, .LBB48_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_max_i8_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: slli a1, a1, 24 -; RV32IA-TSO-NEXT: andi a4, a0, 24 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: srai a1, a1, 24 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: xori a4, a4, 24 -; RV32IA-TSO-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a5, (a2) -; RV32IA-TSO-NEXT: and a7, a5, a3 -; RV32IA-TSO-NEXT: mv a6, a5 -; RV32IA-TSO-NEXT: sll a7, a7, a4 -; RV32IA-TSO-NEXT: sra a7, a7, a4 -; RV32IA-TSO-NEXT: bge a7, a1, .LBB48_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1 -; RV32IA-TSO-NEXT: xor a6, a5, a1 -; RV32IA-TSO-NEXT: and a6, a6, a3 -; RV32IA-TSO-NEXT: xor a6, a5, a6 -; RV32IA-TSO-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a6, a6, (a2) -; RV32IA-TSO-NEXT: bnez a6, .LBB48_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a5, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_max_i8_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: slli a1, a1, 24 +; RV32IA-TSO-NOZACAS-NEXT: andi a4, a0, 24 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: srai a1, a1, 24 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: xori a4, a4, 24 +; RV32IA-TSO-NOZACAS-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: bge a7, a1, .LBB48_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-NOZACAS-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a6, .LBB48_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i8_acq_rel: ; RV64I: # %bb.0: @@ -6274,6 +8383,64 @@ define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_max_i8_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: slli a1, a1, 24 +; RV32IA-WMO-ZACAS-NEXT: andi a4, a0, 24 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: srai a1, a1, 24 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: xori a4, a4, 24 +; RV32IA-WMO-ZACAS-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: bge a7, a1, .LBB48_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-ZACAS-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a6, .LBB48_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_max_i8_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: slli a1, a1, 24 +; RV32IA-TSO-ZACAS-NEXT: andi a4, a0, 24 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: srai a1, a1, 24 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: xori a4, a4, 24 +; RV32IA-TSO-ZACAS-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: bge a7, a1, .LBB48_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-ZACAS-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a6, .LBB48_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_max_i8_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -6332,6 +8499,16 @@ define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_max_i8_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomax.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_max_i8_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomax.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i8_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomax.b.aqrl a0, a1, (a0) @@ -6388,34 +8565,34 @@ define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_max_i8_seq_cst: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: li a3, 255 -; RV32IA-NEXT: slli a1, a1, 24 -; RV32IA-NEXT: andi a4, a0, 24 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: srai a1, a1, 24 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: xori a4, a4, 24 -; RV32IA-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a5, (a2) -; RV32IA-NEXT: and a7, a5, a3 -; RV32IA-NEXT: mv a6, a5 -; RV32IA-NEXT: sll a7, a7, a4 -; RV32IA-NEXT: sra a7, a7, a4 -; RV32IA-NEXT: bge a7, a1, .LBB49_3 -; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1 -; RV32IA-NEXT: xor a6, a5, a1 -; RV32IA-NEXT: and a6, a6, a3 -; RV32IA-NEXT: xor a6, a5, a6 -; RV32IA-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a6, a6, (a2) -; RV32IA-NEXT: bnez a6, .LBB49_1 -; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_max_i8_seq_cst: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: li a3, 255 +; RV32IA-NOZACAS-NEXT: slli a1, a1, 24 +; RV32IA-NOZACAS-NEXT: andi a4, a0, 24 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: srai a1, a1, 24 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: xori a4, a4, 24 +; RV32IA-NOZACAS-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w.aqrl a5, (a2) +; RV32IA-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-NOZACAS-NEXT: mv a6, a5 +; RV32IA-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-NOZACAS-NEXT: bge a7, a1, .LBB49_3 +; RV32IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1 +; RV32IA-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-NOZACAS-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1 +; RV32IA-NOZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-NOZACAS-NEXT: bnez a6, .LBB49_1 +; RV32IA-NOZACAS-NEXT: # %bb.4: +; RV32IA-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i8_seq_cst: ; RV64I: # %bb.0: @@ -6488,6 +8665,35 @@ define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_max_i8_seq_cst: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: li a3, 255 +; RV32IA-ZACAS-NEXT: slli a1, a1, 24 +; RV32IA-ZACAS-NEXT: andi a4, a0, 24 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: srai a1, a1, 24 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: xori a4, a4, 24 +; RV32IA-ZACAS-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w.aqrl a5, (a2) +; RV32IA-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-ZACAS-NEXT: mv a6, a5 +; RV32IA-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-ZACAS-NEXT: bge a7, a1, .LBB49_3 +; RV32IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1 +; RV32IA-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-ZACAS-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1 +; RV32IA-ZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-ZACAS-NEXT: bnez a6, .LBB49_1 +; RV32IA-ZACAS-NEXT: # %bb.4: +; RV32IA-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_max_i8_seq_cst: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -6517,6 +8723,16 @@ define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_max_i8_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomax.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_max_i8_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomax.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i8_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomax.b.aqrl a0, a1, (a0) @@ -6573,34 +8789,34 @@ define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_min_i8_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: li a3, 255 -; RV32IA-NEXT: slli a1, a1, 24 -; RV32IA-NEXT: andi a4, a0, 24 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: srai a1, a1, 24 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: xori a4, a4, 24 -; RV32IA-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a5, (a2) -; RV32IA-NEXT: and a7, a5, a3 -; RV32IA-NEXT: mv a6, a5 -; RV32IA-NEXT: sll a7, a7, a4 -; RV32IA-NEXT: sra a7, a7, a4 -; RV32IA-NEXT: bge a1, a7, .LBB50_3 -; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1 -; RV32IA-NEXT: xor a6, a5, a1 -; RV32IA-NEXT: and a6, a6, a3 -; RV32IA-NEXT: xor a6, a5, a6 -; RV32IA-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1 -; RV32IA-NEXT: sc.w a6, a6, (a2) -; RV32IA-NEXT: bnez a6, .LBB50_1 -; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_min_i8_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: li a3, 255 +; RV32IA-NOZACAS-NEXT: slli a1, a1, 24 +; RV32IA-NOZACAS-NEXT: andi a4, a0, 24 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: srai a1, a1, 24 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: xori a4, a4, 24 +; RV32IA-NOZACAS-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w a5, (a2) +; RV32IA-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-NOZACAS-NEXT: mv a6, a5 +; RV32IA-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-NOZACAS-NEXT: bge a1, a7, .LBB50_3 +; RV32IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1 +; RV32IA-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-NOZACAS-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1 +; RV32IA-NOZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-NOZACAS-NEXT: bnez a6, .LBB50_1 +; RV32IA-NOZACAS-NEXT: # %bb.4: +; RV32IA-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i8_monotonic: ; RV64I: # %bb.0: @@ -6673,6 +8889,35 @@ define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_min_i8_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: li a3, 255 +; RV32IA-ZACAS-NEXT: slli a1, a1, 24 +; RV32IA-ZACAS-NEXT: andi a4, a0, 24 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: srai a1, a1, 24 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: xori a4, a4, 24 +; RV32IA-ZACAS-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w a5, (a2) +; RV32IA-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-ZACAS-NEXT: mv a6, a5 +; RV32IA-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-ZACAS-NEXT: bge a1, a7, .LBB50_3 +; RV32IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1 +; RV32IA-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-ZACAS-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1 +; RV32IA-ZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-ZACAS-NEXT: bnez a6, .LBB50_1 +; RV32IA-ZACAS-NEXT: # %bb.4: +; RV32IA-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_min_i8_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -6702,6 +8947,16 @@ define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_min_i8_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomin.b a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_min_i8_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomin.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i8_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomin.b a0, a1, (a0) @@ -6758,63 +9013,63 @@ define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_min_i8_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: slli a1, a1, 24 -; RV32IA-WMO-NEXT: andi a4, a0, 24 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: srai a1, a1, 24 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: xori a4, a4, 24 -; RV32IA-WMO-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a5, (a2) -; RV32IA-WMO-NEXT: and a7, a5, a3 -; RV32IA-WMO-NEXT: mv a6, a5 -; RV32IA-WMO-NEXT: sll a7, a7, a4 -; RV32IA-WMO-NEXT: sra a7, a7, a4 -; RV32IA-WMO-NEXT: bge a1, a7, .LBB51_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1 -; RV32IA-WMO-NEXT: xor a6, a5, a1 -; RV32IA-WMO-NEXT: and a6, a6, a3 -; RV32IA-WMO-NEXT: xor a6, a5, a6 -; RV32IA-WMO-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w a6, a6, (a2) -; RV32IA-WMO-NEXT: bnez a6, .LBB51_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a5, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: slli a1, a1, 24 +; RV32IA-WMO-NOZACAS-NEXT: andi a4, a0, 24 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: srai a1, a1, 24 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: xori a4, a4, 24 +; RV32IA-WMO-NOZACAS-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: bge a1, a7, .LBB51_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-NOZACAS-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a6, .LBB51_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_min_i8_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: slli a1, a1, 24 -; RV32IA-TSO-NEXT: andi a4, a0, 24 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: srai a1, a1, 24 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: xori a4, a4, 24 -; RV32IA-TSO-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a5, (a2) -; RV32IA-TSO-NEXT: and a7, a5, a3 -; RV32IA-TSO-NEXT: mv a6, a5 -; RV32IA-TSO-NEXT: sll a7, a7, a4 -; RV32IA-TSO-NEXT: sra a7, a7, a4 -; RV32IA-TSO-NEXT: bge a1, a7, .LBB51_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1 -; RV32IA-TSO-NEXT: xor a6, a5, a1 -; RV32IA-TSO-NEXT: and a6, a6, a3 -; RV32IA-TSO-NEXT: xor a6, a5, a6 -; RV32IA-TSO-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a6, a6, (a2) -; RV32IA-TSO-NEXT: bnez a6, .LBB51_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a5, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_min_i8_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: slli a1, a1, 24 +; RV32IA-TSO-NOZACAS-NEXT: andi a4, a0, 24 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: srai a1, a1, 24 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: xori a4, a4, 24 +; RV32IA-TSO-NOZACAS-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: bge a1, a7, .LBB51_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-NOZACAS-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a6, .LBB51_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i8_acquire: ; RV64I: # %bb.0: @@ -6916,6 +9171,64 @@ define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_min_i8_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: slli a1, a1, 24 +; RV32IA-WMO-ZACAS-NEXT: andi a4, a0, 24 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: srai a1, a1, 24 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: xori a4, a4, 24 +; RV32IA-WMO-ZACAS-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: bge a1, a7, .LBB51_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-ZACAS-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a6, .LBB51_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_min_i8_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: slli a1, a1, 24 +; RV32IA-TSO-ZACAS-NEXT: andi a4, a0, 24 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: srai a1, a1, 24 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: xori a4, a4, 24 +; RV32IA-TSO-ZACAS-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: bge a1, a7, .LBB51_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-ZACAS-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a6, .LBB51_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_min_i8_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -6974,6 +9287,16 @@ define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_min_i8_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomin.b.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_min_i8_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomin.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i8_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomin.b.aq a0, a1, (a0) @@ -7030,63 +9353,63 @@ define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_min_i8_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: slli a1, a1, 24 -; RV32IA-WMO-NEXT: andi a4, a0, 24 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: srai a1, a1, 24 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: xori a4, a4, 24 -; RV32IA-WMO-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w a5, (a2) -; RV32IA-WMO-NEXT: and a7, a5, a3 -; RV32IA-WMO-NEXT: mv a6, a5 -; RV32IA-WMO-NEXT: sll a7, a7, a4 -; RV32IA-WMO-NEXT: sra a7, a7, a4 -; RV32IA-WMO-NEXT: bge a1, a7, .LBB52_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1 -; RV32IA-WMO-NEXT: xor a6, a5, a1 -; RV32IA-WMO-NEXT: and a6, a6, a3 -; RV32IA-WMO-NEXT: xor a6, a5, a6 -; RV32IA-WMO-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w.rl a6, a6, (a2) -; RV32IA-WMO-NEXT: bnez a6, .LBB52_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a5, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: slli a1, a1, 24 +; RV32IA-WMO-NOZACAS-NEXT: andi a4, a0, 24 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: srai a1, a1, 24 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: xori a4, a4, 24 +; RV32IA-WMO-NOZACAS-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: bge a1, a7, .LBB52_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-NOZACAS-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a6, .LBB52_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_min_i8_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: slli a1, a1, 24 -; RV32IA-TSO-NEXT: andi a4, a0, 24 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: srai a1, a1, 24 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: xori a4, a4, 24 -; RV32IA-TSO-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a5, (a2) -; RV32IA-TSO-NEXT: and a7, a5, a3 -; RV32IA-TSO-NEXT: mv a6, a5 -; RV32IA-TSO-NEXT: sll a7, a7, a4 -; RV32IA-TSO-NEXT: sra a7, a7, a4 -; RV32IA-TSO-NEXT: bge a1, a7, .LBB52_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1 -; RV32IA-TSO-NEXT: xor a6, a5, a1 -; RV32IA-TSO-NEXT: and a6, a6, a3 -; RV32IA-TSO-NEXT: xor a6, a5, a6 -; RV32IA-TSO-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a6, a6, (a2) -; RV32IA-TSO-NEXT: bnez a6, .LBB52_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a5, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_min_i8_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: slli a1, a1, 24 +; RV32IA-TSO-NOZACAS-NEXT: andi a4, a0, 24 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: srai a1, a1, 24 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: xori a4, a4, 24 +; RV32IA-TSO-NOZACAS-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: bge a1, a7, .LBB52_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-NOZACAS-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a6, .LBB52_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i8_release: ; RV64I: # %bb.0: @@ -7188,6 +9511,64 @@ define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_min_i8_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: slli a1, a1, 24 +; RV32IA-WMO-ZACAS-NEXT: andi a4, a0, 24 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: srai a1, a1, 24 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: xori a4, a4, 24 +; RV32IA-WMO-ZACAS-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: bge a1, a7, .LBB52_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-ZACAS-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a6, .LBB52_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_min_i8_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: slli a1, a1, 24 +; RV32IA-TSO-ZACAS-NEXT: andi a4, a0, 24 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: srai a1, a1, 24 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: xori a4, a4, 24 +; RV32IA-TSO-ZACAS-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: bge a1, a7, .LBB52_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-ZACAS-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a6, .LBB52_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_min_i8_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -7246,6 +9627,16 @@ define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_min_i8_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomin.b.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_min_i8_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomin.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i8_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomin.b.rl a0, a1, (a0) @@ -7302,63 +9693,63 @@ define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_min_i8_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: slli a1, a1, 24 -; RV32IA-WMO-NEXT: andi a4, a0, 24 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: srai a1, a1, 24 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: xori a4, a4, 24 -; RV32IA-WMO-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a5, (a2) -; RV32IA-WMO-NEXT: and a7, a5, a3 -; RV32IA-WMO-NEXT: mv a6, a5 -; RV32IA-WMO-NEXT: sll a7, a7, a4 -; RV32IA-WMO-NEXT: sra a7, a7, a4 -; RV32IA-WMO-NEXT: bge a1, a7, .LBB53_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1 -; RV32IA-WMO-NEXT: xor a6, a5, a1 -; RV32IA-WMO-NEXT: and a6, a6, a3 -; RV32IA-WMO-NEXT: xor a6, a5, a6 -; RV32IA-WMO-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w.rl a6, a6, (a2) -; RV32IA-WMO-NEXT: bnez a6, .LBB53_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a5, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_min_i8_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: slli a1, a1, 24 +; RV32IA-WMO-NOZACAS-NEXT: andi a4, a0, 24 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: srai a1, a1, 24 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: xori a4, a4, 24 +; RV32IA-WMO-NOZACAS-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: bge a1, a7, .LBB53_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-NOZACAS-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a6, .LBB53_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_min_i8_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: slli a1, a1, 24 -; RV32IA-TSO-NEXT: andi a4, a0, 24 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: srai a1, a1, 24 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: xori a4, a4, 24 -; RV32IA-TSO-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a5, (a2) -; RV32IA-TSO-NEXT: and a7, a5, a3 -; RV32IA-TSO-NEXT: mv a6, a5 -; RV32IA-TSO-NEXT: sll a7, a7, a4 -; RV32IA-TSO-NEXT: sra a7, a7, a4 -; RV32IA-TSO-NEXT: bge a1, a7, .LBB53_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1 -; RV32IA-TSO-NEXT: xor a6, a5, a1 -; RV32IA-TSO-NEXT: and a6, a6, a3 -; RV32IA-TSO-NEXT: xor a6, a5, a6 -; RV32IA-TSO-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a6, a6, (a2) -; RV32IA-TSO-NEXT: bnez a6, .LBB53_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a5, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_min_i8_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: slli a1, a1, 24 +; RV32IA-TSO-NOZACAS-NEXT: andi a4, a0, 24 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: srai a1, a1, 24 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: xori a4, a4, 24 +; RV32IA-TSO-NOZACAS-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: bge a1, a7, .LBB53_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-NOZACAS-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a6, .LBB53_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i8_acq_rel: ; RV64I: # %bb.0: @@ -7460,6 +9851,64 @@ define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_min_i8_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: slli a1, a1, 24 +; RV32IA-WMO-ZACAS-NEXT: andi a4, a0, 24 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: srai a1, a1, 24 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: xori a4, a4, 24 +; RV32IA-WMO-ZACAS-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: bge a1, a7, .LBB53_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-ZACAS-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a6, .LBB53_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_min_i8_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: slli a1, a1, 24 +; RV32IA-TSO-ZACAS-NEXT: andi a4, a0, 24 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: srai a1, a1, 24 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: xori a4, a4, 24 +; RV32IA-TSO-ZACAS-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: bge a1, a7, .LBB53_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-ZACAS-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a6, .LBB53_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_min_i8_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -7518,6 +9967,16 @@ define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_min_i8_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomin.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_min_i8_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomin.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i8_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomin.b.aqrl a0, a1, (a0) @@ -7574,34 +10033,34 @@ define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_min_i8_seq_cst: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: li a3, 255 -; RV32IA-NEXT: slli a1, a1, 24 -; RV32IA-NEXT: andi a4, a0, 24 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: srai a1, a1, 24 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: xori a4, a4, 24 -; RV32IA-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a5, (a2) -; RV32IA-NEXT: and a7, a5, a3 -; RV32IA-NEXT: mv a6, a5 -; RV32IA-NEXT: sll a7, a7, a4 -; RV32IA-NEXT: sra a7, a7, a4 -; RV32IA-NEXT: bge a1, a7, .LBB54_3 -; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1 -; RV32IA-NEXT: xor a6, a5, a1 -; RV32IA-NEXT: and a6, a6, a3 -; RV32IA-NEXT: xor a6, a5, a6 -; RV32IA-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a6, a6, (a2) -; RV32IA-NEXT: bnez a6, .LBB54_1 -; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_min_i8_seq_cst: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: li a3, 255 +; RV32IA-NOZACAS-NEXT: slli a1, a1, 24 +; RV32IA-NOZACAS-NEXT: andi a4, a0, 24 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: srai a1, a1, 24 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: xori a4, a4, 24 +; RV32IA-NOZACAS-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w.aqrl a5, (a2) +; RV32IA-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-NOZACAS-NEXT: mv a6, a5 +; RV32IA-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-NOZACAS-NEXT: bge a1, a7, .LBB54_3 +; RV32IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1 +; RV32IA-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-NOZACAS-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1 +; RV32IA-NOZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-NOZACAS-NEXT: bnez a6, .LBB54_1 +; RV32IA-NOZACAS-NEXT: # %bb.4: +; RV32IA-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i8_seq_cst: ; RV64I: # %bb.0: @@ -7674,6 +10133,35 @@ define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_min_i8_seq_cst: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: li a3, 255 +; RV32IA-ZACAS-NEXT: slli a1, a1, 24 +; RV32IA-ZACAS-NEXT: andi a4, a0, 24 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: srai a1, a1, 24 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: xori a4, a4, 24 +; RV32IA-ZACAS-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w.aqrl a5, (a2) +; RV32IA-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-ZACAS-NEXT: mv a6, a5 +; RV32IA-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-ZACAS-NEXT: bge a1, a7, .LBB54_3 +; RV32IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1 +; RV32IA-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-ZACAS-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1 +; RV32IA-ZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-ZACAS-NEXT: bnez a6, .LBB54_1 +; RV32IA-ZACAS-NEXT: # %bb.4: +; RV32IA-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_min_i8_seq_cst: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -7703,6 +10191,16 @@ define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_min_i8_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomin.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_min_i8_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomin.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i8_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomin.b.aqrl a0, a1, (a0) @@ -7757,29 +10255,29 @@ define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_umax_i8_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: li a3, 255 -; RV32IA-NEXT: zext.b a1, a1 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a4, (a2) -; RV32IA-NEXT: and a6, a4, a3 -; RV32IA-NEXT: mv a5, a4 -; RV32IA-NEXT: bgeu a6, a1, .LBB55_3 -; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB55_1 Depth=1 -; RV32IA-NEXT: xor a5, a4, a1 -; RV32IA-NEXT: and a5, a5, a3 -; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: .LBB55_3: # in Loop: Header=BB55_1 Depth=1 -; RV32IA-NEXT: sc.w a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB55_1 -; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a4, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_umax_i8_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: li a3, 255 +; RV32IA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-NOZACAS-NEXT: and a6, a4, a3 +; RV32IA-NOZACAS-NEXT: mv a5, a4 +; RV32IA-NOZACAS-NEXT: bgeu a6, a1, .LBB55_3 +; RV32IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB55_1 Depth=1 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a1 +; RV32IA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-NOZACAS-NEXT: .LBB55_3: # in Loop: Header=BB55_1 Depth=1 +; RV32IA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB55_1 +; RV32IA-NOZACAS-NEXT: # %bb.4: +; RV32IA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umax_i8_monotonic: ; RV64I: # %bb.0: @@ -7845,6 +10343,30 @@ define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_umax_i8_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: li a3, 255 +; RV32IA-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB55_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-ZACAS-NEXT: and a6, a4, a3 +; RV32IA-ZACAS-NEXT: mv a5, a4 +; RV32IA-ZACAS-NEXT: bgeu a6, a1, .LBB55_3 +; RV32IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB55_1 Depth=1 +; RV32IA-ZACAS-NEXT: xor a5, a4, a1 +; RV32IA-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: .LBB55_3: # in Loop: Header=BB55_1 Depth=1 +; RV32IA-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB55_1 +; RV32IA-ZACAS-NEXT: # %bb.4: +; RV32IA-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_umax_i8_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -7869,6 +10391,16 @@ define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_umax_i8_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomaxu.b a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_umax_i8_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomaxu.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i8_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomaxu.b a0, a1, (a0) @@ -7923,53 +10455,53 @@ define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_umax_i8_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a4, (a2) -; RV32IA-WMO-NEXT: and a6, a4, a3 -; RV32IA-WMO-NEXT: mv a5, a4 -; RV32IA-WMO-NEXT: bgeu a6, a1, .LBB56_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1 -; RV32IA-WMO-NEXT: xor a5, a4, a1 -; RV32IA-WMO-NEXT: and a5, a5, a3 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB56_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a4, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a6, a4, a3 +; RV32IA-WMO-NOZACAS-NEXT: mv a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: bgeu a6, a1, .LBB56_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB56_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_umax_i8_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a4, (a2) -; RV32IA-TSO-NEXT: and a6, a4, a3 -; RV32IA-TSO-NEXT: mv a5, a4 -; RV32IA-TSO-NEXT: bgeu a6, a1, .LBB56_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1 -; RV32IA-TSO-NEXT: xor a5, a4, a1 -; RV32IA-TSO-NEXT: and a5, a5, a3 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB56_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a4, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_umax_i8_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a6, a4, a3 +; RV32IA-TSO-NOZACAS-NEXT: mv a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: bgeu a6, a1, .LBB56_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB56_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umax_i8_acquire: ; RV64I: # %bb.0: @@ -8059,6 +10591,54 @@ define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_umax_i8_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a6, a4, a3 +; RV32IA-WMO-ZACAS-NEXT: mv a5, a4 +; RV32IA-WMO-ZACAS-NEXT: bgeu a6, a1, .LBB56_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a1 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB56_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_umax_i8_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB56_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a6, a4, a3 +; RV32IA-TSO-ZACAS-NEXT: mv a5, a4 +; RV32IA-TSO-ZACAS-NEXT: bgeu a6, a1, .LBB56_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB56_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a1 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: .LBB56_3: # in Loop: Header=BB56_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB56_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umax_i8_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -8107,6 +10687,16 @@ define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_umax_i8_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomaxu.b.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_umax_i8_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomaxu.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i8_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomaxu.b.aq a0, a1, (a0) @@ -8161,53 +10751,53 @@ define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_umax_i8_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w a4, (a2) -; RV32IA-WMO-NEXT: and a6, a4, a3 -; RV32IA-WMO-NEXT: mv a5, a4 -; RV32IA-WMO-NEXT: bgeu a6, a1, .LBB57_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1 -; RV32IA-WMO-NEXT: xor a5, a4, a1 -; RV32IA-WMO-NEXT: and a5, a5, a3 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB57_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a4, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a6, a4, a3 +; RV32IA-WMO-NOZACAS-NEXT: mv a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: bgeu a6, a1, .LBB57_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB57_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_umax_i8_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a4, (a2) -; RV32IA-TSO-NEXT: and a6, a4, a3 -; RV32IA-TSO-NEXT: mv a5, a4 -; RV32IA-TSO-NEXT: bgeu a6, a1, .LBB57_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1 -; RV32IA-TSO-NEXT: xor a5, a4, a1 -; RV32IA-TSO-NEXT: and a5, a5, a3 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB57_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a4, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_umax_i8_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a6, a4, a3 +; RV32IA-TSO-NOZACAS-NEXT: mv a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: bgeu a6, a1, .LBB57_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB57_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umax_i8_release: ; RV64I: # %bb.0: @@ -8297,6 +10887,54 @@ define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_umax_i8_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a6, a4, a3 +; RV32IA-WMO-ZACAS-NEXT: mv a5, a4 +; RV32IA-WMO-ZACAS-NEXT: bgeu a6, a1, .LBB57_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a1 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB57_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_umax_i8_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB57_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a6, a4, a3 +; RV32IA-TSO-ZACAS-NEXT: mv a5, a4 +; RV32IA-TSO-ZACAS-NEXT: bgeu a6, a1, .LBB57_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB57_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a1 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: .LBB57_3: # in Loop: Header=BB57_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB57_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umax_i8_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -8345,6 +10983,16 @@ define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_umax_i8_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomaxu.b.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_umax_i8_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomaxu.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i8_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomaxu.b.rl a0, a1, (a0) @@ -8399,53 +11047,53 @@ define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_umax_i8_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a4, (a2) -; RV32IA-WMO-NEXT: and a6, a4, a3 -; RV32IA-WMO-NEXT: mv a5, a4 -; RV32IA-WMO-NEXT: bgeu a6, a1, .LBB58_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1 -; RV32IA-WMO-NEXT: xor a5, a4, a1 -; RV32IA-WMO-NEXT: and a5, a5, a3 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB58_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a4, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i8_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a6, a4, a3 +; RV32IA-WMO-NOZACAS-NEXT: mv a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: bgeu a6, a1, .LBB58_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB58_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_umax_i8_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a4, (a2) -; RV32IA-TSO-NEXT: and a6, a4, a3 -; RV32IA-TSO-NEXT: mv a5, a4 -; RV32IA-TSO-NEXT: bgeu a6, a1, .LBB58_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1 -; RV32IA-TSO-NEXT: xor a5, a4, a1 -; RV32IA-TSO-NEXT: and a5, a5, a3 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB58_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a4, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_umax_i8_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a6, a4, a3 +; RV32IA-TSO-NOZACAS-NEXT: mv a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: bgeu a6, a1, .LBB58_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB58_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umax_i8_acq_rel: ; RV64I: # %bb.0: @@ -8535,6 +11183,54 @@ define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_umax_i8_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a6, a4, a3 +; RV32IA-WMO-ZACAS-NEXT: mv a5, a4 +; RV32IA-WMO-ZACAS-NEXT: bgeu a6, a1, .LBB58_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a1 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB58_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_umax_i8_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB58_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a6, a4, a3 +; RV32IA-TSO-ZACAS-NEXT: mv a5, a4 +; RV32IA-TSO-ZACAS-NEXT: bgeu a6, a1, .LBB58_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB58_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a1 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: .LBB58_3: # in Loop: Header=BB58_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB58_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umax_i8_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -8583,6 +11279,16 @@ define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_umax_i8_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomaxu.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_umax_i8_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomaxu.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i8_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomaxu.b.aqrl a0, a1, (a0) @@ -8637,29 +11343,29 @@ define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_umax_i8_seq_cst: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: li a3, 255 -; RV32IA-NEXT: zext.b a1, a1 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a4, (a2) -; RV32IA-NEXT: and a6, a4, a3 -; RV32IA-NEXT: mv a5, a4 -; RV32IA-NEXT: bgeu a6, a1, .LBB59_3 -; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB59_1 Depth=1 -; RV32IA-NEXT: xor a5, a4, a1 -; RV32IA-NEXT: and a5, a5, a3 -; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: .LBB59_3: # in Loop: Header=BB59_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB59_1 -; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a4, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_umax_i8_seq_cst: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: li a3, 255 +; RV32IA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w.aqrl a4, (a2) +; RV32IA-NOZACAS-NEXT: and a6, a4, a3 +; RV32IA-NOZACAS-NEXT: mv a5, a4 +; RV32IA-NOZACAS-NEXT: bgeu a6, a1, .LBB59_3 +; RV32IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB59_1 Depth=1 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a1 +; RV32IA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-NOZACAS-NEXT: .LBB59_3: # in Loop: Header=BB59_1 Depth=1 +; RV32IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB59_1 +; RV32IA-NOZACAS-NEXT: # %bb.4: +; RV32IA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umax_i8_seq_cst: ; RV64I: # %bb.0: @@ -8725,6 +11431,30 @@ define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_umax_i8_seq_cst: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: li a3, 255 +; RV32IA-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB59_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w.aqrl a4, (a2) +; RV32IA-ZACAS-NEXT: and a6, a4, a3 +; RV32IA-ZACAS-NEXT: mv a5, a4 +; RV32IA-ZACAS-NEXT: bgeu a6, a1, .LBB59_3 +; RV32IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB59_1 Depth=1 +; RV32IA-ZACAS-NEXT: xor a5, a4, a1 +; RV32IA-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: .LBB59_3: # in Loop: Header=BB59_1 Depth=1 +; RV32IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB59_1 +; RV32IA-ZACAS-NEXT: # %bb.4: +; RV32IA-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_umax_i8_seq_cst: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -8749,6 +11479,16 @@ define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_umax_i8_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomaxu.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_umax_i8_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomaxu.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i8_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomaxu.b.aqrl a0, a1, (a0) @@ -8803,29 +11543,29 @@ define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_umin_i8_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: li a3, 255 -; RV32IA-NEXT: zext.b a1, a1 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a4, (a2) -; RV32IA-NEXT: and a6, a4, a3 -; RV32IA-NEXT: mv a5, a4 -; RV32IA-NEXT: bgeu a1, a6, .LBB60_3 -; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB60_1 Depth=1 -; RV32IA-NEXT: xor a5, a4, a1 -; RV32IA-NEXT: and a5, a5, a3 -; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: .LBB60_3: # in Loop: Header=BB60_1 Depth=1 -; RV32IA-NEXT: sc.w a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB60_1 -; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a4, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_umin_i8_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: li a3, 255 +; RV32IA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-NOZACAS-NEXT: and a6, a4, a3 +; RV32IA-NOZACAS-NEXT: mv a5, a4 +; RV32IA-NOZACAS-NEXT: bgeu a1, a6, .LBB60_3 +; RV32IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB60_1 Depth=1 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a1 +; RV32IA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-NOZACAS-NEXT: .LBB60_3: # in Loop: Header=BB60_1 Depth=1 +; RV32IA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB60_1 +; RV32IA-NOZACAS-NEXT: # %bb.4: +; RV32IA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i8_monotonic: ; RV64I: # %bb.0: @@ -8891,6 +11631,30 @@ define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_umin_i8_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: li a3, 255 +; RV32IA-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB60_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-ZACAS-NEXT: and a6, a4, a3 +; RV32IA-ZACAS-NEXT: mv a5, a4 +; RV32IA-ZACAS-NEXT: bgeu a1, a6, .LBB60_3 +; RV32IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB60_1 Depth=1 +; RV32IA-ZACAS-NEXT: xor a5, a4, a1 +; RV32IA-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: .LBB60_3: # in Loop: Header=BB60_1 Depth=1 +; RV32IA-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB60_1 +; RV32IA-ZACAS-NEXT: # %bb.4: +; RV32IA-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_umin_i8_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -8915,6 +11679,16 @@ define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_umin_i8_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amominu.b a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_umin_i8_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amominu.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i8_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amominu.b a0, a1, (a0) @@ -8969,53 +11743,53 @@ define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_umin_i8_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a4, (a2) -; RV32IA-WMO-NEXT: and a6, a4, a3 -; RV32IA-WMO-NEXT: mv a5, a4 -; RV32IA-WMO-NEXT: bgeu a1, a6, .LBB61_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1 -; RV32IA-WMO-NEXT: xor a5, a4, a1 -; RV32IA-WMO-NEXT: and a5, a5, a3 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB61_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a4, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a6, a4, a3 +; RV32IA-WMO-NOZACAS-NEXT: mv a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: bgeu a1, a6, .LBB61_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB61_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_umin_i8_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a4, (a2) -; RV32IA-TSO-NEXT: and a6, a4, a3 -; RV32IA-TSO-NEXT: mv a5, a4 -; RV32IA-TSO-NEXT: bgeu a1, a6, .LBB61_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1 -; RV32IA-TSO-NEXT: xor a5, a4, a1 -; RV32IA-TSO-NEXT: and a5, a5, a3 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB61_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a4, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_umin_i8_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a6, a4, a3 +; RV32IA-TSO-NOZACAS-NEXT: mv a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: bgeu a1, a6, .LBB61_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB61_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i8_acquire: ; RV64I: # %bb.0: @@ -9105,6 +11879,54 @@ define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_umin_i8_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a6, a4, a3 +; RV32IA-WMO-ZACAS-NEXT: mv a5, a4 +; RV32IA-WMO-ZACAS-NEXT: bgeu a1, a6, .LBB61_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a1 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB61_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_umin_i8_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB61_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a6, a4, a3 +; RV32IA-TSO-ZACAS-NEXT: mv a5, a4 +; RV32IA-TSO-ZACAS-NEXT: bgeu a1, a6, .LBB61_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB61_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a1 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: .LBB61_3: # in Loop: Header=BB61_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB61_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umin_i8_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -9153,6 +11975,16 @@ define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_umin_i8_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amominu.b.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_umin_i8_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amominu.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i8_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amominu.b.aq a0, a1, (a0) @@ -9207,53 +12039,53 @@ define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_umin_i8_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w a4, (a2) -; RV32IA-WMO-NEXT: and a6, a4, a3 -; RV32IA-WMO-NEXT: mv a5, a4 -; RV32IA-WMO-NEXT: bgeu a1, a6, .LBB62_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1 -; RV32IA-WMO-NEXT: xor a5, a4, a1 -; RV32IA-WMO-NEXT: and a5, a5, a3 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB62_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a4, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a6, a4, a3 +; RV32IA-WMO-NOZACAS-NEXT: mv a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: bgeu a1, a6, .LBB62_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB62_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_umin_i8_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a4, (a2) -; RV32IA-TSO-NEXT: and a6, a4, a3 -; RV32IA-TSO-NEXT: mv a5, a4 -; RV32IA-TSO-NEXT: bgeu a1, a6, .LBB62_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1 -; RV32IA-TSO-NEXT: xor a5, a4, a1 -; RV32IA-TSO-NEXT: and a5, a5, a3 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB62_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a4, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_umin_i8_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a6, a4, a3 +; RV32IA-TSO-NOZACAS-NEXT: mv a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: bgeu a1, a6, .LBB62_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB62_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i8_release: ; RV64I: # %bb.0: @@ -9343,6 +12175,54 @@ define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_umin_i8_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a6, a4, a3 +; RV32IA-WMO-ZACAS-NEXT: mv a5, a4 +; RV32IA-WMO-ZACAS-NEXT: bgeu a1, a6, .LBB62_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a1 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB62_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_umin_i8_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB62_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a6, a4, a3 +; RV32IA-TSO-ZACAS-NEXT: mv a5, a4 +; RV32IA-TSO-ZACAS-NEXT: bgeu a1, a6, .LBB62_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB62_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a1 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: .LBB62_3: # in Loop: Header=BB62_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB62_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umin_i8_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -9391,6 +12271,16 @@ define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_umin_i8_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amominu.b.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_umin_i8_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amominu.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i8_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amominu.b.rl a0, a1, (a0) @@ -9445,53 +12335,53 @@ define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_umin_i8_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: li a3, 255 -; RV32IA-WMO-NEXT: zext.b a1, a1 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a4, (a2) -; RV32IA-WMO-NEXT: and a6, a4, a3 -; RV32IA-WMO-NEXT: mv a5, a4 -; RV32IA-WMO-NEXT: bgeu a1, a6, .LBB63_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1 -; RV32IA-WMO-NEXT: xor a5, a4, a1 -; RV32IA-WMO-NEXT: and a5, a5, a3 -; RV32IA-WMO-NEXT: xor a5, a4, a5 -; RV32IA-WMO-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB63_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a4, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i8_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: li a3, 255 +; RV32IA-WMO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a6, a4, a3 +; RV32IA-WMO-NOZACAS-NEXT: mv a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: bgeu a1, a6, .LBB63_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB63_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_umin_i8_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: li a3, 255 -; RV32IA-TSO-NEXT: zext.b a1, a1 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a4, (a2) -; RV32IA-TSO-NEXT: and a6, a4, a3 -; RV32IA-TSO-NEXT: mv a5, a4 -; RV32IA-TSO-NEXT: bgeu a1, a6, .LBB63_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1 -; RV32IA-TSO-NEXT: xor a5, a4, a1 -; RV32IA-TSO-NEXT: and a5, a5, a3 -; RV32IA-TSO-NEXT: xor a5, a4, a5 -; RV32IA-TSO-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB63_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a4, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_umin_i8_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: li a3, 255 +; RV32IA-TSO-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a6, a4, a3 +; RV32IA-TSO-NOZACAS-NEXT: mv a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: bgeu a1, a6, .LBB63_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB63_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i8_acq_rel: ; RV64I: # %bb.0: @@ -9581,6 +12471,54 @@ define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_umin_i8_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: li a3, 255 +; RV32IA-WMO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a4, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a6, a4, a3 +; RV32IA-WMO-ZACAS-NEXT: mv a5, a4 +; RV32IA-WMO-ZACAS-NEXT: bgeu a1, a6, .LBB63_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a1 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB63_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_umin_i8_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: li a3, 255 +; RV32IA-TSO-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB63_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a4, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a6, a4, a3 +; RV32IA-TSO-ZACAS-NEXT: mv a5, a4 +; RV32IA-TSO-ZACAS-NEXT: bgeu a1, a6, .LBB63_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB63_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a1 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: .LBB63_3: # in Loop: Header=BB63_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB63_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umin_i8_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -9629,6 +12567,16 @@ define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_umin_i8_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amominu.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_umin_i8_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amominu.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i8_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amominu.b.aqrl a0, a1, (a0) @@ -9683,29 +12631,29 @@ define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_umin_i8_seq_cst: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: li a3, 255 -; RV32IA-NEXT: zext.b a1, a1 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a4, (a2) -; RV32IA-NEXT: and a6, a4, a3 -; RV32IA-NEXT: mv a5, a4 -; RV32IA-NEXT: bgeu a1, a6, .LBB64_3 -; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB64_1 Depth=1 -; RV32IA-NEXT: xor a5, a4, a1 -; RV32IA-NEXT: and a5, a5, a3 -; RV32IA-NEXT: xor a5, a4, a5 -; RV32IA-NEXT: .LBB64_3: # in Loop: Header=BB64_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB64_1 -; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a4, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_umin_i8_seq_cst: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: li a3, 255 +; RV32IA-NOZACAS-NEXT: zext.b a1, a1 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w.aqrl a4, (a2) +; RV32IA-NOZACAS-NEXT: and a6, a4, a3 +; RV32IA-NOZACAS-NEXT: mv a5, a4 +; RV32IA-NOZACAS-NEXT: bgeu a1, a6, .LBB64_3 +; RV32IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB64_1 Depth=1 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a1 +; RV32IA-NOZACAS-NEXT: and a5, a5, a3 +; RV32IA-NOZACAS-NEXT: xor a5, a4, a5 +; RV32IA-NOZACAS-NEXT: .LBB64_3: # in Loop: Header=BB64_1 Depth=1 +; RV32IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB64_1 +; RV32IA-NOZACAS-NEXT: # %bb.4: +; RV32IA-NOZACAS-NEXT: srl a0, a4, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i8_seq_cst: ; RV64I: # %bb.0: @@ -9771,6 +12719,30 @@ define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_umin_i8_seq_cst: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: li a3, 255 +; RV32IA-ZACAS-NEXT: zext.b a1, a1 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB64_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w.aqrl a4, (a2) +; RV32IA-ZACAS-NEXT: and a6, a4, a3 +; RV32IA-ZACAS-NEXT: mv a5, a4 +; RV32IA-ZACAS-NEXT: bgeu a1, a6, .LBB64_3 +; RV32IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB64_1 Depth=1 +; RV32IA-ZACAS-NEXT: xor a5, a4, a1 +; RV32IA-ZACAS-NEXT: and a5, a5, a3 +; RV32IA-ZACAS-NEXT: xor a5, a4, a5 +; RV32IA-ZACAS-NEXT: .LBB64_3: # in Loop: Header=BB64_1 Depth=1 +; RV32IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB64_1 +; RV32IA-ZACAS-NEXT: # %bb.4: +; RV32IA-ZACAS-NEXT: srl a0, a4, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_umin_i8_seq_cst: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -9795,6 +12767,16 @@ define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a4, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_umin_i8_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amominu.b.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_umin_i8_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amominu.b a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i8_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amominu.b.aqrl a0, a1, (a0) @@ -9819,26 +12801,26 @@ define i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_xchg_i16_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a3, (a2) -; RV32IA-NEXT: mv a5, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB65_1 -; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_i16_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-NOZACAS-NEXT: mv a5, a1 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB65_1 +; RV32IA-NOZACAS-NEXT: # %bb.2: +; RV32IA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_i16_monotonic: ; RV64I: # %bb.0: @@ -9871,6 +12853,27 @@ define i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_xchg_i16_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: lui a3, 16 +; RV32IA-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB65_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-ZACAS-NEXT: mv a5, a1 +; RV32IA-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB65_1 +; RV32IA-ZACAS-NEXT: # %bb.2: +; RV32IA-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_xchg_i16_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -9892,6 +12895,16 @@ define i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i16_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoswap.h a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i16_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i16_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoswap.h a0, a1, (a0) @@ -9916,47 +12929,47 @@ define i16 @atomicrmw_xchg_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_i16_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a3, (a2) -; RV32IA-WMO-NEXT: mv a5, a1 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: and a5, a5, a4 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: sc.w a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB66_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a3, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-NOZACAS-NEXT: mv a5, a1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB66_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_i16_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a3, (a2) -; RV32IA-TSO-NEXT: mv a5, a1 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: and a5, a5, a4 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB66_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a3, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_i16_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-NOZACAS-NEXT: mv a5, a1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB66_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_i16_acquire: ; RV64I: # %bb.0: @@ -10010,6 +13023,48 @@ define i16 @atomicrmw_xchg_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i16_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-ZACAS-NEXT: mv a5, a1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB66_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_i16_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB66_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZACAS-NEXT: mv a5, a1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB66_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i16_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -10052,6 +13107,16 @@ define i16 @atomicrmw_xchg_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i16_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoswap.h.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i16_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i16_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aq a0, a1, (a0) @@ -10076,47 +13141,47 @@ define i16 @atomicrmw_xchg_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_i16_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w a3, (a2) -; RV32IA-WMO-NEXT: mv a5, a1 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: and a5, a5, a4 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB67_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a3, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-WMO-NOZACAS-NEXT: mv a5, a1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB67_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_i16_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a3, (a2) -; RV32IA-TSO-NEXT: mv a5, a1 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: and a5, a5, a4 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB67_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a3, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_i16_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-NOZACAS-NEXT: mv a5, a1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB67_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_i16_release: ; RV64I: # %bb.0: @@ -10170,6 +13235,48 @@ define i16 @atomicrmw_xchg_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i16_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-WMO-ZACAS-NEXT: mv a5, a1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB67_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_i16_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB67_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZACAS-NEXT: mv a5, a1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB67_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i16_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -10212,6 +13319,16 @@ define i16 @atomicrmw_xchg_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i16_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoswap.h.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i16_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i16_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoswap.h.rl a0, a1, (a0) @@ -10236,47 +13353,47 @@ define i16 @atomicrmw_xchg_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_i16_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a3, (a2) -; RV32IA-WMO-NEXT: mv a5, a1 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: and a5, a5, a4 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB68_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a3, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_i16_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-NOZACAS-NEXT: mv a5, a1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB68_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_i16_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a3, (a2) -; RV32IA-TSO-NEXT: mv a5, a1 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: and a5, a5, a4 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB68_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a3, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_i16_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-NOZACAS-NEXT: mv a5, a1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB68_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_i16_acq_rel: ; RV64I: # %bb.0: @@ -10330,6 +13447,48 @@ define i16 @atomicrmw_xchg_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i16_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-ZACAS-NEXT: mv a5, a1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB68_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_i16_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB68_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZACAS-NEXT: mv a5, a1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB68_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_i16_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -10372,6 +13531,16 @@ define i16 @atomicrmw_xchg_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i16_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i16_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i16_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, a1, (a0) @@ -10396,26 +13565,26 @@ define i16 @atomicrmw_xchg_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_xchg_i16_seq_cst: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a3, (a2) -; RV32IA-NEXT: mv a5, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB69_1 -; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_i16_seq_cst: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2) +; RV32IA-NOZACAS-NEXT: mv a5, a1 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB69_1 +; RV32IA-NOZACAS-NEXT: # %bb.2: +; RV32IA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV64I: # %bb.0: @@ -10448,6 +13617,27 @@ define i16 @atomicrmw_xchg_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_xchg_i16_seq_cst: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: lui a3, 16 +; RV32IA-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB69_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w.aqrl a3, (a2) +; RV32IA-ZACAS-NEXT: mv a5, a1 +; RV32IA-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB69_1 +; RV32IA-ZACAS-NEXT: # %bb.2: +; RV32IA-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -10469,6 +13659,16 @@ define i16 @atomicrmw_xchg_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i16_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_i16_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_i16_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, a1, (a0) @@ -10497,17 +13697,17 @@ define i16 @atomicrmw_xchg_0_i16_monotonic(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_xchg_0_i16_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a1, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: lui a2, 16 -; RV32IA-NEXT: addi a2, a2, -1 -; RV32IA-NEXT: sll a2, a2, a0 -; RV32IA-NEXT: not a2, a2 -; RV32IA-NEXT: amoand.w a1, a2, (a1) -; RV32IA-NEXT: srl a0, a1, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_0_i16_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: lui a2, 16 +; RV32IA-NOZACAS-NEXT: addi a2, a2, -1 +; RV32IA-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-NOZACAS-NEXT: not a2, a2 +; RV32IA-NOZACAS-NEXT: amoand.w a1, a2, (a1) +; RV32IA-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_0_i16_monotonic: ; RV64I: # %bb.0: @@ -10532,6 +13732,18 @@ define i16 @atomicrmw_xchg_0_i16_monotonic(ptr %a) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_xchg_0_i16_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: lui a2, 16 +; RV32IA-ZACAS-NEXT: addi a2, a2, -1 +; RV32IA-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-ZACAS-NEXT: not a2, a2 +; RV32IA-ZACAS-NEXT: amoand.w a1, a2, (a1) +; RV32IA-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_xchg_0_i16_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a1, a0, -4 @@ -10544,6 +13756,16 @@ define i16 @atomicrmw_xchg_0_i16_monotonic(ptr %a) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i16_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoswap.h a0, zero, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i16_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoswap.h a0, zero, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i16_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoswap.h a0, zero, (a0) @@ -10569,29 +13791,29 @@ define i16 @atomicrmw_xchg_0_i16_acquire(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_0_i16_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a1, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a2, 16 -; RV32IA-WMO-NEXT: addi a2, a2, -1 -; RV32IA-WMO-NEXT: sll a2, a2, a0 -; RV32IA-WMO-NEXT: not a2, a2 -; RV32IA-WMO-NEXT: amoand.w.aq a1, a2, (a1) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a2, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a2, a2, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-NOZACAS-NEXT: not a2, a2 +; RV32IA-WMO-NOZACAS-NEXT: amoand.w.aq a1, a2, (a1) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_0_i16_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a1, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a2, 16 -; RV32IA-TSO-NEXT: addi a2, a2, -1 -; RV32IA-TSO-NEXT: sll a2, a2, a0 -; RV32IA-TSO-NEXT: not a2, a2 -; RV32IA-TSO-NEXT: amoand.w a1, a2, (a1) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a2, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a2, a2, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-NOZACAS-NEXT: not a2, a2 +; RV32IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_0_i16_acquire: ; RV64I: # %bb.0: @@ -10628,6 +13850,30 @@ define i16 @atomicrmw_xchg_0_i16_acquire(ptr %a) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i16_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a2, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a2, a2, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: not a2, a2 +; RV32IA-WMO-ZACAS-NEXT: amoand.w.aq a1, a2, (a1) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i16_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a2, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a2, a2, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: not a2, a2 +; RV32IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i16_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4 @@ -10652,6 +13898,16 @@ define i16 @atomicrmw_xchg_0_i16_acquire(ptr %a) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i16_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoswap.h.aq a0, zero, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i16_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoswap.h a0, zero, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i16_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aq a0, zero, (a0) @@ -10677,29 +13933,29 @@ define i16 @atomicrmw_xchg_0_i16_release(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_0_i16_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a1, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a2, 16 -; RV32IA-WMO-NEXT: addi a2, a2, -1 -; RV32IA-WMO-NEXT: sll a2, a2, a0 -; RV32IA-WMO-NEXT: not a2, a2 -; RV32IA-WMO-NEXT: amoand.w.rl a1, a2, (a1) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a2, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a2, a2, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-NOZACAS-NEXT: not a2, a2 +; RV32IA-WMO-NOZACAS-NEXT: amoand.w.rl a1, a2, (a1) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_0_i16_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a1, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a2, 16 -; RV32IA-TSO-NEXT: addi a2, a2, -1 -; RV32IA-TSO-NEXT: sll a2, a2, a0 -; RV32IA-TSO-NEXT: not a2, a2 -; RV32IA-TSO-NEXT: amoand.w a1, a2, (a1) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a2, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a2, a2, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-NOZACAS-NEXT: not a2, a2 +; RV32IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_0_i16_release: ; RV64I: # %bb.0: @@ -10736,6 +13992,30 @@ define i16 @atomicrmw_xchg_0_i16_release(ptr %a) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i16_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a2, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a2, a2, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: not a2, a2 +; RV32IA-WMO-ZACAS-NEXT: amoand.w.rl a1, a2, (a1) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i16_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a2, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a2, a2, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: not a2, a2 +; RV32IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i16_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4 @@ -10760,6 +14040,16 @@ define i16 @atomicrmw_xchg_0_i16_release(ptr %a) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i16_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoswap.h.rl a0, zero, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i16_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoswap.h a0, zero, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i16_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoswap.h.rl a0, zero, (a0) @@ -10785,29 +14075,29 @@ define i16 @atomicrmw_xchg_0_i16_acq_rel(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_0_i16_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a1, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a2, 16 -; RV32IA-WMO-NEXT: addi a2, a2, -1 -; RV32IA-WMO-NEXT: sll a2, a2, a0 -; RV32IA-WMO-NEXT: not a2, a2 -; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a2, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a2, a2, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-NOZACAS-NEXT: not a2, a2 +; RV32IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a2, (a1) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_0_i16_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a1, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a2, 16 -; RV32IA-TSO-NEXT: addi a2, a2, -1 -; RV32IA-TSO-NEXT: sll a2, a2, a0 -; RV32IA-TSO-NEXT: not a2, a2 -; RV32IA-TSO-NEXT: amoand.w a1, a2, (a1) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a2, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a2, a2, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-NOZACAS-NEXT: not a2, a2 +; RV32IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_0_i16_acq_rel: ; RV64I: # %bb.0: @@ -10844,6 +14134,30 @@ define i16 @atomicrmw_xchg_0_i16_acq_rel(ptr %a) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i16_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a2, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a2, a2, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: not a2, a2 +; RV32IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a2, (a1) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i16_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a2, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a2, a2, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: not a2, a2 +; RV32IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i16_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4 @@ -10868,6 +14182,16 @@ define i16 @atomicrmw_xchg_0_i16_acq_rel(ptr %a) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i16_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, zero, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i16_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoswap.h a0, zero, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i16_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, zero, (a0) @@ -10893,29 +14217,29 @@ define i16 @atomicrmw_xchg_0_i16_seq_cst(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_0_i16_seq_cst: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a1, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a2, 16 -; RV32IA-WMO-NEXT: addi a2, a2, -1 -; RV32IA-WMO-NEXT: sll a2, a2, a0 -; RV32IA-WMO-NEXT: not a2, a2 -; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_seq_cst: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a2, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a2, a2, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-NOZACAS-NEXT: not a2, a2 +; RV32IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a2, (a1) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_0_i16_seq_cst: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a1, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a2, 16 -; RV32IA-TSO-NEXT: addi a2, a2, -1 -; RV32IA-TSO-NEXT: sll a2, a2, a0 -; RV32IA-TSO-NEXT: not a2, a2 -; RV32IA-TSO-NEXT: amoand.w a1, a2, (a1) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_0_i16_seq_cst: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a2, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a2, a2, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-NOZACAS-NEXT: not a2, a2 +; RV32IA-TSO-NOZACAS-NEXT: amoand.w a1, a2, (a1) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_0_i16_seq_cst: ; RV64I: # %bb.0: @@ -10952,6 +14276,30 @@ define i16 @atomicrmw_xchg_0_i16_seq_cst(ptr %a) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i16_seq_cst: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a2, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a2, a2, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: not a2, a2 +; RV32IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a2, (a1) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_0_i16_seq_cst: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a2, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a2, a2, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: not a2, a2 +; RV32IA-TSO-ZACAS-NEXT: amoand.w a1, a2, (a1) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_0_i16_seq_cst: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4 @@ -10976,6 +14324,16 @@ define i16 @atomicrmw_xchg_0_i16_seq_cst(ptr %a) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i16_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, zero, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_0_i16_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoswap.h a0, zero, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_0_i16_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, zero, (a0) @@ -11002,16 +14360,16 @@ define i16 @atomicrmw_xchg_minus_1_i16_monotonic(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_xchg_minus_1_i16_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a1, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: lui a2, 16 -; RV32IA-NEXT: addi a2, a2, -1 -; RV32IA-NEXT: sll a2, a2, a0 -; RV32IA-NEXT: amoor.w a1, a2, (a1) -; RV32IA-NEXT: srl a0, a1, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: lui a2, 16 +; RV32IA-NOZACAS-NEXT: addi a2, a2, -1 +; RV32IA-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-NOZACAS-NEXT: amoor.w a1, a2, (a1) +; RV32IA-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_minus_1_i16_monotonic: ; RV64I: # %bb.0: @@ -11036,6 +14394,17 @@ define i16 @atomicrmw_xchg_minus_1_i16_monotonic(ptr %a) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: lui a2, 16 +; RV32IA-ZACAS-NEXT: addi a2, a2, -1 +; RV32IA-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-ZACAS-NEXT: amoor.w a1, a2, (a1) +; RV32IA-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a1, a0, -4 @@ -11047,6 +14416,18 @@ define i16 @atomicrmw_xchg_minus_1_i16_monotonic(ptr %a) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: li a1, -1 +; RV32IA-WMO-ZABHA-NEXT: amoswap.h a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: li a1, -1 +; RV32IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: li a1, -1 @@ -11075,27 +14456,27 @@ define i16 @atomicrmw_xchg_minus_1_i16_acquire(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_minus_1_i16_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a1, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a2, 16 -; RV32IA-WMO-NEXT: addi a2, a2, -1 -; RV32IA-WMO-NEXT: sll a2, a2, a0 -; RV32IA-WMO-NEXT: amoor.w.aq a1, a2, (a1) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a2, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a2, a2, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoor.w.aq a1, a2, (a1) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_minus_1_i16_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a1, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a2, 16 -; RV32IA-TSO-NEXT: addi a2, a2, -1 -; RV32IA-TSO-NEXT: sll a2, a2, a0 -; RV32IA-TSO-NEXT: amoor.w a1, a2, (a1) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a2, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a2, a2, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_minus_1_i16_acquire: ; RV64I: # %bb.0: @@ -11131,6 +14512,28 @@ define i16 @atomicrmw_xchg_minus_1_i16_acquire(ptr %a) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a2, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a2, a2, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: amoor.w.aq a1, a2, (a1) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a2, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a2, a2, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4 @@ -11153,6 +14556,18 @@ define i16 @atomicrmw_xchg_minus_1_i16_acquire(ptr %a) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: li a1, -1 +; RV32IA-WMO-ZABHA-NEXT: amoswap.h.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: li a1, -1 +; RV32IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: li a1, -1 @@ -11181,27 +14596,27 @@ define i16 @atomicrmw_xchg_minus_1_i16_release(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_minus_1_i16_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a1, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a2, 16 -; RV32IA-WMO-NEXT: addi a2, a2, -1 -; RV32IA-WMO-NEXT: sll a2, a2, a0 -; RV32IA-WMO-NEXT: amoor.w.rl a1, a2, (a1) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a2, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a2, a2, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoor.w.rl a1, a2, (a1) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_minus_1_i16_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a1, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a2, 16 -; RV32IA-TSO-NEXT: addi a2, a2, -1 -; RV32IA-TSO-NEXT: sll a2, a2, a0 -; RV32IA-TSO-NEXT: amoor.w a1, a2, (a1) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a2, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a2, a2, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_minus_1_i16_release: ; RV64I: # %bb.0: @@ -11237,6 +14652,28 @@ define i16 @atomicrmw_xchg_minus_1_i16_release(ptr %a) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a2, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a2, a2, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: amoor.w.rl a1, a2, (a1) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a2, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a2, a2, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4 @@ -11259,6 +14696,18 @@ define i16 @atomicrmw_xchg_minus_1_i16_release(ptr %a) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: li a1, -1 +; RV32IA-WMO-ZABHA-NEXT: amoswap.h.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: li a1, -1 +; RV32IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: li a1, -1 @@ -11287,27 +14736,27 @@ define i16 @atomicrmw_xchg_minus_1_i16_acq_rel(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a1, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a2, 16 -; RV32IA-WMO-NEXT: addi a2, a2, -1 -; RV32IA-WMO-NEXT: sll a2, a2, a0 -; RV32IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a2, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a2, a2, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a2, (a1) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a1, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a2, 16 -; RV32IA-TSO-NEXT: addi a2, a2, -1 -; RV32IA-TSO-NEXT: sll a2, a2, a0 -; RV32IA-TSO-NEXT: amoor.w a1, a2, (a1) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a2, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a2, a2, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel: ; RV64I: # %bb.0: @@ -11343,6 +14792,28 @@ define i16 @atomicrmw_xchg_minus_1_i16_acq_rel(ptr %a) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a2, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a2, a2, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a2, (a1) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a2, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a2, a2, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4 @@ -11365,6 +14836,18 @@ define i16 @atomicrmw_xchg_minus_1_i16_acq_rel(ptr %a) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: li a1, -1 +; RV32IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: li a1, -1 +; RV32IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: li a1, -1 @@ -11393,27 +14876,27 @@ define i16 @atomicrmw_xchg_minus_1_i16_seq_cst(ptr %a) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a1, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a2, 16 -; RV32IA-WMO-NEXT: addi a2, a2, -1 -; RV32IA-WMO-NEXT: sll a2, a2, a0 -; RV32IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a2, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a2, a2, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a2, (a1) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a1, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a2, 16 -; RV32IA-TSO-NEXT: addi a2, a2, -1 -; RV32IA-TSO-NEXT: sll a2, a2, a0 -; RV32IA-TSO-NEXT: amoor.w a1, a2, (a1) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a2, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a2, a2, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoor.w a1, a2, (a1) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst: ; RV64I: # %bb.0: @@ -11449,6 +14932,28 @@ define i16 @atomicrmw_xchg_minus_1_i16_seq_cst(ptr %a) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a2, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a2, a2, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a2, (a1) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a1, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a2, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a2, a2, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a2, a2, a0 +; RV32IA-TSO-ZACAS-NEXT: amoor.w a1, a2, (a1) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a1, a0, -4 @@ -11471,6 +14976,18 @@ define i16 @atomicrmw_xchg_minus_1_i16_seq_cst(ptr %a) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: li a1, -1 +; RV32IA-WMO-ZABHA-NEXT: amoswap.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: li a1, -1 +; RV32IA-TSO-ZABHA-NEXT: amoswap.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xchg_minus_1_i16_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: li a1, -1 @@ -11497,26 +15014,26 @@ define i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_add_i16_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB80_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a3, (a2) -; RV32IA-NEXT: add a5, a3, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB80_1 -; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_add_i16_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB80_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-NOZACAS-NEXT: add a5, a3, a1 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB80_1 +; RV32IA-NOZACAS-NEXT: # %bb.2: +; RV32IA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_add_i16_monotonic: ; RV64I: # %bb.0: @@ -11549,6 +15066,27 @@ define i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_add_i16_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: lui a3, 16 +; RV32IA-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB80_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-ZACAS-NEXT: add a5, a3, a1 +; RV32IA-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB80_1 +; RV32IA-ZACAS-NEXT: # %bb.2: +; RV32IA-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_add_i16_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -11570,6 +15108,16 @@ define i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_add_i16_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoadd.h a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_add_i16_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i16_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoadd.h a0, a1, (a0) @@ -11594,47 +15142,47 @@ define i16 @atomicrmw_add_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_add_i16_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a3, (a2) -; RV32IA-WMO-NEXT: add a5, a3, a1 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: and a5, a5, a4 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: sc.w a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB81_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a3, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-NOZACAS-NEXT: add a5, a3, a1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB81_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_add_i16_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a3, (a2) -; RV32IA-TSO-NEXT: add a5, a3, a1 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: and a5, a5, a4 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB81_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a3, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_add_i16_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-NOZACAS-NEXT: add a5, a3, a1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB81_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_add_i16_acquire: ; RV64I: # %bb.0: @@ -11688,6 +15236,48 @@ define i16 @atomicrmw_add_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_add_i16_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-ZACAS-NEXT: add a5, a3, a1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB81_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_add_i16_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB81_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZACAS-NEXT: add a5, a3, a1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB81_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_add_i16_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -11730,6 +15320,16 @@ define i16 @atomicrmw_add_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_add_i16_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoadd.h.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_add_i16_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i16_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoadd.h.aq a0, a1, (a0) @@ -11754,47 +15354,47 @@ define i16 @atomicrmw_add_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_add_i16_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w a3, (a2) -; RV32IA-WMO-NEXT: add a5, a3, a1 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: and a5, a5, a4 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB82_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a3, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-WMO-NOZACAS-NEXT: add a5, a3, a1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB82_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_add_i16_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a3, (a2) -; RV32IA-TSO-NEXT: add a5, a3, a1 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: and a5, a5, a4 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB82_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a3, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_add_i16_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-NOZACAS-NEXT: add a5, a3, a1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB82_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_add_i16_release: ; RV64I: # %bb.0: @@ -11848,6 +15448,48 @@ define i16 @atomicrmw_add_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_add_i16_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-WMO-ZACAS-NEXT: add a5, a3, a1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB82_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_add_i16_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB82_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZACAS-NEXT: add a5, a3, a1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB82_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_add_i16_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -11890,6 +15532,16 @@ define i16 @atomicrmw_add_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_add_i16_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoadd.h.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_add_i16_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i16_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoadd.h.rl a0, a1, (a0) @@ -11914,47 +15566,47 @@ define i16 @atomicrmw_add_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_add_i16_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a3, (a2) -; RV32IA-WMO-NEXT: add a5, a3, a1 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: and a5, a5, a4 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB83_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a3, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_add_i16_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-NOZACAS-NEXT: add a5, a3, a1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB83_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_add_i16_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a3, (a2) -; RV32IA-TSO-NEXT: add a5, a3, a1 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: and a5, a5, a4 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB83_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a3, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_add_i16_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-NOZACAS-NEXT: add a5, a3, a1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB83_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_add_i16_acq_rel: ; RV64I: # %bb.0: @@ -12008,6 +15660,48 @@ define i16 @atomicrmw_add_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_add_i16_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-ZACAS-NEXT: add a5, a3, a1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB83_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_add_i16_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB83_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZACAS-NEXT: add a5, a3, a1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB83_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_add_i16_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -12050,6 +15744,16 @@ define i16 @atomicrmw_add_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_add_i16_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoadd.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_add_i16_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i16_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoadd.h.aqrl a0, a1, (a0) @@ -12074,26 +15778,26 @@ define i16 @atomicrmw_add_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_add_i16_seq_cst: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB84_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a3, (a2) -; RV32IA-NEXT: add a5, a3, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB84_1 -; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_add_i16_seq_cst: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB84_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2) +; RV32IA-NOZACAS-NEXT: add a5, a3, a1 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB84_1 +; RV32IA-NOZACAS-NEXT: # %bb.2: +; RV32IA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_add_i16_seq_cst: ; RV64I: # %bb.0: @@ -12126,6 +15830,27 @@ define i16 @atomicrmw_add_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_add_i16_seq_cst: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: lui a3, 16 +; RV32IA-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB84_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w.aqrl a3, (a2) +; RV32IA-ZACAS-NEXT: add a5, a3, a1 +; RV32IA-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB84_1 +; RV32IA-ZACAS-NEXT: # %bb.2: +; RV32IA-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_add_i16_seq_cst: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -12147,6 +15872,16 @@ define i16 @atomicrmw_add_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_add_i16_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoadd.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_add_i16_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_add_i16_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoadd.h.aqrl a0, a1, (a0) @@ -12171,26 +15906,26 @@ define i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_sub_i16_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB85_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a3, (a2) -; RV32IA-NEXT: sub a5, a3, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB85_1 -; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_sub_i16_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB85_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-NOZACAS-NEXT: sub a5, a3, a1 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB85_1 +; RV32IA-NOZACAS-NEXT: # %bb.2: +; RV32IA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_sub_i16_monotonic: ; RV64I: # %bb.0: @@ -12223,6 +15958,27 @@ define i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_sub_i16_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: lui a3, 16 +; RV32IA-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB85_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-ZACAS-NEXT: sub a5, a3, a1 +; RV32IA-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB85_1 +; RV32IA-ZACAS-NEXT: # %bb.2: +; RV32IA-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_sub_i16_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -12244,6 +16000,18 @@ define i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_sub_i16_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: neg a1, a1 +; RV32IA-WMO-ZABHA-NEXT: amoadd.h a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_sub_i16_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: neg a1, a1 +; RV32IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i16_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: neg a1, a1 @@ -12270,47 +16038,47 @@ define i16 @atomicrmw_sub_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_sub_i16_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a3, (a2) -; RV32IA-WMO-NEXT: sub a5, a3, a1 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: and a5, a5, a4 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: sc.w a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB86_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a3, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-NOZACAS-NEXT: sub a5, a3, a1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB86_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_sub_i16_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a3, (a2) -; RV32IA-TSO-NEXT: sub a5, a3, a1 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: and a5, a5, a4 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB86_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a3, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_sub_i16_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-NOZACAS-NEXT: sub a5, a3, a1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB86_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_sub_i16_acquire: ; RV64I: # %bb.0: @@ -12364,6 +16132,48 @@ define i16 @atomicrmw_sub_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_sub_i16_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-ZACAS-NEXT: sub a5, a3, a1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB86_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_sub_i16_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB86_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZACAS-NEXT: sub a5, a3, a1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB86_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_sub_i16_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -12406,6 +16216,18 @@ define i16 @atomicrmw_sub_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_sub_i16_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: neg a1, a1 +; RV32IA-WMO-ZABHA-NEXT: amoadd.h.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_sub_i16_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: neg a1, a1 +; RV32IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i16_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: neg a1, a1 @@ -12432,47 +16254,47 @@ define i16 @atomicrmw_sub_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_sub_i16_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w a3, (a2) -; RV32IA-WMO-NEXT: sub a5, a3, a1 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: and a5, a5, a4 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB87_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a3, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-WMO-NOZACAS-NEXT: sub a5, a3, a1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB87_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_sub_i16_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a3, (a2) -; RV32IA-TSO-NEXT: sub a5, a3, a1 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: and a5, a5, a4 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB87_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a3, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_sub_i16_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-NOZACAS-NEXT: sub a5, a3, a1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB87_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_sub_i16_release: ; RV64I: # %bb.0: @@ -12526,6 +16348,48 @@ define i16 @atomicrmw_sub_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_sub_i16_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-WMO-ZACAS-NEXT: sub a5, a3, a1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB87_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_sub_i16_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB87_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZACAS-NEXT: sub a5, a3, a1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB87_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_sub_i16_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -12568,6 +16432,18 @@ define i16 @atomicrmw_sub_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_sub_i16_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: neg a1, a1 +; RV32IA-WMO-ZABHA-NEXT: amoadd.h.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_sub_i16_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: neg a1, a1 +; RV32IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i16_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: neg a1, a1 @@ -12594,47 +16470,47 @@ define i16 @atomicrmw_sub_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_sub_i16_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a3, (a2) -; RV32IA-WMO-NEXT: sub a5, a3, a1 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: and a5, a5, a4 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB88_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a3, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_sub_i16_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-NOZACAS-NEXT: sub a5, a3, a1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB88_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_sub_i16_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a3, (a2) -; RV32IA-TSO-NEXT: sub a5, a3, a1 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: and a5, a5, a4 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB88_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a3, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_sub_i16_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-NOZACAS-NEXT: sub a5, a3, a1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB88_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_sub_i16_acq_rel: ; RV64I: # %bb.0: @@ -12688,6 +16564,48 @@ define i16 @atomicrmw_sub_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_sub_i16_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-ZACAS-NEXT: sub a5, a3, a1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB88_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_sub_i16_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB88_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZACAS-NEXT: sub a5, a3, a1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB88_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_sub_i16_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -12730,6 +16648,18 @@ define i16 @atomicrmw_sub_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_sub_i16_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: neg a1, a1 +; RV32IA-WMO-ZABHA-NEXT: amoadd.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_sub_i16_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: neg a1, a1 +; RV32IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i16_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: neg a1, a1 @@ -12756,26 +16686,26 @@ define i16 @atomicrmw_sub_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_sub_i16_seq_cst: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB89_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a3, (a2) -; RV32IA-NEXT: sub a5, a3, a1 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB89_1 -; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_sub_i16_seq_cst: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB89_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2) +; RV32IA-NOZACAS-NEXT: sub a5, a3, a1 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB89_1 +; RV32IA-NOZACAS-NEXT: # %bb.2: +; RV32IA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_sub_i16_seq_cst: ; RV64I: # %bb.0: @@ -12808,6 +16738,27 @@ define i16 @atomicrmw_sub_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_sub_i16_seq_cst: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: lui a3, 16 +; RV32IA-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB89_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w.aqrl a3, (a2) +; RV32IA-ZACAS-NEXT: sub a5, a3, a1 +; RV32IA-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB89_1 +; RV32IA-ZACAS-NEXT: # %bb.2: +; RV32IA-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_sub_i16_seq_cst: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -12829,6 +16780,18 @@ define i16 @atomicrmw_sub_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_sub_i16_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: neg a1, a1 +; RV32IA-WMO-ZABHA-NEXT: amoadd.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_sub_i16_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: neg a1, a1 +; RV32IA-TSO-ZABHA-NEXT: amoadd.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_sub_i16_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: neg a1, a1 @@ -12855,20 +16818,20 @@ define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_and_i16_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: not a3, a4 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: or a1, a1, a3 -; RV32IA-NEXT: amoand.w a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_and_i16_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-NOZACAS-NEXT: not a3, a4 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: or a1, a1, a3 +; RV32IA-NOZACAS-NEXT: amoand.w a1, a1, (a2) +; RV32IA-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_and_i16_monotonic: ; RV64I: # %bb.0: @@ -12895,6 +16858,21 @@ define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_and_i16_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: lui a3, 16 +; RV32IA-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-ZACAS-NEXT: not a3, a4 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: or a1, a1, a3 +; RV32IA-ZACAS-NEXT: amoand.w a1, a1, (a2) +; RV32IA-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_and_i16_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -12910,6 +16888,16 @@ define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_and_i16_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoand.h a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_and_i16_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoand.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i16_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoand.h a0, a1, (a0) @@ -12934,35 +16922,35 @@ define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_and_i16_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: not a3, a4 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: or a1, a1, a3 -; RV32IA-WMO-NEXT: amoand.w.aq a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: not a3, a4 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: or a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: amoand.w.aq a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_and_i16_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: not a3, a4 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: or a1, a1, a3 -; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_and_i16_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: not a3, a4 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: or a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_and_i16_acquire: ; RV64I: # %bb.0: @@ -13004,6 +16992,36 @@ define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_and_i16_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: not a3, a4 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: or a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: amoand.w.aq a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_and_i16_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: not a3, a4 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: or a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i16_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -13034,6 +17052,16 @@ define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_and_i16_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoand.h.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_and_i16_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoand.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i16_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoand.h.aq a0, a1, (a0) @@ -13058,35 +17086,35 @@ define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_and_i16_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: not a3, a4 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: or a1, a1, a3 -; RV32IA-WMO-NEXT: amoand.w.rl a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: not a3, a4 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: or a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: amoand.w.rl a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_and_i16_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: not a3, a4 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: or a1, a1, a3 -; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_and_i16_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: not a3, a4 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: or a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_and_i16_release: ; RV64I: # %bb.0: @@ -13128,6 +17156,36 @@ define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_and_i16_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: not a3, a4 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: or a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: amoand.w.rl a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_and_i16_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: not a3, a4 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: or a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i16_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -13158,6 +17216,16 @@ define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_and_i16_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoand.h.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_and_i16_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoand.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i16_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoand.h.rl a0, a1, (a0) @@ -13182,35 +17250,35 @@ define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_and_i16_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: not a3, a4 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: or a1, a1, a3 -; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: not a3, a4 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: or a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_and_i16_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: not a3, a4 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: or a1, a1, a3 -; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_and_i16_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: not a3, a4 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: or a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_and_i16_acq_rel: ; RV64I: # %bb.0: @@ -13252,6 +17320,36 @@ define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_and_i16_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: not a3, a4 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: or a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_and_i16_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: not a3, a4 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: or a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i16_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -13282,6 +17380,16 @@ define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_and_i16_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoand.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_and_i16_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoand.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i16_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoand.h.aqrl a0, a1, (a0) @@ -13306,35 +17414,35 @@ define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_and_i16_seq_cst: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: not a3, a4 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: or a1, a1, a3 -; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_and_i16_seq_cst: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: not a3, a4 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: or a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: amoand.w.aqrl a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_and_i16_seq_cst: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: not a3, a4 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: or a1, a1, a3 -; RV32IA-TSO-NEXT: amoand.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_and_i16_seq_cst: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: not a3, a4 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: or a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: amoand.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_and_i16_seq_cst: ; RV64I: # %bb.0: @@ -13376,6 +17484,36 @@ define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_and_i16_seq_cst: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: not a3, a4 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: or a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: amoand.w.aqrl a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_and_i16_seq_cst: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: not a3, a4 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: or a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: amoand.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_and_i16_seq_cst: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -13406,6 +17544,16 @@ define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_and_i16_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoand.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_and_i16_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoand.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_and_i16_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoand.h.aqrl a0, a1, (a0) @@ -13430,27 +17578,27 @@ define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_nand_i16_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a3, (a2) -; RV32IA-NEXT: and a5, a3, a1 -; RV32IA-NEXT: not a5, a5 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB95_1 -; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_nand_i16_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-NOZACAS-NEXT: and a5, a3, a1 +; RV32IA-NOZACAS-NEXT: not a5, a5 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB95_1 +; RV32IA-NOZACAS-NEXT: # %bb.2: +; RV32IA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_nand_i16_monotonic: ; RV64I: # %bb.0: @@ -13484,6 +17632,28 @@ define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_nand_i16_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: lui a3, 16 +; RV32IA-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-ZACAS-NEXT: and a5, a3, a1 +; RV32IA-ZACAS-NEXT: not a5, a5 +; RV32IA-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB95_1 +; RV32IA-ZACAS-NEXT: # %bb.2: +; RV32IA-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_nand_i16_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -13506,6 +17676,50 @@ define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_monotonic: +; RV32IA-WMO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a3, a1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB95_1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_monotonic: +; RV32IA-TSO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a3, a1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB95_1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_monotonic: ; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 @@ -13550,6 +17764,36 @@ define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_monotonic: +; RV32IA-WMO-ZABHA-ZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: .LBB95_1: # %atomicrmw.start +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 16 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: amocas.h a0, a3, (a2) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 16 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB95_1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-WMO-ZABHA-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_monotonic: +; RV32IA-TSO-ZABHA-ZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: .LBB95_1: # %atomicrmw.start +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 16 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: amocas.h a0, a3, (a2) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 16 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB95_1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-TSO-ZABHA-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_monotonic: ; RV64IA-WMO-ZABHA-ZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 @@ -13594,49 +17838,49 @@ define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_nand_i16_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a3, (a2) -; RV32IA-WMO-NEXT: and a5, a3, a1 -; RV32IA-WMO-NEXT: not a5, a5 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: and a5, a5, a4 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: sc.w a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB96_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a3, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a5, a3, a1 +; RV32IA-WMO-NOZACAS-NEXT: not a5, a5 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB96_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_nand_i16_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a3, (a2) -; RV32IA-TSO-NEXT: and a5, a3, a1 -; RV32IA-TSO-NEXT: not a5, a5 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: and a5, a5, a4 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB96_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a3, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_nand_i16_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a5, a3, a1 +; RV32IA-TSO-NOZACAS-NEXT: not a5, a5 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB96_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_nand_i16_acquire: ; RV64I: # %bb.0: @@ -13692,6 +17936,50 @@ define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_nand_i16_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a5, a3, a1 +; RV32IA-WMO-ZACAS-NEXT: not a5, a5 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB96_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_nand_i16_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a5, a3, a1 +; RV32IA-TSO-ZACAS-NEXT: not a5, a5 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB96_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_nand_i16_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -13736,6 +18024,50 @@ define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_acquire: +; RV32IA-WMO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a3, a1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB96_1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_acquire: +; RV32IA-TSO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a3, a1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB96_1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_acquire: ; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 @@ -13780,6 +18112,36 @@ define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_acquire: +; RV32IA-WMO-ZABHA-ZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: .LBB96_1: # %atomicrmw.start +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 16 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: amocas.h.aq a0, a3, (a2) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 16 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB96_1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-WMO-ZABHA-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_acquire: +; RV32IA-TSO-ZABHA-ZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: .LBB96_1: # %atomicrmw.start +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 16 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: amocas.h a0, a3, (a2) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 16 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB96_1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-TSO-ZABHA-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_acquire: ; RV64IA-WMO-ZABHA-ZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 @@ -13824,49 +18186,49 @@ define i16 @atomicrmw_nand_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_nand_i16_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w a3, (a2) -; RV32IA-WMO-NEXT: and a5, a3, a1 -; RV32IA-WMO-NEXT: not a5, a5 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: and a5, a5, a4 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB97_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a3, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a5, a3, a1 +; RV32IA-WMO-NOZACAS-NEXT: not a5, a5 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB97_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_nand_i16_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a3, (a2) -; RV32IA-TSO-NEXT: and a5, a3, a1 -; RV32IA-TSO-NEXT: not a5, a5 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: and a5, a5, a4 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB97_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a3, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_nand_i16_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a5, a3, a1 +; RV32IA-TSO-NOZACAS-NEXT: not a5, a5 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB97_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_nand_i16_release: ; RV64I: # %bb.0: @@ -13922,6 +18284,50 @@ define i16 @atomicrmw_nand_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_nand_i16_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a5, a3, a1 +; RV32IA-WMO-ZACAS-NEXT: not a5, a5 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB97_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_nand_i16_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a5, a3, a1 +; RV32IA-TSO-ZACAS-NEXT: not a5, a5 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB97_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_nand_i16_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -13966,6 +18372,50 @@ define i16 @atomicrmw_nand_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_release: +; RV32IA-WMO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a3, a1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB97_1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_release: +; RV32IA-TSO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a3, a1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB97_1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_release: ; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 @@ -14010,6 +18460,36 @@ define i16 @atomicrmw_nand_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_release: +; RV32IA-WMO-ZABHA-ZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: .LBB97_1: # %atomicrmw.start +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 16 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: amocas.h.rl a0, a3, (a2) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 16 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB97_1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-WMO-ZABHA-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_release: +; RV32IA-TSO-ZABHA-ZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: .LBB97_1: # %atomicrmw.start +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 16 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: amocas.h a0, a3, (a2) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 16 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB97_1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-TSO-ZABHA-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_release: ; RV64IA-WMO-ZABHA-ZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 @@ -14054,49 +18534,49 @@ define i16 @atomicrmw_nand_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_nand_i16_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a3, (a2) -; RV32IA-WMO-NEXT: and a5, a3, a1 -; RV32IA-WMO-NEXT: not a5, a5 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: and a5, a5, a4 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB98_1 -; RV32IA-WMO-NEXT: # %bb.2: -; RV32IA-WMO-NEXT: srl a0, a3, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_nand_i16_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a5, a3, a1 +; RV32IA-WMO-NOZACAS-NEXT: not a5, a5 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB98_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_nand_i16_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a3, (a2) -; RV32IA-TSO-NEXT: and a5, a3, a1 -; RV32IA-TSO-NEXT: not a5, a5 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: and a5, a5, a4 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB98_1 -; RV32IA-TSO-NEXT: # %bb.2: -; RV32IA-TSO-NEXT: srl a0, a3, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_nand_i16_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a5, a3, a1 +; RV32IA-TSO-NOZACAS-NEXT: not a5, a5 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB98_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_nand_i16_acq_rel: ; RV64I: # %bb.0: @@ -14152,6 +18632,50 @@ define i16 @atomicrmw_nand_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_nand_i16_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a5, a3, a1 +; RV32IA-WMO-ZACAS-NEXT: not a5, a5 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB98_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_nand_i16_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a5, a3, a1 +; RV32IA-TSO-ZACAS-NEXT: not a5, a5 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB98_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_nand_i16_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -14196,6 +18720,50 @@ define i16 @atomicrmw_nand_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_acq_rel: +; RV32IA-WMO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a3, a1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB98_1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_acq_rel: +; RV32IA-TSO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a3, a1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB98_1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_acq_rel: ; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 @@ -14240,6 +18808,36 @@ define i16 @atomicrmw_nand_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_acq_rel: +; RV32IA-WMO-ZABHA-ZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: .LBB98_1: # %atomicrmw.start +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 16 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: amocas.h.aqrl a0, a3, (a2) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 16 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB98_1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-WMO-ZABHA-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_acq_rel: +; RV32IA-TSO-ZABHA-ZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: .LBB98_1: # %atomicrmw.start +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 16 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: amocas.h a0, a3, (a2) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 16 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB98_1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-TSO-ZABHA-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_acq_rel: ; RV64IA-WMO-ZABHA-ZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 @@ -14284,27 +18882,27 @@ define i16 @atomicrmw_nand_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_nand_i16_seq_cst: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a3, (a2) -; RV32IA-NEXT: and a5, a3, a1 -; RV32IA-NEXT: not a5, a5 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB99_1 -; RV32IA-NEXT: # %bb.2: -; RV32IA-NEXT: srl a0, a3, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_nand_i16_seq_cst: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2) +; RV32IA-NOZACAS-NEXT: and a5, a3, a1 +; RV32IA-NOZACAS-NEXT: not a5, a5 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB99_1 +; RV32IA-NOZACAS-NEXT: # %bb.2: +; RV32IA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_nand_i16_seq_cst: ; RV64I: # %bb.0: @@ -14338,6 +18936,28 @@ define i16 @atomicrmw_nand_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_nand_i16_seq_cst: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: lui a3, 16 +; RV32IA-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w.aqrl a3, (a2) +; RV32IA-ZACAS-NEXT: and a5, a3, a1 +; RV32IA-ZACAS-NEXT: not a5, a5 +; RV32IA-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB99_1 +; RV32IA-ZACAS-NEXT: # %bb.2: +; RV32IA-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_nand_i16_seq_cst: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -14360,6 +18980,50 @@ define i16 @atomicrmw_nand_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_seq_cst: +; RV32IA-WMO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aqrl a3, (a2) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a3, a1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: not a5, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB99_1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_seq_cst: +; RV32IA-TSO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: lr.w.aqrl a3, (a2) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a3, a1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: not a5, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: bnez a5, .LBB99_1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i16_seq_cst: ; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-NOZACAS-NEXT: andi a2, a0, -4 @@ -14404,6 +19068,38 @@ define i16 @atomicrmw_nand_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_seq_cst: +; RV32IA-WMO-ZABHA-ZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: .LBB99_1: # %atomicrmw.start +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: and a3, a0, a1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: fence rw, rw +; RV32IA-WMO-ZABHA-ZACAS-NEXT: not a3, a3 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: slli a4, a0, 16 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: amocas.h.aqrl a0, a3, (a2) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: srai a4, a4, 16 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB99_1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-WMO-ZABHA-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_seq_cst: +; RV32IA-TSO-ZABHA-ZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: lhu a0, 0(a0) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: .LBB99_1: # %atomicrmw.start +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: and a3, a0, a1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: fence rw, rw +; RV32IA-TSO-ZABHA-ZACAS-NEXT: not a3, a3 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: slli a4, a0, 16 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: amocas.h a0, a3, (a2) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: srai a4, a4, 16 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a4, .LBB99_1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-TSO-ZABHA-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i16_seq_cst: ; RV64IA-WMO-ZABHA-ZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 @@ -14450,16 +19146,16 @@ define i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_or_i16_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: slli a1, a1, 16 -; RV32IA-NEXT: srli a1, a1, 16 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoor.w a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_or_i16_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-NOZACAS-NEXT: srli a1, a1, 16 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: amoor.w a1, a1, (a2) +; RV32IA-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_or_i16_monotonic: ; RV64I: # %bb.0: @@ -14482,6 +19178,17 @@ define i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_or_i16_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-ZACAS-NEXT: srli a1, a1, 16 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: amoor.w a1, a1, (a2) +; RV32IA-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_or_i16_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -14493,6 +19200,16 @@ define i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_or_i16_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoor.h a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_or_i16_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoor.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i16_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoor.h a0, a1, (a0) @@ -14517,27 +19234,27 @@ define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_or_i16_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: slli a1, a1, 16 -; RV32IA-WMO-NEXT: srli a1, a1, 16 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: amoor.w.aq a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: srli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoor.w.aq a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_or_i16_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: slli a1, a1, 16 -; RV32IA-TSO-NEXT: srli a1, a1, 16 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: amoor.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_or_i16_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: srli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_or_i16_acquire: ; RV64I: # %bb.0: @@ -14571,6 +19288,28 @@ define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_or_i16_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: srli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: amoor.w.aq a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_or_i16_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: srli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i16_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -14593,6 +19332,16 @@ define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_or_i16_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoor.h.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_or_i16_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoor.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i16_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoor.h.aq a0, a1, (a0) @@ -14617,27 +19366,27 @@ define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_or_i16_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: slli a1, a1, 16 -; RV32IA-WMO-NEXT: srli a1, a1, 16 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: amoor.w.rl a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: srli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoor.w.rl a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_or_i16_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: slli a1, a1, 16 -; RV32IA-TSO-NEXT: srli a1, a1, 16 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: amoor.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_or_i16_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: srli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_or_i16_release: ; RV64I: # %bb.0: @@ -14671,6 +19420,28 @@ define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_or_i16_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: srli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: amoor.w.rl a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_or_i16_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: srli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i16_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -14693,6 +19464,16 @@ define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_or_i16_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoor.h.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_or_i16_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoor.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i16_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoor.h.rl a0, a1, (a0) @@ -14717,27 +19498,27 @@ define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_or_i16_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: slli a1, a1, 16 -; RV32IA-WMO-NEXT: srli a1, a1, 16 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: amoor.w.aqrl a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: srli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_or_i16_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: slli a1, a1, 16 -; RV32IA-TSO-NEXT: srli a1, a1, 16 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: amoor.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_or_i16_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: srli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_or_i16_acq_rel: ; RV64I: # %bb.0: @@ -14771,6 +19552,28 @@ define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_or_i16_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: srli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_or_i16_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: srli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i16_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -14793,6 +19596,16 @@ define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_or_i16_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoor.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_or_i16_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoor.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i16_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoor.h.aqrl a0, a1, (a0) @@ -14817,27 +19630,27 @@ define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_or_i16_seq_cst: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: slli a1, a1, 16 -; RV32IA-WMO-NEXT: srli a1, a1, 16 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: amoor.w.aqrl a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_or_i16_seq_cst: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: srli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoor.w.aqrl a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_or_i16_seq_cst: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: slli a1, a1, 16 -; RV32IA-TSO-NEXT: srli a1, a1, 16 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: amoor.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_or_i16_seq_cst: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: srli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoor.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_or_i16_seq_cst: ; RV64I: # %bb.0: @@ -14871,6 +19684,28 @@ define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_or_i16_seq_cst: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: srli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: amoor.w.aqrl a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_or_i16_seq_cst: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: srli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: amoor.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_or_i16_seq_cst: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -14893,6 +19728,16 @@ define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_or_i16_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoor.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_or_i16_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoor.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_or_i16_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoor.h.aqrl a0, a1, (a0) @@ -14917,16 +19762,16 @@ define i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_xor_i16_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: slli a1, a1, 16 -; RV32IA-NEXT: srli a1, a1, 16 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: amoxor.w a1, a1, (a2) -; RV32IA-NEXT: srl a0, a1, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_xor_i16_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-NOZACAS-NEXT: srli a1, a1, 16 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: amoxor.w a1, a1, (a2) +; RV32IA-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xor_i16_monotonic: ; RV64I: # %bb.0: @@ -14949,6 +19794,17 @@ define i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_xor_i16_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-ZACAS-NEXT: srli a1, a1, 16 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: amoxor.w a1, a1, (a2) +; RV32IA-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_xor_i16_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -14960,6 +19816,16 @@ define i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xor_i16_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoxor.h a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xor_i16_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoxor.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i16_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoxor.h a0, a1, (a0) @@ -14984,27 +19850,27 @@ define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xor_i16_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: slli a1, a1, 16 -; RV32IA-WMO-NEXT: srli a1, a1, 16 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: amoxor.w.aq a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: srli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoxor.w.aq a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xor_i16_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: slli a1, a1, 16 -; RV32IA-TSO-NEXT: srli a1, a1, 16 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: amoxor.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i16_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: srli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xor_i16_acquire: ; RV64I: # %bb.0: @@ -15038,6 +19904,28 @@ define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xor_i16_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: srli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: amoxor.w.aq a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xor_i16_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: srli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i16_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -15060,6 +19948,16 @@ define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xor_i16_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoxor.h.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xor_i16_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoxor.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i16_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoxor.h.aq a0, a1, (a0) @@ -15084,27 +19982,27 @@ define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xor_i16_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: slli a1, a1, 16 -; RV32IA-WMO-NEXT: srli a1, a1, 16 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: amoxor.w.rl a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: srli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoxor.w.rl a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xor_i16_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: slli a1, a1, 16 -; RV32IA-TSO-NEXT: srli a1, a1, 16 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: amoxor.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i16_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: srli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xor_i16_release: ; RV64I: # %bb.0: @@ -15138,6 +20036,28 @@ define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xor_i16_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: srli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: amoxor.w.rl a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xor_i16_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: srli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i16_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -15160,6 +20080,16 @@ define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xor_i16_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoxor.h.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xor_i16_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoxor.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i16_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoxor.h.rl a0, a1, (a0) @@ -15184,27 +20114,27 @@ define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xor_i16_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: slli a1, a1, 16 -; RV32IA-WMO-NEXT: srli a1, a1, 16 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: amoxor.w.aqrl a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: srli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xor_i16_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: slli a1, a1, 16 -; RV32IA-TSO-NEXT: srli a1, a1, 16 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: amoxor.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i16_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: srli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xor_i16_acq_rel: ; RV64I: # %bb.0: @@ -15238,6 +20168,28 @@ define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xor_i16_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: srli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xor_i16_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: srli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i16_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -15260,6 +20212,16 @@ define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xor_i16_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoxor.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xor_i16_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoxor.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i16_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoxor.h.aqrl a0, a1, (a0) @@ -15284,27 +20246,27 @@ define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_xor_i16_seq_cst: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: slli a1, a1, 16 -; RV32IA-WMO-NEXT: srli a1, a1, 16 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: amoxor.w.aqrl a1, a1, (a2) -; RV32IA-WMO-NEXT: srl a0, a1, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_xor_i16_seq_cst: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: srli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2) +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_xor_i16_seq_cst: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: slli a1, a1, 16 -; RV32IA-TSO-NEXT: srli a1, a1, 16 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: amoxor.w a1, a1, (a2) -; RV32IA-TSO-NEXT: srl a0, a1, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_xor_i16_seq_cst: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: srli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: amoxor.w a1, a1, (a2) +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_xor_i16_seq_cst: ; RV64I: # %bb.0: @@ -15338,6 +20300,28 @@ define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_xor_i16_seq_cst: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: srli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: amoxor.w.aqrl a1, a1, (a2) +; RV32IA-WMO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_xor_i16_seq_cst: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: srli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: amoxor.w a1, a1, (a2) +; RV32IA-TSO-ZACAS-NEXT: srl a0, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_xor_i16_seq_cst: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -15360,6 +20344,16 @@ define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a1, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_xor_i16_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amoxor.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_xor_i16_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amoxor.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_xor_i16_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amoxor.h.aqrl a0, a1, (a0) @@ -15416,36 +20410,36 @@ define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_max_i16_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: slli a1, a1, 16 -; RV32IA-NEXT: li a4, 16 -; RV32IA-NEXT: andi a5, a0, 24 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: srai a1, a1, 16 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: sub a4, a4, a5 -; RV32IA-NEXT: .LBB110_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a5, (a2) -; RV32IA-NEXT: and a7, a5, a3 -; RV32IA-NEXT: mv a6, a5 -; RV32IA-NEXT: sll a7, a7, a4 -; RV32IA-NEXT: sra a7, a7, a4 -; RV32IA-NEXT: bge a7, a1, .LBB110_3 -; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB110_1 Depth=1 -; RV32IA-NEXT: xor a6, a5, a1 -; RV32IA-NEXT: and a6, a6, a3 -; RV32IA-NEXT: xor a6, a5, a6 -; RV32IA-NEXT: .LBB110_3: # in Loop: Header=BB110_1 Depth=1 -; RV32IA-NEXT: sc.w a6, a6, (a2) -; RV32IA-NEXT: bnez a6, .LBB110_1 -; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_max_i16_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-NOZACAS-NEXT: li a4, 16 +; RV32IA-NOZACAS-NEXT: andi a5, a0, 24 +; RV32IA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-NOZACAS-NEXT: srai a1, a1, 16 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: sub a4, a4, a5 +; RV32IA-NOZACAS-NEXT: .LBB110_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w a5, (a2) +; RV32IA-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-NOZACAS-NEXT: mv a6, a5 +; RV32IA-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-NOZACAS-NEXT: bge a7, a1, .LBB110_3 +; RV32IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB110_1 Depth=1 +; RV32IA-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-NOZACAS-NEXT: .LBB110_3: # in Loop: Header=BB110_1 Depth=1 +; RV32IA-NOZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-NOZACAS-NEXT: bnez a6, .LBB110_1 +; RV32IA-NOZACAS-NEXT: # %bb.4: +; RV32IA-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i16_monotonic: ; RV64I: # %bb.0: @@ -15520,6 +20514,37 @@ define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_max_i16_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: lui a3, 16 +; RV32IA-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-ZACAS-NEXT: li a4, 16 +; RV32IA-ZACAS-NEXT: andi a5, a0, 24 +; RV32IA-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-ZACAS-NEXT: srai a1, a1, 16 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: sub a4, a4, a5 +; RV32IA-ZACAS-NEXT: .LBB110_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w a5, (a2) +; RV32IA-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-ZACAS-NEXT: mv a6, a5 +; RV32IA-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-ZACAS-NEXT: bge a7, a1, .LBB110_3 +; RV32IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB110_1 Depth=1 +; RV32IA-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-ZACAS-NEXT: .LBB110_3: # in Loop: Header=BB110_1 Depth=1 +; RV32IA-ZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-ZACAS-NEXT: bnez a6, .LBB110_1 +; RV32IA-ZACAS-NEXT: # %bb.4: +; RV32IA-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_max_i16_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -15551,6 +20576,16 @@ define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_max_i16_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomax.h a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_max_i16_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomax.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i16_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomax.h a0, a1, (a0) @@ -15607,67 +20642,67 @@ define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_max_i16_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: slli a1, a1, 16 -; RV32IA-WMO-NEXT: li a4, 16 -; RV32IA-WMO-NEXT: andi a5, a0, 24 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: srai a1, a1, 16 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: sub a4, a4, a5 -; RV32IA-WMO-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a5, (a2) -; RV32IA-WMO-NEXT: and a7, a5, a3 -; RV32IA-WMO-NEXT: mv a6, a5 -; RV32IA-WMO-NEXT: sll a7, a7, a4 -; RV32IA-WMO-NEXT: sra a7, a7, a4 -; RV32IA-WMO-NEXT: bge a7, a1, .LBB111_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1 -; RV32IA-WMO-NEXT: xor a6, a5, a1 -; RV32IA-WMO-NEXT: and a6, a6, a3 -; RV32IA-WMO-NEXT: xor a6, a5, a6 -; RV32IA-WMO-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w a6, a6, (a2) -; RV32IA-WMO-NEXT: bnez a6, .LBB111_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a5, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: li a4, 16 +; RV32IA-WMO-NOZACAS-NEXT: andi a5, a0, 24 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: srai a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: sub a4, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: bge a7, a1, .LBB111_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-NOZACAS-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a6, .LBB111_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_max_i16_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: slli a1, a1, 16 -; RV32IA-TSO-NEXT: li a4, 16 -; RV32IA-TSO-NEXT: andi a5, a0, 24 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: srai a1, a1, 16 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: sub a4, a4, a5 -; RV32IA-TSO-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a5, (a2) -; RV32IA-TSO-NEXT: and a7, a5, a3 -; RV32IA-TSO-NEXT: mv a6, a5 -; RV32IA-TSO-NEXT: sll a7, a7, a4 -; RV32IA-TSO-NEXT: sra a7, a7, a4 -; RV32IA-TSO-NEXT: bge a7, a1, .LBB111_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1 -; RV32IA-TSO-NEXT: xor a6, a5, a1 -; RV32IA-TSO-NEXT: and a6, a6, a3 -; RV32IA-TSO-NEXT: xor a6, a5, a6 -; RV32IA-TSO-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a6, a6, (a2) -; RV32IA-TSO-NEXT: bnez a6, .LBB111_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a5, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_max_i16_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: li a4, 16 +; RV32IA-TSO-NOZACAS-NEXT: andi a5, a0, 24 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: srai a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: sub a4, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: bge a7, a1, .LBB111_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-NOZACAS-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a6, .LBB111_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i16_acquire: ; RV64I: # %bb.0: @@ -15773,6 +20808,68 @@ define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_max_i16_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: li a4, 16 +; RV32IA-WMO-ZACAS-NEXT: andi a5, a0, 24 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: srai a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: sub a4, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: bge a7, a1, .LBB111_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-ZACAS-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a6, .LBB111_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_max_i16_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: li a4, 16 +; RV32IA-TSO-ZACAS-NEXT: andi a5, a0, 24 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: srai a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: sub a4, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: .LBB111_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: bge a7, a1, .LBB111_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB111_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-ZACAS-NEXT: .LBB111_3: # in Loop: Header=BB111_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a6, .LBB111_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_max_i16_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -15835,6 +20932,16 @@ define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_max_i16_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomax.h.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_max_i16_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomax.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i16_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomax.h.aq a0, a1, (a0) @@ -15891,67 +20998,67 @@ define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_max_i16_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: slli a1, a1, 16 -; RV32IA-WMO-NEXT: li a4, 16 -; RV32IA-WMO-NEXT: andi a5, a0, 24 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: srai a1, a1, 16 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: sub a4, a4, a5 -; RV32IA-WMO-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w a5, (a2) -; RV32IA-WMO-NEXT: and a7, a5, a3 -; RV32IA-WMO-NEXT: mv a6, a5 -; RV32IA-WMO-NEXT: sll a7, a7, a4 -; RV32IA-WMO-NEXT: sra a7, a7, a4 -; RV32IA-WMO-NEXT: bge a7, a1, .LBB112_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1 -; RV32IA-WMO-NEXT: xor a6, a5, a1 -; RV32IA-WMO-NEXT: and a6, a6, a3 -; RV32IA-WMO-NEXT: xor a6, a5, a6 -; RV32IA-WMO-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w.rl a6, a6, (a2) -; RV32IA-WMO-NEXT: bnez a6, .LBB112_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a5, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: li a4, 16 +; RV32IA-WMO-NOZACAS-NEXT: andi a5, a0, 24 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: srai a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: sub a4, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: bge a7, a1, .LBB112_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-NOZACAS-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a6, .LBB112_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_max_i16_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: slli a1, a1, 16 -; RV32IA-TSO-NEXT: li a4, 16 -; RV32IA-TSO-NEXT: andi a5, a0, 24 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: srai a1, a1, 16 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: sub a4, a4, a5 -; RV32IA-TSO-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a5, (a2) -; RV32IA-TSO-NEXT: and a7, a5, a3 -; RV32IA-TSO-NEXT: mv a6, a5 -; RV32IA-TSO-NEXT: sll a7, a7, a4 -; RV32IA-TSO-NEXT: sra a7, a7, a4 -; RV32IA-TSO-NEXT: bge a7, a1, .LBB112_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1 -; RV32IA-TSO-NEXT: xor a6, a5, a1 -; RV32IA-TSO-NEXT: and a6, a6, a3 -; RV32IA-TSO-NEXT: xor a6, a5, a6 -; RV32IA-TSO-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a6, a6, (a2) -; RV32IA-TSO-NEXT: bnez a6, .LBB112_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a5, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_max_i16_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: li a4, 16 +; RV32IA-TSO-NOZACAS-NEXT: andi a5, a0, 24 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: srai a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: sub a4, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: bge a7, a1, .LBB112_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-NOZACAS-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a6, .LBB112_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i16_release: ; RV64I: # %bb.0: @@ -16057,6 +21164,68 @@ define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_max_i16_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: li a4, 16 +; RV32IA-WMO-ZACAS-NEXT: andi a5, a0, 24 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: srai a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: sub a4, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: bge a7, a1, .LBB112_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-ZACAS-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a6, .LBB112_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_max_i16_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: li a4, 16 +; RV32IA-TSO-ZACAS-NEXT: andi a5, a0, 24 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: srai a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: sub a4, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: .LBB112_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: bge a7, a1, .LBB112_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB112_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-ZACAS-NEXT: .LBB112_3: # in Loop: Header=BB112_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a6, .LBB112_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_max_i16_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -16119,6 +21288,16 @@ define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_max_i16_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomax.h.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_max_i16_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomax.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i16_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomax.h.rl a0, a1, (a0) @@ -16175,67 +21354,67 @@ define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_max_i16_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: slli a1, a1, 16 -; RV32IA-WMO-NEXT: li a4, 16 -; RV32IA-WMO-NEXT: andi a5, a0, 24 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: srai a1, a1, 16 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: sub a4, a4, a5 -; RV32IA-WMO-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a5, (a2) -; RV32IA-WMO-NEXT: and a7, a5, a3 -; RV32IA-WMO-NEXT: mv a6, a5 -; RV32IA-WMO-NEXT: sll a7, a7, a4 -; RV32IA-WMO-NEXT: sra a7, a7, a4 -; RV32IA-WMO-NEXT: bge a7, a1, .LBB113_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1 -; RV32IA-WMO-NEXT: xor a6, a5, a1 -; RV32IA-WMO-NEXT: and a6, a6, a3 -; RV32IA-WMO-NEXT: xor a6, a5, a6 -; RV32IA-WMO-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w.rl a6, a6, (a2) -; RV32IA-WMO-NEXT: bnez a6, .LBB113_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a5, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_max_i16_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: li a4, 16 +; RV32IA-WMO-NOZACAS-NEXT: andi a5, a0, 24 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: srai a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: sub a4, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: bge a7, a1, .LBB113_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-NOZACAS-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a6, .LBB113_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_max_i16_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: slli a1, a1, 16 -; RV32IA-TSO-NEXT: li a4, 16 -; RV32IA-TSO-NEXT: andi a5, a0, 24 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: srai a1, a1, 16 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: sub a4, a4, a5 -; RV32IA-TSO-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a5, (a2) -; RV32IA-TSO-NEXT: and a7, a5, a3 -; RV32IA-TSO-NEXT: mv a6, a5 -; RV32IA-TSO-NEXT: sll a7, a7, a4 -; RV32IA-TSO-NEXT: sra a7, a7, a4 -; RV32IA-TSO-NEXT: bge a7, a1, .LBB113_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1 -; RV32IA-TSO-NEXT: xor a6, a5, a1 -; RV32IA-TSO-NEXT: and a6, a6, a3 -; RV32IA-TSO-NEXT: xor a6, a5, a6 -; RV32IA-TSO-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a6, a6, (a2) -; RV32IA-TSO-NEXT: bnez a6, .LBB113_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a5, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_max_i16_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: li a4, 16 +; RV32IA-TSO-NOZACAS-NEXT: andi a5, a0, 24 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: srai a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: sub a4, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: bge a7, a1, .LBB113_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-NOZACAS-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a6, .LBB113_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i16_acq_rel: ; RV64I: # %bb.0: @@ -16341,6 +21520,68 @@ define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_max_i16_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: li a4, 16 +; RV32IA-WMO-ZACAS-NEXT: andi a5, a0, 24 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: srai a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: sub a4, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: bge a7, a1, .LBB113_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-ZACAS-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a6, .LBB113_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_max_i16_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: li a4, 16 +; RV32IA-TSO-ZACAS-NEXT: andi a5, a0, 24 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: srai a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: sub a4, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: .LBB113_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: bge a7, a1, .LBB113_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB113_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-ZACAS-NEXT: .LBB113_3: # in Loop: Header=BB113_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a6, .LBB113_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_max_i16_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -16403,6 +21644,16 @@ define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_max_i16_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomax.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_max_i16_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomax.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i16_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomax.h.aqrl a0, a1, (a0) @@ -16459,36 +21710,36 @@ define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_max_i16_seq_cst: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: slli a1, a1, 16 -; RV32IA-NEXT: li a4, 16 -; RV32IA-NEXT: andi a5, a0, 24 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: srai a1, a1, 16 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: sub a4, a4, a5 -; RV32IA-NEXT: .LBB114_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a5, (a2) -; RV32IA-NEXT: and a7, a5, a3 -; RV32IA-NEXT: mv a6, a5 -; RV32IA-NEXT: sll a7, a7, a4 -; RV32IA-NEXT: sra a7, a7, a4 -; RV32IA-NEXT: bge a7, a1, .LBB114_3 -; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB114_1 Depth=1 -; RV32IA-NEXT: xor a6, a5, a1 -; RV32IA-NEXT: and a6, a6, a3 -; RV32IA-NEXT: xor a6, a5, a6 -; RV32IA-NEXT: .LBB114_3: # in Loop: Header=BB114_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a6, a6, (a2) -; RV32IA-NEXT: bnez a6, .LBB114_1 -; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_max_i16_seq_cst: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-NOZACAS-NEXT: li a4, 16 +; RV32IA-NOZACAS-NEXT: andi a5, a0, 24 +; RV32IA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-NOZACAS-NEXT: srai a1, a1, 16 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: sub a4, a4, a5 +; RV32IA-NOZACAS-NEXT: .LBB114_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w.aqrl a5, (a2) +; RV32IA-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-NOZACAS-NEXT: mv a6, a5 +; RV32IA-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-NOZACAS-NEXT: bge a7, a1, .LBB114_3 +; RV32IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB114_1 Depth=1 +; RV32IA-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-NOZACAS-NEXT: .LBB114_3: # in Loop: Header=BB114_1 Depth=1 +; RV32IA-NOZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-NOZACAS-NEXT: bnez a6, .LBB114_1 +; RV32IA-NOZACAS-NEXT: # %bb.4: +; RV32IA-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i16_seq_cst: ; RV64I: # %bb.0: @@ -16563,6 +21814,37 @@ define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_max_i16_seq_cst: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: lui a3, 16 +; RV32IA-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-ZACAS-NEXT: li a4, 16 +; RV32IA-ZACAS-NEXT: andi a5, a0, 24 +; RV32IA-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-ZACAS-NEXT: srai a1, a1, 16 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: sub a4, a4, a5 +; RV32IA-ZACAS-NEXT: .LBB114_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w.aqrl a5, (a2) +; RV32IA-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-ZACAS-NEXT: mv a6, a5 +; RV32IA-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-ZACAS-NEXT: bge a7, a1, .LBB114_3 +; RV32IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB114_1 Depth=1 +; RV32IA-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-ZACAS-NEXT: .LBB114_3: # in Loop: Header=BB114_1 Depth=1 +; RV32IA-ZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-ZACAS-NEXT: bnez a6, .LBB114_1 +; RV32IA-ZACAS-NEXT: # %bb.4: +; RV32IA-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_max_i16_seq_cst: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -16594,6 +21876,16 @@ define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_max_i16_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomax.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_max_i16_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomax.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_max_i16_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomax.h.aqrl a0, a1, (a0) @@ -16650,36 +21942,36 @@ define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_min_i16_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: slli a1, a1, 16 -; RV32IA-NEXT: li a4, 16 -; RV32IA-NEXT: andi a5, a0, 24 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: srai a1, a1, 16 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: sub a4, a4, a5 -; RV32IA-NEXT: .LBB115_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a5, (a2) -; RV32IA-NEXT: and a7, a5, a3 -; RV32IA-NEXT: mv a6, a5 -; RV32IA-NEXT: sll a7, a7, a4 -; RV32IA-NEXT: sra a7, a7, a4 -; RV32IA-NEXT: bge a1, a7, .LBB115_3 -; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB115_1 Depth=1 -; RV32IA-NEXT: xor a6, a5, a1 -; RV32IA-NEXT: and a6, a6, a3 -; RV32IA-NEXT: xor a6, a5, a6 -; RV32IA-NEXT: .LBB115_3: # in Loop: Header=BB115_1 Depth=1 -; RV32IA-NEXT: sc.w a6, a6, (a2) -; RV32IA-NEXT: bnez a6, .LBB115_1 -; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_min_i16_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-NOZACAS-NEXT: li a4, 16 +; RV32IA-NOZACAS-NEXT: andi a5, a0, 24 +; RV32IA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-NOZACAS-NEXT: srai a1, a1, 16 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: sub a4, a4, a5 +; RV32IA-NOZACAS-NEXT: .LBB115_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w a5, (a2) +; RV32IA-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-NOZACAS-NEXT: mv a6, a5 +; RV32IA-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-NOZACAS-NEXT: bge a1, a7, .LBB115_3 +; RV32IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB115_1 Depth=1 +; RV32IA-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-NOZACAS-NEXT: .LBB115_3: # in Loop: Header=BB115_1 Depth=1 +; RV32IA-NOZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-NOZACAS-NEXT: bnez a6, .LBB115_1 +; RV32IA-NOZACAS-NEXT: # %bb.4: +; RV32IA-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i16_monotonic: ; RV64I: # %bb.0: @@ -16754,6 +22046,37 @@ define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_min_i16_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: lui a3, 16 +; RV32IA-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-ZACAS-NEXT: li a4, 16 +; RV32IA-ZACAS-NEXT: andi a5, a0, 24 +; RV32IA-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-ZACAS-NEXT: srai a1, a1, 16 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: sub a4, a4, a5 +; RV32IA-ZACAS-NEXT: .LBB115_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w a5, (a2) +; RV32IA-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-ZACAS-NEXT: mv a6, a5 +; RV32IA-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-ZACAS-NEXT: bge a1, a7, .LBB115_3 +; RV32IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB115_1 Depth=1 +; RV32IA-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-ZACAS-NEXT: .LBB115_3: # in Loop: Header=BB115_1 Depth=1 +; RV32IA-ZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-ZACAS-NEXT: bnez a6, .LBB115_1 +; RV32IA-ZACAS-NEXT: # %bb.4: +; RV32IA-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_min_i16_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -16785,6 +22108,16 @@ define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_min_i16_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomin.h a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_min_i16_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomin.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i16_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomin.h a0, a1, (a0) @@ -16841,67 +22174,67 @@ define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_min_i16_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: slli a1, a1, 16 -; RV32IA-WMO-NEXT: li a4, 16 -; RV32IA-WMO-NEXT: andi a5, a0, 24 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: srai a1, a1, 16 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: sub a4, a4, a5 -; RV32IA-WMO-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a5, (a2) -; RV32IA-WMO-NEXT: and a7, a5, a3 -; RV32IA-WMO-NEXT: mv a6, a5 -; RV32IA-WMO-NEXT: sll a7, a7, a4 -; RV32IA-WMO-NEXT: sra a7, a7, a4 -; RV32IA-WMO-NEXT: bge a1, a7, .LBB116_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1 -; RV32IA-WMO-NEXT: xor a6, a5, a1 -; RV32IA-WMO-NEXT: and a6, a6, a3 -; RV32IA-WMO-NEXT: xor a6, a5, a6 -; RV32IA-WMO-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w a6, a6, (a2) -; RV32IA-WMO-NEXT: bnez a6, .LBB116_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a5, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: li a4, 16 +; RV32IA-WMO-NOZACAS-NEXT: andi a5, a0, 24 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: srai a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: sub a4, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: bge a1, a7, .LBB116_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-NOZACAS-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a6, .LBB116_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_min_i16_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: slli a1, a1, 16 -; RV32IA-TSO-NEXT: li a4, 16 -; RV32IA-TSO-NEXT: andi a5, a0, 24 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: srai a1, a1, 16 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: sub a4, a4, a5 -; RV32IA-TSO-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a5, (a2) -; RV32IA-TSO-NEXT: and a7, a5, a3 -; RV32IA-TSO-NEXT: mv a6, a5 -; RV32IA-TSO-NEXT: sll a7, a7, a4 -; RV32IA-TSO-NEXT: sra a7, a7, a4 -; RV32IA-TSO-NEXT: bge a1, a7, .LBB116_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1 -; RV32IA-TSO-NEXT: xor a6, a5, a1 -; RV32IA-TSO-NEXT: and a6, a6, a3 -; RV32IA-TSO-NEXT: xor a6, a5, a6 -; RV32IA-TSO-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a6, a6, (a2) -; RV32IA-TSO-NEXT: bnez a6, .LBB116_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a5, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_min_i16_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: li a4, 16 +; RV32IA-TSO-NOZACAS-NEXT: andi a5, a0, 24 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: srai a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: sub a4, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: bge a1, a7, .LBB116_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-NOZACAS-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a6, .LBB116_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i16_acquire: ; RV64I: # %bb.0: @@ -17007,6 +22340,68 @@ define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_min_i16_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: li a4, 16 +; RV32IA-WMO-ZACAS-NEXT: andi a5, a0, 24 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: srai a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: sub a4, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: bge a1, a7, .LBB116_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-ZACAS-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a6, .LBB116_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_min_i16_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: li a4, 16 +; RV32IA-TSO-ZACAS-NEXT: andi a5, a0, 24 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: srai a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: sub a4, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: .LBB116_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: bge a1, a7, .LBB116_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB116_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-ZACAS-NEXT: .LBB116_3: # in Loop: Header=BB116_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a6, .LBB116_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_min_i16_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -17069,6 +22464,16 @@ define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_min_i16_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomin.h.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_min_i16_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomin.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i16_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomin.h.aq a0, a1, (a0) @@ -17125,67 +22530,67 @@ define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_min_i16_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: slli a1, a1, 16 -; RV32IA-WMO-NEXT: li a4, 16 -; RV32IA-WMO-NEXT: andi a5, a0, 24 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: srai a1, a1, 16 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: sub a4, a4, a5 -; RV32IA-WMO-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w a5, (a2) -; RV32IA-WMO-NEXT: and a7, a5, a3 -; RV32IA-WMO-NEXT: mv a6, a5 -; RV32IA-WMO-NEXT: sll a7, a7, a4 -; RV32IA-WMO-NEXT: sra a7, a7, a4 -; RV32IA-WMO-NEXT: bge a1, a7, .LBB117_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1 -; RV32IA-WMO-NEXT: xor a6, a5, a1 -; RV32IA-WMO-NEXT: and a6, a6, a3 -; RV32IA-WMO-NEXT: xor a6, a5, a6 -; RV32IA-WMO-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w.rl a6, a6, (a2) -; RV32IA-WMO-NEXT: bnez a6, .LBB117_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a5, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: li a4, 16 +; RV32IA-WMO-NOZACAS-NEXT: andi a5, a0, 24 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: srai a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: sub a4, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: bge a1, a7, .LBB117_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-NOZACAS-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a6, .LBB117_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_min_i16_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: slli a1, a1, 16 -; RV32IA-TSO-NEXT: li a4, 16 -; RV32IA-TSO-NEXT: andi a5, a0, 24 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: srai a1, a1, 16 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: sub a4, a4, a5 -; RV32IA-TSO-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a5, (a2) -; RV32IA-TSO-NEXT: and a7, a5, a3 -; RV32IA-TSO-NEXT: mv a6, a5 -; RV32IA-TSO-NEXT: sll a7, a7, a4 -; RV32IA-TSO-NEXT: sra a7, a7, a4 -; RV32IA-TSO-NEXT: bge a1, a7, .LBB117_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1 -; RV32IA-TSO-NEXT: xor a6, a5, a1 -; RV32IA-TSO-NEXT: and a6, a6, a3 -; RV32IA-TSO-NEXT: xor a6, a5, a6 -; RV32IA-TSO-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a6, a6, (a2) -; RV32IA-TSO-NEXT: bnez a6, .LBB117_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a5, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_min_i16_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: li a4, 16 +; RV32IA-TSO-NOZACAS-NEXT: andi a5, a0, 24 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: srai a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: sub a4, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: bge a1, a7, .LBB117_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-NOZACAS-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a6, .LBB117_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i16_release: ; RV64I: # %bb.0: @@ -17291,6 +22696,68 @@ define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_min_i16_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: li a4, 16 +; RV32IA-WMO-ZACAS-NEXT: andi a5, a0, 24 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: srai a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: sub a4, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: bge a1, a7, .LBB117_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-ZACAS-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a6, .LBB117_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_min_i16_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: li a4, 16 +; RV32IA-TSO-ZACAS-NEXT: andi a5, a0, 24 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: srai a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: sub a4, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: .LBB117_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: bge a1, a7, .LBB117_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB117_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-ZACAS-NEXT: .LBB117_3: # in Loop: Header=BB117_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a6, .LBB117_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_min_i16_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -17353,6 +22820,16 @@ define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_min_i16_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomin.h.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_min_i16_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomin.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i16_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomin.h.rl a0, a1, (a0) @@ -17409,67 +22886,67 @@ define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_min_i16_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: slli a1, a1, 16 -; RV32IA-WMO-NEXT: li a4, 16 -; RV32IA-WMO-NEXT: andi a5, a0, 24 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: srai a1, a1, 16 -; RV32IA-WMO-NEXT: sll a3, a3, a0 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: sub a4, a4, a5 -; RV32IA-WMO-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a5, (a2) -; RV32IA-WMO-NEXT: and a7, a5, a3 -; RV32IA-WMO-NEXT: mv a6, a5 -; RV32IA-WMO-NEXT: sll a7, a7, a4 -; RV32IA-WMO-NEXT: sra a7, a7, a4 -; RV32IA-WMO-NEXT: bge a1, a7, .LBB118_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1 -; RV32IA-WMO-NEXT: xor a6, a5, a1 -; RV32IA-WMO-NEXT: and a6, a6, a3 -; RV32IA-WMO-NEXT: xor a6, a5, a6 -; RV32IA-WMO-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w.rl a6, a6, (a2) -; RV32IA-WMO-NEXT: bnez a6, .LBB118_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a5, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_min_i16_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: li a4, 16 +; RV32IA-WMO-NOZACAS-NEXT: andi a5, a0, 24 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: srai a1, a1, 16 +; RV32IA-WMO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: sub a4, a4, a5 +; RV32IA-WMO-NOZACAS-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-NOZACAS-NEXT: bge a1, a7, .LBB118_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-NOZACAS-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a6, .LBB118_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_min_i16_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: slli a1, a1, 16 -; RV32IA-TSO-NEXT: li a4, 16 -; RV32IA-TSO-NEXT: andi a5, a0, 24 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: srai a1, a1, 16 -; RV32IA-TSO-NEXT: sll a3, a3, a0 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: sub a4, a4, a5 -; RV32IA-TSO-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a5, (a2) -; RV32IA-TSO-NEXT: and a7, a5, a3 -; RV32IA-TSO-NEXT: mv a6, a5 -; RV32IA-TSO-NEXT: sll a7, a7, a4 -; RV32IA-TSO-NEXT: sra a7, a7, a4 -; RV32IA-TSO-NEXT: bge a1, a7, .LBB118_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1 -; RV32IA-TSO-NEXT: xor a6, a5, a1 -; RV32IA-TSO-NEXT: and a6, a6, a3 -; RV32IA-TSO-NEXT: xor a6, a5, a6 -; RV32IA-TSO-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a6, a6, (a2) -; RV32IA-TSO-NEXT: bnez a6, .LBB118_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a5, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_min_i16_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: li a4, 16 +; RV32IA-TSO-NOZACAS-NEXT: andi a5, a0, 24 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: srai a1, a1, 16 +; RV32IA-TSO-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: sub a4, a4, a5 +; RV32IA-TSO-NOZACAS-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-NOZACAS-NEXT: bge a1, a7, .LBB118_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-NOZACAS-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a6, .LBB118_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i16_acq_rel: ; RV64I: # %bb.0: @@ -17575,6 +23052,68 @@ define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_min_i16_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: li a4, 16 +; RV32IA-WMO-ZACAS-NEXT: andi a5, a0, 24 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: srai a1, a1, 16 +; RV32IA-WMO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: sub a4, a4, a5 +; RV32IA-WMO-ZACAS-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-WMO-ZACAS-NEXT: mv a6, a5 +; RV32IA-WMO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-WMO-ZACAS-NEXT: bge a1, a7, .LBB118_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-WMO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-WMO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-WMO-ZACAS-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a6, .LBB118_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_min_i16_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: li a4, 16 +; RV32IA-TSO-ZACAS-NEXT: andi a5, a0, 24 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: srai a1, a1, 16 +; RV32IA-TSO-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: sub a4, a4, a5 +; RV32IA-TSO-ZACAS-NEXT: .LBB118_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-TSO-ZACAS-NEXT: mv a6, a5 +; RV32IA-TSO-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-TSO-ZACAS-NEXT: bge a1, a7, .LBB118_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB118_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-TSO-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-TSO-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-TSO-ZACAS-NEXT: .LBB118_3: # in Loop: Header=BB118_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a6, a6, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a6, .LBB118_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_min_i16_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -17637,6 +23176,16 @@ define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_min_i16_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomin.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_min_i16_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomin.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i16_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomin.h.aqrl a0, a1, (a0) @@ -17693,36 +23242,36 @@ define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_min_i16_seq_cst: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: slli a1, a1, 16 -; RV32IA-NEXT: li a4, 16 -; RV32IA-NEXT: andi a5, a0, 24 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: srai a1, a1, 16 -; RV32IA-NEXT: sll a3, a3, a0 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: sub a4, a4, a5 -; RV32IA-NEXT: .LBB119_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a5, (a2) -; RV32IA-NEXT: and a7, a5, a3 -; RV32IA-NEXT: mv a6, a5 -; RV32IA-NEXT: sll a7, a7, a4 -; RV32IA-NEXT: sra a7, a7, a4 -; RV32IA-NEXT: bge a1, a7, .LBB119_3 -; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB119_1 Depth=1 -; RV32IA-NEXT: xor a6, a5, a1 -; RV32IA-NEXT: and a6, a6, a3 -; RV32IA-NEXT: xor a6, a5, a6 -; RV32IA-NEXT: .LBB119_3: # in Loop: Header=BB119_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a6, a6, (a2) -; RV32IA-NEXT: bnez a6, .LBB119_1 -; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a5, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_min_i16_seq_cst: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-NOZACAS-NEXT: slli a1, a1, 16 +; RV32IA-NOZACAS-NEXT: li a4, 16 +; RV32IA-NOZACAS-NEXT: andi a5, a0, 24 +; RV32IA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-NOZACAS-NEXT: srai a1, a1, 16 +; RV32IA-NOZACAS-NEXT: sll a3, a3, a0 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: sub a4, a4, a5 +; RV32IA-NOZACAS-NEXT: .LBB119_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w.aqrl a5, (a2) +; RV32IA-NOZACAS-NEXT: and a7, a5, a3 +; RV32IA-NOZACAS-NEXT: mv a6, a5 +; RV32IA-NOZACAS-NEXT: sll a7, a7, a4 +; RV32IA-NOZACAS-NEXT: sra a7, a7, a4 +; RV32IA-NOZACAS-NEXT: bge a1, a7, .LBB119_3 +; RV32IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB119_1 Depth=1 +; RV32IA-NOZACAS-NEXT: xor a6, a5, a1 +; RV32IA-NOZACAS-NEXT: and a6, a6, a3 +; RV32IA-NOZACAS-NEXT: xor a6, a5, a6 +; RV32IA-NOZACAS-NEXT: .LBB119_3: # in Loop: Header=BB119_1 Depth=1 +; RV32IA-NOZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-NOZACAS-NEXT: bnez a6, .LBB119_1 +; RV32IA-NOZACAS-NEXT: # %bb.4: +; RV32IA-NOZACAS-NEXT: srl a0, a5, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i16_seq_cst: ; RV64I: # %bb.0: @@ -17797,6 +23346,37 @@ define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_min_i16_seq_cst: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: lui a3, 16 +; RV32IA-ZACAS-NEXT: slli a1, a1, 16 +; RV32IA-ZACAS-NEXT: li a4, 16 +; RV32IA-ZACAS-NEXT: andi a5, a0, 24 +; RV32IA-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-ZACAS-NEXT: srai a1, a1, 16 +; RV32IA-ZACAS-NEXT: sll a3, a3, a0 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: sub a4, a4, a5 +; RV32IA-ZACAS-NEXT: .LBB119_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w.aqrl a5, (a2) +; RV32IA-ZACAS-NEXT: and a7, a5, a3 +; RV32IA-ZACAS-NEXT: mv a6, a5 +; RV32IA-ZACAS-NEXT: sll a7, a7, a4 +; RV32IA-ZACAS-NEXT: sra a7, a7, a4 +; RV32IA-ZACAS-NEXT: bge a1, a7, .LBB119_3 +; RV32IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB119_1 Depth=1 +; RV32IA-ZACAS-NEXT: xor a6, a5, a1 +; RV32IA-ZACAS-NEXT: and a6, a6, a3 +; RV32IA-ZACAS-NEXT: xor a6, a5, a6 +; RV32IA-ZACAS-NEXT: .LBB119_3: # in Loop: Header=BB119_1 Depth=1 +; RV32IA-ZACAS-NEXT: sc.w.rl a6, a6, (a2) +; RV32IA-ZACAS-NEXT: bnez a6, .LBB119_1 +; RV32IA-ZACAS-NEXT: # %bb.4: +; RV32IA-ZACAS-NEXT: srl a0, a5, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_min_i16_seq_cst: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -17828,6 +23408,16 @@ define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a5, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_min_i16_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomin.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_min_i16_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomin.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_min_i16_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomin.h.aqrl a0, a1, (a0) @@ -17886,30 +23476,30 @@ define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_umax_i16_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB120_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a3, (a2) -; RV32IA-NEXT: and a6, a3, a4 -; RV32IA-NEXT: mv a5, a3 -; RV32IA-NEXT: bgeu a6, a1, .LBB120_3 -; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB120_1 Depth=1 -; RV32IA-NEXT: xor a5, a3, a1 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: .LBB120_3: # in Loop: Header=BB120_1 Depth=1 -; RV32IA-NEXT: sc.w a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB120_1 -; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a3, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_umax_i16_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB120_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-NOZACAS-NEXT: and a6, a3, a4 +; RV32IA-NOZACAS-NEXT: mv a5, a3 +; RV32IA-NOZACAS-NEXT: bgeu a6, a1, .LBB120_3 +; RV32IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB120_1 Depth=1 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a1 +; RV32IA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-NOZACAS-NEXT: .LBB120_3: # in Loop: Header=BB120_1 Depth=1 +; RV32IA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB120_1 +; RV32IA-NOZACAS-NEXT: # %bb.4: +; RV32IA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umax_i16_monotonic: ; RV64I: # %bb.0: @@ -17980,6 +23570,31 @@ define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_umax_i16_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: lui a3, 16 +; RV32IA-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB120_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-ZACAS-NEXT: and a6, a3, a4 +; RV32IA-ZACAS-NEXT: mv a5, a3 +; RV32IA-ZACAS-NEXT: bgeu a6, a1, .LBB120_3 +; RV32IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB120_1 Depth=1 +; RV32IA-ZACAS-NEXT: xor a5, a3, a1 +; RV32IA-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-ZACAS-NEXT: .LBB120_3: # in Loop: Header=BB120_1 Depth=1 +; RV32IA-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB120_1 +; RV32IA-ZACAS-NEXT: # %bb.4: +; RV32IA-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_umax_i16_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -18005,6 +23620,16 @@ define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_umax_i16_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomaxu.h a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_umax_i16_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomaxu.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i16_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomaxu.h a0, a1, (a0) @@ -18063,55 +23688,55 @@ define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_umax_i16_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a3, (a2) -; RV32IA-WMO-NEXT: and a6, a3, a4 -; RV32IA-WMO-NEXT: mv a5, a3 -; RV32IA-WMO-NEXT: bgeu a6, a1, .LBB121_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1 -; RV32IA-WMO-NEXT: xor a5, a3, a1 -; RV32IA-WMO-NEXT: and a5, a5, a4 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB121_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a3, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a6, a3, a4 +; RV32IA-WMO-NOZACAS-NEXT: mv a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: bgeu a6, a1, .LBB121_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB121_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_umax_i16_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a3, (a2) -; RV32IA-TSO-NEXT: and a6, a3, a4 -; RV32IA-TSO-NEXT: mv a5, a3 -; RV32IA-TSO-NEXT: bgeu a6, a1, .LBB121_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1 -; RV32IA-TSO-NEXT: xor a5, a3, a1 -; RV32IA-TSO-NEXT: and a5, a5, a4 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB121_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a3, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_umax_i16_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a6, a3, a4 +; RV32IA-TSO-NOZACAS-NEXT: mv a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: bgeu a6, a1, .LBB121_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB121_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umax_i16_acquire: ; RV64I: # %bb.0: @@ -18207,6 +23832,56 @@ define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_umax_i16_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a6, a3, a4 +; RV32IA-WMO-ZACAS-NEXT: mv a5, a3 +; RV32IA-WMO-ZACAS-NEXT: bgeu a6, a1, .LBB121_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a1 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB121_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_umax_i16_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB121_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a6, a3, a4 +; RV32IA-TSO-ZACAS-NEXT: mv a5, a3 +; RV32IA-TSO-ZACAS-NEXT: bgeu a6, a1, .LBB121_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB121_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a1 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: .LBB121_3: # in Loop: Header=BB121_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB121_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umax_i16_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -18257,6 +23932,16 @@ define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_umax_i16_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomaxu.h.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_umax_i16_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomaxu.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i16_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomaxu.h.aq a0, a1, (a0) @@ -18315,55 +24000,55 @@ define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_umax_i16_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w a3, (a2) -; RV32IA-WMO-NEXT: and a6, a3, a4 -; RV32IA-WMO-NEXT: mv a5, a3 -; RV32IA-WMO-NEXT: bgeu a6, a1, .LBB122_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1 -; RV32IA-WMO-NEXT: xor a5, a3, a1 -; RV32IA-WMO-NEXT: and a5, a5, a4 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB122_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a3, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a6, a3, a4 +; RV32IA-WMO-NOZACAS-NEXT: mv a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: bgeu a6, a1, .LBB122_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB122_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_umax_i16_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a3, (a2) -; RV32IA-TSO-NEXT: and a6, a3, a4 -; RV32IA-TSO-NEXT: mv a5, a3 -; RV32IA-TSO-NEXT: bgeu a6, a1, .LBB122_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1 -; RV32IA-TSO-NEXT: xor a5, a3, a1 -; RV32IA-TSO-NEXT: and a5, a5, a4 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB122_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a3, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_umax_i16_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a6, a3, a4 +; RV32IA-TSO-NOZACAS-NEXT: mv a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: bgeu a6, a1, .LBB122_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB122_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umax_i16_release: ; RV64I: # %bb.0: @@ -18459,6 +24144,56 @@ define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_umax_i16_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a6, a3, a4 +; RV32IA-WMO-ZACAS-NEXT: mv a5, a3 +; RV32IA-WMO-ZACAS-NEXT: bgeu a6, a1, .LBB122_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a1 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB122_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_umax_i16_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB122_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a6, a3, a4 +; RV32IA-TSO-ZACAS-NEXT: mv a5, a3 +; RV32IA-TSO-ZACAS-NEXT: bgeu a6, a1, .LBB122_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB122_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a1 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: .LBB122_3: # in Loop: Header=BB122_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB122_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umax_i16_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -18509,6 +24244,16 @@ define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_umax_i16_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomaxu.h.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_umax_i16_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomaxu.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i16_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomaxu.h.rl a0, a1, (a0) @@ -18567,55 +24312,55 @@ define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_umax_i16_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a3, (a2) -; RV32IA-WMO-NEXT: and a6, a3, a4 -; RV32IA-WMO-NEXT: mv a5, a3 -; RV32IA-WMO-NEXT: bgeu a6, a1, .LBB123_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1 -; RV32IA-WMO-NEXT: xor a5, a3, a1 -; RV32IA-WMO-NEXT: and a5, a5, a4 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB123_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a3, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umax_i16_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a6, a3, a4 +; RV32IA-WMO-NOZACAS-NEXT: mv a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: bgeu a6, a1, .LBB123_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB123_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_umax_i16_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a3, (a2) -; RV32IA-TSO-NEXT: and a6, a3, a4 -; RV32IA-TSO-NEXT: mv a5, a3 -; RV32IA-TSO-NEXT: bgeu a6, a1, .LBB123_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1 -; RV32IA-TSO-NEXT: xor a5, a3, a1 -; RV32IA-TSO-NEXT: and a5, a5, a4 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB123_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a3, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_umax_i16_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a6, a3, a4 +; RV32IA-TSO-NOZACAS-NEXT: mv a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: bgeu a6, a1, .LBB123_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB123_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umax_i16_acq_rel: ; RV64I: # %bb.0: @@ -18711,6 +24456,56 @@ define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_umax_i16_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a6, a3, a4 +; RV32IA-WMO-ZACAS-NEXT: mv a5, a3 +; RV32IA-WMO-ZACAS-NEXT: bgeu a6, a1, .LBB123_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a1 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB123_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_umax_i16_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB123_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a6, a3, a4 +; RV32IA-TSO-ZACAS-NEXT: mv a5, a3 +; RV32IA-TSO-ZACAS-NEXT: bgeu a6, a1, .LBB123_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB123_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a1 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: .LBB123_3: # in Loop: Header=BB123_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB123_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umax_i16_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -18761,6 +24556,16 @@ define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_umax_i16_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomaxu.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_umax_i16_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomaxu.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i16_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomaxu.h.aqrl a0, a1, (a0) @@ -18819,30 +24624,30 @@ define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_umax_i16_seq_cst: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB124_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a3, (a2) -; RV32IA-NEXT: and a6, a3, a4 -; RV32IA-NEXT: mv a5, a3 -; RV32IA-NEXT: bgeu a6, a1, .LBB124_3 -; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB124_1 Depth=1 -; RV32IA-NEXT: xor a5, a3, a1 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: .LBB124_3: # in Loop: Header=BB124_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB124_1 -; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a3, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_umax_i16_seq_cst: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB124_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2) +; RV32IA-NOZACAS-NEXT: and a6, a3, a4 +; RV32IA-NOZACAS-NEXT: mv a5, a3 +; RV32IA-NOZACAS-NEXT: bgeu a6, a1, .LBB124_3 +; RV32IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB124_1 Depth=1 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a1 +; RV32IA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-NOZACAS-NEXT: .LBB124_3: # in Loop: Header=BB124_1 Depth=1 +; RV32IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB124_1 +; RV32IA-NOZACAS-NEXT: # %bb.4: +; RV32IA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umax_i16_seq_cst: ; RV64I: # %bb.0: @@ -18913,6 +24718,31 @@ define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_umax_i16_seq_cst: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: lui a3, 16 +; RV32IA-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB124_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w.aqrl a3, (a2) +; RV32IA-ZACAS-NEXT: and a6, a3, a4 +; RV32IA-ZACAS-NEXT: mv a5, a3 +; RV32IA-ZACAS-NEXT: bgeu a6, a1, .LBB124_3 +; RV32IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB124_1 Depth=1 +; RV32IA-ZACAS-NEXT: xor a5, a3, a1 +; RV32IA-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-ZACAS-NEXT: .LBB124_3: # in Loop: Header=BB124_1 Depth=1 +; RV32IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB124_1 +; RV32IA-ZACAS-NEXT: # %bb.4: +; RV32IA-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_umax_i16_seq_cst: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -18938,6 +24768,16 @@ define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_umax_i16_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amomaxu.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_umax_i16_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amomaxu.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umax_i16_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amomaxu.h.aqrl a0, a1, (a0) @@ -18996,30 +24836,30 @@ define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_umin_i16_monotonic: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB125_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w a3, (a2) -; RV32IA-NEXT: and a6, a3, a4 -; RV32IA-NEXT: mv a5, a3 -; RV32IA-NEXT: bgeu a1, a6, .LBB125_3 -; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB125_1 Depth=1 -; RV32IA-NEXT: xor a5, a3, a1 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: .LBB125_3: # in Loop: Header=BB125_1 Depth=1 -; RV32IA-NEXT: sc.w a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB125_1 -; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a3, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_umin_i16_monotonic: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB125_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-NOZACAS-NEXT: and a6, a3, a4 +; RV32IA-NOZACAS-NEXT: mv a5, a3 +; RV32IA-NOZACAS-NEXT: bgeu a1, a6, .LBB125_3 +; RV32IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB125_1 Depth=1 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a1 +; RV32IA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-NOZACAS-NEXT: .LBB125_3: # in Loop: Header=BB125_1 Depth=1 +; RV32IA-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB125_1 +; RV32IA-NOZACAS-NEXT: # %bb.4: +; RV32IA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i16_monotonic: ; RV64I: # %bb.0: @@ -19090,6 +24930,31 @@ define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_umin_i16_monotonic: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: lui a3, 16 +; RV32IA-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB125_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-ZACAS-NEXT: and a6, a3, a4 +; RV32IA-ZACAS-NEXT: mv a5, a3 +; RV32IA-ZACAS-NEXT: bgeu a1, a6, .LBB125_3 +; RV32IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB125_1 Depth=1 +; RV32IA-ZACAS-NEXT: xor a5, a3, a1 +; RV32IA-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-ZACAS-NEXT: .LBB125_3: # in Loop: Header=BB125_1 Depth=1 +; RV32IA-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB125_1 +; RV32IA-ZACAS-NEXT: # %bb.4: +; RV32IA-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_umin_i16_monotonic: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -19115,6 +24980,16 @@ define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_umin_i16_monotonic: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amominu.h a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_umin_i16_monotonic: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amominu.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i16_monotonic: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amominu.h a0, a1, (a0) @@ -19173,55 +25048,55 @@ define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_umin_i16_acquire: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a3, (a2) -; RV32IA-WMO-NEXT: and a6, a3, a4 -; RV32IA-WMO-NEXT: mv a5, a3 -; RV32IA-WMO-NEXT: bgeu a1, a6, .LBB126_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1 -; RV32IA-WMO-NEXT: xor a5, a3, a1 -; RV32IA-WMO-NEXT: and a5, a5, a4 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB126_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a3, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_acquire: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a6, a3, a4 +; RV32IA-WMO-NOZACAS-NEXT: mv a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: bgeu a1, a6, .LBB126_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB126_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_umin_i16_acquire: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a3, (a2) -; RV32IA-TSO-NEXT: and a6, a3, a4 -; RV32IA-TSO-NEXT: mv a5, a3 -; RV32IA-TSO-NEXT: bgeu a1, a6, .LBB126_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1 -; RV32IA-TSO-NEXT: xor a5, a3, a1 -; RV32IA-TSO-NEXT: and a5, a5, a4 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB126_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a3, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_umin_i16_acquire: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a6, a3, a4 +; RV32IA-TSO-NOZACAS-NEXT: mv a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: bgeu a1, a6, .LBB126_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB126_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i16_acquire: ; RV64I: # %bb.0: @@ -19317,6 +25192,56 @@ define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_umin_i16_acquire: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a6, a3, a4 +; RV32IA-WMO-ZACAS-NEXT: mv a5, a3 +; RV32IA-WMO-ZACAS-NEXT: bgeu a1, a6, .LBB126_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a1 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB126_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_umin_i16_acquire: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a6, a3, a4 +; RV32IA-TSO-ZACAS-NEXT: mv a5, a3 +; RV32IA-TSO-ZACAS-NEXT: bgeu a1, a6, .LBB126_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB126_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a1 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: .LBB126_3: # in Loop: Header=BB126_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB126_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umin_i16_acquire: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -19367,6 +25292,16 @@ define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_umin_i16_acquire: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amominu.h.aq a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_umin_i16_acquire: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amominu.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i16_acquire: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amominu.h.aq a0, a1, (a0) @@ -19425,55 +25360,55 @@ define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_umin_i16_release: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w a3, (a2) -; RV32IA-WMO-NEXT: and a6, a3, a4 -; RV32IA-WMO-NEXT: mv a5, a3 -; RV32IA-WMO-NEXT: bgeu a1, a6, .LBB127_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1 -; RV32IA-WMO-NEXT: xor a5, a3, a1 -; RV32IA-WMO-NEXT: and a5, a5, a4 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB127_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a3, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_release: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a6, a3, a4 +; RV32IA-WMO-NOZACAS-NEXT: mv a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: bgeu a1, a6, .LBB127_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB127_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_umin_i16_release: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a3, (a2) -; RV32IA-TSO-NEXT: and a6, a3, a4 -; RV32IA-TSO-NEXT: mv a5, a3 -; RV32IA-TSO-NEXT: bgeu a1, a6, .LBB127_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1 -; RV32IA-TSO-NEXT: xor a5, a3, a1 -; RV32IA-TSO-NEXT: and a5, a5, a4 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB127_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a3, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_umin_i16_release: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a6, a3, a4 +; RV32IA-TSO-NOZACAS-NEXT: mv a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: bgeu a1, a6, .LBB127_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB127_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i16_release: ; RV64I: # %bb.0: @@ -19569,6 +25504,56 @@ define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_umin_i16_release: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a6, a3, a4 +; RV32IA-WMO-ZACAS-NEXT: mv a5, a3 +; RV32IA-WMO-ZACAS-NEXT: bgeu a1, a6, .LBB127_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a1 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB127_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_umin_i16_release: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB127_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a6, a3, a4 +; RV32IA-TSO-ZACAS-NEXT: mv a5, a3 +; RV32IA-TSO-ZACAS-NEXT: bgeu a1, a6, .LBB127_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB127_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a1 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: .LBB127_3: # in Loop: Header=BB127_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB127_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umin_i16_release: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -19619,6 +25604,16 @@ define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_umin_i16_release: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amominu.h.rl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_umin_i16_release: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amominu.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i16_release: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amominu.h.rl a0, a1, (a0) @@ -19677,55 +25672,55 @@ define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-WMO-LABEL: atomicrmw_umin_i16_acq_rel: -; RV32IA-WMO: # %bb.0: -; RV32IA-WMO-NEXT: andi a2, a0, -4 -; RV32IA-WMO-NEXT: slli a0, a0, 3 -; RV32IA-WMO-NEXT: lui a3, 16 -; RV32IA-WMO-NEXT: addi a3, a3, -1 -; RV32IA-WMO-NEXT: sll a4, a3, a0 -; RV32IA-WMO-NEXT: and a1, a1, a3 -; RV32IA-WMO-NEXT: sll a1, a1, a0 -; RV32IA-WMO-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-WMO-NEXT: lr.w.aq a3, (a2) -; RV32IA-WMO-NEXT: and a6, a3, a4 -; RV32IA-WMO-NEXT: mv a5, a3 -; RV32IA-WMO-NEXT: bgeu a1, a6, .LBB128_3 -; RV32IA-WMO-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1 -; RV32IA-WMO-NEXT: xor a5, a3, a1 -; RV32IA-WMO-NEXT: and a5, a5, a4 -; RV32IA-WMO-NEXT: xor a5, a3, a5 -; RV32IA-WMO-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1 -; RV32IA-WMO-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-WMO-NEXT: bnez a5, .LBB128_1 -; RV32IA-WMO-NEXT: # %bb.4: -; RV32IA-WMO-NEXT: srl a0, a3, a0 -; RV32IA-WMO-NEXT: ret +; RV32IA-WMO-NOZACAS-LABEL: atomicrmw_umin_i16_acq_rel: +; RV32IA-WMO-NOZACAS: # %bb.0: +; RV32IA-WMO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-NOZACAS-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-NOZACAS-NEXT: and a6, a3, a4 +; RV32IA-WMO-NOZACAS-NEXT: mv a5, a3 +; RV32IA-WMO-NOZACAS-NEXT: bgeu a1, a6, .LBB128_3 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a1 +; RV32IA-WMO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-NOZACAS-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1 +; RV32IA-WMO-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-NOZACAS-NEXT: bnez a5, .LBB128_1 +; RV32IA-WMO-NOZACAS-NEXT: # %bb.4: +; RV32IA-WMO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-NOZACAS-NEXT: ret ; -; RV32IA-TSO-LABEL: atomicrmw_umin_i16_acq_rel: -; RV32IA-TSO: # %bb.0: -; RV32IA-TSO-NEXT: andi a2, a0, -4 -; RV32IA-TSO-NEXT: slli a0, a0, 3 -; RV32IA-TSO-NEXT: lui a3, 16 -; RV32IA-TSO-NEXT: addi a3, a3, -1 -; RV32IA-TSO-NEXT: sll a4, a3, a0 -; RV32IA-TSO-NEXT: and a1, a1, a3 -; RV32IA-TSO-NEXT: sll a1, a1, a0 -; RV32IA-TSO-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-TSO-NEXT: lr.w a3, (a2) -; RV32IA-TSO-NEXT: and a6, a3, a4 -; RV32IA-TSO-NEXT: mv a5, a3 -; RV32IA-TSO-NEXT: bgeu a1, a6, .LBB128_3 -; RV32IA-TSO-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1 -; RV32IA-TSO-NEXT: xor a5, a3, a1 -; RV32IA-TSO-NEXT: and a5, a5, a4 -; RV32IA-TSO-NEXT: xor a5, a3, a5 -; RV32IA-TSO-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1 -; RV32IA-TSO-NEXT: sc.w a5, a5, (a2) -; RV32IA-TSO-NEXT: bnez a5, .LBB128_1 -; RV32IA-TSO-NEXT: # %bb.4: -; RV32IA-TSO-NEXT: srl a0, a3, a0 -; RV32IA-TSO-NEXT: ret +; RV32IA-TSO-NOZACAS-LABEL: atomicrmw_umin_i16_acq_rel: +; RV32IA-TSO-NOZACAS: # %bb.0: +; RV32IA-TSO-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-NOZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-NOZACAS-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-NOZACAS-NEXT: and a6, a3, a4 +; RV32IA-TSO-NOZACAS-NEXT: mv a5, a3 +; RV32IA-TSO-NOZACAS-NEXT: bgeu a1, a6, .LBB128_3 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a1 +; RV32IA-TSO-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-NOZACAS-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1 +; RV32IA-TSO-NOZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-NOZACAS-NEXT: bnez a5, .LBB128_1 +; RV32IA-TSO-NOZACAS-NEXT: # %bb.4: +; RV32IA-TSO-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i16_acq_rel: ; RV64I: # %bb.0: @@ -19821,6 +25816,56 @@ define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZACAS-LABEL: atomicrmw_umin_i16_acq_rel: +; RV32IA-WMO-ZACAS: # %bb.0: +; RV32IA-WMO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-WMO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-WMO-ZACAS-NEXT: lui a3, 16 +; RV32IA-WMO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-WMO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-WMO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-WMO-ZACAS-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZACAS-NEXT: lr.w.aq a3, (a2) +; RV32IA-WMO-ZACAS-NEXT: and a6, a3, a4 +; RV32IA-WMO-ZACAS-NEXT: mv a5, a3 +; RV32IA-WMO-ZACAS-NEXT: bgeu a1, a6, .LBB128_3 +; RV32IA-WMO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a1 +; RV32IA-WMO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-WMO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-WMO-ZACAS-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1 +; RV32IA-WMO-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-WMO-ZACAS-NEXT: bnez a5, .LBB128_1 +; RV32IA-WMO-ZACAS-NEXT: # %bb.4: +; RV32IA-WMO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-WMO-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZACAS-LABEL: atomicrmw_umin_i16_acq_rel: +; RV32IA-TSO-ZACAS: # %bb.0: +; RV32IA-TSO-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-TSO-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-TSO-ZACAS-NEXT: lui a3, 16 +; RV32IA-TSO-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-TSO-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-TSO-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-TSO-ZACAS-NEXT: .LBB128_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZACAS-NEXT: lr.w a3, (a2) +; RV32IA-TSO-ZACAS-NEXT: and a6, a3, a4 +; RV32IA-TSO-ZACAS-NEXT: mv a5, a3 +; RV32IA-TSO-ZACAS-NEXT: bgeu a1, a6, .LBB128_3 +; RV32IA-TSO-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB128_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a1 +; RV32IA-TSO-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-TSO-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-TSO-ZACAS-NEXT: .LBB128_3: # in Loop: Header=BB128_1 Depth=1 +; RV32IA-TSO-ZACAS-NEXT: sc.w a5, a5, (a2) +; RV32IA-TSO-ZACAS-NEXT: bnez a5, .LBB128_1 +; RV32IA-TSO-ZACAS-NEXT: # %bb.4: +; RV32IA-TSO-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-TSO-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZACAS-LABEL: atomicrmw_umin_i16_acq_rel: ; RV64IA-WMO-ZACAS: # %bb.0: ; RV64IA-WMO-ZACAS-NEXT: andi a2, a0, -4 @@ -19871,6 +25916,16 @@ define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_umin_i16_acq_rel: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amominu.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_umin_i16_acq_rel: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amominu.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i16_acq_rel: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amominu.h.aqrl a0, a1, (a0) @@ -19929,30 +25984,30 @@ define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; -; RV32IA-LABEL: atomicrmw_umin_i16_seq_cst: -; RV32IA: # %bb.0: -; RV32IA-NEXT: andi a2, a0, -4 -; RV32IA-NEXT: slli a0, a0, 3 -; RV32IA-NEXT: lui a3, 16 -; RV32IA-NEXT: addi a3, a3, -1 -; RV32IA-NEXT: sll a4, a3, a0 -; RV32IA-NEXT: and a1, a1, a3 -; RV32IA-NEXT: sll a1, a1, a0 -; RV32IA-NEXT: .LBB129_1: # =>This Inner Loop Header: Depth=1 -; RV32IA-NEXT: lr.w.aqrl a3, (a2) -; RV32IA-NEXT: and a6, a3, a4 -; RV32IA-NEXT: mv a5, a3 -; RV32IA-NEXT: bgeu a1, a6, .LBB129_3 -; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB129_1 Depth=1 -; RV32IA-NEXT: xor a5, a3, a1 -; RV32IA-NEXT: and a5, a5, a4 -; RV32IA-NEXT: xor a5, a3, a5 -; RV32IA-NEXT: .LBB129_3: # in Loop: Header=BB129_1 Depth=1 -; RV32IA-NEXT: sc.w.rl a5, a5, (a2) -; RV32IA-NEXT: bnez a5, .LBB129_1 -; RV32IA-NEXT: # %bb.4: -; RV32IA-NEXT: srl a0, a3, a0 -; RV32IA-NEXT: ret +; RV32IA-NOZACAS-LABEL: atomicrmw_umin_i16_seq_cst: +; RV32IA-NOZACAS: # %bb.0: +; RV32IA-NOZACAS-NEXT: andi a2, a0, -4 +; RV32IA-NOZACAS-NEXT: slli a0, a0, 3 +; RV32IA-NOZACAS-NEXT: lui a3, 16 +; RV32IA-NOZACAS-NEXT: addi a3, a3, -1 +; RV32IA-NOZACAS-NEXT: sll a4, a3, a0 +; RV32IA-NOZACAS-NEXT: and a1, a1, a3 +; RV32IA-NOZACAS-NEXT: sll a1, a1, a0 +; RV32IA-NOZACAS-NEXT: .LBB129_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-NOZACAS-NEXT: lr.w.aqrl a3, (a2) +; RV32IA-NOZACAS-NEXT: and a6, a3, a4 +; RV32IA-NOZACAS-NEXT: mv a5, a3 +; RV32IA-NOZACAS-NEXT: bgeu a1, a6, .LBB129_3 +; RV32IA-NOZACAS-NEXT: # %bb.2: # in Loop: Header=BB129_1 Depth=1 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a1 +; RV32IA-NOZACAS-NEXT: and a5, a5, a4 +; RV32IA-NOZACAS-NEXT: xor a5, a3, a5 +; RV32IA-NOZACAS-NEXT: .LBB129_3: # in Loop: Header=BB129_1 Depth=1 +; RV32IA-NOZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-NOZACAS-NEXT: bnez a5, .LBB129_1 +; RV32IA-NOZACAS-NEXT: # %bb.4: +; RV32IA-NOZACAS-NEXT: srl a0, a3, a0 +; RV32IA-NOZACAS-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i16_seq_cst: ; RV64I: # %bb.0: @@ -20023,6 +26078,31 @@ define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-NOZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-NOZACAS-NEXT: ret ; +; RV32IA-ZACAS-LABEL: atomicrmw_umin_i16_seq_cst: +; RV32IA-ZACAS: # %bb.0: +; RV32IA-ZACAS-NEXT: andi a2, a0, -4 +; RV32IA-ZACAS-NEXT: slli a0, a0, 3 +; RV32IA-ZACAS-NEXT: lui a3, 16 +; RV32IA-ZACAS-NEXT: addi a3, a3, -1 +; RV32IA-ZACAS-NEXT: sll a4, a3, a0 +; RV32IA-ZACAS-NEXT: and a1, a1, a3 +; RV32IA-ZACAS-NEXT: sll a1, a1, a0 +; RV32IA-ZACAS-NEXT: .LBB129_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-ZACAS-NEXT: lr.w.aqrl a3, (a2) +; RV32IA-ZACAS-NEXT: and a6, a3, a4 +; RV32IA-ZACAS-NEXT: mv a5, a3 +; RV32IA-ZACAS-NEXT: bgeu a1, a6, .LBB129_3 +; RV32IA-ZACAS-NEXT: # %bb.2: # in Loop: Header=BB129_1 Depth=1 +; RV32IA-ZACAS-NEXT: xor a5, a3, a1 +; RV32IA-ZACAS-NEXT: and a5, a5, a4 +; RV32IA-ZACAS-NEXT: xor a5, a3, a5 +; RV32IA-ZACAS-NEXT: .LBB129_3: # in Loop: Header=BB129_1 Depth=1 +; RV32IA-ZACAS-NEXT: sc.w.rl a5, a5, (a2) +; RV32IA-ZACAS-NEXT: bnez a5, .LBB129_1 +; RV32IA-ZACAS-NEXT: # %bb.4: +; RV32IA-ZACAS-NEXT: srl a0, a3, a0 +; RV32IA-ZACAS-NEXT: ret +; ; RV64IA-ZACAS-LABEL: atomicrmw_umin_i16_seq_cst: ; RV64IA-ZACAS: # %bb.0: ; RV64IA-ZACAS-NEXT: andi a2, a0, -4 @@ -20048,6 +26128,16 @@ define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind { ; RV64IA-ZACAS-NEXT: srlw a0, a3, a0 ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-LABEL: atomicrmw_umin_i16_seq_cst: +; RV32IA-WMO-ZABHA: # %bb.0: +; RV32IA-WMO-ZABHA-NEXT: amominu.h.aqrl a0, a1, (a0) +; RV32IA-WMO-ZABHA-NEXT: ret +; +; RV32IA-TSO-ZABHA-LABEL: atomicrmw_umin_i16_seq_cst: +; RV32IA-TSO-ZABHA: # %bb.0: +; RV32IA-TSO-ZABHA-NEXT: amominu.h a0, a1, (a0) +; RV32IA-TSO-ZABHA-NEXT: ret +; ; RV64IA-WMO-ZABHA-LABEL: atomicrmw_umin_i16_seq_cst: ; RV64IA-WMO-ZABHA: # %bb.0: ; RV64IA-WMO-ZABHA-NEXT: amominu.h.aqrl a0, a1, (a0) @@ -20992,6 +27082,30 @@ define i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64IA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end ; RV64IA-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_monotonic: +; RV32IA-WMO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: .LBB150_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: lr.w a2, (a0) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sc.w a3, a3, (a0) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB150_1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_monotonic: +; RV32IA-TSO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: .LBB150_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a2, (a0) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a3, a3, (a0) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB150_1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_monotonic: ; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB150_1: # =>This Inner Loop Header: Depth=1 @@ -21016,6 +27130,34 @@ define i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind { ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2 ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_monotonic: +; RV32IA-WMO-ZABHA-ZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: lw a0, 0(a0) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: .LBB150_1: # %atomicrmw.start +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: amocas.w a0, a4, (a2) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB150_1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-WMO-ZABHA-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_monotonic: +; RV32IA-TSO-ZABHA-ZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: lw a0, 0(a0) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: .LBB150_1: # %atomicrmw.start +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: amocas.w a0, a4, (a2) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB150_1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-TSO-ZABHA-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_monotonic: ; RV64IA-WMO-ZABHA-ZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 @@ -21172,6 +27314,30 @@ define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # %atomicrmw.end ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_acquire: +; RV32IA-WMO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: .LBB151_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aq a2, (a0) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sc.w a3, a3, (a0) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB151_1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_acquire: +; RV32IA-TSO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: .LBB151_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a2, (a0) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a3, a3, (a0) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB151_1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_acquire: ; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB151_1: # =>This Inner Loop Header: Depth=1 @@ -21196,6 +27362,34 @@ define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind { ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2 ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_acquire: +; RV32IA-WMO-ZABHA-ZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: lw a0, 0(a0) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: .LBB151_1: # %atomicrmw.start +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: amocas.w.aq a0, a4, (a2) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB151_1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-WMO-ZABHA-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_acquire: +; RV32IA-TSO-ZABHA-ZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: lw a0, 0(a0) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: .LBB151_1: # %atomicrmw.start +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: amocas.w a0, a4, (a2) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB151_1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-TSO-ZABHA-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_acquire: ; RV64IA-WMO-ZABHA-ZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 @@ -21352,6 +27546,30 @@ define i32 @atomicrmw_nand_i32_release(ptr %a, i32 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # %atomicrmw.end ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_release: +; RV32IA-WMO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: .LBB152_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: lr.w a2, (a0) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a3, a3, (a0) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB152_1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_release: +; RV32IA-TSO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: .LBB152_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a2, (a0) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a3, a3, (a0) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB152_1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_release: ; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB152_1: # =>This Inner Loop Header: Depth=1 @@ -21376,6 +27594,34 @@ define i32 @atomicrmw_nand_i32_release(ptr %a, i32 %b) nounwind { ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2 ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_release: +; RV32IA-WMO-ZABHA-ZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: lw a0, 0(a0) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: .LBB152_1: # %atomicrmw.start +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: amocas.w.rl a0, a4, (a2) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB152_1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-WMO-ZABHA-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_release: +; RV32IA-TSO-ZABHA-ZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: lw a0, 0(a0) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: .LBB152_1: # %atomicrmw.start +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: amocas.w a0, a4, (a2) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB152_1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-TSO-ZABHA-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_release: ; RV64IA-WMO-ZABHA-ZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 @@ -21532,6 +27778,30 @@ define i32 @atomicrmw_nand_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # %atomicrmw.end ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_acq_rel: +; RV32IA-WMO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: .LBB153_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aq a2, (a0) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a3, a3, (a0) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB153_1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_acq_rel: +; RV32IA-TSO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: .LBB153_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: lr.w a2, (a0) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sc.w a3, a3, (a0) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB153_1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_acq_rel: ; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB153_1: # =>This Inner Loop Header: Depth=1 @@ -21556,6 +27826,34 @@ define i32 @atomicrmw_nand_i32_acq_rel(ptr %a, i32 %b) nounwind { ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2 ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_acq_rel: +; RV32IA-WMO-ZABHA-ZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: lw a0, 0(a0) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: .LBB153_1: # %atomicrmw.start +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: amocas.w.aqrl a0, a4, (a2) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB153_1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-WMO-ZABHA-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_acq_rel: +; RV32IA-TSO-ZABHA-ZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: lw a0, 0(a0) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: .LBB153_1: # %atomicrmw.start +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: amocas.w a0, a4, (a2) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB153_1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-TSO-ZABHA-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_acq_rel: ; RV64IA-WMO-ZABHA-ZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 @@ -21692,6 +27990,30 @@ define i32 @atomicrmw_nand_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64IA-TSO-ZACAS-NEXT: # %bb.2: # %atomicrmw.end ; RV64IA-TSO-ZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_seq_cst: +; RV32IA-WMO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: .LBB154_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: lr.w.aqrl a2, (a0) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: and a3, a2, a1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: not a3, a3 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: sc.w.rl a3, a3, (a0) +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB154_1 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: mv a0, a2 +; RV32IA-WMO-ZABHA-NOZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_seq_cst: +; RV32IA-TSO-ZABHA-NOZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: .LBB154_1: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: lr.w.aqrl a2, (a0) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: and a3, a2, a1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: not a3, a3 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: sc.w.rl a3, a3, (a0) +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: bnez a3, .LBB154_1 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: # %bb.2: +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2 +; RV32IA-TSO-ZABHA-NOZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-NOZACAS-LABEL: atomicrmw_nand_i32_seq_cst: ; RV64IA-WMO-ZABHA-NOZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-NOZACAS-NEXT: .LBB154_1: # =>This Inner Loop Header: Depth=1 @@ -21716,6 +28038,36 @@ define i32 @atomicrmw_nand_i32_seq_cst(ptr %a, i32 %b) nounwind { ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: mv a0, a2 ; RV64IA-TSO-ZABHA-NOZACAS-NEXT: ret ; +; RV32IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_seq_cst: +; RV32IA-WMO-ZABHA-ZACAS: # %bb.0: +; RV32IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: lw a0, 0(a0) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: .LBB154_1: # %atomicrmw.start +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: mv a3, a0 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: and a4, a0, a1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: not a4, a4 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: fence rw, rw +; RV32IA-WMO-ZABHA-ZACAS-NEXT: amocas.w.aqrl a0, a4, (a2) +; RV32IA-WMO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB154_1 +; RV32IA-WMO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-WMO-ZABHA-ZACAS-NEXT: ret +; +; RV32IA-TSO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_seq_cst: +; RV32IA-TSO-ZABHA-ZACAS: # %bb.0: +; RV32IA-TSO-ZABHA-ZACAS-NEXT: mv a2, a0 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: lw a0, 0(a0) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: .LBB154_1: # %atomicrmw.start +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # =>This Inner Loop Header: Depth=1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: mv a3, a0 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: and a4, a0, a1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: not a4, a4 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: fence rw, rw +; RV32IA-TSO-ZABHA-ZACAS-NEXT: amocas.w a0, a4, (a2) +; RV32IA-TSO-ZABHA-ZACAS-NEXT: bne a0, a3, .LBB154_1 +; RV32IA-TSO-ZABHA-ZACAS-NEXT: # %bb.2: # %atomicrmw.end +; RV32IA-TSO-ZABHA-ZACAS-NEXT: ret +; ; RV64IA-WMO-ZABHA-ZACAS-LABEL: atomicrmw_nand_i32_seq_cst: ; RV64IA-WMO-ZABHA-ZACAS: # %bb.0: ; RV64IA-WMO-ZABHA-ZACAS-NEXT: mv a2, a0 diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index ead255b..f3529b1 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -443,7 +443,7 @@ ; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" ; RV32ZVFOFP8MIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p2_zvl32b1p0" ; RV32ZACAS: .attribute 5, "rv32i2p1_zaamo1p0_zacas1p0" -; RV32ZALASR: .attribute 5, "rv32i2p1_zalasr0p1" +; RV32ZALASR: .attribute 5, "rv32i2p1_zalasr0p9" ; RV32ZAMA16B: .attribute 5, "rv32i2p1_zama16b1p0" ; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp1p0_zicsr2p0" ; RV32ZABHA: .attribute 5, "rv32i2p1_zaamo1p0_zabha1p0" @@ -590,8 +590,8 @@ ; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" ; RV64ZVFOFP8MIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p2_zvl32b1p0" ; RV64ZACAS: .attribute 5, "rv64i2p1_zaamo1p0_zacas1p0" -; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr0p1" -; RV64ZALASRA: .attribute 5, "rv64i2p1_a2p1_zaamo1p0_zalasr0p1_zalrsc1p0" +; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr0p9" +; RV64ZALASRA: .attribute 5, "rv64i2p1_a2p1_zaamo1p0_zalasr0p9_zalrsc1p0" ; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp1p0_zicsr2p0" ; RV64ZABHA: .attribute 5, "rv64i2p1_zaamo1p0_zabha1p0" ; RV64ZVBC32E: .attribute 5, "rv64i2p1_zicsr2p0_zvbc32e0p7_zve32x1p0_zvl32b1p0" diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir index 021cb4c..8abe5c5 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir @@ -8,7 +8,7 @@ --- | %struct.DCT_InstanceTypeDef = type { ptr, i32, i32 } - + ; Function Attrs: nofree nounwind define hidden arm_aapcs_vfpcc void @test(ptr nocapture readonly %S, ptr %pIn, ptr nocapture %pOut) { entry: @@ -41,7 +41,7 @@ %13 = call i32 @llvm.loop.decrement.reg.i32(i32 %8, i32 1) %14 = icmp ne i32 %13, 0 br i1 %14, label %do.body, label %do.end - + do.end: ; preds = %do.body %15 = extractelement <4 x float> %11, i32 0 %16 = extractelement <4 x float> %11, i32 1 @@ -56,7 +56,7 @@ %sub4 = add i32 %1, -4 %cmp5201 = icmp ugt i32 %sub4, 1 br i1 %cmp5201, label %for.body.lr.ph, label %for.cond54.preheader - + for.body.lr.ph: ; preds = %do.end %scevgep = getelementptr float, ptr %pIn, i32 4 %20 = add i32 %0, 4 @@ -161,7 +161,7 @@ %63 = call i32 @llvm.loop.decrement.reg.i32(i32 %53, i32 1) %64 = icmp ne i32 %63, 0 br i1 %64, label %do.body24, label %do.end33 - + do.end33: ; preds = %do.body24 %65 = bitcast ptr %lsr.iv27 to ptr %66 = bitcast ptr %lsr.iv20 to ptr @@ -254,7 +254,7 @@ %inc = add nuw i32 %k.1200, 1 %exitcond.not = icmp eq i32 %inc, %1 br i1 %exitcond.not, label %for.end72, label %for.body56 - + for.end72: ; preds = %do.end66, %for.cond54.preheader ret void } @@ -428,28 +428,28 @@ body: | renamable $lr = t2LoopDec killed renamable $lr, 1 t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr tB %bb.2, 14 /* CC::al */, $noreg - + bb.2.do.end: successors: %bb.3(0x40000000), %bb.7(0x40000000) liveins: $q0, $r2, $r3, $r4, $r5, $r11 - - renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg + + renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg, implicit $fpscr_rm renamable $r0, dead $cpsr = tSUBi3 renamable $r3, 4, 14 /* CC::al */, $noreg tSTRspi killed renamable $r3, $sp, 1, 14 /* CC::al */, $noreg :: (store (s32) into %stack.8) - renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, renamable $s2, 14 /* CC::al */, $noreg + renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, renamable $s2, 14 /* CC::al */, $noreg, implicit $fpscr_rm tSTRspi renamable $r0, $sp, 8, 14 /* CC::al */, $noreg :: (store (s32) into %stack.1) - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s3, 14 /* CC::al */, $noreg, implicit $q0 + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s3, 14 /* CC::al */, $noreg, implicit $q0, implicit $fpscr_rm renamable $s2 = VLDRS renamable $r11, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.2) tCMPi8 killed renamable $r0, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr renamable $r0 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VMULS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VMULS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg, implicit $fpscr_rm VSTRS killed renamable $s0, renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.pOut) t2Bcc %bb.7, 3 /* CC::lo */, killed $cpsr - + bb.3.for.body.lr.ph: successors: %bb.4(0x80000000) liveins: $r0, $r2, $r4, $r5, $r11 - + renamable $r6 = t2ADDri renamable $r5, 16, 14 /* CC::al */, $noreg, $noreg renamable $r1, dead $cpsr = tSUBi3 renamable $r4, 4, 14 /* CC::al */, $noreg tSTRspi killed renamable $r6, $sp, 4, 14 /* CC::al */, $noreg :: (store (s32) into %stack.5) @@ -523,26 +523,26 @@ body: | renamable $lr = t2LoopDec killed renamable $lr, 1 t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr tB %bb.6, 14 /* CC::al */, $noreg - + bb.6.do.end33: successors: %bb.4(0x7c000000), %bb.7(0x04000000) liveins: $q0, $q1, $q2, $q3, $r0, $r1, $r2, $r6, $r8, $r9, $r10, $r12 - - renamable $s16 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s12, renamable $s13, 14 /* CC::al */, $noreg - renamable $s18 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s8, renamable $s9, 14 /* CC::al */, $noreg - renamable $s16 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s16, renamable $s14, 14 /* CC::al */, $noreg - renamable $s18 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s18, renamable $s10, 14 /* CC::al */, $noreg - renamable $s12 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s16, killed renamable $s15, 14 /* CC::al */, $noreg, implicit $q3 - renamable $s8 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s18, killed renamable $s11, 14 /* CC::al */, $noreg, implicit $q2 - renamable $s10 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s4, renamable $s5, 14 /* CC::al */, $noreg - renamable $s14 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg + + renamable $s16 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s12, renamable $s13, 14 /* CC::al */, $noreg, implicit $fpscr_rm + renamable $s18 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s8, renamable $s9, 14 /* CC::al */, $noreg, implicit $fpscr_rm + renamable $s16 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s16, renamable $s14, 14 /* CC::al */, $noreg, implicit $fpscr_rm + renamable $s18 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s18, renamable $s10, 14 /* CC::al */, $noreg, implicit $fpscr_rm + renamable $s12 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s16, killed renamable $s15, 14 /* CC::al */, $noreg, implicit $q3, implicit $fpscr_rm + renamable $s8 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s18, killed renamable $s11, 14 /* CC::al */, $noreg, implicit $q2, implicit $fpscr_rm + renamable $s10 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s4, renamable $s5, 14 /* CC::al */, $noreg, implicit $fpscr_rm + renamable $s14 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg, implicit $fpscr_rm renamable $r7 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) - renamable $s10 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s10, renamable $s6, 14 /* CC::al */, $noreg - renamable $s14 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s14, renamable $s2, 14 /* CC::al */, $noreg + renamable $s10 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s10, renamable $s6, 14 /* CC::al */, $noreg, implicit $fpscr_rm + renamable $s14 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s14, renamable $s2, 14 /* CC::al */, $noreg, implicit $fpscr_rm renamable $r3 = t2ADDrs renamable $r2, renamable $r0, 18, 14 /* CC::al */, $noreg, $noreg renamable $r7 = t2ADDrs renamable $r2, killed renamable $r7, 18, 14 /* CC::al */, $noreg, $noreg - renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s10, killed renamable $s7, 14 /* CC::al */, $noreg, implicit $q1 - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s14, killed renamable $s3, 14 /* CC::al */, $noreg, implicit $q0 + renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s10, killed renamable $s7, 14 /* CC::al */, $noreg, implicit $q1, implicit $fpscr_rm + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s14, killed renamable $s3, 14 /* CC::al */, $noreg, implicit $q0, implicit $fpscr_rm VSTRS killed renamable $s12, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx37) VSTRS killed renamable $s8, killed renamable $r7, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx42) renamable $r3 = t2ADDrs renamable $r2, killed renamable $r8, 18, 14 /* CC::al */, $noreg, $noreg @@ -597,7 +597,7 @@ body: | bb.13: successors: %bb.10(0x80000000) liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r11, $r12 - + bb.10.do.body59 (align 4): successors: %bb.10(0x7c000000), %bb.11(0x04000000) liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r11, $r12 @@ -611,20 +611,20 @@ body: | renamable $lr = t2LoopDec killed renamable $lr, 1 t2LoopEnd renamable $lr, %bb.10, implicit-def dead $cpsr tB %bb.11, 14 /* CC::al */, $noreg - + bb.11.do.end66: successors: %bb.12(0x04000000), %bb.9(0x7c000000) liveins: $q0, $r0, $r2, $r3, $r4, $r5, $r11, $r12 - - renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg + + renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s0, renamable $s1, 14 /* CC::al */, $noreg, implicit $fpscr_rm renamable $r1 = t2ADDrs renamable $r2, renamable $r0, 18, 14 /* CC::al */, $noreg, $noreg - renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, renamable $s2, 14 /* CC::al */, $noreg + renamable $s4 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, renamable $s2, 14 /* CC::al */, $noreg, implicit $fpscr_rm renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 1, 14 /* CC::al */, $noreg - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s3, 14 /* CC::al */, $noreg, implicit $q0 + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s3, 14 /* CC::al */, $noreg, implicit $q0, implicit $fpscr_rm tCMPhir renamable $r0, renamable $r12, 14 /* CC::al */, $noreg, implicit-def $cpsr VSTRS killed renamable $s0, killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.arrayidx70) tBcc %bb.9, 1 /* CC::ne */, killed $cpsr - + bb.12.for.end72: $sp = frame-destroy tADDspi $sp, 10, 14 /* CC::al */, $noreg $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir index 31e88ea..85b826a 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir @@ -185,15 +185,15 @@ body: | successors: %bb.5(0x80000000) liveins: $q0, $r0, $r1, $r2, $r4 - renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14, $noreg + renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14, $noreg, implicit $fpscr_rm $lr = tMOVr $r4, 14, $noreg $r3 = tMOVr $r1, 14, $noreg - renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14, $noreg - renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14, $noreg, implicit $q0 + renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14, $noreg, implicit $fpscr_rm + renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14, $noreg, implicit $q0, implicit $fpscr_rm $s2 = VMOVSR $r1, 14, $noreg renamable $s2 = VUITOS killed renamable $s2, 14, $noreg $lr = t2DoLoopStart killed $r4 - renamable $s4 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14, $noreg + renamable $s4 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14, $noreg, implicit $fpscr_rm renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 bb.5: @@ -215,13 +215,13 @@ body: | bb.6: liveins: $q0, $r1, $r2 - renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14, $noreg + renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14, $noreg, implicit $fpscr_rm renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14, $noreg - renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14, $noreg - renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14, $noreg, implicit $q0 + renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14, $noreg, implicit $fpscr_rm + renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14, $noreg, implicit $q0, implicit $fpscr_rm $s2 = VMOVSR killed $r0, 14, $noreg renamable $s2 = VUITOS killed renamable $s2, 14, $noreg - renamable $s0 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14, $noreg + renamable $s0 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14, $noreg, implicit $fpscr_rm VSTRS killed renamable $s0, killed renamable $r2, 0, 14, $noreg tPOP_RET 14, $noreg, def $r4, def $pc diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir index f5da7ac..780831c 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir @@ -232,9 +232,9 @@ body: | bb.3.middle.block: liveins: $q1 - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg - renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit $q1 - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg, implicit $fpscr_rm + renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit $q1, implicit $fpscr_rm + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg, implicit $fpscr_rm $sp = frame-destroy t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr tBX_RET 14 /* CC::al */, $noreg, implicit killed $s0 @@ -376,9 +376,9 @@ body: | bb.3.middle.block: liveins: $q1 - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg - renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit $q1 - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg, implicit $fpscr_rm + renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit $q1, implicit $fpscr_rm + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg, implicit $fpscr_rm $sp = frame-destroy t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr tBX_RET 14 /* CC::al */, $noreg, implicit killed $s0 diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir index c331612..5dcd0a1 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir @@ -240,10 +240,10 @@ body: | $s4 = VMOVSR $r1, 14 /* CC::al */, $noreg $lr = tMOVr $r4, 14 /* CC::al */, $noreg - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, renamable $s3, 14 /* CC::al */, $noreg, implicit $q0 + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, renamable $s3, 14 /* CC::al */, $noreg, implicit $q0, implicit $fpscr_rm $lr = t2DoLoopStart killed $r4 renamable $s4 = VUITOS killed renamable $s4, 14 /* CC::al */, $noreg - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s4, 14 /* CC::al */, $noreg + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s4, 14 /* CC::al */, $noreg, implicit $fpscr_rm renamable $r3 = VMOVRS killed renamable $s0, 14 /* CC::al */, $noreg renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0 renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q1 @@ -267,10 +267,10 @@ body: | liveins: $q0, $r1, $r2 renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, renamable $s3, 14 /* CC::al */, $noreg, implicit $q0 + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, renamable $s3, 14 /* CC::al */, $noreg, implicit $q0, implicit $fpscr_rm $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg - renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg, implicit $fpscr_rm VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.pResult) frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc diff --git a/llvm/test/CodeGen/Thumb2/pipeliner-inlineasm.mir b/llvm/test/CodeGen/Thumb2/pipeliner-inlineasm.mir index 5221205..d9d2f25 100644 --- a/llvm/test/CodeGen/Thumb2/pipeliner-inlineasm.mir +++ b/llvm/test/CodeGen/Thumb2/pipeliner-inlineasm.mir @@ -96,7 +96,7 @@ body: | ; CHECK-NEXT: bb.6.for.body: ; CHECK-NEXT: successors: %bb.7(0x80000000), %bb.8(0x00000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], %30, 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], %30, 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[t2ADDri2:%[0-9]+]]:rgpr = t2ADDri [[COPY7]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[VLDRS4:%[0-9]+]]:spr = VLDRS [[COPY7]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4) ; CHECK-NEXT: [[t2ADDri3:%[0-9]+]]:rgpr = t2ADDri [[COPY6]], 4, 14 /* CC::al */, $noreg, $noreg @@ -119,13 +119,13 @@ body: | ; CHECK-NEXT: [[PHI4:%[0-9]+]]:spr = PHI [[VLDRS5]], %bb.6, %47, %bb.7 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:spr = PHI %40, %bb.6, %55, %bb.7 ; CHECK-NEXT: [[PHI6:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, %45, %bb.7 - ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[PHI4]], [[PHI5]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[PHI4]], [[PHI5]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[t2SUBri4:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 1, 14 /* CC::al */, $noreg, def $cpsr ; CHECK-NEXT: [[VLDRS6:%[0-9]+]]:spr = VLDRS [[PHI1]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4) ; CHECK-NEXT: [[VLDRS7:%[0-9]+]]:spr = VLDRS [[PHI]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4) ; CHECK-NEXT: [[t2ADDri4:%[0-9]+]]:rgpr = t2ADDri [[PHI]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[t2ADDri5:%[0-9]+]]:rgpr = t2ADDri [[PHI1]], 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI6]], [[PHI3]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI6]], [[PHI3]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[COPY11:%[0-9]+]]:gpr = COPY [[t2ADDri4]] ; CHECK-NEXT: [[COPY12:%[0-9]+]]:gpr = COPY [[t2ADDri5]] ; CHECK-NEXT: [[COPY13:%[0-9]+]]:gpr = COPY [[t2SUBri4]] @@ -140,7 +140,7 @@ body: | ; CHECK-NEXT: [[PHI8:%[0-9]+]]:spr = PHI [[VLDRS5]], %bb.6, [[VLDRS6]], %bb.7 ; CHECK-NEXT: [[PHI9:%[0-9]+]]:spr = PHI %40, %bb.6, %55, %bb.7 ; CHECK-NEXT: [[PHI10:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, [[VMULS1]], %bb.7 - ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI10]], [[PHI7]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI10]], [[PHI7]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.9: ; CHECK-NEXT: successors: %bb.4(0x80000000) @@ -148,8 +148,8 @@ body: | ; CHECK-NEXT: [[PHI11:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.5, [[VADDS1]], %bb.8 ; CHECK-NEXT: [[PHI12:%[0-9]+]]:spr = PHI [[VLDRS3]], %bb.5, [[PHI8]], %bb.8 ; CHECK-NEXT: [[PHI13:%[0-9]+]]:spr = PHI %30, %bb.5, [[PHI9]], %bb.8 - ; CHECK-NEXT: [[VMULS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[PHI12]], [[PHI13]], 14 /* CC::al */, $noreg - ; CHECK-NEXT: [[VADDS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[VMULS2]], [[PHI11]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[PHI12]], [[PHI13]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: [[VADDS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[VMULS2]], [[PHI11]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4.for.end: @@ -194,8 +194,8 @@ body: | %20:rgpr = t2ADDri %3, 4, 14 /* CC::al */, $noreg, $noreg %21:spr = VLDRS %3, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) INLINEASM &nop, 0 /* attdialect */, 196618 /* regdef:SPR */, def %25, 2147483657 /* reguse tiedto:$0 */, %19(tied-def 3) - %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %25, 14 /* CC::al */, $noreg - %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg + %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %25, 14 /* CC::al */, $noreg, implicit $fpscr_rm + %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg, implicit $fpscr_rm %23:rgpr = t2SUBri %4, 1, 14 /* CC::al */, $noreg, def $cpsr %7:gpr = COPY %23 %8:gpr = COPY %20 diff --git a/llvm/test/CodeGen/Thumb2/scavenge-lr.mir b/llvm/test/CodeGen/Thumb2/scavenge-lr.mir index 5513bed..bfe55a5 100644 --- a/llvm/test/CodeGen/Thumb2/scavenge-lr.mir +++ b/llvm/test/CodeGen/Thumb2/scavenge-lr.mir @@ -147,10 +147,10 @@ body: | $q5 = VLD1q64 $r3, 16, 14 /* CC::al */, $noreg :: (load (s128) from %ir.zzz..sroa_cast241, align 32) $q1 = VMLAfq killed $q1, $q5, killed $q8, 14 /* CC::al */, $noreg $s8 = VLDRS %const.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) - $s3 = VDIVS $s8, $s7, 14 /* CC::al */, $noreg, implicit-def $q0 - $s2 = VDIVS $s8, $s6, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 - $s1 = VDIVS $s8, $s5, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 - $s0 = VDIVS $s8, $s4, 14 /* CC::al */, $noreg, implicit killed $q1, implicit killed $q0, implicit-def $q0 + $s3 = VDIVS $s8, $s7, 14 /* CC::al */, $noreg, implicit-def $q0, implicit $fpscr_rm + $s2 = VDIVS $s8, $s6, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0, implicit $fpscr_rm + $s1 = VDIVS $s8, $s5, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0, implicit $fpscr_rm + $s0 = VDIVS $s8, $s4, 14 /* CC::al */, $noreg, implicit killed $q1, implicit killed $q0, implicit-def $q0, implicit $fpscr_rm $r7 = t2SUBri $r0, 64, 14 /* CC::al */, $noreg, $noreg $q8 = VLD1q64 $r7, 16, 14 /* CC::al */, $noreg :: (load (s128) from %ir.yyy..sroa_cast244, align 32) VSTMQIA $q8, %stack.1, 14 /* CC::al */, $noreg :: (store (s128) into %stack.1) @@ -185,10 +185,10 @@ body: | $r3 = VST1q32wb_fixed killed $r3, 16, killed $q10, 14 /* CC::al */, $noreg :: (store (s128) into %ir.zzz..sroa_cast241, align 32) $q10 = VLD1q64 $r3, 16, 14 /* CC::al */, $noreg :: (load (s128) from %ir.zzz..sroa_cast241 + 16, basealign 32) $q1 = VMLAfq killed $q1, $q10, killed $q8, 14 /* CC::al */, $noreg - $s23 = VDIVS $s8, $s7, 14 /* CC::al */, $noreg, implicit-def $q5 - $s22 = VDIVS $s8, $s6, 14 /* CC::al */, $noreg, implicit killed $q5, implicit-def $q5 - $s21 = VDIVS $s8, $s5, 14 /* CC::al */, $noreg, implicit killed $q5, implicit-def $q5 - $s20 = VDIVS killed $s8, $s4, 14 /* CC::al */, $noreg, implicit killed $q1, implicit killed $q5, implicit-def $q5 + $s23 = VDIVS $s8, $s7, 14 /* CC::al */, $noreg, implicit-def $q5, implicit $fpscr_rm + $s22 = VDIVS $s8, $s6, 14 /* CC::al */, $noreg, implicit killed $q5, implicit-def $q5, implicit $fpscr_rm + $s21 = VDIVS $s8, $s5, 14 /* CC::al */, $noreg, implicit killed $q5, implicit-def $q5, implicit $fpscr_rm + $s20 = VDIVS killed $s8, $s4, 14 /* CC::al */, $noreg, implicit killed $q1, implicit killed $q5, implicit-def $q5, implicit $fpscr_rm VST1q64 killed $r5, 16, $q5, 14 /* CC::al */, $noreg :: (store (s128) into %ir.xxx..sroa_cast248 + 16, basealign 32) VST1q64 killed $r6, 16, $q5, 14 /* CC::al */, $noreg :: (store (s128) into %ir.vvv..sroa_cast230 + 16, basealign 32) $q8 = VLDMQIA %stack.0, 14 /* CC::al */, $noreg :: (load (s128) from %stack.0) diff --git a/llvm/test/CodeGen/Thumb2/swp-exitbranchdir.mir b/llvm/test/CodeGen/Thumb2/swp-exitbranchdir.mir index ba10045..20f044a 100644 --- a/llvm/test/CodeGen/Thumb2/swp-exitbranchdir.mir +++ b/llvm/test/CodeGen/Thumb2/swp-exitbranchdir.mir @@ -83,7 +83,7 @@ body: | ; CHECK-NEXT: [[VLDRS2:%[0-9]+]]:spr = VLDRS [[COPY4]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) ; CHECK-NEXT: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri [[COPY3]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[VLDRS3:%[0-9]+]]:spr = VLDRS [[COPY3]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[t2SUBri2:%[0-9]+]]:rgpr = t2SUBri [[COPY]], 1, 14 /* CC::al */, $noreg, def $cpsr ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprnopc = COPY [[t2SUBri2]] ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gprnopc = COPY [[t2ADDri1]] @@ -98,7 +98,7 @@ body: | ; CHECK-NEXT: [[VLDRS4:%[0-9]+]]:spr = VLDRS [[COPY7]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4) ; CHECK-NEXT: [[t2ADDri3:%[0-9]+]]:rgpr = t2ADDri [[COPY6]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[VLDRS5:%[0-9]+]]:spr = VLDRS [[COPY6]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4) - ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS5]], [[VLDRS4]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS5]], [[VLDRS4]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[t2SUBri3:%[0-9]+]]:rgpr = t2SUBri [[COPY5]], 1, 14 /* CC::al */, $noreg, def $cpsr ; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY [[t2SUBri3]] ; CHECK-NEXT: [[COPY9:%[0-9]+]]:gpr = COPY [[t2ADDri3]] @@ -115,7 +115,7 @@ body: | ; CHECK-NEXT: [[PHI3:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, %43, %bb.7 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:spr = PHI [[VMULS1]], %bb.6, %52, %bb.7 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, [[PHI4]], %bb.7 - ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI5]], [[PHI3]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI5]], [[PHI3]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[t2SUBri4:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 1, 14 /* CC::al */, $noreg, def $cpsr ; CHECK-NEXT: [[VLDRS6:%[0-9]+]]:spr = VLDRS [[PHI1]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4) ; CHECK-NEXT: [[VLDRS7:%[0-9]+]]:spr = VLDRS [[PHI]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4) @@ -124,7 +124,7 @@ body: | ; CHECK-NEXT: [[COPY11:%[0-9]+]]:gpr = COPY [[t2ADDri4]] ; CHECK-NEXT: [[COPY12:%[0-9]+]]:gpr = COPY [[t2ADDri5]] ; CHECK-NEXT: [[COPY13:%[0-9]+]]:gpr = COPY [[t2SUBri4]] - ; CHECK-NEXT: [[VMULS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS6]], [[VLDRS7]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS6]], [[VLDRS7]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: t2Bcc %bb.8, 0 /* CC::eq */, $cpsr ; CHECK-NEXT: t2B %bb.7, 14 /* CC::al */, $noreg ; CHECK-NEXT: {{ $}} @@ -134,14 +134,14 @@ body: | ; CHECK-NEXT: [[PHI6:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, [[VADDS]], %bb.7 ; CHECK-NEXT: [[PHI7:%[0-9]+]]:spr = PHI [[VMULS1]], %bb.6, [[VMULS2]], %bb.7 ; CHECK-NEXT: [[PHI8:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, [[PHI4]], %bb.7 - ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI8]], [[PHI6]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI8]], [[PHI6]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.9: ; CHECK-NEXT: successors: %bb.4(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[PHI9:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.5, [[VADDS1]], %bb.8 ; CHECK-NEXT: [[PHI10:%[0-9]+]]:spr = PHI [[VMULS]], %bb.5, [[PHI7]], %bb.8 - ; CHECK-NEXT: [[VADDS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI10]], [[PHI9]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VADDS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI10]], [[PHI9]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4.for.end: @@ -185,8 +185,8 @@ body: | %19:spr = VLDRS %2, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) %20:rgpr = t2ADDri %3, 4, 14 /* CC::al */, $noreg, $noreg %21:spr = VLDRS %3, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg - %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg + %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg, implicit $fpscr_rm + %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg, implicit $fpscr_rm %23:rgpr = t2SUBri %4, 1, 14 /* CC::al */, $noreg, def $cpsr %7:gpr = COPY %23 %8:gpr = COPY %20 diff --git a/llvm/test/CodeGen/Thumb2/swp-fixedii-le.mir b/llvm/test/CodeGen/Thumb2/swp-fixedii-le.mir index 854c5b8..177c94e 100644 --- a/llvm/test/CodeGen/Thumb2/swp-fixedii-le.mir +++ b/llvm/test/CodeGen/Thumb2/swp-fixedii-le.mir @@ -84,7 +84,7 @@ body: | ; CHECK-NEXT: [[VLDRS2:%[0-9]+]]:spr = VLDRS [[COPY4]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) ; CHECK-NEXT: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri [[COPY3]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[VLDRS3:%[0-9]+]]:spr = VLDRS [[COPY3]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprlr = COPY [[t2DoLoopStart]] ; CHECK-NEXT: [[t2LoopDec:%[0-9]+]]:gprlr = t2LoopDec [[COPY5]], 1 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY [[t2LoopDec]] @@ -110,8 +110,8 @@ body: | ; CHECK-NEXT: [[t2ADDri3:%[0-9]+]]:rgpr = t2ADDri [[PHI1]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[COPY10:%[0-9]+]]:gpr = COPY [[t2ADDri2]] ; CHECK-NEXT: [[COPY11:%[0-9]+]]:gpr = COPY [[t2ADDri3]] - ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS4]], [[VLDRS5]], 14 /* CC::al */, $noreg - ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI4]], [[PHI3]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS4]], [[VLDRS5]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI4]], [[PHI3]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[COPY12:%[0-9]+]]:gpr = COPY [[t2LoopDec1]] ; CHECK-NEXT: t2LoopEnd [[t2LoopDec1]], %bb.6, implicit-def $cpsr ; CHECK-NEXT: t2B %bb.7, 14 /* CC::al */, $noreg @@ -121,7 +121,7 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[PHI5:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.5, [[VADDS]], %bb.6 ; CHECK-NEXT: [[PHI6:%[0-9]+]]:spr = PHI [[VMULS]], %bb.5, [[VMULS1]], %bb.6 - ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI6]], [[PHI5]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI6]], [[PHI5]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4.for.end: @@ -166,8 +166,8 @@ body: | %19:spr = VLDRS %2, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) %20:rgpr = t2ADDri %3, 4, 14 /* CC::al */, $noreg, $noreg %21:spr = VLDRS %3, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg - %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg + %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg, implicit $fpscr_rm + %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg, implicit $fpscr_rm %42:gprlr = COPY %4 %23:gprlr = t2LoopDec %42:gprlr, 1 %7:gpr = COPY %23 diff --git a/llvm/test/CodeGen/Thumb2/swp-fixedii.mir b/llvm/test/CodeGen/Thumb2/swp-fixedii.mir index dd02703..7939717 100644 --- a/llvm/test/CodeGen/Thumb2/swp-fixedii.mir +++ b/llvm/test/CodeGen/Thumb2/swp-fixedii.mir @@ -83,7 +83,7 @@ body: | ; CHECK-NEXT: [[VLDRS2:%[0-9]+]]:spr = VLDRS [[COPY4]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) ; CHECK-NEXT: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri [[COPY3]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[VLDRS3:%[0-9]+]]:spr = VLDRS [[COPY3]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[t2SUBri2:%[0-9]+]]:rgpr = t2SUBri [[COPY]], 1, 14 /* CC::al */, $noreg, def $cpsr ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprnopc = COPY [[t2SUBri2]] ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gprnopc = COPY [[t2ADDri1]] @@ -98,7 +98,7 @@ body: | ; CHECK-NEXT: [[VLDRS4:%[0-9]+]]:spr = VLDRS [[COPY7]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4) ; CHECK-NEXT: [[t2ADDri3:%[0-9]+]]:rgpr = t2ADDri [[COPY6]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[VLDRS5:%[0-9]+]]:spr = VLDRS [[COPY6]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4) - ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS5]], [[VLDRS4]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS5]], [[VLDRS4]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[t2SUBri3:%[0-9]+]]:rgpr = t2SUBri [[COPY5]], 1, 14 /* CC::al */, $noreg, def $cpsr ; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY [[t2SUBri3]] ; CHECK-NEXT: [[COPY9:%[0-9]+]]:gpr = COPY [[t2ADDri3]] @@ -115,7 +115,7 @@ body: | ; CHECK-NEXT: [[PHI3:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, %43, %bb.7 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:spr = PHI [[VMULS1]], %bb.6, %52, %bb.7 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, [[PHI4]], %bb.7 - ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI5]], [[PHI3]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI5]], [[PHI3]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[t2SUBri4:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 1, 14 /* CC::al */, $noreg, def $cpsr ; CHECK-NEXT: [[VLDRS6:%[0-9]+]]:spr = VLDRS [[PHI1]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4) ; CHECK-NEXT: [[VLDRS7:%[0-9]+]]:spr = VLDRS [[PHI]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4) @@ -124,7 +124,7 @@ body: | ; CHECK-NEXT: [[COPY11:%[0-9]+]]:gpr = COPY [[t2ADDri4]] ; CHECK-NEXT: [[COPY12:%[0-9]+]]:gpr = COPY [[t2ADDri5]] ; CHECK-NEXT: [[COPY13:%[0-9]+]]:gpr = COPY [[t2SUBri4]] - ; CHECK-NEXT: [[VMULS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS6]], [[VLDRS7]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS6]], [[VLDRS7]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: t2Bcc %bb.7, 1 /* CC::ne */, $cpsr ; CHECK-NEXT: t2B %bb.8, 14 /* CC::al */, $noreg ; CHECK-NEXT: {{ $}} @@ -134,14 +134,14 @@ body: | ; CHECK-NEXT: [[PHI6:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, [[VADDS]], %bb.7 ; CHECK-NEXT: [[PHI7:%[0-9]+]]:spr = PHI [[VMULS1]], %bb.6, [[VMULS2]], %bb.7 ; CHECK-NEXT: [[PHI8:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, [[PHI4]], %bb.7 - ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI8]], [[PHI6]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI8]], [[PHI6]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.9: ; CHECK-NEXT: successors: %bb.4(0x80000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[PHI9:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.5, [[VADDS1]], %bb.8 ; CHECK-NEXT: [[PHI10:%[0-9]+]]:spr = PHI [[VMULS]], %bb.5, [[PHI7]], %bb.8 - ; CHECK-NEXT: [[VADDS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI10]], [[PHI9]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VADDS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI10]], [[PHI9]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4.for.end: @@ -185,8 +185,8 @@ body: | %19:spr = VLDRS %2, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) %20:rgpr = t2ADDri %3, 4, 14 /* CC::al */, $noreg, $noreg %21:spr = VLDRS %3, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg - %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg + %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg, implicit $fpscr_rm + %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg, implicit $fpscr_rm %23:rgpr = t2SUBri %4, 1, 14 /* CC::al */, $noreg, def $cpsr %7:gpr = COPY %23 %8:gpr = COPY %20 diff --git a/llvm/test/CodeGen/Thumb2/swp-regpressure.mir b/llvm/test/CodeGen/Thumb2/swp-regpressure.mir index 2bcb0c9..955b53df 100644 --- a/llvm/test/CodeGen/Thumb2/swp-regpressure.mir +++ b/llvm/test/CodeGen/Thumb2/swp-regpressure.mir @@ -148,8 +148,8 @@ body: | ; CHECK-NEXT: [[VLDRS2:%[0-9]+]]:spr = VLDRS [[PHI]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) ; CHECK-NEXT: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri [[PHI1]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[VLDRS3:%[0-9]+]]:spr = VLDRS [[PHI1]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg - ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[VMULS]], [[PHI3]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[VMULS]], [[PHI3]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[t2SUBri2:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 1, 14 /* CC::al */, $noreg, def $cpsr ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY [[t2SUBri2]] ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY [[t2ADDri1]] @@ -236,8 +236,8 @@ body: | %19:spr = VLDRS %2, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) %20:rgpr = t2ADDri %3, 4, 14 /* CC::al */, $noreg, $noreg %21:spr = VLDRS %3, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg - %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg + %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg, implicit $fpscr_rm + %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg, implicit $fpscr_rm %23:rgpr = t2SUBri %4, 1, 14 /* CC::al */, $noreg, def $cpsr %7:gpr = COPY %23 %8:gpr = COPY %20 @@ -314,24 +314,24 @@ body: | ; CHECK-NEXT: [[t2SUBri2:%[0-9]+]]:rgpr = t2SUBri [[COPY]], 1, 14 /* CC::al */, $noreg, def $cpsr ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprnopc = COPY [[t2SUBri2]] ; CHECK-NEXT: [[COPY6:%[0-9]+]]:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %66:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %67:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %68:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %69:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %70:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %71:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %72:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %73:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %74:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %75:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %76:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %77:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %78:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %79:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %80:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %81:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %82:rgpr = COPY [[COPY4]] - ; CHECK-NEXT: dead %83:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY7:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY8:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY9:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY10:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY11:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY12:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY13:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY14:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY15:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY16:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY17:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY18:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY19:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY20:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY21:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY22:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY23:%[0-9]+]]:rgpr = COPY [[COPY4]] + ; CHECK-NEXT: dead [[COPY24:%[0-9]+]]:rgpr = COPY [[COPY4]] ; CHECK-NEXT: t2Bcc %bb.9, 0 /* CC::eq */, $cpsr ; CHECK-NEXT: t2B %bb.6, 14 /* CC::al */, $noreg ; CHECK-NEXT: {{ $}} @@ -342,82 +342,82 @@ body: | ; CHECK-NEXT: [[VLDRS2:%[0-9]+]]:spr = VLDRS [[COPY4]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) ; CHECK-NEXT: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri [[COPY3]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[VLDRS3:%[0-9]+]]:spr = VLDRS [[COPY3]], 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg - ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr = COPY [[t2ADDri1]] - ; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY [[t2ADDri]] + ; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS3]], [[VLDRS2]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: [[COPY25:%[0-9]+]]:gpr = COPY [[t2ADDri1]] + ; CHECK-NEXT: [[COPY26:%[0-9]+]]:gpr = COPY [[t2ADDri]] ; CHECK-NEXT: [[t2SUBri3:%[0-9]+]]:rgpr = t2SUBri [[COPY5]], 1, 14 /* CC::al */, $noreg, def $cpsr - ; CHECK-NEXT: [[COPY9:%[0-9]+]]:gpr = COPY [[t2SUBri3]] - ; CHECK-NEXT: [[COPY10:%[0-9]+]]:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %94:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %95:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %96:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %97:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %98:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %99:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %100:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %101:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %102:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %103:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %104:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %105:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %106:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %107:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %108:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %109:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %110:rgpr = COPY [[COPY6]] - ; CHECK-NEXT: dead %111:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: [[COPY27:%[0-9]+]]:gpr = COPY [[t2SUBri3]] + ; CHECK-NEXT: [[COPY28:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY29:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY30:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY31:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY32:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY33:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY34:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY35:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY36:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY37:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY38:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY39:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY40:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY41:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY42:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY43:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY44:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY45:%[0-9]+]]:rgpr = COPY [[COPY6]] + ; CHECK-NEXT: dead [[COPY46:%[0-9]+]]:rgpr = COPY [[COPY6]] ; CHECK-NEXT: t2Bcc %bb.8, 0 /* CC::eq */, $cpsr ; CHECK-NEXT: t2B %bb.7, 14 /* CC::al */, $noreg ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.7.for.body: ; CHECK-NEXT: successors: %bb.8(0x04000000), %bb.7(0x7c000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[PHI:%[0-9]+]]:gprnopc = PHI [[COPY8]], %bb.6, %116, %bb.7 - ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gprnopc = PHI [[COPY7]], %bb.6, %117, %bb.7 - ; CHECK-NEXT: [[PHI2:%[0-9]+]]:gprnopc = PHI [[COPY9]], %bb.6, %140, %bb.7 + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gprnopc = PHI [[COPY26]], %bb.6, %116, %bb.7 + ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gprnopc = PHI [[COPY25]], %bb.6, %117, %bb.7 + ; CHECK-NEXT: [[PHI2:%[0-9]+]]:gprnopc = PHI [[COPY27]], %bb.6, %140, %bb.7 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, %137, %bb.7 - ; CHECK-NEXT: [[PHI4:%[0-9]+]]:gprnopc = PHI [[COPY10]], %bb.6, %139, %bb.7 + ; CHECK-NEXT: [[PHI4:%[0-9]+]]:gprnopc = PHI [[COPY28]], %bb.6, %139, %bb.7 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, %118, %bb.7 ; CHECK-NEXT: [[VLDRS4:%[0-9]+]]:spr = VLDRS [[PHI1]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4) ; CHECK-NEXT: [[VLDRS5:%[0-9]+]]:spr = VLDRS [[PHI]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4) ; CHECK-NEXT: [[t2ADDri2:%[0-9]+]]:rgpr = t2ADDri [[PHI]], 4, 14 /* CC::al */, $noreg, $noreg ; CHECK-NEXT: [[t2ADDri3:%[0-9]+]]:rgpr = t2ADDri [[PHI1]], 4, 14 /* CC::al */, $noreg, $noreg - ; CHECK-NEXT: [[COPY11:%[0-9]+]]:gpr = COPY [[t2ADDri2]] - ; CHECK-NEXT: [[COPY12:%[0-9]+]]:gpr = COPY [[t2ADDri3]] - ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS4]], [[VLDRS5]], 14 /* CC::al */, $noreg - ; CHECK-NEXT: dead %119:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %120:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %121:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %122:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %123:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %124:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %125:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %126:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %127:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %128:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %129:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %130:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %131:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %132:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %133:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %134:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %135:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: dead %136:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI5]], [[PHI3]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[COPY47:%[0-9]+]]:gpr = COPY [[t2ADDri2]] + ; CHECK-NEXT: [[COPY48:%[0-9]+]]:gpr = COPY [[t2ADDri3]] + ; CHECK-NEXT: [[VMULS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS4]], [[VLDRS5]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: dead [[COPY49:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY50:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY51:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY52:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY53:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY54:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY55:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY56:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY57:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY58:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY59:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY60:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY61:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY62:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY63:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY64:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY65:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: dead [[COPY66:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI5]], [[PHI3]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: [[t2SUBri4:%[0-9]+]]:rgpr = t2SUBri [[PHI2]], 1, 14 /* CC::al */, $noreg, def $cpsr - ; CHECK-NEXT: [[COPY13:%[0-9]+]]:rgpr = COPY [[PHI4]] - ; CHECK-NEXT: [[COPY14:%[0-9]+]]:gpr = COPY [[t2SUBri4]] + ; CHECK-NEXT: [[COPY67:%[0-9]+]]:rgpr = COPY [[PHI4]] + ; CHECK-NEXT: [[COPY68:%[0-9]+]]:gpr = COPY [[t2SUBri4]] ; CHECK-NEXT: t2Bcc %bb.7, 1 /* CC::ne */, $cpsr ; CHECK-NEXT: t2B %bb.8, 14 /* CC::al */, $noreg ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.8: ; CHECK-NEXT: successors: %bb.9(0x80000000) ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[PHI6:%[0-9]+]]:gprnopc = PHI [[COPY8]], %bb.6, [[COPY11]], %bb.7 - ; CHECK-NEXT: [[PHI7:%[0-9]+]]:gprnopc = PHI [[COPY7]], %bb.6, [[COPY12]], %bb.7 + ; CHECK-NEXT: [[PHI6:%[0-9]+]]:gprnopc = PHI [[COPY26]], %bb.6, [[COPY47]], %bb.7 + ; CHECK-NEXT: [[PHI7:%[0-9]+]]:gprnopc = PHI [[COPY25]], %bb.6, [[COPY48]], %bb.7 ; CHECK-NEXT: [[PHI8:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.6, [[VADDS]], %bb.7 ; CHECK-NEXT: [[PHI9:%[0-9]+]]:spr = PHI [[VMULS]], %bb.6, [[VMULS1]], %bb.7 - ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI9]], [[PHI8]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VADDS1:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[PHI9]], [[PHI8]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.9: ; CHECK-NEXT: successors: %bb.4(0x80000000) @@ -427,8 +427,8 @@ body: | ; CHECK-NEXT: [[PHI12:%[0-9]+]]:spr = PHI [[VLDRS1]], %bb.5, [[VADDS1]], %bb.8 ; CHECK-NEXT: [[VLDRS6:%[0-9]+]]:spr = VLDRS [[PHI10]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep7, align 4) ; CHECK-NEXT: [[VLDRS7:%[0-9]+]]:spr = VLDRS [[PHI11]], 1, 14 /* CC::al */, $noreg :: (load unknown-size from %ir.scevgep3, align 4) - ; CHECK-NEXT: [[VMULS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS7]], [[VLDRS6]], 14 /* CC::al */, $noreg - ; CHECK-NEXT: [[VADDS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[VMULS2]], [[PHI12]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[VMULS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VMULS [[VLDRS7]], [[VLDRS6]], 14 /* CC::al */, $noreg, implicit $fpscr_rm + ; CHECK-NEXT: [[VADDS2:%[0-9]+]]:spr = nnan ninf nsz arcp contract afn reassoc VADDS [[VMULS2]], [[PHI12]], 14 /* CC::al */, $noreg, implicit $fpscr_rm ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4.for.end: @@ -491,8 +491,8 @@ body: | %19:spr = VLDRS %2, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep7) %20:rgpr = t2ADDri %3, 4, 14 /* CC::al */, $noreg, $noreg %21:spr = VLDRS %3, 1, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep3) - %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg - %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg + %22:spr = nnan ninf nsz arcp contract afn reassoc VMULS killed %21, killed %19, 14 /* CC::al */, $noreg, implicit $fpscr_rm + %6:spr = nnan ninf nsz arcp contract afn reassoc VADDS killed %22, %5, 14 /* CC::al */, $noreg, implicit $fpscr_rm %23:rgpr = t2SUBri %4, 1, 14 /* CC::al */, $noreg, def $cpsr %7:gpr = COPY %23 %8:gpr = COPY %20 diff --git a/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll b/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll index 172ff53..e562c4a 100644 --- a/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll +++ b/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll @@ -132,4 +132,17 @@ define i32 @all_true_2_4_i32(<4 x i32> %v) { ret i32 %conv3 } +; Regression test for the intrinsic pattern matcher with nullary intrinsics +define i64 @other_intrinsic() #0 { +; CHECK-LABEL: other_intrinsic: +; CHECK: .functype other_intrinsic () -> (i64) +; CHECK-NEXT: # %bb.0: # %entry +; CHECK-NEXT: global.get $push0=, __tls_align +; CHECK-NEXT: return $pop0 +entry: + %0 = call i64 @llvm.wasm.tls.align.i64() + ret i64 %0 +} + +attributes #0 = { "target-features"="+atomics" } diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index b8cd6de..111616d 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -420,8 +420,8 @@ .attribute arch, "rv32ia_zacas1p0" # CHECK: attribute 5, "rv32i2p1_a2p1_zaamo1p0_zacas1p0_zalrsc1p0" -.attribute arch, "rv32izalasr0p1" -# CHECK: attribute 5, "rv32i2p1_zalasr0p1" +.attribute arch, "rv32izalasr0p9" +# CHECK: attribute 5, "rv32i2p1_zalasr0p9" .attribute arch, "rv32i_xcvalu" # CHECK: attribute 5, "rv32i2p1_xcvalu1p0" diff --git a/llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-analysis.ll b/llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-analysis.ll index e7b7dff..4173c32 100644 --- a/llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-analysis.ll +++ b/llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-analysis.ll @@ -1,11 +1,12 @@ ; REQUIRES: asserts ; RUN: opt -S -passes=dfa-jump-threading -debug-only=dfa-jump-threading -disable-output %s 2>&1 | FileCheck %s +; RUN: opt -S -passes=dfa-jump-threading -print-prof-data %s -o - | FileCheck %s --check-prefix=PROFILE ; This test checks that the analysis identifies all threadable paths in a ; simple CFG. A threadable path includes a list of basic blocks, the exit ; state, and the block that determines the next state. ; < path of BBs that form a cycle > [ state, determinator ] -define i32 @test1(i32 %num) { +define i32 @test1(i32 %num) !prof !0{ ; CHECK: < case2 for.inc for.body > [ 1, for.inc ] ; CHECK-NEXT: < for.inc for.body > [ 1, for.inc ] ; CHECK-NEXT: < case1 for.inc for.body > [ 2, for.inc ] @@ -25,8 +26,11 @@ case1: br label %for.inc case2: + ; PROFILE-LABEL: @test1 + ; PROFILE-LABEL: case2: + ; PROFILE: br i1 %cmp, label %for.inc.jt1, label %sel.si.unfold.false.jt2, !prof !1 ; !1 = !{!"branch_weights", i32 3, i32 5} %cmp = icmp eq i32 %count, 50 - %sel = select i1 %cmp, i32 1, i32 2 + %sel = select i1 %cmp, i32 1, i32 2, !prof !1 br label %for.inc for.inc: @@ -182,7 +186,7 @@ bb66: ; preds = %bb59 } ; Value %init is not predictable but it's okay since it is the value initial to the switch. -define i32 @initial.value.positive1(i32 %init) { +define i32 @initial.value.positive1(i32 %init) !prof !0 { ; CHECK: < loop.1.backedge loop.1 loop.2 loop.3 > [ 1, loop.1 ] ; CHECK-NEXT: < case4 loop.1.backedge state.1.be2.si.unfold.false loop.1 loop.2 loop.3 > [ 2, loop.1.backedge ] ; CHECK-NEXT: < case2 loop.1.backedge state.1.be2.si.unfold.false loop.1 loop.2 loop.3 > [ 4, loop.1.backedge ] @@ -241,3 +245,6 @@ infloop.i: exit: ret i32 0 } + +!0 = !{!"function_entry_count", i32 10} +!1 = !{!"branch_weights", i32 3, i32 5} diff --git a/llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-transform.ll b/llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-transform.ll index ad05684..092c854 100644 --- a/llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-transform.ll +++ b/llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-transform.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals ; RUN: opt -S -passes=dfa-jump-threading %s | FileCheck %s ; These tests check that the DFA jump threading transformation is applied @@ -301,7 +301,7 @@ end: ret void } -define void @pr106083_invalidBBarg_fold(i1 %cmp1, i1 %cmp2, i1 %not, ptr %d) { +define void @pr106083_invalidBBarg_fold(i1 %cmp1, i1 %cmp2, i1 %not, ptr %d) !prof !0 { ; CHECK-LABEL: @pr106083_invalidBBarg_fold( ; CHECK-NEXT: bb: ; CHECK-NEXT: br label [[BB1:%.*]] @@ -310,7 +310,7 @@ define void @pr106083_invalidBBarg_fold(i1 %cmp1, i1 %cmp2, i1 %not, ptr %d) { ; CHECK-NEXT: br i1 [[NOT:%.*]], label [[BB7_JT0]], label [[BB2:%.*]] ; CHECK: BB2: ; CHECK-NEXT: store i16 0, ptr [[D:%.*]], align 2 -; CHECK-NEXT: br i1 [[CMP2:%.*]], label [[BB7:%.*]], label [[SPEC_SELECT_SI_UNFOLD_FALSE_JT0:%.*]] +; CHECK-NEXT: br i1 [[CMP2:%.*]], label [[BB7:%.*]], label [[SPEC_SELECT_SI_UNFOLD_FALSE_JT0:%.*]], !prof [[PROF1:![0-9]+]] ; CHECK: spec.select.si.unfold.false: ; CHECK-NEXT: br label [[BB9]] ; CHECK: spec.select.si.unfold.false.jt0: @@ -357,7 +357,7 @@ BB1: ; preds = %BB1.backedge, %BB7, BB2: ; preds = %BB1 store i16 0, ptr %d, align 2 - %spec.select = select i1 %cmp2, i32 %sel, i32 0 + %spec.select = select i1 %cmp2, i32 %sel, i32 0, !prof !1 br label %BB7 BB7: ; preds = %BB2, %BB1 @@ -444,3 +444,10 @@ select.unfold: ; preds = %bb1, %.loopexit6 bb2: ; preds = %select.unfold unreachable } + +!0 = !{!"function_entry_count", i32 10} +!1 = !{!"branch_weights", i32 3, i32 5} +;. +; CHECK: [[META0:![0-9]+]] = !{!"function_entry_count", i32 10} +; CHECK: [[PROF1]] = !{!"branch_weights", i32 3, i32 5} +;. diff --git a/llvm/test/Transforms/LoopVectorize/epilog-vectorization-scev-expansion.ll b/llvm/test/Transforms/LoopVectorize/epilog-vectorization-scev-expansion.ll new file mode 100644 index 0000000..b020e59 --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/epilog-vectorization-scev-expansion.ll @@ -0,0 +1,73 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6 +; RUN: opt -p loop-vectorize -force-vector-width=4 -enable-epilogue-vectorization -epilogue-vectorization-force-VF=4 -S %s | FileCheck %s + +@end = external global [128 x i8] + +; Test case for https://github.com/llvm/llvm-project/issues/162128. +define void @test_epilogue_step_scev_expansion(ptr %dst) { +; CHECK-LABEL: define void @test_epilogue_step_scev_expansion( +; CHECK-SAME: ptr [[DST:%.*]]) { +; CHECK-NEXT: [[ITER_CHECK:.*]]: +; CHECK-NEXT: br i1 false, label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]] +; CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]: +; CHECK-NEXT: br i1 false, label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]] +; CHECK: [[VECTOR_PH]]: +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 sub (i64 0, i64 ptrtoint (ptr @end to i64)), 4 +; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 sub (i64 0, i64 ptrtoint (ptr @end to i64)), [[N_MOD_VF]] +; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] +; CHECK: [[VECTOR_BODY]]: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDEX]] +; CHECK-NEXT: store <4 x i8> zeroinitializer, ptr [[TMP0]], align 1 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP1]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK: [[MIDDLE_BLOCK]]: +; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 sub (i64 0, i64 ptrtoint (ptr @end to i64)), [[N_VEC]] +; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]] +; CHECK: [[VEC_EPILOG_ITER_CHECK]]: +; CHECK-NEXT: [[N_VEC_REMAINING:%.*]] = sub i64 sub (i64 0, i64 ptrtoint (ptr @end to i64)), [[N_VEC]] +; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_VEC_REMAINING]], 4 +; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]] +; CHECK: [[VEC_EPILOG_PH]]: +; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ] +; CHECK-NEXT: [[N_MOD_VF1:%.*]] = urem i64 sub (i64 0, i64 ptrtoint (ptr @end to i64)), 4 +; CHECK-NEXT: [[N_VEC2:%.*]] = sub i64 sub (i64 0, i64 ptrtoint (ptr @end to i64)), [[N_MOD_VF1]] +; CHECK-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]] +; CHECK: [[VEC_EPILOG_VECTOR_BODY]]: +; CHECK-NEXT: [[INDEX3:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT4:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDEX3]] +; CHECK-NEXT: store <4 x i8> zeroinitializer, ptr [[TMP2]], align 1 +; CHECK-NEXT: [[INDEX_NEXT4]] = add nuw i64 [[INDEX3]], 4 +; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT4]], [[N_VEC2]] +; CHECK-NEXT: br i1 [[TMP3]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; CHECK: [[VEC_EPILOG_MIDDLE_BLOCK]]: +; CHECK-NEXT: [[CMP_N5:%.*]] = icmp eq i64 sub (i64 0, i64 ptrtoint (ptr @end to i64)), [[N_VEC2]] +; CHECK-NEXT: br i1 [[CMP_N5]], label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]] +; CHECK: [[VEC_EPILOG_SCALAR_PH]]: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC2]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ] +; CHECK-NEXT: br label %[[LOOP:.*]] +; CHECK: [[LOOP]]: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] +; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]] +; CHECK-NEXT: store i8 0, ptr [[GEP_DST]], align 1 +; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], sub (i64 0, i64 ptrtoint (ptr getelementptr inbounds nuw (i8, ptr @end, i64 1) to i64)) +; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] +; CHECK: [[EXIT]]: +; CHECK-NEXT: ret void +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep.dst = getelementptr i8, ptr %dst, i64 %iv + store i8 0, ptr %gep.dst, align 1 + %iv.next = add i64 %iv, 1 + %ec = icmp eq i64 %iv, sub (i64 0, i64 ptrtoint (ptr getelementptr inbounds nuw (i8, ptr @end, i64 1) to i64)) + br i1 %ec, label %exit, label %loop + +exit: + ret void +} diff --git a/llvm/test/tools/llvm-ar/extract.test b/llvm/test/tools/llvm-ar/extract.test index bf46cc0..f8be7fd 100644 --- a/llvm/test/tools/llvm-ar/extract.test +++ b/llvm/test/tools/llvm-ar/extract.test @@ -1,5 +1,4 @@ ## Test extract operation. -# XFAIL: target={{.*}}-darwin{{.*}} # RUN: rm -rf %t && mkdir -p %t/extracted/ @@ -9,7 +8,7 @@ # RUN: echo filea > %t/a.txt # RUN: echo fileb > %t/b.txt -# RUN: llvm-ar rc %t/archive.a %t/a.txt %t/b.txt +# RUN: llvm-ar rc --format=gnu %t/archive.a %t/a.txt %t/b.txt ## Single member: # RUN: cd %t/extracted && llvm-ar xv %t/archive.a a.txt | FileCheck %s --check-prefix=A diff --git a/llvm/test/tools/llvm-ar/print.test b/llvm/test/tools/llvm-ar/print.test index 997c05f..c104fb4 100644 --- a/llvm/test/tools/llvm-ar/print.test +++ b/llvm/test/tools/llvm-ar/print.test @@ -1,12 +1,11 @@ ## Test Print output -# XFAIL: target={{.*}}-darwin{{.*}} # RUN: rm -rf %t && mkdir -p %t # RUN: echo file1 > %t/1.txt # RUN: echo file2 > %t/2.txt # RUN: echo file3 > %t/3.txt -# RUN: llvm-ar -rc %t/archive.a %t/1.txt %t/2.txt %t/3.txt +# RUN: llvm-ar -rc --format=gnu %t/archive.a %t/1.txt %t/2.txt %t/3.txt ## Print empty archive: # RUN: llvm-ar --format=gnu cr %t/empty.a diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-fp.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-fp.s new file mode 100644 index 0000000..b20206f --- /dev/null +++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-fp.s @@ -0,0 +1,4848 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -instruction-tables=full -iterations=1 < %s | FileCheck %s + +# The legal (SEW, LMUL) pairs for FP on sifive-x390 are: +# (e16, mf4) (e16, mf2) (e16, m1) (e16, m2) (e16, m4) (e16, m8) +# (e32, mf2) (e32, m1) (e32, m2) (e32, m4) (e32, m8) +# (e64, m1) (e64, m2) (e64, m4) (e64, m8) +# Widening instructions do not have e64 + +# Vector Single-Width FP +vsetvli zero, zero, e16, mf4, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e16, mf2, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e16, m1, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e16, m2, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e16, m4, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e16, m8, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e32, mf2, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 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v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e32, m4, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e32, m8, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 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v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e64, m2, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e64, m4, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e64, m8, tu, mu +vfadd.vv v8, v16, v24 +vfadd.vf v8, v16, f8 +vfsub.vv v8, v16, v24 +vfsub.vf v8, v16, f8 +vfrsub.vf v8, v16, f8 +vfmul.vv v8, v16, v24 +vfmul.vf v8, v16, f8 +vfdiv.vv v8, v16, v24 +vfdiv.vf v8, v16, f8 +vfrdiv.vf v8, v16, f8 +vfmacc.vv v8, v16, v24 +vfmacc.vf v8, f8, v24 +vfnmacc.vv v8, v16, v24 +vfnmacc.vf v8, f8, v24 +vfmsac.vv v8, v16, v24 +vfmsac.vf v8, f8, v24 +vfnmsac.vv v8, v16, v24 +vfnmsac.vf v8, f8, v24 +vfmadd.vv v8, v16, v24 +vfmadd.vf v8, f8, v24 +vfnmadd.vv v8, v16, v24 +vfnmadd.vf v8, f8, v24 +vfmsub.vv v8, v16, v24 +vfmsub.vf v8, f8, v24 +vfnmsub.vv v8, v16, v24 +vfnmsub.vf v8, f8, v24 +vfsqrt.v v8, v24 +vfrsqrt7.v v8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +# Vector Widening FP +# no e64 +vsetvli zero, zero, e16, mf4, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e16, mf2, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e16, m1, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e16, m2, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e16, m4, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vsetvli zero, zero, e16, m8, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vsetvli zero, zero, e32, mf2, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vsetvli zero, zero, e32, m1, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vsetvli zero, zero, e32, m2, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vsetvli zero, zero, e32, m4, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vsetvli zero, zero, e32, m8, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e16, m8, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e32, mf2, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e32, m1, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e32, m2, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e32, m4, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +vsetvli zero, zero, e32, m8, tu, mu +vfwadd.vv v8, v16, v24 +vfwadd.vf v8, v16, f8 +vfwsub.vv v8, v16, v24 +vfwsub.vf v8, v16, f8 +vfwadd.wv v8, v16, v24 +vfwadd.wf v8, v16, f8 +vfwsub.wv v8, v16, v24 +vfwsub.wf v8, v16, f8 +vfwmul.vv v8, v16, v24 +vfwmul.vf v8, v16, f8 +vfwmacc.vv v8, v16, v24 +vfwmacc.vf v8, f8, v24 +vfwnmacc.vv v8, v16, v24 +vfwnmacc.vf v8, f8, v24 +vfwmsac.vv v8, v16, v24 +vfwmsac.vf v8, f8, v24 +vfwnmsac.vv v8, v16, v24 +vfwnmsac.vf v8, f8, v24 +vfrec7.v v8, v24 +vfmin.vv v8, v16, v24 +vfmin.vf v8, v16, f8 +vfmax.vv v8, v16, v24 +vfmax.vf v8, v16, f8 +vfsgnj.vv v8, v16, v24 +vfsgnj.vf v8, v16, f8 +vfsgnjn.vv v8, v16, v24 +vfsgnjn.vf v8, v16, f8 +vfsgnjx.vv v8, v16, v24 +vfsgnjx.vf v8, v16, f8 +vfcvt.xu.f.v v8, v16 +vfcvt.x.f.v v8, v16 +vfcvt.rtz.xu.f.v v8, v16 +vfcvt.rtz.x.f.v v8, v16 +vfcvt.f.xu.v v8, v16 +vfcvt.f.x.v v8, v16 +vfwcvt.xu.f.v v8, v16 +vfwcvt.x.f.v v8, v16 +vfwcvt.rtz.xu.f.v v8, v16 +vfwcvt.rtz.x.f.v v8, v16 +vfwcvt.f.xu.v v8, v16 +vfwcvt.f.x.v v8, v16 +vfwcvt.f.f.v v8, v16 +vfncvt.xu.f.w v8, v16 +vfncvt.x.f.w v8, v16 +vfncvt.rtz.xu.f.w v8, v16 +vfncvt.rtz.x.f.w v8, v16 +vfncvt.f.xu.w v8, v16 +vfncvt.f.x.w v8, v16 +vfncvt.f.f.w v8, v16 +vfncvt.rod.f.f.w v8, v16 + +# CHECK: Resources: +# CHECK-NEXT: [0] - VLEN512SiFive7FDiv:1 +# CHECK-NEXT: [1] - VLEN512SiFive7IDiv:1 +# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:1 +# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB +# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:1 +# CHECK-NEXT: [5] - VLEN512SiFive7VA:1 +# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:1 +# CHECK-NEXT: [7] - VLEN512SiFive7VL:1 +# CHECK-NEXT: [8] - VLEN512SiFive7VS:1 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) +# CHECK-NEXT: [7]: Bypass Latency +# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle]) +# CHECK-NEXT: [9]: LLVM Opcode Name + +# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf4, tu, mu +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 30 30.00 30 VLEN512SiFive7VA[1,31],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 30 30.00 30 VLEN512SiFive7VA[1,31],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 30 30.00 30 VLEN512SiFive7VA[1,31],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 30 30.00 30 VLEN512SiFive7VA[1,31],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf2, tu, mu +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 60 60.00 60 VLEN512SiFive7VA[1,61],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 60 60.00 60 VLEN512SiFive7VA[1,61],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 60 60.00 60 VLEN512SiFive7VA[1,61],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 60 60.00 60 VLEN512SiFive7VA[1,61],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, tu, mu +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 120 120.00 120 VLEN512SiFive7VA[1,121],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 120 120.00 120 VLEN512SiFive7VA[1,121],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 120 120.00 120 VLEN512SiFive7VA[1,121],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 120 120.00 120 VLEN512SiFive7VA[1,121],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m2, tu, mu +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 240 240.00 240 VLEN512SiFive7VA[1,241],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 240 240.00 240 VLEN512SiFive7VA[1,241],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 240 240.00 240 VLEN512SiFive7VA[1,241],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 240 240.00 240 VLEN512SiFive7VA[1,241],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m4, tu, mu +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 480 480.00 480 VLEN512SiFive7VA[1,481],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 480 480.00 480 VLEN512SiFive7VA[1,481],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 480 480.00 480 VLEN512SiFive7VA[1,481],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 480 480.00 480 VLEN512SiFive7VA[1,481],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m8, tu, mu +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 960 960.00 960 VLEN512SiFive7VA[1,961],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 960 960.00 960 VLEN512SiFive7VA[1,961],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 960 960.00 960 VLEN512SiFive7VA[1,961],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 960 960.00 960 VLEN512SiFive7VA[1,961],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, mf2, tu, mu +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 56 56.00 56 VLEN512SiFive7VA[1,57],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 56 56.00 56 VLEN512SiFive7VA[1,57],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 56 56.00 56 VLEN512SiFive7VA[1,57],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 56 56.00 56 VLEN512SiFive7VA[1,57],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 112 112.00 112 VLEN512SiFive7VA[1,113],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 112 112.00 112 VLEN512SiFive7VA[1,113],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 112 112.00 112 VLEN512SiFive7VA[1,113],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 112 112.00 112 VLEN512SiFive7VA[1,113],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m2, tu, mu +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 224 224.00 224 VLEN512SiFive7VA[1,225],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 224 224.00 224 VLEN512SiFive7VA[1,225],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 224 224.00 224 VLEN512SiFive7VA[1,225],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 224 224.00 224 VLEN512SiFive7VA[1,225],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m4, tu, mu +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 448 448.00 448 VLEN512SiFive7VA[1,449],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 448 448.00 448 VLEN512SiFive7VA[1,449],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 448 448.00 448 VLEN512SiFive7VA[1,449],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 448 448.00 448 VLEN512SiFive7VA[1,449],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m8, tu, mu +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 896 896.00 896 VLEN512SiFive7VA[1,897],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 896 896.00 896 VLEN512SiFive7VA[1,897],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 896 896.00 896 VLEN512SiFive7VA[1,897],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 896 896.00 896 VLEN512SiFive7VA[1,897],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m1, tu, mu +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 114 114.00 114 VLEN512SiFive7VA[1,115],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 114 114.00 114 VLEN512SiFive7VA[1,115],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 114 114.00 114 VLEN512SiFive7VA[1,115],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 114 114.00 114 VLEN512SiFive7VA[1,115],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m2, tu, mu +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 228 228.00 228 VLEN512SiFive7VA[1,229],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 228 228.00 228 VLEN512SiFive7VA[1,229],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 228 228.00 228 VLEN512SiFive7VA[1,229],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 228 228.00 228 VLEN512SiFive7VA[1,229],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m4, tu, mu +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 456 456.00 456 VLEN512SiFive7VA[1,457],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 456 456.00 456 VLEN512SiFive7VA[1,457],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 456 456.00 456 VLEN512SiFive7VA[1,457],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 456 456.00 456 VLEN512SiFive7VA[1,457],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m8, tu, mu +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFADD_VV vfadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFADD_VF vfadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSUB_VV vfsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSUB_VF vfsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFRSUB_VF vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMUL_VV vfmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMUL_VF vfmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 912 912.00 912 VLEN512SiFive7VA[1,913],VLEN512SiFive7VCQ VFDIV_VV vfdiv.vv v8, v16, v24 +# CHECK-NEXT: 1 912 912.00 912 VLEN512SiFive7VA[1,913],VLEN512SiFive7VCQ VFDIV_VF vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 912 912.00 912 VLEN512SiFive7VA[1,913],VLEN512SiFive7VCQ VFRDIV_VF vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMACC_VV vfmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMACC_VF vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMACC_VV vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMACC_VF vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSAC_VV vfmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSAC_VF vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSAC_VV vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSAC_VF vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMADD_VV vfmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMADD_VF vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMADD_VV vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMADD_VF vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSUB_VV vfmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMSUB_VF vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSUB_VV vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNMSUB_VF vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: 1 912 912.00 912 VLEN512SiFive7VA[1,913],VLEN512SiFive7VCQ VFSQRT_V vfsqrt.v v8, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFRSQRT7_V vfrsqrt7.v v8, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf4, tu, mu +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, mf2, tu, mu +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m1, tu, mu +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m2, tu, mu +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m4, tu, mu +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m8, tu, mu +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, mf2, tu, mu +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m2, tu, mu +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m4, tu, mu +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m8, tu, mu +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e16, m8, tu, mu +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, mf2, tu, mu +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 1.00 8 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m1, tu, mu +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m2, tu, mu +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 4.00 4 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 4.00 8 VLEN512SiFive7VA[1,5],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m4, tu, mu +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 8.00 4 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e32, m8, tu, mu +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VV vfwadd.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_VF vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VV vfwsub.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_VF vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WV vfwadd.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWADD_WF vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WV vfwsub.wv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWSUB_WF vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VV vfwmul.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMUL_VF vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VV vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMACC_VF vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VV vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMACC_VF vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VV vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWMSAC_VF vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VV vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWNMSAC_VF vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFREC7_V vfrec7.v v8, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VV vfmin.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMIN_VF vfmin.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VV vfmax.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFMAX_VF vfmax.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VV vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJ_VF vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VV vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJN_VF vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VV vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFSGNJX_VF vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: 1 8 8.00 8 VLEN512SiFive7VA[1,9],VLEN512SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w v8, v16 +# CHECK-NEXT: 1 8 16.00 8 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16 + +# CHECK: Resources: +# CHECK-NEXT: [0] - VLEN512SiFive7FDiv +# CHECK-NEXT: [1] - VLEN512SiFive7IDiv +# CHECK-NEXT: [2] - VLEN512SiFive7PipeA +# CHECK-NEXT: [3] - VLEN512SiFive7PipeB +# CHECK-NEXT: [4] - VLEN512SiFive7VA +# CHECK-NEXT: [5] - VLEN512SiFive7VCQ +# CHECK-NEXT: [6] - VLEN512SiFive7VL +# CHECK-NEXT: [7] - VLEN512SiFive7VS + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] +# CHECK-NEXT: - - 32.00 - 32088.00 1558.00 - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu +# CHECK-NEXT: - - - - 2.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 31.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 31.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 31.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 31.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu +# CHECK-NEXT: - - - - 2.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 61.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 61.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 61.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 61.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu +# CHECK-NEXT: - - - - 3.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 121.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 121.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 121.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 121.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu +# CHECK-NEXT: - - - - 5.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 241.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 241.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 241.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 241.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu +# CHECK-NEXT: - - - - 9.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 481.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 481.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 481.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 481.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu +# CHECK-NEXT: - - - - 17.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 961.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 961.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 961.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 961.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu +# CHECK-NEXT: - - - - 2.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 57.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 57.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 57.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 57.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu +# CHECK-NEXT: - - - - 3.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 113.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 113.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 113.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 113.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu +# CHECK-NEXT: - - - - 5.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 225.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 225.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 225.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 225.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu +# CHECK-NEXT: - - - - 9.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 449.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 449.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 449.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 449.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu +# CHECK-NEXT: - - - - 17.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 897.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 897.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 897.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 897.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu +# CHECK-NEXT: - - - - 3.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 115.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 115.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 115.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 115.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu +# CHECK-NEXT: - - - - 5.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 229.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 229.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 229.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 229.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu +# CHECK-NEXT: - - - - 9.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 457.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 457.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 457.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 457.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu +# CHECK-NEXT: - - - - 17.00 1.00 - - vfadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 913.00 1.00 - - vfdiv.vv v8, v16, v24 +# CHECK-NEXT: - - - - 913.00 1.00 - - vfdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 913.00 1.00 - - vfrdiv.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmadd.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfnmsub.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 913.00 1.00 - - vfsqrt.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrsqrt7.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 2.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 3.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 5.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 +# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwadd.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwsub.wf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmul.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmacc.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vv v8, v16, v24 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwnmsac.vf v8, fs0, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfrec7.v v8, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmin.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfmax.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnj.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjn.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vv v8, v16, v24 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfsgnjx.vf v8, v16, fs0 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.xu.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.rtz.x.f.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.xu.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.x.v v8, v16 +# CHECK-NEXT: - - - - 9.00 1.00 - - vfwcvt.f.f.v v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.xu.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rtz.x.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.xu.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.x.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.f.f.w v8, v16 +# CHECK-NEXT: - - - - 17.00 1.00 - - vfncvt.rod.f.f.w v8, v16 diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s index 8838c86..ecd96a3 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s +++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s @@ -126,19 +126,19 @@ amomaxu.d.aqrl s5, s4, (s3) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_W lr.w t0, (t1) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_W_AQ lr.w.aq t1, (t2) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_W_RL lr.w.rl t2, (t3) -# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_W_AQ_RL lr.w.aqrl t3, (t4) +# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_W_AQRL lr.w.aqrl t3, (t4) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_W sc.w t6, t5, (t4) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_W_AQ sc.w.aq t5, t4, (t3) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_W_RL sc.w.rl t4, t3, (t2) -# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_W_AQ_RL sc.w.aqrl t3, t2, (t1) +# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_W_AQRL sc.w.aqrl t3, t2, (t1) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_D lr.d t0, (t1) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_D_AQ lr.d.aq t1, (t2) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_D_RL lr.d.rl t2, (t3) -# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_D_AQ_RL lr.d.aqrl t3, (t4) +# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_D_AQRL lr.d.aqrl t3, (t4) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_D sc.d t6, t5, (t4) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_D_AQ sc.d.aq t5, t4, (t3) # CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_D_RL sc.d.rl t4, t3, (t2) -# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_D_AQ_RL sc.d.aqrl t3, t2, (t1) +# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_D_AQRL sc.d.aqrl t3, t2, (t1) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_W amoswap.w a4, ra, (s0) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_W amoadd.w a1, a2, (a3) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_W amoxor.w a2, a3, (a4) @@ -166,15 +166,15 @@ amomaxu.d.aqrl s5, s4, (s3) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_W_RL amomax.w.rl s7, s6, (s5) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_W_RL amominu.w.rl s6, s5, (s4) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_W_RL amomaxu.w.rl s5, s4, (s3) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_W_AQ_RL amoswap.w.aqrl a4, ra, (s0) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_W_AQ_RL amoadd.w.aqrl a1, a2, (a3) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_W_AQ_RL amoxor.w.aqrl a2, a3, (a4) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOAND_W_AQ_RL amoand.w.aqrl a3, a4, (a5) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOOR_W_AQ_RL amoor.w.aqrl a4, a5, (a6) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMIN_W_AQ_RL amomin.w.aqrl a5, a6, (a7) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_W_AQ_RL amomax.w.aqrl s7, s6, (s5) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_W_AQ_RL amominu.w.aqrl s6, s5, (s4) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_W_AQ_RL amomaxu.w.aqrl s5, s4, (s3) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_W_AQRL amoswap.w.aqrl a4, ra, (s0) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_W_AQRL amoadd.w.aqrl a1, a2, (a3) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_W_AQRL amoxor.w.aqrl a2, a3, (a4) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOAND_W_AQRL amoand.w.aqrl a3, a4, (a5) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOOR_W_AQRL amoor.w.aqrl a4, a5, (a6) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMIN_W_AQRL amomin.w.aqrl a5, a6, (a7) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_W_AQRL amomax.w.aqrl s7, s6, (s5) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_W_AQRL amominu.w.aqrl s6, s5, (s4) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_W_AQRL amomaxu.w.aqrl s5, s4, (s3) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_D amoswap.d a4, ra, (s0) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_D amoadd.d a1, a2, (a3) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_D amoxor.d a2, a3, (a4) @@ -202,15 +202,15 @@ amomaxu.d.aqrl s5, s4, (s3) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_D_RL amomax.d.rl s7, s6, (s5) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_D_RL amominu.d.rl s6, s5, (s4) # CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_D_RL amomaxu.d.rl s5, s4, (s3) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_D_AQ_RL amoswap.d.aqrl a4, ra, (s0) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_D_AQ_RL amoadd.d.aqrl a1, a2, (a3) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_D_AQ_RL amoxor.d.aqrl a2, a3, (a4) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOAND_D_AQ_RL amoand.d.aqrl a3, a4, (a5) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOOR_D_AQ_RL amoor.d.aqrl a4, a5, (a6) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMIN_D_AQ_RL amomin.d.aqrl a5, a6, (a7) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_D_AQ_RL amomax.d.aqrl s7, s6, (s5) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_D_AQ_RL amominu.d.aqrl s6, s5, (s4) -# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_D_AQ_RL amomaxu.d.aqrl s5, s4, (s3) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_D_AQRL amoswap.d.aqrl a4, ra, (s0) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_D_AQRL amoadd.d.aqrl a1, a2, (a3) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_D_AQRL amoxor.d.aqrl a2, a3, (a4) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOAND_D_AQRL amoand.d.aqrl a3, a4, (a5) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOOR_D_AQRL amoor.d.aqrl a4, a5, (a6) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMIN_D_AQRL amomin.d.aqrl a5, a6, (a7) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_D_AQRL amomax.d.aqrl s7, s6, (s5) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_D_AQRL amominu.d.aqrl s6, s5, (s4) +# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_D_AQRL amomaxu.d.aqrl s5, s4, (s3) # CHECK: Resources: # CHECK-NEXT: [0] - SMX60_FP diff --git a/llvm/test/tools/llvm-offload-binary/llvm-offload-binary.ll b/llvm/test/tools/llvm-offload-binary/llvm-offload-binary.ll index b196c24..c6027b3 100644 --- a/llvm/test/tools/llvm-offload-binary/llvm-offload-binary.ll +++ b/llvm/test/tools/llvm-offload-binary/llvm-offload-binary.ll @@ -8,3 +8,7 @@ ; CHECK-NEXT: arch abc ; CHECK-NEXT: triple x-y-z ; CHECK-NEXT: producer none + +; RUN: llvm-offload-binary -o %t3 --image=file=%s +; RUN: llvm-offload-binary %t3 --image=file=%t4 +; RUN: diff %s %t4 diff --git a/llvm/tools/llc/llc.cpp b/llvm/tools/llc/llc.cpp index a2327fb..7551a80 100644 --- a/llvm/tools/llc/llc.cpp +++ b/llvm/tools/llc/llc.cpp @@ -67,26 +67,25 @@ static codegen::RegisterCodeGenFlags CGF; // and back-end code generation options are specified with the target machine. // static cl::opt<std::string> -InputFilename(cl::Positional, cl::desc("<input bitcode>"), cl::init("-")); + InputFilename(cl::Positional, cl::desc("<input bitcode>"), cl::init("-")); static cl::list<std::string> InstPrinterOptions("M", cl::desc("InstPrinter options")); static cl::opt<std::string> -InputLanguage("x", cl::desc("Input language ('ir' or 'mir')")); + InputLanguage("x", cl::desc("Input language ('ir' or 'mir')")); -static cl::opt<std::string> -OutputFilename("o", cl::desc("Output filename"), cl::value_desc("filename")); +static cl::opt<std::string> OutputFilename("o", cl::desc("Output filename"), + cl::value_desc("filename")); static cl::opt<std::string> - SplitDwarfOutputFile("split-dwarf-output", - cl::desc(".dwo output filename"), + SplitDwarfOutputFile("split-dwarf-output", cl::desc(".dwo output filename"), cl::value_desc("filename")); static cl::opt<unsigned> -TimeCompilations("time-compilations", cl::Hidden, cl::init(1u), - cl::value_desc("N"), - cl::desc("Repeat compilation N times for timing")); + TimeCompilations("time-compilations", cl::Hidden, cl::init(1u), + cl::value_desc("N"), + cl::desc("Repeat compilation N times for timing")); static cl::opt<bool> TimeTrace("time-trace", cl::desc("Record time trace")); @@ -123,7 +122,7 @@ static cl::opt<char> cl::Prefix, cl::init('2')); static cl::opt<std::string> -TargetTriple("mtriple", cl::desc("Override target triple for module")); + TargetTriple("mtriple", cl::desc("Override target triple for module")); static cl::opt<std::string> SplitDwarfFile( "split-dwarf-file", @@ -167,6 +166,11 @@ static cl::opt<bool> DiscardValueNames( cl::desc("Discard names from Value (other than GlobalValue)."), cl::init(false), cl::Hidden); +static cl::opt<bool> + PrintMIR2VecVocab("print-mir2vec-vocab", cl::Hidden, + cl::desc("Print MIR2Vec vocabulary contents"), + cl::init(false)); + static cl::list<std::string> IncludeDirs("I", cl::desc("include search path")); static cl::opt<bool> RemarksWithHotness( @@ -409,8 +413,8 @@ int main(int argc, char **argv) { return 0; } -static bool addPass(PassManagerBase &PM, const char *argv0, - StringRef PassName, TargetPassConfig &TPC) { +static bool addPass(PassManagerBase &PM, const char *argv0, StringRef PassName, + TargetPassConfig &TPC) { if (PassName == "none") return false; @@ -610,7 +614,8 @@ static int compileModule(char **argv, LLVMContext &Context) { // Figure out where we are going to send the output. std::unique_ptr<ToolOutputFile> Out = GetOutputStream(TheTarget->getName(), TheTriple.getOS(), argv[0]); - if (!Out) return 1; + if (!Out) + return 1; // Ensure the filename is passed down to CodeViewDebug. Target->Options.ObjectFilenameForDebug = Out->outputFilename(); @@ -623,7 +628,7 @@ static int compileModule(char **argv, LLVMContext &Context) { if (!SplitDwarfOutputFile.empty()) { std::error_code EC; DwoOut = std::make_unique<ToolOutputFile>(SplitDwarfOutputFile, EC, - sys::fs::OF_None); + sys::fs::OF_None); if (EC) reportError(EC.message(), SplitDwarfOutputFile); } @@ -725,12 +730,25 @@ static int compileModule(char **argv, LLVMContext &Context) { } TPC.setInitialized(); PM.add(createPrintMIRPass(*OS)); + + // Add MIR2Vec vocabulary printer if requested + if (PrintMIR2VecVocab) { + PM.add(createMIR2VecVocabPrinterLegacyPass(errs())); + } + PM.add(createFreeMachineFunctionPass()); - } else if (Target->addPassesToEmitFile( - PM, *OS, DwoOut ? &DwoOut->os() : nullptr, - codegen::getFileType(), NoVerify, MMIWP)) { - if (!HasMCErrors) - reportError("target does not support generation of this file type"); + } else { + if (Target->addPassesToEmitFile(PM, *OS, DwoOut ? &DwoOut->os() : nullptr, + codegen::getFileType(), NoVerify, + MMIWP)) { + if (!HasMCErrors) + reportError("target does not support generation of this file type"); + } + + // Add MIR2Vec vocabulary printer if requested + if (PrintMIR2VecVocab) { + PM.add(createMIR2VecVocabPrinterLegacyPass(errs())); + } } Target->getObjFileLowering()->Initialize(MMIWP->getMMI().getContext(), diff --git a/llvm/tools/llvm-offload-binary/llvm-offload-binary.cpp b/llvm/tools/llvm-offload-binary/llvm-offload-binary.cpp index b1bc335..e22d13b 100644 --- a/llvm/tools/llvm-offload-binary/llvm-offload-binary.cpp +++ b/llvm/tools/llvm-offload-binary/llvm-offload-binary.cpp @@ -92,10 +92,9 @@ static Error bundleImages() { StringSaver Saver(Alloc); DenseMap<StringRef, StringRef> Args = getImageArguments(Image, Saver); - if (!Args.count("triple") || !Args.count("file")) - return createStringError( - inconvertibleErrorCode(), - "'file' and 'triple' are required image arguments"); + if (!Args.count("file")) + return createStringError(inconvertibleErrorCode(), + "'file' is a required image arguments"); // Permit using multiple instances of `file` in a single string. for (auto &File : llvm::split(Args["file"], ",")) { diff --git a/llvm/unittests/Analysis/IR2VecTest.cpp b/llvm/unittests/Analysis/IR2VecTest.cpp index d136cb6..40b4aa2 100644 --- a/llvm/unittests/Analysis/IR2VecTest.cpp +++ b/llvm/unittests/Analysis/IR2VecTest.cpp @@ -430,6 +430,60 @@ TEST_F(IR2VecTestFixture, GetFunctionVector_FlowAware) { EXPECT_TRUE(FuncVec.approximatelyEquals(Embedding(2, 58.1))); } +TEST_F(IR2VecTestFixture, MultipleComputeEmbeddingsConsistency_Symbolic) { + auto Emb = Embedder::create(IR2VecKind::Symbolic, *F, *V); + ASSERT_TRUE(static_cast<bool>(Emb)); + + // Get initial function vector + const auto &FuncVec1 = Emb->getFunctionVector(); + + // Compute embeddings again by calling getFunctionVector multiple times + const auto &FuncVec2 = Emb->getFunctionVector(); + const auto &FuncVec3 = Emb->getFunctionVector(); + + // All function vectors should be identical + EXPECT_TRUE(FuncVec1.approximatelyEquals(FuncVec2)); + EXPECT_TRUE(FuncVec1.approximatelyEquals(FuncVec3)); + EXPECT_TRUE(FuncVec2.approximatelyEquals(FuncVec3)); + + // Also check that instruction vectors remain consistent + const auto &InstMap1 = Emb->getInstVecMap(); + const auto &InstMap2 = Emb->getInstVecMap(); + + EXPECT_EQ(InstMap1.size(), InstMap2.size()); + for (const auto &[Inst, Vec1] : InstMap1) { + ASSERT_TRUE(InstMap2.count(Inst)); + EXPECT_TRUE(Vec1.approximatelyEquals(InstMap2.at(Inst))); + } +} + +TEST_F(IR2VecTestFixture, MultipleComputeEmbeddingsConsistency_FlowAware) { + auto Emb = Embedder::create(IR2VecKind::FlowAware, *F, *V); + ASSERT_TRUE(static_cast<bool>(Emb)); + + // Get initial function vector + const auto &FuncVec1 = Emb->getFunctionVector(); + + // Compute embeddings again by calling getFunctionVector multiple times + const auto &FuncVec2 = Emb->getFunctionVector(); + const auto &FuncVec3 = Emb->getFunctionVector(); + + // All function vectors should be identical + EXPECT_TRUE(FuncVec1.approximatelyEquals(FuncVec2)); + EXPECT_TRUE(FuncVec1.approximatelyEquals(FuncVec3)); + EXPECT_TRUE(FuncVec2.approximatelyEquals(FuncVec3)); + + // Also check that instruction vectors remain consistent + const auto &InstMap1 = Emb->getInstVecMap(); + const auto &InstMap2 = Emb->getInstVecMap(); + + EXPECT_EQ(InstMap1.size(), InstMap2.size()); + for (const auto &[Inst, Vec1] : InstMap1) { + ASSERT_TRUE(InstMap2.count(Inst)); + EXPECT_TRUE(Vec1.approximatelyEquals(InstMap2.at(Inst))); + } +} + static constexpr unsigned MaxOpcodes = Vocabulary::MaxOpcodes; [[maybe_unused]] static constexpr unsigned MaxTypeIDs = Vocabulary::MaxTypeIDs; diff --git a/llvm/unittests/CodeGen/CMakeLists.txt b/llvm/unittests/CodeGen/CMakeLists.txt index 22dbdaa..18332d2 100644 --- a/llvm/unittests/CodeGen/CMakeLists.txt +++ b/llvm/unittests/CodeGen/CMakeLists.txt @@ -37,6 +37,7 @@ add_llvm_unittest(CodeGenTests MachineInstrBundleIteratorTest.cpp MachineInstrTest.cpp MachineOperandTest.cpp + MIR2VecTest.cpp RegAllocScoreTest.cpp PassManagerTest.cpp ScalableVectorMVTsTest.cpp diff --git a/llvm/unittests/CodeGen/MIR2VecTest.cpp b/llvm/unittests/CodeGen/MIR2VecTest.cpp new file mode 100644 index 0000000..d243d82 --- /dev/null +++ b/llvm/unittests/CodeGen/MIR2VecTest.cpp @@ -0,0 +1,217 @@ +//===- MIR2VecTest.cpp ---------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "llvm/CodeGen/MIR2Vec.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/TargetInstrInfo.h" +#include "llvm/CodeGen/TargetSubtargetInfo.h" +#include "llvm/IR/IRBuilder.h" +#include "llvm/IR/Module.h" +#include "llvm/MC/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetOptions.h" +#include "llvm/TargetParser/Triple.h" +#include "gtest/gtest.h" + +using namespace llvm; +using namespace mir2vec; +using VocabMap = std::map<std::string, ir2vec::Embedding>; + +namespace { + +TEST(MIR2VecTest, RegexExtraction) { + // Test simple instruction names + EXPECT_EQ(MIRVocabulary::extractBaseOpcodeName("NOP"), "NOP"); + EXPECT_EQ(MIRVocabulary::extractBaseOpcodeName("RET"), "RET"); + EXPECT_EQ(MIRVocabulary::extractBaseOpcodeName("ADD16ri"), "ADD"); + EXPECT_EQ(MIRVocabulary::extractBaseOpcodeName("ADD32rr"), "ADD"); + EXPECT_EQ(MIRVocabulary::extractBaseOpcodeName("ADD64rm"), "ADD"); + EXPECT_EQ(MIRVocabulary::extractBaseOpcodeName("MOV8ri"), "MOV"); + EXPECT_EQ(MIRVocabulary::extractBaseOpcodeName("MOV32mr"), "MOV"); + EXPECT_EQ(MIRVocabulary::extractBaseOpcodeName("PUSH64r"), "PUSH"); + EXPECT_EQ(MIRVocabulary::extractBaseOpcodeName("POP64r"), "POP"); + EXPECT_EQ(MIRVocabulary::extractBaseOpcodeName("JMP_4"), "JMP"); + EXPECT_EQ(MIRVocabulary::extractBaseOpcodeName("CALL64pcrel32"), "CALL"); + EXPECT_EQ(MIRVocabulary::extractBaseOpcodeName("SOME_INSTR_123"), + "SOME_INSTR"); + EXPECT_EQ(MIRVocabulary::extractBaseOpcodeName("123ADD"), "ADD"); + EXPECT_FALSE(MIRVocabulary::extractBaseOpcodeName("123").empty()); +} + +class MIR2VecVocabTestFixture : public ::testing::Test { +protected: + std::unique_ptr<LLVMContext> Ctx; + std::unique_ptr<Module> M; + std::unique_ptr<TargetMachine> TM; + const TargetInstrInfo *TII; + + static void SetUpTestCase() { + InitializeAllTargets(); + InitializeAllTargetMCs(); + } + + void SetUp() override { + Triple TargetTriple("x86_64-unknown-linux-gnu"); + std::string Error; + const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error); + if (!T) { + GTEST_SKIP() << "x86_64-unknown-linux-gnu target triple not available; " + "Skipping test"; + return; + } + + Ctx = std::make_unique<LLVMContext>(); + M = std::make_unique<Module>("test", *Ctx); + M->setTargetTriple(TargetTriple); + + TargetOptions Options; + TM = std::unique_ptr<TargetMachine>( + T->createTargetMachine(TargetTriple, "", "", Options, std::nullopt)); + if (!TM) { + GTEST_SKIP() << "Failed to create X86 target machine; Skipping test"; + return; + } + + // Create a dummy function to get subtarget info + FunctionType *FT = FunctionType::get(Type::getVoidTy(*Ctx), false); + Function *F = + Function::Create(FT, Function::ExternalLinkage, "test", M.get()); + + // Get the target instruction info + TII = TM->getSubtargetImpl(*F)->getInstrInfo(); + if (!TII) { + GTEST_SKIP() << "Failed to get target instruction info; Skipping test"; + return; + } + } +}; + +// Function to find an opcode by name +static int findOpcodeByName(const TargetInstrInfo *TII, StringRef Name) { + for (unsigned Opcode = 1; Opcode < TII->getNumOpcodes(); ++Opcode) { + if (TII->getName(Opcode) == Name) + return Opcode; + } + return -1; // Not found +} + +TEST_F(MIR2VecVocabTestFixture, CanonicalOpcodeMappingTest) { + // Test that same base opcodes get same canonical indices + std::string BaseName1 = MIRVocabulary::extractBaseOpcodeName("ADD16ri"); + std::string BaseName2 = MIRVocabulary::extractBaseOpcodeName("ADD32rr"); + std::string BaseName3 = MIRVocabulary::extractBaseOpcodeName("ADD64rm"); + + EXPECT_EQ(BaseName1, BaseName2); + EXPECT_EQ(BaseName2, BaseName3); + + // Create a MIRVocabulary instance to test the mapping + // Use a minimal MIRVocabulary to trigger canonical mapping construction + VocabMap VMap; + Embedding Val = Embedding(64, 1.0f); + VMap["ADD"] = Val; + MIRVocabulary TestVocab(std::move(VMap), TII); + + unsigned Index1 = TestVocab.getCanonicalIndexForBaseName(BaseName1); + unsigned Index2 = TestVocab.getCanonicalIndexForBaseName(BaseName2); + unsigned Index3 = TestVocab.getCanonicalIndexForBaseName(BaseName3); + EXPECT_EQ(Index1, Index2); + EXPECT_EQ(Index2, Index3); + + // Test that different base opcodes get different canonical indices + std::string AddBase = MIRVocabulary::extractBaseOpcodeName("ADD32rr"); + std::string SubBase = MIRVocabulary::extractBaseOpcodeName("SUB32rr"); + std::string MovBase = MIRVocabulary::extractBaseOpcodeName("MOV32rr"); + + unsigned AddIndex = TestVocab.getCanonicalIndexForBaseName(AddBase); + unsigned SubIndex = TestVocab.getCanonicalIndexForBaseName(SubBase); + unsigned MovIndex = TestVocab.getCanonicalIndexForBaseName(MovBase); + + EXPECT_NE(AddIndex, SubIndex); + EXPECT_NE(SubIndex, MovIndex); + EXPECT_NE(AddIndex, MovIndex); + + // Even though we only added "ADD" to the vocab, the canonical mapping + // should assign unique indices to all the base opcodes of the target + // Ideally, we would check against the exact number of unique base opcodes + // for X86, but that would make the test brittle. So we just check that + // the number is reasonably closer to the expected number (>6880) and not just + // opcodes that we added. + EXPECT_GT(TestVocab.getCanonicalSize(), + 6880u); // X86 has >6880 unique base opcodes + + // Check that the embeddings for opcodes not in the vocab are zero vectors + int Add32rrOpcode = findOpcodeByName(TII, "ADD32rr"); + ASSERT_NE(Add32rrOpcode, -1) << "ADD32rr opcode not found"; + EXPECT_TRUE(TestVocab[Add32rrOpcode].approximatelyEquals(Val)); + + int Sub32rrOpcode = findOpcodeByName(TII, "SUB32rr"); + ASSERT_NE(Sub32rrOpcode, -1) << "SUB32rr opcode not found"; + EXPECT_TRUE( + TestVocab[Sub32rrOpcode].approximatelyEquals(Embedding(64, 0.0f))); + + int Mov32rrOpcode = findOpcodeByName(TII, "MOV32rr"); + ASSERT_NE(Mov32rrOpcode, -1) << "MOV32rr opcode not found"; + EXPECT_TRUE( + TestVocab[Mov32rrOpcode].approximatelyEquals(Embedding(64, 0.0f))); +} + +// Test deterministic mapping +TEST_F(MIR2VecVocabTestFixture, DeterministicMapping) { + // Test that the same base name always maps to the same canonical index + std::string BaseName = "ADD"; + + // Create a MIRVocabulary instance to test deterministic mapping + // Use a minimal MIRVocabulary to trigger canonical mapping construction + VocabMap VMap; + VMap["ADD"] = Embedding(64, 1.0f); + MIRVocabulary TestVocab(std::move(VMap), TII); + + unsigned Index1 = TestVocab.getCanonicalIndexForBaseName(BaseName); + unsigned Index2 = TestVocab.getCanonicalIndexForBaseName(BaseName); + unsigned Index3 = TestVocab.getCanonicalIndexForBaseName(BaseName); + + EXPECT_EQ(Index1, Index2); + EXPECT_EQ(Index2, Index3); + + // Test across multiple runs + for (int Pos = 0; Pos < 100; ++Pos) { + unsigned Index = TestVocab.getCanonicalIndexForBaseName(BaseName); + EXPECT_EQ(Index, Index1); + } +} + +// Test MIRVocabulary construction +TEST_F(MIR2VecVocabTestFixture, VocabularyConstruction) { + VocabMap VMap; + VMap["ADD"] = Embedding(128, 1.0f); // Dimension 128, all values 1.0 + VMap["SUB"] = Embedding(128, 2.0f); // Dimension 128, all values 2.0 + + MIRVocabulary Vocab(std::move(VMap), TII); + EXPECT_TRUE(Vocab.isValid()); + EXPECT_EQ(Vocab.getDimension(), 128u); + + // Test iterator - iterates over individual embeddings + auto IT = Vocab.begin(); + EXPECT_NE(IT, Vocab.end()); + + // Check first embedding exists and has correct dimension + EXPECT_EQ((*IT).size(), 128u); + + size_t Count = 0; + for (auto IT = Vocab.begin(); IT != Vocab.end(); ++IT) { + EXPECT_EQ((*IT).size(), 128u); + ++Count; + } + EXPECT_GT(Count, 0u); +} + +} // namespace
\ No newline at end of file diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 5c6c824..5d69a31 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -552,7 +552,7 @@ TEST(ParseArchString, const auto &Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 2UL); EXPECT_EQ(Exts.count("zalasr"), 1U); - auto MaybeISAInfo2 = RISCVISAInfo::parseArchString("rv64izalasr0p1", true); + auto MaybeISAInfo2 = RISCVISAInfo::parseArchString("rv64izalasr0p9", true); ASSERT_THAT_EXPECTED(MaybeISAInfo2, Succeeded()); const auto &Exts2 = (*MaybeISAInfo2)->getExtensions(); EXPECT_EQ(Exts2.size(), 2UL); @@ -581,7 +581,7 @@ TEST(ParseArchString, RejectsUnrecognizedVersionForExperimentalExtension) { toString( RISCVISAInfo::parseArchString("rv64izalasr9p9", true).takeError()), "unsupported version number 9.9 for experimental extension 'zalasr' " - "(this compiler supports 0.1)"); + "(this compiler supports 0.9)"); } TEST(ParseArchString, RejectsExtensionVersionForG) { @@ -1188,7 +1188,7 @@ Experimental extensions zibi 0.1 zicfilp 1.0 This is a long dummy description zicfiss 1.0 - zalasr 0.1 + zalasr 0.9 zvbc32e 0.7 zvfbfa 0.1 zvfofp8min 0.2 diff --git a/llvm/utils/gn/secondary/clang/test/BUILD.gn b/llvm/utils/gn/secondary/clang/test/BUILD.gn index 0944216..5c58903 100644 --- a/llvm/utils/gn/secondary/clang/test/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/test/BUILD.gn @@ -185,6 +185,7 @@ group("test") { "//llvm/tools/llvm-nm:symlinks", "//llvm/tools/llvm-objcopy:symlinks", "//llvm/tools/llvm-objdump:symlinks", + "//llvm/tools/llvm-offload-binary", "//llvm/tools/llvm-pdbutil", "//llvm/tools/llvm-profdata", "//llvm/tools/llvm-rc:symlinks", diff --git a/llvm/utils/gn/secondary/llvm/test/BUILD.gn b/llvm/utils/gn/secondary/llvm/test/BUILD.gn index 0b6c81c6..b297dbd 100644 --- a/llvm/utils/gn/secondary/llvm/test/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/test/BUILD.gn @@ -303,6 +303,7 @@ group("test") { "//llvm/tools/llvm-nm", "//llvm/tools/llvm-objcopy:symlinks", "//llvm/tools/llvm-objdump:symlinks", + "//llvm/tools/llvm-offload-binary", "//llvm/tools/llvm-offload-wrapper", "//llvm/tools/llvm-opt-fuzzer", "//llvm/tools/llvm-opt-report", diff --git a/llvm/utils/gn/secondary/llvm/tools/llvm-offload-binary/BUILD.gn b/llvm/utils/gn/secondary/llvm/tools/llvm-offload-binary/BUILD.gn new file mode 100644 index 0000000..4cc0161 --- /dev/null +++ b/llvm/utils/gn/secondary/llvm/tools/llvm-offload-binary/BUILD.gn @@ -0,0 +1,8 @@ +executable("llvm-offload-binary") { + deps = [ + "//llvm/lib/BinaryFormat", + "//llvm/lib/Object", + "//llvm/lib/Support", + ] + sources = [ "llvm-offload-binary.cpp" ] +} diff --git a/llvm/utils/profcheck-xfail.txt b/llvm/utils/profcheck-xfail.txt index bbc8f59..74ed172 100644 --- a/llvm/utils/profcheck-xfail.txt +++ b/llvm/utils/profcheck-xfail.txt @@ -711,11 +711,6 @@ Transforms/CorrelatedValuePropagation/urem.ll Transforms/CrossDSOCFI/basic.ll Transforms/CrossDSOCFI/cfi_functions.ll Transforms/CrossDSOCFI/thumb.ll -Transforms/DFAJumpThreading/dfa-jump-threading-analysis.ll -Transforms/DFAJumpThreading/dfa-jump-threading-transform.ll -Transforms/DFAJumpThreading/dfa-unfold-select.ll -Transforms/DFAJumpThreading/max-path-length.ll -Transforms/DFAJumpThreading/negative.ll Transforms/ExpandFp/AMDGPU/frem-inf.ll Transforms/ExpandFp/AMDGPU/frem.ll Transforms/ExpandLargeDivRem/X86/sdiv129.ll diff --git a/mlir/cmake/modules/AddMLIRPython.cmake b/mlir/cmake/modules/AddMLIRPython.cmake index ea34f94..fa6aec8 100644 --- a/mlir/cmake/modules/AddMLIRPython.cmake +++ b/mlir/cmake/modules/AddMLIRPython.cmake @@ -123,12 +123,12 @@ function(mlir_generate_type_stubs) "IMPORT_PATHS;DEPENDS_TARGETS;OUTPUTS;DEPENDS_TARGET_SRC_DEPS" ${ARGN}) - # for people installing a distro (e.g., pip install) of nanobind + # for people doing find_package(nanobind) if(EXISTS ${nanobind_DIR}/../src/stubgen.py) set(NB_STUBGEN "${nanobind_DIR}/../src/stubgen.py") elseif(EXISTS ${nanobind_DIR}/../stubgen.py) set(NB_STUBGEN "${nanobind_DIR}/../stubgen.py") - # for people using nanobind git source tree (e.g., FetchContent_Declare and FetchContent_MakeAvailable) + # for people using FetchContent_Declare and FetchContent_MakeAvailable elseif(EXISTS ${nanobind_SOURCE_DIR}/src/stubgen.py) set(NB_STUBGEN "${nanobind_SOURCE_DIR}/src/stubgen.py") elseif(EXISTS ${nanobind_SOURCE_DIR}/stubgen.py) @@ -226,10 +226,11 @@ endfunction() # EMBED_CAPI_LINK_LIBS: Dependent CAPI libraries that this extension depends # on. These will be collected for all extensions and put into an # aggregate dylib that is linked against. +# PYTHON_BINDINGS_LIBRARY: Either pybind11 or nanobind. function(declare_mlir_python_extension name) cmake_parse_arguments(ARG "" - "ROOT_DIR;MODULE_NAME;ADD_TO_PARENT" + "ROOT_DIR;MODULE_NAME;ADD_TO_PARENT;PYTHON_BINDINGS_LIBRARY" "SOURCES;PRIVATE_LINK_LIBS;EMBED_CAPI_LINK_LIBS" ${ARGN}) @@ -238,15 +239,20 @@ function(declare_mlir_python_extension name) endif() set(_install_destination "src/python/${name}") + if(NOT ARG_PYTHON_BINDINGS_LIBRARY) + set(ARG_PYTHON_BINDINGS_LIBRARY "pybind11") + endif() + add_library(${name} INTERFACE) set_target_properties(${name} PROPERTIES # Yes: Leading-lowercase property names are load bearing and the recommended # way to do this: https://gitlab.kitware.com/cmake/cmake/-/issues/19261 - EXPORT_PROPERTIES "mlir_python_SOURCES_TYPE;mlir_python_EXTENSION_MODULE_NAME;mlir_python_EMBED_CAPI_LINK_LIBS;mlir_python_DEPENDS" + EXPORT_PROPERTIES "mlir_python_SOURCES_TYPE;mlir_python_EXTENSION_MODULE_NAME;mlir_python_EMBED_CAPI_LINK_LIBS;mlir_python_DEPENDS;mlir_python_BINDINGS_LIBRARY" mlir_python_SOURCES_TYPE extension mlir_python_EXTENSION_MODULE_NAME "${ARG_MODULE_NAME}" mlir_python_EMBED_CAPI_LINK_LIBS "${ARG_EMBED_CAPI_LINK_LIBS}" mlir_python_DEPENDS "" + mlir_python_BINDINGS_LIBRARY "${ARG_PYTHON_BINDINGS_LIBRARY}" ) # Set the interface source and link_libs properties of the target @@ -335,12 +341,14 @@ function(add_mlir_python_modules name) elseif(_source_type STREQUAL "extension") # Native CPP extension. get_target_property(_module_name ${sources_target} mlir_python_EXTENSION_MODULE_NAME) + get_target_property(_bindings_library ${sources_target} mlir_python_BINDINGS_LIBRARY) # Transform relative source to based on root dir. set(_extension_target "${modules_target}.extension.${_module_name}.dso") add_mlir_python_extension(${_extension_target} "${_module_name}" INSTALL_COMPONENT ${modules_target} INSTALL_DIR "${ARG_INSTALL_PREFIX}/_mlir_libs" OUTPUT_DIRECTORY "${ARG_ROOT_PREFIX}/_mlir_libs" + PYTHON_BINDINGS_LIBRARY ${_bindings_library} LINK_LIBS PRIVATE ${sources_target} ${ARG_COMMON_CAPI_LINK_LIBS} @@ -745,7 +753,7 @@ endfunction() function(add_mlir_python_extension libname extname) cmake_parse_arguments(ARG "" - "INSTALL_COMPONENT;INSTALL_DIR;OUTPUT_DIRECTORY" + "INSTALL_COMPONENT;INSTALL_DIR;OUTPUT_DIRECTORY;PYTHON_BINDINGS_LIBRARY" "SOURCES;LINK_LIBS" ${ARGN}) if(ARG_UNPARSED_ARGUMENTS) @@ -753,7 +761,7 @@ function(add_mlir_python_extension libname extname) endif() # The extension itself must be compiled with RTTI and exceptions enabled. - # Also, some warning classes triggered by nanobind are disabled. + # Also, some warning classes triggered by pybind11 are disabled. set(eh_rtti_enable) if (MSVC) set(eh_rtti_enable /EHsc /GR) @@ -761,53 +769,62 @@ function(add_mlir_python_extension libname extname) set(eh_rtti_enable -frtti -fexceptions) endif () - nanobind_add_module(${libname} - NB_DOMAIN ${MLIR_BINDINGS_PYTHON_NB_DOMAIN} - FREE_THREADED - ${ARG_SOURCES} - ) + # The actual extension library produces a shared-object or DLL and has + # sources that must be compiled in accordance with pybind11 needs (RTTI and + # exceptions). + if(NOT DEFINED ARG_PYTHON_BINDINGS_LIBRARY OR ARG_PYTHON_BINDINGS_LIBRARY STREQUAL "pybind11") + pybind11_add_module(${libname} + ${ARG_SOURCES} + ) + elseif(ARG_PYTHON_BINDINGS_LIBRARY STREQUAL "nanobind") + nanobind_add_module(${libname} + NB_DOMAIN ${MLIR_BINDINGS_PYTHON_NB_DOMAIN} + FREE_THREADED + ${ARG_SOURCES} + ) - if (NOT MLIR_DISABLE_CONFIGURE_PYTHON_DEV_PACKAGES - AND (LLVM_COMPILER_IS_GCC_COMPATIBLE OR CLANG_CL)) - # Avoid some warnings from upstream nanobind. - # If a superproject set MLIR_DISABLE_CONFIGURE_PYTHON_DEV_PACKAGES, let - # the super project handle compile options as it wishes. - get_property(NB_LIBRARY_TARGET_NAME TARGET ${libname} PROPERTY LINK_LIBRARIES) - target_compile_options(${NB_LIBRARY_TARGET_NAME} - PRIVATE - -Wall -Wextra -Wpedantic - -Wno-c++98-compat-extra-semi - -Wno-cast-qual - -Wno-covered-switch-default - -Wno-deprecated-literal-operator - -Wno-nested-anon-types - -Wno-unused-parameter - -Wno-zero-length-array - ${eh_rtti_enable}) - - target_compile_options(${libname} - PRIVATE - -Wall -Wextra -Wpedantic - -Wno-c++98-compat-extra-semi - -Wno-cast-qual - -Wno-covered-switch-default - -Wno-deprecated-literal-operator - -Wno-nested-anon-types - -Wno-unused-parameter - -Wno-zero-length-array - ${eh_rtti_enable}) - endif() + if (NOT MLIR_DISABLE_CONFIGURE_PYTHON_DEV_PACKAGES + AND (LLVM_COMPILER_IS_GCC_COMPATIBLE OR CLANG_CL)) + # Avoid some warnings from upstream nanobind. + # If a superproject set MLIR_DISABLE_CONFIGURE_PYTHON_DEV_PACKAGES, let + # the super project handle compile options as it wishes. + get_property(NB_LIBRARY_TARGET_NAME TARGET ${libname} PROPERTY LINK_LIBRARIES) + target_compile_options(${NB_LIBRARY_TARGET_NAME} + PRIVATE + -Wall -Wextra -Wpedantic + -Wno-c++98-compat-extra-semi + -Wno-cast-qual + -Wno-covered-switch-default + -Wno-deprecated-literal-operator + -Wno-nested-anon-types + -Wno-unused-parameter + -Wno-zero-length-array + ${eh_rtti_enable}) + + target_compile_options(${libname} + PRIVATE + -Wall -Wextra -Wpedantic + -Wno-c++98-compat-extra-semi + -Wno-cast-qual + -Wno-covered-switch-default + -Wno-deprecated-literal-operator + -Wno-nested-anon-types + -Wno-unused-parameter + -Wno-zero-length-array + ${eh_rtti_enable}) + endif() - if(APPLE) - # NanobindAdaptors.h uses PyClassMethod_New to build `pure_subclass`es but nanobind - # doesn't declare this API as undefined in its linker flags. So we need to declare it as such - # for downstream users that do not do something like `-undefined dynamic_lookup`. - # Same for the rest. - target_link_options(${libname} PUBLIC - "LINKER:-U,_PyClassMethod_New" - "LINKER:-U,_PyCode_Addr2Location" - "LINKER:-U,_PyFrame_GetLasti" - ) + if(APPLE) + # NanobindAdaptors.h uses PyClassMethod_New to build `pure_subclass`es but nanobind + # doesn't declare this API as undefined in its linker flags. So we need to declare it as such + # for downstream users that do not do something like `-undefined dynamic_lookup`. + # Same for the rest. + target_link_options(${libname} PUBLIC + "LINKER:-U,_PyClassMethod_New" + "LINKER:-U,_PyCode_Addr2Location" + "LINKER:-U,_PyFrame_GetLasti" + ) + endif() endif() target_compile_options(${libname} PRIVATE ${eh_rtti_enable}) @@ -845,11 +862,11 @@ function(add_mlir_python_extension libname extname) if(WIN32) # On Windows, pyconfig.h (and by extension python.h) hardcode the version of the # python library which will be used for linkage depending on the flavor of the build. - # nanobind has a workaround which depends on the definition of Py_DEBUG (if Py_DEBUG - # is not passed in as a compile definition, nanobind undefs _DEBUG when including + # pybind11 has a workaround which depends on the definition of Py_DEBUG (if Py_DEBUG + # is not passed in as a compile definition, pybind11 undefs _DEBUG when including # python.h, so that the release python library would be used). - # Since mlir uses nanobind, we can leverage their workaround by never directly - # pyconfig.h or python.h and instead relying on the nanobind headers to include the + # Since mlir uses pybind11, we can leverage their workaround by never directly + # pyconfig.h or python.h and instead relying on the pybind11 headers to include the # necessary python headers. This results in mlir always linking against the # release python library via the (undocumented) cmake property Python3_LIBRARY_RELEASE. target_link_libraries(${libname} PRIVATE ${Python3_LIBRARY_RELEASE}) diff --git a/mlir/cmake/modules/MLIRDetectPythonEnv.cmake b/mlir/cmake/modules/MLIRDetectPythonEnv.cmake index edbad2e..d18f8c0 100644 --- a/mlir/cmake/modules/MLIRDetectPythonEnv.cmake +++ b/mlir/cmake/modules/MLIRDetectPythonEnv.cmake @@ -46,20 +46,81 @@ macro(mlir_configure_python_dev_packages) message(STATUS "Found python include dirs: ${Python3_INCLUDE_DIRS}") message(STATUS "Found python libraries: ${Python3_LIBRARIES}") message(STATUS "Found numpy v${Python3_NumPy_VERSION}: ${Python3_NumPy_INCLUDE_DIRS}") - message(STATUS "Python extension suffix for modules: '${Python3_SOABI}'") - if(nanobind_DIR) - message(STATUS "Using explicit nanobind cmake directory: ${nanobind_DIR} (-Dnanobind_DIR to change)") - find_package(nanobind 2.9 CONFIG REQUIRED) - else() - include(FetchContent) - FetchContent_Declare( - nanobind - GIT_REPOSITORY https://github.com/wjakob/nanobind.git - GIT_TAG v2.9.0 - GIT_SHALLOW TRUE - ) - FetchContent_MakeAvailable(nanobind) - endif() - message(STATUS "Found nanobind: ${NB_DIR}") + mlir_detect_pybind11_install() + find_package(pybind11 2.10 CONFIG REQUIRED) + message(STATUS "Found pybind11 v${pybind11_VERSION}: ${pybind11_INCLUDE_DIR}") + message(STATUS "Python prefix = '${PYTHON_MODULE_PREFIX}', " + "suffix = '${PYTHON_MODULE_SUFFIX}', " + "extension = '${PYTHON_MODULE_EXTENSION}") + + mlir_detect_nanobind_install() + find_package(nanobind 2.9 CONFIG REQUIRED) + message(STATUS "Found nanobind v${nanobind_VERSION}: ${nanobind_INCLUDE_DIR}") + message(STATUS "Python prefix = '${PYTHON_MODULE_PREFIX}', " + "suffix = '${PYTHON_MODULE_SUFFIX}', " + "extension = '${PYTHON_MODULE_EXTENSION}") endif() endmacro() + +# Detects a pybind11 package installed in the current python environment +# and sets variables to allow it to be found. This allows pybind11 to be +# installed via pip, which typically yields a much more recent version than +# the OS install, which will be available otherwise. +function(mlir_detect_pybind11_install) + if(pybind11_DIR) + message(STATUS "Using explicit pybind11 cmake directory: ${pybind11_DIR} (-Dpybind11_DIR to change)") + else() + message(STATUS "Checking for pybind11 in python path...") + execute_process( + COMMAND "${Python3_EXECUTABLE}" + -c "import pybind11;print(pybind11.get_cmake_dir(), end='')" + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + RESULT_VARIABLE STATUS + OUTPUT_VARIABLE PACKAGE_DIR + ERROR_QUIET) + if(NOT STATUS EQUAL "0") + message(STATUS "not found (install via 'pip install pybind11' or set pybind11_DIR)") + return() + endif() + message(STATUS "found (${PACKAGE_DIR})") + set(pybind11_DIR "${PACKAGE_DIR}" PARENT_SCOPE) + endif() +endfunction() + + +# Detects a nanobind package installed in the current python environment +# and sets variables to allow it to be found. This allows nanobind to be +# installed via pip, which typically yields a much more recent version than +# the OS install, which will be available otherwise. +function(mlir_detect_nanobind_install) + if(nanobind_DIR) + message(STATUS "Using explicit nanobind cmake directory: ${nanobind_DIR} (-Dnanobind_DIR to change)") + else() + message(STATUS "Checking for nanobind in python path...") + execute_process( + COMMAND "${Python3_EXECUTABLE}" + -c "import nanobind;print(nanobind.cmake_dir(), end='')" + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + RESULT_VARIABLE STATUS + OUTPUT_VARIABLE PACKAGE_DIR + ERROR_QUIET) + if(NOT STATUS EQUAL "0") + message(STATUS "not found (install via 'pip install nanobind' or set nanobind_DIR)") + return() + endif() + message(STATUS "found (${PACKAGE_DIR})") + set(nanobind_DIR "${PACKAGE_DIR}" PARENT_SCOPE) + execute_process( + COMMAND "${Python3_EXECUTABLE}" + -c "import nanobind;print(nanobind.include_dir(), end='')" + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + RESULT_VARIABLE STATUS + OUTPUT_VARIABLE PACKAGE_DIR + ERROR_QUIET) + if(NOT STATUS EQUAL "0") + message(STATUS "not found (install via 'pip install nanobind' or set nanobind_DIR)") + return() + endif() + set(nanobind_INCLUDE_DIR "${PACKAGE_DIR}" PARENT_SCOPE) + endif() +endfunction() diff --git a/mlir/docs/Dialects/Linalg/OpDSL.md b/mlir/docs/Dialects/Linalg/OpDSL.md index 5d7e274..b892bbe 100644 --- a/mlir/docs/Dialects/Linalg/OpDSL.md +++ b/mlir/docs/Dialects/Linalg/OpDSL.md @@ -16,7 +16,7 @@ corresponding `linalg.generic` IR for the composition. ## Basic usage The tool is bundled with the MLIR Python bindings. To use from the CMake build -tree, MLIR must be built with Python bindings enabled +tree, MLIR must be build with Python bindings enabled (`-DMLIR_ENABLE_BINDINGS_PYTHON=ON`). Then add the `python` directory in the build tree to your `PYTHONPATH` environment variable (i.e. `export PYTHONPATH=$PWD/build/tools/mlir/python_packages/mlir_core`). Optionally, use an @@ -24,7 +24,7 @@ installed MLIR package, if available, to avoid building. ```shell # Dump the `core_named_ops.py` module as YAML. -python -m mlir.dialects.linalg.opdsl.dump_oplib.ops.core_named_ops +python -m mlir.dialects.linalg.opdsl.dump_oplib .ops.core_named_ops ``` Alternatively, run the `$PWD/build/bin/update_core_linalg_named_ops.sh` script, diff --git a/mlir/docs/Dialects/Transform.md b/mlir/docs/Dialects/Transform.md index 7164cb7..2133b81 100644 --- a/mlir/docs/Dialects/Transform.md +++ b/mlir/docs/Dialects/Transform.md @@ -415,10 +415,14 @@ ops rather than having the methods directly act on the payload IR. [include "Dialects/TransformOps.md"] -## Tuning Extension Operaiton +## Tune Extension Operations [include "Dialects/TuneExtensionOps.md"] +## SMT Extension Operations + +[include "Dialects/SMTExtensionOps.md"] + ## Affine Transform Operations [include "Dialects/AffineLoopTransformOps.md"] diff --git a/mlir/examples/standalone/pyproject.toml b/mlir/examples/standalone/pyproject.toml index 75e2153..5a1e6e8 100644 --- a/mlir/examples/standalone/pyproject.toml +++ b/mlir/examples/standalone/pyproject.toml @@ -23,7 +23,9 @@ Discussions = "https://discourse.llvm.org/" [build-system] requires = [ "scikit-build-core>=0.10.7", - "typing_extensions>=4.12.2" + "typing_extensions>=4.12.2", + "nanobind>=2.9, <3.0", + "pybind11>=2.10.0, <=2.13.6", ] build-backend = "scikit_build_core.build" diff --git a/mlir/examples/standalone/python/CMakeLists.txt b/mlir/examples/standalone/python/CMakeLists.txt index 108c343..905c9449 100644 --- a/mlir/examples/standalone/python/CMakeLists.txt +++ b/mlir/examples/standalone/python/CMakeLists.txt @@ -16,10 +16,27 @@ declare_mlir_dialect_python_bindings( ROOT_DIR "${CMAKE_CURRENT_SOURCE_DIR}/mlir_standalone" TD_FILE dialects/StandaloneOps.td SOURCES + dialects/standalone_pybind11.py dialects/standalone_nanobind.py _mlir_libs/_standaloneDialectsNanobind/py.typed DIALECT_NAME standalone) + +declare_mlir_python_extension(StandalonePythonSources.Pybind11Extension + MODULE_NAME _standaloneDialectsPybind11 + ADD_TO_PARENT StandalonePythonSources + SOURCES + StandaloneExtensionPybind11.cpp + PRIVATE_LINK_LIBS + LLVMSupport + EMBED_CAPI_LINK_LIBS + MLIRCAPIIR + MLIRCAPIArith + MLIRCAPITransforms + StandaloneCAPI + PYTHON_BINDINGS_LIBRARY pybind11 +) + declare_mlir_python_extension(StandalonePythonSources.NanobindExtension MODULE_NAME _standaloneDialectsNanobind ADD_TO_PARENT StandalonePythonSources @@ -32,6 +49,7 @@ declare_mlir_python_extension(StandalonePythonSources.NanobindExtension MLIRCAPIArith MLIRCAPITransforms StandaloneCAPI + PYTHON_BINDINGS_LIBRARY nanobind ) diff --git a/mlir/examples/standalone/python/StandaloneExtensionPybind11.cpp b/mlir/examples/standalone/python/StandaloneExtensionPybind11.cpp new file mode 100644 index 0000000..da8c216 --- /dev/null +++ b/mlir/examples/standalone/python/StandaloneExtensionPybind11.cpp @@ -0,0 +1,38 @@ +//===- StandaloneExtensionPybind11.cpp - Extension module -----------------===// +// +// This is the pybind11 version of the example module. There is also a nanobind +// example in StandaloneExtensionNanobind.cpp. +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "Standalone-c/Dialects.h" +#include "mlir-c/Dialect/Arith.h" +#include "mlir/Bindings/Python/PybindAdaptors.h" + +using namespace mlir::python::adaptors; + +PYBIND11_MODULE(_standaloneDialectsPybind11, m) { + //===--------------------------------------------------------------------===// + // standalone dialect + //===--------------------------------------------------------------------===// + auto standaloneM = m.def_submodule("standalone"); + + standaloneM.def( + "register_dialects", + [](MlirContext context, bool load) { + MlirDialectHandle arithHandle = mlirGetDialectHandle__arith__(); + MlirDialectHandle standaloneHandle = + mlirGetDialectHandle__standalone__(); + mlirDialectHandleRegisterDialect(arithHandle, context); + mlirDialectHandleRegisterDialect(standaloneHandle, context); + if (load) { + mlirDialectHandleLoadDialect(arithHandle, context); + mlirDialectHandleRegisterDialect(standaloneHandle, context); + } + }, + py::arg("context") = py::none(), py::arg("load") = true); +} diff --git a/mlir/examples/standalone/python/mlir_standalone/dialects/standalone_pybind11.py b/mlir/examples/standalone/python/mlir_standalone/dialects/standalone_pybind11.py new file mode 100644 index 0000000..bfb98e40 --- /dev/null +++ b/mlir/examples/standalone/python/mlir_standalone/dialects/standalone_pybind11.py @@ -0,0 +1,6 @@ +# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +# See https://llvm.org/LICENSE.txt for license information. +# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + +from ._standalone_ops_gen import * +from .._mlir_libs._standaloneDialectsPybind11.standalone import * diff --git a/mlir/examples/standalone/test/python/smoketest.py b/mlir/examples/standalone/test/python/smoketest.py index f881984..26d84fd 100644 --- a/mlir/examples/standalone/test/python/smoketest.py +++ b/mlir/examples/standalone/test/python/smoketest.py @@ -1,7 +1,16 @@ +# RUN: %python %s pybind11 | FileCheck %s # RUN: %python %s nanobind | FileCheck %s +import sys from mlir_standalone.ir import * -from mlir_standalone.dialects import standalone_nanobind as standalone_d + +if sys.argv[1] == "pybind11": + from mlir_standalone.dialects import standalone_pybind11 as standalone_d +elif sys.argv[1] == "nanobind": + from mlir_standalone.dialects import standalone_nanobind as standalone_d +else: + raise ValueError("Expected either pybind11 or nanobind as arguments") + with Context(): standalone_d.register_dialects() diff --git a/mlir/include/mlir/Bindings/Python/PybindAdaptors.h b/mlir/include/mlir/Bindings/Python/PybindAdaptors.h new file mode 100644 index 0000000..edc6977 --- /dev/null +++ b/mlir/include/mlir/Bindings/Python/PybindAdaptors.h @@ -0,0 +1,616 @@ +//===- PybindAdaptors.h - Interop with MLIR APIs via pybind11 -------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// This file contains adaptors for clients of the core MLIR Python APIs to +// interop via MLIR CAPI types, using pybind11. The facilities here do not +// depend on implementation details of the MLIR Python API and do not introduce +// C++-level dependencies with it (requiring only Python and CAPI-level +// dependencies). +// +// It is encouraged to be used both in-tree and out-of-tree. For in-tree use +// cases, it should be used for dialect implementations (versus relying on +// Pybind-based internals of the core libraries). +//===----------------------------------------------------------------------===// + +#ifndef MLIR_BINDINGS_PYTHON_PYBINDADAPTORS_H +#define MLIR_BINDINGS_PYTHON_PYBINDADAPTORS_H + +#include <pybind11/functional.h> +#include <pybind11/pybind11.h> +#include <pybind11/pytypes.h> +#include <pybind11/stl.h> + +#include "mlir-c/Bindings/Python/Interop.h" +#include "mlir-c/Diagnostics.h" +#include "mlir-c/IR.h" + +#include "llvm/ADT/Twine.h" + +namespace py = pybind11; +using namespace py::literals; + +// Raw CAPI type casters need to be declared before use, so always include them +// first. +namespace pybind11 { +namespace detail { + +/// Helper to convert a presumed MLIR API object to a capsule, accepting either +/// an explicit Capsule (which can happen when two C APIs are communicating +/// directly via Python) or indirectly by querying the MLIR_PYTHON_CAPI_PTR_ATTR +/// attribute (through which supported MLIR Python API objects export their +/// contained API pointer as a capsule). Throws a type error if the object is +/// neither. This is intended to be used from type casters, which are invoked +/// with a raw handle (unowned). The returned object's lifetime may not extend +/// beyond the apiObject handle without explicitly having its refcount increased +/// (i.e. on return). +static py::object mlirApiObjectToCapsule(py::handle apiObject) { + if (PyCapsule_CheckExact(apiObject.ptr())) + return py::reinterpret_borrow<py::object>(apiObject); + if (!py::hasattr(apiObject, MLIR_PYTHON_CAPI_PTR_ATTR)) { + auto repr = py::repr(apiObject).cast<std::string>(); + throw py::type_error( + (llvm::Twine("Expected an MLIR object (got ") + repr + ").").str()); + } + return apiObject.attr(MLIR_PYTHON_CAPI_PTR_ATTR); +} + +// Note: Currently all of the following support cast from py::object to the +// Mlir* C-API type, but only a few light-weight, context-bound ones +// implicitly cast the other way because the use case has not yet emerged and +// ownership is unclear. + +/// Casts object <-> MlirAffineMap. +template <> +struct type_caster<MlirAffineMap> { + PYBIND11_TYPE_CASTER(MlirAffineMap, _("MlirAffineMap")); + bool load(handle src, bool) { + py::object capsule = mlirApiObjectToCapsule(src); + value = mlirPythonCapsuleToAffineMap(capsule.ptr()); + if (mlirAffineMapIsNull(value)) { + return false; + } + return !mlirAffineMapIsNull(value); + } + static handle cast(MlirAffineMap v, return_value_policy, handle) { + py::object capsule = + py::reinterpret_steal<py::object>(mlirPythonAffineMapToCapsule(v)); + return py::module::import(MAKE_MLIR_PYTHON_QUALNAME("ir")) + .attr("AffineMap") + .attr(MLIR_PYTHON_CAPI_FACTORY_ATTR)(capsule) + .release(); + } +}; + +/// Casts object <-> MlirAttribute. +template <> +struct type_caster<MlirAttribute> { + PYBIND11_TYPE_CASTER(MlirAttribute, _("MlirAttribute")); + bool load(handle src, bool) { + py::object capsule = mlirApiObjectToCapsule(src); + value = mlirPythonCapsuleToAttribute(capsule.ptr()); + return !mlirAttributeIsNull(value); + } + static handle cast(MlirAttribute v, return_value_policy, handle) { + py::object capsule = + py::reinterpret_steal<py::object>(mlirPythonAttributeToCapsule(v)); + return py::module::import(MAKE_MLIR_PYTHON_QUALNAME("ir")) + .attr("Attribute") + .attr(MLIR_PYTHON_CAPI_FACTORY_ATTR)(capsule) + .attr(MLIR_PYTHON_MAYBE_DOWNCAST_ATTR)() + .release(); + } +}; + +/// Casts object -> MlirBlock. +template <> +struct type_caster<MlirBlock> { + PYBIND11_TYPE_CASTER(MlirBlock, _("MlirBlock")); + bool load(handle src, bool) { + py::object capsule = mlirApiObjectToCapsule(src); + value = mlirPythonCapsuleToBlock(capsule.ptr()); + return !mlirBlockIsNull(value); + } +}; + +/// Casts object -> MlirContext. +template <> +struct type_caster<MlirContext> { + PYBIND11_TYPE_CASTER(MlirContext, _("MlirContext")); + bool load(handle src, bool) { + if (src.is_none()) { + // Gets the current thread-bound context. + // TODO: This raises an error of "No current context" currently. + // Update the implementation to pretty-print the helpful error that the + // core implementations print in this case. + src = py::module::import(MAKE_MLIR_PYTHON_QUALNAME("ir")) + .attr("Context") + .attr("current"); + } + py::object capsule = mlirApiObjectToCapsule(src); + value = mlirPythonCapsuleToContext(capsule.ptr()); + return !mlirContextIsNull(value); + } +}; + +/// Casts object <-> MlirDialectRegistry. +template <> +struct type_caster<MlirDialectRegistry> { + PYBIND11_TYPE_CASTER(MlirDialectRegistry, _("MlirDialectRegistry")); + bool load(handle src, bool) { + py::object capsule = mlirApiObjectToCapsule(src); + value = mlirPythonCapsuleToDialectRegistry(capsule.ptr()); + return !mlirDialectRegistryIsNull(value); + } + static handle cast(MlirDialectRegistry v, return_value_policy, handle) { + py::object capsule = py::reinterpret_steal<py::object>( + mlirPythonDialectRegistryToCapsule(v)); + return py::module::import(MAKE_MLIR_PYTHON_QUALNAME("ir")) + .attr("DialectRegistry") + .attr(MLIR_PYTHON_CAPI_FACTORY_ATTR)(capsule) + .release(); + } +}; + +/// Casts object <-> MlirLocation. +template <> +struct type_caster<MlirLocation> { + PYBIND11_TYPE_CASTER(MlirLocation, _("MlirLocation")); + bool load(handle src, bool) { + if (src.is_none()) { + // Gets the current thread-bound context. + src = py::module::import(MAKE_MLIR_PYTHON_QUALNAME("ir")) + .attr("Location") + .attr("current"); + } + py::object capsule = mlirApiObjectToCapsule(src); + value = mlirPythonCapsuleToLocation(capsule.ptr()); + return !mlirLocationIsNull(value); + } + static handle cast(MlirLocation v, return_value_policy, handle) { + py::object capsule = + py::reinterpret_steal<py::object>(mlirPythonLocationToCapsule(v)); + return py::module::import(MAKE_MLIR_PYTHON_QUALNAME("ir")) + .attr("Location") + .attr(MLIR_PYTHON_CAPI_FACTORY_ATTR)(capsule) + .release(); + } +}; + +/// Casts object <-> MlirModule. +template <> +struct type_caster<MlirModule> { + PYBIND11_TYPE_CASTER(MlirModule, _("MlirModule")); + bool load(handle src, bool) { + py::object capsule = mlirApiObjectToCapsule(src); + value = mlirPythonCapsuleToModule(capsule.ptr()); + return !mlirModuleIsNull(value); + } + static handle cast(MlirModule v, return_value_policy, handle) { + py::object capsule = + py::reinterpret_steal<py::object>(mlirPythonModuleToCapsule(v)); + return py::module::import(MAKE_MLIR_PYTHON_QUALNAME("ir")) + .attr("Module") + .attr(MLIR_PYTHON_CAPI_FACTORY_ATTR)(capsule) + .release(); + }; +}; + +/// Casts object <-> MlirFrozenRewritePatternSet. +template <> +struct type_caster<MlirFrozenRewritePatternSet> { + PYBIND11_TYPE_CASTER(MlirFrozenRewritePatternSet, + _("MlirFrozenRewritePatternSet")); + bool load(handle src, bool) { + py::object capsule = mlirApiObjectToCapsule(src); + value = mlirPythonCapsuleToFrozenRewritePatternSet(capsule.ptr()); + return value.ptr != nullptr; + } + static handle cast(MlirFrozenRewritePatternSet v, return_value_policy, + handle) { + py::object capsule = py::reinterpret_steal<py::object>( + mlirPythonFrozenRewritePatternSetToCapsule(v)); + return py::module::import(MAKE_MLIR_PYTHON_QUALNAME("rewrite")) + .attr("FrozenRewritePatternSet") + .attr(MLIR_PYTHON_CAPI_FACTORY_ATTR)(capsule) + .release(); + }; +}; + +/// Casts object <-> MlirOperation. +template <> +struct type_caster<MlirOperation> { + PYBIND11_TYPE_CASTER(MlirOperation, _("MlirOperation")); + bool load(handle src, bool) { + py::object capsule = mlirApiObjectToCapsule(src); + value = mlirPythonCapsuleToOperation(capsule.ptr()); + return !mlirOperationIsNull(value); + } + static handle cast(MlirOperation v, return_value_policy, handle) { + if (v.ptr == nullptr) + return py::none(); + py::object capsule = + py::reinterpret_steal<py::object>(mlirPythonOperationToCapsule(v)); + return py::module::import(MAKE_MLIR_PYTHON_QUALNAME("ir")) + .attr("Operation") + .attr(MLIR_PYTHON_CAPI_FACTORY_ATTR)(capsule) + .release(); + }; +}; + +/// Casts object <-> MlirValue. +template <> +struct type_caster<MlirValue> { + PYBIND11_TYPE_CASTER(MlirValue, _("MlirValue")); + bool load(handle src, bool) { + py::object capsule = mlirApiObjectToCapsule(src); + value = mlirPythonCapsuleToValue(capsule.ptr()); + return !mlirValueIsNull(value); + } + static handle cast(MlirValue v, return_value_policy, handle) { + if (v.ptr == nullptr) + return py::none(); + py::object capsule = + py::reinterpret_steal<py::object>(mlirPythonValueToCapsule(v)); + return py::module::import(MAKE_MLIR_PYTHON_QUALNAME("ir")) + .attr("Value") + .attr(MLIR_PYTHON_CAPI_FACTORY_ATTR)(capsule) + .attr(MLIR_PYTHON_MAYBE_DOWNCAST_ATTR)() + .release(); + }; +}; + +/// Casts object -> MlirPassManager. +template <> +struct type_caster<MlirPassManager> { + PYBIND11_TYPE_CASTER(MlirPassManager, _("MlirPassManager")); + bool load(handle src, bool) { + py::object capsule = mlirApiObjectToCapsule(src); + value = mlirPythonCapsuleToPassManager(capsule.ptr()); + return !mlirPassManagerIsNull(value); + } +}; + +/// Casts object <-> MlirTypeID. +template <> +struct type_caster<MlirTypeID> { + PYBIND11_TYPE_CASTER(MlirTypeID, _("MlirTypeID")); + bool load(handle src, bool) { + py::object capsule = mlirApiObjectToCapsule(src); + value = mlirPythonCapsuleToTypeID(capsule.ptr()); + return !mlirTypeIDIsNull(value); + } + static handle cast(MlirTypeID v, return_value_policy, handle) { + if (v.ptr == nullptr) + return py::none(); + py::object capsule = + py::reinterpret_steal<py::object>(mlirPythonTypeIDToCapsule(v)); + return py::module::import(MAKE_MLIR_PYTHON_QUALNAME("ir")) + .attr("TypeID") + .attr(MLIR_PYTHON_CAPI_FACTORY_ATTR)(capsule) + .release(); + }; +}; + +/// Casts object <-> MlirType. +template <> +struct type_caster<MlirType> { + PYBIND11_TYPE_CASTER(MlirType, _("MlirType")); + bool load(handle src, bool) { + py::object capsule = mlirApiObjectToCapsule(src); + value = mlirPythonCapsuleToType(capsule.ptr()); + return !mlirTypeIsNull(value); + } + static handle cast(MlirType t, return_value_policy, handle) { + py::object capsule = + py::reinterpret_steal<py::object>(mlirPythonTypeToCapsule(t)); + return py::module::import(MAKE_MLIR_PYTHON_QUALNAME("ir")) + .attr("Type") + .attr(MLIR_PYTHON_CAPI_FACTORY_ATTR)(capsule) + .attr(MLIR_PYTHON_MAYBE_DOWNCAST_ATTR)() + .release(); + } +}; + +} // namespace detail +} // namespace pybind11 + +namespace mlir { +namespace python { +namespace adaptors { + +/// Provides a facility like py::class_ for defining a new class in a scope, +/// but this allows extension of an arbitrary Python class, defining methods +/// on it is a similar way. Classes defined in this way are very similar to +/// if defined in Python in the usual way but use Pybind11 machinery to do +/// it. These are not "real" Pybind11 classes but pure Python classes with no +/// relation to a concrete C++ class. +/// +/// Derived from a discussion upstream: +/// https://github.com/pybind/pybind11/issues/1193 +/// (plus a fair amount of extra curricular poking) +/// TODO: If this proves useful, see about including it in pybind11. +class pure_subclass { +public: + pure_subclass(py::handle scope, const char *derivedClassName, + const py::object &superClass) { + py::object pyType = + py::reinterpret_borrow<py::object>((PyObject *)&PyType_Type); + py::object metaclass = pyType(superClass); + py::dict attributes; + + thisClass = + metaclass(derivedClassName, py::make_tuple(superClass), attributes); + scope.attr(derivedClassName) = thisClass; + } + + template <typename Func, typename... Extra> + pure_subclass &def(const char *name, Func &&f, const Extra &...extra) { + py::cpp_function cf( + std::forward<Func>(f), py::name(name), py::is_method(thisClass), + py::sibling(py::getattr(thisClass, name, py::none())), extra...); + thisClass.attr(cf.name()) = cf; + return *this; + } + + template <typename Func, typename... Extra> + pure_subclass &def_property_readonly(const char *name, Func &&f, + const Extra &...extra) { + py::cpp_function cf( + std::forward<Func>(f), py::name(name), py::is_method(thisClass), + py::sibling(py::getattr(thisClass, name, py::none())), extra...); + auto builtinProperty = + py::reinterpret_borrow<py::object>((PyObject *)&PyProperty_Type); + thisClass.attr(name) = builtinProperty(cf); + return *this; + } + + template <typename Func, typename... Extra> + pure_subclass &def_staticmethod(const char *name, Func &&f, + const Extra &...extra) { + static_assert(!std::is_member_function_pointer<Func>::value, + "def_staticmethod(...) called with a non-static member " + "function pointer"); + py::cpp_function cf(std::forward<Func>(f), py::name(name), + py::scope(thisClass), extra...); + thisClass.attr(cf.name()) = py::staticmethod(cf); + return *this; + } + + template <typename Func, typename... Extra> + pure_subclass &def_classmethod(const char *name, Func &&f, + const Extra &...extra) { + static_assert(!std::is_member_function_pointer<Func>::value, + "def_classmethod(...) called with a non-static member " + "function pointer"); + py::cpp_function cf(std::forward<Func>(f), py::name(name), + py::scope(thisClass), extra...); + thisClass.attr(cf.name()) = + py::reinterpret_borrow<py::object>(PyClassMethod_New(cf.ptr())); + return *this; + } + + py::object get_class() const { return thisClass; } + +protected: + py::object superClass; + py::object thisClass; +}; + +/// Creates a custom subclass of mlir.ir.Attribute, implementing a casting +/// constructor and type checking methods. +class mlir_attribute_subclass : public pure_subclass { +public: + using IsAFunctionTy = bool (*)(MlirAttribute); + using GetTypeIDFunctionTy = MlirTypeID (*)(); + + /// Subclasses by looking up the super-class dynamically. + mlir_attribute_subclass(py::handle scope, const char *attrClassName, + IsAFunctionTy isaFunction, + GetTypeIDFunctionTy getTypeIDFunction = nullptr) + : mlir_attribute_subclass( + scope, attrClassName, isaFunction, + py::module::import(MAKE_MLIR_PYTHON_QUALNAME("ir")) + .attr("Attribute"), + getTypeIDFunction) {} + + /// Subclasses with a provided mlir.ir.Attribute super-class. This must + /// be used if the subclass is being defined in the same extension module + /// as the mlir.ir class (otherwise, it will trigger a recursive + /// initialization). + mlir_attribute_subclass(py::handle scope, const char *typeClassName, + IsAFunctionTy isaFunction, const py::object &superCls, + GetTypeIDFunctionTy getTypeIDFunction = nullptr) + : pure_subclass(scope, typeClassName, superCls) { + // Casting constructor. Note that it hard, if not impossible, to properly + // call chain to parent `__init__` in pybind11 due to its special handling + // for init functions that don't have a fully constructed self-reference, + // which makes it impossible to forward it to `__init__` of a superclass. + // Instead, provide a custom `__new__` and call that of a superclass, which + // eventually calls `__init__` of the superclass. Since attribute subclasses + // have no additional members, we can just return the instance thus created + // without amending it. + std::string captureTypeName( + typeClassName); // As string in case if typeClassName is not static. + py::cpp_function newCf( + [superCls, isaFunction, captureTypeName](py::object cls, + py::object otherAttribute) { + MlirAttribute rawAttribute = py::cast<MlirAttribute>(otherAttribute); + if (!isaFunction(rawAttribute)) { + auto origRepr = py::repr(otherAttribute).cast<std::string>(); + throw std::invalid_argument( + (llvm::Twine("Cannot cast attribute to ") + captureTypeName + + " (from " + origRepr + ")") + .str()); + } + py::object self = superCls.attr("__new__")(cls, otherAttribute); + return self; + }, + py::name("__new__"), py::arg("cls"), py::arg("cast_from_attr")); + thisClass.attr("__new__") = newCf; + + // 'isinstance' method. + def_staticmethod( + "isinstance", + [isaFunction](MlirAttribute other) { return isaFunction(other); }, + py::arg("other_attribute")); + def("__repr__", [superCls, captureTypeName](py::object self) { + return py::repr(superCls(self)) + .attr("replace")(superCls.attr("__name__"), captureTypeName); + }); + if (getTypeIDFunction) { + def_staticmethod("get_static_typeid", + [getTypeIDFunction]() { return getTypeIDFunction(); }); + py::module::import(MAKE_MLIR_PYTHON_QUALNAME("ir")) + .attr(MLIR_PYTHON_CAPI_TYPE_CASTER_REGISTER_ATTR)( + getTypeIDFunction())(pybind11::cpp_function( + [thisClass = thisClass](const py::object &mlirAttribute) { + return thisClass(mlirAttribute); + })); + } + } +}; + +/// Creates a custom subclass of mlir.ir.Type, implementing a casting +/// constructor and type checking methods. +class mlir_type_subclass : public pure_subclass { +public: + using IsAFunctionTy = bool (*)(MlirType); + using GetTypeIDFunctionTy = MlirTypeID (*)(); + + /// Subclasses by looking up the super-class dynamically. + mlir_type_subclass(py::handle scope, const char *typeClassName, + IsAFunctionTy isaFunction, + GetTypeIDFunctionTy getTypeIDFunction = nullptr) + : mlir_type_subclass( + scope, typeClassName, isaFunction, + py::module::import(MAKE_MLIR_PYTHON_QUALNAME("ir")).attr("Type"), + getTypeIDFunction) {} + + /// Subclasses with a provided mlir.ir.Type super-class. This must + /// be used if the subclass is being defined in the same extension module + /// as the mlir.ir class (otherwise, it will trigger a recursive + /// initialization). + mlir_type_subclass(py::handle scope, const char *typeClassName, + IsAFunctionTy isaFunction, const py::object &superCls, + GetTypeIDFunctionTy getTypeIDFunction = nullptr) + : pure_subclass(scope, typeClassName, superCls) { + // Casting constructor. Note that it hard, if not impossible, to properly + // call chain to parent `__init__` in pybind11 due to its special handling + // for init functions that don't have a fully constructed self-reference, + // which makes it impossible to forward it to `__init__` of a superclass. + // Instead, provide a custom `__new__` and call that of a superclass, which + // eventually calls `__init__` of the superclass. Since attribute subclasses + // have no additional members, we can just return the instance thus created + // without amending it. + std::string captureTypeName( + typeClassName); // As string in case if typeClassName is not static. + py::cpp_function newCf( + [superCls, isaFunction, captureTypeName](py::object cls, + py::object otherType) { + MlirType rawType = py::cast<MlirType>(otherType); + if (!isaFunction(rawType)) { + auto origRepr = py::repr(otherType).cast<std::string>(); + throw std::invalid_argument((llvm::Twine("Cannot cast type to ") + + captureTypeName + " (from " + + origRepr + ")") + .str()); + } + py::object self = superCls.attr("__new__")(cls, otherType); + return self; + }, + py::name("__new__"), py::arg("cls"), py::arg("cast_from_type")); + thisClass.attr("__new__") = newCf; + + // 'isinstance' method. + def_staticmethod( + "isinstance", + [isaFunction](MlirType other) { return isaFunction(other); }, + py::arg("other_type")); + def("__repr__", [superCls, captureTypeName](py::object self) { + return py::repr(superCls(self)) + .attr("replace")(superCls.attr("__name__"), captureTypeName); + }); + if (getTypeIDFunction) { + // 'get_static_typeid' method. + // This is modeled as a static method instead of a static property because + // `def_property_readonly_static` is not available in `pure_subclass` and + // we do not want to introduce the complexity that pybind uses to + // implement it. + def_staticmethod("get_static_typeid", + [getTypeIDFunction]() { return getTypeIDFunction(); }); + py::module::import(MAKE_MLIR_PYTHON_QUALNAME("ir")) + .attr(MLIR_PYTHON_CAPI_TYPE_CASTER_REGISTER_ATTR)( + getTypeIDFunction())(pybind11::cpp_function( + [thisClass = thisClass](const py::object &mlirType) { + return thisClass(mlirType); + })); + } + } +}; + +/// Creates a custom subclass of mlir.ir.Value, implementing a casting +/// constructor and type checking methods. +class mlir_value_subclass : public pure_subclass { +public: + using IsAFunctionTy = bool (*)(MlirValue); + + /// Subclasses by looking up the super-class dynamically. + mlir_value_subclass(py::handle scope, const char *valueClassName, + IsAFunctionTy isaFunction) + : mlir_value_subclass( + scope, valueClassName, isaFunction, + py::module::import(MAKE_MLIR_PYTHON_QUALNAME("ir")).attr("Value")) { + } + + /// Subclasses with a provided mlir.ir.Value super-class. This must + /// be used if the subclass is being defined in the same extension module + /// as the mlir.ir class (otherwise, it will trigger a recursive + /// initialization). + mlir_value_subclass(py::handle scope, const char *valueClassName, + IsAFunctionTy isaFunction, const py::object &superCls) + : pure_subclass(scope, valueClassName, superCls) { + // Casting constructor. Note that it hard, if not impossible, to properly + // call chain to parent `__init__` in pybind11 due to its special handling + // for init functions that don't have a fully constructed self-reference, + // which makes it impossible to forward it to `__init__` of a superclass. + // Instead, provide a custom `__new__` and call that of a superclass, which + // eventually calls `__init__` of the superclass. Since attribute subclasses + // have no additional members, we can just return the instance thus created + // without amending it. + std::string captureValueName( + valueClassName); // As string in case if valueClassName is not static. + py::cpp_function newCf( + [superCls, isaFunction, captureValueName](py::object cls, + py::object otherValue) { + MlirValue rawValue = py::cast<MlirValue>(otherValue); + if (!isaFunction(rawValue)) { + auto origRepr = py::repr(otherValue).cast<std::string>(); + throw std::invalid_argument((llvm::Twine("Cannot cast value to ") + + captureValueName + " (from " + + origRepr + ")") + .str()); + } + py::object self = superCls.attr("__new__")(cls, otherValue); + return self; + }, + py::name("__new__"), py::arg("cls"), py::arg("cast_from_value")); + thisClass.attr("__new__") = newCf; + + // 'isinstance' method. + def_staticmethod( + "isinstance", + [isaFunction](MlirValue other) { return isaFunction(other); }, + py::arg("other_value")); + } +}; + +} // namespace adaptors + +} // namespace python +} // namespace mlir + +#endif // MLIR_BINDINGS_PYTHON_PYBINDADAPTORS_H diff --git a/mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td b/mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td index 4f7a842..2dd6121 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td +++ b/mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td @@ -190,8 +190,9 @@ def XeVM_StoreCacheControlAttr def XeVM_BlockLoadOp : XeVM_Op<"blockload">, - Results<( - outs FixedVectorOfRankAndType<[1], [XeVM_1DBlockElemType]>:$res)>, + Results<(outs AnyTypeOf< + [XeVM_1DBlockElemType, + FixedVectorOfRankAndType<[1], [XeVM_1DBlockElemType]>]>:$res)>, Arguments<(ins Arg<LLVM_AnyPointer, "", [MemRead]>:$ptr, OptionalAttr<XeVM_LoadCacheControlAttr>:$cache_control)> { let summary = "subgroup block load"; @@ -228,7 +229,9 @@ def XeVM_BlockLoadOp def XeVM_BlockStoreOp : XeVM_Op<"blockstore">, Arguments<(ins Arg<LLVM_AnyPointer, "", [MemWrite]>:$ptr, - FixedVectorOfRankAndType<[1], [XeVM_1DBlockElemType]>:$val, + AnyTypeOf<[XeVM_1DBlockElemType, + FixedVectorOfRankAndType<[1], + [XeVM_1DBlockElemType]>]>:$val, OptionalAttr<XeVM_StoreCacheControlAttr>:$cache_control)> { let summary = "subgroup block store"; let description = [{ diff --git a/mlir/lib/Dialect/LLVMIR/IR/XeVMDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/XeVMDialect.cpp index 8295492..04e8836 100644 --- a/mlir/lib/Dialect/LLVMIR/IR/XeVMDialect.cpp +++ b/mlir/lib/Dialect/LLVMIR/IR/XeVMDialect.cpp @@ -310,26 +310,30 @@ LogicalResult BlockPrefetch2dOp::verify() { template <typename OpType, typename = std::enable_if_t<llvm::is_one_of< OpType, BlockLoadOp, BlockStoreOp>::value>> LogicalResult verify1DBlockArg(OpType op) { - VectorType vTy; + Type srcOrDstTy; if constexpr (std::is_same_v<OpType, BlockLoadOp>) - vTy = op.getResult().getType(); + srcOrDstTy = op.getResult().getType(); else - vTy = op.getVal().getType(); + srcOrDstTy = op.getVal().getType(); + VectorType vTy = dyn_cast<VectorType>(srcOrDstTy); + // scalar case is always valid + if (!vTy) + return success(); int elemTySize = vTy.getElementType().getIntOrFloatBitWidth() / 8; if (elemTySize == 1) { - llvm::SmallSet<int, 5> validSizes{1, 2, 4, 8, 16}; + llvm::SmallSet<int, 4> validSizes{2, 4, 8, 16}; if (validSizes.contains(vTy.getNumElements())) return success(); else return op.emitOpError( - "vector size must be 1, 2, 4, 8 or 16 for 8-bit element type"); + "vector size must be 2, 4, 8 or 16 for 8-bit element type"); } else { - llvm::SmallSet<int, 4> validSizes{1, 2, 4, 8}; + llvm::SmallSet<int, 3> validSizes{2, 4, 8}; if (validSizes.contains(vTy.getNumElements())) return success(); else return op.emitOpError( - "vector size must be 1, 2, 4 or 8 for element type > 8 bits"); + "vector size must be 2, 4 or 8 for element type > 8 bits"); } } diff --git a/mlir/python/CMakeLists.txt b/mlir/python/CMakeLists.txt index cea5b25..9f5246d 100644 --- a/mlir/python/CMakeLists.txt +++ b/mlir/python/CMakeLists.txt @@ -440,11 +440,11 @@ declare_mlir_dialect_python_bindings( DIALECT_NAME smt) declare_mlir_dialect_python_bindings( - ADD_TO_PARENT MLIRPythonSources.Dialects - ROOT_DIR "${CMAKE_CURRENT_SOURCE_DIR}/mlir" - TD_FILE dialects/SPIRVOps.td - SOURCES dialects/spirv.py - DIALECT_NAME spirv) + ADD_TO_PARENT MLIRPythonSources.Dialects + ROOT_DIR "${CMAKE_CURRENT_SOURCE_DIR}/mlir" + TD_FILE dialects/SPIRVOps.td + SOURCES dialects/spirv.py + DIALECT_NAME spirv) declare_mlir_dialect_python_bindings( ADD_TO_PARENT MLIRPythonSources.Dialects @@ -501,6 +501,7 @@ declare_mlir_python_extension(MLIRPythonExtension.Core MODULE_NAME _mlir ADD_TO_PARENT MLIRPythonSources.Core ROOT_DIR "${PYTHON_SOURCE_DIR}" + PYTHON_BINDINGS_LIBRARY nanobind SOURCES MainModule.cpp IRAffine.cpp @@ -539,6 +540,7 @@ declare_mlir_python_extension(MLIRPythonExtension.Core declare_mlir_python_extension(MLIRPythonExtension.RegisterEverything MODULE_NAME _mlirRegisterEverything ROOT_DIR "${PYTHON_SOURCE_DIR}" + PYTHON_BINDINGS_LIBRARY nanobind SOURCES RegisterEverything.cpp PRIVATE_LINK_LIBS @@ -549,10 +551,11 @@ declare_mlir_python_extension(MLIRPythonExtension.RegisterEverything MLIRCAPIRegisterEverything ) -declare_mlir_python_extension(MLIRPythonExtension.Dialects.Linalg.Nanobind +declare_mlir_python_extension(MLIRPythonExtension.Dialects.Linalg.Pybind MODULE_NAME _mlirDialectsLinalg ADD_TO_PARENT MLIRPythonSources.Dialects.linalg ROOT_DIR "${PYTHON_SOURCE_DIR}" + PYTHON_BINDINGS_LIBRARY nanobind SOURCES DialectLinalg.cpp PRIVATE_LINK_LIBS @@ -562,10 +565,11 @@ declare_mlir_python_extension(MLIRPythonExtension.Dialects.Linalg.Nanobind MLIRCAPILinalg ) -declare_mlir_python_extension(MLIRPythonExtension.Dialects.GPU.Nanobind +declare_mlir_python_extension(MLIRPythonExtension.Dialects.GPU.Pybind MODULE_NAME _mlirDialectsGPU ADD_TO_PARENT MLIRPythonSources.Dialects.gpu ROOT_DIR "${PYTHON_SOURCE_DIR}" + PYTHON_BINDINGS_LIBRARY nanobind SOURCES DialectGPU.cpp PRIVATE_LINK_LIBS @@ -575,10 +579,11 @@ declare_mlir_python_extension(MLIRPythonExtension.Dialects.GPU.Nanobind MLIRCAPIGPU ) -declare_mlir_python_extension(MLIRPythonExtension.Dialects.LLVM.Nanobind +declare_mlir_python_extension(MLIRPythonExtension.Dialects.LLVM.Pybind MODULE_NAME _mlirDialectsLLVM ADD_TO_PARENT MLIRPythonSources.Dialects.llvm ROOT_DIR "${PYTHON_SOURCE_DIR}" + PYTHON_BINDINGS_LIBRARY nanobind SOURCES DialectLLVM.cpp PRIVATE_LINK_LIBS @@ -588,10 +593,11 @@ declare_mlir_python_extension(MLIRPythonExtension.Dialects.LLVM.Nanobind MLIRCAPILLVM ) -declare_mlir_python_extension(MLIRPythonExtension.Dialects.Quant.Nanobind +declare_mlir_python_extension(MLIRPythonExtension.Dialects.Quant.Pybind MODULE_NAME _mlirDialectsQuant ADD_TO_PARENT MLIRPythonSources.Dialects.quant ROOT_DIR "${PYTHON_SOURCE_DIR}" + PYTHON_BINDINGS_LIBRARY nanobind SOURCES DialectQuant.cpp PRIVATE_LINK_LIBS @@ -601,10 +607,11 @@ declare_mlir_python_extension(MLIRPythonExtension.Dialects.Quant.Nanobind MLIRCAPIQuant ) -declare_mlir_python_extension(MLIRPythonExtension.Dialects.NVGPU.Nanobind +declare_mlir_python_extension(MLIRPythonExtension.Dialects.NVGPU.Pybind MODULE_NAME _mlirDialectsNVGPU ADD_TO_PARENT MLIRPythonSources.Dialects.nvgpu ROOT_DIR "${PYTHON_SOURCE_DIR}" + PYTHON_BINDINGS_LIBRARY nanobind SOURCES DialectNVGPU.cpp PRIVATE_LINK_LIBS @@ -614,10 +621,11 @@ declare_mlir_python_extension(MLIRPythonExtension.Dialects.NVGPU.Nanobind MLIRCAPINVGPU ) -declare_mlir_python_extension(MLIRPythonExtension.Dialects.PDL.Nanobind +declare_mlir_python_extension(MLIRPythonExtension.Dialects.PDL.Pybind MODULE_NAME _mlirDialectsPDL ADD_TO_PARENT MLIRPythonSources.Dialects.pdl ROOT_DIR "${PYTHON_SOURCE_DIR}" + PYTHON_BINDINGS_LIBRARY nanobind SOURCES DialectPDL.cpp PRIVATE_LINK_LIBS @@ -627,10 +635,11 @@ declare_mlir_python_extension(MLIRPythonExtension.Dialects.PDL.Nanobind MLIRCAPIPDL ) -declare_mlir_python_extension(MLIRPythonExtension.Dialects.SparseTensor.Nanobind +declare_mlir_python_extension(MLIRPythonExtension.Dialects.SparseTensor.Pybind MODULE_NAME _mlirDialectsSparseTensor ADD_TO_PARENT MLIRPythonSources.Dialects.sparse_tensor ROOT_DIR "${PYTHON_SOURCE_DIR}" + PYTHON_BINDINGS_LIBRARY nanobind SOURCES DialectSparseTensor.cpp PRIVATE_LINK_LIBS @@ -640,10 +649,11 @@ declare_mlir_python_extension(MLIRPythonExtension.Dialects.SparseTensor.Nanobind MLIRCAPISparseTensor ) -declare_mlir_python_extension(MLIRPythonExtension.Dialects.Transform.Nanobind +declare_mlir_python_extension(MLIRPythonExtension.Dialects.Transform.Pybind MODULE_NAME _mlirDialectsTransform ADD_TO_PARENT MLIRPythonSources.Dialects.transform ROOT_DIR "${PYTHON_SOURCE_DIR}" + PYTHON_BINDINGS_LIBRARY nanobind SOURCES DialectTransform.cpp PRIVATE_LINK_LIBS @@ -653,10 +663,11 @@ declare_mlir_python_extension(MLIRPythonExtension.Dialects.Transform.Nanobind MLIRCAPITransformDialect ) -declare_mlir_python_extension(MLIRPythonExtension.Dialects.IRDL.Nanobind +declare_mlir_python_extension(MLIRPythonExtension.Dialects.IRDL.Pybind MODULE_NAME _mlirDialectsIRDL ADD_TO_PARENT MLIRPythonSources.Dialects.irdl ROOT_DIR "${PYTHON_SOURCE_DIR}" + PYTHON_BINDINGS_LIBRARY nanobind SOURCES DialectIRDL.cpp PRIVATE_LINK_LIBS @@ -670,6 +681,7 @@ declare_mlir_python_extension(MLIRPythonExtension.AsyncDialectPasses MODULE_NAME _mlirAsyncPasses ADD_TO_PARENT MLIRPythonSources.Dialects.async ROOT_DIR "${PYTHON_SOURCE_DIR}" + PYTHON_BINDINGS_LIBRARY nanobind SOURCES AsyncPasses.cpp PRIVATE_LINK_LIBS @@ -683,6 +695,7 @@ if(MLIR_ENABLE_EXECUTION_ENGINE) MODULE_NAME _mlirExecutionEngine ADD_TO_PARENT MLIRPythonSources.ExecutionEngine ROOT_DIR "${PYTHON_SOURCE_DIR}" + PYTHON_BINDINGS_LIBRARY nanobind SOURCES ExecutionEngineModule.cpp PRIVATE_LINK_LIBS @@ -696,6 +709,7 @@ declare_mlir_python_extension(MLIRPythonExtension.GPUDialectPasses MODULE_NAME _mlirGPUPasses ADD_TO_PARENT MLIRPythonSources.Dialects.gpu ROOT_DIR "${PYTHON_SOURCE_DIR}" + PYTHON_BINDINGS_LIBRARY nanobind SOURCES GPUPasses.cpp PRIVATE_LINK_LIBS @@ -708,6 +722,7 @@ declare_mlir_python_extension(MLIRPythonExtension.LinalgPasses MODULE_NAME _mlirLinalgPasses ADD_TO_PARENT MLIRPythonSources.Dialects.linalg ROOT_DIR "${PYTHON_SOURCE_DIR}" + PYTHON_BINDINGS_LIBRARY nanobind SOURCES LinalgPasses.cpp PRIVATE_LINK_LIBS @@ -716,10 +731,11 @@ declare_mlir_python_extension(MLIRPythonExtension.LinalgPasses MLIRCAPILinalg ) -declare_mlir_python_extension(MLIRPythonExtension.Dialects.SMT.Nanobind +declare_mlir_python_extension(MLIRPythonExtension.Dialects.SMT.Pybind MODULE_NAME _mlirDialectsSMT ADD_TO_PARENT MLIRPythonSources.Dialects.smt ROOT_DIR "${PYTHON_SOURCE_DIR}" + PYTHON_BINDINGS_LIBRARY nanobind SOURCES DialectSMT.cpp # Headers must be included explicitly so they are installed. @@ -736,6 +752,7 @@ declare_mlir_python_extension(MLIRPythonExtension.SparseTensorDialectPasses MODULE_NAME _mlirSparseTensorPasses ADD_TO_PARENT MLIRPythonSources.Dialects.sparse_tensor ROOT_DIR "${PYTHON_SOURCE_DIR}" + PYTHON_BINDINGS_LIBRARY nanobind SOURCES SparseTensorPasses.cpp PRIVATE_LINK_LIBS @@ -748,6 +765,7 @@ declare_mlir_python_extension(MLIRPythonExtension.TransformInterpreter MODULE_NAME _mlirTransformInterpreter ADD_TO_PARENT MLIRPythonSources.Dialects.transform ROOT_DIR "${PYTHON_SOURCE_DIR}" + PYTHON_BINDINGS_LIBRARY nanobind SOURCES TransformInterpreter.cpp PRIVATE_LINK_LIBS @@ -789,10 +807,23 @@ if(MLIR_INCLUDE_TESTS) ADD_TO_PARENT MLIRPythonTestSources.Dialects.PythonTest SOURCES "dialects/_python_test_ops_gen.py") + declare_mlir_python_extension(MLIRPythonTestSources.PythonTestExtensionPybind11 + MODULE_NAME _mlirPythonTestPybind11 + ADD_TO_PARENT MLIRPythonTestSources.Dialects + ROOT_DIR "${MLIR_SOURCE_DIR}/test/python/lib" + PYTHON_BINDINGS_LIBRARY pybind11 + SOURCES + PythonTestModulePybind11.cpp + PRIVATE_LINK_LIBS + LLVMSupport + EMBED_CAPI_LINK_LIBS + MLIRCAPIPythonTestDialect + ) declare_mlir_python_extension(MLIRPythonTestSources.PythonTestExtensionNanobind MODULE_NAME _mlirPythonTestNanobind ADD_TO_PARENT MLIRPythonTestSources.Dialects ROOT_DIR "${MLIR_SOURCE_DIR}/test/python/lib" + PYTHON_BINDINGS_LIBRARY nanobind SOURCES PythonTestModuleNanobind.cpp PRIVATE_LINK_LIBS diff --git a/mlir/python/mlir/dialects/python_test.py b/mlir/python/mlir/dialects/python_test.py index 56d3c0f..9380896 100644 --- a/mlir/python/mlir/dialects/python_test.py +++ b/mlir/python/mlir/dialects/python_test.py @@ -5,7 +5,12 @@ from ._python_test_ops_gen import * -def register_python_test_dialect(registry): - from .._mlir_libs import _mlirPythonTestNanobind +def register_python_test_dialect(registry, use_nanobind): + if use_nanobind: + from .._mlir_libs import _mlirPythonTestNanobind - _mlirPythonTestNanobind.register_dialect(registry) + _mlirPythonTestNanobind.register_dialect(registry) + else: + from .._mlir_libs import _mlirPythonTestPybind11 + + _mlirPythonTestPybind11.register_dialect(registry) diff --git a/mlir/python/mlir/ir.py b/mlir/python/mlir/ir.py index 7ddc70a..11477d0 100644 --- a/mlir/python/mlir/ir.py +++ b/mlir/python/mlir/ir.py @@ -12,7 +12,7 @@ from ._mlir_libs._mlir.ir import _GlobalDebug from ._mlir_libs._mlir import ( register_type_caster, register_value_caster, - globals, + globals as _globals, ) from ._mlir_libs import ( get_dialect_registry, @@ -32,17 +32,17 @@ def loc_tracebacks(*, max_depth: int | None = None) -> Iterable[None]: max_depth: Maximum number of frames to include in the location. If None, the default limit is used. """ - old_enabled = globals.loc_tracebacks_enabled() - old_limit = globals.loc_tracebacks_frame_limit() + old_enabled = _globals.loc_tracebacks_enabled() + old_limit = _globals.loc_tracebacks_frame_limit() try: - globals.set_loc_tracebacks_frame_limit(max_depth) + _globals.set_loc_tracebacks_frame_limit(max_depth) if not old_enabled: - globals.set_loc_tracebacks_enabled(True) + _globals.set_loc_tracebacks_enabled(True) yield finally: if not old_enabled: - globals.set_loc_tracebacks_enabled(False) - globals.set_loc_tracebacks_frame_limit(old_limit) + _globals.set_loc_tracebacks_enabled(False) + _globals.set_loc_tracebacks_frame_limit(old_limit) # Convenience decorator for registering user-friendly Attribute builders. diff --git a/mlir/python/requirements.txt b/mlir/python/requirements.txt index 5ff9500..abe0925 100644 --- a/mlir/python/requirements.txt +++ b/mlir/python/requirements.txt @@ -1,4 +1,6 @@ +nanobind>=2.9, <3.0 numpy>=1.19.5, <=2.1.2 +pybind11>=2.10.0, <=2.13.6 PyYAML>=5.4.0, <=6.0.1 ml_dtypes>=0.1.0, <=0.6.0; python_version<"3.13" # provides several NumPy dtype extensions, including the bf16 ml_dtypes>=0.5.0, <=0.6.0; python_version>="3.13" diff --git a/mlir/test/Dialect/LLVMIR/invalid.mlir b/mlir/test/Dialect/LLVMIR/invalid.mlir index b7ca71a..aaf9f80 100644 --- a/mlir/test/Dialect/LLVMIR/invalid.mlir +++ b/mlir/test/Dialect/LLVMIR/invalid.mlir @@ -1973,14 +1973,14 @@ llvm.func @invalid_xevm_prefetch(%arg0: !llvm.ptr) { // ----- llvm.func @invalid_xevm_blockload(%arg0: !llvm.ptr<1>) { - // expected-error@+1 {{op vector size must be 1, 2, 4 or 8 for element type > 8 bits}} + // expected-error@+1 {{op vector size must be 2, 4 or 8 for element type > 8 bits}} %0 = xevm.blockload %arg0 : (!llvm.ptr<1>) -> vector<3xi16> llvm.return } // ----- llvm.func @invalid_xevm_blockstore(%arg0: !llvm.ptr<1>, %arg1: vector<5xi8>) { - // expected-error@+1 {{op vector size must be 1, 2, 4, 8 or 16 for 8-bit element type}} + // expected-error@+1 {{op vector size must be 2, 4, 8 or 16 for 8-bit element type}} xevm.blockstore %arg0, %arg1 : (!llvm.ptr<1>, vector<5xi8>) llvm.return } diff --git a/mlir/test/python/dialects/python_test.py b/mlir/test/python/dialects/python_test.py index 5a9acc7..1194e32 100644 --- a/mlir/test/python/dialects/python_test.py +++ b/mlir/test/python/dialects/python_test.py @@ -1,4 +1,5 @@ -# RUN: %PYTHON %s | FileCheck %s +# RUN: %PYTHON %s pybind11 | FileCheck %s +# RUN: %PYTHON %s nanobind | FileCheck %s import sys import typing from typing import Union, Optional @@ -9,14 +10,26 @@ import mlir.dialects.python_test as test import mlir.dialects.tensor as tensor import mlir.dialects.arith as arith -from mlir._mlir_libs._mlirPythonTestNanobind import ( - TestAttr, - TestType, - TestTensorValue, - TestIntegerRankedTensorType, -) - -test.register_python_test_dialect(get_dialect_registry()) +if sys.argv[1] == "pybind11": + from mlir._mlir_libs._mlirPythonTestPybind11 import ( + TestAttr, + TestType, + TestTensorValue, + TestIntegerRankedTensorType, + ) + + test.register_python_test_dialect(get_dialect_registry(), use_nanobind=False) +elif sys.argv[1] == "nanobind": + from mlir._mlir_libs._mlirPythonTestNanobind import ( + TestAttr, + TestType, + TestTensorValue, + TestIntegerRankedTensorType, + ) + + test.register_python_test_dialect(get_dialect_registry(), use_nanobind=True) +else: + raise ValueError("Expected pybind11 or nanobind as argument") def run(f): diff --git a/mlir/test/python/lib/CMakeLists.txt b/mlir/test/python/lib/CMakeLists.txt index f51a7b4..9a813da 100644 --- a/mlir/test/python/lib/CMakeLists.txt +++ b/mlir/test/python/lib/CMakeLists.txt @@ -1,6 +1,7 @@ set(LLVM_OPTIONAL_SOURCES PythonTestCAPI.cpp PythonTestDialect.cpp + PythonTestModulePybind11.cpp PythonTestModuleNanobind.cpp ) diff --git a/mlir/test/python/lib/PythonTestModulePybind11.cpp b/mlir/test/python/lib/PythonTestModulePybind11.cpp new file mode 100644 index 0000000..94a5f51 --- /dev/null +++ b/mlir/test/python/lib/PythonTestModulePybind11.cpp @@ -0,0 +1,118 @@ +//===- PythonTestModule.cpp - Python extension for the PythonTest dialect -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// This is the pybind11 edition of the PythonTest dialect module. +//===----------------------------------------------------------------------===// + +#include "PythonTestCAPI.h" +#include "mlir-c/BuiltinAttributes.h" +#include "mlir-c/BuiltinTypes.h" +#include "mlir-c/IR.h" +#include "mlir/Bindings/Python/PybindAdaptors.h" + +namespace py = pybind11; +using namespace mlir::python::adaptors; +using namespace pybind11::literals; + +static bool mlirTypeIsARankedIntegerTensor(MlirType t) { + return mlirTypeIsARankedTensor(t) && + mlirTypeIsAInteger(mlirShapedTypeGetElementType(t)); +} + +PYBIND11_MODULE(_mlirPythonTestPybind11, m) { + m.def( + "register_python_test_dialect", + [](MlirContext context, bool load) { + MlirDialectHandle pythonTestDialect = + mlirGetDialectHandle__python_test__(); + mlirDialectHandleRegisterDialect(pythonTestDialect, context); + if (load) { + mlirDialectHandleLoadDialect(pythonTestDialect, context); + } + }, + py::arg("context"), py::arg("load") = true); + + m.def( + "register_dialect", + [](MlirDialectRegistry registry) { + MlirDialectHandle pythonTestDialect = + mlirGetDialectHandle__python_test__(); + mlirDialectHandleInsertDialect(pythonTestDialect, registry); + }, + py::arg("registry")); + + mlir_attribute_subclass(m, "TestAttr", + mlirAttributeIsAPythonTestTestAttribute, + mlirPythonTestTestAttributeGetTypeID) + .def_classmethod( + "get", + [](const py::object &cls, MlirContext ctx) { + return cls(mlirPythonTestTestAttributeGet(ctx)); + }, + py::arg("cls"), py::arg("context") = py::none()); + + mlir_type_subclass(m, "TestType", mlirTypeIsAPythonTestTestType, + mlirPythonTestTestTypeGetTypeID) + .def_classmethod( + "get", + [](const py::object &cls, MlirContext ctx) { + return cls(mlirPythonTestTestTypeGet(ctx)); + }, + py::arg("cls"), py::arg("context") = py::none()); + + auto typeCls = + mlir_type_subclass(m, "TestIntegerRankedTensorType", + mlirTypeIsARankedIntegerTensor, + py::module::import(MAKE_MLIR_PYTHON_QUALNAME("ir")) + .attr("RankedTensorType")) + .def_classmethod( + "get", + [](const py::object &cls, std::vector<int64_t> shape, + unsigned width, MlirContext ctx) { + MlirAttribute encoding = mlirAttributeGetNull(); + return cls(mlirRankedTensorTypeGet( + shape.size(), shape.data(), mlirIntegerTypeGet(ctx, width), + encoding)); + }, + "cls"_a, "shape"_a, "width"_a, "context"_a = py::none()); + + assert(py::hasattr(typeCls.get_class(), "static_typeid") && + "TestIntegerRankedTensorType has no static_typeid"); + + MlirTypeID mlirRankedTensorTypeID = mlirRankedTensorTypeGetTypeID(); + + py::module::import(MAKE_MLIR_PYTHON_QUALNAME("ir")) + .attr(MLIR_PYTHON_CAPI_TYPE_CASTER_REGISTER_ATTR)(mlirRankedTensorTypeID, + "replace"_a = true)( + pybind11::cpp_function([typeCls](const py::object &mlirType) { + return typeCls.get_class()(mlirType); + })); + + auto valueCls = mlir_value_subclass(m, "TestTensorValue", + mlirTypeIsAPythonTestTestTensorValue) + .def("is_null", [](MlirValue &self) { + return mlirValueIsNull(self); + }); + + py::module::import(MAKE_MLIR_PYTHON_QUALNAME("ir")) + .attr(MLIR_PYTHON_CAPI_VALUE_CASTER_REGISTER_ATTR)( + mlirRankedTensorTypeID)( + pybind11::cpp_function([valueCls](const py::object &valueObj) { + py::object capsule = mlirApiObjectToCapsule(valueObj); + MlirValue v = mlirPythonCapsuleToValue(capsule.ptr()); + MlirType t = mlirValueGetType(v); + // This is hyper-specific in order to exercise/test registering a + // value caster from cpp (but only for a single test case; see + // testTensorValue python_test.py). + if (mlirShapedTypeHasStaticShape(t) && + mlirShapedTypeGetDimSize(t, 0) == 1 && + mlirShapedTypeGetDimSize(t, 1) == 2 && + mlirShapedTypeGetDimSize(t, 2) == 3) + return valueCls.get_class()(valueObj); + return valueObj; + })); +} diff --git a/mlir/tools/mlir-linalg-ods-gen/update_core_linalg_named_ops.sh.in b/mlir/tools/mlir-linalg-ods-gen/update_core_linalg_named_ops.sh.in index 0bb6a20..da4db39 100755 --- a/mlir/tools/mlir-linalg-ods-gen/update_core_linalg_named_ops.sh.in +++ b/mlir/tools/mlir-linalg-ods-gen/update_core_linalg_named_ops.sh.in @@ -26,7 +26,7 @@ export PYTHONPATH="$python_package_dir" OUTPUT="$( echo "### AUTOGENERATED from core_named_ops.py" && \ echo "### To regenerate, run: bin/update_core_linalg_named_ops.sh" && \ - "$python_exe" -m mlir.dialects.linalg.opdsl.dump_oplib.ops.core_named_ops \ + "$python_exe" -m mlir.dialects.linalg.opdsl.dump_oplib .ops.core_named_ops \ )" echo "$OUTPUT" > "$dest_file" echo "Success." diff --git a/utils/bazel/llvm-project-overlay/clang/BUILD.bazel b/utils/bazel/llvm-project-overlay/clang/BUILD.bazel index 258d732..3ea846e 100644 --- a/utils/bazel/llvm-project-overlay/clang/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/clang/BUILD.bazel @@ -2308,18 +2308,6 @@ cc_binary( ], ) -cc_binary( - name = "clang-offload-packager", - srcs = glob(["tools/clang-offload-packager/*.cpp"]), - stamp = 0, - deps = [ - ":basic", - "//llvm:BinaryFormat", - "//llvm:Object", - "//llvm:Support", - ], -) - gentbl_cc_library( name = "linker_wrapper_opts_gen", strip_include_prefix = "tools/clang-linker-wrapper", diff --git a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel index e7925aa..5357a6a 100644 --- a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel @@ -4772,6 +4772,17 @@ cc_binary( ) cc_binary( + name = "llvm-offload-binary", + srcs = glob(["tools/llvm-offload-binary/*.cpp"]), + stamp = 0, + deps = [ + "//llvm:BinaryFormat", + "//llvm:Object", + "//llvm:Support", + ], +) + +cc_binary( name = "llvm-pdbutil", srcs = glob([ "tools/llvm-pdbutil/*.cpp", @@ -4805,7 +4816,7 @@ cc_library( ], ) -llvm_driver_cc_binary( +cc_binary( name = "llvm-profdata", stamp = 0, deps = [":llvm-profdata-lib"], diff --git a/utils/bazel/llvm-project-overlay/llvm/driver.bzl b/utils/bazel/llvm-project-overlay/llvm/driver.bzl index 331e3f7..e38c681 100644 --- a/utils/bazel/llvm-project-overlay/llvm/driver.bzl +++ b/utils/bazel/llvm-project-overlay/llvm/driver.bzl @@ -28,7 +28,6 @@ _TOOLS = { "llvm-nm": "//llvm:llvm-nm-lib", "llvm-objcopy": "//llvm:llvm-objcopy-lib", "llvm-objdump": "//llvm:llvm-objdump-lib", - "llvm-profdata": "//llvm:llvm-profdata-lib", "llvm-rc": "//llvm:llvm-rc-lib", "llvm-readobj": "//llvm:llvm-readobj-lib", "llvm-size": "//llvm:llvm-size-lib", diff --git a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel index 0c77a1e..422c29f 100644 --- a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel @@ -1049,39 +1049,55 @@ filegroup( ) cc_library( - name = "MLIRBindingsPythonNanobindHeaders", + name = "MLIRBindingsPythonHeaders", includes = [ "include", ], textual_hdrs = [":MLIRBindingsPythonHeaderFiles"], deps = [ ":CAPIIRHeaders", - "@nanobind", + "@pybind11", "@rules_python//python/cc:current_py_cc_headers", ], ) -alias( - name = "MLIRBindingsPythonHeaders", - actual = ":MLIRBindingsPythonNanobindHeaders", +cc_library( + name = "MLIRBindingsPythonHeadersAndDeps", + includes = [ + "include", + ], + textual_hdrs = [":MLIRBindingsPythonHeaderFiles"], + deps = [ + ":CAPIIR", + "@pybind11", + "@rules_python//python/cc:current_py_cc_headers", + ], ) cc_library( - name = "MLIRBindingsPythonNanobindHeadersAndDeps", + name = "MLIRBindingsPythonNanobindHeaders", includes = [ "include", ], textual_hdrs = [":MLIRBindingsPythonHeaderFiles"], deps = [ - ":CAPIIR", + ":CAPIIRHeaders", "@nanobind", "@rules_python//python/cc:current_py_cc_headers", ], ) -alias( - name = "MLIRBindingsPythonHeadersAndDeps", - actual = ":MLIRBindingsPythonNanobindHeadersAndDeps", +cc_library( + name = "MLIRBindingsPythonNanobindHeadersAndDeps", + includes = [ + "include", + ], + textual_hdrs = [":MLIRBindingsPythonHeaderFiles"], + deps = [ + ":CAPIIR", + "@nanobind", + "@rules_python//python/cc:current_py_cc_headers", + ], ) # These flags are needed for pybind11 to work. @@ -1131,7 +1147,7 @@ cc_library( ":CAPIIR", ":CAPIInterfaces", ":CAPITransforms", - ":MLIRBindingsPythonHeadersAndDeps", + ":MLIRBindingsPythonNanobindHeadersAndDeps", ":Support", ":config", "//llvm:Support", @@ -1154,7 +1170,7 @@ cc_library( ":CAPIDebugHeaders", ":CAPIIRHeaders", ":CAPITransformsHeaders", - ":MLIRBindingsPythonHeaders", + ":MLIRBindingsPythonNanobindHeaders", ":Support", ":config", "//llvm:Support", @@ -1204,7 +1220,7 @@ cc_binary( linkstatic = 0, deps = [ ":CAPIIR", - ":MLIRBindingsPythonHeadersAndDeps", + ":MLIRBindingsPythonNanobindHeadersAndDeps", "@nanobind", ], ) @@ -1222,7 +1238,7 @@ cc_binary( deps = [ ":CAPIIR", ":CAPILinalg", - ":MLIRBindingsPythonHeadersAndDeps", + ":MLIRBindingsPythonNanobindHeadersAndDeps", "@nanobind", ], ) @@ -1237,7 +1253,7 @@ cc_binary( deps = [ ":CAPIIR", ":CAPILLVM", - ":MLIRBindingsPythonHeadersAndDeps", + ":MLIRBindingsPythonNanobindHeadersAndDeps", "@nanobind", ], ) @@ -1252,7 +1268,7 @@ cc_binary( deps = [ ":CAPIIR", ":CAPIQuant", - ":MLIRBindingsPythonHeadersAndDeps", + ":MLIRBindingsPythonNanobindHeadersAndDeps", "@nanobind", ], ) @@ -1267,7 +1283,7 @@ cc_binary( deps = [ ":CAPIIR", ":CAPISparseTensor", - ":MLIRBindingsPythonHeadersAndDeps", + ":MLIRBindingsPythonNanobindHeadersAndDeps", "@nanobind", ], ) @@ -1282,7 +1298,7 @@ cc_binary( linkstatic = 0, deps = [ ":CAPIExecutionEngine", - ":MLIRBindingsPythonHeadersAndDeps", + ":MLIRBindingsPythonNanobindHeadersAndDeps", "@nanobind", "@rules_python//python/cc:current_py_cc_headers", ], @@ -1298,7 +1314,7 @@ cc_binary( linkstatic = 0, deps = [ ":CAPILinalg", - ":MLIRBindingsPythonHeadersAndDeps", + ":MLIRBindingsPythonNanobindHeadersAndDeps", "@nanobind", "@rules_python//python/cc:current_py_cc_headers", ], |